Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 16
- Errors: 1
- Kernel Errors: 27
- Boot result: PASS
1 00:56:02.869755 lava-dispatcher, installed at version: 2023.10
2 00:56:02.869982 start: 0 validate
3 00:56:02.870120 Start time: 2024-01-19 00:56:02.870113+00:00 (UTC)
4 00:56:02.870237 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:56:02.870367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:56:03.140112 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:56:03.141017 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:56:19.652492 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:56:19.653261 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:56:19.923754 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:56:19.924494 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:56:23.694288 validate duration: 20.82
14 00:56:23.694772 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:56:23.694966 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:56:23.695142 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:56:23.695358 Not decompressing ramdisk as can be used compressed.
18 00:56:23.695521 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 00:56:23.695647 saving as /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/ramdisk/rootfs.cpio.gz
20 00:56:23.695773 total size: 8181372 (7 MB)
21 00:56:23.961223 progress 0 % (0 MB)
22 00:56:23.963572 progress 5 % (0 MB)
23 00:56:23.965635 progress 10 % (0 MB)
24 00:56:23.967949 progress 15 % (1 MB)
25 00:56:23.970063 progress 20 % (1 MB)
26 00:56:23.972408 progress 25 % (1 MB)
27 00:56:23.974525 progress 30 % (2 MB)
28 00:56:23.976879 progress 35 % (2 MB)
29 00:56:23.979030 progress 40 % (3 MB)
30 00:56:23.981243 progress 45 % (3 MB)
31 00:56:23.983332 progress 50 % (3 MB)
32 00:56:23.985576 progress 55 % (4 MB)
33 00:56:23.987603 progress 60 % (4 MB)
34 00:56:23.989847 progress 65 % (5 MB)
35 00:56:23.991897 progress 70 % (5 MB)
36 00:56:23.994151 progress 75 % (5 MB)
37 00:56:23.996163 progress 80 % (6 MB)
38 00:56:23.998370 progress 85 % (6 MB)
39 00:56:24.000371 progress 90 % (7 MB)
40 00:56:24.002574 progress 95 % (7 MB)
41 00:56:24.004595 progress 100 % (7 MB)
42 00:56:24.004790 7 MB downloaded in 0.31 s (25.25 MB/s)
43 00:56:24.004946 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:56:24.005188 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:56:24.005275 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:56:24.005359 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:56:24.005494 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:56:24.005565 saving as /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/kernel/Image
50 00:56:24.005627 total size: 51532288 (49 MB)
51 00:56:24.005689 No compression specified
52 00:56:24.006823 progress 0 % (0 MB)
53 00:56:24.019716 progress 5 % (2 MB)
54 00:56:24.032803 progress 10 % (4 MB)
55 00:56:24.046241 progress 15 % (7 MB)
56 00:56:24.059703 progress 20 % (9 MB)
57 00:56:24.072971 progress 25 % (12 MB)
58 00:56:24.086120 progress 30 % (14 MB)
59 00:56:24.099393 progress 35 % (17 MB)
60 00:56:24.112616 progress 40 % (19 MB)
61 00:56:24.125523 progress 45 % (22 MB)
62 00:56:24.138643 progress 50 % (24 MB)
63 00:56:24.151492 progress 55 % (27 MB)
64 00:56:24.164524 progress 60 % (29 MB)
65 00:56:24.177727 progress 65 % (31 MB)
66 00:56:24.190700 progress 70 % (34 MB)
67 00:56:24.203929 progress 75 % (36 MB)
68 00:56:24.217087 progress 80 % (39 MB)
69 00:56:24.230074 progress 85 % (41 MB)
70 00:56:24.243099 progress 90 % (44 MB)
71 00:56:24.256059 progress 95 % (46 MB)
72 00:56:24.268736 progress 100 % (49 MB)
73 00:56:24.268976 49 MB downloaded in 0.26 s (186.62 MB/s)
74 00:56:24.269134 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:56:24.269367 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:56:24.269458 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:56:24.269547 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:56:24.269683 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:56:24.269754 saving as /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/dtb/mt8192-asurada-spherion-r0.dtb
81 00:56:24.269816 total size: 47278 (0 MB)
82 00:56:24.269879 No compression specified
83 00:56:24.271216 progress 69 % (0 MB)
84 00:56:24.271496 progress 100 % (0 MB)
85 00:56:24.271650 0 MB downloaded in 0.00 s (24.61 MB/s)
86 00:56:24.271773 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:56:24.271997 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:56:24.272085 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:56:24.272167 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:56:24.272279 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:56:24.272346 saving as /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/modules/modules.tar
93 00:56:24.272407 total size: 8625444 (8 MB)
94 00:56:24.272468 Using unxz to decompress xz
95 00:56:24.276259 progress 0 % (0 MB)
96 00:56:24.297517 progress 5 % (0 MB)
97 00:56:24.321469 progress 10 % (0 MB)
98 00:56:24.344919 progress 15 % (1 MB)
99 00:56:24.368346 progress 20 % (1 MB)
100 00:56:24.392681 progress 25 % (2 MB)
101 00:56:24.419326 progress 30 % (2 MB)
102 00:56:24.445891 progress 35 % (2 MB)
103 00:56:24.469312 progress 40 % (3 MB)
104 00:56:24.493464 progress 45 % (3 MB)
105 00:56:24.518878 progress 50 % (4 MB)
106 00:56:24.543360 progress 55 % (4 MB)
107 00:56:24.568058 progress 60 % (4 MB)
108 00:56:24.595295 progress 65 % (5 MB)
109 00:56:24.620127 progress 70 % (5 MB)
110 00:56:24.643731 progress 75 % (6 MB)
111 00:56:24.670643 progress 80 % (6 MB)
112 00:56:24.696504 progress 85 % (7 MB)
113 00:56:24.721539 progress 90 % (7 MB)
114 00:56:24.753454 progress 95 % (7 MB)
115 00:56:24.781422 progress 100 % (8 MB)
116 00:56:24.786477 8 MB downloaded in 0.51 s (16.00 MB/s)
117 00:56:24.786743 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:56:24.787009 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:56:24.787103 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:56:24.787204 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:56:24.787288 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:56:24.787375 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:56:24.787574 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72
125 00:56:24.787704 makedir: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin
126 00:56:24.787808 makedir: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/tests
127 00:56:24.787903 makedir: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/results
128 00:56:24.788014 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-add-keys
129 00:56:24.788159 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-add-sources
130 00:56:24.788291 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-background-process-start
131 00:56:24.788417 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-background-process-stop
132 00:56:24.788537 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-common-functions
133 00:56:24.788656 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-echo-ipv4
134 00:56:24.788776 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-install-packages
135 00:56:24.788896 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-installed-packages
136 00:56:24.789014 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-os-build
137 00:56:24.789132 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-probe-channel
138 00:56:24.789252 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-probe-ip
139 00:56:24.789370 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-target-ip
140 00:56:24.789489 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-target-mac
141 00:56:24.789607 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-target-storage
142 00:56:24.789730 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-case
143 00:56:24.789853 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-event
144 00:56:24.790010 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-feedback
145 00:56:24.790132 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-raise
146 00:56:24.790253 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-reference
147 00:56:24.790373 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-runner
148 00:56:24.790492 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-set
149 00:56:24.790613 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-test-shell
150 00:56:24.790737 Updating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-install-packages (oe)
151 00:56:24.790882 Updating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/bin/lava-installed-packages (oe)
152 00:56:24.791008 Creating /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/environment
153 00:56:24.791109 LAVA metadata
154 00:56:24.791183 - LAVA_JOB_ID=12571130
155 00:56:24.791249 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:56:24.791353 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:56:24.791420 skipped lava-vland-overlay
158 00:56:24.791494 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:56:24.791581 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:56:24.791643 skipped lava-multinode-overlay
161 00:56:24.791716 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:56:24.791795 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:56:24.791870 Loading test definitions
164 00:56:24.791959 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:56:24.792032 Using /lava-12571130 at stage 0
166 00:56:24.792333 uuid=12571130_1.5.2.3.1 testdef=None
167 00:56:24.792421 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:56:24.792508 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:56:24.793019 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:56:24.793243 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:56:24.793874 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:56:24.794149 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:56:24.794757 runner path: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/0/tests/0_dmesg test_uuid 12571130_1.5.2.3.1
176 00:56:24.794911 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:56:24.795136 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 00:56:24.795207 Using /lava-12571130 at stage 1
180 00:56:24.795486 uuid=12571130_1.5.2.3.5 testdef=None
181 00:56:24.795574 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 00:56:24.795657 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 00:56:24.796113 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 00:56:24.796333 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 00:56:24.797451 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 00:56:24.797682 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 00:56:24.798337 runner path: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/1/tests/1_bootrr test_uuid 12571130_1.5.2.3.5
190 00:56:24.798487 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 00:56:24.798692 Creating lava-test-runner.conf files
193 00:56:24.798757 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/0 for stage 0
194 00:56:24.798844 - 0_dmesg
195 00:56:24.798921 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571130/lava-overlay-edos_u72/lava-12571130/1 for stage 1
196 00:56:24.799009 - 1_bootrr
197 00:56:24.799101 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 00:56:24.799184 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 00:56:24.807050 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 00:56:24.807161 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 00:56:24.807247 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 00:56:24.807339 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 00:56:24.807426 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 00:56:25.039497 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 00:56:25.039857 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 00:56:25.039972 extracting modules file /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571130/extract-overlay-ramdisk-u1oxob8r/ramdisk
207 00:56:25.260372 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 00:56:25.260545 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 00:56:25.260650 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571130/compress-overlay-1pd3mdak/overlay-1.5.2.4.tar.gz to ramdisk
210 00:56:25.260719 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571130/compress-overlay-1pd3mdak/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571130/extract-overlay-ramdisk-u1oxob8r/ramdisk
211 00:56:25.268668 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 00:56:25.268780 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 00:56:25.268869 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 00:56:25.268957 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 00:56:25.269036 Building ramdisk /var/lib/lava/dispatcher/tmp/12571130/extract-overlay-ramdisk-u1oxob8r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571130/extract-overlay-ramdisk-u1oxob8r/ramdisk
216 00:56:25.638387 >> 145326 blocks
217 00:56:27.915930 rename /var/lib/lava/dispatcher/tmp/12571130/extract-overlay-ramdisk-u1oxob8r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/ramdisk/ramdisk.cpio.gz
218 00:56:27.916454 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 00:56:27.916630 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 00:56:27.916781 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 00:56:27.916942 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/kernel/Image'
222 00:56:40.942872 Returned 0 in 13 seconds
223 00:56:41.043498 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/kernel/image.itb
224 00:56:41.434880 output: FIT description: Kernel Image image with one or more FDT blobs
225 00:56:41.435232 output: Created: Fri Jan 19 00:56:41 2024
226 00:56:41.435307 output: Image 0 (kernel-1)
227 00:56:41.435371 output: Description:
228 00:56:41.435435 output: Created: Fri Jan 19 00:56:41 2024
229 00:56:41.435496 output: Type: Kernel Image
230 00:56:41.435624 output: Compression: lzma compressed
231 00:56:41.435742 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
232 00:56:41.435799 output: Architecture: AArch64
233 00:56:41.435858 output: OS: Linux
234 00:56:41.435919 output: Load Address: 0x00000000
235 00:56:41.435976 output: Entry Point: 0x00000000
236 00:56:41.436034 output: Hash algo: crc32
237 00:56:41.436095 output: Hash value: a52aa383
238 00:56:41.436155 output: Image 1 (fdt-1)
239 00:56:41.436213 output: Description: mt8192-asurada-spherion-r0
240 00:56:41.436267 output: Created: Fri Jan 19 00:56:41 2024
241 00:56:41.436321 output: Type: Flat Device Tree
242 00:56:41.436375 output: Compression: uncompressed
243 00:56:41.436429 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 00:56:41.436483 output: Architecture: AArch64
245 00:56:41.436536 output: Hash algo: crc32
246 00:56:41.436588 output: Hash value: cc4352de
247 00:56:41.436641 output: Image 2 (ramdisk-1)
248 00:56:41.436694 output: Description: unavailable
249 00:56:41.436747 output: Created: Fri Jan 19 00:56:41 2024
250 00:56:41.436800 output: Type: RAMDisk Image
251 00:56:41.436853 output: Compression: Unknown Compression
252 00:56:41.436906 output: Data Size: 21399595 Bytes = 20898.04 KiB = 20.41 MiB
253 00:56:41.436961 output: Architecture: AArch64
254 00:56:41.437014 output: OS: Linux
255 00:56:41.437067 output: Load Address: unavailable
256 00:56:41.437119 output: Entry Point: unavailable
257 00:56:41.437172 output: Hash algo: crc32
258 00:56:41.437225 output: Hash value: 8e70be2a
259 00:56:41.437277 output: Default Configuration: 'conf-1'
260 00:56:41.437330 output: Configuration 0 (conf-1)
261 00:56:41.437388 output: Description: mt8192-asurada-spherion-r0
262 00:56:41.437441 output: Kernel: kernel-1
263 00:56:41.437526 output: Init Ramdisk: ramdisk-1
264 00:56:41.437627 output: FDT: fdt-1
265 00:56:41.437721 output: Loadables: kernel-1
266 00:56:41.437774 output:
267 00:56:41.437999 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 00:56:41.438101 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 00:56:41.438205 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 00:56:41.438297 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
271 00:56:41.438379 No LXC device requested
272 00:56:41.438456 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 00:56:41.438539 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
274 00:56:41.438614 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 00:56:41.438684 Checking files for TFTP limit of 4294967296 bytes.
276 00:56:41.439170 end: 1 tftp-deploy (duration 00:00:18) [common]
277 00:56:41.439273 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 00:56:41.439363 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 00:56:41.439487 substitutions:
280 00:56:41.439556 - {DTB}: 12571130/tftp-deploy-ryvd6b8t/dtb/mt8192-asurada-spherion-r0.dtb
281 00:56:41.439621 - {INITRD}: 12571130/tftp-deploy-ryvd6b8t/ramdisk/ramdisk.cpio.gz
282 00:56:41.439681 - {KERNEL}: 12571130/tftp-deploy-ryvd6b8t/kernel/Image
283 00:56:41.439739 - {LAVA_MAC}: None
284 00:56:41.439796 - {PRESEED_CONFIG}: None
285 00:56:41.439852 - {PRESEED_LOCAL}: None
286 00:56:41.439907 - {RAMDISK}: 12571130/tftp-deploy-ryvd6b8t/ramdisk/ramdisk.cpio.gz
287 00:56:41.439962 - {ROOT_PART}: None
288 00:56:41.440017 - {ROOT}: None
289 00:56:41.440071 - {SERVER_IP}: 192.168.201.1
290 00:56:41.440126 - {TEE}: None
291 00:56:41.440180 Parsed boot commands:
292 00:56:41.440233 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 00:56:41.440418 Parsed boot commands: tftpboot 192.168.201.1 12571130/tftp-deploy-ryvd6b8t/kernel/image.itb 12571130/tftp-deploy-ryvd6b8t/kernel/cmdline
294 00:56:41.440509 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 00:56:41.440594 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 00:56:41.440686 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 00:56:41.440771 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 00:56:41.440843 Not connected, no need to disconnect.
299 00:56:41.440916 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 00:56:41.440995 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 00:56:41.441062 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
302 00:56:41.444567 Setting prompt string to ['lava-test: # ']
303 00:56:41.444924 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 00:56:41.445038 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 00:56:41.445180 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 00:56:41.445514 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 00:56:41.445758 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 00:56:46.580771 >> Command sent successfully.
309 00:56:46.583237 Returned 0 in 5 seconds
310 00:56:46.683651 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 00:56:46.683988 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 00:56:46.684090 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 00:56:46.684182 Setting prompt string to 'Starting depthcharge on Spherion...'
315 00:56:46.684252 Changing prompt to 'Starting depthcharge on Spherion...'
316 00:56:46.684321 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 00:56:46.684581 [Enter `^Ec?' for help]
318 00:56:46.856874
319 00:56:46.857048
320 00:56:46.857135 F0: 102B 0000
321 00:56:46.857245
322 00:56:46.857343 F3: 1001 0000 [0200]
323 00:56:46.857437
324 00:56:46.860641 F3: 1001 0000
325 00:56:46.860725
326 00:56:46.860793 F7: 102D 0000
327 00:56:46.860854
328 00:56:46.860913 F1: 0000 0000
329 00:56:46.860972
330 00:56:46.864146 V0: 0000 0000 [0001]
331 00:56:46.864233
332 00:56:46.864299 00: 0007 8000
333 00:56:46.864368
334 00:56:46.867947 01: 0000 0000
335 00:56:46.868036
336 00:56:46.868106 BP: 0C00 0209 [0000]
337 00:56:46.868168
338 00:56:46.868227 G0: 1182 0000
339 00:56:46.871753
340 00:56:46.871839 EC: 0000 0021 [4000]
341 00:56:46.871906
342 00:56:46.875747 S7: 0000 0000 [0000]
343 00:56:46.875833
344 00:56:46.875932 CC: 0000 0000 [0001]
345 00:56:46.875994
346 00:56:46.876053 T0: 0000 0040 [010F]
347 00:56:46.878719
348 00:56:46.878803 Jump to BL
349 00:56:46.878918
350 00:56:46.903491
351 00:56:46.903633
352 00:56:46.903701
353 00:56:46.911019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 00:56:46.914099 ARM64: Exception handlers installed.
355 00:56:46.917840 ARM64: Testing exception
356 00:56:46.921516 ARM64: Done test exception
357 00:56:46.928554 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 00:56:46.938992 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 00:56:46.946634 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 00:56:46.956063 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 00:56:46.962714 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 00:56:46.969309 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 00:56:46.980780 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 00:56:46.987326 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 00:56:47.006144 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 00:56:47.009603 WDT: Last reset was cold boot
367 00:56:47.013025 SPI1(PAD0) initialized at 2873684 Hz
368 00:56:47.016351 SPI5(PAD0) initialized at 992727 Hz
369 00:56:47.019984 VBOOT: Loading verstage.
370 00:56:47.026636 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 00:56:47.029525 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 00:56:47.032957 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 00:56:47.036132 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 00:56:47.043776 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 00:56:47.050562 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 00:56:47.061242 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 00:56:47.061336
378 00:56:47.061404
379 00:56:47.071304 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 00:56:47.074778 ARM64: Exception handlers installed.
381 00:56:47.077756 ARM64: Testing exception
382 00:56:47.077848 ARM64: Done test exception
383 00:56:47.084403 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 00:56:47.087680 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 00:56:47.102401 Probing TPM: . done!
386 00:56:47.102525 TPM ready after 0 ms
387 00:56:47.109259 Connected to device vid:did:rid of 1ae0:0028:00
388 00:56:47.115905 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 00:56:47.119423 Initialized TPM device CR50 revision 0
390 00:56:47.185068 tlcl_send_startup: Startup return code is 0
391 00:56:47.185258 TPM: setup succeeded
392 00:56:47.196705 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 00:56:47.205764 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 00:56:47.215582 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 00:56:47.225305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 00:56:47.228662 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 00:56:47.236251 in-header: 03 07 00 00 08 00 00 00
398 00:56:47.240006 in-data: aa e4 47 04 13 02 00 00
399 00:56:47.243721 Chrome EC: UHEPI supported
400 00:56:47.250948 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 00:56:47.254642 in-header: 03 ad 00 00 08 00 00 00
402 00:56:47.258190 in-data: 00 20 20 08 00 00 00 00
403 00:56:47.258276 Phase 1
404 00:56:47.261782 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 00:56:47.269272 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 00:56:47.273697 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 00:56:47.276798 Recovery requested (1009000e)
408 00:56:47.285481 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 00:56:47.290593 tlcl_extend: response is 0
410 00:56:47.300220 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 00:56:47.305845 tlcl_extend: response is 0
412 00:56:47.312718 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 00:56:47.333496 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 00:56:47.339813 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 00:56:47.339903
416 00:56:47.339970
417 00:56:47.349860 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 00:56:47.353375 ARM64: Exception handlers installed.
419 00:56:47.353460 ARM64: Testing exception
420 00:56:47.356479 ARM64: Done test exception
421 00:56:47.375654 pmic_efuse_setting: Set efuses in 11 msecs
422 00:56:47.383916 pmwrap_interface_init: Select PMIF_VLD_RDY
423 00:56:47.387321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 00:56:47.393666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 00:56:47.397190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 00:56:47.400567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 00:56:47.407433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 00:56:47.411435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 00:56:47.414889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 00:56:47.421911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 00:56:47.425600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 00:56:47.429351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 00:56:47.436382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 00:56:47.439602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 00:56:47.442869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 00:56:47.449715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 00:56:47.456708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 00:56:47.463769 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 00:56:47.467355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 00:56:47.475270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 00:56:47.479117 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 00:56:47.485613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 00:56:47.488974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 00:56:47.496432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 00:56:47.500101 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 00:56:47.506292 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 00:56:47.513037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 00:56:47.516192 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 00:56:47.522995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 00:56:47.526345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 00:56:47.533193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 00:56:47.536350 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 00:56:47.543166 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 00:56:47.546399 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 00:56:47.553268 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 00:56:47.556591 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 00:56:47.563381 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 00:56:47.566651 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 00:56:47.573211 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 00:56:47.576487 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 00:56:47.583093 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 00:56:47.586803 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 00:56:47.590055 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 00:56:47.593264 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 00:56:47.600345 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 00:56:47.604049 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 00:56:47.607785 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 00:56:47.611148 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 00:56:47.617781 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 00:56:47.621157 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 00:56:47.624447 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 00:56:47.627756 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 00:56:47.634286 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 00:56:47.641110 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 00:56:47.650977 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 00:56:47.654494 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 00:56:47.661127 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 00:56:47.671541 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 00:56:47.674566 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 00:56:47.681232 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 00:56:47.684736 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 00:56:47.691230 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x3a
483 00:56:47.697877 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 00:56:47.701317 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 00:56:47.704443 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 00:56:47.715916 [RTC]rtc_get_frequency_meter,154: input=15, output=772
487 00:56:47.725328 [RTC]rtc_get_frequency_meter,154: input=23, output=959
488 00:56:47.734869 [RTC]rtc_get_frequency_meter,154: input=19, output=866
489 00:56:47.743950 [RTC]rtc_get_frequency_meter,154: input=17, output=818
490 00:56:47.754449 [RTC]rtc_get_frequency_meter,154: input=16, output=795
491 00:56:47.758421 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 00:56:47.762192 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 00:56:47.765815 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
494 00:56:47.769210 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 00:56:47.775993 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
496 00:56:47.779398 ADC[4]: Raw value=902139 ID=7
497 00:56:47.779485 ADC[3]: Raw value=213179 ID=1
498 00:56:47.782823 RAM Code: 0x71
499 00:56:47.785897 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 00:56:47.792737 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 00:56:47.799499 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 00:56:47.806187 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 00:56:47.809331 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 00:56:47.812657 in-header: 03 07 00 00 08 00 00 00
505 00:56:47.816188 in-data: aa e4 47 04 13 02 00 00
506 00:56:47.819727 Chrome EC: UHEPI supported
507 00:56:47.827294 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 00:56:47.830736 in-header: 03 ed 00 00 08 00 00 00
509 00:56:47.830837 in-data: 80 20 60 08 00 00 00 00
510 00:56:47.834748 MRC: failed to locate region type 0.
511 00:56:47.841900 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 00:56:47.845487 DRAM-K: Running full calibration
513 00:56:47.852198 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 00:56:47.852288 header.status = 0x0
515 00:56:47.855855 header.version = 0x6 (expected: 0x6)
516 00:56:47.858879 header.size = 0xd00 (expected: 0xd00)
517 00:56:47.862067 header.flags = 0x0
518 00:56:47.868794 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 00:56:47.885264 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
520 00:56:47.892273 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 00:56:47.895740 dram_init: ddr_geometry: 2
522 00:56:47.898824 [EMI] MDL number = 2
523 00:56:47.898915 [EMI] Get MDL freq = 0
524 00:56:47.902275 dram_init: ddr_type: 0
525 00:56:47.902362 is_discrete_lpddr4: 1
526 00:56:47.905455 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 00:56:47.905541
528 00:56:47.905608
529 00:56:47.908807 [Bian_co] ETT version 0.0.0.1
530 00:56:47.915676 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 00:56:47.915764
532 00:56:47.918814 dramc_set_vcore_voltage set vcore to 650000
533 00:56:47.918900 Read voltage for 800, 4
534 00:56:47.922280 Vio18 = 0
535 00:56:47.922366 Vcore = 650000
536 00:56:47.922433 Vdram = 0
537 00:56:47.925504 Vddq = 0
538 00:56:47.925590 Vmddr = 0
539 00:56:47.929013 dram_init: config_dvfs: 1
540 00:56:47.932421 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 00:56:47.939117 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 00:56:47.942181 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
543 00:56:47.945457 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
544 00:56:47.949077 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 00:56:47.952656 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 00:56:47.955996 MEM_TYPE=3, freq_sel=18
547 00:56:47.958982 sv_algorithm_assistance_LP4_1600
548 00:56:47.962208 ============ PULL DRAM RESETB DOWN ============
549 00:56:47.965793 ========== PULL DRAM RESETB DOWN end =========
550 00:56:47.972282 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 00:56:47.975402 ===================================
552 00:56:47.978810 LPDDR4 DRAM CONFIGURATION
553 00:56:47.978896 ===================================
554 00:56:47.982178 EX_ROW_EN[0] = 0x0
555 00:56:47.985617 EX_ROW_EN[1] = 0x0
556 00:56:47.985701 LP4Y_EN = 0x0
557 00:56:47.988972 WORK_FSP = 0x0
558 00:56:47.989056 WL = 0x2
559 00:56:47.992304 RL = 0x2
560 00:56:47.992389 BL = 0x2
561 00:56:47.995474 RPST = 0x0
562 00:56:47.995574 RD_PRE = 0x0
563 00:56:47.998621 WR_PRE = 0x1
564 00:56:47.998705 WR_PST = 0x0
565 00:56:48.002304 DBI_WR = 0x0
566 00:56:48.002388 DBI_RD = 0x0
567 00:56:48.005242 OTF = 0x1
568 00:56:48.009136 ===================================
569 00:56:48.012479 ===================================
570 00:56:48.012564 ANA top config
571 00:56:48.016035 ===================================
572 00:56:48.018844 DLL_ASYNC_EN = 0
573 00:56:48.022202 ALL_SLAVE_EN = 1
574 00:56:48.025681 NEW_RANK_MODE = 1
575 00:56:48.025771 DLL_IDLE_MODE = 1
576 00:56:48.028786 LP45_APHY_COMB_EN = 1
577 00:56:48.032240 TX_ODT_DIS = 1
578 00:56:48.035998 NEW_8X_MODE = 1
579 00:56:48.038915 ===================================
580 00:56:48.042383 ===================================
581 00:56:48.045695 data_rate = 1600
582 00:56:48.045780 CKR = 1
583 00:56:48.049240 DQ_P2S_RATIO = 8
584 00:56:48.052208 ===================================
585 00:56:48.056139 CA_P2S_RATIO = 8
586 00:56:48.059306 DQ_CA_OPEN = 0
587 00:56:48.062303 DQ_SEMI_OPEN = 0
588 00:56:48.062388 CA_SEMI_OPEN = 0
589 00:56:48.065846 CA_FULL_RATE = 0
590 00:56:48.068945 DQ_CKDIV4_EN = 1
591 00:56:48.072406 CA_CKDIV4_EN = 1
592 00:56:48.075915 CA_PREDIV_EN = 0
593 00:56:48.079066 PH8_DLY = 0
594 00:56:48.079152 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 00:56:48.082763 DQ_AAMCK_DIV = 4
596 00:56:48.085766 CA_AAMCK_DIV = 4
597 00:56:48.089198 CA_ADMCK_DIV = 4
598 00:56:48.092424 DQ_TRACK_CA_EN = 0
599 00:56:48.095961 CA_PICK = 800
600 00:56:48.096047 CA_MCKIO = 800
601 00:56:48.099690 MCKIO_SEMI = 0
602 00:56:48.102495 PLL_FREQ = 3068
603 00:56:48.105803 DQ_UI_PI_RATIO = 32
604 00:56:48.109357 CA_UI_PI_RATIO = 0
605 00:56:48.112390 ===================================
606 00:56:48.115709 ===================================
607 00:56:48.118969 memory_type:LPDDR4
608 00:56:48.119055 GP_NUM : 10
609 00:56:48.122578 SRAM_EN : 1
610 00:56:48.122662 MD32_EN : 0
611 00:56:48.125891 ===================================
612 00:56:48.129832 [ANA_INIT] >>>>>>>>>>>>>>
613 00:56:48.133208 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 00:56:48.136881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 00:56:48.140508 ===================================
616 00:56:48.140631 data_rate = 1600,PCW = 0X7600
617 00:56:48.144173 ===================================
618 00:56:48.148672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 00:56:48.156244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 00:56:48.159542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 00:56:48.163411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 00:56:48.166696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 00:56:48.170532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 00:56:48.173640 [ANA_INIT] flow start
625 00:56:48.176855 [ANA_INIT] PLL >>>>>>>>
626 00:56:48.176940 [ANA_INIT] PLL <<<<<<<<
627 00:56:48.180282 [ANA_INIT] MIDPI >>>>>>>>
628 00:56:48.183486 [ANA_INIT] MIDPI <<<<<<<<
629 00:56:48.183570 [ANA_INIT] DLL >>>>>>>>
630 00:56:48.187016 [ANA_INIT] flow end
631 00:56:48.190525 ============ LP4 DIFF to SE enter ============
632 00:56:48.193796 ============ LP4 DIFF to SE exit ============
633 00:56:48.196888 [ANA_INIT] <<<<<<<<<<<<<
634 00:56:48.200155 [Flow] Enable top DCM control >>>>>
635 00:56:48.203719 [Flow] Enable top DCM control <<<<<
636 00:56:48.206907 Enable DLL master slave shuffle
637 00:56:48.213501 ==============================================================
638 00:56:48.213586 Gating Mode config
639 00:56:48.220214 ==============================================================
640 00:56:48.220297 Config description:
641 00:56:48.230321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 00:56:48.236968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 00:56:48.243680 SELPH_MODE 0: By rank 1: By Phase
644 00:56:48.247351 ==============================================================
645 00:56:48.250299 GAT_TRACK_EN = 1
646 00:56:48.253683 RX_GATING_MODE = 2
647 00:56:48.257148 RX_GATING_TRACK_MODE = 2
648 00:56:48.260860 SELPH_MODE = 1
649 00:56:48.263807 PICG_EARLY_EN = 1
650 00:56:48.266749 VALID_LAT_VALUE = 1
651 00:56:48.270582 ==============================================================
652 00:56:48.273976 Enter into Gating configuration >>>>
653 00:56:48.277012 Exit from Gating configuration <<<<
654 00:56:48.280564 Enter into DVFS_PRE_config >>>>>
655 00:56:48.294354 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 00:56:48.294451 Exit from DVFS_PRE_config <<<<<
657 00:56:48.297559 Enter into PICG configuration >>>>
658 00:56:48.300383 Exit from PICG configuration <<<<
659 00:56:48.304239 [RX_INPUT] configuration >>>>>
660 00:56:48.307180 [RX_INPUT] configuration <<<<<
661 00:56:48.314010 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 00:56:48.317264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 00:56:48.324464 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 00:56:48.332068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 00:56:48.335291 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 00:56:48.343038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 00:56:48.346381 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 00:56:48.350135 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 00:56:48.354153 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 00:56:48.357506 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 00:56:48.365033 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 00:56:48.368877 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 00:56:48.372409 ===================================
674 00:56:48.372498 LPDDR4 DRAM CONFIGURATION
675 00:56:48.375619 ===================================
676 00:56:48.379583 EX_ROW_EN[0] = 0x0
677 00:56:48.379669 EX_ROW_EN[1] = 0x0
678 00:56:48.383039 LP4Y_EN = 0x0
679 00:56:48.383124 WORK_FSP = 0x0
680 00:56:48.386914 WL = 0x2
681 00:56:48.386999 RL = 0x2
682 00:56:48.390744 BL = 0x2
683 00:56:48.390829 RPST = 0x0
684 00:56:48.394127 RD_PRE = 0x0
685 00:56:48.394215 WR_PRE = 0x1
686 00:56:48.394283 WR_PST = 0x0
687 00:56:48.398117 DBI_WR = 0x0
688 00:56:48.398240 DBI_RD = 0x0
689 00:56:48.401813 OTF = 0x1
690 00:56:48.405404 ===================================
691 00:56:48.408957 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 00:56:48.412788 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 00:56:48.416616 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 00:56:48.420533 ===================================
695 00:56:48.423670 LPDDR4 DRAM CONFIGURATION
696 00:56:48.427587 ===================================
697 00:56:48.427673 EX_ROW_EN[0] = 0x10
698 00:56:48.431293 EX_ROW_EN[1] = 0x0
699 00:56:48.431378 LP4Y_EN = 0x0
700 00:56:48.435430 WORK_FSP = 0x0
701 00:56:48.435514 WL = 0x2
702 00:56:48.438874 RL = 0x2
703 00:56:48.438958 BL = 0x2
704 00:56:48.439025 RPST = 0x0
705 00:56:48.442526 RD_PRE = 0x0
706 00:56:48.442611 WR_PRE = 0x1
707 00:56:48.446562 WR_PST = 0x0
708 00:56:48.446646 DBI_WR = 0x0
709 00:56:48.449887 DBI_RD = 0x0
710 00:56:48.450007 OTF = 0x1
711 00:56:48.453705 ===================================
712 00:56:48.461193 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 00:56:48.464915 nWR fixed to 40
714 00:56:48.465001 [ModeRegInit_LP4] CH0 RK0
715 00:56:48.468921 [ModeRegInit_LP4] CH0 RK1
716 00:56:48.472413 [ModeRegInit_LP4] CH1 RK0
717 00:56:48.472499 [ModeRegInit_LP4] CH1 RK1
718 00:56:48.476605 match AC timing 13
719 00:56:48.480070 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 00:56:48.483388 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 00:56:48.487227 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 00:56:48.494287 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 00:56:48.498186 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 00:56:48.498273 [EMI DOE] emi_dcm 0
725 00:56:48.501935 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 00:56:48.502043 ==
727 00:56:48.505607 Dram Type= 6, Freq= 0, CH_0, rank 0
728 00:56:48.509340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 00:56:48.509427 ==
730 00:56:48.516697 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 00:56:48.523947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 00:56:48.531616 [CA 0] Center 38 (7~69) winsize 63
733 00:56:48.534870 [CA 1] Center 38 (7~69) winsize 63
734 00:56:48.538304 [CA 2] Center 35 (5~66) winsize 62
735 00:56:48.542156 [CA 3] Center 35 (5~66) winsize 62
736 00:56:48.545727 [CA 4] Center 34 (4~65) winsize 62
737 00:56:48.549490 [CA 5] Center 33 (3~64) winsize 62
738 00:56:48.549576
739 00:56:48.552989 [CmdBusTrainingLP45] Vref(ca) range 1: 32
740 00:56:48.553075
741 00:56:48.556743 [CATrainingPosCal] consider 1 rank data
742 00:56:48.560452 u2DelayCellTimex100 = 270/100 ps
743 00:56:48.564707 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
744 00:56:48.568323 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
745 00:56:48.572234 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
746 00:56:48.575478 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
747 00:56:48.579471 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
748 00:56:48.579559 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
749 00:56:48.583276
750 00:56:48.587111 CA PerBit enable=1, Macro0, CA PI delay=33
751 00:56:48.587198
752 00:56:48.587265 [CBTSetCACLKResult] CA Dly = 33
753 00:56:48.590168 CS Dly: 6 (0~37)
754 00:56:48.590253 ==
755 00:56:48.593865 Dram Type= 6, Freq= 0, CH_0, rank 1
756 00:56:48.597516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 00:56:48.597602 ==
758 00:56:48.601530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 00:56:48.608109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 00:56:48.618612 [CA 0] Center 38 (7~69) winsize 63
761 00:56:48.622593 [CA 1] Center 38 (8~69) winsize 62
762 00:56:48.625802 [CA 2] Center 36 (5~67) winsize 63
763 00:56:48.629356 [CA 3] Center 35 (5~66) winsize 62
764 00:56:48.632868 [CA 4] Center 35 (5~66) winsize 62
765 00:56:48.636242 [CA 5] Center 34 (4~65) winsize 62
766 00:56:48.636332
767 00:56:48.639387 [CmdBusTrainingLP45] Vref(ca) range 1: 30
768 00:56:48.639470
769 00:56:48.642843 [CATrainingPosCal] consider 2 rank data
770 00:56:48.646459 u2DelayCellTimex100 = 270/100 ps
771 00:56:48.649736 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
772 00:56:48.653060 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
773 00:56:48.656414 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
774 00:56:48.659607 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 00:56:48.662898 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
776 00:56:48.666250 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 00:56:48.666336
778 00:56:48.669582 CA PerBit enable=1, Macro0, CA PI delay=34
779 00:56:48.673176
780 00:56:48.673262 [CBTSetCACLKResult] CA Dly = 34
781 00:56:48.676672 CS Dly: 6 (0~38)
782 00:56:48.676758
783 00:56:48.679481 ----->DramcWriteLeveling(PI) begin...
784 00:56:48.679568 ==
785 00:56:48.683026 Dram Type= 6, Freq= 0, CH_0, rank 0
786 00:56:48.686381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 00:56:48.686468 ==
788 00:56:48.689428 Write leveling (Byte 0): 33 => 33
789 00:56:48.692963 Write leveling (Byte 1): 27 => 27
790 00:56:48.696180 DramcWriteLeveling(PI) end<-----
791 00:56:48.696267
792 00:56:48.696335 ==
793 00:56:48.699588 Dram Type= 6, Freq= 0, CH_0, rank 0
794 00:56:48.703210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 00:56:48.703299 ==
796 00:56:48.706475 [Gating] SW mode calibration
797 00:56:48.713791 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 00:56:48.721152 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 00:56:48.724813 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
800 00:56:48.728744 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
801 00:56:48.731984 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
802 00:56:48.739023 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
803 00:56:48.742420 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:56:48.745877 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:56:48.749382 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:56:48.755865 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:56:48.759332 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:56:48.762767 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:56:48.769139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:56:48.772866 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:56:48.776013 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:56:48.779417 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 00:56:48.785908 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 00:56:48.789436 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:56:48.792622 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
816 00:56:48.799695 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
817 00:56:48.802450 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
818 00:56:48.806054 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:56:48.812629 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 00:56:48.816202 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 00:56:48.819266 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 00:56:48.825960 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:56:48.829205 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:56:48.832758 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
825 00:56:48.839252 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
826 00:56:48.842901 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
827 00:56:48.846260 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 00:56:48.852876 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 00:56:48.856246 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 00:56:48.859684 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 00:56:48.862710 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
832 00:56:48.869377 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
833 00:56:48.872802 0 10 8 | B1->B0 | 3434 2323 | 0 0 | (1 1) (0 0)
834 00:56:48.876369 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:56:48.882948 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:56:48.886166 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:56:48.889632 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:56:48.896115 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:56:48.899807 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 00:56:48.902849 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
841 00:56:48.909537 0 11 8 | B1->B0 | 2d2c 4545 | 1 0 | (0 0) (0 0)
842 00:56:48.912849 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
843 00:56:48.916459 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 00:56:48.923015 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 00:56:48.926245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 00:56:48.929418 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 00:56:48.933453 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
848 00:56:48.939761 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
849 00:56:48.943009 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
850 00:56:48.946518 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:56:48.953228 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:56:48.956208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 00:56:48.959543 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 00:56:48.966508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 00:56:48.969900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 00:56:48.973195 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 00:56:48.979752 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 00:56:48.983279 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 00:56:48.986471 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 00:56:48.993307 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 00:56:48.996519 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 00:56:48.999869 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 00:56:49.006509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 00:56:49.009756 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
865 00:56:49.013455 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 00:56:49.016653 Total UI for P1: 0, mck2ui 16
867 00:56:49.020217 best dqsien dly found for B0: ( 0, 14, 4)
868 00:56:49.023142 Total UI for P1: 0, mck2ui 16
869 00:56:49.026782 best dqsien dly found for B1: ( 0, 14, 6)
870 00:56:49.029710 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
871 00:56:49.033226 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
872 00:56:49.033312
873 00:56:49.036616 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
874 00:56:49.039859 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
875 00:56:49.043412 [Gating] SW calibration Done
876 00:56:49.043498 ==
877 00:56:49.046539 Dram Type= 6, Freq= 0, CH_0, rank 0
878 00:56:49.050073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
879 00:56:49.053704 ==
880 00:56:49.053789 RX Vref Scan: 0
881 00:56:49.053857
882 00:56:49.056653 RX Vref 0 -> 0, step: 1
883 00:56:49.056739
884 00:56:49.059894 RX Delay -130 -> 252, step: 16
885 00:56:49.063229 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
886 00:56:49.066845 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
887 00:56:49.070074 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
888 00:56:49.073504 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
889 00:56:49.080175 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
890 00:56:49.083282 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
891 00:56:49.086613 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
892 00:56:49.089728 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
893 00:56:49.093192 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
894 00:56:49.099951 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
895 00:56:49.103584 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
896 00:56:49.106675 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
897 00:56:49.109930 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
898 00:56:49.113227 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
899 00:56:49.120537 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
900 00:56:49.123227 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
901 00:56:49.123313 ==
902 00:56:49.126708 Dram Type= 6, Freq= 0, CH_0, rank 0
903 00:56:49.130049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 00:56:49.130135 ==
905 00:56:49.133267 DQS Delay:
906 00:56:49.133351 DQS0 = 0, DQS1 = 0
907 00:56:49.133418 DQM Delay:
908 00:56:49.136790 DQM0 = 88, DQM1 = 79
909 00:56:49.136874 DQ Delay:
910 00:56:49.139926 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
911 00:56:49.143543 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
912 00:56:49.146654 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
913 00:56:49.150157 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
914 00:56:49.150241
915 00:56:49.150307
916 00:56:49.150373 ==
917 00:56:49.153768 Dram Type= 6, Freq= 0, CH_0, rank 0
918 00:56:49.160193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 00:56:49.160277 ==
920 00:56:49.160344
921 00:56:49.160404
922 00:56:49.160462 TX Vref Scan disable
923 00:56:49.163541 == TX Byte 0 ==
924 00:56:49.166729 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
925 00:56:49.170440 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
926 00:56:49.173441 == TX Byte 1 ==
927 00:56:49.177173 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
928 00:56:49.180359 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
929 00:56:49.183531 ==
930 00:56:49.187295 Dram Type= 6, Freq= 0, CH_0, rank 0
931 00:56:49.190267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 00:56:49.190351 ==
933 00:56:49.203241 TX Vref=22, minBit 7, minWin=27, winSum=440
934 00:56:49.206590 TX Vref=24, minBit 7, minWin=27, winSum=444
935 00:56:49.210087 TX Vref=26, minBit 11, minWin=27, winSum=450
936 00:56:49.213278 TX Vref=28, minBit 13, minWin=27, winSum=452
937 00:56:49.216576 TX Vref=30, minBit 5, minWin=28, winSum=455
938 00:56:49.223236 TX Vref=32, minBit 3, minWin=28, winSum=455
939 00:56:49.226760 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 30
940 00:56:49.226846
941 00:56:49.230239 Final TX Range 1 Vref 30
942 00:56:49.230326
943 00:56:49.230394 ==
944 00:56:49.233218 Dram Type= 6, Freq= 0, CH_0, rank 0
945 00:56:49.236725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 00:56:49.236812 ==
947 00:56:49.239909
948 00:56:49.239994
949 00:56:49.240060 TX Vref Scan disable
950 00:56:49.243561 == TX Byte 0 ==
951 00:56:49.247161 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
952 00:56:49.250118 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
953 00:56:49.253320 == TX Byte 1 ==
954 00:56:49.256883 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
955 00:56:49.260466 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
956 00:56:49.260550
957 00:56:49.263737 [DATLAT]
958 00:56:49.263821 Freq=800, CH0 RK0
959 00:56:49.263887
960 00:56:49.267221 DATLAT Default: 0xa
961 00:56:49.267304 0, 0xFFFF, sum = 0
962 00:56:49.270474 1, 0xFFFF, sum = 0
963 00:56:49.270558 2, 0xFFFF, sum = 0
964 00:56:49.273680 3, 0xFFFF, sum = 0
965 00:56:49.273766 4, 0xFFFF, sum = 0
966 00:56:49.277141 5, 0xFFFF, sum = 0
967 00:56:49.277226 6, 0xFFFF, sum = 0
968 00:56:49.280473 7, 0xFFFF, sum = 0
969 00:56:49.280558 8, 0xFFFF, sum = 0
970 00:56:49.283606 9, 0x0, sum = 1
971 00:56:49.283691 10, 0x0, sum = 2
972 00:56:49.287124 11, 0x0, sum = 3
973 00:56:49.287209 12, 0x0, sum = 4
974 00:56:49.290463 best_step = 10
975 00:56:49.290547
976 00:56:49.290613 ==
977 00:56:49.294006 Dram Type= 6, Freq= 0, CH_0, rank 0
978 00:56:49.297262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
979 00:56:49.297347 ==
980 00:56:49.300567 RX Vref Scan: 1
981 00:56:49.300653
982 00:56:49.300720 Set Vref Range= 32 -> 127
983 00:56:49.300780
984 00:56:49.303966 RX Vref 32 -> 127, step: 1
985 00:56:49.304051
986 00:56:49.307386 RX Delay -79 -> 252, step: 8
987 00:56:49.307549
988 00:56:49.310561 Set Vref, RX VrefLevel [Byte0]: 32
989 00:56:49.313587 [Byte1]: 32
990 00:56:49.313757
991 00:56:49.317397 Set Vref, RX VrefLevel [Byte0]: 33
992 00:56:49.320672 [Byte1]: 33
993 00:56:49.323902
994 00:56:49.324062 Set Vref, RX VrefLevel [Byte0]: 34
995 00:56:49.327096 [Byte1]: 34
996 00:56:49.331560
997 00:56:49.331754 Set Vref, RX VrefLevel [Byte0]: 35
998 00:56:49.334574 [Byte1]: 35
999 00:56:49.339182
1000 00:56:49.339356 Set Vref, RX VrefLevel [Byte0]: 36
1001 00:56:49.342028 [Byte1]: 36
1002 00:56:49.346269
1003 00:56:49.346446 Set Vref, RX VrefLevel [Byte0]: 37
1004 00:56:49.349752 [Byte1]: 37
1005 00:56:49.354171
1006 00:56:49.354364 Set Vref, RX VrefLevel [Byte0]: 38
1007 00:56:49.357202 [Byte1]: 38
1008 00:56:49.361544
1009 00:56:49.361760 Set Vref, RX VrefLevel [Byte0]: 39
1010 00:56:49.365254 [Byte1]: 39
1011 00:56:49.368910
1012 00:56:49.369152 Set Vref, RX VrefLevel [Byte0]: 40
1013 00:56:49.372716 [Byte1]: 40
1014 00:56:49.377194
1015 00:56:49.377520 Set Vref, RX VrefLevel [Byte0]: 41
1016 00:56:49.380487 [Byte1]: 41
1017 00:56:49.385302
1018 00:56:49.385638 Set Vref, RX VrefLevel [Byte0]: 42
1019 00:56:49.388332 [Byte1]: 42
1020 00:56:49.392224
1021 00:56:49.392636 Set Vref, RX VrefLevel [Byte0]: 43
1022 00:56:49.395739 [Byte1]: 43
1023 00:56:49.399854
1024 00:56:49.400342 Set Vref, RX VrefLevel [Byte0]: 44
1025 00:56:49.403049 [Byte1]: 44
1026 00:56:49.407345
1027 00:56:49.407774 Set Vref, RX VrefLevel [Byte0]: 45
1028 00:56:49.410580 [Byte1]: 45
1029 00:56:49.414886
1030 00:56:49.415064 Set Vref, RX VrefLevel [Byte0]: 46
1031 00:56:49.418127 [Byte1]: 46
1032 00:56:49.421917
1033 00:56:49.422069 Set Vref, RX VrefLevel [Byte0]: 47
1034 00:56:49.424972 [Byte1]: 47
1035 00:56:49.429205
1036 00:56:49.429320 Set Vref, RX VrefLevel [Byte0]: 48
1037 00:56:49.432621 [Byte1]: 48
1038 00:56:49.436703
1039 00:56:49.436794 Set Vref, RX VrefLevel [Byte0]: 49
1040 00:56:49.440084 [Byte1]: 49
1041 00:56:49.444200
1042 00:56:49.444291 Set Vref, RX VrefLevel [Byte0]: 50
1043 00:56:49.447650 [Byte1]: 50
1044 00:56:49.452054
1045 00:56:49.452179 Set Vref, RX VrefLevel [Byte0]: 51
1046 00:56:49.455172 [Byte1]: 51
1047 00:56:49.459665
1048 00:56:49.459756 Set Vref, RX VrefLevel [Byte0]: 52
1049 00:56:49.462939 [Byte1]: 52
1050 00:56:49.467390
1051 00:56:49.467472 Set Vref, RX VrefLevel [Byte0]: 53
1052 00:56:49.470491 [Byte1]: 53
1053 00:56:49.474461
1054 00:56:49.474544 Set Vref, RX VrefLevel [Byte0]: 54
1055 00:56:49.477796 [Byte1]: 54
1056 00:56:49.481929
1057 00:56:49.482022 Set Vref, RX VrefLevel [Byte0]: 55
1058 00:56:49.485324 [Byte1]: 55
1059 00:56:49.489679
1060 00:56:49.489762 Set Vref, RX VrefLevel [Byte0]: 56
1061 00:56:49.493073 [Byte1]: 56
1062 00:56:49.497100
1063 00:56:49.497183 Set Vref, RX VrefLevel [Byte0]: 57
1064 00:56:49.500533 [Byte1]: 57
1065 00:56:49.504617
1066 00:56:49.504726 Set Vref, RX VrefLevel [Byte0]: 58
1067 00:56:49.508041 [Byte1]: 58
1068 00:56:49.512393
1069 00:56:49.512476 Set Vref, RX VrefLevel [Byte0]: 59
1070 00:56:49.515345 [Byte1]: 59
1071 00:56:49.520219
1072 00:56:49.520302 Set Vref, RX VrefLevel [Byte0]: 60
1073 00:56:49.523486 [Byte1]: 60
1074 00:56:49.527282
1075 00:56:49.527364 Set Vref, RX VrefLevel [Byte0]: 61
1076 00:56:49.530498 [Byte1]: 61
1077 00:56:49.534923
1078 00:56:49.535005 Set Vref, RX VrefLevel [Byte0]: 62
1079 00:56:49.538375 [Byte1]: 62
1080 00:56:49.542538
1081 00:56:49.542622 Set Vref, RX VrefLevel [Byte0]: 63
1082 00:56:49.545774 [Byte1]: 63
1083 00:56:49.549891
1084 00:56:49.550024 Set Vref, RX VrefLevel [Byte0]: 64
1085 00:56:49.553485 [Byte1]: 64
1086 00:56:49.557831
1087 00:56:49.557946 Set Vref, RX VrefLevel [Byte0]: 65
1088 00:56:49.560782 [Byte1]: 65
1089 00:56:49.564928
1090 00:56:49.565012 Set Vref, RX VrefLevel [Byte0]: 66
1091 00:56:49.568218 [Byte1]: 66
1092 00:56:49.572592
1093 00:56:49.572675 Set Vref, RX VrefLevel [Byte0]: 67
1094 00:56:49.576117 [Byte1]: 67
1095 00:56:49.580187
1096 00:56:49.580270 Set Vref, RX VrefLevel [Byte0]: 68
1097 00:56:49.583634 [Byte1]: 68
1098 00:56:49.587956
1099 00:56:49.588040 Set Vref, RX VrefLevel [Byte0]: 69
1100 00:56:49.590896 [Byte1]: 69
1101 00:56:49.595428
1102 00:56:49.595512 Set Vref, RX VrefLevel [Byte0]: 70
1103 00:56:49.598658 [Byte1]: 70
1104 00:56:49.602704
1105 00:56:49.602792 Set Vref, RX VrefLevel [Byte0]: 71
1106 00:56:49.605963 [Byte1]: 71
1107 00:56:49.610548
1108 00:56:49.610631 Set Vref, RX VrefLevel [Byte0]: 72
1109 00:56:49.613507 [Byte1]: 72
1110 00:56:49.618093
1111 00:56:49.618176 Set Vref, RX VrefLevel [Byte0]: 73
1112 00:56:49.621270 [Byte1]: 73
1113 00:56:49.625478
1114 00:56:49.625562 Set Vref, RX VrefLevel [Byte0]: 74
1115 00:56:49.628925 [Byte1]: 74
1116 00:56:49.632919
1117 00:56:49.633002 Set Vref, RX VrefLevel [Byte0]: 75
1118 00:56:49.636300 [Byte1]: 75
1119 00:56:49.640650
1120 00:56:49.640732 Set Vref, RX VrefLevel [Byte0]: 76
1121 00:56:49.643854 [Byte1]: 76
1122 00:56:49.648498
1123 00:56:49.648581 Set Vref, RX VrefLevel [Byte0]: 77
1124 00:56:49.651805 [Byte1]: 77
1125 00:56:49.655691
1126 00:56:49.655774 Set Vref, RX VrefLevel [Byte0]: 78
1127 00:56:49.658843 [Byte1]: 78
1128 00:56:49.663343
1129 00:56:49.663426 Set Vref, RX VrefLevel [Byte0]: 79
1130 00:56:49.666489 [Byte1]: 79
1131 00:56:49.670856
1132 00:56:49.670940 Final RX Vref Byte 0 = 61 to rank0
1133 00:56:49.674581 Final RX Vref Byte 1 = 62 to rank0
1134 00:56:49.677699 Final RX Vref Byte 0 = 61 to rank1
1135 00:56:49.680584 Final RX Vref Byte 1 = 62 to rank1==
1136 00:56:49.684331 Dram Type= 6, Freq= 0, CH_0, rank 0
1137 00:56:49.690971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 00:56:49.691059 ==
1139 00:56:49.691126 DQS Delay:
1140 00:56:49.691187 DQS0 = 0, DQS1 = 0
1141 00:56:49.694285 DQM Delay:
1142 00:56:49.694369 DQM0 = 93, DQM1 = 83
1143 00:56:49.697579 DQ Delay:
1144 00:56:49.700849 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1145 00:56:49.703979 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1146 00:56:49.707456 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1147 00:56:49.710929 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1148 00:56:49.711013
1149 00:56:49.711079
1150 00:56:49.717640 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1151 00:56:49.721124 CH0 RK0: MR19=606, MR18=3A35
1152 00:56:49.727370 CH0_RK0: MR19=0x606, MR18=0x3A35, DQSOSC=395, MR23=63, INC=94, DEC=63
1153 00:56:49.727454
1154 00:56:49.730947 ----->DramcWriteLeveling(PI) begin...
1155 00:56:49.731032 ==
1156 00:56:49.734340 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 00:56:49.737497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 00:56:49.737580 ==
1159 00:56:49.741099 Write leveling (Byte 0): 32 => 32
1160 00:56:49.744756 Write leveling (Byte 1): 27 => 27
1161 00:56:49.747667 DramcWriteLeveling(PI) end<-----
1162 00:56:49.747750
1163 00:56:49.747815 ==
1164 00:56:49.751046 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 00:56:49.754306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1166 00:56:49.754391 ==
1167 00:56:49.758032 [Gating] SW mode calibration
1168 00:56:49.764295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1169 00:56:49.771131 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1170 00:56:49.774577 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1171 00:56:49.777803 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 00:56:49.825608 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1173 00:56:49.825911 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:56:49.826159 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:56:49.826587 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:56:49.826757 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:56:49.826910 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:56:49.827059 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:56:49.827206 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:56:49.827351 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 00:56:49.827496 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 00:56:49.870208 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 00:56:49.870780 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 00:56:49.871176 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 00:56:49.871649 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:56:49.872520 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1187 00:56:49.873040 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1188 00:56:49.873363 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1189 00:56:49.873667 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:56:49.873996 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:56:49.874299 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:56:49.874588 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:56:49.892874 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 00:56:49.893826 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 00:56:49.894253 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1196 00:56:49.894580 0 9 8 | B1->B0 | 3232 3434 | 0 0 | (0 0) (1 1)
1197 00:56:49.894889 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 00:56:49.896595 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 00:56:49.903246 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 00:56:49.906698 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 00:56:49.910465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 00:56:49.917082 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 00:56:49.920458 0 10 4 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 0)
1204 00:56:49.923402 0 10 8 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
1205 00:56:49.930356 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:56:49.933651 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 00:56:49.936684 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 00:56:49.943652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 00:56:49.947035 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 00:56:49.950286 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 00:56:49.953513 0 11 4 | B1->B0 | 2c2c 3737 | 0 0 | (0 0) (0 0)
1212 00:56:49.960570 0 11 8 | B1->B0 | 3837 4545 | 1 0 | (0 0) (0 0)
1213 00:56:49.964201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 00:56:49.967853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 00:56:49.971624 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 00:56:49.977990 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 00:56:49.981565 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 00:56:49.984656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 00:56:49.988737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1220 00:56:49.995787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1221 00:56:49.999217 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 00:56:50.002247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 00:56:50.009082 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 00:56:50.012124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 00:56:50.015516 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 00:56:50.022452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 00:56:50.025788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 00:56:50.029101 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 00:56:50.035657 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 00:56:50.038856 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 00:56:50.042375 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 00:56:50.048896 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 00:56:50.052368 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 00:56:50.055760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 00:56:50.058631 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1236 00:56:50.065690 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 00:56:50.069003 Total UI for P1: 0, mck2ui 16
1238 00:56:50.072454 best dqsien dly found for B0: ( 0, 14, 4)
1239 00:56:50.075744 Total UI for P1: 0, mck2ui 16
1240 00:56:50.079226 best dqsien dly found for B1: ( 0, 14, 4)
1241 00:56:50.082357 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1242 00:56:50.085691 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1243 00:56:50.086283
1244 00:56:50.088900 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1245 00:56:50.092148 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1246 00:56:50.095556 [Gating] SW calibration Done
1247 00:56:50.096084 ==
1248 00:56:50.099007 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 00:56:50.102405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 00:56:50.102838 ==
1251 00:56:50.105456 RX Vref Scan: 0
1252 00:56:50.105874
1253 00:56:50.106315 RX Vref 0 -> 0, step: 1
1254 00:56:50.106827
1255 00:56:50.109051 RX Delay -130 -> 252, step: 16
1256 00:56:50.112524 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1257 00:56:50.119140 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1258 00:56:50.122343 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1259 00:56:50.126096 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1260 00:56:50.129407 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1261 00:56:50.132709 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1262 00:56:50.139127 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1263 00:56:50.142907 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1264 00:56:50.146286 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1265 00:56:50.149210 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1266 00:56:50.152851 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1267 00:56:50.159295 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1268 00:56:50.162575 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1269 00:56:50.166142 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1270 00:56:50.169308 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1271 00:56:50.172839 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1272 00:56:50.173367 ==
1273 00:56:50.175873 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 00:56:50.182551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 00:56:50.183087 ==
1276 00:56:50.183475 DQS Delay:
1277 00:56:50.185809 DQS0 = 0, DQS1 = 0
1278 00:56:50.186260 DQM Delay:
1279 00:56:50.186596 DQM0 = 90, DQM1 = 83
1280 00:56:50.189325 DQ Delay:
1281 00:56:50.192564 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1282 00:56:50.196338 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1283 00:56:50.199495 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1284 00:56:50.202933 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1285 00:56:50.203674
1286 00:56:50.204068
1287 00:56:50.204383 ==
1288 00:56:50.206074 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 00:56:50.209253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 00:56:50.209677 ==
1291 00:56:50.210054
1292 00:56:50.210373
1293 00:56:50.212605 TX Vref Scan disable
1294 00:56:50.213132 == TX Byte 0 ==
1295 00:56:50.219783 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1296 00:56:50.222597 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1297 00:56:50.223173 == TX Byte 1 ==
1298 00:56:50.229438 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1299 00:56:50.232741 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1300 00:56:50.233165 ==
1301 00:56:50.236442 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 00:56:50.239516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 00:56:50.239942 ==
1304 00:56:50.254191 TX Vref=22, minBit 1, minWin=27, winSum=448
1305 00:56:50.257806 TX Vref=24, minBit 8, minWin=27, winSum=449
1306 00:56:50.261174 TX Vref=26, minBit 4, minWin=28, winSum=455
1307 00:56:50.264425 TX Vref=28, minBit 4, minWin=28, winSum=455
1308 00:56:50.267240 TX Vref=30, minBit 8, minWin=28, winSum=460
1309 00:56:50.270775 TX Vref=32, minBit 0, minWin=28, winSum=460
1310 00:56:50.277648 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1311 00:56:50.278101
1312 00:56:50.280761 Final TX Range 1 Vref 30
1313 00:56:50.281171
1314 00:56:50.281492 ==
1315 00:56:50.284018 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 00:56:50.287515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 00:56:50.287928 ==
1318 00:56:50.288360
1319 00:56:50.288784
1320 00:56:50.290978 TX Vref Scan disable
1321 00:56:50.294648 == TX Byte 0 ==
1322 00:56:50.297831 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1323 00:56:50.301303 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1324 00:56:50.304290 == TX Byte 1 ==
1325 00:56:50.307579 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1326 00:56:50.310868 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1327 00:56:50.311307
1328 00:56:50.314872 [DATLAT]
1329 00:56:50.315282 Freq=800, CH0 RK1
1330 00:56:50.315606
1331 00:56:50.317803 DATLAT Default: 0xa
1332 00:56:50.318301 0, 0xFFFF, sum = 0
1333 00:56:50.321032 1, 0xFFFF, sum = 0
1334 00:56:50.321448 2, 0xFFFF, sum = 0
1335 00:56:50.324345 3, 0xFFFF, sum = 0
1336 00:56:50.324887 4, 0xFFFF, sum = 0
1337 00:56:50.327891 5, 0xFFFF, sum = 0
1338 00:56:50.328305 6, 0xFFFF, sum = 0
1339 00:56:50.330927 7, 0xFFFF, sum = 0
1340 00:56:50.331344 8, 0xFFFF, sum = 0
1341 00:56:50.334292 9, 0x0, sum = 1
1342 00:56:50.334722 10, 0x0, sum = 2
1343 00:56:50.337499 11, 0x0, sum = 3
1344 00:56:50.337914 12, 0x0, sum = 4
1345 00:56:50.341498 best_step = 10
1346 00:56:50.342087
1347 00:56:50.342427 ==
1348 00:56:50.344730 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 00:56:50.347843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 00:56:50.348362 ==
1351 00:56:50.351305 RX Vref Scan: 0
1352 00:56:50.351815
1353 00:56:50.352145 RX Vref 0 -> 0, step: 1
1354 00:56:50.352444
1355 00:56:50.354542 RX Delay -79 -> 252, step: 8
1356 00:56:50.361172 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1357 00:56:50.364567 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1358 00:56:50.367991 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1359 00:56:50.371169 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1360 00:56:50.374827 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1361 00:56:50.378237 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1362 00:56:50.384944 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1363 00:56:50.388179 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1364 00:56:50.391331 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1365 00:56:50.394818 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1366 00:56:50.398207 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1367 00:56:50.404963 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1368 00:56:50.407768 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1369 00:56:50.411192 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1370 00:56:50.414310 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1371 00:56:50.418074 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1372 00:56:50.421641 ==
1373 00:56:50.424914 Dram Type= 6, Freq= 0, CH_0, rank 1
1374 00:56:50.427970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 00:56:50.428386 ==
1376 00:56:50.428708 DQS Delay:
1377 00:56:50.431618 DQS0 = 0, DQS1 = 0
1378 00:56:50.432138 DQM Delay:
1379 00:56:50.434608 DQM0 = 91, DQM1 = 81
1380 00:56:50.435016 DQ Delay:
1381 00:56:50.438121 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =84
1382 00:56:50.441242 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1383 00:56:50.444609 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1384 00:56:50.448141 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1385 00:56:50.448654
1386 00:56:50.448977
1387 00:56:50.454830 [DQSOSCAuto] RK1, (LSB)MR18= 0x441d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1388 00:56:50.458180 CH0 RK1: MR19=606, MR18=441D
1389 00:56:50.464876 CH0_RK1: MR19=0x606, MR18=0x441D, DQSOSC=392, MR23=63, INC=96, DEC=64
1390 00:56:50.468075 [RxdqsGatingPostProcess] freq 800
1391 00:56:50.471580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1392 00:56:50.475002 Pre-setting of DQS Precalculation
1393 00:56:50.481619 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1394 00:56:50.482196 ==
1395 00:56:50.484966 Dram Type= 6, Freq= 0, CH_1, rank 0
1396 00:56:50.488375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 00:56:50.488908 ==
1398 00:56:50.494991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 00:56:50.501583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 00:56:50.509421 [CA 0] Center 36 (6~67) winsize 62
1401 00:56:50.512626 [CA 1] Center 36 (6~67) winsize 62
1402 00:56:50.515816 [CA 2] Center 35 (5~65) winsize 61
1403 00:56:50.519236 [CA 3] Center 34 (4~65) winsize 62
1404 00:56:50.522297 [CA 4] Center 34 (4~65) winsize 62
1405 00:56:50.525822 [CA 5] Center 34 (3~65) winsize 63
1406 00:56:50.526409
1407 00:56:50.529574 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1408 00:56:50.530235
1409 00:56:50.532824 [CATrainingPosCal] consider 1 rank data
1410 00:56:50.536007 u2DelayCellTimex100 = 270/100 ps
1411 00:56:50.539024 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1412 00:56:50.542474 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1413 00:56:50.549562 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1414 00:56:50.552910 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 00:56:50.556244 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1416 00:56:50.559495 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1417 00:56:50.560028
1418 00:56:50.562781 CA PerBit enable=1, Macro0, CA PI delay=34
1419 00:56:50.563322
1420 00:56:50.566067 [CBTSetCACLKResult] CA Dly = 34
1421 00:56:50.566598 CS Dly: 5 (0~36)
1422 00:56:50.566938 ==
1423 00:56:50.569528 Dram Type= 6, Freq= 0, CH_1, rank 1
1424 00:56:50.576004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 00:56:50.576803 ==
1426 00:56:50.579361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1427 00:56:50.586338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1428 00:56:50.595740 [CA 0] Center 36 (6~67) winsize 62
1429 00:56:50.598831 [CA 1] Center 37 (6~68) winsize 63
1430 00:56:50.602086 [CA 2] Center 35 (5~66) winsize 62
1431 00:56:50.605471 [CA 3] Center 34 (4~65) winsize 62
1432 00:56:50.608621 [CA 4] Center 34 (4~65) winsize 62
1433 00:56:50.611946 [CA 5] Center 34 (4~65) winsize 62
1434 00:56:50.612372
1435 00:56:50.615476 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1436 00:56:50.616007
1437 00:56:50.618859 [CATrainingPosCal] consider 2 rank data
1438 00:56:50.621880 u2DelayCellTimex100 = 270/100 ps
1439 00:56:50.625263 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 00:56:50.629108 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1441 00:56:50.633037 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 00:56:50.636680 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 00:56:50.640449 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 00:56:50.644385 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1445 00:56:50.644818
1446 00:56:50.648013 CA PerBit enable=1, Macro0, CA PI delay=34
1447 00:56:50.648645
1448 00:56:50.652037 [CBTSetCACLKResult] CA Dly = 34
1449 00:56:50.652514 CS Dly: 6 (0~38)
1450 00:56:50.652855
1451 00:56:50.655523 ----->DramcWriteLeveling(PI) begin...
1452 00:56:50.655950 ==
1453 00:56:50.659520 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 00:56:50.662904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 00:56:50.666573 ==
1456 00:56:50.667087 Write leveling (Byte 0): 25 => 25
1457 00:56:50.670035 Write leveling (Byte 1): 31 => 31
1458 00:56:50.672833 DramcWriteLeveling(PI) end<-----
1459 00:56:50.673256
1460 00:56:50.673586 ==
1461 00:56:50.676518 Dram Type= 6, Freq= 0, CH_1, rank 0
1462 00:56:50.683159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 00:56:50.683597 ==
1464 00:56:50.683944 [Gating] SW mode calibration
1465 00:56:50.692716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1466 00:56:50.696329 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1467 00:56:50.699959 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1468 00:56:50.706617 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:56:50.709922 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:56:50.713289 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:56:50.720042 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:56:50.723694 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:56:50.726743 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:56:50.733467 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:56:50.736681 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:56:50.740079 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 00:56:50.746748 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 00:56:50.749888 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 00:56:50.753225 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 00:56:50.756676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 00:56:50.763406 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:56:50.767089 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:56:50.770332 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1484 00:56:50.776864 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1485 00:56:50.780361 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:56:50.783833 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:56:50.790301 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:56:50.793909 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:56:50.797062 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:56:50.803326 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:56:50.806541 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:56:50.810417 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1493 00:56:50.817425 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 00:56:50.820674 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 00:56:50.823672 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 00:56:50.827202 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 00:56:50.833749 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 00:56:50.836991 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 00:56:50.840442 0 10 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1500 00:56:50.847195 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (1 0) (1 0)
1501 00:56:50.850075 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:56:50.853583 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:56:50.860496 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 00:56:50.863688 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 00:56:50.867420 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:56:50.873431 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:56:50.877403 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1508 00:56:50.880560 0 11 4 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
1509 00:56:50.887570 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 00:56:50.890714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 00:56:50.894021 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 00:56:50.900758 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 00:56:50.904289 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 00:56:50.907206 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 00:56:50.910278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 00:56:50.916884 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1517 00:56:50.920632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 00:56:50.927137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 00:56:50.930256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 00:56:50.933720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 00:56:50.936980 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 00:56:50.943646 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 00:56:50.947096 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 00:56:50.950309 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 00:56:50.956857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 00:56:50.960425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 00:56:50.963596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 00:56:50.970739 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 00:56:50.973835 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 00:56:50.977153 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 00:56:50.983394 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 00:56:50.987596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1533 00:56:50.990457 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 00:56:50.993655 Total UI for P1: 0, mck2ui 16
1535 00:56:50.997184 best dqsien dly found for B0: ( 0, 14, 4)
1536 00:56:51.000497 Total UI for P1: 0, mck2ui 16
1537 00:56:51.004065 best dqsien dly found for B1: ( 0, 14, 4)
1538 00:56:51.007150 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1539 00:56:51.010486 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1540 00:56:51.010908
1541 00:56:51.013541 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1542 00:56:51.017047 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1543 00:56:51.020617 [Gating] SW calibration Done
1544 00:56:51.021142 ==
1545 00:56:51.023857 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 00:56:51.030869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 00:56:51.031400 ==
1548 00:56:51.031738 RX Vref Scan: 0
1549 00:56:51.032051
1550 00:56:51.034108 RX Vref 0 -> 0, step: 1
1551 00:56:51.034635
1552 00:56:51.037501 RX Delay -130 -> 252, step: 16
1553 00:56:51.040771 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1554 00:56:51.043967 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1555 00:56:51.047602 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1556 00:56:51.050766 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1557 00:56:51.057224 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1558 00:56:51.060553 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1559 00:56:51.063910 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1560 00:56:51.067385 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1561 00:56:51.070513 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1562 00:56:51.077254 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1563 00:56:51.080534 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1564 00:56:51.083836 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1565 00:56:51.087505 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1566 00:56:51.090666 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1567 00:56:51.097507 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1568 00:56:51.100884 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1569 00:56:51.101411 ==
1570 00:56:51.104209 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 00:56:51.107076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 00:56:51.107591 ==
1573 00:56:51.110698 DQS Delay:
1574 00:56:51.111121 DQS0 = 0, DQS1 = 0
1575 00:56:51.111454 DQM Delay:
1576 00:56:51.114099 DQM0 = 87, DQM1 = 80
1577 00:56:51.114526 DQ Delay:
1578 00:56:51.117471 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1579 00:56:51.120775 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1580 00:56:51.123849 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1581 00:56:51.127263 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1582 00:56:51.127785
1583 00:56:51.128124
1584 00:56:51.128434 ==
1585 00:56:51.130474 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 00:56:51.137303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 00:56:51.137828 ==
1588 00:56:51.138187
1589 00:56:51.138502
1590 00:56:51.138798 TX Vref Scan disable
1591 00:56:51.140959 == TX Byte 0 ==
1592 00:56:51.143872 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1593 00:56:51.147567 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1594 00:56:51.150904 == TX Byte 1 ==
1595 00:56:51.154467 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1596 00:56:51.157505 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1597 00:56:51.161010 ==
1598 00:56:51.164291 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 00:56:51.167836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 00:56:51.168386 ==
1601 00:56:51.180189 TX Vref=22, minBit 15, minWin=26, winSum=446
1602 00:56:51.183812 TX Vref=24, minBit 13, minWin=27, winSum=452
1603 00:56:51.187245 TX Vref=26, minBit 8, minWin=27, winSum=457
1604 00:56:51.191226 TX Vref=28, minBit 8, minWin=28, winSum=459
1605 00:56:51.193689 TX Vref=30, minBit 15, minWin=27, winSum=459
1606 00:56:51.200745 TX Vref=32, minBit 15, minWin=27, winSum=458
1607 00:56:51.203878 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1608 00:56:51.204404
1609 00:56:51.206671 Final TX Range 1 Vref 28
1610 00:56:51.207094
1611 00:56:51.207424 ==
1612 00:56:51.210523 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 00:56:51.214676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 00:56:51.215102 ==
1615 00:56:51.215435
1616 00:56:51.215743
1617 00:56:51.218129 TX Vref Scan disable
1618 00:56:51.221380 == TX Byte 0 ==
1619 00:56:51.224926 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1620 00:56:51.228327 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1621 00:56:51.231339 == TX Byte 1 ==
1622 00:56:51.234654 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1623 00:56:51.238272 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1624 00:56:51.238804
1625 00:56:51.241566 [DATLAT]
1626 00:56:51.242120 Freq=800, CH1 RK0
1627 00:56:51.242465
1628 00:56:51.244669 DATLAT Default: 0xa
1629 00:56:51.245194 0, 0xFFFF, sum = 0
1630 00:56:51.248057 1, 0xFFFF, sum = 0
1631 00:56:51.248589 2, 0xFFFF, sum = 0
1632 00:56:51.251209 3, 0xFFFF, sum = 0
1633 00:56:51.251741 4, 0xFFFF, sum = 0
1634 00:56:51.254549 5, 0xFFFF, sum = 0
1635 00:56:51.255086 6, 0xFFFF, sum = 0
1636 00:56:51.258461 7, 0xFFFF, sum = 0
1637 00:56:51.258995 8, 0xFFFF, sum = 0
1638 00:56:51.261728 9, 0x0, sum = 1
1639 00:56:51.262377 10, 0x0, sum = 2
1640 00:56:51.264882 11, 0x0, sum = 3
1641 00:56:51.265419 12, 0x0, sum = 4
1642 00:56:51.268003 best_step = 10
1643 00:56:51.268442
1644 00:56:51.268965 ==
1645 00:56:51.271236 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 00:56:51.274742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 00:56:51.275288 ==
1648 00:56:51.275630 RX Vref Scan: 1
1649 00:56:51.278272
1650 00:56:51.278690 Set Vref Range= 32 -> 127
1651 00:56:51.279024
1652 00:56:51.281215 RX Vref 32 -> 127, step: 1
1653 00:56:51.281638
1654 00:56:51.284532 RX Delay -95 -> 252, step: 8
1655 00:56:51.284956
1656 00:56:51.288003 Set Vref, RX VrefLevel [Byte0]: 32
1657 00:56:51.291597 [Byte1]: 32
1658 00:56:51.292123
1659 00:56:51.295101 Set Vref, RX VrefLevel [Byte0]: 33
1660 00:56:51.297786 [Byte1]: 33
1661 00:56:51.298250
1662 00:56:51.301460 Set Vref, RX VrefLevel [Byte0]: 34
1663 00:56:51.304637 [Byte1]: 34
1664 00:56:51.308865
1665 00:56:51.309290 Set Vref, RX VrefLevel [Byte0]: 35
1666 00:56:51.311793 [Byte1]: 35
1667 00:56:51.316458
1668 00:56:51.316975 Set Vref, RX VrefLevel [Byte0]: 36
1669 00:56:51.319580 [Byte1]: 36
1670 00:56:51.323925
1671 00:56:51.324346 Set Vref, RX VrefLevel [Byte0]: 37
1672 00:56:51.327245 [Byte1]: 37
1673 00:56:51.331407
1674 00:56:51.331942 Set Vref, RX VrefLevel [Byte0]: 38
1675 00:56:51.335077 [Byte1]: 38
1676 00:56:51.339206
1677 00:56:51.339724 Set Vref, RX VrefLevel [Byte0]: 39
1678 00:56:51.342179 [Byte1]: 39
1679 00:56:51.346745
1680 00:56:51.347260 Set Vref, RX VrefLevel [Byte0]: 40
1681 00:56:51.349785 [Byte1]: 40
1682 00:56:51.354581
1683 00:56:51.355096 Set Vref, RX VrefLevel [Byte0]: 41
1684 00:56:51.357707 [Byte1]: 41
1685 00:56:51.362163
1686 00:56:51.362674 Set Vref, RX VrefLevel [Byte0]: 42
1687 00:56:51.365425 [Byte1]: 42
1688 00:56:51.369649
1689 00:56:51.370216 Set Vref, RX VrefLevel [Byte0]: 43
1690 00:56:51.373001 [Byte1]: 43
1691 00:56:51.377281
1692 00:56:51.377807 Set Vref, RX VrefLevel [Byte0]: 44
1693 00:56:51.383150 [Byte1]: 44
1694 00:56:51.383571
1695 00:56:51.387045 Set Vref, RX VrefLevel [Byte0]: 45
1696 00:56:51.390116 [Byte1]: 45
1697 00:56:51.390645
1698 00:56:51.393754 Set Vref, RX VrefLevel [Byte0]: 46
1699 00:56:51.396739 [Byte1]: 46
1700 00:56:51.397260
1701 00:56:51.400137 Set Vref, RX VrefLevel [Byte0]: 47
1702 00:56:51.403649 [Byte1]: 47
1703 00:56:51.407517
1704 00:56:51.408039 Set Vref, RX VrefLevel [Byte0]: 48
1705 00:56:51.410650 [Byte1]: 48
1706 00:56:51.415409
1707 00:56:51.415935 Set Vref, RX VrefLevel [Byte0]: 49
1708 00:56:51.418651 [Byte1]: 49
1709 00:56:51.423007
1710 00:56:51.423536 Set Vref, RX VrefLevel [Byte0]: 50
1711 00:56:51.426173 [Byte1]: 50
1712 00:56:51.430296
1713 00:56:51.430838 Set Vref, RX VrefLevel [Byte0]: 51
1714 00:56:51.433720 [Byte1]: 51
1715 00:56:51.438301
1716 00:56:51.438823 Set Vref, RX VrefLevel [Byte0]: 52
1717 00:56:51.441169 [Byte1]: 52
1718 00:56:51.445230
1719 00:56:51.445759 Set Vref, RX VrefLevel [Byte0]: 53
1720 00:56:51.448810 [Byte1]: 53
1721 00:56:51.453068
1722 00:56:51.453590 Set Vref, RX VrefLevel [Byte0]: 54
1723 00:56:51.456124 [Byte1]: 54
1724 00:56:51.460916
1725 00:56:51.461441 Set Vref, RX VrefLevel [Byte0]: 55
1726 00:56:51.464054 [Byte1]: 55
1727 00:56:51.468362
1728 00:56:51.468884 Set Vref, RX VrefLevel [Byte0]: 56
1729 00:56:51.471611 [Byte1]: 56
1730 00:56:51.475687
1731 00:56:51.476241 Set Vref, RX VrefLevel [Byte0]: 57
1732 00:56:51.479111 [Byte1]: 57
1733 00:56:51.483272
1734 00:56:51.483799 Set Vref, RX VrefLevel [Byte0]: 58
1735 00:56:51.487108 [Byte1]: 58
1736 00:56:51.490865
1737 00:56:51.491399 Set Vref, RX VrefLevel [Byte0]: 59
1738 00:56:51.494373 [Byte1]: 59
1739 00:56:51.498522
1740 00:56:51.499086 Set Vref, RX VrefLevel [Byte0]: 60
1741 00:56:51.501741 [Byte1]: 60
1742 00:56:51.505976
1743 00:56:51.506508 Set Vref, RX VrefLevel [Byte0]: 61
1744 00:56:51.509684 [Byte1]: 61
1745 00:56:51.513675
1746 00:56:51.514241 Set Vref, RX VrefLevel [Byte0]: 62
1747 00:56:51.516789 [Byte1]: 62
1748 00:56:51.521593
1749 00:56:51.522145 Set Vref, RX VrefLevel [Byte0]: 63
1750 00:56:51.524631 [Byte1]: 63
1751 00:56:51.529031
1752 00:56:51.529554 Set Vref, RX VrefLevel [Byte0]: 64
1753 00:56:51.532321 [Byte1]: 64
1754 00:56:51.536926
1755 00:56:51.537451 Set Vref, RX VrefLevel [Byte0]: 65
1756 00:56:51.540113 [Byte1]: 65
1757 00:56:51.544259
1758 00:56:51.544778 Set Vref, RX VrefLevel [Byte0]: 66
1759 00:56:51.547453 [Byte1]: 66
1760 00:56:51.552020
1761 00:56:51.552541 Set Vref, RX VrefLevel [Byte0]: 67
1762 00:56:51.555294 [Byte1]: 67
1763 00:56:51.559185
1764 00:56:51.559711 Set Vref, RX VrefLevel [Byte0]: 68
1765 00:56:51.562676 [Byte1]: 68
1766 00:56:51.567326
1767 00:56:51.567853 Set Vref, RX VrefLevel [Byte0]: 69
1768 00:56:51.570361 [Byte1]: 69
1769 00:56:51.574530
1770 00:56:51.575054 Set Vref, RX VrefLevel [Byte0]: 70
1771 00:56:51.578058 [Byte1]: 70
1772 00:56:51.582068
1773 00:56:51.582629 Set Vref, RX VrefLevel [Byte0]: 71
1774 00:56:51.585809 [Byte1]: 71
1775 00:56:51.589757
1776 00:56:51.590214 Set Vref, RX VrefLevel [Byte0]: 72
1777 00:56:51.592724 [Byte1]: 72
1778 00:56:51.597101
1779 00:56:51.597532 Set Vref, RX VrefLevel [Byte0]: 73
1780 00:56:51.600571 [Byte1]: 73
1781 00:56:51.604740
1782 00:56:51.605271 Set Vref, RX VrefLevel [Byte0]: 74
1783 00:56:51.608059 [Byte1]: 74
1784 00:56:51.612567
1785 00:56:51.613103 Set Vref, RX VrefLevel [Byte0]: 75
1786 00:56:51.615835 [Byte1]: 75
1787 00:56:51.620157
1788 00:56:51.620752 Set Vref, RX VrefLevel [Byte0]: 76
1789 00:56:51.623505 [Byte1]: 76
1790 00:56:51.627652
1791 00:56:51.628185 Set Vref, RX VrefLevel [Byte0]: 77
1792 00:56:51.631091 [Byte1]: 77
1793 00:56:51.635236
1794 00:56:51.635664 Set Vref, RX VrefLevel [Byte0]: 78
1795 00:56:51.638497 [Byte1]: 78
1796 00:56:51.643307
1797 00:56:51.643837 Set Vref, RX VrefLevel [Byte0]: 79
1798 00:56:51.646299 [Byte1]: 79
1799 00:56:51.650536
1800 00:56:51.651071 Final RX Vref Byte 0 = 51 to rank0
1801 00:56:51.654092 Final RX Vref Byte 1 = 63 to rank0
1802 00:56:51.657446 Final RX Vref Byte 0 = 51 to rank1
1803 00:56:51.660875 Final RX Vref Byte 1 = 63 to rank1==
1804 00:56:51.664120 Dram Type= 6, Freq= 0, CH_1, rank 0
1805 00:56:51.670872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 00:56:51.671455 ==
1807 00:56:51.671833 DQS Delay:
1808 00:56:51.672195 DQS0 = 0, DQS1 = 0
1809 00:56:51.674146 DQM Delay:
1810 00:56:51.674678 DQM0 = 91, DQM1 = 83
1811 00:56:51.677357 DQ Delay:
1812 00:56:51.680387 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1813 00:56:51.683885 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1814 00:56:51.684379 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1815 00:56:51.690752 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1816 00:56:51.691289
1817 00:56:51.691631
1818 00:56:51.697384 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1819 00:56:51.700841 CH1 RK0: MR19=606, MR18=314E
1820 00:56:51.707184 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1821 00:56:51.707691
1822 00:56:51.710091 ----->DramcWriteLeveling(PI) begin...
1823 00:56:51.710556 ==
1824 00:56:51.713500 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 00:56:51.716911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 00:56:51.717344 ==
1827 00:56:51.720953 Write leveling (Byte 0): 29 => 29
1828 00:56:51.723835 Write leveling (Byte 1): 31 => 31
1829 00:56:51.726815 DramcWriteLeveling(PI) end<-----
1830 00:56:51.727343
1831 00:56:51.727689 ==
1832 00:56:51.730206 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 00:56:51.734019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 00:56:51.734563 ==
1835 00:56:51.737262 [Gating] SW mode calibration
1836 00:56:51.743621 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1837 00:56:51.750612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1838 00:56:51.753817 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1839 00:56:51.757474 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1840 00:56:51.764115 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 00:56:51.771152 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 00:56:51.771635 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:56:51.777148 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:56:51.780954 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:56:51.783529 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:56:51.790823 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:56:51.793631 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 00:56:51.797245 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 00:56:51.804073 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 00:56:51.807439 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 00:56:51.810584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 00:56:51.814100 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 00:56:51.820457 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 00:56:51.824012 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1855 00:56:51.827389 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 00:56:51.834437 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 00:56:51.837478 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 00:56:51.840920 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:56:51.847249 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:56:51.851218 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:56:51.854802 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:56:51.861230 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:56:51.864472 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1864 00:56:51.867604 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 00:56:51.874431 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 00:56:51.877673 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 00:56:51.881121 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 00:56:51.884014 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 00:56:51.890723 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 00:56:51.893988 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1871 00:56:51.897540 0 10 4 | B1->B0 | 2a2a 2e2e | 0 0 | (0 0) (0 0)
1872 00:56:51.904422 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:56:51.907382 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 00:56:51.910552 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 00:56:51.917693 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:56:51.920924 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:56:51.924697 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:56:51.930769 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:56:51.934532 0 11 4 | B1->B0 | 2f2f 3131 | 1 1 | (0 0) (0 0)
1880 00:56:51.937916 0 11 8 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
1881 00:56:51.944007 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 00:56:51.947720 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 00:56:51.951096 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 00:56:51.957918 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 00:56:51.961254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 00:56:51.964872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 00:56:51.968130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1888 00:56:51.974679 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1889 00:56:51.977747 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 00:56:51.981396 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 00:56:51.987846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 00:56:51.990984 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 00:56:51.994472 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 00:56:52.001359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 00:56:52.004704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 00:56:52.007836 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 00:56:52.014382 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 00:56:52.017836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 00:56:52.021006 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 00:56:52.027581 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 00:56:52.031053 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 00:56:52.034020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 00:56:52.040997 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1904 00:56:52.044575 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 00:56:52.047664 Total UI for P1: 0, mck2ui 16
1906 00:56:52.051157 best dqsien dly found for B0: ( 0, 14, 4)
1907 00:56:52.054785 Total UI for P1: 0, mck2ui 16
1908 00:56:52.057536 best dqsien dly found for B1: ( 0, 14, 4)
1909 00:56:52.061083 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1910 00:56:52.064281 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1911 00:56:52.064865
1912 00:56:52.068015 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1913 00:56:52.071154 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1914 00:56:52.074606 [Gating] SW calibration Done
1915 00:56:52.075205 ==
1916 00:56:52.078021 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 00:56:52.081233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 00:56:52.081818 ==
1919 00:56:52.084333 RX Vref Scan: 0
1920 00:56:52.084904
1921 00:56:52.087557 RX Vref 0 -> 0, step: 1
1922 00:56:52.088126
1923 00:56:52.088500 RX Delay -130 -> 252, step: 16
1924 00:56:52.094122 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1925 00:56:52.098043 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1926 00:56:52.101281 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1927 00:56:52.104535 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1928 00:56:52.107641 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1929 00:56:52.111051 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1930 00:56:52.117898 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1931 00:56:52.121056 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1932 00:56:52.124915 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1933 00:56:52.127799 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1934 00:56:52.131030 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1935 00:56:52.137901 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1936 00:56:52.141236 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1937 00:56:52.144490 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1938 00:56:52.147918 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1939 00:56:52.154486 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1940 00:56:52.155055 ==
1941 00:56:52.157708 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 00:56:52.161306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 00:56:52.161881 ==
1944 00:56:52.162284 DQS Delay:
1945 00:56:52.164847 DQS0 = 0, DQS1 = 0
1946 00:56:52.165412 DQM Delay:
1947 00:56:52.167898 DQM0 = 93, DQM1 = 86
1948 00:56:52.168461 DQ Delay:
1949 00:56:52.171236 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1950 00:56:52.174724 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1951 00:56:52.177971 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1952 00:56:52.181441 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1953 00:56:52.182048
1954 00:56:52.182422
1955 00:56:52.182763 ==
1956 00:56:52.184452 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 00:56:52.187784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 00:56:52.188254 ==
1959 00:56:52.188625
1960 00:56:52.188963
1961 00:56:52.191190 TX Vref Scan disable
1962 00:56:52.194601 == TX Byte 0 ==
1963 00:56:52.198096 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 00:56:52.201127 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 00:56:52.204291 == TX Byte 1 ==
1966 00:56:52.207631 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1967 00:56:52.211133 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1968 00:56:52.211556 ==
1969 00:56:52.214987 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 00:56:52.217933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 00:56:52.220882 ==
1972 00:56:52.232786 TX Vref=22, minBit 12, minWin=27, winSum=449
1973 00:56:52.235886 TX Vref=24, minBit 13, minWin=27, winSum=454
1974 00:56:52.239152 TX Vref=26, minBit 13, minWin=27, winSum=455
1975 00:56:52.242562 TX Vref=28, minBit 9, minWin=28, winSum=458
1976 00:56:52.245866 TX Vref=30, minBit 8, minWin=28, winSum=459
1977 00:56:52.252500 TX Vref=32, minBit 15, minWin=27, winSum=456
1978 00:56:52.256381 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1979 00:56:52.256951
1980 00:56:52.259515 Final TX Range 1 Vref 30
1981 00:56:52.260108
1982 00:56:52.260483 ==
1983 00:56:52.262495 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 00:56:52.265781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 00:56:52.269704 ==
1986 00:56:52.270343
1987 00:56:52.270715
1988 00:56:52.271059 TX Vref Scan disable
1989 00:56:52.272921 == TX Byte 0 ==
1990 00:56:52.276028 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 00:56:52.279645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 00:56:52.282802 == TX Byte 1 ==
1993 00:56:52.286307 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1994 00:56:52.289791 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1995 00:56:52.292983
1996 00:56:52.293546 [DATLAT]
1997 00:56:52.293917 Freq=800, CH1 RK1
1998 00:56:52.294320
1999 00:56:52.296172 DATLAT Default: 0xa
2000 00:56:52.296635 0, 0xFFFF, sum = 0
2001 00:56:52.299649 1, 0xFFFF, sum = 0
2002 00:56:52.300077 2, 0xFFFF, sum = 0
2003 00:56:52.302855 3, 0xFFFF, sum = 0
2004 00:56:52.303282 4, 0xFFFF, sum = 0
2005 00:56:52.306651 5, 0xFFFF, sum = 0
2006 00:56:52.307179 6, 0xFFFF, sum = 0
2007 00:56:52.309888 7, 0xFFFF, sum = 0
2008 00:56:52.310355 8, 0xFFFF, sum = 0
2009 00:56:52.312914 9, 0x0, sum = 1
2010 00:56:52.313347 10, 0x0, sum = 2
2011 00:56:52.316138 11, 0x0, sum = 3
2012 00:56:52.316579 12, 0x0, sum = 4
2013 00:56:52.320061 best_step = 10
2014 00:56:52.320585
2015 00:56:52.320924 ==
2016 00:56:52.323043 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 00:56:52.326189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 00:56:52.326624 ==
2019 00:56:52.329461 RX Vref Scan: 0
2020 00:56:52.329889
2021 00:56:52.330268 RX Vref 0 -> 0, step: 1
2022 00:56:52.330591
2023 00:56:52.332784 RX Delay -79 -> 252, step: 8
2024 00:56:52.339500 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2025 00:56:52.342930 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2026 00:56:52.346604 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2027 00:56:52.349708 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2028 00:56:52.353026 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2029 00:56:52.356584 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2030 00:56:52.363052 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2031 00:56:52.366593 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2032 00:56:52.370004 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2033 00:56:52.373260 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2034 00:56:52.376661 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2035 00:56:52.383054 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2036 00:56:52.386471 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2037 00:56:52.390225 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2038 00:56:52.393456 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2039 00:56:52.396537 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2040 00:56:52.399840 ==
2041 00:56:52.403292 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 00:56:52.406638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 00:56:52.407205 ==
2044 00:56:52.407571 DQS Delay:
2045 00:56:52.409767 DQS0 = 0, DQS1 = 0
2046 00:56:52.410322 DQM Delay:
2047 00:56:52.412948 DQM0 = 90, DQM1 = 83
2048 00:56:52.413407 DQ Delay:
2049 00:56:52.416207 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2050 00:56:52.419692 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2051 00:56:52.422862 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2052 00:56:52.426441 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2053 00:56:52.426862
2054 00:56:52.427193
2055 00:56:52.433217 [DQSOSCAuto] RK1, (LSB)MR18= 0x370c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2056 00:56:52.436485 CH1 RK1: MR19=606, MR18=370C
2057 00:56:52.442865 CH1_RK1: MR19=0x606, MR18=0x370C, DQSOSC=395, MR23=63, INC=94, DEC=63
2058 00:56:52.446557 [RxdqsGatingPostProcess] freq 800
2059 00:56:52.449643 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2060 00:56:52.452866 Pre-setting of DQS Precalculation
2061 00:56:52.459736 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2062 00:56:52.466541 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2063 00:56:52.472779 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2064 00:56:52.473348
2065 00:56:52.473838
2066 00:56:52.476263 [Calibration Summary] 1600 Mbps
2067 00:56:52.479588 CH 0, Rank 0
2068 00:56:52.480177 SW Impedance : PASS
2069 00:56:52.483002 DUTY Scan : NO K
2070 00:56:52.483488 ZQ Calibration : PASS
2071 00:56:52.486461 Jitter Meter : NO K
2072 00:56:52.489770 CBT Training : PASS
2073 00:56:52.490302 Write leveling : PASS
2074 00:56:52.493587 RX DQS gating : PASS
2075 00:56:52.496932 RX DQ/DQS(RDDQC) : PASS
2076 00:56:52.497470 TX DQ/DQS : PASS
2077 00:56:52.499630 RX DATLAT : PASS
2078 00:56:52.503135 RX DQ/DQS(Engine): PASS
2079 00:56:52.503560 TX OE : NO K
2080 00:56:52.506629 All Pass.
2081 00:56:52.507055
2082 00:56:52.507387 CH 0, Rank 1
2083 00:56:52.510146 SW Impedance : PASS
2084 00:56:52.510566 DUTY Scan : NO K
2085 00:56:52.513366 ZQ Calibration : PASS
2086 00:56:52.516381 Jitter Meter : NO K
2087 00:56:52.516850 CBT Training : PASS
2088 00:56:52.520455 Write leveling : PASS
2089 00:56:52.521027 RX DQS gating : PASS
2090 00:56:52.523398 RX DQ/DQS(RDDQC) : PASS
2091 00:56:52.526733 TX DQ/DQS : PASS
2092 00:56:52.527296 RX DATLAT : PASS
2093 00:56:52.530187 RX DQ/DQS(Engine): PASS
2094 00:56:52.533421 TX OE : NO K
2095 00:56:52.534033 All Pass.
2096 00:56:52.534417
2097 00:56:52.534762 CH 1, Rank 0
2098 00:56:52.536384 SW Impedance : PASS
2099 00:56:52.539675 DUTY Scan : NO K
2100 00:56:52.540243 ZQ Calibration : PASS
2101 00:56:52.543294 Jitter Meter : NO K
2102 00:56:52.546456 CBT Training : PASS
2103 00:56:52.547018 Write leveling : PASS
2104 00:56:52.549456 RX DQS gating : PASS
2105 00:56:52.552914 RX DQ/DQS(RDDQC) : PASS
2106 00:56:52.553717 TX DQ/DQS : PASS
2107 00:56:52.556544 RX DATLAT : PASS
2108 00:56:52.559467 RX DQ/DQS(Engine): PASS
2109 00:56:52.560104 TX OE : NO K
2110 00:56:52.562748 All Pass.
2111 00:56:52.563314
2112 00:56:52.563687 CH 1, Rank 1
2113 00:56:52.566838 SW Impedance : PASS
2114 00:56:52.567395 DUTY Scan : NO K
2115 00:56:52.569901 ZQ Calibration : PASS
2116 00:56:52.572946 Jitter Meter : NO K
2117 00:56:52.573689 CBT Training : PASS
2118 00:56:52.576298 Write leveling : PASS
2119 00:56:52.576886 RX DQS gating : PASS
2120 00:56:52.579579 RX DQ/DQS(RDDQC) : PASS
2121 00:56:52.582812 TX DQ/DQS : PASS
2122 00:56:52.583398 RX DATLAT : PASS
2123 00:56:52.586366 RX DQ/DQS(Engine): PASS
2124 00:56:52.589883 TX OE : NO K
2125 00:56:52.590369 All Pass.
2126 00:56:52.590804
2127 00:56:52.593103 DramC Write-DBI off
2128 00:56:52.593540 PER_BANK_REFRESH: Hybrid Mode
2129 00:56:52.596375 TX_TRACKING: ON
2130 00:56:52.599646 [GetDramInforAfterCalByMRR] Vendor 6.
2131 00:56:52.602897 [GetDramInforAfterCalByMRR] Revision 606.
2132 00:56:52.606351 [GetDramInforAfterCalByMRR] Revision 2 0.
2133 00:56:52.606794 MR0 0x3b3b
2134 00:56:52.609521 MR8 0x5151
2135 00:56:52.613117 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 00:56:52.613548
2137 00:56:52.613885 MR0 0x3b3b
2138 00:56:52.614243 MR8 0x5151
2139 00:56:52.619677 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2140 00:56:52.620110
2141 00:56:52.626380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2142 00:56:52.629716 [FAST_K] Save calibration result to emmc
2143 00:56:52.633124 [FAST_K] Save calibration result to emmc
2144 00:56:52.636793 dram_init: config_dvfs: 1
2145 00:56:52.640189 dramc_set_vcore_voltage set vcore to 662500
2146 00:56:52.643349 Read voltage for 1200, 2
2147 00:56:52.643927 Vio18 = 0
2148 00:56:52.646545 Vcore = 662500
2149 00:56:52.647116 Vdram = 0
2150 00:56:52.647491 Vddq = 0
2151 00:56:52.647839 Vmddr = 0
2152 00:56:52.653592 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2153 00:56:52.659947 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2154 00:56:52.660526 MEM_TYPE=3, freq_sel=15
2155 00:56:52.663688 sv_algorithm_assistance_LP4_1600
2156 00:56:52.666632 ============ PULL DRAM RESETB DOWN ============
2157 00:56:52.673517 ========== PULL DRAM RESETB DOWN end =========
2158 00:56:52.676941 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2159 00:56:52.680078 ===================================
2160 00:56:52.683287 LPDDR4 DRAM CONFIGURATION
2161 00:56:52.686549 ===================================
2162 00:56:52.687115 EX_ROW_EN[0] = 0x0
2163 00:56:52.690098 EX_ROW_EN[1] = 0x0
2164 00:56:52.690566 LP4Y_EN = 0x0
2165 00:56:52.693354 WORK_FSP = 0x0
2166 00:56:52.693825 WL = 0x4
2167 00:56:52.696515 RL = 0x4
2168 00:56:52.696939 BL = 0x2
2169 00:56:52.699988 RPST = 0x0
2170 00:56:52.700458 RD_PRE = 0x0
2171 00:56:52.703463 WR_PRE = 0x1
2172 00:56:52.703934 WR_PST = 0x0
2173 00:56:52.706956 DBI_WR = 0x0
2174 00:56:52.710166 DBI_RD = 0x0
2175 00:56:52.710691 OTF = 0x1
2176 00:56:52.713083 ===================================
2177 00:56:52.716389 ===================================
2178 00:56:52.716856 ANA top config
2179 00:56:52.720014 ===================================
2180 00:56:52.723692 DLL_ASYNC_EN = 0
2181 00:56:52.726842 ALL_SLAVE_EN = 0
2182 00:56:52.729716 NEW_RANK_MODE = 1
2183 00:56:52.730174 DLL_IDLE_MODE = 1
2184 00:56:52.733306 LP45_APHY_COMB_EN = 1
2185 00:56:52.736436 TX_ODT_DIS = 1
2186 00:56:52.739759 NEW_8X_MODE = 1
2187 00:56:52.743207 ===================================
2188 00:56:52.746393 ===================================
2189 00:56:52.749466 data_rate = 2400
2190 00:56:52.753244 CKR = 1
2191 00:56:52.753672 DQ_P2S_RATIO = 8
2192 00:56:52.756623 ===================================
2193 00:56:52.760043 CA_P2S_RATIO = 8
2194 00:56:52.763380 DQ_CA_OPEN = 0
2195 00:56:52.766913 DQ_SEMI_OPEN = 0
2196 00:56:52.769917 CA_SEMI_OPEN = 0
2197 00:56:52.770380 CA_FULL_RATE = 0
2198 00:56:52.773179 DQ_CKDIV4_EN = 0
2199 00:56:52.776957 CA_CKDIV4_EN = 0
2200 00:56:52.780085 CA_PREDIV_EN = 0
2201 00:56:52.783198 PH8_DLY = 17
2202 00:56:52.786668 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2203 00:56:52.787194 DQ_AAMCK_DIV = 4
2204 00:56:52.789981 CA_AAMCK_DIV = 4
2205 00:56:52.793386 CA_ADMCK_DIV = 4
2206 00:56:52.797019 DQ_TRACK_CA_EN = 0
2207 00:56:52.800110 CA_PICK = 1200
2208 00:56:52.803307 CA_MCKIO = 1200
2209 00:56:52.806762 MCKIO_SEMI = 0
2210 00:56:52.807188 PLL_FREQ = 2366
2211 00:56:52.809884 DQ_UI_PI_RATIO = 32
2212 00:56:52.813392 CA_UI_PI_RATIO = 0
2213 00:56:52.816503 ===================================
2214 00:56:52.820598 ===================================
2215 00:56:52.823641 memory_type:LPDDR4
2216 00:56:52.824066 GP_NUM : 10
2217 00:56:52.827259 SRAM_EN : 1
2218 00:56:52.830201 MD32_EN : 0
2219 00:56:52.833879 ===================================
2220 00:56:52.834447 [ANA_INIT] >>>>>>>>>>>>>>
2221 00:56:52.837208 <<<<<< [CONFIGURE PHASE]: ANA_TX
2222 00:56:52.840138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2223 00:56:52.843767 ===================================
2224 00:56:52.847119 data_rate = 2400,PCW = 0X5b00
2225 00:56:52.850560 ===================================
2226 00:56:52.853919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2227 00:56:52.860498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2228 00:56:52.863710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 00:56:52.870859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2230 00:56:52.873574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2231 00:56:52.877228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2232 00:56:52.877784 [ANA_INIT] flow start
2233 00:56:52.880572 [ANA_INIT] PLL >>>>>>>>
2234 00:56:52.883675 [ANA_INIT] PLL <<<<<<<<
2235 00:56:52.884144 [ANA_INIT] MIDPI >>>>>>>>
2236 00:56:52.886898 [ANA_INIT] MIDPI <<<<<<<<
2237 00:56:52.890360 [ANA_INIT] DLL >>>>>>>>
2238 00:56:52.890826 [ANA_INIT] DLL <<<<<<<<
2239 00:56:52.893633 [ANA_INIT] flow end
2240 00:56:52.896916 ============ LP4 DIFF to SE enter ============
2241 00:56:52.903674 ============ LP4 DIFF to SE exit ============
2242 00:56:52.904267 [ANA_INIT] <<<<<<<<<<<<<
2243 00:56:52.907543 [Flow] Enable top DCM control >>>>>
2244 00:56:52.910303 [Flow] Enable top DCM control <<<<<
2245 00:56:52.913680 Enable DLL master slave shuffle
2246 00:56:52.921098 ==============================================================
2247 00:56:52.921684 Gating Mode config
2248 00:56:52.927198 ==============================================================
2249 00:56:52.927782 Config description:
2250 00:56:52.937584 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2251 00:56:52.944218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2252 00:56:52.950816 SELPH_MODE 0: By rank 1: By Phase
2253 00:56:52.954086 ==============================================================
2254 00:56:52.957378 GAT_TRACK_EN = 1
2255 00:56:52.960820 RX_GATING_MODE = 2
2256 00:56:52.964054 RX_GATING_TRACK_MODE = 2
2257 00:56:52.967457 SELPH_MODE = 1
2258 00:56:52.970717 PICG_EARLY_EN = 1
2259 00:56:52.974218 VALID_LAT_VALUE = 1
2260 00:56:52.977627 ==============================================================
2261 00:56:52.983895 Enter into Gating configuration >>>>
2262 00:56:52.984451 Exit from Gating configuration <<<<
2263 00:56:52.987287 Enter into DVFS_PRE_config >>>>>
2264 00:56:53.000950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2265 00:56:53.004200 Exit from DVFS_PRE_config <<<<<
2266 00:56:53.007297 Enter into PICG configuration >>>>
2267 00:56:53.007775 Exit from PICG configuration <<<<
2268 00:56:53.010980 [RX_INPUT] configuration >>>>>
2269 00:56:53.014479 [RX_INPUT] configuration <<<<<
2270 00:56:53.020628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2271 00:56:53.024229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2272 00:56:53.030929 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2273 00:56:53.037871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2274 00:56:53.044013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 00:56:53.050798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 00:56:53.054293 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2277 00:56:53.057648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2278 00:56:53.061348 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2279 00:56:53.067904 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2280 00:56:53.071380 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2281 00:56:53.074744 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 00:56:53.077837 ===================================
2283 00:56:53.081974 LPDDR4 DRAM CONFIGURATION
2284 00:56:53.084607 ===================================
2285 00:56:53.085172 EX_ROW_EN[0] = 0x0
2286 00:56:53.087885 EX_ROW_EN[1] = 0x0
2287 00:56:53.088358 LP4Y_EN = 0x0
2288 00:56:53.091603 WORK_FSP = 0x0
2289 00:56:53.094405 WL = 0x4
2290 00:56:53.094878 RL = 0x4
2291 00:56:53.097784 BL = 0x2
2292 00:56:53.098293 RPST = 0x0
2293 00:56:53.101359 RD_PRE = 0x0
2294 00:56:53.101881 WR_PRE = 0x1
2295 00:56:53.104725 WR_PST = 0x0
2296 00:56:53.105196 DBI_WR = 0x0
2297 00:56:53.108015 DBI_RD = 0x0
2298 00:56:53.108487 OTF = 0x1
2299 00:56:53.111239 ===================================
2300 00:56:53.114771 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2301 00:56:53.117987 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2302 00:56:53.124653 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 00:56:53.128135 ===================================
2304 00:56:53.131365 LPDDR4 DRAM CONFIGURATION
2305 00:56:53.134762 ===================================
2306 00:56:53.135237 EX_ROW_EN[0] = 0x10
2307 00:56:53.137873 EX_ROW_EN[1] = 0x0
2308 00:56:53.138376 LP4Y_EN = 0x0
2309 00:56:53.141115 WORK_FSP = 0x0
2310 00:56:53.141574 WL = 0x4
2311 00:56:53.144755 RL = 0x4
2312 00:56:53.145174 BL = 0x2
2313 00:56:53.148138 RPST = 0x0
2314 00:56:53.148554 RD_PRE = 0x0
2315 00:56:53.151131 WR_PRE = 0x1
2316 00:56:53.151553 WR_PST = 0x0
2317 00:56:53.154673 DBI_WR = 0x0
2318 00:56:53.155089 DBI_RD = 0x0
2319 00:56:53.157878 OTF = 0x1
2320 00:56:53.161215 ===================================
2321 00:56:53.168368 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2322 00:56:53.168886 ==
2323 00:56:53.171596 Dram Type= 6, Freq= 0, CH_0, rank 0
2324 00:56:53.174771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2325 00:56:53.175289 ==
2326 00:56:53.178070 [Duty_Offset_Calibration]
2327 00:56:53.178633 B0:2 B1:0 CA:1
2328 00:56:53.178969
2329 00:56:53.181382 [DutyScan_Calibration_Flow] k_type=0
2330 00:56:53.191011
2331 00:56:53.191611 ==CLK 0==
2332 00:56:53.194369 Final CLK duty delay cell = -4
2333 00:56:53.197789 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2334 00:56:53.201319 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2335 00:56:53.204672 [-4] AVG Duty = 4953%(X100)
2336 00:56:53.205090
2337 00:56:53.208111 CH0 CLK Duty spec in!! Max-Min= 156%
2338 00:56:53.211434 [DutyScan_Calibration_Flow] ====Done====
2339 00:56:53.211858
2340 00:56:53.214433 [DutyScan_Calibration_Flow] k_type=1
2341 00:56:53.229907
2342 00:56:53.230492 ==DQS 0 ==
2343 00:56:53.233239 Final DQS duty delay cell = 0
2344 00:56:53.236881 [0] MAX Duty = 5187%(X100), DQS PI = 30
2345 00:56:53.240670 [0] MIN Duty = 4938%(X100), DQS PI = 0
2346 00:56:53.241245 [0] AVG Duty = 5062%(X100)
2347 00:56:53.241614
2348 00:56:53.243385 ==DQS 1 ==
2349 00:56:53.246782 Final DQS duty delay cell = -4
2350 00:56:53.250263 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2351 00:56:53.253625 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2352 00:56:53.254139 [-4] AVG Duty = 5015%(X100)
2353 00:56:53.257112
2354 00:56:53.260389 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2355 00:56:53.260850
2356 00:56:53.263873 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2357 00:56:53.267058 [DutyScan_Calibration_Flow] ====Done====
2358 00:56:53.267610
2359 00:56:53.270303 [DutyScan_Calibration_Flow] k_type=3
2360 00:56:53.286667
2361 00:56:53.287234 ==DQM 0 ==
2362 00:56:53.290101 Final DQM duty delay cell = 0
2363 00:56:53.293218 [0] MAX Duty = 5062%(X100), DQS PI = 24
2364 00:56:53.296555 [0] MIN Duty = 4813%(X100), DQS PI = 0
2365 00:56:53.300433 [0] AVG Duty = 4937%(X100)
2366 00:56:53.300984
2367 00:56:53.301347 ==DQM 1 ==
2368 00:56:53.303138 Final DQM duty delay cell = 0
2369 00:56:53.306677 [0] MAX Duty = 5218%(X100), DQS PI = 48
2370 00:56:53.310035 [0] MIN Duty = 5000%(X100), DQS PI = 14
2371 00:56:53.310499 [0] AVG Duty = 5109%(X100)
2372 00:56:53.313514
2373 00:56:53.316629 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2374 00:56:53.317090
2375 00:56:53.320068 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2376 00:56:53.323611 [DutyScan_Calibration_Flow] ====Done====
2377 00:56:53.324175
2378 00:56:53.326600 [DutyScan_Calibration_Flow] k_type=2
2379 00:56:53.343493
2380 00:56:53.344009 ==DQ 0 ==
2381 00:56:53.346683 Final DQ duty delay cell = -4
2382 00:56:53.350447 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2383 00:56:53.353385 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2384 00:56:53.356862 [-4] AVG Duty = 4968%(X100)
2385 00:56:53.357470
2386 00:56:53.357838 ==DQ 1 ==
2387 00:56:53.360408 Final DQ duty delay cell = 4
2388 00:56:53.363592 [4] MAX Duty = 5093%(X100), DQS PI = 4
2389 00:56:53.366597 [4] MIN Duty = 5031%(X100), DQS PI = 0
2390 00:56:53.367056 [4] AVG Duty = 5062%(X100)
2391 00:56:53.367411
2392 00:56:53.373651 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2393 00:56:53.374247
2394 00:56:53.376958 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2395 00:56:53.380908 [DutyScan_Calibration_Flow] ====Done====
2396 00:56:53.381459 ==
2397 00:56:53.383710 Dram Type= 6, Freq= 0, CH_1, rank 0
2398 00:56:53.386890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2399 00:56:53.387352 ==
2400 00:56:53.389887 [Duty_Offset_Calibration]
2401 00:56:53.390476 B0:0 B1:-1 CA:2
2402 00:56:53.390832
2403 00:56:53.393560 [DutyScan_Calibration_Flow] k_type=0
2404 00:56:53.403653
2405 00:56:53.404172 ==CLK 0==
2406 00:56:53.407081 Final CLK duty delay cell = 0
2407 00:56:53.410061 [0] MAX Duty = 5156%(X100), DQS PI = 18
2408 00:56:53.413130 [0] MIN Duty = 4938%(X100), DQS PI = 44
2409 00:56:53.413703 [0] AVG Duty = 5047%(X100)
2410 00:56:53.416764
2411 00:56:53.419933 CH1 CLK Duty spec in!! Max-Min= 218%
2412 00:56:53.423621 [DutyScan_Calibration_Flow] ====Done====
2413 00:56:53.424318
2414 00:56:53.426909 [DutyScan_Calibration_Flow] k_type=1
2415 00:56:53.442932
2416 00:56:53.443454 ==DQS 0 ==
2417 00:56:53.446240 Final DQS duty delay cell = 0
2418 00:56:53.449903 [0] MAX Duty = 5093%(X100), DQS PI = 24
2419 00:56:53.453271 [0] MIN Duty = 4969%(X100), DQS PI = 0
2420 00:56:53.453792 [0] AVG Duty = 5031%(X100)
2421 00:56:53.456647
2422 00:56:53.457170 ==DQS 1 ==
2423 00:56:53.459713 Final DQS duty delay cell = 0
2424 00:56:53.463142 [0] MAX Duty = 5156%(X100), DQS PI = 0
2425 00:56:53.466551 [0] MIN Duty = 4813%(X100), DQS PI = 36
2426 00:56:53.467082 [0] AVG Duty = 4984%(X100)
2427 00:56:53.467418
2428 00:56:53.473087 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2429 00:56:53.473611
2430 00:56:53.476579 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2431 00:56:53.479617 [DutyScan_Calibration_Flow] ====Done====
2432 00:56:53.480040
2433 00:56:53.482891 [DutyScan_Calibration_Flow] k_type=3
2434 00:56:53.499489
2435 00:56:53.500055 ==DQM 0 ==
2436 00:56:53.502564 Final DQM duty delay cell = 4
2437 00:56:53.506462 [4] MAX Duty = 5093%(X100), DQS PI = 6
2438 00:56:53.509456 [4] MIN Duty = 4938%(X100), DQS PI = 48
2439 00:56:53.509927 [4] AVG Duty = 5015%(X100)
2440 00:56:53.512998
2441 00:56:53.513510 ==DQM 1 ==
2442 00:56:53.516146 Final DQM duty delay cell = -4
2443 00:56:53.519464 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2444 00:56:53.522611 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2445 00:56:53.526094 [-4] AVG Duty = 4875%(X100)
2446 00:56:53.526600
2447 00:56:53.529478 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2448 00:56:53.529980
2449 00:56:53.533000 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2450 00:56:53.536058 [DutyScan_Calibration_Flow] ====Done====
2451 00:56:53.536547
2452 00:56:53.539226 [DutyScan_Calibration_Flow] k_type=2
2453 00:56:53.555912
2454 00:56:53.556438 ==DQ 0 ==
2455 00:56:53.559288 Final DQ duty delay cell = 0
2456 00:56:53.562677 [0] MAX Duty = 5062%(X100), DQS PI = 20
2457 00:56:53.566364 [0] MIN Duty = 4938%(X100), DQS PI = 0
2458 00:56:53.566931 [0] AVG Duty = 5000%(X100)
2459 00:56:53.567304
2460 00:56:53.570003 ==DQ 1 ==
2461 00:56:53.572724 Final DQ duty delay cell = 0
2462 00:56:53.575973 [0] MAX Duty = 5031%(X100), DQS PI = 2
2463 00:56:53.579465 [0] MIN Duty = 4813%(X100), DQS PI = 34
2464 00:56:53.580035 [0] AVG Duty = 4922%(X100)
2465 00:56:53.580403
2466 00:56:53.583298 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2467 00:56:53.583891
2468 00:56:53.586347 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2469 00:56:53.593363 [DutyScan_Calibration_Flow] ====Done====
2470 00:56:53.596546 nWR fixed to 30
2471 00:56:53.597148 [ModeRegInit_LP4] CH0 RK0
2472 00:56:53.600154 [ModeRegInit_LP4] CH0 RK1
2473 00:56:53.602782 [ModeRegInit_LP4] CH1 RK0
2474 00:56:53.603259 [ModeRegInit_LP4] CH1 RK1
2475 00:56:53.606404 match AC timing 7
2476 00:56:53.609375 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2477 00:56:53.612651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2478 00:56:53.619482 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2479 00:56:53.623380 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2480 00:56:53.629743 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2481 00:56:53.630362 ==
2482 00:56:53.633106 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 00:56:53.636433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 00:56:53.637013 ==
2485 00:56:53.642774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 00:56:53.646621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2487 00:56:53.655962 [CA 0] Center 38 (8~69) winsize 62
2488 00:56:53.659392 [CA 1] Center 38 (8~69) winsize 62
2489 00:56:53.662364 [CA 2] Center 35 (5~66) winsize 62
2490 00:56:53.665937 [CA 3] Center 35 (4~66) winsize 63
2491 00:56:53.668954 [CA 4] Center 34 (4~65) winsize 62
2492 00:56:53.672521 [CA 5] Center 33 (3~64) winsize 62
2493 00:56:53.673100
2494 00:56:53.676188 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2495 00:56:53.676771
2496 00:56:53.679439 [CATrainingPosCal] consider 1 rank data
2497 00:56:53.682532 u2DelayCellTimex100 = 270/100 ps
2498 00:56:53.685831 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2499 00:56:53.689245 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2500 00:56:53.695957 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2501 00:56:53.699454 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2502 00:56:53.702582 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2503 00:56:53.706072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2504 00:56:53.706638
2505 00:56:53.709041 CA PerBit enable=1, Macro0, CA PI delay=33
2506 00:56:53.709515
2507 00:56:53.712422 [CBTSetCACLKResult] CA Dly = 33
2508 00:56:53.712892 CS Dly: 6 (0~37)
2509 00:56:53.713266 ==
2510 00:56:53.716453 Dram Type= 6, Freq= 0, CH_0, rank 1
2511 00:56:53.722393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 00:56:53.722873 ==
2513 00:56:53.726064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 00:56:53.732315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2515 00:56:53.741482 [CA 0] Center 39 (8~70) winsize 63
2516 00:56:53.744819 [CA 1] Center 38 (8~69) winsize 62
2517 00:56:53.748061 [CA 2] Center 35 (5~66) winsize 62
2518 00:56:53.751463 [CA 3] Center 35 (5~66) winsize 62
2519 00:56:53.754761 [CA 4] Center 34 (4~65) winsize 62
2520 00:56:53.757896 [CA 5] Center 34 (4~64) winsize 61
2521 00:56:53.758712
2522 00:56:53.761640 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2523 00:56:53.762425
2524 00:56:53.765016 [CATrainingPosCal] consider 2 rank data
2525 00:56:53.767961 u2DelayCellTimex100 = 270/100 ps
2526 00:56:53.771745 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2527 00:56:53.775129 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2528 00:56:53.781478 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2529 00:56:53.785195 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2530 00:56:53.788394 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2531 00:56:53.791519 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2532 00:56:53.791949
2533 00:56:53.795453 CA PerBit enable=1, Macro0, CA PI delay=34
2534 00:56:53.795984
2535 00:56:53.798406 [CBTSetCACLKResult] CA Dly = 34
2536 00:56:53.798829 CS Dly: 7 (0~39)
2537 00:56:53.799166
2538 00:56:53.801864 ----->DramcWriteLeveling(PI) begin...
2539 00:56:53.802319 ==
2540 00:56:53.804922 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 00:56:53.811849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 00:56:53.812379 ==
2543 00:56:53.815205 Write leveling (Byte 0): 33 => 33
2544 00:56:53.818706 Write leveling (Byte 1): 32 => 32
2545 00:56:53.819127 DramcWriteLeveling(PI) end<-----
2546 00:56:53.819459
2547 00:56:53.821852 ==
2548 00:56:53.825310 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 00:56:53.828882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 00:56:53.829410 ==
2551 00:56:53.832030 [Gating] SW mode calibration
2552 00:56:53.838410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2553 00:56:53.841794 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2554 00:56:53.848441 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2555 00:56:53.852078 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2556 00:56:53.855160 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 00:56:53.862100 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 00:56:53.865170 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 00:56:53.868611 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 00:56:53.875054 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2561 00:56:53.878429 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2562 00:56:53.882140 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2563 00:56:53.888768 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 00:56:53.892221 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 00:56:53.895243 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 00:56:53.898448 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 00:56:53.905559 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 00:56:53.908948 1 0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2569 00:56:53.912038 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2570 00:56:53.918876 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2571 00:56:53.921872 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 00:56:53.925390 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 00:56:53.932217 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 00:56:53.935489 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 00:56:53.938504 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 00:56:53.945437 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2577 00:56:53.948858 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 00:56:53.952113 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2579 00:56:53.959152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 00:56:53.961898 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 00:56:53.965789 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 00:56:53.968711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 00:56:53.975477 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 00:56:53.979255 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 00:56:53.982247 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 00:56:53.988598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 00:56:53.992303 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 00:56:53.995602 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 00:56:54.002291 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 00:56:54.005304 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 00:56:54.009199 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 00:56:54.015291 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 00:56:54.018741 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2594 00:56:54.022227 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2595 00:56:54.029249 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 00:56:54.029855 Total UI for P1: 0, mck2ui 16
2597 00:56:54.035670 best dqsien dly found for B0: ( 1, 3, 30)
2598 00:56:54.036230 Total UI for P1: 0, mck2ui 16
2599 00:56:54.039414 best dqsien dly found for B1: ( 1, 3, 30)
2600 00:56:54.042282 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2601 00:56:54.049370 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2602 00:56:54.049971
2603 00:56:54.052651 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2604 00:56:54.056132 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2605 00:56:54.059115 [Gating] SW calibration Done
2606 00:56:54.059585 ==
2607 00:56:54.062507 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 00:56:54.065607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 00:56:54.066264 ==
2610 00:56:54.066639 RX Vref Scan: 0
2611 00:56:54.069019
2612 00:56:54.069709 RX Vref 0 -> 0, step: 1
2613 00:56:54.070131
2614 00:56:54.072790 RX Delay -40 -> 252, step: 8
2615 00:56:54.075740 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2616 00:56:54.078991 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2617 00:56:54.085714 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2618 00:56:54.088716 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2619 00:56:54.092417 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2620 00:56:54.095316 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2621 00:56:54.099190 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2622 00:56:54.105251 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2623 00:56:54.109043 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2624 00:56:54.112571 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2625 00:56:54.115338 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2626 00:56:54.118604 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2627 00:56:54.125346 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2628 00:56:54.128806 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2629 00:56:54.131909 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2630 00:56:54.135378 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2631 00:56:54.135856 ==
2632 00:56:54.138575 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 00:56:54.145505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 00:56:54.146104 ==
2635 00:56:54.146482 DQS Delay:
2636 00:56:54.148794 DQS0 = 0, DQS1 = 0
2637 00:56:54.149263 DQM Delay:
2638 00:56:54.149631 DQM0 = 122, DQM1 = 110
2639 00:56:54.151981 DQ Delay:
2640 00:56:54.155300 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2641 00:56:54.158600 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2642 00:56:54.161833 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2643 00:56:54.165473 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2644 00:56:54.165994
2645 00:56:54.166332
2646 00:56:54.166683 ==
2647 00:56:54.168954 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 00:56:54.172349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 00:56:54.172873 ==
2650 00:56:54.175421
2651 00:56:54.175837
2652 00:56:54.176167 TX Vref Scan disable
2653 00:56:54.178471 == TX Byte 0 ==
2654 00:56:54.182253 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2655 00:56:54.185435 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2656 00:56:54.188734 == TX Byte 1 ==
2657 00:56:54.192161 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2658 00:56:54.195411 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2659 00:56:54.195850 ==
2660 00:56:54.199001 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 00:56:54.205449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 00:56:54.205976 ==
2663 00:56:54.216084 TX Vref=22, minBit 7, minWin=23, winSum=408
2664 00:56:54.218957 TX Vref=24, minBit 7, minWin=24, winSum=413
2665 00:56:54.222177 TX Vref=26, minBit 0, minWin=25, winSum=420
2666 00:56:54.225852 TX Vref=28, minBit 7, minWin=24, winSum=416
2667 00:56:54.229349 TX Vref=30, minBit 4, minWin=25, winSum=420
2668 00:56:54.232662 TX Vref=32, minBit 1, minWin=25, winSum=415
2669 00:56:54.239425 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
2670 00:56:54.239955
2671 00:56:54.242432 Final TX Range 1 Vref 26
2672 00:56:54.242930
2673 00:56:54.243435 ==
2674 00:56:54.245832 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 00:56:54.249392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 00:56:54.249815 ==
2677 00:56:54.250214
2678 00:56:54.252580
2679 00:56:54.252998 TX Vref Scan disable
2680 00:56:54.255967 == TX Byte 0 ==
2681 00:56:54.259408 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2682 00:56:54.262364 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2683 00:56:54.266090 == TX Byte 1 ==
2684 00:56:54.269152 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2685 00:56:54.272520 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2686 00:56:54.273037
2687 00:56:54.276014 [DATLAT]
2688 00:56:54.276433 Freq=1200, CH0 RK0
2689 00:56:54.276768
2690 00:56:54.279247 DATLAT Default: 0xd
2691 00:56:54.279666 0, 0xFFFF, sum = 0
2692 00:56:54.282516 1, 0xFFFF, sum = 0
2693 00:56:54.282942 2, 0xFFFF, sum = 0
2694 00:56:54.286393 3, 0xFFFF, sum = 0
2695 00:56:54.286925 4, 0xFFFF, sum = 0
2696 00:56:54.289424 5, 0xFFFF, sum = 0
2697 00:56:54.289870 6, 0xFFFF, sum = 0
2698 00:56:54.292705 7, 0xFFFF, sum = 0
2699 00:56:54.293174 8, 0xFFFF, sum = 0
2700 00:56:54.295958 9, 0xFFFF, sum = 0
2701 00:56:54.296390 10, 0xFFFF, sum = 0
2702 00:56:54.299381 11, 0xFFFF, sum = 0
2703 00:56:54.299807 12, 0x0, sum = 1
2704 00:56:54.302795 13, 0x0, sum = 2
2705 00:56:54.303291 14, 0x0, sum = 3
2706 00:56:54.306177 15, 0x0, sum = 4
2707 00:56:54.306708 best_step = 13
2708 00:56:54.307042
2709 00:56:54.307515 ==
2710 00:56:54.309293 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 00:56:54.315788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 00:56:54.316212 ==
2713 00:56:54.316546 RX Vref Scan: 1
2714 00:56:54.316853
2715 00:56:54.319181 Set Vref Range= 32 -> 127
2716 00:56:54.319629
2717 00:56:54.322701 RX Vref 32 -> 127, step: 1
2718 00:56:54.323245
2719 00:56:54.325721 RX Delay -13 -> 252, step: 4
2720 00:56:54.326187
2721 00:56:54.329542 Set Vref, RX VrefLevel [Byte0]: 32
2722 00:56:54.332614 [Byte1]: 32
2723 00:56:54.333112
2724 00:56:54.336088 Set Vref, RX VrefLevel [Byte0]: 33
2725 00:56:54.339103 [Byte1]: 33
2726 00:56:54.339535
2727 00:56:54.342815 Set Vref, RX VrefLevel [Byte0]: 34
2728 00:56:54.346019 [Byte1]: 34
2729 00:56:54.350031
2730 00:56:54.350559 Set Vref, RX VrefLevel [Byte0]: 35
2731 00:56:54.356294 [Byte1]: 35
2732 00:56:54.356838
2733 00:56:54.359738 Set Vref, RX VrefLevel [Byte0]: 36
2734 00:56:54.362872 [Byte1]: 36
2735 00:56:54.363411
2736 00:56:54.366180 Set Vref, RX VrefLevel [Byte0]: 37
2737 00:56:54.369552 [Byte1]: 37
2738 00:56:54.373474
2739 00:56:54.374044 Set Vref, RX VrefLevel [Byte0]: 38
2740 00:56:54.376641 [Byte1]: 38
2741 00:56:54.381862
2742 00:56:54.382477 Set Vref, RX VrefLevel [Byte0]: 39
2743 00:56:54.385102 [Byte1]: 39
2744 00:56:54.389305
2745 00:56:54.389845 Set Vref, RX VrefLevel [Byte0]: 40
2746 00:56:54.392761 [Byte1]: 40
2747 00:56:54.397353
2748 00:56:54.397883 Set Vref, RX VrefLevel [Byte0]: 41
2749 00:56:54.400573 [Byte1]: 41
2750 00:56:54.405134
2751 00:56:54.405703 Set Vref, RX VrefLevel [Byte0]: 42
2752 00:56:54.408302 [Byte1]: 42
2753 00:56:54.412944
2754 00:56:54.413406 Set Vref, RX VrefLevel [Byte0]: 43
2755 00:56:54.416188 [Byte1]: 43
2756 00:56:54.420849
2757 00:56:54.421375 Set Vref, RX VrefLevel [Byte0]: 44
2758 00:56:54.424368 [Byte1]: 44
2759 00:56:54.428627
2760 00:56:54.429189 Set Vref, RX VrefLevel [Byte0]: 45
2761 00:56:54.431886 [Byte1]: 45
2762 00:56:54.436626
2763 00:56:54.437192 Set Vref, RX VrefLevel [Byte0]: 46
2764 00:56:54.439682 [Byte1]: 46
2765 00:56:54.444843
2766 00:56:54.445553 Set Vref, RX VrefLevel [Byte0]: 47
2767 00:56:54.448201 [Byte1]: 47
2768 00:56:54.452348
2769 00:56:54.452815 Set Vref, RX VrefLevel [Byte0]: 48
2770 00:56:54.455375 [Byte1]: 48
2771 00:56:54.460591
2772 00:56:54.461229 Set Vref, RX VrefLevel [Byte0]: 49
2773 00:56:54.463889 [Byte1]: 49
2774 00:56:54.468448
2775 00:56:54.469159 Set Vref, RX VrefLevel [Byte0]: 50
2776 00:56:54.471922 [Byte1]: 50
2777 00:56:54.476170
2778 00:56:54.476637 Set Vref, RX VrefLevel [Byte0]: 51
2779 00:56:54.479345 [Byte1]: 51
2780 00:56:54.484089
2781 00:56:54.484694 Set Vref, RX VrefLevel [Byte0]: 52
2782 00:56:54.486938 [Byte1]: 52
2783 00:56:54.491894
2784 00:56:54.492589 Set Vref, RX VrefLevel [Byte0]: 53
2785 00:56:54.495205 [Byte1]: 53
2786 00:56:54.499926
2787 00:56:54.500491 Set Vref, RX VrefLevel [Byte0]: 54
2788 00:56:54.502716 [Byte1]: 54
2789 00:56:54.507521
2790 00:56:54.508127 Set Vref, RX VrefLevel [Byte0]: 55
2791 00:56:54.510806 [Byte1]: 55
2792 00:56:54.515361
2793 00:56:54.515863 Set Vref, RX VrefLevel [Byte0]: 56
2794 00:56:54.518622 [Byte1]: 56
2795 00:56:54.523704
2796 00:56:54.524195 Set Vref, RX VrefLevel [Byte0]: 57
2797 00:56:54.526542 [Byte1]: 57
2798 00:56:54.531392
2799 00:56:54.531869 Set Vref, RX VrefLevel [Byte0]: 58
2800 00:56:54.534638 [Byte1]: 58
2801 00:56:54.539127
2802 00:56:54.539545 Set Vref, RX VrefLevel [Byte0]: 59
2803 00:56:54.542101 [Byte1]: 59
2804 00:56:54.547009
2805 00:56:54.547521 Set Vref, RX VrefLevel [Byte0]: 60
2806 00:56:54.550280 [Byte1]: 60
2807 00:56:54.555280
2808 00:56:54.555783 Set Vref, RX VrefLevel [Byte0]: 61
2809 00:56:54.558055 [Byte1]: 61
2810 00:56:54.562661
2811 00:56:54.563082 Set Vref, RX VrefLevel [Byte0]: 62
2812 00:56:54.565995 [Byte1]: 62
2813 00:56:54.570729
2814 00:56:54.571239 Set Vref, RX VrefLevel [Byte0]: 63
2815 00:56:54.574010 [Byte1]: 63
2816 00:56:54.578887
2817 00:56:54.579452 Set Vref, RX VrefLevel [Byte0]: 64
2818 00:56:54.581870 [Byte1]: 64
2819 00:56:54.586322
2820 00:56:54.586882 Set Vref, RX VrefLevel [Byte0]: 65
2821 00:56:54.589980 [Byte1]: 65
2822 00:56:54.594644
2823 00:56:54.595221 Set Vref, RX VrefLevel [Byte0]: 66
2824 00:56:54.597510 [Byte1]: 66
2825 00:56:54.602546
2826 00:56:54.603100 Set Vref, RX VrefLevel [Byte0]: 67
2827 00:56:54.605523 [Byte1]: 67
2828 00:56:54.610223
2829 00:56:54.610798 Set Vref, RX VrefLevel [Byte0]: 68
2830 00:56:54.613479 [Byte1]: 68
2831 00:56:54.617791
2832 00:56:54.618313 Set Vref, RX VrefLevel [Byte0]: 69
2833 00:56:54.621104 [Byte1]: 69
2834 00:56:54.625664
2835 00:56:54.626182 Final RX Vref Byte 0 = 61 to rank0
2836 00:56:54.629517 Final RX Vref Byte 1 = 50 to rank0
2837 00:56:54.632806 Final RX Vref Byte 0 = 61 to rank1
2838 00:56:54.635874 Final RX Vref Byte 1 = 50 to rank1==
2839 00:56:54.639324 Dram Type= 6, Freq= 0, CH_0, rank 0
2840 00:56:54.646123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 00:56:54.646709 ==
2842 00:56:54.647200 DQS Delay:
2843 00:56:54.647650 DQS0 = 0, DQS1 = 0
2844 00:56:54.649702 DQM Delay:
2845 00:56:54.650349 DQM0 = 122, DQM1 = 109
2846 00:56:54.652942 DQ Delay:
2847 00:56:54.656412 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2848 00:56:54.659469 DQ4 =126, DQ5 =116, DQ6 =128, DQ7 =128
2849 00:56:54.662887 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2850 00:56:54.666552 DQ12 =116, DQ13 =112, DQ14 =122, DQ15 =116
2851 00:56:54.667135
2852 00:56:54.667510
2853 00:56:54.673142 [DQSOSCAuto] RK0, (LSB)MR18= 0x704, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 407 ps
2854 00:56:54.676486 CH0 RK0: MR19=404, MR18=704
2855 00:56:54.683336 CH0_RK0: MR19=0x404, MR18=0x704, DQSOSC=407, MR23=63, INC=39, DEC=26
2856 00:56:54.683919
2857 00:56:54.686159 ----->DramcWriteLeveling(PI) begin...
2858 00:56:54.686653 ==
2859 00:56:54.689709 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 00:56:54.692674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 00:56:54.693264 ==
2862 00:56:54.696417 Write leveling (Byte 0): 36 => 36
2863 00:56:54.699265 Write leveling (Byte 1): 30 => 30
2864 00:56:54.702743 DramcWriteLeveling(PI) end<-----
2865 00:56:54.703218
2866 00:56:54.703592 ==
2867 00:56:54.706108 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 00:56:54.709408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 00:56:54.712615 ==
2870 00:56:54.713092 [Gating] SW mode calibration
2871 00:56:54.719612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2872 00:56:54.726118 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2873 00:56:54.729547 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2874 00:56:54.736013 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 00:56:54.739735 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 00:56:54.742596 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 00:56:54.749420 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 00:56:54.753011 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 00:56:54.756057 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 00:56:54.762615 0 15 28 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
2881 00:56:54.766188 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 00:56:54.769449 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 00:56:54.776218 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 00:56:54.779289 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 00:56:54.782863 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 00:56:54.786316 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 00:56:54.792524 1 0 24 | B1->B0 | 2727 2b2b | 1 0 | (1 1) (1 1)
2888 00:56:54.796462 1 0 28 | B1->B0 | 3d3d 4444 | 1 0 | (0 0) (0 0)
2889 00:56:54.799407 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 00:56:54.805779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 00:56:54.809491 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 00:56:54.812528 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 00:56:54.819625 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 00:56:54.822861 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 00:56:54.826296 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 00:56:54.832627 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2897 00:56:54.836037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2898 00:56:54.839491 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 00:56:54.846188 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 00:56:54.849491 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 00:56:54.852671 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 00:56:54.860055 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 00:56:54.862645 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 00:56:54.866281 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 00:56:54.873305 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 00:56:54.876218 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 00:56:54.879631 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 00:56:54.882786 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 00:56:54.889542 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 00:56:54.892589 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 00:56:54.896132 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2912 00:56:54.902706 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2913 00:56:54.905913 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 00:56:54.909099 Total UI for P1: 0, mck2ui 16
2915 00:56:54.912879 best dqsien dly found for B0: ( 1, 3, 26)
2916 00:56:54.915972 Total UI for P1: 0, mck2ui 16
2917 00:56:54.919461 best dqsien dly found for B1: ( 1, 3, 28)
2918 00:56:54.922696 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2919 00:56:54.925934 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2920 00:56:54.926416
2921 00:56:54.929402 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2922 00:56:54.932906 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2923 00:56:54.936141 [Gating] SW calibration Done
2924 00:56:54.936614 ==
2925 00:56:54.939960 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 00:56:54.942735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 00:56:54.946196 ==
2928 00:56:54.946628 RX Vref Scan: 0
2929 00:56:54.947045
2930 00:56:54.949402 RX Vref 0 -> 0, step: 1
2931 00:56:54.949867
2932 00:56:54.950436 RX Delay -40 -> 252, step: 8
2933 00:56:54.956294 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2934 00:56:54.959627 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2935 00:56:54.963054 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2936 00:56:54.966678 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2937 00:56:54.969665 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2938 00:56:54.976438 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2939 00:56:54.979506 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2940 00:56:54.983556 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2941 00:56:54.986556 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2942 00:56:54.989612 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2943 00:56:54.996341 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2944 00:56:54.999927 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2945 00:56:55.003248 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2946 00:56:55.006534 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2947 00:56:55.009817 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2948 00:56:55.016733 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2949 00:56:55.017234 ==
2950 00:56:55.019999 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 00:56:55.023794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 00:56:55.024352 ==
2953 00:56:55.024699 DQS Delay:
2954 00:56:55.026617 DQS0 = 0, DQS1 = 0
2955 00:56:55.027040 DQM Delay:
2956 00:56:55.029994 DQM0 = 120, DQM1 = 108
2957 00:56:55.030417 DQ Delay:
2958 00:56:55.033267 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2959 00:56:55.036497 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2960 00:56:55.040231 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2961 00:56:55.043368 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2962 00:56:55.043804
2963 00:56:55.044227
2964 00:56:55.044552 ==
2965 00:56:55.046501 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 00:56:55.053177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 00:56:55.053613 ==
2968 00:56:55.053979
2969 00:56:55.054306
2970 00:56:55.054608 TX Vref Scan disable
2971 00:56:55.057341 == TX Byte 0 ==
2972 00:56:55.060378 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2973 00:56:55.063507 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2974 00:56:55.067116 == TX Byte 1 ==
2975 00:56:55.070406 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2976 00:56:55.073742 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2977 00:56:55.076855 ==
2978 00:56:55.080191 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 00:56:55.083444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 00:56:55.084010 ==
2981 00:56:55.095221 TX Vref=22, minBit 3, minWin=24, winSum=418
2982 00:56:55.098522 TX Vref=24, minBit 0, minWin=25, winSum=424
2983 00:56:55.101765 TX Vref=26, minBit 2, minWin=25, winSum=424
2984 00:56:55.105551 TX Vref=28, minBit 0, minWin=26, winSum=431
2985 00:56:55.108745 TX Vref=30, minBit 0, minWin=26, winSum=430
2986 00:56:55.112038 TX Vref=32, minBit 5, minWin=25, winSum=433
2987 00:56:55.118614 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
2988 00:56:55.119197
2989 00:56:55.122211 Final TX Range 1 Vref 28
2990 00:56:55.122758
2991 00:56:55.123284 ==
2992 00:56:55.125397 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 00:56:55.128886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 00:56:55.129360 ==
2995 00:56:55.129731
2996 00:56:55.131804
2997 00:56:55.132275 TX Vref Scan disable
2998 00:56:55.135175 == TX Byte 0 ==
2999 00:56:55.138761 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3000 00:56:55.141903 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3001 00:56:55.145136 == TX Byte 1 ==
3002 00:56:55.148359 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3003 00:56:55.151701 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3004 00:56:55.152148
3005 00:56:55.155405 [DATLAT]
3006 00:56:55.155935 Freq=1200, CH0 RK1
3007 00:56:55.156420
3008 00:56:55.158652 DATLAT Default: 0xd
3009 00:56:55.159077 0, 0xFFFF, sum = 0
3010 00:56:55.161826 1, 0xFFFF, sum = 0
3011 00:56:55.162298 2, 0xFFFF, sum = 0
3012 00:56:55.165217 3, 0xFFFF, sum = 0
3013 00:56:55.165649 4, 0xFFFF, sum = 0
3014 00:56:55.168600 5, 0xFFFF, sum = 0
3015 00:56:55.169050 6, 0xFFFF, sum = 0
3016 00:56:55.172066 7, 0xFFFF, sum = 0
3017 00:56:55.172522 8, 0xFFFF, sum = 0
3018 00:56:55.175724 9, 0xFFFF, sum = 0
3019 00:56:55.178933 10, 0xFFFF, sum = 0
3020 00:56:55.179485 11, 0xFFFF, sum = 0
3021 00:56:55.179888 12, 0x0, sum = 1
3022 00:56:55.182230 13, 0x0, sum = 2
3023 00:56:55.182664 14, 0x0, sum = 3
3024 00:56:55.185696 15, 0x0, sum = 4
3025 00:56:55.186302 best_step = 13
3026 00:56:55.186743
3027 00:56:55.187091 ==
3028 00:56:55.189002 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 00:56:55.195995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 00:56:55.196541 ==
3031 00:56:55.196988 RX Vref Scan: 0
3032 00:56:55.197329
3033 00:56:55.198917 RX Vref 0 -> 0, step: 1
3034 00:56:55.199346
3035 00:56:55.202253 RX Delay -21 -> 252, step: 4
3036 00:56:55.205808 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3037 00:56:55.208999 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3038 00:56:55.215281 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3039 00:56:55.218734 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3040 00:56:55.221933 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3041 00:56:55.225501 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3042 00:56:55.228807 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3043 00:56:55.235412 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3044 00:56:55.238884 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3045 00:56:55.242351 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3046 00:56:55.245638 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3047 00:56:55.249173 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3048 00:56:55.256002 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3049 00:56:55.259398 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3050 00:56:55.262119 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3051 00:56:55.265381 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3052 00:56:55.265858 ==
3053 00:56:55.268905 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 00:56:55.272486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 00:56:55.275304 ==
3056 00:56:55.275785 DQS Delay:
3057 00:56:55.276160 DQS0 = 0, DQS1 = 0
3058 00:56:55.278599 DQM Delay:
3059 00:56:55.279077 DQM0 = 119, DQM1 = 107
3060 00:56:55.282031 DQ Delay:
3061 00:56:55.285368 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =112
3062 00:56:55.288580 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3063 00:56:55.292189 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3064 00:56:55.295516 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3065 00:56:55.295998
3066 00:56:55.296375
3067 00:56:55.302138 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3068 00:56:55.305189 CH0 RK1: MR19=403, MR18=DF4
3069 00:56:55.312292 CH0_RK1: MR19=0x403, MR18=0xDF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3070 00:56:55.315354 [RxdqsGatingPostProcess] freq 1200
3071 00:56:55.322113 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3072 00:56:55.322666 best DQS0 dly(2T, 0.5T) = (0, 11)
3073 00:56:55.325190 best DQS1 dly(2T, 0.5T) = (0, 11)
3074 00:56:55.328625 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3075 00:56:55.332529 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3076 00:56:55.335770 best DQS0 dly(2T, 0.5T) = (0, 11)
3077 00:56:55.338568 best DQS1 dly(2T, 0.5T) = (0, 11)
3078 00:56:55.342097 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3079 00:56:55.345679 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3080 00:56:55.348794 Pre-setting of DQS Precalculation
3081 00:56:55.351959 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3082 00:56:55.355062 ==
3083 00:56:55.358658 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 00:56:55.362274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 00:56:55.362893 ==
3086 00:56:55.365588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 00:56:55.371761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
3088 00:56:55.381193 [CA 0] Center 38 (8~68) winsize 61
3089 00:56:55.384386 [CA 1] Center 37 (7~68) winsize 62
3090 00:56:55.388248 [CA 2] Center 35 (5~65) winsize 61
3091 00:56:55.390954 [CA 3] Center 34 (4~65) winsize 62
3092 00:56:55.394497 [CA 4] Center 34 (4~65) winsize 62
3093 00:56:55.397696 [CA 5] Center 33 (3~64) winsize 62
3094 00:56:55.398154
3095 00:56:55.401405 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3096 00:56:55.401838
3097 00:56:55.404457 [CATrainingPosCal] consider 1 rank data
3098 00:56:55.407734 u2DelayCellTimex100 = 270/100 ps
3099 00:56:55.411084 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3100 00:56:55.414835 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 00:56:55.421255 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3102 00:56:55.424618 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3103 00:56:55.428204 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3104 00:56:55.431063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3105 00:56:55.431539
3106 00:56:55.434522 CA PerBit enable=1, Macro0, CA PI delay=33
3107 00:56:55.435046
3108 00:56:55.437775 [CBTSetCACLKResult] CA Dly = 33
3109 00:56:55.438318 CS Dly: 5 (0~36)
3110 00:56:55.438819 ==
3111 00:56:55.441037 Dram Type= 6, Freq= 0, CH_1, rank 1
3112 00:56:55.447746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 00:56:55.448188 ==
3114 00:56:55.451212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 00:56:55.457623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3116 00:56:55.466766 [CA 0] Center 38 (8~68) winsize 61
3117 00:56:55.470007 [CA 1] Center 38 (7~69) winsize 63
3118 00:56:55.473498 [CA 2] Center 35 (5~66) winsize 62
3119 00:56:55.476791 [CA 3] Center 35 (5~65) winsize 61
3120 00:56:55.480069 [CA 4] Center 35 (5~65) winsize 61
3121 00:56:55.483614 [CA 5] Center 34 (4~64) winsize 61
3122 00:56:55.484037
3123 00:56:55.486721 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3124 00:56:55.487142
3125 00:56:55.490654 [CATrainingPosCal] consider 2 rank data
3126 00:56:55.493557 u2DelayCellTimex100 = 270/100 ps
3127 00:56:55.496766 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3128 00:56:55.500399 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3129 00:56:55.505535 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3130 00:56:55.510697 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3131 00:56:55.513349 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3132 00:56:55.517090 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3133 00:56:55.517519
3134 00:56:55.520110 CA PerBit enable=1, Macro0, CA PI delay=34
3135 00:56:55.520565
3136 00:56:55.523582 [CBTSetCACLKResult] CA Dly = 34
3137 00:56:55.524010 CS Dly: 6 (0~39)
3138 00:56:55.524536
3139 00:56:55.526822 ----->DramcWriteLeveling(PI) begin...
3140 00:56:55.527351 ==
3141 00:56:55.530386 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 00:56:55.536933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 00:56:55.537371 ==
3144 00:56:55.540511 Write leveling (Byte 0): 25 => 25
3145 00:56:55.543893 Write leveling (Byte 1): 28 => 28
3146 00:56:55.544325 DramcWriteLeveling(PI) end<-----
3147 00:56:55.544668
3148 00:56:55.547338 ==
3149 00:56:55.550814 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 00:56:55.553751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 00:56:55.554285 ==
3152 00:56:55.557521 [Gating] SW mode calibration
3153 00:56:55.563947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3154 00:56:55.567062 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3155 00:56:55.574250 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3156 00:56:55.576847 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 00:56:55.580403 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 00:56:55.587050 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 00:56:55.590634 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 00:56:55.593928 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3161 00:56:55.600584 0 15 24 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (1 0)
3162 00:56:55.603776 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3163 00:56:55.607391 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3164 00:56:55.613591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 00:56:55.617133 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 00:56:55.620675 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 00:56:55.624079 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 00:56:55.630456 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 00:56:55.633671 1 0 24 | B1->B0 | 3939 4646 | 1 0 | (1 1) (0 0)
3170 00:56:55.637214 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 00:56:55.643728 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 00:56:55.647488 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 00:56:55.650790 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 00:56:55.657213 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 00:56:55.660838 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 00:56:55.664203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3177 00:56:55.671120 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3178 00:56:55.674197 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3179 00:56:55.677855 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 00:56:55.684533 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 00:56:55.687739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 00:56:55.690781 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 00:56:55.694300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 00:56:55.700809 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 00:56:55.704093 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 00:56:55.707422 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 00:56:55.714024 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 00:56:55.717626 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 00:56:55.721172 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 00:56:55.727644 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 00:56:55.731139 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 00:56:55.734471 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3193 00:56:55.740819 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3194 00:56:55.741251 Total UI for P1: 0, mck2ui 16
3195 00:56:55.747796 best dqsien dly found for B0: ( 1, 3, 20)
3196 00:56:55.751165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3197 00:56:55.754258 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 00:56:55.758067 Total UI for P1: 0, mck2ui 16
3199 00:56:55.760937 best dqsien dly found for B1: ( 1, 3, 26)
3200 00:56:55.764423 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3201 00:56:55.767923 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3202 00:56:55.768357
3203 00:56:55.770965 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3204 00:56:55.778040 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3205 00:56:55.778530 [Gating] SW calibration Done
3206 00:56:55.778868 ==
3207 00:56:55.781071 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 00:56:55.788177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 00:56:55.788607 ==
3210 00:56:55.788944 RX Vref Scan: 0
3211 00:56:55.789261
3212 00:56:55.791073 RX Vref 0 -> 0, step: 1
3213 00:56:55.791516
3214 00:56:55.794542 RX Delay -40 -> 252, step: 8
3215 00:56:55.797871 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3216 00:56:55.801147 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3217 00:56:55.804665 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3218 00:56:55.808403 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3219 00:56:55.814366 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3220 00:56:55.817992 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3221 00:56:55.821221 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3222 00:56:55.824779 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3223 00:56:55.827969 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3224 00:56:55.831374 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3225 00:56:55.838203 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3226 00:56:55.841614 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3227 00:56:55.844741 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3228 00:56:55.848594 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3229 00:56:55.855156 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3230 00:56:55.858072 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3231 00:56:55.858588 ==
3232 00:56:55.861678 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 00:56:55.865234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 00:56:55.865702 ==
3235 00:56:55.866104 DQS Delay:
3236 00:56:55.868394 DQS0 = 0, DQS1 = 0
3237 00:56:55.868981 DQM Delay:
3238 00:56:55.871900 DQM0 = 119, DQM1 = 112
3239 00:56:55.872431 DQ Delay:
3240 00:56:55.874889 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3241 00:56:55.878527 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3242 00:56:55.881856 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3243 00:56:55.885109 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3244 00:56:55.885695
3245 00:56:55.888180
3246 00:56:55.888644 ==
3247 00:56:55.891442 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 00:56:55.895166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 00:56:55.895707 ==
3250 00:56:55.896145
3251 00:56:55.896507
3252 00:56:55.898226 TX Vref Scan disable
3253 00:56:55.898848 == TX Byte 0 ==
3254 00:56:55.901736 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3255 00:56:55.908472 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3256 00:56:55.909068 == TX Byte 1 ==
3257 00:56:55.911831 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3258 00:56:55.918634 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3259 00:56:55.919228 ==
3260 00:56:55.922287 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 00:56:55.925116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 00:56:55.925591 ==
3263 00:56:55.937028 TX Vref=22, minBit 10, minWin=24, winSum=405
3264 00:56:55.940277 TX Vref=24, minBit 3, minWin=25, winSum=411
3265 00:56:55.943566 TX Vref=26, minBit 8, minWin=25, winSum=419
3266 00:56:55.946970 TX Vref=28, minBit 8, minWin=25, winSum=422
3267 00:56:55.950503 TX Vref=30, minBit 10, minWin=25, winSum=423
3268 00:56:55.956698 TX Vref=32, minBit 1, minWin=26, winSum=423
3269 00:56:55.960034 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 32
3270 00:56:55.960635
3271 00:56:55.963823 Final TX Range 1 Vref 32
3272 00:56:55.964499
3273 00:56:55.965106 ==
3274 00:56:55.966850 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 00:56:55.970703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 00:56:55.971129 ==
3277 00:56:55.971468
3278 00:56:55.973609
3279 00:56:55.974069 TX Vref Scan disable
3280 00:56:55.977746 == TX Byte 0 ==
3281 00:56:55.980683 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3282 00:56:55.983466 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3283 00:56:55.986994 == TX Byte 1 ==
3284 00:56:55.990110 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3285 00:56:55.993664 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3286 00:56:55.994430
3287 00:56:55.996911 [DATLAT]
3288 00:56:55.997546 Freq=1200, CH1 RK0
3289 00:56:55.998030
3290 00:56:56.000345 DATLAT Default: 0xd
3291 00:56:56.000986 0, 0xFFFF, sum = 0
3292 00:56:56.003772 1, 0xFFFF, sum = 0
3293 00:56:56.004372 2, 0xFFFF, sum = 0
3294 00:56:56.007102 3, 0xFFFF, sum = 0
3295 00:56:56.007751 4, 0xFFFF, sum = 0
3296 00:56:56.010505 5, 0xFFFF, sum = 0
3297 00:56:56.010989 6, 0xFFFF, sum = 0
3298 00:56:56.014145 7, 0xFFFF, sum = 0
3299 00:56:56.014867 8, 0xFFFF, sum = 0
3300 00:56:56.017041 9, 0xFFFF, sum = 0
3301 00:56:56.020606 10, 0xFFFF, sum = 0
3302 00:56:56.021092 11, 0xFFFF, sum = 0
3303 00:56:56.023878 12, 0x0, sum = 1
3304 00:56:56.024481 13, 0x0, sum = 2
3305 00:56:56.024938 14, 0x0, sum = 3
3306 00:56:56.027138 15, 0x0, sum = 4
3307 00:56:56.027620 best_step = 13
3308 00:56:56.027989
3309 00:56:56.028328 ==
3310 00:56:56.030367 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 00:56:56.037173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 00:56:56.037615 ==
3313 00:56:56.037982 RX Vref Scan: 1
3314 00:56:56.038307
3315 00:56:56.040333 Set Vref Range= 32 -> 127
3316 00:56:56.040748
3317 00:56:56.043789 RX Vref 32 -> 127, step: 1
3318 00:56:56.044206
3319 00:56:56.047102 RX Delay -13 -> 252, step: 4
3320 00:56:56.047521
3321 00:56:56.050605 Set Vref, RX VrefLevel [Byte0]: 32
3322 00:56:56.051023 [Byte1]: 32
3323 00:56:56.055257
3324 00:56:56.055738 Set Vref, RX VrefLevel [Byte0]: 33
3325 00:56:56.058657 [Byte1]: 33
3326 00:56:56.063065
3327 00:56:56.063622 Set Vref, RX VrefLevel [Byte0]: 34
3328 00:56:56.066168 [Byte1]: 34
3329 00:56:56.070886
3330 00:56:56.071403 Set Vref, RX VrefLevel [Byte0]: 35
3331 00:56:56.073901 [Byte1]: 35
3332 00:56:56.078654
3333 00:56:56.079289 Set Vref, RX VrefLevel [Byte0]: 36
3334 00:56:56.082065 [Byte1]: 36
3335 00:56:56.086994
3336 00:56:56.087538 Set Vref, RX VrefLevel [Byte0]: 37
3337 00:56:56.090024 [Byte1]: 37
3338 00:56:56.094396
3339 00:56:56.094910 Set Vref, RX VrefLevel [Byte0]: 38
3340 00:56:56.097964 [Byte1]: 38
3341 00:56:56.102416
3342 00:56:56.102845 Set Vref, RX VrefLevel [Byte0]: 39
3343 00:56:56.105613 [Byte1]: 39
3344 00:56:56.110294
3345 00:56:56.110815 Set Vref, RX VrefLevel [Byte0]: 40
3346 00:56:56.113295 [Byte1]: 40
3347 00:56:56.118021
3348 00:56:56.118395 Set Vref, RX VrefLevel [Byte0]: 41
3349 00:56:56.121783 [Byte1]: 41
3350 00:56:56.126487
3351 00:56:56.126894 Set Vref, RX VrefLevel [Byte0]: 42
3352 00:56:56.129701 [Byte1]: 42
3353 00:56:56.134054
3354 00:56:56.134517 Set Vref, RX VrefLevel [Byte0]: 43
3355 00:56:56.137312 [Byte1]: 43
3356 00:56:56.141890
3357 00:56:56.142456 Set Vref, RX VrefLevel [Byte0]: 44
3358 00:56:56.145106 [Byte1]: 44
3359 00:56:56.149782
3360 00:56:56.150336 Set Vref, RX VrefLevel [Byte0]: 45
3361 00:56:56.152993 [Byte1]: 45
3362 00:56:56.157796
3363 00:56:56.158328 Set Vref, RX VrefLevel [Byte0]: 46
3364 00:56:56.161069 [Byte1]: 46
3365 00:56:56.165994
3366 00:56:56.166535 Set Vref, RX VrefLevel [Byte0]: 47
3367 00:56:56.169271 [Byte1]: 47
3368 00:56:56.173457
3369 00:56:56.174101 Set Vref, RX VrefLevel [Byte0]: 48
3370 00:56:56.177078 [Byte1]: 48
3371 00:56:56.181121
3372 00:56:56.181605 Set Vref, RX VrefLevel [Byte0]: 49
3373 00:56:56.184775 [Byte1]: 49
3374 00:56:56.189337
3375 00:56:56.189772 Set Vref, RX VrefLevel [Byte0]: 50
3376 00:56:56.192984 [Byte1]: 50
3377 00:56:56.197333
3378 00:56:56.197773 Set Vref, RX VrefLevel [Byte0]: 51
3379 00:56:56.200532 [Byte1]: 51
3380 00:56:56.205115
3381 00:56:56.205570 Set Vref, RX VrefLevel [Byte0]: 52
3382 00:56:56.208229 [Byte1]: 52
3383 00:56:56.212804
3384 00:56:56.213110 Set Vref, RX VrefLevel [Byte0]: 53
3385 00:56:56.216078 [Byte1]: 53
3386 00:56:56.220695
3387 00:56:56.221003 Set Vref, RX VrefLevel [Byte0]: 54
3388 00:56:56.224432 [Byte1]: 54
3389 00:56:56.228600
3390 00:56:56.228973 Set Vref, RX VrefLevel [Byte0]: 55
3391 00:56:56.231760 [Byte1]: 55
3392 00:56:56.236387
3393 00:56:56.236691 Set Vref, RX VrefLevel [Byte0]: 56
3394 00:56:56.239766 [Byte1]: 56
3395 00:56:56.244602
3396 00:56:56.244907 Set Vref, RX VrefLevel [Byte0]: 57
3397 00:56:56.247788 [Byte1]: 57
3398 00:56:56.252373
3399 00:56:56.252679 Set Vref, RX VrefLevel [Byte0]: 58
3400 00:56:56.255633 [Byte1]: 58
3401 00:56:56.260151
3402 00:56:56.260458 Set Vref, RX VrefLevel [Byte0]: 59
3403 00:56:56.263266 [Byte1]: 59
3404 00:56:56.268125
3405 00:56:56.268532 Set Vref, RX VrefLevel [Byte0]: 60
3406 00:56:56.271174 [Byte1]: 60
3407 00:56:56.275774
3408 00:56:56.276206 Set Vref, RX VrefLevel [Byte0]: 61
3409 00:56:56.279561 [Byte1]: 61
3410 00:56:56.284136
3411 00:56:56.284558 Set Vref, RX VrefLevel [Byte0]: 62
3412 00:56:56.287134 [Byte1]: 62
3413 00:56:56.291388
3414 00:56:56.291472 Set Vref, RX VrefLevel [Byte0]: 63
3415 00:56:56.294950 [Byte1]: 63
3416 00:56:56.299646
3417 00:56:56.299730 Set Vref, RX VrefLevel [Byte0]: 64
3418 00:56:56.302550 [Byte1]: 64
3419 00:56:56.307446
3420 00:56:56.307559 Set Vref, RX VrefLevel [Byte0]: 65
3421 00:56:56.310358 [Byte1]: 65
3422 00:56:56.315090
3423 00:56:56.315208 Set Vref, RX VrefLevel [Byte0]: 66
3424 00:56:56.318287 [Byte1]: 66
3425 00:56:56.323022
3426 00:56:56.323124 Set Vref, RX VrefLevel [Byte0]: 67
3427 00:56:56.326461 [Byte1]: 67
3428 00:56:56.330847
3429 00:56:56.330955 Set Vref, RX VrefLevel [Byte0]: 68
3430 00:56:56.334203 [Byte1]: 68
3431 00:56:56.338819
3432 00:56:56.338902 Set Vref, RX VrefLevel [Byte0]: 69
3433 00:56:56.342161 [Byte1]: 69
3434 00:56:56.346954
3435 00:56:56.347124 Final RX Vref Byte 0 = 51 to rank0
3436 00:56:56.350087 Final RX Vref Byte 1 = 51 to rank0
3437 00:56:56.353541 Final RX Vref Byte 0 = 51 to rank1
3438 00:56:56.356974 Final RX Vref Byte 1 = 51 to rank1==
3439 00:56:56.360350 Dram Type= 6, Freq= 0, CH_1, rank 0
3440 00:56:56.366985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 00:56:56.367165 ==
3442 00:56:56.367309 DQS Delay:
3443 00:56:56.367417 DQS0 = 0, DQS1 = 0
3444 00:56:56.370527 DQM Delay:
3445 00:56:56.370749 DQM0 = 119, DQM1 = 112
3446 00:56:56.373856 DQ Delay:
3447 00:56:56.377375 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3448 00:56:56.380484 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3449 00:56:56.383724 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3450 00:56:56.387333 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =116
3451 00:56:56.387672
3452 00:56:56.387877
3453 00:56:56.393585 [DQSOSCAuto] RK0, (LSB)MR18= 0x619, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3454 00:56:56.397108 CH1 RK0: MR19=404, MR18=619
3455 00:56:56.403839 CH1_RK0: MR19=0x404, MR18=0x619, DQSOSC=400, MR23=63, INC=40, DEC=27
3456 00:56:56.404428
3457 00:56:56.407267 ----->DramcWriteLeveling(PI) begin...
3458 00:56:56.407748 ==
3459 00:56:56.410544 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 00:56:56.414077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 00:56:56.414640 ==
3462 00:56:56.417177 Write leveling (Byte 0): 26 => 26
3463 00:56:56.420343 Write leveling (Byte 1): 29 => 29
3464 00:56:56.424274 DramcWriteLeveling(PI) end<-----
3465 00:56:56.424846
3466 00:56:56.425224 ==
3467 00:56:56.427250 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 00:56:56.433986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 00:56:56.434470 ==
3470 00:56:56.434843 [Gating] SW mode calibration
3471 00:56:56.444074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3472 00:56:56.447381 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3473 00:56:56.450596 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 00:56:56.457325 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 00:56:56.460618 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 00:56:56.463736 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 00:56:56.470583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 00:56:56.473981 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 00:56:56.477679 0 15 24 | B1->B0 | 2828 3333 | 1 1 | (1 0) (1 0)
3480 00:56:56.484146 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
3481 00:56:56.487565 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 00:56:56.490762 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 00:56:56.497008 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 00:56:56.500927 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 00:56:56.504128 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 00:56:56.510529 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 00:56:56.513888 1 0 24 | B1->B0 | 3e3e 2c2b | 1 1 | (0 0) (0 0)
3488 00:56:56.517316 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3489 00:56:56.523964 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:56:56.526896 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 00:56:56.530350 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 00:56:56.533917 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 00:56:56.540569 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 00:56:56.543777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 00:56:56.547227 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3496 00:56:56.554097 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 00:56:56.557269 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 00:56:56.560750 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 00:56:56.567289 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 00:56:56.570405 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 00:56:56.574274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 00:56:56.580667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 00:56:56.584205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 00:56:56.587297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 00:56:56.594216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 00:56:56.597376 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 00:56:56.600732 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 00:56:56.607294 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 00:56:56.610644 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 00:56:56.613909 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3511 00:56:56.620417 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3512 00:56:56.623861 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3513 00:56:56.627005 Total UI for P1: 0, mck2ui 16
3514 00:56:56.630647 best dqsien dly found for B1: ( 1, 3, 22)
3515 00:56:56.634033 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 00:56:56.637289 Total UI for P1: 0, mck2ui 16
3517 00:56:56.640656 best dqsien dly found for B0: ( 1, 3, 24)
3518 00:56:56.643774 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3519 00:56:56.646872 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3520 00:56:56.647346
3521 00:56:56.650508 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3522 00:56:56.656909 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3523 00:56:56.657464 [Gating] SW calibration Done
3524 00:56:56.657836 ==
3525 00:56:56.660708 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 00:56:56.667132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 00:56:56.667715 ==
3528 00:56:56.668092 RX Vref Scan: 0
3529 00:56:56.668439
3530 00:56:56.670326 RX Vref 0 -> 0, step: 1
3531 00:56:56.670797
3532 00:56:56.673534 RX Delay -40 -> 252, step: 8
3533 00:56:56.676508 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3534 00:56:56.679980 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3535 00:56:56.683421 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3536 00:56:56.690382 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3537 00:56:56.693661 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3538 00:56:56.696713 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3539 00:56:56.699599 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3540 00:56:56.703182 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3541 00:56:56.706730 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3542 00:56:56.713133 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3543 00:56:56.716392 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3544 00:56:56.720313 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3545 00:56:56.723595 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3546 00:56:56.726772 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3547 00:56:56.733558 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3548 00:56:56.736548 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3549 00:56:56.736982 ==
3550 00:56:56.739863 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 00:56:56.743308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 00:56:56.743742 ==
3553 00:56:56.746953 DQS Delay:
3554 00:56:56.747378 DQS0 = 0, DQS1 = 0
3555 00:56:56.747716 DQM Delay:
3556 00:56:56.749845 DQM0 = 119, DQM1 = 113
3557 00:56:56.750325 DQ Delay:
3558 00:56:56.753280 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3559 00:56:56.756349 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3560 00:56:56.759607 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3561 00:56:56.766338 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =127
3562 00:56:56.766761
3563 00:56:56.767255
3564 00:56:56.767628 ==
3565 00:56:56.770258 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 00:56:56.773299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 00:56:56.773880 ==
3568 00:56:56.774291
3569 00:56:56.774632
3570 00:56:56.776456 TX Vref Scan disable
3571 00:56:56.777044 == TX Byte 0 ==
3572 00:56:56.782571 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3573 00:56:56.786165 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3574 00:56:56.786448 == TX Byte 1 ==
3575 00:56:56.792709 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3576 00:56:56.795865 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3577 00:56:56.796107 ==
3578 00:56:56.799711 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 00:56:56.803159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 00:56:56.803356 ==
3581 00:56:56.815420 TX Vref=22, minBit 1, minWin=25, winSum=417
3582 00:56:56.818999 TX Vref=24, minBit 1, minWin=26, winSum=427
3583 00:56:56.822089 TX Vref=26, minBit 1, minWin=25, winSum=426
3584 00:56:56.825700 TX Vref=28, minBit 11, minWin=25, winSum=430
3585 00:56:56.829093 TX Vref=30, minBit 9, minWin=25, winSum=429
3586 00:56:56.835440 TX Vref=32, minBit 2, minWin=26, winSum=428
3587 00:56:56.838780 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 32
3588 00:56:56.838968
3589 00:56:56.842362 Final TX Range 1 Vref 32
3590 00:56:56.842581
3591 00:56:56.842798 ==
3592 00:56:56.845596 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 00:56:56.848617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 00:56:56.848885 ==
3595 00:56:56.851851
3596 00:56:56.851935
3597 00:56:56.852020 TX Vref Scan disable
3598 00:56:56.855424 == TX Byte 0 ==
3599 00:56:56.858472 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3600 00:56:56.865322 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3601 00:56:56.865409 == TX Byte 1 ==
3602 00:56:56.868651 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3603 00:56:56.875205 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3604 00:56:56.875288
3605 00:56:56.875354 [DATLAT]
3606 00:56:56.875414 Freq=1200, CH1 RK1
3607 00:56:56.875474
3608 00:56:56.878304 DATLAT Default: 0xd
3609 00:56:56.878387 0, 0xFFFF, sum = 0
3610 00:56:56.882068 1, 0xFFFF, sum = 0
3611 00:56:56.885298 2, 0xFFFF, sum = 0
3612 00:56:56.885415 3, 0xFFFF, sum = 0
3613 00:56:56.888453 4, 0xFFFF, sum = 0
3614 00:56:56.888539 5, 0xFFFF, sum = 0
3615 00:56:56.891912 6, 0xFFFF, sum = 0
3616 00:56:56.891996 7, 0xFFFF, sum = 0
3617 00:56:56.895109 8, 0xFFFF, sum = 0
3618 00:56:56.895194 9, 0xFFFF, sum = 0
3619 00:56:56.898315 10, 0xFFFF, sum = 0
3620 00:56:56.898400 11, 0xFFFF, sum = 0
3621 00:56:56.901929 12, 0x0, sum = 1
3622 00:56:56.902033 13, 0x0, sum = 2
3623 00:56:56.904950 14, 0x0, sum = 3
3624 00:56:56.905038 15, 0x0, sum = 4
3625 00:56:56.908284 best_step = 13
3626 00:56:56.908361
3627 00:56:56.908423 ==
3628 00:56:56.912059 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 00:56:56.915178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 00:56:56.915267 ==
3631 00:56:56.915337 RX Vref Scan: 0
3632 00:56:56.915402
3633 00:56:56.918440 RX Vref 0 -> 0, step: 1
3634 00:56:56.918536
3635 00:56:56.921752 RX Delay -13 -> 252, step: 4
3636 00:56:56.925195 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3637 00:56:56.931954 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3638 00:56:56.935776 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3639 00:56:56.938688 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3640 00:56:56.941695 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3641 00:56:56.945301 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3642 00:56:56.951775 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3643 00:56:56.955123 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3644 00:56:56.958755 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3645 00:56:56.961626 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3646 00:56:56.965497 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3647 00:56:56.971726 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3648 00:56:56.975575 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3649 00:56:56.978336 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3650 00:56:56.981963 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3651 00:56:56.988207 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3652 00:56:56.988629 ==
3653 00:56:56.991419 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 00:56:56.994702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 00:56:56.994789 ==
3656 00:56:56.994855 DQS Delay:
3657 00:56:56.997906 DQS0 = 0, DQS1 = 0
3658 00:56:56.998025 DQM Delay:
3659 00:56:57.001349 DQM0 = 119, DQM1 = 113
3660 00:56:57.001436 DQ Delay:
3661 00:56:57.004771 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3662 00:56:57.007933 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3663 00:56:57.011173 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3664 00:56:57.014438 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =124
3665 00:56:57.014521
3666 00:56:57.014585
3667 00:56:57.024790 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3668 00:56:57.027877 CH1 RK1: MR19=403, MR18=8EC
3669 00:56:57.031756 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3670 00:56:57.034835 [RxdqsGatingPostProcess] freq 1200
3671 00:56:57.041793 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3672 00:56:57.044604 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 00:56:57.048696 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 00:56:57.051407 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 00:56:57.054970 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 00:56:57.058099 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 00:56:57.061660 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 00:56:57.064686 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 00:56:57.068143 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 00:56:57.068353 Pre-setting of DQS Precalculation
3681 00:56:57.074541 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3682 00:56:57.081601 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3683 00:56:57.088262 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3684 00:56:57.088661
3685 00:56:57.088969
3686 00:56:57.091825 [Calibration Summary] 2400 Mbps
3687 00:56:57.094753 CH 0, Rank 0
3688 00:56:57.095179 SW Impedance : PASS
3689 00:56:57.098250 DUTY Scan : NO K
3690 00:56:57.101149 ZQ Calibration : PASS
3691 00:56:57.101626 Jitter Meter : NO K
3692 00:56:57.104826 CBT Training : PASS
3693 00:56:57.108061 Write leveling : PASS
3694 00:56:57.108557 RX DQS gating : PASS
3695 00:56:57.111704 RX DQ/DQS(RDDQC) : PASS
3696 00:56:57.114567 TX DQ/DQS : PASS
3697 00:56:57.115000 RX DATLAT : PASS
3698 00:56:57.117998 RX DQ/DQS(Engine): PASS
3699 00:56:57.118484 TX OE : NO K
3700 00:56:57.121383 All Pass.
3701 00:56:57.121832
3702 00:56:57.122219 CH 0, Rank 1
3703 00:56:57.125029 SW Impedance : PASS
3704 00:56:57.125554 DUTY Scan : NO K
3705 00:56:57.127931 ZQ Calibration : PASS
3706 00:56:57.131157 Jitter Meter : NO K
3707 00:56:57.131629 CBT Training : PASS
3708 00:56:57.134943 Write leveling : PASS
3709 00:56:57.137647 RX DQS gating : PASS
3710 00:56:57.138203 RX DQ/DQS(RDDQC) : PASS
3711 00:56:57.141294 TX DQ/DQS : PASS
3712 00:56:57.144815 RX DATLAT : PASS
3713 00:56:57.145374 RX DQ/DQS(Engine): PASS
3714 00:56:57.147835 TX OE : NO K
3715 00:56:57.148286 All Pass.
3716 00:56:57.148719
3717 00:56:57.151472 CH 1, Rank 0
3718 00:56:57.151909 SW Impedance : PASS
3719 00:56:57.154463 DUTY Scan : NO K
3720 00:56:57.158155 ZQ Calibration : PASS
3721 00:56:57.158594 Jitter Meter : NO K
3722 00:56:57.161207 CBT Training : PASS
3723 00:56:57.161743 Write leveling : PASS
3724 00:56:57.164481 RX DQS gating : PASS
3725 00:56:57.168063 RX DQ/DQS(RDDQC) : PASS
3726 00:56:57.168492 TX DQ/DQS : PASS
3727 00:56:57.171074 RX DATLAT : PASS
3728 00:56:57.174382 RX DQ/DQS(Engine): PASS
3729 00:56:57.174949 TX OE : NO K
3730 00:56:57.177869 All Pass.
3731 00:56:57.178320
3732 00:56:57.178645 CH 1, Rank 1
3733 00:56:57.181180 SW Impedance : PASS
3734 00:56:57.181603 DUTY Scan : NO K
3735 00:56:57.184902 ZQ Calibration : PASS
3736 00:56:57.188160 Jitter Meter : NO K
3737 00:56:57.188698 CBT Training : PASS
3738 00:56:57.191561 Write leveling : PASS
3739 00:56:57.194723 RX DQS gating : PASS
3740 00:56:57.195328 RX DQ/DQS(RDDQC) : PASS
3741 00:56:57.197881 TX DQ/DQS : PASS
3742 00:56:57.201150 RX DATLAT : PASS
3743 00:56:57.201748 RX DQ/DQS(Engine): PASS
3744 00:56:57.204879 TX OE : NO K
3745 00:56:57.205338 All Pass.
3746 00:56:57.205679
3747 00:56:57.207950 DramC Write-DBI off
3748 00:56:57.211495 PER_BANK_REFRESH: Hybrid Mode
3749 00:56:57.211923 TX_TRACKING: ON
3750 00:56:57.221314 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3751 00:56:57.224818 [FAST_K] Save calibration result to emmc
3752 00:56:57.227723 dramc_set_vcore_voltage set vcore to 650000
3753 00:56:57.231489 Read voltage for 600, 5
3754 00:56:57.231916 Vio18 = 0
3755 00:56:57.232252 Vcore = 650000
3756 00:56:57.232569 Vdram = 0
3757 00:56:57.234589 Vddq = 0
3758 00:56:57.235017 Vmddr = 0
3759 00:56:57.241715 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3760 00:56:57.244927 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3761 00:56:57.248113 MEM_TYPE=3, freq_sel=19
3762 00:56:57.251338 sv_algorithm_assistance_LP4_1600
3763 00:56:57.254982 ============ PULL DRAM RESETB DOWN ============
3764 00:56:57.257934 ========== PULL DRAM RESETB DOWN end =========
3765 00:56:57.264696 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3766 00:56:57.267728 ===================================
3767 00:56:57.268204 LPDDR4 DRAM CONFIGURATION
3768 00:56:57.271760 ===================================
3769 00:56:57.274511 EX_ROW_EN[0] = 0x0
3770 00:56:57.277834 EX_ROW_EN[1] = 0x0
3771 00:56:57.278442 LP4Y_EN = 0x0
3772 00:56:57.281361 WORK_FSP = 0x0
3773 00:56:57.282041 WL = 0x2
3774 00:56:57.284575 RL = 0x2
3775 00:56:57.285047 BL = 0x2
3776 00:56:57.288030 RPST = 0x0
3777 00:56:57.288606 RD_PRE = 0x0
3778 00:56:57.290883 WR_PRE = 0x1
3779 00:56:57.291370 WR_PST = 0x0
3780 00:56:57.294487 DBI_WR = 0x0
3781 00:56:57.294959 DBI_RD = 0x0
3782 00:56:57.297653 OTF = 0x1
3783 00:56:57.301054 ===================================
3784 00:56:57.304430 ===================================
3785 00:56:57.304910 ANA top config
3786 00:56:57.307954 ===================================
3787 00:56:57.310941 DLL_ASYNC_EN = 0
3788 00:56:57.314494 ALL_SLAVE_EN = 1
3789 00:56:57.314971 NEW_RANK_MODE = 1
3790 00:56:57.317600 DLL_IDLE_MODE = 1
3791 00:56:57.320839 LP45_APHY_COMB_EN = 1
3792 00:56:57.324660 TX_ODT_DIS = 1
3793 00:56:57.327713 NEW_8X_MODE = 1
3794 00:56:57.331034 ===================================
3795 00:56:57.334261 ===================================
3796 00:56:57.334770 data_rate = 1200
3797 00:56:57.337560 CKR = 1
3798 00:56:57.340791 DQ_P2S_RATIO = 8
3799 00:56:57.344541 ===================================
3800 00:56:57.347931 CA_P2S_RATIO = 8
3801 00:56:57.350914 DQ_CA_OPEN = 0
3802 00:56:57.354486 DQ_SEMI_OPEN = 0
3803 00:56:57.355073 CA_SEMI_OPEN = 0
3804 00:56:57.357634 CA_FULL_RATE = 0
3805 00:56:57.360784 DQ_CKDIV4_EN = 1
3806 00:56:57.364611 CA_CKDIV4_EN = 1
3807 00:56:57.367638 CA_PREDIV_EN = 0
3808 00:56:57.370963 PH8_DLY = 0
3809 00:56:57.371437 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3810 00:56:57.374377 DQ_AAMCK_DIV = 4
3811 00:56:57.377396 CA_AAMCK_DIV = 4
3812 00:56:57.381038 CA_ADMCK_DIV = 4
3813 00:56:57.384504 DQ_TRACK_CA_EN = 0
3814 00:56:57.387263 CA_PICK = 600
3815 00:56:57.387735 CA_MCKIO = 600
3816 00:56:57.390899 MCKIO_SEMI = 0
3817 00:56:57.394294 PLL_FREQ = 2288
3818 00:56:57.397518 DQ_UI_PI_RATIO = 32
3819 00:56:57.401050 CA_UI_PI_RATIO = 0
3820 00:56:57.404022 ===================================
3821 00:56:57.407597 ===================================
3822 00:56:57.410712 memory_type:LPDDR4
3823 00:56:57.411397 GP_NUM : 10
3824 00:56:57.413760 SRAM_EN : 1
3825 00:56:57.414278 MD32_EN : 0
3826 00:56:57.417530 ===================================
3827 00:56:57.420719 [ANA_INIT] >>>>>>>>>>>>>>
3828 00:56:57.424147 <<<<<< [CONFIGURE PHASE]: ANA_TX
3829 00:56:57.427620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3830 00:56:57.430643 ===================================
3831 00:56:57.433906 data_rate = 1200,PCW = 0X5800
3832 00:56:57.437599 ===================================
3833 00:56:57.440188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3834 00:56:57.447195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 00:56:57.450838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 00:56:57.457161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3837 00:56:57.460193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3838 00:56:57.463617 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3839 00:56:57.464092 [ANA_INIT] flow start
3840 00:56:57.467091 [ANA_INIT] PLL >>>>>>>>
3841 00:56:57.470387 [ANA_INIT] PLL <<<<<<<<
3842 00:56:57.470859 [ANA_INIT] MIDPI >>>>>>>>
3843 00:56:57.474047 [ANA_INIT] MIDPI <<<<<<<<
3844 00:56:57.477179 [ANA_INIT] DLL >>>>>>>>
3845 00:56:57.477739 [ANA_INIT] flow end
3846 00:56:57.483620 ============ LP4 DIFF to SE enter ============
3847 00:56:57.487144 ============ LP4 DIFF to SE exit ============
3848 00:56:57.490533 [ANA_INIT] <<<<<<<<<<<<<
3849 00:56:57.493825 [Flow] Enable top DCM control >>>>>
3850 00:56:57.497043 [Flow] Enable top DCM control <<<<<
3851 00:56:57.497614 Enable DLL master slave shuffle
3852 00:56:57.503566 ==============================================================
3853 00:56:57.507289 Gating Mode config
3854 00:56:57.510571 ==============================================================
3855 00:56:57.513444 Config description:
3856 00:56:57.523592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3857 00:56:57.530097 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3858 00:56:57.533370 SELPH_MODE 0: By rank 1: By Phase
3859 00:56:57.539891 ==============================================================
3860 00:56:57.543555 GAT_TRACK_EN = 1
3861 00:56:57.546479 RX_GATING_MODE = 2
3862 00:56:57.550394 RX_GATING_TRACK_MODE = 2
3863 00:56:57.550981 SELPH_MODE = 1
3864 00:56:57.553123 PICG_EARLY_EN = 1
3865 00:56:57.556892 VALID_LAT_VALUE = 1
3866 00:56:57.563629 ==============================================================
3867 00:56:57.566308 Enter into Gating configuration >>>>
3868 00:56:57.570030 Exit from Gating configuration <<<<
3869 00:56:57.573318 Enter into DVFS_PRE_config >>>>>
3870 00:56:57.583474 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3871 00:56:57.586510 Exit from DVFS_PRE_config <<<<<
3872 00:56:57.590099 Enter into PICG configuration >>>>
3873 00:56:57.593532 Exit from PICG configuration <<<<
3874 00:56:57.596698 [RX_INPUT] configuration >>>>>
3875 00:56:57.599758 [RX_INPUT] configuration <<<<<
3876 00:56:57.603134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3877 00:56:57.609915 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3878 00:56:57.616843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 00:56:57.623309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 00:56:57.626721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 00:56:57.633488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 00:56:57.639857 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3883 00:56:57.643504 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3884 00:56:57.646691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3885 00:56:57.650058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3886 00:56:57.653216 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3887 00:56:57.659498 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 00:56:57.663115 ===================================
3889 00:56:57.666496 LPDDR4 DRAM CONFIGURATION
3890 00:56:57.669538 ===================================
3891 00:56:57.670140 EX_ROW_EN[0] = 0x0
3892 00:56:57.672862 EX_ROW_EN[1] = 0x0
3893 00:56:57.673433 LP4Y_EN = 0x0
3894 00:56:57.676182 WORK_FSP = 0x0
3895 00:56:57.676752 WL = 0x2
3896 00:56:57.679317 RL = 0x2
3897 00:56:57.679790 BL = 0x2
3898 00:56:57.682884 RPST = 0x0
3899 00:56:57.683462 RD_PRE = 0x0
3900 00:56:57.686080 WR_PRE = 0x1
3901 00:56:57.686659 WR_PST = 0x0
3902 00:56:57.689384 DBI_WR = 0x0
3903 00:56:57.692866 DBI_RD = 0x0
3904 00:56:57.693443 OTF = 0x1
3905 00:56:57.695936 ===================================
3906 00:56:57.699461 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3907 00:56:57.702570 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3908 00:56:57.709463 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 00:56:57.712491 ===================================
3910 00:56:57.716071 LPDDR4 DRAM CONFIGURATION
3911 00:56:57.719035 ===================================
3912 00:56:57.719563 EX_ROW_EN[0] = 0x10
3913 00:56:57.722615 EX_ROW_EN[1] = 0x0
3914 00:56:57.723151 LP4Y_EN = 0x0
3915 00:56:57.726094 WORK_FSP = 0x0
3916 00:56:57.726668 WL = 0x2
3917 00:56:57.728845 RL = 0x2
3918 00:56:57.729318 BL = 0x2
3919 00:56:57.732822 RPST = 0x0
3920 00:56:57.733398 RD_PRE = 0x0
3921 00:56:57.736285 WR_PRE = 0x1
3922 00:56:57.736857 WR_PST = 0x0
3923 00:56:57.738909 DBI_WR = 0x0
3924 00:56:57.739384 DBI_RD = 0x0
3925 00:56:57.742438 OTF = 0x1
3926 00:56:57.746060 ===================================
3927 00:56:57.752560 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3928 00:56:57.755610 nWR fixed to 30
3929 00:56:57.759284 [ModeRegInit_LP4] CH0 RK0
3930 00:56:57.759849 [ModeRegInit_LP4] CH0 RK1
3931 00:56:57.762179 [ModeRegInit_LP4] CH1 RK0
3932 00:56:57.765975 [ModeRegInit_LP4] CH1 RK1
3933 00:56:57.766548 match AC timing 17
3934 00:56:57.772303 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3935 00:56:57.775716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3936 00:56:57.778693 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3937 00:56:57.785506 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3938 00:56:57.788845 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3939 00:56:57.789413 ==
3940 00:56:57.792268 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 00:56:57.795356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 00:56:57.795832 ==
3943 00:56:57.802226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 00:56:57.808897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 00:56:57.812031 [CA 0] Center 36 (6~67) winsize 62
3946 00:56:57.815492 [CA 1] Center 36 (6~67) winsize 62
3947 00:56:57.818918 [CA 2] Center 34 (4~65) winsize 62
3948 00:56:57.821916 [CA 3] Center 34 (4~65) winsize 62
3949 00:56:57.825696 [CA 4] Center 33 (3~64) winsize 62
3950 00:56:57.828636 [CA 5] Center 33 (3~64) winsize 62
3951 00:56:57.829105
3952 00:56:57.832082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 00:56:57.832650
3954 00:56:57.835655 [CATrainingPosCal] consider 1 rank data
3955 00:56:57.838633 u2DelayCellTimex100 = 270/100 ps
3956 00:56:57.842064 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3957 00:56:57.845503 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 00:56:57.848984 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 00:56:57.851982 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 00:56:57.855837 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 00:56:57.858685 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 00:56:57.862097
3963 00:56:57.865661 CA PerBit enable=1, Macro0, CA PI delay=33
3964 00:56:57.866165
3965 00:56:57.868789 [CBTSetCACLKResult] CA Dly = 33
3966 00:56:57.869518 CS Dly: 5 (0~36)
3967 00:56:57.869970 ==
3968 00:56:57.871844 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 00:56:57.875140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 00:56:57.875622 ==
3971 00:56:57.882041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 00:56:57.888617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3973 00:56:57.891668 [CA 0] Center 36 (6~67) winsize 62
3974 00:56:57.895541 [CA 1] Center 36 (6~67) winsize 62
3975 00:56:57.898426 [CA 2] Center 34 (4~65) winsize 62
3976 00:56:57.901847 [CA 3] Center 34 (4~65) winsize 62
3977 00:56:57.905173 [CA 4] Center 34 (3~65) winsize 63
3978 00:56:57.908454 [CA 5] Center 33 (3~64) winsize 62
3979 00:56:57.909022
3980 00:56:57.911829 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3981 00:56:57.912361
3982 00:56:57.915427 [CATrainingPosCal] consider 2 rank data
3983 00:56:57.918652 u2DelayCellTimex100 = 270/100 ps
3984 00:56:57.921489 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3985 00:56:57.925019 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 00:56:57.928321 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 00:56:57.932106 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 00:56:57.938491 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 00:56:57.941470 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 00:56:57.941973
3991 00:56:57.945199 CA PerBit enable=1, Macro0, CA PI delay=33
3992 00:56:57.945887
3993 00:56:57.948763 [CBTSetCACLKResult] CA Dly = 33
3994 00:56:57.949329 CS Dly: 5 (0~37)
3995 00:56:57.949703
3996 00:56:57.951910 ----->DramcWriteLeveling(PI) begin...
3997 00:56:57.952484 ==
3998 00:56:57.955149 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 00:56:57.961804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 00:56:57.962428 ==
4001 00:56:57.965329 Write leveling (Byte 0): 33 => 33
4002 00:56:57.965897 Write leveling (Byte 1): 33 => 33
4003 00:56:57.968623 DramcWriteLeveling(PI) end<-----
4004 00:56:57.969188
4005 00:56:57.971365 ==
4006 00:56:57.971832 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 00:56:57.978555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 00:56:57.979133 ==
4009 00:56:57.981827 [Gating] SW mode calibration
4010 00:56:57.988558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 00:56:57.991514 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4012 00:56:57.998068 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 00:56:58.001706 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 00:56:58.004559 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 00:56:58.011526 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
4016 00:56:58.014567 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4017 00:56:58.017835 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 00:56:58.024541 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 00:56:58.027894 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 00:56:58.031439 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 00:56:58.038198 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 00:56:58.041367 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 00:56:58.044786 0 10 12 | B1->B0 | 2626 3e3e | 0 0 | (0 0) (0 0)
4024 00:56:58.047723 0 10 16 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
4025 00:56:58.054548 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 00:56:58.058177 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 00:56:58.061594 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:56:58.067966 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 00:56:58.071511 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 00:56:58.074817 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 00:56:58.081325 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4032 00:56:58.085232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4033 00:56:58.088164 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 00:56:58.094655 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 00:56:58.097674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 00:56:58.101098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 00:56:58.107837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 00:56:58.111663 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 00:56:58.114431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 00:56:58.121175 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 00:56:58.124153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 00:56:58.127886 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 00:56:58.134433 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:56:58.138168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:56:58.141462 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 00:56:58.147811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4047 00:56:58.150846 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4048 00:56:58.154534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4049 00:56:58.157398 Total UI for P1: 0, mck2ui 16
4050 00:56:58.161309 best dqsien dly found for B0: ( 0, 13, 10)
4051 00:56:58.167569 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 00:56:58.168141 Total UI for P1: 0, mck2ui 16
4053 00:56:58.170785 best dqsien dly found for B1: ( 0, 13, 16)
4054 00:56:58.177657 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4055 00:56:58.180701 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4056 00:56:58.181265
4057 00:56:58.184178 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4058 00:56:58.187451 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4059 00:56:58.191040 [Gating] SW calibration Done
4060 00:56:58.191609 ==
4061 00:56:58.194169 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 00:56:58.197419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 00:56:58.198089 ==
4064 00:56:58.200863 RX Vref Scan: 0
4065 00:56:58.201483
4066 00:56:58.202074 RX Vref 0 -> 0, step: 1
4067 00:56:58.202594
4068 00:56:58.203807 RX Delay -230 -> 252, step: 16
4069 00:56:58.207834 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4070 00:56:58.214275 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4071 00:56:58.217835 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4072 00:56:58.220606 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4073 00:56:58.223917 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4074 00:56:58.230564 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4075 00:56:58.233993 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4076 00:56:58.237344 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4077 00:56:58.240390 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4078 00:56:58.244022 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4079 00:56:58.250723 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4080 00:56:58.254048 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4081 00:56:58.256996 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4082 00:56:58.260711 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4083 00:56:58.267308 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4084 00:56:58.270544 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4085 00:56:58.271120 ==
4086 00:56:58.273683 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 00:56:58.277295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 00:56:58.277863 ==
4089 00:56:58.280418 DQS Delay:
4090 00:56:58.280983 DQS0 = 0, DQS1 = 0
4091 00:56:58.281353 DQM Delay:
4092 00:56:58.283819 DQM0 = 53, DQM1 = 40
4093 00:56:58.284541 DQ Delay:
4094 00:56:58.287263 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4095 00:56:58.290587 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4096 00:56:58.293893 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4097 00:56:58.297141 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4098 00:56:58.297708
4099 00:56:58.298125
4100 00:56:58.298473 ==
4101 00:56:58.300297 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 00:56:58.307016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 00:56:58.307591 ==
4104 00:56:58.307962
4105 00:56:58.308303
4106 00:56:58.308627 TX Vref Scan disable
4107 00:56:58.310651 == TX Byte 0 ==
4108 00:56:58.313894 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4109 00:56:58.320446 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4110 00:56:58.320914 == TX Byte 1 ==
4111 00:56:58.323921 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4112 00:56:58.330376 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4113 00:56:58.330949 ==
4114 00:56:58.333891 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 00:56:58.337153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 00:56:58.337731 ==
4117 00:56:58.338165
4118 00:56:58.338721
4119 00:56:58.340122 TX Vref Scan disable
4120 00:56:58.343702 == TX Byte 0 ==
4121 00:56:58.346755 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4122 00:56:58.350224 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4123 00:56:58.353676 == TX Byte 1 ==
4124 00:56:58.356910 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4125 00:56:58.360186 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4126 00:56:58.360652
4127 00:56:58.361015 [DATLAT]
4128 00:56:58.363578 Freq=600, CH0 RK0
4129 00:56:58.364044
4130 00:56:58.364407 DATLAT Default: 0x9
4131 00:56:58.366938 0, 0xFFFF, sum = 0
4132 00:56:58.370330 1, 0xFFFF, sum = 0
4133 00:56:58.370909 2, 0xFFFF, sum = 0
4134 00:56:58.373444 3, 0xFFFF, sum = 0
4135 00:56:58.374093 4, 0xFFFF, sum = 0
4136 00:56:58.377079 5, 0xFFFF, sum = 0
4137 00:56:58.377653 6, 0xFFFF, sum = 0
4138 00:56:58.380288 7, 0xFFFF, sum = 0
4139 00:56:58.380860 8, 0x0, sum = 1
4140 00:56:58.383662 9, 0x0, sum = 2
4141 00:56:58.384241 10, 0x0, sum = 3
4142 00:56:58.386535 11, 0x0, sum = 4
4143 00:56:58.387077 best_step = 9
4144 00:56:58.387445
4145 00:56:58.387786 ==
4146 00:56:58.389915 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 00:56:58.393362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 00:56:58.393933 ==
4149 00:56:58.396472 RX Vref Scan: 1
4150 00:56:58.397038
4151 00:56:58.397407 RX Vref 0 -> 0, step: 1
4152 00:56:58.399741
4153 00:56:58.400307 RX Delay -179 -> 252, step: 8
4154 00:56:58.400680
4155 00:56:58.403413 Set Vref, RX VrefLevel [Byte0]: 61
4156 00:56:58.406430 [Byte1]: 50
4157 00:56:58.411107
4158 00:56:58.411671 Final RX Vref Byte 0 = 61 to rank0
4159 00:56:58.414007 Final RX Vref Byte 1 = 50 to rank0
4160 00:56:58.417368 Final RX Vref Byte 0 = 61 to rank1
4161 00:56:58.420629 Final RX Vref Byte 1 = 50 to rank1==
4162 00:56:58.424030 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 00:56:58.430557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 00:56:58.431114 ==
4165 00:56:58.431485 DQS Delay:
4166 00:56:58.431824 DQS0 = 0, DQS1 = 0
4167 00:56:58.433908 DQM Delay:
4168 00:56:58.434405 DQM0 = 49, DQM1 = 37
4169 00:56:58.437540 DQ Delay:
4170 00:56:58.441106 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4171 00:56:58.444093 DQ4 =52, DQ5 =40, DQ6 =64, DQ7 =56
4172 00:56:58.444681 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4173 00:56:58.450791 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4174 00:56:58.451361
4175 00:56:58.451727
4176 00:56:58.457430 [DQSOSCAuto] RK0, (LSB)MR18= 0x5650, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4177 00:56:58.460847 CH0 RK0: MR19=808, MR18=5650
4178 00:56:58.467651 CH0_RK0: MR19=0x808, MR18=0x5650, DQSOSC=393, MR23=63, INC=169, DEC=113
4179 00:56:58.468227
4180 00:56:58.470738 ----->DramcWriteLeveling(PI) begin...
4181 00:56:58.471319 ==
4182 00:56:58.473736 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 00:56:58.477341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 00:56:58.477908 ==
4185 00:56:58.480735 Write leveling (Byte 0): 37 => 37
4186 00:56:58.483917 Write leveling (Byte 1): 30 => 30
4187 00:56:58.487273 DramcWriteLeveling(PI) end<-----
4188 00:56:58.487837
4189 00:56:58.488204 ==
4190 00:56:58.490764 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 00:56:58.493929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 00:56:58.494687 ==
4193 00:56:58.497463 [Gating] SW mode calibration
4194 00:56:58.503870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4195 00:56:58.510220 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4196 00:56:58.513933 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 00:56:58.517139 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 00:56:58.523727 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 00:56:58.527151 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4200 00:56:58.530400 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4201 00:56:58.536650 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 00:56:58.540071 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 00:56:58.543592 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 00:56:58.550035 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 00:56:58.553373 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 00:56:58.556999 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 00:56:58.563565 0 10 12 | B1->B0 | 3131 2e2e | 0 1 | (0 0) (0 0)
4208 00:56:58.566724 0 10 16 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
4209 00:56:58.570305 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 00:56:58.576885 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 00:56:58.580526 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 00:56:58.583679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 00:56:58.590114 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 00:56:58.593541 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 00:56:58.597057 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 00:56:58.603498 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 00:56:58.606558 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 00:56:58.609976 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 00:56:58.617044 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 00:56:58.620115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 00:56:58.623220 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 00:56:58.630240 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 00:56:58.633602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 00:56:58.637034 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 00:56:58.639940 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 00:56:58.647001 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 00:56:58.650247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 00:56:58.653246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 00:56:58.659910 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 00:56:58.663447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 00:56:58.666926 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4232 00:56:58.673006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 00:56:58.676258 Total UI for P1: 0, mck2ui 16
4234 00:56:58.679815 best dqsien dly found for B0: ( 0, 13, 12)
4235 00:56:58.680100 Total UI for P1: 0, mck2ui 16
4236 00:56:58.686748 best dqsien dly found for B1: ( 0, 13, 14)
4237 00:56:58.689875 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4238 00:56:58.693213 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4239 00:56:58.693467
4240 00:56:58.696629 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4241 00:56:58.700015 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4242 00:56:58.702887 [Gating] SW calibration Done
4243 00:56:58.703075 ==
4244 00:56:58.706337 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 00:56:58.709441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 00:56:58.709634 ==
4247 00:56:58.713225 RX Vref Scan: 0
4248 00:56:58.713466
4249 00:56:58.713679 RX Vref 0 -> 0, step: 1
4250 00:56:58.716369
4251 00:56:58.716569 RX Delay -230 -> 252, step: 16
4252 00:56:58.722918 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4253 00:56:58.726202 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4254 00:56:58.729673 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4255 00:56:58.732960 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4256 00:56:58.736382 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4257 00:56:58.742999 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4258 00:56:58.746452 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4259 00:56:58.749810 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4260 00:56:58.752916 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4261 00:56:58.759636 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4262 00:56:58.763094 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4263 00:56:58.766403 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4264 00:56:58.769652 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4265 00:56:58.776206 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4266 00:56:58.779598 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4267 00:56:58.782933 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4268 00:56:58.783122 ==
4269 00:56:58.786273 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 00:56:58.789338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 00:56:58.789502 ==
4272 00:56:58.792772 DQS Delay:
4273 00:56:58.792993 DQS0 = 0, DQS1 = 0
4274 00:56:58.795880 DQM Delay:
4275 00:56:58.796056 DQM0 = 52, DQM1 = 41
4276 00:56:58.796206 DQ Delay:
4277 00:56:58.799393 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4278 00:56:58.802736 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4279 00:56:58.806286 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4280 00:56:58.809795 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4281 00:56:58.810487
4282 00:56:58.811094
4283 00:56:58.811699 ==
4284 00:56:58.813127 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 00:56:58.819577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 00:56:58.820248 ==
4287 00:56:58.820859
4288 00:56:58.821462
4289 00:56:58.822079 TX Vref Scan disable
4290 00:56:58.823905 == TX Byte 0 ==
4291 00:56:58.826685 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4292 00:56:58.830333 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4293 00:56:58.833448 == TX Byte 1 ==
4294 00:56:58.836647 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4295 00:56:58.843330 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4296 00:56:58.843527 ==
4297 00:56:58.846605 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 00:56:58.850147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 00:56:58.850408 ==
4300 00:56:58.850607
4301 00:56:58.850791
4302 00:56:58.853384 TX Vref Scan disable
4303 00:56:58.856729 == TX Byte 0 ==
4304 00:56:58.859840 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4305 00:56:58.863271 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4306 00:56:58.866846 == TX Byte 1 ==
4307 00:56:58.870004 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4308 00:56:58.873340 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4309 00:56:58.873600
4310 00:56:58.873787 [DATLAT]
4311 00:56:58.876729 Freq=600, CH0 RK1
4312 00:56:58.876966
4313 00:56:58.879624 DATLAT Default: 0x9
4314 00:56:58.879862 0, 0xFFFF, sum = 0
4315 00:56:58.883294 1, 0xFFFF, sum = 0
4316 00:56:58.883491 2, 0xFFFF, sum = 0
4317 00:56:58.886727 3, 0xFFFF, sum = 0
4318 00:56:58.886889 4, 0xFFFF, sum = 0
4319 00:56:58.889585 5, 0xFFFF, sum = 0
4320 00:56:58.889745 6, 0xFFFF, sum = 0
4321 00:56:58.893247 7, 0xFFFF, sum = 0
4322 00:56:58.893389 8, 0x0, sum = 1
4323 00:56:58.896432 9, 0x0, sum = 2
4324 00:56:58.896551 10, 0x0, sum = 3
4325 00:56:58.896645 11, 0x0, sum = 4
4326 00:56:58.899552 best_step = 9
4327 00:56:58.899716
4328 00:56:58.899812 ==
4329 00:56:58.903203 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 00:56:58.906394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 00:56:58.906504 ==
4332 00:56:58.909785 RX Vref Scan: 0
4333 00:56:58.909886
4334 00:56:58.909984 RX Vref 0 -> 0, step: 1
4335 00:56:58.912976
4336 00:56:58.913098 RX Delay -179 -> 252, step: 8
4337 00:56:58.920380 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4338 00:56:58.924051 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4339 00:56:58.927307 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4340 00:56:58.930396 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4341 00:56:58.933962 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4342 00:56:58.940464 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4343 00:56:58.943873 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4344 00:56:58.947841 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4345 00:56:58.950591 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4346 00:56:58.954448 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4347 00:56:58.960515 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4348 00:56:58.964220 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4349 00:56:58.967602 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4350 00:56:58.970959 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4351 00:56:58.977215 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4352 00:56:58.980234 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4353 00:56:58.980474 ==
4354 00:56:58.983672 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 00:56:58.987375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 00:56:58.987559 ==
4357 00:56:58.990305 DQS Delay:
4358 00:56:58.990458 DQS0 = 0, DQS1 = 0
4359 00:56:58.990577 DQM Delay:
4360 00:56:58.993489 DQM0 = 48, DQM1 = 41
4361 00:56:58.993640 DQ Delay:
4362 00:56:58.996880 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4363 00:56:59.000236 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4364 00:56:59.003549 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4365 00:56:59.006903 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4366 00:56:59.007005
4367 00:56:59.007084
4368 00:56:59.016863 [DQSOSCAuto] RK1, (LSB)MR18= 0x6330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4369 00:56:59.019887 CH0 RK1: MR19=808, MR18=6330
4370 00:56:59.023156 CH0_RK1: MR19=0x808, MR18=0x6330, DQSOSC=391, MR23=63, INC=171, DEC=114
4371 00:56:59.026887 [RxdqsGatingPostProcess] freq 600
4372 00:56:59.032988 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 00:56:59.036631 Pre-setting of DQS Precalculation
4374 00:56:59.039860 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 00:56:59.039967 ==
4376 00:56:59.043160 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 00:56:59.049759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 00:56:59.049886 ==
4379 00:56:59.052797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 00:56:59.059645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4381 00:56:59.063118 [CA 0] Center 35 (5~66) winsize 62
4382 00:56:59.066339 [CA 1] Center 35 (5~66) winsize 62
4383 00:56:59.069692 [CA 2] Center 34 (4~65) winsize 62
4384 00:56:59.073197 [CA 3] Center 33 (3~64) winsize 62
4385 00:56:59.076124 [CA 4] Center 34 (3~65) winsize 63
4386 00:56:59.079550 [CA 5] Center 33 (3~64) winsize 62
4387 00:56:59.079635
4388 00:56:59.083085 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4389 00:56:59.083172
4390 00:56:59.086182 [CATrainingPosCal] consider 1 rank data
4391 00:56:59.089765 u2DelayCellTimex100 = 270/100 ps
4392 00:56:59.092674 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 00:56:59.099589 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 00:56:59.102803 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 00:56:59.106466 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 00:56:59.109417 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4397 00:56:59.113242 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 00:56:59.113370
4399 00:56:59.116315 CA PerBit enable=1, Macro0, CA PI delay=33
4400 00:56:59.116457
4401 00:56:59.119877 [CBTSetCACLKResult] CA Dly = 33
4402 00:56:59.120020 CS Dly: 4 (0~35)
4403 00:56:59.123052 ==
4404 00:56:59.123212 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 00:56:59.129723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 00:56:59.129908 ==
4407 00:56:59.133344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 00:56:59.139712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4409 00:56:59.143216 [CA 0] Center 35 (5~66) winsize 62
4410 00:56:59.146704 [CA 1] Center 35 (5~66) winsize 62
4411 00:56:59.150152 [CA 2] Center 34 (4~65) winsize 62
4412 00:56:59.153427 [CA 3] Center 34 (4~65) winsize 62
4413 00:56:59.156766 [CA 4] Center 34 (4~64) winsize 61
4414 00:56:59.160137 [CA 5] Center 33 (3~64) winsize 62
4415 00:56:59.160360
4416 00:56:59.163400 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4417 00:56:59.163607
4418 00:56:59.166570 [CATrainingPosCal] consider 2 rank data
4419 00:56:59.169954 u2DelayCellTimex100 = 270/100 ps
4420 00:56:59.173095 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 00:56:59.176689 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 00:56:59.183395 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 00:56:59.186714 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4424 00:56:59.189841 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4425 00:56:59.193199 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 00:56:59.193308
4427 00:56:59.196661 CA PerBit enable=1, Macro0, CA PI delay=33
4428 00:56:59.196770
4429 00:56:59.199672 [CBTSetCACLKResult] CA Dly = 33
4430 00:56:59.199784 CS Dly: 4 (0~36)
4431 00:56:59.199870
4432 00:56:59.202967 ----->DramcWriteLeveling(PI) begin...
4433 00:56:59.206252 ==
4434 00:56:59.209656 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 00:56:59.213074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 00:56:59.213259 ==
4437 00:56:59.216546 Write leveling (Byte 0): 31 => 31
4438 00:56:59.219729 Write leveling (Byte 1): 31 => 31
4439 00:56:59.222963 DramcWriteLeveling(PI) end<-----
4440 00:56:59.223133
4441 00:56:59.223273 ==
4442 00:56:59.226431 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 00:56:59.229410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 00:56:59.229606 ==
4445 00:56:59.233091 [Gating] SW mode calibration
4446 00:56:59.239835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 00:56:59.246809 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 00:56:59.250133 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 00:56:59.253379 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 00:56:59.256596 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 00:56:59.263339 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
4452 00:56:59.268367 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 00:56:59.269899 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 00:56:59.276286 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 00:56:59.280074 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 00:56:59.283178 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 00:56:59.289608 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 00:56:59.293133 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4459 00:56:59.296386 0 10 12 | B1->B0 | 3f3f 4343 | 0 0 | (1 1) (0 0)
4460 00:56:59.302974 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:56:59.306333 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 00:56:59.309563 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 00:56:59.316434 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 00:56:59.319756 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 00:56:59.323585 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 00:56:59.329557 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4467 00:56:59.333141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4468 00:56:59.336460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 00:56:59.342901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 00:56:59.346708 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 00:56:59.349757 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 00:56:59.356398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 00:56:59.359998 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 00:56:59.362847 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 00:56:59.369250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 00:56:59.372706 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 00:56:59.376319 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 00:56:59.382595 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:56:59.385866 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 00:56:59.389487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 00:56:59.395997 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:56:59.399427 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4483 00:56:59.402649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4484 00:56:59.405856 Total UI for P1: 0, mck2ui 16
4485 00:56:59.409295 best dqsien dly found for B0: ( 0, 13, 8)
4486 00:56:59.412706 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 00:56:59.415879 Total UI for P1: 0, mck2ui 16
4488 00:56:59.419242 best dqsien dly found for B1: ( 0, 13, 12)
4489 00:56:59.422495 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4490 00:56:59.429054 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4491 00:56:59.429484
4492 00:56:59.432539 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4493 00:56:59.435786 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4494 00:56:59.439434 [Gating] SW calibration Done
4495 00:56:59.440029 ==
4496 00:56:59.442729 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 00:56:59.445885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 00:56:59.446343 ==
4499 00:56:59.446724 RX Vref Scan: 0
4500 00:56:59.447220
4501 00:56:59.449472 RX Vref 0 -> 0, step: 1
4502 00:56:59.449900
4503 00:56:59.452645 RX Delay -230 -> 252, step: 16
4504 00:56:59.455885 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4505 00:56:59.459222 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4506 00:56:59.466006 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4507 00:56:59.469647 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4508 00:56:59.472419 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4509 00:56:59.475816 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4510 00:56:59.482505 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4511 00:56:59.486004 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4512 00:56:59.489111 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4513 00:56:59.492215 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4514 00:56:59.498818 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4515 00:56:59.502723 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4516 00:56:59.505664 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4517 00:56:59.509132 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4518 00:56:59.515503 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4519 00:56:59.518705 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4520 00:56:59.519292 ==
4521 00:56:59.522472 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 00:56:59.525503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 00:56:59.526100 ==
4524 00:56:59.526692 DQS Delay:
4525 00:56:59.528886 DQS0 = 0, DQS1 = 0
4526 00:56:59.529343 DQM Delay:
4527 00:56:59.532046 DQM0 = 49, DQM1 = 45
4528 00:56:59.532498 DQ Delay:
4529 00:56:59.535380 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4530 00:56:59.538624 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4531 00:56:59.542267 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4532 00:56:59.545390 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4533 00:56:59.545857
4534 00:56:59.546305
4535 00:56:59.546655 ==
4536 00:56:59.548650 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 00:56:59.552134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 00:56:59.555200 ==
4539 00:56:59.555586
4540 00:56:59.555920
4541 00:56:59.556249 TX Vref Scan disable
4542 00:56:59.558539 == TX Byte 0 ==
4543 00:56:59.561744 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 00:56:59.565458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 00:56:59.568668 == TX Byte 1 ==
4546 00:56:59.572073 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4547 00:56:59.575180 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4548 00:56:59.578850 ==
4549 00:56:59.581785 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 00:56:59.585574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 00:56:59.586048 ==
4552 00:56:59.586409
4553 00:56:59.586732
4554 00:56:59.588649 TX Vref Scan disable
4555 00:56:59.589090 == TX Byte 0 ==
4556 00:56:59.595408 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4557 00:56:59.598541 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4558 00:56:59.598986 == TX Byte 1 ==
4559 00:56:59.605246 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4560 00:56:59.608673 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4561 00:56:59.609238
4562 00:56:59.609597 [DATLAT]
4563 00:56:59.612168 Freq=600, CH1 RK0
4564 00:56:59.612619
4565 00:56:59.612971 DATLAT Default: 0x9
4566 00:56:59.615284 0, 0xFFFF, sum = 0
4567 00:56:59.615731 1, 0xFFFF, sum = 0
4568 00:56:59.619225 2, 0xFFFF, sum = 0
4569 00:56:59.619728 3, 0xFFFF, sum = 0
4570 00:56:59.622035 4, 0xFFFF, sum = 0
4571 00:56:59.622642 5, 0xFFFF, sum = 0
4572 00:56:59.625371 6, 0xFFFF, sum = 0
4573 00:56:59.625814 7, 0xFFFF, sum = 0
4574 00:56:59.628845 8, 0x0, sum = 1
4575 00:56:59.629371 9, 0x0, sum = 2
4576 00:56:59.632182 10, 0x0, sum = 3
4577 00:56:59.632609 11, 0x0, sum = 4
4578 00:56:59.635202 best_step = 9
4579 00:56:59.635623
4580 00:56:59.635950 ==
4581 00:56:59.638508 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 00:56:59.642327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 00:56:59.642750 ==
4584 00:56:59.645494 RX Vref Scan: 1
4585 00:56:59.645912
4586 00:56:59.646286 RX Vref 0 -> 0, step: 1
4587 00:56:59.646598
4588 00:56:59.648921 RX Delay -179 -> 252, step: 8
4589 00:56:59.649447
4590 00:56:59.652132 Set Vref, RX VrefLevel [Byte0]: 51
4591 00:56:59.655352 [Byte1]: 51
4592 00:56:59.659035
4593 00:56:59.659542 Final RX Vref Byte 0 = 51 to rank0
4594 00:56:59.662173 Final RX Vref Byte 1 = 51 to rank0
4595 00:56:59.665512 Final RX Vref Byte 0 = 51 to rank1
4596 00:56:59.668959 Final RX Vref Byte 1 = 51 to rank1==
4597 00:56:59.672547 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 00:56:59.678791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 00:56:59.679235 ==
4600 00:56:59.679609 DQS Delay:
4601 00:56:59.679968 DQS0 = 0, DQS1 = 0
4602 00:56:59.682406 DQM Delay:
4603 00:56:59.682846 DQM0 = 48, DQM1 = 39
4604 00:56:59.685621 DQ Delay:
4605 00:56:59.689256 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4606 00:56:59.689812 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4607 00:56:59.692595 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4608 00:56:59.698584 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4609 00:56:59.699029
4610 00:56:59.699436
4611 00:56:59.705802 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4612 00:56:59.708899 CH1 RK0: MR19=808, MR18=4A70
4613 00:56:59.715765 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4614 00:56:59.716287
4615 00:56:59.718535 ----->DramcWriteLeveling(PI) begin...
4616 00:56:59.719117 ==
4617 00:56:59.722202 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 00:56:59.725484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 00:56:59.725961 ==
4620 00:56:59.729246 Write leveling (Byte 0): 31 => 31
4621 00:56:59.732152 Write leveling (Byte 1): 29 => 29
4622 00:56:59.735239 DramcWriteLeveling(PI) end<-----
4623 00:56:59.735692
4624 00:56:59.736043 ==
4625 00:56:59.738479 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 00:56:59.742063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 00:56:59.742611 ==
4628 00:56:59.745307 [Gating] SW mode calibration
4629 00:56:59.752012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4630 00:56:59.758976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4631 00:56:59.761979 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 00:56:59.765465 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 00:56:59.771938 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4634 00:56:59.775076 0 9 12 | B1->B0 | 2828 3232 | 0 1 | (0 0) (0 1)
4635 00:56:59.778393 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 00:56:59.785328 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 00:56:59.788470 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 00:56:59.791632 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 00:56:59.798497 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 00:56:59.801540 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 00:56:59.805010 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
4642 00:56:59.811595 0 10 12 | B1->B0 | 3f3f 2f2f | 0 0 | (0 0) (0 0)
4643 00:56:59.815273 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 00:56:59.818519 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 00:56:59.824916 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 00:56:59.828222 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 00:56:59.832013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 00:56:59.838524 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 00:56:59.841840 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 00:56:59.845229 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 00:56:59.851678 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 00:56:59.854961 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 00:56:59.858326 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 00:56:59.864922 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 00:56:59.868674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 00:56:59.871707 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 00:56:59.878357 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 00:56:59.882056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 00:56:59.885242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 00:56:59.888661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 00:56:59.895086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 00:56:59.898494 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 00:56:59.901674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 00:56:59.908716 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 00:56:59.911681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 00:56:59.915189 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4667 00:56:59.918507 Total UI for P1: 0, mck2ui 16
4668 00:56:59.921640 best dqsien dly found for B0: ( 0, 13, 10)
4669 00:56:59.928389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 00:56:59.928889 Total UI for P1: 0, mck2ui 16
4671 00:56:59.935034 best dqsien dly found for B1: ( 0, 13, 12)
4672 00:56:59.938525 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4673 00:56:59.941625 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4674 00:56:59.942261
4675 00:56:59.944858 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4676 00:56:59.948605 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4677 00:56:59.951588 [Gating] SW calibration Done
4678 00:56:59.952017 ==
4679 00:56:59.954761 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 00:56:59.958185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 00:56:59.958616 ==
4682 00:56:59.961603 RX Vref Scan: 0
4683 00:56:59.962169
4684 00:56:59.962507 RX Vref 0 -> 0, step: 1
4685 00:56:59.962934
4686 00:56:59.964852 RX Delay -230 -> 252, step: 16
4687 00:56:59.971460 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4688 00:56:59.974748 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4689 00:56:59.977910 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4690 00:56:59.981319 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4691 00:56:59.984795 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4692 00:56:59.991014 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4693 00:56:59.994516 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4694 00:56:59.998076 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4695 00:57:00.001262 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4696 00:57:00.007775 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4697 00:57:00.010920 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4698 00:57:00.014411 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4699 00:57:00.018170 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4700 00:57:00.024293 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4701 00:57:00.027696 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4702 00:57:00.031257 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4703 00:57:00.031679 ==
4704 00:57:00.034561 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 00:57:00.038052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 00:57:00.038476 ==
4707 00:57:00.040743 DQS Delay:
4708 00:57:00.041161 DQS0 = 0, DQS1 = 0
4709 00:57:00.044159 DQM Delay:
4710 00:57:00.044578 DQM0 = 52, DQM1 = 47
4711 00:57:00.044914 DQ Delay:
4712 00:57:00.047515 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4713 00:57:00.050828 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4714 00:57:00.054317 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4715 00:57:00.057667 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4716 00:57:00.058135
4717 00:57:00.058475
4718 00:57:00.058780 ==
4719 00:57:00.060783 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 00:57:00.067507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 00:57:00.067934 ==
4722 00:57:00.068270
4723 00:57:00.068579
4724 00:57:00.068918 TX Vref Scan disable
4725 00:57:00.071376 == TX Byte 0 ==
4726 00:57:00.074706 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4727 00:57:00.081616 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4728 00:57:00.082150 == TX Byte 1 ==
4729 00:57:00.085004 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4730 00:57:00.091502 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4731 00:57:00.091930 ==
4732 00:57:00.094793 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 00:57:00.098139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 00:57:00.098564 ==
4735 00:57:00.098896
4736 00:57:00.099204
4737 00:57:00.101188 TX Vref Scan disable
4738 00:57:00.104692 == TX Byte 0 ==
4739 00:57:00.107916 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 00:57:00.111254 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 00:57:00.114776 == TX Byte 1 ==
4742 00:57:00.118016 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4743 00:57:00.121314 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4744 00:57:00.121739
4745 00:57:00.122131 [DATLAT]
4746 00:57:00.124416 Freq=600, CH1 RK1
4747 00:57:00.124845
4748 00:57:00.125175 DATLAT Default: 0x9
4749 00:57:00.127631 0, 0xFFFF, sum = 0
4750 00:57:00.130844 1, 0xFFFF, sum = 0
4751 00:57:00.131276 2, 0xFFFF, sum = 0
4752 00:57:00.134358 3, 0xFFFF, sum = 0
4753 00:57:00.134443 4, 0xFFFF, sum = 0
4754 00:57:00.137273 5, 0xFFFF, sum = 0
4755 00:57:00.137357 6, 0xFFFF, sum = 0
4756 00:57:00.140632 7, 0xFFFF, sum = 0
4757 00:57:00.140716 8, 0x0, sum = 1
4758 00:57:00.143905 9, 0x0, sum = 2
4759 00:57:00.143990 10, 0x0, sum = 3
4760 00:57:00.144057 11, 0x0, sum = 4
4761 00:57:00.147620 best_step = 9
4762 00:57:00.147703
4763 00:57:00.147767 ==
4764 00:57:00.150656 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 00:57:00.153805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 00:57:00.153889 ==
4767 00:57:00.157297 RX Vref Scan: 0
4768 00:57:00.157380
4769 00:57:00.157461 RX Vref 0 -> 0, step: 1
4770 00:57:00.160545
4771 00:57:00.160629 RX Delay -163 -> 252, step: 8
4772 00:57:00.168007 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4773 00:57:00.171349 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4774 00:57:00.174667 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4775 00:57:00.178357 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4776 00:57:00.181542 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4777 00:57:00.188363 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4778 00:57:00.191507 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4779 00:57:00.194760 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4780 00:57:00.197977 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4781 00:57:00.201336 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4782 00:57:00.207876 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4783 00:57:00.211822 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4784 00:57:00.214779 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4785 00:57:00.218126 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4786 00:57:00.224709 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4787 00:57:00.227903 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4788 00:57:00.227990 ==
4789 00:57:00.231641 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 00:57:00.234527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 00:57:00.234612 ==
4792 00:57:00.237767 DQS Delay:
4793 00:57:00.237850 DQS0 = 0, DQS1 = 0
4794 00:57:00.237916 DQM Delay:
4795 00:57:00.241339 DQM0 = 50, DQM1 = 44
4796 00:57:00.241422 DQ Delay:
4797 00:57:00.244663 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4798 00:57:00.247801 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4799 00:57:00.251395 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4800 00:57:00.254533 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4801 00:57:00.254616
4802 00:57:00.254682
4803 00:57:00.264655 [DQSOSCAuto] RK1, (LSB)MR18= 0x541b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4804 00:57:00.264740 CH1 RK1: MR19=808, MR18=541B
4805 00:57:00.271072 CH1_RK1: MR19=0x808, MR18=0x541B, DQSOSC=393, MR23=63, INC=169, DEC=113
4806 00:57:00.274327 [RxdqsGatingPostProcess] freq 600
4807 00:57:00.281376 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 00:57:00.284349 Pre-setting of DQS Precalculation
4809 00:57:00.287668 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 00:57:00.294457 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 00:57:00.304367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 00:57:00.304452
4813 00:57:00.304518
4814 00:57:00.307650 [Calibration Summary] 1200 Mbps
4815 00:57:00.307735 CH 0, Rank 0
4816 00:57:00.310847 SW Impedance : PASS
4817 00:57:00.310931 DUTY Scan : NO K
4818 00:57:00.314185 ZQ Calibration : PASS
4819 00:57:00.317338 Jitter Meter : NO K
4820 00:57:00.317421 CBT Training : PASS
4821 00:57:00.320621 Write leveling : PASS
4822 00:57:00.320705 RX DQS gating : PASS
4823 00:57:00.323952 RX DQ/DQS(RDDQC) : PASS
4824 00:57:00.327527 TX DQ/DQS : PASS
4825 00:57:00.327611 RX DATLAT : PASS
4826 00:57:00.330667 RX DQ/DQS(Engine): PASS
4827 00:57:00.333919 TX OE : NO K
4828 00:57:00.334013 All Pass.
4829 00:57:00.334080
4830 00:57:00.334142 CH 0, Rank 1
4831 00:57:00.337419 SW Impedance : PASS
4832 00:57:00.340604 DUTY Scan : NO K
4833 00:57:00.340687 ZQ Calibration : PASS
4834 00:57:00.343789 Jitter Meter : NO K
4835 00:57:00.347015 CBT Training : PASS
4836 00:57:00.347099 Write leveling : PASS
4837 00:57:00.350632 RX DQS gating : PASS
4838 00:57:00.353733 RX DQ/DQS(RDDQC) : PASS
4839 00:57:00.353817 TX DQ/DQS : PASS
4840 00:57:00.357418 RX DATLAT : PASS
4841 00:57:00.360586 RX DQ/DQS(Engine): PASS
4842 00:57:00.360669 TX OE : NO K
4843 00:57:00.364036 All Pass.
4844 00:57:00.364119
4845 00:57:00.364185 CH 1, Rank 0
4846 00:57:00.366846 SW Impedance : PASS
4847 00:57:00.366931 DUTY Scan : NO K
4848 00:57:00.370070 ZQ Calibration : PASS
4849 00:57:00.373576 Jitter Meter : NO K
4850 00:57:00.373660 CBT Training : PASS
4851 00:57:00.376713 Write leveling : PASS
4852 00:57:00.380003 RX DQS gating : PASS
4853 00:57:00.380087 RX DQ/DQS(RDDQC) : PASS
4854 00:57:00.383473 TX DQ/DQS : PASS
4855 00:57:00.386872 RX DATLAT : PASS
4856 00:57:00.386956 RX DQ/DQS(Engine): PASS
4857 00:57:00.389906 TX OE : NO K
4858 00:57:00.390033 All Pass.
4859 00:57:00.390100
4860 00:57:00.393159 CH 1, Rank 1
4861 00:57:00.393242 SW Impedance : PASS
4862 00:57:00.396636 DUTY Scan : NO K
4863 00:57:00.396720 ZQ Calibration : PASS
4864 00:57:00.400289 Jitter Meter : NO K
4865 00:57:00.403291 CBT Training : PASS
4866 00:57:00.403375 Write leveling : PASS
4867 00:57:00.406531 RX DQS gating : PASS
4868 00:57:00.410122 RX DQ/DQS(RDDQC) : PASS
4869 00:57:00.410206 TX DQ/DQS : PASS
4870 00:57:00.413652 RX DATLAT : PASS
4871 00:57:00.416671 RX DQ/DQS(Engine): PASS
4872 00:57:00.416755 TX OE : NO K
4873 00:57:00.419914 All Pass.
4874 00:57:00.419997
4875 00:57:00.420063 DramC Write-DBI off
4876 00:57:00.423423 PER_BANK_REFRESH: Hybrid Mode
4877 00:57:00.423508 TX_TRACKING: ON
4878 00:57:00.433136 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 00:57:00.436557 [FAST_K] Save calibration result to emmc
4880 00:57:00.440186 dramc_set_vcore_voltage set vcore to 662500
4881 00:57:00.443463 Read voltage for 933, 3
4882 00:57:00.443546 Vio18 = 0
4883 00:57:00.446642 Vcore = 662500
4884 00:57:00.446726 Vdram = 0
4885 00:57:00.446791 Vddq = 0
4886 00:57:00.446853 Vmddr = 0
4887 00:57:00.453268 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 00:57:00.459993 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 00:57:00.460077 MEM_TYPE=3, freq_sel=17
4890 00:57:00.462962 sv_algorithm_assistance_LP4_1600
4891 00:57:00.466575 ============ PULL DRAM RESETB DOWN ============
4892 00:57:00.473217 ========== PULL DRAM RESETB DOWN end =========
4893 00:57:00.476316 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 00:57:00.479785 ===================================
4895 00:57:00.483276 LPDDR4 DRAM CONFIGURATION
4896 00:57:00.486267 ===================================
4897 00:57:00.486351 EX_ROW_EN[0] = 0x0
4898 00:57:00.489825 EX_ROW_EN[1] = 0x0
4899 00:57:00.492955 LP4Y_EN = 0x0
4900 00:57:00.493038 WORK_FSP = 0x0
4901 00:57:00.496393 WL = 0x3
4902 00:57:00.496477 RL = 0x3
4903 00:57:00.499406 BL = 0x2
4904 00:57:00.499489 RPST = 0x0
4905 00:57:00.502959 RD_PRE = 0x0
4906 00:57:00.503043 WR_PRE = 0x1
4907 00:57:00.506050 WR_PST = 0x0
4908 00:57:00.506133 DBI_WR = 0x0
4909 00:57:00.509378 DBI_RD = 0x0
4910 00:57:00.509462 OTF = 0x1
4911 00:57:00.512681 ===================================
4912 00:57:00.516117 ===================================
4913 00:57:00.519453 ANA top config
4914 00:57:00.522784 ===================================
4915 00:57:00.522895 DLL_ASYNC_EN = 0
4916 00:57:00.525991 ALL_SLAVE_EN = 1
4917 00:57:00.529439 NEW_RANK_MODE = 1
4918 00:57:00.532620 DLL_IDLE_MODE = 1
4919 00:57:00.536079 LP45_APHY_COMB_EN = 1
4920 00:57:00.536188 TX_ODT_DIS = 1
4921 00:57:00.539386 NEW_8X_MODE = 1
4922 00:57:00.542685 ===================================
4923 00:57:00.545852 ===================================
4924 00:57:00.549467 data_rate = 1866
4925 00:57:00.552518 CKR = 1
4926 00:57:00.556157 DQ_P2S_RATIO = 8
4927 00:57:00.559482 ===================================
4928 00:57:00.559567 CA_P2S_RATIO = 8
4929 00:57:00.562707 DQ_CA_OPEN = 0
4930 00:57:00.565932 DQ_SEMI_OPEN = 0
4931 00:57:00.569300 CA_SEMI_OPEN = 0
4932 00:57:00.572653 CA_FULL_RATE = 0
4933 00:57:00.576015 DQ_CKDIV4_EN = 1
4934 00:57:00.576125 CA_CKDIV4_EN = 1
4935 00:57:00.579041 CA_PREDIV_EN = 0
4936 00:57:00.582364 PH8_DLY = 0
4937 00:57:00.585909 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 00:57:00.589572 DQ_AAMCK_DIV = 4
4939 00:57:00.592697 CA_AAMCK_DIV = 4
4940 00:57:00.592776 CA_ADMCK_DIV = 4
4941 00:57:00.595502 DQ_TRACK_CA_EN = 0
4942 00:57:00.599081 CA_PICK = 933
4943 00:57:00.602496 CA_MCKIO = 933
4944 00:57:00.605874 MCKIO_SEMI = 0
4945 00:57:00.609360 PLL_FREQ = 3732
4946 00:57:00.612268 DQ_UI_PI_RATIO = 32
4947 00:57:00.612345 CA_UI_PI_RATIO = 0
4948 00:57:00.615646 ===================================
4949 00:57:00.619094 ===================================
4950 00:57:00.622098 memory_type:LPDDR4
4951 00:57:00.625681 GP_NUM : 10
4952 00:57:00.625755 SRAM_EN : 1
4953 00:57:00.629039 MD32_EN : 0
4954 00:57:00.632352 ===================================
4955 00:57:00.635605 [ANA_INIT] >>>>>>>>>>>>>>
4956 00:57:00.638966 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 00:57:00.642241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 00:57:00.645404 ===================================
4959 00:57:00.645481 data_rate = 1866,PCW = 0X8f00
4960 00:57:00.648701 ===================================
4961 00:57:00.651895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 00:57:00.658589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 00:57:00.665245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 00:57:00.668872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 00:57:00.672114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 00:57:00.675418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 00:57:00.678469 [ANA_INIT] flow start
4968 00:57:00.682424 [ANA_INIT] PLL >>>>>>>>
4969 00:57:00.682533 [ANA_INIT] PLL <<<<<<<<
4970 00:57:00.685218 [ANA_INIT] MIDPI >>>>>>>>
4971 00:57:00.688631 [ANA_INIT] MIDPI <<<<<<<<
4972 00:57:00.688699 [ANA_INIT] DLL >>>>>>>>
4973 00:57:00.692256 [ANA_INIT] flow end
4974 00:57:00.695301 ============ LP4 DIFF to SE enter ============
4975 00:57:00.698479 ============ LP4 DIFF to SE exit ============
4976 00:57:00.702024 [ANA_INIT] <<<<<<<<<<<<<
4977 00:57:00.705213 [Flow] Enable top DCM control >>>>>
4978 00:57:00.708595 [Flow] Enable top DCM control <<<<<
4979 00:57:00.711838 Enable DLL master slave shuffle
4980 00:57:00.718415 ==============================================================
4981 00:57:00.718493 Gating Mode config
4982 00:57:00.724889 ==============================================================
4983 00:57:00.724971 Config description:
4984 00:57:00.735051 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 00:57:00.741468 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 00:57:00.748344 SELPH_MODE 0: By rank 1: By Phase
4987 00:57:00.751703 ==============================================================
4988 00:57:00.754765 GAT_TRACK_EN = 1
4989 00:57:00.758502 RX_GATING_MODE = 2
4990 00:57:00.761793 RX_GATING_TRACK_MODE = 2
4991 00:57:00.764727 SELPH_MODE = 1
4992 00:57:00.768210 PICG_EARLY_EN = 1
4993 00:57:00.771543 VALID_LAT_VALUE = 1
4994 00:57:00.778065 ==============================================================
4995 00:57:00.781598 Enter into Gating configuration >>>>
4996 00:57:00.784983 Exit from Gating configuration <<<<
4997 00:57:00.785059 Enter into DVFS_PRE_config >>>>>
4998 00:57:00.798133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 00:57:00.801533 Exit from DVFS_PRE_config <<<<<
5000 00:57:00.805113 Enter into PICG configuration >>>>
5001 00:57:00.808090 Exit from PICG configuration <<<<
5002 00:57:00.808162 [RX_INPUT] configuration >>>>>
5003 00:57:00.811690 [RX_INPUT] configuration <<<<<
5004 00:57:00.818150 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 00:57:00.821365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 00:57:00.828124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 00:57:00.834687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 00:57:00.841214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 00:57:00.847928 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 00:57:00.851345 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 00:57:00.854529 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 00:57:00.861239 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 00:57:00.864749 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 00:57:00.867930 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 00:57:00.871423 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 00:57:00.874505 ===================================
5017 00:57:00.877883 LPDDR4 DRAM CONFIGURATION
5018 00:57:00.881290 ===================================
5019 00:57:00.884681 EX_ROW_EN[0] = 0x0
5020 00:57:00.884754 EX_ROW_EN[1] = 0x0
5021 00:57:00.887809 LP4Y_EN = 0x0
5022 00:57:00.887879 WORK_FSP = 0x0
5023 00:57:00.891250 WL = 0x3
5024 00:57:00.891322 RL = 0x3
5025 00:57:00.894690 BL = 0x2
5026 00:57:00.894760 RPST = 0x0
5027 00:57:00.897854 RD_PRE = 0x0
5028 00:57:00.897957 WR_PRE = 0x1
5029 00:57:00.901260 WR_PST = 0x0
5030 00:57:00.901328 DBI_WR = 0x0
5031 00:57:00.904634 DBI_RD = 0x0
5032 00:57:00.907565 OTF = 0x1
5033 00:57:00.911203 ===================================
5034 00:57:00.914267 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 00:57:00.917691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 00:57:00.921303 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 00:57:00.924139 ===================================
5038 00:57:00.927678 LPDDR4 DRAM CONFIGURATION
5039 00:57:00.930909 ===================================
5040 00:57:00.934203 EX_ROW_EN[0] = 0x10
5041 00:57:00.934279 EX_ROW_EN[1] = 0x0
5042 00:57:00.937395 LP4Y_EN = 0x0
5043 00:57:00.937486 WORK_FSP = 0x0
5044 00:57:00.941272 WL = 0x3
5045 00:57:00.941347 RL = 0x3
5046 00:57:00.944400 BL = 0x2
5047 00:57:00.944471 RPST = 0x0
5048 00:57:00.947775 RD_PRE = 0x0
5049 00:57:00.947847 WR_PRE = 0x1
5050 00:57:00.951016 WR_PST = 0x0
5051 00:57:00.951091 DBI_WR = 0x0
5052 00:57:00.954485 DBI_RD = 0x0
5053 00:57:00.954563 OTF = 0x1
5054 00:57:00.957844 ===================================
5055 00:57:00.964290 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 00:57:00.969034 nWR fixed to 30
5057 00:57:00.972514 [ModeRegInit_LP4] CH0 RK0
5058 00:57:00.972584 [ModeRegInit_LP4] CH0 RK1
5059 00:57:00.975571 [ModeRegInit_LP4] CH1 RK0
5060 00:57:00.978866 [ModeRegInit_LP4] CH1 RK1
5061 00:57:00.978936 match AC timing 9
5062 00:57:00.985837 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 00:57:00.989070 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 00:57:00.992255 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 00:57:00.999041 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 00:57:01.002235 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 00:57:01.002305 ==
5068 00:57:01.005370 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 00:57:01.008896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 00:57:01.008965 ==
5071 00:57:01.015349 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 00:57:01.022344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 00:57:01.025824 [CA 0] Center 37 (7~68) winsize 62
5074 00:57:01.029399 [CA 1] Center 38 (8~69) winsize 62
5075 00:57:01.032272 [CA 2] Center 35 (5~66) winsize 62
5076 00:57:01.035709 [CA 3] Center 34 (4~65) winsize 62
5077 00:57:01.038836 [CA 4] Center 34 (4~64) winsize 61
5078 00:57:01.042266 [CA 5] Center 33 (3~64) winsize 62
5079 00:57:01.042336
5080 00:57:01.045508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 00:57:01.045578
5082 00:57:01.048633 [CATrainingPosCal] consider 1 rank data
5083 00:57:01.052311 u2DelayCellTimex100 = 270/100 ps
5084 00:57:01.055532 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5085 00:57:01.059226 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5086 00:57:01.062260 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5087 00:57:01.065323 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5088 00:57:01.068718 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5089 00:57:01.072223 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5090 00:57:01.072295
5091 00:57:01.078844 CA PerBit enable=1, Macro0, CA PI delay=33
5092 00:57:01.078923
5093 00:57:01.081974 [CBTSetCACLKResult] CA Dly = 33
5094 00:57:01.082042 CS Dly: 7 (0~38)
5095 00:57:01.082106 ==
5096 00:57:01.085458 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 00:57:01.088515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 00:57:01.088582 ==
5099 00:57:01.095570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 00:57:01.101870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5101 00:57:01.105674 [CA 0] Center 38 (7~69) winsize 63
5102 00:57:01.108521 [CA 1] Center 38 (8~69) winsize 62
5103 00:57:01.112018 [CA 2] Center 36 (6~66) winsize 61
5104 00:57:01.115388 [CA 3] Center 35 (5~66) winsize 62
5105 00:57:01.118716 [CA 4] Center 34 (4~65) winsize 62
5106 00:57:01.121836 [CA 5] Center 34 (4~65) winsize 62
5107 00:57:01.121911
5108 00:57:01.125458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5109 00:57:01.125531
5110 00:57:01.128460 [CATrainingPosCal] consider 2 rank data
5111 00:57:01.131915 u2DelayCellTimex100 = 270/100 ps
5112 00:57:01.135140 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5113 00:57:01.138676 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5114 00:57:01.141915 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5115 00:57:01.145133 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5116 00:57:01.148367 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5117 00:57:01.155317 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5118 00:57:01.155395
5119 00:57:01.158620 CA PerBit enable=1, Macro0, CA PI delay=34
5120 00:57:01.158696
5121 00:57:01.161749 [CBTSetCACLKResult] CA Dly = 34
5122 00:57:01.161821 CS Dly: 7 (0~39)
5123 00:57:01.161882
5124 00:57:01.165112 ----->DramcWriteLeveling(PI) begin...
5125 00:57:01.165195 ==
5126 00:57:01.168629 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 00:57:01.175045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 00:57:01.175121 ==
5129 00:57:01.178327 Write leveling (Byte 0): 34 => 34
5130 00:57:01.178402 Write leveling (Byte 1): 29 => 29
5131 00:57:01.181674 DramcWriteLeveling(PI) end<-----
5132 00:57:01.181745
5133 00:57:01.181806 ==
5134 00:57:01.184864 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 00:57:01.192001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 00:57:01.192079 ==
5137 00:57:01.195227 [Gating] SW mode calibration
5138 00:57:01.201649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 00:57:01.204794 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 00:57:01.211642 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5141 00:57:01.214705 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 00:57:01.218016 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 00:57:01.225355 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 00:57:01.228540 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 00:57:01.231453 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 00:57:01.235108 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5147 00:57:01.241469 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
5148 00:57:01.245150 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
5149 00:57:01.248258 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 00:57:01.254698 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 00:57:01.258100 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 00:57:01.261444 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 00:57:01.268440 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 00:57:01.271294 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5155 00:57:01.275077 0 15 28 | B1->B0 | 2f2f 4646 | 0 0 | (1 1) (0 0)
5156 00:57:01.281511 1 0 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5157 00:57:01.284953 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 00:57:01.288192 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:57:01.294762 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 00:57:01.298376 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 00:57:01.301311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 00:57:01.308185 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5163 00:57:01.311897 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5164 00:57:01.314626 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 00:57:01.321352 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 00:57:01.324823 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 00:57:01.328138 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 00:57:01.334968 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 00:57:01.338294 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 00:57:01.341339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 00:57:01.344967 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 00:57:01.351399 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 00:57:01.355044 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 00:57:01.358165 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:57:01.365041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:57:01.367840 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:57:01.371303 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:57:01.377845 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5179 00:57:01.381298 Total UI for P1: 0, mck2ui 16
5180 00:57:01.384491 best dqsien dly found for B0: ( 1, 2, 22)
5181 00:57:01.388052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5182 00:57:01.391226 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5183 00:57:01.397727 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 00:57:01.397806 Total UI for P1: 0, mck2ui 16
5185 00:57:01.404280 best dqsien dly found for B1: ( 1, 2, 28)
5186 00:57:01.407617 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5187 00:57:01.411059 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5188 00:57:01.411136
5189 00:57:01.414178 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5190 00:57:01.417817 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5191 00:57:01.421070 [Gating] SW calibration Done
5192 00:57:01.421146 ==
5193 00:57:01.424701 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 00:57:01.427679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 00:57:01.427753 ==
5196 00:57:01.431021 RX Vref Scan: 0
5197 00:57:01.431097
5198 00:57:01.431158 RX Vref 0 -> 0, step: 1
5199 00:57:01.431216
5200 00:57:01.434524 RX Delay -80 -> 252, step: 8
5201 00:57:01.440848 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5202 00:57:01.444277 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5203 00:57:01.447915 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5204 00:57:01.451171 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5205 00:57:01.454537 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5206 00:57:01.457835 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5207 00:57:01.464143 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5208 00:57:01.467540 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5209 00:57:01.470803 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5210 00:57:01.474179 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5211 00:57:01.477811 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5212 00:57:01.480710 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5213 00:57:01.487595 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5214 00:57:01.490787 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5215 00:57:01.494265 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5216 00:57:01.497270 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5217 00:57:01.497344 ==
5218 00:57:01.500502 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 00:57:01.504067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 00:57:01.504148 ==
5221 00:57:01.507228 DQS Delay:
5222 00:57:01.507300 DQS0 = 0, DQS1 = 0
5223 00:57:01.510900 DQM Delay:
5224 00:57:01.510972 DQM0 = 106, DQM1 = 90
5225 00:57:01.513994 DQ Delay:
5226 00:57:01.514066 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5227 00:57:01.520535 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5228 00:57:01.520616 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5229 00:57:01.527232 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5230 00:57:01.527310
5231 00:57:01.527379
5232 00:57:01.527440 ==
5233 00:57:01.530765 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 00:57:01.533973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 00:57:01.534066 ==
5236 00:57:01.534128
5237 00:57:01.534186
5238 00:57:01.537022 TX Vref Scan disable
5239 00:57:01.537093 == TX Byte 0 ==
5240 00:57:01.544117 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5241 00:57:01.547218 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5242 00:57:01.547292 == TX Byte 1 ==
5243 00:57:01.553832 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5244 00:57:01.557236 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5245 00:57:01.557317 ==
5246 00:57:01.560307 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 00:57:01.564094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 00:57:01.564166 ==
5249 00:57:01.564227
5250 00:57:01.564285
5251 00:57:01.567345 TX Vref Scan disable
5252 00:57:01.570435 == TX Byte 0 ==
5253 00:57:01.573639 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5254 00:57:01.577214 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5255 00:57:01.580844 == TX Byte 1 ==
5256 00:57:01.583932 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5257 00:57:01.587015 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5258 00:57:01.587086
5259 00:57:01.590340 [DATLAT]
5260 00:57:01.590409 Freq=933, CH0 RK0
5261 00:57:01.590468
5262 00:57:01.593679 DATLAT Default: 0xd
5263 00:57:01.593746 0, 0xFFFF, sum = 0
5264 00:57:01.596992 1, 0xFFFF, sum = 0
5265 00:57:01.597062 2, 0xFFFF, sum = 0
5266 00:57:01.600038 3, 0xFFFF, sum = 0
5267 00:57:01.600108 4, 0xFFFF, sum = 0
5268 00:57:01.603291 5, 0xFFFF, sum = 0
5269 00:57:01.603361 6, 0xFFFF, sum = 0
5270 00:57:01.606847 7, 0xFFFF, sum = 0
5271 00:57:01.610135 8, 0xFFFF, sum = 0
5272 00:57:01.610211 9, 0xFFFF, sum = 0
5273 00:57:01.613459 10, 0x0, sum = 1
5274 00:57:01.613529 11, 0x0, sum = 2
5275 00:57:01.613590 12, 0x0, sum = 3
5276 00:57:01.616556 13, 0x0, sum = 4
5277 00:57:01.616633 best_step = 11
5278 00:57:01.616693
5279 00:57:01.616750 ==
5280 00:57:01.620228 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 00:57:01.626839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 00:57:01.626917 ==
5283 00:57:01.626980 RX Vref Scan: 1
5284 00:57:01.627041
5285 00:57:01.629914 RX Vref 0 -> 0, step: 1
5286 00:57:01.630004
5287 00:57:01.633177 RX Delay -53 -> 252, step: 4
5288 00:57:01.633246
5289 00:57:01.636511 Set Vref, RX VrefLevel [Byte0]: 61
5290 00:57:01.640138 [Byte1]: 50
5291 00:57:01.640207
5292 00:57:01.643293 Final RX Vref Byte 0 = 61 to rank0
5293 00:57:01.646635 Final RX Vref Byte 1 = 50 to rank0
5294 00:57:01.650120 Final RX Vref Byte 0 = 61 to rank1
5295 00:57:01.653289 Final RX Vref Byte 1 = 50 to rank1==
5296 00:57:01.656326 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 00:57:01.659914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 00:57:01.659986 ==
5299 00:57:01.662964 DQS Delay:
5300 00:57:01.663039 DQS0 = 0, DQS1 = 0
5301 00:57:01.666322 DQM Delay:
5302 00:57:01.666396 DQM0 = 108, DQM1 = 92
5303 00:57:01.666456 DQ Delay:
5304 00:57:01.673430 DQ0 =106, DQ1 =108, DQ2 =106, DQ3 =106
5305 00:57:01.676200 DQ4 =110, DQ5 =100, DQ6 =118, DQ7 =114
5306 00:57:01.679849 DQ8 =88, DQ9 =80, DQ10 =92, DQ11 =90
5307 00:57:01.683253 DQ12 =96, DQ13 =92, DQ14 =104, DQ15 =100
5308 00:57:01.683324
5309 00:57:01.683391
5310 00:57:01.689614 [DQSOSCAuto] RK0, (LSB)MR18= 0x2522, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5311 00:57:01.692827 CH0 RK0: MR19=505, MR18=2522
5312 00:57:01.699607 CH0_RK0: MR19=0x505, MR18=0x2522, DQSOSC=410, MR23=63, INC=64, DEC=42
5313 00:57:01.699682
5314 00:57:01.702972 ----->DramcWriteLeveling(PI) begin...
5315 00:57:01.703052 ==
5316 00:57:01.706279 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 00:57:01.709354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 00:57:01.709425 ==
5319 00:57:01.712739 Write leveling (Byte 0): 33 => 33
5320 00:57:01.716261 Write leveling (Byte 1): 31 => 31
5321 00:57:01.719275 DramcWriteLeveling(PI) end<-----
5322 00:57:01.719356
5323 00:57:01.719429 ==
5324 00:57:01.722971 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 00:57:01.726415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 00:57:01.726497 ==
5327 00:57:01.729415 [Gating] SW mode calibration
5328 00:57:01.735883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 00:57:01.742570 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 00:57:01.745771 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5331 00:57:01.752380 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 00:57:01.755991 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 00:57:01.759373 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 00:57:01.765796 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 00:57:01.768966 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 00:57:01.772603 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5337 00:57:01.779108 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5338 00:57:01.782346 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5339 00:57:01.785638 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 00:57:01.792415 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 00:57:01.795637 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 00:57:01.799291 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 00:57:01.805484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 00:57:01.808958 0 15 24 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
5345 00:57:01.812254 0 15 28 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
5346 00:57:01.815585 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 00:57:01.822308 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 00:57:01.825678 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 00:57:01.828892 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 00:57:01.835732 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 00:57:01.839309 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 00:57:01.842277 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 00:57:01.849168 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5354 00:57:01.852460 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 00:57:01.855825 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 00:57:01.862118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 00:57:01.865629 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 00:57:01.868871 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 00:57:01.875576 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 00:57:01.878728 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 00:57:01.882140 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 00:57:01.888553 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 00:57:01.891946 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 00:57:01.895544 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 00:57:01.902049 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 00:57:01.905263 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 00:57:01.908604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 00:57:01.915413 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5369 00:57:01.918541 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 00:57:01.921822 Total UI for P1: 0, mck2ui 16
5371 00:57:01.925009 best dqsien dly found for B0: ( 1, 2, 24)
5372 00:57:01.928407 Total UI for P1: 0, mck2ui 16
5373 00:57:01.931784 best dqsien dly found for B1: ( 1, 2, 26)
5374 00:57:01.935392 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5375 00:57:01.938273 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5376 00:57:01.938353
5377 00:57:01.941928 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5378 00:57:01.945161 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5379 00:57:01.948293 [Gating] SW calibration Done
5380 00:57:01.948372 ==
5381 00:57:01.951535 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 00:57:01.954791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 00:57:01.958292 ==
5384 00:57:01.958374 RX Vref Scan: 0
5385 00:57:01.958438
5386 00:57:01.961347 RX Vref 0 -> 0, step: 1
5387 00:57:01.961432
5388 00:57:01.964615 RX Delay -80 -> 252, step: 8
5389 00:57:01.968262 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5390 00:57:01.971337 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5391 00:57:01.974867 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5392 00:57:01.977935 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5393 00:57:01.981394 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5394 00:57:01.988069 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5395 00:57:01.991317 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5396 00:57:01.995066 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5397 00:57:01.998028 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5398 00:57:02.001374 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5399 00:57:02.004731 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5400 00:57:02.011461 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5401 00:57:02.014695 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5402 00:57:02.017884 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5403 00:57:02.021331 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5404 00:57:02.024469 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5405 00:57:02.024552 ==
5406 00:57:02.028042 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 00:57:02.034696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 00:57:02.034779 ==
5409 00:57:02.034844 DQS Delay:
5410 00:57:02.037826 DQS0 = 0, DQS1 = 0
5411 00:57:02.037908 DQM Delay:
5412 00:57:02.038011 DQM0 = 105, DQM1 = 91
5413 00:57:02.041347 DQ Delay:
5414 00:57:02.044532 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5415 00:57:02.047916 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5416 00:57:02.051351 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5417 00:57:02.054713 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5418 00:57:02.054812
5419 00:57:02.054908
5420 00:57:02.054984 ==
5421 00:57:02.057846 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 00:57:02.061113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 00:57:02.061212 ==
5424 00:57:02.061311
5425 00:57:02.061409
5426 00:57:02.064787 TX Vref Scan disable
5427 00:57:02.067610 == TX Byte 0 ==
5428 00:57:02.070958 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5429 00:57:02.074339 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5430 00:57:02.077800 == TX Byte 1 ==
5431 00:57:02.080882 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5432 00:57:02.084272 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5433 00:57:02.084355 ==
5434 00:57:02.087825 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 00:57:02.091111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 00:57:02.094356 ==
5437 00:57:02.094438
5438 00:57:02.094502
5439 00:57:02.094562 TX Vref Scan disable
5440 00:57:02.097869 == TX Byte 0 ==
5441 00:57:02.101331 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5442 00:57:02.104506 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5443 00:57:02.107860 == TX Byte 1 ==
5444 00:57:02.111113 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5445 00:57:02.114375 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5446 00:57:02.117748
5447 00:57:02.117830 [DATLAT]
5448 00:57:02.117895 Freq=933, CH0 RK1
5449 00:57:02.117994
5450 00:57:02.121233 DATLAT Default: 0xb
5451 00:57:02.121315 0, 0xFFFF, sum = 0
5452 00:57:02.124339 1, 0xFFFF, sum = 0
5453 00:57:02.124423 2, 0xFFFF, sum = 0
5454 00:57:02.128058 3, 0xFFFF, sum = 0
5455 00:57:02.131344 4, 0xFFFF, sum = 0
5456 00:57:02.131428 5, 0xFFFF, sum = 0
5457 00:57:02.134426 6, 0xFFFF, sum = 0
5458 00:57:02.134510 7, 0xFFFF, sum = 0
5459 00:57:02.137644 8, 0xFFFF, sum = 0
5460 00:57:02.137728 9, 0xFFFF, sum = 0
5461 00:57:02.141117 10, 0x0, sum = 1
5462 00:57:02.141200 11, 0x0, sum = 2
5463 00:57:02.141266 12, 0x0, sum = 3
5464 00:57:02.144345 13, 0x0, sum = 4
5465 00:57:02.144428 best_step = 11
5466 00:57:02.144493
5467 00:57:02.147699 ==
5468 00:57:02.147781 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 00:57:02.154563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 00:57:02.154646 ==
5471 00:57:02.154711 RX Vref Scan: 0
5472 00:57:02.154770
5473 00:57:02.157554 RX Vref 0 -> 0, step: 1
5474 00:57:02.157636
5475 00:57:02.161001 RX Delay -53 -> 252, step: 4
5476 00:57:02.164628 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5477 00:57:02.170958 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5478 00:57:02.174478 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5479 00:57:02.177856 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5480 00:57:02.181092 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5481 00:57:02.184450 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5482 00:57:02.190953 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
5483 00:57:02.194486 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5484 00:57:02.197730 iDelay=203, Bit 8, Center 86 (3 ~ 170) 168
5485 00:57:02.200857 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5486 00:57:02.204437 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5487 00:57:02.207929 iDelay=203, Bit 11, Center 90 (7 ~ 174) 168
5488 00:57:02.214244 iDelay=203, Bit 12, Center 98 (15 ~ 182) 168
5489 00:57:02.217488 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5490 00:57:02.221230 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5491 00:57:02.224358 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5492 00:57:02.224443 ==
5493 00:57:02.227646 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 00:57:02.231146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 00:57:02.233973 ==
5496 00:57:02.234069 DQS Delay:
5497 00:57:02.234134 DQS0 = 0, DQS1 = 0
5498 00:57:02.237703 DQM Delay:
5499 00:57:02.237811 DQM0 = 104, DQM1 = 92
5500 00:57:02.241226 DQ Delay:
5501 00:57:02.244172 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5502 00:57:02.247458 DQ4 =104, DQ5 =96, DQ6 =116, DQ7 =110
5503 00:57:02.251238 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5504 00:57:02.254047 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5505 00:57:02.254146
5506 00:57:02.254235
5507 00:57:02.260788 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5508 00:57:02.264318 CH0 RK1: MR19=505, MR18=2B0D
5509 00:57:02.270490 CH0_RK1: MR19=0x505, MR18=0x2B0D, DQSOSC=408, MR23=63, INC=65, DEC=43
5510 00:57:02.274142 [RxdqsGatingPostProcess] freq 933
5511 00:57:02.277716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5512 00:57:02.280621 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 00:57:02.284159 best DQS1 dly(2T, 0.5T) = (0, 10)
5514 00:57:02.287788 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 00:57:02.290733 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5516 00:57:02.293720 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 00:57:02.297355 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 00:57:02.300603 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 00:57:02.303941 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 00:57:02.307142 Pre-setting of DQS Precalculation
5521 00:57:02.310761 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5522 00:57:02.313653 ==
5523 00:57:02.317340 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 00:57:02.320602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 00:57:02.320686 ==
5526 00:57:02.323969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 00:57:02.330574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5528 00:57:02.333772 [CA 0] Center 37 (7~68) winsize 62
5529 00:57:02.337658 [CA 1] Center 37 (7~68) winsize 62
5530 00:57:02.340584 [CA 2] Center 35 (5~66) winsize 62
5531 00:57:02.344372 [CA 3] Center 35 (5~65) winsize 61
5532 00:57:02.347255 [CA 4] Center 35 (5~66) winsize 62
5533 00:57:02.350855 [CA 5] Center 34 (4~65) winsize 62
5534 00:57:02.350937
5535 00:57:02.353818 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5536 00:57:02.353950
5537 00:57:02.357192 [CATrainingPosCal] consider 1 rank data
5538 00:57:02.360675 u2DelayCellTimex100 = 270/100 ps
5539 00:57:02.364011 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5540 00:57:02.370548 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5541 00:57:02.373666 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5542 00:57:02.377229 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5543 00:57:02.380374 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5544 00:57:02.383701 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5545 00:57:02.383784
5546 00:57:02.387176 CA PerBit enable=1, Macro0, CA PI delay=34
5547 00:57:02.387260
5548 00:57:02.390508 [CBTSetCACLKResult] CA Dly = 34
5549 00:57:02.390592 CS Dly: 6 (0~37)
5550 00:57:02.393645 ==
5551 00:57:02.397158 Dram Type= 6, Freq= 0, CH_1, rank 1
5552 00:57:02.400403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 00:57:02.400486 ==
5554 00:57:02.403846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 00:57:02.410124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5556 00:57:02.414070 [CA 0] Center 37 (7~68) winsize 62
5557 00:57:02.417206 [CA 1] Center 38 (8~69) winsize 62
5558 00:57:02.420767 [CA 2] Center 36 (6~66) winsize 61
5559 00:57:02.423958 [CA 3] Center 35 (5~65) winsize 61
5560 00:57:02.427182 [CA 4] Center 36 (6~66) winsize 61
5561 00:57:02.430382 [CA 5] Center 34 (5~64) winsize 60
5562 00:57:02.430491
5563 00:57:02.434329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5564 00:57:02.434413
5565 00:57:02.437116 [CATrainingPosCal] consider 2 rank data
5566 00:57:02.440391 u2DelayCellTimex100 = 270/100 ps
5567 00:57:02.443796 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5568 00:57:02.447291 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5569 00:57:02.453774 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5570 00:57:02.457185 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5571 00:57:02.460257 CA4 delay=36 (6~66),Diff = 2 PI (12 cell)
5572 00:57:02.463631 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5573 00:57:02.463714
5574 00:57:02.467041 CA PerBit enable=1, Macro0, CA PI delay=34
5575 00:57:02.467125
5576 00:57:02.470233 [CBTSetCACLKResult] CA Dly = 34
5577 00:57:02.470316 CS Dly: 7 (0~39)
5578 00:57:02.473740
5579 00:57:02.476893 ----->DramcWriteLeveling(PI) begin...
5580 00:57:02.476977 ==
5581 00:57:02.480335 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 00:57:02.483831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 00:57:02.483916 ==
5584 00:57:02.487243 Write leveling (Byte 0): 27 => 27
5585 00:57:02.490610 Write leveling (Byte 1): 30 => 30
5586 00:57:02.493639 DramcWriteLeveling(PI) end<-----
5587 00:57:02.493723
5588 00:57:02.493789 ==
5589 00:57:02.497210 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 00:57:02.500268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 00:57:02.500352 ==
5592 00:57:02.503816 [Gating] SW mode calibration
5593 00:57:02.510593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 00:57:02.517526 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5595 00:57:02.520807 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 00:57:02.524241 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 00:57:02.527519 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 00:57:02.533737 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 00:57:02.536896 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 00:57:02.540403 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 00:57:02.547185 0 14 24 | B1->B0 | 3333 3131 | 0 0 | (0 1) (0 1)
5602 00:57:02.550589 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5603 00:57:02.553844 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 00:57:02.560499 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 00:57:02.563701 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 00:57:02.567142 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 00:57:02.573648 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 00:57:02.577051 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 00:57:02.580363 0 15 24 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
5610 00:57:02.586847 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5611 00:57:02.590094 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 00:57:02.593432 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 00:57:02.600002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:57:02.603558 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:57:02.607348 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 00:57:02.613320 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 00:57:02.616701 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 00:57:02.620166 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 00:57:02.626901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 00:57:02.630162 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 00:57:02.633710 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 00:57:02.640410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 00:57:02.643484 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 00:57:02.646885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 00:57:02.650247 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 00:57:02.657156 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:57:02.660120 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:57:02.663443 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:57:02.670333 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 00:57:02.673520 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 00:57:02.677128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 00:57:02.683505 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5633 00:57:02.686886 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5634 00:57:02.689911 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5635 00:57:02.693581 Total UI for P1: 0, mck2ui 16
5636 00:57:02.696804 best dqsien dly found for B0: ( 1, 2, 22)
5637 00:57:02.703755 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 00:57:02.703858 Total UI for P1: 0, mck2ui 16
5639 00:57:02.709846 best dqsien dly found for B1: ( 1, 2, 26)
5640 00:57:02.713120 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5641 00:57:02.716774 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5642 00:57:02.716848
5643 00:57:02.719891 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5644 00:57:02.723177 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5645 00:57:02.726684 [Gating] SW calibration Done
5646 00:57:02.726784 ==
5647 00:57:02.729833 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 00:57:02.733453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 00:57:02.733528 ==
5650 00:57:02.736934 RX Vref Scan: 0
5651 00:57:02.737002
5652 00:57:02.737063 RX Vref 0 -> 0, step: 1
5653 00:57:02.737123
5654 00:57:02.739935 RX Delay -80 -> 252, step: 8
5655 00:57:02.743370 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5656 00:57:02.749845 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5657 00:57:02.753208 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5658 00:57:02.756388 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5659 00:57:02.760137 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5660 00:57:02.763384 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5661 00:57:02.766511 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5662 00:57:02.773090 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5663 00:57:02.776321 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5664 00:57:02.779959 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5665 00:57:02.783393 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5666 00:57:02.786337 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5667 00:57:02.789890 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5668 00:57:02.796521 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5669 00:57:02.799808 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5670 00:57:02.803267 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5671 00:57:02.803369 ==
5672 00:57:02.806533 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 00:57:02.809707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 00:57:02.809781 ==
5675 00:57:02.813074 DQS Delay:
5676 00:57:02.813148 DQS0 = 0, DQS1 = 0
5677 00:57:02.816287 DQM Delay:
5678 00:57:02.816360 DQM0 = 101, DQM1 = 95
5679 00:57:02.816426 DQ Delay:
5680 00:57:02.819435 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5681 00:57:02.823186 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5682 00:57:02.826202 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5683 00:57:02.829812 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5684 00:57:02.833170
5685 00:57:02.833245
5686 00:57:02.833311 ==
5687 00:57:02.836263 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 00:57:02.839365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 00:57:02.839436 ==
5690 00:57:02.839500
5691 00:57:02.839559
5692 00:57:02.842934 TX Vref Scan disable
5693 00:57:02.843000 == TX Byte 0 ==
5694 00:57:02.849567 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 00:57:02.852663 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 00:57:02.852763 == TX Byte 1 ==
5697 00:57:02.859254 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 00:57:02.863008 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 00:57:02.863082 ==
5700 00:57:02.866059 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 00:57:02.869881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 00:57:02.870021 ==
5703 00:57:02.870113
5704 00:57:02.870200
5705 00:57:02.872676 TX Vref Scan disable
5706 00:57:02.876439 == TX Byte 0 ==
5707 00:57:02.879677 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5708 00:57:02.882805 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5709 00:57:02.886249 == TX Byte 1 ==
5710 00:57:02.889528 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 00:57:02.892863 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 00:57:02.892969
5713 00:57:02.895982 [DATLAT]
5714 00:57:02.896079 Freq=933, CH1 RK0
5715 00:57:02.896169
5716 00:57:02.899596 DATLAT Default: 0xd
5717 00:57:02.899704 0, 0xFFFF, sum = 0
5718 00:57:02.902517 1, 0xFFFF, sum = 0
5719 00:57:02.902595 2, 0xFFFF, sum = 0
5720 00:57:02.906064 3, 0xFFFF, sum = 0
5721 00:57:02.906168 4, 0xFFFF, sum = 0
5722 00:57:02.909709 5, 0xFFFF, sum = 0
5723 00:57:02.909812 6, 0xFFFF, sum = 0
5724 00:57:02.913246 7, 0xFFFF, sum = 0
5725 00:57:02.913345 8, 0xFFFF, sum = 0
5726 00:57:02.915931 9, 0xFFFF, sum = 0
5727 00:57:02.916006 10, 0x0, sum = 1
5728 00:57:02.919494 11, 0x0, sum = 2
5729 00:57:02.919572 12, 0x0, sum = 3
5730 00:57:02.922862 13, 0x0, sum = 4
5731 00:57:02.922933 best_step = 11
5732 00:57:02.922996
5733 00:57:02.923055 ==
5734 00:57:02.926054 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 00:57:02.929594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 00:57:02.932604 ==
5737 00:57:02.932705 RX Vref Scan: 1
5738 00:57:02.932797
5739 00:57:02.936231 RX Vref 0 -> 0, step: 1
5740 00:57:02.936332
5741 00:57:02.939035 RX Delay -53 -> 252, step: 4
5742 00:57:02.939134
5743 00:57:02.942873 Set Vref, RX VrefLevel [Byte0]: 51
5744 00:57:02.946083 [Byte1]: 51
5745 00:57:02.946165
5746 00:57:02.949352 Final RX Vref Byte 0 = 51 to rank0
5747 00:57:02.952692 Final RX Vref Byte 1 = 51 to rank0
5748 00:57:02.956010 Final RX Vref Byte 0 = 51 to rank1
5749 00:57:02.959127 Final RX Vref Byte 1 = 51 to rank1==
5750 00:57:02.962672 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 00:57:02.966135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 00:57:02.966210 ==
5753 00:57:02.969334 DQS Delay:
5754 00:57:02.969436 DQS0 = 0, DQS1 = 0
5755 00:57:02.969529 DQM Delay:
5756 00:57:02.972599 DQM0 = 104, DQM1 = 97
5757 00:57:02.972696 DQ Delay:
5758 00:57:02.975730 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5759 00:57:02.979125 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =100
5760 00:57:02.982265 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =90
5761 00:57:02.985653 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5762 00:57:02.989124
5763 00:57:02.989195
5764 00:57:02.995618 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5765 00:57:02.998727 CH1 RK0: MR19=505, MR18=1B33
5766 00:57:03.005549 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5767 00:57:03.005662
5768 00:57:03.008759 ----->DramcWriteLeveling(PI) begin...
5769 00:57:03.008873 ==
5770 00:57:03.012218 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 00:57:03.015453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 00:57:03.015561 ==
5773 00:57:03.019030 Write leveling (Byte 0): 27 => 27
5774 00:57:03.021902 Write leveling (Byte 1): 27 => 27
5775 00:57:03.025485 DramcWriteLeveling(PI) end<-----
5776 00:57:03.025559
5777 00:57:03.025627 ==
5778 00:57:03.028908 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 00:57:03.032028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 00:57:03.032133 ==
5781 00:57:03.035626 [Gating] SW mode calibration
5782 00:57:03.042052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5783 00:57:03.048787 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5784 00:57:03.052117 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 00:57:03.055262 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 00:57:03.062186 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 00:57:03.065457 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 00:57:03.068651 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 00:57:03.075292 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 00:57:03.078271 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 1)
5791 00:57:03.081916 0 14 28 | B1->B0 | 2525 2b2b | 0 1 | (1 0) (1 0)
5792 00:57:03.088379 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5793 00:57:03.091518 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 00:57:03.094685 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 00:57:03.101830 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 00:57:03.104593 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 00:57:03.108028 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 00:57:03.114972 0 15 24 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
5799 00:57:03.118119 0 15 28 | B1->B0 | 4242 3434 | 0 1 | (0 0) (0 0)
5800 00:57:03.121412 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 00:57:03.128023 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 00:57:03.131247 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 00:57:03.134810 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 00:57:03.141240 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 00:57:03.144431 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 00:57:03.147616 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5807 00:57:03.154119 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5808 00:57:03.157800 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5809 00:57:03.161108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 00:57:03.167838 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 00:57:03.170693 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 00:57:03.174263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 00:57:03.180925 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 00:57:03.184189 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 00:57:03.187242 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 00:57:03.194166 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 00:57:03.197409 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 00:57:03.200615 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 00:57:03.207582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 00:57:03.210645 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 00:57:03.213909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 00:57:03.220790 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5823 00:57:03.223699 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5824 00:57:03.227273 Total UI for P1: 0, mck2ui 16
5825 00:57:03.230700 best dqsien dly found for B1: ( 1, 2, 24)
5826 00:57:03.233974 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 00:57:03.237118 Total UI for P1: 0, mck2ui 16
5828 00:57:03.240773 best dqsien dly found for B0: ( 1, 2, 26)
5829 00:57:03.243859 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5830 00:57:03.247395 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5831 00:57:03.247497
5832 00:57:03.250432 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5833 00:57:03.257283 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 00:57:03.257400 [Gating] SW calibration Done
5835 00:57:03.257494 ==
5836 00:57:03.260704 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 00:57:03.267201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 00:57:03.267284 ==
5839 00:57:03.267349 RX Vref Scan: 0
5840 00:57:03.267409
5841 00:57:03.270546 RX Vref 0 -> 0, step: 1
5842 00:57:03.270629
5843 00:57:03.274108 RX Delay -80 -> 252, step: 8
5844 00:57:03.277152 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5845 00:57:03.280414 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5846 00:57:03.283691 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5847 00:57:03.290530 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5848 00:57:03.293695 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5849 00:57:03.297060 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5850 00:57:03.300354 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5851 00:57:03.303692 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5852 00:57:03.307157 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5853 00:57:03.313658 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5854 00:57:03.316963 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5855 00:57:03.320627 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5856 00:57:03.323665 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5857 00:57:03.327125 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5858 00:57:03.333747 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5859 00:57:03.337379 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5860 00:57:03.337462 ==
5861 00:57:03.340610 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 00:57:03.344016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 00:57:03.344100 ==
5864 00:57:03.344165 DQS Delay:
5865 00:57:03.346913 DQS0 = 0, DQS1 = 0
5866 00:57:03.346995 DQM Delay:
5867 00:57:03.350470 DQM0 = 103, DQM1 = 95
5868 00:57:03.350553 DQ Delay:
5869 00:57:03.353736 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =103
5870 00:57:03.356816 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103
5871 00:57:03.360483 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =91
5872 00:57:03.363545 DQ12 =107, DQ13 =99, DQ14 =99, DQ15 =107
5873 00:57:03.363632
5874 00:57:03.363717
5875 00:57:03.363796 ==
5876 00:57:03.367249 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 00:57:03.373449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 00:57:03.373536 ==
5879 00:57:03.373621
5880 00:57:03.373721
5881 00:57:03.373819 TX Vref Scan disable
5882 00:57:03.377172 == TX Byte 0 ==
5883 00:57:03.380706 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5884 00:57:03.387145 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5885 00:57:03.387232 == TX Byte 1 ==
5886 00:57:03.390458 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5887 00:57:03.397269 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5888 00:57:03.397355 ==
5889 00:57:03.400366 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 00:57:03.403712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 00:57:03.403799 ==
5892 00:57:03.403885
5893 00:57:03.403966
5894 00:57:03.406978 TX Vref Scan disable
5895 00:57:03.407064 == TX Byte 0 ==
5896 00:57:03.413682 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 00:57:03.416843 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 00:57:03.416930 == TX Byte 1 ==
5899 00:57:03.423581 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5900 00:57:03.426991 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5901 00:57:03.427103
5902 00:57:03.427198 [DATLAT]
5903 00:57:03.430110 Freq=933, CH1 RK1
5904 00:57:03.430194
5905 00:57:03.430260 DATLAT Default: 0xb
5906 00:57:03.433362 0, 0xFFFF, sum = 0
5907 00:57:03.433448 1, 0xFFFF, sum = 0
5908 00:57:03.436773 2, 0xFFFF, sum = 0
5909 00:57:03.440133 3, 0xFFFF, sum = 0
5910 00:57:03.440218 4, 0xFFFF, sum = 0
5911 00:57:03.443645 5, 0xFFFF, sum = 0
5912 00:57:03.443730 6, 0xFFFF, sum = 0
5913 00:57:03.446588 7, 0xFFFF, sum = 0
5914 00:57:03.446673 8, 0xFFFF, sum = 0
5915 00:57:03.450236 9, 0xFFFF, sum = 0
5916 00:57:03.450323 10, 0x0, sum = 1
5917 00:57:03.453268 11, 0x0, sum = 2
5918 00:57:03.453355 12, 0x0, sum = 3
5919 00:57:03.456629 13, 0x0, sum = 4
5920 00:57:03.456716 best_step = 11
5921 00:57:03.456801
5922 00:57:03.456881 ==
5923 00:57:03.459932 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 00:57:03.463398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 00:57:03.463485 ==
5926 00:57:03.466467 RX Vref Scan: 0
5927 00:57:03.466564
5928 00:57:03.470345 RX Vref 0 -> 0, step: 1
5929 00:57:03.470431
5930 00:57:03.470515 RX Delay -61 -> 252, step: 4
5931 00:57:03.477683 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5932 00:57:03.480912 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5933 00:57:03.484071 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5934 00:57:03.487713 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5935 00:57:03.490873 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5936 00:57:03.497436 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5937 00:57:03.500733 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5938 00:57:03.504046 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5939 00:57:03.507216 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5940 00:57:03.510792 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5941 00:57:03.517417 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5942 00:57:03.520843 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5943 00:57:03.524073 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5944 00:57:03.527437 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5945 00:57:03.530915 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5946 00:57:03.537202 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5947 00:57:03.537286 ==
5948 00:57:03.540645 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 00:57:03.543889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 00:57:03.543973 ==
5951 00:57:03.544040 DQS Delay:
5952 00:57:03.547032 DQS0 = 0, DQS1 = 0
5953 00:57:03.547115 DQM Delay:
5954 00:57:03.550351 DQM0 = 105, DQM1 = 97
5955 00:57:03.550435 DQ Delay:
5956 00:57:03.554168 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =102
5957 00:57:03.557307 DQ4 =104, DQ5 =116, DQ6 =114, DQ7 =102
5958 00:57:03.560486 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5959 00:57:03.563883 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5960 00:57:03.563969
5961 00:57:03.564053
5962 00:57:03.573630 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5963 00:57:03.577309 CH1 RK1: MR19=504, MR18=20FC
5964 00:57:03.580369 CH1_RK1: MR19=0x504, MR18=0x20FC, DQSOSC=411, MR23=63, INC=64, DEC=42
5965 00:57:03.583460 [RxdqsGatingPostProcess] freq 933
5966 00:57:03.590638 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5967 00:57:03.593646 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 00:57:03.596943 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 00:57:03.600605 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 00:57:03.603577 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 00:57:03.606826 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 00:57:03.610313 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 00:57:03.613361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 00:57:03.616832 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 00:57:03.616919 Pre-setting of DQS Precalculation
5976 00:57:03.623618 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5977 00:57:03.630368 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5978 00:57:03.636941 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5979 00:57:03.637030
5980 00:57:03.637116
5981 00:57:03.640151 [Calibration Summary] 1866 Mbps
5982 00:57:03.643545 CH 0, Rank 0
5983 00:57:03.643632 SW Impedance : PASS
5984 00:57:03.646557 DUTY Scan : NO K
5985 00:57:03.650118 ZQ Calibration : PASS
5986 00:57:03.650204 Jitter Meter : NO K
5987 00:57:03.653555 CBT Training : PASS
5988 00:57:03.656778 Write leveling : PASS
5989 00:57:03.656865 RX DQS gating : PASS
5990 00:57:03.660436 RX DQ/DQS(RDDQC) : PASS
5991 00:57:03.660522 TX DQ/DQS : PASS
5992 00:57:03.663563 RX DATLAT : PASS
5993 00:57:03.666651 RX DQ/DQS(Engine): PASS
5994 00:57:03.666737 TX OE : NO K
5995 00:57:03.669913 All Pass.
5996 00:57:03.670023
5997 00:57:03.670108 CH 0, Rank 1
5998 00:57:03.673554 SW Impedance : PASS
5999 00:57:03.673640 DUTY Scan : NO K
6000 00:57:03.677030 ZQ Calibration : PASS
6001 00:57:03.679834 Jitter Meter : NO K
6002 00:57:03.679920 CBT Training : PASS
6003 00:57:03.683476 Write leveling : PASS
6004 00:57:03.686592 RX DQS gating : PASS
6005 00:57:03.686678 RX DQ/DQS(RDDQC) : PASS
6006 00:57:03.689851 TX DQ/DQS : PASS
6007 00:57:03.693462 RX DATLAT : PASS
6008 00:57:03.693548 RX DQ/DQS(Engine): PASS
6009 00:57:03.696630 TX OE : NO K
6010 00:57:03.696716 All Pass.
6011 00:57:03.696801
6012 00:57:03.699946 CH 1, Rank 0
6013 00:57:03.700032 SW Impedance : PASS
6014 00:57:03.703137 DUTY Scan : NO K
6015 00:57:03.706431 ZQ Calibration : PASS
6016 00:57:03.706517 Jitter Meter : NO K
6017 00:57:03.709641 CBT Training : PASS
6018 00:57:03.713226 Write leveling : PASS
6019 00:57:03.713313 RX DQS gating : PASS
6020 00:57:03.716526 RX DQ/DQS(RDDQC) : PASS
6021 00:57:03.716612 TX DQ/DQS : PASS
6022 00:57:03.719741 RX DATLAT : PASS
6023 00:57:03.722789 RX DQ/DQS(Engine): PASS
6024 00:57:03.722875 TX OE : NO K
6025 00:57:03.726397 All Pass.
6026 00:57:03.726483
6027 00:57:03.726568 CH 1, Rank 1
6028 00:57:03.729720 SW Impedance : PASS
6029 00:57:03.729806 DUTY Scan : NO K
6030 00:57:03.732837 ZQ Calibration : PASS
6031 00:57:03.736072 Jitter Meter : NO K
6032 00:57:03.736158 CBT Training : PASS
6033 00:57:03.739867 Write leveling : PASS
6034 00:57:03.742960 RX DQS gating : PASS
6035 00:57:03.743046 RX DQ/DQS(RDDQC) : PASS
6036 00:57:03.745976 TX DQ/DQS : PASS
6037 00:57:03.749499 RX DATLAT : PASS
6038 00:57:03.749584 RX DQ/DQS(Engine): PASS
6039 00:57:03.752781 TX OE : NO K
6040 00:57:03.752867 All Pass.
6041 00:57:03.752952
6042 00:57:03.756333 DramC Write-DBI off
6043 00:57:03.759642 PER_BANK_REFRESH: Hybrid Mode
6044 00:57:03.759728 TX_TRACKING: ON
6045 00:57:03.769735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6046 00:57:03.773000 [FAST_K] Save calibration result to emmc
6047 00:57:03.776211 dramc_set_vcore_voltage set vcore to 650000
6048 00:57:03.779482 Read voltage for 400, 6
6049 00:57:03.779568 Vio18 = 0
6050 00:57:03.779654 Vcore = 650000
6051 00:57:03.783068 Vdram = 0
6052 00:57:03.783154 Vddq = 0
6053 00:57:03.783240 Vmddr = 0
6054 00:57:03.789458 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6055 00:57:03.792872 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6056 00:57:03.796231 MEM_TYPE=3, freq_sel=20
6057 00:57:03.799816 sv_algorithm_assistance_LP4_800
6058 00:57:03.802953 ============ PULL DRAM RESETB DOWN ============
6059 00:57:03.806354 ========== PULL DRAM RESETB DOWN end =========
6060 00:57:03.812920 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6061 00:57:03.816130 ===================================
6062 00:57:03.816217 LPDDR4 DRAM CONFIGURATION
6063 00:57:03.819582 ===================================
6064 00:57:03.823353 EX_ROW_EN[0] = 0x0
6065 00:57:03.826418 EX_ROW_EN[1] = 0x0
6066 00:57:03.826505 LP4Y_EN = 0x0
6067 00:57:03.829509 WORK_FSP = 0x0
6068 00:57:03.829595 WL = 0x2
6069 00:57:03.832971 RL = 0x2
6070 00:57:03.833058 BL = 0x2
6071 00:57:03.836144 RPST = 0x0
6072 00:57:03.836230 RD_PRE = 0x0
6073 00:57:03.839609 WR_PRE = 0x1
6074 00:57:03.839694 WR_PST = 0x0
6075 00:57:03.842715 DBI_WR = 0x0
6076 00:57:03.842801 DBI_RD = 0x0
6077 00:57:03.846295 OTF = 0x1
6078 00:57:03.849412 ===================================
6079 00:57:03.853008 ===================================
6080 00:57:03.853094 ANA top config
6081 00:57:03.856366 ===================================
6082 00:57:03.859387 DLL_ASYNC_EN = 0
6083 00:57:03.863206 ALL_SLAVE_EN = 1
6084 00:57:03.863289 NEW_RANK_MODE = 1
6085 00:57:03.866377 DLL_IDLE_MODE = 1
6086 00:57:03.869561 LP45_APHY_COMB_EN = 1
6087 00:57:03.872927 TX_ODT_DIS = 1
6088 00:57:03.876315 NEW_8X_MODE = 1
6089 00:57:03.879435 ===================================
6090 00:57:03.882882 ===================================
6091 00:57:03.882966 data_rate = 800
6092 00:57:03.886345 CKR = 1
6093 00:57:03.889479 DQ_P2S_RATIO = 4
6094 00:57:03.892704 ===================================
6095 00:57:03.896080 CA_P2S_RATIO = 4
6096 00:57:03.899635 DQ_CA_OPEN = 0
6097 00:57:03.902872 DQ_SEMI_OPEN = 1
6098 00:57:03.902956 CA_SEMI_OPEN = 1
6099 00:57:03.906064 CA_FULL_RATE = 0
6100 00:57:03.909224 DQ_CKDIV4_EN = 0
6101 00:57:03.913045 CA_CKDIV4_EN = 1
6102 00:57:03.916055 CA_PREDIV_EN = 0
6103 00:57:03.919536 PH8_DLY = 0
6104 00:57:03.919619 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6105 00:57:03.922759 DQ_AAMCK_DIV = 0
6106 00:57:03.926252 CA_AAMCK_DIV = 0
6107 00:57:03.929536 CA_ADMCK_DIV = 4
6108 00:57:03.932515 DQ_TRACK_CA_EN = 0
6109 00:57:03.935940 CA_PICK = 800
6110 00:57:03.936024 CA_MCKIO = 400
6111 00:57:03.939316 MCKIO_SEMI = 400
6112 00:57:03.942643 PLL_FREQ = 3016
6113 00:57:03.945816 DQ_UI_PI_RATIO = 32
6114 00:57:03.949378 CA_UI_PI_RATIO = 32
6115 00:57:03.952552 ===================================
6116 00:57:03.955875 ===================================
6117 00:57:03.959256 memory_type:LPDDR4
6118 00:57:03.959342 GP_NUM : 10
6119 00:57:03.962791 SRAM_EN : 1
6120 00:57:03.962877 MD32_EN : 0
6121 00:57:03.965995 ===================================
6122 00:57:03.969383 [ANA_INIT] >>>>>>>>>>>>>>
6123 00:57:03.972749 <<<<<< [CONFIGURE PHASE]: ANA_TX
6124 00:57:03.975842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6125 00:57:03.979504 ===================================
6126 00:57:03.982851 data_rate = 800,PCW = 0X7400
6127 00:57:03.986000 ===================================
6128 00:57:03.989216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6129 00:57:03.995947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 00:57:04.005522 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 00:57:04.008929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6132 00:57:04.012216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6133 00:57:04.015661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6134 00:57:04.018880 [ANA_INIT] flow start
6135 00:57:04.022109 [ANA_INIT] PLL >>>>>>>>
6136 00:57:04.022194 [ANA_INIT] PLL <<<<<<<<
6137 00:57:04.025651 [ANA_INIT] MIDPI >>>>>>>>
6138 00:57:04.029048 [ANA_INIT] MIDPI <<<<<<<<
6139 00:57:04.032227 [ANA_INIT] DLL >>>>>>>>
6140 00:57:04.032313 [ANA_INIT] flow end
6141 00:57:04.035599 ============ LP4 DIFF to SE enter ============
6142 00:57:04.042213 ============ LP4 DIFF to SE exit ============
6143 00:57:04.042301 [ANA_INIT] <<<<<<<<<<<<<
6144 00:57:04.045486 [Flow] Enable top DCM control >>>>>
6145 00:57:04.048740 [Flow] Enable top DCM control <<<<<
6146 00:57:04.051967 Enable DLL master slave shuffle
6147 00:57:04.058614 ==============================================================
6148 00:57:04.058702 Gating Mode config
6149 00:57:04.065788 ==============================================================
6150 00:57:04.068681 Config description:
6151 00:57:04.075646 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6152 00:57:04.082465 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6153 00:57:04.088650 SELPH_MODE 0: By rank 1: By Phase
6154 00:57:04.095475 ==============================================================
6155 00:57:04.098697 GAT_TRACK_EN = 0
6156 00:57:04.098807 RX_GATING_MODE = 2
6157 00:57:04.102061 RX_GATING_TRACK_MODE = 2
6158 00:57:04.105363 SELPH_MODE = 1
6159 00:57:04.108495 PICG_EARLY_EN = 1
6160 00:57:04.112160 VALID_LAT_VALUE = 1
6161 00:57:04.118644 ==============================================================
6162 00:57:04.122121 Enter into Gating configuration >>>>
6163 00:57:04.125498 Exit from Gating configuration <<<<
6164 00:57:04.128623 Enter into DVFS_PRE_config >>>>>
6165 00:57:04.138457 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6166 00:57:04.141634 Exit from DVFS_PRE_config <<<<<
6167 00:57:04.145461 Enter into PICG configuration >>>>
6168 00:57:04.148280 Exit from PICG configuration <<<<
6169 00:57:04.151797 [RX_INPUT] configuration >>>>>
6170 00:57:04.155020 [RX_INPUT] configuration <<<<<
6171 00:57:04.158414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6172 00:57:04.165097 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6173 00:57:04.171680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 00:57:04.175018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 00:57:04.181888 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 00:57:04.188516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 00:57:04.191750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6178 00:57:04.198198 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6179 00:57:04.201565 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6180 00:57:04.204683 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6181 00:57:04.208359 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6182 00:57:04.214849 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 00:57:04.217977 ===================================
6184 00:57:04.218060 LPDDR4 DRAM CONFIGURATION
6185 00:57:04.221361 ===================================
6186 00:57:04.224693 EX_ROW_EN[0] = 0x0
6187 00:57:04.228253 EX_ROW_EN[1] = 0x0
6188 00:57:04.228336 LP4Y_EN = 0x0
6189 00:57:04.231441 WORK_FSP = 0x0
6190 00:57:04.231524 WL = 0x2
6191 00:57:04.234661 RL = 0x2
6192 00:57:04.234744 BL = 0x2
6193 00:57:04.237951 RPST = 0x0
6194 00:57:04.238047 RD_PRE = 0x0
6195 00:57:04.241571 WR_PRE = 0x1
6196 00:57:04.241653 WR_PST = 0x0
6197 00:57:04.244752 DBI_WR = 0x0
6198 00:57:04.244835 DBI_RD = 0x0
6199 00:57:04.248052 OTF = 0x1
6200 00:57:04.251525 ===================================
6201 00:57:04.254769 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6202 00:57:04.257982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6203 00:57:04.265207 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 00:57:04.268076 ===================================
6205 00:57:04.268159 LPDDR4 DRAM CONFIGURATION
6206 00:57:04.271410 ===================================
6207 00:57:04.274878 EX_ROW_EN[0] = 0x10
6208 00:57:04.274961 EX_ROW_EN[1] = 0x0
6209 00:57:04.277992 LP4Y_EN = 0x0
6210 00:57:04.278074 WORK_FSP = 0x0
6211 00:57:04.281148 WL = 0x2
6212 00:57:04.284811 RL = 0x2
6213 00:57:04.284894 BL = 0x2
6214 00:57:04.287850 RPST = 0x0
6215 00:57:04.287932 RD_PRE = 0x0
6216 00:57:04.291179 WR_PRE = 0x1
6217 00:57:04.291262 WR_PST = 0x0
6218 00:57:04.294976 DBI_WR = 0x0
6219 00:57:04.295059 DBI_RD = 0x0
6220 00:57:04.297751 OTF = 0x1
6221 00:57:04.301107 ===================================
6222 00:57:04.308008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6223 00:57:04.311225 nWR fixed to 30
6224 00:57:04.311312 [ModeRegInit_LP4] CH0 RK0
6225 00:57:04.314467 [ModeRegInit_LP4] CH0 RK1
6226 00:57:04.317757 [ModeRegInit_LP4] CH1 RK0
6227 00:57:04.317840 [ModeRegInit_LP4] CH1 RK1
6228 00:57:04.321100 match AC timing 19
6229 00:57:04.324453 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6230 00:57:04.327697 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6231 00:57:04.334435 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6232 00:57:04.337631 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6233 00:57:04.344284 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6234 00:57:04.344367 ==
6235 00:57:04.347597 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 00:57:04.350985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 00:57:04.351069 ==
6238 00:57:04.357592 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 00:57:04.360991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6240 00:57:04.364791 [CA 0] Center 36 (8~64) winsize 57
6241 00:57:04.367564 [CA 1] Center 36 (8~64) winsize 57
6242 00:57:04.371123 [CA 2] Center 36 (8~64) winsize 57
6243 00:57:04.374334 [CA 3] Center 36 (8~64) winsize 57
6244 00:57:04.377511 [CA 4] Center 36 (8~64) winsize 57
6245 00:57:04.381235 [CA 5] Center 36 (8~64) winsize 57
6246 00:57:04.381318
6247 00:57:04.384108 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6248 00:57:04.384190
6249 00:57:04.387587 [CATrainingPosCal] consider 1 rank data
6250 00:57:04.390724 u2DelayCellTimex100 = 270/100 ps
6251 00:57:04.394290 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 00:57:04.397646 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 00:57:04.400977 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 00:57:04.407785 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 00:57:04.410835 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 00:57:04.414552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:57:04.414635
6258 00:57:04.417703 CA PerBit enable=1, Macro0, CA PI delay=36
6259 00:57:04.417787
6260 00:57:04.420980 [CBTSetCACLKResult] CA Dly = 36
6261 00:57:04.421063 CS Dly: 1 (0~32)
6262 00:57:04.421129 ==
6263 00:57:04.424251 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 00:57:04.430651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 00:57:04.430755 ==
6266 00:57:04.434135 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 00:57:04.440848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6268 00:57:04.444431 [CA 0] Center 36 (8~64) winsize 57
6269 00:57:04.447474 [CA 1] Center 36 (8~64) winsize 57
6270 00:57:04.450771 [CA 2] Center 36 (8~64) winsize 57
6271 00:57:04.454091 [CA 3] Center 36 (8~64) winsize 57
6272 00:57:04.457374 [CA 4] Center 36 (8~64) winsize 57
6273 00:57:04.460925 [CA 5] Center 36 (8~64) winsize 57
6274 00:57:04.461023
6275 00:57:04.464238 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6276 00:57:04.464346
6277 00:57:04.467387 [CATrainingPosCal] consider 2 rank data
6278 00:57:04.470953 u2DelayCellTimex100 = 270/100 ps
6279 00:57:04.474159 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 00:57:04.477400 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 00:57:04.480768 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 00:57:04.484130 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 00:57:04.487540 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 00:57:04.490699 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 00:57:04.490782
6286 00:57:04.497522 CA PerBit enable=1, Macro0, CA PI delay=36
6287 00:57:04.497608
6288 00:57:04.497683 [CBTSetCACLKResult] CA Dly = 36
6289 00:57:04.500929 CS Dly: 1 (0~32)
6290 00:57:04.501012
6291 00:57:04.504088 ----->DramcWriteLeveling(PI) begin...
6292 00:57:04.504172 ==
6293 00:57:04.507521 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 00:57:04.510508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 00:57:04.510599 ==
6296 00:57:04.513817 Write leveling (Byte 0): 40 => 8
6297 00:57:04.517330 Write leveling (Byte 1): 32 => 0
6298 00:57:04.520918 DramcWriteLeveling(PI) end<-----
6299 00:57:04.521001
6300 00:57:04.521066 ==
6301 00:57:04.524258 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 00:57:04.527385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 00:57:04.530586 ==
6304 00:57:04.530696 [Gating] SW mode calibration
6305 00:57:04.537347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6306 00:57:04.543820 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6307 00:57:04.547567 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 00:57:04.553766 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 00:57:04.557217 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 00:57:04.560403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 00:57:04.567226 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 00:57:04.570419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 00:57:04.574067 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 00:57:04.580494 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 00:57:04.584025 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 00:57:04.587016 Total UI for P1: 0, mck2ui 16
6317 00:57:04.590735 best dqsien dly found for B0: ( 0, 14, 24)
6318 00:57:04.594028 Total UI for P1: 0, mck2ui 16
6319 00:57:04.597272 best dqsien dly found for B1: ( 0, 14, 24)
6320 00:57:04.600738 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6321 00:57:04.604076 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6322 00:57:04.604157
6323 00:57:04.607306 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 00:57:04.610437 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 00:57:04.614151 [Gating] SW calibration Done
6326 00:57:04.614232 ==
6327 00:57:04.617317 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 00:57:04.620336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 00:57:04.620417 ==
6330 00:57:04.624076 RX Vref Scan: 0
6331 00:57:04.624156
6332 00:57:04.626948 RX Vref 0 -> 0, step: 1
6333 00:57:04.627029
6334 00:57:04.627092 RX Delay -410 -> 252, step: 16
6335 00:57:04.633909 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6336 00:57:04.637506 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6337 00:57:04.640806 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6338 00:57:04.643927 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6339 00:57:04.650884 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6340 00:57:04.653935 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6341 00:57:04.657060 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6342 00:57:04.660472 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6343 00:57:04.666880 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6344 00:57:04.670183 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6345 00:57:04.673732 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6346 00:57:04.680433 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6347 00:57:04.683661 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6348 00:57:04.686711 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6349 00:57:04.690047 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6350 00:57:04.696676 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6351 00:57:04.696758 ==
6352 00:57:04.700161 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 00:57:04.703558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 00:57:04.703639 ==
6355 00:57:04.703702 DQS Delay:
6356 00:57:04.706855 DQS0 = 27, DQS1 = 43
6357 00:57:04.706939 DQM Delay:
6358 00:57:04.710060 DQM0 = 12, DQM1 = 13
6359 00:57:04.710143 DQ Delay:
6360 00:57:04.713223 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6361 00:57:04.716459 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6362 00:57:04.719749 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6363 00:57:04.722950 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6364 00:57:04.723033
6365 00:57:04.723098
6366 00:57:04.723159 ==
6367 00:57:04.726510 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 00:57:04.729784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 00:57:04.729869 ==
6370 00:57:04.729934
6371 00:57:04.732884
6372 00:57:04.732966 TX Vref Scan disable
6373 00:57:04.735998 == TX Byte 0 ==
6374 00:57:04.739634 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 00:57:04.742815 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 00:57:04.746186 == TX Byte 1 ==
6377 00:57:04.749344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6378 00:57:04.752950 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6379 00:57:04.753053 ==
6380 00:57:04.756085 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 00:57:04.759251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 00:57:04.762641 ==
6383 00:57:04.762727
6384 00:57:04.762792
6385 00:57:04.762854 TX Vref Scan disable
6386 00:57:04.765962 == TX Byte 0 ==
6387 00:57:04.769645 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 00:57:04.772782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 00:57:04.775843 == TX Byte 1 ==
6390 00:57:04.779204 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 00:57:04.782833 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 00:57:04.782916
6393 00:57:04.785848 [DATLAT]
6394 00:57:04.785992 Freq=400, CH0 RK0
6395 00:57:04.786060
6396 00:57:04.789314 DATLAT Default: 0xf
6397 00:57:04.789400 0, 0xFFFF, sum = 0
6398 00:57:04.792401 1, 0xFFFF, sum = 0
6399 00:57:04.792490 2, 0xFFFF, sum = 0
6400 00:57:04.795845 3, 0xFFFF, sum = 0
6401 00:57:04.795935 4, 0xFFFF, sum = 0
6402 00:57:04.799189 5, 0xFFFF, sum = 0
6403 00:57:04.799275 6, 0xFFFF, sum = 0
6404 00:57:04.802791 7, 0xFFFF, sum = 0
6405 00:57:04.802902 8, 0xFFFF, sum = 0
6406 00:57:04.805951 9, 0xFFFF, sum = 0
6407 00:57:04.806035 10, 0xFFFF, sum = 0
6408 00:57:04.809414 11, 0xFFFF, sum = 0
6409 00:57:04.809514 12, 0xFFFF, sum = 0
6410 00:57:04.812436 13, 0x0, sum = 1
6411 00:57:04.812536 14, 0x0, sum = 2
6412 00:57:04.816218 15, 0x0, sum = 3
6413 00:57:04.816320 16, 0x0, sum = 4
6414 00:57:04.819116 best_step = 14
6415 00:57:04.819186
6416 00:57:04.819247 ==
6417 00:57:04.822634 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 00:57:04.825731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 00:57:04.825814 ==
6420 00:57:04.829331 RX Vref Scan: 1
6421 00:57:04.829415
6422 00:57:04.829480 RX Vref 0 -> 0, step: 1
6423 00:57:04.829540
6424 00:57:04.832465 RX Delay -327 -> 252, step: 8
6425 00:57:04.832547
6426 00:57:04.835830 Set Vref, RX VrefLevel [Byte0]: 61
6427 00:57:04.838887 [Byte1]: 50
6428 00:57:04.843646
6429 00:57:04.843728 Final RX Vref Byte 0 = 61 to rank0
6430 00:57:04.847323 Final RX Vref Byte 1 = 50 to rank0
6431 00:57:04.850330 Final RX Vref Byte 0 = 61 to rank1
6432 00:57:04.854184 Final RX Vref Byte 1 = 50 to rank1==
6433 00:57:04.857127 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 00:57:04.863635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 00:57:04.863742 ==
6436 00:57:04.863810 DQS Delay:
6437 00:57:04.867014 DQS0 = 28, DQS1 = 48
6438 00:57:04.867098 DQM Delay:
6439 00:57:04.867165 DQM0 = 12, DQM1 = 15
6440 00:57:04.870389 DQ Delay:
6441 00:57:04.873743 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6442 00:57:04.873827 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6443 00:57:04.877507 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6444 00:57:04.880846 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6445 00:57:04.880930
6446 00:57:04.883789
6447 00:57:04.890299 [DQSOSCAuto] RK0, (LSB)MR18= 0xa79f, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6448 00:57:04.894074 CH0 RK0: MR19=C0C, MR18=A79F
6449 00:57:04.900601 CH0_RK0: MR19=0xC0C, MR18=0xA79F, DQSOSC=389, MR23=63, INC=390, DEC=260
6450 00:57:04.900716 ==
6451 00:57:04.903808 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 00:57:04.906985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 00:57:04.907072 ==
6454 00:57:04.910359 [Gating] SW mode calibration
6455 00:57:04.917079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6456 00:57:04.920371 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6457 00:57:04.927165 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 00:57:04.930692 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 00:57:04.933840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 00:57:04.940499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 00:57:04.943864 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 00:57:04.947109 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 00:57:04.953797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 00:57:04.957277 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 00:57:04.960647 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 00:57:04.964014 Total UI for P1: 0, mck2ui 16
6467 00:57:04.967379 best dqsien dly found for B0: ( 0, 14, 24)
6468 00:57:04.970293 Total UI for P1: 0, mck2ui 16
6469 00:57:04.973817 best dqsien dly found for B1: ( 0, 14, 24)
6470 00:57:04.977065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6471 00:57:04.980601 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6472 00:57:04.980685
6473 00:57:04.987028 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 00:57:04.990539 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 00:57:04.993451 [Gating] SW calibration Done
6476 00:57:04.993534 ==
6477 00:57:04.996871 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 00:57:05.000628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 00:57:05.000712 ==
6480 00:57:05.000777 RX Vref Scan: 0
6481 00:57:05.000838
6482 00:57:05.003759 RX Vref 0 -> 0, step: 1
6483 00:57:05.003842
6484 00:57:05.007108 RX Delay -410 -> 252, step: 16
6485 00:57:05.010190 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6486 00:57:05.016708 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6487 00:57:05.020387 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6488 00:57:05.023532 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6489 00:57:05.026783 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6490 00:57:05.033767 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6491 00:57:05.036920 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6492 00:57:05.040088 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6493 00:57:05.043596 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6494 00:57:05.049953 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6495 00:57:05.053274 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6496 00:57:05.056531 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6497 00:57:05.060094 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6498 00:57:05.067013 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6499 00:57:05.069986 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6500 00:57:05.073270 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6501 00:57:05.073354 ==
6502 00:57:05.076626 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 00:57:05.079900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 00:57:05.083576 ==
6505 00:57:05.083659 DQS Delay:
6506 00:57:05.083725 DQS0 = 27, DQS1 = 35
6507 00:57:05.086656 DQM Delay:
6508 00:57:05.086738 DQM0 = 9, DQM1 = 9
6509 00:57:05.090065 DQ Delay:
6510 00:57:05.090147 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6511 00:57:05.093157 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6512 00:57:05.096620 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6513 00:57:05.099963 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6514 00:57:05.100046
6515 00:57:05.100112
6516 00:57:05.100173 ==
6517 00:57:05.103264 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 00:57:05.109766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 00:57:05.109850 ==
6520 00:57:05.109916
6521 00:57:05.110020
6522 00:57:05.110079 TX Vref Scan disable
6523 00:57:05.113318 == TX Byte 0 ==
6524 00:57:05.116241 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6525 00:57:05.119932 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6526 00:57:05.122894 == TX Byte 1 ==
6527 00:57:05.126000 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6528 00:57:05.129668 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6529 00:57:05.129751 ==
6530 00:57:05.132847 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 00:57:05.139789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 00:57:05.139873 ==
6533 00:57:05.139939
6534 00:57:05.139999
6535 00:57:05.140058 TX Vref Scan disable
6536 00:57:05.142859 == TX Byte 0 ==
6537 00:57:05.146369 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6538 00:57:05.149622 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6539 00:57:05.153035 == TX Byte 1 ==
6540 00:57:05.156148 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6541 00:57:05.159272 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6542 00:57:05.162767
6543 00:57:05.162849 [DATLAT]
6544 00:57:05.162914 Freq=400, CH0 RK1
6545 00:57:05.162975
6546 00:57:05.165915 DATLAT Default: 0xe
6547 00:57:05.166018 0, 0xFFFF, sum = 0
6548 00:57:05.169081 1, 0xFFFF, sum = 0
6549 00:57:05.169166 2, 0xFFFF, sum = 0
6550 00:57:05.172517 3, 0xFFFF, sum = 0
6551 00:57:05.172601 4, 0xFFFF, sum = 0
6552 00:57:05.175822 5, 0xFFFF, sum = 0
6553 00:57:05.179371 6, 0xFFFF, sum = 0
6554 00:57:05.179455 7, 0xFFFF, sum = 0
6555 00:57:05.182529 8, 0xFFFF, sum = 0
6556 00:57:05.182613 9, 0xFFFF, sum = 0
6557 00:57:05.185781 10, 0xFFFF, sum = 0
6558 00:57:05.185865 11, 0xFFFF, sum = 0
6559 00:57:05.188868 12, 0xFFFF, sum = 0
6560 00:57:05.188952 13, 0x0, sum = 1
6561 00:57:05.192429 14, 0x0, sum = 2
6562 00:57:05.192513 15, 0x0, sum = 3
6563 00:57:05.195942 16, 0x0, sum = 4
6564 00:57:05.196026 best_step = 14
6565 00:57:05.196091
6566 00:57:05.196152 ==
6567 00:57:05.199191 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 00:57:05.202252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 00:57:05.202335 ==
6570 00:57:05.205914 RX Vref Scan: 0
6571 00:57:05.206018
6572 00:57:05.208804 RX Vref 0 -> 0, step: 1
6573 00:57:05.208887
6574 00:57:05.208952 RX Delay -311 -> 252, step: 8
6575 00:57:05.217457 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6576 00:57:05.221079 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6577 00:57:05.224410 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6578 00:57:05.227771 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6579 00:57:05.234173 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6580 00:57:05.237719 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6581 00:57:05.240610 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6582 00:57:05.244264 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6583 00:57:05.250855 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6584 00:57:05.253926 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6585 00:57:05.257494 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6586 00:57:05.260863 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6587 00:57:05.267375 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6588 00:57:05.270846 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6589 00:57:05.274436 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6590 00:57:05.281031 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6591 00:57:05.281115 ==
6592 00:57:05.284387 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 00:57:05.287624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 00:57:05.287708 ==
6595 00:57:05.287773 DQS Delay:
6596 00:57:05.291171 DQS0 = 24, DQS1 = 40
6597 00:57:05.291257 DQM Delay:
6598 00:57:05.294069 DQM0 = 6, DQM1 = 12
6599 00:57:05.294149 DQ Delay:
6600 00:57:05.297826 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6601 00:57:05.301253 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6602 00:57:05.304387 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6603 00:57:05.307448 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =16
6604 00:57:05.307526
6605 00:57:05.307591
6606 00:57:05.314321 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6607 00:57:05.317429 CH0 RK1: MR19=C0C, MR18=B86B
6608 00:57:05.324338 CH0_RK1: MR19=0xC0C, MR18=0xB86B, DQSOSC=386, MR23=63, INC=396, DEC=264
6609 00:57:05.327424 [RxdqsGatingPostProcess] freq 400
6610 00:57:05.330775 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6611 00:57:05.334237 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 00:57:05.337444 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 00:57:05.340876 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 00:57:05.344506 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 00:57:05.347357 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 00:57:05.350725 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 00:57:05.353855 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 00:57:05.357404 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 00:57:05.360871 Pre-setting of DQS Precalculation
6620 00:57:05.364017 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6621 00:57:05.364088 ==
6622 00:57:05.367293 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 00:57:05.374234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 00:57:05.374309 ==
6625 00:57:05.377450 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 00:57:05.384108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6627 00:57:05.387323 [CA 0] Center 36 (8~64) winsize 57
6628 00:57:05.390595 [CA 1] Center 36 (8~64) winsize 57
6629 00:57:05.393865 [CA 2] Center 36 (8~64) winsize 57
6630 00:57:05.397186 [CA 3] Center 36 (8~64) winsize 57
6631 00:57:05.400794 [CA 4] Center 36 (8~64) winsize 57
6632 00:57:05.403951 [CA 5] Center 36 (8~64) winsize 57
6633 00:57:05.404022
6634 00:57:05.407360 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6635 00:57:05.407428
6636 00:57:05.410824 [CATrainingPosCal] consider 1 rank data
6637 00:57:05.413907 u2DelayCellTimex100 = 270/100 ps
6638 00:57:05.417265 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 00:57:05.420570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 00:57:05.423543 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 00:57:05.427200 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 00:57:05.430236 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 00:57:05.433573 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:57:05.437326
6645 00:57:05.440582 CA PerBit enable=1, Macro0, CA PI delay=36
6646 00:57:05.440664
6647 00:57:05.443713 [CBTSetCACLKResult] CA Dly = 36
6648 00:57:05.443783 CS Dly: 1 (0~32)
6649 00:57:05.443851 ==
6650 00:57:05.447012 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 00:57:05.449857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 00:57:05.453315 ==
6653 00:57:05.456835 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 00:57:05.463349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 00:57:05.466701 [CA 0] Center 36 (8~64) winsize 57
6656 00:57:05.470528 [CA 1] Center 36 (8~64) winsize 57
6657 00:57:05.473580 [CA 2] Center 36 (8~64) winsize 57
6658 00:57:05.476708 [CA 3] Center 36 (8~64) winsize 57
6659 00:57:05.479940 [CA 4] Center 36 (8~64) winsize 57
6660 00:57:05.483247 [CA 5] Center 36 (8~64) winsize 57
6661 00:57:05.483318
6662 00:57:05.486747 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 00:57:05.486817
6664 00:57:05.489891 [CATrainingPosCal] consider 2 rank data
6665 00:57:05.493374 u2DelayCellTimex100 = 270/100 ps
6666 00:57:05.496776 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 00:57:05.499944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 00:57:05.503222 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 00:57:05.506707 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 00:57:05.509901 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 00:57:05.513215 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 00:57:05.513285
6673 00:57:05.516410 CA PerBit enable=1, Macro0, CA PI delay=36
6674 00:57:05.516479
6675 00:57:05.519733 [CBTSetCACLKResult] CA Dly = 36
6676 00:57:05.523099 CS Dly: 1 (0~32)
6677 00:57:05.523197
6678 00:57:05.526575 ----->DramcWriteLeveling(PI) begin...
6679 00:57:05.526659 ==
6680 00:57:05.529813 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 00:57:05.533118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 00:57:05.533201 ==
6683 00:57:05.536377 Write leveling (Byte 0): 40 => 8
6684 00:57:05.539752 Write leveling (Byte 1): 32 => 0
6685 00:57:05.543136 DramcWriteLeveling(PI) end<-----
6686 00:57:05.543218
6687 00:57:05.543283 ==
6688 00:57:05.546327 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 00:57:05.549703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 00:57:05.549810 ==
6691 00:57:05.553371 [Gating] SW mode calibration
6692 00:57:05.559733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6693 00:57:05.566476 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6694 00:57:05.569568 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 00:57:05.576579 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 00:57:05.579680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 00:57:05.582958 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 00:57:05.586573 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 00:57:05.593113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 00:57:05.596420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 00:57:05.600042 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 00:57:05.606338 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 00:57:05.609710 Total UI for P1: 0, mck2ui 16
6704 00:57:05.612957 best dqsien dly found for B0: ( 0, 14, 24)
6705 00:57:05.613041 Total UI for P1: 0, mck2ui 16
6706 00:57:05.619557 best dqsien dly found for B1: ( 0, 14, 24)
6707 00:57:05.623079 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6708 00:57:05.626290 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6709 00:57:05.626374
6710 00:57:05.629698 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 00:57:05.632945 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 00:57:05.636296 [Gating] SW calibration Done
6713 00:57:05.636380 ==
6714 00:57:05.639319 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 00:57:05.642669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 00:57:05.642753 ==
6717 00:57:05.646308 RX Vref Scan: 0
6718 00:57:05.646398
6719 00:57:05.649610 RX Vref 0 -> 0, step: 1
6720 00:57:05.649693
6721 00:57:05.649758 RX Delay -410 -> 252, step: 16
6722 00:57:05.656035 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6723 00:57:05.659208 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6724 00:57:05.662821 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6725 00:57:05.665825 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6726 00:57:05.672539 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6727 00:57:05.675830 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6728 00:57:05.679476 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6729 00:57:05.682601 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6730 00:57:05.689196 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6731 00:57:05.692886 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6732 00:57:05.695966 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6733 00:57:05.699383 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6734 00:57:05.705967 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6735 00:57:05.709197 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6736 00:57:05.712572 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6737 00:57:05.719439 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6738 00:57:05.719522 ==
6739 00:57:05.722481 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 00:57:05.725937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 00:57:05.726038 ==
6742 00:57:05.726103 DQS Delay:
6743 00:57:05.729111 DQS0 = 27, DQS1 = 43
6744 00:57:05.729193 DQM Delay:
6745 00:57:05.732643 DQM0 = 5, DQM1 = 16
6746 00:57:05.732726 DQ Delay:
6747 00:57:05.736027 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6748 00:57:05.739442 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6749 00:57:05.742766 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6750 00:57:05.745874 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6751 00:57:05.746002
6752 00:57:05.746068
6753 00:57:05.746129 ==
6754 00:57:05.749162 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 00:57:05.752402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 00:57:05.752486 ==
6757 00:57:05.752552
6758 00:57:05.752613
6759 00:57:05.756093 TX Vref Scan disable
6760 00:57:05.756177 == TX Byte 0 ==
6761 00:57:05.762467 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 00:57:05.765814 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 00:57:05.765898 == TX Byte 1 ==
6764 00:57:05.772604 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6765 00:57:05.775921 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6766 00:57:05.776004 ==
6767 00:57:05.779125 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 00:57:05.782344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 00:57:05.782428 ==
6770 00:57:05.782493
6771 00:57:05.782554
6772 00:57:05.785665 TX Vref Scan disable
6773 00:57:05.785748 == TX Byte 0 ==
6774 00:57:05.792581 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 00:57:05.795725 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 00:57:05.795808 == TX Byte 1 ==
6777 00:57:05.802726 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6778 00:57:05.805900 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6779 00:57:05.805990
6780 00:57:05.806055 [DATLAT]
6781 00:57:05.809166 Freq=400, CH1 RK0
6782 00:57:05.809249
6783 00:57:05.809313 DATLAT Default: 0xf
6784 00:57:05.812441 0, 0xFFFF, sum = 0
6785 00:57:05.812525 1, 0xFFFF, sum = 0
6786 00:57:05.815730 2, 0xFFFF, sum = 0
6787 00:57:05.815815 3, 0xFFFF, sum = 0
6788 00:57:05.819476 4, 0xFFFF, sum = 0
6789 00:57:05.819584 5, 0xFFFF, sum = 0
6790 00:57:05.822817 6, 0xFFFF, sum = 0
6791 00:57:05.822900 7, 0xFFFF, sum = 0
6792 00:57:05.825782 8, 0xFFFF, sum = 0
6793 00:57:05.825867 9, 0xFFFF, sum = 0
6794 00:57:05.829045 10, 0xFFFF, sum = 0
6795 00:57:05.832516 11, 0xFFFF, sum = 0
6796 00:57:05.832601 12, 0xFFFF, sum = 0
6797 00:57:05.835522 13, 0x0, sum = 1
6798 00:57:05.835633 14, 0x0, sum = 2
6799 00:57:05.838915 15, 0x0, sum = 3
6800 00:57:05.838998 16, 0x0, sum = 4
6801 00:57:05.839064 best_step = 14
6802 00:57:05.839125
6803 00:57:05.842397 ==
6804 00:57:05.842480 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 00:57:05.849125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 00:57:05.849208 ==
6807 00:57:05.849274 RX Vref Scan: 1
6808 00:57:05.849335
6809 00:57:05.852221 RX Vref 0 -> 0, step: 1
6810 00:57:05.852303
6811 00:57:05.855548 RX Delay -327 -> 252, step: 8
6812 00:57:05.855671
6813 00:57:05.859048 Set Vref, RX VrefLevel [Byte0]: 51
6814 00:57:05.862442 [Byte1]: 51
6815 00:57:05.865924
6816 00:57:05.866017 Final RX Vref Byte 0 = 51 to rank0
6817 00:57:05.869243 Final RX Vref Byte 1 = 51 to rank0
6818 00:57:05.872626 Final RX Vref Byte 0 = 51 to rank1
6819 00:57:05.875752 Final RX Vref Byte 1 = 51 to rank1==
6820 00:57:05.878923 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 00:57:05.885701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 00:57:05.885784 ==
6823 00:57:05.885849 DQS Delay:
6824 00:57:05.888871 DQS0 = 32, DQS1 = 40
6825 00:57:05.888954 DQM Delay:
6826 00:57:05.889020 DQM0 = 11, DQM1 = 12
6827 00:57:05.892223 DQ Delay:
6828 00:57:05.895532 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6829 00:57:05.895615 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6830 00:57:05.899171 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6831 00:57:05.902292 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6832 00:57:05.902374
6833 00:57:05.902440
6834 00:57:05.912320 [DQSOSCAuto] RK0, (LSB)MR18= 0x91cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6835 00:57:05.915692 CH1 RK0: MR19=C0C, MR18=91CB
6836 00:57:05.922215 CH1_RK0: MR19=0xC0C, MR18=0x91CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6837 00:57:05.922299 ==
6838 00:57:05.925630 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 00:57:05.928765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 00:57:05.928849 ==
6841 00:57:05.932034 [Gating] SW mode calibration
6842 00:57:05.938513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6843 00:57:05.945403 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6844 00:57:05.948346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 00:57:05.951678 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 00:57:05.958853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 00:57:05.961965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 00:57:05.965147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 00:57:05.968670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 00:57:05.975021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 00:57:05.978636 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 00:57:05.981915 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 00:57:05.985084 Total UI for P1: 0, mck2ui 16
6854 00:57:05.988598 best dqsien dly found for B0: ( 0, 14, 24)
6855 00:57:05.991772 Total UI for P1: 0, mck2ui 16
6856 00:57:05.995247 best dqsien dly found for B1: ( 0, 14, 24)
6857 00:57:05.998241 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6858 00:57:06.005166 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6859 00:57:06.005250
6860 00:57:06.008230 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 00:57:06.012180 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 00:57:06.015099 [Gating] SW calibration Done
6863 00:57:06.015183 ==
6864 00:57:06.018744 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 00:57:06.021839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 00:57:06.021922 ==
6867 00:57:06.022024 RX Vref Scan: 0
6868 00:57:06.024967
6869 00:57:06.025049 RX Vref 0 -> 0, step: 1
6870 00:57:06.025115
6871 00:57:06.028285 RX Delay -410 -> 252, step: 16
6872 00:57:06.031702 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6873 00:57:06.038515 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6874 00:57:06.041838 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6875 00:57:06.044960 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6876 00:57:06.048245 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6877 00:57:06.054912 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6878 00:57:06.058327 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6879 00:57:06.061557 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6880 00:57:06.064816 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6881 00:57:06.071511 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6882 00:57:06.074697 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6883 00:57:06.078015 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6884 00:57:06.081797 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6885 00:57:06.088205 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6886 00:57:06.091492 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6887 00:57:06.094598 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6888 00:57:06.094674 ==
6889 00:57:06.098290 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 00:57:06.101438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 00:57:06.105137 ==
6892 00:57:06.105216 DQS Delay:
6893 00:57:06.105300 DQS0 = 35, DQS1 = 35
6894 00:57:06.108123 DQM Delay:
6895 00:57:06.108201 DQM0 = 17, DQM1 = 11
6896 00:57:06.111472 DQ Delay:
6897 00:57:06.114784 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6898 00:57:06.114894 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6899 00:57:06.118322 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6900 00:57:06.121274 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6901 00:57:06.121358
6902 00:57:06.121441
6903 00:57:06.124634 ==
6904 00:57:06.127965 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 00:57:06.131284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 00:57:06.131378 ==
6907 00:57:06.131446
6908 00:57:06.131507
6909 00:57:06.134663 TX Vref Scan disable
6910 00:57:06.134770 == TX Byte 0 ==
6911 00:57:06.138138 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 00:57:06.144718 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 00:57:06.144795 == TX Byte 1 ==
6914 00:57:06.148206 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6915 00:57:06.151397 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6916 00:57:06.154722 ==
6917 00:57:06.158721 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 00:57:06.161404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 00:57:06.161511 ==
6920 00:57:06.161608
6921 00:57:06.161675
6922 00:57:06.164826 TX Vref Scan disable
6923 00:57:06.164897 == TX Byte 0 ==
6924 00:57:06.168079 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 00:57:06.174910 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 00:57:06.174988 == TX Byte 1 ==
6927 00:57:06.177867 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6928 00:57:06.181252 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6929 00:57:06.184711
6930 00:57:06.184785 [DATLAT]
6931 00:57:06.184847 Freq=400, CH1 RK1
6932 00:57:06.184914
6933 00:57:06.188021 DATLAT Default: 0xe
6934 00:57:06.188095 0, 0xFFFF, sum = 0
6935 00:57:06.191597 1, 0xFFFF, sum = 0
6936 00:57:06.191679 2, 0xFFFF, sum = 0
6937 00:57:06.194814 3, 0xFFFF, sum = 0
6938 00:57:06.194895 4, 0xFFFF, sum = 0
6939 00:57:06.197912 5, 0xFFFF, sum = 0
6940 00:57:06.201496 6, 0xFFFF, sum = 0
6941 00:57:06.201598 7, 0xFFFF, sum = 0
6942 00:57:06.204620 8, 0xFFFF, sum = 0
6943 00:57:06.204695 9, 0xFFFF, sum = 0
6944 00:57:06.207900 10, 0xFFFF, sum = 0
6945 00:57:06.207975 11, 0xFFFF, sum = 0
6946 00:57:06.211768 12, 0xFFFF, sum = 0
6947 00:57:06.211844 13, 0x0, sum = 1
6948 00:57:06.214665 14, 0x0, sum = 2
6949 00:57:06.214740 15, 0x0, sum = 3
6950 00:57:06.217843 16, 0x0, sum = 4
6951 00:57:06.217917 best_step = 14
6952 00:57:06.218029
6953 00:57:06.218089 ==
6954 00:57:06.221316 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 00:57:06.224792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 00:57:06.224896 ==
6957 00:57:06.227986 RX Vref Scan: 0
6958 00:57:06.228064
6959 00:57:06.231378 RX Vref 0 -> 0, step: 1
6960 00:57:06.231455
6961 00:57:06.231524 RX Delay -311 -> 252, step: 8
6962 00:57:06.239836 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6963 00:57:06.243226 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6964 00:57:06.246668 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6965 00:57:06.249721 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6966 00:57:06.256791 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6967 00:57:06.259716 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6968 00:57:06.263345 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6969 00:57:06.266411 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6970 00:57:06.273128 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6971 00:57:06.276354 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6972 00:57:06.279433 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6973 00:57:06.283285 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6974 00:57:06.289851 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6975 00:57:06.293177 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6976 00:57:06.296220 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6977 00:57:06.302628 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6978 00:57:06.302713 ==
6979 00:57:06.306345 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 00:57:06.309455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 00:57:06.309531 ==
6982 00:57:06.309595 DQS Delay:
6983 00:57:06.312740 DQS0 = 28, DQS1 = 36
6984 00:57:06.312810 DQM Delay:
6985 00:57:06.316415 DQM0 = 9, DQM1 = 11
6986 00:57:06.316501 DQ Delay:
6987 00:57:06.319651 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =12
6988 00:57:06.322815 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =4
6989 00:57:06.326652 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6990 00:57:06.329515 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6991 00:57:06.329591
6992 00:57:06.329663
6993 00:57:06.336283 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa52, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6994 00:57:06.339452 CH1 RK1: MR19=C0C, MR18=AA52
6995 00:57:06.346239 CH1_RK1: MR19=0xC0C, MR18=0xAA52, DQSOSC=388, MR23=63, INC=392, DEC=261
6996 00:57:06.349326 [RxdqsGatingPostProcess] freq 400
6997 00:57:06.356029 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6998 00:57:06.359580 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 00:57:06.359690 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 00:57:06.362588 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 00:57:06.365660 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 00:57:06.369405 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 00:57:06.372358 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 00:57:06.375862 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 00:57:06.379282 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 00:57:06.382772 Pre-setting of DQS Precalculation
7007 00:57:06.388964 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7008 00:57:06.395669 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7009 00:57:06.402264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7010 00:57:06.402367
7011 00:57:06.402461
7012 00:57:06.406084 [Calibration Summary] 800 Mbps
7013 00:57:06.406168 CH 0, Rank 0
7014 00:57:06.409072 SW Impedance : PASS
7015 00:57:06.412670 DUTY Scan : NO K
7016 00:57:06.412753 ZQ Calibration : PASS
7017 00:57:06.415943 Jitter Meter : NO K
7018 00:57:06.416057 CBT Training : PASS
7019 00:57:06.419272 Write leveling : PASS
7020 00:57:06.422430 RX DQS gating : PASS
7021 00:57:06.422513 RX DQ/DQS(RDDQC) : PASS
7022 00:57:06.425662 TX DQ/DQS : PASS
7023 00:57:06.428987 RX DATLAT : PASS
7024 00:57:06.429092 RX DQ/DQS(Engine): PASS
7025 00:57:06.432330 TX OE : NO K
7026 00:57:06.432429 All Pass.
7027 00:57:06.432495
7028 00:57:06.435423 CH 0, Rank 1
7029 00:57:06.435506 SW Impedance : PASS
7030 00:57:06.439037 DUTY Scan : NO K
7031 00:57:06.442463 ZQ Calibration : PASS
7032 00:57:06.442546 Jitter Meter : NO K
7033 00:57:06.445788 CBT Training : PASS
7034 00:57:06.448857 Write leveling : NO K
7035 00:57:06.448940 RX DQS gating : PASS
7036 00:57:06.452159 RX DQ/DQS(RDDQC) : PASS
7037 00:57:06.455432 TX DQ/DQS : PASS
7038 00:57:06.455515 RX DATLAT : PASS
7039 00:57:06.458689 RX DQ/DQS(Engine): PASS
7040 00:57:06.462078 TX OE : NO K
7041 00:57:06.462161 All Pass.
7042 00:57:06.462226
7043 00:57:06.462287 CH 1, Rank 0
7044 00:57:06.465290 SW Impedance : PASS
7045 00:57:06.468766 DUTY Scan : NO K
7046 00:57:06.468849 ZQ Calibration : PASS
7047 00:57:06.472289 Jitter Meter : NO K
7048 00:57:06.472419 CBT Training : PASS
7049 00:57:06.475444 Write leveling : PASS
7050 00:57:06.479006 RX DQS gating : PASS
7051 00:57:06.479089 RX DQ/DQS(RDDQC) : PASS
7052 00:57:06.482282 TX DQ/DQS : PASS
7053 00:57:06.485407 RX DATLAT : PASS
7054 00:57:06.485489 RX DQ/DQS(Engine): PASS
7055 00:57:06.489098 TX OE : NO K
7056 00:57:06.489182 All Pass.
7057 00:57:06.489247
7058 00:57:06.492203 CH 1, Rank 1
7059 00:57:06.492304 SW Impedance : PASS
7060 00:57:06.495359 DUTY Scan : NO K
7061 00:57:06.498908 ZQ Calibration : PASS
7062 00:57:06.499001 Jitter Meter : NO K
7063 00:57:06.502181 CBT Training : PASS
7064 00:57:06.505439 Write leveling : NO K
7065 00:57:06.505523 RX DQS gating : PASS
7066 00:57:06.508937 RX DQ/DQS(RDDQC) : PASS
7067 00:57:06.509021 TX DQ/DQS : PASS
7068 00:57:06.511854 RX DATLAT : PASS
7069 00:57:06.515506 RX DQ/DQS(Engine): PASS
7070 00:57:06.515589 TX OE : NO K
7071 00:57:06.518700 All Pass.
7072 00:57:06.518800
7073 00:57:06.518866 DramC Write-DBI off
7074 00:57:06.522164 PER_BANK_REFRESH: Hybrid Mode
7075 00:57:06.525260 TX_TRACKING: ON
7076 00:57:06.532106 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7077 00:57:06.535700 [FAST_K] Save calibration result to emmc
7078 00:57:06.538962 dramc_set_vcore_voltage set vcore to 725000
7079 00:57:06.542157 Read voltage for 1600, 0
7080 00:57:06.542243 Vio18 = 0
7081 00:57:06.545196 Vcore = 725000
7082 00:57:06.545281 Vdram = 0
7083 00:57:06.545349 Vddq = 0
7084 00:57:06.548375 Vmddr = 0
7085 00:57:06.551674 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7086 00:57:06.558352 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7087 00:57:06.558439 MEM_TYPE=3, freq_sel=13
7088 00:57:06.561794 sv_algorithm_assistance_LP4_3733
7089 00:57:06.568645 ============ PULL DRAM RESETB DOWN ============
7090 00:57:06.571977 ========== PULL DRAM RESETB DOWN end =========
7091 00:57:06.575199 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7092 00:57:06.578479 ===================================
7093 00:57:06.581890 LPDDR4 DRAM CONFIGURATION
7094 00:57:06.585515 ===================================
7095 00:57:06.588730 EX_ROW_EN[0] = 0x0
7096 00:57:06.588806 EX_ROW_EN[1] = 0x0
7097 00:57:06.592065 LP4Y_EN = 0x0
7098 00:57:06.592140 WORK_FSP = 0x1
7099 00:57:06.595061 WL = 0x5
7100 00:57:06.595140 RL = 0x5
7101 00:57:06.598719 BL = 0x2
7102 00:57:06.598848 RPST = 0x0
7103 00:57:06.602029 RD_PRE = 0x0
7104 00:57:06.602110 WR_PRE = 0x1
7105 00:57:06.605055 WR_PST = 0x1
7106 00:57:06.605134 DBI_WR = 0x0
7107 00:57:06.608215 DBI_RD = 0x0
7108 00:57:06.608294 OTF = 0x1
7109 00:57:06.611391 ===================================
7110 00:57:06.615015 ===================================
7111 00:57:06.618288 ANA top config
7112 00:57:06.621604 ===================================
7113 00:57:06.624859 DLL_ASYNC_EN = 0
7114 00:57:06.624933 ALL_SLAVE_EN = 0
7115 00:57:06.628075 NEW_RANK_MODE = 1
7116 00:57:06.631595 DLL_IDLE_MODE = 1
7117 00:57:06.634810 LP45_APHY_COMB_EN = 1
7118 00:57:06.634892 TX_ODT_DIS = 0
7119 00:57:06.637876 NEW_8X_MODE = 1
7120 00:57:06.641604 ===================================
7121 00:57:06.644684 ===================================
7122 00:57:06.648004 data_rate = 3200
7123 00:57:06.651646 CKR = 1
7124 00:57:06.654602 DQ_P2S_RATIO = 8
7125 00:57:06.658497 ===================================
7126 00:57:06.661336 CA_P2S_RATIO = 8
7127 00:57:06.661413 DQ_CA_OPEN = 0
7128 00:57:06.664905 DQ_SEMI_OPEN = 0
7129 00:57:06.668085 CA_SEMI_OPEN = 0
7130 00:57:06.671331 CA_FULL_RATE = 0
7131 00:57:06.674397 DQ_CKDIV4_EN = 0
7132 00:57:06.678152 CA_CKDIV4_EN = 0
7133 00:57:06.678232 CA_PREDIV_EN = 0
7134 00:57:06.681410 PH8_DLY = 12
7135 00:57:06.684620 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7136 00:57:06.687884 DQ_AAMCK_DIV = 4
7137 00:57:06.691270 CA_AAMCK_DIV = 4
7138 00:57:06.694665 CA_ADMCK_DIV = 4
7139 00:57:06.694741 DQ_TRACK_CA_EN = 0
7140 00:57:06.697792 CA_PICK = 1600
7141 00:57:06.701297 CA_MCKIO = 1600
7142 00:57:06.705363 MCKIO_SEMI = 0
7143 00:57:06.707971 PLL_FREQ = 3068
7144 00:57:06.710990 DQ_UI_PI_RATIO = 32
7145 00:57:06.714600 CA_UI_PI_RATIO = 0
7146 00:57:06.717802 ===================================
7147 00:57:06.721303 ===================================
7148 00:57:06.721377 memory_type:LPDDR4
7149 00:57:06.724396 GP_NUM : 10
7150 00:57:06.728060 SRAM_EN : 1
7151 00:57:06.728134 MD32_EN : 0
7152 00:57:06.731283 ===================================
7153 00:57:06.734271 [ANA_INIT] >>>>>>>>>>>>>>
7154 00:57:06.737925 <<<<<< [CONFIGURE PHASE]: ANA_TX
7155 00:57:06.741241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7156 00:57:06.744378 ===================================
7157 00:57:06.747663 data_rate = 3200,PCW = 0X7600
7158 00:57:06.751072 ===================================
7159 00:57:06.754227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7160 00:57:06.757747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 00:57:06.764731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 00:57:06.767495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7163 00:57:06.771057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7164 00:57:06.774371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7165 00:57:06.777371 [ANA_INIT] flow start
7166 00:57:06.781201 [ANA_INIT] PLL >>>>>>>>
7167 00:57:06.781283 [ANA_INIT] PLL <<<<<<<<
7168 00:57:06.784431 [ANA_INIT] MIDPI >>>>>>>>
7169 00:57:06.787764 [ANA_INIT] MIDPI <<<<<<<<
7170 00:57:06.791154 [ANA_INIT] DLL >>>>>>>>
7171 00:57:06.791232 [ANA_INIT] DLL <<<<<<<<
7172 00:57:06.794488 [ANA_INIT] flow end
7173 00:57:06.797629 ============ LP4 DIFF to SE enter ============
7174 00:57:06.800989 ============ LP4 DIFF to SE exit ============
7175 00:57:06.804183 [ANA_INIT] <<<<<<<<<<<<<
7176 00:57:06.807623 [Flow] Enable top DCM control >>>>>
7177 00:57:06.810870 [Flow] Enable top DCM control <<<<<
7178 00:57:06.814224 Enable DLL master slave shuffle
7179 00:57:06.817438 ==============================================================
7180 00:57:06.820564 Gating Mode config
7181 00:57:06.827546 ==============================================================
7182 00:57:06.827629 Config description:
7183 00:57:06.837388 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7184 00:57:06.844235 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7185 00:57:06.850545 SELPH_MODE 0: By rank 1: By Phase
7186 00:57:06.853827 ==============================================================
7187 00:57:06.857391 GAT_TRACK_EN = 1
7188 00:57:06.860727 RX_GATING_MODE = 2
7189 00:57:06.864270 RX_GATING_TRACK_MODE = 2
7190 00:57:06.867326 SELPH_MODE = 1
7191 00:57:06.870630 PICG_EARLY_EN = 1
7192 00:57:06.873799 VALID_LAT_VALUE = 1
7193 00:57:06.877148 ==============================================================
7194 00:57:06.880536 Enter into Gating configuration >>>>
7195 00:57:06.883885 Exit from Gating configuration <<<<
7196 00:57:06.887183 Enter into DVFS_PRE_config >>>>>
7197 00:57:06.900563 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7198 00:57:06.903890 Exit from DVFS_PRE_config <<<<<
7199 00:57:06.903965 Enter into PICG configuration >>>>
7200 00:57:06.907049 Exit from PICG configuration <<<<
7201 00:57:06.910585 [RX_INPUT] configuration >>>>>
7202 00:57:06.913715 [RX_INPUT] configuration <<<<<
7203 00:57:06.920526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7204 00:57:06.923859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7205 00:57:06.930649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 00:57:06.937230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 00:57:06.943984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 00:57:06.950442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 00:57:06.953698 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7210 00:57:06.956884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7211 00:57:06.960457 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7212 00:57:06.967226 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7213 00:57:06.970378 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7214 00:57:06.973830 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 00:57:06.977123 ===================================
7216 00:57:06.980184 LPDDR4 DRAM CONFIGURATION
7217 00:57:06.983545 ===================================
7218 00:57:06.987081 EX_ROW_EN[0] = 0x0
7219 00:57:06.987168 EX_ROW_EN[1] = 0x0
7220 00:57:06.990384 LP4Y_EN = 0x0
7221 00:57:06.990452 WORK_FSP = 0x1
7222 00:57:06.993575 WL = 0x5
7223 00:57:06.993642 RL = 0x5
7224 00:57:06.996820 BL = 0x2
7225 00:57:06.996887 RPST = 0x0
7226 00:57:07.000363 RD_PRE = 0x0
7227 00:57:07.000430 WR_PRE = 0x1
7228 00:57:07.003574 WR_PST = 0x1
7229 00:57:07.003641 DBI_WR = 0x0
7230 00:57:07.007207 DBI_RD = 0x0
7231 00:57:07.007280 OTF = 0x1
7232 00:57:07.010284 ===================================
7233 00:57:07.013803 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7234 00:57:07.020262 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7235 00:57:07.023333 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 00:57:07.026697 ===================================
7237 00:57:07.030315 LPDDR4 DRAM CONFIGURATION
7238 00:57:07.033302 ===================================
7239 00:57:07.033388 EX_ROW_EN[0] = 0x10
7240 00:57:07.036666 EX_ROW_EN[1] = 0x0
7241 00:57:07.040265 LP4Y_EN = 0x0
7242 00:57:07.040348 WORK_FSP = 0x1
7243 00:57:07.043285 WL = 0x5
7244 00:57:07.043356 RL = 0x5
7245 00:57:07.046571 BL = 0x2
7246 00:57:07.046647 RPST = 0x0
7247 00:57:07.049783 RD_PRE = 0x0
7248 00:57:07.049863 WR_PRE = 0x1
7249 00:57:07.053458 WR_PST = 0x1
7250 00:57:07.053539 DBI_WR = 0x0
7251 00:57:07.056727 DBI_RD = 0x0
7252 00:57:07.056802 OTF = 0x1
7253 00:57:07.059849 ===================================
7254 00:57:07.066477 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7255 00:57:07.066562 ==
7256 00:57:07.069734 Dram Type= 6, Freq= 0, CH_0, rank 0
7257 00:57:07.072960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7258 00:57:07.076571 ==
7259 00:57:07.076651 [Duty_Offset_Calibration]
7260 00:57:07.079629 B0:2 B1:0 CA:1
7261 00:57:07.079713
7262 00:57:07.083101 [DutyScan_Calibration_Flow] k_type=0
7263 00:57:07.091359
7264 00:57:07.091444 ==CLK 0==
7265 00:57:07.094500 Final CLK duty delay cell = -4
7266 00:57:07.097967 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7267 00:57:07.101102 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7268 00:57:07.104356 [-4] AVG Duty = 4906%(X100)
7269 00:57:07.104453
7270 00:57:07.107668 CH0 CLK Duty spec in!! Max-Min= 187%
7271 00:57:07.110969 [DutyScan_Calibration_Flow] ====Done====
7272 00:57:07.111052
7273 00:57:07.114375 [DutyScan_Calibration_Flow] k_type=1
7274 00:57:07.130879
7275 00:57:07.130959 ==DQS 0 ==
7276 00:57:07.134301 Final DQS duty delay cell = 0
7277 00:57:07.137287 [0] MAX Duty = 5249%(X100), DQS PI = 32
7278 00:57:07.140619 [0] MIN Duty = 4938%(X100), DQS PI = 62
7279 00:57:07.144073 [0] AVG Duty = 5093%(X100)
7280 00:57:07.144149
7281 00:57:07.144220 ==DQS 1 ==
7282 00:57:07.147208 Final DQS duty delay cell = -4
7283 00:57:07.150735 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7284 00:57:07.153895 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7285 00:57:07.157299 [-4] AVG Duty = 5000%(X100)
7286 00:57:07.157381
7287 00:57:07.160602 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7288 00:57:07.160713
7289 00:57:07.163918 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7290 00:57:07.167223 [DutyScan_Calibration_Flow] ====Done====
7291 00:57:07.167304
7292 00:57:07.170473 [DutyScan_Calibration_Flow] k_type=3
7293 00:57:07.188368
7294 00:57:07.188447 ==DQM 0 ==
7295 00:57:07.191653 Final DQM duty delay cell = 0
7296 00:57:07.194794 [0] MAX Duty = 5093%(X100), DQS PI = 26
7297 00:57:07.198017 [0] MIN Duty = 4813%(X100), DQS PI = 52
7298 00:57:07.201346 [0] AVG Duty = 4953%(X100)
7299 00:57:07.201427
7300 00:57:07.201490 ==DQM 1 ==
7301 00:57:07.204569 Final DQM duty delay cell = 0
7302 00:57:07.208038 [0] MAX Duty = 5249%(X100), DQS PI = 28
7303 00:57:07.211407 [0] MIN Duty = 5000%(X100), DQS PI = 20
7304 00:57:07.214501 [0] AVG Duty = 5124%(X100)
7305 00:57:07.214576
7306 00:57:07.217821 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7307 00:57:07.217920
7308 00:57:07.221378 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7309 00:57:07.224746 [DutyScan_Calibration_Flow] ====Done====
7310 00:57:07.224818
7311 00:57:07.227743 [DutyScan_Calibration_Flow] k_type=2
7312 00:57:07.245415
7313 00:57:07.245526 ==DQ 0 ==
7314 00:57:07.248841 Final DQ duty delay cell = 0
7315 00:57:07.252091 [0] MAX Duty = 5124%(X100), DQS PI = 34
7316 00:57:07.255401 [0] MIN Duty = 5000%(X100), DQS PI = 0
7317 00:57:07.255476 [0] AVG Duty = 5062%(X100)
7318 00:57:07.258779
7319 00:57:07.258858 ==DQ 1 ==
7320 00:57:07.261912 Final DQ duty delay cell = 0
7321 00:57:07.265526 [0] MAX Duty = 4969%(X100), DQS PI = 28
7322 00:57:07.268616 [0] MIN Duty = 4875%(X100), DQS PI = 12
7323 00:57:07.268696 [0] AVG Duty = 4922%(X100)
7324 00:57:07.268766
7325 00:57:07.272010 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7326 00:57:07.272083
7327 00:57:07.275511 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7328 00:57:07.282262 [DutyScan_Calibration_Flow] ====Done====
7329 00:57:07.282339 ==
7330 00:57:07.285557 Dram Type= 6, Freq= 0, CH_1, rank 0
7331 00:57:07.288819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 00:57:07.288895 ==
7333 00:57:07.291898 [Duty_Offset_Calibration]
7334 00:57:07.291967 B0:0 B1:-1 CA:2
7335 00:57:07.292027
7336 00:57:07.295363 [DutyScan_Calibration_Flow] k_type=0
7337 00:57:07.305305
7338 00:57:07.305404 ==CLK 0==
7339 00:57:07.309254 Final CLK duty delay cell = 0
7340 00:57:07.312302 [0] MAX Duty = 5156%(X100), DQS PI = 10
7341 00:57:07.315595 [0] MIN Duty = 4906%(X100), DQS PI = 46
7342 00:57:07.315675 [0] AVG Duty = 5031%(X100)
7343 00:57:07.318871
7344 00:57:07.322391 CH1 CLK Duty spec in!! Max-Min= 250%
7345 00:57:07.325281 [DutyScan_Calibration_Flow] ====Done====
7346 00:57:07.325361
7347 00:57:07.329039 [DutyScan_Calibration_Flow] k_type=1
7348 00:57:07.345477
7349 00:57:07.345556 ==DQS 0 ==
7350 00:57:07.348796 Final DQS duty delay cell = 0
7351 00:57:07.351772 [0] MAX Duty = 5124%(X100), DQS PI = 26
7352 00:57:07.355382 [0] MIN Duty = 4969%(X100), DQS PI = 0
7353 00:57:07.355541 [0] AVG Duty = 5046%(X100)
7354 00:57:07.358847
7355 00:57:07.358928 ==DQS 1 ==
7356 00:57:07.361972 Final DQS duty delay cell = 0
7357 00:57:07.365263 [0] MAX Duty = 5156%(X100), DQS PI = 0
7358 00:57:07.368445 [0] MIN Duty = 4844%(X100), DQS PI = 34
7359 00:57:07.368526 [0] AVG Duty = 5000%(X100)
7360 00:57:07.372121
7361 00:57:07.375348 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7362 00:57:07.375429
7363 00:57:07.378591 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7364 00:57:07.382403 [DutyScan_Calibration_Flow] ====Done====
7365 00:57:07.382484
7366 00:57:07.385216 [DutyScan_Calibration_Flow] k_type=3
7367 00:57:07.402890
7368 00:57:07.402970 ==DQM 0 ==
7369 00:57:07.406207 Final DQM duty delay cell = 4
7370 00:57:07.409308 [4] MAX Duty = 5156%(X100), DQS PI = 24
7371 00:57:07.413019 [4] MIN Duty = 4969%(X100), DQS PI = 48
7372 00:57:07.416335 [4] AVG Duty = 5062%(X100)
7373 00:57:07.416417
7374 00:57:07.416481 ==DQM 1 ==
7375 00:57:07.419911 Final DQM duty delay cell = 0
7376 00:57:07.422802 [0] MAX Duty = 5281%(X100), DQS PI = 58
7377 00:57:07.426253 [0] MIN Duty = 4876%(X100), DQS PI = 34
7378 00:57:07.429638 [0] AVG Duty = 5078%(X100)
7379 00:57:07.429719
7380 00:57:07.432837 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7381 00:57:07.432952
7382 00:57:07.436437 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7383 00:57:07.439296 [DutyScan_Calibration_Flow] ====Done====
7384 00:57:07.439377
7385 00:57:07.442680 [DutyScan_Calibration_Flow] k_type=2
7386 00:57:07.459893
7387 00:57:07.459980 ==DQ 0 ==
7388 00:57:07.463268 Final DQ duty delay cell = 0
7389 00:57:07.466387 [0] MAX Duty = 5062%(X100), DQS PI = 16
7390 00:57:07.469625 [0] MIN Duty = 4969%(X100), DQS PI = 46
7391 00:57:07.469709 [0] AVG Duty = 5015%(X100)
7392 00:57:07.472996
7393 00:57:07.473079 ==DQ 1 ==
7394 00:57:07.476417 Final DQ duty delay cell = 0
7395 00:57:07.479594 [0] MAX Duty = 5062%(X100), DQS PI = 2
7396 00:57:07.482981 [0] MIN Duty = 4813%(X100), DQS PI = 34
7397 00:57:07.483083 [0] AVG Duty = 4937%(X100)
7398 00:57:07.483150
7399 00:57:07.486507 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7400 00:57:07.490000
7401 00:57:07.492892 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7402 00:57:07.496476 [DutyScan_Calibration_Flow] ====Done====
7403 00:57:07.499439 nWR fixed to 30
7404 00:57:07.499523 [ModeRegInit_LP4] CH0 RK0
7405 00:57:07.503000 [ModeRegInit_LP4] CH0 RK1
7406 00:57:07.506091 [ModeRegInit_LP4] CH1 RK0
7407 00:57:07.506200 [ModeRegInit_LP4] CH1 RK1
7408 00:57:07.509818 match AC timing 5
7409 00:57:07.513109 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7410 00:57:07.516371 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7411 00:57:07.522993 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7412 00:57:07.526579 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7413 00:57:07.533085 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7414 00:57:07.533186 [MiockJmeterHQA]
7415 00:57:07.533285
7416 00:57:07.536261 [DramcMiockJmeter] u1RxGatingPI = 0
7417 00:57:07.539494 0 : 4258, 4029
7418 00:57:07.539595 4 : 4252, 4027
7419 00:57:07.539678 8 : 4252, 4027
7420 00:57:07.543018 12 : 4252, 4027
7421 00:57:07.543103 16 : 4252, 4026
7422 00:57:07.546216 20 : 4252, 4027
7423 00:57:07.546318 24 : 4254, 4029
7424 00:57:07.549613 28 : 4363, 4137
7425 00:57:07.549714 32 : 4252, 4027
7426 00:57:07.552814 36 : 4252, 4027
7427 00:57:07.552916 40 : 4253, 4027
7428 00:57:07.553017 44 : 4255, 4029
7429 00:57:07.556033 48 : 4252, 4027
7430 00:57:07.556134 52 : 4366, 4140
7431 00:57:07.559494 56 : 4363, 4137
7432 00:57:07.559603 60 : 4253, 4027
7433 00:57:07.562814 64 : 4250, 4027
7434 00:57:07.562931 68 : 4250, 4027
7435 00:57:07.563030 72 : 4250, 4027
7436 00:57:07.566058 76 : 4252, 4029
7437 00:57:07.566145 80 : 4360, 4138
7438 00:57:07.569393 84 : 4250, 4027
7439 00:57:07.569494 88 : 4250, 3704
7440 00:57:07.572853 92 : 4250, 0
7441 00:57:07.572954 96 : 4360, 0
7442 00:57:07.573053 100 : 4252, 0
7443 00:57:07.576040 104 : 4252, 0
7444 00:57:07.576142 108 : 4250, 0
7445 00:57:07.579404 112 : 4250, 0
7446 00:57:07.579505 116 : 4252, 0
7447 00:57:07.579605 120 : 4360, 0
7448 00:57:07.582970 124 : 4361, 0
7449 00:57:07.583055 128 : 4362, 0
7450 00:57:07.583122 132 : 4250, 0
7451 00:57:07.586090 136 : 4250, 0
7452 00:57:07.586175 140 : 4250, 0
7453 00:57:07.589327 144 : 4252, 0
7454 00:57:07.589411 148 : 4250, 0
7455 00:57:07.589478 152 : 4250, 0
7456 00:57:07.592947 156 : 4252, 0
7457 00:57:07.593032 160 : 4250, 0
7458 00:57:07.595998 164 : 4250, 0
7459 00:57:07.596082 168 : 4250, 0
7460 00:57:07.596149 172 : 4360, 0
7461 00:57:07.599837 176 : 4361, 0
7462 00:57:07.599922 180 : 4363, 0
7463 00:57:07.602549 184 : 4250, 0
7464 00:57:07.602647 188 : 4361, 0
7465 00:57:07.602714 192 : 4250, 0
7466 00:57:07.606183 196 : 4250, 0
7467 00:57:07.606268 200 : 4250, 2
7468 00:57:07.609265 204 : 4361, 2320
7469 00:57:07.609350 208 : 4250, 4027
7470 00:57:07.609417 212 : 4360, 4138
7471 00:57:07.612729 216 : 4249, 4027
7472 00:57:07.612814 220 : 4250, 4026
7473 00:57:07.616034 224 : 4361, 4137
7474 00:57:07.616119 228 : 4250, 4027
7475 00:57:07.619478 232 : 4253, 4027
7476 00:57:07.619562 236 : 4363, 4140
7477 00:57:07.622873 240 : 4250, 4026
7478 00:57:07.622957 244 : 4250, 4027
7479 00:57:07.625855 248 : 4250, 4027
7480 00:57:07.625960 252 : 4252, 4029
7481 00:57:07.629194 256 : 4250, 4026
7482 00:57:07.629278 260 : 4250, 4027
7483 00:57:07.632793 264 : 4363, 4138
7484 00:57:07.632893 268 : 4249, 4027
7485 00:57:07.632960 272 : 4250, 4026
7486 00:57:07.635981 276 : 4361, 4137
7487 00:57:07.636066 280 : 4250, 4027
7488 00:57:07.639742 284 : 4249, 4027
7489 00:57:07.639826 288 : 4363, 4140
7490 00:57:07.642622 292 : 4250, 4026
7491 00:57:07.642707 296 : 4250, 4027
7492 00:57:07.645836 300 : 4250, 4027
7493 00:57:07.645921 304 : 4252, 4029
7494 00:57:07.649237 308 : 4250, 4026
7495 00:57:07.649321 312 : 4250, 3974
7496 00:57:07.652599 316 : 4360, 2154
7497 00:57:07.652684
7498 00:57:07.652750 MIOCK jitter meter ch=0
7499 00:57:07.652812
7500 00:57:07.655668 1T = (316-92) = 224 dly cells
7501 00:57:07.662457 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7502 00:57:07.662540 ==
7503 00:57:07.665858 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 00:57:07.669087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 00:57:07.669171 ==
7506 00:57:07.675707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 00:57:07.679360 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 00:57:07.682665 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 00:57:07.689142 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 00:57:07.698797 [CA 0] Center 42 (12~73) winsize 62
7511 00:57:07.702023 [CA 1] Center 43 (13~73) winsize 61
7512 00:57:07.705342 [CA 2] Center 37 (8~67) winsize 60
7513 00:57:07.708514 [CA 3] Center 37 (8~67) winsize 60
7514 00:57:07.711939 [CA 4] Center 36 (6~66) winsize 61
7515 00:57:07.715056 [CA 5] Center 35 (5~65) winsize 61
7516 00:57:07.715142
7517 00:57:07.719120 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 00:57:07.719207
7519 00:57:07.721891 [CATrainingPosCal] consider 1 rank data
7520 00:57:07.725125 u2DelayCellTimex100 = 290/100 ps
7521 00:57:07.728853 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 00:57:07.735378 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7523 00:57:07.738702 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 00:57:07.742060 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7525 00:57:07.745303 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7526 00:57:07.748462 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7527 00:57:07.748548
7528 00:57:07.752061 CA PerBit enable=1, Macro0, CA PI delay=35
7529 00:57:07.752148
7530 00:57:07.755376 [CBTSetCACLKResult] CA Dly = 35
7531 00:57:07.755462 CS Dly: 9 (0~40)
7532 00:57:07.761923 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 00:57:07.765059 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 00:57:07.765145 ==
7535 00:57:07.768447 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 00:57:07.771615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 00:57:07.771702 ==
7538 00:57:07.778356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 00:57:07.781543 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 00:57:07.788344 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 00:57:07.791605 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 00:57:07.801778 [CA 0] Center 43 (13~73) winsize 61
7543 00:57:07.805046 [CA 1] Center 43 (13~73) winsize 61
7544 00:57:07.808200 [CA 2] Center 37 (8~67) winsize 60
7545 00:57:07.811784 [CA 3] Center 38 (9~68) winsize 60
7546 00:57:07.815466 [CA 4] Center 36 (6~67) winsize 62
7547 00:57:07.818722 [CA 5] Center 36 (6~66) winsize 61
7548 00:57:07.818808
7549 00:57:07.821645 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7550 00:57:07.821738
7551 00:57:07.825358 [CATrainingPosCal] consider 2 rank data
7552 00:57:07.828754 u2DelayCellTimex100 = 290/100 ps
7553 00:57:07.831999 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7554 00:57:07.838387 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7555 00:57:07.841687 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7556 00:57:07.845148 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7557 00:57:07.848676 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 00:57:07.851849 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7559 00:57:07.851938
7560 00:57:07.855304 CA PerBit enable=1, Macro0, CA PI delay=35
7561 00:57:07.855393
7562 00:57:07.858172 [CBTSetCACLKResult] CA Dly = 35
7563 00:57:07.861411 CS Dly: 10 (0~43)
7564 00:57:07.864748 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 00:57:07.868554 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 00:57:07.868643
7567 00:57:07.871684 ----->DramcWriteLeveling(PI) begin...
7568 00:57:07.871773 ==
7569 00:57:07.875032 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 00:57:07.878508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 00:57:07.881787 ==
7572 00:57:07.881875 Write leveling (Byte 0): 37 => 37
7573 00:57:07.884862 Write leveling (Byte 1): 29 => 29
7574 00:57:07.888457 DramcWriteLeveling(PI) end<-----
7575 00:57:07.888546
7576 00:57:07.888633 ==
7577 00:57:07.891482 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 00:57:07.898185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 00:57:07.898274 ==
7580 00:57:07.901772 [Gating] SW mode calibration
7581 00:57:07.908337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 00:57:07.911514 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 00:57:07.918013 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 00:57:07.921599 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 00:57:07.924780 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7586 00:57:07.928416 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7587 00:57:07.934902 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7588 00:57:07.938296 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7589 00:57:07.941477 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 00:57:07.948107 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 00:57:07.951455 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 00:57:07.954891 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 00:57:07.961331 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7594 00:57:07.964548 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7595 00:57:07.968310 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7596 00:57:07.974917 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7597 00:57:07.978114 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 00:57:07.981446 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 00:57:07.988313 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 00:57:07.991557 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7601 00:57:07.994509 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7602 00:57:08.001140 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7603 00:57:08.004429 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7604 00:57:08.007690 1 6 20 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7605 00:57:08.014309 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 00:57:08.018020 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 00:57:08.020969 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 00:57:08.027910 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 00:57:08.031111 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 00:57:08.034410 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 00:57:08.041232 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7612 00:57:08.044600 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 00:57:08.047779 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 00:57:08.051025 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 00:57:08.057840 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 00:57:08.061190 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 00:57:08.064409 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 00:57:08.070938 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 00:57:08.074572 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 00:57:08.077971 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 00:57:08.084580 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 00:57:08.087762 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 00:57:08.091585 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 00:57:08.097813 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 00:57:08.101203 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 00:57:08.104472 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 00:57:08.110771 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 00:57:08.110863 Total UI for P1: 0, mck2ui 16
7629 00:57:08.117734 best dqsien dly found for B0: ( 1, 9, 8)
7630 00:57:08.121032 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 00:57:08.124226 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 00:57:08.127595 Total UI for P1: 0, mck2ui 16
7633 00:57:08.131224 best dqsien dly found for B1: ( 1, 9, 18)
7634 00:57:08.134231 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7635 00:57:08.137832 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7636 00:57:08.137951
7637 00:57:08.141054 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7638 00:57:08.147844 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7639 00:57:08.147966 [Gating] SW calibration Done
7640 00:57:08.151189 ==
7641 00:57:08.151295 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 00:57:08.157699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 00:57:08.157803 ==
7644 00:57:08.157904 RX Vref Scan: 0
7645 00:57:08.158018
7646 00:57:08.160808 RX Vref 0 -> 0, step: 1
7647 00:57:08.160908
7648 00:57:08.164106 RX Delay 0 -> 252, step: 8
7649 00:57:08.167655 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7650 00:57:08.170998 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7651 00:57:08.174833 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7652 00:57:08.181074 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7653 00:57:08.184415 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7654 00:57:08.187670 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7655 00:57:08.191132 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7656 00:57:08.194300 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7657 00:57:08.197404 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7658 00:57:08.204220 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7659 00:57:08.207228 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7660 00:57:08.211111 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7661 00:57:08.214122 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7662 00:57:08.220718 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7663 00:57:08.224257 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7664 00:57:08.227290 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7665 00:57:08.227395 ==
7666 00:57:08.230869 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 00:57:08.234308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 00:57:08.234411 ==
7669 00:57:08.237330 DQS Delay:
7670 00:57:08.237439 DQS0 = 0, DQS1 = 0
7671 00:57:08.237534 DQM Delay:
7672 00:57:08.240831 DQM0 = 138, DQM1 = 127
7673 00:57:08.240930 DQ Delay:
7674 00:57:08.243927 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7675 00:57:08.247425 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7676 00:57:08.253789 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7677 00:57:08.257022 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7678 00:57:08.257099
7679 00:57:08.257166
7680 00:57:08.257224 ==
7681 00:57:08.260443 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 00:57:08.264060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 00:57:08.264136 ==
7684 00:57:08.264199
7685 00:57:08.264273
7686 00:57:08.267203 TX Vref Scan disable
7687 00:57:08.270968 == TX Byte 0 ==
7688 00:57:08.273721 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7689 00:57:08.277411 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7690 00:57:08.280429 == TX Byte 1 ==
7691 00:57:08.283984 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7692 00:57:08.287523 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7693 00:57:08.287596 ==
7694 00:57:08.290832 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 00:57:08.294236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 00:57:08.294312 ==
7697 00:57:08.308603
7698 00:57:08.312060 TX Vref early break, caculate TX vref
7699 00:57:08.315118 TX Vref=16, minBit 12, minWin=22, winSum=376
7700 00:57:08.318517 TX Vref=18, minBit 8, minWin=23, winSum=389
7701 00:57:08.322292 TX Vref=20, minBit 12, minWin=23, winSum=398
7702 00:57:08.325531 TX Vref=22, minBit 12, minWin=24, winSum=409
7703 00:57:08.328510 TX Vref=24, minBit 0, minWin=25, winSum=412
7704 00:57:08.335115 TX Vref=26, minBit 0, minWin=26, winSum=427
7705 00:57:08.338664 TX Vref=28, minBit 2, minWin=25, winSum=433
7706 00:57:08.342114 TX Vref=30, minBit 0, minWin=26, winSum=424
7707 00:57:08.345496 TX Vref=32, minBit 1, minWin=25, winSum=416
7708 00:57:08.348936 TX Vref=34, minBit 9, minWin=24, winSum=409
7709 00:57:08.355344 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
7710 00:57:08.355464
7711 00:57:08.358627 Final TX Range 0 Vref 26
7712 00:57:08.358717
7713 00:57:08.358815 ==
7714 00:57:08.362200 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 00:57:08.365347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 00:57:08.365462 ==
7717 00:57:08.365582
7718 00:57:08.365700
7719 00:57:08.368846 TX Vref Scan disable
7720 00:57:08.375390 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7721 00:57:08.375509 == TX Byte 0 ==
7722 00:57:08.378715 u2DelayCellOfst[0]=13 cells (4 PI)
7723 00:57:08.381844 u2DelayCellOfst[1]=20 cells (6 PI)
7724 00:57:08.385125 u2DelayCellOfst[2]=13 cells (4 PI)
7725 00:57:08.388377 u2DelayCellOfst[3]=13 cells (4 PI)
7726 00:57:08.391647 u2DelayCellOfst[4]=10 cells (3 PI)
7727 00:57:08.395400 u2DelayCellOfst[5]=0 cells (0 PI)
7728 00:57:08.398596 u2DelayCellOfst[6]=20 cells (6 PI)
7729 00:57:08.401665 u2DelayCellOfst[7]=16 cells (5 PI)
7730 00:57:08.405128 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7731 00:57:08.408633 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7732 00:57:08.411769 == TX Byte 1 ==
7733 00:57:08.411859 u2DelayCellOfst[8]=0 cells (0 PI)
7734 00:57:08.415004 u2DelayCellOfst[9]=0 cells (0 PI)
7735 00:57:08.418286 u2DelayCellOfst[10]=6 cells (2 PI)
7736 00:57:08.422009 u2DelayCellOfst[11]=3 cells (1 PI)
7737 00:57:08.424924 u2DelayCellOfst[12]=13 cells (4 PI)
7738 00:57:08.428271 u2DelayCellOfst[13]=10 cells (3 PI)
7739 00:57:08.431882 u2DelayCellOfst[14]=16 cells (5 PI)
7740 00:57:08.434933 u2DelayCellOfst[15]=10 cells (3 PI)
7741 00:57:08.438190 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7742 00:57:08.444949 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7743 00:57:08.445069 DramC Write-DBI on
7744 00:57:08.445199 ==
7745 00:57:08.448457 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 00:57:08.451554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 00:57:08.454787 ==
7748 00:57:08.454878
7749 00:57:08.454973
7750 00:57:08.455076 TX Vref Scan disable
7751 00:57:08.458563 == TX Byte 0 ==
7752 00:57:08.461697 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7753 00:57:08.465288 == TX Byte 1 ==
7754 00:57:08.468305 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7755 00:57:08.471870 DramC Write-DBI off
7756 00:57:08.471976
7757 00:57:08.472072 [DATLAT]
7758 00:57:08.472173 Freq=1600, CH0 RK0
7759 00:57:08.472265
7760 00:57:08.475055 DATLAT Default: 0xf
7761 00:57:08.475143 0, 0xFFFF, sum = 0
7762 00:57:08.478719 1, 0xFFFF, sum = 0
7763 00:57:08.478824 2, 0xFFFF, sum = 0
7764 00:57:08.481636 3, 0xFFFF, sum = 0
7765 00:57:08.485437 4, 0xFFFF, sum = 0
7766 00:57:08.485534 5, 0xFFFF, sum = 0
7767 00:57:08.488612 6, 0xFFFF, sum = 0
7768 00:57:08.488690 7, 0xFFFF, sum = 0
7769 00:57:08.492064 8, 0xFFFF, sum = 0
7770 00:57:08.492183 9, 0xFFFF, sum = 0
7771 00:57:08.495592 10, 0xFFFF, sum = 0
7772 00:57:08.495686 11, 0xFFFF, sum = 0
7773 00:57:08.498603 12, 0xFFFF, sum = 0
7774 00:57:08.498690 13, 0xFFFF, sum = 0
7775 00:57:08.502096 14, 0x0, sum = 1
7776 00:57:08.502184 15, 0x0, sum = 2
7777 00:57:08.505289 16, 0x0, sum = 3
7778 00:57:08.505390 17, 0x0, sum = 4
7779 00:57:08.508691 best_step = 15
7780 00:57:08.508805
7781 00:57:08.508924 ==
7782 00:57:08.511924 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 00:57:08.515330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 00:57:08.515424 ==
7785 00:57:08.515530 RX Vref Scan: 1
7786 00:57:08.515625
7787 00:57:08.518494 Set Vref Range= 24 -> 127
7788 00:57:08.518583
7789 00:57:08.521555 RX Vref 24 -> 127, step: 1
7790 00:57:08.521666
7791 00:57:08.525045 RX Delay 19 -> 252, step: 4
7792 00:57:08.525158
7793 00:57:08.528258 Set Vref, RX VrefLevel [Byte0]: 24
7794 00:57:08.531600 [Byte1]: 24
7795 00:57:08.531699
7796 00:57:08.535193 Set Vref, RX VrefLevel [Byte0]: 25
7797 00:57:08.538535 [Byte1]: 25
7798 00:57:08.538628
7799 00:57:08.542205 Set Vref, RX VrefLevel [Byte0]: 26
7800 00:57:08.544941 [Byte1]: 26
7801 00:57:08.548714
7802 00:57:08.548832 Set Vref, RX VrefLevel [Byte0]: 27
7803 00:57:08.552275 [Byte1]: 27
7804 00:57:08.556409
7805 00:57:08.556514 Set Vref, RX VrefLevel [Byte0]: 28
7806 00:57:08.559464 [Byte1]: 28
7807 00:57:08.564081
7808 00:57:08.564174 Set Vref, RX VrefLevel [Byte0]: 29
7809 00:57:08.567410 [Byte1]: 29
7810 00:57:08.571681
7811 00:57:08.571761 Set Vref, RX VrefLevel [Byte0]: 30
7812 00:57:08.574694 [Byte1]: 30
7813 00:57:08.579147
7814 00:57:08.579231 Set Vref, RX VrefLevel [Byte0]: 31
7815 00:57:08.582421 [Byte1]: 31
7816 00:57:08.586854
7817 00:57:08.586971 Set Vref, RX VrefLevel [Byte0]: 32
7818 00:57:08.590205 [Byte1]: 32
7819 00:57:08.594077
7820 00:57:08.594170 Set Vref, RX VrefLevel [Byte0]: 33
7821 00:57:08.597419 [Byte1]: 33
7822 00:57:08.601828
7823 00:57:08.601943 Set Vref, RX VrefLevel [Byte0]: 34
7824 00:57:08.605161 [Byte1]: 34
7825 00:57:08.609166
7826 00:57:08.609266 Set Vref, RX VrefLevel [Byte0]: 35
7827 00:57:08.613051 [Byte1]: 35
7828 00:57:08.617015
7829 00:57:08.617088 Set Vref, RX VrefLevel [Byte0]: 36
7830 00:57:08.620240 [Byte1]: 36
7831 00:57:08.624404
7832 00:57:08.624503 Set Vref, RX VrefLevel [Byte0]: 37
7833 00:57:08.627909 [Byte1]: 37
7834 00:57:08.632055
7835 00:57:08.632161 Set Vref, RX VrefLevel [Byte0]: 38
7836 00:57:08.635554 [Byte1]: 38
7837 00:57:08.639749
7838 00:57:08.639852 Set Vref, RX VrefLevel [Byte0]: 39
7839 00:57:08.642988 [Byte1]: 39
7840 00:57:08.647024
7841 00:57:08.647126 Set Vref, RX VrefLevel [Byte0]: 40
7842 00:57:08.653579 [Byte1]: 40
7843 00:57:08.653691
7844 00:57:08.657201 Set Vref, RX VrefLevel [Byte0]: 41
7845 00:57:08.660284 [Byte1]: 41
7846 00:57:08.660390
7847 00:57:08.663812 Set Vref, RX VrefLevel [Byte0]: 42
7848 00:57:08.666915 [Byte1]: 42
7849 00:57:08.667017
7850 00:57:08.670248 Set Vref, RX VrefLevel [Byte0]: 43
7851 00:57:08.673823 [Byte1]: 43
7852 00:57:08.677445
7853 00:57:08.677551 Set Vref, RX VrefLevel [Byte0]: 44
7854 00:57:08.680647 [Byte1]: 44
7855 00:57:08.685120
7856 00:57:08.685225 Set Vref, RX VrefLevel [Byte0]: 45
7857 00:57:08.688312 [Byte1]: 45
7858 00:57:08.693000
7859 00:57:08.693100 Set Vref, RX VrefLevel [Byte0]: 46
7860 00:57:08.696266 [Byte1]: 46
7861 00:57:08.700067
7862 00:57:08.700173 Set Vref, RX VrefLevel [Byte0]: 47
7863 00:57:08.703490 [Byte1]: 47
7864 00:57:08.708128
7865 00:57:08.708227 Set Vref, RX VrefLevel [Byte0]: 48
7866 00:57:08.711356 [Byte1]: 48
7867 00:57:08.715527
7868 00:57:08.715631 Set Vref, RX VrefLevel [Byte0]: 49
7869 00:57:08.718818 [Byte1]: 49
7870 00:57:08.722840
7871 00:57:08.722945 Set Vref, RX VrefLevel [Byte0]: 50
7872 00:57:08.726342 [Byte1]: 50
7873 00:57:08.730739
7874 00:57:08.730838 Set Vref, RX VrefLevel [Byte0]: 51
7875 00:57:08.733738 [Byte1]: 51
7876 00:57:08.738051
7877 00:57:08.738128 Set Vref, RX VrefLevel [Byte0]: 52
7878 00:57:08.741452 [Byte1]: 52
7879 00:57:08.746396
7880 00:57:08.746472 Set Vref, RX VrefLevel [Byte0]: 53
7881 00:57:08.748930 [Byte1]: 53
7882 00:57:08.753163
7883 00:57:08.753269 Set Vref, RX VrefLevel [Byte0]: 54
7884 00:57:08.757032 [Byte1]: 54
7885 00:57:08.760901
7886 00:57:08.761007 Set Vref, RX VrefLevel [Byte0]: 55
7887 00:57:08.764347 [Byte1]: 55
7888 00:57:08.768294
7889 00:57:08.768398 Set Vref, RX VrefLevel [Byte0]: 56
7890 00:57:08.771767 [Byte1]: 56
7891 00:57:08.775745
7892 00:57:08.775847 Set Vref, RX VrefLevel [Byte0]: 57
7893 00:57:08.779296 [Byte1]: 57
7894 00:57:08.783385
7895 00:57:08.783465 Set Vref, RX VrefLevel [Byte0]: 58
7896 00:57:08.786951 [Byte1]: 58
7897 00:57:08.790956
7898 00:57:08.791041 Set Vref, RX VrefLevel [Byte0]: 59
7899 00:57:08.794663 [Byte1]: 59
7900 00:57:08.798776
7901 00:57:08.798861 Set Vref, RX VrefLevel [Byte0]: 60
7902 00:57:08.801988 [Byte1]: 60
7903 00:57:08.806766
7904 00:57:08.806850 Set Vref, RX VrefLevel [Byte0]: 61
7905 00:57:08.809672 [Byte1]: 61
7906 00:57:08.813910
7907 00:57:08.814001 Set Vref, RX VrefLevel [Byte0]: 62
7908 00:57:08.817279 [Byte1]: 62
7909 00:57:08.821311
7910 00:57:08.821396 Set Vref, RX VrefLevel [Byte0]: 63
7911 00:57:08.824556 [Byte1]: 63
7912 00:57:08.828937
7913 00:57:08.829022 Set Vref, RX VrefLevel [Byte0]: 64
7914 00:57:08.832755 [Byte1]: 64
7915 00:57:08.836490
7916 00:57:08.836576 Set Vref, RX VrefLevel [Byte0]: 65
7917 00:57:08.839955 [Byte1]: 65
7918 00:57:08.844156
7919 00:57:08.844260 Set Vref, RX VrefLevel [Byte0]: 66
7920 00:57:08.847505 [Byte1]: 66
7921 00:57:08.851679
7922 00:57:08.851765 Set Vref, RX VrefLevel [Byte0]: 67
7923 00:57:08.854970 [Byte1]: 67
7924 00:57:08.859343
7925 00:57:08.859426 Set Vref, RX VrefLevel [Byte0]: 68
7926 00:57:08.862597 [Byte1]: 68
7927 00:57:08.866892
7928 00:57:08.866969 Set Vref, RX VrefLevel [Byte0]: 69
7929 00:57:08.870094 [Byte1]: 69
7930 00:57:08.874711
7931 00:57:08.874799 Set Vref, RX VrefLevel [Byte0]: 70
7932 00:57:08.877758 [Byte1]: 70
7933 00:57:08.882063
7934 00:57:08.882162 Set Vref, RX VrefLevel [Byte0]: 71
7935 00:57:08.885286 [Byte1]: 71
7936 00:57:08.889445
7937 00:57:08.889551 Set Vref, RX VrefLevel [Byte0]: 72
7938 00:57:08.892868 [Byte1]: 72
7939 00:57:08.897148
7940 00:57:08.897290 Set Vref, RX VrefLevel [Byte0]: 73
7941 00:57:08.900383 [Byte1]: 73
7942 00:57:08.904629
7943 00:57:08.904722 Set Vref, RX VrefLevel [Byte0]: 74
7944 00:57:08.908301 [Byte1]: 74
7945 00:57:08.912212
7946 00:57:08.912311 Set Vref, RX VrefLevel [Byte0]: 75
7947 00:57:08.915467 [Byte1]: 75
7948 00:57:08.919940
7949 00:57:08.920033 Set Vref, RX VrefLevel [Byte0]: 76
7950 00:57:08.923231 [Byte1]: 76
7951 00:57:08.927269
7952 00:57:08.927374 Set Vref, RX VrefLevel [Byte0]: 77
7953 00:57:08.930474 [Byte1]: 77
7954 00:57:08.935122
7955 00:57:08.935217 Set Vref, RX VrefLevel [Byte0]: 78
7956 00:57:08.938180 [Byte1]: 78
7957 00:57:08.942609
7958 00:57:08.942709 Set Vref, RX VrefLevel [Byte0]: 79
7959 00:57:08.945676 [Byte1]: 79
7960 00:57:08.949885
7961 00:57:08.950006 Set Vref, RX VrefLevel [Byte0]: 80
7962 00:57:08.953535 [Byte1]: 80
7963 00:57:08.957857
7964 00:57:08.957964 Final RX Vref Byte 0 = 60 to rank0
7965 00:57:08.961165 Final RX Vref Byte 1 = 62 to rank0
7966 00:57:08.964305 Final RX Vref Byte 0 = 60 to rank1
7967 00:57:08.967893 Final RX Vref Byte 1 = 62 to rank1==
7968 00:57:08.971184 Dram Type= 6, Freq= 0, CH_0, rank 0
7969 00:57:08.977816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 00:57:08.977901 ==
7971 00:57:08.978006 DQS Delay:
7972 00:57:08.978098 DQS0 = 0, DQS1 = 0
7973 00:57:08.980860 DQM Delay:
7974 00:57:08.980944 DQM0 = 136, DQM1 = 124
7975 00:57:08.984250 DQ Delay:
7976 00:57:08.987704 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7977 00:57:08.990838 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7978 00:57:08.994206 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
7979 00:57:08.997753 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
7980 00:57:08.997838
7981 00:57:08.997904
7982 00:57:08.998004
7983 00:57:09.000679 [DramC_TX_OE_Calibration] TA2
7984 00:57:09.004027 Original DQ_B0 (3 6) =30, OEN = 27
7985 00:57:09.007749 Original DQ_B1 (3 6) =30, OEN = 27
7986 00:57:09.010683 24, 0x0, End_B0=24 End_B1=24
7987 00:57:09.010769 25, 0x0, End_B0=25 End_B1=25
7988 00:57:09.013979 26, 0x0, End_B0=26 End_B1=26
7989 00:57:09.017688 27, 0x0, End_B0=27 End_B1=27
7990 00:57:09.021028 28, 0x0, End_B0=28 End_B1=28
7991 00:57:09.021116 29, 0x0, End_B0=29 End_B1=29
7992 00:57:09.024397 30, 0x0, End_B0=30 End_B1=30
7993 00:57:09.027366 31, 0x4141, End_B0=30 End_B1=30
7994 00:57:09.030980 Byte0 end_step=30 best_step=27
7995 00:57:09.034209 Byte1 end_step=30 best_step=27
7996 00:57:09.037482 Byte0 TX OE(2T, 0.5T) = (3, 3)
7997 00:57:09.037568 Byte1 TX OE(2T, 0.5T) = (3, 3)
7998 00:57:09.040795
7999 00:57:09.040881
8000 00:57:09.047402 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8001 00:57:09.051055 CH0 RK0: MR19=303, MR18=1F1D
8002 00:57:09.057328 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8003 00:57:09.057415
8004 00:57:09.060924 ----->DramcWriteLeveling(PI) begin...
8005 00:57:09.061012 ==
8006 00:57:09.064125 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 00:57:09.067383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 00:57:09.067469 ==
8009 00:57:09.070932 Write leveling (Byte 0): 36 => 36
8010 00:57:09.074028 Write leveling (Byte 1): 28 => 28
8011 00:57:09.077528 DramcWriteLeveling(PI) end<-----
8012 00:57:09.077614
8013 00:57:09.077682 ==
8014 00:57:09.081077 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 00:57:09.083913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 00:57:09.083999 ==
8017 00:57:09.087365 [Gating] SW mode calibration
8018 00:57:09.093892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8019 00:57:09.101012 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8020 00:57:09.104698 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 00:57:09.107246 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 00:57:09.113960 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 00:57:09.117147 1 4 12 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
8024 00:57:09.120700 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 00:57:09.127117 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 00:57:09.130318 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 00:57:09.134020 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 00:57:09.140471 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 00:57:09.143702 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 00:57:09.147017 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 00:57:09.153494 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
8032 00:57:09.156795 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8033 00:57:09.160519 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 00:57:09.167226 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 00:57:09.170439 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 00:57:09.173714 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 00:57:09.180235 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 00:57:09.183427 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8039 00:57:09.186677 1 6 12 | B1->B0 | 3333 4545 | 0 0 | (1 1) (0 0)
8040 00:57:09.193499 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 00:57:09.196796 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 00:57:09.200333 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 00:57:09.206972 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 00:57:09.210219 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 00:57:09.213573 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 00:57:09.216960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 00:57:09.223602 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8048 00:57:09.226859 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 00:57:09.230548 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 00:57:09.236963 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 00:57:09.240455 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 00:57:09.243745 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 00:57:09.250337 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 00:57:09.253497 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 00:57:09.256864 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 00:57:09.263574 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 00:57:09.266875 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 00:57:09.270253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 00:57:09.276728 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 00:57:09.280349 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 00:57:09.283680 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 00:57:09.290113 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 00:57:09.293667 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8064 00:57:09.297043 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8065 00:57:09.300224 Total UI for P1: 0, mck2ui 16
8066 00:57:09.303335 best dqsien dly found for B0: ( 1, 9, 10)
8067 00:57:09.306802 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 00:57:09.310323 Total UI for P1: 0, mck2ui 16
8069 00:57:09.313252 best dqsien dly found for B1: ( 1, 9, 14)
8070 00:57:09.320136 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8071 00:57:09.323174 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8072 00:57:09.323258
8073 00:57:09.326603 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8074 00:57:09.329856 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8075 00:57:09.333575 [Gating] SW calibration Done
8076 00:57:09.333693 ==
8077 00:57:09.336711 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 00:57:09.339963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 00:57:09.340065 ==
8080 00:57:09.343269 RX Vref Scan: 0
8081 00:57:09.343368
8082 00:57:09.343448 RX Vref 0 -> 0, step: 1
8083 00:57:09.343510
8084 00:57:09.346489 RX Delay 0 -> 252, step: 8
8085 00:57:09.350232 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8086 00:57:09.353409 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8087 00:57:09.359961 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8088 00:57:09.363256 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8089 00:57:09.366449 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8090 00:57:09.369886 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8091 00:57:09.373234 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8092 00:57:09.379786 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8093 00:57:09.382927 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8094 00:57:09.386806 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8095 00:57:09.389839 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8096 00:57:09.393438 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8097 00:57:09.399912 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8098 00:57:09.403497 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8099 00:57:09.406604 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8100 00:57:09.409837 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8101 00:57:09.409955 ==
8102 00:57:09.413433 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 00:57:09.419901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 00:57:09.419988 ==
8105 00:57:09.420056 DQS Delay:
8106 00:57:09.423213 DQS0 = 0, DQS1 = 0
8107 00:57:09.423297 DQM Delay:
8108 00:57:09.423364 DQM0 = 136, DQM1 = 125
8109 00:57:09.426846 DQ Delay:
8110 00:57:09.429626 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8111 00:57:09.432885 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8112 00:57:09.436582 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8113 00:57:09.439681 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8114 00:57:09.439768
8115 00:57:09.439835
8116 00:57:09.439898 ==
8117 00:57:09.442912 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 00:57:09.446505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 00:57:09.449809 ==
8120 00:57:09.449899
8121 00:57:09.450007
8122 00:57:09.450106 TX Vref Scan disable
8123 00:57:09.453188 == TX Byte 0 ==
8124 00:57:09.456425 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8125 00:57:09.459800 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8126 00:57:09.462985 == TX Byte 1 ==
8127 00:57:09.466085 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8128 00:57:09.469712 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8129 00:57:09.473053 ==
8130 00:57:09.476367 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 00:57:09.479403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 00:57:09.479491 ==
8133 00:57:09.493879
8134 00:57:09.497261 TX Vref early break, caculate TX vref
8135 00:57:09.500820 TX Vref=16, minBit 2, minWin=23, winSum=390
8136 00:57:09.504265 TX Vref=18, minBit 0, minWin=24, winSum=401
8137 00:57:09.507418 TX Vref=20, minBit 0, minWin=24, winSum=402
8138 00:57:09.510389 TX Vref=22, minBit 0, minWin=25, winSum=415
8139 00:57:09.513798 TX Vref=24, minBit 1, minWin=25, winSum=423
8140 00:57:09.520327 TX Vref=26, minBit 1, minWin=26, winSum=427
8141 00:57:09.523682 TX Vref=28, minBit 2, minWin=25, winSum=430
8142 00:57:09.526974 TX Vref=30, minBit 2, minWin=25, winSum=427
8143 00:57:09.530581 TX Vref=32, minBit 0, minWin=25, winSum=417
8144 00:57:09.533817 TX Vref=34, minBit 0, minWin=25, winSum=410
8145 00:57:09.536858 TX Vref=36, minBit 2, minWin=23, winSum=401
8146 00:57:09.543683 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26
8147 00:57:09.543764
8148 00:57:09.546965 Final TX Range 0 Vref 26
8149 00:57:09.547039
8150 00:57:09.547118 ==
8151 00:57:09.550591 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 00:57:09.553499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 00:57:09.553588 ==
8154 00:57:09.553666
8155 00:57:09.556574
8156 00:57:09.556687 TX Vref Scan disable
8157 00:57:09.563487 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8158 00:57:09.563597 == TX Byte 0 ==
8159 00:57:09.566655 u2DelayCellOfst[0]=10 cells (3 PI)
8160 00:57:09.570392 u2DelayCellOfst[1]=16 cells (5 PI)
8161 00:57:09.573472 u2DelayCellOfst[2]=10 cells (3 PI)
8162 00:57:09.576761 u2DelayCellOfst[3]=10 cells (3 PI)
8163 00:57:09.580132 u2DelayCellOfst[4]=6 cells (2 PI)
8164 00:57:09.583587 u2DelayCellOfst[5]=0 cells (0 PI)
8165 00:57:09.586990 u2DelayCellOfst[6]=16 cells (5 PI)
8166 00:57:09.590175 u2DelayCellOfst[7]=16 cells (5 PI)
8167 00:57:09.593547 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8168 00:57:09.596978 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8169 00:57:09.599973 == TX Byte 1 ==
8170 00:57:09.603650 u2DelayCellOfst[8]=0 cells (0 PI)
8171 00:57:09.606601 u2DelayCellOfst[9]=0 cells (0 PI)
8172 00:57:09.606676 u2DelayCellOfst[10]=6 cells (2 PI)
8173 00:57:09.610121 u2DelayCellOfst[11]=3 cells (1 PI)
8174 00:57:09.613335 u2DelayCellOfst[12]=13 cells (4 PI)
8175 00:57:09.616797 u2DelayCellOfst[13]=13 cells (4 PI)
8176 00:57:09.619990 u2DelayCellOfst[14]=16 cells (5 PI)
8177 00:57:09.623374 u2DelayCellOfst[15]=10 cells (3 PI)
8178 00:57:09.626867 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8179 00:57:09.633454 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8180 00:57:09.633559 DramC Write-DBI on
8181 00:57:09.633650 ==
8182 00:57:09.636918 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 00:57:09.643409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 00:57:09.643490 ==
8185 00:57:09.643555
8186 00:57:09.643622
8187 00:57:09.643681 TX Vref Scan disable
8188 00:57:09.647479 == TX Byte 0 ==
8189 00:57:09.650769 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8190 00:57:09.654131 == TX Byte 1 ==
8191 00:57:09.657395 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8192 00:57:09.660484 DramC Write-DBI off
8193 00:57:09.660585
8194 00:57:09.660674 [DATLAT]
8195 00:57:09.660771 Freq=1600, CH0 RK1
8196 00:57:09.660863
8197 00:57:09.664115 DATLAT Default: 0xf
8198 00:57:09.664192 0, 0xFFFF, sum = 0
8199 00:57:09.667127 1, 0xFFFF, sum = 0
8200 00:57:09.667201 2, 0xFFFF, sum = 0
8201 00:57:09.670700 3, 0xFFFF, sum = 0
8202 00:57:09.673599 4, 0xFFFF, sum = 0
8203 00:57:09.673700 5, 0xFFFF, sum = 0
8204 00:57:09.676858 6, 0xFFFF, sum = 0
8205 00:57:09.676936 7, 0xFFFF, sum = 0
8206 00:57:09.680319 8, 0xFFFF, sum = 0
8207 00:57:09.680411 9, 0xFFFF, sum = 0
8208 00:57:09.683847 10, 0xFFFF, sum = 0
8209 00:57:09.683919 11, 0xFFFF, sum = 0
8210 00:57:09.687008 12, 0xFFFF, sum = 0
8211 00:57:09.687088 13, 0xFFFF, sum = 0
8212 00:57:09.690534 14, 0x0, sum = 1
8213 00:57:09.690621 15, 0x0, sum = 2
8214 00:57:09.693747 16, 0x0, sum = 3
8215 00:57:09.693847 17, 0x0, sum = 4
8216 00:57:09.696865 best_step = 15
8217 00:57:09.696936
8218 00:57:09.697001 ==
8219 00:57:09.700456 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 00:57:09.703738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 00:57:09.703813 ==
8222 00:57:09.706992 RX Vref Scan: 0
8223 00:57:09.707093
8224 00:57:09.707154 RX Vref 0 -> 0, step: 1
8225 00:57:09.707212
8226 00:57:09.710386 RX Delay 11 -> 252, step: 4
8227 00:57:09.713683 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8228 00:57:09.720300 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8229 00:57:09.723346 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8230 00:57:09.726746 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8231 00:57:09.730220 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8232 00:57:09.733533 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8233 00:57:09.739877 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8234 00:57:09.743389 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8235 00:57:09.746617 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8236 00:57:09.749978 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8237 00:57:09.753136 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8238 00:57:09.760070 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8239 00:57:09.763312 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8240 00:57:09.766924 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8241 00:57:09.770168 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8242 00:57:09.773108 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8243 00:57:09.776976 ==
8244 00:57:09.779950 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 00:57:09.783097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 00:57:09.783172 ==
8247 00:57:09.783235 DQS Delay:
8248 00:57:09.786664 DQS0 = 0, DQS1 = 0
8249 00:57:09.786737 DQM Delay:
8250 00:57:09.789957 DQM0 = 132, DQM1 = 123
8251 00:57:09.790046 DQ Delay:
8252 00:57:09.793152 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8253 00:57:09.796503 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8254 00:57:09.799691 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8255 00:57:09.803193 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8256 00:57:09.803266
8257 00:57:09.803329
8258 00:57:09.803388
8259 00:57:09.806612 [DramC_TX_OE_Calibration] TA2
8260 00:57:09.809856 Original DQ_B0 (3 6) =30, OEN = 27
8261 00:57:09.813204 Original DQ_B1 (3 6) =30, OEN = 27
8262 00:57:09.816911 24, 0x0, End_B0=24 End_B1=24
8263 00:57:09.819938 25, 0x0, End_B0=25 End_B1=25
8264 00:57:09.820013 26, 0x0, End_B0=26 End_B1=26
8265 00:57:09.823000 27, 0x0, End_B0=27 End_B1=27
8266 00:57:09.826810 28, 0x0, End_B0=28 End_B1=28
8267 00:57:09.829607 29, 0x0, End_B0=29 End_B1=29
8268 00:57:09.833446 30, 0x0, End_B0=30 End_B1=30
8269 00:57:09.833522 31, 0x4141, End_B0=30 End_B1=30
8270 00:57:09.836671 Byte0 end_step=30 best_step=27
8271 00:57:09.839878 Byte1 end_step=30 best_step=27
8272 00:57:09.843049 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 00:57:09.846418 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 00:57:09.846494
8275 00:57:09.846556
8276 00:57:09.852865 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
8277 00:57:09.856251 CH0 RK1: MR19=303, MR18=1D0A
8278 00:57:09.862845 CH0_RK1: MR19=0x303, MR18=0x1D0A, DQSOSC=395, MR23=63, INC=23, DEC=15
8279 00:57:09.866332 [RxdqsGatingPostProcess] freq 1600
8280 00:57:09.872858 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 00:57:09.872934 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 00:57:09.876268 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 00:57:09.879710 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 00:57:09.882873 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 00:57:09.886127 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 00:57:09.889584 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 00:57:09.893052 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 00:57:09.896372 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 00:57:09.899437 Pre-setting of DQS Precalculation
8290 00:57:09.902863 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 00:57:09.902932 ==
8292 00:57:09.906181 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 00:57:09.912543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 00:57:09.912642 ==
8295 00:57:09.915739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 00:57:09.922562 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 00:57:09.926155 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 00:57:09.932399 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 00:57:09.940267 [CA 0] Center 42 (12~72) winsize 61
8300 00:57:09.943581 [CA 1] Center 42 (12~72) winsize 61
8301 00:57:09.946741 [CA 2] Center 38 (9~68) winsize 60
8302 00:57:09.950129 [CA 3] Center 37 (8~67) winsize 60
8303 00:57:09.953473 [CA 4] Center 37 (8~67) winsize 60
8304 00:57:09.957118 [CA 5] Center 37 (7~67) winsize 61
8305 00:57:09.957191
8306 00:57:09.960039 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 00:57:09.960109
8308 00:57:09.963398 [CATrainingPosCal] consider 1 rank data
8309 00:57:09.966936 u2DelayCellTimex100 = 290/100 ps
8310 00:57:09.970173 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8311 00:57:09.976793 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8312 00:57:09.980100 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8313 00:57:09.983455 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8314 00:57:09.986721 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 00:57:09.990127 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8316 00:57:09.990201
8317 00:57:09.993290 CA PerBit enable=1, Macro0, CA PI delay=37
8318 00:57:09.993362
8319 00:57:09.996526 [CBTSetCACLKResult] CA Dly = 37
8320 00:57:10.000050 CS Dly: 8 (0~39)
8321 00:57:10.003480 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 00:57:10.006756 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 00:57:10.006829 ==
8324 00:57:10.009973 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 00:57:10.013082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 00:57:10.013184 ==
8327 00:57:10.019920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 00:57:10.023171 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 00:57:10.030029 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 00:57:10.033291 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 00:57:10.043322 [CA 0] Center 42 (13~72) winsize 60
8332 00:57:10.046582 [CA 1] Center 42 (13~72) winsize 60
8333 00:57:10.050376 [CA 2] Center 39 (10~68) winsize 59
8334 00:57:10.053307 [CA 3] Center 37 (8~67) winsize 60
8335 00:57:10.056550 [CA 4] Center 38 (9~68) winsize 60
8336 00:57:10.060011 [CA 5] Center 37 (8~67) winsize 60
8337 00:57:10.060108
8338 00:57:10.063319 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8339 00:57:10.063392
8340 00:57:10.066505 [CATrainingPosCal] consider 2 rank data
8341 00:57:10.070092 u2DelayCellTimex100 = 290/100 ps
8342 00:57:10.073231 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8343 00:57:10.079762 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8344 00:57:10.083386 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8345 00:57:10.086582 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8346 00:57:10.089872 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8347 00:57:10.093207 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 00:57:10.093321
8349 00:57:10.096417 CA PerBit enable=1, Macro0, CA PI delay=37
8350 00:57:10.096503
8351 00:57:10.100051 [CBTSetCACLKResult] CA Dly = 37
8352 00:57:10.103111 CS Dly: 9 (0~42)
8353 00:57:10.106729 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 00:57:10.110065 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 00:57:10.110152
8356 00:57:10.113142 ----->DramcWriteLeveling(PI) begin...
8357 00:57:10.113226 ==
8358 00:57:10.116499 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 00:57:10.123248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 00:57:10.123336 ==
8361 00:57:10.126485 Write leveling (Byte 0): 25 => 25
8362 00:57:10.126585 Write leveling (Byte 1): 28 => 28
8363 00:57:10.129670 DramcWriteLeveling(PI) end<-----
8364 00:57:10.129753
8365 00:57:10.129837 ==
8366 00:57:10.132881 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 00:57:10.139825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 00:57:10.139942 ==
8369 00:57:10.142636 [Gating] SW mode calibration
8370 00:57:10.149617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 00:57:10.152686 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 00:57:10.159506 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 00:57:10.162741 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 00:57:10.165954 1 4 8 | B1->B0 | 2727 3030 | 0 1 | (0 0) (1 1)
8375 00:57:10.172482 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
8376 00:57:10.175963 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 00:57:10.179103 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 00:57:10.185644 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 00:57:10.189243 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 00:57:10.192175 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 00:57:10.199282 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8382 00:57:10.202248 1 5 8 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (1 0)
8383 00:57:10.205658 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
8384 00:57:10.212119 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8385 00:57:10.215340 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 00:57:10.219096 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 00:57:10.225462 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 00:57:10.229004 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 00:57:10.231906 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8390 00:57:10.238569 1 6 8 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
8391 00:57:10.242015 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8392 00:57:10.245249 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 00:57:10.251827 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 00:57:10.255283 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 00:57:10.258545 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 00:57:10.265022 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 00:57:10.268544 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8398 00:57:10.271910 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8399 00:57:10.278228 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8400 00:57:10.281721 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8401 00:57:10.285106 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 00:57:10.288217 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 00:57:10.294796 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 00:57:10.298113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 00:57:10.301432 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 00:57:10.308544 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 00:57:10.311379 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 00:57:10.314943 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 00:57:10.321436 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 00:57:10.324822 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 00:57:10.328025 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 00:57:10.334714 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 00:57:10.337954 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 00:57:10.341390 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 00:57:10.348196 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8416 00:57:10.351207 Total UI for P1: 0, mck2ui 16
8417 00:57:10.354660 best dqsien dly found for B0: ( 1, 9, 8)
8418 00:57:10.357848 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 00:57:10.361552 Total UI for P1: 0, mck2ui 16
8420 00:57:10.364863 best dqsien dly found for B1: ( 1, 9, 10)
8421 00:57:10.367511 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8422 00:57:10.371228 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8423 00:57:10.371307
8424 00:57:10.374328 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8425 00:57:10.377741 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 00:57:10.381082 [Gating] SW calibration Done
8427 00:57:10.381156 ==
8428 00:57:10.384212 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 00:57:10.390902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 00:57:10.391026 ==
8431 00:57:10.391108 RX Vref Scan: 0
8432 00:57:10.391170
8433 00:57:10.394576 RX Vref 0 -> 0, step: 1
8434 00:57:10.394653
8435 00:57:10.397559 RX Delay 0 -> 252, step: 8
8436 00:57:10.400867 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8437 00:57:10.404295 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8438 00:57:10.407149 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8439 00:57:10.410579 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8440 00:57:10.417229 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8441 00:57:10.420447 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 00:57:10.424144 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 00:57:10.427282 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8444 00:57:10.430568 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8445 00:57:10.437209 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8446 00:57:10.440555 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 00:57:10.443668 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8448 00:57:10.447341 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8449 00:57:10.450417 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8450 00:57:10.457301 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8451 00:57:10.460550 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8452 00:57:10.460643 ==
8453 00:57:10.463714 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 00:57:10.466894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 00:57:10.466980 ==
8456 00:57:10.470247 DQS Delay:
8457 00:57:10.470341 DQS0 = 0, DQS1 = 0
8458 00:57:10.470403 DQM Delay:
8459 00:57:10.473585 DQM0 = 139, DQM1 = 130
8460 00:57:10.473659 DQ Delay:
8461 00:57:10.477204 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8462 00:57:10.480236 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8463 00:57:10.483695 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8464 00:57:10.490247 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8465 00:57:10.490324
8466 00:57:10.490387
8467 00:57:10.490453 ==
8468 00:57:10.493615 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 00:57:10.496849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 00:57:10.496928 ==
8471 00:57:10.496999
8472 00:57:10.497059
8473 00:57:10.500489 TX Vref Scan disable
8474 00:57:10.500563 == TX Byte 0 ==
8475 00:57:10.506825 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8476 00:57:10.510379 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 00:57:10.510461 == TX Byte 1 ==
8478 00:57:10.517171 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8479 00:57:10.520317 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 00:57:10.520393 ==
8481 00:57:10.523492 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 00:57:10.526954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 00:57:10.527034 ==
8484 00:57:10.540131
8485 00:57:10.543727 TX Vref early break, caculate TX vref
8486 00:57:10.546962 TX Vref=16, minBit 9, minWin=22, winSum=375
8487 00:57:10.550601 TX Vref=18, minBit 1, minWin=23, winSum=383
8488 00:57:10.553820 TX Vref=20, minBit 9, minWin=23, winSum=390
8489 00:57:10.557129 TX Vref=22, minBit 12, minWin=24, winSum=407
8490 00:57:10.560322 TX Vref=24, minBit 15, minWin=24, winSum=415
8491 00:57:10.567227 TX Vref=26, minBit 15, minWin=25, winSum=422
8492 00:57:10.570449 TX Vref=28, minBit 10, minWin=25, winSum=430
8493 00:57:10.573846 TX Vref=30, minBit 10, minWin=25, winSum=419
8494 00:57:10.576811 TX Vref=32, minBit 10, minWin=24, winSum=413
8495 00:57:10.580391 TX Vref=34, minBit 10, minWin=24, winSum=405
8496 00:57:10.586683 [TxChooseVref] Worse bit 10, Min win 25, Win sum 430, Final Vref 28
8497 00:57:10.586806
8498 00:57:10.590657 Final TX Range 0 Vref 28
8499 00:57:10.590816
8500 00:57:10.590907 ==
8501 00:57:10.593410 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 00:57:10.597030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 00:57:10.597120 ==
8504 00:57:10.597184
8505 00:57:10.597249
8506 00:57:10.600181 TX Vref Scan disable
8507 00:57:10.606866 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8508 00:57:10.606947 == TX Byte 0 ==
8509 00:57:10.610121 u2DelayCellOfst[0]=13 cells (4 PI)
8510 00:57:10.613573 u2DelayCellOfst[1]=10 cells (3 PI)
8511 00:57:10.616739 u2DelayCellOfst[2]=0 cells (0 PI)
8512 00:57:10.620119 u2DelayCellOfst[3]=6 cells (2 PI)
8513 00:57:10.623321 u2DelayCellOfst[4]=6 cells (2 PI)
8514 00:57:10.626845 u2DelayCellOfst[5]=16 cells (5 PI)
8515 00:57:10.630171 u2DelayCellOfst[6]=16 cells (5 PI)
8516 00:57:10.633221 u2DelayCellOfst[7]=3 cells (1 PI)
8517 00:57:10.636425 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8518 00:57:10.640212 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 00:57:10.643506 == TX Byte 1 ==
8520 00:57:10.646538 u2DelayCellOfst[8]=0 cells (0 PI)
8521 00:57:10.646627 u2DelayCellOfst[9]=0 cells (0 PI)
8522 00:57:10.649949 u2DelayCellOfst[10]=6 cells (2 PI)
8523 00:57:10.653444 u2DelayCellOfst[11]=0 cells (0 PI)
8524 00:57:10.656670 u2DelayCellOfst[12]=13 cells (4 PI)
8525 00:57:10.659786 u2DelayCellOfst[13]=13 cells (4 PI)
8526 00:57:10.663136 u2DelayCellOfst[14]=13 cells (4 PI)
8527 00:57:10.666713 u2DelayCellOfst[15]=13 cells (4 PI)
8528 00:57:10.670067 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8529 00:57:10.676350 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8530 00:57:10.676446 DramC Write-DBI on
8531 00:57:10.676509 ==
8532 00:57:10.679847 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 00:57:10.686244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 00:57:10.686333 ==
8535 00:57:10.686430
8536 00:57:10.686489
8537 00:57:10.686547 TX Vref Scan disable
8538 00:57:10.690246 == TX Byte 0 ==
8539 00:57:10.693503 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8540 00:57:10.696692 == TX Byte 1 ==
8541 00:57:10.700416 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 00:57:10.700503 DramC Write-DBI off
8543 00:57:10.703635
8544 00:57:10.703731 [DATLAT]
8545 00:57:10.703805 Freq=1600, CH1 RK0
8546 00:57:10.703881
8547 00:57:10.706876 DATLAT Default: 0xf
8548 00:57:10.706977 0, 0xFFFF, sum = 0
8549 00:57:10.709946 1, 0xFFFF, sum = 0
8550 00:57:10.710018 2, 0xFFFF, sum = 0
8551 00:57:10.713635 3, 0xFFFF, sum = 0
8552 00:57:10.716564 4, 0xFFFF, sum = 0
8553 00:57:10.716686 5, 0xFFFF, sum = 0
8554 00:57:10.720225 6, 0xFFFF, sum = 0
8555 00:57:10.720311 7, 0xFFFF, sum = 0
8556 00:57:10.723478 8, 0xFFFF, sum = 0
8557 00:57:10.723562 9, 0xFFFF, sum = 0
8558 00:57:10.726685 10, 0xFFFF, sum = 0
8559 00:57:10.726755 11, 0xFFFF, sum = 0
8560 00:57:10.730314 12, 0xFFFF, sum = 0
8561 00:57:10.730410 13, 0xFFFF, sum = 0
8562 00:57:10.733241 14, 0x0, sum = 1
8563 00:57:10.733312 15, 0x0, sum = 2
8564 00:57:10.736635 16, 0x0, sum = 3
8565 00:57:10.736714 17, 0x0, sum = 4
8566 00:57:10.740266 best_step = 15
8567 00:57:10.740368
8568 00:57:10.740437 ==
8569 00:57:10.743131 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 00:57:10.746549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 00:57:10.746620 ==
8572 00:57:10.749857 RX Vref Scan: 1
8573 00:57:10.749956
8574 00:57:10.750026 Set Vref Range= 24 -> 127
8575 00:57:10.750085
8576 00:57:10.753525 RX Vref 24 -> 127, step: 1
8577 00:57:10.753595
8578 00:57:10.756615 RX Delay 19 -> 252, step: 4
8579 00:57:10.756687
8580 00:57:10.760121 Set Vref, RX VrefLevel [Byte0]: 24
8581 00:57:10.763693 [Byte1]: 24
8582 00:57:10.763766
8583 00:57:10.766897 Set Vref, RX VrefLevel [Byte0]: 25
8584 00:57:10.770249 [Byte1]: 25
8585 00:57:10.770326
8586 00:57:10.773250 Set Vref, RX VrefLevel [Byte0]: 26
8587 00:57:10.776538 [Byte1]: 26
8588 00:57:10.780158
8589 00:57:10.780230 Set Vref, RX VrefLevel [Byte0]: 27
8590 00:57:10.783800 [Byte1]: 27
8591 00:57:10.787785
8592 00:57:10.787863 Set Vref, RX VrefLevel [Byte0]: 28
8593 00:57:10.791240 [Byte1]: 28
8594 00:57:10.795418
8595 00:57:10.795496 Set Vref, RX VrefLevel [Byte0]: 29
8596 00:57:10.798861 [Byte1]: 29
8597 00:57:10.803312
8598 00:57:10.803387 Set Vref, RX VrefLevel [Byte0]: 30
8599 00:57:10.806288 [Byte1]: 30
8600 00:57:10.810562
8601 00:57:10.810640 Set Vref, RX VrefLevel [Byte0]: 31
8602 00:57:10.813904 [Byte1]: 31
8603 00:57:10.818602
8604 00:57:10.818676 Set Vref, RX VrefLevel [Byte0]: 32
8605 00:57:10.821591 [Byte1]: 32
8606 00:57:10.825691
8607 00:57:10.825768 Set Vref, RX VrefLevel [Byte0]: 33
8608 00:57:10.829313 [Byte1]: 33
8609 00:57:10.833508
8610 00:57:10.833582 Set Vref, RX VrefLevel [Byte0]: 34
8611 00:57:10.836460 [Byte1]: 34
8612 00:57:10.841088
8613 00:57:10.841163 Set Vref, RX VrefLevel [Byte0]: 35
8614 00:57:10.844418 [Byte1]: 35
8615 00:57:10.848508
8616 00:57:10.848586 Set Vref, RX VrefLevel [Byte0]: 36
8617 00:57:10.851923 [Byte1]: 36
8618 00:57:10.856133
8619 00:57:10.856203 Set Vref, RX VrefLevel [Byte0]: 37
8620 00:57:10.859626 [Byte1]: 37
8621 00:57:10.863792
8622 00:57:10.863865 Set Vref, RX VrefLevel [Byte0]: 38
8623 00:57:10.867191 [Byte1]: 38
8624 00:57:10.871302
8625 00:57:10.871374 Set Vref, RX VrefLevel [Byte0]: 39
8626 00:57:10.874564 [Byte1]: 39
8627 00:57:10.878927
8628 00:57:10.878999 Set Vref, RX VrefLevel [Byte0]: 40
8629 00:57:10.881920 [Byte1]: 40
8630 00:57:10.886411
8631 00:57:10.886486 Set Vref, RX VrefLevel [Byte0]: 41
8632 00:57:10.889467 [Byte1]: 41
8633 00:57:10.894261
8634 00:57:10.894333 Set Vref, RX VrefLevel [Byte0]: 42
8635 00:57:10.897346 [Byte1]: 42
8636 00:57:10.901619
8637 00:57:10.901696 Set Vref, RX VrefLevel [Byte0]: 43
8638 00:57:10.905040 [Byte1]: 43
8639 00:57:10.909444
8640 00:57:10.909522 Set Vref, RX VrefLevel [Byte0]: 44
8641 00:57:10.912357 [Byte1]: 44
8642 00:57:10.916789
8643 00:57:10.916868 Set Vref, RX VrefLevel [Byte0]: 45
8644 00:57:10.920048 [Byte1]: 45
8645 00:57:10.924254
8646 00:57:10.924327 Set Vref, RX VrefLevel [Byte0]: 46
8647 00:57:10.927519 [Byte1]: 46
8648 00:57:10.931994
8649 00:57:10.932066 Set Vref, RX VrefLevel [Byte0]: 47
8650 00:57:10.935123 [Byte1]: 47
8651 00:57:10.939766
8652 00:57:10.939845 Set Vref, RX VrefLevel [Byte0]: 48
8653 00:57:10.942804 [Byte1]: 48
8654 00:57:10.946792
8655 00:57:10.946870 Set Vref, RX VrefLevel [Byte0]: 49
8656 00:57:10.950427 [Byte1]: 49
8657 00:57:10.954682
8658 00:57:10.954758 Set Vref, RX VrefLevel [Byte0]: 50
8659 00:57:10.957759 [Byte1]: 50
8660 00:57:10.962080
8661 00:57:10.962160 Set Vref, RX VrefLevel [Byte0]: 51
8662 00:57:10.965390 [Byte1]: 51
8663 00:57:10.969495
8664 00:57:10.969570 Set Vref, RX VrefLevel [Byte0]: 52
8665 00:57:10.972872 [Byte1]: 52
8666 00:57:10.977081
8667 00:57:10.977188 Set Vref, RX VrefLevel [Byte0]: 53
8668 00:57:10.980436 [Byte1]: 53
8669 00:57:10.984849
8670 00:57:10.984921 Set Vref, RX VrefLevel [Byte0]: 54
8671 00:57:10.987931 [Byte1]: 54
8672 00:57:10.992415
8673 00:57:10.992496 Set Vref, RX VrefLevel [Byte0]: 55
8674 00:57:10.995608 [Byte1]: 55
8675 00:57:10.999793
8676 00:57:10.999867 Set Vref, RX VrefLevel [Byte0]: 56
8677 00:57:11.003158 [Byte1]: 56
8678 00:57:11.008148
8679 00:57:11.008222 Set Vref, RX VrefLevel [Byte0]: 57
8680 00:57:11.010659 [Byte1]: 57
8681 00:57:11.014910
8682 00:57:11.014988 Set Vref, RX VrefLevel [Byte0]: 58
8683 00:57:11.018811 [Byte1]: 58
8684 00:57:11.022654
8685 00:57:11.022732 Set Vref, RX VrefLevel [Byte0]: 59
8686 00:57:11.025997 [Byte1]: 59
8687 00:57:11.030086
8688 00:57:11.030170 Set Vref, RX VrefLevel [Byte0]: 60
8689 00:57:11.033438 [Byte1]: 60
8690 00:57:11.037989
8691 00:57:11.038069 Set Vref, RX VrefLevel [Byte0]: 61
8692 00:57:11.041250 [Byte1]: 61
8693 00:57:11.045417
8694 00:57:11.045494 Set Vref, RX VrefLevel [Byte0]: 62
8695 00:57:11.048538 [Byte1]: 62
8696 00:57:11.052994
8697 00:57:11.053096 Set Vref, RX VrefLevel [Byte0]: 63
8698 00:57:11.056263 [Byte1]: 63
8699 00:57:11.060546
8700 00:57:11.064038 Set Vref, RX VrefLevel [Byte0]: 64
8701 00:57:11.064119 [Byte1]: 64
8702 00:57:11.068503
8703 00:57:11.068580 Set Vref, RX VrefLevel [Byte0]: 65
8704 00:57:11.071220 [Byte1]: 65
8705 00:57:11.075699
8706 00:57:11.075780 Set Vref, RX VrefLevel [Byte0]: 66
8707 00:57:11.079085 [Byte1]: 66
8708 00:57:11.083249
8709 00:57:11.083353 Set Vref, RX VrefLevel [Byte0]: 67
8710 00:57:11.086350 [Byte1]: 67
8711 00:57:11.090676
8712 00:57:11.090756 Set Vref, RX VrefLevel [Byte0]: 68
8713 00:57:11.094004 [Byte1]: 68
8714 00:57:11.098608
8715 00:57:11.098683 Set Vref, RX VrefLevel [Byte0]: 69
8716 00:57:11.101863 [Byte1]: 69
8717 00:57:11.105777
8718 00:57:11.105883 Set Vref, RX VrefLevel [Byte0]: 70
8719 00:57:11.109372 [Byte1]: 70
8720 00:57:11.113930
8721 00:57:11.114037 Set Vref, RX VrefLevel [Byte0]: 71
8722 00:57:11.116785 [Byte1]: 71
8723 00:57:11.121062
8724 00:57:11.121169 Set Vref, RX VrefLevel [Byte0]: 72
8725 00:57:11.124475 [Byte1]: 72
8726 00:57:11.128704
8727 00:57:11.128779 Set Vref, RX VrefLevel [Byte0]: 73
8728 00:57:11.132090 [Byte1]: 73
8729 00:57:11.136309
8730 00:57:11.136417 Set Vref, RX VrefLevel [Byte0]: 74
8731 00:57:11.139610 [Byte1]: 74
8732 00:57:11.143841
8733 00:57:11.143928 Final RX Vref Byte 0 = 59 to rank0
8734 00:57:11.147368 Final RX Vref Byte 1 = 64 to rank0
8735 00:57:11.150619 Final RX Vref Byte 0 = 59 to rank1
8736 00:57:11.153908 Final RX Vref Byte 1 = 64 to rank1==
8737 00:57:11.157100 Dram Type= 6, Freq= 0, CH_1, rank 0
8738 00:57:11.163750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 00:57:11.163825 ==
8740 00:57:11.163896 DQS Delay:
8741 00:57:11.166929 DQS0 = 0, DQS1 = 0
8742 00:57:11.167012 DQM Delay:
8743 00:57:11.167075 DQM0 = 135, DQM1 = 128
8744 00:57:11.170146 DQ Delay:
8745 00:57:11.173502 DQ0 =140, DQ1 =130, DQ2 =124, DQ3 =132
8746 00:57:11.177137 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
8747 00:57:11.180164 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8748 00:57:11.183461 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8749 00:57:11.183554
8750 00:57:11.183620
8751 00:57:11.183680
8752 00:57:11.186721 [DramC_TX_OE_Calibration] TA2
8753 00:57:11.190135 Original DQ_B0 (3 6) =30, OEN = 27
8754 00:57:11.193761 Original DQ_B1 (3 6) =30, OEN = 27
8755 00:57:11.196633 24, 0x0, End_B0=24 End_B1=24
8756 00:57:11.196708 25, 0x0, End_B0=25 End_B1=25
8757 00:57:11.200226 26, 0x0, End_B0=26 End_B1=26
8758 00:57:11.203655 27, 0x0, End_B0=27 End_B1=27
8759 00:57:11.206832 28, 0x0, End_B0=28 End_B1=28
8760 00:57:11.209952 29, 0x0, End_B0=29 End_B1=29
8761 00:57:11.210031 30, 0x0, End_B0=30 End_B1=30
8762 00:57:11.213545 31, 0x4545, End_B0=30 End_B1=30
8763 00:57:11.216957 Byte0 end_step=30 best_step=27
8764 00:57:11.220408 Byte1 end_step=30 best_step=27
8765 00:57:11.223395 Byte0 TX OE(2T, 0.5T) = (3, 3)
8766 00:57:11.226750 Byte1 TX OE(2T, 0.5T) = (3, 3)
8767 00:57:11.226826
8768 00:57:11.226897
8769 00:57:11.233822 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8770 00:57:11.236857 CH1 RK0: MR19=303, MR18=1927
8771 00:57:11.243454 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8772 00:57:11.243574
8773 00:57:11.247274 ----->DramcWriteLeveling(PI) begin...
8774 00:57:11.247393 ==
8775 00:57:11.250201 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 00:57:11.253462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 00:57:11.253548 ==
8778 00:57:11.256919 Write leveling (Byte 0): 24 => 24
8779 00:57:11.260125 Write leveling (Byte 1): 29 => 29
8780 00:57:11.263615 DramcWriteLeveling(PI) end<-----
8781 00:57:11.263700
8782 00:57:11.263767 ==
8783 00:57:11.266855 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 00:57:11.270100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 00:57:11.270186 ==
8786 00:57:11.273772 [Gating] SW mode calibration
8787 00:57:11.280333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8788 00:57:11.287024 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8789 00:57:11.290122 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 00:57:11.293189 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 00:57:11.300305 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8792 00:57:11.303258 1 4 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 1)
8793 00:57:11.307034 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 00:57:11.313196 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 00:57:11.316746 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 00:57:11.319963 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 00:57:11.326531 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 00:57:11.330123 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 00:57:11.333251 1 5 8 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
8800 00:57:11.339807 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (1 0) (1 0)
8801 00:57:11.343192 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 00:57:11.346767 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 00:57:11.353115 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 00:57:11.356574 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 00:57:11.359927 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 00:57:11.366468 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 00:57:11.369663 1 6 8 | B1->B0 | 3a3a 2424 | 0 0 | (0 0) (0 0)
8808 00:57:11.373119 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8809 00:57:11.379927 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 00:57:11.382967 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 00:57:11.386440 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 00:57:11.392909 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 00:57:11.396492 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 00:57:11.399499 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 00:57:11.406284 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8816 00:57:11.409392 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8817 00:57:11.412815 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8818 00:57:11.416355 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 00:57:11.422673 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 00:57:11.426085 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 00:57:11.429336 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 00:57:11.436178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 00:57:11.439309 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 00:57:11.442759 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 00:57:11.449477 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 00:57:11.452880 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 00:57:11.456025 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 00:57:11.462903 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 00:57:11.465905 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 00:57:11.469344 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 00:57:11.476186 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8832 00:57:11.479213 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8833 00:57:11.482883 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 00:57:11.486227 Total UI for P1: 0, mck2ui 16
8835 00:57:11.489548 best dqsien dly found for B0: ( 1, 9, 10)
8836 00:57:11.492850 Total UI for P1: 0, mck2ui 16
8837 00:57:11.495941 best dqsien dly found for B1: ( 1, 9, 10)
8838 00:57:11.499232 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8839 00:57:11.502841 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8840 00:57:11.502924
8841 00:57:11.509733 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8842 00:57:11.512870 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8843 00:57:11.512949 [Gating] SW calibration Done
8844 00:57:11.516178 ==
8845 00:57:11.519292 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 00:57:11.522790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 00:57:11.522866 ==
8848 00:57:11.522932 RX Vref Scan: 0
8849 00:57:11.523000
8850 00:57:11.525759 RX Vref 0 -> 0, step: 1
8851 00:57:11.525840
8852 00:57:11.529060 RX Delay 0 -> 252, step: 8
8853 00:57:11.532772 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8854 00:57:11.535761 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8855 00:57:11.539488 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8856 00:57:11.545603 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8857 00:57:11.549096 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8858 00:57:11.552566 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8859 00:57:11.555842 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8860 00:57:11.559272 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8861 00:57:11.562634 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8862 00:57:11.569309 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8863 00:57:11.572536 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8864 00:57:11.575834 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8865 00:57:11.579126 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8866 00:57:11.585762 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8867 00:57:11.588921 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8868 00:57:11.592684 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8869 00:57:11.592754 ==
8870 00:57:11.595578 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 00:57:11.599186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 00:57:11.599256 ==
8873 00:57:11.602441 DQS Delay:
8874 00:57:11.602516 DQS0 = 0, DQS1 = 0
8875 00:57:11.605470 DQM Delay:
8876 00:57:11.605537 DQM0 = 139, DQM1 = 131
8877 00:57:11.605597 DQ Delay:
8878 00:57:11.612721 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8879 00:57:11.616003 DQ4 =139, DQ5 =151, DQ6 =143, DQ7 =139
8880 00:57:11.619150 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8881 00:57:11.622256 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8882 00:57:11.622326
8883 00:57:11.622388
8884 00:57:11.622448 ==
8885 00:57:11.625354 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 00:57:11.628973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 00:57:11.629050 ==
8888 00:57:11.629112
8889 00:57:11.629171
8890 00:57:11.632486 TX Vref Scan disable
8891 00:57:11.635487 == TX Byte 0 ==
8892 00:57:11.639146 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8893 00:57:11.642266 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8894 00:57:11.645668 == TX Byte 1 ==
8895 00:57:11.648729 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8896 00:57:11.652443 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8897 00:57:11.652513 ==
8898 00:57:11.655312 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 00:57:11.662064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 00:57:11.662143 ==
8901 00:57:11.674601
8902 00:57:11.677741 TX Vref early break, caculate TX vref
8903 00:57:11.680964 TX Vref=16, minBit 13, minWin=22, winSum=385
8904 00:57:11.684277 TX Vref=18, minBit 9, minWin=23, winSum=395
8905 00:57:11.687762 TX Vref=20, minBit 9, minWin=24, winSum=406
8906 00:57:11.691160 TX Vref=22, minBit 13, minWin=24, winSum=411
8907 00:57:11.694792 TX Vref=24, minBit 9, minWin=24, winSum=421
8908 00:57:11.701235 TX Vref=26, minBit 13, minWin=24, winSum=425
8909 00:57:11.704371 TX Vref=28, minBit 10, minWin=25, winSum=426
8910 00:57:11.707881 TX Vref=30, minBit 10, minWin=25, winSum=418
8911 00:57:11.711495 TX Vref=32, minBit 10, minWin=24, winSum=411
8912 00:57:11.714816 TX Vref=34, minBit 10, minWin=24, winSum=405
8913 00:57:11.721115 TX Vref=36, minBit 10, minWin=23, winSum=396
8914 00:57:11.724436 [TxChooseVref] Worse bit 10, Min win 25, Win sum 426, Final Vref 28
8915 00:57:11.724509
8916 00:57:11.727744 Final TX Range 0 Vref 28
8917 00:57:11.727821
8918 00:57:11.727882 ==
8919 00:57:11.731254 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 00:57:11.734331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 00:57:11.737429 ==
8922 00:57:11.737506
8923 00:57:11.737575
8924 00:57:11.737636 TX Vref Scan disable
8925 00:57:11.744726 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8926 00:57:11.744806 == TX Byte 0 ==
8927 00:57:11.747917 u2DelayCellOfst[0]=16 cells (5 PI)
8928 00:57:11.751141 u2DelayCellOfst[1]=10 cells (3 PI)
8929 00:57:11.754233 u2DelayCellOfst[2]=0 cells (0 PI)
8930 00:57:11.757838 u2DelayCellOfst[3]=3 cells (1 PI)
8931 00:57:11.761040 u2DelayCellOfst[4]=6 cells (2 PI)
8932 00:57:11.764160 u2DelayCellOfst[5]=16 cells (5 PI)
8933 00:57:11.767495 u2DelayCellOfst[6]=16 cells (5 PI)
8934 00:57:11.771034 u2DelayCellOfst[7]=3 cells (1 PI)
8935 00:57:11.774394 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8936 00:57:11.777789 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8937 00:57:11.780782 == TX Byte 1 ==
8938 00:57:11.784534 u2DelayCellOfst[8]=0 cells (0 PI)
8939 00:57:11.787367 u2DelayCellOfst[9]=3 cells (1 PI)
8940 00:57:11.791015 u2DelayCellOfst[10]=10 cells (3 PI)
8941 00:57:11.794265 u2DelayCellOfst[11]=3 cells (1 PI)
8942 00:57:11.797448 u2DelayCellOfst[12]=13 cells (4 PI)
8943 00:57:11.797521 u2DelayCellOfst[13]=13 cells (4 PI)
8944 00:57:11.800842 u2DelayCellOfst[14]=16 cells (5 PI)
8945 00:57:11.803989 u2DelayCellOfst[15]=13 cells (4 PI)
8946 00:57:11.810789 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8947 00:57:11.814249 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8948 00:57:11.814323 DramC Write-DBI on
8949 00:57:11.817186 ==
8950 00:57:11.820842 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 00:57:11.823905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 00:57:11.823984 ==
8953 00:57:11.824048
8954 00:57:11.824108
8955 00:57:11.827112 TX Vref Scan disable
8956 00:57:11.827181 == TX Byte 0 ==
8957 00:57:11.833794 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8958 00:57:11.833868 == TX Byte 1 ==
8959 00:57:11.837569 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8960 00:57:11.840677 DramC Write-DBI off
8961 00:57:11.840760
8962 00:57:11.840821 [DATLAT]
8963 00:57:11.843950 Freq=1600, CH1 RK1
8964 00:57:11.844024
8965 00:57:11.844085 DATLAT Default: 0xf
8966 00:57:11.847163 0, 0xFFFF, sum = 0
8967 00:57:11.847236 1, 0xFFFF, sum = 0
8968 00:57:11.850655 2, 0xFFFF, sum = 0
8969 00:57:11.850730 3, 0xFFFF, sum = 0
8970 00:57:11.853958 4, 0xFFFF, sum = 0
8971 00:57:11.854031 5, 0xFFFF, sum = 0
8972 00:57:11.857209 6, 0xFFFF, sum = 0
8973 00:57:11.857289 7, 0xFFFF, sum = 0
8974 00:57:11.860424 8, 0xFFFF, sum = 0
8975 00:57:11.860503 9, 0xFFFF, sum = 0
8976 00:57:11.863649 10, 0xFFFF, sum = 0
8977 00:57:11.866852 11, 0xFFFF, sum = 0
8978 00:57:11.866933 12, 0xFFFF, sum = 0
8979 00:57:11.870342 13, 0xFFFF, sum = 0
8980 00:57:11.870416 14, 0x0, sum = 1
8981 00:57:11.873801 15, 0x0, sum = 2
8982 00:57:11.873884 16, 0x0, sum = 3
8983 00:57:11.876818 17, 0x0, sum = 4
8984 00:57:11.876910 best_step = 15
8985 00:57:11.876976
8986 00:57:11.877038 ==
8987 00:57:11.880066 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 00:57:11.883555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 00:57:11.883640 ==
8990 00:57:11.886780 RX Vref Scan: 0
8991 00:57:11.886858
8992 00:57:11.890124 RX Vref 0 -> 0, step: 1
8993 00:57:11.890228
8994 00:57:11.890290 RX Delay 19 -> 252, step: 4
8995 00:57:11.897073 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8996 00:57:11.900738 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8997 00:57:11.903751 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8998 00:57:11.907069 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8999 00:57:11.910466 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9000 00:57:11.917197 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9001 00:57:11.920346 iDelay=195, Bit 6, Center 146 (99 ~ 194) 96
9002 00:57:11.923728 iDelay=195, Bit 7, Center 134 (87 ~ 182) 96
9003 00:57:11.927176 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9004 00:57:11.930179 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9005 00:57:11.934049 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9006 00:57:11.940494 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9007 00:57:11.943862 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9008 00:57:11.947038 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9009 00:57:11.950227 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9010 00:57:11.956917 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9011 00:57:11.956991 ==
9012 00:57:11.960097 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 00:57:11.963760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 00:57:11.963831 ==
9015 00:57:11.963927 DQS Delay:
9016 00:57:11.967069 DQS0 = 0, DQS1 = 0
9017 00:57:11.967179 DQM Delay:
9018 00:57:11.970230 DQM0 = 135, DQM1 = 129
9019 00:57:11.970301 DQ Delay:
9020 00:57:11.973633 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
9021 00:57:11.976967 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =134
9022 00:57:11.980195 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9023 00:57:11.983678 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
9024 00:57:11.983801
9025 00:57:11.983863
9026 00:57:11.987090
9027 00:57:11.987194 [DramC_TX_OE_Calibration] TA2
9028 00:57:11.990082 Original DQ_B0 (3 6) =30, OEN = 27
9029 00:57:11.993400 Original DQ_B1 (3 6) =30, OEN = 27
9030 00:57:11.996777 24, 0x0, End_B0=24 End_B1=24
9031 00:57:12.000129 25, 0x0, End_B0=25 End_B1=25
9032 00:57:12.003309 26, 0x0, End_B0=26 End_B1=26
9033 00:57:12.003422 27, 0x0, End_B0=27 End_B1=27
9034 00:57:12.006912 28, 0x0, End_B0=28 End_B1=28
9035 00:57:12.009902 29, 0x0, End_B0=29 End_B1=29
9036 00:57:12.013294 30, 0x0, End_B0=30 End_B1=30
9037 00:57:12.016738 31, 0x4141, End_B0=30 End_B1=30
9038 00:57:12.016825 Byte0 end_step=30 best_step=27
9039 00:57:12.019828 Byte1 end_step=30 best_step=27
9040 00:57:12.023677 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 00:57:12.026815 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 00:57:12.026935
9043 00:57:12.026997
9044 00:57:12.033621 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9045 00:57:12.036548 CH1 RK1: MR19=303, MR18=1F08
9046 00:57:12.043366 CH1_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15
9047 00:57:12.046649 [RxdqsGatingPostProcess] freq 1600
9048 00:57:12.053163 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 00:57:12.056633 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 00:57:12.056741 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 00:57:12.059803 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 00:57:12.063154 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 00:57:12.066733 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 00:57:12.069977 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 00:57:12.073240 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 00:57:12.076405 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 00:57:12.079963 Pre-setting of DQS Precalculation
9058 00:57:12.083116 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 00:57:12.092984 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 00:57:12.099812 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 00:57:12.099899
9062 00:57:12.099964
9063 00:57:12.102944 [Calibration Summary] 3200 Mbps
9064 00:57:12.103021 CH 0, Rank 0
9065 00:57:12.106533 SW Impedance : PASS
9066 00:57:12.106608 DUTY Scan : NO K
9067 00:57:12.109637 ZQ Calibration : PASS
9068 00:57:12.112869 Jitter Meter : NO K
9069 00:57:12.112948 CBT Training : PASS
9070 00:57:12.116307 Write leveling : PASS
9071 00:57:12.119596 RX DQS gating : PASS
9072 00:57:12.119702 RX DQ/DQS(RDDQC) : PASS
9073 00:57:12.123012 TX DQ/DQS : PASS
9074 00:57:12.126464 RX DATLAT : PASS
9075 00:57:12.126551 RX DQ/DQS(Engine): PASS
9076 00:57:12.129609 TX OE : PASS
9077 00:57:12.129680 All Pass.
9078 00:57:12.129743
9079 00:57:12.132757 CH 0, Rank 1
9080 00:57:12.132842 SW Impedance : PASS
9081 00:57:12.136456 DUTY Scan : NO K
9082 00:57:12.139717 ZQ Calibration : PASS
9083 00:57:12.139803 Jitter Meter : NO K
9084 00:57:12.142713 CBT Training : PASS
9085 00:57:12.146084 Write leveling : PASS
9086 00:57:12.146169 RX DQS gating : PASS
9087 00:57:12.149780 RX DQ/DQS(RDDQC) : PASS
9088 00:57:12.149864 TX DQ/DQS : PASS
9089 00:57:12.153091 RX DATLAT : PASS
9090 00:57:12.156342 RX DQ/DQS(Engine): PASS
9091 00:57:12.156426 TX OE : PASS
9092 00:57:12.159682 All Pass.
9093 00:57:12.159767
9094 00:57:12.159833 CH 1, Rank 0
9095 00:57:12.162847 SW Impedance : PASS
9096 00:57:12.162933 DUTY Scan : NO K
9097 00:57:12.166186 ZQ Calibration : PASS
9098 00:57:12.169354 Jitter Meter : NO K
9099 00:57:12.169440 CBT Training : PASS
9100 00:57:12.172905 Write leveling : PASS
9101 00:57:12.176148 RX DQS gating : PASS
9102 00:57:12.176233 RX DQ/DQS(RDDQC) : PASS
9103 00:57:12.179762 TX DQ/DQS : PASS
9104 00:57:12.183011 RX DATLAT : PASS
9105 00:57:12.183096 RX DQ/DQS(Engine): PASS
9106 00:57:12.186060 TX OE : PASS
9107 00:57:12.186145 All Pass.
9108 00:57:12.186212
9109 00:57:12.189456 CH 1, Rank 1
9110 00:57:12.189541 SW Impedance : PASS
9111 00:57:12.192838 DUTY Scan : NO K
9112 00:57:12.192923 ZQ Calibration : PASS
9113 00:57:12.196179 Jitter Meter : NO K
9114 00:57:12.199465 CBT Training : PASS
9115 00:57:12.199550 Write leveling : PASS
9116 00:57:12.202819 RX DQS gating : PASS
9117 00:57:12.206089 RX DQ/DQS(RDDQC) : PASS
9118 00:57:12.206174 TX DQ/DQS : PASS
9119 00:57:12.209358 RX DATLAT : PASS
9120 00:57:12.212660 RX DQ/DQS(Engine): PASS
9121 00:57:12.212746 TX OE : PASS
9122 00:57:12.216204 All Pass.
9123 00:57:12.216288
9124 00:57:12.216354 DramC Write-DBI on
9125 00:57:12.219204 PER_BANK_REFRESH: Hybrid Mode
9126 00:57:12.219289 TX_TRACKING: ON
9127 00:57:12.229161 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 00:57:12.239605 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 00:57:12.246212 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 00:57:12.249495 [FAST_K] Save calibration result to emmc
9131 00:57:12.252799 sync common calibartion params.
9132 00:57:12.252882 sync cbt_mode0:1, 1:1
9133 00:57:12.256331 dram_init: ddr_geometry: 2
9134 00:57:12.259564 dram_init: ddr_geometry: 2
9135 00:57:12.259662 dram_init: ddr_geometry: 2
9136 00:57:12.262588 0:dram_rank_size:100000000
9137 00:57:12.266047 1:dram_rank_size:100000000
9138 00:57:12.272848 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 00:57:12.272947 DFS_SHUFFLE_HW_MODE: ON
9140 00:57:12.276116 dramc_set_vcore_voltage set vcore to 725000
9141 00:57:12.279300 Read voltage for 1600, 0
9142 00:57:12.279384 Vio18 = 0
9143 00:57:12.282456 Vcore = 725000
9144 00:57:12.282539 Vdram = 0
9145 00:57:12.282634 Vddq = 0
9146 00:57:12.285733 Vmddr = 0
9147 00:57:12.285817 switch to 3200 Mbps bootup
9148 00:57:12.289034 [DramcRunTimeConfig]
9149 00:57:12.289118 PHYPLL
9150 00:57:12.292637 DPM_CONTROL_AFTERK: ON
9151 00:57:12.292751 PER_BANK_REFRESH: ON
9152 00:57:12.295771 REFRESH_OVERHEAD_REDUCTION: ON
9153 00:57:12.299112 CMD_PICG_NEW_MODE: OFF
9154 00:57:12.299195 XRTWTW_NEW_MODE: ON
9155 00:57:12.302332 XRTRTR_NEW_MODE: ON
9156 00:57:12.302431 TX_TRACKING: ON
9157 00:57:12.305839 RDSEL_TRACKING: OFF
9158 00:57:12.309015 DQS Precalculation for DVFS: ON
9159 00:57:12.309114 RX_TRACKING: OFF
9160 00:57:12.312440 HW_GATING DBG: ON
9161 00:57:12.312531 ZQCS_ENABLE_LP4: ON
9162 00:57:12.315858 RX_PICG_NEW_MODE: ON
9163 00:57:12.315956 TX_PICG_NEW_MODE: ON
9164 00:57:12.318833 ENABLE_RX_DCM_DPHY: ON
9165 00:57:12.322342 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 00:57:12.325884 DUMMY_READ_FOR_TRACKING: OFF
9167 00:57:12.325978 !!! SPM_CONTROL_AFTERK: OFF
9168 00:57:12.328845 !!! SPM could not control APHY
9169 00:57:12.332449 IMPEDANCE_TRACKING: ON
9170 00:57:12.332534 TEMP_SENSOR: ON
9171 00:57:12.335533 HW_SAVE_FOR_SR: OFF
9172 00:57:12.339183 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 00:57:12.342403 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 00:57:12.342488 Read ODT Tracking: ON
9175 00:57:12.345433 Refresh Rate DeBounce: ON
9176 00:57:12.349069 DFS_NO_QUEUE_FLUSH: ON
9177 00:57:12.352149 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 00:57:12.355195 ENABLE_DFS_RUNTIME_MRW: OFF
9179 00:57:12.355281 DDR_RESERVE_NEW_MODE: ON
9180 00:57:12.358778 MR_CBT_SWITCH_FREQ: ON
9181 00:57:12.361717 =========================
9182 00:57:12.379495 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 00:57:12.382734 dram_init: ddr_geometry: 2
9184 00:57:12.400922 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 00:57:12.404151 dram_init: dram init end (result: 0)
9186 00:57:12.411107 DRAM-K: Full calibration passed in 24554 msecs
9187 00:57:12.414387 MRC: failed to locate region type 0.
9188 00:57:12.414473 DRAM rank0 size:0x100000000,
9189 00:57:12.417173 DRAM rank1 size=0x100000000
9190 00:57:12.427212 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 00:57:12.433860 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 00:57:12.440522 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 00:57:12.447622 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 00:57:12.450760 DRAM rank0 size:0x100000000,
9195 00:57:12.453713 DRAM rank1 size=0x100000000
9196 00:57:12.453797 CBMEM:
9197 00:57:12.457558 IMD: root @ 0xfffff000 254 entries.
9198 00:57:12.460699 IMD: root @ 0xffffec00 62 entries.
9199 00:57:12.463801 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 00:57:12.467026 WARNING: RO_VPD is uninitialized or empty.
9201 00:57:12.473675 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 00:57:12.480685 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 00:57:12.493657 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9204 00:57:12.505059 BS: romstage times (exec / console): total (unknown) / 24044 ms
9205 00:57:12.505175
9206 00:57:12.505274
9207 00:57:12.515150 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 00:57:12.518523 ARM64: Exception handlers installed.
9209 00:57:12.521574 ARM64: Testing exception
9210 00:57:12.524951 ARM64: Done test exception
9211 00:57:12.525054 Enumerating buses...
9212 00:57:12.528458 Show all devs... Before device enumeration.
9213 00:57:12.531716 Root Device: enabled 1
9214 00:57:12.535026 CPU_CLUSTER: 0: enabled 1
9215 00:57:12.535127 CPU: 00: enabled 1
9216 00:57:12.538210 Compare with tree...
9217 00:57:12.538327 Root Device: enabled 1
9218 00:57:12.541526 CPU_CLUSTER: 0: enabled 1
9219 00:57:12.544777 CPU: 00: enabled 1
9220 00:57:12.544903 Root Device scanning...
9221 00:57:12.548226 scan_static_bus for Root Device
9222 00:57:12.551867 CPU_CLUSTER: 0 enabled
9223 00:57:12.554746 scan_static_bus for Root Device done
9224 00:57:12.558374 scan_bus: bus Root Device finished in 8 msecs
9225 00:57:12.558460 done
9226 00:57:12.564812 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 00:57:12.568161 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 00:57:12.574809 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 00:57:12.578088 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 00:57:12.581633 Allocating resources...
9231 00:57:12.581707 Reading resources...
9232 00:57:12.588117 Root Device read_resources bus 0 link: 0
9233 00:57:12.588219 DRAM rank0 size:0x100000000,
9234 00:57:12.591604 DRAM rank1 size=0x100000000
9235 00:57:12.594748 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 00:57:12.598078 CPU: 00 missing read_resources
9237 00:57:12.601789 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 00:57:12.608320 Root Device read_resources bus 0 link: 0 done
9239 00:57:12.608395 Done reading resources.
9240 00:57:12.614831 Show resources in subtree (Root Device)...After reading.
9241 00:57:12.618353 Root Device child on link 0 CPU_CLUSTER: 0
9242 00:57:12.621241 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 00:57:12.631561 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 00:57:12.631638 CPU: 00
9245 00:57:12.634992 Root Device assign_resources, bus 0 link: 0
9246 00:57:12.637840 CPU_CLUSTER: 0 missing set_resources
9247 00:57:12.641554 Root Device assign_resources, bus 0 link: 0 done
9248 00:57:12.644737 Done setting resources.
9249 00:57:12.651293 Show resources in subtree (Root Device)...After assigning values.
9250 00:57:12.654785 Root Device child on link 0 CPU_CLUSTER: 0
9251 00:57:12.658067 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 00:57:12.668041 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 00:57:12.668154 CPU: 00
9254 00:57:12.671220 Done allocating resources.
9255 00:57:12.674747 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 00:57:12.677877 Enabling resources...
9257 00:57:12.677981 done.
9258 00:57:12.684313 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 00:57:12.684416 Initializing devices...
9260 00:57:12.687983 Root Device init
9261 00:57:12.688085 init hardware done!
9262 00:57:12.691315 0x00000018: ctrlr->caps
9263 00:57:12.694432 52.000 MHz: ctrlr->f_max
9264 00:57:12.694508 0.400 MHz: ctrlr->f_min
9265 00:57:12.697821 0x40ff8080: ctrlr->voltages
9266 00:57:12.697925 sclk: 390625
9267 00:57:12.700912 Bus Width = 1
9268 00:57:12.701001 sclk: 390625
9269 00:57:12.704283 Bus Width = 1
9270 00:57:12.704386 Early init status = 3
9271 00:57:12.711093 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 00:57:12.714398 in-header: 03 fc 00 00 01 00 00 00
9273 00:57:12.717583 in-data: 00
9274 00:57:12.720733 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 00:57:12.725836 in-header: 03 fd 00 00 00 00 00 00
9276 00:57:12.729233 in-data:
9277 00:57:12.732290 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 00:57:12.736902 in-header: 03 fc 00 00 01 00 00 00
9279 00:57:12.740141 in-data: 00
9280 00:57:12.743406 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 00:57:12.749084 in-header: 03 fd 00 00 00 00 00 00
9282 00:57:12.752496 in-data:
9283 00:57:12.755773 [SSUSB] Setting up USB HOST controller...
9284 00:57:12.759019 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 00:57:12.762594 [SSUSB] phy power-on done.
9286 00:57:12.765699 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 00:57:12.772577 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 00:57:12.775559 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 00:57:12.782242 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 00:57:12.788924 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 00:57:12.795771 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 00:57:12.802569 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 00:57:12.809183 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 00:57:12.809291 SPM: binary array size = 0x9dc
9295 00:57:12.815941 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 00:57:12.822537 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 00:57:12.829176 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 00:57:12.832392 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 00:57:12.835744 configure_display: Starting display init
9300 00:57:12.872591 anx7625_power_on_init: Init interface.
9301 00:57:12.875914 anx7625_disable_pd_protocol: Disabled PD feature.
9302 00:57:12.879082 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 00:57:12.906872 anx7625_start_dp_work: Secure OCM version=00
9304 00:57:12.909979 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 00:57:12.924741 sp_tx_get_edid_block: EDID Block = 1
9306 00:57:13.027702 Extracted contents:
9307 00:57:13.030613 header: 00 ff ff ff ff ff ff 00
9308 00:57:13.033845 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 00:57:13.037169 version: 01 04
9310 00:57:13.040809 basic params: 95 1f 11 78 0a
9311 00:57:13.044023 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 00:57:13.047289 established: 00 00 00
9313 00:57:13.053746 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 00:57:13.060328 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 00:57:13.063851 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 00:57:13.070274 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 00:57:13.076876 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 00:57:13.079991 extensions: 00
9319 00:57:13.080094 checksum: fb
9320 00:57:13.080183
9321 00:57:13.083619 Manufacturer: IVO Model 57d Serial Number 0
9322 00:57:13.086789 Made week 0 of 2020
9323 00:57:13.090061 EDID version: 1.4
9324 00:57:13.090142 Digital display
9325 00:57:13.093246 6 bits per primary color channel
9326 00:57:13.093344 DisplayPort interface
9327 00:57:13.096823 Maximum image size: 31 cm x 17 cm
9328 00:57:13.100074 Gamma: 220%
9329 00:57:13.100173 Check DPMS levels
9330 00:57:13.103686 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 00:57:13.109815 First detailed timing is preferred timing
9332 00:57:13.109913 Established timings supported:
9333 00:57:13.113280 Standard timings supported:
9334 00:57:13.116445 Detailed timings
9335 00:57:13.119715 Hex of detail: 383680a07038204018303c0035ae10000019
9336 00:57:13.126598 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 00:57:13.129696 0780 0798 07c8 0820 hborder 0
9338 00:57:13.133143 0438 043b 0447 0458 vborder 0
9339 00:57:13.136240 -hsync -vsync
9340 00:57:13.136336 Did detailed timing
9341 00:57:13.142989 Hex of detail: 000000000000000000000000000000000000
9342 00:57:13.146256 Manufacturer-specified data, tag 0
9343 00:57:13.149676 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 00:57:13.152833 ASCII string: InfoVision
9345 00:57:13.156083 Hex of detail: 000000fe00523134304e574635205248200a
9346 00:57:13.159420 ASCII string: R140NWF5 RH
9347 00:57:13.159519 Checksum
9348 00:57:13.163277 Checksum: 0xfb (valid)
9349 00:57:13.166286 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 00:57:13.169602 DSI data_rate: 832800000 bps
9351 00:57:13.175986 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 00:57:13.179691 anx7625_parse_edid: pixelclock(138800).
9353 00:57:13.182744 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 00:57:13.186090 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 00:57:13.189421 anx7625_dsi_config: config dsi.
9356 00:57:13.196151 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 00:57:13.209615 anx7625_dsi_config: success to config DSI
9358 00:57:13.212834 anx7625_dp_start: MIPI phy setup OK.
9359 00:57:13.216364 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 00:57:13.219524 mtk_ddp_mode_set invalid vrefresh 60
9361 00:57:13.223083 main_disp_path_setup
9362 00:57:13.223189 ovl_layer_smi_id_en
9363 00:57:13.226310 ovl_layer_smi_id_en
9364 00:57:13.226424 ccorr_config
9365 00:57:13.226533 aal_config
9366 00:57:13.229517 gamma_config
9367 00:57:13.229614 postmask_config
9368 00:57:13.232950 dither_config
9369 00:57:13.236220 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 00:57:13.242936 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 00:57:13.246138 Root Device init finished in 555 msecs
9372 00:57:13.249577 CPU_CLUSTER: 0 init
9373 00:57:13.256462 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 00:57:13.259241 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 00:57:13.262456 APU_MBOX 0x190000b0 = 0x10001
9376 00:57:13.265787 APU_MBOX 0x190001b0 = 0x10001
9377 00:57:13.269123 APU_MBOX 0x190005b0 = 0x10001
9378 00:57:13.272804 APU_MBOX 0x190006b0 = 0x10001
9379 00:57:13.275655 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 00:57:13.288456 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9381 00:57:13.300778 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 00:57:13.307449 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 00:57:13.319202 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9384 00:57:13.328458 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 00:57:13.331547 CPU_CLUSTER: 0 init finished in 81 msecs
9386 00:57:13.334923 Devices initialized
9387 00:57:13.338245 Show all devs... After init.
9388 00:57:13.338329 Root Device: enabled 1
9389 00:57:13.341689 CPU_CLUSTER: 0: enabled 1
9390 00:57:13.345110 CPU: 00: enabled 1
9391 00:57:13.348608 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9392 00:57:13.351926 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 00:57:13.355094 ELOG: NV offset 0x57f000 size 0x1000
9394 00:57:13.361635 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9395 00:57:13.368133 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 00:57:13.371424 ELOG: Event(17) added with size 13 at 2024-01-19 00:56:33 UTC
9397 00:57:13.374974 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 00:57:13.378465 in-header: 03 fb 00 00 2c 00 00 00
9399 00:57:13.391712 in-data: 64 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 00:57:13.398388 ELOG: Event(A1) added with size 10 at 2024-01-19 00:56:33 UTC
9401 00:57:13.404985 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9402 00:57:13.412157 ELOG: Event(A0) added with size 9 at 2024-01-19 00:56:34 UTC
9403 00:57:13.415206 elog_add_boot_reason: Logged dev mode boot
9404 00:57:13.418335 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 00:57:13.422080 Finalize devices...
9406 00:57:13.422195 Devices finalized
9407 00:57:13.428482 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 00:57:13.432165 Writing coreboot table at 0xffe64000
9409 00:57:13.435299 0. 000000000010a000-0000000000113fff: RAMSTAGE
9410 00:57:13.438542 1. 0000000040000000-00000000400fffff: RAM
9411 00:57:13.441609 2. 0000000040100000-000000004032afff: RAMSTAGE
9412 00:57:13.448287 3. 000000004032b000-00000000545fffff: RAM
9413 00:57:13.451936 4. 0000000054600000-000000005465ffff: BL31
9414 00:57:13.455151 5. 0000000054660000-00000000ffe63fff: RAM
9415 00:57:13.458210 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9416 00:57:13.465046 7. 0000000100000000-000000023fffffff: RAM
9417 00:57:13.465133 Passing 5 GPIOs to payload:
9418 00:57:13.471517 NAME | PORT | POLARITY | VALUE
9419 00:57:13.475029 EC in RW | 0x000000aa | low | undefined
9420 00:57:13.481555 EC interrupt | 0x00000005 | low | undefined
9421 00:57:13.484766 TPM interrupt | 0x000000ab | high | undefined
9422 00:57:13.488265 SD card detect | 0x00000011 | high | undefined
9423 00:57:13.494816 speaker enable | 0x00000093 | high | undefined
9424 00:57:13.498095 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9425 00:57:13.501543 in-header: 03 f9 00 00 02 00 00 00
9426 00:57:13.501642 in-data: 02 00
9427 00:57:13.504708 ADC[4]: Raw value=901770 ID=7
9428 00:57:13.508155 ADC[3]: Raw value=213179 ID=1
9429 00:57:13.508225 RAM Code: 0x71
9430 00:57:13.511427 ADC[6]: Raw value=74502 ID=0
9431 00:57:13.514813 ADC[5]: Raw value=212441 ID=1
9432 00:57:13.514885 SKU Code: 0x1
9433 00:57:13.521373 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bcf0
9434 00:57:13.525042 coreboot table: 964 bytes.
9435 00:57:13.528061 IMD ROOT 0. 0xfffff000 0x00001000
9436 00:57:13.531338 IMD SMALL 1. 0xffffe000 0x00001000
9437 00:57:13.534567 RO MCACHE 2. 0xffffc000 0x00001104
9438 00:57:13.538178 CONSOLE 3. 0xfff7c000 0x00080000
9439 00:57:13.541226 FMAP 4. 0xfff7b000 0x00000452
9440 00:57:13.544541 TIME STAMP 5. 0xfff7a000 0x00000910
9441 00:57:13.548143 VBOOT WORK 6. 0xfff66000 0x00014000
9442 00:57:13.551314 RAMOOPS 7. 0xffe66000 0x00100000
9443 00:57:13.554320 COREBOOT 8. 0xffe64000 0x00002000
9444 00:57:13.554403 IMD small region:
9445 00:57:13.557735 IMD ROOT 0. 0xffffec00 0x00000400
9446 00:57:13.561274 VPD 1. 0xffffeb80 0x0000006c
9447 00:57:13.564611 MMC STATUS 2. 0xffffeb60 0x00000004
9448 00:57:13.571160 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9449 00:57:13.571276 Probing TPM: done!
9450 00:57:13.577906 Connected to device vid:did:rid of 1ae0:0028:00
9451 00:57:13.588342 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9452 00:57:13.592328 Initialized TPM device CR50 revision 0
9453 00:57:13.592413 Checking cr50 for pending updates
9454 00:57:13.597739 Reading cr50 TPM mode
9455 00:57:13.606458 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9456 00:57:13.613413 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9457 00:57:13.653262 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9458 00:57:13.656833 Checking segment from ROM address 0x40100000
9459 00:57:13.659810 Checking segment from ROM address 0x4010001c
9460 00:57:13.666636 Loading segment from ROM address 0x40100000
9461 00:57:13.666712 code (compression=0)
9462 00:57:13.676652 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9463 00:57:13.682962 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9464 00:57:13.683041 it's not compressed!
9465 00:57:13.689710 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9466 00:57:13.693211 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9467 00:57:13.713601 Loading segment from ROM address 0x4010001c
9468 00:57:13.713726 Entry Point 0x80000000
9469 00:57:13.716926 Loaded segments
9470 00:57:13.719973 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9471 00:57:13.727135 Jumping to boot code at 0x80000000(0xffe64000)
9472 00:57:13.733388 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9473 00:57:13.740179 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9474 00:57:13.748164 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9475 00:57:13.751441 Checking segment from ROM address 0x40100000
9476 00:57:13.754547 Checking segment from ROM address 0x4010001c
9477 00:57:13.761397 Loading segment from ROM address 0x40100000
9478 00:57:13.761493 code (compression=1)
9479 00:57:13.768175 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9480 00:57:13.777849 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9481 00:57:13.777981 using LZMA
9482 00:57:13.786507 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9483 00:57:13.793153 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9484 00:57:13.796449 Loading segment from ROM address 0x4010001c
9485 00:57:13.796565 Entry Point 0x54601000
9486 00:57:13.799635 Loaded segments
9487 00:57:13.803242 NOTICE: MT8192 bl31_setup
9488 00:57:13.810004 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9489 00:57:13.813549 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9490 00:57:13.816993 WARNING: region 0:
9491 00:57:13.820418 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 00:57:13.820490 WARNING: region 1:
9493 00:57:13.826536 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9494 00:57:13.830229 WARNING: region 2:
9495 00:57:13.833287 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9496 00:57:13.836600 WARNING: region 3:
9497 00:57:13.839974 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 00:57:13.843639 WARNING: region 4:
9499 00:57:13.847001 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 00:57:13.850095 WARNING: region 5:
9501 00:57:13.853747 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 00:57:13.856819 WARNING: region 6:
9503 00:57:13.860450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 00:57:13.860551 WARNING: region 7:
9505 00:57:13.866899 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 00:57:13.873690 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9507 00:57:13.876951 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9508 00:57:13.880231 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9509 00:57:13.886951 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9510 00:57:13.890497 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9511 00:57:13.893741 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9512 00:57:13.900084 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9513 00:57:13.903656 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9514 00:57:13.909915 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9515 00:57:13.913682 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9516 00:57:13.916786 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9517 00:57:13.923485 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9518 00:57:13.927064 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9519 00:57:13.930454 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9520 00:57:13.937126 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9521 00:57:13.940285 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9522 00:57:13.943596 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9523 00:57:13.950459 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9524 00:57:13.953747 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9525 00:57:13.957059 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9526 00:57:13.963528 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9527 00:57:13.967171 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9528 00:57:13.973431 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9529 00:57:13.976767 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9530 00:57:13.983476 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9531 00:57:13.986816 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9532 00:57:13.990489 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9533 00:57:13.996832 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9534 00:57:14.000364 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9535 00:57:14.003478 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9536 00:57:14.010173 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9537 00:57:14.013744 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9538 00:57:14.017037 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9539 00:57:14.023608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9540 00:57:14.027114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9541 00:57:14.030093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9542 00:57:14.033766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9543 00:57:14.040326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9544 00:57:14.043814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9545 00:57:14.046962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9546 00:57:14.050258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9547 00:57:14.057074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9548 00:57:14.060470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9549 00:57:14.063780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9550 00:57:14.067229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9551 00:57:14.073613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9552 00:57:14.077174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9553 00:57:14.080151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9554 00:57:14.087140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9555 00:57:14.090263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9556 00:57:14.093842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9557 00:57:14.100656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9558 00:57:14.103829 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9559 00:57:14.110641 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9560 00:57:14.113736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9561 00:57:14.120475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9562 00:57:14.123764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9563 00:57:14.127065 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9564 00:57:14.133784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9565 00:57:14.137138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9566 00:57:14.143831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9567 00:57:14.146981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9568 00:57:14.153809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9569 00:57:14.157061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9570 00:57:14.160760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9571 00:57:14.167153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9572 00:57:14.170478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9573 00:57:14.177111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9574 00:57:14.181063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9575 00:57:14.187466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9576 00:57:14.190799 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9577 00:57:14.193958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9578 00:57:14.200802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9579 00:57:14.204127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9580 00:57:14.210814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9581 00:57:14.213865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9582 00:57:14.220877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9583 00:57:14.224156 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9584 00:57:14.227385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9585 00:57:14.234141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9586 00:57:14.237391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9587 00:57:14.244352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9588 00:57:14.247801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9589 00:57:14.254014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9590 00:57:14.257719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9591 00:57:14.260674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9592 00:57:14.267598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9593 00:57:14.270623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9594 00:57:14.277559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9595 00:57:14.280664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9596 00:57:14.287773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9597 00:57:14.290880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9598 00:57:14.294103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9599 00:57:14.300642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9600 00:57:14.303940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9601 00:57:14.310931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9602 00:57:14.314173 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9603 00:57:14.317435 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9604 00:57:14.324114 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9605 00:57:14.327196 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9606 00:57:14.330659 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9607 00:57:14.333972 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9608 00:57:14.340697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9609 00:57:14.344176 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9610 00:57:14.351045 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9611 00:57:14.354367 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9612 00:57:14.357437 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9613 00:57:14.364253 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9614 00:57:14.367450 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9615 00:57:14.373954 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9616 00:57:14.377498 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9617 00:57:14.380802 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9618 00:57:14.387454 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9619 00:57:14.390801 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9620 00:57:14.397470 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9621 00:57:14.401273 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9622 00:57:14.404201 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9623 00:57:14.407301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9624 00:57:14.414135 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9625 00:57:14.417479 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9626 00:57:14.421020 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9627 00:57:14.424560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9628 00:57:14.430764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9629 00:57:14.434584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9630 00:57:14.437766 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9631 00:57:14.444216 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9632 00:57:14.447697 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9633 00:57:14.454287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9634 00:57:14.457650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9635 00:57:14.461014 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9636 00:57:14.467709 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9637 00:57:14.470903 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9638 00:57:14.474233 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9639 00:57:14.480816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9640 00:57:14.484125 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9641 00:57:14.490957 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9642 00:57:14.494380 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9643 00:57:14.497731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9644 00:57:14.504421 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9645 00:57:14.507818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9646 00:57:14.511059 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9647 00:57:14.517598 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9648 00:57:14.521189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9649 00:57:14.527561 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9650 00:57:14.531179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9651 00:57:14.534390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9652 00:57:14.540836 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9653 00:57:14.544334 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9654 00:57:14.550875 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9655 00:57:14.554329 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9656 00:57:14.557637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9657 00:57:14.564091 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9658 00:57:14.567560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9659 00:57:14.574128 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9660 00:57:14.577285 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9661 00:57:14.580898 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9662 00:57:14.587646 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9663 00:57:14.591030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9664 00:57:14.597216 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9665 00:57:14.600722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9666 00:57:14.603998 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9667 00:57:14.610691 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9668 00:57:14.614110 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9669 00:57:14.620768 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9670 00:57:14.624176 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9671 00:57:14.627176 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9672 00:57:14.633630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9673 00:57:14.636904 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9674 00:57:14.643853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9675 00:57:14.647030 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9676 00:57:14.650373 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9677 00:57:14.657509 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9678 00:57:14.660301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9679 00:57:14.663704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9680 00:57:14.670272 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9681 00:57:14.673721 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9682 00:57:14.680504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9683 00:57:14.683735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9684 00:57:14.687160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9685 00:57:14.693947 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9686 00:57:14.696856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9687 00:57:14.700366 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9688 00:57:14.706932 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9689 00:57:14.710187 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9690 00:57:14.717180 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9691 00:57:14.720299 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9692 00:57:14.723716 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9693 00:57:14.730368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9694 00:57:14.733578 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9695 00:57:14.739988 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9696 00:57:14.743791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9697 00:57:14.750270 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9698 00:57:14.753486 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9699 00:57:14.756727 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9700 00:57:14.763837 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9701 00:57:14.766822 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9702 00:57:14.773298 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9703 00:57:14.777106 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9704 00:57:14.780262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9705 00:57:14.786831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9706 00:57:14.790125 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9707 00:57:14.796743 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9708 00:57:14.800205 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9709 00:57:14.807116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9710 00:57:14.810133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9711 00:57:14.813558 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9712 00:57:14.820111 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9713 00:57:14.823242 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9714 00:57:14.829980 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9715 00:57:14.833395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9716 00:57:14.836873 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9717 00:57:14.843567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9718 00:57:14.846567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9719 00:57:14.853535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9720 00:57:14.856533 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9721 00:57:14.859877 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9722 00:57:14.866787 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9723 00:57:14.870057 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9724 00:57:14.876711 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9725 00:57:14.880334 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9726 00:57:14.886405 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9727 00:57:14.889821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9728 00:57:14.893289 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9729 00:57:14.899754 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9730 00:57:14.903437 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9731 00:57:14.909691 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9732 00:57:14.913529 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9733 00:57:14.916466 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9734 00:57:14.922998 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9735 00:57:14.926583 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9736 00:57:14.929696 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9737 00:57:14.933181 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9738 00:57:14.939601 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9739 00:57:14.942900 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9740 00:57:14.946723 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9741 00:57:14.953196 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9742 00:57:14.956283 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9743 00:57:14.963076 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9744 00:57:14.966244 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9745 00:57:14.969526 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9746 00:57:14.975928 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9747 00:57:14.979426 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9748 00:57:14.982929 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9749 00:57:14.989505 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9750 00:57:14.992732 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9751 00:57:14.996105 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9752 00:57:15.002861 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9753 00:57:15.005931 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9754 00:57:15.009213 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9755 00:57:15.016090 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9756 00:57:15.019495 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9757 00:57:15.025994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9758 00:57:15.029288 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9759 00:57:15.032546 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9760 00:57:15.039157 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9761 00:57:15.042802 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9762 00:57:15.045904 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9763 00:57:15.052823 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9764 00:57:15.055873 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9765 00:57:15.059259 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9766 00:57:15.065742 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9767 00:57:15.069290 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9768 00:57:15.075713 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9769 00:57:15.078808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9770 00:57:15.082260 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9771 00:57:15.088930 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9772 00:57:15.091926 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9773 00:57:15.098520 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9774 00:57:15.102109 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9775 00:57:15.105157 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9776 00:57:15.108592 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9777 00:57:15.112223 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9778 00:57:15.118463 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9779 00:57:15.121616 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9780 00:57:15.125197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9781 00:57:15.128502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9782 00:57:15.135020 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9783 00:57:15.138659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9784 00:57:15.141802 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9785 00:57:15.144812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9786 00:57:15.151780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9787 00:57:15.154592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9788 00:57:15.161480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9789 00:57:15.164790 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9790 00:57:15.167956 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9791 00:57:15.174945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9792 00:57:15.178042 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9793 00:57:15.184775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9794 00:57:15.187826 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9795 00:57:15.191533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9796 00:57:15.198145 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9797 00:57:15.201396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9798 00:57:15.207739 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9799 00:57:15.211093 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9800 00:57:15.217581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9801 00:57:15.220972 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9802 00:57:15.224255 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9803 00:57:15.230650 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9804 00:57:15.234053 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9805 00:57:15.240644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9806 00:57:15.244343 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9807 00:57:15.247288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9808 00:57:15.253747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9809 00:57:15.257377 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9810 00:57:15.263963 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9811 00:57:15.266960 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9812 00:57:15.270640 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9813 00:57:15.277147 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9814 00:57:15.280242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9815 00:57:15.287010 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9816 00:57:15.290299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9817 00:57:15.297320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9818 00:57:15.300254 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9819 00:57:15.303762 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9820 00:57:15.310146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9821 00:57:15.313634 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9822 00:57:15.320245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9823 00:57:15.323547 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9824 00:57:15.326844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9825 00:57:15.333520 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9826 00:57:15.336892 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9827 00:57:15.343638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9828 00:57:15.346573 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9829 00:57:15.349987 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9830 00:57:15.356552 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9831 00:57:15.359724 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9832 00:57:15.366698 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9833 00:57:15.369897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9834 00:57:15.376627 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9835 00:57:15.379772 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9836 00:57:15.383131 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9837 00:57:15.389921 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9838 00:57:15.393356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9839 00:57:15.399983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9840 00:57:15.403177 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9841 00:57:15.409696 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9842 00:57:15.413119 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9843 00:57:15.416506 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9844 00:57:15.422998 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9845 00:57:15.426253 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9846 00:57:15.429621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9847 00:57:15.436412 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9848 00:57:15.439536 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9849 00:57:15.446238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9850 00:57:15.449475 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9851 00:57:15.453184 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9852 00:57:15.459828 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9853 00:57:15.463130 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9854 00:57:15.469590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9855 00:57:15.472952 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9856 00:57:15.476374 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9857 00:57:15.483145 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9858 00:57:15.486124 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9859 00:57:15.492791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9860 00:57:15.496452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9861 00:57:15.502850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9862 00:57:15.506400 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9863 00:57:15.509628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9864 00:57:15.516462 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9865 00:57:15.519379 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9866 00:57:15.526304 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9867 00:57:15.529316 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9868 00:57:15.536615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9869 00:57:15.539545 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9870 00:57:15.542783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9871 00:57:15.549324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9872 00:57:15.552651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9873 00:57:15.559386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9874 00:57:15.562826 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9875 00:57:15.569121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9876 00:57:15.572717 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9877 00:57:15.575891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9878 00:57:15.582711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9879 00:57:15.585909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9880 00:57:15.592670 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9881 00:57:15.596006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9882 00:57:15.602793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9883 00:57:15.605951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9884 00:57:15.609163 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9885 00:57:15.615942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9886 00:57:15.618891 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9887 00:57:15.625841 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9888 00:57:15.628805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9889 00:57:15.635830 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9890 00:57:15.639125 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9891 00:57:15.645316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9892 00:57:15.648588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9893 00:57:15.651987 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9894 00:57:15.658613 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9895 00:57:15.662186 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9896 00:57:15.669143 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9897 00:57:15.672610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9898 00:57:15.678678 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9899 00:57:15.681852 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9900 00:57:15.685516 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9901 00:57:15.691800 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9902 00:57:15.695636 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9903 00:57:15.701913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9904 00:57:15.705167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9905 00:57:15.711647 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9906 00:57:15.715138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9907 00:57:15.721666 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9908 00:57:15.725204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9909 00:57:15.728327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9910 00:57:15.734914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9911 00:57:15.738297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9912 00:57:15.744899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9913 00:57:15.748414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9914 00:57:15.755018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9915 00:57:15.758198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9916 00:57:15.764707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9917 00:57:15.768168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9918 00:57:15.774663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9919 00:57:15.777976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9920 00:57:15.784929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9921 00:57:15.788085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9922 00:57:15.794785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9923 00:57:15.797883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9924 00:57:15.804494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9925 00:57:15.808146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9926 00:57:15.811203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9927 00:57:15.818037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9928 00:57:15.821306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9929 00:57:15.827842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9930 00:57:15.834821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9931 00:57:15.837978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9932 00:57:15.844228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9933 00:57:15.847982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9934 00:57:15.854517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9935 00:57:15.857753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9936 00:57:15.864355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9937 00:57:15.867911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9938 00:57:15.874204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9939 00:57:15.877742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9940 00:57:15.880676 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9941 00:57:15.883880 INFO: [APUAPC] vio 0
9942 00:57:15.887327 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9943 00:57:15.894501 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9944 00:57:15.897549 INFO: [APUAPC] D0_APC_0: 0x400510
9945 00:57:15.901176 INFO: [APUAPC] D0_APC_1: 0x0
9946 00:57:15.904226 INFO: [APUAPC] D0_APC_2: 0x1540
9947 00:57:15.904311 INFO: [APUAPC] D0_APC_3: 0x0
9948 00:57:15.907608 INFO: [APUAPC] D1_APC_0: 0xffffffff
9949 00:57:15.914122 INFO: [APUAPC] D1_APC_1: 0xffffffff
9950 00:57:15.917815 INFO: [APUAPC] D1_APC_2: 0x3fffff
9951 00:57:15.917899 INFO: [APUAPC] D1_APC_3: 0x0
9952 00:57:15.920949 INFO: [APUAPC] D2_APC_0: 0xffffffff
9953 00:57:15.924189 INFO: [APUAPC] D2_APC_1: 0xffffffff
9954 00:57:15.927552 INFO: [APUAPC] D2_APC_2: 0x3fffff
9955 00:57:15.930884 INFO: [APUAPC] D2_APC_3: 0x0
9956 00:57:15.934137 INFO: [APUAPC] D3_APC_0: 0xffffffff
9957 00:57:15.937301 INFO: [APUAPC] D3_APC_1: 0xffffffff
9958 00:57:15.940735 INFO: [APUAPC] D3_APC_2: 0x3fffff
9959 00:57:15.943866 INFO: [APUAPC] D3_APC_3: 0x0
9960 00:57:15.947111 INFO: [APUAPC] D4_APC_0: 0xffffffff
9961 00:57:15.950664 INFO: [APUAPC] D4_APC_1: 0xffffffff
9962 00:57:15.953674 INFO: [APUAPC] D4_APC_2: 0x3fffff
9963 00:57:15.956882 INFO: [APUAPC] D4_APC_3: 0x0
9964 00:57:15.960337 INFO: [APUAPC] D5_APC_0: 0xffffffff
9965 00:57:15.963641 INFO: [APUAPC] D5_APC_1: 0xffffffff
9966 00:57:15.967081 INFO: [APUAPC] D5_APC_2: 0x3fffff
9967 00:57:15.970575 INFO: [APUAPC] D5_APC_3: 0x0
9968 00:57:15.973357 INFO: [APUAPC] D6_APC_0: 0xffffffff
9969 00:57:15.976620 INFO: [APUAPC] D6_APC_1: 0xffffffff
9970 00:57:15.980355 INFO: [APUAPC] D6_APC_2: 0x3fffff
9971 00:57:15.983599 INFO: [APUAPC] D6_APC_3: 0x0
9972 00:57:15.986856 INFO: [APUAPC] D7_APC_0: 0xffffffff
9973 00:57:15.990157 INFO: [APUAPC] D7_APC_1: 0xffffffff
9974 00:57:15.993355 INFO: [APUAPC] D7_APC_2: 0x3fffff
9975 00:57:15.997107 INFO: [APUAPC] D7_APC_3: 0x0
9976 00:57:15.999952 INFO: [APUAPC] D8_APC_0: 0xffffffff
9977 00:57:16.003675 INFO: [APUAPC] D8_APC_1: 0xffffffff
9978 00:57:16.006913 INFO: [APUAPC] D8_APC_2: 0x3fffff
9979 00:57:16.010336 INFO: [APUAPC] D8_APC_3: 0x0
9980 00:57:16.013073 INFO: [APUAPC] D9_APC_0: 0xffffffff
9981 00:57:16.016269 INFO: [APUAPC] D9_APC_1: 0xffffffff
9982 00:57:16.019961 INFO: [APUAPC] D9_APC_2: 0x3fffff
9983 00:57:16.023048 INFO: [APUAPC] D9_APC_3: 0x0
9984 00:57:16.026652 INFO: [APUAPC] D10_APC_0: 0xffffffff
9985 00:57:16.029807 INFO: [APUAPC] D10_APC_1: 0xffffffff
9986 00:57:16.033330 INFO: [APUAPC] D10_APC_2: 0x3fffff
9987 00:57:16.036276 INFO: [APUAPC] D10_APC_3: 0x0
9988 00:57:16.039454 INFO: [APUAPC] D11_APC_0: 0xffffffff
9989 00:57:16.043036 INFO: [APUAPC] D11_APC_1: 0xffffffff
9990 00:57:16.046353 INFO: [APUAPC] D11_APC_2: 0x3fffff
9991 00:57:16.049549 INFO: [APUAPC] D11_APC_3: 0x0
9992 00:57:16.053021 INFO: [APUAPC] D12_APC_0: 0xffffffff
9993 00:57:16.056171 INFO: [APUAPC] D12_APC_1: 0xffffffff
9994 00:57:16.059575 INFO: [APUAPC] D12_APC_2: 0x3fffff
9995 00:57:16.062672 INFO: [APUAPC] D12_APC_3: 0x0
9996 00:57:16.066154 INFO: [APUAPC] D13_APC_0: 0xffffffff
9997 00:57:16.069563 INFO: [APUAPC] D13_APC_1: 0xffffffff
9998 00:57:16.072946 INFO: [APUAPC] D13_APC_2: 0x3fffff
9999 00:57:16.076239 INFO: [APUAPC] D13_APC_3: 0x0
10000 00:57:16.079146 INFO: [APUAPC] D14_APC_0: 0xffffffff
10001 00:57:16.082658 INFO: [APUAPC] D14_APC_1: 0xffffffff
10002 00:57:16.086367 INFO: [APUAPC] D14_APC_2: 0x3fffff
10003 00:57:16.089534 INFO: [APUAPC] D14_APC_3: 0x0
10004 00:57:16.092831 INFO: [APUAPC] D15_APC_0: 0xffffffff
10005 00:57:16.096044 INFO: [APUAPC] D15_APC_1: 0xffffffff
10006 00:57:16.099230 INFO: [APUAPC] D15_APC_2: 0x3fffff
10007 00:57:16.102450 INFO: [APUAPC] D15_APC_3: 0x0
10008 00:57:16.105718 INFO: [APUAPC] APC_CON: 0x4
10009 00:57:16.109460 INFO: [NOCDAPC] D0_APC_0: 0x0
10010 00:57:16.112469 INFO: [NOCDAPC] D0_APC_1: 0x0
10011 00:57:16.115745 INFO: [NOCDAPC] D1_APC_0: 0x0
10012 00:57:16.119116 INFO: [NOCDAPC] D1_APC_1: 0xfff
10013 00:57:16.119200 INFO: [NOCDAPC] D2_APC_0: 0x0
10014 00:57:16.122713 INFO: [NOCDAPC] D2_APC_1: 0xfff
10015 00:57:16.125744 INFO: [NOCDAPC] D3_APC_0: 0x0
10016 00:57:16.129489 INFO: [NOCDAPC] D3_APC_1: 0xfff
10017 00:57:16.132321 INFO: [NOCDAPC] D4_APC_0: 0x0
10018 00:57:16.135745 INFO: [NOCDAPC] D4_APC_1: 0xfff
10019 00:57:16.139047 INFO: [NOCDAPC] D5_APC_0: 0x0
10020 00:57:16.142481 INFO: [NOCDAPC] D5_APC_1: 0xfff
10021 00:57:16.145852 INFO: [NOCDAPC] D6_APC_0: 0x0
10022 00:57:16.149142 INFO: [NOCDAPC] D6_APC_1: 0xfff
10023 00:57:16.149226 INFO: [NOCDAPC] D7_APC_0: 0x0
10024 00:57:16.152425 INFO: [NOCDAPC] D7_APC_1: 0xfff
10025 00:57:16.155744 INFO: [NOCDAPC] D8_APC_0: 0x0
10026 00:57:16.159238 INFO: [NOCDAPC] D8_APC_1: 0xfff
10027 00:57:16.162840 INFO: [NOCDAPC] D9_APC_0: 0x0
10028 00:57:16.165823 INFO: [NOCDAPC] D9_APC_1: 0xfff
10029 00:57:16.168940 INFO: [NOCDAPC] D10_APC_0: 0x0
10030 00:57:16.172264 INFO: [NOCDAPC] D10_APC_1: 0xfff
10031 00:57:16.175875 INFO: [NOCDAPC] D11_APC_0: 0x0
10032 00:57:16.179288 INFO: [NOCDAPC] D11_APC_1: 0xfff
10033 00:57:16.182524 INFO: [NOCDAPC] D12_APC_0: 0x0
10034 00:57:16.185592 INFO: [NOCDAPC] D12_APC_1: 0xfff
10035 00:57:16.189168 INFO: [NOCDAPC] D13_APC_0: 0x0
10036 00:57:16.189252 INFO: [NOCDAPC] D13_APC_1: 0xfff
10037 00:57:16.192189 INFO: [NOCDAPC] D14_APC_0: 0x0
10038 00:57:16.195801 INFO: [NOCDAPC] D14_APC_1: 0xfff
10039 00:57:16.198692 INFO: [NOCDAPC] D15_APC_0: 0x0
10040 00:57:16.202059 INFO: [NOCDAPC] D15_APC_1: 0xfff
10041 00:57:16.205496 INFO: [NOCDAPC] APC_CON: 0x4
10042 00:57:16.208825 INFO: [APUAPC] set_apusys_apc done
10043 00:57:16.212244 INFO: [DEVAPC] devapc_init done
10044 00:57:16.215435 INFO: GICv3 without legacy support detected.
10045 00:57:16.221866 INFO: ARM GICv3 driver initialized in EL3
10046 00:57:16.225129 INFO: Maximum SPI INTID supported: 639
10047 00:57:16.228876 INFO: BL31: Initializing runtime services
10048 00:57:16.235342 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10049 00:57:16.235427 INFO: SPM: enable CPC mode
10050 00:57:16.241556 INFO: mcdi ready for mcusys-off-idle and system suspend
10051 00:57:16.244908 INFO: BL31: Preparing for EL3 exit to normal world
10052 00:57:16.251708 INFO: Entry point address = 0x80000000
10053 00:57:16.251793 INFO: SPSR = 0x8
10054 00:57:16.257935
10055 00:57:16.258026
10056 00:57:16.258092
10057 00:57:16.261352 Starting depthcharge on Spherion...
10058 00:57:16.261436
10059 00:57:16.261502 Wipe memory regions:
10060 00:57:16.261563
10061 00:57:16.262213 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10062 00:57:16.262315 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10063 00:57:16.262400 Setting prompt string to ['asurada:']
10064 00:57:16.262480 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10065 00:57:16.264620 [0x00000040000000, 0x00000054600000)
10066 00:57:16.386786
10067 00:57:16.386899 [0x00000054660000, 0x00000080000000)
10068 00:57:16.647598
10069 00:57:16.647731 [0x000000821a7280, 0x000000ffe64000)
10070 00:57:17.392467
10071 00:57:17.392601 [0x00000100000000, 0x00000240000000)
10072 00:57:19.282844
10073 00:57:19.285983 Initializing XHCI USB controller at 0x11200000.
10074 00:57:20.323890
10075 00:57:20.326988 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10076 00:57:20.327105
10077 00:57:20.327204
10078 00:57:20.327269
10079 00:57:20.327548 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 00:57:20.427912 asurada: tftpboot 192.168.201.1 12571130/tftp-deploy-ryvd6b8t/kernel/image.itb 12571130/tftp-deploy-ryvd6b8t/kernel/cmdline
10082 00:57:20.428065 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 00:57:20.428168 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 00:57:20.432262 tftpboot 192.168.201.1 12571130/tftp-deploy-ryvd6b8t/kernel/image.itp-deploy-ryvd6b8t/kernel/cmdline
10085 00:57:20.432349
10086 00:57:20.432417 Waiting for link
10087 00:57:20.592872
10088 00:57:20.593003 R8152: Initializing
10089 00:57:20.593070
10090 00:57:20.595963 Version 9 (ocp_data = 6010)
10091 00:57:20.596049
10092 00:57:20.599194 R8152: Done initializing
10093 00:57:20.599279
10094 00:57:20.599345 Adding net device
10095 00:57:22.472032
10096 00:57:22.472172 done.
10097 00:57:22.472276
10098 00:57:22.472339 MAC: 00:e0:4c:72:2d:d6
10099 00:57:22.472400
10100 00:57:22.475297 Sending DHCP discover... done.
10101 00:57:22.475384
10102 00:57:22.478474 Waiting for reply... done.
10103 00:57:22.478561
10104 00:57:22.482199 Sending DHCP request... done.
10105 00:57:22.482283
10106 00:57:22.482350 Waiting for reply... done.
10107 00:57:22.482411
10108 00:57:22.485313 My ip is 192.168.201.21
10109 00:57:22.485409
10110 00:57:22.488714 The DHCP server ip is 192.168.201.1
10111 00:57:22.488799
10112 00:57:22.492020 TFTP server IP predefined by user: 192.168.201.1
10113 00:57:22.492105
10114 00:57:22.498612 Bootfile predefined by user: 12571130/tftp-deploy-ryvd6b8t/kernel/image.itb
10115 00:57:22.498697
10116 00:57:22.501682 Sending tftp read request... done.
10117 00:57:22.501766
10118 00:57:22.505099 Waiting for the transfer...
10119 00:57:22.505187
10120 00:57:22.771918 00000000 ################################################################
10121 00:57:22.772058
10122 00:57:23.011315 00080000 ################################################################
10123 00:57:23.011441
10124 00:57:23.254250 00100000 ################################################################
10125 00:57:23.254378
10126 00:57:23.496105 00180000 ################################################################
10127 00:57:23.496232
10128 00:57:23.740356 00200000 ################################################################
10129 00:57:23.740520
10130 00:57:23.985695 00280000 ################################################################
10131 00:57:23.985824
10132 00:57:24.230691 00300000 ################################################################
10133 00:57:24.230816
10134 00:57:24.473240 00380000 ################################################################
10135 00:57:24.473383
10136 00:57:24.714173 00400000 ################################################################
10137 00:57:24.714309
10138 00:57:24.959764 00480000 ################################################################
10139 00:57:24.959923
10140 00:57:25.205172 00500000 ################################################################
10141 00:57:25.205306
10142 00:57:25.453863 00580000 ################################################################
10143 00:57:25.454029
10144 00:57:25.698733 00600000 ################################################################
10145 00:57:25.698875
10146 00:57:25.954511 00680000 ################################################################
10147 00:57:25.954640
10148 00:57:26.224036 00700000 ################################################################
10149 00:57:26.224165
10150 00:57:26.479103 00780000 ################################################################
10151 00:57:26.479235
10152 00:57:26.720748 00800000 ################################################################
10153 00:57:26.720909
10154 00:57:26.976554 00880000 ################################################################
10155 00:57:26.976707
10156 00:57:27.222461 00900000 ################################################################
10157 00:57:27.222588
10158 00:57:27.464805 00980000 ################################################################
10159 00:57:27.464969
10160 00:57:27.707761 00a00000 ################################################################
10161 00:57:27.707914
10162 00:57:27.951701 00a80000 ################################################################
10163 00:57:27.951864
10164 00:57:28.195557 00b00000 ################################################################
10165 00:57:28.195685
10166 00:57:28.463354 00b80000 ################################################################
10167 00:57:28.463485
10168 00:57:28.714069 00c00000 ################################################################
10169 00:57:28.714212
10170 00:57:28.958303 00c80000 ################################################################
10171 00:57:28.958434
10172 00:57:29.198515 00d00000 ################################################################
10173 00:57:29.198646
10174 00:57:29.439712 00d80000 ################################################################
10175 00:57:29.439853
10176 00:57:29.680376 00e00000 ################################################################
10177 00:57:29.680509
10178 00:57:29.921589 00e80000 ################################################################
10179 00:57:29.921727
10180 00:57:30.163133 00f00000 ################################################################
10181 00:57:30.163268
10182 00:57:30.404416 00f80000 ################################################################
10183 00:57:30.404549
10184 00:57:30.647014 01000000 ################################################################
10185 00:57:30.647138
10186 00:57:30.903788 01080000 ################################################################
10187 00:57:30.903929
10188 00:57:31.156051 01100000 ################################################################
10189 00:57:31.156204
10190 00:57:31.398429 01180000 ################################################################
10191 00:57:31.398556
10192 00:57:31.639844 01200000 ################################################################
10193 00:57:31.639966
10194 00:57:31.881823 01280000 ################################################################
10195 00:57:31.881983
10196 00:57:32.124073 01300000 ################################################################
10197 00:57:32.124204
10198 00:57:32.365861 01380000 ################################################################
10199 00:57:32.366024
10200 00:57:32.609762 01400000 ################################################################
10201 00:57:32.609891
10202 00:57:32.850482 01480000 ################################################################
10203 00:57:32.850610
10204 00:57:33.092192 01500000 ################################################################
10205 00:57:33.092320
10206 00:57:33.334756 01580000 ################################################################
10207 00:57:33.334906
10208 00:57:33.577033 01600000 ################################################################
10209 00:57:33.577166
10210 00:57:33.818700 01680000 ################################################################
10211 00:57:33.818821
10212 00:57:34.061526 01700000 ################################################################
10213 00:57:34.061666
10214 00:57:34.304133 01780000 ################################################################
10215 00:57:34.304272
10216 00:57:34.549782 01800000 ################################################################
10217 00:57:34.549920
10218 00:57:34.796720 01880000 ################################################################
10219 00:57:34.796858
10220 00:57:35.037710 01900000 ################################################################
10221 00:57:35.037850
10222 00:57:35.279209 01980000 ################################################################
10223 00:57:35.279341
10224 00:57:35.520983 01a00000 ################################################################
10225 00:57:35.521117
10226 00:57:35.762667 01a80000 ################################################################
10227 00:57:35.762791
10228 00:57:36.004591 01b00000 ################################################################
10229 00:57:36.004729
10230 00:57:36.246415 01b80000 ################################################################
10231 00:57:36.246541
10232 00:57:36.497360 01c00000 ################################################################
10233 00:57:36.497503
10234 00:57:36.757344 01c80000 ################################################################
10235 00:57:36.757483
10236 00:57:37.021166 01d00000 ################################################################
10237 00:57:37.021310
10238 00:57:37.286239 01d80000 ################################################################
10239 00:57:37.286378
10240 00:57:37.546088 01e00000 ################################################################
10241 00:57:37.546230
10242 00:57:37.797092 01e80000 ################################################################
10243 00:57:37.797221
10244 00:57:38.050213 01f00000 ################################################################
10245 00:57:38.050368
10246 00:57:38.268783 01f80000 ########################################################## done.
10247 00:57:38.268919
10248 00:57:38.272402 The bootfile was 33497530 bytes long.
10249 00:57:38.272490
10250 00:57:38.275185 Sending tftp read request... done.
10251 00:57:38.275296
10252 00:57:38.275396 Waiting for the transfer...
10253 00:57:38.275486
10254 00:57:38.278820 00000000 # done.
10255 00:57:38.278907
10256 00:57:38.285045 Command line loaded dynamically from TFTP file: 12571130/tftp-deploy-ryvd6b8t/kernel/cmdline
10257 00:57:38.285130
10258 00:57:38.298402 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10259 00:57:38.298490
10260 00:57:38.301548 Loading FIT.
10261 00:57:38.301633
10262 00:57:38.304914 Image ramdisk-1 has 21399595 bytes.
10263 00:57:38.304999
10264 00:57:38.308195 Image fdt-1 has 47278 bytes.
10265 00:57:38.308280
10266 00:57:38.308346 Image kernel-1 has 12048624 bytes.
10267 00:57:38.312046
10268 00:57:38.318219 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10269 00:57:38.318305
10270 00:57:38.334744 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10271 00:57:38.338250
10272 00:57:38.341425 Choosing best match conf-1 for compat google,spherion-rev2.
10273 00:57:38.346118
10274 00:57:38.350851 Connected to device vid:did:rid of 1ae0:0028:00
10275 00:57:38.357373
10276 00:57:38.360832 tpm_get_response: command 0x17b, return code 0x0
10277 00:57:38.360917
10278 00:57:38.364167 ec_init: CrosEC protocol v3 supported (256, 248)
10279 00:57:38.368007
10280 00:57:38.371485 tpm_cleanup: add release locality here.
10281 00:57:38.371596
10282 00:57:38.371696 Shutting down all USB controllers.
10283 00:57:38.374864
10284 00:57:38.374948 Removing current net device
10285 00:57:38.375016
10286 00:57:38.381423 Exiting depthcharge with code 4 at timestamp: 51474520
10287 00:57:38.381508
10288 00:57:38.384782 LZMA decompressing kernel-1 to 0x821a6718
10289 00:57:38.384867
10290 00:57:38.388013 LZMA decompressing kernel-1 to 0x40000000
10291 00:57:39.886863
10292 00:57:39.887031 jumping to kernel
10293 00:57:39.887897 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10294 00:57:39.888025 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10295 00:57:39.888126 Setting prompt string to ['Linux version [0-9]']
10296 00:57:39.888223 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10297 00:57:39.888318 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10298 00:57:39.968922
10299 00:57:39.972106 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10300 00:57:39.976267 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10301 00:57:39.976879 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10302 00:57:39.977347 Setting prompt string to []
10303 00:57:39.977884 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10304 00:57:39.978336 Using line separator: #'\n'#
10305 00:57:39.978689 No login prompt set.
10306 00:57:39.979257 Parsing kernel messages
10307 00:57:39.979704 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10308 00:57:39.980641 [login-action] Waiting for messages, (timeout 00:04:01)
10309 00:57:39.995410 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10310 00:57:39.998926 [ 0.000000] random: crng init done
10311 00:57:40.005812 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 00:57:40.006346 [ 0.000000] efi: UEFI not found.
10313 00:57:40.015419 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 00:57:40.021748 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 00:57:40.032140 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 00:57:40.042055 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 00:57:40.048486 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 00:57:40.055177 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 00:57:40.061707 [ 0.000000] NUMA: No NUMA configuration found
10320 00:57:40.068435 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 00:57:40.071499 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10322 00:57:40.075498 [ 0.000000] Zone ranges:
10323 00:57:40.081749 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 00:57:40.085128 [ 0.000000] DMA32 empty
10325 00:57:40.091729 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 00:57:40.094893 [ 0.000000] Movable zone start for each node
10327 00:57:40.098313 [ 0.000000] Early memory node ranges
10328 00:57:40.104755 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 00:57:40.111361 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 00:57:40.118315 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 00:57:40.124798 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 00:57:40.127962 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 00:57:40.137758 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 00:57:40.193636 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 00:57:40.200007 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 00:57:40.206749 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 00:57:40.210091 [ 0.000000] psci: probing for conduit method from DT.
10338 00:57:40.217056 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 00:57:40.220463 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 00:57:40.227115 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 00:57:40.229868 [ 0.000000] psci: SMC Calling Convention v1.2
10342 00:57:40.236847 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10343 00:57:40.240078 [ 0.000000] Detected VIPT I-cache on CPU0
10344 00:57:40.246606 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 00:57:40.253292 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 00:57:40.260153 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 00:57:40.267206 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 00:57:40.273433 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 00:57:40.280183 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 00:57:40.286856 [ 0.000000] alternatives: applying boot alternatives
10351 00:57:40.289905 [ 0.000000] Fallback order for Node 0: 0
10352 00:57:40.299789 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 00:57:40.299875 [ 0.000000] Policy zone: Normal
10354 00:57:40.316457 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10355 00:57:40.325955 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 00:57:40.337769 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 00:57:40.347695 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 00:57:40.354383 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 00:57:40.357847 <6>[ 0.000000] software IO TLB: area num 8.
10360 00:57:40.414353 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 00:57:40.563206 <6>[ 0.000000] Memory: 7946360K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 406408K reserved, 32768K cma-reserved)
10362 00:57:40.570005 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 00:57:40.576557 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 00:57:40.579898 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 00:57:40.586279 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 00:57:40.592919 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 00:57:40.596167 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 00:57:40.606294 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 00:57:40.612789 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 00:57:40.619598 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 00:57:40.626009 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 00:57:40.629391 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 00:57:40.632629 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 00:57:40.639331 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 00:57:40.642443 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 00:57:40.649507 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 00:57:40.662418 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 00:57:40.672445 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 00:57:40.682618 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 00:57:40.690062 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 00:57:40.702815 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 00:57:40.709454 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 00:57:40.715960 <6>[ 0.009181] Console: colour dummy device 80x25
10384 00:57:40.725901 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 00:57:40.732750 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10386 00:57:40.735995 <6>[ 0.029221] LSM: Security Framework initializing
10387 00:57:40.742802 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 00:57:40.752537 <6>[ 0.042023] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 00:57:40.759375 <6>[ 0.051438] cblist_init_generic: Setting adjustable number of callback queues.
10390 00:57:40.765854 <6>[ 0.058881] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 00:57:40.775904 <6>[ 0.065259] cblist_init_generic: Setting adjustable number of callback queues.
10392 00:57:40.782595 <6>[ 0.072686] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 00:57:40.786054 <6>[ 0.079127] rcu: Hierarchical SRCU implementation.
10394 00:57:40.792401 <6>[ 0.084174] rcu: Max phase no-delay instances is 1000.
10395 00:57:40.799162 <6>[ 0.091197] EFI services will not be available.
10396 00:57:40.802453 <6>[ 0.096151] smp: Bringing up secondary CPUs ...
10397 00:57:40.810448 <6>[ 0.101201] Detected VIPT I-cache on CPU1
10398 00:57:40.816941 <6>[ 0.101271] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 00:57:40.823613 <6>[ 0.101301] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 00:57:40.827206 <6>[ 0.101640] Detected VIPT I-cache on CPU2
10401 00:57:40.833657 <6>[ 0.101693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 00:57:40.840544 <6>[ 0.101710] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 00:57:40.846860 <6>[ 0.101969] Detected VIPT I-cache on CPU3
10404 00:57:40.853411 <6>[ 0.102015] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 00:57:40.860501 <6>[ 0.102030] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 00:57:40.863823 <6>[ 0.102335] CPU features: detected: Spectre-v4
10407 00:57:40.870166 <6>[ 0.102342] CPU features: detected: Spectre-BHB
10408 00:57:40.873738 <6>[ 0.102347] Detected PIPT I-cache on CPU4
10409 00:57:40.880146 <6>[ 0.102403] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 00:57:40.886853 <6>[ 0.102419] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 00:57:40.893476 <6>[ 0.102712] Detected PIPT I-cache on CPU5
10412 00:57:40.900246 <6>[ 0.102774] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 00:57:40.906775 <6>[ 0.102791] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 00:57:40.910141 <6>[ 0.103072] Detected PIPT I-cache on CPU6
10415 00:57:40.916862 <6>[ 0.103137] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 00:57:40.923204 <6>[ 0.103154] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 00:57:40.929999 <6>[ 0.103453] Detected PIPT I-cache on CPU7
10418 00:57:40.936575 <6>[ 0.103518] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 00:57:40.943004 <6>[ 0.103534] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 00:57:40.946684 <6>[ 0.103583] smp: Brought up 1 node, 8 CPUs
10421 00:57:40.952900 <6>[ 0.244884] SMP: Total of 8 processors activated.
10422 00:57:40.956224 <6>[ 0.249805] CPU features: detected: 32-bit EL0 Support
10423 00:57:40.966315 <6>[ 0.255167] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 00:57:40.973315 <6>[ 0.263967] CPU features: detected: Common not Private translations
10425 00:57:40.976079 <6>[ 0.270443] CPU features: detected: CRC32 instructions
10426 00:57:40.982790 <6>[ 0.275795] CPU features: detected: RCpc load-acquire (LDAPR)
10427 00:57:40.989683 <6>[ 0.281754] CPU features: detected: LSE atomic instructions
10428 00:57:40.996574 <6>[ 0.287535] CPU features: detected: Privileged Access Never
10429 00:57:40.999424 <6>[ 0.293315] CPU features: detected: RAS Extension Support
10430 00:57:41.009475 <6>[ 0.298959] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 00:57:41.012641 <6>[ 0.306182] CPU: All CPU(s) started at EL2
10432 00:57:41.019352 <6>[ 0.310499] alternatives: applying system-wide alternatives
10433 00:57:41.028165 <6>[ 0.321165] devtmpfs: initialized
10434 00:57:41.040590 <6>[ 0.330018] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 00:57:41.050167 <6>[ 0.339978] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 00:57:41.057102 <6>[ 0.348219] pinctrl core: initialized pinctrl subsystem
10437 00:57:41.060468 <6>[ 0.354848] DMI not present or invalid.
10438 00:57:41.066755 <6>[ 0.359258] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 00:57:41.076679 <6>[ 0.366132] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 00:57:41.083245 <6>[ 0.373719] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 00:57:41.093398 <6>[ 0.381949] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 00:57:41.096772 <6>[ 0.390189] audit: initializing netlink subsys (disabled)
10443 00:57:41.106758 <5>[ 0.395882] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 00:57:41.113335 <6>[ 0.396575] thermal_sys: Registered thermal governor 'step_wise'
10445 00:57:41.119823 <6>[ 0.403849] thermal_sys: Registered thermal governor 'power_allocator'
10446 00:57:41.123282 <6>[ 0.410106] cpuidle: using governor menu
10447 00:57:41.129817 <6>[ 0.421066] NET: Registered PF_QIPCRTR protocol family
10448 00:57:41.136608 <6>[ 0.426536] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 00:57:41.142991 <6>[ 0.433641] ASID allocator initialised with 32768 entries
10450 00:57:41.146277 <6>[ 0.440199] Serial: AMBA PL011 UART driver
10451 00:57:41.156161 <4>[ 0.448918] Trying to register duplicate clock ID: 134
10452 00:57:41.209780 <6>[ 0.505872] KASLR enabled
10453 00:57:41.224000 <6>[ 0.513585] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 00:57:41.230799 <6>[ 0.520595] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 00:57:41.237307 <6>[ 0.527085] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 00:57:41.244175 <6>[ 0.534088] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 00:57:41.250522 <6>[ 0.540577] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 00:57:41.257438 <6>[ 0.547581] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 00:57:41.263579 <6>[ 0.554069] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 00:57:41.270376 <6>[ 0.561073] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 00:57:41.273580 <6>[ 0.568571] ACPI: Interpreter disabled.
10462 00:57:41.282443 <6>[ 0.574981] iommu: Default domain type: Translated
10463 00:57:41.288655 <6>[ 0.580093] iommu: DMA domain TLB invalidation policy: strict mode
10464 00:57:41.292209 <5>[ 0.586751] SCSI subsystem initialized
10465 00:57:41.299043 <6>[ 0.590915] usbcore: registered new interface driver usbfs
10466 00:57:41.305320 <6>[ 0.596648] usbcore: registered new interface driver hub
10467 00:57:41.308818 <6>[ 0.602199] usbcore: registered new device driver usb
10468 00:57:41.315533 <6>[ 0.608295] pps_core: LinuxPPS API ver. 1 registered
10469 00:57:41.325537 <6>[ 0.613490] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 00:57:41.328817 <6>[ 0.622838] PTP clock support registered
10471 00:57:41.332078 <6>[ 0.627081] EDAC MC: Ver: 3.0.0
10472 00:57:41.339328 <6>[ 0.632244] FPGA manager framework
10473 00:57:41.346163 <6>[ 0.635923] Advanced Linux Sound Architecture Driver Initialized.
10474 00:57:41.349513 <6>[ 0.642696] vgaarb: loaded
10475 00:57:41.355944 <6>[ 0.645842] clocksource: Switched to clocksource arch_sys_counter
10476 00:57:41.359143 <5>[ 0.652280] VFS: Disk quotas dquot_6.6.0
10477 00:57:41.366051 <6>[ 0.656468] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 00:57:41.369396 <6>[ 0.663657] pnp: PnP ACPI: disabled
10479 00:57:41.377212 <6>[ 0.670292] NET: Registered PF_INET protocol family
10480 00:57:41.387306 <6>[ 0.675886] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 00:57:41.398704 <6>[ 0.688216] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 00:57:41.408757 <6>[ 0.697029] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 00:57:41.415236 <6>[ 0.704997] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 00:57:41.422040 <6>[ 0.713698] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 00:57:41.433936 <6>[ 0.723451] TCP: Hash tables configured (established 65536 bind 65536)
10486 00:57:41.440902 <6>[ 0.730308] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 00:57:41.447351 <6>[ 0.737507] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 00:57:41.453915 <6>[ 0.745210] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 00:57:41.460616 <6>[ 0.751379] RPC: Registered named UNIX socket transport module.
10490 00:57:41.464059 <6>[ 0.757532] RPC: Registered udp transport module.
10491 00:57:41.470735 <6>[ 0.762465] RPC: Registered tcp transport module.
10492 00:57:41.477082 <6>[ 0.767398] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 00:57:41.480329 <6>[ 0.774067] PCI: CLS 0 bytes, default 64
10494 00:57:41.483660 <6>[ 0.778448] Unpacking initramfs...
10495 00:57:41.500840 <6>[ 0.790439] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 00:57:41.511064 <6>[ 0.799096] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 00:57:41.514054 <6>[ 0.807945] kvm [1]: IPA Size Limit: 40 bits
10498 00:57:41.520683 <6>[ 0.812473] kvm [1]: GICv3: no GICV resource entry
10499 00:57:41.523814 <6>[ 0.817496] kvm [1]: disabling GICv2 emulation
10500 00:57:41.530132 <6>[ 0.822182] kvm [1]: GIC system register CPU interface enabled
10501 00:57:41.533414 <6>[ 0.828352] kvm [1]: vgic interrupt IRQ18
10502 00:57:41.540282 <6>[ 0.832708] kvm [1]: VHE mode initialized successfully
10503 00:57:41.546854 <5>[ 0.839126] Initialise system trusted keyrings
10504 00:57:41.553537 <6>[ 0.843925] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 00:57:41.560828 <6>[ 0.853934] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 00:57:41.567516 <5>[ 0.860402] NFS: Registering the id_resolver key type
10507 00:57:41.570820 <5>[ 0.865713] Key type id_resolver registered
10508 00:57:41.577360 <5>[ 0.870130] Key type id_legacy registered
10509 00:57:41.583904 <6>[ 0.874418] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 00:57:41.590653 <6>[ 0.881339] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 00:57:41.597213 <6>[ 0.889110] 9p: Installing v9fs 9p2000 file system support
10512 00:57:41.634789 <5>[ 0.927456] Key type asymmetric registered
10513 00:57:41.637898 <5>[ 0.931790] Asymmetric key parser 'x509' registered
10514 00:57:41.648009 <6>[ 0.936935] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 00:57:41.650808 <6>[ 0.944548] io scheduler mq-deadline registered
10516 00:57:41.654152 <6>[ 0.949328] io scheduler kyber registered
10517 00:57:41.673341 <6>[ 0.966461] EINJ: ACPI disabled.
10518 00:57:41.705445 <4>[ 0.991824] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 00:57:41.715107 <4>[ 1.002443] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 00:57:41.729859 <6>[ 1.023052] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 00:57:41.737878 <6>[ 1.031080] printk: console [ttyS0] disabled
10522 00:57:41.765912 <6>[ 1.055728] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 00:57:41.772925 <6>[ 1.065201] printk: console [ttyS0] enabled
10524 00:57:41.776036 <6>[ 1.065201] printk: console [ttyS0] enabled
10525 00:57:41.782835 <6>[ 1.074095] printk: bootconsole [mtk8250] disabled
10526 00:57:41.786232 <6>[ 1.074095] printk: bootconsole [mtk8250] disabled
10527 00:57:41.792998 <6>[ 1.085362] SuperH (H)SCI(F) driver initialized
10528 00:57:41.795919 <6>[ 1.090666] msm_serial: driver initialized
10529 00:57:41.810407 <6>[ 1.099684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 00:57:41.820178 <6>[ 1.108241] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 00:57:41.826793 <6>[ 1.116784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 00:57:41.836814 <6>[ 1.125416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 00:57:41.843801 <6>[ 1.134124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 00:57:41.853477 <6>[ 1.142837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 00:57:41.863704 <6>[ 1.151388] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 00:57:41.869778 <6>[ 1.160200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 00:57:41.879896 <6>[ 1.168749] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 00:57:41.891446 <6>[ 1.184386] loop: module loaded
10539 00:57:41.898425 <6>[ 1.190405] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 00:57:41.920898 <4>[ 1.213797] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 00:57:41.928053 <6>[ 1.220709] megasas: 07.719.03.00-rc1
10542 00:57:41.937519 <6>[ 1.230247] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 00:57:41.944420 <6>[ 1.237228] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 00:57:41.961449 <6>[ 1.253976] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 00:57:42.017878 <6>[ 1.304124] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10546 00:57:42.387480 <6>[ 1.680779] Freeing initrd memory: 20892K
10547 00:57:42.403558 <6>[ 1.696477] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 00:57:42.414784 <6>[ 1.707332] tun: Universal TUN/TAP device driver, 1.6
10549 00:57:42.418174 <6>[ 1.713384] thunder_xcv, ver 1.0
10550 00:57:42.421472 <6>[ 1.716885] thunder_bgx, ver 1.0
10551 00:57:42.424668 <6>[ 1.720379] nicpf, ver 1.0
10552 00:57:42.434754 <6>[ 1.724379] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 00:57:42.438411 <6>[ 1.731854] hns3: Copyright (c) 2017 Huawei Corporation.
10554 00:57:42.444654 <6>[ 1.737439] hclge is initializing
10555 00:57:42.448188 <6>[ 1.741019] e1000: Intel(R) PRO/1000 Network Driver
10556 00:57:42.454667 <6>[ 1.746148] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 00:57:42.458231 <6>[ 1.752160] e1000e: Intel(R) PRO/1000 Network Driver
10558 00:57:42.464713 <6>[ 1.757375] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 00:57:42.471415 <6>[ 1.763563] igb: Intel(R) Gigabit Ethernet Network Driver
10560 00:57:42.477659 <6>[ 1.769214] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 00:57:42.484636 <6>[ 1.775049] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 00:57:42.491131 <6>[ 1.781567] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 00:57:42.494345 <6>[ 1.788031] sky2: driver version 1.30
10564 00:57:42.501058 <6>[ 1.793004] VFIO - User Level meta-driver version: 0.3
10565 00:57:42.508244 <6>[ 1.801203] usbcore: registered new interface driver usb-storage
10566 00:57:42.514831 <6>[ 1.807653] usbcore: registered new device driver onboard-usb-hub
10567 00:57:42.523865 <6>[ 1.816782] mt6397-rtc mt6359-rtc: registered as rtc0
10568 00:57:42.533832 <6>[ 1.822249] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T00:57:03 UTC (1705625823)
10569 00:57:42.537445 <6>[ 1.831804] i2c_dev: i2c /dev entries driver
10570 00:57:42.553867 <6>[ 1.843466] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10571 00:57:42.573494 <6>[ 1.866445] cpu cpu0: EM: created perf domain
10572 00:57:42.576683 <6>[ 1.871385] cpu cpu4: EM: created perf domain
10573 00:57:42.583644 <6>[ 1.876774] sdhci: Secure Digital Host Controller Interface driver
10574 00:57:42.590181 <6>[ 1.883208] sdhci: Copyright(c) Pierre Ossman
10575 00:57:42.597053 <6>[ 1.888156] Synopsys Designware Multimedia Card Interface Driver
10576 00:57:42.603605 <6>[ 1.894792] sdhci-pltfm: SDHCI platform and OF driver helper
10577 00:57:42.606830 <6>[ 1.894943] mmc0: CQHCI version 5.10
10578 00:57:42.613668 <6>[ 1.904865] ledtrig-cpu: registered to indicate activity on CPUs
10579 00:57:42.621181 <6>[ 1.911963] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10580 00:57:42.626932 <6>[ 1.919018] usbcore: registered new interface driver usbhid
10581 00:57:42.630431 <6>[ 1.924839] usbhid: USB HID core driver
10582 00:57:42.637009 <6>[ 1.929035] spi_master spi0: will run message pump with realtime priority
10583 00:57:42.679998 <6>[ 1.966584] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10584 00:57:42.695888 <6>[ 1.982209] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10585 00:57:42.703112 <6>[ 1.995793] mmc0: Command Queue Engine enabled
10586 00:57:42.709678 <6>[ 2.000578] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10587 00:57:42.716421 <6>[ 2.007717] cros-ec-spi spi0.0: Chrome EC device registered
10588 00:57:42.719537 <6>[ 2.008082] mmcblk0: mmc0:0001 DA4128 116 GiB
10589 00:57:42.732194 <6>[ 2.025455] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10590 00:57:42.739713 <6>[ 2.033000] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 00:57:42.746248 <6>[ 2.039124] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10592 00:57:42.756143 <6>[ 2.044051] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10593 00:57:42.763003 <6>[ 2.045144] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10594 00:57:42.766354 <6>[ 2.054969] NET: Registered PF_PACKET protocol family
10595 00:57:42.773003 <6>[ 2.065595] 9pnet: Installing 9P2000 support
10596 00:57:42.776384 <5>[ 2.070182] Key type dns_resolver registered
10597 00:57:42.782894 <6>[ 2.075280] registered taskstats version 1
10598 00:57:42.786249 <5>[ 2.079672] Loading compiled-in X.509 certificates
10599 00:57:42.814913 <4>[ 2.101594] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 00:57:42.824829 <4>[ 2.112372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 00:57:42.831778 <3>[ 2.122978] debugfs: File 'uA_load' in directory '/' already present!
10602 00:57:42.838676 <3>[ 2.129686] debugfs: File 'min_uV' in directory '/' already present!
10603 00:57:42.844917 <3>[ 2.136300] debugfs: File 'max_uV' in directory '/' already present!
10604 00:57:42.851946 <3>[ 2.142911] debugfs: File 'constraint_flags' in directory '/' already present!
10605 00:57:42.864019 <3>[ 2.153353] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10606 00:57:42.872936 <6>[ 2.165976] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10607 00:57:42.880109 <6>[ 2.172982] xhci-mtk 11200000.usb: xHCI Host Controller
10608 00:57:42.886961 <6>[ 2.178481] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10609 00:57:42.896687 <6>[ 2.186320] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10610 00:57:42.903556 <6>[ 2.195752] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10611 00:57:42.910377 <6>[ 2.201845] xhci-mtk 11200000.usb: xHCI Host Controller
10612 00:57:42.916516 <6>[ 2.207320] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10613 00:57:42.923472 <6>[ 2.214971] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10614 00:57:42.930443 <6>[ 2.222668] hub 1-0:1.0: USB hub found
10615 00:57:42.933666 <6>[ 2.226676] hub 1-0:1.0: 1 port detected
10616 00:57:42.940508 <6>[ 2.230943] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10617 00:57:42.947005 <6>[ 2.239490] hub 2-0:1.0: USB hub found
10618 00:57:42.950082 <6>[ 2.243494] hub 2-0:1.0: 1 port detected
10619 00:57:42.958194 <6>[ 2.251225] mtk-msdc 11f70000.mmc: Got CD GPIO
10620 00:57:42.971358 <6>[ 2.260919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10621 00:57:42.978087 <6>[ 2.268963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10622 00:57:42.987749 <4>[ 2.276874] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10623 00:57:42.998021 <6>[ 2.286419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10624 00:57:43.004610 <6>[ 2.294499] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10625 00:57:43.010995 <6>[ 2.302515] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10626 00:57:43.020937 <6>[ 2.310427] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10627 00:57:43.027778 <6>[ 2.318246] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10628 00:57:43.037987 <6>[ 2.326066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10629 00:57:43.047887 <6>[ 2.336460] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10630 00:57:43.054250 <6>[ 2.344817] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10631 00:57:43.064023 <6>[ 2.353163] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10632 00:57:43.070810 <6>[ 2.361501] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10633 00:57:43.080847 <6>[ 2.369844] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10634 00:57:43.087182 <6>[ 2.378184] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10635 00:57:43.097173 <6>[ 2.386522] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10636 00:57:43.103996 <6>[ 2.394861] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10637 00:57:43.114359 <6>[ 2.403199] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10638 00:57:43.120627 <6>[ 2.411537] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10639 00:57:43.130509 <6>[ 2.419888] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10640 00:57:43.137454 <6>[ 2.428228] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10641 00:57:43.147081 <6>[ 2.436567] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10642 00:57:43.156792 <6>[ 2.444907] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10643 00:57:43.163494 <6>[ 2.453246] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10644 00:57:43.169996 <6>[ 2.461981] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10645 00:57:43.176600 <6>[ 2.469138] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10646 00:57:43.183265 <6>[ 2.475892] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10647 00:57:43.190154 <6>[ 2.482657] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10648 00:57:43.200027 <6>[ 2.489592] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10649 00:57:43.206558 <6>[ 2.496430] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10650 00:57:43.216512 <6>[ 2.505562] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10651 00:57:43.226531 <6>[ 2.514680] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10652 00:57:43.236086 <6>[ 2.523974] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10653 00:57:43.246531 <6>[ 2.533443] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10654 00:57:43.252453 <6>[ 2.542911] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10655 00:57:43.262511 <6>[ 2.552029] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10656 00:57:43.272508 <6>[ 2.561496] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10657 00:57:43.282137 <6>[ 2.570614] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10658 00:57:43.291912 <6>[ 2.579908] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10659 00:57:43.302173 <6>[ 2.590068] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10660 00:57:43.311801 <6>[ 2.602062] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10661 00:57:43.340277 <6>[ 2.630227] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10662 00:57:43.368648 <6>[ 2.661896] hub 2-1:1.0: USB hub found
10663 00:57:43.372120 <6>[ 2.666355] hub 2-1:1.0: 3 ports detected
10664 00:57:43.380504 <6>[ 2.673461] hub 2-1:1.0: USB hub found
10665 00:57:43.383659 <6>[ 2.677839] hub 2-1:1.0: 3 ports detected
10666 00:57:43.492555 <6>[ 2.782141] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 00:57:43.647402 <6>[ 2.940196] hub 1-1:1.0: USB hub found
10668 00:57:43.650448 <6>[ 2.944688] hub 1-1:1.0: 4 ports detected
10669 00:57:43.660570 <6>[ 2.953809] hub 1-1:1.0: USB hub found
10670 00:57:43.663841 <6>[ 2.958354] hub 1-1:1.0: 4 ports detected
10671 00:57:43.732253 <6>[ 3.022348] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10672 00:57:43.984320 <6>[ 3.274170] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10673 00:57:44.117071 <6>[ 3.410288] hub 1-1.4:1.0: USB hub found
10674 00:57:44.120629 <6>[ 3.414975] hub 1-1.4:1.0: 2 ports detected
10675 00:57:44.131009 <6>[ 3.423842] hub 1-1.4:1.0: USB hub found
10676 00:57:44.134048 <6>[ 3.428527] hub 1-1.4:1.0: 2 ports detected
10677 00:57:44.432532 <6>[ 3.722146] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10678 00:57:44.624392 <6>[ 3.914147] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10679 00:57:55.597919 <6>[ 14.895117] ALSA device list:
10680 00:57:55.603972 <6>[ 14.898404] No soundcards found.
10681 00:57:55.612610 <6>[ 14.906402] Freeing unused kernel memory: 8448K
10682 00:57:55.615688 <6>[ 14.911370] Run /init as init process
10683 00:57:55.650178 Starting syslogd: OK
10684 00:57:55.655759 Starting klogd: OK
10685 00:57:55.664435 Running sysctl: OK
10686 00:57:55.674713 Populating /dev using udev: <30>[ 14.968420] udevd[194]: starting version 3.2.9
10687 00:57:55.682758 <27>[ 14.977294] udevd[194]: specified user 'tss' unknown
10688 00:57:55.689586 <27>[ 14.982680] udevd[194]: specified group 'tss' unknown
10689 00:57:55.693489 <30>[ 14.989205] udevd[195]: starting eudev-3.2.9
10690 00:57:55.715293 <27>[ 15.009734] udevd[195]: specified user 'tss' unknown
10691 00:57:55.722182 <27>[ 15.015154] udevd[195]: specified group 'tss' unknown
10692 00:57:55.841311 <6>[ 15.132301] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10693 00:57:55.899231 <6>[ 15.190189] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10694 00:57:55.909666 <4>[ 15.200076] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10695 00:57:55.915830 <6>[ 15.201909] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10696 00:57:55.925916 <4>[ 15.207778] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10697 00:57:55.934900 <6>[ 15.229176] usbcore: registered new device driver r8152-cfgselector
10698 00:57:55.945333 <3>[ 15.232762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 00:57:55.954865 <3>[ 15.244339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 00:57:55.957908 <6>[ 15.244673] mc: Linux media interface: v0.10
10701 00:57:55.964681 <6>[ 15.246445] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10702 00:57:55.974671 <3>[ 15.252496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 00:57:55.981297 <3>[ 15.252556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 00:57:55.991200 <6>[ 15.266543] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10705 00:57:56.001039 <3>[ 15.273136] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 00:57:56.008014 <6>[ 15.286116] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10707 00:57:56.017935 <3>[ 15.291048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 00:57:56.020965 <6>[ 15.305749] videodev: Linux video capture interface: v2.00
10709 00:57:56.031042 <3>[ 15.308287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 00:57:56.037574 <6>[ 15.322400] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10711 00:57:56.047494 <3>[ 15.330101] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 00:57:56.054450 <6>[ 15.335334] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10713 00:57:56.060994 <6>[ 15.335340] pci_bus 0000:00: root bus resource [bus 00-ff]
10714 00:57:56.067473 <6>[ 15.335344] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10715 00:57:56.077336 <6>[ 15.335346] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10716 00:57:56.083788 <6>[ 15.335370] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10717 00:57:56.090315 <6>[ 15.335383] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10718 00:57:56.093679 <6>[ 15.335446] pci 0000:00:00.0: supports D1 D2
10719 00:57:56.103794 <6>[ 15.335448] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10720 00:57:56.110305 <6>[ 15.336311] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10721 00:57:56.117234 <6>[ 15.336410] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10722 00:57:56.123933 <6>[ 15.336435] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10723 00:57:56.133523 <6>[ 15.336450] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10724 00:57:56.140464 <6>[ 15.336464] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10725 00:57:56.143144 <6>[ 15.336567] pci 0000:01:00.0: supports D1 D2
10726 00:57:56.150305 <6>[ 15.336568] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 00:57:56.160141 <6>[ 15.342989] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10728 00:57:56.169778 <3>[ 15.346545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 00:57:56.176813 <6>[ 15.349898] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10730 00:57:56.184085 <6>[ 15.349937] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10731 00:57:56.190598 <6>[ 15.349942] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10732 00:57:56.200920 <6>[ 15.349950] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10733 00:57:56.207240 <6>[ 15.349963] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10734 00:57:56.214083 <6>[ 15.349976] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10735 00:57:56.220846 <6>[ 15.349988] pci 0000:00:00.0: PCI bridge to [bus 01]
10736 00:57:56.227794 <6>[ 15.349992] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10737 00:57:56.234525 <6>[ 15.350159] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10738 00:57:56.240266 <6>[ 15.350769] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10739 00:57:56.247500 <6>[ 15.351016] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10740 00:57:56.257027 <4>[ 15.373804] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10741 00:57:56.264222 <3>[ 15.376853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 00:57:56.270123 <6>[ 15.378197] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10743 00:57:56.277013 <6>[ 15.382009] remoteproc remoteproc0: scp is available
10744 00:57:56.280361 <6>[ 15.382092] remoteproc remoteproc0: powering up scp
10745 00:57:56.290238 <6>[ 15.382098] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10746 00:57:56.296888 <6>[ 15.382120] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10747 00:57:56.303189 <4>[ 15.382487] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10748 00:57:56.313068 <3>[ 15.390019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 00:57:56.316284 <6>[ 15.401819] Bluetooth: Core ver 2.22
10750 00:57:56.323452 <5>[ 15.403463] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10751 00:57:56.333462 <3>[ 15.409641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 00:57:56.340122 <3>[ 15.409951] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 00:57:56.346673 <6>[ 15.416958] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10754 00:57:56.353241 <6>[ 15.417088] NET: Registered PF_BLUETOOTH protocol family
10755 00:57:56.359423 <6>[ 15.417098] Bluetooth: HCI device and connection manager initialized
10756 00:57:56.362710 <6>[ 15.417141] Bluetooth: HCI socket layer initialized
10757 00:57:56.369510 <6>[ 15.417157] Bluetooth: L2CAP socket layer initialized
10758 00:57:56.376574 <6>[ 15.417187] Bluetooth: SCO socket layer initialized
10759 00:57:56.382835 <5>[ 15.421237] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10760 00:57:56.389456 <5>[ 15.421467] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10761 00:57:56.399894 <4>[ 15.421518] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 00:57:56.402790 <6>[ 15.421522] cfg80211: failed to load regulatory.db
10763 00:57:56.412557 <3>[ 15.423638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 00:57:56.419602 <3>[ 15.423643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 00:57:56.429079 <3>[ 15.423652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 00:57:56.435960 <3>[ 15.423655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 00:57:56.442255 <3>[ 15.423711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 00:57:56.448914 <6>[ 15.440173] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10769 00:57:56.462154 <6>[ 15.444427] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10770 00:57:56.468941 <6>[ 15.458032] r8152 2-1.3:1.0 eth0: v1.12.13
10771 00:57:56.472023 <6>[ 15.459517] usbcore: registered new interface driver uvcvideo
10772 00:57:56.482140 <4>[ 15.460266] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10773 00:57:56.485847 <4>[ 15.460266] Fallback method does not support PEC.
10774 00:57:56.492064 <6>[ 15.467502] usbcore: registered new interface driver r8152
10775 00:57:56.498654 <6>[ 15.475596] usbcore: registered new interface driver btusb
10776 00:57:56.508388 <4>[ 15.477660] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10777 00:57:56.515076 <3>[ 15.477684] Bluetooth: hci0: Failed to load firmware file (-2)
10778 00:57:56.521616 <3>[ 15.477688] Bluetooth: hci0: Failed to set up firmware (-2)
10779 00:57:56.531463 <4>[ 15.477711] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10780 00:57:56.538569 <3>[ 15.479996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10781 00:57:56.548467 <3>[ 15.502516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10782 00:57:56.554861 <6>[ 15.504955] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10783 00:57:56.561855 <6>[ 15.505056] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10784 00:57:56.568272 <6>[ 15.507836] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10785 00:57:56.578321 <6>[ 15.507872] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10786 00:57:56.584766 <6>[ 15.507880] remoteproc remoteproc0: remote processor scp is now up
10787 00:57:56.591367 <6>[ 15.514731] usbcore: registered new interface driver cdc_ether
10788 00:57:56.594698 <6>[ 15.521987] mt7921e 0000:01:00.0: ASIC revision: 79610010
10789 00:57:56.601244 <6>[ 15.534250] usbcore: registered new interface driver r8153_ecm
10790 00:57:56.611236 <6>[ 15.541237] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10791 00:57:56.617497 <6>[ 15.633298] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10792 00:57:56.621033 <6>[ 15.633298]
10793 00:57:56.627554 <6>[ 15.641771] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10794 00:57:56.637880 <6>[ 15.904354] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10795 00:57:56.638544 done
10796 00:57:56.649003 Saving random seed: OK
10797 00:57:56.667112 Starting network: OK
10798 00:57:56.712626 Starting dropbear sshd: <6>[ 16.006968] NET: Registered PF_INET6 protocol family
10799 00:57:56.719337 <6>[ 16.013653] Segment Routing with IPv6
10800 00:57:56.722590 <6>[ 16.017590] In-situ OAM (IOAM) with IPv6
10801 00:57:56.726493 OK
10802 00:57:56.736641 /bin/sh: can't access tty; job control turned off
10803 00:57:56.737915 Matched prompt #10: / #
10805 00:57:56.739060 Setting prompt string to ['/ #']
10806 00:57:56.739531 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10808 00:57:56.740599 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10809 00:57:56.741068 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10810 00:57:56.741453 Setting prompt string to ['/ #']
10811 00:57:56.741796 Forcing a shell prompt, looking for ['/ #']
10813 00:57:56.792811 / #
10814 00:57:56.793465 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10815 00:57:56.794078 Waiting using forced prompt support (timeout 00:02:30)
10816 00:57:56.799189
10817 00:57:56.800135 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10818 00:57:56.800645 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10819 00:57:56.801152 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10820 00:57:56.801626 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10821 00:57:56.802163 end: 2 depthcharge-action (duration 00:01:15) [common]
10822 00:57:56.802660 start: 3 lava-test-retry (timeout 00:01:00) [common]
10823 00:57:56.803129 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10824 00:57:56.803545 Using namespace: common
10826 00:57:56.904903 / # #
10827 00:57:56.905549 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10828 00:57:56.911552 #
10829 00:57:56.912441 Using /lava-12571130
10831 00:57:57.013759 / # export SHELL=/bin/sh
10832 00:57:57.020362 export SHELL=/bin/sh
10834 00:57:57.122201 / # . /lava-12571130/environment
10835 00:57:57.128454 . /lava-12571130/environment
10837 00:57:57.230244 / # /lava-12571130/bin/lava-test-runner /lava-12571130/0
10838 00:57:57.230883 Test shell timeout: 10s (minimum of the action and connection timeout)
10839 00:57:57.236807 /lava-12571130/bin/lava-test-runner /lava-12571130/0
10840 00:57:57.254176 + export 'TESTRUN_ID=0_dmesg'
10841 00:57:57.261021 +<8>[ 16.554305] <LAVA_SIGNAL_STARTRUN 0_dmesg 12571130_1.5.2.3.1>
10842 00:57:57.261870 Received signal: <STARTRUN> 0_dmesg 12571130_1.5.2.3.1
10843 00:57:57.262343 Starting test lava.0_dmesg (12571130_1.5.2.3.1)
10844 00:57:57.262791 Skipping test definition patterns.
10845 00:57:57.264416 cd /lava-12571130/0/tests/0_dmesg
10846 00:57:57.265044 + cat uuid
10847 00:57:57.267116 + UUID=12571130_1.5.2.3.1
10848 00:57:57.267592 + set +x
10849 00:57:57.274068 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10850 00:57:57.284483 <8>[ 16.575846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10851 00:57:57.285373 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10853 00:57:57.303238 <8>[ 16.594616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10854 00:57:57.304138 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10856 00:57:57.322330 <8>[ 16.613278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10857 00:57:57.323181 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10859 00:57:57.325506 + set +x
10860 00:57:57.328760 <8>[ 16.622761] <LAVA_SIGNAL_ENDRUN 0_dmesg 12571130_1.5.2.3.1>
10861 00:57:57.329619 Received signal: <ENDRUN> 0_dmesg 12571130_1.5.2.3.1
10862 00:57:57.330116 Ending use of test pattern.
10863 00:57:57.330478 Ending test lava.0_dmesg (12571130_1.5.2.3.1), duration 0.07
10865 00:57:57.332632 <LAVA_TEST_RUNNER EXIT>
10866 00:57:57.333345 ok: lava_test_shell seems to have completed
10867 00:57:57.333915 alert: pass
crit: pass
emerg: pass
10868 00:57:57.334448 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10869 00:57:57.334928 end: 3 lava-test-retry (duration 00:00:01) [common]
10870 00:57:57.335383 start: 4 lava-test-retry (timeout 00:01:00) [common]
10871 00:57:57.335840 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10872 00:57:57.336204 Using namespace: common
10874 00:57:57.437451 / # #
10875 00:57:57.438150 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10876 00:57:57.438771 Using /lava-12571130
10878 00:57:57.539944 export SHELL=/bin/sh
10879 00:57:57.540734 #
10880 00:57:57.541187 / # <6>[ 16.776912] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10882 00:57:57.642747 export SHELL=/bin/sh. /lava-12571130/environment
10883 00:57:57.643680
10885 00:57:57.745766 / # . /lava-12571130/environment/lava-12571130/bin/lava-test-runner /lava-12571130/1
10886 00:57:57.746456 Test shell timeout: 10s (minimum of the action and connection timeout)
10887 00:57:57.747191
10888 00:57:57.752449 / # /lava-12571130/bin/lava-test-runner /lava-12571130/1
10889 00:57:57.770397 + export 'TESTRUN_ID=1_bootrr'
10890 00:57:57.777272 <8>[ 17.070633] <LAVA_SIGNAL_STARTRUN 1_bootrr 12571130_1.5.2.3.5>
10891 00:57:57.778115 Received signal: <STARTRUN> 1_bootrr 12571130_1.5.2.3.5
10892 00:57:57.778519 Starting test lava.1_bootrr (12571130_1.5.2.3.5)
10893 00:57:57.778991 Skipping test definition patterns.
10894 00:57:57.780379 + cd /lava-12571130/1/tests/1_bootrr
10895 00:57:57.780849 + cat uuid
10896 00:57:57.783850 + UUID=12571130_1.5.2.3.5
10897 00:57:57.784426 + set +x
10898 00:57:57.794104 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12571130/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10899 00:57:57.803659 + cd /opt/bootrr/libexec/bootrr<8>[ 17.095624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10900 00:57:57.804287
10901 00:57:57.804938 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10903 00:57:57.806643 + sh helpers/bootrr-auto
10904 00:57:57.810340 /lava-12571130/1/../bin/lava-test-case
10905 00:57:57.819634 /lava-12571130/1/../bin/lava-test-case
10906 00:57:57.826746 <8>[ 17.119333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10907 00:57:57.827781 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10909 00:57:57.833233 /usr/bin/tpm2_getcap
10910 00:57:57.941712 /lava-12571130/1/../bin/lava-test-case
10911 00:57:57.948173 <8>[ 17.240143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10912 00:57:57.948988 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10914 00:57:57.966400 /lava-12571130/1/../bin/lava-test-case
10915 00:57:57.972809 <8>[ 17.264892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10916 00:57:57.973656 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10918 00:57:57.985474 /lava-12571130/1/../bin/lava-test-case
10919 00:57:57.992170 <8>[ 17.284128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10920 00:57:57.993012 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10922 00:57:58.005027 /lava-12571130/1/../bin/lava-test-case
10923 00:57:58.011361 <8>[ 17.302618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10924 00:57:58.012213 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10926 00:57:58.023041 /lava-12571130/1/../bin/lava-test-case
10927 00:57:58.030052 <8>[ 17.320490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10928 00:57:58.030920 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10930 00:57:58.044353 /lava-12571130/1/../bin/lava-test-case
10931 00:57:58.050917 <8>[ 17.343275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10932 00:57:58.051778 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10934 00:57:58.060942 /lava-12571130/1/../bin/lava-test-case
10935 00:57:58.072185 <8>[ 17.363389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10936 00:57:58.073040 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10938 00:57:58.083829 /lava-12571130/1/../bin/lava-test-case
10939 00:57:58.093648 <8>[ 17.383994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10940 00:57:58.094523 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10942 00:57:58.102083 /lava-12571130/1/../bin/lava-test-case
10943 00:57:58.108862 <8>[ 17.400175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10944 00:57:58.109719 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10946 00:57:58.121416 /lava-12571130/1/../bin/lava-test-case
10947 00:57:58.127937 <8>[ 17.419846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10948 00:57:58.128779 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10950 00:57:58.140477 /lava-12571130/1/../bin/lava-test-case
10951 00:57:58.147175 <8>[ 17.439393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10952 00:57:58.148028 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10954 00:57:58.160096 /lava-12571130/1/../bin/lava-test-case
10955 00:57:58.166520 <8>[ 17.458154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10956 00:57:58.167368 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10958 00:57:58.178889 /lava-12571130/1/../bin/lava-test-case
10959 00:57:58.185488 <8>[ 17.476517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10960 00:57:58.186369 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10962 00:57:58.195024 /lava-12571130/1/../bin/lava-test-case
10963 00:57:58.204809 <8>[ 17.495140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10964 00:57:58.205664 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10966 00:57:58.215291 /lava-12571130/1/../bin/lava-test-case
10967 00:57:58.221782 <8>[ 17.513555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10968 00:57:58.222658 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10970 00:57:58.231250 /lava-12571130/1/../bin/lava-test-case
10971 00:57:58.237410 <8>[ 17.528595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10972 00:57:58.238282 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10974 00:57:58.248795 /lava-12571130/1/../bin/lava-test-case
10975 00:57:58.255043 <8>[ 17.546779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10976 00:57:58.255910 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10978 00:57:58.263756 /lava-12571130/1/../bin/lava-test-case
10979 00:57:58.270645 <8>[ 17.561791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10980 00:57:58.271507 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10982 00:57:58.280984 /lava-12571130/1/../bin/lava-test-case
10983 00:57:58.291015 <8>[ 17.582434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10984 00:57:58.291866 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10986 00:57:58.299573 /lava-12571130/1/../bin/lava-test-case
10987 00:57:58.306327 <8>[ 17.598029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10988 00:57:58.307166 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10990 00:57:58.317778 /lava-12571130/1/../bin/lava-test-case
10991 00:57:58.324279 <8>[ 17.616428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10992 00:57:58.325122 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10994 00:57:58.333631 /lava-12571130/1/../bin/lava-test-case
10995 00:57:58.340543 <8>[ 17.631502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10996 00:57:58.341401 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10998 00:57:58.350764 /lava-12571130/1/../bin/lava-test-case
10999 00:57:58.357552 <8>[ 17.649670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11000 00:57:58.358424 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11002 00:57:58.370115 /lava-12571130/1/../bin/lava-test-case
11003 00:57:58.376634 <8>[ 17.668286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11004 00:57:58.377479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11006 00:57:58.385493 /lava-12571130/1/../bin/lava-test-case
11007 00:57:58.391908 <8>[ 17.683989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11008 00:57:58.392745 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11010 00:57:58.403562 /lava-12571130/1/../bin/lava-test-case
11011 00:57:58.410199 <8>[ 17.700963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11012 00:57:58.411056 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11014 00:57:58.420966 /lava-12571130/1/../bin/lava-test-case
11015 00:57:58.430770 <8>[ 17.721363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11016 00:57:58.431512 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11018 00:57:58.441767 /lava-12571130/1/../bin/lava-test-case
11019 00:57:58.448005 <8>[ 17.739740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11020 00:57:58.448830 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11022 00:57:58.459626 /lava-12571130/1/../bin/lava-test-case
11023 00:57:58.466171 <8>[ 17.757699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11024 00:57:58.467022 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11026 00:57:58.477476 /lava-12571130/1/../bin/lava-test-case
11027 00:57:58.484162 <8>[ 17.775530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11028 00:57:58.484907 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11030 00:57:58.496103 /lava-12571130/1/../bin/lava-test-case
11031 00:57:58.502070 <8>[ 17.793659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11032 00:57:58.502803 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11034 00:57:58.510800 /lava-12571130/1/../bin/lava-test-case
11035 00:57:58.518049 <8>[ 17.809431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11036 00:57:58.518910 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11038 00:57:58.528448 /lava-12571130/1/../bin/lava-test-case
11039 00:57:58.534929 <8>[ 17.827235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11040 00:57:58.535882 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11042 00:57:58.546855 /lava-12571130/1/../bin/lava-test-case
11043 00:57:58.553561 <8>[ 17.845049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11044 00:57:58.554325 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11046 00:57:58.561618 /lava-12571130/1/../bin/lava-test-case
11047 00:57:58.568928 <8>[ 17.860937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11048 00:57:58.569734 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11050 00:57:58.582109 /lava-12571130/1/../bin/lava-test-case
11051 00:57:58.588220 <8>[ 17.879536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11052 00:57:58.589027 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11054 00:57:58.604221 /lava-12571130/1/../bin/lava-tes<8>[ 17.894577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11055 00:57:58.604815 t-case
11056 00:57:58.605470 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11058 00:57:58.622718 /lava-12571130/1/../bin/lava-tes<8>[ 17.913154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11059 00:57:58.623282 t-case
11060 00:57:58.623913 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11062 00:57:58.631337 /lava-12571130/1/../bin/lava-test-case
11063 00:57:58.638237 <8>[ 17.929992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11064 00:57:58.639088 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11066 00:57:58.651719 /lava-12571130/1/../bin/lava-test-case
11067 00:57:58.658472 <8>[ 17.951831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11068 00:57:58.659328 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11070 00:57:58.671498 /lava-12571130/1/../bin/lava-test-case
11071 00:57:58.681489 <8>[ 17.970700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11072 00:57:58.682421 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11074 00:57:58.693072 /lava-12571130/1/../bin/lava-test-case
11075 00:57:58.699360 <8>[ 17.992249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11076 00:57:58.700223 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11078 00:57:58.709358 /lava-12571130/1/../bin/lava-test-case
11079 00:57:58.720869 <8>[ 18.012010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11080 00:57:58.721739 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11082 00:57:58.732865 /lava-12571130/1/../bin/lava-test-case
11083 00:57:58.739726 <8>[ 18.031077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11084 00:57:58.740586 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11086 00:57:58.748050 /lava-12571130/1/../bin/lava-test-case
11087 00:57:58.757750 <8>[ 18.048772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11088 00:57:58.758674 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11090 00:57:58.768810 /lava-12571130/1/../bin/lava-test-case
11091 00:57:58.775706 <8>[ 18.066222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11092 00:57:58.776450 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11094 00:57:58.782803 /lava-12571130/1/../bin/lava-test-case
11095 00:57:58.792744 <8>[ 18.084279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11096 00:57:58.793570 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11098 00:57:58.804379 /lava-12571130/1/../bin/lava-test-case
11099 00:57:58.810845 <8>[ 18.103011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11100 00:57:58.811735 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11102 00:57:58.823851 /lava-12571130/1/../bin/lava-test-case
11103 00:57:58.834135 <8>[ 18.125362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11104 00:57:58.835002 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11106 00:57:58.843317 /lava-12571130/1/../bin/lava-test-case
11107 00:57:58.849795 <8>[ 18.141435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11108 00:57:58.850733 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11110 00:57:58.863128 /lava-12571130/1/../bin/lava-test-case
11111 00:57:58.869735 <8>[ 18.160972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11112 00:57:58.870600 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11114 00:57:58.877567 /lava-12571130/1/../bin/lava-test-case
11115 00:57:58.884355 <8>[ 18.177101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11116 00:57:58.885282 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11118 00:57:58.898749 /lava-12571130/1/../bin/lava-test-case
11119 00:57:58.904886 <8>[ 18.196619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11120 00:57:58.905615 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11122 00:57:58.914935 /lava-12571130/1/../bin/lava-test-case
11123 00:57:58.925879 <8>[ 18.217050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11124 00:57:58.926777 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11126 00:57:58.936459 /lava-12571130/1/../bin/lava-test-case
11127 00:57:58.943130 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11129 00:57:58.946183 <8>[ 18.236598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11130 00:57:58.955899 /lava-12571130/1/../bin/lava-test-case
11131 00:57:58.962095 <8>[ 18.254000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11132 00:57:58.962918 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11134 00:57:58.972449 /lava-12571130/1/../bin/lava-test-case
11135 00:57:58.978777 <8>[ 18.271111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11136 00:57:58.979520 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11138 00:57:58.988498 /lava-12571130/1/../bin/lava-test-case
11139 00:57:58.994847 <8>[ 18.286534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11140 00:57:58.995647 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11142 00:57:59.005315 /lava-12571130/1/../bin/lava-test-case
11143 00:57:59.011427 <8>[ 18.303720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11144 00:57:59.012181 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11146 00:57:59.022359 /lava-12571130/1/../bin/lava-test-case
11147 00:57:59.029274 <8>[ 18.321081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11148 00:57:59.030081 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11150 00:57:59.037480 /lava-12571130/1/../bin/lava-test-case
11151 00:57:59.044153 <8>[ 18.335397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11152 00:57:59.045009 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11154 00:57:59.057410 /lava-12571130/1/../bin/lava-test-case
11155 00:57:59.063700 <8>[ 18.354838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11156 00:57:59.064570 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11158 00:57:59.075014 /lava-12571130/1/../bin/lava-test-case
11159 00:57:59.081692 <8>[ 18.372491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11160 00:57:59.082472 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11162 00:57:59.093156 /lava-12571130/1/../bin/lava-test-case
11163 00:57:59.099658 <8>[ 18.391195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11164 00:57:59.100439 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11166 00:57:59.108730 /lava-12571130/1/../bin/lava-test-case
11167 00:57:59.115275 <8>[ 18.406426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11168 00:57:59.116021 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11170 00:57:59.126982 /lava-12571130/1/../bin/lava-test-case
11171 00:57:59.133685 <8>[ 18.425276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11172 00:57:59.134598 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11174 00:57:59.144292 /lava-12571130/1/../bin/lava-test-case
11175 00:57:59.155100 <8>[ 18.446590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11176 00:57:59.156106 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11178 00:57:59.165357 /lava-12571130/1/../bin/lava-test-case
11179 00:57:59.172221 <8>[ 18.464047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11180 00:57:59.173167 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11182 00:57:59.183326 /lava-12571130/1/../bin/lava-test-case
11183 00:57:59.189901 <8>[ 18.481335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11184 00:57:59.190803 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11186 00:57:59.202488 /lava-12571130/1/../bin/lava-test-case
11187 00:57:59.212233 <8>[ 18.503156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11188 00:57:59.213112 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11190 00:57:59.222103 /lava-12571130/1/../bin/lava-test-case
11191 00:57:59.229047 <8>[ 18.520404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11192 00:57:59.230117 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11194 00:57:59.239738 /lava-12571130/1/../bin/lava-test-case
11195 00:57:59.246301 <8>[ 18.537132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11196 00:57:59.247155 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11198 00:57:59.257924 /lava-12571130/1/../bin/lava-test-case
11199 00:57:59.264407 <8>[ 18.555271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11200 00:57:59.265280 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11202 00:57:59.276303 /lava-12571130/1/../bin/lava-test-case
11203 00:57:59.282985 <8>[ 18.574485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11204 00:57:59.283820 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11206 00:57:59.292984 /lava-12571130/1/../bin/lava-test-case
11207 00:57:59.299142 <8>[ 18.592603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11208 00:57:59.299875 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11210 00:57:59.312503 /lava-12571130/1/../bin/lava-test-case
11211 00:57:59.319157 <8>[ 18.611028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11212 00:57:59.320056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11214 00:57:59.330290 /lava-12571130/1/../bin/lava-test-case
11215 00:57:59.336948 <8>[ 18.627921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11216 00:57:59.337809 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11218 00:57:59.355555 /lava-12571130/1/../bin/lava-tes<8>[ 18.646604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11219 00:57:59.356095 t-case
11220 00:57:59.356723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11222 00:57:59.375137 /lava-12571130/1/../bin/lava-tes<8>[ 18.665605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11223 00:57:59.375768 t-case
11224 00:57:59.376422 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11226 00:57:59.385255 /lava-12571130/1/../bin/lava-test-case
11227 00:57:59.391540 <8>[ 18.683662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11228 00:57:59.392368 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11230 00:57:59.401714 /lava-12571130/1/../bin/lava-test-case
11231 00:57:59.408042 <8>[ 18.699594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11232 00:57:59.408788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11234 00:57:59.419991 /lava-12571130/1/../bin/lava-test-case
11235 00:57:59.426784 <8>[ 18.718869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11236 00:57:59.427515 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11238 00:57:59.436234 /lava-12571130/1/../bin/lava-test-case
11239 00:57:59.443169 <8>[ 18.734558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11240 00:57:59.444015 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11242 00:57:59.456890 /lava-12571130/1/../bin/lava-test-case
11243 00:57:59.463047 <8>[ 18.755123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11244 00:57:59.463891 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11246 00:57:59.471836 /lava-12571130/1/../bin/lava-test-case
11247 00:57:59.478321 <8>[ 18.769948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11248 00:57:59.479353 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11250 00:57:59.491937 /lava-12571130/1/../bin/lava-test-case
11251 00:57:59.502102 <8>[ 18.792766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11252 00:57:59.502936 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11254 00:57:59.510726 /lava-12571130/1/../bin/lava-test-case
11255 00:57:59.517239 <8>[ 18.808089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11256 00:57:59.518082 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11258 00:57:59.531464 /lava-12571130/1/../bin/lava-test-case
11259 00:57:59.541992 <8>[ 18.832755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11260 00:57:59.542909 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11262 00:57:59.549627 /lava-12571130/1/../bin/lava-test-case
11263 00:57:59.556174 <8>[ 18.847679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11264 00:57:59.556920 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11266 00:57:59.566509 /lava-12571130/1/../bin/lava-test-case
11267 00:57:59.572988 <8>[ 18.865011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11268 00:57:59.573748 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11270 00:57:59.581486 /lava-12571130/1/../bin/lava-test-case
11271 00:57:59.588166 <8>[ 18.880306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11272 00:57:59.589118 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11274 00:57:59.600853 /lava-12571130/1/../bin/lava-test-case
11275 00:57:59.607750 <8>[ 18.899788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11276 00:57:59.608546 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11278 00:57:59.621196 /lava-12571130/1/../bin/lava-test-case
11279 00:57:59.627359 <8>[ 18.919365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11280 00:57:59.628221 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11282 00:57:59.637052 /lava-12571130/1/../bin/lava-test-case
11283 00:57:59.643224 <8>[ 18.935522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11284 00:57:59.644058 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11286 00:57:59.656653 /lava-12571130/1/../bin/lava-test-case
11287 00:57:59.663327 <8>[ 18.954553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11288 00:57:59.664176 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11290 00:57:59.672386 /lava-12571130/1/../bin/lava-test-case
11291 00:57:59.682165 <8>[ 18.972768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11292 00:57:59.682912 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11294 00:57:59.692653 /lava-12571130/1/../bin/lava-test-case
11295 00:57:59.698976 <8>[ 18.990678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11296 00:57:59.699816 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11298 00:57:59.706652 /lava-12571130/1/../bin/lava-test-case
11299 00:57:59.716595 <8>[ 19.007432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11300 00:57:59.717398 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11302 00:58:00.730025 /lava-12571130/1/../bin/lava-test-case
11303 00:58:00.736579 <8>[ 20.030487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11304 00:58:00.737402 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11306 00:58:00.746371 /lava-12571130/1/../bin/lava-test-case
11307 00:58:00.753009 <8>[ 20.045742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11308 00:58:00.753556 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11310 00:58:01.767117 /lava-12571130/1/../bin/lava-test-case
11311 00:58:01.773587 <8>[ 21.065473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11312 00:58:01.774449 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11314 00:58:01.781373 /lava-12571130/1/../bin/lava-test-case
11315 00:58:01.792733 <8>[ 21.084345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11316 00:58:01.793573 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11318 00:58:02.806973 /lava-12571130/1/../bin/lava-test-case
11319 00:58:02.813393 <8>[ 22.105231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11320 00:58:02.814305 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11322 00:58:02.822325 /lava-12571130/1/../bin/lava-test-case
11323 00:58:02.828535 <8>[ 22.121995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11324 00:58:02.829419 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11326 00:58:03.842197 /lava-12571130/1/../bin/lava-test-case
11327 00:58:03.849041 <8>[ 23.140964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11328 00:58:03.849861 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11330 00:58:03.856946 /lava-12571130/1/../bin/lava-test-case
11331 00:58:03.866578 <8>[ 23.158441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11332 00:58:03.867356 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11334 00:58:04.881183 /lava-12571130/1/../bin/lava-test-case
11335 00:58:04.887883 <8>[ 24.179974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11336 00:58:04.888746 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11338 00:58:04.897043 /lava-12571130/1/../bin/lava-test-case
11339 00:58:04.903698 <8>[ 24.196823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11340 00:58:04.904548 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11342 00:58:05.918040 /lava-12571130/1/../bin/lava-test-case
11343 00:58:05.924875 <8>[ 25.216610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11344 00:58:05.925713 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11346 00:58:05.933795 /lava-12571130/1/../bin/lava-test-case
11347 00:58:05.940432 <8>[ 25.233164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11348 00:58:05.941279 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11350 00:58:06.954324 /lava-12571130/1/../bin/lava-test-case
11351 00:58:06.960842 <8>[ 26.253217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11352 00:58:06.961684 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11354 00:58:06.971453 /lava-12571130/1/../bin/lava-test-case
11355 00:58:06.978322 <8>[ 26.271369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11356 00:58:06.979170 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11358 00:58:06.987820 /lava-12571130/1/../bin/lava-test-case
11359 00:58:06.994427 <8>[ 26.287443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11360 00:58:06.995284 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11362 00:58:08.009124 /lava-12571130/1/../bin/lava-test-case
11363 00:58:08.018577 <8>[ 27.310371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11364 00:58:08.019410 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11366 00:58:08.027471 /lava-12571130/1/../bin/lava-test-case
11367 00:58:08.034047 <8>[ 27.326586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11368 00:58:08.034909 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11370 00:58:08.047330 /lava-12571130/1/../bin/lava-test-case
11371 00:58:08.057049 <8>[ 27.349141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11372 00:58:08.057974 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11374 00:58:08.065194 /lava-12571130/1/../bin/lava-test-case
11375 00:58:08.071572 <8>[ 27.364121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11376 00:58:08.072411 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11378 00:58:08.088472 /lava-12571130/1/../bin/lava-test-case
11379 00:58:08.094841 <8>[ 27.387676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11380 00:58:08.095673 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11382 00:58:08.105620 /lava-12571130/1/../bin/lava-test-case
11383 00:58:08.112411 <8>[ 27.405234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11384 00:58:08.113253 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11386 00:58:08.123468 /lava-12571130/1/../bin/lava-test-case
11387 00:58:08.133131 <8>[ 27.425226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11388 00:58:08.133984 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11390 00:58:08.141573 /lava-12571130/1/../bin/lava-test-case
11391 00:58:08.148332 <8>[ 27.440577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11392 00:58:08.149178 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11394 00:58:08.161850 /lava-12571130/1/../bin/lava-test-case
11395 00:58:08.168074 <8>[ 27.460797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11396 00:58:08.168890 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11398 00:58:08.181507 /lava-12571130/1/../bin/lava-test-case
11399 00:58:08.188006 <8>[ 27.479807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11400 00:58:08.188841 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11402 00:58:08.196867 /lava-12571130/1/../bin/lava-test-case
11403 00:58:08.203585 <8>[ 27.496442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11404 00:58:08.204417 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11406 00:58:08.216431 /lava-12571130/1/../bin/lava-test-case
11407 00:58:08.222935 <8>[ 27.515608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11408 00:58:08.223772 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11410 00:58:08.231752 /lava-12571130/1/../bin/lava-test-case
11411 00:58:08.242561 <8>[ 27.535231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11412 00:58:08.243398 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11414 00:58:08.253654 /lava-12571130/1/../bin/lava-test-case
11415 00:58:08.260314 <8>[ 27.552888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11416 00:58:08.261140 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11418 00:58:08.269165 /lava-12571130/1/../bin/lava-test-case
11419 00:58:08.279423 <8>[ 27.571657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11420 00:58:08.280278 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11422 00:58:08.290775 /lava-12571130/1/../bin/lava-test-case
11423 00:58:08.297203 <8>[ 27.590134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11424 00:58:08.298065 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11426 00:58:08.307875 /lava-12571130/1/../bin/lava-test-case
11427 00:58:08.314491 <8>[ 27.607208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11428 00:58:08.315334 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11430 00:58:08.327738 /lava-12571130/1/../bin/lava-test-case
11431 00:58:08.334273 <8>[ 27.626587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11432 00:58:08.335008 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11434 00:58:08.345365 /lava-12571130/1/../bin/lava-test-case
11435 00:58:08.352118 <8>[ 27.646168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11436 00:58:08.352985 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11438 00:58:08.366934 /lava-12571130/1/../bin/lava-test-case
11439 00:58:08.378277 <8>[ 27.670829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11440 00:58:08.379019 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11442 00:58:08.386624 /lava-12571130/1/../bin/lava-test-case
11443 00:58:08.393316 <8>[ 27.686619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11444 00:58:08.394165 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11446 00:58:09.408201 /lava-12571130/1/../bin/lava-test-case
11447 00:58:09.414722 <8>[ 28.707394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11448 00:58:09.415576 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11450 00:58:10.428881 /lava-12571130/1/../bin/lava-test-case
11451 00:58:10.435406 <8>[ 29.728242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11452 00:58:10.436142 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11454 00:58:10.444042 /lava-12571130/1/../bin/lava-test-case
11455 00:58:10.453544 <8>[ 29.745196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11456 00:58:10.454446 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11458 00:58:10.462830 /lava-12571130/1/../bin/lava-test-case
11459 00:58:10.469493 <8>[ 29.762304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11460 00:58:10.470397 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11462 00:58:10.478833 /lava-12571130/1/../bin/lava-test-case
11463 00:58:10.485582 <8>[ 29.778731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11464 00:58:10.486473 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11466 00:58:10.497001 /lava-12571130/1/../bin/lava-test-case
11467 00:58:10.503355 <8>[ 29.797227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11468 00:58:10.504217 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11470 00:58:10.513607 /lava-12571130/1/../bin/lava-test-case
11471 00:58:10.520141 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11473 00:58:10.523303 <8>[ 29.814807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11474 00:58:10.532369 /lava-12571130/1/../bin/lava-test-case
11475 00:58:10.538676 <8>[ 29.832067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11476 00:58:10.539410 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11478 00:58:10.546940 /lava-12571130/1/../bin/lava-test-case
11479 00:58:10.554040 <8>[ 29.846741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11480 00:58:10.554879 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11482 00:58:10.565504 /lava-12571130/1/../bin/lava-test-case
11483 00:58:10.571995 <8>[ 29.864987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11484 00:58:10.572845 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11486 00:58:10.580467 /lava-12571130/1/../bin/lava-test-case
11487 00:58:10.587071 <8>[ 29.880663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11488 00:58:10.587927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11490 00:58:10.598635 /lava-12571130/1/../bin/lava-test-case
11491 00:58:10.604906 <8>[ 29.898353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11492 00:58:10.605759 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11494 00:58:10.613667 /lava-12571130/1/../bin/lava-test-case
11495 00:58:10.625319 <8>[ 29.918034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11496 00:58:10.626149 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11498 00:58:10.636136 /lava-12571130/1/../bin/lava-test-case
11499 00:58:10.642361 <8>[ 29.936108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11500 00:58:10.643132 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11502 00:58:10.651797 /lava-12571130/1/../bin/lava-test-case
11503 00:58:10.658058 <8>[ 29.952073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11504 00:58:10.658927 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11506 00:58:10.669847 /lava-12571130/1/../bin/lava-test-case
11507 00:58:10.676174 <8>[ 29.969084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11508 00:58:10.677048 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11510 00:58:10.684256 /lava-12571130/1/../bin/lava-test-case
11511 00:58:10.695549 <8>[ 29.988047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11512 00:58:10.696428 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11514 00:58:10.705631 /lava-12571130/1/../bin/lava-test-case
11515 00:58:10.712057 <8>[ 30.005319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11516 00:58:10.712929 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11518 00:58:10.721509 /lava-12571130/1/../bin/lava-test-case
11519 00:58:10.728233 <8>[ 30.020865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11520 00:58:10.729109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11522 00:58:10.738516 /lava-12571130/1/../bin/lava-test-case
11523 00:58:10.744638 <8>[ 30.037051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11524 00:58:10.745517 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11526 00:58:10.761021 /lava-12571130/1/../bin/lava-tes<8>[ 30.053180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11527 00:58:10.761599 t-case
11528 00:58:10.762485 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11530 00:58:10.772036 /lava-12571130/1/../bin/lava-test-case
11531 00:58:10.778513 <8>[ 30.071534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11532 00:58:10.779383 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11534 00:58:11.790650 /lava-12571130/1/../bin/lava-test-case
11535 00:58:11.796712 <8>[ 31.091103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11536 00:58:11.797003 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11538 00:58:12.811563 /lava-12571130/1/../bin/lava-test-case
11539 00:58:12.817681 <8>[ 32.110807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11540 00:58:12.818596 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11541 00:58:12.819122 Bad test result: blocked
11542 00:58:12.829150 /lava-12571130/1/../bin/lava-test-case
11543 00:58:12.838735 <8>[ 32.130755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11544 00:58:12.839638 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11546 00:58:13.850376 /lava-12571130/1/../bin/lava-test-case
11547 00:58:13.856864 <8>[ 33.150300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11548 00:58:13.857739 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11550 00:58:13.866990 /lava-12571130/1/../bin/lava-test-case
11551 00:58:13.877305 <8>[ 33.169385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11552 00:58:13.878148 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11554 00:58:13.886958 /lava-12571130/1/../bin/lava-test-case
11555 00:58:13.893894 <8>[ 33.186388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11556 00:58:13.894769 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11558 00:58:13.905929 /lava-12571130/1/../bin/lava-test-case
11559 00:58:13.916000 <8>[ 33.208984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11560 00:58:13.916841 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11562 00:58:13.925275 /lava-12571130/1/../bin/lava-test-case
11563 00:58:13.931248 <8>[ 33.224797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11564 00:58:13.932090 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11566 00:58:13.945092 /lava-12571130/1/../bin/lava-test-case
11567 00:58:13.951107 <8>[ 33.244082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11568 00:58:13.951843 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11570 00:58:13.959392 /lava-12571130/1/../bin/lava-test-case
11571 00:58:13.970759 <8>[ 33.263720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11572 00:58:13.971486 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11574 00:58:14.984882 /lava-12571130/1/../bin/lava-test-case
11575 00:58:14.991573 <8>[ 34.285263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11576 00:58:14.992568 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11578 00:58:14.999450 /lava-12571130/1/../bin/lava-test-case
11579 00:58:15.011172 <8>[ 34.304487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11580 00:58:15.012025 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11582 00:58:16.023731 /lava-12571130/1/../bin/lava-test-case
11583 00:58:16.030392 <8>[ 35.324075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11584 00:58:16.031247 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11586 00:58:16.038390 /lava-12571130/1/../bin/lava-test-case
11587 00:58:16.049874 <8>[ 35.342976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11588 00:58:16.050773 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11590 00:58:17.061826 /lava-12571130/1/../bin/lava-test-case
11591 00:58:17.068218 <8>[ 36.362313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11592 00:58:17.068941 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11594 00:58:17.078632 /lava-12571130/1/../bin/lava-test-case
11595 00:58:17.088939 <8>[ 36.381490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11596 00:58:17.089776 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11598 00:58:18.102248 /lava-12571130/1/../bin/lava-test-case
11599 00:58:18.108718 <8>[ 37.402309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11600 00:58:18.109569 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11602 00:58:18.119752 /lava-12571130/1/../bin/lava-test-case
11603 00:58:18.126042 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11605 00:58:18.129400 <8>[ 37.422073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11606 00:58:18.139621 /lava-12571130/1/../bin/lava-test-case
11607 00:58:18.145679 <8>[ 37.439466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11608 00:58:18.146591 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11610 00:58:18.156936 /lava-12571130/1/../bin/lava-test-case
11611 00:58:18.162663 <8>[ 37.456372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11612 00:58:18.163507 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11614 00:58:18.178104 /lava-12571130/1/../bin/lava-tes<8>[ 37.470943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11615 00:58:18.178709 t-case
11616 00:58:18.179493 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11618 00:58:18.189163 /lava-12571130/1/../bin/lava-test-case
11619 00:58:18.195692 <8>[ 37.489292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11620 00:58:18.196537 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11622 00:58:18.204576 /lava-12571130/1/../bin/lava-test-case
11623 00:58:18.211269 <8>[ 37.504736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11624 00:58:18.212136 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11626 00:58:18.228587 /lava-12571130/1/../bin/lava-tes<8>[ 37.521451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11627 00:58:18.229174 t-case
11628 00:58:18.229816 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11630 00:58:18.239267 /lava-12571130/1/../bin/lava-test-case
11631 00:58:18.245430 <8>[ 37.539534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11632 00:58:18.246302 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11634 00:58:18.259007 /lava-12571130/1/../bin/lava-test-case
11635 00:58:18.268949 <8>[ 37.562673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11636 00:58:18.269794 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11638 00:58:18.272467 + set +x
11639 00:58:18.278726 <8>[ 37.572656] <LAVA_SIGNAL_ENDRUN 1_bootrr 12571130_1.5.2.3.5>
11640 00:58:18.279676 Received signal: <ENDRUN> 1_bootrr 12571130_1.5.2.3.5
11641 00:58:18.280119 Ending use of test pattern.
11642 00:58:18.280483 Ending test lava.1_bootrr (12571130_1.5.2.3.5), duration 20.50
11644 00:58:18.282179 ok: lava_test_shell seems to have completed
11645 00:58:18.287839 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11646 00:58:18.288781 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11647 00:58:18.289334 end: 4 lava-test-retry (duration 00:00:21) [common]
11648 00:58:18.289828 start: 5 finalize (timeout 00:08:05) [common]
11649 00:58:18.290409 start: 5.1 power-off (timeout 00:00:30) [common]
11650 00:58:18.291588 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11651 00:58:18.413652 >> Command sent successfully.
11652 00:58:18.424526 Returned 0 in 0 seconds
11653 00:58:18.526011 end: 5.1 power-off (duration 00:00:00) [common]
11655 00:58:18.527538 start: 5.2 read-feedback (timeout 00:08:05) [common]
11657 00:58:18.529872 Listened to connection for namespace 'common' for up to 1s
11658 00:58:19.529703 Finalising connection for namespace 'common'
11659 00:58:19.530554 Disconnecting from shell: Finalise
11660 00:58:19.530998 / #
11661 00:58:19.632086 end: 5.2 read-feedback (duration 00:00:01) [common]
11662 00:58:19.632798 end: 5 finalize (duration 00:00:01) [common]
11663 00:58:19.633485 Cleaning after the job
11664 00:58:19.634204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/ramdisk
11665 00:58:19.646173 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/kernel
11666 00:58:19.672390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/dtb
11667 00:58:19.672760 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571130/tftp-deploy-ryvd6b8t/modules
11668 00:58:19.682975 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571130
11669 00:58:19.725695 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571130
11670 00:58:19.725876 Job finished correctly