Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 16
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
1 00:57:59.380733 lava-dispatcher, installed at version: 2023.10
2 00:57:59.380958 start: 0 validate
3 00:57:59.381095 Start time: 2024-01-19 00:57:59.381087+00:00 (UTC)
4 00:57:59.381221 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:57:59.381358 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:57:59.648362 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:57:59.648573 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:57:59.915678 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:57:59.916465 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:58:00.178864 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:58:00.179911 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:58:00.937538 validate duration: 1.56
14 00:58:00.937950 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:58:00.938103 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:58:00.938249 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:58:00.938434 Not decompressing ramdisk as can be used compressed.
18 00:58:00.938569 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 00:58:00.938678 saving as /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/ramdisk/rootfs.cpio.gz
20 00:58:00.938780 total size: 43284872 (41 MB)
21 00:58:00.940329 progress 0 % (0 MB)
22 00:58:00.954405 progress 5 % (2 MB)
23 00:58:00.965813 progress 10 % (4 MB)
24 00:58:00.977272 progress 15 % (6 MB)
25 00:58:00.988647 progress 20 % (8 MB)
26 00:58:00.999977 progress 25 % (10 MB)
27 00:58:01.011190 progress 30 % (12 MB)
28 00:58:01.022472 progress 35 % (14 MB)
29 00:58:01.033828 progress 40 % (16 MB)
30 00:58:01.045033 progress 45 % (18 MB)
31 00:58:01.056391 progress 50 % (20 MB)
32 00:58:01.067807 progress 55 % (22 MB)
33 00:58:01.079164 progress 60 % (24 MB)
34 00:58:01.090312 progress 65 % (26 MB)
35 00:58:01.101578 progress 70 % (28 MB)
36 00:58:01.112825 progress 75 % (30 MB)
37 00:58:01.124000 progress 80 % (33 MB)
38 00:58:01.135164 progress 85 % (35 MB)
39 00:58:01.146573 progress 90 % (37 MB)
40 00:58:01.157905 progress 95 % (39 MB)
41 00:58:01.169042 progress 100 % (41 MB)
42 00:58:01.169330 41 MB downloaded in 0.23 s (179.05 MB/s)
43 00:58:01.169507 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:58:01.169755 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:58:01.169842 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:58:01.169925 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:58:01.170067 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:58:01.170140 saving as /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/kernel/Image
50 00:58:01.170201 total size: 51532288 (49 MB)
51 00:58:01.170261 No compression specified
52 00:58:01.171641 progress 0 % (0 MB)
53 00:58:01.185611 progress 5 % (2 MB)
54 00:58:01.199322 progress 10 % (4 MB)
55 00:58:01.213002 progress 15 % (7 MB)
56 00:58:01.226358 progress 20 % (9 MB)
57 00:58:01.240040 progress 25 % (12 MB)
58 00:58:01.253513 progress 30 % (14 MB)
59 00:58:01.267617 progress 35 % (17 MB)
60 00:58:01.281622 progress 40 % (19 MB)
61 00:58:01.295070 progress 45 % (22 MB)
62 00:58:01.309547 progress 50 % (24 MB)
63 00:58:01.323575 progress 55 % (27 MB)
64 00:58:01.337342 progress 60 % (29 MB)
65 00:58:01.351328 progress 65 % (31 MB)
66 00:58:01.365816 progress 70 % (34 MB)
67 00:58:01.380679 progress 75 % (36 MB)
68 00:58:01.394358 progress 80 % (39 MB)
69 00:58:01.407847 progress 85 % (41 MB)
70 00:58:01.421874 progress 90 % (44 MB)
71 00:58:01.435803 progress 95 % (46 MB)
72 00:58:01.449167 progress 100 % (49 MB)
73 00:58:01.449421 49 MB downloaded in 0.28 s (176.01 MB/s)
74 00:58:01.449580 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:58:01.449808 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:58:01.449896 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:58:01.449984 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:58:01.450124 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:58:01.450199 saving as /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/dtb/mt8192-asurada-spherion-r0.dtb
81 00:58:01.450263 total size: 47278 (0 MB)
82 00:58:01.450325 No compression specified
83 00:58:01.451441 progress 69 % (0 MB)
84 00:58:01.451713 progress 100 % (0 MB)
85 00:58:01.451870 0 MB downloaded in 0.00 s (28.11 MB/s)
86 00:58:01.451993 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:58:01.452211 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:58:01.452324 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:58:01.452422 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:58:01.452534 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:58:01.452605 saving as /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/modules/modules.tar
93 00:58:01.452665 total size: 8625444 (8 MB)
94 00:58:01.452726 Using unxz to decompress xz
95 00:58:01.456872 progress 0 % (0 MB)
96 00:58:01.479428 progress 5 % (0 MB)
97 00:58:01.505180 progress 10 % (0 MB)
98 00:58:01.530693 progress 15 % (1 MB)
99 00:58:01.555960 progress 20 % (1 MB)
100 00:58:01.581537 progress 25 % (2 MB)
101 00:58:01.609651 progress 30 % (2 MB)
102 00:58:01.638107 progress 35 % (2 MB)
103 00:58:01.663863 progress 40 % (3 MB)
104 00:58:01.690628 progress 45 % (3 MB)
105 00:58:01.718125 progress 50 % (4 MB)
106 00:58:01.745221 progress 55 % (4 MB)
107 00:58:01.771992 progress 60 % (4 MB)
108 00:58:01.801786 progress 65 % (5 MB)
109 00:58:01.828373 progress 70 % (5 MB)
110 00:58:01.852745 progress 75 % (6 MB)
111 00:58:01.881854 progress 80 % (6 MB)
112 00:58:01.909566 progress 85 % (7 MB)
113 00:58:01.936481 progress 90 % (7 MB)
114 00:58:01.970411 progress 95 % (7 MB)
115 00:58:02.000319 progress 100 % (8 MB)
116 00:58:02.005401 8 MB downloaded in 0.55 s (14.88 MB/s)
117 00:58:02.005659 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:58:02.005930 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:58:02.006022 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:58:02.006116 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:58:02.006197 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:58:02.006280 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:58:02.006507 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu
125 00:58:02.006642 makedir: /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin
126 00:58:02.006746 makedir: /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/tests
127 00:58:02.006850 makedir: /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/results
128 00:58:02.007060 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-add-keys
129 00:58:02.007251 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-add-sources
130 00:58:02.007419 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-background-process-start
131 00:58:02.007583 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-background-process-stop
132 00:58:02.007747 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-common-functions
133 00:58:02.007906 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-echo-ipv4
134 00:58:02.008106 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-install-packages
135 00:58:02.008266 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-installed-packages
136 00:58:02.008438 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-os-build
137 00:58:02.008565 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-probe-channel
138 00:58:02.008691 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-probe-ip
139 00:58:02.008818 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-target-ip
140 00:58:02.008943 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-target-mac
141 00:58:02.009068 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-target-storage
142 00:58:02.009199 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-case
143 00:58:02.009326 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-event
144 00:58:02.009453 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-feedback
145 00:58:02.009578 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-raise
146 00:58:02.009705 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-reference
147 00:58:02.009833 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-runner
148 00:58:02.009960 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-set
149 00:58:02.010086 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-test-shell
150 00:58:02.010217 Updating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-install-packages (oe)
151 00:58:02.010372 Updating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/bin/lava-installed-packages (oe)
152 00:58:02.010495 Creating /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/environment
153 00:58:02.010594 LAVA metadata
154 00:58:02.010667 - LAVA_JOB_ID=12571066
155 00:58:02.010732 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:58:02.010835 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:58:02.010903 skipped lava-vland-overlay
158 00:58:02.010977 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:58:02.011057 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:58:02.011126 skipped lava-multinode-overlay
161 00:58:02.011198 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:58:02.011308 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:58:02.011385 Loading test definitions
164 00:58:02.011479 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:58:02.011553 Using /lava-12571066 at stage 0
166 00:58:02.011868 uuid=12571066_1.5.2.3.1 testdef=None
167 00:58:02.011955 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:58:02.012038 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:58:02.012619 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:58:02.012837 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:58:02.013462 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:58:02.013688 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:58:02.014285 runner path: /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/0/tests/0_igt-gpu-panfrost test_uuid 12571066_1.5.2.3.1
176 00:58:02.014444 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:58:02.014650 Creating lava-test-runner.conf files
179 00:58:02.014728 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571066/lava-overlay-1xfcjkwu/lava-12571066/0 for stage 0
180 00:58:02.014831 - 0_igt-gpu-panfrost
181 00:58:02.014929 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:58:02.015013 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:58:02.021787 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:58:02.021911 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:58:02.022000 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:58:02.022089 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:58:02.022180 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:58:03.482059 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:58:03.482450 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 00:58:03.482562 extracting modules file /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571066/extract-overlay-ramdisk-s0c2xbdx/ramdisk
191 00:58:03.718379 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:58:03.718569 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 00:58:03.718676 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571066/compress-overlay-twuusqoc/overlay-1.5.2.4.tar.gz to ramdisk
194 00:58:03.718746 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571066/compress-overlay-twuusqoc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571066/extract-overlay-ramdisk-s0c2xbdx/ramdisk
195 00:58:03.725607 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:58:03.725727 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 00:58:03.725820 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:58:03.725909 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 00:58:03.725991 Building ramdisk /var/lib/lava/dispatcher/tmp/12571066/extract-overlay-ramdisk-s0c2xbdx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571066/extract-overlay-ramdisk-s0c2xbdx/ramdisk
200 00:58:07.544643 >> 369992 blocks
201 00:58:13.382519 rename /var/lib/lava/dispatcher/tmp/12571066/extract-overlay-ramdisk-s0c2xbdx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/ramdisk/ramdisk.cpio.gz
202 00:58:13.382962 end: 1.5.7 compress-ramdisk (duration 00:00:10) [common]
203 00:58:13.383093 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 00:58:13.383190 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 00:58:13.383298 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/kernel/Image'
206 00:58:26.760631 Returned 0 in 13 seconds
207 00:58:26.861264 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/kernel/image.itb
208 00:58:27.728027 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:58:27.728436 output: Created: Fri Jan 19 00:58:27 2024
210 00:58:27.728512 output: Image 0 (kernel-1)
211 00:58:27.728581 output: Description:
212 00:58:27.728647 output: Created: Fri Jan 19 00:58:27 2024
213 00:58:27.728710 output: Type: Kernel Image
214 00:58:27.728772 output: Compression: lzma compressed
215 00:58:27.728830 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
216 00:58:27.728915 output: Architecture: AArch64
217 00:58:27.728977 output: OS: Linux
218 00:58:27.729037 output: Load Address: 0x00000000
219 00:58:27.729099 output: Entry Point: 0x00000000
220 00:58:27.729181 output: Hash algo: crc32
221 00:58:27.729285 output: Hash value: a52aa383
222 00:58:27.729373 output: Image 1 (fdt-1)
223 00:58:27.729463 output: Description: mt8192-asurada-spherion-r0
224 00:58:27.729547 output: Created: Fri Jan 19 00:58:27 2024
225 00:58:27.729630 output: Type: Flat Device Tree
226 00:58:27.729712 output: Compression: uncompressed
227 00:58:27.729794 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 00:58:27.729909 output: Architecture: AArch64
229 00:58:27.729992 output: Hash algo: crc32
230 00:58:27.730102 output: Hash value: cc4352de
231 00:58:27.730194 output: Image 2 (ramdisk-1)
232 00:58:27.730258 output: Description: unavailable
233 00:58:27.730357 output: Created: Fri Jan 19 00:58:27 2024
234 00:58:27.730453 output: Type: RAMDisk Image
235 00:58:27.730535 output: Compression: Unknown Compression
236 00:58:27.730617 output: Data Size: 56441665 Bytes = 55118.81 KiB = 53.83 MiB
237 00:58:27.730699 output: Architecture: AArch64
238 00:58:27.730780 output: OS: Linux
239 00:58:27.730862 output: Load Address: unavailable
240 00:58:27.730944 output: Entry Point: unavailable
241 00:58:27.731025 output: Hash algo: crc32
242 00:58:27.731106 output: Hash value: ccfe2ba0
243 00:58:27.731215 output: Default Configuration: 'conf-1'
244 00:58:27.731296 output: Configuration 0 (conf-1)
245 00:58:27.731378 output: Description: mt8192-asurada-spherion-r0
246 00:58:27.731459 output: Kernel: kernel-1
247 00:58:27.731540 output: Init Ramdisk: ramdisk-1
248 00:58:27.731622 output: FDT: fdt-1
249 00:58:27.731703 output: Loadables: kernel-1
250 00:58:27.731801 output:
251 00:58:27.732149 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 00:58:27.732309 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 00:58:27.732456 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 00:58:27.732598 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 00:58:27.732680 No LXC device requested
256 00:58:27.732763 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:58:27.732852 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 00:58:27.732928 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:58:27.732999 Checking files for TFTP limit of 4294967296 bytes.
260 00:58:27.733515 end: 1 tftp-deploy (duration 00:00:27) [common]
261 00:58:27.733619 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:58:27.733711 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:58:27.733832 substitutions:
264 00:58:27.733902 - {DTB}: 12571066/tftp-deploy-rlef6bsi/dtb/mt8192-asurada-spherion-r0.dtb
265 00:58:27.733965 - {INITRD}: 12571066/tftp-deploy-rlef6bsi/ramdisk/ramdisk.cpio.gz
266 00:58:27.734024 - {KERNEL}: 12571066/tftp-deploy-rlef6bsi/kernel/Image
267 00:58:27.734081 - {LAVA_MAC}: None
268 00:58:27.734137 - {PRESEED_CONFIG}: None
269 00:58:27.734193 - {PRESEED_LOCAL}: None
270 00:58:27.734246 - {RAMDISK}: 12571066/tftp-deploy-rlef6bsi/ramdisk/ramdisk.cpio.gz
271 00:58:27.734303 - {ROOT_PART}: None
272 00:58:27.734357 - {ROOT}: None
273 00:58:27.734411 - {SERVER_IP}: 192.168.201.1
274 00:58:27.734465 - {TEE}: None
275 00:58:27.734519 Parsed boot commands:
276 00:58:27.734573 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:58:27.734747 Parsed boot commands: tftpboot 192.168.201.1 12571066/tftp-deploy-rlef6bsi/kernel/image.itb 12571066/tftp-deploy-rlef6bsi/kernel/cmdline
278 00:58:27.734838 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:58:27.734925 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:58:27.735019 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:58:27.735103 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:58:27.735173 Not connected, no need to disconnect.
283 00:58:27.735246 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:58:27.735330 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:58:27.735396 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 00:58:27.739490 Setting prompt string to ['lava-test: # ']
287 00:58:27.739863 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:58:27.739975 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:58:27.740075 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:58:27.740204 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:58:27.740645 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 00:58:32.879268 >> Command sent successfully.
293 00:58:32.881875 Returned 0 in 5 seconds
294 00:58:32.982273 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 00:58:32.982610 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 00:58:32.982703 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 00:58:32.982792 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:58:32.982859 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:58:32.982949 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:58:32.983232 [Enter `^Ec?' for help]
302 00:58:33.155235
303 00:58:33.155386
304 00:58:33.155456 F0: 102B 0000
305 00:58:33.155523
306 00:58:33.155582 F3: 1001 0000 [0200]
307 00:58:33.158812
308 00:58:33.158902 F3: 1001 0000
309 00:58:33.158969
310 00:58:33.159029 F7: 102D 0000
311 00:58:33.159087
312 00:58:33.161615 F1: 0000 0000
313 00:58:33.161700
314 00:58:33.161765 V0: 0000 0000 [0001]
315 00:58:33.161824
316 00:58:33.164853 00: 0007 8000
317 00:58:33.164944
318 00:58:33.165009 01: 0000 0000
319 00:58:33.165072
320 00:58:33.168759 BP: 0C00 0209 [0000]
321 00:58:33.168848
322 00:58:33.168914 G0: 1182 0000
323 00:58:33.168975
324 00:58:33.172046 EC: 0000 0021 [4000]
325 00:58:33.172132
326 00:58:33.172197 S7: 0000 0000 [0000]
327 00:58:33.172258
328 00:58:33.175565 CC: 0000 0000 [0001]
329 00:58:33.175653
330 00:58:33.175719 T0: 0000 0040 [010F]
331 00:58:33.175780
332 00:58:33.175839 Jump to BL
333 00:58:33.175897
334 00:58:33.202508
335 00:58:33.202661
336 00:58:33.202732
337 00:58:33.209561 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 00:58:33.213332 ARM64: Exception handlers installed.
339 00:58:33.217027 ARM64: Testing exception
340 00:58:33.220123 ARM64: Done test exception
341 00:58:33.226795 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 00:58:33.237297 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 00:58:33.244187 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 00:58:33.253901 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 00:58:33.261027 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 00:58:33.267786 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 00:58:33.279580 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 00:58:33.285850 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 00:58:33.304897 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 00:58:33.308362 WDT: Last reset was cold boot
351 00:58:33.311278 SPI1(PAD0) initialized at 2873684 Hz
352 00:58:33.315244 SPI5(PAD0) initialized at 992727 Hz
353 00:58:33.318243 VBOOT: Loading verstage.
354 00:58:33.324894 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 00:58:33.328231 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 00:58:33.331264 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 00:58:33.334710 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 00:58:33.342397 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 00:58:33.348992 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 00:58:33.360544 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 00:58:33.360709
362 00:58:33.360778
363 00:58:33.370900 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 00:58:33.373945 ARM64: Exception handlers installed.
365 00:58:33.377511 ARM64: Testing exception
366 00:58:33.377603 ARM64: Done test exception
367 00:58:33.383989 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 00:58:33.387237 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 00:58:33.400981 Probing TPM: . done!
370 00:58:33.401145 TPM ready after 0 ms
371 00:58:33.408196 Connected to device vid:did:rid of 1ae0:0028:00
372 00:58:33.414730 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 00:58:33.474302 Initialized TPM device CR50 revision 0
374 00:58:33.485560 tlcl_send_startup: Startup return code is 0
375 00:58:33.485713 TPM: setup succeeded
376 00:58:33.497158 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 00:58:33.506091 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:58:33.518498 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 00:58:33.528580 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 00:58:33.532340 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 00:58:33.536305 in-header: 03 07 00 00 08 00 00 00
382 00:58:33.540101 in-data: aa e4 47 04 13 02 00 00
383 00:58:33.540236 Chrome EC: UHEPI supported
384 00:58:33.546607 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 00:58:33.550336 in-header: 03 95 00 00 08 00 00 00
386 00:58:33.554362 in-data: 18 20 20 08 00 00 00 00
387 00:58:33.554497 Phase 1
388 00:58:33.558075 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 00:58:33.565124 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 00:58:33.572579 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 00:58:33.572715 Recovery requested (1009000e)
392 00:58:33.584122 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:58:33.588870 tlcl_extend: response is 0
394 00:58:33.598968 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:58:33.603311 tlcl_extend: response is 0
396 00:58:33.610126 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:58:33.630102 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 00:58:33.636829 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:58:33.636956
400 00:58:33.637022
401 00:58:33.647033 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:58:33.650163 ARM64: Exception handlers installed.
403 00:58:33.653369 ARM64: Testing exception
404 00:58:33.653470 ARM64: Done test exception
405 00:58:33.675485 pmic_efuse_setting: Set efuses in 11 msecs
406 00:58:33.679327 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:58:33.685494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:58:33.689228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:58:33.696768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:58:33.700254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:58:33.703968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:58:33.707962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:58:33.715054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:58:33.718941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:58:33.723129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:58:33.726227 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:58:33.734151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:58:33.737695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:58:33.741496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:58:33.748875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:58:33.752682 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:58:33.759856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:58:33.763851 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:58:33.770992 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:58:33.778446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:58:33.781637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:58:33.789678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:58:33.793387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:58:33.800182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:58:33.804031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:58:33.808114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:58:33.815344 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:58:33.818930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:58:33.825875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:58:33.829666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:58:33.833662 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:58:33.840943 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:58:33.844891 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:58:33.848021 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:58:33.855227 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:58:33.859452 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:58:33.863159 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:58:33.870895 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:58:33.874157 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:58:33.877865 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:58:33.884954 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:58:33.888671 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:58:33.892260 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:58:33.895549 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:58:33.899360 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:58:33.906537 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:58:33.910637 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:58:33.914528 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:58:33.917759 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:58:33.921405 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:58:33.925514 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:58:33.928892 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:58:33.940447 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 00:58:33.947577 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:58:33.950574 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:58:33.961400 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:58:33.969165 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:58:33.972890 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:58:33.975992 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:58:33.980085 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:58:33.989695 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2d
467 00:58:33.992988 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:58:34.001054 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:58:34.004231 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:58:34.013469 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 00:58:34.023044 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 00:58:34.032299 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 00:58:34.041835 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 00:58:34.051366 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 00:58:34.060544 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 00:58:34.071604 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 00:58:34.074899 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:58:34.078637 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:58:34.082511 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:58:34.090173 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 00:58:34.093336 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:58:34.097855 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 00:58:34.097962 ADC[4]: Raw value=906203 ID=7
484 00:58:34.101662 ADC[3]: Raw value=213810 ID=1
485 00:58:34.104874 RAM Code: 0x71
486 00:58:34.108478 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:58:34.112226 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:58:34.119958 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 00:58:34.127212 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 00:58:34.130275 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:58:34.133854 in-header: 03 07 00 00 08 00 00 00
492 00:58:34.137719 in-data: aa e4 47 04 13 02 00 00
493 00:58:34.141426 Chrome EC: UHEPI supported
494 00:58:34.149339 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:58:34.153079 in-header: 03 95 00 00 08 00 00 00
496 00:58:34.153193 in-data: 18 20 20 08 00 00 00 00
497 00:58:34.156687 MRC: failed to locate region type 0.
498 00:58:34.164248 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:58:34.167867 DRAM-K: Running full calibration
500 00:58:34.171536 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 00:58:34.175432 header.status = 0x0
502 00:58:34.179386 header.version = 0x6 (expected: 0x6)
503 00:58:34.183297 header.size = 0xd00 (expected: 0xd00)
504 00:58:34.183396 header.flags = 0x0
505 00:58:34.190333 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:58:34.207903 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 00:58:34.215425 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:58:34.215607 dram_init: ddr_geometry: 2
509 00:58:34.218779 [EMI] MDL number = 2
510 00:58:34.222567 [EMI] Get MDL freq = 0
511 00:58:34.222664 dram_init: ddr_type: 0
512 00:58:34.226447 is_discrete_lpddr4: 1
513 00:58:34.230143 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:58:34.230244
515 00:58:34.230310
516 00:58:34.230369 [Bian_co] ETT version 0.0.0.1
517 00:58:34.237119 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 00:58:34.237228
519 00:58:34.241540 dramc_set_vcore_voltage set vcore to 650000
520 00:58:34.241632 Read voltage for 800, 4
521 00:58:34.244676 Vio18 = 0
522 00:58:34.244763 Vcore = 650000
523 00:58:34.244828 Vdram = 0
524 00:58:34.244888 Vddq = 0
525 00:58:34.248424 Vmddr = 0
526 00:58:34.248511 dram_init: config_dvfs: 1
527 00:58:34.255648 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:58:34.259268 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:58:34.263477 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 00:58:34.267412 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 00:58:34.270783 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 00:58:34.274764 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 00:58:34.278383 MEM_TYPE=3, freq_sel=18
534 00:58:34.281980 sv_algorithm_assistance_LP4_1600
535 00:58:34.285523 ============ PULL DRAM RESETB DOWN ============
536 00:58:34.288599 ========== PULL DRAM RESETB DOWN end =========
537 00:58:34.292232 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:58:34.295427 ===================================
539 00:58:34.298888 LPDDR4 DRAM CONFIGURATION
540 00:58:34.302575 ===================================
541 00:58:34.306232 EX_ROW_EN[0] = 0x0
542 00:58:34.306333 EX_ROW_EN[1] = 0x0
543 00:58:34.309892 LP4Y_EN = 0x0
544 00:58:34.310074 WORK_FSP = 0x0
545 00:58:34.310189 WL = 0x2
546 00:58:34.313941 RL = 0x2
547 00:58:34.314040 BL = 0x2
548 00:58:34.317461 RPST = 0x0
549 00:58:34.317555 RD_PRE = 0x0
550 00:58:34.321269 WR_PRE = 0x1
551 00:58:34.321364 WR_PST = 0x0
552 00:58:34.324445 DBI_WR = 0x0
553 00:58:34.324535 DBI_RD = 0x0
554 00:58:34.328171 OTF = 0x1
555 00:58:34.331471 ===================================
556 00:58:34.334501 ===================================
557 00:58:34.334590 ANA top config
558 00:58:34.337781 ===================================
559 00:58:34.341039 DLL_ASYNC_EN = 0
560 00:58:34.344257 ALL_SLAVE_EN = 1
561 00:58:34.344386 NEW_RANK_MODE = 1
562 00:58:34.348082 DLL_IDLE_MODE = 1
563 00:58:34.351168 LP45_APHY_COMB_EN = 1
564 00:58:34.354748 TX_ODT_DIS = 1
565 00:58:34.354844 NEW_8X_MODE = 1
566 00:58:34.358637 ===================================
567 00:58:34.361868 ===================================
568 00:58:34.365223 data_rate = 1600
569 00:58:34.368471 CKR = 1
570 00:58:34.371598 DQ_P2S_RATIO = 8
571 00:58:34.375326 ===================================
572 00:58:34.378696 CA_P2S_RATIO = 8
573 00:58:34.378790 DQ_CA_OPEN = 0
574 00:58:34.381923 DQ_SEMI_OPEN = 0
575 00:58:34.385012 CA_SEMI_OPEN = 0
576 00:58:34.388696 CA_FULL_RATE = 0
577 00:58:34.391783 DQ_CKDIV4_EN = 1
578 00:58:34.395238 CA_CKDIV4_EN = 1
579 00:58:34.395333 CA_PREDIV_EN = 0
580 00:58:34.398722 PH8_DLY = 0
581 00:58:34.402165 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:58:34.405325 DQ_AAMCK_DIV = 4
583 00:58:34.408419 CA_AAMCK_DIV = 4
584 00:58:34.411964 CA_ADMCK_DIV = 4
585 00:58:34.412148 DQ_TRACK_CA_EN = 0
586 00:58:34.415540 CA_PICK = 800
587 00:58:34.418730 CA_MCKIO = 800
588 00:58:34.421976 MCKIO_SEMI = 0
589 00:58:34.425827 PLL_FREQ = 3068
590 00:58:34.429415 DQ_UI_PI_RATIO = 32
591 00:58:34.429541 CA_UI_PI_RATIO = 0
592 00:58:34.433031 ===================================
593 00:58:34.437107 ===================================
594 00:58:34.441111 memory_type:LPDDR4
595 00:58:34.441241 GP_NUM : 10
596 00:58:34.444655 SRAM_EN : 1
597 00:58:34.444772 MD32_EN : 0
598 00:58:34.448523 ===================================
599 00:58:34.452379 [ANA_INIT] >>>>>>>>>>>>>>
600 00:58:34.456192 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:58:34.456365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:58:34.459454 ===================================
603 00:58:34.462836 data_rate = 1600,PCW = 0X7600
604 00:58:34.466613 ===================================
605 00:58:34.469827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:58:34.476254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:58:34.482758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:58:34.486746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:58:34.489936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:58:34.492914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:58:34.496043 [ANA_INIT] flow start
612 00:58:34.496138 [ANA_INIT] PLL >>>>>>>>
613 00:58:34.499767 [ANA_INIT] PLL <<<<<<<<
614 00:58:34.502861 [ANA_INIT] MIDPI >>>>>>>>
615 00:58:34.502957 [ANA_INIT] MIDPI <<<<<<<<
616 00:58:34.505962 [ANA_INIT] DLL >>>>>>>>
617 00:58:34.509401 [ANA_INIT] flow end
618 00:58:34.512621 ============ LP4 DIFF to SE enter ============
619 00:58:34.516460 ============ LP4 DIFF to SE exit ============
620 00:58:34.519733 [ANA_INIT] <<<<<<<<<<<<<
621 00:58:34.522947 [Flow] Enable top DCM control >>>>>
622 00:58:34.526160 [Flow] Enable top DCM control <<<<<
623 00:58:34.529390 Enable DLL master slave shuffle
624 00:58:34.533103 ==============================================================
625 00:58:34.536378 Gating Mode config
626 00:58:34.542558 ==============================================================
627 00:58:34.542684 Config description:
628 00:58:34.552867 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:58:34.559271 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:58:34.562830 SELPH_MODE 0: By rank 1: By Phase
631 00:58:34.569594 ==============================================================
632 00:58:34.572756 GAT_TRACK_EN = 1
633 00:58:34.576069 RX_GATING_MODE = 2
634 00:58:34.579256 RX_GATING_TRACK_MODE = 2
635 00:58:34.582929 SELPH_MODE = 1
636 00:58:34.586157 PICG_EARLY_EN = 1
637 00:58:34.586296 VALID_LAT_VALUE = 1
638 00:58:34.592995 ==============================================================
639 00:58:34.596098 Enter into Gating configuration >>>>
640 00:58:34.599805 Exit from Gating configuration <<<<
641 00:58:34.602963 Enter into DVFS_PRE_config >>>>>
642 00:58:34.612942 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:58:34.616027 Exit from DVFS_PRE_config <<<<<
644 00:58:34.619946 Enter into PICG configuration >>>>
645 00:58:34.623009 Exit from PICG configuration <<<<
646 00:58:34.626151 [RX_INPUT] configuration >>>>>
647 00:58:34.629965 [RX_INPUT] configuration <<<<<
648 00:58:34.633147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:58:34.639870 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:58:34.646889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:58:34.653174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:58:34.656314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:58:34.663444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:58:34.669864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:58:34.673128 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:58:34.676656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:58:34.679693 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:58:34.683178 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:58:34.689827 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:58:34.693392 ===================================
661 00:58:34.696546 LPDDR4 DRAM CONFIGURATION
662 00:58:34.696667 ===================================
663 00:58:34.699729 EX_ROW_EN[0] = 0x0
664 00:58:34.703069 EX_ROW_EN[1] = 0x0
665 00:58:34.703177 LP4Y_EN = 0x0
666 00:58:34.706907 WORK_FSP = 0x0
667 00:58:34.707013 WL = 0x2
668 00:58:34.709749 RL = 0x2
669 00:58:34.709858 BL = 0x2
670 00:58:34.713048 RPST = 0x0
671 00:58:34.713162 RD_PRE = 0x0
672 00:58:34.716542 WR_PRE = 0x1
673 00:58:34.716654 WR_PST = 0x0
674 00:58:34.719960 DBI_WR = 0x0
675 00:58:34.720071 DBI_RD = 0x0
676 00:58:34.723029 OTF = 0x1
677 00:58:34.726441 ===================================
678 00:58:34.729770 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:58:34.733584 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:58:34.739908 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:58:34.743074 ===================================
682 00:58:34.743191 LPDDR4 DRAM CONFIGURATION
683 00:58:34.746936 ===================================
684 00:58:34.750163 EX_ROW_EN[0] = 0x10
685 00:58:34.753391 EX_ROW_EN[1] = 0x0
686 00:58:34.753511 LP4Y_EN = 0x0
687 00:58:34.756539 WORK_FSP = 0x0
688 00:58:34.756652 WL = 0x2
689 00:58:34.760174 RL = 0x2
690 00:58:34.760250 BL = 0x2
691 00:58:34.763259 RPST = 0x0
692 00:58:34.763362 RD_PRE = 0x0
693 00:58:34.766890 WR_PRE = 0x1
694 00:58:34.767004 WR_PST = 0x0
695 00:58:34.770124 DBI_WR = 0x0
696 00:58:34.770199 DBI_RD = 0x0
697 00:58:34.773513 OTF = 0x1
698 00:58:34.776661 ===================================
699 00:58:34.783222 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:58:34.786388 nWR fixed to 40
701 00:58:34.786501 [ModeRegInit_LP4] CH0 RK0
702 00:58:34.790213 [ModeRegInit_LP4] CH0 RK1
703 00:58:34.793625 [ModeRegInit_LP4] CH1 RK0
704 00:58:34.793741 [ModeRegInit_LP4] CH1 RK1
705 00:58:34.796757 match AC timing 13
706 00:58:34.799936 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 00:58:34.803811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:58:34.810404 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:58:34.813572 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:58:34.820533 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:58:34.820668 [EMI DOE] emi_dcm 0
712 00:58:34.823693 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:58:34.823808 ==
714 00:58:34.826699 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:58:34.833446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 00:58:34.833583 ==
717 00:58:34.836921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:58:34.843641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:58:34.852836 [CA 0] Center 36 (6~67) winsize 62
720 00:58:34.856229 [CA 1] Center 36 (6~67) winsize 62
721 00:58:34.859912 [CA 2] Center 34 (4~65) winsize 62
722 00:58:34.863103 [CA 3] Center 34 (3~65) winsize 63
723 00:58:34.866463 [CA 4] Center 33 (3~64) winsize 62
724 00:58:34.870302 [CA 5] Center 32 (3~62) winsize 60
725 00:58:34.870394
726 00:58:34.872955 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 00:58:34.873030
728 00:58:34.876505 [CATrainingPosCal] consider 1 rank data
729 00:58:34.879687 u2DelayCellTimex100 = 270/100 ps
730 00:58:34.883191 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 00:58:34.886422 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 00:58:34.892938 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 00:58:34.896759 CA3 delay=34 (3~65),Diff = 2 PI (14 cell)
734 00:58:34.899945 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 00:58:34.903379 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 00:58:34.903473
737 00:58:34.906353 CA PerBit enable=1, Macro0, CA PI delay=32
738 00:58:34.906442
739 00:58:34.909626 [CBTSetCACLKResult] CA Dly = 32
740 00:58:34.909711 CS Dly: 5 (0~36)
741 00:58:34.909776 ==
742 00:58:34.913467 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:58:34.919625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 00:58:34.919740 ==
745 00:58:34.922865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:58:34.929619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:58:34.939488 [CA 0] Center 36 (6~67) winsize 62
748 00:58:34.942616 [CA 1] Center 36 (6~67) winsize 62
749 00:58:34.945852 [CA 2] Center 34 (4~65) winsize 62
750 00:58:34.949591 [CA 3] Center 34 (3~65) winsize 63
751 00:58:34.952876 [CA 4] Center 33 (3~64) winsize 62
752 00:58:34.956086 [CA 5] Center 32 (2~63) winsize 62
753 00:58:34.956174
754 00:58:34.959319 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 00:58:34.959404
756 00:58:34.962583 [CATrainingPosCal] consider 2 rank data
757 00:58:34.966281 u2DelayCellTimex100 = 270/100 ps
758 00:58:34.969113 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 00:58:34.972901 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 00:58:34.979349 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 00:58:34.982495 CA3 delay=34 (3~65),Diff = 2 PI (14 cell)
762 00:58:34.985744 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
763 00:58:34.989365 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 00:58:34.989460
765 00:58:34.992647 CA PerBit enable=1, Macro0, CA PI delay=32
766 00:58:34.992737
767 00:58:34.996213 [CBTSetCACLKResult] CA Dly = 32
768 00:58:34.996366 CS Dly: 5 (0~36)
769 00:58:34.996460
770 00:58:34.999312 ----->DramcWriteLeveling(PI) begin...
771 00:58:35.002701 ==
772 00:58:35.002802 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:58:35.010224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 00:58:35.010357 ==
775 00:58:35.010452 Write leveling (Byte 0): 32 => 32
776 00:58:35.014247 Write leveling (Byte 1): 30 => 30
777 00:58:35.017777 DramcWriteLeveling(PI) end<-----
778 00:58:35.017898
779 00:58:35.017995 ==
780 00:58:35.021981 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:58:35.025416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 00:58:35.025515 ==
783 00:58:35.028430 [Gating] SW mode calibration
784 00:58:35.036149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:58:35.039205 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:58:35.046069 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 00:58:35.049234 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 00:58:35.052438 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 00:58:35.059437 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:58:35.062430 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:58:35.065817 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:58:35.072743 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:58:35.075950 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:58:35.079080 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:58:35.086017 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:58:35.089819 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:58:35.092983 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:58:35.099302 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:58:35.102521 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:58:35.106097 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:58:35.112445 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:58:35.116372 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:58:35.119577 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 00:58:35.122634 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 00:58:35.129225 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:58:35.132473 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:58:35.136242 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:58:35.142492 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 00:58:35.146097 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:58:35.149661 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 00:58:35.156062 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:58:35.159750 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
813 00:58:35.162774 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 00:58:35.169918 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 00:58:35.173175 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 00:58:35.176223 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 00:58:35.183145 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 00:58:35.186425 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 00:58:35.189499 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 00:58:35.193187 0 10 8 | B1->B0 | 3232 2727 | 0 0 | (0 1) (1 1)
821 00:58:35.199629 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
822 00:58:35.203527 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 00:58:35.206391 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 00:58:35.213417 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 00:58:35.216282 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 00:58:35.220258 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 00:58:35.227069 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:58:35.230212 0 11 8 | B1->B0 | 3030 3c3c | 1 0 | (0 0) (0 0)
829 00:58:35.233426 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 00:58:35.240500 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 00:58:35.243562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 00:58:35.246833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 00:58:35.249962 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 00:58:35.257068 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 00:58:35.260140 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 00:58:35.263880 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 00:58:35.270109 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:58:35.273956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:58:35.277043 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:58:35.283736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:58:35.286970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:58:35.290114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:58:35.297081 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:58:35.300215 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:58:35.303537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:58:35.310267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:58:35.313793 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:58:35.317149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:58:35.320214 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:58:35.327099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:58:35.330591 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 00:58:35.334068 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 00:58:35.337154 Total UI for P1: 0, mck2ui 16
854 00:58:35.340448 best dqsien dly found for B0: ( 0, 14, 4)
855 00:58:35.346919 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 00:58:35.350789 Total UI for P1: 0, mck2ui 16
857 00:58:35.354200 best dqsien dly found for B1: ( 0, 14, 8)
858 00:58:35.357912 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 00:58:35.361265 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 00:58:35.361378
861 00:58:35.364575 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 00:58:35.367656 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 00:58:35.370980 [Gating] SW calibration Done
864 00:58:35.371086 ==
865 00:58:35.374948 Dram Type= 6, Freq= 0, CH_0, rank 0
866 00:58:35.378122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 00:58:35.378230 ==
868 00:58:35.378325 RX Vref Scan: 0
869 00:58:35.378416
870 00:58:35.381365 RX Vref 0 -> 0, step: 1
871 00:58:35.381464
872 00:58:35.384596 RX Delay -130 -> 252, step: 16
873 00:58:35.387903 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 00:58:35.391612 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 00:58:35.398059 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
876 00:58:35.401035 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
877 00:58:35.404881 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 00:58:35.407870 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 00:58:35.411553 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
880 00:58:35.414693 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
881 00:58:35.421758 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
882 00:58:35.425036 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 00:58:35.427949 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
884 00:58:35.431164 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 00:58:35.438204 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 00:58:35.441215 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 00:58:35.444594 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 00:58:35.447789 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 00:58:35.447879 ==
890 00:58:35.451238 Dram Type= 6, Freq= 0, CH_0, rank 0
891 00:58:35.454361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 00:58:35.458127 ==
893 00:58:35.458251 DQS Delay:
894 00:58:35.458333 DQS0 = 0, DQS1 = 0
895 00:58:35.461040 DQM Delay:
896 00:58:35.461129 DQM0 = 93, DQM1 = 85
897 00:58:35.464681 DQ Delay:
898 00:58:35.468271 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 00:58:35.468398 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 00:58:35.471548 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
901 00:58:35.474688 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 00:58:35.477813
903 00:58:35.477901
904 00:58:35.477966 ==
905 00:58:35.481611 Dram Type= 6, Freq= 0, CH_0, rank 0
906 00:58:35.484855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 00:58:35.484946 ==
908 00:58:35.485013
909 00:58:35.485074
910 00:58:35.488002 TX Vref Scan disable
911 00:58:35.488088 == TX Byte 0 ==
912 00:58:35.494463 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 00:58:35.497713 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 00:58:35.497807 == TX Byte 1 ==
915 00:58:35.504789 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 00:58:35.508193 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 00:58:35.508324 ==
918 00:58:35.511576 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:58:35.514689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:58:35.514815 ==
921 00:58:35.528223 TX Vref=22, minBit 9, minWin=27, winSum=448
922 00:58:35.531948 TX Vref=24, minBit 12, minWin=27, winSum=453
923 00:58:35.535164 TX Vref=26, minBit 0, minWin=28, winSum=456
924 00:58:35.538255 TX Vref=28, minBit 9, minWin=27, winSum=455
925 00:58:35.541540 TX Vref=30, minBit 10, minWin=27, winSum=456
926 00:58:35.548426 TX Vref=32, minBit 0, minWin=28, winSum=453
927 00:58:35.551677 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
928 00:58:35.551799
929 00:58:35.554865 Final TX Range 1 Vref 26
930 00:58:35.555018
931 00:58:35.555116 ==
932 00:58:35.558674 Dram Type= 6, Freq= 0, CH_0, rank 0
933 00:58:35.561626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 00:58:35.561743 ==
935 00:58:35.565029
936 00:58:35.565134
937 00:58:35.565281 TX Vref Scan disable
938 00:58:35.568444 == TX Byte 0 ==
939 00:58:35.571903 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 00:58:35.575166 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 00:58:35.578199 == TX Byte 1 ==
942 00:58:35.581854 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 00:58:35.585870 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 00:58:35.588308
945 00:58:35.588443 [DATLAT]
946 00:58:35.588571 Freq=800, CH0 RK0
947 00:58:35.588665
948 00:58:35.591867 DATLAT Default: 0xa
949 00:58:35.591961 0, 0xFFFF, sum = 0
950 00:58:35.595188 1, 0xFFFF, sum = 0
951 00:58:35.595330 2, 0xFFFF, sum = 0
952 00:58:35.598625 3, 0xFFFF, sum = 0
953 00:58:35.598717 4, 0xFFFF, sum = 0
954 00:58:35.601735 5, 0xFFFF, sum = 0
955 00:58:35.601886 6, 0xFFFF, sum = 0
956 00:58:35.605119 7, 0xFFFF, sum = 0
957 00:58:35.605276 8, 0xFFFF, sum = 0
958 00:58:35.608980 9, 0x0, sum = 1
959 00:58:35.609104 10, 0x0, sum = 2
960 00:58:35.612179 11, 0x0, sum = 3
961 00:58:35.612331 12, 0x0, sum = 4
962 00:58:35.615126 best_step = 10
963 00:58:35.615246
964 00:58:35.615343 ==
965 00:58:35.618697 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:58:35.622319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 00:58:35.622436 ==
968 00:58:35.625446 RX Vref Scan: 1
969 00:58:35.625560
970 00:58:35.625656 Set Vref Range= 32 -> 127
971 00:58:35.625746
972 00:58:35.628781 RX Vref 32 -> 127, step: 1
973 00:58:35.628888
974 00:58:35.631886 RX Delay -79 -> 252, step: 8
975 00:58:35.631996
976 00:58:35.635188 Set Vref, RX VrefLevel [Byte0]: 32
977 00:58:35.639168 [Byte1]: 32
978 00:58:35.639263
979 00:58:35.642284 Set Vref, RX VrefLevel [Byte0]: 33
980 00:58:35.645355 [Byte1]: 33
981 00:58:35.649172
982 00:58:35.649267 Set Vref, RX VrefLevel [Byte0]: 34
983 00:58:35.651813 [Byte1]: 34
984 00:58:35.656213
985 00:58:35.656370 Set Vref, RX VrefLevel [Byte0]: 35
986 00:58:35.659383 [Byte1]: 35
987 00:58:35.663799
988 00:58:35.663889 Set Vref, RX VrefLevel [Byte0]: 36
989 00:58:35.666851 [Byte1]: 36
990 00:58:35.671375
991 00:58:35.671469 Set Vref, RX VrefLevel [Byte0]: 37
992 00:58:35.675094 [Byte1]: 37
993 00:58:35.679356
994 00:58:35.679456 Set Vref, RX VrefLevel [Byte0]: 38
995 00:58:35.682629 [Byte1]: 38
996 00:58:35.687108
997 00:58:35.687200 Set Vref, RX VrefLevel [Byte0]: 39
998 00:58:35.690259 [Byte1]: 39
999 00:58:35.694831
1000 00:58:35.694937 Set Vref, RX VrefLevel [Byte0]: 40
1001 00:58:35.697936 [Byte1]: 40
1002 00:58:35.701868
1003 00:58:35.702001 Set Vref, RX VrefLevel [Byte0]: 41
1004 00:58:35.705111 [Byte1]: 41
1005 00:58:35.709227
1006 00:58:35.709362 Set Vref, RX VrefLevel [Byte0]: 42
1007 00:58:35.712269 [Byte1]: 42
1008 00:58:35.716710
1009 00:58:35.716826 Set Vref, RX VrefLevel [Byte0]: 43
1010 00:58:35.719764 [Byte1]: 43
1011 00:58:35.724251
1012 00:58:35.724377 Set Vref, RX VrefLevel [Byte0]: 44
1013 00:58:35.727560 [Byte1]: 44
1014 00:58:35.731770
1015 00:58:35.731876 Set Vref, RX VrefLevel [Byte0]: 45
1016 00:58:35.735225 [Byte1]: 45
1017 00:58:35.739015
1018 00:58:35.739108 Set Vref, RX VrefLevel [Byte0]: 46
1019 00:58:35.742525 [Byte1]: 46
1020 00:58:35.746655
1021 00:58:35.746757 Set Vref, RX VrefLevel [Byte0]: 47
1022 00:58:35.750087 [Byte1]: 47
1023 00:58:35.754567
1024 00:58:35.754664 Set Vref, RX VrefLevel [Byte0]: 48
1025 00:58:35.757755 [Byte1]: 48
1026 00:58:35.761976
1027 00:58:35.762130 Set Vref, RX VrefLevel [Byte0]: 49
1028 00:58:35.765291 [Byte1]: 49
1029 00:58:35.769235
1030 00:58:35.769390 Set Vref, RX VrefLevel [Byte0]: 50
1031 00:58:35.773106 [Byte1]: 50
1032 00:58:35.776733
1033 00:58:35.776825 Set Vref, RX VrefLevel [Byte0]: 51
1034 00:58:35.780542 [Byte1]: 51
1035 00:58:35.784478
1036 00:58:35.784579 Set Vref, RX VrefLevel [Byte0]: 52
1037 00:58:35.787593 [Byte1]: 52
1038 00:58:35.792170
1039 00:58:35.792311 Set Vref, RX VrefLevel [Byte0]: 53
1040 00:58:35.795295 [Byte1]: 53
1041 00:58:35.799927
1042 00:58:35.800039 Set Vref, RX VrefLevel [Byte0]: 54
1043 00:58:35.803089 [Byte1]: 54
1044 00:58:35.807265
1045 00:58:35.807381 Set Vref, RX VrefLevel [Byte0]: 55
1046 00:58:35.810442 [Byte1]: 55
1047 00:58:35.815087
1048 00:58:35.815212 Set Vref, RX VrefLevel [Byte0]: 56
1049 00:58:35.818252 [Byte1]: 56
1050 00:58:35.822077
1051 00:58:35.822202 Set Vref, RX VrefLevel [Byte0]: 57
1052 00:58:35.826133 [Byte1]: 57
1053 00:58:35.829823
1054 00:58:35.829929 Set Vref, RX VrefLevel [Byte0]: 58
1055 00:58:35.832920 [Byte1]: 58
1056 00:58:35.837219
1057 00:58:35.837345 Set Vref, RX VrefLevel [Byte0]: 59
1058 00:58:35.840805 [Byte1]: 59
1059 00:58:35.845205
1060 00:58:35.845311 Set Vref, RX VrefLevel [Byte0]: 60
1061 00:58:35.848203 [Byte1]: 60
1062 00:58:35.852230
1063 00:58:35.852358 Set Vref, RX VrefLevel [Byte0]: 61
1064 00:58:35.855850 [Byte1]: 61
1065 00:58:35.859814
1066 00:58:35.859968 Set Vref, RX VrefLevel [Byte0]: 62
1067 00:58:35.863377 [Byte1]: 62
1068 00:58:35.867445
1069 00:58:35.867547 Set Vref, RX VrefLevel [Byte0]: 63
1070 00:58:35.871348 [Byte1]: 63
1071 00:58:35.875002
1072 00:58:35.875088 Set Vref, RX VrefLevel [Byte0]: 64
1073 00:58:35.878336 [Byte1]: 64
1074 00:58:35.882758
1075 00:58:35.882854 Set Vref, RX VrefLevel [Byte0]: 65
1076 00:58:35.886126 [Byte1]: 65
1077 00:58:35.890275
1078 00:58:35.890360 Set Vref, RX VrefLevel [Byte0]: 66
1079 00:58:35.893509 [Byte1]: 66
1080 00:58:35.897717
1081 00:58:35.897837 Set Vref, RX VrefLevel [Byte0]: 67
1082 00:58:35.901283 [Byte1]: 67
1083 00:58:35.905503
1084 00:58:35.905626 Set Vref, RX VrefLevel [Byte0]: 68
1085 00:58:35.908641 [Byte1]: 68
1086 00:58:35.913338
1087 00:58:35.913491 Set Vref, RX VrefLevel [Byte0]: 69
1088 00:58:35.916408 [Byte1]: 69
1089 00:58:35.920249
1090 00:58:35.920407 Set Vref, RX VrefLevel [Byte0]: 70
1091 00:58:35.924023 [Byte1]: 70
1092 00:58:35.927837
1093 00:58:35.927943 Set Vref, RX VrefLevel [Byte0]: 71
1094 00:58:35.931044 [Byte1]: 71
1095 00:58:35.935701
1096 00:58:35.935806 Set Vref, RX VrefLevel [Byte0]: 72
1097 00:58:35.938885 [Byte1]: 72
1098 00:58:35.943342
1099 00:58:35.943425 Set Vref, RX VrefLevel [Byte0]: 73
1100 00:58:35.946509 [Byte1]: 73
1101 00:58:35.950911
1102 00:58:35.951021 Set Vref, RX VrefLevel [Byte0]: 74
1103 00:58:35.953977 [Byte1]: 74
1104 00:58:35.958172
1105 00:58:35.958277 Set Vref, RX VrefLevel [Byte0]: 75
1106 00:58:35.961635 [Byte1]: 75
1107 00:58:35.965498
1108 00:58:35.965581 Set Vref, RX VrefLevel [Byte0]: 76
1109 00:58:35.969318 [Byte1]: 76
1110 00:58:35.973070
1111 00:58:35.973180 Set Vref, RX VrefLevel [Byte0]: 77
1112 00:58:35.976259 [Byte1]: 77
1113 00:58:35.980749
1114 00:58:35.980844 Final RX Vref Byte 0 = 55 to rank0
1115 00:58:35.984043 Final RX Vref Byte 1 = 65 to rank0
1116 00:58:35.987470 Final RX Vref Byte 0 = 55 to rank1
1117 00:58:35.990679 Final RX Vref Byte 1 = 65 to rank1==
1118 00:58:35.994450 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 00:58:36.000942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 00:58:36.001061 ==
1121 00:58:36.001156 DQS Delay:
1122 00:58:36.001245 DQS0 = 0, DQS1 = 0
1123 00:58:36.004234 DQM Delay:
1124 00:58:36.004353 DQM0 = 91, DQM1 = 86
1125 00:58:36.007506 DQ Delay:
1126 00:58:36.010775 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 00:58:36.013829 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1128 00:58:36.017574 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1129 00:58:36.021092 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1130 00:58:36.021212
1131 00:58:36.021285
1132 00:58:36.027783 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1133 00:58:36.031035 CH0 RK0: MR19=606, MR18=4B41
1134 00:58:36.038005 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1135 00:58:36.038123
1136 00:58:36.041181 ----->DramcWriteLeveling(PI) begin...
1137 00:58:36.041267 ==
1138 00:58:36.044230 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 00:58:36.047523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 00:58:36.047609 ==
1141 00:58:36.050768 Write leveling (Byte 0): 32 => 32
1142 00:58:36.054534 Write leveling (Byte 1): 28 => 28
1143 00:58:36.057775 DramcWriteLeveling(PI) end<-----
1144 00:58:36.057861
1145 00:58:36.057925 ==
1146 00:58:36.061082 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 00:58:36.064097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 00:58:36.064180 ==
1149 00:58:36.067637 [Gating] SW mode calibration
1150 00:58:36.074620 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 00:58:36.118142 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 00:58:36.118876 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 00:58:36.119164 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 00:58:36.119259 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 00:58:36.119326 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:58:36.119396 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:58:36.120003 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:58:36.120281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:58:36.120399 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:58:36.120491 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:58:36.131455 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:58:36.131808 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:58:36.134549 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:58:36.137725 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:58:36.141316 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:58:36.144422 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:58:36.151441 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:58:36.154549 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:58:36.157900 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1170 00:58:36.164898 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1171 00:58:36.168216 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1172 00:58:36.171418 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:58:36.178068 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:58:36.181429 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:58:36.184902 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:58:36.191696 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:58:36.194462 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:58:36.198051 0 9 8 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
1179 00:58:36.201213 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:58:36.208123 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:58:36.211362 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:58:36.214466 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:58:36.221426 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:58:36.224673 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:58:36.227759 0 10 4 | B1->B0 | 3232 3232 | 1 1 | (1 1) (1 1)
1186 00:58:36.234995 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 0)
1187 00:58:36.237853 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1188 00:58:36.241277 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:58:36.248201 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:58:36.251544 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:58:36.255487 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:58:36.259387 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:58:36.262972 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1194 00:58:36.270123 0 11 8 | B1->B0 | 3f3f 3838 | 0 0 | (0 0) (0 0)
1195 00:58:36.273101 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:58:36.276675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:58:36.280222 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:58:36.287382 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:58:36.290281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:58:36.293941 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:58:36.300824 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:58:36.303689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 00:58:36.307406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:58:36.313748 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:58:36.317423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:58:36.320570 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:58:36.327053 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:58:36.330858 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:58:36.334008 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:58:36.340349 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:58:36.343981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:58:36.347251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:58:36.353991 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:58:36.357228 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:58:36.360674 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:58:36.364166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:58:36.370812 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 00:58:36.374064 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 00:58:36.377143 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 00:58:36.380847 Total UI for P1: 0, mck2ui 16
1221 00:58:36.383990 best dqsien dly found for B0: ( 0, 14, 8)
1222 00:58:36.387414 Total UI for P1: 0, mck2ui 16
1223 00:58:36.390470 best dqsien dly found for B1: ( 0, 14, 8)
1224 00:58:36.394046 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1225 00:58:36.397578 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 00:58:36.397671
1227 00:58:36.404168 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 00:58:36.407240 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 00:58:36.407382 [Gating] SW calibration Done
1230 00:58:36.410936 ==
1231 00:58:36.414628 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 00:58:36.417348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 00:58:36.417444 ==
1234 00:58:36.417511 RX Vref Scan: 0
1235 00:58:36.417571
1236 00:58:36.420657 RX Vref 0 -> 0, step: 1
1237 00:58:36.420740
1238 00:58:36.424103 RX Delay -130 -> 252, step: 16
1239 00:58:36.427362 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 00:58:36.431064 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 00:58:36.434206 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 00:58:36.440662 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 00:58:36.444544 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 00:58:36.447522 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 00:58:36.450864 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 00:58:36.454018 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 00:58:36.460917 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 00:58:36.464140 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1249 00:58:36.467652 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1250 00:58:36.471037 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 00:58:36.474485 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1252 00:58:36.480929 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 00:58:36.484149 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 00:58:36.487911 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1255 00:58:36.488002 ==
1256 00:58:36.491029 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:58:36.494418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 00:58:36.494506 ==
1259 00:58:36.497555 DQS Delay:
1260 00:58:36.497637 DQS0 = 0, DQS1 = 0
1261 00:58:36.500704 DQM Delay:
1262 00:58:36.500790 DQM0 = 93, DQM1 = 83
1263 00:58:36.500854 DQ Delay:
1264 00:58:36.504046 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 00:58:36.507720 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 00:58:36.510998 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1267 00:58:36.514151 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1268 00:58:36.514239
1269 00:58:36.514302
1270 00:58:36.517411 ==
1271 00:58:36.521184 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:58:36.524209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:58:36.524356 ==
1274 00:58:36.524422
1275 00:58:36.524488
1276 00:58:36.527674 TX Vref Scan disable
1277 00:58:36.527781 == TX Byte 0 ==
1278 00:58:36.530928 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 00:58:36.537580 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 00:58:36.537707 == TX Byte 1 ==
1281 00:58:36.541142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1282 00:58:36.547241 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1283 00:58:36.547339 ==
1284 00:58:36.550823 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:58:36.554404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 00:58:36.554510 ==
1287 00:58:36.568210 TX Vref=22, minBit 8, minWin=27, winSum=446
1288 00:58:36.571479 TX Vref=24, minBit 11, minWin=27, winSum=452
1289 00:58:36.574620 TX Vref=26, minBit 1, minWin=28, winSum=457
1290 00:58:36.578112 TX Vref=28, minBit 4, minWin=28, winSum=458
1291 00:58:36.581064 TX Vref=30, minBit 4, minWin=28, winSum=459
1292 00:58:36.587825 TX Vref=32, minBit 12, minWin=27, winSum=456
1293 00:58:36.591141 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 30
1294 00:58:36.591225
1295 00:58:36.594642 Final TX Range 1 Vref 30
1296 00:58:36.594729
1297 00:58:36.594791 ==
1298 00:58:36.597844 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 00:58:36.601081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 00:58:36.601167 ==
1301 00:58:36.604869
1302 00:58:36.604956
1303 00:58:36.605018 TX Vref Scan disable
1304 00:58:36.608446 == TX Byte 0 ==
1305 00:58:36.611518 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1306 00:58:36.614650 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1307 00:58:36.618008 == TX Byte 1 ==
1308 00:58:36.621652 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1309 00:58:36.624817 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1310 00:58:36.628050
1311 00:58:36.628211 [DATLAT]
1312 00:58:36.628345 Freq=800, CH0 RK1
1313 00:58:36.628411
1314 00:58:36.631194 DATLAT Default: 0xa
1315 00:58:36.631279 0, 0xFFFF, sum = 0
1316 00:58:36.634869 1, 0xFFFF, sum = 0
1317 00:58:36.634956 2, 0xFFFF, sum = 0
1318 00:58:36.637895 3, 0xFFFF, sum = 0
1319 00:58:36.637986 4, 0xFFFF, sum = 0
1320 00:58:36.641731 5, 0xFFFF, sum = 0
1321 00:58:36.641820 6, 0xFFFF, sum = 0
1322 00:58:36.644694 7, 0xFFFF, sum = 0
1323 00:58:36.647943 8, 0xFFFF, sum = 0
1324 00:58:36.648029 9, 0x0, sum = 1
1325 00:58:36.648094 10, 0x0, sum = 2
1326 00:58:36.651638 11, 0x0, sum = 3
1327 00:58:36.651725 12, 0x0, sum = 4
1328 00:58:36.654636 best_step = 10
1329 00:58:36.654720
1330 00:58:36.654783 ==
1331 00:58:36.658099 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:58:36.661318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:58:36.661405 ==
1334 00:58:36.664857 RX Vref Scan: 0
1335 00:58:36.664944
1336 00:58:36.665007 RX Vref 0 -> 0, step: 1
1337 00:58:36.665069
1338 00:58:36.668221 RX Delay -95 -> 252, step: 8
1339 00:58:36.674833 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1340 00:58:36.678215 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1341 00:58:36.681511 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 00:58:36.684572 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1343 00:58:36.688435 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1344 00:58:36.694625 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1345 00:58:36.697976 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 00:58:36.701460 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 00:58:36.704495 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1348 00:58:36.708271 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 00:58:36.714697 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 00:58:36.718140 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 00:58:36.721297 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1352 00:58:36.725137 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1353 00:58:36.728493 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 00:58:36.734966 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1355 00:58:36.735071 ==
1356 00:58:36.738231 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 00:58:36.741247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 00:58:36.741332 ==
1359 00:58:36.741394 DQS Delay:
1360 00:58:36.744934 DQS0 = 0, DQS1 = 0
1361 00:58:36.745018 DQM Delay:
1362 00:58:36.747849 DQM0 = 93, DQM1 = 83
1363 00:58:36.747931 DQ Delay:
1364 00:58:36.751561 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =92
1365 00:58:36.754776 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1366 00:58:36.758057 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1367 00:58:36.761339 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1368 00:58:36.761428
1369 00:58:36.761490
1370 00:58:36.771686 [DQSOSCAuto] RK1, (LSB)MR18= 0x4213, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 00:58:36.771799 CH0 RK1: MR19=606, MR18=4213
1372 00:58:36.778081 CH0_RK1: MR19=0x606, MR18=0x4213, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 00:58:36.781604 [RxdqsGatingPostProcess] freq 800
1374 00:58:36.788152 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 00:58:36.791471 Pre-setting of DQS Precalculation
1376 00:58:36.795179 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 00:58:36.795270 ==
1378 00:58:36.798048 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 00:58:36.801249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 00:58:36.801363 ==
1381 00:58:36.808067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 00:58:36.814843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 00:58:36.823592 [CA 0] Center 36 (6~67) winsize 62
1384 00:58:36.827320 [CA 1] Center 36 (6~67) winsize 62
1385 00:58:36.829789 [CA 2] Center 35 (5~65) winsize 61
1386 00:58:36.833585 [CA 3] Center 34 (4~65) winsize 62
1387 00:58:36.836873 [CA 4] Center 35 (5~65) winsize 61
1388 00:58:36.840127 [CA 5] Center 34 (4~64) winsize 61
1389 00:58:36.840238
1390 00:58:36.843412 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1391 00:58:36.843510
1392 00:58:36.846480 [CATrainingPosCal] consider 1 rank data
1393 00:58:36.850232 u2DelayCellTimex100 = 270/100 ps
1394 00:58:36.853744 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 00:58:36.856885 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 00:58:36.860020 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1397 00:58:36.867113 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 00:58:36.870254 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 00:58:36.873524 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 00:58:36.873612
1401 00:58:36.877287 CA PerBit enable=1, Macro0, CA PI delay=34
1402 00:58:36.877371
1403 00:58:36.880494 [CBTSetCACLKResult] CA Dly = 34
1404 00:58:36.880576 CS Dly: 6 (0~37)
1405 00:58:36.880640 ==
1406 00:58:36.883287 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 00:58:36.890060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 00:58:36.890167 ==
1409 00:58:36.893211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 00:58:36.899962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 00:58:36.909307 [CA 0] Center 36 (6~67) winsize 62
1412 00:58:36.912574 [CA 1] Center 36 (6~67) winsize 62
1413 00:58:36.917096 [CA 2] Center 34 (4~65) winsize 62
1414 00:58:36.920685 [CA 3] Center 34 (4~65) winsize 62
1415 00:58:36.924239 [CA 4] Center 35 (5~66) winsize 62
1416 00:58:36.927970 [CA 5] Center 34 (4~65) winsize 62
1417 00:58:36.928068
1418 00:58:36.931688 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1419 00:58:36.931777
1420 00:58:36.935081 [CATrainingPosCal] consider 2 rank data
1421 00:58:36.935169 u2DelayCellTimex100 = 270/100 ps
1422 00:58:36.938822 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 00:58:36.942830 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 00:58:36.946258 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 00:58:36.950310 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 00:58:36.953852 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 00:58:36.956772 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 00:58:36.960514
1429 00:58:36.963662 CA PerBit enable=1, Macro0, CA PI delay=34
1430 00:58:36.963752
1431 00:58:36.966996 [CBTSetCACLKResult] CA Dly = 34
1432 00:58:36.967078 CS Dly: 6 (0~38)
1433 00:58:36.967143
1434 00:58:36.970849 ----->DramcWriteLeveling(PI) begin...
1435 00:58:36.970933 ==
1436 00:58:36.974069 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 00:58:36.977334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 00:58:36.980582 ==
1439 00:58:36.980668 Write leveling (Byte 0): 30 => 30
1440 00:58:36.983714 Write leveling (Byte 1): 26 => 26
1441 00:58:36.987398 DramcWriteLeveling(PI) end<-----
1442 00:58:36.987484
1443 00:58:36.987548 ==
1444 00:58:36.990620 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 00:58:36.997100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 00:58:36.997197 ==
1447 00:58:36.997262 [Gating] SW mode calibration
1448 00:58:37.007154 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 00:58:37.010574 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 00:58:37.013960 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1451 00:58:37.020839 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 00:58:37.024084 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:58:37.027108 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:58:37.034319 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:58:37.037490 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:58:37.040775 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:58:37.047165 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:58:37.051289 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:58:37.053958 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:58:37.060627 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:58:37.064146 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:58:37.067736 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:58:37.070953 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:58:37.077422 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:58:37.080589 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:58:37.083741 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 00:58:37.090920 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1468 00:58:37.094014 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:58:37.097203 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:58:37.103951 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:58:37.107509 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:58:37.110431 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:58:37.117450 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:58:37.121041 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:58:37.124232 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1476 00:58:37.130579 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1477 00:58:37.133798 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:58:37.137229 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:58:37.144228 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:58:37.147208 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:58:37.150804 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:58:37.157134 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1483 00:58:37.160489 0 10 4 | B1->B0 | 3030 2a2a | 0 0 | (1 1) (1 1)
1484 00:58:37.164104 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1485 00:58:37.167097 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:58:37.174132 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:58:37.177672 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:58:37.180902 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:58:37.187625 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:58:37.190737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:58:37.194049 0 11 4 | B1->B0 | 2828 3838 | 0 1 | (0 0) (0 0)
1492 00:58:37.201070 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1493 00:58:37.204256 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:58:37.207297 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:58:37.214235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:58:37.217274 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:58:37.220852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:58:37.227374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1499 00:58:37.230475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 00:58:37.234295 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:58:37.240815 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:58:37.244234 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:58:37.247700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:58:37.253958 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:58:37.257296 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:58:37.260580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:58:37.263775 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:58:37.270699 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:58:37.273825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:58:37.277468 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:58:37.283703 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:58:37.287273 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:58:37.290350 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:58:37.297103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:58:37.300464 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 00:58:37.304323 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 00:58:37.307508 Total UI for P1: 0, mck2ui 16
1518 00:58:37.310688 best dqsien dly found for B0: ( 0, 14, 4)
1519 00:58:37.314390 Total UI for P1: 0, mck2ui 16
1520 00:58:37.317455 best dqsien dly found for B1: ( 0, 14, 4)
1521 00:58:37.321228 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 00:58:37.324439 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 00:58:37.324535
1524 00:58:37.327449 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 00:58:37.334466 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 00:58:37.334578 [Gating] SW calibration Done
1527 00:58:37.334668 ==
1528 00:58:37.337493 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 00:58:37.344522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 00:58:37.344628 ==
1531 00:58:37.344715 RX Vref Scan: 0
1532 00:58:37.344796
1533 00:58:37.347750 RX Vref 0 -> 0, step: 1
1534 00:58:37.347836
1535 00:58:37.351574 RX Delay -130 -> 252, step: 16
1536 00:58:37.354613 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 00:58:37.357612 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 00:58:37.361105 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1539 00:58:37.364624 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 00:58:37.371030 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 00:58:37.374768 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 00:58:37.377693 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1543 00:58:37.381038 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 00:58:37.384442 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1545 00:58:37.390966 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1546 00:58:37.394238 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 00:58:37.397758 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 00:58:37.401066 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 00:58:37.404259 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 00:58:37.410948 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 00:58:37.414643 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1552 00:58:37.414749 ==
1553 00:58:37.417620 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 00:58:37.421048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 00:58:37.421138 ==
1556 00:58:37.424705 DQS Delay:
1557 00:58:37.424791 DQS0 = 0, DQS1 = 0
1558 00:58:37.424854 DQM Delay:
1559 00:58:37.427911 DQM0 = 93, DQM1 = 90
1560 00:58:37.428021 DQ Delay:
1561 00:58:37.430882 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1562 00:58:37.434605 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1563 00:58:37.437808 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1564 00:58:37.440783 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1565 00:58:37.440875
1566 00:58:37.440939
1567 00:58:37.440996 ==
1568 00:58:37.444699 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 00:58:37.451119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 00:58:37.451221 ==
1571 00:58:37.451285
1572 00:58:37.451344
1573 00:58:37.451400 TX Vref Scan disable
1574 00:58:37.454742 == TX Byte 0 ==
1575 00:58:37.457908 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1576 00:58:37.461664 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1577 00:58:37.464998 == TX Byte 1 ==
1578 00:58:37.467855 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1579 00:58:37.471667 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1580 00:58:37.474834 ==
1581 00:58:37.478221 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 00:58:37.481326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 00:58:37.481432 ==
1584 00:58:37.494667 TX Vref=22, minBit 0, minWin=27, winSum=441
1585 00:58:37.498394 TX Vref=24, minBit 0, minWin=27, winSum=445
1586 00:58:37.501617 TX Vref=26, minBit 0, minWin=27, winSum=445
1587 00:58:37.504876 TX Vref=28, minBit 0, minWin=27, winSum=446
1588 00:58:37.508126 TX Vref=30, minBit 1, minWin=27, winSum=448
1589 00:58:37.511830 TX Vref=32, minBit 0, minWin=27, winSum=448
1590 00:58:37.518179 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1591 00:58:37.518293
1592 00:58:37.521646 Final TX Range 1 Vref 30
1593 00:58:37.521768
1594 00:58:37.521906 ==
1595 00:58:37.524941 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 00:58:37.528478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 00:58:37.528570 ==
1598 00:58:37.528635
1599 00:58:37.528693
1600 00:58:37.531396 TX Vref Scan disable
1601 00:58:37.534946 == TX Byte 0 ==
1602 00:58:37.538451 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1603 00:58:37.541622 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1604 00:58:37.545351 == TX Byte 1 ==
1605 00:58:37.548516 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 00:58:37.551932 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 00:58:37.552017
1608 00:58:37.555098 [DATLAT]
1609 00:58:37.555180 Freq=800, CH1 RK0
1610 00:58:37.555245
1611 00:58:37.558179 DATLAT Default: 0xa
1612 00:58:37.558261 0, 0xFFFF, sum = 0
1613 00:58:37.561529 1, 0xFFFF, sum = 0
1614 00:58:37.561611 2, 0xFFFF, sum = 0
1615 00:58:37.564777 3, 0xFFFF, sum = 0
1616 00:58:37.564860 4, 0xFFFF, sum = 0
1617 00:58:37.568043 5, 0xFFFF, sum = 0
1618 00:58:37.568127 6, 0xFFFF, sum = 0
1619 00:58:37.571516 7, 0xFFFF, sum = 0
1620 00:58:37.571600 8, 0xFFFF, sum = 0
1621 00:58:37.575138 9, 0x0, sum = 1
1622 00:58:37.575221 10, 0x0, sum = 2
1623 00:58:37.578424 11, 0x0, sum = 3
1624 00:58:37.578508 12, 0x0, sum = 4
1625 00:58:37.581597 best_step = 10
1626 00:58:37.581687
1627 00:58:37.581757 ==
1628 00:58:37.584805 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 00:58:37.588602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 00:58:37.588686 ==
1631 00:58:37.588750 RX Vref Scan: 1
1632 00:58:37.588809
1633 00:58:37.591810 Set Vref Range= 32 -> 127
1634 00:58:37.591890
1635 00:58:37.594920 RX Vref 32 -> 127, step: 1
1636 00:58:37.595001
1637 00:58:37.598674 RX Delay -63 -> 252, step: 8
1638 00:58:37.598759
1639 00:58:37.601852 Set Vref, RX VrefLevel [Byte0]: 32
1640 00:58:37.604671 [Byte1]: 32
1641 00:58:37.604755
1642 00:58:37.608378 Set Vref, RX VrefLevel [Byte0]: 33
1643 00:58:37.611733 [Byte1]: 33
1644 00:58:37.611818
1645 00:58:37.614560 Set Vref, RX VrefLevel [Byte0]: 34
1646 00:58:37.618075 [Byte1]: 34
1647 00:58:37.621523
1648 00:58:37.621613 Set Vref, RX VrefLevel [Byte0]: 35
1649 00:58:37.624917 [Byte1]: 35
1650 00:58:37.629264
1651 00:58:37.629357 Set Vref, RX VrefLevel [Byte0]: 36
1652 00:58:37.632733 [Byte1]: 36
1653 00:58:37.636804
1654 00:58:37.636894 Set Vref, RX VrefLevel [Byte0]: 37
1655 00:58:37.640248 [Byte1]: 37
1656 00:58:37.644270
1657 00:58:37.644403 Set Vref, RX VrefLevel [Byte0]: 38
1658 00:58:37.647531 [Byte1]: 38
1659 00:58:37.651506
1660 00:58:37.651594 Set Vref, RX VrefLevel [Byte0]: 39
1661 00:58:37.655207 [Byte1]: 39
1662 00:58:37.659262
1663 00:58:37.659481 Set Vref, RX VrefLevel [Byte0]: 40
1664 00:58:37.662727 [Byte1]: 40
1665 00:58:37.666556
1666 00:58:37.666645 Set Vref, RX VrefLevel [Byte0]: 41
1667 00:58:37.669903 [Byte1]: 41
1668 00:58:37.674435
1669 00:58:37.674528 Set Vref, RX VrefLevel [Byte0]: 42
1670 00:58:37.677521 [Byte1]: 42
1671 00:58:37.682215
1672 00:58:37.682310 Set Vref, RX VrefLevel [Byte0]: 43
1673 00:58:37.685284 [Byte1]: 43
1674 00:58:37.689342
1675 00:58:37.689429 Set Vref, RX VrefLevel [Byte0]: 44
1676 00:58:37.692524 [Byte1]: 44
1677 00:58:37.697048
1678 00:58:37.697139 Set Vref, RX VrefLevel [Byte0]: 45
1679 00:58:37.700161 [Byte1]: 45
1680 00:58:37.704023
1681 00:58:37.704117 Set Vref, RX VrefLevel [Byte0]: 46
1682 00:58:37.707878 [Byte1]: 46
1683 00:58:37.711781
1684 00:58:37.711869 Set Vref, RX VrefLevel [Byte0]: 47
1685 00:58:37.714831 [Byte1]: 47
1686 00:58:37.719091
1687 00:58:37.719195 Set Vref, RX VrefLevel [Byte0]: 48
1688 00:58:37.722548 [Byte1]: 48
1689 00:58:37.726898
1690 00:58:37.726994 Set Vref, RX VrefLevel [Byte0]: 49
1691 00:58:37.729999 [Byte1]: 49
1692 00:58:37.734347
1693 00:58:37.734435 Set Vref, RX VrefLevel [Byte0]: 50
1694 00:58:37.737396 [Byte1]: 50
1695 00:58:37.741613
1696 00:58:37.741708 Set Vref, RX VrefLevel [Byte0]: 51
1697 00:58:37.745279 [Byte1]: 51
1698 00:58:37.749055
1699 00:58:37.749142 Set Vref, RX VrefLevel [Byte0]: 52
1700 00:58:37.752457 [Byte1]: 52
1701 00:58:37.756530
1702 00:58:37.756620 Set Vref, RX VrefLevel [Byte0]: 53
1703 00:58:37.760140 [Byte1]: 53
1704 00:58:37.764125
1705 00:58:37.764239 Set Vref, RX VrefLevel [Byte0]: 54
1706 00:58:37.767546 [Byte1]: 54
1707 00:58:37.771564
1708 00:58:37.771651 Set Vref, RX VrefLevel [Byte0]: 55
1709 00:58:37.775430 [Byte1]: 55
1710 00:58:37.778990
1711 00:58:37.779086 Set Vref, RX VrefLevel [Byte0]: 56
1712 00:58:37.782230 [Byte1]: 56
1713 00:58:37.787027
1714 00:58:37.787115 Set Vref, RX VrefLevel [Byte0]: 57
1715 00:58:37.790246 [Byte1]: 57
1716 00:58:37.793960
1717 00:58:37.794045 Set Vref, RX VrefLevel [Byte0]: 58
1718 00:58:37.797938 [Byte1]: 58
1719 00:58:37.801623
1720 00:58:37.801740 Set Vref, RX VrefLevel [Byte0]: 59
1721 00:58:37.804751 [Byte1]: 59
1722 00:58:37.809272
1723 00:58:37.809372 Set Vref, RX VrefLevel [Byte0]: 60
1724 00:58:37.812436 [Byte1]: 60
1725 00:58:37.816555
1726 00:58:37.816689 Set Vref, RX VrefLevel [Byte0]: 61
1727 00:58:37.820251 [Byte1]: 61
1728 00:58:37.824044
1729 00:58:37.824159 Set Vref, RX VrefLevel [Byte0]: 62
1730 00:58:37.827384 [Byte1]: 62
1731 00:58:37.831472
1732 00:58:37.831564 Set Vref, RX VrefLevel [Byte0]: 63
1733 00:58:37.835110 [Byte1]: 63
1734 00:58:37.838948
1735 00:58:37.839035 Set Vref, RX VrefLevel [Byte0]: 64
1736 00:58:37.842790 [Byte1]: 64
1737 00:58:37.846452
1738 00:58:37.846539 Set Vref, RX VrefLevel [Byte0]: 65
1739 00:58:37.850245 [Byte1]: 65
1740 00:58:37.854042
1741 00:58:37.854130 Set Vref, RX VrefLevel [Byte0]: 66
1742 00:58:37.857799 [Byte1]: 66
1743 00:58:37.861774
1744 00:58:37.861863 Set Vref, RX VrefLevel [Byte0]: 67
1745 00:58:37.864892 [Byte1]: 67
1746 00:58:37.869107
1747 00:58:37.869189 Set Vref, RX VrefLevel [Byte0]: 68
1748 00:58:37.872408 [Byte1]: 68
1749 00:58:37.876784
1750 00:58:37.876871 Set Vref, RX VrefLevel [Byte0]: 69
1751 00:58:37.879820 [Byte1]: 69
1752 00:58:37.883846
1753 00:58:37.883959 Set Vref, RX VrefLevel [Byte0]: 70
1754 00:58:37.887339 [Byte1]: 70
1755 00:58:37.892058
1756 00:58:37.892145 Set Vref, RX VrefLevel [Byte0]: 71
1757 00:58:37.894874 [Byte1]: 71
1758 00:58:37.898998
1759 00:58:37.899093 Final RX Vref Byte 0 = 56 to rank0
1760 00:58:37.902687 Final RX Vref Byte 1 = 54 to rank0
1761 00:58:37.905964 Final RX Vref Byte 0 = 56 to rank1
1762 00:58:37.909098 Final RX Vref Byte 1 = 54 to rank1==
1763 00:58:37.912656 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 00:58:37.919257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 00:58:37.919374 ==
1766 00:58:37.919439 DQS Delay:
1767 00:58:37.919498 DQS0 = 0, DQS1 = 0
1768 00:58:37.922402 DQM Delay:
1769 00:58:37.922486 DQM0 = 95, DQM1 = 90
1770 00:58:37.925502 DQ Delay:
1771 00:58:37.929365 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1772 00:58:37.932279 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =96
1773 00:58:37.936011 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1774 00:58:37.938946 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1775 00:58:37.939034
1776 00:58:37.939098
1777 00:58:37.945650 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1778 00:58:37.949330 CH1 RK0: MR19=606, MR18=2D49
1779 00:58:37.956132 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1780 00:58:37.956245
1781 00:58:37.959484 ----->DramcWriteLeveling(PI) begin...
1782 00:58:37.959570 ==
1783 00:58:37.962526 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 00:58:37.965868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 00:58:37.965955 ==
1786 00:58:37.969082 Write leveling (Byte 0): 25 => 25
1787 00:58:37.972926 Write leveling (Byte 1): 28 => 28
1788 00:58:37.975920 DramcWriteLeveling(PI) end<-----
1789 00:58:37.976004
1790 00:58:37.976066 ==
1791 00:58:37.979081 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 00:58:37.982911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 00:58:37.982997 ==
1794 00:58:37.985985 [Gating] SW mode calibration
1795 00:58:37.992746 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 00:58:37.999148 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 00:58:38.002451 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1798 00:58:38.005922 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 00:58:38.012845 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 00:58:38.016071 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 00:58:38.019257 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 00:58:38.026376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:58:38.029639 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:58:38.033274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:58:38.036420 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:58:38.042888 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:58:38.046425 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:58:38.049285 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:58:38.055935 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:58:38.059655 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:58:38.062880 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:58:38.069888 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:58:38.072949 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1814 00:58:38.076183 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1815 00:58:38.083304 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:58:38.086402 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:58:38.089927 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:58:38.096235 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:58:38.099332 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:58:38.102808 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:58:38.109638 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:58:38.112592 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1823 00:58:38.116237 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1824 00:58:38.122985 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 00:58:38.126226 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 00:58:38.129392 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 00:58:38.135959 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 00:58:38.139618 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 00:58:38.142741 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1830 00:58:38.145994 0 10 4 | B1->B0 | 2f2f 3030 | 1 0 | (1 1) (0 1)
1831 00:58:38.153164 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:58:38.156445 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 00:58:38.159283 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 00:58:38.166074 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 00:58:38.169127 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:58:38.173042 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:58:38.179418 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 00:58:38.182787 0 11 4 | B1->B0 | 3c3c 3231 | 0 1 | (0 0) (0 0)
1839 00:58:38.185815 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 00:58:38.192633 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 00:58:38.196111 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 00:58:38.199346 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 00:58:38.206074 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:58:38.209186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 00:58:38.212766 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 00:58:38.219239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1847 00:58:38.222501 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1848 00:58:38.225830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 00:58:38.232694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 00:58:38.236070 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:58:38.239303 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:58:38.242443 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:58:38.249329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:58:38.252410 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:58:38.256245 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:58:38.262699 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:58:38.265799 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:58:38.269458 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:58:38.275850 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:58:38.279320 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:58:38.282671 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:58:38.289053 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1863 00:58:38.292858 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 00:58:38.295985 Total UI for P1: 0, mck2ui 16
1865 00:58:38.299285 best dqsien dly found for B0: ( 0, 14, 4)
1866 00:58:38.302264 Total UI for P1: 0, mck2ui 16
1867 00:58:38.305875 best dqsien dly found for B1: ( 0, 14, 4)
1868 00:58:38.309330 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1869 00:58:38.312544 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1870 00:58:38.312637
1871 00:58:38.315791 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 00:58:38.319409 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 00:58:38.322559 [Gating] SW calibration Done
1874 00:58:38.322652 ==
1875 00:58:38.325758 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 00:58:38.328898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 00:58:38.332097 ==
1878 00:58:38.332193 RX Vref Scan: 0
1879 00:58:38.332304
1880 00:58:38.335568 RX Vref 0 -> 0, step: 1
1881 00:58:38.335655
1882 00:58:38.339013 RX Delay -130 -> 252, step: 16
1883 00:58:38.342386 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1884 00:58:38.345964 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1885 00:58:38.349092 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1886 00:58:38.352528 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1887 00:58:38.356239 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1888 00:58:38.362571 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1889 00:58:38.366129 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1890 00:58:38.369236 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1891 00:58:38.372490 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1892 00:58:38.376329 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1893 00:58:38.382797 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1894 00:58:38.386213 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1895 00:58:38.389168 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1896 00:58:38.392467 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1897 00:58:38.396227 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1898 00:58:38.402684 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1899 00:58:38.402786 ==
1900 00:58:38.405841 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 00:58:38.409746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 00:58:38.409838 ==
1903 00:58:38.409903 DQS Delay:
1904 00:58:38.412850 DQS0 = 0, DQS1 = 0
1905 00:58:38.412933 DQM Delay:
1906 00:58:38.416502 DQM0 = 92, DQM1 = 91
1907 00:58:38.416588 DQ Delay:
1908 00:58:38.419511 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1909 00:58:38.422876 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1910 00:58:38.425949 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1911 00:58:38.429282 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1912 00:58:38.429376
1913 00:58:38.429440
1914 00:58:38.429500 ==
1915 00:58:38.432504 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 00:58:38.439261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 00:58:38.439390 ==
1918 00:58:38.439457
1919 00:58:38.439516
1920 00:58:38.439573 TX Vref Scan disable
1921 00:58:38.443004 == TX Byte 0 ==
1922 00:58:38.445958 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1923 00:58:38.449483 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1924 00:58:38.452883 == TX Byte 1 ==
1925 00:58:38.456101 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1926 00:58:38.459261 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1927 00:58:38.462400 ==
1928 00:58:38.466212 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 00:58:38.469253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 00:58:38.469339 ==
1931 00:58:38.481801 TX Vref=22, minBit 5, minWin=26, winSum=443
1932 00:58:38.485573 TX Vref=24, minBit 1, minWin=26, winSum=442
1933 00:58:38.488697 TX Vref=26, minBit 0, minWin=27, winSum=446
1934 00:58:38.491669 TX Vref=28, minBit 0, minWin=27, winSum=450
1935 00:58:38.495023 TX Vref=30, minBit 2, minWin=27, winSum=453
1936 00:58:38.498705 TX Vref=32, minBit 0, minWin=27, winSum=449
1937 00:58:38.505054 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
1938 00:58:38.505143
1939 00:58:38.508760 Final TX Range 1 Vref 30
1940 00:58:38.508845
1941 00:58:38.508931 ==
1942 00:58:38.511953 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 00:58:38.515104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 00:58:38.515200 ==
1945 00:58:38.515271
1946 00:58:38.515330
1947 00:58:38.519150 TX Vref Scan disable
1948 00:58:38.522300 == TX Byte 0 ==
1949 00:58:38.525553 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1950 00:58:38.528659 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1951 00:58:38.532214 == TX Byte 1 ==
1952 00:58:38.535623 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 00:58:38.538837 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 00:58:38.538919
1955 00:58:38.542320 [DATLAT]
1956 00:58:38.542421 Freq=800, CH1 RK1
1957 00:58:38.542487
1958 00:58:38.545405 DATLAT Default: 0xa
1959 00:58:38.545486 0, 0xFFFF, sum = 0
1960 00:58:38.549110 1, 0xFFFF, sum = 0
1961 00:58:38.549193 2, 0xFFFF, sum = 0
1962 00:58:38.552502 3, 0xFFFF, sum = 0
1963 00:58:38.552585 4, 0xFFFF, sum = 0
1964 00:58:38.555709 5, 0xFFFF, sum = 0
1965 00:58:38.555791 6, 0xFFFF, sum = 0
1966 00:58:38.558955 7, 0xFFFF, sum = 0
1967 00:58:38.559038 8, 0xFFFF, sum = 0
1968 00:58:38.562253 9, 0x0, sum = 1
1969 00:58:38.562335 10, 0x0, sum = 2
1970 00:58:38.566055 11, 0x0, sum = 3
1971 00:58:38.566136 12, 0x0, sum = 4
1972 00:58:38.568843 best_step = 10
1973 00:58:38.568924
1974 00:58:38.568987 ==
1975 00:58:38.572241 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 00:58:38.575695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 00:58:38.575776 ==
1978 00:58:38.579316 RX Vref Scan: 0
1979 00:58:38.579397
1980 00:58:38.579460 RX Vref 0 -> 0, step: 1
1981 00:58:38.579520
1982 00:58:38.582586 RX Delay -79 -> 252, step: 8
1983 00:58:38.585735 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1984 00:58:38.592224 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1985 00:58:38.595904 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1986 00:58:38.599032 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1987 00:58:38.602417 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1988 00:58:38.605835 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1989 00:58:38.608893 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1990 00:58:38.615432 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1991 00:58:38.619337 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1992 00:58:38.622644 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1993 00:58:38.625932 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1994 00:58:38.629171 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1995 00:58:38.635767 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1996 00:58:38.638868 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1997 00:58:38.642631 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1998 00:58:38.645569 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1999 00:58:38.645651 ==
2000 00:58:38.649017 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 00:58:38.652260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 00:58:38.655403 ==
2003 00:58:38.655485 DQS Delay:
2004 00:58:38.655549 DQS0 = 0, DQS1 = 0
2005 00:58:38.659047 DQM Delay:
2006 00:58:38.659128 DQM0 = 97, DQM1 = 91
2007 00:58:38.662369 DQ Delay:
2008 00:58:38.666277 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2009 00:58:38.666358 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2010 00:58:38.669405 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2011 00:58:38.676158 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2012 00:58:38.676246
2013 00:58:38.676360
2014 00:58:38.682378 [DQSOSCAuto] RK1, (LSB)MR18= 0x460f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2015 00:58:38.685744 CH1 RK1: MR19=606, MR18=460F
2016 00:58:38.692910 CH1_RK1: MR19=0x606, MR18=0x460F, DQSOSC=392, MR23=63, INC=96, DEC=64
2017 00:58:38.695928 [RxdqsGatingPostProcess] freq 800
2018 00:58:38.699461 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 00:58:38.702890 Pre-setting of DQS Precalculation
2020 00:58:38.709294 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 00:58:38.716149 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 00:58:38.723052 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 00:58:38.723152
2024 00:58:38.723229
2025 00:58:38.726045 [Calibration Summary] 1600 Mbps
2026 00:58:38.726127 CH 0, Rank 0
2027 00:58:38.729294 SW Impedance : PASS
2028 00:58:38.729375 DUTY Scan : NO K
2029 00:58:38.732510 ZQ Calibration : PASS
2030 00:58:38.736459 Jitter Meter : NO K
2031 00:58:38.736540 CBT Training : PASS
2032 00:58:38.739569 Write leveling : PASS
2033 00:58:38.742717 RX DQS gating : PASS
2034 00:58:38.742799 RX DQ/DQS(RDDQC) : PASS
2035 00:58:38.746016 TX DQ/DQS : PASS
2036 00:58:38.749197 RX DATLAT : PASS
2037 00:58:38.749277 RX DQ/DQS(Engine): PASS
2038 00:58:38.753068 TX OE : NO K
2039 00:58:38.753158 All Pass.
2040 00:58:38.753222
2041 00:58:38.756111 CH 0, Rank 1
2042 00:58:38.756191 SW Impedance : PASS
2043 00:58:38.759338 DUTY Scan : NO K
2044 00:58:38.762603 ZQ Calibration : PASS
2045 00:58:38.762684 Jitter Meter : NO K
2046 00:58:38.766188 CBT Training : PASS
2047 00:58:38.769670 Write leveling : PASS
2048 00:58:38.769751 RX DQS gating : PASS
2049 00:58:38.772501 RX DQ/DQS(RDDQC) : PASS
2050 00:58:38.772582 TX DQ/DQS : PASS
2051 00:58:38.775757 RX DATLAT : PASS
2052 00:58:38.779111 RX DQ/DQS(Engine): PASS
2053 00:58:38.779193 TX OE : NO K
2054 00:58:38.782957 All Pass.
2055 00:58:38.783038
2056 00:58:38.783101 CH 1, Rank 0
2057 00:58:38.786235 SW Impedance : PASS
2058 00:58:38.786316 DUTY Scan : NO K
2059 00:58:38.789255 ZQ Calibration : PASS
2060 00:58:38.792908 Jitter Meter : NO K
2061 00:58:38.792988 CBT Training : PASS
2062 00:58:38.796225 Write leveling : PASS
2063 00:58:38.799112 RX DQS gating : PASS
2064 00:58:38.799209 RX DQ/DQS(RDDQC) : PASS
2065 00:58:38.802528 TX DQ/DQS : PASS
2066 00:58:38.805670 RX DATLAT : PASS
2067 00:58:38.805750 RX DQ/DQS(Engine): PASS
2068 00:58:38.809410 TX OE : NO K
2069 00:58:38.809492 All Pass.
2070 00:58:38.809555
2071 00:58:38.812511 CH 1, Rank 1
2072 00:58:38.812592 SW Impedance : PASS
2073 00:58:38.815801 DUTY Scan : NO K
2074 00:58:38.819095 ZQ Calibration : PASS
2075 00:58:38.819180 Jitter Meter : NO K
2076 00:58:38.822965 CBT Training : PASS
2077 00:58:38.823047 Write leveling : PASS
2078 00:58:38.826237 RX DQS gating : PASS
2079 00:58:38.829508 RX DQ/DQS(RDDQC) : PASS
2080 00:58:38.829590 TX DQ/DQS : PASS
2081 00:58:38.832505 RX DATLAT : PASS
2082 00:58:38.836120 RX DQ/DQS(Engine): PASS
2083 00:58:38.836200 TX OE : NO K
2084 00:58:38.839376 All Pass.
2085 00:58:38.839456
2086 00:58:38.839519 DramC Write-DBI off
2087 00:58:38.842666 PER_BANK_REFRESH: Hybrid Mode
2088 00:58:38.842747 TX_TRACKING: ON
2089 00:58:38.845818 [GetDramInforAfterCalByMRR] Vendor 6.
2090 00:58:38.852954 [GetDramInforAfterCalByMRR] Revision 606.
2091 00:58:38.856130 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 00:58:38.856263 MR0 0x3b3b
2093 00:58:38.856360 MR8 0x5151
2094 00:58:38.859853 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 00:58:38.859934
2096 00:58:38.862859 MR0 0x3b3b
2097 00:58:38.862940 MR8 0x5151
2098 00:58:38.866162 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 00:58:38.866244
2100 00:58:38.876323 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 00:58:38.879467 [FAST_K] Save calibration result to emmc
2102 00:58:38.882999 [FAST_K] Save calibration result to emmc
2103 00:58:38.886559 dram_init: config_dvfs: 1
2104 00:58:38.889892 dramc_set_vcore_voltage set vcore to 662500
2105 00:58:38.892832 Read voltage for 1200, 2
2106 00:58:38.892912 Vio18 = 0
2107 00:58:38.892975 Vcore = 662500
2108 00:58:38.896617 Vdram = 0
2109 00:58:38.896698 Vddq = 0
2110 00:58:38.896761 Vmddr = 0
2111 00:58:38.903475 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 00:58:38.906426 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 00:58:38.909799 MEM_TYPE=3, freq_sel=15
2114 00:58:38.913098 sv_algorithm_assistance_LP4_1600
2115 00:58:38.916642 ============ PULL DRAM RESETB DOWN ============
2116 00:58:38.919829 ========== PULL DRAM RESETB DOWN end =========
2117 00:58:38.926456 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 00:58:38.929585 ===================================
2119 00:58:38.929670 LPDDR4 DRAM CONFIGURATION
2120 00:58:38.933085 ===================================
2121 00:58:38.936407 EX_ROW_EN[0] = 0x0
2122 00:58:38.936489 EX_ROW_EN[1] = 0x0
2123 00:58:38.939765 LP4Y_EN = 0x0
2124 00:58:38.939846 WORK_FSP = 0x0
2125 00:58:38.942911 WL = 0x4
2126 00:58:38.946129 RL = 0x4
2127 00:58:38.946210 BL = 0x2
2128 00:58:38.949641 RPST = 0x0
2129 00:58:38.949722 RD_PRE = 0x0
2130 00:58:38.952799 WR_PRE = 0x1
2131 00:58:38.952880 WR_PST = 0x0
2132 00:58:38.956638 DBI_WR = 0x0
2133 00:58:38.956719 DBI_RD = 0x0
2134 00:58:38.959830 OTF = 0x1
2135 00:58:38.962990 ===================================
2136 00:58:38.966630 ===================================
2137 00:58:38.966712 ANA top config
2138 00:58:38.969751 ===================================
2139 00:58:38.972945 DLL_ASYNC_EN = 0
2140 00:58:38.976116 ALL_SLAVE_EN = 0
2141 00:58:38.976196 NEW_RANK_MODE = 1
2142 00:58:38.979904 DLL_IDLE_MODE = 1
2143 00:58:38.983046 LP45_APHY_COMB_EN = 1
2144 00:58:38.986215 TX_ODT_DIS = 1
2145 00:58:38.986296 NEW_8X_MODE = 1
2146 00:58:38.989284 ===================================
2147 00:58:38.993010 ===================================
2148 00:58:38.995925 data_rate = 2400
2149 00:58:38.999368 CKR = 1
2150 00:58:39.002660 DQ_P2S_RATIO = 8
2151 00:58:39.006304 ===================================
2152 00:58:39.009609 CA_P2S_RATIO = 8
2153 00:58:39.012778 DQ_CA_OPEN = 0
2154 00:58:39.012891 DQ_SEMI_OPEN = 0
2155 00:58:39.016327 CA_SEMI_OPEN = 0
2156 00:58:39.019287 CA_FULL_RATE = 0
2157 00:58:39.022804 DQ_CKDIV4_EN = 0
2158 00:58:39.026042 CA_CKDIV4_EN = 0
2159 00:58:39.029286 CA_PREDIV_EN = 0
2160 00:58:39.029372 PH8_DLY = 17
2161 00:58:39.032682 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 00:58:39.036435 DQ_AAMCK_DIV = 4
2163 00:58:39.039487 CA_AAMCK_DIV = 4
2164 00:58:39.042813 CA_ADMCK_DIV = 4
2165 00:58:39.046094 DQ_TRACK_CA_EN = 0
2166 00:58:39.049701 CA_PICK = 1200
2167 00:58:39.049784 CA_MCKIO = 1200
2168 00:58:39.052836 MCKIO_SEMI = 0
2169 00:58:39.056317 PLL_FREQ = 2366
2170 00:58:39.059672 DQ_UI_PI_RATIO = 32
2171 00:58:39.062866 CA_UI_PI_RATIO = 0
2172 00:58:39.066190 ===================================
2173 00:58:39.069179 ===================================
2174 00:58:39.073053 memory_type:LPDDR4
2175 00:58:39.073134 GP_NUM : 10
2176 00:58:39.076200 SRAM_EN : 1
2177 00:58:39.076282 MD32_EN : 0
2178 00:58:39.079317 ===================================
2179 00:58:39.083181 [ANA_INIT] >>>>>>>>>>>>>>
2180 00:58:39.086233 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 00:58:39.089412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 00:58:39.092651 ===================================
2183 00:58:39.095990 data_rate = 2400,PCW = 0X5b00
2184 00:58:39.099816 ===================================
2185 00:58:39.103377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 00:58:39.106092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 00:58:39.113034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 00:58:39.116273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 00:58:39.119429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 00:58:39.123229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 00:58:39.126441 [ANA_INIT] flow start
2192 00:58:39.129570 [ANA_INIT] PLL >>>>>>>>
2193 00:58:39.129654 [ANA_INIT] PLL <<<<<<<<
2194 00:58:39.132770 [ANA_INIT] MIDPI >>>>>>>>
2195 00:58:39.136144 [ANA_INIT] MIDPI <<<<<<<<
2196 00:58:39.139461 [ANA_INIT] DLL >>>>>>>>
2197 00:58:39.139544 [ANA_INIT] DLL <<<<<<<<
2198 00:58:39.143039 [ANA_INIT] flow end
2199 00:58:39.146369 ============ LP4 DIFF to SE enter ============
2200 00:58:39.149497 ============ LP4 DIFF to SE exit ============
2201 00:58:39.153026 [ANA_INIT] <<<<<<<<<<<<<
2202 00:58:39.156247 [Flow] Enable top DCM control >>>>>
2203 00:58:39.159360 [Flow] Enable top DCM control <<<<<
2204 00:58:39.163083 Enable DLL master slave shuffle
2205 00:58:39.169669 ==============================================================
2206 00:58:39.169757 Gating Mode config
2207 00:58:39.176056 ==============================================================
2208 00:58:39.176144 Config description:
2209 00:58:39.186385 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 00:58:39.193155 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 00:58:39.199520 SELPH_MODE 0: By rank 1: By Phase
2212 00:58:39.202791 ==============================================================
2213 00:58:39.206716 GAT_TRACK_EN = 1
2214 00:58:39.209976 RX_GATING_MODE = 2
2215 00:58:39.213212 RX_GATING_TRACK_MODE = 2
2216 00:58:39.216433 SELPH_MODE = 1
2217 00:58:39.219979 PICG_EARLY_EN = 1
2218 00:58:39.222890 VALID_LAT_VALUE = 1
2219 00:58:39.226320 ==============================================================
2220 00:58:39.229757 Enter into Gating configuration >>>>
2221 00:58:39.233180 Exit from Gating configuration <<<<
2222 00:58:39.236443 Enter into DVFS_PRE_config >>>>>
2223 00:58:39.249985 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 00:58:39.250097 Exit from DVFS_PRE_config <<<<<
2225 00:58:39.252999 Enter into PICG configuration >>>>
2226 00:58:39.256560 Exit from PICG configuration <<<<
2227 00:58:39.259893 [RX_INPUT] configuration >>>>>
2228 00:58:39.262976 [RX_INPUT] configuration <<<<<
2229 00:58:39.270131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 00:58:39.273208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 00:58:39.280113 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 00:58:39.286425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 00:58:39.293383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 00:58:39.299737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 00:58:39.303411 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 00:58:39.306451 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 00:58:39.309982 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 00:58:39.316849 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 00:58:39.320050 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 00:58:39.323285 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 00:58:39.326445 ===================================
2242 00:58:39.330199 LPDDR4 DRAM CONFIGURATION
2243 00:58:39.333353 ===================================
2244 00:58:39.333453 EX_ROW_EN[0] = 0x0
2245 00:58:39.336477 EX_ROW_EN[1] = 0x0
2246 00:58:39.336563 LP4Y_EN = 0x0
2247 00:58:39.339927 WORK_FSP = 0x0
2248 00:58:39.340014 WL = 0x4
2249 00:58:39.343087 RL = 0x4
2250 00:58:39.343171 BL = 0x2
2251 00:58:39.346847 RPST = 0x0
2252 00:58:39.346988 RD_PRE = 0x0
2253 00:58:39.350145 WR_PRE = 0x1
2254 00:58:39.353228 WR_PST = 0x0
2255 00:58:39.353325 DBI_WR = 0x0
2256 00:58:39.356742 DBI_RD = 0x0
2257 00:58:39.356838 OTF = 0x1
2258 00:58:39.359852 ===================================
2259 00:58:39.363611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 00:58:39.366784 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 00:58:39.373422 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 00:58:39.376822 ===================================
2263 00:58:39.376927 LPDDR4 DRAM CONFIGURATION
2264 00:58:39.380107 ===================================
2265 00:58:39.383646 EX_ROW_EN[0] = 0x10
2266 00:58:39.386855 EX_ROW_EN[1] = 0x0
2267 00:58:39.386988 LP4Y_EN = 0x0
2268 00:58:39.390065 WORK_FSP = 0x0
2269 00:58:39.390156 WL = 0x4
2270 00:58:39.393843 RL = 0x4
2271 00:58:39.393937 BL = 0x2
2272 00:58:39.396999 RPST = 0x0
2273 00:58:39.397100 RD_PRE = 0x0
2274 00:58:39.400366 WR_PRE = 0x1
2275 00:58:39.400458 WR_PST = 0x0
2276 00:58:39.403995 DBI_WR = 0x0
2277 00:58:39.404083 DBI_RD = 0x0
2278 00:58:39.407542 OTF = 0x1
2279 00:58:39.410243 ===================================
2280 00:58:39.417493 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 00:58:39.417585 ==
2282 00:58:39.420418 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 00:58:39.423922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 00:58:39.424007 ==
2285 00:58:39.427149 [Duty_Offset_Calibration]
2286 00:58:39.427226 B0:2 B1:1 CA:1
2287 00:58:39.427289
2288 00:58:39.430522 [DutyScan_Calibration_Flow] k_type=0
2289 00:58:39.440493
2290 00:58:39.440583 ==CLK 0==
2291 00:58:39.443690 Final CLK duty delay cell = 0
2292 00:58:39.447250 [0] MAX Duty = 5187%(X100), DQS PI = 24
2293 00:58:39.450333 [0] MIN Duty = 4844%(X100), DQS PI = 48
2294 00:58:39.450409 [0] AVG Duty = 5015%(X100)
2295 00:58:39.453662
2296 00:58:39.456940 CH0 CLK Duty spec in!! Max-Min= 343%
2297 00:58:39.460259 [DutyScan_Calibration_Flow] ====Done====
2298 00:58:39.460351
2299 00:58:39.463977 [DutyScan_Calibration_Flow] k_type=1
2300 00:58:39.478366
2301 00:58:39.478482 ==DQS 0 ==
2302 00:58:39.481347 Final DQS duty delay cell = -4
2303 00:58:39.485082 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2304 00:58:39.488499 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2305 00:58:39.491374 [-4] AVG Duty = 4937%(X100)
2306 00:58:39.491452
2307 00:58:39.491511 ==DQS 1 ==
2308 00:58:39.494837 Final DQS duty delay cell = -4
2309 00:58:39.498414 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2310 00:58:39.501618 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2311 00:58:39.505355 [-4] AVG Duty = 4922%(X100)
2312 00:58:39.505435
2313 00:58:39.508463 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2314 00:58:39.508539
2315 00:58:39.511730 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2316 00:58:39.514877 [DutyScan_Calibration_Flow] ====Done====
2317 00:58:39.514950
2318 00:58:39.518002 [DutyScan_Calibration_Flow] k_type=3
2319 00:58:39.535473
2320 00:58:39.535614 ==DQM 0 ==
2321 00:58:39.539042 Final DQM duty delay cell = 0
2322 00:58:39.542266 [0] MAX Duty = 5156%(X100), DQS PI = 30
2323 00:58:39.545461 [0] MIN Duty = 4938%(X100), DQS PI = 0
2324 00:58:39.545537 [0] AVG Duty = 5047%(X100)
2325 00:58:39.548732
2326 00:58:39.548811 ==DQM 1 ==
2327 00:58:39.551911 Final DQM duty delay cell = 0
2328 00:58:39.555168 [0] MAX Duty = 5093%(X100), DQS PI = 0
2329 00:58:39.558431 [0] MIN Duty = 5031%(X100), DQS PI = 18
2330 00:58:39.561986 [0] AVG Duty = 5062%(X100)
2331 00:58:39.562064
2332 00:58:39.565403 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2333 00:58:39.565476
2334 00:58:39.568239 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2335 00:58:39.571881 [DutyScan_Calibration_Flow] ====Done====
2336 00:58:39.571959
2337 00:58:39.575202 [DutyScan_Calibration_Flow] k_type=2
2338 00:58:39.591654
2339 00:58:39.591767 ==DQ 0 ==
2340 00:58:39.595017 Final DQ duty delay cell = 0
2341 00:58:39.598900 [0] MAX Duty = 5031%(X100), DQS PI = 26
2342 00:58:39.601721 [0] MIN Duty = 4875%(X100), DQS PI = 62
2343 00:58:39.601798 [0] AVG Duty = 4953%(X100)
2344 00:58:39.605201
2345 00:58:39.605277 ==DQ 1 ==
2346 00:58:39.608719 Final DQ duty delay cell = 0
2347 00:58:39.612195 [0] MAX Duty = 5093%(X100), DQS PI = 24
2348 00:58:39.615390 [0] MIN Duty = 4938%(X100), DQS PI = 36
2349 00:58:39.615466 [0] AVG Duty = 5015%(X100)
2350 00:58:39.615528
2351 00:58:39.618608 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2352 00:58:39.621773
2353 00:58:39.625508 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2354 00:58:39.628587 [DutyScan_Calibration_Flow] ====Done====
2355 00:58:39.628668 ==
2356 00:58:39.632390 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 00:58:39.635525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 00:58:39.635600 ==
2359 00:58:39.638669 [Duty_Offset_Calibration]
2360 00:58:39.638742 B0:1 B1:0 CA:0
2361 00:58:39.638803
2362 00:58:39.641968 [DutyScan_Calibration_Flow] k_type=0
2363 00:58:39.651035
2364 00:58:39.651119 ==CLK 0==
2365 00:58:39.654295 Final CLK duty delay cell = -4
2366 00:58:39.657620 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2367 00:58:39.660902 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2368 00:58:39.664755 [-4] AVG Duty = 4953%(X100)
2369 00:58:39.664832
2370 00:58:39.667895 CH1 CLK Duty spec in!! Max-Min= 93%
2371 00:58:39.671112 [DutyScan_Calibration_Flow] ====Done====
2372 00:58:39.671180
2373 00:58:39.674624 [DutyScan_Calibration_Flow] k_type=1
2374 00:58:39.690622
2375 00:58:39.690755 ==DQS 0 ==
2376 00:58:39.694003 Final DQS duty delay cell = 0
2377 00:58:39.697491 [0] MAX Duty = 5094%(X100), DQS PI = 26
2378 00:58:39.700713 [0] MIN Duty = 4875%(X100), DQS PI = 0
2379 00:58:39.700808 [0] AVG Duty = 4984%(X100)
2380 00:58:39.703855
2381 00:58:39.703959 ==DQS 1 ==
2382 00:58:39.707537 Final DQS duty delay cell = 0
2383 00:58:39.710611 [0] MAX Duty = 5218%(X100), DQS PI = 20
2384 00:58:39.714215 [0] MIN Duty = 4969%(X100), DQS PI = 10
2385 00:58:39.717455 [0] AVG Duty = 5093%(X100)
2386 00:58:39.717542
2387 00:58:39.720468 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2388 00:58:39.720553
2389 00:58:39.724169 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2390 00:58:39.727316 [DutyScan_Calibration_Flow] ====Done====
2391 00:58:39.727401
2392 00:58:39.730230 [DutyScan_Calibration_Flow] k_type=3
2393 00:58:39.747576
2394 00:58:39.747696 ==DQM 0 ==
2395 00:58:39.750809 Final DQM duty delay cell = 0
2396 00:58:39.754284 [0] MAX Duty = 5187%(X100), DQS PI = 8
2397 00:58:39.757560 [0] MIN Duty = 5031%(X100), DQS PI = 0
2398 00:58:39.757653 [0] AVG Duty = 5109%(X100)
2399 00:58:39.757736
2400 00:58:39.760833 ==DQM 1 ==
2401 00:58:39.764084 Final DQM duty delay cell = 0
2402 00:58:39.767173 [0] MAX Duty = 5031%(X100), DQS PI = 16
2403 00:58:39.771000 [0] MIN Duty = 4907%(X100), DQS PI = 34
2404 00:58:39.771075 [0] AVG Duty = 4969%(X100)
2405 00:58:39.771146
2406 00:58:39.777424 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2407 00:58:39.777509
2408 00:58:39.780657 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2409 00:58:39.784430 [DutyScan_Calibration_Flow] ====Done====
2410 00:58:39.784508
2411 00:58:39.787597 [DutyScan_Calibration_Flow] k_type=2
2412 00:58:39.803270
2413 00:58:39.803387 ==DQ 0 ==
2414 00:58:39.806303 Final DQ duty delay cell = -4
2415 00:58:39.809895 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2416 00:58:39.813155 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2417 00:58:39.816743 [-4] AVG Duty = 5000%(X100)
2418 00:58:39.816843
2419 00:58:39.816931 ==DQ 1 ==
2420 00:58:39.819947 Final DQ duty delay cell = 0
2421 00:58:39.823220 [0] MAX Duty = 5125%(X100), DQS PI = 20
2422 00:58:39.826402 [0] MIN Duty = 4969%(X100), DQS PI = 10
2423 00:58:39.826487 [0] AVG Duty = 5047%(X100)
2424 00:58:39.829979
2425 00:58:39.833525 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2426 00:58:39.833607
2427 00:58:39.836385 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2428 00:58:39.840325 [DutyScan_Calibration_Flow] ====Done====
2429 00:58:39.843644 nWR fixed to 30
2430 00:58:39.843767 [ModeRegInit_LP4] CH0 RK0
2431 00:58:39.846880 [ModeRegInit_LP4] CH0 RK1
2432 00:58:39.850053 [ModeRegInit_LP4] CH1 RK0
2433 00:58:39.850133 [ModeRegInit_LP4] CH1 RK1
2434 00:58:39.853358 match AC timing 7
2435 00:58:39.856600 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 00:58:39.859793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 00:58:39.866554 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 00:58:39.870018 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 00:58:39.876643 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 00:58:39.876755 ==
2441 00:58:39.879754 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 00:58:39.883562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 00:58:39.883645 ==
2444 00:58:39.889861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 00:58:39.893144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 00:58:39.903152 [CA 0] Center 39 (8~70) winsize 63
2447 00:58:39.906806 [CA 1] Center 39 (8~70) winsize 63
2448 00:58:39.909838 [CA 2] Center 35 (5~66) winsize 62
2449 00:58:39.913572 [CA 3] Center 34 (4~65) winsize 62
2450 00:58:39.916751 [CA 4] Center 33 (3~64) winsize 62
2451 00:58:39.919991 [CA 5] Center 32 (3~62) winsize 60
2452 00:58:39.920072
2453 00:58:39.923301 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2454 00:58:39.923384
2455 00:58:39.927071 [CATrainingPosCal] consider 1 rank data
2456 00:58:39.930067 u2DelayCellTimex100 = 270/100 ps
2457 00:58:39.933544 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 00:58:39.936938 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 00:58:39.943249 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2460 00:58:39.946706 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2461 00:58:39.950125 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2462 00:58:39.953714 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2463 00:58:39.953789
2464 00:58:39.957153 CA PerBit enable=1, Macro0, CA PI delay=32
2465 00:58:39.957224
2466 00:58:39.960305 [CBTSetCACLKResult] CA Dly = 32
2467 00:58:39.960398 CS Dly: 6 (0~37)
2468 00:58:39.960462 ==
2469 00:58:39.963386 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 00:58:39.970403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 00:58:39.970507 ==
2472 00:58:39.973475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 00:58:39.979818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 00:58:39.989158 [CA 0] Center 38 (8~69) winsize 62
2475 00:58:39.992209 [CA 1] Center 38 (8~69) winsize 62
2476 00:58:39.996148 [CA 2] Center 35 (4~66) winsize 63
2477 00:58:39.998852 [CA 3] Center 34 (4~65) winsize 62
2478 00:58:40.002513 [CA 4] Center 33 (3~64) winsize 62
2479 00:58:40.005539 [CA 5] Center 32 (3~62) winsize 60
2480 00:58:40.005618
2481 00:58:40.009352 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 00:58:40.009432
2483 00:58:40.012440 [CATrainingPosCal] consider 2 rank data
2484 00:58:40.015866 u2DelayCellTimex100 = 270/100 ps
2485 00:58:40.019381 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 00:58:40.022614 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 00:58:40.028907 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 00:58:40.032731 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 00:58:40.035802 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 00:58:40.038882 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 00:58:40.038962
2492 00:58:40.042409 CA PerBit enable=1, Macro0, CA PI delay=32
2493 00:58:40.042489
2494 00:58:40.045449 [CBTSetCACLKResult] CA Dly = 32
2495 00:58:40.045529 CS Dly: 7 (0~39)
2496 00:58:40.045611
2497 00:58:40.048923 ----->DramcWriteLeveling(PI) begin...
2498 00:58:40.052562 ==
2499 00:58:40.052638 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 00:58:40.059256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 00:58:40.059332 ==
2502 00:58:40.062405 Write leveling (Byte 0): 33 => 33
2503 00:58:40.065840 Write leveling (Byte 1): 31 => 31
2504 00:58:40.065910 DramcWriteLeveling(PI) end<-----
2505 00:58:40.069097
2506 00:58:40.069168 ==
2507 00:58:40.072378 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 00:58:40.076121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 00:58:40.076225 ==
2510 00:58:40.079156 [Gating] SW mode calibration
2511 00:58:40.086223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 00:58:40.089828 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 00:58:40.095623 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2514 00:58:40.099429 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2515 00:58:40.102520 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 00:58:40.109388 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 00:58:40.112477 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 00:58:40.115723 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 00:58:40.122650 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2520 00:58:40.125658 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
2521 00:58:40.129168 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2522 00:58:40.136078 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 00:58:40.139197 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 00:58:40.142887 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 00:58:40.148908 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 00:58:40.152521 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 00:58:40.155796 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2528 00:58:40.159502 1 0 28 | B1->B0 | 2e2e 4545 | 1 0 | (0 0) (0 0)
2529 00:58:40.166314 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2530 00:58:40.169425 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 00:58:40.172683 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 00:58:40.179411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 00:58:40.182892 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 00:58:40.186031 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 00:58:40.192415 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 00:58:40.196072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2537 00:58:40.199374 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2538 00:58:40.205791 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 00:58:40.209363 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 00:58:40.212545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:58:40.219091 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:58:40.222319 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:58:40.226214 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:58:40.232504 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:58:40.236101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:58:40.238991 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:58:40.245916 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:58:40.249164 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:58:40.252988 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:58:40.255938 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:58:40.262632 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:58:40.265751 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 00:58:40.269302 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2554 00:58:40.272878 Total UI for P1: 0, mck2ui 16
2555 00:58:40.275999 best dqsien dly found for B0: ( 1, 3, 28)
2556 00:58:40.283112 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 00:58:40.283199 Total UI for P1: 0, mck2ui 16
2558 00:58:40.289810 best dqsien dly found for B1: ( 1, 4, 0)
2559 00:58:40.293381 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2560 00:58:40.296496 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 00:58:40.296579
2562 00:58:40.299782 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2563 00:58:40.303137 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 00:58:40.306296 [Gating] SW calibration Done
2565 00:58:40.306378 ==
2566 00:58:40.309487 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 00:58:40.313195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 00:58:40.313277 ==
2569 00:58:40.316605 RX Vref Scan: 0
2570 00:58:40.316710
2571 00:58:40.316804 RX Vref 0 -> 0, step: 1
2572 00:58:40.316918
2573 00:58:40.319649 RX Delay -40 -> 252, step: 8
2574 00:58:40.323223 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2575 00:58:40.326366 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2576 00:58:40.333312 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 00:58:40.336647 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2578 00:58:40.339659 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 00:58:40.343292 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2580 00:58:40.346250 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2581 00:58:40.353347 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 00:58:40.356607 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2583 00:58:40.359849 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2584 00:58:40.362971 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2585 00:58:40.366488 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2586 00:58:40.373309 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2587 00:58:40.376480 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2588 00:58:40.379639 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2589 00:58:40.382884 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2590 00:58:40.382959 ==
2591 00:58:40.386700 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 00:58:40.393142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 00:58:40.393231 ==
2594 00:58:40.393296 DQS Delay:
2595 00:58:40.393355 DQS0 = 0, DQS1 = 0
2596 00:58:40.396260 DQM Delay:
2597 00:58:40.396353 DQM0 = 121, DQM1 = 113
2598 00:58:40.400005 DQ Delay:
2599 00:58:40.403109 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2600 00:58:40.406488 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2601 00:58:40.410096 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2602 00:58:40.413057 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2603 00:58:40.413145
2604 00:58:40.413211
2605 00:58:40.413270 ==
2606 00:58:40.416903 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 00:58:40.419960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 00:58:40.420036 ==
2609 00:58:40.420098
2610 00:58:40.423111
2611 00:58:40.423229 TX Vref Scan disable
2612 00:58:40.426755 == TX Byte 0 ==
2613 00:58:40.429854 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2614 00:58:40.433370 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2615 00:58:40.436675 == TX Byte 1 ==
2616 00:58:40.439900 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2617 00:58:40.443474 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2618 00:58:40.443560 ==
2619 00:58:40.446565 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 00:58:40.453337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 00:58:40.453430 ==
2622 00:58:40.463380 TX Vref=22, minBit 0, minWin=25, winSum=411
2623 00:58:40.467131 TX Vref=24, minBit 0, minWin=25, winSum=413
2624 00:58:40.470292 TX Vref=26, minBit 4, minWin=25, winSum=417
2625 00:58:40.473903 TX Vref=28, minBit 10, minWin=25, winSum=421
2626 00:58:40.476927 TX Vref=30, minBit 0, minWin=26, winSum=426
2627 00:58:40.483767 TX Vref=32, minBit 13, minWin=25, winSum=425
2628 00:58:40.486834 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2629 00:58:40.486910
2630 00:58:40.490014 Final TX Range 1 Vref 30
2631 00:58:40.490088
2632 00:58:40.490155 ==
2633 00:58:40.493829 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 00:58:40.497024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 00:58:40.497106 ==
2636 00:58:40.500241
2637 00:58:40.500341
2638 00:58:40.500402 TX Vref Scan disable
2639 00:58:40.503241 == TX Byte 0 ==
2640 00:58:40.507139 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2641 00:58:40.510329 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2642 00:58:40.513536 == TX Byte 1 ==
2643 00:58:40.517282 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2644 00:58:40.520085 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2645 00:58:40.520168
2646 00:58:40.523710 [DATLAT]
2647 00:58:40.523801 Freq=1200, CH0 RK0
2648 00:58:40.523874
2649 00:58:40.526960 DATLAT Default: 0xd
2650 00:58:40.527035 0, 0xFFFF, sum = 0
2651 00:58:40.530119 1, 0xFFFF, sum = 0
2652 00:58:40.530193 2, 0xFFFF, sum = 0
2653 00:58:40.533829 3, 0xFFFF, sum = 0
2654 00:58:40.533914 4, 0xFFFF, sum = 0
2655 00:58:40.536860 5, 0xFFFF, sum = 0
2656 00:58:40.536939 6, 0xFFFF, sum = 0
2657 00:58:40.540622 7, 0xFFFF, sum = 0
2658 00:58:40.540693 8, 0xFFFF, sum = 0
2659 00:58:40.543655 9, 0xFFFF, sum = 0
2660 00:58:40.546953 10, 0xFFFF, sum = 0
2661 00:58:40.547037 11, 0xFFFF, sum = 0
2662 00:58:40.550395 12, 0x0, sum = 1
2663 00:58:40.550472 13, 0x0, sum = 2
2664 00:58:40.550534 14, 0x0, sum = 3
2665 00:58:40.553834 15, 0x0, sum = 4
2666 00:58:40.553917 best_step = 13
2667 00:58:40.553980
2668 00:58:40.556960 ==
2669 00:58:40.557033 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 00:58:40.563520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 00:58:40.563617 ==
2672 00:58:40.563683 RX Vref Scan: 1
2673 00:58:40.563743
2674 00:58:40.567356 Set Vref Range= 32 -> 127
2675 00:58:40.567438
2676 00:58:40.570535 RX Vref 32 -> 127, step: 1
2677 00:58:40.570617
2678 00:58:40.573844 RX Delay -13 -> 252, step: 4
2679 00:58:40.573925
2680 00:58:40.576844 Set Vref, RX VrefLevel [Byte0]: 32
2681 00:58:40.580435 [Byte1]: 32
2682 00:58:40.580517
2683 00:58:40.583501 Set Vref, RX VrefLevel [Byte0]: 33
2684 00:58:40.587088 [Byte1]: 33
2685 00:58:40.587164
2686 00:58:40.590411 Set Vref, RX VrefLevel [Byte0]: 34
2687 00:58:40.593774 [Byte1]: 34
2688 00:58:40.597507
2689 00:58:40.597581 Set Vref, RX VrefLevel [Byte0]: 35
2690 00:58:40.601449 [Byte1]: 35
2691 00:58:40.605761
2692 00:58:40.605845 Set Vref, RX VrefLevel [Byte0]: 36
2693 00:58:40.608861 [Byte1]: 36
2694 00:58:40.613341
2695 00:58:40.613421 Set Vref, RX VrefLevel [Byte0]: 37
2696 00:58:40.616529 [Byte1]: 37
2697 00:58:40.621516
2698 00:58:40.621671 Set Vref, RX VrefLevel [Byte0]: 38
2699 00:58:40.624608 [Byte1]: 38
2700 00:58:40.629286
2701 00:58:40.629384 Set Vref, RX VrefLevel [Byte0]: 39
2702 00:58:40.632681 [Byte1]: 39
2703 00:58:40.637158
2704 00:58:40.637258 Set Vref, RX VrefLevel [Byte0]: 40
2705 00:58:40.640269 [Byte1]: 40
2706 00:58:40.645312
2707 00:58:40.645395 Set Vref, RX VrefLevel [Byte0]: 41
2708 00:58:40.648462 [Byte1]: 41
2709 00:58:40.653002
2710 00:58:40.653103 Set Vref, RX VrefLevel [Byte0]: 42
2711 00:58:40.656185 [Byte1]: 42
2712 00:58:40.661165
2713 00:58:40.661283 Set Vref, RX VrefLevel [Byte0]: 43
2714 00:58:40.663961 [Byte1]: 43
2715 00:58:40.668882
2716 00:58:40.668975 Set Vref, RX VrefLevel [Byte0]: 44
2717 00:58:40.671872 [Byte1]: 44
2718 00:58:40.676435
2719 00:58:40.676521 Set Vref, RX VrefLevel [Byte0]: 45
2720 00:58:40.679648 [Byte1]: 45
2721 00:58:40.684489
2722 00:58:40.684575 Set Vref, RX VrefLevel [Byte0]: 46
2723 00:58:40.687733 [Byte1]: 46
2724 00:58:40.692247
2725 00:58:40.692337 Set Vref, RX VrefLevel [Byte0]: 47
2726 00:58:40.695343 [Byte1]: 47
2727 00:58:40.700106
2728 00:58:40.700190 Set Vref, RX VrefLevel [Byte0]: 48
2729 00:58:40.703248 [Byte1]: 48
2730 00:58:40.708378
2731 00:58:40.708470 Set Vref, RX VrefLevel [Byte0]: 49
2732 00:58:40.711441 [Byte1]: 49
2733 00:58:40.716018
2734 00:58:40.716102 Set Vref, RX VrefLevel [Byte0]: 50
2735 00:58:40.719339 [Byte1]: 50
2736 00:58:40.723870
2737 00:58:40.723989 Set Vref, RX VrefLevel [Byte0]: 51
2738 00:58:40.727047 [Byte1]: 51
2739 00:58:40.732082
2740 00:58:40.732201 Set Vref, RX VrefLevel [Byte0]: 52
2741 00:58:40.735219 [Byte1]: 52
2742 00:58:40.739995
2743 00:58:40.740140 Set Vref, RX VrefLevel [Byte0]: 53
2744 00:58:40.742985 [Byte1]: 53
2745 00:58:40.747386
2746 00:58:40.747517 Set Vref, RX VrefLevel [Byte0]: 54
2747 00:58:40.751137 [Byte1]: 54
2748 00:58:40.755520
2749 00:58:40.755621 Set Vref, RX VrefLevel [Byte0]: 55
2750 00:58:40.758933 [Byte1]: 55
2751 00:58:40.763486
2752 00:58:40.763567 Set Vref, RX VrefLevel [Byte0]: 56
2753 00:58:40.766500 [Byte1]: 56
2754 00:58:40.771500
2755 00:58:40.771581 Set Vref, RX VrefLevel [Byte0]: 57
2756 00:58:40.774422 [Byte1]: 57
2757 00:58:40.779223
2758 00:58:40.779323 Set Vref, RX VrefLevel [Byte0]: 58
2759 00:58:40.782545 [Byte1]: 58
2760 00:58:40.786759
2761 00:58:40.786839 Set Vref, RX VrefLevel [Byte0]: 59
2762 00:58:40.790037 [Byte1]: 59
2763 00:58:40.794828
2764 00:58:40.794910 Set Vref, RX VrefLevel [Byte0]: 60
2765 00:58:40.798187 [Byte1]: 60
2766 00:58:40.803188
2767 00:58:40.803265 Set Vref, RX VrefLevel [Byte0]: 61
2768 00:58:40.806181 [Byte1]: 61
2769 00:58:40.810724
2770 00:58:40.810815 Set Vref, RX VrefLevel [Byte0]: 62
2771 00:58:40.814247 [Byte1]: 62
2772 00:58:40.818863
2773 00:58:40.818951 Set Vref, RX VrefLevel [Byte0]: 63
2774 00:58:40.821934 [Byte1]: 63
2775 00:58:40.826473
2776 00:58:40.826561 Set Vref, RX VrefLevel [Byte0]: 64
2777 00:58:40.829747 [Byte1]: 64
2778 00:58:40.834521
2779 00:58:40.834613 Set Vref, RX VrefLevel [Byte0]: 65
2780 00:58:40.837451 [Byte1]: 65
2781 00:58:40.842085
2782 00:58:40.842165 Set Vref, RX VrefLevel [Byte0]: 66
2783 00:58:40.845612 [Byte1]: 66
2784 00:58:40.850392
2785 00:58:40.850472 Set Vref, RX VrefLevel [Byte0]: 67
2786 00:58:40.853384 [Byte1]: 67
2787 00:58:40.858225
2788 00:58:40.858312 Set Vref, RX VrefLevel [Byte0]: 68
2789 00:58:40.861150 [Byte1]: 68
2790 00:58:40.865977
2791 00:58:40.866069 Set Vref, RX VrefLevel [Byte0]: 69
2792 00:58:40.869305 [Byte1]: 69
2793 00:58:40.873631
2794 00:58:40.873711 Set Vref, RX VrefLevel [Byte0]: 70
2795 00:58:40.877342 [Byte1]: 70
2796 00:58:40.882012
2797 00:58:40.882103 Final RX Vref Byte 0 = 57 to rank0
2798 00:58:40.885181 Final RX Vref Byte 1 = 49 to rank0
2799 00:58:40.888441 Final RX Vref Byte 0 = 57 to rank1
2800 00:58:40.891545 Final RX Vref Byte 1 = 49 to rank1==
2801 00:58:40.894668 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 00:58:40.901324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 00:58:40.901414 ==
2804 00:58:40.901479 DQS Delay:
2805 00:58:40.901546 DQS0 = 0, DQS1 = 0
2806 00:58:40.904872 DQM Delay:
2807 00:58:40.904983 DQM0 = 120, DQM1 = 112
2808 00:58:40.908018 DQ Delay:
2809 00:58:40.911869 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2810 00:58:40.915020 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2811 00:58:40.918607 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2812 00:58:40.921333 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2813 00:58:40.921418
2814 00:58:40.921489
2815 00:58:40.931379 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2816 00:58:40.931496 CH0 RK0: MR19=404, MR18=130C
2817 00:58:40.938472 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2818 00:58:40.938568
2819 00:58:40.941502 ----->DramcWriteLeveling(PI) begin...
2820 00:58:40.941595 ==
2821 00:58:40.945005 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 00:58:40.948243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 00:58:40.952046 ==
2824 00:58:40.952166 Write leveling (Byte 0): 35 => 35
2825 00:58:40.955018 Write leveling (Byte 1): 27 => 27
2826 00:58:40.958051 DramcWriteLeveling(PI) end<-----
2827 00:58:40.958134
2828 00:58:40.958204 ==
2829 00:58:40.961692 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 00:58:40.968348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 00:58:40.968444 ==
2832 00:58:40.968512 [Gating] SW mode calibration
2833 00:58:40.978098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 00:58:40.981784 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 00:58:40.988275 0 15 0 | B1->B0 | 3131 2e2e | 1 1 | (0 0) (1 1)
2836 00:58:40.991449 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 00:58:40.995171 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 00:58:40.998420 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 00:58:41.004706 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 00:58:41.008203 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 00:58:41.011758 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 00:58:41.018401 0 15 28 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (1 0)
2843 00:58:41.021455 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2844 00:58:41.025085 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 00:58:41.031922 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 00:58:41.034912 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 00:58:41.038570 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 00:58:41.044934 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 00:58:41.048479 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2850 00:58:41.051771 1 0 28 | B1->B0 | 3c3c 3e3e | 0 0 | (0 0) (0 0)
2851 00:58:41.058618 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 00:58:41.061742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 00:58:41.065448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 00:58:41.071753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 00:58:41.074894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 00:58:41.078476 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 00:58:41.081961 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 00:58:41.088457 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2859 00:58:41.091810 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 00:58:41.094924 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 00:58:41.101976 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 00:58:41.105265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 00:58:41.108306 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:58:41.115426 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:58:41.118645 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:58:41.122116 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 00:58:41.128870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 00:58:41.131646 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:58:41.134893 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:58:41.141670 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 00:58:41.145121 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 00:58:41.148772 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:58:41.154982 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 00:58:41.158287 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2875 00:58:41.161995 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2876 00:58:41.165202 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:58:41.168466 Total UI for P1: 0, mck2ui 16
2878 00:58:41.172095 best dqsien dly found for B0: ( 1, 3, 30)
2879 00:58:41.175174 Total UI for P1: 0, mck2ui 16
2880 00:58:41.178842 best dqsien dly found for B1: ( 1, 3, 30)
2881 00:58:41.182080 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2882 00:58:41.185223 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2883 00:58:41.188881
2884 00:58:41.191884 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2885 00:58:41.195286 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2886 00:58:41.198407 [Gating] SW calibration Done
2887 00:58:41.198514 ==
2888 00:58:41.202302 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 00:58:41.205475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 00:58:41.205560 ==
2891 00:58:41.205625 RX Vref Scan: 0
2892 00:58:41.205683
2893 00:58:41.208623 RX Vref 0 -> 0, step: 1
2894 00:58:41.208705
2895 00:58:41.211733 RX Delay -40 -> 252, step: 8
2896 00:58:41.215792 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2897 00:58:41.218413 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 00:58:41.225344 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2899 00:58:41.228563 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2900 00:58:41.231697 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2901 00:58:41.235244 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2902 00:58:41.238336 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 00:58:41.245376 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2904 00:58:41.248162 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 00:58:41.251491 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2906 00:58:41.255208 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2907 00:58:41.258701 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2908 00:58:41.265087 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2909 00:58:41.268493 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2910 00:58:41.271537 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2911 00:58:41.274660 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2912 00:58:41.274740 ==
2913 00:58:41.278029 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 00:58:41.285163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 00:58:41.285269 ==
2916 00:58:41.285346 DQS Delay:
2917 00:58:41.285410 DQS0 = 0, DQS1 = 0
2918 00:58:41.288306 DQM Delay:
2919 00:58:41.288383 DQM0 = 122, DQM1 = 112
2920 00:58:41.292095 DQ Delay:
2921 00:58:41.295285 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2922 00:58:41.298399 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2923 00:58:41.301432 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2924 00:58:41.305006 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2925 00:58:41.305098
2926 00:58:41.305162
2927 00:58:41.305220 ==
2928 00:58:41.308501 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 00:58:41.311549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 00:58:41.311670 ==
2931 00:58:41.311751
2932 00:58:41.315394
2933 00:58:41.315476 TX Vref Scan disable
2934 00:58:41.318666 == TX Byte 0 ==
2935 00:58:41.321798 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2936 00:58:41.324970 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2937 00:58:41.328751 == TX Byte 1 ==
2938 00:58:41.331854 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2939 00:58:41.335047 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2940 00:58:41.335145 ==
2941 00:58:41.338239 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 00:58:41.345284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 00:58:41.345389 ==
2944 00:58:41.356737 TX Vref=22, minBit 2, minWin=25, winSum=419
2945 00:58:41.359488 TX Vref=24, minBit 1, minWin=25, winSum=424
2946 00:58:41.363313 TX Vref=26, minBit 0, minWin=26, winSum=430
2947 00:58:41.366346 TX Vref=28, minBit 5, minWin=25, winSum=428
2948 00:58:41.369953 TX Vref=30, minBit 2, minWin=26, winSum=430
2949 00:58:41.372994 TX Vref=32, minBit 2, minWin=26, winSum=430
2950 00:58:41.379639 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
2951 00:58:41.379756
2952 00:58:41.383370 Final TX Range 1 Vref 26
2953 00:58:41.383453
2954 00:58:41.383516 ==
2955 00:58:41.386296 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 00:58:41.389875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 00:58:41.389973 ==
2958 00:58:41.390075
2959 00:58:41.390181
2960 00:58:41.393132 TX Vref Scan disable
2961 00:58:41.396221 == TX Byte 0 ==
2962 00:58:41.399863 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2963 00:58:41.403253 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2964 00:58:41.406559 == TX Byte 1 ==
2965 00:58:41.409725 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2966 00:58:41.413443 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2967 00:58:41.413537
2968 00:58:41.416416 [DATLAT]
2969 00:58:41.416489 Freq=1200, CH0 RK1
2970 00:58:41.416551
2971 00:58:41.419898 DATLAT Default: 0xd
2972 00:58:41.420021 0, 0xFFFF, sum = 0
2973 00:58:41.423214 1, 0xFFFF, sum = 0
2974 00:58:41.423298 2, 0xFFFF, sum = 0
2975 00:58:41.426533 3, 0xFFFF, sum = 0
2976 00:58:41.426623 4, 0xFFFF, sum = 0
2977 00:58:41.429739 5, 0xFFFF, sum = 0
2978 00:58:41.429866 6, 0xFFFF, sum = 0
2979 00:58:41.433478 7, 0xFFFF, sum = 0
2980 00:58:41.433562 8, 0xFFFF, sum = 0
2981 00:58:41.436620 9, 0xFFFF, sum = 0
2982 00:58:41.436704 10, 0xFFFF, sum = 0
2983 00:58:41.439757 11, 0xFFFF, sum = 0
2984 00:58:41.439840 12, 0x0, sum = 1
2985 00:58:41.443556 13, 0x0, sum = 2
2986 00:58:41.443639 14, 0x0, sum = 3
2987 00:58:41.446906 15, 0x0, sum = 4
2988 00:58:41.446989 best_step = 13
2989 00:58:41.447052
2990 00:58:41.447111 ==
2991 00:58:41.449846 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 00:58:41.456250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 00:58:41.456368 ==
2994 00:58:41.456433 RX Vref Scan: 0
2995 00:58:41.456492
2996 00:58:41.460176 RX Vref 0 -> 0, step: 1
2997 00:58:41.460299
2998 00:58:41.463236 RX Delay -13 -> 252, step: 4
2999 00:58:41.466836 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3000 00:58:41.470200 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3001 00:58:41.476189 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3002 00:58:41.480184 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3003 00:58:41.483186 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3004 00:58:41.486961 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3005 00:58:41.490240 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3006 00:58:41.496566 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3007 00:58:41.499866 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3008 00:58:41.503146 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3009 00:58:41.506499 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3010 00:58:41.509969 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3011 00:58:41.516592 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3012 00:58:41.520172 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3013 00:58:41.523378 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3014 00:58:41.527071 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3015 00:58:41.527182 ==
3016 00:58:41.530085 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 00:58:41.533060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 00:58:41.536824 ==
3019 00:58:41.536915 DQS Delay:
3020 00:58:41.536979 DQS0 = 0, DQS1 = 0
3021 00:58:41.540163 DQM Delay:
3022 00:58:41.540276 DQM0 = 121, DQM1 = 110
3023 00:58:41.543715 DQ Delay:
3024 00:58:41.546792 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3025 00:58:41.550082 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3026 00:58:41.553760 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3027 00:58:41.556892 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3028 00:58:41.556980
3029 00:58:41.557044
3030 00:58:41.563774 [DQSOSCAuto] RK1, (LSB)MR18= 0xeef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3031 00:58:41.566741 CH0 RK1: MR19=403, MR18=EEF
3032 00:58:41.573527 CH0_RK1: MR19=0x403, MR18=0xEEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3033 00:58:41.576638 [RxdqsGatingPostProcess] freq 1200
3034 00:58:41.583861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 00:58:41.583965 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 00:58:41.586880 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 00:58:41.590108 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 00:58:41.593918 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 00:58:41.597222 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 00:58:41.600279 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 00:58:41.603570 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 00:58:41.606833 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 00:58:41.610459 Pre-setting of DQS Precalculation
3044 00:58:41.613858 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 00:58:41.613942 ==
3046 00:58:41.617209 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 00:58:41.623532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 00:58:41.623632 ==
3049 00:58:41.627176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 00:58:41.634070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3051 00:58:41.642780 [CA 0] Center 37 (7~68) winsize 62
3052 00:58:41.645854 [CA 1] Center 37 (7~68) winsize 62
3053 00:58:41.648897 [CA 2] Center 35 (5~65) winsize 61
3054 00:58:41.652784 [CA 3] Center 34 (5~64) winsize 60
3055 00:58:41.655732 [CA 4] Center 34 (5~64) winsize 60
3056 00:58:41.659551 [CA 5] Center 33 (3~63) winsize 61
3057 00:58:41.659640
3058 00:58:41.662219 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3059 00:58:41.662315
3060 00:58:41.665680 [CATrainingPosCal] consider 1 rank data
3061 00:58:41.668870 u2DelayCellTimex100 = 270/100 ps
3062 00:58:41.672176 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 00:58:41.675841 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 00:58:41.682613 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 00:58:41.685593 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3066 00:58:41.689083 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3067 00:58:41.692758 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3068 00:58:41.692840
3069 00:58:41.695580 CA PerBit enable=1, Macro0, CA PI delay=33
3070 00:58:41.695660
3071 00:58:41.699450 [CBTSetCACLKResult] CA Dly = 33
3072 00:58:41.699530 CS Dly: 8 (0~39)
3073 00:58:41.699593 ==
3074 00:58:41.702546 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 00:58:41.709913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 00:58:41.709995 ==
3077 00:58:41.712763 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 00:58:41.719360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3079 00:58:41.727752 [CA 0] Center 37 (7~68) winsize 62
3080 00:58:41.731489 [CA 1] Center 37 (7~68) winsize 62
3081 00:58:41.734780 [CA 2] Center 35 (5~66) winsize 62
3082 00:58:41.737928 [CA 3] Center 34 (4~65) winsize 62
3083 00:58:41.741088 [CA 4] Center 34 (4~65) winsize 62
3084 00:58:41.744405 [CA 5] Center 34 (4~64) winsize 61
3085 00:58:41.744489
3086 00:58:41.748263 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3087 00:58:41.748373
3088 00:58:41.751450 [CATrainingPosCal] consider 2 rank data
3089 00:58:41.754390 u2DelayCellTimex100 = 270/100 ps
3090 00:58:41.758016 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 00:58:41.761175 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 00:58:41.767697 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 00:58:41.771377 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3094 00:58:41.774867 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3095 00:58:41.778049 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3096 00:58:41.778129
3097 00:58:41.781539 CA PerBit enable=1, Macro0, CA PI delay=33
3098 00:58:41.781619
3099 00:58:41.785054 [CBTSetCACLKResult] CA Dly = 33
3100 00:58:41.785152 CS Dly: 9 (0~41)
3101 00:58:41.785229
3102 00:58:41.787808 ----->DramcWriteLeveling(PI) begin...
3103 00:58:41.791342 ==
3104 00:58:41.791422 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 00:58:41.797968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 00:58:41.798048 ==
3107 00:58:41.801374 Write leveling (Byte 0): 25 => 25
3108 00:58:41.804949 Write leveling (Byte 1): 28 => 28
3109 00:58:41.805043 DramcWriteLeveling(PI) end<-----
3110 00:58:41.807977
3111 00:58:41.808085 ==
3112 00:58:41.811729 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 00:58:41.814737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 00:58:41.814852 ==
3115 00:58:41.818241 [Gating] SW mode calibration
3116 00:58:41.824910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 00:58:41.828129 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 00:58:41.834513 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 00:58:41.837616 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 00:58:41.841392 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 00:58:41.848212 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 00:58:41.851417 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 00:58:41.854540 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 00:58:41.860875 0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 1)
3125 00:58:41.864591 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3126 00:58:41.867656 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 00:58:41.874487 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 00:58:41.877734 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 00:58:41.880893 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 00:58:41.887854 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 00:58:41.891130 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3132 00:58:41.894409 1 0 24 | B1->B0 | 2e2e 4141 | 0 1 | (0 0) (1 1)
3133 00:58:41.901259 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 00:58:41.904157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 00:58:41.907972 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 00:58:41.914455 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 00:58:41.917892 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 00:58:41.921407 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 00:58:41.927886 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 00:58:41.931204 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 00:58:41.934736 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 00:58:41.937702 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 00:58:41.944182 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 00:58:41.947591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 00:58:41.951102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:58:41.958164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:58:41.961221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:58:41.964422 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 00:58:41.971135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 00:58:41.974255 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 00:58:41.977434 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 00:58:41.984218 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 00:58:41.987845 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 00:58:41.991125 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:58:41.997701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:58:42.001219 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3157 00:58:42.004591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3158 00:58:42.007756 Total UI for P1: 0, mck2ui 16
3159 00:58:42.011895 best dqsien dly found for B0: ( 1, 3, 24)
3160 00:58:42.014406 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 00:58:42.017939 Total UI for P1: 0, mck2ui 16
3162 00:58:42.021621 best dqsien dly found for B1: ( 1, 3, 26)
3163 00:58:42.024772 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3164 00:58:42.028048 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3165 00:58:42.031338
3166 00:58:42.034337 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3167 00:58:42.038031 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 00:58:42.041384 [Gating] SW calibration Done
3169 00:58:42.041465 ==
3170 00:58:42.044809 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 00:58:42.048069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 00:58:42.048149 ==
3173 00:58:42.048211 RX Vref Scan: 0
3174 00:58:42.048269
3175 00:58:42.051237 RX Vref 0 -> 0, step: 1
3176 00:58:42.051317
3177 00:58:42.054418 RX Delay -40 -> 252, step: 8
3178 00:58:42.057983 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3179 00:58:42.060971 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3180 00:58:42.067995 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3181 00:58:42.071362 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3182 00:58:42.074416 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3183 00:58:42.078076 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3184 00:58:42.081741 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3185 00:58:42.088166 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3186 00:58:42.091363 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3187 00:58:42.094973 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3188 00:58:42.098223 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3189 00:58:42.101414 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3190 00:58:42.107945 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 00:58:42.111119 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3192 00:58:42.114807 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3193 00:58:42.117840 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3194 00:58:42.117922 ==
3195 00:58:42.121604 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 00:58:42.124579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 00:58:42.128107 ==
3198 00:58:42.128213 DQS Delay:
3199 00:58:42.128329 DQS0 = 0, DQS1 = 0
3200 00:58:42.131194 DQM Delay:
3201 00:58:42.131281 DQM0 = 119, DQM1 = 117
3202 00:58:42.134542 DQ Delay:
3203 00:58:42.137778 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3204 00:58:42.141261 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3205 00:58:42.144563 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3206 00:58:42.147783 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =127
3207 00:58:42.147864
3208 00:58:42.147926
3209 00:58:42.147983 ==
3210 00:58:42.151507 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 00:58:42.154724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 00:58:42.154810 ==
3213 00:58:42.157948
3214 00:58:42.158028
3215 00:58:42.158090 TX Vref Scan disable
3216 00:58:42.161110 == TX Byte 0 ==
3217 00:58:42.164529 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3218 00:58:42.168105 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3219 00:58:42.171085 == TX Byte 1 ==
3220 00:58:42.174770 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3221 00:58:42.178207 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3222 00:58:42.178289 ==
3223 00:58:42.181432 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 00:58:42.187868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 00:58:42.187973 ==
3226 00:58:42.198531 TX Vref=22, minBit 9, minWin=24, winSum=412
3227 00:58:42.201425 TX Vref=24, minBit 9, minWin=24, winSum=416
3228 00:58:42.205272 TX Vref=26, minBit 9, minWin=25, winSum=421
3229 00:58:42.208521 TX Vref=28, minBit 11, minWin=25, winSum=425
3230 00:58:42.211570 TX Vref=30, minBit 2, minWin=26, winSum=430
3231 00:58:42.218723 TX Vref=32, minBit 10, minWin=25, winSum=430
3232 00:58:42.221801 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 30
3233 00:58:42.221884
3234 00:58:42.224915 Final TX Range 1 Vref 30
3235 00:58:42.225039
3236 00:58:42.225150 ==
3237 00:58:42.228707 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 00:58:42.231808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 00:58:42.231890 ==
3240 00:58:42.231954
3241 00:58:42.235348
3242 00:58:42.235445 TX Vref Scan disable
3243 00:58:42.238505 == TX Byte 0 ==
3244 00:58:42.241790 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3245 00:58:42.245487 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3246 00:58:42.248501 == TX Byte 1 ==
3247 00:58:42.252143 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3248 00:58:42.255306 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3249 00:58:42.255388
3250 00:58:42.258582 [DATLAT]
3251 00:58:42.258663 Freq=1200, CH1 RK0
3252 00:58:42.258727
3253 00:58:42.261836 DATLAT Default: 0xd
3254 00:58:42.261917 0, 0xFFFF, sum = 0
3255 00:58:42.265003 1, 0xFFFF, sum = 0
3256 00:58:42.265085 2, 0xFFFF, sum = 0
3257 00:58:42.268922 3, 0xFFFF, sum = 0
3258 00:58:42.269004 4, 0xFFFF, sum = 0
3259 00:58:42.272015 5, 0xFFFF, sum = 0
3260 00:58:42.272097 6, 0xFFFF, sum = 0
3261 00:58:42.275198 7, 0xFFFF, sum = 0
3262 00:58:42.275281 8, 0xFFFF, sum = 0
3263 00:58:42.278774 9, 0xFFFF, sum = 0
3264 00:58:42.281765 10, 0xFFFF, sum = 0
3265 00:58:42.281848 11, 0xFFFF, sum = 0
3266 00:58:42.285065 12, 0x0, sum = 1
3267 00:58:42.285148 13, 0x0, sum = 2
3268 00:58:42.285212 14, 0x0, sum = 3
3269 00:58:42.288310 15, 0x0, sum = 4
3270 00:58:42.288406 best_step = 13
3271 00:58:42.288470
3272 00:58:42.291875 ==
3273 00:58:42.291972 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 00:58:42.298430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 00:58:42.298515 ==
3276 00:58:42.298579 RX Vref Scan: 1
3277 00:58:42.298638
3278 00:58:42.302252 Set Vref Range= 32 -> 127
3279 00:58:42.302333
3280 00:58:42.305402 RX Vref 32 -> 127, step: 1
3281 00:58:42.305500
3282 00:58:42.308591 RX Delay -5 -> 252, step: 4
3283 00:58:42.308672
3284 00:58:42.312095 Set Vref, RX VrefLevel [Byte0]: 32
3285 00:58:42.312176 [Byte1]: 32
3286 00:58:42.316815
3287 00:58:42.316895 Set Vref, RX VrefLevel [Byte0]: 33
3288 00:58:42.319669 [Byte1]: 33
3289 00:58:42.324783
3290 00:58:42.324864 Set Vref, RX VrefLevel [Byte0]: 34
3291 00:58:42.327967 [Byte1]: 34
3292 00:58:42.332218
3293 00:58:42.332347 Set Vref, RX VrefLevel [Byte0]: 35
3294 00:58:42.335472 [Byte1]: 35
3295 00:58:42.340506
3296 00:58:42.340594 Set Vref, RX VrefLevel [Byte0]: 36
3297 00:58:42.343524 [Byte1]: 36
3298 00:58:42.347989
3299 00:58:42.348068 Set Vref, RX VrefLevel [Byte0]: 37
3300 00:58:42.351199 [Byte1]: 37
3301 00:58:42.355900
3302 00:58:42.355980 Set Vref, RX VrefLevel [Byte0]: 38
3303 00:58:42.359324 [Byte1]: 38
3304 00:58:42.363690
3305 00:58:42.363812 Set Vref, RX VrefLevel [Byte0]: 39
3306 00:58:42.366920 [Byte1]: 39
3307 00:58:42.371332
3308 00:58:42.371414 Set Vref, RX VrefLevel [Byte0]: 40
3309 00:58:42.374730 [Byte1]: 40
3310 00:58:42.379294
3311 00:58:42.379373 Set Vref, RX VrefLevel [Byte0]: 41
3312 00:58:42.382836 [Byte1]: 41
3313 00:58:42.387436
3314 00:58:42.387516 Set Vref, RX VrefLevel [Byte0]: 42
3315 00:58:42.390607 [Byte1]: 42
3316 00:58:42.394956
3317 00:58:42.395036 Set Vref, RX VrefLevel [Byte0]: 43
3318 00:58:42.398935 [Byte1]: 43
3319 00:58:42.402783
3320 00:58:42.402863 Set Vref, RX VrefLevel [Byte0]: 44
3321 00:58:42.406531 [Byte1]: 44
3322 00:58:42.411052
3323 00:58:42.411165 Set Vref, RX VrefLevel [Byte0]: 45
3324 00:58:42.414539 [Byte1]: 45
3325 00:58:42.418953
3326 00:58:42.419033 Set Vref, RX VrefLevel [Byte0]: 46
3327 00:58:42.422158 [Byte1]: 46
3328 00:58:42.426365
3329 00:58:42.426474 Set Vref, RX VrefLevel [Byte0]: 47
3330 00:58:42.430116 [Byte1]: 47
3331 00:58:42.434263
3332 00:58:42.434344 Set Vref, RX VrefLevel [Byte0]: 48
3333 00:58:42.437584 [Byte1]: 48
3334 00:58:42.442385
3335 00:58:42.442499 Set Vref, RX VrefLevel [Byte0]: 49
3336 00:58:42.445420 [Byte1]: 49
3337 00:58:42.449985
3338 00:58:42.450131 Set Vref, RX VrefLevel [Byte0]: 50
3339 00:58:42.453222 [Byte1]: 50
3340 00:58:42.457814
3341 00:58:42.457927 Set Vref, RX VrefLevel [Byte0]: 51
3342 00:58:42.461209 [Byte1]: 51
3343 00:58:42.465697
3344 00:58:42.465853 Set Vref, RX VrefLevel [Byte0]: 52
3345 00:58:42.469243 [Byte1]: 52
3346 00:58:42.473985
3347 00:58:42.474115 Set Vref, RX VrefLevel [Byte0]: 53
3348 00:58:42.477310 [Byte1]: 53
3349 00:58:42.481810
3350 00:58:42.481939 Set Vref, RX VrefLevel [Byte0]: 54
3351 00:58:42.485060 [Byte1]: 54
3352 00:58:42.489501
3353 00:58:42.489582 Set Vref, RX VrefLevel [Byte0]: 55
3354 00:58:42.493028 [Byte1]: 55
3355 00:58:42.497001
3356 00:58:42.497081 Set Vref, RX VrefLevel [Byte0]: 56
3357 00:58:42.500549 [Byte1]: 56
3358 00:58:42.504937
3359 00:58:42.505017 Set Vref, RX VrefLevel [Byte0]: 57
3360 00:58:42.508281 [Byte1]: 57
3361 00:58:42.512841
3362 00:58:42.512921 Set Vref, RX VrefLevel [Byte0]: 58
3363 00:58:42.516082 [Byte1]: 58
3364 00:58:42.520834
3365 00:58:42.520915 Set Vref, RX VrefLevel [Byte0]: 59
3366 00:58:42.523838 [Byte1]: 59
3367 00:58:42.528217
3368 00:58:42.528366 Set Vref, RX VrefLevel [Byte0]: 60
3369 00:58:42.532110 [Byte1]: 60
3370 00:58:42.536544
3371 00:58:42.536624 Set Vref, RX VrefLevel [Byte0]: 61
3372 00:58:42.539777 [Byte1]: 61
3373 00:58:42.544638
3374 00:58:42.544718 Set Vref, RX VrefLevel [Byte0]: 62
3375 00:58:42.547802 [Byte1]: 62
3376 00:58:42.552164
3377 00:58:42.552271 Set Vref, RX VrefLevel [Byte0]: 63
3378 00:58:42.555494 [Byte1]: 63
3379 00:58:42.559834
3380 00:58:42.559916 Set Vref, RX VrefLevel [Byte0]: 64
3381 00:58:42.563466 [Byte1]: 64
3382 00:58:42.567910
3383 00:58:42.567992 Set Vref, RX VrefLevel [Byte0]: 65
3384 00:58:42.571484 [Byte1]: 65
3385 00:58:42.575819
3386 00:58:42.575900 Set Vref, RX VrefLevel [Byte0]: 66
3387 00:58:42.579604 [Byte1]: 66
3388 00:58:42.583282
3389 00:58:42.583364 Set Vref, RX VrefLevel [Byte0]: 67
3390 00:58:42.587210 [Byte1]: 67
3391 00:58:42.591770
3392 00:58:42.591859 Final RX Vref Byte 0 = 56 to rank0
3393 00:58:42.594887 Final RX Vref Byte 1 = 47 to rank0
3394 00:58:42.597987 Final RX Vref Byte 0 = 56 to rank1
3395 00:58:42.601720 Final RX Vref Byte 1 = 47 to rank1==
3396 00:58:42.604486 Dram Type= 6, Freq= 0, CH_1, rank 0
3397 00:58:42.608276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3398 00:58:42.611214 ==
3399 00:58:42.611295 DQS Delay:
3400 00:58:42.611359 DQS0 = 0, DQS1 = 0
3401 00:58:42.615135 DQM Delay:
3402 00:58:42.615215 DQM0 = 120, DQM1 = 116
3403 00:58:42.618224 DQ Delay:
3404 00:58:42.621345 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3405 00:58:42.625032 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3406 00:58:42.627966 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3407 00:58:42.631546 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3408 00:58:42.631657
3409 00:58:42.631762
3410 00:58:42.638365 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3411 00:58:42.641512 CH1 RK0: MR19=404, MR18=13
3412 00:58:42.648512 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3413 00:58:42.648613
3414 00:58:42.651596 ----->DramcWriteLeveling(PI) begin...
3415 00:58:42.651678 ==
3416 00:58:42.654710 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 00:58:42.658502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 00:58:42.658585 ==
3419 00:58:42.661392 Write leveling (Byte 0): 25 => 25
3420 00:58:42.664674 Write leveling (Byte 1): 29 => 29
3421 00:58:42.668746 DramcWriteLeveling(PI) end<-----
3422 00:58:42.668828
3423 00:58:42.668892 ==
3424 00:58:42.671517 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 00:58:42.674801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 00:58:42.674901 ==
3427 00:58:42.678332 [Gating] SW mode calibration
3428 00:58:42.684709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3429 00:58:42.691524 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3430 00:58:42.694899 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 00:58:42.701749 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 00:58:42.704900 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 00:58:42.708791 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 00:58:42.714923 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 00:58:42.718424 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3436 00:58:42.721983 0 15 24 | B1->B0 | 2828 3131 | 0 1 | (1 0) (1 0)
3437 00:58:42.724767 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 00:58:42.731506 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 00:58:42.734953 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 00:58:42.738402 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 00:58:42.745092 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 00:58:42.748222 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 00:58:42.751974 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3444 00:58:42.758907 1 0 24 | B1->B0 | 4343 2b2a | 0 1 | (0 0) (1 1)
3445 00:58:42.761989 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3446 00:58:42.765125 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 00:58:42.772116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 00:58:42.775357 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 00:58:42.778313 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 00:58:42.784799 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 00:58:42.788385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3452 00:58:42.791432 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3453 00:58:42.798170 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3454 00:58:42.801835 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 00:58:42.805160 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 00:58:42.811336 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 00:58:42.815138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 00:58:42.818376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 00:58:42.824748 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 00:58:42.828454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 00:58:42.831388 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 00:58:42.834782 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 00:58:42.841866 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 00:58:42.844672 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 00:58:42.848147 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 00:58:42.854815 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 00:58:42.857935 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3468 00:58:42.861698 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3469 00:58:42.867721 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 00:58:42.871464 Total UI for P1: 0, mck2ui 16
3471 00:58:42.874617 best dqsien dly found for B0: ( 1, 3, 24)
3472 00:58:42.874697 Total UI for P1: 0, mck2ui 16
3473 00:58:42.881159 best dqsien dly found for B1: ( 1, 3, 22)
3474 00:58:42.885081 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3475 00:58:42.888167 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3476 00:58:42.888247
3477 00:58:42.891631 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3478 00:58:42.894575 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3479 00:58:42.898077 [Gating] SW calibration Done
3480 00:58:42.898161 ==
3481 00:58:42.901253 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 00:58:42.904467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 00:58:42.904549 ==
3484 00:58:42.908147 RX Vref Scan: 0
3485 00:58:42.908247
3486 00:58:42.908323 RX Vref 0 -> 0, step: 1
3487 00:58:42.908387
3488 00:58:42.911309 RX Delay -40 -> 252, step: 8
3489 00:58:42.917924 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3490 00:58:42.921277 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3491 00:58:42.924942 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3492 00:58:42.928226 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3493 00:58:42.931468 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3494 00:58:42.934818 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3495 00:58:42.941572 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3496 00:58:42.944422 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3497 00:58:42.947822 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3498 00:58:42.951211 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3499 00:58:42.954159 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3500 00:58:42.961461 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3501 00:58:42.964803 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3502 00:58:42.967595 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3503 00:58:42.971600 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3504 00:58:42.978158 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3505 00:58:42.978276 ==
3506 00:58:42.981097 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 00:58:42.984314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 00:58:42.984409 ==
3509 00:58:42.984472 DQS Delay:
3510 00:58:42.987505 DQS0 = 0, DQS1 = 0
3511 00:58:42.987625 DQM Delay:
3512 00:58:42.990871 DQM0 = 120, DQM1 = 119
3513 00:58:42.990952 DQ Delay:
3514 00:58:42.994137 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3515 00:58:42.997277 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3516 00:58:43.000990 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3517 00:58:43.004056 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3518 00:58:43.004137
3519 00:58:43.007320
3520 00:58:43.007401 ==
3521 00:58:43.010442 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 00:58:43.014132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 00:58:43.014215 ==
3524 00:58:43.014279
3525 00:58:43.014337
3526 00:58:43.017240 TX Vref Scan disable
3527 00:58:43.017322 == TX Byte 0 ==
3528 00:58:43.023681 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3529 00:58:43.027326 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3530 00:58:43.027412 == TX Byte 1 ==
3531 00:58:43.033716 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3532 00:58:43.036766 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3533 00:58:43.036845 ==
3534 00:58:43.040550 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 00:58:43.043773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 00:58:43.043857 ==
3537 00:58:43.056114 TX Vref=22, minBit 9, minWin=25, winSum=421
3538 00:58:43.059363 TX Vref=24, minBit 10, minWin=25, winSum=423
3539 00:58:43.063058 TX Vref=26, minBit 2, minWin=26, winSum=433
3540 00:58:43.065933 TX Vref=28, minBit 2, minWin=26, winSum=432
3541 00:58:43.069638 TX Vref=30, minBit 9, minWin=26, winSum=436
3542 00:58:43.075608 TX Vref=32, minBit 1, minWin=26, winSum=435
3543 00:58:43.079131 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3544 00:58:43.079217
3545 00:58:43.082615 Final TX Range 1 Vref 30
3546 00:58:43.082699
3547 00:58:43.082765 ==
3548 00:58:43.085989 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 00:58:43.089258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 00:58:43.089343 ==
3551 00:58:43.092999
3552 00:58:43.093080
3553 00:58:43.093144 TX Vref Scan disable
3554 00:58:43.096260 == TX Byte 0 ==
3555 00:58:43.099380 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3556 00:58:43.102759 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3557 00:58:43.105782 == TX Byte 1 ==
3558 00:58:43.109497 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3559 00:58:43.112561 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3560 00:58:43.116185
3561 00:58:43.116266 [DATLAT]
3562 00:58:43.116377 Freq=1200, CH1 RK1
3563 00:58:43.116439
3564 00:58:43.119186 DATLAT Default: 0xd
3565 00:58:43.119266 0, 0xFFFF, sum = 0
3566 00:58:43.122690 1, 0xFFFF, sum = 0
3567 00:58:43.122772 2, 0xFFFF, sum = 0
3568 00:58:43.125538 3, 0xFFFF, sum = 0
3569 00:58:43.129398 4, 0xFFFF, sum = 0
3570 00:58:43.129484 5, 0xFFFF, sum = 0
3571 00:58:43.132518 6, 0xFFFF, sum = 0
3572 00:58:43.132631 7, 0xFFFF, sum = 0
3573 00:58:43.135761 8, 0xFFFF, sum = 0
3574 00:58:43.135846 9, 0xFFFF, sum = 0
3575 00:58:43.139395 10, 0xFFFF, sum = 0
3576 00:58:43.139477 11, 0xFFFF, sum = 0
3577 00:58:43.142304 12, 0x0, sum = 1
3578 00:58:43.142378 13, 0x0, sum = 2
3579 00:58:43.145581 14, 0x0, sum = 3
3580 00:58:43.145662 15, 0x0, sum = 4
3581 00:58:43.145726 best_step = 13
3582 00:58:43.148785
3583 00:58:43.148898 ==
3584 00:58:43.152530 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 00:58:43.155715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 00:58:43.155796 ==
3587 00:58:43.155859 RX Vref Scan: 0
3588 00:58:43.155924
3589 00:58:43.158663 RX Vref 0 -> 0, step: 1
3590 00:58:43.158742
3591 00:58:43.162440 RX Delay -5 -> 252, step: 4
3592 00:58:43.165357 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3593 00:58:43.172039 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3594 00:58:43.175545 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3595 00:58:43.178660 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3596 00:58:43.182353 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3597 00:58:43.185318 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3598 00:58:43.192046 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3599 00:58:43.195159 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3600 00:58:43.198686 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3601 00:58:43.201914 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3602 00:58:43.205637 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3603 00:58:43.212009 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3604 00:58:43.215171 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3605 00:58:43.218917 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3606 00:58:43.221943 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3607 00:58:43.225065 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3608 00:58:43.228878 ==
3609 00:58:43.231793 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 00:58:43.235232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 00:58:43.235314 ==
3612 00:58:43.235377 DQS Delay:
3613 00:58:43.238318 DQS0 = 0, DQS1 = 0
3614 00:58:43.238399 DQM Delay:
3615 00:58:43.242112 DQM0 = 120, DQM1 = 116
3616 00:58:43.242193 DQ Delay:
3617 00:58:43.245390 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3618 00:58:43.248474 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3619 00:58:43.252087 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3620 00:58:43.255069 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3621 00:58:43.255149
3622 00:58:43.255212
3623 00:58:43.265282 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3624 00:58:43.268491 CH1 RK1: MR19=403, MR18=11EE
3625 00:58:43.271696 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3626 00:58:43.275586 [RxdqsGatingPostProcess] freq 1200
3627 00:58:43.281696 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3628 00:58:43.285391 best DQS0 dly(2T, 0.5T) = (0, 11)
3629 00:58:43.288711 best DQS1 dly(2T, 0.5T) = (0, 11)
3630 00:58:43.291931 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3631 00:58:43.295207 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3632 00:58:43.298403 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 00:58:43.301762 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 00:58:43.305245 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 00:58:43.308212 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 00:58:43.311694 Pre-setting of DQS Precalculation
3637 00:58:43.315179 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3638 00:58:43.321957 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3639 00:58:43.328188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3640 00:58:43.328340
3641 00:58:43.328408
3642 00:58:43.331764 [Calibration Summary] 2400 Mbps
3643 00:58:43.334946 CH 0, Rank 0
3644 00:58:43.335028 SW Impedance : PASS
3645 00:58:43.338732 DUTY Scan : NO K
3646 00:58:43.341455 ZQ Calibration : PASS
3647 00:58:43.341537 Jitter Meter : NO K
3648 00:58:43.344934 CBT Training : PASS
3649 00:58:43.347967 Write leveling : PASS
3650 00:58:43.348048 RX DQS gating : PASS
3651 00:58:43.351854 RX DQ/DQS(RDDQC) : PASS
3652 00:58:43.354951 TX DQ/DQS : PASS
3653 00:58:43.355033 RX DATLAT : PASS
3654 00:58:43.358284 RX DQ/DQS(Engine): PASS
3655 00:58:43.358365 TX OE : NO K
3656 00:58:43.361305 All Pass.
3657 00:58:43.361386
3658 00:58:43.361450 CH 0, Rank 1
3659 00:58:43.364929 SW Impedance : PASS
3660 00:58:43.365027 DUTY Scan : NO K
3661 00:58:43.368407 ZQ Calibration : PASS
3662 00:58:43.371238 Jitter Meter : NO K
3663 00:58:43.371319 CBT Training : PASS
3664 00:58:43.375121 Write leveling : PASS
3665 00:58:43.377961 RX DQS gating : PASS
3666 00:58:43.378042 RX DQ/DQS(RDDQC) : PASS
3667 00:58:43.381776 TX DQ/DQS : PASS
3668 00:58:43.384817 RX DATLAT : PASS
3669 00:58:43.384915 RX DQ/DQS(Engine): PASS
3670 00:58:43.387831 TX OE : NO K
3671 00:58:43.387913 All Pass.
3672 00:58:43.387978
3673 00:58:43.391498 CH 1, Rank 0
3674 00:58:43.391579 SW Impedance : PASS
3675 00:58:43.394681 DUTY Scan : NO K
3676 00:58:43.397868 ZQ Calibration : PASS
3677 00:58:43.397950 Jitter Meter : NO K
3678 00:58:43.401759 CBT Training : PASS
3679 00:58:43.404837 Write leveling : PASS
3680 00:58:43.404919 RX DQS gating : PASS
3681 00:58:43.408145 RX DQ/DQS(RDDQC) : PASS
3682 00:58:43.408243 TX DQ/DQS : PASS
3683 00:58:43.411231 RX DATLAT : PASS
3684 00:58:43.414520 RX DQ/DQS(Engine): PASS
3685 00:58:43.414599 TX OE : NO K
3686 00:58:43.417954 All Pass.
3687 00:58:43.418037
3688 00:58:43.418100 CH 1, Rank 1
3689 00:58:43.421440 SW Impedance : PASS
3690 00:58:43.421520 DUTY Scan : NO K
3691 00:58:43.424480 ZQ Calibration : PASS
3692 00:58:43.428106 Jitter Meter : NO K
3693 00:58:43.428235 CBT Training : PASS
3694 00:58:43.431387 Write leveling : PASS
3695 00:58:43.434604 RX DQS gating : PASS
3696 00:58:43.434685 RX DQ/DQS(RDDQC) : PASS
3697 00:58:43.437742 TX DQ/DQS : PASS
3698 00:58:43.441113 RX DATLAT : PASS
3699 00:58:43.441195 RX DQ/DQS(Engine): PASS
3700 00:58:43.444917 TX OE : NO K
3701 00:58:43.445014 All Pass.
3702 00:58:43.445093
3703 00:58:43.447870 DramC Write-DBI off
3704 00:58:43.451353 PER_BANK_REFRESH: Hybrid Mode
3705 00:58:43.451434 TX_TRACKING: ON
3706 00:58:43.460972 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3707 00:58:43.464743 [FAST_K] Save calibration result to emmc
3708 00:58:43.468106 dramc_set_vcore_voltage set vcore to 650000
3709 00:58:43.471000 Read voltage for 600, 5
3710 00:58:43.471096 Vio18 = 0
3711 00:58:43.471191 Vcore = 650000
3712 00:58:43.474352 Vdram = 0
3713 00:58:43.474440 Vddq = 0
3714 00:58:43.474550 Vmddr = 0
3715 00:58:43.481158 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3716 00:58:43.484165 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3717 00:58:43.487567 MEM_TYPE=3, freq_sel=19
3718 00:58:43.490896 sv_algorithm_assistance_LP4_1600
3719 00:58:43.494386 ============ PULL DRAM RESETB DOWN ============
3720 00:58:43.497351 ========== PULL DRAM RESETB DOWN end =========
3721 00:58:43.504160 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3722 00:58:43.507394 ===================================
3723 00:58:43.507519 LPDDR4 DRAM CONFIGURATION
3724 00:58:43.510775 ===================================
3725 00:58:43.514398 EX_ROW_EN[0] = 0x0
3726 00:58:43.517739 EX_ROW_EN[1] = 0x0
3727 00:58:43.517819 LP4Y_EN = 0x0
3728 00:58:43.520902 WORK_FSP = 0x0
3729 00:58:43.520981 WL = 0x2
3730 00:58:43.524017 RL = 0x2
3731 00:58:43.524096 BL = 0x2
3732 00:58:43.527495 RPST = 0x0
3733 00:58:43.527615 RD_PRE = 0x0
3734 00:58:43.531206 WR_PRE = 0x1
3735 00:58:43.531303 WR_PST = 0x0
3736 00:58:43.534287 DBI_WR = 0x0
3737 00:58:43.534372 DBI_RD = 0x0
3738 00:58:43.537641 OTF = 0x1
3739 00:58:43.540748 ===================================
3740 00:58:43.544401 ===================================
3741 00:58:43.544483 ANA top config
3742 00:58:43.547758 ===================================
3743 00:58:43.551129 DLL_ASYNC_EN = 0
3744 00:58:43.554045 ALL_SLAVE_EN = 1
3745 00:58:43.557428 NEW_RANK_MODE = 1
3746 00:58:43.557509 DLL_IDLE_MODE = 1
3747 00:58:43.560958 LP45_APHY_COMB_EN = 1
3748 00:58:43.564437 TX_ODT_DIS = 1
3749 00:58:43.567764 NEW_8X_MODE = 1
3750 00:58:43.571159 ===================================
3751 00:58:43.574320 ===================================
3752 00:58:43.577619 data_rate = 1200
3753 00:58:43.577700 CKR = 1
3754 00:58:43.580813 DQ_P2S_RATIO = 8
3755 00:58:43.583861 ===================================
3756 00:58:43.587128 CA_P2S_RATIO = 8
3757 00:58:43.590518 DQ_CA_OPEN = 0
3758 00:58:43.594128 DQ_SEMI_OPEN = 0
3759 00:58:43.597163 CA_SEMI_OPEN = 0
3760 00:58:43.597243 CA_FULL_RATE = 0
3761 00:58:43.600489 DQ_CKDIV4_EN = 1
3762 00:58:43.603723 CA_CKDIV4_EN = 1
3763 00:58:43.606965 CA_PREDIV_EN = 0
3764 00:58:43.610442 PH8_DLY = 0
3765 00:58:43.614055 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3766 00:58:43.614136 DQ_AAMCK_DIV = 4
3767 00:58:43.617297 CA_AAMCK_DIV = 4
3768 00:58:43.620507 CA_ADMCK_DIV = 4
3769 00:58:43.623547 DQ_TRACK_CA_EN = 0
3770 00:58:43.626890 CA_PICK = 600
3771 00:58:43.630269 CA_MCKIO = 600
3772 00:58:43.633397 MCKIO_SEMI = 0
3773 00:58:43.633472 PLL_FREQ = 2288
3774 00:58:43.636650 DQ_UI_PI_RATIO = 32
3775 00:58:43.640123 CA_UI_PI_RATIO = 0
3776 00:58:43.643229 ===================================
3777 00:58:43.646578 ===================================
3778 00:58:43.649722 memory_type:LPDDR4
3779 00:58:43.653293 GP_NUM : 10
3780 00:58:43.653363 SRAM_EN : 1
3781 00:58:43.656374 MD32_EN : 0
3782 00:58:43.659875 ===================================
3783 00:58:43.660014 [ANA_INIT] >>>>>>>>>>>>>>
3784 00:58:43.663521 <<<<<< [CONFIGURE PHASE]: ANA_TX
3785 00:58:43.666541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3786 00:58:43.670289 ===================================
3787 00:58:43.673328 data_rate = 1200,PCW = 0X5800
3788 00:58:43.676489 ===================================
3789 00:58:43.679975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3790 00:58:43.686355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3791 00:58:43.692916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 00:58:43.696210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3793 00:58:43.699515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3794 00:58:43.702726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3795 00:58:43.706517 [ANA_INIT] flow start
3796 00:58:43.706621 [ANA_INIT] PLL >>>>>>>>
3797 00:58:43.709524 [ANA_INIT] PLL <<<<<<<<
3798 00:58:43.713066 [ANA_INIT] MIDPI >>>>>>>>
3799 00:58:43.713172 [ANA_INIT] MIDPI <<<<<<<<
3800 00:58:43.715894 [ANA_INIT] DLL >>>>>>>>
3801 00:58:43.719310 [ANA_INIT] flow end
3802 00:58:43.722533 ============ LP4 DIFF to SE enter ============
3803 00:58:43.725963 ============ LP4 DIFF to SE exit ============
3804 00:58:43.729692 [ANA_INIT] <<<<<<<<<<<<<
3805 00:58:43.732877 [Flow] Enable top DCM control >>>>>
3806 00:58:43.735979 [Flow] Enable top DCM control <<<<<
3807 00:58:43.739315 Enable DLL master slave shuffle
3808 00:58:43.742391 ==============================================================
3809 00:58:43.745748 Gating Mode config
3810 00:58:43.752885 ==============================================================
3811 00:58:43.752973 Config description:
3812 00:58:43.762291 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3813 00:58:43.769333 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3814 00:58:43.772407 SELPH_MODE 0: By rank 1: By Phase
3815 00:58:43.779513 ==============================================================
3816 00:58:43.782726 GAT_TRACK_EN = 1
3817 00:58:43.785996 RX_GATING_MODE = 2
3818 00:58:43.789284 RX_GATING_TRACK_MODE = 2
3819 00:58:43.792296 SELPH_MODE = 1
3820 00:58:43.795903 PICG_EARLY_EN = 1
3821 00:58:43.799040 VALID_LAT_VALUE = 1
3822 00:58:43.802683 ==============================================================
3823 00:58:43.805885 Enter into Gating configuration >>>>
3824 00:58:43.809353 Exit from Gating configuration <<<<
3825 00:58:43.812645 Enter into DVFS_PRE_config >>>>>
3826 00:58:43.825962 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3827 00:58:43.826085 Exit from DVFS_PRE_config <<<<<
3828 00:58:43.829086 Enter into PICG configuration >>>>
3829 00:58:43.832439 Exit from PICG configuration <<<<
3830 00:58:43.835798 [RX_INPUT] configuration >>>>>
3831 00:58:43.838775 [RX_INPUT] configuration <<<<<
3832 00:58:43.845588 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3833 00:58:43.848961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3834 00:58:43.855516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3835 00:58:43.862447 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3836 00:58:43.868673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 00:58:43.875236 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 00:58:43.878903 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3839 00:58:43.882367 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3840 00:58:43.885653 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3841 00:58:43.892213 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3842 00:58:43.895440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3843 00:58:43.899280 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3844 00:58:43.902453 ===================================
3845 00:58:43.905595 LPDDR4 DRAM CONFIGURATION
3846 00:58:43.909224 ===================================
3847 00:58:43.909311 EX_ROW_EN[0] = 0x0
3848 00:58:43.912270 EX_ROW_EN[1] = 0x0
3849 00:58:43.915654 LP4Y_EN = 0x0
3850 00:58:43.915766 WORK_FSP = 0x0
3851 00:58:43.918850 WL = 0x2
3852 00:58:43.918930 RL = 0x2
3853 00:58:43.922380 BL = 0x2
3854 00:58:43.922462 RPST = 0x0
3855 00:58:43.925545 RD_PRE = 0x0
3856 00:58:43.925626 WR_PRE = 0x1
3857 00:58:43.928535 WR_PST = 0x0
3858 00:58:43.928620 DBI_WR = 0x0
3859 00:58:43.931834 DBI_RD = 0x0
3860 00:58:43.931957 OTF = 0x1
3861 00:58:43.935514 ===================================
3862 00:58:43.938737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3863 00:58:43.945388 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3864 00:58:43.948764 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 00:58:43.952183 ===================================
3866 00:58:43.955152 LPDDR4 DRAM CONFIGURATION
3867 00:58:43.958567 ===================================
3868 00:58:43.958652 EX_ROW_EN[0] = 0x10
3869 00:58:43.962299 EX_ROW_EN[1] = 0x0
3870 00:58:43.962389 LP4Y_EN = 0x0
3871 00:58:43.965185 WORK_FSP = 0x0
3872 00:58:43.965268 WL = 0x2
3873 00:58:43.968916 RL = 0x2
3874 00:58:43.972064 BL = 0x2
3875 00:58:43.972147 RPST = 0x0
3876 00:58:43.975189 RD_PRE = 0x0
3877 00:58:43.975302 WR_PRE = 0x1
3878 00:58:43.978470 WR_PST = 0x0
3879 00:58:43.978555 DBI_WR = 0x0
3880 00:58:43.981873 DBI_RD = 0x0
3881 00:58:43.981958 OTF = 0x1
3882 00:58:43.985614 ===================================
3883 00:58:43.991787 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3884 00:58:43.995575 nWR fixed to 30
3885 00:58:43.999315 [ModeRegInit_LP4] CH0 RK0
3886 00:58:43.999402 [ModeRegInit_LP4] CH0 RK1
3887 00:58:44.002512 [ModeRegInit_LP4] CH1 RK0
3888 00:58:44.005773 [ModeRegInit_LP4] CH1 RK1
3889 00:58:44.005859 match AC timing 17
3890 00:58:44.011962 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3891 00:58:44.015252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3892 00:58:44.019092 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3893 00:58:44.025413 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3894 00:58:44.028522 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3895 00:58:44.028609 ==
3896 00:58:44.032630 Dram Type= 6, Freq= 0, CH_0, rank 0
3897 00:58:44.035519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3898 00:58:44.035604 ==
3899 00:58:44.042296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3900 00:58:44.048553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3901 00:58:44.052238 [CA 0] Center 35 (5~66) winsize 62
3902 00:58:44.055314 [CA 1] Center 36 (5~67) winsize 63
3903 00:58:44.058991 [CA 2] Center 34 (3~65) winsize 63
3904 00:58:44.061910 [CA 3] Center 33 (3~64) winsize 62
3905 00:58:44.065447 [CA 4] Center 33 (2~64) winsize 63
3906 00:58:44.068389 [CA 5] Center 32 (2~63) winsize 62
3907 00:58:44.068473
3908 00:58:44.071607 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3909 00:58:44.071690
3910 00:58:44.075316 [CATrainingPosCal] consider 1 rank data
3911 00:58:44.078934 u2DelayCellTimex100 = 270/100 ps
3912 00:58:44.082027 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3913 00:58:44.084954 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3914 00:58:44.088792 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3915 00:58:44.091474 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3916 00:58:44.098284 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3917 00:58:44.101856 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3918 00:58:44.101939
3919 00:58:44.105432 CA PerBit enable=1, Macro0, CA PI delay=32
3920 00:58:44.105516
3921 00:58:44.108727 [CBTSetCACLKResult] CA Dly = 32
3922 00:58:44.108878 CS Dly: 4 (0~35)
3923 00:58:44.108971 ==
3924 00:58:44.111998 Dram Type= 6, Freq= 0, CH_0, rank 1
3925 00:58:44.118386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3926 00:58:44.118489 ==
3927 00:58:44.121384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3928 00:58:44.128316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3929 00:58:44.131500 [CA 0] Center 36 (5~67) winsize 63
3930 00:58:44.134783 [CA 1] Center 36 (5~67) winsize 63
3931 00:58:44.138049 [CA 2] Center 34 (3~65) winsize 63
3932 00:58:44.141712 [CA 3] Center 34 (3~65) winsize 63
3933 00:58:44.144865 [CA 4] Center 33 (2~64) winsize 63
3934 00:58:44.148304 [CA 5] Center 32 (2~63) winsize 62
3935 00:58:44.148391
3936 00:58:44.151243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3937 00:58:44.151328
3938 00:58:44.154822 [CATrainingPosCal] consider 2 rank data
3939 00:58:44.157752 u2DelayCellTimex100 = 270/100 ps
3940 00:58:44.161016 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3941 00:58:44.164774 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3942 00:58:44.171013 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3943 00:58:44.174840 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3944 00:58:44.177943 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3945 00:58:44.181543 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3946 00:58:44.181627
3947 00:58:44.184388 CA PerBit enable=1, Macro0, CA PI delay=32
3948 00:58:44.184472
3949 00:58:44.187862 [CBTSetCACLKResult] CA Dly = 32
3950 00:58:44.187947 CS Dly: 4 (0~36)
3951 00:58:44.188033
3952 00:58:44.191486 ----->DramcWriteLeveling(PI) begin...
3953 00:58:44.194866 ==
3954 00:58:44.198098 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 00:58:44.201287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 00:58:44.201370 ==
3957 00:58:44.204558 Write leveling (Byte 0): 35 => 35
3958 00:58:44.207624 Write leveling (Byte 1): 31 => 31
3959 00:58:44.211164 DramcWriteLeveling(PI) end<-----
3960 00:58:44.211245
3961 00:58:44.211308 ==
3962 00:58:44.214563 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 00:58:44.217599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 00:58:44.217681 ==
3965 00:58:44.221008 [Gating] SW mode calibration
3966 00:58:44.227451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3967 00:58:44.234309 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3968 00:58:44.237708 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 00:58:44.240901 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 00:58:44.244109 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3971 00:58:44.251136 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
3972 00:58:44.254114 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
3973 00:58:44.257309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 00:58:44.264169 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 00:58:44.267583 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 00:58:44.270847 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 00:58:44.277778 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 00:58:44.280426 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 00:58:44.284214 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
3980 00:58:44.290413 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3981 00:58:44.293721 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 00:58:44.297279 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 00:58:44.304538 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 00:58:44.307211 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 00:58:44.310307 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 00:58:44.317201 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 00:58:44.320669 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3988 00:58:44.323629 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3989 00:58:44.330198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 00:58:44.333827 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 00:58:44.336978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 00:58:44.343359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 00:58:44.346815 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 00:58:44.350572 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:58:44.356839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:58:44.360007 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:58:44.363799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:58:44.370349 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:58:44.373530 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:58:44.376966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:58:44.383449 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 00:58:44.386581 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 00:58:44.389957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 00:58:44.396786 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4005 00:58:44.396896 Total UI for P1: 0, mck2ui 16
4006 00:58:44.402984 best dqsien dly found for B0: ( 0, 13, 14)
4007 00:58:44.406660 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 00:58:44.409975 Total UI for P1: 0, mck2ui 16
4009 00:58:44.413169 best dqsien dly found for B1: ( 0, 13, 16)
4010 00:58:44.416681 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4011 00:58:44.419925 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4012 00:58:44.420006
4013 00:58:44.423174 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4014 00:58:44.426242 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4015 00:58:44.429677 [Gating] SW calibration Done
4016 00:58:44.429790 ==
4017 00:58:44.433315 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 00:58:44.436548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 00:58:44.440159 ==
4020 00:58:44.440266 RX Vref Scan: 0
4021 00:58:44.440396
4022 00:58:44.443031 RX Vref 0 -> 0, step: 1
4023 00:58:44.443111
4024 00:58:44.446820 RX Delay -230 -> 252, step: 16
4025 00:58:44.450028 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4026 00:58:44.453252 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4027 00:58:44.456397 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4028 00:58:44.459615 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4029 00:58:44.466082 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4030 00:58:44.469320 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4031 00:58:44.472963 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4032 00:58:44.475990 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4033 00:58:44.482936 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4034 00:58:44.486118 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4035 00:58:44.489266 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4036 00:58:44.492884 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4037 00:58:44.499594 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4038 00:58:44.503028 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4039 00:58:44.506113 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4040 00:58:44.509538 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4041 00:58:44.509635 ==
4042 00:58:44.513119 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 00:58:44.519812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 00:58:44.519894 ==
4045 00:58:44.519958 DQS Delay:
4046 00:58:44.520017 DQS0 = 0, DQS1 = 0
4047 00:58:44.522517 DQM Delay:
4048 00:58:44.522603 DQM0 = 49, DQM1 = 45
4049 00:58:44.525792 DQ Delay:
4050 00:58:44.529629 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4051 00:58:44.532847 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4052 00:58:44.535826 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4053 00:58:44.539348 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4054 00:58:44.539451
4055 00:58:44.539554
4056 00:58:44.539645 ==
4057 00:58:44.542304 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 00:58:44.545929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 00:58:44.546011 ==
4060 00:58:44.546076
4061 00:58:44.546134
4062 00:58:44.549145 TX Vref Scan disable
4063 00:58:44.552509 == TX Byte 0 ==
4064 00:58:44.555696 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4065 00:58:44.559471 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4066 00:58:44.559618 == TX Byte 1 ==
4067 00:58:44.565813 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4068 00:58:44.568920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4069 00:58:44.569025 ==
4070 00:58:44.572083 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 00:58:44.575824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 00:58:44.575921 ==
4073 00:58:44.578734
4074 00:58:44.578819
4075 00:58:44.578885 TX Vref Scan disable
4076 00:58:44.583000 == TX Byte 0 ==
4077 00:58:44.586197 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4078 00:58:44.589427 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4079 00:58:44.592598 == TX Byte 1 ==
4080 00:58:44.595844 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 00:58:44.602803 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 00:58:44.602938
4083 00:58:44.603007 [DATLAT]
4084 00:58:44.603082 Freq=600, CH0 RK0
4085 00:58:44.603144
4086 00:58:44.605953 DATLAT Default: 0x9
4087 00:58:44.606038 0, 0xFFFF, sum = 0
4088 00:58:44.609412 1, 0xFFFF, sum = 0
4089 00:58:44.609521 2, 0xFFFF, sum = 0
4090 00:58:44.612569 3, 0xFFFF, sum = 0
4091 00:58:44.616083 4, 0xFFFF, sum = 0
4092 00:58:44.616166 5, 0xFFFF, sum = 0
4093 00:58:44.619385 6, 0xFFFF, sum = 0
4094 00:58:44.619468 7, 0xFFFF, sum = 0
4095 00:58:44.622442 8, 0x0, sum = 1
4096 00:58:44.622525 9, 0x0, sum = 2
4097 00:58:44.622590 10, 0x0, sum = 3
4098 00:58:44.625700 11, 0x0, sum = 4
4099 00:58:44.625789 best_step = 9
4100 00:58:44.625875
4101 00:58:44.625956 ==
4102 00:58:44.628827 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 00:58:44.635937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 00:58:44.636082 ==
4105 00:58:44.636177 RX Vref Scan: 1
4106 00:58:44.636265
4107 00:58:44.639032 RX Vref 0 -> 0, step: 1
4108 00:58:44.639114
4109 00:58:44.642400 RX Delay -163 -> 252, step: 8
4110 00:58:44.642511
4111 00:58:44.646068 Set Vref, RX VrefLevel [Byte0]: 57
4112 00:58:44.649157 [Byte1]: 49
4113 00:58:44.649239
4114 00:58:44.652501 Final RX Vref Byte 0 = 57 to rank0
4115 00:58:44.655962 Final RX Vref Byte 1 = 49 to rank0
4116 00:58:44.659100 Final RX Vref Byte 0 = 57 to rank1
4117 00:58:44.662547 Final RX Vref Byte 1 = 49 to rank1==
4118 00:58:44.666282 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 00:58:44.669232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 00:58:44.669322 ==
4121 00:58:44.672429 DQS Delay:
4122 00:58:44.672525 DQS0 = 0, DQS1 = 0
4123 00:58:44.672632 DQM Delay:
4124 00:58:44.675551 DQM0 = 53, DQM1 = 47
4125 00:58:44.675671 DQ Delay:
4126 00:58:44.679456 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4127 00:58:44.682557 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4128 00:58:44.685475 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4129 00:58:44.688741 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4130 00:58:44.688838
4131 00:58:44.688924
4132 00:58:44.699084 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4133 00:58:44.702286 CH0 RK0: MR19=808, MR18=6E61
4134 00:58:44.705592 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4135 00:58:44.708812
4136 00:58:44.711858 ----->DramcWriteLeveling(PI) begin...
4137 00:58:44.711941 ==
4138 00:58:44.715768 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 00:58:44.718825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:58:44.718906 ==
4141 00:58:44.722048 Write leveling (Byte 0): 34 => 34
4142 00:58:44.725217 Write leveling (Byte 1): 31 => 31
4143 00:58:44.728853 DramcWriteLeveling(PI) end<-----
4144 00:58:44.728965
4145 00:58:44.729058 ==
4146 00:58:44.731860 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 00:58:44.735507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 00:58:44.735616 ==
4149 00:58:44.738525 [Gating] SW mode calibration
4150 00:58:44.745126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4151 00:58:44.751936 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4152 00:58:44.755493 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 00:58:44.758539 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 00:58:44.762495 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 00:58:44.768909 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4156 00:58:44.772221 0 9 16 | B1->B0 | 2b2b 2b2b | 1 1 | (1 0) (1 0)
4157 00:58:44.775510 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 00:58:44.782077 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 00:58:44.785546 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 00:58:44.788703 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 00:58:44.795526 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 00:58:44.798715 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 00:58:44.802027 0 10 12 | B1->B0 | 2828 2c2c | 0 1 | (0 0) (0 0)
4164 00:58:44.808457 0 10 16 | B1->B0 | 4040 3e3e | 0 1 | (0 0) (0 0)
4165 00:58:44.811784 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 00:58:44.815419 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 00:58:44.822330 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 00:58:44.824909 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 00:58:44.828196 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 00:58:44.835193 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 00:58:44.838159 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4172 00:58:44.841755 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4173 00:58:44.848589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 00:58:44.851704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 00:58:44.854791 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 00:58:44.861743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 00:58:44.865032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 00:58:44.868367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 00:58:44.875050 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 00:58:44.878683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:58:44.881931 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:58:44.887910 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 00:58:44.891383 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 00:58:44.894993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 00:58:44.901404 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 00:58:44.904704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 00:58:44.908258 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4188 00:58:44.911701 Total UI for P1: 0, mck2ui 16
4189 00:58:44.914949 best dqsien dly found for B0: ( 0, 13, 10)
4190 00:58:44.918154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 00:58:44.921402 Total UI for P1: 0, mck2ui 16
4192 00:58:44.924555 best dqsien dly found for B1: ( 0, 13, 12)
4193 00:58:44.931076 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4194 00:58:44.934187 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4195 00:58:44.934296
4196 00:58:44.937870 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4197 00:58:44.941078 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4198 00:58:44.944232 [Gating] SW calibration Done
4199 00:58:44.944347 ==
4200 00:58:44.947765 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 00:58:44.951232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 00:58:44.951348 ==
4203 00:58:44.954210 RX Vref Scan: 0
4204 00:58:44.954333
4205 00:58:44.954427 RX Vref 0 -> 0, step: 1
4206 00:58:44.954522
4207 00:58:44.958231 RX Delay -230 -> 252, step: 16
4208 00:58:44.961342 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4209 00:58:44.967477 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4210 00:58:44.970713 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4211 00:58:44.974358 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4212 00:58:44.977860 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4213 00:58:44.984214 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4214 00:58:44.987266 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4215 00:58:44.990659 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4216 00:58:44.994083 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4217 00:58:44.997340 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4218 00:58:45.004075 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4219 00:58:45.007505 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4220 00:58:45.011063 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4221 00:58:45.013908 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4222 00:58:45.020991 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4223 00:58:45.023799 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4224 00:58:45.023884 ==
4225 00:58:45.027501 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 00:58:45.030733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 00:58:45.030823 ==
4228 00:58:45.034085 DQS Delay:
4229 00:58:45.034169 DQS0 = 0, DQS1 = 0
4230 00:58:45.037305 DQM Delay:
4231 00:58:45.037389 DQM0 = 52, DQM1 = 44
4232 00:58:45.037474 DQ Delay:
4233 00:58:45.040532 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4234 00:58:45.043612 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4235 00:58:45.046953 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4236 00:58:45.050197 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4237 00:58:45.050278
4238 00:58:45.050342
4239 00:58:45.053852 ==
4240 00:58:45.053933 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 00:58:45.059994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 00:58:45.060075 ==
4243 00:58:45.060138
4244 00:58:45.060197
4245 00:58:45.063393 TX Vref Scan disable
4246 00:58:45.063473 == TX Byte 0 ==
4247 00:58:45.066763 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4248 00:58:45.073562 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4249 00:58:45.073643 == TX Byte 1 ==
4250 00:58:45.076963 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4251 00:58:45.083505 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4252 00:58:45.083586 ==
4253 00:58:45.086720 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 00:58:45.090020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 00:58:45.090105 ==
4256 00:58:45.090169
4257 00:58:45.090228
4258 00:58:45.093510 TX Vref Scan disable
4259 00:58:45.096490 == TX Byte 0 ==
4260 00:58:45.099707 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4261 00:58:45.103111 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4262 00:58:45.106349 == TX Byte 1 ==
4263 00:58:45.109645 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4264 00:58:45.113380 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4265 00:58:45.113485
4266 00:58:45.116535 [DATLAT]
4267 00:58:45.116641 Freq=600, CH0 RK1
4268 00:58:45.116734
4269 00:58:45.119536 DATLAT Default: 0x9
4270 00:58:45.119636 0, 0xFFFF, sum = 0
4271 00:58:45.123159 1, 0xFFFF, sum = 0
4272 00:58:45.123261 2, 0xFFFF, sum = 0
4273 00:58:45.126707 3, 0xFFFF, sum = 0
4274 00:58:45.126825 4, 0xFFFF, sum = 0
4275 00:58:45.129799 5, 0xFFFF, sum = 0
4276 00:58:45.129906 6, 0xFFFF, sum = 0
4277 00:58:45.133325 7, 0xFFFF, sum = 0
4278 00:58:45.133431 8, 0x0, sum = 1
4279 00:58:45.136556 9, 0x0, sum = 2
4280 00:58:45.136660 10, 0x0, sum = 3
4281 00:58:45.139881 11, 0x0, sum = 4
4282 00:58:45.139997 best_step = 9
4283 00:58:45.140100
4284 00:58:45.140193 ==
4285 00:58:45.142980 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 00:58:45.149983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 00:58:45.150083 ==
4288 00:58:45.150180 RX Vref Scan: 0
4289 00:58:45.150273
4290 00:58:45.153465 RX Vref 0 -> 0, step: 1
4291 00:58:45.153558
4292 00:58:45.156070 RX Delay -163 -> 252, step: 8
4293 00:58:45.159344 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4294 00:58:45.163099 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4295 00:58:45.169339 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4296 00:58:45.172667 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4297 00:58:45.176371 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4298 00:58:45.179461 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4299 00:58:45.182701 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4300 00:58:45.189298 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4301 00:58:45.192597 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4302 00:58:45.196372 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4303 00:58:45.199568 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4304 00:58:45.202869 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4305 00:58:45.209509 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4306 00:58:45.213143 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4307 00:58:45.215993 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4308 00:58:45.219294 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4309 00:58:45.219393 ==
4310 00:58:45.222575 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 00:58:45.229429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 00:58:45.229540 ==
4313 00:58:45.229603 DQS Delay:
4314 00:58:45.233014 DQS0 = 0, DQS1 = 0
4315 00:58:45.233095 DQM Delay:
4316 00:58:45.233158 DQM0 = 53, DQM1 = 46
4317 00:58:45.235990 DQ Delay:
4318 00:58:45.239382 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4319 00:58:45.242699 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4320 00:58:45.245715 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4321 00:58:45.249298 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4322 00:58:45.249397
4323 00:58:45.249491
4324 00:58:45.256056 [DQSOSCAuto] RK1, (LSB)MR18= 0x6829, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4325 00:58:45.259387 CH0 RK1: MR19=808, MR18=6829
4326 00:58:45.266032 CH0_RK1: MR19=0x808, MR18=0x6829, DQSOSC=390, MR23=63, INC=172, DEC=114
4327 00:58:45.269221 [RxdqsGatingPostProcess] freq 600
4328 00:58:45.272446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4329 00:58:45.276043 Pre-setting of DQS Precalculation
4330 00:58:45.282451 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4331 00:58:45.282559 ==
4332 00:58:45.285619 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 00:58:45.288910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 00:58:45.288989 ==
4335 00:58:45.296004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4336 00:58:45.302447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4337 00:58:45.305733 [CA 0] Center 36 (5~67) winsize 63
4338 00:58:45.309032 [CA 1] Center 36 (5~67) winsize 63
4339 00:58:45.312173 [CA 2] Center 34 (4~65) winsize 62
4340 00:58:45.315983 [CA 3] Center 34 (4~65) winsize 62
4341 00:58:45.319343 [CA 4] Center 34 (4~65) winsize 62
4342 00:58:45.322453 [CA 5] Center 34 (3~65) winsize 63
4343 00:58:45.322555
4344 00:58:45.325658 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4345 00:58:45.325740
4346 00:58:45.329125 [CATrainingPosCal] consider 1 rank data
4347 00:58:45.332056 u2DelayCellTimex100 = 270/100 ps
4348 00:58:45.335444 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4349 00:58:45.339001 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4350 00:58:45.342329 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4351 00:58:45.345784 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4352 00:58:45.349177 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 00:58:45.352068 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4354 00:58:45.352152
4355 00:58:45.355267 CA PerBit enable=1, Macro0, CA PI delay=34
4356 00:58:45.358547
4357 00:58:45.358630 [CBTSetCACLKResult] CA Dly = 34
4358 00:58:45.362298 CS Dly: 4 (0~35)
4359 00:58:45.362382 ==
4360 00:58:45.365392 Dram Type= 6, Freq= 0, CH_1, rank 1
4361 00:58:45.368831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 00:58:45.368915 ==
4363 00:58:45.375745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4364 00:58:45.382339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4365 00:58:45.385578 [CA 0] Center 36 (5~67) winsize 63
4366 00:58:45.388643 [CA 1] Center 36 (5~67) winsize 63
4367 00:58:45.392293 [CA 2] Center 34 (4~65) winsize 62
4368 00:58:45.395671 [CA 3] Center 34 (4~65) winsize 62
4369 00:58:45.398841 [CA 4] Center 34 (4~65) winsize 62
4370 00:58:45.402012 [CA 5] Center 34 (3~65) winsize 63
4371 00:58:45.402095
4372 00:58:45.405281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4373 00:58:45.405365
4374 00:58:45.408482 [CATrainingPosCal] consider 2 rank data
4375 00:58:45.411765 u2DelayCellTimex100 = 270/100 ps
4376 00:58:45.415678 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4377 00:58:45.418825 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4378 00:58:45.421978 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 00:58:45.425322 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4380 00:58:45.428576 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 00:58:45.432452 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4382 00:58:45.432536
4383 00:58:45.438944 CA PerBit enable=1, Macro0, CA PI delay=34
4384 00:58:45.439027
4385 00:58:45.439112 [CBTSetCACLKResult] CA Dly = 34
4386 00:58:45.442163 CS Dly: 5 (0~38)
4387 00:58:45.442246
4388 00:58:45.445260 ----->DramcWriteLeveling(PI) begin...
4389 00:58:45.445345 ==
4390 00:58:45.448711 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 00:58:45.452040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 00:58:45.452125 ==
4393 00:58:45.455383 Write leveling (Byte 0): 28 => 28
4394 00:58:45.458540 Write leveling (Byte 1): 30 => 30
4395 00:58:45.461595 DramcWriteLeveling(PI) end<-----
4396 00:58:45.461678
4397 00:58:45.461763 ==
4398 00:58:45.465141 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 00:58:45.471560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 00:58:45.471645 ==
4401 00:58:45.471730 [Gating] SW mode calibration
4402 00:58:45.481776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4403 00:58:45.485193 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4404 00:58:45.488172 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 00:58:45.494800 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 00:58:45.498548 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 00:58:45.501395 0 9 12 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (1 0)
4408 00:58:45.508379 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 00:58:45.511658 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 00:58:45.514905 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 00:58:45.521481 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 00:58:45.524652 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 00:58:45.527982 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 00:58:45.534453 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4415 00:58:45.538317 0 10 12 | B1->B0 | 3535 3a3a | 0 0 | (0 0) (1 1)
4416 00:58:45.541596 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 00:58:45.548105 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 00:58:45.551385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 00:58:45.554777 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 00:58:45.561428 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 00:58:45.565156 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 00:58:45.568220 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 00:58:45.574929 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4424 00:58:45.578366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 00:58:45.581567 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:58:45.584999 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:58:45.591652 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:58:45.594707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:58:45.597983 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:58:45.604825 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:58:45.607991 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:58:45.611595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:58:45.617935 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:58:45.621342 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:58:45.626052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 00:58:45.631338 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 00:58:45.634572 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 00:58:45.637791 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 00:58:45.644564 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4440 00:58:45.644648 Total UI for P1: 0, mck2ui 16
4441 00:58:45.651026 best dqsien dly found for B0: ( 0, 13, 10)
4442 00:58:45.654339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 00:58:45.658252 Total UI for P1: 0, mck2ui 16
4444 00:58:45.661524 best dqsien dly found for B1: ( 0, 13, 12)
4445 00:58:45.664777 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4446 00:58:45.668052 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4447 00:58:45.668132
4448 00:58:45.671341 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4449 00:58:45.674458 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4450 00:58:45.678115 [Gating] SW calibration Done
4451 00:58:45.678196 ==
4452 00:58:45.681389 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 00:58:45.684682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 00:58:45.687936 ==
4455 00:58:45.688016 RX Vref Scan: 0
4456 00:58:45.688079
4457 00:58:45.691208 RX Vref 0 -> 0, step: 1
4458 00:58:45.691288
4459 00:58:45.694355 RX Delay -230 -> 252, step: 16
4460 00:58:45.697452 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4461 00:58:45.701154 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4462 00:58:45.704384 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4463 00:58:45.710651 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4464 00:58:45.714029 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4465 00:58:45.718006 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4466 00:58:45.720596 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4467 00:58:45.724255 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4468 00:58:45.730894 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4469 00:58:45.734420 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4470 00:58:45.737636 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4471 00:58:45.740863 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4472 00:58:45.747825 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4473 00:58:45.751239 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4474 00:58:45.754223 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4475 00:58:45.757733 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4476 00:58:45.757815 ==
4477 00:58:45.761003 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 00:58:45.767676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 00:58:45.767758 ==
4480 00:58:45.767821 DQS Delay:
4481 00:58:45.770933 DQS0 = 0, DQS1 = 0
4482 00:58:45.771014 DQM Delay:
4483 00:58:45.771077 DQM0 = 50, DQM1 = 46
4484 00:58:45.774180 DQ Delay:
4485 00:58:45.777422 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4486 00:58:45.780747 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4487 00:58:45.784407 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4488 00:58:45.787622 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4489 00:58:45.787702
4490 00:58:45.787793
4491 00:58:45.787857 ==
4492 00:58:45.790921 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 00:58:45.794013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 00:58:45.794094 ==
4495 00:58:45.794158
4496 00:58:45.794217
4497 00:58:45.797752 TX Vref Scan disable
4498 00:58:45.797833 == TX Byte 0 ==
4499 00:58:45.804155 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4500 00:58:45.807387 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4501 00:58:45.807468 == TX Byte 1 ==
4502 00:58:45.813830 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4503 00:58:45.817743 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4504 00:58:45.817825 ==
4505 00:58:45.821114 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 00:58:45.823998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 00:58:45.824080 ==
4508 00:58:45.824144
4509 00:58:45.827304
4510 00:58:45.827453 TX Vref Scan disable
4511 00:58:45.830579 == TX Byte 0 ==
4512 00:58:45.834359 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4513 00:58:45.837286 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4514 00:58:45.840775 == TX Byte 1 ==
4515 00:58:45.844491 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 00:58:45.850945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 00:58:45.851027
4518 00:58:45.851091 [DATLAT]
4519 00:58:45.851150 Freq=600, CH1 RK0
4520 00:58:45.851209
4521 00:58:45.854109 DATLAT Default: 0x9
4522 00:58:45.854190 0, 0xFFFF, sum = 0
4523 00:58:45.857249 1, 0xFFFF, sum = 0
4524 00:58:45.857371 2, 0xFFFF, sum = 0
4525 00:58:45.860985 3, 0xFFFF, sum = 0
4526 00:58:45.864005 4, 0xFFFF, sum = 0
4527 00:58:45.864102 5, 0xFFFF, sum = 0
4528 00:58:45.867307 6, 0xFFFF, sum = 0
4529 00:58:45.867422 7, 0xFFFF, sum = 0
4530 00:58:45.870728 8, 0x0, sum = 1
4531 00:58:45.870811 9, 0x0, sum = 2
4532 00:58:45.870906 10, 0x0, sum = 3
4533 00:58:45.873811 11, 0x0, sum = 4
4534 00:58:45.873936 best_step = 9
4535 00:58:45.874014
4536 00:58:45.874072 ==
4537 00:58:45.877092 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 00:58:45.883748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 00:58:45.883830 ==
4540 00:58:45.883894 RX Vref Scan: 1
4541 00:58:45.883953
4542 00:58:45.886911 RX Vref 0 -> 0, step: 1
4543 00:58:45.886992
4544 00:58:45.890631 RX Delay -163 -> 252, step: 8
4545 00:58:45.890712
4546 00:58:45.893982 Set Vref, RX VrefLevel [Byte0]: 56
4547 00:58:45.897205 [Byte1]: 47
4548 00:58:45.897303
4549 00:58:45.900351 Final RX Vref Byte 0 = 56 to rank0
4550 00:58:45.903586 Final RX Vref Byte 1 = 47 to rank0
4551 00:58:45.907284 Final RX Vref Byte 0 = 56 to rank1
4552 00:58:45.910691 Final RX Vref Byte 1 = 47 to rank1==
4553 00:58:45.913964 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 00:58:45.917163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 00:58:45.917245 ==
4556 00:58:45.920239 DQS Delay:
4557 00:58:45.920369 DQS0 = 0, DQS1 = 0
4558 00:58:45.923564 DQM Delay:
4559 00:58:45.923645 DQM0 = 49, DQM1 = 46
4560 00:58:45.923709 DQ Delay:
4561 00:58:45.926940 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4562 00:58:45.930645 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4563 00:58:45.933829 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4564 00:58:45.936960 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4565 00:58:45.937041
4566 00:58:45.937104
4567 00:58:45.946612 [DQSOSCAuto] RK0, (LSB)MR18= 0x476d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4568 00:58:45.950209 CH1 RK0: MR19=808, MR18=476D
4569 00:58:45.953705 CH1_RK0: MR19=0x808, MR18=0x476D, DQSOSC=389, MR23=63, INC=173, DEC=115
4570 00:58:45.956540
4571 00:58:45.960184 ----->DramcWriteLeveling(PI) begin...
4572 00:58:45.960329 ==
4573 00:58:45.963834 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 00:58:45.967208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 00:58:45.967289 ==
4576 00:58:45.970427 Write leveling (Byte 0): 28 => 28
4577 00:58:45.973744 Write leveling (Byte 1): 30 => 30
4578 00:58:45.976911 DramcWriteLeveling(PI) end<-----
4579 00:58:45.976992
4580 00:58:45.977056 ==
4581 00:58:45.979958 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 00:58:45.983508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 00:58:45.983591 ==
4584 00:58:45.986774 [Gating] SW mode calibration
4585 00:58:45.993591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4586 00:58:46.000193 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4587 00:58:46.003521 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 00:58:46.006579 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 00:58:46.013130 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 00:58:46.016469 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (1 1) (0 1)
4591 00:58:46.019733 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 00:58:46.026760 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 00:58:46.029938 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 00:58:46.033134 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 00:58:46.040212 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 00:58:46.043228 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 00:58:46.046250 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 00:58:46.052733 0 10 12 | B1->B0 | 3b3b 3535 | 0 0 | (0 0) (0 0)
4599 00:58:46.056636 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 00:58:46.059624 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 00:58:46.063176 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 00:58:46.069686 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 00:58:46.072868 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 00:58:46.076405 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 00:58:46.082731 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4606 00:58:46.086083 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4607 00:58:46.089372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 00:58:46.095891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 00:58:46.099708 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 00:58:46.102568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 00:58:46.110131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 00:58:46.112605 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 00:58:46.115730 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 00:58:46.122450 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 00:58:46.125929 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:58:46.128979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:58:46.136135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 00:58:46.139245 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 00:58:46.142384 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 00:58:46.149548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 00:58:46.152728 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 00:58:46.155831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:58:46.159082 Total UI for P1: 0, mck2ui 16
4624 00:58:46.162288 best dqsien dly found for B0: ( 0, 13, 10)
4625 00:58:46.165774 Total UI for P1: 0, mck2ui 16
4626 00:58:46.169484 best dqsien dly found for B1: ( 0, 13, 10)
4627 00:58:46.172760 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4628 00:58:46.176012 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4629 00:58:46.176110
4630 00:58:46.182548 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4631 00:58:46.185945 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4632 00:58:46.186046 [Gating] SW calibration Done
4633 00:58:46.189233 ==
4634 00:58:46.192226 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 00:58:46.195714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 00:58:46.195811 ==
4637 00:58:46.195903 RX Vref Scan: 0
4638 00:58:46.195989
4639 00:58:46.198973 RX Vref 0 -> 0, step: 1
4640 00:58:46.199068
4641 00:58:46.202274 RX Delay -230 -> 252, step: 16
4642 00:58:46.205634 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4643 00:58:46.208966 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4644 00:58:46.215365 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4645 00:58:46.219104 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4646 00:58:46.222211 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4647 00:58:46.225609 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4648 00:58:46.232271 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4649 00:58:46.235437 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4650 00:58:46.239019 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4651 00:58:46.242283 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4652 00:58:46.245522 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4653 00:58:46.252234 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4654 00:58:46.255494 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4655 00:58:46.259008 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4656 00:58:46.262026 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4657 00:58:46.268982 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4658 00:58:46.269063 ==
4659 00:58:46.272163 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 00:58:46.275717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 00:58:46.275801 ==
4662 00:58:46.275866 DQS Delay:
4663 00:58:46.278887 DQS0 = 0, DQS1 = 0
4664 00:58:46.278968 DQM Delay:
4665 00:58:46.282238 DQM0 = 45, DQM1 = 46
4666 00:58:46.282320 DQ Delay:
4667 00:58:46.285416 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4668 00:58:46.289320 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4669 00:58:46.292363 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4670 00:58:46.296083 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4671 00:58:46.296192
4672 00:58:46.296292
4673 00:58:46.296362 ==
4674 00:58:46.299024 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 00:58:46.302405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 00:58:46.302489 ==
4677 00:58:46.302554
4678 00:58:46.305835
4679 00:58:46.305918 TX Vref Scan disable
4680 00:58:46.309095 == TX Byte 0 ==
4681 00:58:46.312375 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4682 00:58:46.315744 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4683 00:58:46.318926 == TX Byte 1 ==
4684 00:58:46.322243 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4685 00:58:46.325564 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4686 00:58:46.325654 ==
4687 00:58:46.328693 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 00:58:46.335281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 00:58:46.335365 ==
4690 00:58:46.335431
4691 00:58:46.335512
4692 00:58:46.335574 TX Vref Scan disable
4693 00:58:46.339820 == TX Byte 0 ==
4694 00:58:46.343080 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4695 00:58:46.349605 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4696 00:58:46.349684 == TX Byte 1 ==
4697 00:58:46.352872 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 00:58:46.359743 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 00:58:46.359844
4700 00:58:46.359935 [DATLAT]
4701 00:58:46.360032 Freq=600, CH1 RK1
4702 00:58:46.360122
4703 00:58:46.363156 DATLAT Default: 0x9
4704 00:58:46.363253 0, 0xFFFF, sum = 0
4705 00:58:46.366134 1, 0xFFFF, sum = 0
4706 00:58:46.369331 2, 0xFFFF, sum = 0
4707 00:58:46.369431 3, 0xFFFF, sum = 0
4708 00:58:46.372888 4, 0xFFFF, sum = 0
4709 00:58:46.372972 5, 0xFFFF, sum = 0
4710 00:58:46.376211 6, 0xFFFF, sum = 0
4711 00:58:46.376303 7, 0xFFFF, sum = 0
4712 00:58:46.379414 8, 0x0, sum = 1
4713 00:58:46.379498 9, 0x0, sum = 2
4714 00:58:46.379564 10, 0x0, sum = 3
4715 00:58:46.382749 11, 0x0, sum = 4
4716 00:58:46.382833 best_step = 9
4717 00:58:46.382899
4718 00:58:46.382959 ==
4719 00:58:46.386058 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 00:58:46.392565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 00:58:46.392654 ==
4722 00:58:46.392719 RX Vref Scan: 0
4723 00:58:46.392780
4724 00:58:46.396152 RX Vref 0 -> 0, step: 1
4725 00:58:46.396261
4726 00:58:46.399175 RX Delay -163 -> 252, step: 8
4727 00:58:46.402904 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4728 00:58:46.409605 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4729 00:58:46.413025 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4730 00:58:46.415843 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4731 00:58:46.419390 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4732 00:58:46.422650 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4733 00:58:46.428961 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4734 00:58:46.432297 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4735 00:58:46.435653 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4736 00:58:46.439472 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4737 00:58:46.442776 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4738 00:58:46.449049 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4739 00:58:46.452315 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4740 00:58:46.456304 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4741 00:58:46.458995 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4742 00:58:46.466054 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4743 00:58:46.466138 ==
4744 00:58:46.469382 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 00:58:46.472590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 00:58:46.472674 ==
4747 00:58:46.472738 DQS Delay:
4748 00:58:46.475753 DQS0 = 0, DQS1 = 0
4749 00:58:46.475835 DQM Delay:
4750 00:58:46.479032 DQM0 = 48, DQM1 = 44
4751 00:58:46.479114 DQ Delay:
4752 00:58:46.482090 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4753 00:58:46.485768 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4754 00:58:46.489167 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4755 00:58:46.492302 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4756 00:58:46.492414
4757 00:58:46.492514
4758 00:58:46.499073 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4759 00:58:46.502035 CH1 RK1: MR19=808, MR18=6C24
4760 00:58:46.508614 CH1_RK1: MR19=0x808, MR18=0x6C24, DQSOSC=389, MR23=63, INC=173, DEC=115
4761 00:58:46.512239 [RxdqsGatingPostProcess] freq 600
4762 00:58:46.518714 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4763 00:58:46.522219 Pre-setting of DQS Precalculation
4764 00:58:46.525644 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4765 00:58:46.531910 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4766 00:58:46.539276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4767 00:58:46.539387
4768 00:58:46.539488
4769 00:58:46.542019 [Calibration Summary] 1200 Mbps
4770 00:58:46.545084 CH 0, Rank 0
4771 00:58:46.545191 SW Impedance : PASS
4772 00:58:46.548761 DUTY Scan : NO K
4773 00:58:46.551802 ZQ Calibration : PASS
4774 00:58:46.551915 Jitter Meter : NO K
4775 00:58:46.555776 CBT Training : PASS
4776 00:58:46.558957 Write leveling : PASS
4777 00:58:46.559053 RX DQS gating : PASS
4778 00:58:46.562286 RX DQ/DQS(RDDQC) : PASS
4779 00:58:46.565111 TX DQ/DQS : PASS
4780 00:58:46.565210 RX DATLAT : PASS
4781 00:58:46.568269 RX DQ/DQS(Engine): PASS
4782 00:58:46.571621 TX OE : NO K
4783 00:58:46.571719 All Pass.
4784 00:58:46.571808
4785 00:58:46.571914 CH 0, Rank 1
4786 00:58:46.574765 SW Impedance : PASS
4787 00:58:46.578528 DUTY Scan : NO K
4788 00:58:46.578639 ZQ Calibration : PASS
4789 00:58:46.581725 Jitter Meter : NO K
4790 00:58:46.581826 CBT Training : PASS
4791 00:58:46.584941 Write leveling : PASS
4792 00:58:46.588522 RX DQS gating : PASS
4793 00:58:46.588625 RX DQ/DQS(RDDQC) : PASS
4794 00:58:46.591704 TX DQ/DQS : PASS
4795 00:58:46.595066 RX DATLAT : PASS
4796 00:58:46.595167 RX DQ/DQS(Engine): PASS
4797 00:58:46.598379 TX OE : NO K
4798 00:58:46.598478 All Pass.
4799 00:58:46.598569
4800 00:58:46.601645 CH 1, Rank 0
4801 00:58:46.601744 SW Impedance : PASS
4802 00:58:46.605020 DUTY Scan : NO K
4803 00:58:46.608210 ZQ Calibration : PASS
4804 00:58:46.608341 Jitter Meter : NO K
4805 00:58:46.611427 CBT Training : PASS
4806 00:58:46.614732 Write leveling : PASS
4807 00:58:46.614832 RX DQS gating : PASS
4808 00:58:46.617925 RX DQ/DQS(RDDQC) : PASS
4809 00:58:46.621636 TX DQ/DQS : PASS
4810 00:58:46.621734 RX DATLAT : PASS
4811 00:58:46.624783 RX DQ/DQS(Engine): PASS
4812 00:58:46.624890 TX OE : NO K
4813 00:58:46.628439 All Pass.
4814 00:58:46.628535
4815 00:58:46.628633 CH 1, Rank 1
4816 00:58:46.631694 SW Impedance : PASS
4817 00:58:46.634933 DUTY Scan : NO K
4818 00:58:46.635032 ZQ Calibration : PASS
4819 00:58:46.637951 Jitter Meter : NO K
4820 00:58:46.638048 CBT Training : PASS
4821 00:58:46.641364 Write leveling : PASS
4822 00:58:46.644752 RX DQS gating : PASS
4823 00:58:46.644858 RX DQ/DQS(RDDQC) : PASS
4824 00:58:46.647986 TX DQ/DQS : PASS
4825 00:58:46.651421 RX DATLAT : PASS
4826 00:58:46.651521 RX DQ/DQS(Engine): PASS
4827 00:58:46.654402 TX OE : NO K
4828 00:58:46.654507 All Pass.
4829 00:58:46.654601
4830 00:58:46.658308 DramC Write-DBI off
4831 00:58:46.661570 PER_BANK_REFRESH: Hybrid Mode
4832 00:58:46.661679 TX_TRACKING: ON
4833 00:58:46.671164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4834 00:58:46.674796 [FAST_K] Save calibration result to emmc
4835 00:58:46.677804 dramc_set_vcore_voltage set vcore to 662500
4836 00:58:46.681151 Read voltage for 933, 3
4837 00:58:46.681234 Vio18 = 0
4838 00:58:46.681298 Vcore = 662500
4839 00:58:46.684812 Vdram = 0
4840 00:58:46.684894 Vddq = 0
4841 00:58:46.684959 Vmddr = 0
4842 00:58:46.691337 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4843 00:58:46.694541 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4844 00:58:46.698109 MEM_TYPE=3, freq_sel=17
4845 00:58:46.701477 sv_algorithm_assistance_LP4_1600
4846 00:58:46.704719 ============ PULL DRAM RESETB DOWN ============
4847 00:58:46.707999 ========== PULL DRAM RESETB DOWN end =========
4848 00:58:46.714607 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4849 00:58:46.717716 ===================================
4850 00:58:46.720815 LPDDR4 DRAM CONFIGURATION
4851 00:58:46.724117 ===================================
4852 00:58:46.724201 EX_ROW_EN[0] = 0x0
4853 00:58:46.727401 EX_ROW_EN[1] = 0x0
4854 00:58:46.727493 LP4Y_EN = 0x0
4855 00:58:46.731143 WORK_FSP = 0x0
4856 00:58:46.731275 WL = 0x3
4857 00:58:46.734153 RL = 0x3
4858 00:58:46.734248 BL = 0x2
4859 00:58:46.737348 RPST = 0x0
4860 00:58:46.737487 RD_PRE = 0x0
4861 00:58:46.741320 WR_PRE = 0x1
4862 00:58:46.741417 WR_PST = 0x0
4863 00:58:46.744533 DBI_WR = 0x0
4864 00:58:46.744622 DBI_RD = 0x0
4865 00:58:46.747731 OTF = 0x1
4866 00:58:46.750995 ===================================
4867 00:58:46.754198 ===================================
4868 00:58:46.754328 ANA top config
4869 00:58:46.757836 ===================================
4870 00:58:46.760924 DLL_ASYNC_EN = 0
4871 00:58:46.764302 ALL_SLAVE_EN = 1
4872 00:58:46.767797 NEW_RANK_MODE = 1
4873 00:58:46.767886 DLL_IDLE_MODE = 1
4874 00:58:46.771139 LP45_APHY_COMB_EN = 1
4875 00:58:46.774382 TX_ODT_DIS = 1
4876 00:58:46.777655 NEW_8X_MODE = 1
4877 00:58:46.781020 ===================================
4878 00:58:46.784121 ===================================
4879 00:58:46.787615 data_rate = 1866
4880 00:58:46.787705 CKR = 1
4881 00:58:46.790617 DQ_P2S_RATIO = 8
4882 00:58:46.793954 ===================================
4883 00:58:46.797612 CA_P2S_RATIO = 8
4884 00:58:46.801058 DQ_CA_OPEN = 0
4885 00:58:46.804084 DQ_SEMI_OPEN = 0
4886 00:58:46.807087 CA_SEMI_OPEN = 0
4887 00:58:46.807193 CA_FULL_RATE = 0
4888 00:58:46.810375 DQ_CKDIV4_EN = 1
4889 00:58:46.813565 CA_CKDIV4_EN = 1
4890 00:58:46.817235 CA_PREDIV_EN = 0
4891 00:58:46.820680 PH8_DLY = 0
4892 00:58:46.823764 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4893 00:58:46.823870 DQ_AAMCK_DIV = 4
4894 00:58:46.827057 CA_AAMCK_DIV = 4
4895 00:58:46.830412 CA_ADMCK_DIV = 4
4896 00:58:46.833746 DQ_TRACK_CA_EN = 0
4897 00:58:46.836911 CA_PICK = 933
4898 00:58:46.840799 CA_MCKIO = 933
4899 00:58:46.840903 MCKIO_SEMI = 0
4900 00:58:46.843586 PLL_FREQ = 3732
4901 00:58:46.846983 DQ_UI_PI_RATIO = 32
4902 00:58:46.850798 CA_UI_PI_RATIO = 0
4903 00:58:46.854086 ===================================
4904 00:58:46.857237 ===================================
4905 00:58:46.860522 memory_type:LPDDR4
4906 00:58:46.860605 GP_NUM : 10
4907 00:58:46.863821 SRAM_EN : 1
4908 00:58:46.866945 MD32_EN : 0
4909 00:58:46.870733 ===================================
4910 00:58:46.870829 [ANA_INIT] >>>>>>>>>>>>>>
4911 00:58:46.873894 <<<<<< [CONFIGURE PHASE]: ANA_TX
4912 00:58:46.877327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4913 00:58:46.880581 ===================================
4914 00:58:46.884104 data_rate = 1866,PCW = 0X8f00
4915 00:58:46.887184 ===================================
4916 00:58:46.890566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4917 00:58:46.897062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4918 00:58:46.900234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4919 00:58:46.906736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4920 00:58:46.909977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4921 00:58:46.913559 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4922 00:58:46.917073 [ANA_INIT] flow start
4923 00:58:46.917157 [ANA_INIT] PLL >>>>>>>>
4924 00:58:46.920337 [ANA_INIT] PLL <<<<<<<<
4925 00:58:46.923493 [ANA_INIT] MIDPI >>>>>>>>
4926 00:58:46.923601 [ANA_INIT] MIDPI <<<<<<<<
4927 00:58:46.926942 [ANA_INIT] DLL >>>>>>>>
4928 00:58:46.930192 [ANA_INIT] flow end
4929 00:58:46.933521 ============ LP4 DIFF to SE enter ============
4930 00:58:46.936984 ============ LP4 DIFF to SE exit ============
4931 00:58:46.940142 [ANA_INIT] <<<<<<<<<<<<<
4932 00:58:46.943581 [Flow] Enable top DCM control >>>>>
4933 00:58:46.946776 [Flow] Enable top DCM control <<<<<
4934 00:58:46.950038 Enable DLL master slave shuffle
4935 00:58:46.953421 ==============================================================
4936 00:58:46.957000 Gating Mode config
4937 00:58:46.960071 ==============================================================
4938 00:58:46.963250 Config description:
4939 00:58:46.973704 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4940 00:58:46.980139 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4941 00:58:46.983359 SELPH_MODE 0: By rank 1: By Phase
4942 00:58:46.990488 ==============================================================
4943 00:58:46.993405 GAT_TRACK_EN = 1
4944 00:58:46.996681 RX_GATING_MODE = 2
4945 00:58:46.999910 RX_GATING_TRACK_MODE = 2
4946 00:58:47.003227 SELPH_MODE = 1
4947 00:58:47.006349 PICG_EARLY_EN = 1
4948 00:58:47.006469 VALID_LAT_VALUE = 1
4949 00:58:47.012983 ==============================================================
4950 00:58:47.016261 Enter into Gating configuration >>>>
4951 00:58:47.020219 Exit from Gating configuration <<<<
4952 00:58:47.023419 Enter into DVFS_PRE_config >>>>>
4953 00:58:47.033405 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4954 00:58:47.036763 Exit from DVFS_PRE_config <<<<<
4955 00:58:47.039987 Enter into PICG configuration >>>>
4956 00:58:47.042727 Exit from PICG configuration <<<<
4957 00:58:47.046395 [RX_INPUT] configuration >>>>>
4958 00:58:47.049919 [RX_INPUT] configuration <<<<<
4959 00:58:47.056598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4960 00:58:47.059568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4961 00:58:47.066243 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 00:58:47.072990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 00:58:47.079190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4964 00:58:47.086082 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4965 00:58:47.089339 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4966 00:58:47.092641 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4967 00:58:47.096109 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4968 00:58:47.102312 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4969 00:58:47.106131 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4970 00:58:47.109348 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4971 00:58:47.112449 ===================================
4972 00:58:47.115746 LPDDR4 DRAM CONFIGURATION
4973 00:58:47.119056 ===================================
4974 00:58:47.119138 EX_ROW_EN[0] = 0x0
4975 00:58:47.122302 EX_ROW_EN[1] = 0x0
4976 00:58:47.125761 LP4Y_EN = 0x0
4977 00:58:47.125841 WORK_FSP = 0x0
4978 00:58:47.128942 WL = 0x3
4979 00:58:47.129023 RL = 0x3
4980 00:58:47.132633 BL = 0x2
4981 00:58:47.132730 RPST = 0x0
4982 00:58:47.135690 RD_PRE = 0x0
4983 00:58:47.135773 WR_PRE = 0x1
4984 00:58:47.139443 WR_PST = 0x0
4985 00:58:47.139541 DBI_WR = 0x0
4986 00:58:47.142686 DBI_RD = 0x0
4987 00:58:47.142783 OTF = 0x1
4988 00:58:47.146037 ===================================
4989 00:58:47.149482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4990 00:58:47.155881 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4991 00:58:47.158832 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 00:58:47.162238 ===================================
4993 00:58:47.165442 LPDDR4 DRAM CONFIGURATION
4994 00:58:47.168720 ===================================
4995 00:58:47.168804 EX_ROW_EN[0] = 0x10
4996 00:58:47.172619 EX_ROW_EN[1] = 0x0
4997 00:58:47.172707 LP4Y_EN = 0x0
4998 00:58:47.175845 WORK_FSP = 0x0
4999 00:58:47.179174 WL = 0x3
5000 00:58:47.179278 RL = 0x3
5001 00:58:47.182395 BL = 0x2
5002 00:58:47.182477 RPST = 0x0
5003 00:58:47.185332 RD_PRE = 0x0
5004 00:58:47.185428 WR_PRE = 0x1
5005 00:58:47.188809 WR_PST = 0x0
5006 00:58:47.188889 DBI_WR = 0x0
5007 00:58:47.192164 DBI_RD = 0x0
5008 00:58:47.192246 OTF = 0x1
5009 00:58:47.195308 ===================================
5010 00:58:47.202520 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5011 00:58:47.206015 nWR fixed to 30
5012 00:58:47.209328 [ModeRegInit_LP4] CH0 RK0
5013 00:58:47.209408 [ModeRegInit_LP4] CH0 RK1
5014 00:58:47.212933 [ModeRegInit_LP4] CH1 RK0
5015 00:58:47.215968 [ModeRegInit_LP4] CH1 RK1
5016 00:58:47.216047 match AC timing 9
5017 00:58:47.222829 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5018 00:58:47.225702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5019 00:58:47.229299 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5020 00:58:47.235740 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5021 00:58:47.239484 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5022 00:58:47.239565 ==
5023 00:58:47.242693 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 00:58:47.245678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5025 00:58:47.245758 ==
5026 00:58:47.252255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5027 00:58:47.258829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5028 00:58:47.262054 [CA 0] Center 37 (6~68) winsize 63
5029 00:58:47.265900 [CA 1] Center 37 (7~68) winsize 62
5030 00:58:47.268928 [CA 2] Center 34 (4~65) winsize 62
5031 00:58:47.272323 [CA 3] Center 34 (3~65) winsize 63
5032 00:58:47.275475 [CA 4] Center 33 (3~64) winsize 62
5033 00:58:47.278695 [CA 5] Center 32 (2~62) winsize 61
5034 00:58:47.278775
5035 00:58:47.282585 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5036 00:58:47.282664
5037 00:58:47.285820 [CATrainingPosCal] consider 1 rank data
5038 00:58:47.289138 u2DelayCellTimex100 = 270/100 ps
5039 00:58:47.292330 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5040 00:58:47.295527 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5041 00:58:47.298770 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5042 00:58:47.301943 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5043 00:58:47.305285 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5044 00:58:47.312282 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5045 00:58:47.312420
5046 00:58:47.315343 CA PerBit enable=1, Macro0, CA PI delay=32
5047 00:58:47.315441
5048 00:58:47.318935 [CBTSetCACLKResult] CA Dly = 32
5049 00:58:47.319015 CS Dly: 5 (0~36)
5050 00:58:47.319078 ==
5051 00:58:47.321799 Dram Type= 6, Freq= 0, CH_0, rank 1
5052 00:58:47.325318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 00:58:47.328968 ==
5054 00:58:47.332221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 00:58:47.338554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5056 00:58:47.341945 [CA 0] Center 37 (6~68) winsize 63
5057 00:58:47.345083 [CA 1] Center 37 (7~68) winsize 62
5058 00:58:47.348900 [CA 2] Center 34 (4~65) winsize 62
5059 00:58:47.351771 [CA 3] Center 34 (3~65) winsize 63
5060 00:58:47.355253 [CA 4] Center 33 (3~64) winsize 62
5061 00:58:47.358488 [CA 5] Center 32 (2~62) winsize 61
5062 00:58:47.358592
5063 00:58:47.361683 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5064 00:58:47.361762
5065 00:58:47.365017 [CATrainingPosCal] consider 2 rank data
5066 00:58:47.368121 u2DelayCellTimex100 = 270/100 ps
5067 00:58:47.372097 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5068 00:58:47.375330 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5069 00:58:47.378452 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5070 00:58:47.384815 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5071 00:58:47.388660 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5072 00:58:47.391927 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5073 00:58:47.392006
5074 00:58:47.395121 CA PerBit enable=1, Macro0, CA PI delay=32
5075 00:58:47.395201
5076 00:58:47.398302 [CBTSetCACLKResult] CA Dly = 32
5077 00:58:47.398382 CS Dly: 5 (0~37)
5078 00:58:47.398446
5079 00:58:47.401464 ----->DramcWriteLeveling(PI) begin...
5080 00:58:47.401546 ==
5081 00:58:47.404766 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 00:58:47.411786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 00:58:47.411867 ==
5084 00:58:47.414992 Write leveling (Byte 0): 34 => 34
5085 00:58:47.418188 Write leveling (Byte 1): 29 => 29
5086 00:58:47.421321 DramcWriteLeveling(PI) end<-----
5087 00:58:47.421401
5088 00:58:47.421465 ==
5089 00:58:47.424680 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 00:58:47.427937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 00:58:47.428017 ==
5092 00:58:47.431559 [Gating] SW mode calibration
5093 00:58:47.437988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5094 00:58:47.441274 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5095 00:58:47.448037 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
5096 00:58:47.451397 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 00:58:47.454684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 00:58:47.461235 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 00:58:47.464929 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 00:58:47.467781 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 00:58:47.474547 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5102 00:58:47.477443 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 0)
5103 00:58:47.481240 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5104 00:58:47.487957 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 00:58:47.491052 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 00:58:47.494539 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 00:58:47.501187 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 00:58:47.504362 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 00:58:47.507584 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5110 00:58:47.514121 0 15 28 | B1->B0 | 2424 3838 | 0 1 | (0 0) (1 1)
5111 00:58:47.517344 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5112 00:58:47.521134 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 00:58:47.527605 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 00:58:47.530802 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 00:58:47.533945 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 00:58:47.540951 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 00:58:47.544266 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 00:58:47.547547 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5119 00:58:47.554007 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 00:58:47.557206 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 00:58:47.560359 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 00:58:47.567399 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 00:58:47.570462 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 00:58:47.573697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:58:47.580476 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:58:47.583727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:58:47.586873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:58:47.593832 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:58:47.596966 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:58:47.600337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:58:47.606845 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 00:58:47.610078 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 00:58:47.613513 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5134 00:58:47.620145 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5135 00:58:47.623369 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5136 00:58:47.627166 Total UI for P1: 0, mck2ui 16
5137 00:58:47.630375 best dqsien dly found for B0: ( 1, 2, 26)
5138 00:58:47.633707 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 00:58:47.637052 Total UI for P1: 0, mck2ui 16
5140 00:58:47.640321 best dqsien dly found for B1: ( 1, 3, 0)
5141 00:58:47.643360 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5142 00:58:47.646655 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5143 00:58:47.646735
5144 00:58:47.650552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5145 00:58:47.653851 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5146 00:58:47.656679 [Gating] SW calibration Done
5147 00:58:47.656759 ==
5148 00:58:47.660463 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 00:58:47.666957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 00:58:47.667038 ==
5151 00:58:47.667101 RX Vref Scan: 0
5152 00:58:47.667159
5153 00:58:47.670188 RX Vref 0 -> 0, step: 1
5154 00:58:47.670268
5155 00:58:47.673379 RX Delay -80 -> 252, step: 8
5156 00:58:47.676684 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5157 00:58:47.680325 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5158 00:58:47.683217 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5159 00:58:47.686909 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5160 00:58:47.693281 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5161 00:58:47.696521 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5162 00:58:47.699909 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5163 00:58:47.703194 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5164 00:58:47.706262 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5165 00:58:47.710002 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5166 00:58:47.716583 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5167 00:58:47.719891 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5168 00:58:47.722896 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5169 00:58:47.726467 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5170 00:58:47.729677 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5171 00:58:47.736513 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5172 00:58:47.736595 ==
5173 00:58:47.739802 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 00:58:47.743189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 00:58:47.743270 ==
5176 00:58:47.743334 DQS Delay:
5177 00:58:47.746355 DQS0 = 0, DQS1 = 0
5178 00:58:47.746436 DQM Delay:
5179 00:58:47.749457 DQM0 = 104, DQM1 = 95
5180 00:58:47.749537 DQ Delay:
5181 00:58:47.753465 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5182 00:58:47.756590 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5183 00:58:47.759830 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5184 00:58:47.763227 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5185 00:58:47.763307
5186 00:58:47.763370
5187 00:58:47.763428 ==
5188 00:58:47.766438 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 00:58:47.769732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 00:58:47.773043 ==
5191 00:58:47.773122
5192 00:58:47.773216
5193 00:58:47.773275 TX Vref Scan disable
5194 00:58:47.776290 == TX Byte 0 ==
5195 00:58:47.779484 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5196 00:58:47.782670 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5197 00:58:47.786233 == TX Byte 1 ==
5198 00:58:47.789915 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5199 00:58:47.792678 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5200 00:58:47.796432 ==
5201 00:58:47.796512 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 00:58:47.802821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 00:58:47.802902 ==
5204 00:58:47.802966
5205 00:58:47.803024
5206 00:58:47.806112 TX Vref Scan disable
5207 00:58:47.806192 == TX Byte 0 ==
5208 00:58:47.812993 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5209 00:58:47.816221 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5210 00:58:47.816366 == TX Byte 1 ==
5211 00:58:47.822823 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5212 00:58:47.826089 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5213 00:58:47.826169
5214 00:58:47.826232 [DATLAT]
5215 00:58:47.829319 Freq=933, CH0 RK0
5216 00:58:47.829399
5217 00:58:47.829462 DATLAT Default: 0xd
5218 00:58:47.832461 0, 0xFFFF, sum = 0
5219 00:58:47.832543 1, 0xFFFF, sum = 0
5220 00:58:47.836067 2, 0xFFFF, sum = 0
5221 00:58:47.836148 3, 0xFFFF, sum = 0
5222 00:58:47.839513 4, 0xFFFF, sum = 0
5223 00:58:47.839613 5, 0xFFFF, sum = 0
5224 00:58:47.842492 6, 0xFFFF, sum = 0
5225 00:58:47.842573 7, 0xFFFF, sum = 0
5226 00:58:47.845634 8, 0xFFFF, sum = 0
5227 00:58:47.849383 9, 0xFFFF, sum = 0
5228 00:58:47.849465 10, 0x0, sum = 1
5229 00:58:47.849529 11, 0x0, sum = 2
5230 00:58:47.852464 12, 0x0, sum = 3
5231 00:58:47.852546 13, 0x0, sum = 4
5232 00:58:47.855828 best_step = 11
5233 00:58:47.855908
5234 00:58:47.855970 ==
5235 00:58:47.858916 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 00:58:47.862511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 00:58:47.862592 ==
5238 00:58:47.865700 RX Vref Scan: 1
5239 00:58:47.865800
5240 00:58:47.865865 RX Vref 0 -> 0, step: 1
5241 00:58:47.865923
5242 00:58:47.869282 RX Delay -53 -> 252, step: 4
5243 00:58:47.869361
5244 00:58:47.872503 Set Vref, RX VrefLevel [Byte0]: 57
5245 00:58:47.875808 [Byte1]: 49
5246 00:58:47.879643
5247 00:58:47.879723 Final RX Vref Byte 0 = 57 to rank0
5248 00:58:47.883458 Final RX Vref Byte 1 = 49 to rank0
5249 00:58:47.886673 Final RX Vref Byte 0 = 57 to rank1
5250 00:58:47.889983 Final RX Vref Byte 1 = 49 to rank1==
5251 00:58:47.893091 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 00:58:47.899851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 00:58:47.899932 ==
5254 00:58:47.899996 DQS Delay:
5255 00:58:47.900055 DQS0 = 0, DQS1 = 0
5256 00:58:47.903482 DQM Delay:
5257 00:58:47.903562 DQM0 = 105, DQM1 = 95
5258 00:58:47.906651 DQ Delay:
5259 00:58:47.910257 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5260 00:58:47.913558 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5261 00:58:47.916726 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =90
5262 00:58:47.919877 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =102
5263 00:58:47.919957
5264 00:58:47.920019
5265 00:58:47.926572 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5266 00:58:47.929731 CH0 RK0: MR19=505, MR18=342C
5267 00:58:47.936882 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5268 00:58:47.936965
5269 00:58:47.939927 ----->DramcWriteLeveling(PI) begin...
5270 00:58:47.940010 ==
5271 00:58:47.943088 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 00:58:47.946585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 00:58:47.946693 ==
5274 00:58:47.949598 Write leveling (Byte 0): 34 => 34
5275 00:58:47.952757 Write leveling (Byte 1): 30 => 30
5276 00:58:47.956713 DramcWriteLeveling(PI) end<-----
5277 00:58:47.956794
5278 00:58:47.956857 ==
5279 00:58:47.959999 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 00:58:47.963335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 00:58:47.966371 ==
5282 00:58:47.966452 [Gating] SW mode calibration
5283 00:58:47.976401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5284 00:58:47.979558 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5285 00:58:47.982730 0 14 0 | B1->B0 | 3131 3030 | 0 1 | (0 0) (1 1)
5286 00:58:47.989526 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 00:58:47.992714 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 00:58:47.996416 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 00:58:48.002588 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 00:58:48.005811 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 00:58:48.009638 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
5292 00:58:48.016095 0 14 28 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (0 0)
5293 00:58:48.019269 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5294 00:58:48.022443 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 00:58:48.029481 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 00:58:48.032718 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 00:58:48.035954 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 00:58:48.042482 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 00:58:48.045738 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5300 00:58:48.049022 0 15 28 | B1->B0 | 3b3b 3a3a | 0 1 | (0 0) (0 0)
5301 00:58:48.055745 1 0 0 | B1->B0 | 4545 3e3e | 0 0 | (0 0) (0 0)
5302 00:58:48.059150 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 00:58:48.062489 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 00:58:48.069420 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 00:58:48.072692 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 00:58:48.075726 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 00:58:48.082774 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 00:58:48.086018 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5309 00:58:48.089283 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 00:58:48.095851 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 00:58:48.099009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 00:58:48.102475 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 00:58:48.109059 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 00:58:48.112470 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 00:58:48.115696 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 00:58:48.122577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 00:58:48.125658 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 00:58:48.128930 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:58:48.135219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:58:48.138526 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:58:48.141789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 00:58:48.145702 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 00:58:48.152178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 00:58:48.155391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5325 00:58:48.158708 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:58:48.162149 Total UI for P1: 0, mck2ui 16
5327 00:58:48.165277 best dqsien dly found for B0: ( 1, 2, 28)
5328 00:58:48.168850 Total UI for P1: 0, mck2ui 16
5329 00:58:48.171792 best dqsien dly found for B1: ( 1, 2, 28)
5330 00:58:48.175617 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5331 00:58:48.178687 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5332 00:58:48.178768
5333 00:58:48.185243 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5334 00:58:48.188925 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5335 00:58:48.192251 [Gating] SW calibration Done
5336 00:58:48.192339 ==
5337 00:58:48.195478 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 00:58:48.198800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 00:58:48.198881 ==
5340 00:58:48.198944 RX Vref Scan: 0
5341 00:58:48.199003
5342 00:58:48.201988 RX Vref 0 -> 0, step: 1
5343 00:58:48.202068
5344 00:58:48.205157 RX Delay -80 -> 252, step: 8
5345 00:58:48.208919 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5346 00:58:48.211798 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5347 00:58:48.218782 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5348 00:58:48.222011 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5349 00:58:48.225592 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5350 00:58:48.228613 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5351 00:58:48.232116 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5352 00:58:48.235074 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5353 00:58:48.242273 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5354 00:58:48.245324 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5355 00:58:48.248777 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5356 00:58:48.251683 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5357 00:58:48.255462 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5358 00:58:48.258777 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5359 00:58:48.265501 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5360 00:58:48.268759 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5361 00:58:48.268839 ==
5362 00:58:48.272026 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 00:58:48.275150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 00:58:48.275231 ==
5365 00:58:48.278902 DQS Delay:
5366 00:58:48.278982 DQS0 = 0, DQS1 = 0
5367 00:58:48.279045 DQM Delay:
5368 00:58:48.281995 DQM0 = 105, DQM1 = 93
5369 00:58:48.282075 DQ Delay:
5370 00:58:48.285542 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =99
5371 00:58:48.288672 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5372 00:58:48.291751 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5373 00:58:48.295417 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5374 00:58:48.295497
5375 00:58:48.295568
5376 00:58:48.295628 ==
5377 00:58:48.298842 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 00:58:48.305198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 00:58:48.305279 ==
5380 00:58:48.305342
5381 00:58:48.305400
5382 00:58:48.305456 TX Vref Scan disable
5383 00:58:48.309148 == TX Byte 0 ==
5384 00:58:48.312257 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5385 00:58:48.318861 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5386 00:58:48.318941 == TX Byte 1 ==
5387 00:58:48.322587 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5388 00:58:48.329325 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5389 00:58:48.329406 ==
5390 00:58:48.332282 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 00:58:48.335252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 00:58:48.335350 ==
5393 00:58:48.335415
5394 00:58:48.335474
5395 00:58:48.338844 TX Vref Scan disable
5396 00:58:48.338924 == TX Byte 0 ==
5397 00:58:48.345654 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5398 00:58:48.349067 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5399 00:58:48.349148 == TX Byte 1 ==
5400 00:58:48.355285 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5401 00:58:48.358966 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5402 00:58:48.359047
5403 00:58:48.359109 [DATLAT]
5404 00:58:48.362267 Freq=933, CH0 RK1
5405 00:58:48.362347
5406 00:58:48.362410 DATLAT Default: 0xb
5407 00:58:48.365760 0, 0xFFFF, sum = 0
5408 00:58:48.365843 1, 0xFFFF, sum = 0
5409 00:58:48.369252 2, 0xFFFF, sum = 0
5410 00:58:48.369340 3, 0xFFFF, sum = 0
5411 00:58:48.372525 4, 0xFFFF, sum = 0
5412 00:58:48.372633 5, 0xFFFF, sum = 0
5413 00:58:48.375254 6, 0xFFFF, sum = 0
5414 00:58:48.379209 7, 0xFFFF, sum = 0
5415 00:58:48.379291 8, 0xFFFF, sum = 0
5416 00:58:48.381950 9, 0xFFFF, sum = 0
5417 00:58:48.382059 10, 0x0, sum = 1
5418 00:58:48.382153 11, 0x0, sum = 2
5419 00:58:48.385124 12, 0x0, sum = 3
5420 00:58:48.385223 13, 0x0, sum = 4
5421 00:58:48.388995 best_step = 11
5422 00:58:48.389074
5423 00:58:48.389138 ==
5424 00:58:48.392054 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 00:58:48.395275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 00:58:48.395355 ==
5427 00:58:48.398823 RX Vref Scan: 0
5428 00:58:48.398903
5429 00:58:48.398966 RX Vref 0 -> 0, step: 1
5430 00:58:48.401847
5431 00:58:48.401926 RX Delay -53 -> 252, step: 4
5432 00:58:48.409086 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5433 00:58:48.412354 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5434 00:58:48.415709 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5435 00:58:48.418957 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5436 00:58:48.423076 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5437 00:58:48.429386 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5438 00:58:48.432591 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5439 00:58:48.435753 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5440 00:58:48.439186 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5441 00:58:48.442349 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5442 00:58:48.449575 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5443 00:58:48.452346 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5444 00:58:48.455995 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5445 00:58:48.459304 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5446 00:58:48.462715 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5447 00:58:48.469104 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5448 00:58:48.469183 ==
5449 00:58:48.472583 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 00:58:48.476000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 00:58:48.476080 ==
5452 00:58:48.476144 DQS Delay:
5453 00:58:48.479463 DQS0 = 0, DQS1 = 0
5454 00:58:48.479543 DQM Delay:
5455 00:58:48.482421 DQM0 = 105, DQM1 = 94
5456 00:58:48.482501 DQ Delay:
5457 00:58:48.485796 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5458 00:58:48.489648 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5459 00:58:48.492902 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =90
5460 00:58:48.495979 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =104
5461 00:58:48.496058
5462 00:58:48.496120
5463 00:58:48.505904 [DQSOSCAuto] RK1, (LSB)MR18= 0x2901, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5464 00:58:48.505985 CH0 RK1: MR19=505, MR18=2901
5465 00:58:48.512660 CH0_RK1: MR19=0x505, MR18=0x2901, DQSOSC=408, MR23=63, INC=65, DEC=43
5466 00:58:48.515755 [RxdqsGatingPostProcess] freq 933
5467 00:58:48.522861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5468 00:58:48.526078 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 00:58:48.529353 best DQS1 dly(2T, 0.5T) = (0, 11)
5470 00:58:48.532578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 00:58:48.535680 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5472 00:58:48.535780 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 00:58:48.539507 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 00:58:48.542588 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 00:58:48.545695 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 00:58:48.549298 Pre-setting of DQS Precalculation
5477 00:58:48.555952 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5478 00:58:48.556053 ==
5479 00:58:48.558907 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 00:58:48.562493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 00:58:48.562574 ==
5482 00:58:48.568947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5483 00:58:48.575489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5484 00:58:48.578700 [CA 0] Center 37 (6~68) winsize 63
5485 00:58:48.582394 [CA 1] Center 37 (6~68) winsize 63
5486 00:58:48.585334 [CA 2] Center 34 (4~65) winsize 62
5487 00:58:48.588871 [CA 3] Center 34 (4~65) winsize 62
5488 00:58:48.592527 [CA 4] Center 34 (4~65) winsize 62
5489 00:58:48.592608 [CA 5] Center 33 (3~64) winsize 62
5490 00:58:48.595513
5491 00:58:48.598747 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5492 00:58:48.598860
5493 00:58:48.602504 [CATrainingPosCal] consider 1 rank data
5494 00:58:48.605746 u2DelayCellTimex100 = 270/100 ps
5495 00:58:48.608750 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5496 00:58:48.611973 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5497 00:58:48.615334 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 00:58:48.619039 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5499 00:58:48.622085 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 00:58:48.625296 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5501 00:58:48.625377
5502 00:58:48.628462 CA PerBit enable=1, Macro0, CA PI delay=33
5503 00:58:48.628543
5504 00:58:48.632217 [CBTSetCACLKResult] CA Dly = 33
5505 00:58:48.635618 CS Dly: 6 (0~37)
5506 00:58:48.635699 ==
5507 00:58:48.638837 Dram Type= 6, Freq= 0, CH_1, rank 1
5508 00:58:48.642098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 00:58:48.642179 ==
5510 00:58:48.648780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 00:58:48.654962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 00:58:48.658490 [CA 0] Center 37 (6~68) winsize 63
5513 00:58:48.661682 [CA 1] Center 37 (7~68) winsize 62
5514 00:58:48.665516 [CA 2] Center 35 (4~66) winsize 63
5515 00:58:48.668531 [CA 3] Center 34 (4~65) winsize 62
5516 00:58:48.672107 [CA 4] Center 34 (4~65) winsize 62
5517 00:58:48.675315 [CA 5] Center 34 (4~64) winsize 61
5518 00:58:48.675398
5519 00:58:48.678482 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 00:58:48.678566
5521 00:58:48.681720 [CATrainingPosCal] consider 2 rank data
5522 00:58:48.684913 u2DelayCellTimex100 = 270/100 ps
5523 00:58:48.688084 CA0 delay=37 (6~68),Diff = 3 PI (18 cell)
5524 00:58:48.691833 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5525 00:58:48.694994 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5526 00:58:48.698717 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5527 00:58:48.701603 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5528 00:58:48.705153 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5529 00:58:48.705237
5530 00:58:48.708741 CA PerBit enable=1, Macro0, CA PI delay=34
5531 00:58:48.711534
5532 00:58:48.711617 [CBTSetCACLKResult] CA Dly = 34
5533 00:58:48.715034 CS Dly: 7 (0~40)
5534 00:58:48.715123
5535 00:58:48.718614 ----->DramcWriteLeveling(PI) begin...
5536 00:58:48.718735 ==
5537 00:58:48.721765 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 00:58:48.724967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 00:58:48.725054 ==
5540 00:58:48.728707 Write leveling (Byte 0): 26 => 26
5541 00:58:48.731970 Write leveling (Byte 1): 27 => 27
5542 00:58:48.735328 DramcWriteLeveling(PI) end<-----
5543 00:58:48.735405
5544 00:58:48.735502 ==
5545 00:58:48.738532 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 00:58:48.741801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 00:58:48.741886 ==
5548 00:58:48.744951 [Gating] SW mode calibration
5549 00:58:48.751957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 00:58:48.758140 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5551 00:58:48.762019 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 00:58:48.768523 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 00:58:48.771586 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 00:58:48.774840 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 00:58:48.781558 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 00:58:48.784847 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5557 00:58:48.788641 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5558 00:58:48.795194 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
5559 00:58:48.798388 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 00:58:48.801729 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 00:58:48.808148 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 00:58:48.811282 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 00:58:48.815006 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 00:58:48.818055 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 00:58:48.824547 0 15 24 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5566 00:58:48.828118 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5567 00:58:48.831575 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 00:58:48.837746 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 00:58:48.841424 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 00:58:48.844652 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 00:58:48.851068 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 00:58:48.854505 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5573 00:58:48.857567 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5574 00:58:48.864620 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 00:58:48.867793 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 00:58:48.871065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:58:48.877646 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:58:48.881286 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:58:48.884390 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 00:58:48.891133 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 00:58:48.894339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 00:58:48.897708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:58:48.904213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:58:48.907842 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:58:48.911041 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:58:48.918016 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:58:48.921086 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 00:58:48.924222 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 00:58:48.931171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5590 00:58:48.934342 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 00:58:48.937673 Total UI for P1: 0, mck2ui 16
5592 00:58:48.941397 best dqsien dly found for B0: ( 1, 2, 24)
5593 00:58:48.944445 Total UI for P1: 0, mck2ui 16
5594 00:58:48.947797 best dqsien dly found for B1: ( 1, 2, 24)
5595 00:58:48.951011 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5596 00:58:48.954474 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5597 00:58:48.954555
5598 00:58:48.957736 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5599 00:58:48.961180 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5600 00:58:48.964472 [Gating] SW calibration Done
5601 00:58:48.964553 ==
5602 00:58:48.967540 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 00:58:48.971317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 00:58:48.971397 ==
5605 00:58:48.974558 RX Vref Scan: 0
5606 00:58:48.974638
5607 00:58:48.977737 RX Vref 0 -> 0, step: 1
5608 00:58:48.977816
5609 00:58:48.977880 RX Delay -80 -> 252, step: 8
5610 00:58:48.984458 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5611 00:58:48.987522 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5612 00:58:48.991040 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5613 00:58:48.994126 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5614 00:58:48.997857 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5615 00:58:49.000849 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5616 00:58:49.007268 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5617 00:58:49.010975 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5618 00:58:49.014224 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5619 00:58:49.017575 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5620 00:58:49.020827 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5621 00:58:49.023982 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5622 00:58:49.030941 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5623 00:58:49.034040 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5624 00:58:49.037211 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5625 00:58:49.040698 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5626 00:58:49.040778 ==
5627 00:58:49.044324 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 00:58:49.051093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 00:58:49.051178 ==
5630 00:58:49.051241 DQS Delay:
5631 00:58:49.054407 DQS0 = 0, DQS1 = 0
5632 00:58:49.054488 DQM Delay:
5633 00:58:49.054551 DQM0 = 102, DQM1 = 98
5634 00:58:49.057532 DQ Delay:
5635 00:58:49.061231 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5636 00:58:49.064252 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5637 00:58:49.067389 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5638 00:58:49.070958 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5639 00:58:49.071038
5640 00:58:49.071101
5641 00:58:49.071159 ==
5642 00:58:49.074442 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 00:58:49.077624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 00:58:49.077704 ==
5645 00:58:49.077766
5646 00:58:49.077823
5647 00:58:49.080977 TX Vref Scan disable
5648 00:58:49.084120 == TX Byte 0 ==
5649 00:58:49.087199 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5650 00:58:49.090430 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5651 00:58:49.094226 == TX Byte 1 ==
5652 00:58:49.097282 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5653 00:58:49.100899 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5654 00:58:49.100979 ==
5655 00:58:49.104009 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 00:58:49.107021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 00:58:49.110677 ==
5658 00:58:49.110757
5659 00:58:49.110820
5660 00:58:49.110879 TX Vref Scan disable
5661 00:58:49.114122 == TX Byte 0 ==
5662 00:58:49.117500 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 00:58:49.121144 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 00:58:49.124441 == TX Byte 1 ==
5665 00:58:49.127627 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 00:58:49.130972 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 00:58:49.134140
5668 00:58:49.134219 [DATLAT]
5669 00:58:49.134297 Freq=933, CH1 RK0
5670 00:58:49.134374
5671 00:58:49.137719 DATLAT Default: 0xd
5672 00:58:49.137799 0, 0xFFFF, sum = 0
5673 00:58:49.140787 1, 0xFFFF, sum = 0
5674 00:58:49.140869 2, 0xFFFF, sum = 0
5675 00:58:49.144103 3, 0xFFFF, sum = 0
5676 00:58:49.144184 4, 0xFFFF, sum = 0
5677 00:58:49.147406 5, 0xFFFF, sum = 0
5678 00:58:49.150603 6, 0xFFFF, sum = 0
5679 00:58:49.150684 7, 0xFFFF, sum = 0
5680 00:58:49.153894 8, 0xFFFF, sum = 0
5681 00:58:49.153975 9, 0xFFFF, sum = 0
5682 00:58:49.157837 10, 0x0, sum = 1
5683 00:58:49.157918 11, 0x0, sum = 2
5684 00:58:49.157982 12, 0x0, sum = 3
5685 00:58:49.160981 13, 0x0, sum = 4
5686 00:58:49.161062 best_step = 11
5687 00:58:49.161125
5688 00:58:49.164163 ==
5689 00:58:49.164243 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 00:58:49.170549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 00:58:49.170630 ==
5692 00:58:49.170693 RX Vref Scan: 1
5693 00:58:49.170752
5694 00:58:49.174266 RX Vref 0 -> 0, step: 1
5695 00:58:49.174345
5696 00:58:49.177460 RX Delay -45 -> 252, step: 4
5697 00:58:49.177540
5698 00:58:49.180860 Set Vref, RX VrefLevel [Byte0]: 56
5699 00:58:49.184138 [Byte1]: 47
5700 00:58:49.184217
5701 00:58:49.187382 Final RX Vref Byte 0 = 56 to rank0
5702 00:58:49.191186 Final RX Vref Byte 1 = 47 to rank0
5703 00:58:49.193983 Final RX Vref Byte 0 = 56 to rank1
5704 00:58:49.197291 Final RX Vref Byte 1 = 47 to rank1==
5705 00:58:49.200416 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 00:58:49.203833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 00:58:49.203913 ==
5708 00:58:49.207544 DQS Delay:
5709 00:58:49.207624 DQS0 = 0, DQS1 = 0
5710 00:58:49.210768 DQM Delay:
5711 00:58:49.210848 DQM0 = 103, DQM1 = 99
5712 00:58:49.210911 DQ Delay:
5713 00:58:49.214096 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5714 00:58:49.217216 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5715 00:58:49.220696 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
5716 00:58:49.227458 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =108
5717 00:58:49.227537
5718 00:58:49.227600
5719 00:58:49.234059 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5720 00:58:49.237414 CH1 RK0: MR19=505, MR18=1931
5721 00:58:49.244177 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5722 00:58:49.244306
5723 00:58:49.247283 ----->DramcWriteLeveling(PI) begin...
5724 00:58:49.247364 ==
5725 00:58:49.250431 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 00:58:49.253917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 00:58:49.253997 ==
5728 00:58:49.257660 Write leveling (Byte 0): 27 => 27
5729 00:58:49.260862 Write leveling (Byte 1): 30 => 30
5730 00:58:49.264114 DramcWriteLeveling(PI) end<-----
5731 00:58:49.264197
5732 00:58:49.264260 ==
5733 00:58:49.267209 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 00:58:49.270509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 00:58:49.270590 ==
5736 00:58:49.273757 [Gating] SW mode calibration
5737 00:58:49.280462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5738 00:58:49.287047 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5739 00:58:49.290494 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 00:58:49.296925 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 00:58:49.300181 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 00:58:49.304086 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 00:58:49.306956 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 00:58:49.314046 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5745 00:58:49.316945 0 14 24 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 1)
5746 00:58:49.320467 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 00:58:49.327031 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 00:58:49.330340 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 00:58:49.333572 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 00:58:49.340359 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 00:58:49.343851 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 00:58:49.346720 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 00:58:49.353557 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
5754 00:58:49.356727 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5755 00:58:49.360361 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 00:58:49.366822 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 00:58:49.370071 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 00:58:49.373217 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 00:58:49.380256 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 00:58:49.383467 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 00:58:49.386534 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5762 00:58:49.393744 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5763 00:58:49.396973 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 00:58:49.400274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 00:58:49.406815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 00:58:49.410535 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 00:58:49.413461 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 00:58:49.419878 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 00:58:49.423472 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 00:58:49.426528 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 00:58:49.433430 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 00:58:49.436490 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:58:49.439689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:58:49.446225 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:58:49.449835 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:58:49.452855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 00:58:49.456359 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5778 00:58:49.462958 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 00:58:49.466526 Total UI for P1: 0, mck2ui 16
5780 00:58:49.469853 best dqsien dly found for B0: ( 1, 2, 24)
5781 00:58:49.472942 Total UI for P1: 0, mck2ui 16
5782 00:58:49.476251 best dqsien dly found for B1: ( 1, 2, 24)
5783 00:58:49.479741 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5784 00:58:49.482779 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5785 00:58:49.482863
5786 00:58:49.486034 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5787 00:58:49.489789 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5788 00:58:49.492950 [Gating] SW calibration Done
5789 00:58:49.493033 ==
5790 00:58:49.496218 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 00:58:49.499459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 00:58:49.499543 ==
5793 00:58:49.503286 RX Vref Scan: 0
5794 00:58:49.503369
5795 00:58:49.503454 RX Vref 0 -> 0, step: 1
5796 00:58:49.506598
5797 00:58:49.506681 RX Delay -80 -> 252, step: 8
5798 00:58:49.512956 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5799 00:58:49.516191 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5800 00:58:49.519470 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5801 00:58:49.522946 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5802 00:58:49.526132 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5803 00:58:49.529289 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5804 00:58:49.536060 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5805 00:58:49.539497 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5806 00:58:49.542709 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5807 00:58:49.546545 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5808 00:58:49.549744 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5809 00:58:49.552890 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5810 00:58:49.556056 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5811 00:58:49.562846 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5812 00:58:49.565935 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5813 00:58:49.569699 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5814 00:58:49.569782 ==
5815 00:58:49.572940 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 00:58:49.576126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 00:58:49.579156 ==
5818 00:58:49.579240 DQS Delay:
5819 00:58:49.579326 DQS0 = 0, DQS1 = 0
5820 00:58:49.582791 DQM Delay:
5821 00:58:49.582874 DQM0 = 101, DQM1 = 97
5822 00:58:49.586364 DQ Delay:
5823 00:58:49.589476 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5824 00:58:49.592856 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5825 00:58:49.596678 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5826 00:58:49.599352 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5827 00:58:49.599435
5828 00:58:49.599519
5829 00:58:49.599599 ==
5830 00:58:49.602456 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 00:58:49.605872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 00:58:49.605957 ==
5833 00:58:49.606041
5834 00:58:49.606120
5835 00:58:49.609609 TX Vref Scan disable
5836 00:58:49.612404 == TX Byte 0 ==
5837 00:58:49.616258 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5838 00:58:49.619600 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5839 00:58:49.619684 == TX Byte 1 ==
5840 00:58:49.626168 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5841 00:58:49.629221 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5842 00:58:49.629304 ==
5843 00:58:49.632872 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 00:58:49.636051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 00:58:49.636135 ==
5846 00:58:49.636234
5847 00:58:49.639656
5848 00:58:49.639738 TX Vref Scan disable
5849 00:58:49.642820 == TX Byte 0 ==
5850 00:58:49.645995 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5851 00:58:49.649220 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5852 00:58:49.652903 == TX Byte 1 ==
5853 00:58:49.656079 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5854 00:58:49.659260 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5855 00:58:49.662575
5856 00:58:49.662658 [DATLAT]
5857 00:58:49.662743 Freq=933, CH1 RK1
5858 00:58:49.662824
5859 00:58:49.665869 DATLAT Default: 0xb
5860 00:58:49.665970 0, 0xFFFF, sum = 0
5861 00:58:49.668908 1, 0xFFFF, sum = 0
5862 00:58:49.668993 2, 0xFFFF, sum = 0
5863 00:58:49.672652 3, 0xFFFF, sum = 0
5864 00:58:49.672737 4, 0xFFFF, sum = 0
5865 00:58:49.675869 5, 0xFFFF, sum = 0
5866 00:58:49.679022 6, 0xFFFF, sum = 0
5867 00:58:49.679107 7, 0xFFFF, sum = 0
5868 00:58:49.682321 8, 0xFFFF, sum = 0
5869 00:58:49.682406 9, 0xFFFF, sum = 0
5870 00:58:49.685555 10, 0x0, sum = 1
5871 00:58:49.685639 11, 0x0, sum = 2
5872 00:58:49.685724 12, 0x0, sum = 3
5873 00:58:49.688759 13, 0x0, sum = 4
5874 00:58:49.688843 best_step = 11
5875 00:58:49.688927
5876 00:58:49.692484 ==
5877 00:58:49.692568 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 00:58:49.699016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 00:58:49.699100 ==
5880 00:58:49.699185 RX Vref Scan: 0
5881 00:58:49.699265
5882 00:58:49.702154 RX Vref 0 -> 0, step: 1
5883 00:58:49.702237
5884 00:58:49.705811 RX Delay -45 -> 252, step: 4
5885 00:58:49.708766 iDelay=203, Bit 0, Center 108 (23 ~ 194) 172
5886 00:58:49.715254 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5887 00:58:49.718916 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5888 00:58:49.722175 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5889 00:58:49.725254 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5890 00:58:49.729096 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5891 00:58:49.735586 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5892 00:58:49.738474 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5893 00:58:49.742184 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5894 00:58:49.745152 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5895 00:58:49.748179 iDelay=203, Bit 10, Center 98 (15 ~ 182) 168
5896 00:58:49.755233 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5897 00:58:49.758223 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5898 00:58:49.761531 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5899 00:58:49.765330 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5900 00:58:49.768088 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5901 00:58:49.771399 ==
5902 00:58:49.771483 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 00:58:49.778128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 00:58:49.778212 ==
5905 00:58:49.778297 DQS Delay:
5906 00:58:49.781961 DQS0 = 0, DQS1 = 0
5907 00:58:49.782044 DQM Delay:
5908 00:58:49.785139 DQM0 = 104, DQM1 = 98
5909 00:58:49.785222 DQ Delay:
5910 00:58:49.788443 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5911 00:58:49.791803 DQ4 =100, DQ5 =116, DQ6 =112, DQ7 =104
5912 00:58:49.794800 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5913 00:58:49.797952 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =106
5914 00:58:49.798036
5915 00:58:49.798120
5916 00:58:49.808180 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5917 00:58:49.808311 CH1 RK1: MR19=505, MR18=2E01
5918 00:58:49.814753 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5919 00:58:49.818096 [RxdqsGatingPostProcess] freq 933
5920 00:58:49.824532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5921 00:58:49.827792 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 00:58:49.831394 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 00:58:49.834860 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 00:58:49.837877 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 00:58:49.837961 best DQS0 dly(2T, 0.5T) = (0, 10)
5926 00:58:49.841238 best DQS1 dly(2T, 0.5T) = (0, 10)
5927 00:58:49.844778 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5928 00:58:49.847644 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5929 00:58:49.851159 Pre-setting of DQS Precalculation
5930 00:58:49.857954 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5931 00:58:49.864442 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5932 00:58:49.871318 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5933 00:58:49.871402
5934 00:58:49.871487
5935 00:58:49.874641 [Calibration Summary] 1866 Mbps
5936 00:58:49.874725 CH 0, Rank 0
5937 00:58:49.878008 SW Impedance : PASS
5938 00:58:49.881292 DUTY Scan : NO K
5939 00:58:49.881376 ZQ Calibration : PASS
5940 00:58:49.884238 Jitter Meter : NO K
5941 00:58:49.887797 CBT Training : PASS
5942 00:58:49.887881 Write leveling : PASS
5943 00:58:49.890988 RX DQS gating : PASS
5944 00:58:49.894184 RX DQ/DQS(RDDQC) : PASS
5945 00:58:49.894268 TX DQ/DQS : PASS
5946 00:58:49.898146 RX DATLAT : PASS
5947 00:58:49.901266 RX DQ/DQS(Engine): PASS
5948 00:58:49.901374 TX OE : NO K
5949 00:58:49.904526 All Pass.
5950 00:58:49.904609
5951 00:58:49.904693 CH 0, Rank 1
5952 00:58:49.907716 SW Impedance : PASS
5953 00:58:49.907800 DUTY Scan : NO K
5954 00:58:49.910893 ZQ Calibration : PASS
5955 00:58:49.914036 Jitter Meter : NO K
5956 00:58:49.914119 CBT Training : PASS
5957 00:58:49.917957 Write leveling : PASS
5958 00:58:49.918040 RX DQS gating : PASS
5959 00:58:49.921149 RX DQ/DQS(RDDQC) : PASS
5960 00:58:49.924473 TX DQ/DQS : PASS
5961 00:58:49.924557 RX DATLAT : PASS
5962 00:58:49.927732 RX DQ/DQS(Engine): PASS
5963 00:58:49.931069 TX OE : NO K
5964 00:58:49.931152 All Pass.
5965 00:58:49.931236
5966 00:58:49.931316 CH 1, Rank 0
5967 00:58:49.934475 SW Impedance : PASS
5968 00:58:49.937674 DUTY Scan : NO K
5969 00:58:49.937786 ZQ Calibration : PASS
5970 00:58:49.941020 Jitter Meter : NO K
5971 00:58:49.944251 CBT Training : PASS
5972 00:58:49.944379 Write leveling : PASS
5973 00:58:49.947428 RX DQS gating : PASS
5974 00:58:49.951216 RX DQ/DQS(RDDQC) : PASS
5975 00:58:49.951297 TX DQ/DQS : PASS
5976 00:58:49.954252 RX DATLAT : PASS
5977 00:58:49.957582 RX DQ/DQS(Engine): PASS
5978 00:58:49.957664 TX OE : NO K
5979 00:58:49.957728 All Pass.
5980 00:58:49.960818
5981 00:58:49.960919 CH 1, Rank 1
5982 00:58:49.964379 SW Impedance : PASS
5983 00:58:49.964460 DUTY Scan : NO K
5984 00:58:49.967382 ZQ Calibration : PASS
5985 00:58:49.967463 Jitter Meter : NO K
5986 00:58:49.970964 CBT Training : PASS
5987 00:58:49.973959 Write leveling : PASS
5988 00:58:49.974040 RX DQS gating : PASS
5989 00:58:49.977529 RX DQ/DQS(RDDQC) : PASS
5990 00:58:49.980896 TX DQ/DQS : PASS
5991 00:58:49.980978 RX DATLAT : PASS
5992 00:58:49.984193 RX DQ/DQS(Engine): PASS
5993 00:58:49.987398 TX OE : NO K
5994 00:58:49.987480 All Pass.
5995 00:58:49.987543
5996 00:58:49.990480 DramC Write-DBI off
5997 00:58:49.990560 PER_BANK_REFRESH: Hybrid Mode
5998 00:58:49.993838 TX_TRACKING: ON
5999 00:58:50.000362 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6000 00:58:50.007278 [FAST_K] Save calibration result to emmc
6001 00:58:50.010676 dramc_set_vcore_voltage set vcore to 650000
6002 00:58:50.010757 Read voltage for 400, 6
6003 00:58:50.014031 Vio18 = 0
6004 00:58:50.014110 Vcore = 650000
6005 00:58:50.014173 Vdram = 0
6006 00:58:50.017241 Vddq = 0
6007 00:58:50.017324 Vmddr = 0
6008 00:58:50.020739 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6009 00:58:50.027375 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6010 00:58:50.030640 MEM_TYPE=3, freq_sel=20
6011 00:58:50.033923 sv_algorithm_assistance_LP4_800
6012 00:58:50.037174 ============ PULL DRAM RESETB DOWN ============
6013 00:58:50.040437 ========== PULL DRAM RESETB DOWN end =========
6014 00:58:50.046974 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6015 00:58:50.050185 ===================================
6016 00:58:50.050265 LPDDR4 DRAM CONFIGURATION
6017 00:58:50.053966 ===================================
6018 00:58:50.057030 EX_ROW_EN[0] = 0x0
6019 00:58:50.057110 EX_ROW_EN[1] = 0x0
6020 00:58:50.060250 LP4Y_EN = 0x0
6021 00:58:50.060374 WORK_FSP = 0x0
6022 00:58:50.063449 WL = 0x2
6023 00:58:50.063529 RL = 0x2
6024 00:58:50.066692 BL = 0x2
6025 00:58:50.070407 RPST = 0x0
6026 00:58:50.070486 RD_PRE = 0x0
6027 00:58:50.073700 WR_PRE = 0x1
6028 00:58:50.073780 WR_PST = 0x0
6029 00:58:50.076681 DBI_WR = 0x0
6030 00:58:50.076761 DBI_RD = 0x0
6031 00:58:50.079902 OTF = 0x1
6032 00:58:50.083087 ===================================
6033 00:58:50.087077 ===================================
6034 00:58:50.087159 ANA top config
6035 00:58:50.090241 ===================================
6036 00:58:50.093338 DLL_ASYNC_EN = 0
6037 00:58:50.096668 ALL_SLAVE_EN = 1
6038 00:58:50.096749 NEW_RANK_MODE = 1
6039 00:58:50.100208 DLL_IDLE_MODE = 1
6040 00:58:50.103611 LP45_APHY_COMB_EN = 1
6041 00:58:50.106738 TX_ODT_DIS = 1
6042 00:58:50.106820 NEW_8X_MODE = 1
6043 00:58:50.110572 ===================================
6044 00:58:50.113663 ===================================
6045 00:58:50.116620 data_rate = 800
6046 00:58:50.120115 CKR = 1
6047 00:58:50.123446 DQ_P2S_RATIO = 4
6048 00:58:50.126640 ===================================
6049 00:58:50.130137 CA_P2S_RATIO = 4
6050 00:58:50.133588 DQ_CA_OPEN = 0
6051 00:58:50.133669 DQ_SEMI_OPEN = 1
6052 00:58:50.136895 CA_SEMI_OPEN = 1
6053 00:58:50.140281 CA_FULL_RATE = 0
6054 00:58:50.143239 DQ_CKDIV4_EN = 0
6055 00:58:50.147003 CA_CKDIV4_EN = 1
6056 00:58:50.150132 CA_PREDIV_EN = 0
6057 00:58:50.150213 PH8_DLY = 0
6058 00:58:50.153327 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6059 00:58:50.156690 DQ_AAMCK_DIV = 0
6060 00:58:50.160401 CA_AAMCK_DIV = 0
6061 00:58:50.163781 CA_ADMCK_DIV = 4
6062 00:58:50.166993 DQ_TRACK_CA_EN = 0
6063 00:58:50.167074 CA_PICK = 800
6064 00:58:50.170134 CA_MCKIO = 400
6065 00:58:50.173276 MCKIO_SEMI = 400
6066 00:58:50.176891 PLL_FREQ = 3016
6067 00:58:50.180144 DQ_UI_PI_RATIO = 32
6068 00:58:50.183319 CA_UI_PI_RATIO = 32
6069 00:58:50.186571 ===================================
6070 00:58:50.189745 ===================================
6071 00:58:50.193562 memory_type:LPDDR4
6072 00:58:50.193642 GP_NUM : 10
6073 00:58:50.196822 SRAM_EN : 1
6074 00:58:50.196902 MD32_EN : 0
6075 00:58:50.200199 ===================================
6076 00:58:50.203494 [ANA_INIT] >>>>>>>>>>>>>>
6077 00:58:50.206710 <<<<<< [CONFIGURE PHASE]: ANA_TX
6078 00:58:50.209736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6079 00:58:50.213285 ===================================
6080 00:58:50.216326 data_rate = 800,PCW = 0X7400
6081 00:58:50.220169 ===================================
6082 00:58:50.223384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6083 00:58:50.226679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 00:58:50.239804 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6085 00:58:50.243306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6086 00:58:50.246957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6087 00:58:50.249824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6088 00:58:50.253852 [ANA_INIT] flow start
6089 00:58:50.256412 [ANA_INIT] PLL >>>>>>>>
6090 00:58:50.256491 [ANA_INIT] PLL <<<<<<<<
6091 00:58:50.260072 [ANA_INIT] MIDPI >>>>>>>>
6092 00:58:50.262950 [ANA_INIT] MIDPI <<<<<<<<
6093 00:58:50.263029 [ANA_INIT] DLL >>>>>>>>
6094 00:58:50.266644 [ANA_INIT] flow end
6095 00:58:50.269971 ============ LP4 DIFF to SE enter ============
6096 00:58:50.273301 ============ LP4 DIFF to SE exit ============
6097 00:58:50.276694 [ANA_INIT] <<<<<<<<<<<<<
6098 00:58:50.279782 [Flow] Enable top DCM control >>>>>
6099 00:58:50.283443 [Flow] Enable top DCM control <<<<<
6100 00:58:50.286873 Enable DLL master slave shuffle
6101 00:58:50.293033 ==============================================================
6102 00:58:50.293114 Gating Mode config
6103 00:58:50.299953 ==============================================================
6104 00:58:50.300034 Config description:
6105 00:58:50.309909 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6106 00:58:50.316368 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6107 00:58:50.323130 SELPH_MODE 0: By rank 1: By Phase
6108 00:58:50.326245 ==============================================================
6109 00:58:50.329513 GAT_TRACK_EN = 0
6110 00:58:50.332946 RX_GATING_MODE = 2
6111 00:58:50.336060 RX_GATING_TRACK_MODE = 2
6112 00:58:50.339867 SELPH_MODE = 1
6113 00:58:50.343023 PICG_EARLY_EN = 1
6114 00:58:50.346100 VALID_LAT_VALUE = 1
6115 00:58:50.353014 ==============================================================
6116 00:58:50.356153 Enter into Gating configuration >>>>
6117 00:58:50.359235 Exit from Gating configuration <<<<
6118 00:58:50.362984 Enter into DVFS_PRE_config >>>>>
6119 00:58:50.373069 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6120 00:58:50.376145 Exit from DVFS_PRE_config <<<<<
6121 00:58:50.379237 Enter into PICG configuration >>>>
6122 00:58:50.382758 Exit from PICG configuration <<<<
6123 00:58:50.385863 [RX_INPUT] configuration >>>>>
6124 00:58:50.385943 [RX_INPUT] configuration <<<<<
6125 00:58:50.392816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6126 00:58:50.399140 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6127 00:58:50.402818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6128 00:58:50.409127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6129 00:58:50.415702 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 00:58:50.422673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 00:58:50.425809 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6132 00:58:50.429061 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6133 00:58:50.436175 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6134 00:58:50.439214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6135 00:58:50.442532 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6136 00:58:50.448978 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6137 00:58:50.452017 ===================================
6138 00:58:50.452098 LPDDR4 DRAM CONFIGURATION
6139 00:58:50.455801 ===================================
6140 00:58:50.458977 EX_ROW_EN[0] = 0x0
6141 00:58:50.459057 EX_ROW_EN[1] = 0x0
6142 00:58:50.462131 LP4Y_EN = 0x0
6143 00:58:50.462211 WORK_FSP = 0x0
6144 00:58:50.465502 WL = 0x2
6145 00:58:50.468807 RL = 0x2
6146 00:58:50.468886 BL = 0x2
6147 00:58:50.472150 RPST = 0x0
6148 00:58:50.472248 RD_PRE = 0x0
6149 00:58:50.475133 WR_PRE = 0x1
6150 00:58:50.475213 WR_PST = 0x0
6151 00:58:50.478985 DBI_WR = 0x0
6152 00:58:50.479065 DBI_RD = 0x0
6153 00:58:50.482186 OTF = 0x1
6154 00:58:50.485260 ===================================
6155 00:58:50.488810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6156 00:58:50.491770 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6157 00:58:50.495181 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 00:58:50.498806 ===================================
6159 00:58:50.501873 LPDDR4 DRAM CONFIGURATION
6160 00:58:50.505143 ===================================
6161 00:58:50.508944 EX_ROW_EN[0] = 0x10
6162 00:58:50.509024 EX_ROW_EN[1] = 0x0
6163 00:58:50.512458 LP4Y_EN = 0x0
6164 00:58:50.512538 WORK_FSP = 0x0
6165 00:58:50.515149 WL = 0x2
6166 00:58:50.515228 RL = 0x2
6167 00:58:50.518866 BL = 0x2
6168 00:58:50.518946 RPST = 0x0
6169 00:58:50.522262 RD_PRE = 0x0
6170 00:58:50.522342 WR_PRE = 0x1
6171 00:58:50.525447 WR_PST = 0x0
6172 00:58:50.528554 DBI_WR = 0x0
6173 00:58:50.528650 DBI_RD = 0x0
6174 00:58:50.532098 OTF = 0x1
6175 00:58:50.535322 ===================================
6176 00:58:50.538943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6177 00:58:50.544139 nWR fixed to 30
6178 00:58:50.547452 [ModeRegInit_LP4] CH0 RK0
6179 00:58:50.547532 [ModeRegInit_LP4] CH0 RK1
6180 00:58:50.550500 [ModeRegInit_LP4] CH1 RK0
6181 00:58:50.553759 [ModeRegInit_LP4] CH1 RK1
6182 00:58:50.553839 match AC timing 19
6183 00:58:50.560555 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6184 00:58:50.563689 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6185 00:58:50.567383 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6186 00:58:50.573938 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6187 00:58:50.577077 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6188 00:58:50.577158 ==
6189 00:58:50.580274 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 00:58:50.583661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6191 00:58:50.583741 ==
6192 00:58:50.590063 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6193 00:58:50.597159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6194 00:58:50.600405 [CA 0] Center 36 (8~64) winsize 57
6195 00:58:50.603642 [CA 1] Center 36 (8~64) winsize 57
6196 00:58:50.606716 [CA 2] Center 36 (8~64) winsize 57
6197 00:58:50.606796 [CA 3] Center 36 (8~64) winsize 57
6198 00:58:50.610439 [CA 4] Center 36 (8~64) winsize 57
6199 00:58:50.613419 [CA 5] Center 36 (8~64) winsize 57
6200 00:58:50.613499
6201 00:58:50.620174 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6202 00:58:50.620278
6203 00:58:50.623920 [CATrainingPosCal] consider 1 rank data
6204 00:58:50.624000 u2DelayCellTimex100 = 270/100 ps
6205 00:58:50.630461 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 00:58:50.633784 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 00:58:50.636857 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 00:58:50.639942 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 00:58:50.643529 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 00:58:50.646728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 00:58:50.646820
6212 00:58:50.650100 CA PerBit enable=1, Macro0, CA PI delay=36
6213 00:58:50.650181
6214 00:58:50.653182 [CBTSetCACLKResult] CA Dly = 36
6215 00:58:50.657096 CS Dly: 1 (0~32)
6216 00:58:50.657177 ==
6217 00:58:50.660362 Dram Type= 6, Freq= 0, CH_0, rank 1
6218 00:58:50.663697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6219 00:58:50.663778 ==
6220 00:58:50.669870 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6221 00:58:50.672914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6222 00:58:50.676726 [CA 0] Center 36 (8~64) winsize 57
6223 00:58:50.680030 [CA 1] Center 36 (8~64) winsize 57
6224 00:58:50.683341 [CA 2] Center 36 (8~64) winsize 57
6225 00:58:50.686443 [CA 3] Center 36 (8~64) winsize 57
6226 00:58:50.689746 [CA 4] Center 36 (8~64) winsize 57
6227 00:58:50.693106 [CA 5] Center 36 (8~64) winsize 57
6228 00:58:50.693189
6229 00:58:50.696399 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6230 00:58:50.696482
6231 00:58:50.699638 [CATrainingPosCal] consider 2 rank data
6232 00:58:50.703169 u2DelayCellTimex100 = 270/100 ps
6233 00:58:50.707022 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:58:50.709832 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 00:58:50.713003 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 00:58:50.719682 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 00:58:50.723457 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 00:58:50.726186 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 00:58:50.726269
6240 00:58:50.729632 CA PerBit enable=1, Macro0, CA PI delay=36
6241 00:58:50.729716
6242 00:58:50.732929 [CBTSetCACLKResult] CA Dly = 36
6243 00:58:50.733029 CS Dly: 1 (0~32)
6244 00:58:50.733127
6245 00:58:50.736356 ----->DramcWriteLeveling(PI) begin...
6246 00:58:50.739651 ==
6247 00:58:50.739767 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 00:58:50.746311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 00:58:50.746396 ==
6250 00:58:50.749650 Write leveling (Byte 0): 40 => 8
6251 00:58:50.752548 Write leveling (Byte 1): 40 => 8
6252 00:58:50.755950 DramcWriteLeveling(PI) end<-----
6253 00:58:50.756034
6254 00:58:50.756151 ==
6255 00:58:50.759501 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 00:58:50.762341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 00:58:50.762425 ==
6258 00:58:50.765919 [Gating] SW mode calibration
6259 00:58:50.772482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6260 00:58:50.775691 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6261 00:58:50.782457 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 00:58:50.785692 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 00:58:50.788938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 00:58:50.796069 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 00:58:50.799465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 00:58:50.802476 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 00:58:50.809153 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 00:58:50.812435 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 00:58:50.815922 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 00:58:50.818939 Total UI for P1: 0, mck2ui 16
6271 00:58:50.822489 best dqsien dly found for B0: ( 0, 14, 24)
6272 00:58:50.825743 Total UI for P1: 0, mck2ui 16
6273 00:58:50.829110 best dqsien dly found for B1: ( 0, 14, 24)
6274 00:58:50.832243 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6275 00:58:50.838952 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6276 00:58:50.839038
6277 00:58:50.842313 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 00:58:50.845615 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6279 00:58:50.849163 [Gating] SW calibration Done
6280 00:58:50.849247 ==
6281 00:58:50.852153 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 00:58:50.855848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 00:58:50.855933 ==
6284 00:58:50.856017 RX Vref Scan: 0
6285 00:58:50.859043
6286 00:58:50.859141 RX Vref 0 -> 0, step: 1
6287 00:58:50.859220
6288 00:58:50.861858 RX Delay -410 -> 252, step: 16
6289 00:58:50.865525 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6290 00:58:50.872157 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6291 00:58:50.875380 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6292 00:58:50.878867 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6293 00:58:50.882227 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6294 00:58:50.889077 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6295 00:58:50.891924 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6296 00:58:50.895526 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6297 00:58:50.898563 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6298 00:58:50.905599 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6299 00:58:50.908684 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6300 00:58:50.911916 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6301 00:58:50.915223 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6302 00:58:50.921869 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6303 00:58:50.925972 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6304 00:58:50.928526 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6305 00:58:50.928605 ==
6306 00:58:50.932316 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 00:58:50.935579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 00:58:50.938728 ==
6309 00:58:50.938807 DQS Delay:
6310 00:58:50.938871 DQS0 = 27, DQS1 = 35
6311 00:58:50.942049 DQM Delay:
6312 00:58:50.942128 DQM0 = 11, DQM1 = 11
6313 00:58:50.945330 DQ Delay:
6314 00:58:50.945409 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6315 00:58:50.948531 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6316 00:58:50.951744 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6317 00:58:50.955462 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6318 00:58:50.955542
6319 00:58:50.955604
6320 00:58:50.958708 ==
6321 00:58:50.958788 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 00:58:50.965210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 00:58:50.965290 ==
6324 00:58:50.965352
6325 00:58:50.965409
6326 00:58:50.968950 TX Vref Scan disable
6327 00:58:50.969029 == TX Byte 0 ==
6328 00:58:50.972307 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 00:58:50.978796 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 00:58:50.978908 == TX Byte 1 ==
6331 00:58:50.981668 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 00:58:50.985275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 00:58:50.988441 ==
6334 00:58:50.992025 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 00:58:50.995183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 00:58:50.995264 ==
6337 00:58:50.995328
6338 00:58:50.995387
6339 00:58:50.998321 TX Vref Scan disable
6340 00:58:50.998401 == TX Byte 0 ==
6341 00:58:51.001791 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 00:58:51.008256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 00:58:51.008376 == TX Byte 1 ==
6344 00:58:51.011812 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 00:58:51.018510 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 00:58:51.018629
6347 00:58:51.018721 [DATLAT]
6348 00:58:51.018816 Freq=400, CH0 RK0
6349 00:58:51.018902
6350 00:58:51.021919 DATLAT Default: 0xf
6351 00:58:51.022026 0, 0xFFFF, sum = 0
6352 00:58:51.024571 1, 0xFFFF, sum = 0
6353 00:58:51.027912 2, 0xFFFF, sum = 0
6354 00:58:51.028015 3, 0xFFFF, sum = 0
6355 00:58:51.031242 4, 0xFFFF, sum = 0
6356 00:58:51.031318 5, 0xFFFF, sum = 0
6357 00:58:51.034472 6, 0xFFFF, sum = 0
6358 00:58:51.034542 7, 0xFFFF, sum = 0
6359 00:58:51.037855 8, 0xFFFF, sum = 0
6360 00:58:51.037936 9, 0xFFFF, sum = 0
6361 00:58:51.041587 10, 0xFFFF, sum = 0
6362 00:58:51.041694 11, 0xFFFF, sum = 0
6363 00:58:51.044739 12, 0xFFFF, sum = 0
6364 00:58:51.044820 13, 0x0, sum = 1
6365 00:58:51.047895 14, 0x0, sum = 2
6366 00:58:51.047965 15, 0x0, sum = 3
6367 00:58:51.051732 16, 0x0, sum = 4
6368 00:58:51.051813 best_step = 14
6369 00:58:51.051875
6370 00:58:51.051932 ==
6371 00:58:51.055092 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 00:58:51.058294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 00:58:51.061358 ==
6374 00:58:51.061441 RX Vref Scan: 1
6375 00:58:51.061508
6376 00:58:51.064619 RX Vref 0 -> 0, step: 1
6377 00:58:51.064723
6378 00:58:51.068475 RX Delay -311 -> 252, step: 8
6379 00:58:51.068571
6380 00:58:51.071467 Set Vref, RX VrefLevel [Byte0]: 57
6381 00:58:51.071538 [Byte1]: 49
6382 00:58:51.077246
6383 00:58:51.077317 Final RX Vref Byte 0 = 57 to rank0
6384 00:58:51.080600 Final RX Vref Byte 1 = 49 to rank0
6385 00:58:51.083822 Final RX Vref Byte 0 = 57 to rank1
6386 00:58:51.087134 Final RX Vref Byte 1 = 49 to rank1==
6387 00:58:51.090545 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 00:58:51.096851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 00:58:51.096943 ==
6390 00:58:51.097020 DQS Delay:
6391 00:58:51.100504 DQS0 = 28, DQS1 = 36
6392 00:58:51.100617 DQM Delay:
6393 00:58:51.100710 DQM0 = 10, DQM1 = 13
6394 00:58:51.103538 DQ Delay:
6395 00:58:51.107181 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6396 00:58:51.107284 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6397 00:58:51.110438 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6398 00:58:51.113858 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6399 00:58:51.113956
6400 00:58:51.114072
6401 00:58:51.123235 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6402 00:58:51.126910 CH0 RK0: MR19=C0C, MR18=C8B5
6403 00:58:51.133677 CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265
6404 00:58:51.133772 ==
6405 00:58:51.136936 Dram Type= 6, Freq= 0, CH_0, rank 1
6406 00:58:51.140436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 00:58:51.140523 ==
6408 00:58:51.143514 [Gating] SW mode calibration
6409 00:58:51.150282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6410 00:58:51.156873 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6411 00:58:51.159679 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 00:58:51.163570 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6413 00:58:51.169893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 00:58:51.173037 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 00:58:51.176413 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 00:58:51.183519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 00:58:51.186809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 00:58:51.189970 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 00:58:51.193273 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 00:58:51.196552 Total UI for P1: 0, mck2ui 16
6421 00:58:51.199944 best dqsien dly found for B0: ( 0, 14, 24)
6422 00:58:51.203312 Total UI for P1: 0, mck2ui 16
6423 00:58:51.206383 best dqsien dly found for B1: ( 0, 14, 24)
6424 00:58:51.209631 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6425 00:58:51.216578 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6426 00:58:51.216690
6427 00:58:51.219723 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 00:58:51.223071 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6429 00:58:51.226271 [Gating] SW calibration Done
6430 00:58:51.226367 ==
6431 00:58:51.229539 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 00:58:51.232688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 00:58:51.232763 ==
6434 00:58:51.236021 RX Vref Scan: 0
6435 00:58:51.236093
6436 00:58:51.236156 RX Vref 0 -> 0, step: 1
6437 00:58:51.236220
6438 00:58:51.239321 RX Delay -410 -> 252, step: 16
6439 00:58:51.242503 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6440 00:58:51.249349 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6441 00:58:51.253031 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6442 00:58:51.255960 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6443 00:58:51.259320 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6444 00:58:51.266267 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6445 00:58:51.269852 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6446 00:58:51.272548 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6447 00:58:51.275891 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6448 00:58:51.282957 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6449 00:58:51.286036 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6450 00:58:51.289185 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6451 00:58:51.292460 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6452 00:58:51.299564 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6453 00:58:51.302809 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6454 00:58:51.306066 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6455 00:58:51.306175 ==
6456 00:58:51.309427 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 00:58:51.315731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 00:58:51.315840 ==
6459 00:58:51.315932 DQS Delay:
6460 00:58:51.319457 DQS0 = 27, DQS1 = 35
6461 00:58:51.319551 DQM Delay:
6462 00:58:51.319629 DQM0 = 12, DQM1 = 12
6463 00:58:51.322563 DQ Delay:
6464 00:58:51.325662 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6465 00:58:51.325771 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6466 00:58:51.329194 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6467 00:58:51.332437 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6468 00:58:51.332546
6469 00:58:51.332675
6470 00:58:51.336209 ==
6471 00:58:51.339349 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 00:58:51.342692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 00:58:51.342773 ==
6474 00:58:51.342836
6475 00:58:51.342930
6476 00:58:51.345893 TX Vref Scan disable
6477 00:58:51.346033 == TX Byte 0 ==
6478 00:58:51.349321 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6479 00:58:51.355839 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6480 00:58:51.355921 == TX Byte 1 ==
6481 00:58:51.359116 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6482 00:58:51.365645 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6483 00:58:51.365726 ==
6484 00:58:51.368968 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 00:58:51.372583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 00:58:51.372665 ==
6487 00:58:51.372759
6488 00:58:51.372860
6489 00:58:51.375492 TX Vref Scan disable
6490 00:58:51.375627 == TX Byte 0 ==
6491 00:58:51.379040 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6492 00:58:51.385421 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6493 00:58:51.385530 == TX Byte 1 ==
6494 00:58:51.388654 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6495 00:58:51.395457 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6496 00:58:51.395553
6497 00:58:51.395623 [DATLAT]
6498 00:58:51.395687 Freq=400, CH0 RK1
6499 00:58:51.395746
6500 00:58:51.398709 DATLAT Default: 0xe
6501 00:58:51.401812 0, 0xFFFF, sum = 0
6502 00:58:51.401924 1, 0xFFFF, sum = 0
6503 00:58:51.405139 2, 0xFFFF, sum = 0
6504 00:58:51.405217 3, 0xFFFF, sum = 0
6505 00:58:51.408512 4, 0xFFFF, sum = 0
6506 00:58:51.408587 5, 0xFFFF, sum = 0
6507 00:58:51.411885 6, 0xFFFF, sum = 0
6508 00:58:51.411995 7, 0xFFFF, sum = 0
6509 00:58:51.416121 8, 0xFFFF, sum = 0
6510 00:58:51.416222 9, 0xFFFF, sum = 0
6511 00:58:51.418419 10, 0xFFFF, sum = 0
6512 00:58:51.418531 11, 0xFFFF, sum = 0
6513 00:58:51.421691 12, 0xFFFF, sum = 0
6514 00:58:51.421767 13, 0x0, sum = 1
6515 00:58:51.425606 14, 0x0, sum = 2
6516 00:58:51.425683 15, 0x0, sum = 3
6517 00:58:51.428868 16, 0x0, sum = 4
6518 00:58:51.428968 best_step = 14
6519 00:58:51.429057
6520 00:58:51.429147 ==
6521 00:58:51.432240 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 00:58:51.435514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 00:58:51.438621 ==
6524 00:58:51.438735 RX Vref Scan: 0
6525 00:58:51.438839
6526 00:58:51.441575 RX Vref 0 -> 0, step: 1
6527 00:58:51.441682
6528 00:58:51.444902 RX Delay -311 -> 252, step: 8
6529 00:58:51.451817 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6530 00:58:51.454923 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6531 00:58:51.458269 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6532 00:58:51.461493 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6533 00:58:51.468730 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6534 00:58:51.471374 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6535 00:58:51.474767 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6536 00:58:51.478140 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6537 00:58:51.481857 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6538 00:58:51.488233 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6539 00:58:51.492055 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6540 00:58:51.495441 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6541 00:58:51.498517 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6542 00:58:51.505098 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6543 00:58:51.508223 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6544 00:58:51.511496 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6545 00:58:51.511594 ==
6546 00:58:51.514838 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 00:58:51.521883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 00:58:51.521999 ==
6549 00:58:51.522092 DQS Delay:
6550 00:58:51.525151 DQS0 = 24, DQS1 = 32
6551 00:58:51.525228 DQM Delay:
6552 00:58:51.525295 DQM0 = 8, DQM1 = 10
6553 00:58:51.528329 DQ Delay:
6554 00:58:51.531643 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6555 00:58:51.531769 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6556 00:58:51.535155 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6557 00:58:51.538371 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6558 00:58:51.538472
6559 00:58:51.538563
6560 00:58:51.548936 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6561 00:58:51.551799 CH0 RK1: MR19=C0C, MR18=BA5A
6562 00:58:51.558410 CH0_RK1: MR19=0xC0C, MR18=0xBA5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6563 00:58:51.558523 [RxdqsGatingPostProcess] freq 400
6564 00:58:51.564902 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6565 00:58:51.568337 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 00:58:51.571605 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 00:58:51.574881 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 00:58:51.578236 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 00:58:51.581478 best DQS0 dly(2T, 0.5T) = (0, 10)
6570 00:58:51.584820 best DQS1 dly(2T, 0.5T) = (0, 10)
6571 00:58:51.587900 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6572 00:58:51.591775 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6573 00:58:51.594915 Pre-setting of DQS Precalculation
6574 00:58:51.598281 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6575 00:58:51.598381 ==
6576 00:58:51.601464 Dram Type= 6, Freq= 0, CH_1, rank 0
6577 00:58:51.604828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 00:58:51.608041 ==
6579 00:58:51.611262 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6580 00:58:51.618353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6581 00:58:51.621317 [CA 0] Center 36 (8~64) winsize 57
6582 00:58:51.624572 [CA 1] Center 36 (8~64) winsize 57
6583 00:58:51.628051 [CA 2] Center 36 (8~64) winsize 57
6584 00:58:51.631383 [CA 3] Center 36 (8~64) winsize 57
6585 00:58:51.634654 [CA 4] Center 36 (8~64) winsize 57
6586 00:58:51.638075 [CA 5] Center 36 (8~64) winsize 57
6587 00:58:51.638175
6588 00:58:51.641359 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6589 00:58:51.641457
6590 00:58:51.644565 [CATrainingPosCal] consider 1 rank data
6591 00:58:51.647883 u2DelayCellTimex100 = 270/100 ps
6592 00:58:51.651149 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 00:58:51.654480 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 00:58:51.657694 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 00:58:51.660838 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 00:58:51.664177 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 00:58:51.667486 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 00:58:51.667562
6599 00:58:51.674385 CA PerBit enable=1, Macro0, CA PI delay=36
6600 00:58:51.674467
6601 00:58:51.674531 [CBTSetCACLKResult] CA Dly = 36
6602 00:58:51.677873 CS Dly: 1 (0~32)
6603 00:58:51.677953 ==
6604 00:58:51.680733 Dram Type= 6, Freq= 0, CH_1, rank 1
6605 00:58:51.684586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 00:58:51.684668 ==
6607 00:58:51.691091 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6608 00:58:51.697626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6609 00:58:51.701112 [CA 0] Center 36 (8~64) winsize 57
6610 00:58:51.704314 [CA 1] Center 36 (8~64) winsize 57
6611 00:58:51.707576 [CA 2] Center 36 (8~64) winsize 57
6612 00:58:51.707652 [CA 3] Center 36 (8~64) winsize 57
6613 00:58:51.710972 [CA 4] Center 36 (8~64) winsize 57
6614 00:58:51.714344 [CA 5] Center 36 (8~64) winsize 57
6615 00:58:51.714414
6616 00:58:51.720803 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6617 00:58:51.720882
6618 00:58:51.723984 [CATrainingPosCal] consider 2 rank data
6619 00:58:51.727860 u2DelayCellTimex100 = 270/100 ps
6620 00:58:51.730797 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:58:51.733966 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 00:58:51.737183 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 00:58:51.740341 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 00:58:51.743683 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 00:58:51.747349 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 00:58:51.747452
6627 00:58:51.750953 CA PerBit enable=1, Macro0, CA PI delay=36
6628 00:58:51.751060
6629 00:58:51.753878 [CBTSetCACLKResult] CA Dly = 36
6630 00:58:51.757033 CS Dly: 1 (0~32)
6631 00:58:51.757141
6632 00:58:51.760382 ----->DramcWriteLeveling(PI) begin...
6633 00:58:51.760455 ==
6634 00:58:51.763627 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 00:58:51.767319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 00:58:51.767393 ==
6637 00:58:51.770315 Write leveling (Byte 0): 40 => 8
6638 00:58:51.774331 Write leveling (Byte 1): 40 => 8
6639 00:58:51.776920 DramcWriteLeveling(PI) end<-----
6640 00:58:51.777002
6641 00:58:51.777065 ==
6642 00:58:51.780239 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 00:58:51.783539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 00:58:51.783646 ==
6645 00:58:51.787312 [Gating] SW mode calibration
6646 00:58:51.794026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6647 00:58:51.800496 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6648 00:58:51.803850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 00:58:51.806906 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 00:58:51.813735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 00:58:51.816868 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 00:58:51.820297 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 00:58:51.826760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 00:58:51.830032 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 00:58:51.833818 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 00:58:51.840410 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 00:58:51.840499 Total UI for P1: 0, mck2ui 16
6658 00:58:51.846721 best dqsien dly found for B0: ( 0, 14, 24)
6659 00:58:51.846831 Total UI for P1: 0, mck2ui 16
6660 00:58:51.853446 best dqsien dly found for B1: ( 0, 14, 24)
6661 00:58:51.856740 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6662 00:58:51.859892 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6663 00:58:51.859974
6664 00:58:51.863134 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 00:58:51.866394 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6666 00:58:51.869857 [Gating] SW calibration Done
6667 00:58:51.869936 ==
6668 00:58:51.873314 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 00:58:51.876892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 00:58:51.877020 ==
6671 00:58:51.879662 RX Vref Scan: 0
6672 00:58:51.879775
6673 00:58:51.879850 RX Vref 0 -> 0, step: 1
6674 00:58:51.879907
6675 00:58:51.883389 RX Delay -410 -> 252, step: 16
6676 00:58:51.889825 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6677 00:58:51.893162 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6678 00:58:51.896939 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6679 00:58:51.899946 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6680 00:58:51.906545 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6681 00:58:51.909786 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6682 00:58:51.912898 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6683 00:58:51.916225 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6684 00:58:51.923164 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6685 00:58:51.926194 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6686 00:58:51.929734 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6687 00:58:51.933076 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6688 00:58:51.939920 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6689 00:58:51.943052 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6690 00:58:51.946376 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6691 00:58:51.950078 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6692 00:58:51.953137 ==
6693 00:58:51.953221 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 00:58:51.959596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 00:58:51.959679 ==
6696 00:58:51.959743 DQS Delay:
6697 00:58:51.962835 DQS0 = 35, DQS1 = 35
6698 00:58:51.962917 DQM Delay:
6699 00:58:51.966023 DQM0 = 18, DQM1 = 13
6700 00:58:51.966134 DQ Delay:
6701 00:58:51.969356 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6702 00:58:51.973228 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6703 00:58:51.976487 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6704 00:58:51.979780 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6705 00:58:51.979861
6706 00:58:51.979924
6707 00:58:51.979982 ==
6708 00:58:51.983023 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 00:58:51.986277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 00:58:51.986357 ==
6711 00:58:51.986421
6712 00:58:51.986515
6713 00:58:51.989409 TX Vref Scan disable
6714 00:58:51.989506 == TX Byte 0 ==
6715 00:58:51.996356 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 00:58:51.999613 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 00:58:51.999698 == TX Byte 1 ==
6718 00:58:52.006429 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 00:58:52.009638 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 00:58:52.009730 ==
6721 00:58:52.012427 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 00:58:52.016260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 00:58:52.016371 ==
6724 00:58:52.016441
6725 00:58:52.016507
6726 00:58:52.019724 TX Vref Scan disable
6727 00:58:52.019797 == TX Byte 0 ==
6728 00:58:52.026288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 00:58:52.029106 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 00:58:52.029185 == TX Byte 1 ==
6731 00:58:52.035671 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 00:58:52.039487 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 00:58:52.039562
6734 00:58:52.039639 [DATLAT]
6735 00:58:52.042717 Freq=400, CH1 RK0
6736 00:58:52.042808
6737 00:58:52.042870 DATLAT Default: 0xf
6738 00:58:52.045865 0, 0xFFFF, sum = 0
6739 00:58:52.045944 1, 0xFFFF, sum = 0
6740 00:58:52.049030 2, 0xFFFF, sum = 0
6741 00:58:52.049132 3, 0xFFFF, sum = 0
6742 00:58:52.052299 4, 0xFFFF, sum = 0
6743 00:58:52.052458 5, 0xFFFF, sum = 0
6744 00:58:52.056036 6, 0xFFFF, sum = 0
6745 00:58:52.056118 7, 0xFFFF, sum = 0
6746 00:58:52.059231 8, 0xFFFF, sum = 0
6747 00:58:52.059353 9, 0xFFFF, sum = 0
6748 00:58:52.062699 10, 0xFFFF, sum = 0
6749 00:58:52.065845 11, 0xFFFF, sum = 0
6750 00:58:52.066039 12, 0xFFFF, sum = 0
6751 00:58:52.069030 13, 0x0, sum = 1
6752 00:58:52.069134 14, 0x0, sum = 2
6753 00:58:52.072408 15, 0x0, sum = 3
6754 00:58:52.072506 16, 0x0, sum = 4
6755 00:58:52.072612 best_step = 14
6756 00:58:52.072734
6757 00:58:52.075665 ==
6758 00:58:52.078737 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 00:58:52.082721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 00:58:52.082802 ==
6761 00:58:52.082867 RX Vref Scan: 1
6762 00:58:52.082927
6763 00:58:52.085942 RX Vref 0 -> 0, step: 1
6764 00:58:52.086068
6765 00:58:52.089168 RX Delay -311 -> 252, step: 8
6766 00:58:52.089253
6767 00:58:52.092583 Set Vref, RX VrefLevel [Byte0]: 56
6768 00:58:52.095822 [Byte1]: 47
6769 00:58:52.099108
6770 00:58:52.099223 Final RX Vref Byte 0 = 56 to rank0
6771 00:58:52.102528 Final RX Vref Byte 1 = 47 to rank0
6772 00:58:52.105819 Final RX Vref Byte 0 = 56 to rank1
6773 00:58:52.109108 Final RX Vref Byte 1 = 47 to rank1==
6774 00:58:52.112729 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 00:58:52.119297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 00:58:52.119382 ==
6777 00:58:52.119471 DQS Delay:
6778 00:58:52.122452 DQS0 = 28, DQS1 = 32
6779 00:58:52.122535 DQM Delay:
6780 00:58:52.122626 DQM0 = 10, DQM1 = 11
6781 00:58:52.126020 DQ Delay:
6782 00:58:52.126103 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6783 00:58:52.129670 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6784 00:58:52.132808 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6785 00:58:52.135812 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6786 00:58:52.135895
6787 00:58:52.135960
6788 00:58:52.145910 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6789 00:58:52.149384 CH1 RK0: MR19=C0C, MR18=8FC8
6790 00:58:52.156154 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6791 00:58:52.156277 ==
6792 00:58:52.159680 Dram Type= 6, Freq= 0, CH_1, rank 1
6793 00:58:52.162879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 00:58:52.162979 ==
6795 00:58:52.166544 [Gating] SW mode calibration
6796 00:58:52.172971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6797 00:58:52.176213 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6798 00:58:52.182649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 00:58:52.185817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6800 00:58:52.188999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 00:58:52.195657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 00:58:52.199520 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 00:58:52.202588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 00:58:52.209183 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 00:58:52.212477 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 00:58:52.215780 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 00:58:52.219092 Total UI for P1: 0, mck2ui 16
6808 00:58:52.222235 best dqsien dly found for B0: ( 0, 14, 24)
6809 00:58:52.225233 Total UI for P1: 0, mck2ui 16
6810 00:58:52.228680 best dqsien dly found for B1: ( 0, 14, 24)
6811 00:58:52.232003 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6812 00:58:52.239224 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6813 00:58:52.239331
6814 00:58:52.242383 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 00:58:52.245453 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6816 00:58:52.248260 [Gating] SW calibration Done
6817 00:58:52.248367 ==
6818 00:58:52.252095 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 00:58:52.255791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 00:58:52.255871 ==
6821 00:58:52.255934 RX Vref Scan: 0
6822 00:58:52.258471
6823 00:58:52.258550 RX Vref 0 -> 0, step: 1
6824 00:58:52.258613
6825 00:58:52.261769 RX Delay -410 -> 252, step: 16
6826 00:58:52.265631 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6827 00:58:52.271884 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6828 00:58:52.275424 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6829 00:58:52.278516 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6830 00:58:52.282321 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6831 00:58:52.288304 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6832 00:58:52.292074 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6833 00:58:52.295488 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6834 00:58:52.298814 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6835 00:58:52.302087 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6836 00:58:52.308600 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6837 00:58:52.311918 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6838 00:58:52.315140 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6839 00:58:52.321720 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6840 00:58:52.325458 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6841 00:58:52.328664 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6842 00:58:52.328801 ==
6843 00:58:52.331861 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 00:58:52.335154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 00:58:52.338240 ==
6846 00:58:52.338368 DQS Delay:
6847 00:58:52.338466 DQS0 = 35, DQS1 = 35
6848 00:58:52.341866 DQM Delay:
6849 00:58:52.341942 DQM0 = 18, DQM1 = 13
6850 00:58:52.344788 DQ Delay:
6851 00:58:52.348302 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6852 00:58:52.348417 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6853 00:58:52.351892 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6854 00:58:52.355137 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6855 00:58:52.355213
6856 00:58:52.358318
6857 00:58:52.358387 ==
6858 00:58:52.361622 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 00:58:52.364676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 00:58:52.364744 ==
6861 00:58:52.364803
6862 00:58:52.364861
6863 00:58:52.368438 TX Vref Scan disable
6864 00:58:52.368537 == TX Byte 0 ==
6865 00:58:52.371369 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6866 00:58:52.378391 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6867 00:58:52.378468 == TX Byte 1 ==
6868 00:58:52.381848 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6869 00:58:52.388144 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6870 00:58:52.388221 ==
6871 00:58:52.391794 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 00:58:52.394748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 00:58:52.394818 ==
6874 00:58:52.394882
6875 00:58:52.394939
6876 00:58:52.398256 TX Vref Scan disable
6877 00:58:52.398332 == TX Byte 0 ==
6878 00:58:52.401372 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6879 00:58:52.408423 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6880 00:58:52.408500 == TX Byte 1 ==
6881 00:58:52.411510 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6882 00:58:52.418633 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6883 00:58:52.418717
6884 00:58:52.418780 [DATLAT]
6885 00:58:52.418838 Freq=400, CH1 RK1
6886 00:58:52.418898
6887 00:58:52.421955 DATLAT Default: 0xe
6888 00:58:52.422025 0, 0xFFFF, sum = 0
6889 00:58:52.425203 1, 0xFFFF, sum = 0
6890 00:58:52.425275 2, 0xFFFF, sum = 0
6891 00:58:52.428531 3, 0xFFFF, sum = 0
6892 00:58:52.428605 4, 0xFFFF, sum = 0
6893 00:58:52.431694 5, 0xFFFF, sum = 0
6894 00:58:52.434784 6, 0xFFFF, sum = 0
6895 00:58:52.434855 7, 0xFFFF, sum = 0
6896 00:58:52.438205 8, 0xFFFF, sum = 0
6897 00:58:52.438301 9, 0xFFFF, sum = 0
6898 00:58:52.441436 10, 0xFFFF, sum = 0
6899 00:58:52.441541 11, 0xFFFF, sum = 0
6900 00:58:52.445281 12, 0xFFFF, sum = 0
6901 00:58:52.445352 13, 0x0, sum = 1
6902 00:58:52.448188 14, 0x0, sum = 2
6903 00:58:52.448252 15, 0x0, sum = 3
6904 00:58:52.451904 16, 0x0, sum = 4
6905 00:58:52.451970 best_step = 14
6906 00:58:52.452028
6907 00:58:52.452083 ==
6908 00:58:52.454910 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 00:58:52.458068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 00:58:52.458139 ==
6911 00:58:52.461568 RX Vref Scan: 0
6912 00:58:52.461636
6913 00:58:52.464702 RX Vref 0 -> 0, step: 1
6914 00:58:52.464772
6915 00:58:52.464830 RX Delay -311 -> 252, step: 8
6916 00:58:52.473305 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6917 00:58:52.477206 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6918 00:58:52.480237 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6919 00:58:52.483369 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6920 00:58:52.490214 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6921 00:58:52.493540 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6922 00:58:52.497062 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6923 00:58:52.500472 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6924 00:58:52.506750 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6925 00:58:52.509975 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6926 00:58:52.513673 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6927 00:58:52.516781 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6928 00:58:52.523271 iDelay=217, Bit 12, Center -8 (-231 ~ 216) 448
6929 00:58:52.526781 iDelay=217, Bit 13, Center -12 (-231 ~ 208) 440
6930 00:58:52.529725 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6931 00:58:52.533730 iDelay=217, Bit 15, Center -12 (-231 ~ 208) 440
6932 00:58:52.536827 ==
6933 00:58:52.539979 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 00:58:52.543212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 00:58:52.543317 ==
6936 00:58:52.543436 DQS Delay:
6937 00:58:52.546727 DQS0 = 28, DQS1 = 32
6938 00:58:52.546850 DQM Delay:
6939 00:58:52.549974 DQM0 = 11, DQM1 = 13
6940 00:58:52.550096 DQ Delay:
6941 00:58:52.553143 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6942 00:58:52.556631 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6943 00:58:52.559828 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6944 00:58:52.562873 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6945 00:58:52.562954
6946 00:58:52.563017
6947 00:58:52.569709 [DQSOSCAuto] RK1, (LSB)MR18= 0xc454, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6948 00:58:52.572802 CH1 RK1: MR19=C0C, MR18=C454
6949 00:58:52.579430 CH1_RK1: MR19=0xC0C, MR18=0xC454, DQSOSC=385, MR23=63, INC=398, DEC=265
6950 00:58:52.583350 [RxdqsGatingPostProcess] freq 400
6951 00:58:52.589634 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6952 00:58:52.589709 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 00:58:52.593007 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 00:58:52.596389 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 00:58:52.599389 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 00:58:52.603226 best DQS0 dly(2T, 0.5T) = (0, 10)
6957 00:58:52.605788 best DQS1 dly(2T, 0.5T) = (0, 10)
6958 00:58:52.609154 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6959 00:58:52.612505 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6960 00:58:52.616298 Pre-setting of DQS Precalculation
6961 00:58:52.622774 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6962 00:58:52.629039 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6963 00:58:52.635600 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6964 00:58:52.635682
6965 00:58:52.635747
6966 00:58:52.639013 [Calibration Summary] 800 Mbps
6967 00:58:52.639125 CH 0, Rank 0
6968 00:58:52.642536 SW Impedance : PASS
6969 00:58:52.645674 DUTY Scan : NO K
6970 00:58:52.645757 ZQ Calibration : PASS
6971 00:58:52.649160 Jitter Meter : NO K
6972 00:58:52.649242 CBT Training : PASS
6973 00:58:52.652492 Write leveling : PASS
6974 00:58:52.655772 RX DQS gating : PASS
6975 00:58:52.655854 RX DQ/DQS(RDDQC) : PASS
6976 00:58:52.659030 TX DQ/DQS : PASS
6977 00:58:52.662513 RX DATLAT : PASS
6978 00:58:52.662596 RX DQ/DQS(Engine): PASS
6979 00:58:52.665544 TX OE : NO K
6980 00:58:52.665627 All Pass.
6981 00:58:52.665693
6982 00:58:52.669432 CH 0, Rank 1
6983 00:58:52.669515 SW Impedance : PASS
6984 00:58:52.672168 DUTY Scan : NO K
6985 00:58:52.675679 ZQ Calibration : PASS
6986 00:58:52.675761 Jitter Meter : NO K
6987 00:58:52.679237 CBT Training : PASS
6988 00:58:52.682642 Write leveling : NO K
6989 00:58:52.682724 RX DQS gating : PASS
6990 00:58:52.685929 RX DQ/DQS(RDDQC) : PASS
6991 00:58:52.689094 TX DQ/DQS : PASS
6992 00:58:52.689176 RX DATLAT : PASS
6993 00:58:52.692908 RX DQ/DQS(Engine): PASS
6994 00:58:52.692988 TX OE : NO K
6995 00:58:52.696054 All Pass.
6996 00:58:52.696160
6997 00:58:52.696256 CH 1, Rank 0
6998 00:58:52.699377 SW Impedance : PASS
6999 00:58:52.699457 DUTY Scan : NO K
7000 00:58:52.702710 ZQ Calibration : PASS
7001 00:58:52.706068 Jitter Meter : NO K
7002 00:58:52.706148 CBT Training : PASS
7003 00:58:52.709503 Write leveling : PASS
7004 00:58:52.712547 RX DQS gating : PASS
7005 00:58:52.712627 RX DQ/DQS(RDDQC) : PASS
7006 00:58:52.715721 TX DQ/DQS : PASS
7007 00:58:52.718792 RX DATLAT : PASS
7008 00:58:52.718872 RX DQ/DQS(Engine): PASS
7009 00:58:52.722499 TX OE : NO K
7010 00:58:52.722580 All Pass.
7011 00:58:52.722643
7012 00:58:52.726205 CH 1, Rank 1
7013 00:58:52.726285 SW Impedance : PASS
7014 00:58:52.729243 DUTY Scan : NO K
7015 00:58:52.731930 ZQ Calibration : PASS
7016 00:58:52.732052 Jitter Meter : NO K
7017 00:58:52.735742 CBT Training : PASS
7018 00:58:52.738612 Write leveling : NO K
7019 00:58:52.738692 RX DQS gating : PASS
7020 00:58:52.742354 RX DQ/DQS(RDDQC) : PASS
7021 00:58:52.742451 TX DQ/DQS : PASS
7022 00:58:52.745805 RX DATLAT : PASS
7023 00:58:52.748633 RX DQ/DQS(Engine): PASS
7024 00:58:52.748714 TX OE : NO K
7025 00:58:52.752120 All Pass.
7026 00:58:52.752233
7027 00:58:52.752382 DramC Write-DBI off
7028 00:58:52.755648 PER_BANK_REFRESH: Hybrid Mode
7029 00:58:52.758961 TX_TRACKING: ON
7030 00:58:52.765571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7031 00:58:52.768838 [FAST_K] Save calibration result to emmc
7032 00:58:52.772002 dramc_set_vcore_voltage set vcore to 725000
7033 00:58:52.775367 Read voltage for 1600, 0
7034 00:58:52.775446 Vio18 = 0
7035 00:58:52.778569 Vcore = 725000
7036 00:58:52.778649 Vdram = 0
7037 00:58:52.778712 Vddq = 0
7038 00:58:52.781645 Vmddr = 0
7039 00:58:52.785467 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7040 00:58:52.792219 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7041 00:58:52.792366 MEM_TYPE=3, freq_sel=13
7042 00:58:52.795298 sv_algorithm_assistance_LP4_3733
7043 00:58:52.802275 ============ PULL DRAM RESETB DOWN ============
7044 00:58:52.805616 ========== PULL DRAM RESETB DOWN end =========
7045 00:58:52.808949 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7046 00:58:52.812151 ===================================
7047 00:58:52.815507 LPDDR4 DRAM CONFIGURATION
7048 00:58:52.818862 ===================================
7049 00:58:52.822188 EX_ROW_EN[0] = 0x0
7050 00:58:52.822268 EX_ROW_EN[1] = 0x0
7051 00:58:52.825492 LP4Y_EN = 0x0
7052 00:58:52.825572 WORK_FSP = 0x1
7053 00:58:52.828915 WL = 0x5
7054 00:58:52.828994 RL = 0x5
7055 00:58:52.832121 BL = 0x2
7056 00:58:52.832231 RPST = 0x0
7057 00:58:52.834808 RD_PRE = 0x0
7058 00:58:52.834889 WR_PRE = 0x1
7059 00:58:52.838556 WR_PST = 0x1
7060 00:58:52.838636 DBI_WR = 0x0
7061 00:58:52.841792 DBI_RD = 0x0
7062 00:58:52.841875 OTF = 0x1
7063 00:58:52.844713 ===================================
7064 00:58:52.848234 ===================================
7065 00:58:52.851767 ANA top config
7066 00:58:52.854817 ===================================
7067 00:58:52.858077 DLL_ASYNC_EN = 0
7068 00:58:52.858179 ALL_SLAVE_EN = 0
7069 00:58:52.861803 NEW_RANK_MODE = 1
7070 00:58:52.864625 DLL_IDLE_MODE = 1
7071 00:58:52.868119 LP45_APHY_COMB_EN = 1
7072 00:58:52.871049 TX_ODT_DIS = 0
7073 00:58:52.871163 NEW_8X_MODE = 1
7074 00:58:52.874441 ===================================
7075 00:58:52.877678 ===================================
7076 00:58:52.880942 data_rate = 3200
7077 00:58:52.884707 CKR = 1
7078 00:58:52.887879 DQ_P2S_RATIO = 8
7079 00:58:52.891658 ===================================
7080 00:58:52.894608 CA_P2S_RATIO = 8
7081 00:58:52.897791 DQ_CA_OPEN = 0
7082 00:58:52.897874 DQ_SEMI_OPEN = 0
7083 00:58:52.901050 CA_SEMI_OPEN = 0
7084 00:58:52.904821 CA_FULL_RATE = 0
7085 00:58:52.908140 DQ_CKDIV4_EN = 0
7086 00:58:52.911400 CA_CKDIV4_EN = 0
7087 00:58:52.914718 CA_PREDIV_EN = 0
7088 00:58:52.914795 PH8_DLY = 12
7089 00:58:52.918360 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7090 00:58:52.921358 DQ_AAMCK_DIV = 4
7091 00:58:52.924715 CA_AAMCK_DIV = 4
7092 00:58:52.927871 CA_ADMCK_DIV = 4
7093 00:58:52.931160 DQ_TRACK_CA_EN = 0
7094 00:58:52.931235 CA_PICK = 1600
7095 00:58:52.934460 CA_MCKIO = 1600
7096 00:58:52.937641 MCKIO_SEMI = 0
7097 00:58:52.940960 PLL_FREQ = 3068
7098 00:58:52.944171 DQ_UI_PI_RATIO = 32
7099 00:58:52.947537 CA_UI_PI_RATIO = 0
7100 00:58:52.950864 ===================================
7101 00:58:52.954015 ===================================
7102 00:58:52.957792 memory_type:LPDDR4
7103 00:58:52.957874 GP_NUM : 10
7104 00:58:52.961071 SRAM_EN : 1
7105 00:58:52.961154 MD32_EN : 0
7106 00:58:52.964517 ===================================
7107 00:58:52.967425 [ANA_INIT] >>>>>>>>>>>>>>
7108 00:58:52.970911 <<<<<< [CONFIGURE PHASE]: ANA_TX
7109 00:58:52.974009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7110 00:58:52.977499 ===================================
7111 00:58:52.981033 data_rate = 3200,PCW = 0X7600
7112 00:58:52.984211 ===================================
7113 00:58:52.987334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7114 00:58:52.991011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 00:58:52.997454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7116 00:58:53.000739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7117 00:58:53.007473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7118 00:58:53.010861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7119 00:58:53.010961 [ANA_INIT] flow start
7120 00:58:53.013984 [ANA_INIT] PLL >>>>>>>>
7121 00:58:53.016986 [ANA_INIT] PLL <<<<<<<<
7122 00:58:53.017058 [ANA_INIT] MIDPI >>>>>>>>
7123 00:58:53.020766 [ANA_INIT] MIDPI <<<<<<<<
7124 00:58:53.024081 [ANA_INIT] DLL >>>>>>>>
7125 00:58:53.024184 [ANA_INIT] DLL <<<<<<<<
7126 00:58:53.027347 [ANA_INIT] flow end
7127 00:58:53.030474 ============ LP4 DIFF to SE enter ============
7128 00:58:53.033696 ============ LP4 DIFF to SE exit ============
7129 00:58:53.037482 [ANA_INIT] <<<<<<<<<<<<<
7130 00:58:53.040742 [Flow] Enable top DCM control >>>>>
7131 00:58:53.043951 [Flow] Enable top DCM control <<<<<
7132 00:58:53.047328 Enable DLL master slave shuffle
7133 00:58:53.053749 ==============================================================
7134 00:58:53.053851 Gating Mode config
7135 00:58:53.060302 ==============================================================
7136 00:58:53.060423 Config description:
7137 00:58:53.070210 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7138 00:58:53.076815 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7139 00:58:53.083761 SELPH_MODE 0: By rank 1: By Phase
7140 00:58:53.086844 ==============================================================
7141 00:58:53.090419 GAT_TRACK_EN = 1
7142 00:58:53.093413 RX_GATING_MODE = 2
7143 00:58:53.097141 RX_GATING_TRACK_MODE = 2
7144 00:58:53.100447 SELPH_MODE = 1
7145 00:58:53.103735 PICG_EARLY_EN = 1
7146 00:58:53.106856 VALID_LAT_VALUE = 1
7147 00:58:53.110796 ==============================================================
7148 00:58:53.113901 Enter into Gating configuration >>>>
7149 00:58:53.116944 Exit from Gating configuration <<<<
7150 00:58:53.120479 Enter into DVFS_PRE_config >>>>>
7151 00:58:53.133978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7152 00:58:53.137115 Exit from DVFS_PRE_config <<<<<
7153 00:58:53.140438 Enter into PICG configuration >>>>
7154 00:58:53.143888 Exit from PICG configuration <<<<
7155 00:58:53.143991 [RX_INPUT] configuration >>>>>
7156 00:58:53.147063 [RX_INPUT] configuration <<<<<
7157 00:58:53.153632 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7158 00:58:53.156888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7159 00:58:53.163398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7160 00:58:53.170381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7161 00:58:53.176998 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 00:58:53.183402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 00:58:53.186963 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7164 00:58:53.190034 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7165 00:58:53.197096 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7166 00:58:53.200046 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7167 00:58:53.203648 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7168 00:58:53.206511 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7169 00:58:53.209823 ===================================
7170 00:58:53.213242 LPDDR4 DRAM CONFIGURATION
7171 00:58:53.216571 ===================================
7172 00:58:53.219934 EX_ROW_EN[0] = 0x0
7173 00:58:53.220041 EX_ROW_EN[1] = 0x0
7174 00:58:53.223181 LP4Y_EN = 0x0
7175 00:58:53.223287 WORK_FSP = 0x1
7176 00:58:53.226451 WL = 0x5
7177 00:58:53.226557 RL = 0x5
7178 00:58:53.229769 BL = 0x2
7179 00:58:53.229849 RPST = 0x0
7180 00:58:53.233109 RD_PRE = 0x0
7181 00:58:53.233189 WR_PRE = 0x1
7182 00:58:53.236825 WR_PST = 0x1
7183 00:58:53.236905 DBI_WR = 0x0
7184 00:58:53.239858 DBI_RD = 0x0
7185 00:58:53.239941 OTF = 0x1
7186 00:58:53.243480 ===================================
7187 00:58:53.250244 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7188 00:58:53.252976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7189 00:58:53.256731 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 00:58:53.259823 ===================================
7191 00:58:53.263290 LPDDR4 DRAM CONFIGURATION
7192 00:58:53.267003 ===================================
7193 00:58:53.270180 EX_ROW_EN[0] = 0x10
7194 00:58:53.270256 EX_ROW_EN[1] = 0x0
7195 00:58:53.273406 LP4Y_EN = 0x0
7196 00:58:53.273511 WORK_FSP = 0x1
7197 00:58:53.276844 WL = 0x5
7198 00:58:53.276915 RL = 0x5
7199 00:58:53.280120 BL = 0x2
7200 00:58:53.280214 RPST = 0x0
7201 00:58:53.283581 RD_PRE = 0x0
7202 00:58:53.283674 WR_PRE = 0x1
7203 00:58:53.286654 WR_PST = 0x1
7204 00:58:53.286745 DBI_WR = 0x0
7205 00:58:53.289881 DBI_RD = 0x0
7206 00:58:53.289949 OTF = 0x1
7207 00:58:53.293038 ===================================
7208 00:58:53.299777 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7209 00:58:53.299853 ==
7210 00:58:53.302939 Dram Type= 6, Freq= 0, CH_0, rank 0
7211 00:58:53.306777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7212 00:58:53.309995 ==
7213 00:58:53.310089 [Duty_Offset_Calibration]
7214 00:58:53.313535 B0:2 B1:1 CA:1
7215 00:58:53.313630
7216 00:58:53.316423 [DutyScan_Calibration_Flow] k_type=0
7217 00:58:53.325229
7218 00:58:53.325304 ==CLK 0==
7219 00:58:53.329114 Final CLK duty delay cell = 0
7220 00:58:53.332256 [0] MAX Duty = 5156%(X100), DQS PI = 22
7221 00:58:53.335481 [0] MIN Duty = 4907%(X100), DQS PI = 0
7222 00:58:53.335579 [0] AVG Duty = 5031%(X100)
7223 00:58:53.338607
7224 00:58:53.341848 CH0 CLK Duty spec in!! Max-Min= 249%
7225 00:58:53.345626 [DutyScan_Calibration_Flow] ====Done====
7226 00:58:53.345704
7227 00:58:53.348828 [DutyScan_Calibration_Flow] k_type=1
7228 00:58:53.364297
7229 00:58:53.364417 ==DQS 0 ==
7230 00:58:53.367887 Final DQS duty delay cell = -4
7231 00:58:53.371391 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7232 00:58:53.374148 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7233 00:58:53.377910 [-4] AVG Duty = 4891%(X100)
7234 00:58:53.377977
7235 00:58:53.378035 ==DQS 1 ==
7236 00:58:53.380959 Final DQS duty delay cell = 0
7237 00:58:53.384584 [0] MAX Duty = 5187%(X100), DQS PI = 4
7238 00:58:53.387539 [0] MIN Duty = 5062%(X100), DQS PI = 30
7239 00:58:53.390998 [0] AVG Duty = 5124%(X100)
7240 00:58:53.391083
7241 00:58:53.394659 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7242 00:58:53.394742
7243 00:58:53.397871 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7244 00:58:53.401099 [DutyScan_Calibration_Flow] ====Done====
7245 00:58:53.401182
7246 00:58:53.404753 [DutyScan_Calibration_Flow] k_type=3
7247 00:58:53.421173
7248 00:58:53.421257 ==DQM 0 ==
7249 00:58:53.424195 Final DQM duty delay cell = 0
7250 00:58:53.427965 [0] MAX Duty = 5218%(X100), DQS PI = 34
7251 00:58:53.431653 [0] MIN Duty = 4907%(X100), DQS PI = 56
7252 00:58:53.431763 [0] AVG Duty = 5062%(X100)
7253 00:58:53.434281
7254 00:58:53.434361 ==DQM 1 ==
7255 00:58:53.438046 Final DQM duty delay cell = -4
7256 00:58:53.441256 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7257 00:58:53.444507 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7258 00:58:53.447726 [-4] AVG Duty = 4891%(X100)
7259 00:58:53.447806
7260 00:58:53.451008 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7261 00:58:53.451088
7262 00:58:53.454619 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7263 00:58:53.457770 [DutyScan_Calibration_Flow] ====Done====
7264 00:58:53.457851
7265 00:58:53.461067 [DutyScan_Calibration_Flow] k_type=2
7266 00:58:53.478558
7267 00:58:53.478638 ==DQ 0 ==
7268 00:58:53.481939 Final DQ duty delay cell = 0
7269 00:58:53.485197 [0] MAX Duty = 5062%(X100), DQS PI = 26
7270 00:58:53.488489 [0] MIN Duty = 4907%(X100), DQS PI = 0
7271 00:58:53.488570 [0] AVG Duty = 4984%(X100)
7272 00:58:53.491670
7273 00:58:53.491749 ==DQ 1 ==
7274 00:58:53.495176 Final DQ duty delay cell = 0
7275 00:58:53.498750 [0] MAX Duty = 5125%(X100), DQS PI = 6
7276 00:58:53.501651 [0] MIN Duty = 4907%(X100), DQS PI = 34
7277 00:58:53.501734 [0] AVG Duty = 5016%(X100)
7278 00:58:53.501836
7279 00:58:53.505108 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7280 00:58:53.508494
7281 00:58:53.511525 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7282 00:58:53.514970 [DutyScan_Calibration_Flow] ====Done====
7283 00:58:53.515056 ==
7284 00:58:53.518464 Dram Type= 6, Freq= 0, CH_1, rank 0
7285 00:58:53.521661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 00:58:53.521745 ==
7287 00:58:53.524929 [Duty_Offset_Calibration]
7288 00:58:53.525011 B0:1 B1:0 CA:0
7289 00:58:53.525095
7290 00:58:53.528608 [DutyScan_Calibration_Flow] k_type=0
7291 00:58:53.538030
7292 00:58:53.538139 ==CLK 0==
7293 00:58:53.541603 Final CLK duty delay cell = -4
7294 00:58:53.544409 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7295 00:58:53.547951 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7296 00:58:53.551059 [-4] AVG Duty = 4906%(X100)
7297 00:58:53.551139
7298 00:58:53.554539 CH1 CLK Duty spec in!! Max-Min= 125%
7299 00:58:53.558157 [DutyScan_Calibration_Flow] ====Done====
7300 00:58:53.558238
7301 00:58:53.561166 [DutyScan_Calibration_Flow] k_type=1
7302 00:58:53.577793
7303 00:58:53.577872 ==DQS 0 ==
7304 00:58:53.581069 Final DQS duty delay cell = 0
7305 00:58:53.584405 [0] MAX Duty = 5094%(X100), DQS PI = 46
7306 00:58:53.587796 [0] MIN Duty = 4844%(X100), DQS PI = 14
7307 00:58:53.591604 [0] AVG Duty = 4969%(X100)
7308 00:58:53.591708
7309 00:58:53.591799 ==DQS 1 ==
7310 00:58:53.594906 Final DQS duty delay cell = 0
7311 00:58:53.598243 [0] MAX Duty = 5249%(X100), DQS PI = 48
7312 00:58:53.601466 [0] MIN Duty = 4907%(X100), DQS PI = 40
7313 00:58:53.604954 [0] AVG Duty = 5078%(X100)
7314 00:58:53.605034
7315 00:58:53.608212 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7316 00:58:53.608315
7317 00:58:53.611617 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7318 00:58:53.614778 [DutyScan_Calibration_Flow] ====Done====
7319 00:58:53.614858
7320 00:58:53.617966 [DutyScan_Calibration_Flow] k_type=3
7321 00:58:53.634783
7322 00:58:53.634888 ==DQM 0 ==
7323 00:58:53.638455 Final DQM duty delay cell = 0
7324 00:58:53.641477 [0] MAX Duty = 5187%(X100), DQS PI = 40
7325 00:58:53.644923 [0] MIN Duty = 5000%(X100), DQS PI = 16
7326 00:58:53.648165 [0] AVG Duty = 5093%(X100)
7327 00:58:53.648244
7328 00:58:53.648327 ==DQM 1 ==
7329 00:58:53.651545 Final DQM duty delay cell = 0
7330 00:58:53.654702 [0] MAX Duty = 5093%(X100), DQS PI = 8
7331 00:58:53.658176 [0] MIN Duty = 4907%(X100), DQS PI = 0
7332 00:58:53.658300 [0] AVG Duty = 5000%(X100)
7333 00:58:53.658411
7334 00:58:53.665067 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7335 00:58:53.665147
7336 00:58:53.668539 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7337 00:58:53.671499 [DutyScan_Calibration_Flow] ====Done====
7338 00:58:53.671592
7339 00:58:53.674610 [DutyScan_Calibration_Flow] k_type=2
7340 00:58:53.690812
7341 00:58:53.690917 ==DQ 0 ==
7342 00:58:53.693988 Final DQ duty delay cell = -4
7343 00:58:53.697500 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7344 00:58:53.700656 [-4] MIN Duty = 4875%(X100), DQS PI = 14
7345 00:58:53.704112 [-4] AVG Duty = 4953%(X100)
7346 00:58:53.704217
7347 00:58:53.704344 ==DQ 1 ==
7348 00:58:53.707546 Final DQ duty delay cell = 0
7349 00:58:53.710769 [0] MAX Duty = 5093%(X100), DQS PI = 8
7350 00:58:53.714072 [0] MIN Duty = 4938%(X100), DQS PI = 0
7351 00:58:53.714152 [0] AVG Duty = 5015%(X100)
7352 00:58:53.717265
7353 00:58:53.721136 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7354 00:58:53.721241
7355 00:58:53.724544 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7356 00:58:53.727137 [DutyScan_Calibration_Flow] ====Done====
7357 00:58:53.731211 nWR fixed to 30
7358 00:58:53.731291 [ModeRegInit_LP4] CH0 RK0
7359 00:58:53.734404 [ModeRegInit_LP4] CH0 RK1
7360 00:58:53.737069 [ModeRegInit_LP4] CH1 RK0
7361 00:58:53.740883 [ModeRegInit_LP4] CH1 RK1
7362 00:58:53.740963 match AC timing 5
7363 00:58:53.747234 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7364 00:58:53.750485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7365 00:58:53.754151 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7366 00:58:53.760530 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7367 00:58:53.763727 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7368 00:58:53.763807 [MiockJmeterHQA]
7369 00:58:53.763869
7370 00:58:53.767287 [DramcMiockJmeter] u1RxGatingPI = 0
7371 00:58:53.770773 0 : 4363, 4138
7372 00:58:53.770854 4 : 4252, 4027
7373 00:58:53.773933 8 : 4252, 4027
7374 00:58:53.774040 12 : 4252, 4027
7375 00:58:53.774132 16 : 4253, 4027
7376 00:58:53.776898 20 : 4252, 4027
7377 00:58:53.776986 24 : 4250, 4027
7378 00:58:53.780244 28 : 4363, 4137
7379 00:58:53.780415 32 : 4252, 4027
7380 00:58:53.783591 36 : 4250, 4027
7381 00:58:53.783675 40 : 4252, 4026
7382 00:58:53.786952 44 : 4252, 4029
7383 00:58:53.787036 48 : 4249, 4027
7384 00:58:53.787122 52 : 4363, 4137
7385 00:58:53.790549 56 : 4360, 4138
7386 00:58:53.790633 60 : 4253, 4026
7387 00:58:53.793645 64 : 4250, 4027
7388 00:58:53.793729 68 : 4249, 4027
7389 00:58:53.796936 72 : 4250, 4026
7390 00:58:53.797020 76 : 4252, 4030
7391 00:58:53.797137 80 : 4360, 4137
7392 00:58:53.800708 84 : 4250, 4026
7393 00:58:53.800839 88 : 4249, 66
7394 00:58:53.803899 92 : 4253, 0
7395 00:58:53.803983 96 : 4363, 0
7396 00:58:53.804068 100 : 4252, 0
7397 00:58:53.807165 104 : 4249, 0
7398 00:58:53.807250 108 : 4250, 0
7399 00:58:53.809944 112 : 4250, 0
7400 00:58:53.810029 116 : 4249, 0
7401 00:58:53.810133 120 : 4252, 0
7402 00:58:53.813741 124 : 4361, 0
7403 00:58:53.813843 128 : 4360, 0
7404 00:58:53.817379 132 : 4363, 0
7405 00:58:53.817502 136 : 4250, 0
7406 00:58:53.817626 140 : 4250, 0
7407 00:58:53.820035 144 : 4249, 0
7408 00:58:53.820116 148 : 4250, 0
7409 00:58:53.823772 152 : 4250, 0
7410 00:58:53.823869 156 : 4249, 0
7411 00:58:53.823964 160 : 4252, 0
7412 00:58:53.827083 164 : 4250, 0
7413 00:58:53.827165 168 : 4249, 0
7414 00:58:53.827245 172 : 4252, 0
7415 00:58:53.830578 176 : 4361, 0
7416 00:58:53.830659 180 : 4360, 0
7417 00:58:53.833784 184 : 4249, 0
7418 00:58:53.833867 188 : 4250, 0
7419 00:58:53.833962 192 : 4250, 0
7420 00:58:53.837033 196 : 4249, 0
7421 00:58:53.837116 200 : 4250, 0
7422 00:58:53.840406 204 : 4250, 1638
7423 00:58:53.840502 208 : 4250, 3985
7424 00:58:53.843657 212 : 4252, 4030
7425 00:58:53.843759 216 : 4250, 4027
7426 00:58:53.846992 220 : 4250, 4026
7427 00:58:53.847073 224 : 4361, 4137
7428 00:58:53.847138 228 : 4250, 4027
7429 00:58:53.850416 232 : 4249, 4027
7430 00:58:53.850514 236 : 4360, 4137
7431 00:58:53.853787 240 : 4250, 4026
7432 00:58:53.853900 244 : 4250, 4027
7433 00:58:53.856465 248 : 4363, 4140
7434 00:58:53.856610 252 : 4250, 4026
7435 00:58:53.860196 256 : 4250, 4026
7436 00:58:53.860278 260 : 4250, 4027
7437 00:58:53.863393 264 : 4252, 4030
7438 00:58:53.863474 268 : 4249, 4027
7439 00:58:53.866724 272 : 4250, 4026
7440 00:58:53.866805 276 : 4361, 4137
7441 00:58:53.870185 280 : 4250, 4027
7442 00:58:53.870266 284 : 4249, 4027
7443 00:58:53.873469 288 : 4361, 4138
7444 00:58:53.873552 292 : 4250, 4026
7445 00:58:53.873618 296 : 4250, 4027
7446 00:58:53.876037 300 : 4363, 4140
7447 00:58:53.876120 304 : 4249, 4027
7448 00:58:53.879919 308 : 4250, 3916
7449 00:58:53.880001 312 : 4250, 1779
7450 00:58:53.880067
7451 00:58:53.882873 MIOCK jitter meter ch=0
7452 00:58:53.882968
7453 00:58:53.886094 1T = (312-88) = 224 dly cells
7454 00:58:53.892652 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7455 00:58:53.892735 ==
7456 00:58:53.896250 Dram Type= 6, Freq= 0, CH_0, rank 0
7457 00:58:53.899327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7458 00:58:53.899410 ==
7459 00:58:53.906393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7460 00:58:53.909601 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7461 00:58:53.912635 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7462 00:58:53.919755 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7463 00:58:53.928292 [CA 0] Center 42 (12~73) winsize 62
7464 00:58:53.931978 [CA 1] Center 42 (12~73) winsize 62
7465 00:58:53.934994 [CA 2] Center 38 (8~68) winsize 61
7466 00:58:53.938104 [CA 3] Center 37 (8~67) winsize 60
7467 00:58:53.941592 [CA 4] Center 36 (7~66) winsize 60
7468 00:58:53.945107 [CA 5] Center 35 (6~65) winsize 60
7469 00:58:53.945212
7470 00:58:53.948261 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7471 00:58:53.948361
7472 00:58:53.951805 [CATrainingPosCal] consider 1 rank data
7473 00:58:53.955032 u2DelayCellTimex100 = 290/100 ps
7474 00:58:53.958400 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7475 00:58:53.964759 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7476 00:58:53.968569 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7477 00:58:53.971726 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7478 00:58:53.974988 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7479 00:58:53.978389 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7480 00:58:53.978463
7481 00:58:53.981707 CA PerBit enable=1, Macro0, CA PI delay=35
7482 00:58:53.981791
7483 00:58:53.985154 [CBTSetCACLKResult] CA Dly = 35
7484 00:58:53.988336 CS Dly: 9 (0~40)
7485 00:58:53.991422 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7486 00:58:53.994941 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7487 00:58:53.995022 ==
7488 00:58:53.998323 Dram Type= 6, Freq= 0, CH_0, rank 1
7489 00:58:54.001447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7490 00:58:54.001527 ==
7491 00:58:54.008122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7492 00:58:54.011289 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7493 00:58:54.018464 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7494 00:58:54.021521 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7495 00:58:54.031686 [CA 0] Center 42 (12~73) winsize 62
7496 00:58:54.035098 [CA 1] Center 42 (12~73) winsize 62
7497 00:58:54.038267 [CA 2] Center 38 (8~68) winsize 61
7498 00:58:54.041445 [CA 3] Center 38 (8~68) winsize 61
7499 00:58:54.044628 [CA 4] Center 36 (6~66) winsize 61
7500 00:58:54.048270 [CA 5] Center 35 (5~65) winsize 61
7501 00:58:54.048393
7502 00:58:54.051715 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7503 00:58:54.051800
7504 00:58:54.054882 [CATrainingPosCal] consider 2 rank data
7505 00:58:54.058151 u2DelayCellTimex100 = 290/100 ps
7506 00:58:54.061370 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7507 00:58:54.068068 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7508 00:58:54.071261 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7509 00:58:54.075048 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7510 00:58:54.078280 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7511 00:58:54.081582 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7512 00:58:54.081692
7513 00:58:54.085018 CA PerBit enable=1, Macro0, CA PI delay=35
7514 00:58:54.085121
7515 00:58:54.088217 [CBTSetCACLKResult] CA Dly = 35
7516 00:58:54.091501 CS Dly: 10 (0~42)
7517 00:58:54.094538 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7518 00:58:54.098478 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7519 00:58:54.098583
7520 00:58:54.101579 ----->DramcWriteLeveling(PI) begin...
7521 00:58:54.101653 ==
7522 00:58:54.104643 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 00:58:54.108577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 00:58:54.111738 ==
7525 00:58:54.111861 Write leveling (Byte 0): 36 => 36
7526 00:58:54.114920 Write leveling (Byte 1): 26 => 26
7527 00:58:54.118386 DramcWriteLeveling(PI) end<-----
7528 00:58:54.118517
7529 00:58:54.118614 ==
7530 00:58:54.121717 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 00:58:54.127766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 00:58:54.127843 ==
7533 00:58:54.131521 [Gating] SW mode calibration
7534 00:58:54.137884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7535 00:58:54.141075 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7536 00:58:54.148222 1 4 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7537 00:58:54.151602 1 4 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7538 00:58:54.154807 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7539 00:58:54.161229 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7540 00:58:54.164475 1 4 16 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
7541 00:58:54.167802 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 00:58:54.171501 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7543 00:58:54.177901 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7544 00:58:54.180836 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7545 00:58:54.184445 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 00:58:54.190848 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7547 00:58:54.194234 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
7548 00:58:54.197523 1 5 16 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
7549 00:58:54.204334 1 5 20 | B1->B0 | 2525 2525 | 0 0 | (1 0) (0 0)
7550 00:58:54.207725 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7551 00:58:54.211349 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7552 00:58:54.217754 1 6 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7553 00:58:54.220898 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 00:58:54.224425 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7555 00:58:54.230913 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7556 00:58:54.233902 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7557 00:58:54.237478 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7558 00:58:54.244059 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7559 00:58:54.247152 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 00:58:54.251113 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 00:58:54.257702 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 00:58:54.260824 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 00:58:54.264082 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 00:58:54.270501 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7565 00:58:54.273757 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 00:58:54.277016 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 00:58:54.284247 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 00:58:54.287480 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 00:58:54.290695 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 00:58:54.297481 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 00:58:54.300417 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 00:58:54.303834 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 00:58:54.311010 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 00:58:54.313981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 00:58:54.317453 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 00:58:54.320603 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 00:58:54.327456 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 00:58:54.330369 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7579 00:58:54.333711 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 00:58:54.340478 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 00:58:54.343889 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7582 00:58:54.346951 Total UI for P1: 0, mck2ui 16
7583 00:58:54.350378 best dqsien dly found for B0: ( 1, 9, 12)
7584 00:58:54.353734 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 00:58:54.357136 Total UI for P1: 0, mck2ui 16
7586 00:58:54.360445 best dqsien dly found for B1: ( 1, 9, 20)
7587 00:58:54.363682 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7588 00:58:54.366755 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7589 00:58:54.366835
7590 00:58:54.373977 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7591 00:58:54.377255 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7592 00:58:54.380420 [Gating] SW calibration Done
7593 00:58:54.380501 ==
7594 00:58:54.383728 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 00:58:54.387059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 00:58:54.387141 ==
7597 00:58:54.387204 RX Vref Scan: 0
7598 00:58:54.390273
7599 00:58:54.390353 RX Vref 0 -> 0, step: 1
7600 00:58:54.390416
7601 00:58:54.393462 RX Delay 0 -> 252, step: 8
7602 00:58:54.397198 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7603 00:58:54.400487 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7604 00:58:54.407087 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7605 00:58:54.410285 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7606 00:58:54.413558 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7607 00:58:54.416761 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7608 00:58:54.420008 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7609 00:58:54.423609 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7610 00:58:54.430137 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7611 00:58:54.433571 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7612 00:58:54.437192 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7613 00:58:54.440093 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7614 00:58:54.443460 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7615 00:58:54.450206 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7616 00:58:54.453518 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7617 00:58:54.456988 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7618 00:58:54.457092 ==
7619 00:58:54.460414 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 00:58:54.463734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 00:58:54.466912 ==
7622 00:58:54.466992 DQS Delay:
7623 00:58:54.467055 DQS0 = 0, DQS1 = 0
7624 00:58:54.470204 DQM Delay:
7625 00:58:54.470284 DQM0 = 137, DQM1 = 130
7626 00:58:54.473093 DQ Delay:
7627 00:58:54.476730 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7628 00:58:54.480232 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7629 00:58:54.483456 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7630 00:58:54.486836 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7631 00:58:54.486918
7632 00:58:54.486981
7633 00:58:54.487039 ==
7634 00:58:54.490018 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 00:58:54.493204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 00:58:54.493286 ==
7637 00:58:54.493349
7638 00:58:54.497093
7639 00:58:54.497172 TX Vref Scan disable
7640 00:58:54.500219 == TX Byte 0 ==
7641 00:58:54.503407 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7642 00:58:54.506689 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7643 00:58:54.510008 == TX Byte 1 ==
7644 00:58:54.513033 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7645 00:58:54.516422 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7646 00:58:54.516523 ==
7647 00:58:54.519810 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 00:58:54.526800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 00:58:54.526899 ==
7650 00:58:54.539137
7651 00:58:54.542411 TX Vref early break, caculate TX vref
7652 00:58:54.545780 TX Vref=16, minBit 4, minWin=22, winSum=379
7653 00:58:54.549079 TX Vref=18, minBit 0, minWin=23, winSum=386
7654 00:58:54.552397 TX Vref=20, minBit 0, minWin=24, winSum=400
7655 00:58:54.555482 TX Vref=22, minBit 0, minWin=24, winSum=407
7656 00:58:54.559098 TX Vref=24, minBit 0, minWin=25, winSum=415
7657 00:58:54.565585 TX Vref=26, minBit 2, minWin=25, winSum=425
7658 00:58:54.568914 TX Vref=28, minBit 1, minWin=24, winSum=422
7659 00:58:54.572302 TX Vref=30, minBit 1, minWin=24, winSum=414
7660 00:58:54.575535 TX Vref=32, minBit 6, minWin=23, winSum=403
7661 00:58:54.578853 TX Vref=34, minBit 6, minWin=23, winSum=395
7662 00:58:54.585561 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 26
7663 00:58:54.585670
7664 00:58:54.588811 Final TX Range 0 Vref 26
7665 00:58:54.588892
7666 00:58:54.588990 ==
7667 00:58:54.592313 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 00:58:54.595502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 00:58:54.595583 ==
7670 00:58:54.595683
7671 00:58:54.595741
7672 00:58:54.598529 TX Vref Scan disable
7673 00:58:54.605668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7674 00:58:54.605747 == TX Byte 0 ==
7675 00:58:54.608878 u2DelayCellOfst[0]=10 cells (3 PI)
7676 00:58:54.612026 u2DelayCellOfst[1]=13 cells (4 PI)
7677 00:58:54.615396 u2DelayCellOfst[2]=10 cells (3 PI)
7678 00:58:54.618608 u2DelayCellOfst[3]=6 cells (2 PI)
7679 00:58:54.622221 u2DelayCellOfst[4]=6 cells (2 PI)
7680 00:58:54.625445 u2DelayCellOfst[5]=0 cells (0 PI)
7681 00:58:54.628703 u2DelayCellOfst[6]=16 cells (5 PI)
7682 00:58:54.631990 u2DelayCellOfst[7]=16 cells (5 PI)
7683 00:58:54.635254 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7684 00:58:54.638506 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7685 00:58:54.641722 == TX Byte 1 ==
7686 00:58:54.641802 u2DelayCellOfst[8]=0 cells (0 PI)
7687 00:58:54.645019 u2DelayCellOfst[9]=0 cells (0 PI)
7688 00:58:54.648241 u2DelayCellOfst[10]=6 cells (2 PI)
7689 00:58:54.652168 u2DelayCellOfst[11]=3 cells (1 PI)
7690 00:58:54.655497 u2DelayCellOfst[12]=13 cells (4 PI)
7691 00:58:54.658934 u2DelayCellOfst[13]=13 cells (4 PI)
7692 00:58:54.661615 u2DelayCellOfst[14]=16 cells (5 PI)
7693 00:58:54.664912 u2DelayCellOfst[15]=10 cells (3 PI)
7694 00:58:54.668806 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7695 00:58:54.675095 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7696 00:58:54.675175 DramC Write-DBI on
7697 00:58:54.675253 ==
7698 00:58:54.678391 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 00:58:54.684678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 00:58:54.684759 ==
7701 00:58:54.684836
7702 00:58:54.684939
7703 00:58:54.684995 TX Vref Scan disable
7704 00:58:54.688579 == TX Byte 0 ==
7705 00:58:54.692116 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7706 00:58:54.695563 == TX Byte 1 ==
7707 00:58:54.698731 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7708 00:58:54.701767 DramC Write-DBI off
7709 00:58:54.701917
7710 00:58:54.702039 [DATLAT]
7711 00:58:54.702187 Freq=1600, CH0 RK0
7712 00:58:54.702274
7713 00:58:54.705097 DATLAT Default: 0xf
7714 00:58:54.705179 0, 0xFFFF, sum = 0
7715 00:58:54.708921 1, 0xFFFF, sum = 0
7716 00:58:54.709019 2, 0xFFFF, sum = 0
7717 00:58:54.711817 3, 0xFFFF, sum = 0
7718 00:58:54.715637 4, 0xFFFF, sum = 0
7719 00:58:54.715734 5, 0xFFFF, sum = 0
7720 00:58:54.718839 6, 0xFFFF, sum = 0
7721 00:58:54.718950 7, 0xFFFF, sum = 0
7722 00:58:54.722140 8, 0xFFFF, sum = 0
7723 00:58:54.722250 9, 0xFFFF, sum = 0
7724 00:58:54.725396 10, 0xFFFF, sum = 0
7725 00:58:54.725522 11, 0xFFFF, sum = 0
7726 00:58:54.728717 12, 0xFFFF, sum = 0
7727 00:58:54.728813 13, 0xFFFF, sum = 0
7728 00:58:54.732293 14, 0x0, sum = 1
7729 00:58:54.732407 15, 0x0, sum = 2
7730 00:58:54.734939 16, 0x0, sum = 3
7731 00:58:54.735021 17, 0x0, sum = 4
7732 00:58:54.738532 best_step = 15
7733 00:58:54.738628
7734 00:58:54.738692 ==
7735 00:58:54.741927 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 00:58:54.745071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 00:58:54.745153 ==
7738 00:58:54.745222 RX Vref Scan: 1
7739 00:58:54.748623
7740 00:58:54.748720 Set Vref Range= 24 -> 127
7741 00:58:54.748827
7742 00:58:54.751845 RX Vref 24 -> 127, step: 1
7743 00:58:54.751940
7744 00:58:54.755213 RX Delay 19 -> 252, step: 4
7745 00:58:54.755293
7746 00:58:54.758402 Set Vref, RX VrefLevel [Byte0]: 24
7747 00:58:54.761751 [Byte1]: 24
7748 00:58:54.761832
7749 00:58:54.765080 Set Vref, RX VrefLevel [Byte0]: 25
7750 00:58:54.768192 [Byte1]: 25
7751 00:58:54.768321
7752 00:58:54.772088 Set Vref, RX VrefLevel [Byte0]: 26
7753 00:58:54.775204 [Byte1]: 26
7754 00:58:54.778877
7755 00:58:54.778957 Set Vref, RX VrefLevel [Byte0]: 27
7756 00:58:54.782866 [Byte1]: 27
7757 00:58:54.786725
7758 00:58:54.786804 Set Vref, RX VrefLevel [Byte0]: 28
7759 00:58:54.789955 [Byte1]: 28
7760 00:58:54.793863
7761 00:58:54.793945 Set Vref, RX VrefLevel [Byte0]: 29
7762 00:58:54.797113 [Byte1]: 29
7763 00:58:54.801650
7764 00:58:54.801731 Set Vref, RX VrefLevel [Byte0]: 30
7765 00:58:54.804648 [Byte1]: 30
7766 00:58:54.809357
7767 00:58:54.809438 Set Vref, RX VrefLevel [Byte0]: 31
7768 00:58:54.812768 [Byte1]: 31
7769 00:58:54.816537
7770 00:58:54.816618 Set Vref, RX VrefLevel [Byte0]: 32
7771 00:58:54.820011 [Byte1]: 32
7772 00:58:54.824701
7773 00:58:54.824786 Set Vref, RX VrefLevel [Byte0]: 33
7774 00:58:54.827731 [Byte1]: 33
7775 00:58:54.831645
7776 00:58:54.831726 Set Vref, RX VrefLevel [Byte0]: 34
7777 00:58:54.835523 [Byte1]: 34
7778 00:58:54.839551
7779 00:58:54.839632 Set Vref, RX VrefLevel [Byte0]: 35
7780 00:58:54.842754 [Byte1]: 35
7781 00:58:54.847424
7782 00:58:54.847505 Set Vref, RX VrefLevel [Byte0]: 36
7783 00:58:54.850716 [Byte1]: 36
7784 00:58:54.854571
7785 00:58:54.854652 Set Vref, RX VrefLevel [Byte0]: 37
7786 00:58:54.858031 [Byte1]: 37
7787 00:58:54.862061
7788 00:58:54.862143 Set Vref, RX VrefLevel [Byte0]: 38
7789 00:58:54.865227 [Byte1]: 38
7790 00:58:54.869977
7791 00:58:54.870059 Set Vref, RX VrefLevel [Byte0]: 39
7792 00:58:54.873158 [Byte1]: 39
7793 00:58:54.877677
7794 00:58:54.877758 Set Vref, RX VrefLevel [Byte0]: 40
7795 00:58:54.880600 [Byte1]: 40
7796 00:58:54.885085
7797 00:58:54.885166 Set Vref, RX VrefLevel [Byte0]: 41
7798 00:58:54.888522 [Byte1]: 41
7799 00:58:54.892668
7800 00:58:54.892748 Set Vref, RX VrefLevel [Byte0]: 42
7801 00:58:54.896207 [Byte1]: 42
7802 00:58:54.900321
7803 00:58:54.900415 Set Vref, RX VrefLevel [Byte0]: 43
7804 00:58:54.903635 [Byte1]: 43
7805 00:58:54.907510
7806 00:58:54.907589 Set Vref, RX VrefLevel [Byte0]: 44
7807 00:58:54.910733 [Byte1]: 44
7808 00:58:54.915180
7809 00:58:54.915259 Set Vref, RX VrefLevel [Byte0]: 45
7810 00:58:54.918226 [Byte1]: 45
7811 00:58:54.922683
7812 00:58:54.922762 Set Vref, RX VrefLevel [Byte0]: 46
7813 00:58:54.926102 [Byte1]: 46
7814 00:58:54.930143
7815 00:58:54.930223 Set Vref, RX VrefLevel [Byte0]: 47
7816 00:58:54.933664 [Byte1]: 47
7817 00:58:54.938104
7818 00:58:54.938184 Set Vref, RX VrefLevel [Byte0]: 48
7819 00:58:54.941376 [Byte1]: 48
7820 00:58:54.945380
7821 00:58:54.945460 Set Vref, RX VrefLevel [Byte0]: 49
7822 00:58:54.948702 [Byte1]: 49
7823 00:58:54.953282
7824 00:58:54.953362 Set Vref, RX VrefLevel [Byte0]: 50
7825 00:58:54.956409 [Byte1]: 50
7826 00:58:54.960262
7827 00:58:54.960364 Set Vref, RX VrefLevel [Byte0]: 51
7828 00:58:54.964274 [Byte1]: 51
7829 00:58:54.968195
7830 00:58:54.968322 Set Vref, RX VrefLevel [Byte0]: 52
7831 00:58:54.971475 [Byte1]: 52
7832 00:58:54.975598
7833 00:58:54.975678 Set Vref, RX VrefLevel [Byte0]: 53
7834 00:58:54.978896 [Byte1]: 53
7835 00:58:54.983291
7836 00:58:54.983373 Set Vref, RX VrefLevel [Byte0]: 54
7837 00:58:54.986426 [Byte1]: 54
7838 00:58:54.991144
7839 00:58:54.991224 Set Vref, RX VrefLevel [Byte0]: 55
7840 00:58:54.993931 [Byte1]: 55
7841 00:58:54.998910
7842 00:58:54.999023 Set Vref, RX VrefLevel [Byte0]: 56
7843 00:58:55.001673 [Byte1]: 56
7844 00:58:55.006125
7845 00:58:55.006204 Set Vref, RX VrefLevel [Byte0]: 57
7846 00:58:55.009237 [Byte1]: 57
7847 00:58:55.013453
7848 00:58:55.013532 Set Vref, RX VrefLevel [Byte0]: 58
7849 00:58:55.016824 [Byte1]: 58
7850 00:58:55.021039
7851 00:58:55.021119 Set Vref, RX VrefLevel [Byte0]: 59
7852 00:58:55.024618 [Byte1]: 59
7853 00:58:55.029069
7854 00:58:55.029149 Set Vref, RX VrefLevel [Byte0]: 60
7855 00:58:55.032149 [Byte1]: 60
7856 00:58:55.036217
7857 00:58:55.036320 Set Vref, RX VrefLevel [Byte0]: 61
7858 00:58:55.039707 [Byte1]: 61
7859 00:58:55.043697
7860 00:58:55.043782 Set Vref, RX VrefLevel [Byte0]: 62
7861 00:58:55.047333 [Byte1]: 62
7862 00:58:55.051601
7863 00:58:55.051681 Set Vref, RX VrefLevel [Byte0]: 63
7864 00:58:55.054854 [Byte1]: 63
7865 00:58:55.058734
7866 00:58:55.058814 Set Vref, RX VrefLevel [Byte0]: 64
7867 00:58:55.062124 [Byte1]: 64
7868 00:58:55.066686
7869 00:58:55.066766 Set Vref, RX VrefLevel [Byte0]: 65
7870 00:58:55.069942 [Byte1]: 65
7871 00:58:55.074514
7872 00:58:55.074625 Set Vref, RX VrefLevel [Byte0]: 66
7873 00:58:55.077786 [Byte1]: 66
7874 00:58:55.082096
7875 00:58:55.082176 Set Vref, RX VrefLevel [Byte0]: 67
7876 00:58:55.085136 [Byte1]: 67
7877 00:58:55.089199
7878 00:58:55.089293 Set Vref, RX VrefLevel [Byte0]: 68
7879 00:58:55.092514 [Byte1]: 68
7880 00:58:55.096900
7881 00:58:55.096980 Set Vref, RX VrefLevel [Byte0]: 69
7882 00:58:55.100199 [Byte1]: 69
7883 00:58:55.104685
7884 00:58:55.104765 Set Vref, RX VrefLevel [Byte0]: 70
7885 00:58:55.107680 [Byte1]: 70
7886 00:58:55.112069
7887 00:58:55.112149 Set Vref, RX VrefLevel [Byte0]: 71
7888 00:58:55.115819 [Byte1]: 71
7889 00:58:55.119830
7890 00:58:55.119910 Set Vref, RX VrefLevel [Byte0]: 72
7891 00:58:55.122891 [Byte1]: 72
7892 00:58:55.127077
7893 00:58:55.127157 Set Vref, RX VrefLevel [Byte0]: 73
7894 00:58:55.130674 [Byte1]: 73
7895 00:58:55.134861
7896 00:58:55.134967 Set Vref, RX VrefLevel [Byte0]: 74
7897 00:58:55.138091 [Byte1]: 74
7898 00:58:55.142147
7899 00:58:55.142256 Set Vref, RX VrefLevel [Byte0]: 75
7900 00:58:55.145689 [Byte1]: 75
7901 00:58:55.149874
7902 00:58:55.149974 Final RX Vref Byte 0 = 54 to rank0
7903 00:58:55.153136 Final RX Vref Byte 1 = 60 to rank0
7904 00:58:55.156668 Final RX Vref Byte 0 = 54 to rank1
7905 00:58:55.159697 Final RX Vref Byte 1 = 60 to rank1==
7906 00:58:55.163075 Dram Type= 6, Freq= 0, CH_0, rank 0
7907 00:58:55.169944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7908 00:58:55.170050 ==
7909 00:58:55.170145 DQS Delay:
7910 00:58:55.170219 DQS0 = 0, DQS1 = 0
7911 00:58:55.173150 DQM Delay:
7912 00:58:55.173230 DQM0 = 133, DQM1 = 127
7913 00:58:55.176444 DQ Delay:
7914 00:58:55.180170 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7915 00:58:55.183519 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =138
7916 00:58:55.186867 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7917 00:58:55.189921 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7918 00:58:55.190002
7919 00:58:55.190106
7920 00:58:55.190164
7921 00:58:55.193560 [DramC_TX_OE_Calibration] TA2
7922 00:58:55.196770 Original DQ_B0 (3 6) =30, OEN = 27
7923 00:58:55.200057 Original DQ_B1 (3 6) =30, OEN = 27
7924 00:58:55.203343 24, 0x0, End_B0=24 End_B1=24
7925 00:58:55.203427 25, 0x0, End_B0=25 End_B1=25
7926 00:58:55.206519 26, 0x0, End_B0=26 End_B1=26
7927 00:58:55.209770 27, 0x0, End_B0=27 End_B1=27
7928 00:58:55.212939 28, 0x0, End_B0=28 End_B1=28
7929 00:58:55.213022 29, 0x0, End_B0=29 End_B1=29
7930 00:58:55.216450 30, 0x0, End_B0=30 End_B1=30
7931 00:58:55.220139 31, 0x4141, End_B0=30 End_B1=30
7932 00:58:55.223356 Byte0 end_step=30 best_step=27
7933 00:58:55.226567 Byte1 end_step=30 best_step=27
7934 00:58:55.229752 Byte0 TX OE(2T, 0.5T) = (3, 3)
7935 00:58:55.229828 Byte1 TX OE(2T, 0.5T) = (3, 3)
7936 00:58:55.233054
7937 00:58:55.233154
7938 00:58:55.239963 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7939 00:58:55.243127 CH0 RK0: MR19=303, MR18=2622
7940 00:58:55.249500 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7941 00:58:55.249608
7942 00:58:55.253384 ----->DramcWriteLeveling(PI) begin...
7943 00:58:55.253487 ==
7944 00:58:55.256261 Dram Type= 6, Freq= 0, CH_0, rank 1
7945 00:58:55.259810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 00:58:55.259913 ==
7947 00:58:55.263030 Write leveling (Byte 0): 34 => 34
7948 00:58:55.266391 Write leveling (Byte 1): 27 => 27
7949 00:58:55.269426 DramcWriteLeveling(PI) end<-----
7950 00:58:55.269529
7951 00:58:55.269621 ==
7952 00:58:55.272980 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 00:58:55.275968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 00:58:55.276078 ==
7955 00:58:55.279231 [Gating] SW mode calibration
7956 00:58:55.285974 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7957 00:58:55.293030 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7958 00:58:55.296176 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7959 00:58:55.299170 1 4 4 | B1->B0 | 2323 2222 | 0 1 | (0 0) (0 0)
7960 00:58:55.306113 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 00:58:55.309431 1 4 12 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7962 00:58:55.312841 1 4 16 | B1->B0 | 3131 3837 | 0 1 | (0 0) (0 0)
7963 00:58:55.319129 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7964 00:58:55.322723 1 4 24 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7965 00:58:55.325718 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7966 00:58:55.332303 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7967 00:58:55.336142 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7968 00:58:55.339454 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7969 00:58:55.345829 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
7970 00:58:55.348989 1 5 16 | B1->B0 | 3131 2525 | 1 0 | (1 0) (1 0)
7971 00:58:55.352219 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7972 00:58:55.359333 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 00:58:55.362536 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7974 00:58:55.365771 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7975 00:58:55.372777 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7976 00:58:55.375976 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7977 00:58:55.379521 1 6 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7978 00:58:55.385930 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7979 00:58:55.389215 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 00:58:55.392601 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 00:58:55.395800 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 00:58:55.402398 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 00:58:55.406333 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 00:58:55.409598 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 00:58:55.415855 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7986 00:58:55.418993 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7987 00:58:55.422911 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 00:58:55.429365 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 00:58:55.432262 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 00:58:55.435834 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 00:58:55.442787 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 00:58:55.445752 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 00:58:55.448867 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 00:58:55.455985 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 00:58:55.459144 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 00:58:55.462315 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 00:58:55.468893 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 00:58:55.472729 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 00:58:55.476053 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 00:58:55.482737 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8001 00:58:55.485981 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8002 00:58:55.489265 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8003 00:58:55.492179 Total UI for P1: 0, mck2ui 16
8004 00:58:55.495905 best dqsien dly found for B1: ( 1, 9, 12)
8005 00:58:55.499284 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 00:58:55.502218 Total UI for P1: 0, mck2ui 16
8007 00:58:55.505944 best dqsien dly found for B0: ( 1, 9, 12)
8008 00:58:55.512248 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8009 00:58:55.515568 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8010 00:58:55.515648
8011 00:58:55.519115 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8012 00:58:55.522889 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8013 00:58:55.525673 [Gating] SW calibration Done
8014 00:58:55.525770 ==
8015 00:58:55.528775 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 00:58:55.532564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 00:58:55.532645 ==
8018 00:58:55.535749 RX Vref Scan: 0
8019 00:58:55.535829
8020 00:58:55.535892 RX Vref 0 -> 0, step: 1
8021 00:58:55.535950
8022 00:58:55.539028 RX Delay 0 -> 252, step: 8
8023 00:58:55.542156 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8024 00:58:55.545696 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8025 00:58:55.552136 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8026 00:58:55.555547 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8027 00:58:55.559487 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8028 00:58:55.562082 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8029 00:58:55.565838 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8030 00:58:55.572465 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8031 00:58:55.575703 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8032 00:58:55.579066 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8033 00:58:55.582386 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8034 00:58:55.585710 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8035 00:58:55.592355 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8036 00:58:55.595509 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8037 00:58:55.598660 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8038 00:58:55.601702 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8039 00:58:55.601782 ==
8040 00:58:55.605462 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 00:58:55.611783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 00:58:55.611889 ==
8043 00:58:55.611980 DQS Delay:
8044 00:58:55.615076 DQS0 = 0, DQS1 = 0
8045 00:58:55.615157 DQM Delay:
8046 00:58:55.618596 DQM0 = 137, DQM1 = 128
8047 00:58:55.618676 DQ Delay:
8048 00:58:55.621607 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8049 00:58:55.625107 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8050 00:58:55.628429 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8051 00:58:55.631792 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8052 00:58:55.631888
8053 00:58:55.631982
8054 00:58:55.632055 ==
8055 00:58:55.635093 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 00:58:55.641218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 00:58:55.641333 ==
8058 00:58:55.641426
8059 00:58:55.641513
8060 00:58:55.641593 TX Vref Scan disable
8061 00:58:55.645234 == TX Byte 0 ==
8062 00:58:55.648567 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8063 00:58:55.654900 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8064 00:58:55.655010 == TX Byte 1 ==
8065 00:58:55.658764 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8066 00:58:55.664719 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8067 00:58:55.664798 ==
8068 00:58:55.668318 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 00:58:55.671332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 00:58:55.671442 ==
8071 00:58:55.684924
8072 00:58:55.688164 TX Vref early break, caculate TX vref
8073 00:58:55.691478 TX Vref=16, minBit 1, minWin=23, winSum=385
8074 00:58:55.694576 TX Vref=18, minBit 0, minWin=24, winSum=400
8075 00:58:55.697863 TX Vref=20, minBit 1, minWin=24, winSum=406
8076 00:58:55.701744 TX Vref=22, minBit 1, minWin=25, winSum=415
8077 00:58:55.704859 TX Vref=24, minBit 1, minWin=25, winSum=422
8078 00:58:55.711614 TX Vref=26, minBit 7, minWin=25, winSum=429
8079 00:58:55.714936 TX Vref=28, minBit 2, minWin=25, winSum=425
8080 00:58:55.718210 TX Vref=30, minBit 0, minWin=25, winSum=419
8081 00:58:55.721443 TX Vref=32, minBit 0, minWin=25, winSum=411
8082 00:58:55.724876 TX Vref=34, minBit 1, minWin=23, winSum=401
8083 00:58:55.731349 [TxChooseVref] Worse bit 7, Min win 25, Win sum 429, Final Vref 26
8084 00:58:55.731438
8085 00:58:55.734416 Final TX Range 0 Vref 26
8086 00:58:55.734517
8087 00:58:55.734616 ==
8088 00:58:55.738043 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 00:58:55.741396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 00:58:55.741502 ==
8091 00:58:55.741595
8092 00:58:55.741687
8093 00:58:55.744740 TX Vref Scan disable
8094 00:58:55.751062 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8095 00:58:55.751165 == TX Byte 0 ==
8096 00:58:55.754248 u2DelayCellOfst[0]=13 cells (4 PI)
8097 00:58:55.757528 u2DelayCellOfst[1]=16 cells (5 PI)
8098 00:58:55.761168 u2DelayCellOfst[2]=10 cells (3 PI)
8099 00:58:55.764567 u2DelayCellOfst[3]=10 cells (3 PI)
8100 00:58:55.767407 u2DelayCellOfst[4]=6 cells (2 PI)
8101 00:58:55.771118 u2DelayCellOfst[5]=0 cells (0 PI)
8102 00:58:55.774098 u2DelayCellOfst[6]=13 cells (4 PI)
8103 00:58:55.777386 u2DelayCellOfst[7]=16 cells (5 PI)
8104 00:58:55.780691 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8105 00:58:55.784105 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8106 00:58:55.787473 == TX Byte 1 ==
8107 00:58:55.790519 u2DelayCellOfst[8]=3 cells (1 PI)
8108 00:58:55.790620 u2DelayCellOfst[9]=0 cells (0 PI)
8109 00:58:55.793828 u2DelayCellOfst[10]=6 cells (2 PI)
8110 00:58:55.797845 u2DelayCellOfst[11]=3 cells (1 PI)
8111 00:58:55.801075 u2DelayCellOfst[12]=10 cells (3 PI)
8112 00:58:55.804379 u2DelayCellOfst[13]=10 cells (3 PI)
8113 00:58:55.807562 u2DelayCellOfst[14]=16 cells (5 PI)
8114 00:58:55.810783 u2DelayCellOfst[15]=10 cells (3 PI)
8115 00:58:55.813878 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8116 00:58:55.820806 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8117 00:58:55.820886 DramC Write-DBI on
8118 00:58:55.820950 ==
8119 00:58:55.824065 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 00:58:55.830545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 00:58:55.830626 ==
8122 00:58:55.830690
8123 00:58:55.830748
8124 00:58:55.830804 TX Vref Scan disable
8125 00:58:55.834510 == TX Byte 0 ==
8126 00:58:55.837537 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8127 00:58:55.841081 == TX Byte 1 ==
8128 00:58:55.844161 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8129 00:58:55.847801 DramC Write-DBI off
8130 00:58:55.847881
8131 00:58:55.847944 [DATLAT]
8132 00:58:55.848004 Freq=1600, CH0 RK1
8133 00:58:55.848061
8134 00:58:55.851064 DATLAT Default: 0xf
8135 00:58:55.851143 0, 0xFFFF, sum = 0
8136 00:58:55.854257 1, 0xFFFF, sum = 0
8137 00:58:55.857415 2, 0xFFFF, sum = 0
8138 00:58:55.857497 3, 0xFFFF, sum = 0
8139 00:58:55.860544 4, 0xFFFF, sum = 0
8140 00:58:55.860626 5, 0xFFFF, sum = 0
8141 00:58:55.863831 6, 0xFFFF, sum = 0
8142 00:58:55.863912 7, 0xFFFF, sum = 0
8143 00:58:55.867665 8, 0xFFFF, sum = 0
8144 00:58:55.867746 9, 0xFFFF, sum = 0
8145 00:58:55.871007 10, 0xFFFF, sum = 0
8146 00:58:55.871088 11, 0xFFFF, sum = 0
8147 00:58:55.874408 12, 0xFFFF, sum = 0
8148 00:58:55.874504 13, 0xFFFF, sum = 0
8149 00:58:55.877575 14, 0x0, sum = 1
8150 00:58:55.877656 15, 0x0, sum = 2
8151 00:58:55.880616 16, 0x0, sum = 3
8152 00:58:55.880697 17, 0x0, sum = 4
8153 00:58:55.884072 best_step = 15
8154 00:58:55.884155
8155 00:58:55.884219 ==
8156 00:58:55.887567 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 00:58:55.890785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 00:58:55.890867 ==
8159 00:58:55.890930 RX Vref Scan: 0
8160 00:58:55.894058
8161 00:58:55.894138 RX Vref 0 -> 0, step: 1
8162 00:58:55.894201
8163 00:58:55.897624 RX Delay 19 -> 252, step: 4
8164 00:58:55.900702 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8165 00:58:55.907431 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8166 00:58:55.910886 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8167 00:58:55.914214 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8168 00:58:55.917419 iDelay=191, Bit 4, Center 136 (83 ~ 190) 108
8169 00:58:55.920545 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8170 00:58:55.927165 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8171 00:58:55.931113 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8172 00:58:55.934380 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8173 00:58:55.937670 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8174 00:58:55.940928 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8175 00:58:55.947264 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8176 00:58:55.951072 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8177 00:58:55.953942 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8178 00:58:55.957664 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8179 00:58:55.960706 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8180 00:58:55.963914 ==
8181 00:58:55.964015 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 00:58:55.970864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 00:58:55.970941 ==
8184 00:58:55.971004 DQS Delay:
8185 00:58:55.973936 DQS0 = 0, DQS1 = 0
8186 00:58:55.974041 DQM Delay:
8187 00:58:55.977204 DQM0 = 134, DQM1 = 127
8188 00:58:55.977291 DQ Delay:
8189 00:58:55.980477 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8190 00:58:55.983757 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8191 00:58:55.987000 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8192 00:58:55.990679 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8193 00:58:55.990752
8194 00:58:55.990815
8195 00:58:55.990871
8196 00:58:55.993653 [DramC_TX_OE_Calibration] TA2
8197 00:58:55.996891 Original DQ_B0 (3 6) =30, OEN = 27
8198 00:58:56.000154 Original DQ_B1 (3 6) =30, OEN = 27
8199 00:58:56.003938 24, 0x0, End_B0=24 End_B1=24
8200 00:58:56.007015 25, 0x0, End_B0=25 End_B1=25
8201 00:58:56.007088 26, 0x0, End_B0=26 End_B1=26
8202 00:58:56.010478 27, 0x0, End_B0=27 End_B1=27
8203 00:58:56.013505 28, 0x0, End_B0=28 End_B1=28
8204 00:58:56.016703 29, 0x0, End_B0=29 End_B1=29
8205 00:58:56.016805 30, 0x0, End_B0=30 End_B1=30
8206 00:58:56.020624 31, 0x4141, End_B0=30 End_B1=30
8207 00:58:56.023855 Byte0 end_step=30 best_step=27
8208 00:58:56.027079 Byte1 end_step=30 best_step=27
8209 00:58:56.030473 Byte0 TX OE(2T, 0.5T) = (3, 3)
8210 00:58:56.033750 Byte1 TX OE(2T, 0.5T) = (3, 3)
8211 00:58:56.033857
8212 00:58:56.033946
8213 00:58:56.040191 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8214 00:58:56.043677 CH0 RK1: MR19=303, MR18=220A
8215 00:58:56.050161 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8216 00:58:56.054024 [RxdqsGatingPostProcess] freq 1600
8217 00:58:56.057102 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8218 00:58:56.060127 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 00:58:56.063714 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 00:58:56.066810 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 00:58:56.070477 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 00:58:56.073698 best DQS0 dly(2T, 0.5T) = (1, 1)
8223 00:58:56.076541 best DQS1 dly(2T, 0.5T) = (1, 1)
8224 00:58:56.080428 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8225 00:58:56.083668 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8226 00:58:56.086821 Pre-setting of DQS Precalculation
8227 00:58:56.090159 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8228 00:58:56.090240 ==
8229 00:58:56.093396 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 00:58:56.099711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 00:58:56.099793 ==
8232 00:58:56.103483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8233 00:58:56.109984 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8234 00:58:56.113194 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8235 00:58:56.119765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8236 00:58:56.127360 [CA 0] Center 42 (12~72) winsize 61
8237 00:58:56.130966 [CA 1] Center 42 (12~72) winsize 61
8238 00:58:56.133900 [CA 2] Center 38 (9~68) winsize 60
8239 00:58:56.137420 [CA 3] Center 38 (9~67) winsize 59
8240 00:58:56.140519 [CA 4] Center 38 (9~68) winsize 60
8241 00:58:56.144094 [CA 5] Center 37 (8~67) winsize 60
8242 00:58:56.144190
8243 00:58:56.147069 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8244 00:58:56.147168
8245 00:58:56.150344 [CATrainingPosCal] consider 1 rank data
8246 00:58:56.154057 u2DelayCellTimex100 = 290/100 ps
8247 00:58:56.157569 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8248 00:58:56.163796 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8249 00:58:56.166983 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8250 00:58:56.170528 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8251 00:58:56.173753 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8252 00:58:56.176954 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8253 00:58:56.177034
8254 00:58:56.180825 CA PerBit enable=1, Macro0, CA PI delay=37
8255 00:58:56.180905
8256 00:58:56.183820 [CBTSetCACLKResult] CA Dly = 37
8257 00:58:56.187180 CS Dly: 11 (0~42)
8258 00:58:56.190677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8259 00:58:56.193764 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8260 00:58:56.193847 ==
8261 00:58:56.197025 Dram Type= 6, Freq= 0, CH_1, rank 1
8262 00:58:56.200221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 00:58:56.204237 ==
8264 00:58:56.207436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 00:58:56.210657 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 00:58:56.216945 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 00:58:56.220317 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 00:58:56.230385 [CA 0] Center 41 (12~71) winsize 60
8269 00:58:56.233681 [CA 1] Center 41 (12~71) winsize 60
8270 00:58:56.236985 [CA 2] Center 38 (9~68) winsize 60
8271 00:58:56.240579 [CA 3] Center 38 (8~68) winsize 61
8272 00:58:56.243558 [CA 4] Center 38 (9~68) winsize 60
8273 00:58:56.247351 [CA 5] Center 37 (7~67) winsize 61
8274 00:58:56.247437
8275 00:58:56.250696 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8276 00:58:56.250793
8277 00:58:56.253772 [CATrainingPosCal] consider 2 rank data
8278 00:58:56.257400 u2DelayCellTimex100 = 290/100 ps
8279 00:58:56.260406 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8280 00:58:56.267531 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8281 00:58:56.270378 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8282 00:58:56.273834 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8283 00:58:56.277350 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8284 00:58:56.280424 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8285 00:58:56.280532
8286 00:58:56.283685 CA PerBit enable=1, Macro0, CA PI delay=37
8287 00:58:56.283764
8288 00:58:56.287113 [CBTSetCACLKResult] CA Dly = 37
8289 00:58:56.290147 CS Dly: 12 (0~45)
8290 00:58:56.293757 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 00:58:56.296956 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 00:58:56.297036
8293 00:58:56.300564 ----->DramcWriteLeveling(PI) begin...
8294 00:58:56.300645 ==
8295 00:58:56.303608 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 00:58:56.307159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 00:58:56.310435 ==
8298 00:58:56.310515 Write leveling (Byte 0): 25 => 25
8299 00:58:56.313654 Write leveling (Byte 1): 27 => 27
8300 00:58:56.316896 DramcWriteLeveling(PI) end<-----
8301 00:58:56.316975
8302 00:58:56.317037 ==
8303 00:58:56.319972 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 00:58:56.326546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 00:58:56.326626 ==
8306 00:58:56.329920 [Gating] SW mode calibration
8307 00:58:56.336757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8308 00:58:56.339992 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8309 00:58:56.346956 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 00:58:56.349987 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 00:58:56.353492 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8312 00:58:56.359931 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8313 00:58:56.363104 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 00:58:56.366955 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 00:58:56.370023 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 00:58:56.376418 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 00:58:56.379913 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 00:58:56.383467 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 00:58:56.389995 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
8320 00:58:56.393437 1 5 12 | B1->B0 | 2626 2323 | 1 0 | (1 0) (1 0)
8321 00:58:56.396584 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8322 00:58:56.403180 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 00:58:56.406265 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 00:58:56.410248 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 00:58:56.416788 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 00:58:56.419918 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 00:58:56.423124 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8328 00:58:56.429596 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8329 00:58:56.432879 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 00:58:56.436178 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 00:58:56.442898 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 00:58:56.446054 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 00:58:56.449254 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 00:58:56.456391 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 00:58:56.459424 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8336 00:58:56.462891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8337 00:58:56.469577 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8338 00:58:56.472777 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 00:58:56.475842 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 00:58:56.482576 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 00:58:56.485780 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 00:58:56.489411 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 00:58:56.495851 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 00:58:56.499446 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:58:56.502777 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:58:56.509225 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:58:56.512655 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 00:58:56.516128 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:58:56.522509 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:58:56.525526 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 00:58:56.529408 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8352 00:58:56.535762 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 00:58:56.539080 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 00:58:56.542348 Total UI for P1: 0, mck2ui 16
8355 00:58:56.545518 best dqsien dly found for B0: ( 1, 9, 10)
8356 00:58:56.549204 Total UI for P1: 0, mck2ui 16
8357 00:58:56.552399 best dqsien dly found for B1: ( 1, 9, 10)
8358 00:58:56.555588 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8359 00:58:56.558898 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8360 00:58:56.558997
8361 00:58:56.562647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8362 00:58:56.565879 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8363 00:58:56.568978 [Gating] SW calibration Done
8364 00:58:56.569051 ==
8365 00:58:56.572559 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 00:58:56.575594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 00:58:56.575666 ==
8368 00:58:56.578982 RX Vref Scan: 0
8369 00:58:56.579081
8370 00:58:56.582111 RX Vref 0 -> 0, step: 1
8371 00:58:56.582212
8372 00:58:56.582300 RX Delay 0 -> 252, step: 8
8373 00:58:56.589201 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8374 00:58:56.592529 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8375 00:58:56.595402 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8376 00:58:56.598748 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8377 00:58:56.602631 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8378 00:58:56.608973 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8379 00:58:56.612099 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8380 00:58:56.615726 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8381 00:58:56.619252 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8382 00:58:56.622111 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8383 00:58:56.625842 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8384 00:58:56.632201 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8385 00:58:56.635465 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8386 00:58:56.638902 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8387 00:58:56.642182 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8388 00:58:56.649078 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8389 00:58:56.649179 ==
8390 00:58:56.652248 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 00:58:56.655303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 00:58:56.655398 ==
8393 00:58:56.655461 DQS Delay:
8394 00:58:56.659162 DQS0 = 0, DQS1 = 0
8395 00:58:56.659242 DQM Delay:
8396 00:58:56.662350 DQM0 = 136, DQM1 = 132
8397 00:58:56.662430 DQ Delay:
8398 00:58:56.665755 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8399 00:58:56.668989 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8400 00:58:56.672159 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8401 00:58:56.675233 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8402 00:58:56.675315
8403 00:58:56.675379
8404 00:58:56.678944 ==
8405 00:58:56.679026 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 00:58:56.685325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 00:58:56.685408 ==
8408 00:58:56.685472
8409 00:58:56.685531
8410 00:58:56.688912 TX Vref Scan disable
8411 00:58:56.688993 == TX Byte 0 ==
8412 00:58:56.691955 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8413 00:58:56.699022 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8414 00:58:56.699102 == TX Byte 1 ==
8415 00:58:56.702189 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8416 00:58:56.708831 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8417 00:58:56.708915 ==
8418 00:58:56.712028 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 00:58:56.715479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 00:58:56.715559 ==
8421 00:58:56.728143
8422 00:58:56.731277 TX Vref early break, caculate TX vref
8423 00:58:56.735056 TX Vref=16, minBit 0, minWin=23, winSum=379
8424 00:58:56.738112 TX Vref=18, minBit 1, minWin=23, winSum=388
8425 00:58:56.741412 TX Vref=20, minBit 0, minWin=24, winSum=401
8426 00:58:56.744561 TX Vref=22, minBit 1, minWin=25, winSum=412
8427 00:58:56.748143 TX Vref=24, minBit 0, minWin=25, winSum=419
8428 00:58:56.754877 TX Vref=26, minBit 0, minWin=26, winSum=428
8429 00:58:56.757865 TX Vref=28, minBit 1, minWin=25, winSum=429
8430 00:58:56.761122 TX Vref=30, minBit 6, minWin=24, winSum=419
8431 00:58:56.764555 TX Vref=32, minBit 2, minWin=24, winSum=411
8432 00:58:56.767870 TX Vref=34, minBit 0, minWin=24, winSum=404
8433 00:58:56.774751 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8434 00:58:56.774832
8435 00:58:56.778080 Final TX Range 0 Vref 26
8436 00:58:56.778161
8437 00:58:56.778223 ==
8438 00:58:56.781336 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 00:58:56.784498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 00:58:56.784581 ==
8441 00:58:56.784706
8442 00:58:56.784793
8443 00:58:56.787489 TX Vref Scan disable
8444 00:58:56.794557 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8445 00:58:56.794637 == TX Byte 0 ==
8446 00:58:56.797712 u2DelayCellOfst[0]=16 cells (5 PI)
8447 00:58:56.800861 u2DelayCellOfst[1]=10 cells (3 PI)
8448 00:58:56.804223 u2DelayCellOfst[2]=0 cells (0 PI)
8449 00:58:56.807902 u2DelayCellOfst[3]=6 cells (2 PI)
8450 00:58:56.811148 u2DelayCellOfst[4]=6 cells (2 PI)
8451 00:58:56.814324 u2DelayCellOfst[5]=16 cells (5 PI)
8452 00:58:56.817799 u2DelayCellOfst[6]=16 cells (5 PI)
8453 00:58:56.817879 u2DelayCellOfst[7]=3 cells (1 PI)
8454 00:58:56.824213 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8455 00:58:56.827605 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8456 00:58:56.827687 == TX Byte 1 ==
8457 00:58:56.830921 u2DelayCellOfst[8]=0 cells (0 PI)
8458 00:58:56.834066 u2DelayCellOfst[9]=3 cells (1 PI)
8459 00:58:56.837595 u2DelayCellOfst[10]=13 cells (4 PI)
8460 00:58:56.840963 u2DelayCellOfst[11]=3 cells (1 PI)
8461 00:58:56.843986 u2DelayCellOfst[12]=13 cells (4 PI)
8462 00:58:56.847598 u2DelayCellOfst[13]=16 cells (5 PI)
8463 00:58:56.850828 u2DelayCellOfst[14]=16 cells (5 PI)
8464 00:58:56.854025 u2DelayCellOfst[15]=16 cells (5 PI)
8465 00:58:56.857396 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8466 00:58:56.863765 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 00:58:56.863850 DramC Write-DBI on
8468 00:58:56.863914 ==
8469 00:58:56.867339 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 00:58:56.870570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 00:58:56.873578 ==
8472 00:58:56.873658
8473 00:58:56.873722
8474 00:58:56.873829 TX Vref Scan disable
8475 00:58:56.877074 == TX Byte 0 ==
8476 00:58:56.880477 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8477 00:58:56.883834 == TX Byte 1 ==
8478 00:58:56.887422 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8479 00:58:56.890456 DramC Write-DBI off
8480 00:58:56.890537
8481 00:58:56.890599 [DATLAT]
8482 00:58:56.890658 Freq=1600, CH1 RK0
8483 00:58:56.890714
8484 00:58:56.893603 DATLAT Default: 0xf
8485 00:58:56.893682 0, 0xFFFF, sum = 0
8486 00:58:56.897442 1, 0xFFFF, sum = 0
8487 00:58:56.897524 2, 0xFFFF, sum = 0
8488 00:58:56.900477 3, 0xFFFF, sum = 0
8489 00:58:56.903506 4, 0xFFFF, sum = 0
8490 00:58:56.903587 5, 0xFFFF, sum = 0
8491 00:58:56.907151 6, 0xFFFF, sum = 0
8492 00:58:56.907233 7, 0xFFFF, sum = 0
8493 00:58:56.910775 8, 0xFFFF, sum = 0
8494 00:58:56.910857 9, 0xFFFF, sum = 0
8495 00:58:56.913550 10, 0xFFFF, sum = 0
8496 00:58:56.913631 11, 0xFFFF, sum = 0
8497 00:58:56.917241 12, 0xFFFF, sum = 0
8498 00:58:56.917323 13, 0xFFFF, sum = 0
8499 00:58:56.920507 14, 0x0, sum = 1
8500 00:58:56.920589 15, 0x0, sum = 2
8501 00:58:56.923541 16, 0x0, sum = 3
8502 00:58:56.923621 17, 0x0, sum = 4
8503 00:58:56.926902 best_step = 15
8504 00:58:56.927008
8505 00:58:56.927104 ==
8506 00:58:56.930192 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 00:58:56.933400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 00:58:56.933481 ==
8509 00:58:56.936640 RX Vref Scan: 1
8510 00:58:56.936720
8511 00:58:56.936783 Set Vref Range= 24 -> 127
8512 00:58:56.936841
8513 00:58:56.940078 RX Vref 24 -> 127, step: 1
8514 00:58:56.940157
8515 00:58:56.943259 RX Delay 27 -> 252, step: 4
8516 00:58:56.943338
8517 00:58:56.947026 Set Vref, RX VrefLevel [Byte0]: 24
8518 00:58:56.949939 [Byte1]: 24
8519 00:58:56.950044
8520 00:58:56.953440 Set Vref, RX VrefLevel [Byte0]: 25
8521 00:58:56.956832 [Byte1]: 25
8522 00:58:56.956913
8523 00:58:56.960176 Set Vref, RX VrefLevel [Byte0]: 26
8524 00:58:56.963846 [Byte1]: 26
8525 00:58:56.967631
8526 00:58:56.967710 Set Vref, RX VrefLevel [Byte0]: 27
8527 00:58:56.970913 [Byte1]: 27
8528 00:58:56.974704
8529 00:58:56.974784 Set Vref, RX VrefLevel [Byte0]: 28
8530 00:58:56.977964 [Byte1]: 28
8531 00:58:56.982668
8532 00:58:56.982765 Set Vref, RX VrefLevel [Byte0]: 29
8533 00:58:56.985519 [Byte1]: 29
8534 00:58:56.989836
8535 00:58:56.989916 Set Vref, RX VrefLevel [Byte0]: 30
8536 00:58:56.993190 [Byte1]: 30
8537 00:58:56.997710
8538 00:58:56.997806 Set Vref, RX VrefLevel [Byte0]: 31
8539 00:58:57.000919 [Byte1]: 31
8540 00:58:57.004998
8541 00:58:57.005077 Set Vref, RX VrefLevel [Byte0]: 32
8542 00:58:57.008447 [Byte1]: 32
8543 00:58:57.012239
8544 00:58:57.012362 Set Vref, RX VrefLevel [Byte0]: 33
8545 00:58:57.015757 [Byte1]: 33
8546 00:58:57.020029
8547 00:58:57.020136 Set Vref, RX VrefLevel [Byte0]: 34
8548 00:58:57.023639 [Byte1]: 34
8549 00:58:57.027949
8550 00:58:57.028028 Set Vref, RX VrefLevel [Byte0]: 35
8551 00:58:57.031054 [Byte1]: 35
8552 00:58:57.035182
8553 00:58:57.035262 Set Vref, RX VrefLevel [Byte0]: 36
8554 00:58:57.038344 [Byte1]: 36
8555 00:58:57.042921
8556 00:58:57.043001 Set Vref, RX VrefLevel [Byte0]: 37
8557 00:58:57.046236 [Byte1]: 37
8558 00:58:57.050501
8559 00:58:57.050582 Set Vref, RX VrefLevel [Byte0]: 38
8560 00:58:57.053626 [Byte1]: 38
8561 00:58:57.057437
8562 00:58:57.057517 Set Vref, RX VrefLevel [Byte0]: 39
8563 00:58:57.061295 [Byte1]: 39
8564 00:58:57.065546
8565 00:58:57.065625 Set Vref, RX VrefLevel [Byte0]: 40
8566 00:58:57.068483 [Byte1]: 40
8567 00:58:57.072529
8568 00:58:57.072609 Set Vref, RX VrefLevel [Byte0]: 41
8569 00:58:57.075838 [Byte1]: 41
8570 00:58:57.080331
8571 00:58:57.080425 Set Vref, RX VrefLevel [Byte0]: 42
8572 00:58:57.083448 [Byte1]: 42
8573 00:58:57.087993
8574 00:58:57.088072 Set Vref, RX VrefLevel [Byte0]: 43
8575 00:58:57.091301 [Byte1]: 43
8576 00:58:57.095737
8577 00:58:57.095817 Set Vref, RX VrefLevel [Byte0]: 44
8578 00:58:57.098826 [Byte1]: 44
8579 00:58:57.102626
8580 00:58:57.102706 Set Vref, RX VrefLevel [Byte0]: 45
8581 00:58:57.106442 [Byte1]: 45
8582 00:58:57.110202
8583 00:58:57.110282 Set Vref, RX VrefLevel [Byte0]: 46
8584 00:58:57.113822 [Byte1]: 46
8585 00:58:57.118125
8586 00:58:57.118204 Set Vref, RX VrefLevel [Byte0]: 47
8587 00:58:57.121118 [Byte1]: 47
8588 00:58:57.125306
8589 00:58:57.125385 Set Vref, RX VrefLevel [Byte0]: 48
8590 00:58:57.128641 [Byte1]: 48
8591 00:58:57.133104
8592 00:58:57.133185 Set Vref, RX VrefLevel [Byte0]: 49
8593 00:58:57.136260 [Byte1]: 49
8594 00:58:57.140632
8595 00:58:57.140713 Set Vref, RX VrefLevel [Byte0]: 50
8596 00:58:57.143985 [Byte1]: 50
8597 00:58:57.147948
8598 00:58:57.148028 Set Vref, RX VrefLevel [Byte0]: 51
8599 00:58:57.151161 [Byte1]: 51
8600 00:58:57.155632
8601 00:58:57.155726 Set Vref, RX VrefLevel [Byte0]: 52
8602 00:58:57.158927 [Byte1]: 52
8603 00:58:57.163475
8604 00:58:57.163581 Set Vref, RX VrefLevel [Byte0]: 53
8605 00:58:57.166745 [Byte1]: 53
8606 00:58:57.170713
8607 00:58:57.170794 Set Vref, RX VrefLevel [Byte0]: 54
8608 00:58:57.173894 [Byte1]: 54
8609 00:58:57.178272
8610 00:58:57.178351 Set Vref, RX VrefLevel [Byte0]: 55
8611 00:58:57.181468 [Byte1]: 55
8612 00:58:57.185723
8613 00:58:57.185803 Set Vref, RX VrefLevel [Byte0]: 56
8614 00:58:57.189126 [Byte1]: 56
8615 00:58:57.193011
8616 00:58:57.193119 Set Vref, RX VrefLevel [Byte0]: 57
8617 00:58:57.196461 [Byte1]: 57
8618 00:58:57.200910
8619 00:58:57.200989 Set Vref, RX VrefLevel [Byte0]: 58
8620 00:58:57.204162 [Byte1]: 58
8621 00:58:57.208527
8622 00:58:57.208607 Set Vref, RX VrefLevel [Byte0]: 59
8623 00:58:57.211763 [Byte1]: 59
8624 00:58:57.215770
8625 00:58:57.219079 Set Vref, RX VrefLevel [Byte0]: 60
8626 00:58:57.219160 [Byte1]: 60
8627 00:58:57.223647
8628 00:58:57.223727 Set Vref, RX VrefLevel [Byte0]: 61
8629 00:58:57.226932 [Byte1]: 61
8630 00:58:57.231083
8631 00:58:57.231162 Set Vref, RX VrefLevel [Byte0]: 62
8632 00:58:57.234078 [Byte1]: 62
8633 00:58:57.238383
8634 00:58:57.238500 Set Vref, RX VrefLevel [Byte0]: 63
8635 00:58:57.241825 [Byte1]: 63
8636 00:58:57.246077
8637 00:58:57.246197 Set Vref, RX VrefLevel [Byte0]: 64
8638 00:58:57.249404 [Byte1]: 64
8639 00:58:57.253783
8640 00:58:57.253900 Set Vref, RX VrefLevel [Byte0]: 65
8641 00:58:57.256828 [Byte1]: 65
8642 00:58:57.260963
8643 00:58:57.261042 Set Vref, RX VrefLevel [Byte0]: 66
8644 00:58:57.264409 [Byte1]: 66
8645 00:58:57.268751
8646 00:58:57.268833 Set Vref, RX VrefLevel [Byte0]: 67
8647 00:58:57.271855 [Byte1]: 67
8648 00:58:57.276135
8649 00:58:57.276240 Set Vref, RX VrefLevel [Byte0]: 68
8650 00:58:57.279360 [Byte1]: 68
8651 00:58:57.283799
8652 00:58:57.283879 Set Vref, RX VrefLevel [Byte0]: 69
8653 00:58:57.286997 [Byte1]: 69
8654 00:58:57.290935
8655 00:58:57.291014 Set Vref, RX VrefLevel [Byte0]: 70
8656 00:58:57.294231 [Byte1]: 70
8657 00:58:57.298732
8658 00:58:57.298812 Set Vref, RX VrefLevel [Byte0]: 71
8659 00:58:57.302286 [Byte1]: 71
8660 00:58:57.306215
8661 00:58:57.306294 Set Vref, RX VrefLevel [Byte0]: 72
8662 00:58:57.309435 [Byte1]: 72
8663 00:58:57.313684
8664 00:58:57.313764 Set Vref, RX VrefLevel [Byte0]: 73
8665 00:58:57.317290 [Byte1]: 73
8666 00:58:57.321280
8667 00:58:57.321359 Set Vref, RX VrefLevel [Byte0]: 74
8668 00:58:57.324648 [Byte1]: 74
8669 00:58:57.329195
8670 00:58:57.329275 Set Vref, RX VrefLevel [Byte0]: 75
8671 00:58:57.332372 [Byte1]: 75
8672 00:58:57.336159
8673 00:58:57.336247 Set Vref, RX VrefLevel [Byte0]: 76
8674 00:58:57.339860 [Byte1]: 76
8675 00:58:57.343675
8676 00:58:57.343769 Set Vref, RX VrefLevel [Byte0]: 77
8677 00:58:57.347461 [Byte1]: 77
8678 00:58:57.351544
8679 00:58:57.351625 Final RX Vref Byte 0 = 60 to rank0
8680 00:58:57.354578 Final RX Vref Byte 1 = 59 to rank0
8681 00:58:57.358338 Final RX Vref Byte 0 = 60 to rank1
8682 00:58:57.361735 Final RX Vref Byte 1 = 59 to rank1==
8683 00:58:57.364772 Dram Type= 6, Freq= 0, CH_1, rank 0
8684 00:58:57.371486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8685 00:58:57.371567 ==
8686 00:58:57.371631 DQS Delay:
8687 00:58:57.371690 DQS0 = 0, DQS1 = 0
8688 00:58:57.374970 DQM Delay:
8689 00:58:57.375049 DQM0 = 134, DQM1 = 131
8690 00:58:57.378195 DQ Delay:
8691 00:58:57.381555 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8692 00:58:57.384666 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8693 00:58:57.388012 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124
8694 00:58:57.391192 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8695 00:58:57.391273
8696 00:58:57.391335
8697 00:58:57.391394
8698 00:58:57.394679 [DramC_TX_OE_Calibration] TA2
8699 00:58:57.397999 Original DQ_B0 (3 6) =30, OEN = 27
8700 00:58:57.401249 Original DQ_B1 (3 6) =30, OEN = 27
8701 00:58:57.404575 24, 0x0, End_B0=24 End_B1=24
8702 00:58:57.404657 25, 0x0, End_B0=25 End_B1=25
8703 00:58:57.407700 26, 0x0, End_B0=26 End_B1=26
8704 00:58:57.410963 27, 0x0, End_B0=27 End_B1=27
8705 00:58:57.414687 28, 0x0, End_B0=28 End_B1=28
8706 00:58:57.417518 29, 0x0, End_B0=29 End_B1=29
8707 00:58:57.417599 30, 0x0, End_B0=30 End_B1=30
8708 00:58:57.421127 31, 0x4545, End_B0=30 End_B1=30
8709 00:58:57.424563 Byte0 end_step=30 best_step=27
8710 00:58:57.427971 Byte1 end_step=30 best_step=27
8711 00:58:57.431015 Byte0 TX OE(2T, 0.5T) = (3, 3)
8712 00:58:57.434341 Byte1 TX OE(2T, 0.5T) = (3, 3)
8713 00:58:57.434421
8714 00:58:57.434484
8715 00:58:57.440875 [DQSOSCAuto] RK0, (LSB)MR18= 0x1522, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8716 00:58:57.444570 CH1 RK0: MR19=303, MR18=1522
8717 00:58:57.451262 CH1_RK0: MR19=0x303, MR18=0x1522, DQSOSC=392, MR23=63, INC=24, DEC=16
8718 00:58:57.451344
8719 00:58:57.454581 ----->DramcWriteLeveling(PI) begin...
8720 00:58:57.454662 ==
8721 00:58:57.457700 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 00:58:57.461296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 00:58:57.461377 ==
8724 00:58:57.464543 Write leveling (Byte 0): 24 => 24
8725 00:58:57.467842 Write leveling (Byte 1): 28 => 28
8726 00:58:57.471213 DramcWriteLeveling(PI) end<-----
8727 00:58:57.471293
8728 00:58:57.471356 ==
8729 00:58:57.474524 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 00:58:57.477732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 00:58:57.477813 ==
8732 00:58:57.480943 [Gating] SW mode calibration
8733 00:58:57.487518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8734 00:58:57.494575 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8735 00:58:57.497708 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 00:58:57.501268 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 00:58:57.507874 1 4 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8738 00:58:57.511094 1 4 12 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (0 0)
8739 00:58:57.514339 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 00:58:57.521305 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 00:58:57.524593 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 00:58:57.527712 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 00:58:57.534598 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 00:58:57.537975 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8745 00:58:57.540692 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8746 00:58:57.548007 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8747 00:58:57.551237 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 00:58:57.554252 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 00:58:57.560813 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 00:58:57.564861 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 00:58:57.567799 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 00:58:57.574231 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8753 00:58:57.577411 1 6 8 | B1->B0 | 4040 2626 | 0 0 | (0 0) (0 0)
8754 00:58:57.580754 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8755 00:58:57.587326 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 00:58:57.591059 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 00:58:57.594622 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 00:58:57.597693 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 00:58:57.604040 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 00:58:57.607367 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8761 00:58:57.611159 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8762 00:58:57.617413 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8763 00:58:57.620711 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 00:58:57.624215 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 00:58:57.630568 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 00:58:57.633892 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 00:58:57.637140 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 00:58:57.644034 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 00:58:57.647427 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 00:58:57.650577 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 00:58:57.657211 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 00:58:57.660333 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 00:58:57.664055 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:58:57.670731 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:58:57.673871 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:58:57.677024 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8777 00:58:57.684131 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8778 00:58:57.686811 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8779 00:58:57.690732 Total UI for P1: 0, mck2ui 16
8780 00:58:57.693989 best dqsien dly found for B1: ( 1, 9, 6)
8781 00:58:57.696909 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 00:58:57.700635 Total UI for P1: 0, mck2ui 16
8783 00:58:57.703507 best dqsien dly found for B0: ( 1, 9, 10)
8784 00:58:57.707188 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8785 00:58:57.710315 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8786 00:58:57.710413
8787 00:58:57.713611 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8788 00:58:57.720233 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8789 00:58:57.720339 [Gating] SW calibration Done
8790 00:58:57.720405 ==
8791 00:58:57.723576 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 00:58:57.730358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 00:58:57.730449 ==
8794 00:58:57.730515 RX Vref Scan: 0
8795 00:58:57.730576
8796 00:58:57.733459 RX Vref 0 -> 0, step: 1
8797 00:58:57.733530
8798 00:58:57.736698 RX Delay 0 -> 252, step: 8
8799 00:58:57.740468 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8800 00:58:57.743277 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8801 00:58:57.746735 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8802 00:58:57.753253 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8803 00:58:57.756627 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8804 00:58:57.760283 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8805 00:58:57.763167 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8806 00:58:57.766723 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8807 00:58:57.773204 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8808 00:58:57.776749 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8809 00:58:57.780343 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8810 00:58:57.783522 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8811 00:58:57.786571 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8812 00:58:57.793747 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8813 00:58:57.796962 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8814 00:58:57.800273 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8815 00:58:57.800398 ==
8816 00:58:57.803637 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 00:58:57.806686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 00:58:57.806768 ==
8819 00:58:57.809890 DQS Delay:
8820 00:58:57.809970 DQS0 = 0, DQS1 = 0
8821 00:58:57.813525 DQM Delay:
8822 00:58:57.813605 DQM0 = 136, DQM1 = 134
8823 00:58:57.813668 DQ Delay:
8824 00:58:57.816795 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8825 00:58:57.823498 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8826 00:58:57.826675 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8827 00:58:57.829786 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8828 00:58:57.829866
8829 00:58:57.829929
8830 00:58:57.829987 ==
8831 00:58:57.833569 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 00:58:57.836952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 00:58:57.837032 ==
8834 00:58:57.837095
8835 00:58:57.837152
8836 00:58:57.840189 TX Vref Scan disable
8837 00:58:57.843580 == TX Byte 0 ==
8838 00:58:57.846740 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8839 00:58:57.849896 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8840 00:58:57.853369 == TX Byte 1 ==
8841 00:58:57.856496 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8842 00:58:57.859936 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8843 00:58:57.860016 ==
8844 00:58:57.863402 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 00:58:57.866364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 00:58:57.870067 ==
8847 00:58:57.880878
8848 00:58:57.884228 TX Vref early break, caculate TX vref
8849 00:58:57.887581 TX Vref=16, minBit 0, minWin=23, winSum=385
8850 00:58:57.891083 TX Vref=18, minBit 0, minWin=23, winSum=395
8851 00:58:57.894538 TX Vref=20, minBit 0, minWin=24, winSum=403
8852 00:58:57.897556 TX Vref=22, minBit 0, minWin=24, winSum=408
8853 00:58:57.900833 TX Vref=24, minBit 10, minWin=25, winSum=421
8854 00:58:57.907283 TX Vref=26, minBit 0, minWin=26, winSum=423
8855 00:58:57.911171 TX Vref=28, minBit 0, minWin=26, winSum=429
8856 00:58:57.914252 TX Vref=30, minBit 1, minWin=25, winSum=420
8857 00:58:57.917333 TX Vref=32, minBit 0, minWin=25, winSum=414
8858 00:58:57.920435 TX Vref=34, minBit 0, minWin=24, winSum=402
8859 00:58:57.927552 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8860 00:58:57.927634
8861 00:58:57.930782 Final TX Range 0 Vref 28
8862 00:58:57.930863
8863 00:58:57.930925 ==
8864 00:58:57.933968 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 00:58:57.937043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 00:58:57.937140 ==
8867 00:58:57.937234
8868 00:58:57.937307
8869 00:58:57.940341 TX Vref Scan disable
8870 00:58:57.947554 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8871 00:58:57.947635 == TX Byte 0 ==
8872 00:58:57.950329 u2DelayCellOfst[0]=16 cells (5 PI)
8873 00:58:57.954033 u2DelayCellOfst[1]=10 cells (3 PI)
8874 00:58:57.957089 u2DelayCellOfst[2]=0 cells (0 PI)
8875 00:58:57.960545 u2DelayCellOfst[3]=6 cells (2 PI)
8876 00:58:57.963561 u2DelayCellOfst[4]=10 cells (3 PI)
8877 00:58:57.967360 u2DelayCellOfst[5]=16 cells (5 PI)
8878 00:58:57.970757 u2DelayCellOfst[6]=16 cells (5 PI)
8879 00:58:57.973945 u2DelayCellOfst[7]=6 cells (2 PI)
8880 00:58:57.976892 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8881 00:58:57.980662 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8882 00:58:57.983835 == TX Byte 1 ==
8883 00:58:57.983914 u2DelayCellOfst[8]=0 cells (0 PI)
8884 00:58:57.987013 u2DelayCellOfst[9]=3 cells (1 PI)
8885 00:58:57.990476 u2DelayCellOfst[10]=10 cells (3 PI)
8886 00:58:57.993334 u2DelayCellOfst[11]=6 cells (2 PI)
8887 00:58:57.997014 u2DelayCellOfst[12]=13 cells (4 PI)
8888 00:58:57.999974 u2DelayCellOfst[13]=13 cells (4 PI)
8889 00:58:58.003470 u2DelayCellOfst[14]=13 cells (4 PI)
8890 00:58:58.006796 u2DelayCellOfst[15]=16 cells (5 PI)
8891 00:58:58.010335 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8892 00:58:58.016632 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 00:58:58.016714 DramC Write-DBI on
8894 00:58:58.016778 ==
8895 00:58:58.020941 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 00:58:58.023849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 00:58:58.027074 ==
8898 00:58:58.027154
8899 00:58:58.027217
8900 00:58:58.027275 TX Vref Scan disable
8901 00:58:58.030373 == TX Byte 0 ==
8902 00:58:58.033700 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8903 00:58:58.036834 == TX Byte 1 ==
8904 00:58:58.040647 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8905 00:58:58.043900 DramC Write-DBI off
8906 00:58:58.043980
8907 00:58:58.044043 [DATLAT]
8908 00:58:58.044102 Freq=1600, CH1 RK1
8909 00:58:58.044158
8910 00:58:58.047088 DATLAT Default: 0xf
8911 00:58:58.047168 0, 0xFFFF, sum = 0
8912 00:58:58.050342 1, 0xFFFF, sum = 0
8913 00:58:58.053705 2, 0xFFFF, sum = 0
8914 00:58:58.053787 3, 0xFFFF, sum = 0
8915 00:58:58.056903 4, 0xFFFF, sum = 0
8916 00:58:58.056985 5, 0xFFFF, sum = 0
8917 00:58:58.060702 6, 0xFFFF, sum = 0
8918 00:58:58.060784 7, 0xFFFF, sum = 0
8919 00:58:58.063976 8, 0xFFFF, sum = 0
8920 00:58:58.064070 9, 0xFFFF, sum = 0
8921 00:58:58.067198 10, 0xFFFF, sum = 0
8922 00:58:58.067279 11, 0xFFFF, sum = 0
8923 00:58:58.070453 12, 0xFFFF, sum = 0
8924 00:58:58.070534 13, 0xFFFF, sum = 0
8925 00:58:58.073601 14, 0x0, sum = 1
8926 00:58:58.073682 15, 0x0, sum = 2
8927 00:58:58.076775 16, 0x0, sum = 3
8928 00:58:58.076856 17, 0x0, sum = 4
8929 00:58:58.080506 best_step = 15
8930 00:58:58.080586
8931 00:58:58.080648 ==
8932 00:58:58.083648 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 00:58:58.086868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 00:58:58.086949 ==
8935 00:58:58.087012 RX Vref Scan: 0
8936 00:58:58.090159
8937 00:58:58.090289 RX Vref 0 -> 0, step: 1
8938 00:58:58.090354
8939 00:58:58.093611 RX Delay 19 -> 252, step: 4
8940 00:58:58.097107 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8941 00:58:58.103308 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8942 00:58:58.106836 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8943 00:58:58.110284 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8944 00:58:58.113619 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8945 00:58:58.116504 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8946 00:58:58.119943 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8947 00:58:58.126730 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8948 00:58:58.129863 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8949 00:58:58.133663 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8950 00:58:58.136819 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8951 00:58:58.143101 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8952 00:58:58.146339 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8953 00:58:58.150275 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8954 00:58:58.153444 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8955 00:58:58.156777 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8956 00:58:58.156857 ==
8957 00:58:58.159994 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 00:58:58.166377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 00:58:58.166461 ==
8960 00:58:58.166525 DQS Delay:
8961 00:58:58.169723 DQS0 = 0, DQS1 = 0
8962 00:58:58.169804 DQM Delay:
8963 00:58:58.172796 DQM0 = 134, DQM1 = 130
8964 00:58:58.172875 DQ Delay:
8965 00:58:58.176758 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8966 00:58:58.180003 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8967 00:58:58.183255 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8968 00:58:58.186345 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8969 00:58:58.186425
8970 00:58:58.186488
8971 00:58:58.186547
8972 00:58:58.189970 [DramC_TX_OE_Calibration] TA2
8973 00:58:58.193161 Original DQ_B0 (3 6) =30, OEN = 27
8974 00:58:58.196507 Original DQ_B1 (3 6) =30, OEN = 27
8975 00:58:58.199760 24, 0x0, End_B0=24 End_B1=24
8976 00:58:58.202997 25, 0x0, End_B0=25 End_B1=25
8977 00:58:58.203081 26, 0x0, End_B0=26 End_B1=26
8978 00:58:58.206324 27, 0x0, End_B0=27 End_B1=27
8979 00:58:58.209315 28, 0x0, End_B0=28 End_B1=28
8980 00:58:58.212985 29, 0x0, End_B0=29 End_B1=29
8981 00:58:58.213068 30, 0x0, End_B0=30 End_B1=30
8982 00:58:58.216002 31, 0x4141, End_B0=30 End_B1=30
8983 00:58:58.219418 Byte0 end_step=30 best_step=27
8984 00:58:58.222791 Byte1 end_step=30 best_step=27
8985 00:58:58.225759 Byte0 TX OE(2T, 0.5T) = (3, 3)
8986 00:58:58.229329 Byte1 TX OE(2T, 0.5T) = (3, 3)
8987 00:58:58.229411
8988 00:58:58.229475
8989 00:58:58.236150 [DQSOSCAuto] RK1, (LSB)MR18= 0x230a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8990 00:58:58.239049 CH1 RK1: MR19=303, MR18=230A
8991 00:58:58.245506 CH1_RK1: MR19=0x303, MR18=0x230A, DQSOSC=392, MR23=63, INC=24, DEC=16
8992 00:58:58.249033 [RxdqsGatingPostProcess] freq 1600
8993 00:58:58.255394 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8994 00:58:58.255477 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 00:58:58.258704 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 00:58:58.262639 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 00:58:58.265851 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 00:58:58.268969 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 00:58:58.272183 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 00:58:58.275703 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 00:58:58.278830 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 00:58:58.282676 Pre-setting of DQS Precalculation
9003 00:58:58.285731 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9004 00:58:58.295567 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9005 00:58:58.301976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9006 00:58:58.302058
9007 00:58:58.302123
9008 00:58:58.305398 [Calibration Summary] 3200 Mbps
9009 00:58:58.305481 CH 0, Rank 0
9010 00:58:58.309232 SW Impedance : PASS
9011 00:58:58.309315 DUTY Scan : NO K
9012 00:58:58.312435 ZQ Calibration : PASS
9013 00:58:58.315287 Jitter Meter : NO K
9014 00:58:58.315370 CBT Training : PASS
9015 00:58:58.319157 Write leveling : PASS
9016 00:58:58.322264 RX DQS gating : PASS
9017 00:58:58.322347 RX DQ/DQS(RDDQC) : PASS
9018 00:58:58.325379 TX DQ/DQS : PASS
9019 00:58:58.328682 RX DATLAT : PASS
9020 00:58:58.328764 RX DQ/DQS(Engine): PASS
9021 00:58:58.332319 TX OE : PASS
9022 00:58:58.332402 All Pass.
9023 00:58:58.332466
9024 00:58:58.335293 CH 0, Rank 1
9025 00:58:58.335375 SW Impedance : PASS
9026 00:58:58.338936 DUTY Scan : NO K
9027 00:58:58.339018 ZQ Calibration : PASS
9028 00:58:58.341902 Jitter Meter : NO K
9029 00:58:58.345474 CBT Training : PASS
9030 00:58:58.345583 Write leveling : PASS
9031 00:58:58.348867 RX DQS gating : PASS
9032 00:58:58.351881 RX DQ/DQS(RDDQC) : PASS
9033 00:58:58.351989 TX DQ/DQS : PASS
9034 00:58:58.355480 RX DATLAT : PASS
9035 00:58:58.358373 RX DQ/DQS(Engine): PASS
9036 00:58:58.358454 TX OE : PASS
9037 00:58:58.361876 All Pass.
9038 00:58:58.361957
9039 00:58:58.362021 CH 1, Rank 0
9040 00:58:58.365126 SW Impedance : PASS
9041 00:58:58.365215 DUTY Scan : NO K
9042 00:58:58.368626 ZQ Calibration : PASS
9043 00:58:58.371699 Jitter Meter : NO K
9044 00:58:58.371781 CBT Training : PASS
9045 00:58:58.375582 Write leveling : PASS
9046 00:58:58.378888 RX DQS gating : PASS
9047 00:58:58.378970 RX DQ/DQS(RDDQC) : PASS
9048 00:58:58.382096 TX DQ/DQS : PASS
9049 00:58:58.385379 RX DATLAT : PASS
9050 00:58:58.385461 RX DQ/DQS(Engine): PASS
9051 00:58:58.388513 TX OE : PASS
9052 00:58:58.388595 All Pass.
9053 00:58:58.388659
9054 00:58:58.391670 CH 1, Rank 1
9055 00:58:58.391751 SW Impedance : PASS
9056 00:58:58.394936 DUTY Scan : NO K
9057 00:58:58.395031 ZQ Calibration : PASS
9058 00:58:58.398804 Jitter Meter : NO K
9059 00:58:58.401967 CBT Training : PASS
9060 00:58:58.402047 Write leveling : PASS
9061 00:58:58.405283 RX DQS gating : PASS
9062 00:58:58.408585 RX DQ/DQS(RDDQC) : PASS
9063 00:58:58.408665 TX DQ/DQS : PASS
9064 00:58:58.411769 RX DATLAT : PASS
9065 00:58:58.414857 RX DQ/DQS(Engine): PASS
9066 00:58:58.414938 TX OE : PASS
9067 00:58:58.418744 All Pass.
9068 00:58:58.418824
9069 00:58:58.418887 DramC Write-DBI on
9070 00:58:58.421510 PER_BANK_REFRESH: Hybrid Mode
9071 00:58:58.421590 TX_TRACKING: ON
9072 00:58:58.431721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9073 00:58:58.441389 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9074 00:58:58.448528 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9075 00:58:58.451645 [FAST_K] Save calibration result to emmc
9076 00:58:58.454765 sync common calibartion params.
9077 00:58:58.454846 sync cbt_mode0:1, 1:1
9078 00:58:58.458558 dram_init: ddr_geometry: 2
9079 00:58:58.461677 dram_init: ddr_geometry: 2
9080 00:58:58.461771 dram_init: ddr_geometry: 2
9081 00:58:58.464778 0:dram_rank_size:100000000
9082 00:58:58.467939 1:dram_rank_size:100000000
9083 00:58:58.474776 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9084 00:58:58.474857 DFS_SHUFFLE_HW_MODE: ON
9085 00:58:58.478065 dramc_set_vcore_voltage set vcore to 725000
9086 00:58:58.481479 Read voltage for 1600, 0
9087 00:58:58.481574 Vio18 = 0
9088 00:58:58.484947 Vcore = 725000
9089 00:58:58.485027 Vdram = 0
9090 00:58:58.485091 Vddq = 0
9091 00:58:58.488063 Vmddr = 0
9092 00:58:58.488144 switch to 3200 Mbps bootup
9093 00:58:58.491307 [DramcRunTimeConfig]
9094 00:58:58.491386 PHYPLL
9095 00:58:58.494511 DPM_CONTROL_AFTERK: ON
9096 00:58:58.494591 PER_BANK_REFRESH: ON
9097 00:58:58.498378 REFRESH_OVERHEAD_REDUCTION: ON
9098 00:58:58.501598 CMD_PICG_NEW_MODE: OFF
9099 00:58:58.501678 XRTWTW_NEW_MODE: ON
9100 00:58:58.504704 XRTRTR_NEW_MODE: ON
9101 00:58:58.504784 TX_TRACKING: ON
9102 00:58:58.507983 RDSEL_TRACKING: OFF
9103 00:58:58.511449 DQS Precalculation for DVFS: ON
9104 00:58:58.511529 RX_TRACKING: OFF
9105 00:58:58.514612 HW_GATING DBG: ON
9106 00:58:58.514681 ZQCS_ENABLE_LP4: ON
9107 00:58:58.517951 RX_PICG_NEW_MODE: ON
9108 00:58:58.518030 TX_PICG_NEW_MODE: ON
9109 00:58:58.521185 ENABLE_RX_DCM_DPHY: ON
9110 00:58:58.524392 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9111 00:58:58.527649 DUMMY_READ_FOR_TRACKING: OFF
9112 00:58:58.527730 !!! SPM_CONTROL_AFTERK: OFF
9113 00:58:58.531087 !!! SPM could not control APHY
9114 00:58:58.534874 IMPEDANCE_TRACKING: ON
9115 00:58:58.534954 TEMP_SENSOR: ON
9116 00:58:58.537928 HW_SAVE_FOR_SR: OFF
9117 00:58:58.541156 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9118 00:58:58.544412 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9119 00:58:58.544492 Read ODT Tracking: ON
9120 00:58:58.547537 Refresh Rate DeBounce: ON
9121 00:58:58.551204 DFS_NO_QUEUE_FLUSH: ON
9122 00:58:58.554215 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9123 00:58:58.557872 ENABLE_DFS_RUNTIME_MRW: OFF
9124 00:58:58.557952 DDR_RESERVE_NEW_MODE: ON
9125 00:58:58.560907 MR_CBT_SWITCH_FREQ: ON
9126 00:58:58.564192 =========================
9127 00:58:58.581419 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9128 00:58:58.584520 dram_init: ddr_geometry: 2
9129 00:58:58.603471 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9130 00:58:58.606721 dram_init: dram init end (result: 0)
9131 00:58:58.613472 DRAM-K: Full calibration passed in 24434 msecs
9132 00:58:58.616296 MRC: failed to locate region type 0.
9133 00:58:58.616392 DRAM rank0 size:0x100000000,
9134 00:58:58.619655 DRAM rank1 size=0x100000000
9135 00:58:58.630072 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9136 00:58:58.636555 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9137 00:58:58.643274 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9138 00:58:58.649438 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9139 00:58:58.653307 DRAM rank0 size:0x100000000,
9140 00:58:58.656731 DRAM rank1 size=0x100000000
9141 00:58:58.656812 CBMEM:
9142 00:58:58.659964 IMD: root @ 0xfffff000 254 entries.
9143 00:58:58.662953 IMD: root @ 0xffffec00 62 entries.
9144 00:58:58.666696 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9145 00:58:58.670275 WARNING: RO_VPD is uninitialized or empty.
9146 00:58:58.676440 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9147 00:58:58.683261 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9148 00:58:58.696263 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9149 00:58:58.707422 BS: romstage times (exec / console): total (unknown) / 23969 ms
9150 00:58:58.707505
9151 00:58:58.707570
9152 00:58:58.717481 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9153 00:58:58.720470 ARM64: Exception handlers installed.
9154 00:58:58.724075 ARM64: Testing exception
9155 00:58:58.727151 ARM64: Done test exception
9156 00:58:58.727233 Enumerating buses...
9157 00:58:58.730411 Show all devs... Before device enumeration.
9158 00:58:58.734259 Root Device: enabled 1
9159 00:58:58.737677 CPU_CLUSTER: 0: enabled 1
9160 00:58:58.737757 CPU: 00: enabled 1
9161 00:58:58.740917 Compare with tree...
9162 00:58:58.741025 Root Device: enabled 1
9163 00:58:58.744439 CPU_CLUSTER: 0: enabled 1
9164 00:58:58.747395 CPU: 00: enabled 1
9165 00:58:58.747474 Root Device scanning...
9166 00:58:58.750905 scan_static_bus for Root Device
9167 00:58:58.754014 CPU_CLUSTER: 0 enabled
9168 00:58:58.757589 scan_static_bus for Root Device done
9169 00:58:58.760763 scan_bus: bus Root Device finished in 8 msecs
9170 00:58:58.760856 done
9171 00:58:58.767173 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9172 00:58:58.770839 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9173 00:58:58.777462 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9174 00:58:58.780431 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9175 00:58:58.784203 Allocating resources...
9176 00:58:58.784309 Reading resources...
9177 00:58:58.790547 Root Device read_resources bus 0 link: 0
9178 00:58:58.790628 DRAM rank0 size:0x100000000,
9179 00:58:58.793867 DRAM rank1 size=0x100000000
9180 00:58:58.797564 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9181 00:58:58.800220 CPU: 00 missing read_resources
9182 00:58:58.804051 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9183 00:58:58.810308 Root Device read_resources bus 0 link: 0 done
9184 00:58:58.810388 Done reading resources.
9185 00:58:58.817282 Show resources in subtree (Root Device)...After reading.
9186 00:58:58.820414 Root Device child on link 0 CPU_CLUSTER: 0
9187 00:58:58.823561 CPU_CLUSTER: 0 child on link 0 CPU: 00
9188 00:58:58.833973 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9189 00:58:58.834059 CPU: 00
9190 00:58:58.836913 Root Device assign_resources, bus 0 link: 0
9191 00:58:58.840595 CPU_CLUSTER: 0 missing set_resources
9192 00:58:58.843878 Root Device assign_resources, bus 0 link: 0 done
9193 00:58:58.847146 Done setting resources.
9194 00:58:58.853718 Show resources in subtree (Root Device)...After assigning values.
9195 00:58:58.856924 Root Device child on link 0 CPU_CLUSTER: 0
9196 00:58:58.860344 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 00:58:58.870505 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 00:58:58.870588 CPU: 00
9199 00:58:58.873735 Done allocating resources.
9200 00:58:58.876741 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9201 00:58:58.880436 Enabling resources...
9202 00:58:58.880516 done.
9203 00:58:58.887297 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9204 00:58:58.887377 Initializing devices...
9205 00:58:58.890147 Root Device init
9206 00:58:58.890227 init hardware done!
9207 00:58:58.893752 0x00000018: ctrlr->caps
9208 00:58:58.896960 52.000 MHz: ctrlr->f_max
9209 00:58:58.897046 0.400 MHz: ctrlr->f_min
9210 00:58:58.900064 0x40ff8080: ctrlr->voltages
9211 00:58:58.900146 sclk: 390625
9212 00:58:58.903445 Bus Width = 1
9213 00:58:58.903524 sclk: 390625
9214 00:58:58.903587 Bus Width = 1
9215 00:58:58.907227 Early init status = 3
9216 00:58:58.913733 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9217 00:58:58.916938 in-header: 03 fc 00 00 01 00 00 00
9218 00:58:58.920112 in-data: 00
9219 00:58:58.923325 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9220 00:58:58.928018 in-header: 03 fd 00 00 00 00 00 00
9221 00:58:58.931171 in-data:
9222 00:58:58.934407 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9223 00:58:58.939117 in-header: 03 fc 00 00 01 00 00 00
9224 00:58:58.942262 in-data: 00
9225 00:58:58.946012 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9226 00:58:58.951344 in-header: 03 fd 00 00 00 00 00 00
9227 00:58:58.954748 in-data:
9228 00:58:58.958082 [SSUSB] Setting up USB HOST controller...
9229 00:58:58.961248 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9230 00:58:58.964484 [SSUSB] phy power-on done.
9231 00:58:58.967712 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9232 00:58:58.974094 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9233 00:58:58.977788 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9234 00:58:58.984280 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9235 00:58:58.991202 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9236 00:58:58.997959 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9237 00:58:59.004113 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9238 00:58:59.010806 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9239 00:58:59.014730 SPM: binary array size = 0x9dc
9240 00:58:59.017169 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9241 00:58:59.024154 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9242 00:58:59.030607 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9243 00:58:59.037043 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9244 00:58:59.040330 configure_display: Starting display init
9245 00:58:59.074383 anx7625_power_on_init: Init interface.
9246 00:58:59.078157 anx7625_disable_pd_protocol: Disabled PD feature.
9247 00:58:59.081341 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9248 00:58:59.108711 anx7625_start_dp_work: Secure OCM version=00
9249 00:58:59.112221 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9250 00:58:59.126928 sp_tx_get_edid_block: EDID Block = 1
9251 00:58:59.229524 Extracted contents:
9252 00:58:59.232712 header: 00 ff ff ff ff ff ff 00
9253 00:58:59.235950 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9254 00:58:59.239299 version: 01 04
9255 00:58:59.242601 basic params: 95 1f 11 78 0a
9256 00:58:59.245796 chroma info: 76 90 94 55 54 90 27 21 50 54
9257 00:58:59.249522 established: 00 00 00
9258 00:58:59.255984 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9259 00:58:59.259370 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9260 00:58:59.266130 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9261 00:58:59.272692 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9262 00:58:59.279152 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9263 00:58:59.282505 extensions: 00
9264 00:58:59.282601 checksum: fb
9265 00:58:59.282664
9266 00:58:59.285450 Manufacturer: IVO Model 57d Serial Number 0
9267 00:58:59.289108 Made week 0 of 2020
9268 00:58:59.292110 EDID version: 1.4
9269 00:58:59.292205 Digital display
9270 00:58:59.295629 6 bits per primary color channel
9271 00:58:59.295711 DisplayPort interface
9272 00:58:59.298812 Maximum image size: 31 cm x 17 cm
9273 00:58:59.302197 Gamma: 220%
9274 00:58:59.302271 Check DPMS levels
9275 00:58:59.305792 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9276 00:58:59.312067 First detailed timing is preferred timing
9277 00:58:59.312149 Established timings supported:
9278 00:58:59.315604 Standard timings supported:
9279 00:58:59.318932 Detailed timings
9280 00:58:59.322180 Hex of detail: 383680a07038204018303c0035ae10000019
9281 00:58:59.328820 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9282 00:58:59.331793 0780 0798 07c8 0820 hborder 0
9283 00:58:59.335317 0438 043b 0447 0458 vborder 0
9284 00:58:59.338831 -hsync -vsync
9285 00:58:59.338908 Did detailed timing
9286 00:58:59.345239 Hex of detail: 000000000000000000000000000000000000
9287 00:58:59.348476 Manufacturer-specified data, tag 0
9288 00:58:59.352240 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9289 00:58:59.354879 ASCII string: InfoVision
9290 00:58:59.358670 Hex of detail: 000000fe00523134304e574635205248200a
9291 00:58:59.361958 ASCII string: R140NWF5 RH
9292 00:58:59.362039 Checksum
9293 00:58:59.365133 Checksum: 0xfb (valid)
9294 00:58:59.368463 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9295 00:58:59.371676 DSI data_rate: 832800000 bps
9296 00:58:59.378764 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9297 00:58:59.382008 anx7625_parse_edid: pixelclock(138800).
9298 00:58:59.384766 hactive(1920), hsync(48), hfp(24), hbp(88)
9299 00:58:59.388521 vactive(1080), vsync(12), vfp(3), vbp(17)
9300 00:58:59.391800 anx7625_dsi_config: config dsi.
9301 00:58:59.398252 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9302 00:58:59.411743 anx7625_dsi_config: success to config DSI
9303 00:58:59.415315 anx7625_dp_start: MIPI phy setup OK.
9304 00:58:59.418328 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9305 00:58:59.421991 mtk_ddp_mode_set invalid vrefresh 60
9306 00:58:59.424862 main_disp_path_setup
9307 00:58:59.424965 ovl_layer_smi_id_en
9308 00:58:59.428439 ovl_layer_smi_id_en
9309 00:58:59.428511 ccorr_config
9310 00:58:59.428570 aal_config
9311 00:58:59.431848 gamma_config
9312 00:58:59.431949 postmask_config
9313 00:58:59.434843 dither_config
9314 00:58:59.438288 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9315 00:58:59.445240 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9316 00:58:59.448459 Root Device init finished in 555 msecs
9317 00:58:59.448534 CPU_CLUSTER: 0 init
9318 00:58:59.458373 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9319 00:58:59.461310 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9320 00:58:59.464411 APU_MBOX 0x190000b0 = 0x10001
9321 00:58:59.468249 APU_MBOX 0x190001b0 = 0x10001
9322 00:58:59.471590 APU_MBOX 0x190005b0 = 0x10001
9323 00:58:59.474736 APU_MBOX 0x190006b0 = 0x10001
9324 00:58:59.478094 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9325 00:58:59.490811 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9326 00:58:59.503357 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9327 00:58:59.509855 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9328 00:58:59.521647 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9329 00:58:59.530745 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9330 00:58:59.533828 CPU_CLUSTER: 0 init finished in 81 msecs
9331 00:58:59.536931 Devices initialized
9332 00:58:59.540703 Show all devs... After init.
9333 00:58:59.540782 Root Device: enabled 1
9334 00:58:59.543930 CPU_CLUSTER: 0: enabled 1
9335 00:58:59.547144 CPU: 00: enabled 1
9336 00:58:59.550200 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9337 00:58:59.553724 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9338 00:58:59.557173 ELOG: NV offset 0x57f000 size 0x1000
9339 00:58:59.563385 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9340 00:58:59.569871 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9341 00:58:59.573465 ELOG: Event(17) added with size 13 at 2024-01-19 00:56:20 UTC
9342 00:58:59.577206 out: cmd=0x121: 03 db 21 01 00 00 00 00
9343 00:58:59.580823 in-header: 03 f4 00 00 2c 00 00 00
9344 00:58:59.593838 in-data: 6b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 00:58:59.600476 ELOG: Event(A1) added with size 10 at 2024-01-19 00:56:20 UTC
9346 00:58:59.607490 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9347 00:58:59.614170 ELOG: Event(A0) added with size 9 at 2024-01-19 00:56:20 UTC
9348 00:58:59.617288 elog_add_boot_reason: Logged dev mode boot
9349 00:58:59.620491 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9350 00:58:59.624190 Finalize devices...
9351 00:58:59.624271 Devices finalized
9352 00:58:59.630454 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9353 00:58:59.634037 Writing coreboot table at 0xffe64000
9354 00:58:59.637031 0. 000000000010a000-0000000000113fff: RAMSTAGE
9355 00:58:59.640247 1. 0000000040000000-00000000400fffff: RAM
9356 00:58:59.643805 2. 0000000040100000-000000004032afff: RAMSTAGE
9357 00:58:59.650626 3. 000000004032b000-00000000545fffff: RAM
9358 00:58:59.653950 4. 0000000054600000-000000005465ffff: BL31
9359 00:58:59.657076 5. 0000000054660000-00000000ffe63fff: RAM
9360 00:58:59.664060 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9361 00:58:59.667371 7. 0000000100000000-000000023fffffff: RAM
9362 00:58:59.667467 Passing 5 GPIOs to payload:
9363 00:58:59.674441 NAME | PORT | POLARITY | VALUE
9364 00:58:59.677063 EC in RW | 0x000000aa | low | undefined
9365 00:58:59.683936 EC interrupt | 0x00000005 | low | undefined
9366 00:58:59.687039 TPM interrupt | 0x000000ab | high | undefined
9367 00:58:59.690300 SD card detect | 0x00000011 | high | undefined
9368 00:58:59.697314 speaker enable | 0x00000093 | high | undefined
9369 00:58:59.700458 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9370 00:58:59.703917 in-header: 03 f9 00 00 02 00 00 00
9371 00:58:59.703998 in-data: 02 00
9372 00:58:59.707185 ADC[4]: Raw value=903988 ID=7
9373 00:58:59.710486 ADC[3]: Raw value=213441 ID=1
9374 00:58:59.710567 RAM Code: 0x71
9375 00:58:59.713760 ADC[6]: Raw value=75332 ID=0
9376 00:58:59.717098 ADC[5]: Raw value=212703 ID=1
9377 00:58:59.717179 SKU Code: 0x1
9378 00:58:59.724067 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4709
9379 00:58:59.727327 coreboot table: 964 bytes.
9380 00:58:59.730534 IMD ROOT 0. 0xfffff000 0x00001000
9381 00:58:59.733749 IMD SMALL 1. 0xffffe000 0x00001000
9382 00:58:59.736729 RO MCACHE 2. 0xffffc000 0x00001104
9383 00:58:59.740509 CONSOLE 3. 0xfff7c000 0x00080000
9384 00:58:59.743499 FMAP 4. 0xfff7b000 0x00000452
9385 00:58:59.747223 TIME STAMP 5. 0xfff7a000 0x00000910
9386 00:58:59.750119 VBOOT WORK 6. 0xfff66000 0x00014000
9387 00:58:59.753733 RAMOOPS 7. 0xffe66000 0x00100000
9388 00:58:59.756936 COREBOOT 8. 0xffe64000 0x00002000
9389 00:58:59.757018 IMD small region:
9390 00:58:59.760105 IMD ROOT 0. 0xffffec00 0x00000400
9391 00:58:59.763218 VPD 1. 0xffffeb80 0x0000006c
9392 00:58:59.766912 MMC STATUS 2. 0xffffeb60 0x00000004
9393 00:58:59.773880 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9394 00:58:59.773962 Probing TPM: done!
9395 00:58:59.780708 Connected to device vid:did:rid of 1ae0:0028:00
9396 00:58:59.787193 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9397 00:58:59.790430 Initialized TPM device CR50 revision 0
9398 00:58:59.795037 Checking cr50 for pending updates
9399 00:58:59.800727 Reading cr50 TPM mode
9400 00:58:59.809409 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9401 00:58:59.816054 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9402 00:58:59.855718 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9403 00:58:59.858837 Checking segment from ROM address 0x40100000
9404 00:58:59.862561 Checking segment from ROM address 0x4010001c
9405 00:58:59.869301 Loading segment from ROM address 0x40100000
9406 00:58:59.869384 code (compression=0)
9407 00:58:59.875620 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9408 00:58:59.885674 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9409 00:58:59.885782 it's not compressed!
9410 00:58:59.892662 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9411 00:58:59.895837 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9412 00:58:59.916074 Loading segment from ROM address 0x4010001c
9413 00:58:59.916157 Entry Point 0x80000000
9414 00:58:59.919819 Loaded segments
9415 00:58:59.922635 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9416 00:58:59.929434 Jumping to boot code at 0x80000000(0xffe64000)
9417 00:58:59.936533 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9418 00:58:59.943014 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9419 00:58:59.950453 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9420 00:58:59.953764 Checking segment from ROM address 0x40100000
9421 00:58:59.957264 Checking segment from ROM address 0x4010001c
9422 00:58:59.964108 Loading segment from ROM address 0x40100000
9423 00:58:59.964213 code (compression=1)
9424 00:58:59.970499 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9425 00:58:59.980410 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9426 00:58:59.980514 using LZMA
9427 00:58:59.988701 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9428 00:58:59.995504 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9429 00:58:59.999180 Loading segment from ROM address 0x4010001c
9430 00:58:59.999256 Entry Point 0x54601000
9431 00:59:00.002411 Loaded segments
9432 00:59:00.005567 NOTICE: MT8192 bl31_setup
9433 00:59:00.012777 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9434 00:59:00.016086 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9435 00:59:00.019102 WARNING: region 0:
9436 00:59:00.022722 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 00:59:00.022823 WARNING: region 1:
9438 00:59:00.029301 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9439 00:59:00.032442 WARNING: region 2:
9440 00:59:00.036094 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9441 00:59:00.039310 WARNING: region 3:
9442 00:59:00.042586 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 00:59:00.045954 WARNING: region 4:
9444 00:59:00.049486 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 00:59:00.052650 WARNING: region 5:
9446 00:59:00.055937 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 00:59:00.059580 WARNING: region 6:
9448 00:59:00.062655 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 00:59:00.062761 WARNING: region 7:
9450 00:59:00.069758 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 00:59:00.076076 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9452 00:59:00.079232 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9453 00:59:00.083038 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9454 00:59:00.089677 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9455 00:59:00.092873 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9456 00:59:00.096142 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9457 00:59:00.102871 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9458 00:59:00.106098 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9459 00:59:00.109323 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9460 00:59:00.116435 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9461 00:59:00.119709 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9462 00:59:00.122973 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9463 00:59:00.129190 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9464 00:59:00.133140 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9465 00:59:00.139469 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9466 00:59:00.142774 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9467 00:59:00.146141 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9468 00:59:00.152791 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9469 00:59:00.155900 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9470 00:59:00.159337 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9471 00:59:00.165781 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9472 00:59:00.169693 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9473 00:59:00.176422 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9474 00:59:00.179480 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9475 00:59:00.186199 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9476 00:59:00.189396 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9477 00:59:00.192512 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9478 00:59:00.199109 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9479 00:59:00.202845 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9480 00:59:00.205754 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9481 00:59:00.212357 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9482 00:59:00.215758 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9483 00:59:00.222193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9484 00:59:00.226116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9485 00:59:00.229401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9486 00:59:00.232589 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9487 00:59:00.239421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9488 00:59:00.242464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9489 00:59:00.245810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9490 00:59:00.249087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9491 00:59:00.252283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9492 00:59:00.259482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9493 00:59:00.262724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9494 00:59:00.266130 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9495 00:59:00.269086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9496 00:59:00.275684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9497 00:59:00.279470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9498 00:59:00.282543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9499 00:59:00.289329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9500 00:59:00.292692 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9501 00:59:00.299262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9502 00:59:00.302496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9503 00:59:00.305816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9504 00:59:00.312936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9505 00:59:00.316043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9506 00:59:00.322721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9507 00:59:00.325857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9508 00:59:00.329361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9509 00:59:00.336138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9510 00:59:00.339342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9511 00:59:00.346012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9512 00:59:00.349538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9513 00:59:00.356048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9514 00:59:00.359899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9515 00:59:00.366401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9516 00:59:00.369844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9517 00:59:00.373050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9518 00:59:00.379815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9519 00:59:00.382813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9520 00:59:00.389569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9521 00:59:00.392666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9522 00:59:00.396222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9523 00:59:00.403217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9524 00:59:00.406326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9525 00:59:00.413008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9526 00:59:00.416242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9527 00:59:00.422690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9528 00:59:00.426402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9529 00:59:00.432774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9530 00:59:00.436074 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9531 00:59:00.439659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9532 00:59:00.445986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9533 00:59:00.449489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9534 00:59:00.456462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9535 00:59:00.459365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9536 00:59:00.466307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9537 00:59:00.469555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9538 00:59:00.472854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9539 00:59:00.479368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9540 00:59:00.482726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9541 00:59:00.489807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9542 00:59:00.492907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9543 00:59:00.499674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9544 00:59:00.502732 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9545 00:59:00.506235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9546 00:59:00.512882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9547 00:59:00.516092 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9548 00:59:00.519224 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9549 00:59:00.526343 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9550 00:59:00.529541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9551 00:59:00.532726 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9552 00:59:00.539540 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9553 00:59:00.542763 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9554 00:59:00.546111 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9555 00:59:00.552727 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9556 00:59:00.556237 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9557 00:59:00.562918 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9558 00:59:00.566356 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9559 00:59:00.569148 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9560 00:59:00.576241 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9561 00:59:00.579602 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9562 00:59:00.586350 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9563 00:59:00.589443 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9564 00:59:00.592775 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9565 00:59:00.599278 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9566 00:59:00.602566 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9567 00:59:00.606219 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9568 00:59:00.612917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9569 00:59:00.616071 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9570 00:59:00.619718 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9571 00:59:00.622966 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9572 00:59:00.629625 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9573 00:59:00.632883 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9574 00:59:00.635864 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9575 00:59:00.642501 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9576 00:59:00.646209 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9577 00:59:00.649386 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9578 00:59:00.656120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9579 00:59:00.659101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9580 00:59:00.665807 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9581 00:59:00.669712 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9582 00:59:00.672911 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9583 00:59:00.679154 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9584 00:59:00.682443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9585 00:59:00.686001 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9586 00:59:00.693015 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9587 00:59:00.696099 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9588 00:59:00.702721 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9589 00:59:00.706030 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9590 00:59:00.709830 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9591 00:59:00.716249 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9592 00:59:00.719868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9593 00:59:00.723072 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9594 00:59:00.729376 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9595 00:59:00.733485 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9596 00:59:00.740137 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9597 00:59:00.743015 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9598 00:59:00.746712 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9599 00:59:00.752801 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9600 00:59:00.756536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9601 00:59:00.763393 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9602 00:59:00.766498 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9603 00:59:00.769434 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9604 00:59:00.776319 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9605 00:59:00.780043 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9606 00:59:00.783248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9607 00:59:00.789901 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9608 00:59:00.792903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9609 00:59:00.799627 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9610 00:59:00.803381 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9611 00:59:00.806440 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9612 00:59:00.813039 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9613 00:59:00.816413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9614 00:59:00.819491 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9615 00:59:00.826535 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9616 00:59:00.829630 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9617 00:59:00.836110 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9618 00:59:00.839337 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9619 00:59:00.842653 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9620 00:59:00.849870 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9621 00:59:00.852905 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9622 00:59:00.859931 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9623 00:59:00.863521 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9624 00:59:00.866408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9625 00:59:00.873150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9626 00:59:00.876460 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9627 00:59:00.882777 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9628 00:59:00.886097 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9629 00:59:00.889605 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9630 00:59:00.896091 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9631 00:59:00.899285 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9632 00:59:00.902965 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9633 00:59:00.909368 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9634 00:59:00.912780 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9635 00:59:00.919755 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9636 00:59:00.922895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9637 00:59:00.926023 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9638 00:59:00.933092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9639 00:59:00.936257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9640 00:59:00.942689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9641 00:59:00.945995 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9642 00:59:00.952594 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9643 00:59:00.955886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9644 00:59:00.959054 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9645 00:59:00.966339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9646 00:59:00.969389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9647 00:59:00.976066 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9648 00:59:00.979237 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9649 00:59:00.982506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9650 00:59:00.989157 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9651 00:59:00.992470 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9652 00:59:00.999186 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9653 00:59:01.002443 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9654 00:59:01.005897 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9655 00:59:01.012736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9656 00:59:01.015771 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9657 00:59:01.022570 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9658 00:59:01.025901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9659 00:59:01.032218 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9660 00:59:01.035782 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9661 00:59:01.038946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9662 00:59:01.045379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9663 00:59:01.048671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9664 00:59:01.055835 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9665 00:59:01.059020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9666 00:59:01.062465 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9667 00:59:01.068930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9668 00:59:01.072138 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9669 00:59:01.078971 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9670 00:59:01.082013 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9671 00:59:01.088577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9672 00:59:01.091930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9673 00:59:01.095272 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9674 00:59:01.102310 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9675 00:59:01.105771 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9676 00:59:01.112264 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9677 00:59:01.115342 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9678 00:59:01.118853 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9679 00:59:01.125255 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9680 00:59:01.128624 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9681 00:59:01.132102 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9682 00:59:01.138628 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9683 00:59:01.142052 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9684 00:59:01.145348 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9685 00:59:01.148752 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9686 00:59:01.154910 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9687 00:59:01.158768 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9688 00:59:01.165182 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9689 00:59:01.168399 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9690 00:59:01.171624 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9691 00:59:01.178391 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9692 00:59:01.181791 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9693 00:59:01.185368 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9694 00:59:01.191708 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9695 00:59:01.195013 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9696 00:59:01.198314 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9697 00:59:01.204788 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9698 00:59:01.207999 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9699 00:59:01.211181 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9700 00:59:01.218277 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9701 00:59:01.221296 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9702 00:59:01.228095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9703 00:59:01.231641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9704 00:59:01.234537 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9705 00:59:01.241545 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9706 00:59:01.244761 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9707 00:59:01.251109 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9708 00:59:01.254867 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9709 00:59:01.258017 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9710 00:59:01.264549 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9711 00:59:01.268030 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9712 00:59:01.271346 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9713 00:59:01.277803 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9714 00:59:01.281060 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9715 00:59:01.284296 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9716 00:59:01.291431 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9717 00:59:01.294443 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9718 00:59:01.301117 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9719 00:59:01.304470 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9720 00:59:01.307718 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9721 00:59:01.310956 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9722 00:59:01.314404 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9723 00:59:01.320961 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9724 00:59:01.324681 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9725 00:59:01.327604 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9726 00:59:01.330951 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9727 00:59:01.337462 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9728 00:59:01.341136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9729 00:59:01.344739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9730 00:59:01.347575 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9731 00:59:01.354679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9732 00:59:01.357762 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9733 00:59:01.361275 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9734 00:59:01.367834 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9735 00:59:01.371063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9736 00:59:01.377856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9737 00:59:01.381446 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9738 00:59:01.384534 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9739 00:59:01.391101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9740 00:59:01.394309 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9741 00:59:01.400782 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9742 00:59:01.404003 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9743 00:59:01.407750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9744 00:59:01.414325 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9745 00:59:01.417712 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9746 00:59:01.424159 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9747 00:59:01.427534 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9748 00:59:01.434215 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9749 00:59:01.437320 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9750 00:59:01.440841 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9751 00:59:01.447387 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9752 00:59:01.450342 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9753 00:59:01.457266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9754 00:59:01.460729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9755 00:59:01.467324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9756 00:59:01.470664 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9757 00:59:01.473462 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9758 00:59:01.480174 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9759 00:59:01.483393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9760 00:59:01.490447 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9761 00:59:01.493489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9762 00:59:01.496729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9763 00:59:01.503666 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9764 00:59:01.506970 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9765 00:59:01.513457 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9766 00:59:01.517425 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9767 00:59:01.520407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9768 00:59:01.526848 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9769 00:59:01.530146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9770 00:59:01.536785 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9771 00:59:01.540024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9772 00:59:01.543241 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9773 00:59:01.549979 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9774 00:59:01.552887 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9775 00:59:01.559958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9776 00:59:01.563218 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9777 00:59:01.570158 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9778 00:59:01.573200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9779 00:59:01.576169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9780 00:59:01.583152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9781 00:59:01.586330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9782 00:59:01.592897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9783 00:59:01.596147 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9784 00:59:01.599312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9785 00:59:01.606268 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9786 00:59:01.609726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9787 00:59:01.616074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9788 00:59:01.619383 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9789 00:59:01.622713 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9790 00:59:01.629876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9791 00:59:01.632591 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9792 00:59:01.639834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9793 00:59:01.643098 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9794 00:59:01.646209 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9795 00:59:01.652841 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9796 00:59:01.655967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9797 00:59:01.662775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9798 00:59:01.665900 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9799 00:59:01.672334 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9800 00:59:01.675666 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9801 00:59:01.678793 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9802 00:59:01.686031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9803 00:59:01.689230 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9804 00:59:01.695462 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9805 00:59:01.699131 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9806 00:59:01.702355 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9807 00:59:01.708919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9808 00:59:01.712240 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9809 00:59:01.719039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9810 00:59:01.722043 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9811 00:59:01.728650 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9812 00:59:01.731822 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9813 00:59:01.738802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9814 00:59:01.741901 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9815 00:59:01.745635 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9816 00:59:01.751643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9817 00:59:01.754913 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9818 00:59:01.762071 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9819 00:59:01.765350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9820 00:59:01.771948 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9821 00:59:01.775069 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9822 00:59:01.778468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9823 00:59:01.785248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9824 00:59:01.788233 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9825 00:59:01.794850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9826 00:59:01.798045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9827 00:59:01.804624 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9828 00:59:01.808536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9829 00:59:01.811672 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9830 00:59:01.818386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9831 00:59:01.821623 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9832 00:59:01.828413 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9833 00:59:01.831614 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9834 00:59:01.837918 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9835 00:59:01.841342 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9836 00:59:01.848390 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9837 00:59:01.851714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9838 00:59:01.854734 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9839 00:59:01.861724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9840 00:59:01.864810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9841 00:59:01.871237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9842 00:59:01.874462 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9843 00:59:01.881111 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9844 00:59:01.884273 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9845 00:59:01.888022 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9846 00:59:01.894561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9847 00:59:01.897479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9848 00:59:01.904682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9849 00:59:01.907571 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9850 00:59:01.914267 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9851 00:59:01.917368 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9852 00:59:01.921369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9853 00:59:01.927542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9854 00:59:01.930923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9855 00:59:01.937469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9856 00:59:01.940913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9857 00:59:01.947746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9858 00:59:01.951273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9859 00:59:01.957379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9860 00:59:01.960755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9861 00:59:01.967224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9862 00:59:01.970686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9863 00:59:01.977260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9864 00:59:01.980603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9865 00:59:01.987082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9866 00:59:01.990627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9867 00:59:01.997532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9868 00:59:02.000731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9869 00:59:02.003770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9870 00:59:02.010900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9871 00:59:02.013924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9872 00:59:02.020403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9873 00:59:02.024202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9874 00:59:02.030698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9875 00:59:02.034015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9876 00:59:02.040425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9877 00:59:02.043879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9878 00:59:02.050598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9879 00:59:02.053743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9880 00:59:02.060602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9881 00:59:02.063959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9882 00:59:02.070726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9883 00:59:02.073689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9884 00:59:02.080239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9885 00:59:02.083729 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9886 00:59:02.086754 INFO: [APUAPC] vio 0
9887 00:59:02.090062 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9888 00:59:02.097164 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9889 00:59:02.100283 INFO: [APUAPC] D0_APC_0: 0x400510
9890 00:59:02.103492 INFO: [APUAPC] D0_APC_1: 0x0
9891 00:59:02.103573 INFO: [APUAPC] D0_APC_2: 0x1540
9892 00:59:02.107147 INFO: [APUAPC] D0_APC_3: 0x0
9893 00:59:02.110240 INFO: [APUAPC] D1_APC_0: 0xffffffff
9894 00:59:02.113534 INFO: [APUAPC] D1_APC_1: 0xffffffff
9895 00:59:02.116816 INFO: [APUAPC] D1_APC_2: 0x3fffff
9896 00:59:02.120169 INFO: [APUAPC] D1_APC_3: 0x0
9897 00:59:02.123817 INFO: [APUAPC] D2_APC_0: 0xffffffff
9898 00:59:02.126808 INFO: [APUAPC] D2_APC_1: 0xffffffff
9899 00:59:02.130178 INFO: [APUAPC] D2_APC_2: 0x3fffff
9900 00:59:02.133292 INFO: [APUAPC] D2_APC_3: 0x0
9901 00:59:02.136693 INFO: [APUAPC] D3_APC_0: 0xffffffff
9902 00:59:02.139941 INFO: [APUAPC] D3_APC_1: 0xffffffff
9903 00:59:02.143268 INFO: [APUAPC] D3_APC_2: 0x3fffff
9904 00:59:02.146720 INFO: [APUAPC] D3_APC_3: 0x0
9905 00:59:02.150234 INFO: [APUAPC] D4_APC_0: 0xffffffff
9906 00:59:02.153915 INFO: [APUAPC] D4_APC_1: 0xffffffff
9907 00:59:02.156895 INFO: [APUAPC] D4_APC_2: 0x3fffff
9908 00:59:02.160118 INFO: [APUAPC] D4_APC_3: 0x0
9909 00:59:02.163360 INFO: [APUAPC] D5_APC_0: 0xffffffff
9910 00:59:02.166582 INFO: [APUAPC] D5_APC_1: 0xffffffff
9911 00:59:02.169629 INFO: [APUAPC] D5_APC_2: 0x3fffff
9912 00:59:02.173386 INFO: [APUAPC] D5_APC_3: 0x0
9913 00:59:02.176928 INFO: [APUAPC] D6_APC_0: 0xffffffff
9914 00:59:02.179791 INFO: [APUAPC] D6_APC_1: 0xffffffff
9915 00:59:02.183267 INFO: [APUAPC] D6_APC_2: 0x3fffff
9916 00:59:02.186520 INFO: [APUAPC] D6_APC_3: 0x0
9917 00:59:02.189643 INFO: [APUAPC] D7_APC_0: 0xffffffff
9918 00:59:02.193551 INFO: [APUAPC] D7_APC_1: 0xffffffff
9919 00:59:02.196226 INFO: [APUAPC] D7_APC_2: 0x3fffff
9920 00:59:02.200012 INFO: [APUAPC] D7_APC_3: 0x0
9921 00:59:02.202954 INFO: [APUAPC] D8_APC_0: 0xffffffff
9922 00:59:02.206635 INFO: [APUAPC] D8_APC_1: 0xffffffff
9923 00:59:02.209931 INFO: [APUAPC] D8_APC_2: 0x3fffff
9924 00:59:02.213156 INFO: [APUAPC] D8_APC_3: 0x0
9925 00:59:02.216091 INFO: [APUAPC] D9_APC_0: 0xffffffff
9926 00:59:02.219909 INFO: [APUAPC] D9_APC_1: 0xffffffff
9927 00:59:02.223130 INFO: [APUAPC] D9_APC_2: 0x3fffff
9928 00:59:02.226339 INFO: [APUAPC] D9_APC_3: 0x0
9929 00:59:02.229627 INFO: [APUAPC] D10_APC_0: 0xffffffff
9930 00:59:02.232948 INFO: [APUAPC] D10_APC_1: 0xffffffff
9931 00:59:02.235930 INFO: [APUAPC] D10_APC_2: 0x3fffff
9932 00:59:02.239584 INFO: [APUAPC] D10_APC_3: 0x0
9933 00:59:02.243070 INFO: [APUAPC] D11_APC_0: 0xffffffff
9934 00:59:02.246274 INFO: [APUAPC] D11_APC_1: 0xffffffff
9935 00:59:02.249494 INFO: [APUAPC] D11_APC_2: 0x3fffff
9936 00:59:02.252768 INFO: [APUAPC] D11_APC_3: 0x0
9937 00:59:02.255987 INFO: [APUAPC] D12_APC_0: 0xffffffff
9938 00:59:02.259024 INFO: [APUAPC] D12_APC_1: 0xffffffff
9939 00:59:02.262644 INFO: [APUAPC] D12_APC_2: 0x3fffff
9940 00:59:02.265717 INFO: [APUAPC] D12_APC_3: 0x0
9941 00:59:02.268965 INFO: [APUAPC] D13_APC_0: 0xffffffff
9942 00:59:02.272929 INFO: [APUAPC] D13_APC_1: 0xffffffff
9943 00:59:02.276250 INFO: [APUAPC] D13_APC_2: 0x3fffff
9944 00:59:02.279553 INFO: [APUAPC] D13_APC_3: 0x0
9945 00:59:02.282358 INFO: [APUAPC] D14_APC_0: 0xffffffff
9946 00:59:02.285994 INFO: [APUAPC] D14_APC_1: 0xffffffff
9947 00:59:02.289073 INFO: [APUAPC] D14_APC_2: 0x3fffff
9948 00:59:02.292751 INFO: [APUAPC] D14_APC_3: 0x0
9949 00:59:02.295996 INFO: [APUAPC] D15_APC_0: 0xffffffff
9950 00:59:02.299285 INFO: [APUAPC] D15_APC_1: 0xffffffff
9951 00:59:02.302393 INFO: [APUAPC] D15_APC_2: 0x3fffff
9952 00:59:02.305638 INFO: [APUAPC] D15_APC_3: 0x0
9953 00:59:02.309518 INFO: [APUAPC] APC_CON: 0x4
9954 00:59:02.312573 INFO: [NOCDAPC] D0_APC_0: 0x0
9955 00:59:02.312661 INFO: [NOCDAPC] D0_APC_1: 0x0
9956 00:59:02.315779 INFO: [NOCDAPC] D1_APC_0: 0x0
9957 00:59:02.319069 INFO: [NOCDAPC] D1_APC_1: 0xfff
9958 00:59:02.322306 INFO: [NOCDAPC] D2_APC_0: 0x0
9959 00:59:02.326062 INFO: [NOCDAPC] D2_APC_1: 0xfff
9960 00:59:02.329265 INFO: [NOCDAPC] D3_APC_0: 0x0
9961 00:59:02.332468 INFO: [NOCDAPC] D3_APC_1: 0xfff
9962 00:59:02.335635 INFO: [NOCDAPC] D4_APC_0: 0x0
9963 00:59:02.339181 INFO: [NOCDAPC] D4_APC_1: 0xfff
9964 00:59:02.342328 INFO: [NOCDAPC] D5_APC_0: 0x0
9965 00:59:02.342422 INFO: [NOCDAPC] D5_APC_1: 0xfff
9966 00:59:02.345402 INFO: [NOCDAPC] D6_APC_0: 0x0
9967 00:59:02.349192 INFO: [NOCDAPC] D6_APC_1: 0xfff
9968 00:59:02.352359 INFO: [NOCDAPC] D7_APC_0: 0x0
9969 00:59:02.355471 INFO: [NOCDAPC] D7_APC_1: 0xfff
9970 00:59:02.359359 INFO: [NOCDAPC] D8_APC_0: 0x0
9971 00:59:02.362558 INFO: [NOCDAPC] D8_APC_1: 0xfff
9972 00:59:02.365640 INFO: [NOCDAPC] D9_APC_0: 0x0
9973 00:59:02.369245 INFO: [NOCDAPC] D9_APC_1: 0xfff
9974 00:59:02.372181 INFO: [NOCDAPC] D10_APC_0: 0x0
9975 00:59:02.375456 INFO: [NOCDAPC] D10_APC_1: 0xfff
9976 00:59:02.379267 INFO: [NOCDAPC] D11_APC_0: 0x0
9977 00:59:02.379369 INFO: [NOCDAPC] D11_APC_1: 0xfff
9978 00:59:02.382474 INFO: [NOCDAPC] D12_APC_0: 0x0
9979 00:59:02.385770 INFO: [NOCDAPC] D12_APC_1: 0xfff
9980 00:59:02.389084 INFO: [NOCDAPC] D13_APC_0: 0x0
9981 00:59:02.392387 INFO: [NOCDAPC] D13_APC_1: 0xfff
9982 00:59:02.395584 INFO: [NOCDAPC] D14_APC_0: 0x0
9983 00:59:02.398867 INFO: [NOCDAPC] D14_APC_1: 0xfff
9984 00:59:02.402077 INFO: [NOCDAPC] D15_APC_0: 0x0
9985 00:59:02.405676 INFO: [NOCDAPC] D15_APC_1: 0xfff
9986 00:59:02.409191 INFO: [NOCDAPC] APC_CON: 0x4
9987 00:59:02.412538 INFO: [APUAPC] set_apusys_apc done
9988 00:59:02.415703 INFO: [DEVAPC] devapc_init done
9989 00:59:02.418755 INFO: GICv3 without legacy support detected.
9990 00:59:02.422386 INFO: ARM GICv3 driver initialized in EL3
9991 00:59:02.425411 INFO: Maximum SPI INTID supported: 639
9992 00:59:02.432417 INFO: BL31: Initializing runtime services
9993 00:59:02.435636 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9994 00:59:02.438796 INFO: SPM: enable CPC mode
9995 00:59:02.445679 INFO: mcdi ready for mcusys-off-idle and system suspend
9996 00:59:02.449037 INFO: BL31: Preparing for EL3 exit to normal world
9997 00:59:02.452224 INFO: Entry point address = 0x80000000
9998 00:59:02.455468 INFO: SPSR = 0x8
9999 00:59:02.460468
10000 00:59:02.460549
10001 00:59:02.460613
10002 00:59:02.461264 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10003 00:59:02.461365 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10004 00:59:02.461446 Setting prompt string to ['asurada:']
10005 00:59:02.461524 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10006 00:59:02.464090 Starting depthcharge on Spherion...
10007 00:59:02.464172
10008 00:59:02.464250 Wipe memory regions:
10009 00:59:02.464336
10010 00:59:02.466888 [0x00000040000000, 0x00000054600000)
10011 00:59:02.589146
10012 00:59:02.589284 [0x00000054660000, 0x00000080000000)
10013 00:59:02.850187
10014 00:59:02.850329 [0x000000821a7280, 0x000000ffe64000)
10015 00:59:03.594627
10016 00:59:03.594797 [0x00000100000000, 0x00000240000000)
10017 00:59:05.485427
10018 00:59:05.488538 Initializing XHCI USB controller at 0x11200000.
10019 00:59:06.526531
10020 00:59:06.529888 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10021 00:59:06.529969
10022 00:59:06.530032
10023 00:59:06.530098
10024 00:59:06.530376 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 00:59:06.630661 asurada: tftpboot 192.168.201.1 12571066/tftp-deploy-rlef6bsi/kernel/image.itb 12571066/tftp-deploy-rlef6bsi/kernel/cmdline
10027 00:59:06.630789 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10028 00:59:06.630915 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10029 00:59:06.634894 tftpboot 192.168.201.1 12571066/tftp-deploy-rlef6bsi/kernel/image.ittp-deploy-rlef6bsi/kernel/cmdline
10030 00:59:06.635003
10031 00:59:06.635070 Waiting for link
10032 00:59:06.795270
10033 00:59:06.795394 R8152: Initializing
10034 00:59:06.795460
10035 00:59:06.798939 Version 9 (ocp_data = 6010)
10036 00:59:06.799023
10037 00:59:06.802105 R8152: Done initializing
10038 00:59:06.802177
10039 00:59:06.802238 Adding net device
10040 00:59:08.748008
10041 00:59:08.748147 done.
10042 00:59:08.748214
10043 00:59:08.748274 MAC: 00:e0:4c:78:7a:aa
10044 00:59:08.748384
10045 00:59:08.750916 Sending DHCP discover... done.
10046 00:59:08.751031
10047 00:59:12.581585 Waiting for reply... done.
10048 00:59:12.582109
10049 00:59:12.582476 Sending DHCP request... done.
10050 00:59:12.585321
10051 00:59:12.588445 Waiting for reply... done.
10052 00:59:12.588899
10053 00:59:12.589262 My ip is 192.168.201.12
10054 00:59:12.589597
10055 00:59:12.591662 The DHCP server ip is 192.168.201.1
10056 00:59:12.592072
10057 00:59:12.594983 TFTP server IP predefined by user: 192.168.201.1
10058 00:59:12.598253
10059 00:59:12.601574 Bootfile predefined by user: 12571066/tftp-deploy-rlef6bsi/kernel/image.itb
10060 00:59:12.604713
10061 00:59:12.605123 Sending tftp read request... done.
10062 00:59:12.605445
10063 00:59:12.613907 Waiting for the transfer...
10064 00:59:12.614323
10065 00:59:12.893203 00000000 ################################################################
10066 00:59:12.893335
10067 00:59:13.178530 00080000 ################################################################
10068 00:59:13.178688
10069 00:59:13.459074 00100000 ################################################################
10070 00:59:13.459208
10071 00:59:13.731733 00180000 ################################################################
10072 00:59:13.731891
10073 00:59:13.997807 00200000 ################################################################
10074 00:59:13.997938
10075 00:59:14.257432 00280000 ################################################################
10076 00:59:14.257562
10077 00:59:14.541217 00300000 ################################################################
10078 00:59:14.541348
10079 00:59:14.819419 00380000 ################################################################
10080 00:59:14.819554
10081 00:59:15.105456 00400000 ################################################################
10082 00:59:15.105590
10083 00:59:15.391936 00480000 ################################################################
10084 00:59:15.392098
10085 00:59:15.672264 00500000 ################################################################
10086 00:59:15.672446
10087 00:59:15.943945 00580000 ################################################################
10088 00:59:15.944085
10089 00:59:16.222399 00600000 ################################################################
10090 00:59:16.222539
10091 00:59:16.506175 00680000 ################################################################
10092 00:59:16.506313
10093 00:59:16.777211 00700000 ################################################################
10094 00:59:16.777356
10095 00:59:17.050550 00780000 ################################################################
10096 00:59:17.050686
10097 00:59:17.342366 00800000 ################################################################
10098 00:59:17.342535
10099 00:59:17.632091 00880000 ################################################################
10100 00:59:17.632236
10101 00:59:17.913067 00900000 ################################################################
10102 00:59:17.913213
10103 00:59:18.208622 00980000 ################################################################
10104 00:59:18.208796
10105 00:59:18.486199 00a00000 ################################################################
10106 00:59:18.486347
10107 00:59:18.766963 00a80000 ################################################################
10108 00:59:18.767154
10109 00:59:19.047850 00b00000 ################################################################
10110 00:59:19.047990
10111 00:59:19.325930 00b80000 ################################################################
10112 00:59:19.326075
10113 00:59:19.622982 00c00000 ################################################################
10114 00:59:19.623127
10115 00:59:19.914950 00c80000 ################################################################
10116 00:59:19.915097
10117 00:59:20.190545 00d00000 ################################################################
10118 00:59:20.190686
10119 00:59:20.446454 00d80000 ################################################################
10120 00:59:20.446592
10121 00:59:20.740007 00e00000 ################################################################
10122 00:59:20.740143
10123 00:59:21.035079 00e80000 ################################################################
10124 00:59:21.035226
10125 00:59:21.326999 00f00000 ################################################################
10126 00:59:21.327172
10127 00:59:21.602545 00f80000 ################################################################
10128 00:59:21.602711
10129 00:59:21.880093 01000000 ################################################################
10130 00:59:21.880235
10131 00:59:22.175942 01080000 ################################################################
10132 00:59:22.176083
10133 00:59:22.450514 01100000 ################################################################
10134 00:59:22.450655
10135 00:59:22.724933 01180000 ################################################################
10136 00:59:22.725071
10137 00:59:23.011916 01200000 ################################################################
10138 00:59:23.012063
10139 00:59:23.301507 01280000 ################################################################
10140 00:59:23.301673
10141 00:59:23.583504 01300000 ################################################################
10142 00:59:23.583671
10143 00:59:23.859387 01380000 ################################################################
10144 00:59:23.859561
10145 00:59:24.127342 01400000 ################################################################
10146 00:59:24.127476
10147 00:59:24.378992 01480000 ################################################################
10148 00:59:24.379150
10149 00:59:24.643610 01500000 ################################################################
10150 00:59:24.643743
10151 00:59:24.933390 01580000 ################################################################
10152 00:59:24.933533
10153 00:59:25.197826 01600000 ################################################################
10154 00:59:25.197962
10155 00:59:25.478422 01680000 ################################################################
10156 00:59:25.478562
10157 00:59:25.750608 01700000 ################################################################
10158 00:59:25.750757
10159 00:59:26.044035 01780000 ################################################################
10160 00:59:26.044181
10161 00:59:26.332163 01800000 ################################################################
10162 00:59:26.332373
10163 00:59:26.623916 01880000 ################################################################
10164 00:59:26.624061
10165 00:59:26.897832 01900000 ################################################################
10166 00:59:26.897969
10167 00:59:27.190113 01980000 ################################################################
10168 00:59:27.190256
10169 00:59:27.466818 01a00000 ################################################################
10170 00:59:27.466957
10171 00:59:27.743797 01a80000 ################################################################
10172 00:59:27.743945
10173 00:59:28.028268 01b00000 ################################################################
10174 00:59:28.028433
10175 00:59:28.315587 01b80000 ################################################################
10176 00:59:28.315724
10177 00:59:28.609647 01c00000 ################################################################
10178 00:59:28.609788
10179 00:59:28.893863 01c80000 ################################################################
10180 00:59:28.893996
10181 00:59:29.171469 01d00000 ################################################################
10182 00:59:29.171599
10183 00:59:29.429637 01d80000 ################################################################
10184 00:59:29.429767
10185 00:59:29.684253 01e00000 ################################################################
10186 00:59:29.684401
10187 00:59:29.934272 01e80000 ################################################################
10188 00:59:29.934415
10189 00:59:30.183713 01f00000 ################################################################
10190 00:59:30.183856
10191 00:59:30.457871 01f80000 ################################################################
10192 00:59:30.458011
10193 00:59:30.744511 02000000 ################################################################
10194 00:59:30.744649
10195 00:59:31.027606 02080000 ################################################################
10196 00:59:31.027763
10197 00:59:31.287916 02100000 ################################################################
10198 00:59:31.288061
10199 00:59:31.556878 02180000 ################################################################
10200 00:59:31.557012
10201 00:59:31.846026 02200000 ################################################################
10202 00:59:31.846163
10203 00:59:32.141403 02280000 ################################################################
10204 00:59:32.141536
10205 00:59:32.426360 02300000 ################################################################
10206 00:59:32.426508
10207 00:59:32.713336 02380000 ################################################################
10208 00:59:32.713502
10209 00:59:32.998763 02400000 ################################################################
10210 00:59:32.998912
10211 00:59:33.281482 02480000 ################################################################
10212 00:59:33.281659
10213 00:59:33.565207 02500000 ################################################################
10214 00:59:33.565351
10215 00:59:33.842134 02580000 ################################################################
10216 00:59:33.842267
10217 00:59:34.129579 02600000 ################################################################
10218 00:59:34.129735
10219 00:59:34.404814 02680000 ################################################################
10220 00:59:34.404967
10221 00:59:34.687879 02700000 ################################################################
10222 00:59:34.688009
10223 00:59:34.945033 02780000 ################################################################
10224 00:59:34.945162
10225 00:59:35.199848 02800000 ################################################################
10226 00:59:35.199989
10227 00:59:35.476180 02880000 ################################################################
10228 00:59:35.476398
10229 00:59:35.762377 02900000 ################################################################
10230 00:59:35.762534
10231 00:59:36.011683 02980000 ################################################################
10232 00:59:36.011814
10233 00:59:36.273495 02a00000 ################################################################
10234 00:59:36.273626
10235 00:59:36.539420 02a80000 ################################################################
10236 00:59:36.539586
10237 00:59:36.796450 02b00000 ################################################################
10238 00:59:36.796580
10239 00:59:37.063520 02b80000 ################################################################
10240 00:59:37.063660
10241 00:59:37.319641 02c00000 ################################################################
10242 00:59:37.319781
10243 00:59:37.575479 02c80000 ################################################################
10244 00:59:37.575649
10245 00:59:37.833666 02d00000 ################################################################
10246 00:59:37.833801
10247 00:59:38.094875 02d80000 ################################################################
10248 00:59:38.095014
10249 00:59:38.360648 02e00000 ################################################################
10250 00:59:38.360783
10251 00:59:38.620095 02e80000 ################################################################
10252 00:59:38.620242
10253 00:59:38.889172 02f00000 ################################################################
10254 00:59:38.889304
10255 00:59:39.162919 02f80000 ################################################################
10256 00:59:39.163059
10257 00:59:39.452686 03000000 ################################################################
10258 00:59:39.452832
10259 00:59:39.738617 03080000 ################################################################
10260 00:59:39.738752
10261 00:59:40.029707 03100000 ################################################################
10262 00:59:40.029840
10263 00:59:40.310143 03180000 ################################################################
10264 00:59:40.310284
10265 00:59:40.591946 03200000 ################################################################
10266 00:59:40.592080
10267 00:59:40.867655 03280000 ################################################################
10268 00:59:40.867793
10269 00:59:41.127702 03300000 ################################################################
10270 00:59:41.127842
10271 00:59:41.394230 03380000 ################################################################
10272 00:59:41.394755
10273 00:59:41.666710 03400000 ################################################################
10274 00:59:41.666851
10275 00:59:41.935988 03480000 ################################################################
10276 00:59:41.936134
10277 00:59:42.220950 03500000 ################################################################
10278 00:59:42.221115
10279 00:59:42.508555 03580000 ################################################################
10280 00:59:42.508687
10281 00:59:42.790892 03600000 ################################################################
10282 00:59:42.791022
10283 00:59:43.075190 03680000 ################################################################
10284 00:59:43.075324
10285 00:59:43.334673 03700000 ################################################################
10286 00:59:43.334828
10287 00:59:43.593317 03780000 ################################################################
10288 00:59:43.593452
10289 00:59:43.862392 03800000 ################################################################
10290 00:59:43.862538
10291 00:59:44.136153 03880000 ################################################################
10292 00:59:44.136300
10293 00:59:44.426766 03900000 ################################################################
10294 00:59:44.426940
10295 00:59:44.700923 03980000 ################################################################
10296 00:59:44.701060
10297 00:59:44.992727 03a00000 ################################################################
10298 00:59:44.992873
10299 00:59:45.290632 03a80000 ################################################################
10300 00:59:45.290774
10301 00:59:45.575592 03b00000 ################################################################
10302 00:59:45.575724
10303 00:59:45.838663 03b80000 ################################################################
10304 00:59:45.838791
10305 00:59:46.098844 03c00000 ################################################################
10306 00:59:46.098975
10307 00:59:46.354496 03c80000 ################################################################
10308 00:59:46.354630
10309 00:59:46.617886 03d00000 ################################################################
10310 00:59:46.618018
10311 00:59:46.881761 03d80000 ################################################################
10312 00:59:46.881915
10313 00:59:47.160762 03e00000 ################################################################
10314 00:59:47.160903
10315 00:59:47.432030 03e80000 ################################################################
10316 00:59:47.432164
10317 00:59:47.697029 03f00000 ################################################################
10318 00:59:47.697160
10319 00:59:47.975700 03f80000 ################################################################
10320 00:59:47.975834
10321 00:59:48.250161 04000000 ################################################################
10322 00:59:48.250298
10323 00:59:48.526030 04080000 ################################################################
10324 00:59:48.526191
10325 00:59:48.721523 04100000 ############################################### done.
10326 00:59:48.721654
10327 00:59:48.724633 The bootfile was 68539602 bytes long.
10328 00:59:48.724714
10329 00:59:48.728198 Sending tftp read request... done.
10330 00:59:48.728278
10331 00:59:48.731472 Waiting for the transfer...
10332 00:59:48.731574
10333 00:59:48.734609 00000000 # done.
10334 00:59:48.734691
10335 00:59:48.741182 Command line loaded dynamically from TFTP file: 12571066/tftp-deploy-rlef6bsi/kernel/cmdline
10336 00:59:48.741265
10337 00:59:48.754585 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10338 00:59:48.754669
10339 00:59:48.754733 Loading FIT.
10340 00:59:48.758317
10341 00:59:48.758398 Image ramdisk-1 has 56441665 bytes.
10342 00:59:48.758462
10343 00:59:48.761331 Image fdt-1 has 47278 bytes.
10344 00:59:48.761412
10345 00:59:48.764551 Image kernel-1 has 12048624 bytes.
10346 00:59:48.764632
10347 00:59:48.774445 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10348 00:59:48.774533
10349 00:59:48.791402 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10350 00:59:48.791578
10351 00:59:48.798425 Choosing best match conf-1 for compat google,spherion-rev2.
10352 00:59:48.798611
10353 00:59:48.806032 Connected to device vid:did:rid of 1ae0:0028:00
10354 00:59:48.813814
10355 00:59:48.817702 tpm_get_response: command 0x17b, return code 0x0
10356 00:59:48.817783
10357 00:59:48.820473 ec_init: CrosEC protocol v3 supported (256, 248)
10358 00:59:48.825388
10359 00:59:48.828626 tpm_cleanup: add release locality here.
10360 00:59:48.828706
10361 00:59:48.828769 Shutting down all USB controllers.
10362 00:59:48.831680
10363 00:59:48.831764 Removing current net device
10364 00:59:48.831827
10365 00:59:48.838432 Exiting depthcharge with code 4 at timestamp: 75632256
10366 00:59:48.838512
10367 00:59:48.842115 LZMA decompressing kernel-1 to 0x821a6718
10368 00:59:48.842196
10369 00:59:48.845369 LZMA decompressing kernel-1 to 0x40000000
10370 00:59:50.344886
10371 00:59:50.345391 jumping to kernel
10372 00:59:50.347294 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10373 00:59:50.347754 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10374 00:59:50.348110 Setting prompt string to ['Linux version [0-9]']
10375 00:59:50.348491 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10376 00:59:50.348829 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10377 00:59:50.427642
10378 00:59:50.430972 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10379 00:59:50.434508 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10380 00:59:50.434970 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10381 00:59:50.435370 Setting prompt string to []
10382 00:59:50.435757 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10383 00:59:50.436111 Using line separator: #'\n'#
10384 00:59:50.436460 No login prompt set.
10385 00:59:50.436825 Parsing kernel messages
10386 00:59:50.437104 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10387 00:59:50.437602 [login-action] Waiting for messages, (timeout 00:03:37)
10388 00:59:50.453877 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10389 00:59:50.457086 [ 0.000000] random: crng init done
10390 00:59:50.464453 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10391 00:59:50.464965 [ 0.000000] efi: UEFI not found.
10392 00:59:50.474130 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10393 00:59:50.480978 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10394 00:59:50.491175 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10395 00:59:50.500344 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10396 00:59:50.507393 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10397 00:59:50.510503 [ 0.000000] printk: bootconsole [mtk8250] enabled
10398 00:59:50.519542 [ 0.000000] NUMA: No NUMA configuration found
10399 00:59:50.526021 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10400 00:59:50.532975 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10401 00:59:50.533398 [ 0.000000] Zone ranges:
10402 00:59:50.539583 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10403 00:59:50.542678 [ 0.000000] DMA32 empty
10404 00:59:50.549062 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10405 00:59:50.552261 [ 0.000000] Movable zone start for each node
10406 00:59:50.555697 [ 0.000000] Early memory node ranges
10407 00:59:50.562402 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10408 00:59:50.568866 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10409 00:59:50.575560 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10410 00:59:50.582307 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10411 00:59:50.589231 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10412 00:59:50.595601 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10413 00:59:50.651567 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10414 00:59:50.658459 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10415 00:59:50.665246 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10416 00:59:50.668205 [ 0.000000] psci: probing for conduit method from DT.
10417 00:59:50.674975 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10418 00:59:50.678395 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10419 00:59:50.684792 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10420 00:59:50.688105 [ 0.000000] psci: SMC Calling Convention v1.2
10421 00:59:50.694965 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10422 00:59:50.698517 [ 0.000000] Detected VIPT I-cache on CPU0
10423 00:59:50.704928 [ 0.000000] CPU features: detected: GIC system register CPU interface
10424 00:59:50.711593 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10425 00:59:50.718783 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10426 00:59:50.724591 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10427 00:59:50.731700 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10428 00:59:50.741355 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10429 00:59:50.744501 [ 0.000000] alternatives: applying boot alternatives
10430 00:59:50.751065 [ 0.000000] Fallback order for Node 0: 0
10431 00:59:50.758005 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10432 00:59:50.761100 [ 0.000000] Policy zone: Normal
10433 00:59:50.774069 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10434 00:59:50.784122 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10435 00:59:50.796042 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10436 00:59:50.806128 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10437 00:59:50.812456 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10438 00:59:50.816019 <6>[ 0.000000] software IO TLB: area num 8.
10439 00:59:50.874245 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10440 00:59:51.023281 <6>[ 0.000000] Memory: 7912140K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 440628K reserved, 32768K cma-reserved)
10441 00:59:51.029579 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10442 00:59:51.036041 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10443 00:59:51.039297 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10444 00:59:51.046618 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10445 00:59:51.052954 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10446 00:59:51.056227 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10447 00:59:51.066337 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10448 00:59:51.072382 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10449 00:59:51.079426 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10450 00:59:51.085754 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10451 00:59:51.088911 <6>[ 0.000000] GICv3: 608 SPIs implemented
10452 00:59:51.092128 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10453 00:59:51.099045 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10454 00:59:51.102323 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10455 00:59:51.108969 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10456 00:59:51.122364 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10457 00:59:51.132324 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10458 00:59:51.141897 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10459 00:59:51.149211 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10460 00:59:51.162754 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10461 00:59:51.169430 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10462 00:59:51.175840 <6>[ 0.009187] Console: colour dummy device 80x25
10463 00:59:51.185906 <6>[ 0.013917] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10464 00:59:51.192499 <6>[ 0.024359] pid_max: default: 32768 minimum: 301
10465 00:59:51.195701 <6>[ 0.029259] LSM: Security Framework initializing
10466 00:59:51.202675 <6>[ 0.034227] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10467 00:59:51.212251 <6>[ 0.042041] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10468 00:59:51.219309 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10469 00:59:51.225687 <6>[ 0.058943] cblist_init_generic: Setting shift to 3 and lim to 1.
10470 00:59:51.235397 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10471 00:59:51.242706 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 00:59:51.245744 <6>[ 0.079112] rcu: Hierarchical SRCU implementation.
10473 00:59:51.283776 <6>[ 0.084128] rcu: Max phase no-delay instances is 1000.
10474 00:59:51.283880 <6>[ 0.091145] EFI services will not be available.
10475 00:59:51.283946 <6>[ 0.096100] smp: Bringing up secondary CPUs ...
10476 00:59:51.284005 <6>[ 0.101178] Detected VIPT I-cache on CPU1
10477 00:59:51.284064 <6>[ 0.101248] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10478 00:59:51.284121 <6>[ 0.101278] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10479 00:59:51.286912 <6>[ 0.101618] Detected VIPT I-cache on CPU2
10480 00:59:51.293816 <6>[ 0.101667] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10481 00:59:51.299952 <6>[ 0.101683] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10482 00:59:51.306854 <6>[ 0.101945] Detected VIPT I-cache on CPU3
10483 00:59:51.313404 <6>[ 0.101992] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10484 00:59:51.320454 <6>[ 0.102006] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10485 00:59:51.323255 <6>[ 0.102315] CPU features: detected: Spectre-v4
10486 00:59:51.330089 <6>[ 0.102322] CPU features: detected: Spectre-BHB
10487 00:59:51.333045 <6>[ 0.102327] Detected PIPT I-cache on CPU4
10488 00:59:51.339917 <6>[ 0.102382] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10489 00:59:51.346817 <6>[ 0.102398] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10490 00:59:51.353130 <6>[ 0.102690] Detected PIPT I-cache on CPU5
10491 00:59:51.360053 <6>[ 0.102751] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10492 00:59:51.366315 <6>[ 0.102767] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10493 00:59:51.369503 <6>[ 0.103047] Detected PIPT I-cache on CPU6
10494 00:59:51.376456 <6>[ 0.103111] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10495 00:59:51.383279 <6>[ 0.103129] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10496 00:59:51.389463 <6>[ 0.103426] Detected PIPT I-cache on CPU7
10497 00:59:51.396171 <6>[ 0.103489] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10498 00:59:51.402883 <6>[ 0.103506] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10499 00:59:51.406514 <6>[ 0.103553] smp: Brought up 1 node, 8 CPUs
10500 00:59:51.412840 <6>[ 0.244932] SMP: Total of 8 processors activated.
10501 00:59:51.416254 <6>[ 0.249853] CPU features: detected: 32-bit EL0 Support
10502 00:59:51.426245 <6>[ 0.255216] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10503 00:59:51.432801 <6>[ 0.264070] CPU features: detected: Common not Private translations
10504 00:59:51.436069 <6>[ 0.270586] CPU features: detected: CRC32 instructions
10505 00:59:51.442737 <6>[ 0.275937] CPU features: detected: RCpc load-acquire (LDAPR)
10506 00:59:51.449226 <6>[ 0.281897] CPU features: detected: LSE atomic instructions
10507 00:59:51.455988 <6>[ 0.287687] CPU features: detected: Privileged Access Never
10508 00:59:51.459681 <6>[ 0.293503] CPU features: detected: RAS Extension Support
10509 00:59:51.469173 <6>[ 0.299146] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10510 00:59:51.472890 <6>[ 0.306367] CPU: All CPU(s) started at EL2
10511 00:59:51.479064 <6>[ 0.310683] alternatives: applying system-wide alternatives
10512 00:59:51.488063 <6>[ 0.321394] devtmpfs: initialized
10513 00:59:51.503390 <6>[ 0.330250] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10514 00:59:51.510503 <6>[ 0.340215] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10515 00:59:51.516782 <6>[ 0.348437] pinctrl core: initialized pinctrl subsystem
10516 00:59:51.519903 <6>[ 0.355080] DMI not present or invalid.
10517 00:59:51.526918 <6>[ 0.359488] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10518 00:59:51.536400 <6>[ 0.366357] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10519 00:59:51.542900 <6>[ 0.373942] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10520 00:59:51.553109 <6>[ 0.382173] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10521 00:59:51.556430 <6>[ 0.390415] audit: initializing netlink subsys (disabled)
10522 00:59:51.566177 <5>[ 0.396110] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10523 00:59:51.572701 <6>[ 0.396801] thermal_sys: Registered thermal governor 'step_wise'
10524 00:59:51.579215 <6>[ 0.404077] thermal_sys: Registered thermal governor 'power_allocator'
10525 00:59:51.583059 <6>[ 0.410335] cpuidle: using governor menu
10526 00:59:51.589803 <6>[ 0.421297] NET: Registered PF_QIPCRTR protocol family
10527 00:59:51.596239 <6>[ 0.426772] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10528 00:59:51.602887 <6>[ 0.433877] ASID allocator initialised with 32768 entries
10529 00:59:51.605958 <6>[ 0.440432] Serial: AMBA PL011 UART driver
10530 00:59:51.616155 <4>[ 0.449189] Trying to register duplicate clock ID: 134
10531 00:59:51.669858 <6>[ 0.506553] KASLR enabled
10532 00:59:51.684197 <6>[ 0.514330] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10533 00:59:51.690954 <6>[ 0.521344] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10534 00:59:51.697413 <6>[ 0.527833] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10535 00:59:51.704531 <6>[ 0.534838] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10536 00:59:51.711195 <6>[ 0.541325] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10537 00:59:51.717228 <6>[ 0.548330] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10538 00:59:51.723891 <6>[ 0.554814] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10539 00:59:51.730515 <6>[ 0.561819] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10540 00:59:51.733685 <6>[ 0.569331] ACPI: Interpreter disabled.
10541 00:59:51.742668 <6>[ 0.575732] iommu: Default domain type: Translated
10542 00:59:51.748876 <6>[ 0.580843] iommu: DMA domain TLB invalidation policy: strict mode
10543 00:59:51.752465 <5>[ 0.587501] SCSI subsystem initialized
10544 00:59:51.758836 <6>[ 0.591667] usbcore: registered new interface driver usbfs
10545 00:59:51.765802 <6>[ 0.597398] usbcore: registered new interface driver hub
10546 00:59:51.768664 <6>[ 0.602948] usbcore: registered new device driver usb
10547 00:59:51.775729 <6>[ 0.609046] pps_core: LinuxPPS API ver. 1 registered
10548 00:59:51.785713 <6>[ 0.614241] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10549 00:59:51.788885 <6>[ 0.623591] PTP clock support registered
10550 00:59:51.791855 <6>[ 0.627833] EDAC MC: Ver: 3.0.0
10551 00:59:51.799482 <6>[ 0.632993] FPGA manager framework
10552 00:59:51.803173 <6>[ 0.636671] Advanced Linux Sound Architecture Driver Initialized.
10553 00:59:51.806788 <6>[ 0.643405] vgaarb: loaded
10554 00:59:51.813512 <6>[ 0.646557] clocksource: Switched to clocksource arch_sys_counter
10555 00:59:51.819808 <5>[ 0.652995] VFS: Disk quotas dquot_6.6.0
10556 00:59:51.826817 <6>[ 0.657179] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10557 00:59:51.829962 <6>[ 0.664366] pnp: PnP ACPI: disabled
10558 00:59:51.837892 <6>[ 0.671057] NET: Registered PF_INET protocol family
10559 00:59:51.844269 <6>[ 0.676336] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10560 00:59:51.858752 <6>[ 0.688633] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10561 00:59:51.868237 <6>[ 0.697447] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10562 00:59:51.875064 <6>[ 0.705418] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10563 00:59:51.881714 <6>[ 0.714118] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10564 00:59:51.894239 <6>[ 0.723859] TCP: Hash tables configured (established 65536 bind 65536)
10565 00:59:51.900729 <6>[ 0.730719] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10566 00:59:51.907124 <6>[ 0.737917] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10567 00:59:51.913819 <6>[ 0.745617] NET: Registered PF_UNIX/PF_LOCAL protocol family
10568 00:59:51.921082 <6>[ 0.751787] RPC: Registered named UNIX socket transport module.
10569 00:59:51.924362 <6>[ 0.757941] RPC: Registered udp transport module.
10570 00:59:51.930630 <6>[ 0.762871] RPC: Registered tcp transport module.
10571 00:59:51.937695 <6>[ 0.767803] RPC: Registered tcp NFSv4.1 backchannel transport module.
10572 00:59:51.940806 <6>[ 0.774471] PCI: CLS 0 bytes, default 64
10573 00:59:51.944109 <6>[ 0.778870] Unpacking initramfs...
10574 00:59:51.961615 <6>[ 0.791183] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10575 00:59:51.971808 <6>[ 0.799841] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10576 00:59:51.975200 <6>[ 0.808703] kvm [1]: IPA Size Limit: 40 bits
10577 00:59:51.981452 <6>[ 0.813232] kvm [1]: GICv3: no GICV resource entry
10578 00:59:51.984845 <6>[ 0.818253] kvm [1]: disabling GICv2 emulation
10579 00:59:51.991162 <6>[ 0.822941] kvm [1]: GIC system register CPU interface enabled
10580 00:59:51.995279 <6>[ 0.829108] kvm [1]: vgic interrupt IRQ18
10581 00:59:52.001923 <6>[ 0.833467] kvm [1]: VHE mode initialized successfully
10582 00:59:52.007703 <5>[ 0.839967] Initialise system trusted keyrings
10583 00:59:52.014193 <6>[ 0.844772] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10584 00:59:52.022174 <6>[ 0.854789] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10585 00:59:52.028837 <5>[ 0.861140] NFS: Registering the id_resolver key type
10586 00:59:52.031508 <5>[ 0.866445] Key type id_resolver registered
10587 00:59:52.038570 <5>[ 0.870860] Key type id_legacy registered
10588 00:59:52.045414 <6>[ 0.875135] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10589 00:59:52.051940 <6>[ 0.882054] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10590 00:59:52.058183 <6>[ 0.889767] 9p: Installing v9fs 9p2000 file system support
10591 00:59:52.095046 <5>[ 0.927973] Key type asymmetric registered
10592 00:59:52.098320 <5>[ 0.932302] Asymmetric key parser 'x509' registered
10593 00:59:52.108397 <6>[ 0.937444] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10594 00:59:52.111566 <6>[ 0.945076] io scheduler mq-deadline registered
10595 00:59:52.115036 <6>[ 0.949858] io scheduler kyber registered
10596 00:59:52.133559 <6>[ 0.966766] EINJ: ACPI disabled.
10597 00:59:52.165788 <4>[ 0.992005] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 00:59:52.175739 <4>[ 1.002634] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 00:59:52.189969 <6>[ 1.023362] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10600 00:59:52.198373 <6>[ 1.031369] printk: console [ttyS0] disabled
10601 00:59:52.226031 <6>[ 1.056013] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10602 00:59:52.233070 <6>[ 1.065486] printk: console [ttyS0] enabled
10603 00:59:52.236084 <6>[ 1.065486] printk: console [ttyS0] enabled
10604 00:59:52.242927 <6>[ 1.074381] printk: bootconsole [mtk8250] disabled
10605 00:59:52.246029 <6>[ 1.074381] printk: bootconsole [mtk8250] disabled
10606 00:59:52.252450 <6>[ 1.085614] SuperH (H)SCI(F) driver initialized
10607 00:59:52.256366 <6>[ 1.090914] msm_serial: driver initialized
10608 00:59:52.270296 <6>[ 1.099805] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10609 00:59:52.280165 <6>[ 1.108353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10610 00:59:52.286568 <6>[ 1.116895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10611 00:59:52.296659 <6>[ 1.125524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10612 00:59:52.303365 <6>[ 1.134231] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10613 00:59:52.313303 <6>[ 1.142952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10614 00:59:52.323103 <6>[ 1.151493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10615 00:59:52.330058 <6>[ 1.160297] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10616 00:59:52.340059 <6>[ 1.168842] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10617 00:59:52.351217 <6>[ 1.184440] loop: module loaded
10618 00:59:52.358108 <6>[ 1.190430] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10619 00:59:52.380549 <4>[ 1.213237] mtk-pmic-keys: Failed to locate of_node [id: -1]
10620 00:59:52.387266 <6>[ 1.220291] megasas: 07.719.03.00-rc1
10621 00:59:52.397273 <6>[ 1.230030] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10622 00:59:52.405326 <6>[ 1.237942] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10623 00:59:52.421349 <6>[ 1.254423] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10624 00:59:52.477136 <6>[ 1.303792] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10625 00:59:54.348321 <6>[ 3.181213] Freeing initrd memory: 55112K
10626 00:59:54.358093 <6>[ 3.191488] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10627 00:59:54.369544 <6>[ 3.202435] tun: Universal TUN/TAP device driver, 1.6
10628 00:59:54.372667 <6>[ 3.208493] thunder_xcv, ver 1.0
10629 00:59:54.375622 <6>[ 3.211999] thunder_bgx, ver 1.0
10630 00:59:54.378922 <6>[ 3.215494] nicpf, ver 1.0
10631 00:59:54.389607 <6>[ 3.219494] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10632 00:59:54.392695 <6>[ 3.226970] hns3: Copyright (c) 2017 Huawei Corporation.
10633 00:59:54.399617 <6>[ 3.232555] hclge is initializing
10634 00:59:54.402746 <6>[ 3.236133] e1000: Intel(R) PRO/1000 Network Driver
10635 00:59:54.409871 <6>[ 3.241262] e1000: Copyright (c) 1999-2006 Intel Corporation.
10636 00:59:54.413167 <6>[ 3.247273] e1000e: Intel(R) PRO/1000 Network Driver
10637 00:59:54.419358 <6>[ 3.252489] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10638 00:59:54.426288 <6>[ 3.258677] igb: Intel(R) Gigabit Ethernet Network Driver
10639 00:59:54.432638 <6>[ 3.264327] igb: Copyright (c) 2007-2014 Intel Corporation.
10640 00:59:54.439275 <6>[ 3.270163] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10641 00:59:54.445922 <6>[ 3.276681] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10642 00:59:54.449091 <6>[ 3.283139] sky2: driver version 1.30
10643 00:59:54.455606 <6>[ 3.288122] VFIO - User Level meta-driver version: 0.3
10644 00:59:54.463237 <6>[ 3.296330] usbcore: registered new interface driver usb-storage
10645 00:59:54.470121 <6>[ 3.302773] usbcore: registered new device driver onboard-usb-hub
10646 00:59:54.478587 <6>[ 3.311897] mt6397-rtc mt6359-rtc: registered as rtc0
10647 00:59:54.488707 <6>[ 3.317366] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T00:57:15 UTC (1705625835)
10648 00:59:54.492114 <6>[ 3.326930] i2c_dev: i2c /dev entries driver
10649 00:59:54.508444 <6>[ 3.338576] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10650 00:59:54.528157 <6>[ 3.361566] cpu cpu0: EM: created perf domain
10651 00:59:54.531351 <6>[ 3.366484] cpu cpu4: EM: created perf domain
10652 00:59:54.539238 <6>[ 3.372071] sdhci: Secure Digital Host Controller Interface driver
10653 00:59:54.545642 <6>[ 3.378504] sdhci: Copyright(c) Pierre Ossman
10654 00:59:54.552442 <6>[ 3.383464] Synopsys Designware Multimedia Card Interface Driver
10655 00:59:54.558776 <6>[ 3.390097] sdhci-pltfm: SDHCI platform and OF driver helper
10656 00:59:54.561911 <6>[ 3.390127] mmc0: CQHCI version 5.10
10657 00:59:54.569005 <6>[ 3.400525] ledtrig-cpu: registered to indicate activity on CPUs
10658 00:59:54.575574 <6>[ 3.407609] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10659 00:59:54.581946 <6>[ 3.414665] usbcore: registered new interface driver usbhid
10660 00:59:54.584997 <6>[ 3.420486] usbhid: USB HID core driver
10661 00:59:54.595270 <6>[ 3.424663] spi_master spi0: will run message pump with realtime priority
10662 00:59:54.635838 <6>[ 3.462339] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10663 00:59:54.654256 <6>[ 3.477333] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10664 00:59:54.661454 <6>[ 3.492691] cros-ec-spi spi0.0: Chrome EC device registered
10665 00:59:54.665074 <6>[ 3.498738] mmc0: Command Queue Engine enabled
10666 00:59:54.671400 <6>[ 3.503472] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10667 00:59:54.677811 <6>[ 3.510943] mmcblk0: mmc0:0001 DA4128 116 GiB
10668 00:59:54.687726 <6>[ 3.520886] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10669 00:59:54.695029 <6>[ 3.528326] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10670 00:59:54.704980 <6>[ 3.531762] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10671 00:59:54.708439 <6>[ 3.534201] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10672 00:59:54.714792 <6>[ 3.544084] NET: Registered PF_PACKET protocol family
10673 00:59:54.721813 <6>[ 3.548776] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10674 00:59:54.724986 <6>[ 3.553448] 9pnet: Installing 9P2000 support
10675 00:59:54.731710 <5>[ 3.564459] Key type dns_resolver registered
10676 00:59:54.734649 <6>[ 3.569444] registered taskstats version 1
10677 00:59:54.741179 <5>[ 3.573819] Loading compiled-in X.509 certificates
10678 00:59:54.770473 <4>[ 3.597060] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10679 00:59:54.780271 <4>[ 3.607774] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10680 00:59:54.787323 <3>[ 3.618304] debugfs: File 'uA_load' in directory '/' already present!
10681 00:59:54.793660 <3>[ 3.625071] debugfs: File 'min_uV' in directory '/' already present!
10682 00:59:54.800399 <3>[ 3.631692] debugfs: File 'max_uV' in directory '/' already present!
10683 00:59:54.807198 <3>[ 3.638305] debugfs: File 'constraint_flags' in directory '/' already present!
10684 00:59:54.817835 <3>[ 3.648056] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10685 00:59:54.827236 <6>[ 3.660364] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10686 00:59:54.833602 <6>[ 3.667195] xhci-mtk 11200000.usb: xHCI Host Controller
10687 00:59:54.840456 <6>[ 3.672707] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10688 00:59:54.850556 <6>[ 3.680572] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10689 00:59:54.857261 <6>[ 3.690001] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10690 00:59:54.864146 <6>[ 3.696077] xhci-mtk 11200000.usb: xHCI Host Controller
10691 00:59:54.870263 <6>[ 3.701556] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10692 00:59:54.877033 <6>[ 3.709202] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10693 00:59:54.883664 <6>[ 3.716929] hub 1-0:1.0: USB hub found
10694 00:59:54.887079 <6>[ 3.720949] hub 1-0:1.0: 1 port detected
10695 00:59:54.893646 <6>[ 3.725240] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10696 00:59:54.900349 <6>[ 3.733807] hub 2-0:1.0: USB hub found
10697 00:59:54.903745 <6>[ 3.737825] hub 2-0:1.0: 1 port detected
10698 00:59:54.911560 <6>[ 3.745007] mtk-msdc 11f70000.mmc: Got CD GPIO
10699 00:59:54.923652 <6>[ 3.753323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10700 00:59:54.930003 <6>[ 3.761373] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10701 00:59:54.939867 <4>[ 3.769298] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10702 00:59:54.949975 <6>[ 3.778840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10703 00:59:54.956857 <6>[ 3.786917] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10704 00:59:54.963487 <6>[ 3.795070] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10705 00:59:54.973420 <6>[ 3.803017] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10706 00:59:54.979697 <6>[ 3.810836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10707 00:59:54.989762 <6>[ 3.818654] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10708 00:59:54.999806 <6>[ 3.829050] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10709 00:59:55.006505 <6>[ 3.837449] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10710 00:59:55.016198 <6>[ 3.845791] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10711 00:59:55.022942 <6>[ 3.854130] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10712 00:59:55.032535 <6>[ 3.862469] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10713 00:59:55.039223 <6>[ 3.870808] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10714 00:59:55.049291 <6>[ 3.879149] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10715 00:59:55.059102 <6>[ 3.887488] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10716 00:59:55.065950 <6>[ 3.895827] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10717 00:59:55.075716 <6>[ 3.904169] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10718 00:59:55.082045 <6>[ 3.912509] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10719 00:59:55.092168 <6>[ 3.920847] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10720 00:59:55.099087 <6>[ 3.929185] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10721 00:59:55.108579 <6>[ 3.937523] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10722 00:59:55.115407 <6>[ 3.945862] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10723 00:59:55.121900 <6>[ 3.954634] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10724 00:59:55.128413 <6>[ 3.961619] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10725 00:59:55.135290 <6>[ 3.968387] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10726 00:59:55.145404 <6>[ 3.975143] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10727 00:59:55.151654 <6>[ 3.982079] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10728 00:59:55.158599 <6>[ 3.988939] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10729 00:59:55.168513 <6>[ 3.998067] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10730 00:59:55.178301 <6>[ 4.007187] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10731 00:59:55.188354 <6>[ 4.016480] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10732 00:59:55.197932 <6>[ 4.025946] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10733 00:59:55.204178 <6>[ 4.035413] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10734 00:59:55.214674 <6>[ 4.044549] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10735 00:59:55.224225 <6>[ 4.054014] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10736 00:59:55.234191 <6>[ 4.063132] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10737 00:59:55.244713 <6>[ 4.072426] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10738 00:59:55.255010 <6>[ 4.082585] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10739 00:59:55.264072 <6>[ 4.094185] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10740 00:59:55.292581 <6>[ 4.123124] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10741 00:59:55.321094 <6>[ 4.154250] hub 2-1:1.0: USB hub found
10742 00:59:55.324337 <6>[ 4.158696] hub 2-1:1.0: 3 ports detected
10743 00:59:55.332554 <6>[ 4.166048] hub 2-1:1.0: USB hub found
10744 00:59:55.335996 <6>[ 4.170403] hub 2-1:1.0: 3 ports detected
10745 00:59:55.444931 <6>[ 4.274833] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10746 00:59:55.598801 <6>[ 4.432270] hub 1-1:1.0: USB hub found
10747 00:59:55.602090 <6>[ 4.436770] hub 1-1:1.0: 4 ports detected
10748 00:59:55.611788 <6>[ 4.445319] hub 1-1:1.0: USB hub found
10749 00:59:55.615576 <6>[ 4.449645] hub 1-1:1.0: 4 ports detected
10750 00:59:55.685409 <6>[ 4.515051] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10751 00:59:55.936604 <6>[ 4.766878] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10752 00:59:56.069424 <6>[ 4.902863] hub 1-1.4:1.0: USB hub found
10753 00:59:56.072517 <6>[ 4.907544] hub 1-1.4:1.0: 2 ports detected
10754 00:59:56.082439 <6>[ 4.915861] hub 1-1.4:1.0: USB hub found
10755 00:59:56.085984 <6>[ 4.920466] hub 1-1.4:1.0: 2 ports detected
10756 00:59:56.384546 <6>[ 5.214857] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10757 00:59:56.576563 <6>[ 5.406875] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10758 01:00:07.561389 <6>[ 16.399888] ALSA device list:
10759 01:00:07.568138 <6>[ 16.403175] No soundcards found.
10760 01:00:07.576009 <6>[ 16.411151] Freeing unused kernel memory: 8448K
10761 01:00:07.579400 <6>[ 16.416136] Run /init as init process
10762 01:00:07.628608 <6>[ 16.463758] NET: Registered PF_INET6 protocol family
10763 01:00:07.635425 <6>[ 16.470086] Segment Routing with IPv6
10764 01:00:07.638431 <6>[ 16.474042] In-situ OAM (IOAM) with IPv6
10765 01:00:07.673615 <30>[ 16.488875] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10766 01:00:07.676886 <30>[ 16.512614] systemd[1]: Detected architecture arm64.
10767 01:00:07.676974
10768 01:00:07.683395 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10769 01:00:07.683476
10770 01:00:07.695471 <30>[ 16.530790] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10771 01:00:07.866579 <30>[ 16.698449] systemd[1]: Queued start job for default target Graphical Interface.
10772 01:00:07.904738 <30>[ 16.739713] systemd[1]: Created slice system-getty.slice.
10773 01:00:07.911388 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10774 01:00:07.928151 <30>[ 16.763441] systemd[1]: Created slice system-modprobe.slice.
10775 01:00:07.934942 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10776 01:00:07.952744 <30>[ 16.788129] systemd[1]: Created slice system-serial\x2dgetty.slice.
10777 01:00:07.963111 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10778 01:00:07.976191 <30>[ 16.811300] systemd[1]: Created slice User and Session Slice.
10779 01:00:07.982747 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10780 01:00:08.003984 <30>[ 16.835481] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10781 01:00:08.013941 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10782 01:00:08.030993 <30>[ 16.862980] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10783 01:00:08.037711 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10784 01:00:08.058473 <30>[ 16.886947] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10785 01:00:08.065412 <30>[ 16.899103] systemd[1]: Reached target Local Encrypted Volumes.
10786 01:00:08.071399 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10787 01:00:08.088031 <30>[ 16.923349] systemd[1]: Reached target Paths.
10788 01:00:08.091592 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10789 01:00:08.107901 <30>[ 16.942844] systemd[1]: Reached target Remote File Systems.
10790 01:00:08.114044 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10791 01:00:08.132469 <30>[ 16.967204] systemd[1]: Reached target Slices.
10792 01:00:08.138751 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10793 01:00:08.151695 <30>[ 16.986867] systemd[1]: Reached target Swap.
10794 01:00:08.154755 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10795 01:00:08.175519 <30>[ 17.007352] systemd[1]: Listening on initctl Compatibility Named Pipe.
10796 01:00:08.182171 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10797 01:00:08.188838 <30>[ 17.022503] systemd[1]: Listening on Journal Audit Socket.
10798 01:00:08.195190 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10799 01:00:08.208150 <30>[ 17.043330] systemd[1]: Listening on Journal Socket (/dev/log).
10800 01:00:08.214820 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10801 01:00:08.232821 <30>[ 17.068090] systemd[1]: Listening on Journal Socket.
10802 01:00:08.239470 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10803 01:00:08.252713 <30>[ 17.087405] systemd[1]: Listening on udev Control Socket.
10804 01:00:08.258950 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10805 01:00:08.276930 <30>[ 17.111878] systemd[1]: Listening on udev Kernel Socket.
10806 01:00:08.283129 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10807 01:00:08.323935 <30>[ 17.158968] systemd[1]: Mounting Huge Pages File System...
10808 01:00:08.330302 Mounting [0;1;39mHuge Pages File System[0m...
10809 01:00:08.347231 <30>[ 17.182447] systemd[1]: Mounting POSIX Message Queue File System...
10810 01:00:08.354237 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10811 01:00:08.376022 <30>[ 17.210886] systemd[1]: Mounting Kernel Debug File System...
10812 01:00:08.382392 Mounting [0;1;39mKernel Debug File System[0m...
10813 01:00:08.399013 <30>[ 17.231008] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10814 01:00:08.412271 <30>[ 17.244078] systemd[1]: Starting Create list of static device nodes for the current kernel...
10815 01:00:08.419026 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10816 01:00:08.439925 <30>[ 17.275410] systemd[1]: Starting Load Kernel Module configfs...
10817 01:00:08.447465 Starting [0;1;39mLoad Kernel Module configfs[0m...
10818 01:00:08.484115 <30>[ 17.319252] systemd[1]: Starting Load Kernel Module drm...
10819 01:00:08.490645 Starting [0;1;39mLoad Kernel Module drm[0m...
10820 01:00:08.506766 <30>[ 17.338943] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10821 01:00:08.521508 <30>[ 17.356614] systemd[1]: Starting Journal Service...
10822 01:00:08.524698 Starting [0;1;39mJournal Service[0m...
10823 01:00:08.542306 <30>[ 17.377592] systemd[1]: Starting Load Kernel Modules...
10824 01:00:08.548748 Starting [0;1;39mLoad Kernel Modules[0m...
10825 01:00:08.570537 <30>[ 17.402393] systemd[1]: Starting Remount Root and Kernel File Systems...
10826 01:00:08.577423 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10827 01:00:08.594455 <30>[ 17.429737] systemd[1]: Starting Coldplug All udev Devices...
10828 01:00:08.601497 Starting [0;1;39mColdplug All udev Devices[0m...
10829 01:00:08.623094 <30>[ 17.458160] systemd[1]: Started Journal Service.
10830 01:00:08.629303 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10831 01:00:08.646730 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10832 01:00:08.670516 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10833 01:00:08.692244 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10834 01:00:08.711726 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10835 01:00:08.734915 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10836 01:00:08.758726 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10837 01:00:08.781359 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10838 01:00:08.805627 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10839 01:00:08.824136 See 'systemctl status systemd-remount-fs.service' for details.
10840 01:00:08.870062 Mounting [0;1;39mKernel Configuration File System[0m...
10841 01:00:08.892177 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10842 01:00:08.915255 <46>[ 17.746800] systemd-journald[177]: Received client request to flush runtime journal.
10843 01:00:08.921310 Starting [0;1;39mLoad/Save Random Seed[0m...
10844 01:00:08.945619 Starting [0;1;39mApply Kernel Variables[0m...
10845 01:00:08.965104 Starting [0;1;39mCreate System Users[0m...
10846 01:00:08.989033 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10847 01:00:09.008612 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10848 01:00:09.032653 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10849 01:00:09.049441 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10850 01:00:09.065427 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10851 01:00:09.081131 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10852 01:00:09.119941 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10853 01:00:09.142349 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10854 01:00:09.159916 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10855 01:00:09.180024 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10856 01:00:09.212683 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10857 01:00:09.239084 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10858 01:00:09.262739 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10859 01:00:09.282415 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10860 01:00:09.325789 Starting [0;1;39mNetwork Time Synchronization[0m...
10861 01:00:09.347375 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10862 01:00:09.409820 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10863 01:00:09.429080 <6>[ 18.260796] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10864 01:00:09.442139 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10865 01:00:09.450297 <6>[ 18.285524] remoteproc remoteproc0: scp is available
10866 01:00:09.456672 <6>[ 18.290636] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10867 01:00:09.463608 <6>[ 18.291001] remoteproc remoteproc0: powering up scp
10868 01:00:09.473441 <6>[ 18.298513] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10869 01:00:09.479952 <6>[ 18.305956] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10870 01:00:09.490034 <6>[ 18.312272] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10871 01:00:09.493111 <6>[ 18.321670] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10872 01:00:09.503116 <3>[ 18.334967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 01:00:09.506848 <6>[ 18.338530] mc: Linux media interface: v0.10
10874 01:00:09.516297 <3>[ 18.343197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 01:00:09.523306 <3>[ 18.355806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 01:00:09.532861 <3>[ 18.355991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 01:00:09.539621 <4>[ 18.357408] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10878 01:00:09.546204 <4>[ 18.359623] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10879 01:00:09.552714 [[0;32m OK [<6>[ 18.384407] usbcore: registered new device driver r8152-cfgselector
10880 01:00:09.563235 0m] Found device<3>[ 18.386753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 01:00:09.570006 [0;1;39m/dev/t<6>[ 18.395914] videodev: Linux video capture interface: v2.00
10882 01:00:09.572772 tyS0[0m.
10883 01:00:09.579557 <3>[ 18.404352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 01:00:09.589626 <3>[ 18.420902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 01:00:09.596833 <6>[ 18.421062] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10886 01:00:09.606308 <3>[ 18.429539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 01:00:09.612952 <3>[ 18.445356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 01:00:09.619303 <6>[ 18.452028] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10889 01:00:09.628965 <3>[ 18.453569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 01:00:09.635911 <6>[ 18.460919] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10891 01:00:09.642262 <6>[ 18.461464] pci_bus 0000:00: root bus resource [bus 00-ff]
10892 01:00:09.649209 <6>[ 18.461473] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10893 01:00:09.659088 <6>[ 18.461476] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10894 01:00:09.665821 <6>[ 18.461518] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10895 01:00:09.672441 <6>[ 18.461533] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10896 01:00:09.675719 <6>[ 18.461618] pci 0000:00:00.0: supports D1 D2
10897 01:00:09.682660 <6>[ 18.461620] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10898 01:00:09.692153 <6>[ 18.463520] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10899 01:00:09.698787 <6>[ 18.463671] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10900 01:00:09.705551 <6>[ 18.463696] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10901 01:00:09.712037 <6>[ 18.463714] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10902 01:00:09.722312 <6>[ 18.463729] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10903 01:00:09.725714 <6>[ 18.463844] pci 0000:01:00.0: supports D1 D2
10904 01:00:09.732552 <6>[ 18.463848] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10905 01:00:09.740073 <6>[ 18.468427] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10906 01:00:09.747065 <6>[ 18.468442] remoteproc remoteproc0: remote processor scp is now up
10907 01:00:09.754027 <3>[ 18.468467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 01:00:09.763836 <3>[ 18.468473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 01:00:09.770275 <3>[ 18.473218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 01:00:09.780531 <6>[ 18.474721] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10911 01:00:09.788368 <6>[ 18.474752] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10912 01:00:09.795345 <6>[ 18.474756] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10913 01:00:09.801506 <6>[ 18.474765] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10914 01:00:09.811374 <6>[ 18.474778] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10915 01:00:09.819046 <6>[ 18.474791] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10916 01:00:09.825686 <6>[ 18.474802] pci 0000:00:00.0: PCI bridge to [bus 01]
10917 01:00:09.832403 <6>[ 18.474808] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10918 01:00:09.838737 <6>[ 18.474960] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10919 01:00:09.845298 <6>[ 18.475458] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10920 01:00:09.849315 <6>[ 18.475653] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10921 01:00:09.859671 <6>[ 18.479592] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10922 01:00:09.869480 <4>[ 18.481845] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10923 01:00:09.872460 <4>[ 18.481845] Fallback method does not support PEC.
10924 01:00:09.882645 <3>[ 18.482350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 01:00:09.889841 <3>[ 18.482356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 01:00:09.896408 <3>[ 18.482362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 01:00:09.906315 <3>[ 18.482366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 01:00:09.913097 <3>[ 18.482396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 01:00:09.923098 <6>[ 18.489817] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10930 01:00:09.930646 <6>[ 18.491108] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10931 01:00:09.939944 <6>[ 18.491580] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10932 01:00:09.950217 <6>[ 18.491857] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10933 01:00:09.959954 <4>[ 18.513857] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10934 01:00:09.966613 <5>[ 18.515838] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10935 01:00:09.973314 <5>[ 18.540943] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10936 01:00:09.980137 <4>[ 18.546143] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10937 01:00:09.990082 <6>[ 18.548069] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10938 01:00:09.999569 <6>[ 18.550860] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10939 01:00:10.009835 <6>[ 18.551256] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10940 01:00:10.016101 <6>[ 18.551769] usbcore: registered new interface driver uvcvideo
10941 01:00:10.022770 <5>[ 18.559338] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10942 01:00:10.027099 <6>[ 18.559980] Bluetooth: Core ver 2.22
10943 01:00:10.033374 <6>[ 18.560057] NET: Registered PF_BLUETOOTH protocol family
10944 01:00:10.039835 <6>[ 18.560059] Bluetooth: HCI device and connection manager initialized
10945 01:00:10.043628 <6>[ 18.560078] Bluetooth: HCI socket layer initialized
10946 01:00:10.049992 <6>[ 18.560083] Bluetooth: L2CAP socket layer initialized
10947 01:00:10.056400 <6>[ 18.560090] Bluetooth: SCO socket layer initialized
10948 01:00:10.063272 <6>[ 18.567939] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10949 01:00:10.070025 <4>[ 18.572895] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10950 01:00:10.079963 <3>[ 18.576297] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 01:00:10.086357 <3>[ 18.578955] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10952 01:00:10.096426 <3>[ 18.588744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 01:00:10.099572 <6>[ 18.595693] cfg80211: failed to load regulatory.db
10954 01:00:10.106208 <6>[ 18.619968] usbcore: registered new interface driver btusb
10955 01:00:10.116185 <4>[ 18.620740] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10956 01:00:10.123252 <3>[ 18.620752] Bluetooth: hci0: Failed to load firmware file (-2)
10957 01:00:10.129804 <3>[ 18.620756] Bluetooth: hci0: Failed to set up firmware (-2)
10958 01:00:10.139225 <4>[ 18.620759] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10959 01:00:10.149098 <3>[ 18.627335] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 01:00:10.155944 <3>[ 18.628114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10961 01:00:10.162743 <6>[ 18.642886] r8152 2-1.3:1.0 eth0: v1.12.13
10962 01:00:10.169149 <3>[ 18.663667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 01:00:10.175518 <6>[ 18.664444] usbcore: registered new interface driver r8152
10964 01:00:10.182237 <6>[ 18.678082] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10965 01:00:10.192670 <3>[ 18.693589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 01:00:10.199029 <6>[ 18.700121] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10967 01:00:10.205379 <6>[ 18.700230] usbcore: registered new interface driver cdc_ether
10968 01:00:10.212613 <6>[ 18.713843] usbcore: registered new interface driver r8153_ecm
10969 01:00:10.218667 <3>[ 18.734778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 01:00:10.225813 <6>[ 18.738602] mt7921e 0000:01:00.0: ASIC revision: 79610010
10971 01:00:10.232415 <6>[ 18.753571] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10972 01:00:10.238514 <3>[ 18.767622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 01:00:10.249032 <6>[ 18.845813] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10974 01:00:10.249170 <6>[ 18.845813]
10975 01:00:10.258321 <3>[ 18.870301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 01:00:10.265177 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10977 01:00:10.280191 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10978 01:00:10.302897 [[0;32m OK [0m] Reached targ<6>[ 19.132879] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10979 01:00:10.305724 et [0;1;39mSystem Time Synchronized[0m.
10980 01:00:10.323706 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10981 01:00:10.363260 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10982 01:00:10.385251 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10983 01:00:10.433750 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10984 01:00:10.447549 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10985 01:00:10.467536 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10986 01:00:10.482646 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10987 01:00:10.495550 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10988 01:00:10.515346 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10989 01:00:10.527637 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10990 01:00:10.543673 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10991 01:00:10.580556 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10992 01:00:10.612501 Starting [0;1;39mUser Login Management[0m...
10993 01:00:10.632599 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10994 01:00:10.653549 Starting [0;1;39mPermit User Sessions[0m...
10995 01:00:10.668688 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10996 01:00:10.689353 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10997 01:00:10.708203 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10998 01:00:10.727736 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10999 01:00:10.743796 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11000 01:00:10.764276 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11001 01:00:10.772573 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11002 01:00:10.787767 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11003 01:00:10.848218 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11004 01:00:10.878932 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11005 01:00:10.924647
11006 01:00:10.924816
11007 01:00:10.927592 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11008 01:00:10.927693
11009 01:00:10.931286 debian-bullseye-arm64 login: root (automatic login)
11010 01:00:10.931369
11011 01:00:10.931433
11012 01:00:10.951667 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
11013 01:00:10.951805
11014 01:00:10.958870 The programs included with the Debian GNU/Linux system are free software;
11015 01:00:10.964868 the exact distribution terms for each program are described in the
11016 01:00:10.968638 individual files in /usr/share/doc/*/copyright.
11017 01:00:10.968730
11018 01:00:10.974871 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 01:00:10.978528 permitted by applicable law.
11020 01:00:10.978937 Matched prompt #10: / #
11022 01:00:10.979139 Setting prompt string to ['/ #']
11023 01:00:10.979229 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11025 01:00:10.979420 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11026 01:00:10.979505 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11027 01:00:10.979575 Setting prompt string to ['/ #']
11028 01:00:10.979636 Forcing a shell prompt, looking for ['/ #']
11030 01:00:11.029841 / #
11031 01:00:11.030021 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 01:00:11.030148 Waiting using forced prompt support (timeout 00:02:30)
11033 01:00:11.035021
11034 01:00:11.035312 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11035 01:00:11.035426 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11036 01:00:11.035537 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11037 01:00:11.035636 end: 2.2 depthcharge-retry (duration 00:01:43) [common]
11038 01:00:11.035739 end: 2 depthcharge-action (duration 00:01:43) [common]
11039 01:00:11.035844 start: 3 lava-test-retry (timeout 00:07:50) [common]
11040 01:00:11.035969 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11041 01:00:11.036078 Using namespace: common
11043 01:00:11.136453 / # #
11044 01:00:11.136612 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11045 01:00:11.141712 #
11046 01:00:11.141989 Using /lava-12571066
11048 01:00:11.242391 / # export SHELL=/bin/sh
11049 01:00:11.242615 <6>[ 19.989889] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11050 01:00:11.247660 export SHELL=/bin/sh
11052 01:00:11.348276 / # . /lava-12571066/environment
11053 01:00:11.353345 . /lava-12571066/environment
11055 01:00:11.453981 / # /lava-12571066/bin/lava-test-runner /lava-12571066/0
11056 01:00:11.454146 Test shell timeout: 10s (minimum of the action and connection timeout)
11057 01:00:11.458829 /lava-12571066/bin/lava-test-runner /lava-12571066/0
11058 01:00:11.485004 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 20.320147] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12571066_1.5.2.3.1>
11059 01:00:11.485337 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12571066_1.5.2.3.1
11060 01:00:11.485434 Starting test lava.0_igt-gpu-panfrost (12571066_1.5.2.3.1)
11061 01:00:11.485550 Skipping test definition patterns.
11062 01:00:11.488720 rost
11063 01:00:11.492133 + cd /lava-12571066/0/tests/0_igt-gpu-panfrost
11064 01:00:11.492230 + cat uuid
11065 01:00:11.494923 + UUID=12571066_1.5.2.3.1
11066 01:00:11.495012 + set +x
11067 01:00:11.505192 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11068 01:00:11.511938 <8>[ 20.345914] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11069 01:00:11.512247 Received signal: <TESTSET> START panfrost_gem_new
11070 01:00:11.512371 Starting test_set panfrost_gem_new
11071 01:00:11.528560 <14>[ 20.364321] [IGT] panfrost_gem_new: executing
11072 01:00:11.535775 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.371194] [IGT] panfrost_gem_new: exiting, ret=77
11073 01:00:11.538850 rch64) (Linux: 6.1.72-cip13 aarch64)
11074 01:00:11.549085 Test requirement not met i<8>[ 20.382246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11075 01:00:11.549344 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11077 01:00:11.555473 n function drm_open_driver, file ../lib/drmtest.c:621:
11078 01:00:11.555558 Test requirement: !(fd<0)
11079 01:00:11.561548 No known gpu found for chipset flags 0x32 (panfrost)
11080 01:00:11.565175 Last er<14>[ 20.401763] [IGT] panfrost_gem_new: executing
11081 01:00:11.575355 rno: 2, No such file or director<14>[ 20.409377] [IGT] panfrost_gem_new: exiting, ret=77
11082 01:00:11.575483 y
11083 01:00:11.578805 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11084 01:00:11.585418 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11086 01:00:11.588144 IGT-Version: 1.2<8>[ 20.420072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11087 01:00:11.591845 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11088 01:00:11.598212 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11089 01:00:11.604852 Test req<14>[ 20.439251] [IGT] panfrost_gem_new: executing
11090 01:00:11.604939 uirement: !(fd<0)
11091 01:00:11.611543 No known gpu <14>[ 20.446857] [IGT] panfrost_gem_new: exiting, ret=77
11092 01:00:11.615101 found for chipset flags 0x32 (panfrost)
11093 01:00:11.625023 Last errno: 2, No such <8>[ 20.457391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11094 01:00:11.625287 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11096 01:00:11.628215 file or directory
11097 01:00:11.631352 [1mSubtest g<8>[ 20.466843] <LAVA_SIGNAL_TESTSET STOP>
11098 01:00:11.631603 Received signal: <TESTSET> STOP
11099 01:00:11.631675 Closing test_set panfrost_gem_new
11100 01:00:11.635012 em-new-0: SKIP (0.000s)[0m
11101 01:00:11.641550 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11102 01:00:11.651566 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:6<8>[ 20.487269] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11103 01:00:11.652138 Received signal: <TESTSET> START panfrost_get_param
11104 01:00:11.652433 Starting test_set panfrost_get_param
11105 01:00:11.654897 21:
11106 01:00:11.655217 Test requirement: !(fd<0)
11107 01:00:11.661761 No known gpu found for chipset flags 0x32 (panfrost)
11108 01:00:11.664910 Last errno: 2, No such file or directory
11109 01:00:11.667669 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11110 01:00:11.674445 <14>[ 20.508954] [IGT] panfrost_get_param: executing
11111 01:00:11.681374 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.516038] [IGT] panfrost_get_param: exiting, ret=77
11112 01:00:11.684413 rch64) (Linux: 6.1.72-cip13 aarch64)
11113 01:00:11.694411 Test requirement not met i<8>[ 20.526612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11114 01:00:11.694664 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11116 01:00:11.697425 n function drm_open_driver, file ../lib/drmtest.c:621:
11117 01:00:11.700786 Test requirement: !(fd<0)
11118 01:00:11.707686 No known gpu found for chipset flags 0x32 (panfrost)
11119 01:00:11.710797 Last er<14>[ 20.546489] [IGT] panfrost_get_param: executing
11120 01:00:11.721258 rno: 2, No such file or director<14>[ 20.554024] [IGT] panfrost_get_param: exiting, ret=77
11121 01:00:11.721339 y
11122 01:00:11.724437 [1mSubtest base-params: SKIP (0.000s)[0m
11123 01:00:11.730939 IGT-Version: 1.27<8>[ 20.564972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11124 01:00:11.731191 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11126 01:00:11.737483 .1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11127 01:00:11.744545 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11128 01:00:11.751176 Test requ<14>[ 20.585407] [IGT] panfrost_get_param: executing
11129 01:00:11.751256 irement: !(fd<0)
11130 01:00:11.757431 No known gpu f<14>[ 20.592558] [IGT] panfrost_get_param: exiting, ret=77
11131 01:00:11.760744 ound for chipset flags 0x32 (panfrost)
11132 01:00:11.771189 Last errno: 2, No such f<8>[ 20.603909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11133 01:00:11.771509 ile or directory
11134 01:00:11.771988 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11136 01:00:11.777625 [1mSubtest ge<8>[ 20.613004] <LAVA_SIGNAL_TESTSET STOP>
11137 01:00:11.778170 Received signal: <TESTSET> STOP
11138 01:00:11.778434 Closing test_set panfrost_get_param
11139 01:00:11.781312 t-bad-param: SKIP (0.000s)[0m
11140 01:00:11.787918 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11141 01:00:11.794384 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11142 01:00:11.797529 Test requirement: !(fd<0)
11143 01:00:11.801268 No known gpu found for chipset flags 0x32 (panfrost)
11144 01:00:11.811042 Last errno: 2, No such file or director<8>[ 20.643285] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11145 01:00:11.811369 y
11146 01:00:11.811854 Received signal: <TESTSET> START panfrost_prime
11147 01:00:11.812118 Starting test_set panfrost_prime
11148 01:00:11.814063 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11149 01:00:11.835584 <14>[ 20.671082] [IGT] panfrost_prime: executing
11150 01:00:11.842536 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.678522] [IGT] panfrost_prime: exiting, ret=77
11151 01:00:11.845875 rch64) (Linux: 6.1.72-cip13 aarch64)
11152 01:00:11.859130 Test requirement not met in function drm_o<8>[ 20.689697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11153 01:00:11.859682 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11155 01:00:11.865397 pen_driver, file ../lib/drmtest.<8>[ 20.699638] <LAVA_SIGNAL_TESTSET STOP>
11156 01:00:11.865748 c:621:
11157 01:00:11.866280 Received signal: <TESTSET> STOP
11158 01:00:11.866557 Closing test_set panfrost_prime
11159 01:00:11.868957 Test requirement: !(fd<0)
11160 01:00:11.872416 No known gpu found for chipset flags 0x32 (panfrost)
11161 01:00:11.875558 Last errno: 2, No such file or directory
11162 01:00:11.885362 [1mSubtest gem-prime-import: SKIP (0.000s)[<8>[ 20.720020] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11163 01:00:11.885712 0m
11164 01:00:11.886224 Received signal: <TESTSET> START panfrost_submit
11165 01:00:11.886502 Starting test_set panfrost_submit
11166 01:00:11.905655 <14>[ 20.741100] [IGT] panfrost_submit: executing
11167 01:00:11.912399 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.747943] [IGT] panfrost_submit: exiting, ret=77
11168 01:00:11.915833 rch64) (Linux: 6.1.72-cip13 aarch64)
11169 01:00:11.925200 Test requirement not met i<8>[ 20.758967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11170 01:00:11.925459 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11172 01:00:11.932046 n function drm_open_driver, file ../lib/drmtest.c:621:
11173 01:00:11.932131 Test requirement: !(fd<0)
11174 01:00:11.939087 No known gpu found for chipset flags 0x32 (panfrost)
11175 01:00:11.941653 Last errno: 2, No such file or directory
11176 01:00:11.945555 [1mSubtest pan-submit: SKIP (0.000s)[0m
11177 01:00:11.952343 <14>[ 20.787654] [IGT] panfrost_submit: executing
11178 01:00:11.962335 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.795402] [IGT] panfrost_submit: exiting, ret=77
11179 01:00:11.962475 .1.72-cip13 aarch64)
11180 01:00:11.979137 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.809259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11181 01:00:11.979542 c:621:
11182 01:00:11.980187 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11184 01:00:11.982269 Test requirement: !(fd<0)
11185 01:00:11.985721 No known gpu found for chipset flags 0x32 (panfrost)
11186 01:00:11.989190 Last errno: 2, No such file or directory
11187 01:00:11.995788 [1mSubtest pan-submit-error-<14>[ 20.831223] [IGT] panfrost_submit: executing
11188 01:00:11.998999 no-jc: SKIP (0.000s)[0m
11189 01:00:12.005468 IGT-Ve<14>[ 20.838822] [IGT] panfrost_submit: exiting, ret=77
11190 01:00:12.009091 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11191 01:00:12.019072 Test requirement<8>[ 20.850273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11192 01:00:12.019785 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11194 01:00:12.025977 not met in function drm_open_driver, file ../lib/drmtest.c:621:
11195 01:00:12.028677 Test requirement: !(fd<0)
11196 01:00:12.032018 No known gpu found for chipset flags 0x32 (panfrost)
11197 01:00:12.038800 Last errno: 2<14>[ 20.872823] [IGT] panfrost_submit: executing
11198 01:00:12.042087 , No such file or directory
11199 01:00:12.045177 [1<14>[ 20.880568] [IGT] panfrost_submit: exiting, ret=77
11200 01:00:12.052140 mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11201 01:00:12.062149 IGT-V<8>[ 20.891846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11202 01:00:12.062771 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11204 01:00:12.065254 ersion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11205 01:00:12.078898 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621<14>[ 20.913185] [IGT] panfrost_submit: executing
11206 01:00:12.079276 :
11207 01:00:12.081971 Test requirement: !(fd<0)
11208 01:00:12.085041 No<14>[ 20.920031] [IGT] panfrost_submit: exiting, ret=77
11209 01:00:12.088280 known gpu found for chipset flags 0x32 (panfrost)
11210 01:00:12.098403 Last errno: <8>[ 20.931016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11211 01:00:12.099040 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11213 01:00:12.102096 2, No such file or directory
11214 01:00:12.108562 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11215 01:00:12.118239 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1<14>[ 20.952244] [IGT] panfrost_submit: executing
11216 01:00:12.118337 .72-cip13 aarch64)
11217 01:00:12.124572 Test require<14>[ 20.959499] [IGT] panfrost_submit: exiting, ret=77
11218 01:00:12.138025 ment not met in function drm_open_driver, file ../lib/drmtest.c:<8>[ 20.970519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11219 01:00:12.138137 621:
11220 01:00:12.138410 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11222 01:00:12.141548 Test requirement: !(fd<0)
11223 01:00:12.148015 No known gpu found for chipset flags 0x32 (panfrost)
11224 01:00:12.151345 Last errno: 2, No such file or directory
11225 01:00:12.154473 [1mSubtest pan<14>[ 20.991352] [IGT] panfrost_submit: executing
11226 01:00:12.164357 -submit-error-bad-requirements: <14>[ 20.998412] [IGT] panfrost_submit: exiting, ret=77
11227 01:00:12.164736 SKIP (0.000s)[0m
11228 01:00:12.178029 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<8>[ 21.009890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11229 01:00:12.178422 : 6.1.72-cip13 aarch64)
11230 01:00:12.179174 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11232 01:00:12.184787 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11233 01:00:12.187974 Test requirement: !(fd<0)
11234 01:00:12.194424 No known g<14>[ 21.029197] [IGT] panfrost_submit: executing
11235 01:00:12.201512 pu found for chipset flags 0x32 <14>[ 21.036068] [IGT] panfrost_submit: exiting, ret=77
11236 01:00:12.202160 (panfrost)
11237 01:00:12.207569 Last errno: 2, No such file or directory
11238 01:00:12.214238 [1mSubtes<8>[ 21.047155] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11239 01:00:12.214499 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11241 01:00:12.220612 t pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11242 01:00:12.224167 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11243 01:00:12.230399 Test requirement not m<14>[ 21.067094] [IGT] panfrost_submit: executing
11244 01:00:12.240535 et in function drm_open_driver, <14>[ 21.074362] [IGT] panfrost_submit: exiting, ret=77
11245 01:00:12.243681 file ../lib/drmtest.c:621:
11246 01:00:12.243763 Test requirement: !(fd<0)
11247 01:00:12.253811 No known <8>[ 21.085713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11248 01:00:12.254072 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11250 01:00:12.260224 gpu found for chipset flags 0x32<8>[ 21.095300] <LAVA_SIGNAL_TESTSET STOP>
11251 01:00:12.260348 (panfrost)
11252 01:00:12.260585 Received signal: <TESTSET> STOP
11253 01:00:12.260683 Closing test_set panfrost_submit
11254 01:00:12.267141 Las<8>[ 21.101394] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12571066_1.5.2.3.1>
11255 01:00:12.267393 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12571066_1.5.2.3.1
11256 01:00:12.267476 Ending use of test pattern.
11257 01:00:12.267539 Ending test lava.0_igt-gpu-panfrost (12571066_1.5.2.3.1), duration 0.78
11259 01:00:12.270184 t errno: 2, No such file or directory
11260 01:00:12.273667 [1mSubtest pan-reset: SKIP (0.000s)[0m
11261 01:00:12.280594 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11262 01:00:12.286715 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11263 01:00:12.290491 Test requirement: !(fd<0)
11264 01:00:12.296690 No known gpu found for chipset flags 0x32 (panfrost)
11265 01:00:12.300371 Last errno: 2, No such file or directory
11266 01:00:12.303470 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11267 01:00:12.309985 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11268 01:00:12.316981 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11269 01:00:12.320149 Test requirement: !(fd<0)
11270 01:00:12.323289 No known gpu found for chipset flags 0x32 (panfrost)
11271 01:00:12.326474 Last errno: 2, No such file or directory
11272 01:00:12.333228 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11273 01:00:12.333303 + set +x
11274 01:00:12.336846 <LAVA_TEST_RUNNER EXIT>
11275 01:00:12.337091 ok: lava_test_shell seems to have completed
11276 01:00:12.337414 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11277 01:00:12.337517 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11278 01:00:12.337605 end: 3 lava-test-retry (duration 00:00:01) [common]
11279 01:00:12.337693 start: 4 finalize (timeout 00:07:49) [common]
11280 01:00:12.337785 start: 4.1 power-off (timeout 00:00:30) [common]
11281 01:00:12.337935 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11282 01:00:12.414191 >> Command sent successfully.
11283 01:00:12.416597 Returned 0 in 0 seconds
11284 01:00:12.517068 end: 4.1 power-off (duration 00:00:00) [common]
11286 01:00:12.517397 start: 4.2 read-feedback (timeout 00:07:48) [common]
11287 01:00:12.517660 Listened to connection for namespace 'common' for up to 1s
11288 01:00:13.518579 Finalising connection for namespace 'common'
11289 01:00:13.518758 Disconnecting from shell: Finalise
11290 01:00:13.518851 / #
11291 01:00:13.619166 end: 4.2 read-feedback (duration 00:00:01) [common]
11292 01:00:13.619452 end: 4 finalize (duration 00:00:01) [common]
11293 01:00:13.619609 Cleaning after the job
11294 01:00:13.619743 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/ramdisk
11295 01:00:13.628260 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/kernel
11296 01:00:13.637605 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/dtb
11297 01:00:13.637807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571066/tftp-deploy-rlef6bsi/modules
11298 01:00:13.645265 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571066
11299 01:00:13.769909 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571066
11300 01:00:13.770092 Job finished correctly