Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 16
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 01:00:59.485889 lava-dispatcher, installed at version: 2023.10
2 01:00:59.486123 start: 0 validate
3 01:00:59.486268 Start time: 2024-01-19 01:00:59.486260+00:00 (UTC)
4 01:00:59.486403 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:00:59.486549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 01:00:59.773020 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:00:59.773201 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:01:00.037926 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:01:00.038163 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:01:00.295943 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:01:00.296133 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:01:00.554359 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:01:00.554600 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:01:00.812698 validate duration: 1.33
16 01:01:00.812997 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:01:00.813098 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:01:00.813188 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:01:00.813316 Not decompressing ramdisk as can be used compressed.
20 01:01:00.813402 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 01:01:00.813471 saving as /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/ramdisk/initrd.cpio.gz
22 01:01:00.813539 total size: 4665395 (4 MB)
23 01:01:00.814616 progress 0 % (0 MB)
24 01:01:00.816199 progress 5 % (0 MB)
25 01:01:00.817555 progress 10 % (0 MB)
26 01:01:00.818819 progress 15 % (0 MB)
27 01:01:00.820071 progress 20 % (0 MB)
28 01:01:00.821427 progress 25 % (1 MB)
29 01:01:00.822686 progress 30 % (1 MB)
30 01:01:00.823933 progress 35 % (1 MB)
31 01:01:00.825309 progress 40 % (1 MB)
32 01:01:00.826723 progress 45 % (2 MB)
33 01:01:00.828058 progress 50 % (2 MB)
34 01:01:00.829402 progress 55 % (2 MB)
35 01:01:00.830632 progress 60 % (2 MB)
36 01:01:00.831870 progress 65 % (2 MB)
37 01:01:00.833178 progress 70 % (3 MB)
38 01:01:00.834408 progress 75 % (3 MB)
39 01:01:00.835675 progress 80 % (3 MB)
40 01:01:00.837188 progress 85 % (3 MB)
41 01:01:00.838412 progress 90 % (4 MB)
42 01:01:00.839725 progress 95 % (4 MB)
43 01:01:00.841029 progress 100 % (4 MB)
44 01:01:00.841186 4 MB downloaded in 0.03 s (160.94 MB/s)
45 01:01:00.841339 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:01:00.841589 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:01:00.841676 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:01:00.841761 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:01:00.841903 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:01:00.841977 saving as /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/kernel/Image
52 01:01:00.842038 total size: 51532288 (49 MB)
53 01:01:00.842099 No compression specified
54 01:01:00.843211 progress 0 % (0 MB)
55 01:01:00.856871 progress 5 % (2 MB)
56 01:01:00.870526 progress 10 % (4 MB)
57 01:01:00.883989 progress 15 % (7 MB)
58 01:01:00.897744 progress 20 % (9 MB)
59 01:01:00.911648 progress 25 % (12 MB)
60 01:01:00.925360 progress 30 % (14 MB)
61 01:01:00.939556 progress 35 % (17 MB)
62 01:01:00.953157 progress 40 % (19 MB)
63 01:01:00.966626 progress 45 % (22 MB)
64 01:01:00.980351 progress 50 % (24 MB)
65 01:01:00.993566 progress 55 % (27 MB)
66 01:01:01.007102 progress 60 % (29 MB)
67 01:01:01.020679 progress 65 % (31 MB)
68 01:01:01.034304 progress 70 % (34 MB)
69 01:01:01.048070 progress 75 % (36 MB)
70 01:01:01.062013 progress 80 % (39 MB)
71 01:01:01.075566 progress 85 % (41 MB)
72 01:01:01.089190 progress 90 % (44 MB)
73 01:01:01.102827 progress 95 % (46 MB)
74 01:01:01.115800 progress 100 % (49 MB)
75 01:01:01.116040 49 MB downloaded in 0.27 s (179.36 MB/s)
76 01:01:01.116196 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:01:01.116436 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:01:01.116528 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:01:01.116616 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:01:01.116756 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:01:01.116828 saving as /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/dtb/mt8192-asurada-spherion-r0.dtb
83 01:01:01.116890 total size: 47278 (0 MB)
84 01:01:01.116952 No compression specified
85 01:01:01.118084 progress 69 % (0 MB)
86 01:01:01.118366 progress 100 % (0 MB)
87 01:01:01.118523 0 MB downloaded in 0.00 s (27.65 MB/s)
88 01:01:01.118646 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:01:01.118874 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:01:01.118963 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:01:01.119047 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:01:01.119163 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 01:01:01.119231 saving as /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/nfsrootfs/full.rootfs.tar
95 01:01:01.119293 total size: 200813988 (191 MB)
96 01:01:01.119355 Using unxz to decompress xz
97 01:01:01.123600 progress 0 % (0 MB)
98 01:01:01.665719 progress 5 % (9 MB)
99 01:01:02.192765 progress 10 % (19 MB)
100 01:01:02.785505 progress 15 % (28 MB)
101 01:01:03.165100 progress 20 % (38 MB)
102 01:01:03.493564 progress 25 % (47 MB)
103 01:01:04.113769 progress 30 % (57 MB)
104 01:01:04.693117 progress 35 % (67 MB)
105 01:01:05.304208 progress 40 % (76 MB)
106 01:01:05.868072 progress 45 % (86 MB)
107 01:01:06.443969 progress 50 % (95 MB)
108 01:01:07.071358 progress 55 % (105 MB)
109 01:01:07.744903 progress 60 % (114 MB)
110 01:01:07.862696 progress 65 % (124 MB)
111 01:01:08.003117 progress 70 % (134 MB)
112 01:01:08.100741 progress 75 % (143 MB)
113 01:01:08.171727 progress 80 % (153 MB)
114 01:01:08.240315 progress 85 % (162 MB)
115 01:01:08.341669 progress 90 % (172 MB)
116 01:01:08.618453 progress 95 % (181 MB)
117 01:01:09.199293 progress 100 % (191 MB)
118 01:01:09.204531 191 MB downloaded in 8.09 s (23.69 MB/s)
119 01:01:09.204793 end: 1.4.1 http-download (duration 00:00:08) [common]
121 01:01:09.205058 end: 1.4 download-retry (duration 00:00:08) [common]
122 01:01:09.205148 start: 1.5 download-retry (timeout 00:09:52) [common]
123 01:01:09.205236 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 01:01:09.205398 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:01:09.205469 saving as /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/modules/modules.tar
126 01:01:09.205531 total size: 8625444 (8 MB)
127 01:01:09.205595 Using unxz to decompress xz
128 01:01:09.209875 progress 0 % (0 MB)
129 01:01:09.231878 progress 5 % (0 MB)
130 01:01:09.255553 progress 10 % (0 MB)
131 01:01:09.278922 progress 15 % (1 MB)
132 01:01:09.303290 progress 20 % (1 MB)
133 01:01:09.327751 progress 25 % (2 MB)
134 01:01:09.353698 progress 30 % (2 MB)
135 01:01:09.381635 progress 35 % (2 MB)
136 01:01:09.408191 progress 40 % (3 MB)
137 01:01:09.432515 progress 45 % (3 MB)
138 01:01:09.459154 progress 50 % (4 MB)
139 01:01:09.487617 progress 55 % (4 MB)
140 01:01:09.513352 progress 60 % (4 MB)
141 01:01:09.545783 progress 65 % (5 MB)
142 01:01:09.574172 progress 70 % (5 MB)
143 01:01:09.598509 progress 75 % (6 MB)
144 01:01:09.628028 progress 80 % (6 MB)
145 01:01:09.656342 progress 85 % (7 MB)
146 01:01:09.682525 progress 90 % (7 MB)
147 01:01:09.716476 progress 95 % (7 MB)
148 01:01:09.745828 progress 100 % (8 MB)
149 01:01:09.750926 8 MB downloaded in 0.55 s (15.08 MB/s)
150 01:01:09.751182 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:01:09.751450 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:01:09.751546 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 01:01:09.751646 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 01:01:13.526132 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r
156 01:01:13.526329 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 01:01:13.526430 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 01:01:13.526597 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr
159 01:01:13.526730 makedir: /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin
160 01:01:13.526831 makedir: /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/tests
161 01:01:13.526929 makedir: /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/results
162 01:01:13.527029 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-add-keys
163 01:01:13.527173 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-add-sources
164 01:01:13.527304 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-background-process-start
165 01:01:13.527432 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-background-process-stop
166 01:01:13.527557 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-common-functions
167 01:01:13.527681 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-echo-ipv4
168 01:01:13.527805 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-install-packages
169 01:01:13.527929 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-installed-packages
170 01:01:13.528052 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-os-build
171 01:01:13.528176 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-probe-channel
172 01:01:13.528511 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-probe-ip
173 01:01:13.528640 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-target-ip
174 01:01:13.528766 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-target-mac
175 01:01:13.528891 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-target-storage
176 01:01:13.529018 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-case
177 01:01:13.529144 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-event
178 01:01:13.529267 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-feedback
179 01:01:13.529391 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-raise
180 01:01:13.529517 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-reference
181 01:01:13.529640 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-runner
182 01:01:13.529764 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-set
183 01:01:13.529886 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-test-shell
184 01:01:13.530011 Updating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-add-keys (debian)
185 01:01:13.530162 Updating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-add-sources (debian)
186 01:01:13.530308 Updating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-install-packages (debian)
187 01:01:13.530447 Updating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-installed-packages (debian)
188 01:01:13.530590 Updating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/bin/lava-os-build (debian)
189 01:01:13.530714 Creating /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/environment
190 01:01:13.530812 LAVA metadata
191 01:01:13.530882 - LAVA_JOB_ID=12571086
192 01:01:13.530945 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:01:13.531045 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 01:01:13.531110 skipped lava-vland-overlay
195 01:01:13.531184 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:01:13.531264 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 01:01:13.531324 skipped lava-multinode-overlay
198 01:01:13.531395 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:01:13.531471 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 01:01:13.531543 Loading test definitions
201 01:01:13.531628 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 01:01:13.531697 Using /lava-12571086 at stage 0
203 01:01:13.531980 uuid=12571086_1.6.2.3.1 testdef=None
204 01:01:13.532066 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:01:13.532149 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 01:01:13.532648 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:01:13.532864 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 01:01:13.533411 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:01:13.533633 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 01:01:13.534167 runner path: /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/0/tests/0_timesync-off test_uuid 12571086_1.6.2.3.1
213 01:01:13.534317 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:01:13.534535 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 01:01:13.534606 Using /lava-12571086 at stage 0
217 01:01:13.534701 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:01:13.534779 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/0/tests/1_kselftest-rtc'
219 01:01:16.076320 Running '/usr/bin/git checkout kernelci.org
220 01:01:16.146967 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 01:01:16.147752 uuid=12571086_1.6.2.3.5 testdef=None
222 01:01:16.147922 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 01:01:16.148192 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 01:01:16.149016 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:01:16.149272 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 01:01:16.150373 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:01:16.150621 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 01:01:16.151596 runner path: /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/0/tests/1_kselftest-rtc test_uuid 12571086_1.6.2.3.5
232 01:01:16.151690 BOARD='mt8192-asurada-spherion-r0'
233 01:01:16.151756 BRANCH='cip'
234 01:01:16.151822 SKIPFILE='/dev/null'
235 01:01:16.151881 SKIP_INSTALL='True'
236 01:01:16.151942 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:01:16.152001 TST_CASENAME=''
238 01:01:16.152057 TST_CMDFILES='rtc'
239 01:01:16.152208 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:01:16.152499 Creating lava-test-runner.conf files
242 01:01:16.152571 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571086/lava-overlay-iw__wcsr/lava-12571086/0 for stage 0
243 01:01:16.152670 - 0_timesync-off
244 01:01:16.152741 - 1_kselftest-rtc
245 01:01:16.152843 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 01:01:16.152934 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 01:01:23.864896 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 01:01:23.865053 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 01:01:23.865147 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:01:23.865248 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:01:23.865338 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 01:01:23.989672 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:01:23.990066 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 01:01:23.990185 extracting modules file /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r
255 01:01:24.216950 extracting modules file /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571086/extract-overlay-ramdisk-vbwk_6bd/ramdisk
256 01:01:24.468014 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 01:01:24.468204 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 01:01:24.468325 [common] Applying overlay to NFS
259 01:01:24.468396 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571086/compress-overlay-2ri3y8me/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r
260 01:01:25.392294 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:01:25.392496 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 01:01:25.392590 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:01:25.392677 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 01:01:25.392757 Building ramdisk /var/lib/lava/dispatcher/tmp/12571086/extract-overlay-ramdisk-vbwk_6bd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571086/extract-overlay-ramdisk-vbwk_6bd/ramdisk
265 01:01:25.742330 >> 119414 blocks
266 01:01:27.667777 rename /var/lib/lava/dispatcher/tmp/12571086/extract-overlay-ramdisk-vbwk_6bd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/ramdisk/ramdisk.cpio.gz
267 01:01:27.668242 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 01:01:27.668417 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 01:01:27.668522 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 01:01:27.668631 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/kernel/Image'
271 01:01:41.196691 Returned 0 in 13 seconds
272 01:01:41.297616 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/kernel/image.itb
273 01:01:41.676582 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:01:41.676961 output: Created: Fri Jan 19 01:01:41 2024
275 01:01:41.677043 output: Image 0 (kernel-1)
276 01:01:41.677108 output: Description:
277 01:01:41.677174 output: Created: Fri Jan 19 01:01:41 2024
278 01:01:41.677233 output: Type: Kernel Image
279 01:01:41.677293 output: Compression: lzma compressed
280 01:01:41.677354 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
281 01:01:41.677410 output: Architecture: AArch64
282 01:01:41.677464 output: OS: Linux
283 01:01:41.677522 output: Load Address: 0x00000000
284 01:01:41.677581 output: Entry Point: 0x00000000
285 01:01:41.677639 output: Hash algo: crc32
286 01:01:41.677695 output: Hash value: a52aa383
287 01:01:41.677751 output: Image 1 (fdt-1)
288 01:01:41.677803 output: Description: mt8192-asurada-spherion-r0
289 01:01:41.677856 output: Created: Fri Jan 19 01:01:41 2024
290 01:01:41.677908 output: Type: Flat Device Tree
291 01:01:41.677962 output: Compression: uncompressed
292 01:01:41.678015 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 01:01:41.678068 output: Architecture: AArch64
294 01:01:41.678120 output: Hash algo: crc32
295 01:01:41.678172 output: Hash value: cc4352de
296 01:01:41.678224 output: Image 2 (ramdisk-1)
297 01:01:41.678276 output: Description: unavailable
298 01:01:41.678329 output: Created: Fri Jan 19 01:01:41 2024
299 01:01:41.678381 output: Type: RAMDisk Image
300 01:01:41.678434 output: Compression: Unknown Compression
301 01:01:41.678487 output: Data Size: 17799310 Bytes = 17382.14 KiB = 16.97 MiB
302 01:01:41.678539 output: Architecture: AArch64
303 01:01:41.678592 output: OS: Linux
304 01:01:41.678644 output: Load Address: unavailable
305 01:01:41.678696 output: Entry Point: unavailable
306 01:01:41.678748 output: Hash algo: crc32
307 01:01:41.678800 output: Hash value: 6e1f1000
308 01:01:41.678852 output: Default Configuration: 'conf-1'
309 01:01:41.678904 output: Configuration 0 (conf-1)
310 01:01:41.678956 output: Description: mt8192-asurada-spherion-r0
311 01:01:41.679008 output: Kernel: kernel-1
312 01:01:41.679060 output: Init Ramdisk: ramdisk-1
313 01:01:41.679111 output: FDT: fdt-1
314 01:01:41.679163 output: Loadables: kernel-1
315 01:01:41.679215 output:
316 01:01:41.679416 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 01:01:41.679519 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 01:01:41.679623 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 01:01:41.679713 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 01:01:41.679795 No LXC device requested
321 01:01:41.679873 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:01:41.679956 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 01:01:41.680031 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:01:41.680098 Checking files for TFTP limit of 4294967296 bytes.
325 01:01:41.680630 end: 1 tftp-deploy (duration 00:00:41) [common]
326 01:01:41.680737 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:01:41.680830 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:01:41.680958 substitutions:
329 01:01:41.681024 - {DTB}: 12571086/tftp-deploy-gwbojakf/dtb/mt8192-asurada-spherion-r0.dtb
330 01:01:41.681089 - {INITRD}: 12571086/tftp-deploy-gwbojakf/ramdisk/ramdisk.cpio.gz
331 01:01:41.681149 - {KERNEL}: 12571086/tftp-deploy-gwbojakf/kernel/Image
332 01:01:41.681206 - {LAVA_MAC}: None
333 01:01:41.681263 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r
334 01:01:41.681319 - {NFS_SERVER_IP}: 192.168.201.1
335 01:01:41.681373 - {PRESEED_CONFIG}: None
336 01:01:41.681427 - {PRESEED_LOCAL}: None
337 01:01:41.681482 - {RAMDISK}: 12571086/tftp-deploy-gwbojakf/ramdisk/ramdisk.cpio.gz
338 01:01:41.681573 - {ROOT_PART}: None
339 01:01:41.681626 - {ROOT}: None
340 01:01:41.681679 - {SERVER_IP}: 192.168.201.1
341 01:01:41.681732 - {TEE}: None
342 01:01:41.681785 Parsed boot commands:
343 01:01:41.681837 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:01:41.682020 Parsed boot commands: tftpboot 192.168.201.1 12571086/tftp-deploy-gwbojakf/kernel/image.itb 12571086/tftp-deploy-gwbojakf/kernel/cmdline
345 01:01:41.682107 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:01:41.682190 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:01:41.682283 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:01:41.682370 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:01:41.682444 Not connected, no need to disconnect.
350 01:01:41.682519 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:01:41.682599 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:01:41.682668 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 01:01:41.686823 Setting prompt string to ['lava-test: # ']
354 01:01:41.687212 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:01:41.687326 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:01:41.687428 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:01:41.687518 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:01:41.687774 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 01:01:46.814778 >> Command sent successfully.
360 01:01:46.817276 Returned 0 in 5 seconds
361 01:01:46.917685 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:01:46.918008 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:01:46.918111 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:01:46.918201 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:01:46.918274 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:01:46.918344 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:01:46.918607 [Enter `^Ec?' for help]
369 01:01:47.090493
370 01:01:47.090635
371 01:01:47.090711 F0: 102B 0000
372 01:01:47.090776
373 01:01:47.090835 F3: 1001 0000 [0200]
374 01:01:47.093486
375 01:01:47.093578 F3: 1001 0000
376 01:01:47.093646
377 01:01:47.093709 F7: 102D 0000
378 01:01:47.093787
379 01:01:47.096866 F1: 0000 0000
380 01:01:47.096997
381 01:01:47.097126 V0: 0000 0000 [0001]
382 01:01:47.097236
383 01:01:47.100061 00: 0007 8000
384 01:01:47.100150
385 01:01:47.100235 01: 0000 0000
386 01:01:47.100311
387 01:01:47.103416 BP: 0C00 0209 [0000]
388 01:01:47.103502
389 01:01:47.103570 G0: 1182 0000
390 01:01:47.103634
391 01:01:47.107228 EC: 0000 0021 [4000]
392 01:01:47.107311
393 01:01:47.107377 S7: 0000 0000 [0000]
394 01:01:47.107439
395 01:01:47.110461 CC: 0000 0000 [0001]
396 01:01:47.110572
397 01:01:47.110685 T0: 0000 0040 [010F]
398 01:01:47.110788
399 01:01:47.113664 Jump to BL
400 01:01:47.113748
401 01:01:47.137091
402 01:01:47.137243
403 01:01:47.137381
404 01:01:47.144494 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:01:47.148551 ARM64: Exception handlers installed.
406 01:01:47.152257 ARM64: Testing exception
407 01:01:47.155795 ARM64: Done test exception
408 01:01:47.162240 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:01:47.172627 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:01:47.178719 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:01:47.189117 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:01:47.195526 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:01:47.202112 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:01:47.213825 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:01:47.221034 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:01:47.240223 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:01:47.243461 WDT: Last reset was cold boot
418 01:01:47.246828 SPI1(PAD0) initialized at 2873684 Hz
419 01:01:47.250099 SPI5(PAD0) initialized at 992727 Hz
420 01:01:47.253364 VBOOT: Loading verstage.
421 01:01:47.260481 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:01:47.263740 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:01:47.267195 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:01:47.270262 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:01:47.277651 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:01:47.284480 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:01:47.294760 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 01:01:47.294852
429 01:01:47.294918
430 01:01:47.306001 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:01:47.308991 ARM64: Exception handlers installed.
432 01:01:47.312136 ARM64: Testing exception
433 01:01:47.312240 ARM64: Done test exception
434 01:01:47.315540 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:01:47.322532 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:01:47.336283 Probing TPM: . done!
437 01:01:47.336391 TPM ready after 0 ms
438 01:01:47.343162 Connected to device vid:did:rid of 1ae0:0028:00
439 01:01:47.350433 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 01:01:47.409614 Initialized TPM device CR50 revision 0
441 01:01:47.421825 tlcl_send_startup: Startup return code is 0
442 01:01:47.422250 TPM: setup succeeded
443 01:01:47.433208 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:01:47.442162 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:01:47.456230 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:01:47.463267 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:01:47.466587 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:01:47.470442 in-header: 03 07 00 00 08 00 00 00
449 01:01:47.473815 in-data: aa e4 47 04 13 02 00 00
450 01:01:47.477676 Chrome EC: UHEPI supported
451 01:01:47.481661 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:01:47.485536 in-header: 03 95 00 00 08 00 00 00
453 01:01:47.488682 in-data: 18 20 20 08 00 00 00 00
454 01:01:47.488778 Phase 1
455 01:01:47.492266 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:01:47.500101 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:01:47.507673 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:01:47.507847 Recovery requested (1009000e)
459 01:01:47.520472 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:01:47.523641 tlcl_extend: response is 0
461 01:01:47.534152 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:01:47.538620 tlcl_extend: response is 0
463 01:01:47.545876 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:01:47.565694 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 01:01:47.572344 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 01:01:47.572864
467 01:01:47.573220
468 01:01:47.582409 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:01:47.585411 ARM64: Exception handlers installed.
470 01:01:47.588479 ARM64: Testing exception
471 01:01:47.588918 ARM64: Done test exception
472 01:01:47.611083 pmic_efuse_setting: Set efuses in 11 msecs
473 01:01:47.614226 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:01:47.621276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:01:47.624507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:01:47.631922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:01:47.635658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:01:47.639177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:01:47.645806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:01:47.649566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:01:47.653476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:01:47.657123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:01:47.665019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:01:47.668348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:01:47.671797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:01:47.674841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:01:47.683107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:01:47.690788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:01:47.694901 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:01:47.702254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:01:47.706017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:01:47.713539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:01:47.717658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:01:47.721207 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:01:47.729420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:01:47.732748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:01:47.740469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:01:47.743860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:01:47.751490 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:01:47.754751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:01:47.762324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:01:47.765706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:01:47.769755 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:01:47.777016 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:01:47.780550 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:01:47.783937 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:01:47.791740 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:01:47.794564 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:01:47.798946 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:01:47.806384 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:01:47.810056 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:01:47.813824 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:01:47.817594 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:01:47.824533 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:01:47.828368 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:01:47.832347 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:01:47.836235 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:01:47.839734 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:01:47.847064 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:01:47.850419 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:01:47.854576 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:01:47.858375 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:01:47.862130 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:01:47.865816 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:01:47.873217 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:01:47.884561 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:01:47.887881 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:01:47.895148 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:01:47.902953 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:01:47.910377 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:01:47.914356 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:01:47.917991 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:01:47.925129 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2d
534 01:01:47.928785 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:01:47.936338 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 01:01:47.939754 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:01:47.948479 [RTC]rtc_get_frequency_meter,154: input=15, output=760
538 01:01:47.958114 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 01:01:47.967423 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 01:01:47.977313 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 01:01:47.986231 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 01:01:47.995857 [RTC]rtc_get_frequency_meter,154: input=16, output=780
543 01:01:48.006621 [RTC]rtc_get_frequency_meter,154: input=17, output=806
544 01:01:48.010209 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 01:01:48.014033 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 01:01:48.017748 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 01:01:48.025258 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 01:01:48.028563 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 01:01:48.032268 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 01:01:48.036166 ADC[4]: Raw value=905834 ID=7
551 01:01:48.036760 ADC[3]: Raw value=213441 ID=1
552 01:01:48.039857 RAM Code: 0x71
553 01:01:48.043523 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 01:01:48.047995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 01:01:48.054941 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 01:01:48.062071 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 01:01:48.065507 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 01:01:48.069828 in-header: 03 07 00 00 08 00 00 00
559 01:01:48.073953 in-data: aa e4 47 04 13 02 00 00
560 01:01:48.077125 Chrome EC: UHEPI supported
561 01:01:48.084513 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 01:01:48.087814 in-header: 03 95 00 00 08 00 00 00
563 01:01:48.091614 in-data: 18 20 20 08 00 00 00 00
564 01:01:48.092053 MRC: failed to locate region type 0.
565 01:01:48.099073 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 01:01:48.103028 DRAM-K: Running full calibration
567 01:01:48.110702 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 01:01:48.111138 header.status = 0x0
569 01:01:48.113911 header.version = 0x6 (expected: 0x6)
570 01:01:48.118415 header.size = 0xd00 (expected: 0xd00)
571 01:01:48.118925 header.flags = 0x0
572 01:01:48.124776 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 01:01:48.144158 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 01:01:48.151646 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 01:01:48.152116 dram_init: ddr_geometry: 2
576 01:01:48.155554 [EMI] MDL number = 2
577 01:01:48.156013 [EMI] Get MDL freq = 0
578 01:01:48.159386 dram_init: ddr_type: 0
579 01:01:48.159923 is_discrete_lpddr4: 1
580 01:01:48.163150 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 01:01:48.163589
582 01:01:48.164143
583 01:01:48.166778 [Bian_co] ETT version 0.0.0.1
584 01:01:48.171437 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 01:01:48.171864
586 01:01:48.175185 dramc_set_vcore_voltage set vcore to 650000
587 01:01:48.179099 Read voltage for 800, 4
588 01:01:48.179753 Vio18 = 0
589 01:01:48.180226 Vcore = 650000
590 01:01:48.182589 Vdram = 0
591 01:01:48.183018 Vddq = 0
592 01:01:48.183360 Vmddr = 0
593 01:01:48.186276 dram_init: config_dvfs: 1
594 01:01:48.190084 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 01:01:48.194667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 01:01:48.201583 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 01:01:48.205403 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 01:01:48.209473 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 01:01:48.212676 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 01:01:48.213113 MEM_TYPE=3, freq_sel=18
601 01:01:48.216563 sv_algorithm_assistance_LP4_1600
602 01:01:48.219760 ============ PULL DRAM RESETB DOWN ============
603 01:01:48.223134 ========== PULL DRAM RESETB DOWN end =========
604 01:01:48.229935 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 01:01:48.234044 ===================================
606 01:01:48.234474 LPDDR4 DRAM CONFIGURATION
607 01:01:48.237797 ===================================
608 01:01:48.242002 EX_ROW_EN[0] = 0x0
609 01:01:48.242543 EX_ROW_EN[1] = 0x0
610 01:01:48.245188 LP4Y_EN = 0x0
611 01:01:48.245822 WORK_FSP = 0x0
612 01:01:48.248953 WL = 0x2
613 01:01:48.249404 RL = 0x2
614 01:01:48.252752 BL = 0x2
615 01:01:48.253321 RPST = 0x0
616 01:01:48.255675 RD_PRE = 0x0
617 01:01:48.256113 WR_PRE = 0x1
618 01:01:48.259429 WR_PST = 0x0
619 01:01:48.259908 DBI_WR = 0x0
620 01:01:48.262791 DBI_RD = 0x0
621 01:01:48.263278 OTF = 0x1
622 01:01:48.265897 ===================================
623 01:01:48.269307 ===================================
624 01:01:48.269779 ANA top config
625 01:01:48.272530 ===================================
626 01:01:48.275789 DLL_ASYNC_EN = 0
627 01:01:48.279248 ALL_SLAVE_EN = 1
628 01:01:48.282770 NEW_RANK_MODE = 1
629 01:01:48.285846 DLL_IDLE_MODE = 1
630 01:01:48.286291 LP45_APHY_COMB_EN = 1
631 01:01:48.289337 TX_ODT_DIS = 1
632 01:01:48.292622 NEW_8X_MODE = 1
633 01:01:48.296395 ===================================
634 01:01:48.299760 ===================================
635 01:01:48.302737 data_rate = 1600
636 01:01:48.303177 CKR = 1
637 01:01:48.306120 DQ_P2S_RATIO = 8
638 01:01:48.309734 ===================================
639 01:01:48.313343 CA_P2S_RATIO = 8
640 01:01:48.316728 DQ_CA_OPEN = 0
641 01:01:48.319991 DQ_SEMI_OPEN = 0
642 01:01:48.323266 CA_SEMI_OPEN = 0
643 01:01:48.323809 CA_FULL_RATE = 0
644 01:01:48.326414 DQ_CKDIV4_EN = 1
645 01:01:48.330232 CA_CKDIV4_EN = 1
646 01:01:48.333413 CA_PREDIV_EN = 0
647 01:01:48.336680 PH8_DLY = 0
648 01:01:48.339789 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 01:01:48.340511 DQ_AAMCK_DIV = 4
650 01:01:48.343400 CA_AAMCK_DIV = 4
651 01:01:48.346374 CA_ADMCK_DIV = 4
652 01:01:48.349649 DQ_TRACK_CA_EN = 0
653 01:01:48.353274 CA_PICK = 800
654 01:01:48.357046 CA_MCKIO = 800
655 01:01:48.357561 MCKIO_SEMI = 0
656 01:01:48.360207 PLL_FREQ = 3068
657 01:01:48.364023 DQ_UI_PI_RATIO = 32
658 01:01:48.368013 CA_UI_PI_RATIO = 0
659 01:01:48.371173 ===================================
660 01:01:48.371610 ===================================
661 01:01:48.375050 memory_type:LPDDR4
662 01:01:48.378995 GP_NUM : 10
663 01:01:48.379541 SRAM_EN : 1
664 01:01:48.382882 MD32_EN : 0
665 01:01:48.386240 ===================================
666 01:01:48.386684 [ANA_INIT] >>>>>>>>>>>>>>
667 01:01:48.390027 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 01:01:48.393906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 01:01:48.396966 ===================================
670 01:01:48.400953 data_rate = 1600,PCW = 0X7600
671 01:01:48.404374 ===================================
672 01:01:48.407576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 01:01:48.410535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:01:48.417933 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 01:01:48.420712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 01:01:48.424278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:01:48.427498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 01:01:48.430873 [ANA_INIT] flow start
679 01:01:48.434277 [ANA_INIT] PLL >>>>>>>>
680 01:01:48.434871 [ANA_INIT] PLL <<<<<<<<
681 01:01:48.437812 [ANA_INIT] MIDPI >>>>>>>>
682 01:01:48.441305 [ANA_INIT] MIDPI <<<<<<<<
683 01:01:48.441877 [ANA_INIT] DLL >>>>>>>>
684 01:01:48.444625 [ANA_INIT] flow end
685 01:01:48.447689 ============ LP4 DIFF to SE enter ============
686 01:01:48.450820 ============ LP4 DIFF to SE exit ============
687 01:01:48.454691 [ANA_INIT] <<<<<<<<<<<<<
688 01:01:48.457980 [Flow] Enable top DCM control >>>>>
689 01:01:48.461192 [Flow] Enable top DCM control <<<<<
690 01:01:48.464506 Enable DLL master slave shuffle
691 01:01:48.471473 ==============================================================
692 01:01:48.472053 Gating Mode config
693 01:01:48.477767 ==============================================================
694 01:01:48.478238 Config description:
695 01:01:48.487768 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 01:01:48.494390 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 01:01:48.501472 SELPH_MODE 0: By rank 1: By Phase
698 01:01:48.504475 ==============================================================
699 01:01:48.507849 GAT_TRACK_EN = 1
700 01:01:48.511123 RX_GATING_MODE = 2
701 01:01:48.514261 RX_GATING_TRACK_MODE = 2
702 01:01:48.517627 SELPH_MODE = 1
703 01:01:48.521513 PICG_EARLY_EN = 1
704 01:01:48.524627 VALID_LAT_VALUE = 1
705 01:01:48.527861 ==============================================================
706 01:01:48.530924 Enter into Gating configuration >>>>
707 01:01:48.534545 Exit from Gating configuration <<<<
708 01:01:48.537696 Enter into DVFS_PRE_config >>>>>
709 01:01:48.551108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 01:01:48.554693 Exit from DVFS_PRE_config <<<<<
711 01:01:48.557557 Enter into PICG configuration >>>>
712 01:01:48.557997 Exit from PICG configuration <<<<
713 01:01:48.560994 [RX_INPUT] configuration >>>>>
714 01:01:48.564641 [RX_INPUT] configuration <<<<<
715 01:01:48.571402 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 01:01:48.574734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 01:01:48.581076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 01:01:48.587868 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 01:01:48.594425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 01:01:48.607513 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 01:01:48.608017 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 01:01:48.608748 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 01:01:48.611281 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 01:01:48.618387 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 01:01:48.621563 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 01:01:48.624909 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 01:01:48.628041 ===================================
728 01:01:48.631384 LPDDR4 DRAM CONFIGURATION
729 01:01:48.635113 ===================================
730 01:01:48.635558 EX_ROW_EN[0] = 0x0
731 01:01:48.638666 EX_ROW_EN[1] = 0x0
732 01:01:48.641749 LP4Y_EN = 0x0
733 01:01:48.642305 WORK_FSP = 0x0
734 01:01:48.644655 WL = 0x2
735 01:01:48.645081 RL = 0x2
736 01:01:48.648768 BL = 0x2
737 01:01:48.649339 RPST = 0x0
738 01:01:48.651685 RD_PRE = 0x0
739 01:01:48.652111 WR_PRE = 0x1
740 01:01:48.654844 WR_PST = 0x0
741 01:01:48.655265 DBI_WR = 0x0
742 01:01:48.658034 DBI_RD = 0x0
743 01:01:48.658472 OTF = 0x1
744 01:01:48.661662 ===================================
745 01:01:48.664797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 01:01:48.671067 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 01:01:48.674371 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 01:01:48.678687 ===================================
749 01:01:48.681221 LPDDR4 DRAM CONFIGURATION
750 01:01:48.684641 ===================================
751 01:01:48.685075 EX_ROW_EN[0] = 0x10
752 01:01:48.687821 EX_ROW_EN[1] = 0x0
753 01:01:48.688263 LP4Y_EN = 0x0
754 01:01:48.691276 WORK_FSP = 0x0
755 01:01:48.691704 WL = 0x2
756 01:01:48.694429 RL = 0x2
757 01:01:48.694854 BL = 0x2
758 01:01:48.698330 RPST = 0x0
759 01:01:48.701235 RD_PRE = 0x0
760 01:01:48.701666 WR_PRE = 0x1
761 01:01:48.704888 WR_PST = 0x0
762 01:01:48.705320 DBI_WR = 0x0
763 01:01:48.708224 DBI_RD = 0x0
764 01:01:48.708695 OTF = 0x1
765 01:01:48.711585 ===================================
766 01:01:48.718319 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 01:01:48.721458 nWR fixed to 40
768 01:01:48.725073 [ModeRegInit_LP4] CH0 RK0
769 01:01:48.725302 [ModeRegInit_LP4] CH0 RK1
770 01:01:48.728218 [ModeRegInit_LP4] CH1 RK0
771 01:01:48.731468 [ModeRegInit_LP4] CH1 RK1
772 01:01:48.731651 match AC timing 13
773 01:01:48.738393 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 01:01:48.741589 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 01:01:48.744861 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 01:01:48.751215 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 01:01:48.754489 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 01:01:48.754585 [EMI DOE] emi_dcm 0
779 01:01:48.761461 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 01:01:48.761551 ==
781 01:01:48.765203 Dram Type= 6, Freq= 0, CH_0, rank 0
782 01:01:48.767852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 01:01:48.767936 ==
784 01:01:48.774824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 01:01:48.781032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 01:01:48.788677 [CA 0] Center 36 (6~67) winsize 62
787 01:01:48.791945 [CA 1] Center 36 (6~67) winsize 62
788 01:01:48.795471 [CA 2] Center 34 (4~65) winsize 62
789 01:01:48.798740 [CA 3] Center 34 (4~64) winsize 61
790 01:01:48.801900 [CA 4] Center 33 (3~64) winsize 62
791 01:01:48.805158 [CA 5] Center 33 (3~63) winsize 61
792 01:01:48.805242
793 01:01:48.808850 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 01:01:48.808938
795 01:01:48.812560 [CATrainingPosCal] consider 1 rank data
796 01:01:48.815238 u2DelayCellTimex100 = 270/100 ps
797 01:01:48.819196 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
798 01:01:48.822259 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 01:01:48.825547 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 01:01:48.832169 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
801 01:01:48.835611 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 01:01:48.838765 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
803 01:01:48.838852
804 01:01:48.841874 CA PerBit enable=1, Macro0, CA PI delay=33
805 01:01:48.841959
806 01:01:48.845322 [CBTSetCACLKResult] CA Dly = 33
807 01:01:48.845407 CS Dly: 5 (0~36)
808 01:01:48.845475 ==
809 01:01:48.848746 Dram Type= 6, Freq= 0, CH_0, rank 1
810 01:01:48.855410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 01:01:48.855499 ==
812 01:01:48.858834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 01:01:48.865138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 01:01:48.874591 [CA 0] Center 36 (6~67) winsize 62
815 01:01:48.878406 [CA 1] Center 36 (6~67) winsize 62
816 01:01:48.881761 [CA 2] Center 34 (4~65) winsize 62
817 01:01:48.884645 [CA 3] Center 33 (3~64) winsize 62
818 01:01:48.887893 [CA 4] Center 32 (2~63) winsize 62
819 01:01:48.891635 [CA 5] Center 32 (2~63) winsize 62
820 01:01:48.891721
821 01:01:48.894679 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 01:01:48.894765
823 01:01:48.898266 [CATrainingPosCal] consider 2 rank data
824 01:01:48.901580 u2DelayCellTimex100 = 270/100 ps
825 01:01:48.904515 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
826 01:01:48.907745 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
827 01:01:48.914805 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 01:01:48.917951 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
829 01:01:48.921247 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
830 01:01:48.925014 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
831 01:01:48.925099
832 01:01:48.928235 CA PerBit enable=1, Macro0, CA PI delay=33
833 01:01:48.928356
834 01:01:48.931408 [CBTSetCACLKResult] CA Dly = 33
835 01:01:48.931494 CS Dly: 5 (0~37)
836 01:01:48.931564
837 01:01:48.934562 ----->DramcWriteLeveling(PI) begin...
838 01:01:48.938731 ==
839 01:01:48.938816 Dram Type= 6, Freq= 0, CH_0, rank 0
840 01:01:48.942298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 01:01:48.945929 ==
842 01:01:48.946018 Write leveling (Byte 0): 32 => 32
843 01:01:48.950171 Write leveling (Byte 1): 28 => 28
844 01:01:48.953571 DramcWriteLeveling(PI) end<-----
845 01:01:48.953658
846 01:01:48.953725 ==
847 01:01:48.956821 Dram Type= 6, Freq= 0, CH_0, rank 0
848 01:01:48.960511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 01:01:48.960598 ==
850 01:01:48.963827 [Gating] SW mode calibration
851 01:01:48.971094 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 01:01:48.977550 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 01:01:48.980967 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 01:01:48.984066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 01:01:48.990916 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 01:01:48.994188 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 01:01:48.997927 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:01:49.001089 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:01:49.007957 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:01:49.011101 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:01:49.014373 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:01:49.020794 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:01:49.024574 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:01:49.027568 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:01:49.034794 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:01:49.038068 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:01:49.041275 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:01:49.048012 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:01:49.051005 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 01:01:49.054706 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 01:01:49.061094 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 01:01:49.064744 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:01:49.067981 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:01:49.071077 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:01:49.077856 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:01:49.080931 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:01:49.084573 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:01:49.090971 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 01:01:49.094641 0 9 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
880 01:01:49.098257 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 01:01:49.104756 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:01:49.108120 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:01:49.111534 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:01:49.118068 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:01:49.121180 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 01:01:49.125158 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
887 01:01:49.131709 0 10 8 | B1->B0 | 3333 2424 | 0 1 | (0 1) (1 0)
888 01:01:49.134865 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
889 01:01:49.138257 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:01:49.144939 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:01:49.148008 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:01:49.151344 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:01:49.154811 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 01:01:49.161786 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 01:01:49.164837 0 11 8 | B1->B0 | 2e2d 3f3f | 1 0 | (0 0) (0 0)
896 01:01:49.168407 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 01:01:49.174986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:01:49.178748 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:01:49.181756 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:01:49.188756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:01:49.191940 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 01:01:49.195032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 01:01:49.201559 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 01:01:49.205280 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 01:01:49.208250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:01:49.211950 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:01:49.218642 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:01:49.221888 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:01:49.225147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:01:49.232234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:01:49.235386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:01:49.238407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:01:49.245264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:01:49.249013 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:01:49.252096 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:01:49.258435 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:01:49.262242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 01:01:49.265384 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 01:01:49.272213 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 01:01:49.272348 Total UI for P1: 0, mck2ui 16
921 01:01:49.275250 best dqsien dly found for B0: ( 0, 14, 4)
922 01:01:49.282338 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 01:01:49.285604 Total UI for P1: 0, mck2ui 16
924 01:01:49.288683 best dqsien dly found for B1: ( 0, 14, 8)
925 01:01:49.293038 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 01:01:49.296162 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 01:01:49.296249
928 01:01:49.299427 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 01:01:49.303292 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 01:01:49.306533 [Gating] SW calibration Done
931 01:01:49.306617 ==
932 01:01:49.309784 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:01:49.312743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:01:49.312828 ==
935 01:01:49.312895 RX Vref Scan: 0
936 01:01:49.316342
937 01:01:49.316427 RX Vref 0 -> 0, step: 1
938 01:01:49.316496
939 01:01:49.319551 RX Delay -130 -> 252, step: 16
940 01:01:49.322927 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
941 01:01:49.326253 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 01:01:49.333270 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
943 01:01:49.336134 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
944 01:01:49.339704 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 01:01:49.342822 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 01:01:49.346134 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
947 01:01:49.353031 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
948 01:01:49.356264 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
949 01:01:49.359748 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
950 01:01:49.362696 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
951 01:01:49.366047 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 01:01:49.373024 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
953 01:01:49.376603 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
954 01:01:49.379538 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 01:01:49.383324 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
956 01:01:49.383410 ==
957 01:01:49.386594 Dram Type= 6, Freq= 0, CH_0, rank 0
958 01:01:49.393219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 01:01:49.393308 ==
960 01:01:49.393376 DQS Delay:
961 01:01:49.393438 DQS0 = 0, DQS1 = 0
962 01:01:49.396140 DQM Delay:
963 01:01:49.396238 DQM0 = 88, DQM1 = 82
964 01:01:49.399912 DQ Delay:
965 01:01:49.403055 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 01:01:49.403140 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
967 01:01:49.406251 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
968 01:01:49.409523 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
969 01:01:49.413348
970 01:01:49.413432
971 01:01:49.413497 ==
972 01:01:49.416674 Dram Type= 6, Freq= 0, CH_0, rank 0
973 01:01:49.419703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 01:01:49.419798 ==
975 01:01:49.419867
976 01:01:49.419928
977 01:01:49.423590 TX Vref Scan disable
978 01:01:49.423750 == TX Byte 0 ==
979 01:01:49.430220 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 01:01:49.433233 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 01:01:49.433382 == TX Byte 1 ==
982 01:01:49.440233 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 01:01:49.443505 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 01:01:49.443660 ==
985 01:01:49.446723 Dram Type= 6, Freq= 0, CH_0, rank 0
986 01:01:49.449777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 01:01:49.449873 ==
988 01:01:49.463763 TX Vref=22, minBit 8, minWin=27, winSum=448
989 01:01:49.467523 TX Vref=24, minBit 8, minWin=27, winSum=450
990 01:01:49.470503 TX Vref=26, minBit 0, minWin=28, winSum=456
991 01:01:49.473942 TX Vref=28, minBit 9, minWin=28, winSum=458
992 01:01:49.477167 TX Vref=30, minBit 8, minWin=28, winSum=459
993 01:01:49.480426 TX Vref=32, minBit 5, minWin=28, winSum=455
994 01:01:49.486886 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
995 01:01:49.487027
996 01:01:49.490369 Final TX Range 1 Vref 30
997 01:01:49.490530
998 01:01:49.490654 ==
999 01:01:49.493867 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 01:01:49.497236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 01:01:49.497415 ==
1002 01:01:49.497556
1003 01:01:49.497687
1004 01:01:49.501261 TX Vref Scan disable
1005 01:01:49.504063 == TX Byte 0 ==
1006 01:01:49.507659 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 01:01:49.510876 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 01:01:49.514140 == TX Byte 1 ==
1009 01:01:49.517567 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1010 01:01:49.520790 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1011 01:01:49.521223
1012 01:01:49.524545 [DATLAT]
1013 01:01:49.524973 Freq=800, CH0 RK0
1014 01:01:49.525317
1015 01:01:49.527451 DATLAT Default: 0xa
1016 01:01:49.527879 0, 0xFFFF, sum = 0
1017 01:01:49.531187 1, 0xFFFF, sum = 0
1018 01:01:49.531638 2, 0xFFFF, sum = 0
1019 01:01:49.534066 3, 0xFFFF, sum = 0
1020 01:01:49.534152 4, 0xFFFF, sum = 0
1021 01:01:49.537359 5, 0xFFFF, sum = 0
1022 01:01:49.537511 6, 0xFFFF, sum = 0
1023 01:01:49.540628 7, 0xFFFF, sum = 0
1024 01:01:49.540761 8, 0xFFFF, sum = 0
1025 01:01:49.544215 9, 0x0, sum = 1
1026 01:01:49.544378 10, 0x0, sum = 2
1027 01:01:49.547316 11, 0x0, sum = 3
1028 01:01:49.547423 12, 0x0, sum = 4
1029 01:01:49.550569 best_step = 10
1030 01:01:49.550687
1031 01:01:49.550757 ==
1032 01:01:49.554241 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 01:01:49.557224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 01:01:49.557323 ==
1035 01:01:49.560517 RX Vref Scan: 1
1036 01:01:49.560601
1037 01:01:49.560666 Set Vref Range= 32 -> 127
1038 01:01:49.560727
1039 01:01:49.564660 RX Vref 32 -> 127, step: 1
1040 01:01:49.565081
1041 01:01:49.567784 RX Delay -95 -> 252, step: 8
1042 01:01:49.568202
1043 01:01:49.571026 Set Vref, RX VrefLevel [Byte0]: 32
1044 01:01:49.574691 [Byte1]: 32
1045 01:01:49.575111
1046 01:01:49.578116 Set Vref, RX VrefLevel [Byte0]: 33
1047 01:01:49.581168 [Byte1]: 33
1048 01:01:49.584412
1049 01:01:49.584968 Set Vref, RX VrefLevel [Byte0]: 34
1050 01:01:49.588041 [Byte1]: 34
1051 01:01:49.592218
1052 01:01:49.592677 Set Vref, RX VrefLevel [Byte0]: 35
1053 01:01:49.595357 [Byte1]: 35
1054 01:01:49.599555
1055 01:01:49.599940 Set Vref, RX VrefLevel [Byte0]: 36
1056 01:01:49.602756 [Byte1]: 36
1057 01:01:49.607326
1058 01:01:49.607626 Set Vref, RX VrefLevel [Byte0]: 37
1059 01:01:49.610606 [Byte1]: 37
1060 01:01:49.614876
1061 01:01:49.615093 Set Vref, RX VrefLevel [Byte0]: 38
1062 01:01:49.618206 [Byte1]: 38
1063 01:01:49.622178
1064 01:01:49.622309 Set Vref, RX VrefLevel [Byte0]: 39
1065 01:01:49.625743 [Byte1]: 39
1066 01:01:49.630252
1067 01:01:49.630452 Set Vref, RX VrefLevel [Byte0]: 40
1068 01:01:49.633194 [Byte1]: 40
1069 01:01:49.637692
1070 01:01:49.637822 Set Vref, RX VrefLevel [Byte0]: 41
1071 01:01:49.641277 [Byte1]: 41
1072 01:01:49.645153
1073 01:01:49.645581 Set Vref, RX VrefLevel [Byte0]: 42
1074 01:01:49.648754 [Byte1]: 42
1075 01:01:49.652592
1076 01:01:49.653009 Set Vref, RX VrefLevel [Byte0]: 43
1077 01:01:49.656672 [Byte1]: 43
1078 01:01:49.660905
1079 01:01:49.661336 Set Vref, RX VrefLevel [Byte0]: 44
1080 01:01:49.663661 [Byte1]: 44
1081 01:01:49.668489
1082 01:01:49.668906 Set Vref, RX VrefLevel [Byte0]: 45
1083 01:01:49.671414 [Byte1]: 45
1084 01:01:49.675669
1085 01:01:49.676089 Set Vref, RX VrefLevel [Byte0]: 46
1086 01:01:49.679025 [Byte1]: 46
1087 01:01:49.683520
1088 01:01:49.683936 Set Vref, RX VrefLevel [Byte0]: 47
1089 01:01:49.686208 [Byte1]: 47
1090 01:01:49.690662
1091 01:01:49.693826 Set Vref, RX VrefLevel [Byte0]: 48
1092 01:01:49.694263 [Byte1]: 48
1093 01:01:49.698337
1094 01:01:49.698760 Set Vref, RX VrefLevel [Byte0]: 49
1095 01:01:49.701490 [Byte1]: 49
1096 01:01:49.706176
1097 01:01:49.706709 Set Vref, RX VrefLevel [Byte0]: 50
1098 01:01:49.709259 [Byte1]: 50
1099 01:01:49.713773
1100 01:01:49.714194 Set Vref, RX VrefLevel [Byte0]: 51
1101 01:01:49.716841 [Byte1]: 51
1102 01:01:49.721260
1103 01:01:49.721680 Set Vref, RX VrefLevel [Byte0]: 52
1104 01:01:49.724385 [Byte1]: 52
1105 01:01:49.728918
1106 01:01:49.729371 Set Vref, RX VrefLevel [Byte0]: 53
1107 01:01:49.731946 [Byte1]: 53
1108 01:01:49.736658
1109 01:01:49.737076 Set Vref, RX VrefLevel [Byte0]: 54
1110 01:01:49.739453 [Byte1]: 54
1111 01:01:49.743823
1112 01:01:49.744243 Set Vref, RX VrefLevel [Byte0]: 55
1113 01:01:49.747066 [Byte1]: 55
1114 01:01:49.751422
1115 01:01:49.751857 Set Vref, RX VrefLevel [Byte0]: 56
1116 01:01:49.754735 [Byte1]: 56
1117 01:01:49.759358
1118 01:01:49.760085 Set Vref, RX VrefLevel [Byte0]: 57
1119 01:01:49.762747 [Byte1]: 57
1120 01:01:49.766689
1121 01:01:49.767108 Set Vref, RX VrefLevel [Byte0]: 58
1122 01:01:49.770116 [Byte1]: 58
1123 01:01:49.774493
1124 01:01:49.774917 Set Vref, RX VrefLevel [Byte0]: 59
1125 01:01:49.777902 [Byte1]: 59
1126 01:01:49.782246
1127 01:01:49.782741 Set Vref, RX VrefLevel [Byte0]: 60
1128 01:01:49.785733 [Byte1]: 60
1129 01:01:49.789970
1130 01:01:49.790487 Set Vref, RX VrefLevel [Byte0]: 61
1131 01:01:49.792911 [Byte1]: 61
1132 01:01:49.797402
1133 01:01:49.797864 Set Vref, RX VrefLevel [Byte0]: 62
1134 01:01:49.800627 [Byte1]: 62
1135 01:01:49.804887
1136 01:01:49.805303 Set Vref, RX VrefLevel [Byte0]: 63
1137 01:01:49.807685 [Byte1]: 63
1138 01:01:49.812000
1139 01:01:49.812478 Set Vref, RX VrefLevel [Byte0]: 64
1140 01:01:49.815432 [Byte1]: 64
1141 01:01:49.819941
1142 01:01:49.820519 Set Vref, RX VrefLevel [Byte0]: 65
1143 01:01:49.823197 [Byte1]: 65
1144 01:01:49.827726
1145 01:01:49.828147 Set Vref, RX VrefLevel [Byte0]: 66
1146 01:01:49.831043 [Byte1]: 66
1147 01:01:49.835073
1148 01:01:49.835493 Set Vref, RX VrefLevel [Byte0]: 67
1149 01:01:49.838288 [Byte1]: 67
1150 01:01:49.842807
1151 01:01:49.843226 Set Vref, RX VrefLevel [Byte0]: 68
1152 01:01:49.846123 [Byte1]: 68
1153 01:01:49.850585
1154 01:01:49.851005 Set Vref, RX VrefLevel [Byte0]: 69
1155 01:01:49.853885 [Byte1]: 69
1156 01:01:49.857668
1157 01:01:49.858091 Set Vref, RX VrefLevel [Byte0]: 70
1158 01:01:49.861023 [Byte1]: 70
1159 01:01:49.865377
1160 01:01:49.865800 Set Vref, RX VrefLevel [Byte0]: 71
1161 01:01:49.868660 [Byte1]: 71
1162 01:01:49.873161
1163 01:01:49.873583 Set Vref, RX VrefLevel [Byte0]: 72
1164 01:01:49.876260 [Byte1]: 72
1165 01:01:49.880643
1166 01:01:49.880725 Set Vref, RX VrefLevel [Byte0]: 73
1167 01:01:49.883897 [Byte1]: 73
1168 01:01:49.887735
1169 01:01:49.887820 Set Vref, RX VrefLevel [Byte0]: 74
1170 01:01:49.890982 [Byte1]: 74
1171 01:01:49.895761
1172 01:01:49.895845 Set Vref, RX VrefLevel [Byte0]: 75
1173 01:01:49.898825 [Byte1]: 75
1174 01:01:49.902966
1175 01:01:49.903049 Set Vref, RX VrefLevel [Byte0]: 76
1176 01:01:49.906508 [Byte1]: 76
1177 01:01:49.910754
1178 01:01:49.910832 Set Vref, RX VrefLevel [Byte0]: 77
1179 01:01:49.914272 [Byte1]: 77
1180 01:01:49.918810
1181 01:01:49.919226 Final RX Vref Byte 0 = 57 to rank0
1182 01:01:49.922550 Final RX Vref Byte 1 = 60 to rank0
1183 01:01:49.925257 Final RX Vref Byte 0 = 57 to rank1
1184 01:01:49.928876 Final RX Vref Byte 1 = 60 to rank1==
1185 01:01:49.932206 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 01:01:49.938562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 01:01:49.938984 ==
1188 01:01:49.939318 DQS Delay:
1189 01:01:49.939623 DQS0 = 0, DQS1 = 0
1190 01:01:49.942136 DQM Delay:
1191 01:01:49.942558 DQM0 = 92, DQM1 = 85
1192 01:01:49.945530 DQ Delay:
1193 01:01:49.948737 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1194 01:01:49.949157 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1195 01:01:49.952546 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1196 01:01:49.955753 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1197 01:01:49.959059
1198 01:01:49.959476
1199 01:01:49.965437 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1200 01:01:49.968891 CH0 RK0: MR19=606, MR18=4B41
1201 01:01:49.975315 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1202 01:01:49.975737
1203 01:01:49.979181 ----->DramcWriteLeveling(PI) begin...
1204 01:01:49.979606 ==
1205 01:01:49.982438 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 01:01:49.985503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 01:01:49.986141 ==
1208 01:01:49.989087 Write leveling (Byte 0): 33 => 33
1209 01:01:49.992395 Write leveling (Byte 1): 30 => 30
1210 01:01:49.995606 DramcWriteLeveling(PI) end<-----
1211 01:01:49.996048
1212 01:01:49.996477 ==
1213 01:01:49.998850 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 01:01:50.001878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 01:01:50.002306 ==
1216 01:01:50.005772 [Gating] SW mode calibration
1217 01:01:50.052944 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 01:01:50.053335 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 01:01:50.054004 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 01:01:50.054229 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 01:01:50.054407 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1222 01:01:50.054646 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 01:01:50.054816 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 01:01:50.054979 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 01:01:50.055211 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 01:01:50.055409 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 01:01:50.066356 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 01:01:50.066954 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:01:50.069784 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:01:50.070011 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:01:50.073100 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 01:01:50.079947 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:01:50.083746 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 01:01:50.086795 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 01:01:50.093263 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:01:50.096366 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:01:50.100192 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1238 01:01:50.106619 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:01:50.110072 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:01:50.113247 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 01:01:50.120499 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:01:50.123619 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 01:01:50.127318 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:01:50.133724 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 01:01:50.137296 0 9 8 | B1->B0 | 2c2c 2928 | 0 1 | (0 0) (1 1)
1246 01:01:50.139901 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 01:01:50.146850 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 01:01:50.149799 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 01:01:50.153403 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 01:01:50.159942 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 01:01:50.163322 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 01:01:50.166925 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1253 01:01:50.170228 0 10 8 | B1->B0 | 2727 2b2b | 0 0 | (1 0) (0 0)
1254 01:01:50.176388 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1255 01:01:50.180239 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 01:01:50.183829 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 01:01:50.187803 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 01:01:50.194782 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 01:01:50.198385 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 01:01:50.202434 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1261 01:01:50.204799 0 11 8 | B1->B0 | 3c3c 3939 | 0 0 | (1 1) (1 1)
1262 01:01:50.212451 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 01:01:50.215715 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 01:01:50.218999 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 01:01:50.225611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 01:01:50.228931 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 01:01:50.232277 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 01:01:50.235416 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 01:01:50.242482 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 01:01:50.245561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1271 01:01:50.249287 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 01:01:50.255643 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 01:01:50.258787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 01:01:50.262487 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 01:01:50.269154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 01:01:50.272324 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 01:01:50.275581 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 01:01:50.282712 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 01:01:50.285795 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 01:01:50.289365 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 01:01:50.295899 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 01:01:50.299260 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 01:01:50.302248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 01:01:50.309278 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 01:01:50.312626 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 01:01:50.315803 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1287 01:01:50.318994 Total UI for P1: 0, mck2ui 16
1288 01:01:50.322299 best dqsien dly found for B1: ( 0, 14, 8)
1289 01:01:50.326528 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 01:01:50.329988 Total UI for P1: 0, mck2ui 16
1291 01:01:50.332793 best dqsien dly found for B0: ( 0, 14, 8)
1292 01:01:50.335980 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1293 01:01:50.339857 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1294 01:01:50.342993
1295 01:01:50.346393 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 01:01:50.349920 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 01:01:50.353378 [Gating] SW calibration Done
1298 01:01:50.353959 ==
1299 01:01:50.356447 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 01:01:50.359719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 01:01:50.360351 ==
1302 01:01:50.360771 RX Vref Scan: 0
1303 01:01:50.361120
1304 01:01:50.363137 RX Vref 0 -> 0, step: 1
1305 01:01:50.363600
1306 01:01:50.366084 RX Delay -130 -> 252, step: 16
1307 01:01:50.370123 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1308 01:01:50.373162 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1309 01:01:50.376314 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1310 01:01:50.383329 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1311 01:01:50.386710 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1312 01:01:50.389882 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1313 01:01:50.393010 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1314 01:01:50.396584 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1315 01:01:50.403296 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1316 01:01:50.406262 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1317 01:01:50.409938 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1318 01:01:50.413015 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1319 01:01:50.416094 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1320 01:01:50.423081 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1321 01:01:50.426505 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1322 01:01:50.429957 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1323 01:01:50.430460 ==
1324 01:01:50.433188 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 01:01:50.436434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 01:01:50.439475 ==
1327 01:01:50.439941 DQS Delay:
1328 01:01:50.440486 DQS0 = 0, DQS1 = 0
1329 01:01:50.442965 DQM Delay:
1330 01:01:50.443384 DQM0 = 91, DQM1 = 82
1331 01:01:50.443721 DQ Delay:
1332 01:01:50.446654 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1333 01:01:50.449487 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1334 01:01:50.452875 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1335 01:01:50.456833 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1336 01:01:50.457255
1337 01:01:50.457588
1338 01:01:50.459867 ==
1339 01:01:50.462980 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 01:01:50.466712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 01:01:50.467175 ==
1342 01:01:50.467518
1343 01:01:50.467833
1344 01:01:50.469807 TX Vref Scan disable
1345 01:01:50.470241 == TX Byte 0 ==
1346 01:01:50.476125 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1347 01:01:50.479535 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1348 01:01:50.479962 == TX Byte 1 ==
1349 01:01:50.486048 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1350 01:01:50.490021 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1351 01:01:50.490548 ==
1352 01:01:50.493106 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 01:01:50.495775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 01:01:50.496198 ==
1355 01:01:50.510165 TX Vref=22, minBit 10, minWin=27, winSum=450
1356 01:01:50.513452 TX Vref=24, minBit 12, minWin=27, winSum=448
1357 01:01:50.516689 TX Vref=26, minBit 1, minWin=28, winSum=457
1358 01:01:50.519979 TX Vref=28, minBit 2, minWin=28, winSum=456
1359 01:01:50.523335 TX Vref=30, minBit 1, minWin=28, winSum=455
1360 01:01:50.529773 TX Vref=32, minBit 12, minWin=27, winSum=452
1361 01:01:50.533363 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 26
1362 01:01:50.533785
1363 01:01:50.536722 Final TX Range 1 Vref 26
1364 01:01:50.537144
1365 01:01:50.537473 ==
1366 01:01:50.539590 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 01:01:50.543207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 01:01:50.543630 ==
1369 01:01:50.546451
1370 01:01:50.546900
1371 01:01:50.547237 TX Vref Scan disable
1372 01:01:50.550042 == TX Byte 0 ==
1373 01:01:50.553093 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1374 01:01:50.559617 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1375 01:01:50.560033 == TX Byte 1 ==
1376 01:01:50.563140 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1377 01:01:50.569833 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1378 01:01:50.570231
1379 01:01:50.570584 [DATLAT]
1380 01:01:50.570940 Freq=800, CH0 RK1
1381 01:01:50.571222
1382 01:01:50.575905 DATLAT Default: 0xa
1383 01:01:50.576213 0, 0xFFFF, sum = 0
1384 01:01:50.576773 1, 0xFFFF, sum = 0
1385 01:01:50.577024 2, 0xFFFF, sum = 0
1386 01:01:50.579371 3, 0xFFFF, sum = 0
1387 01:01:50.582951 4, 0xFFFF, sum = 0
1388 01:01:50.583334 5, 0xFFFF, sum = 0
1389 01:01:50.586482 6, 0xFFFF, sum = 0
1390 01:01:50.586709 7, 0xFFFF, sum = 0
1391 01:01:50.589783 8, 0xFFFF, sum = 0
1392 01:01:50.589973 9, 0x0, sum = 1
1393 01:01:50.593003 10, 0x0, sum = 2
1394 01:01:50.593186 11, 0x0, sum = 3
1395 01:01:50.593331 12, 0x0, sum = 4
1396 01:01:50.596375 best_step = 10
1397 01:01:50.596554
1398 01:01:50.596786 ==
1399 01:01:50.599946 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 01:01:50.603069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 01:01:50.603320 ==
1402 01:01:50.606368 RX Vref Scan: 0
1403 01:01:50.606618
1404 01:01:50.606838 RX Vref 0 -> 0, step: 1
1405 01:01:50.607049
1406 01:01:50.609595 RX Delay -95 -> 252, step: 8
1407 01:01:50.616760 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1408 01:01:50.620060 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1409 01:01:50.623422 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1410 01:01:50.626687 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1411 01:01:50.629977 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1412 01:01:50.636604 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1413 01:01:50.639719 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1414 01:01:50.642953 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 01:01:50.646411 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1416 01:01:50.649673 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1417 01:01:50.656078 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1418 01:01:50.659426 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1419 01:01:50.663230 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1420 01:01:50.665999 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1421 01:01:50.669618 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 01:01:50.676271 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1423 01:01:50.676401 ==
1424 01:01:50.679530 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 01:01:50.682656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 01:01:50.682763 ==
1427 01:01:50.682859 DQS Delay:
1428 01:01:50.686072 DQS0 = 0, DQS1 = 0
1429 01:01:50.686152 DQM Delay:
1430 01:01:50.689520 DQM0 = 93, DQM1 = 83
1431 01:01:50.689601 DQ Delay:
1432 01:01:50.692800 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1433 01:01:50.696517 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1434 01:01:50.699517 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1435 01:01:50.703097 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1436 01:01:50.703203
1437 01:01:50.703298
1438 01:01:50.713121 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1439 01:01:50.713224 CH0 RK1: MR19=606, MR18=3F10
1440 01:01:50.719878 CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63
1441 01:01:50.722987 [RxdqsGatingPostProcess] freq 800
1442 01:01:50.729596 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 01:01:50.733105 Pre-setting of DQS Precalculation
1444 01:01:50.736312 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 01:01:50.736428 ==
1446 01:01:50.739613 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 01:01:50.742854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 01:01:50.742965 ==
1449 01:01:50.749726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 01:01:50.756653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 01:01:50.765258 [CA 0] Center 36 (6~67) winsize 62
1452 01:01:50.768413 [CA 1] Center 36 (6~67) winsize 62
1453 01:01:50.771715 [CA 2] Center 35 (4~66) winsize 63
1454 01:01:50.775069 [CA 3] Center 34 (4~65) winsize 62
1455 01:01:50.778835 [CA 4] Center 35 (5~65) winsize 61
1456 01:01:50.781986 [CA 5] Center 34 (4~65) winsize 62
1457 01:01:50.782423
1458 01:01:50.785520 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 01:01:50.785941
1460 01:01:50.788209 [CATrainingPosCal] consider 1 rank data
1461 01:01:50.791614 u2DelayCellTimex100 = 270/100 ps
1462 01:01:50.795237 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 01:01:50.798447 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 01:01:50.805117 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1465 01:01:50.808329 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 01:01:50.811617 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1467 01:01:50.814848 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 01:01:50.815221
1469 01:01:50.818317 CA PerBit enable=1, Macro0, CA PI delay=34
1470 01:01:50.818660
1471 01:01:50.821844 [CBTSetCACLKResult] CA Dly = 34
1472 01:01:50.822179 CS Dly: 6 (0~37)
1473 01:01:50.822419 ==
1474 01:01:50.825283 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 01:01:50.832151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 01:01:50.832489 ==
1477 01:01:50.834959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 01:01:50.841665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 01:01:50.851417 [CA 0] Center 36 (6~67) winsize 62
1480 01:01:50.855234 [CA 1] Center 37 (6~68) winsize 63
1481 01:01:50.859070 [CA 2] Center 35 (5~66) winsize 62
1482 01:01:50.862446 [CA 3] Center 34 (4~65) winsize 62
1483 01:01:50.866420 [CA 4] Center 35 (5~66) winsize 62
1484 01:01:50.870345 [CA 5] Center 34 (4~65) winsize 62
1485 01:01:50.870646
1486 01:01:50.873624 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1487 01:01:50.873923
1488 01:01:50.877602 [CATrainingPosCal] consider 2 rank data
1489 01:01:50.877903 u2DelayCellTimex100 = 270/100 ps
1490 01:01:50.880991 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 01:01:50.884844 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 01:01:50.891432 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1493 01:01:50.894609 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 01:01:50.897769 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1495 01:01:50.901100 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 01:01:50.901401
1497 01:01:50.904622 CA PerBit enable=1, Macro0, CA PI delay=34
1498 01:01:50.904922
1499 01:01:50.907654 [CBTSetCACLKResult] CA Dly = 34
1500 01:01:50.907952 CS Dly: 6 (0~38)
1501 01:01:50.908192
1502 01:01:50.911514 ----->DramcWriteLeveling(PI) begin...
1503 01:01:50.911817 ==
1504 01:01:50.914745 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 01:01:50.921539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 01:01:50.921843 ==
1507 01:01:50.924892 Write leveling (Byte 0): 27 => 27
1508 01:01:50.927971 Write leveling (Byte 1): 25 => 25
1509 01:01:50.928270 DramcWriteLeveling(PI) end<-----
1510 01:01:50.931202
1511 01:01:50.931498 ==
1512 01:01:50.934853 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 01:01:50.937983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 01:01:50.938287 ==
1515 01:01:50.941192 [Gating] SW mode calibration
1516 01:01:50.948315 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 01:01:50.951555 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 01:01:50.958131 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 01:01:50.961523 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 01:01:50.964900 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 01:01:50.971623 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 01:01:50.974409 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 01:01:50.978675 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 01:01:50.984705 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 01:01:50.988224 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 01:01:50.991107 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:01:50.998337 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:01:51.001572 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:01:51.004712 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:01:51.008026 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:01:51.015102 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:01:51.018131 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:01:51.021796 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 01:01:51.028135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 01:01:51.031336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1536 01:01:51.034803 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:01:51.041441 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:01:51.044963 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:01:51.047867 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:01:51.055165 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:01:51.058294 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 01:01:51.061625 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:01:51.068248 0 9 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1544 01:01:51.071347 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1545 01:01:51.074619 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 01:01:51.081211 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 01:01:51.084932 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 01:01:51.088085 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 01:01:51.091476 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 01:01:51.098239 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1551 01:01:51.101772 0 10 4 | B1->B0 | 3030 2b2b | 0 1 | (0 1) (1 0)
1552 01:01:51.104817 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1553 01:01:51.111434 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:01:51.114844 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:01:51.118081 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 01:01:51.124763 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 01:01:51.128083 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 01:01:51.131529 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 01:01:51.138061 0 11 4 | B1->B0 | 2a2a 3838 | 0 1 | (1 1) (0 0)
1560 01:01:51.141232 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1561 01:01:51.144755 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 01:01:51.151131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 01:01:51.154321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 01:01:51.157935 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 01:01:51.164743 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 01:01:51.168036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 01:01:51.171345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 01:01:51.177967 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 01:01:51.181039 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 01:01:51.184965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 01:01:51.187896 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 01:01:51.194552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 01:01:51.198408 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 01:01:51.201766 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 01:01:51.208114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 01:01:51.211376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 01:01:51.214575 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 01:01:51.221802 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 01:01:51.224867 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 01:01:51.228233 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 01:01:51.234808 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 01:01:51.238207 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 01:01:51.241515 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 01:01:51.248204 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 01:01:51.248297 Total UI for P1: 0, mck2ui 16
1586 01:01:51.251831 best dqsien dly found for B0: ( 0, 14, 4)
1587 01:01:51.254959 Total UI for P1: 0, mck2ui 16
1588 01:01:51.258096 best dqsien dly found for B1: ( 0, 14, 4)
1589 01:01:51.262115 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1590 01:01:51.265057 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1591 01:01:51.268357
1592 01:01:51.272022 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 01:01:51.275296 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 01:01:51.278698 [Gating] SW calibration Done
1595 01:01:51.278810 ==
1596 01:01:51.281639 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 01:01:51.284767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 01:01:51.284866 ==
1599 01:01:51.284955 RX Vref Scan: 0
1600 01:01:51.285020
1601 01:01:51.288435 RX Vref 0 -> 0, step: 1
1602 01:01:51.288574
1603 01:01:51.291445 RX Delay -130 -> 252, step: 16
1604 01:01:51.295171 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1605 01:01:51.298360 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1606 01:01:51.304726 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 01:01:51.308803 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1608 01:01:51.311998 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1609 01:01:51.315219 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1610 01:01:51.318436 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1611 01:01:51.324932 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1612 01:01:51.328206 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1613 01:01:51.331570 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1614 01:01:51.334794 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1615 01:01:51.338705 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1616 01:01:51.345335 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1617 01:01:51.348543 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1618 01:01:51.351696 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1619 01:01:51.355396 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1620 01:01:51.355495 ==
1621 01:01:51.358369 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 01:01:51.361656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 01:01:51.365007 ==
1624 01:01:51.365108 DQS Delay:
1625 01:01:51.365170 DQS0 = 0, DQS1 = 0
1626 01:01:51.368588 DQM Delay:
1627 01:01:51.368697 DQM0 = 93, DQM1 = 89
1628 01:01:51.371661 DQ Delay:
1629 01:01:51.374939 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1630 01:01:51.375101 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1631 01:01:51.378453 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1632 01:01:51.385024 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1633 01:01:51.385104
1634 01:01:51.385167
1635 01:01:51.385225 ==
1636 01:01:51.388111 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 01:01:51.391838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 01:01:51.391938 ==
1639 01:01:51.392029
1640 01:01:51.392115
1641 01:01:51.395070 TX Vref Scan disable
1642 01:01:51.395170 == TX Byte 0 ==
1643 01:01:51.401796 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 01:01:51.404991 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 01:01:51.405060 == TX Byte 1 ==
1646 01:01:51.411493 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1647 01:01:51.414914 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1648 01:01:51.414998 ==
1649 01:01:51.418810 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 01:01:51.421852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 01:01:51.421936 ==
1652 01:01:51.435656 TX Vref=22, minBit 0, minWin=26, winSum=429
1653 01:01:51.439070 TX Vref=24, minBit 1, minWin=26, winSum=435
1654 01:01:51.442268 TX Vref=26, minBit 1, minWin=27, winSum=442
1655 01:01:51.445614 TX Vref=28, minBit 1, minWin=27, winSum=444
1656 01:01:51.449458 TX Vref=30, minBit 2, minWin=26, winSum=445
1657 01:01:51.452722 TX Vref=32, minBit 2, minWin=26, winSum=439
1658 01:01:51.459061 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
1659 01:01:51.459142
1660 01:01:51.462355 Final TX Range 1 Vref 28
1661 01:01:51.462430
1662 01:01:51.462493 ==
1663 01:01:51.465615 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 01:01:51.469042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 01:01:51.469120 ==
1666 01:01:51.469183
1667 01:01:51.469243
1668 01:01:51.472829 TX Vref Scan disable
1669 01:01:51.475757 == TX Byte 0 ==
1670 01:01:51.479363 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 01:01:51.482468 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 01:01:51.485621 == TX Byte 1 ==
1673 01:01:51.489292 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1674 01:01:51.492224 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1675 01:01:51.496166
1676 01:01:51.496270 [DATLAT]
1677 01:01:51.496353 Freq=800, CH1 RK0
1678 01:01:51.496424
1679 01:01:51.498759 DATLAT Default: 0xa
1680 01:01:51.498873 0, 0xFFFF, sum = 0
1681 01:01:51.502298 1, 0xFFFF, sum = 0
1682 01:01:51.502383 2, 0xFFFF, sum = 0
1683 01:01:51.505554 3, 0xFFFF, sum = 0
1684 01:01:51.505665 4, 0xFFFF, sum = 0
1685 01:01:51.509522 5, 0xFFFF, sum = 0
1686 01:01:51.509638 6, 0xFFFF, sum = 0
1687 01:01:51.512458 7, 0xFFFF, sum = 0
1688 01:01:51.516006 8, 0xFFFF, sum = 0
1689 01:01:51.516118 9, 0x0, sum = 1
1690 01:01:51.516217 10, 0x0, sum = 2
1691 01:01:51.519369 11, 0x0, sum = 3
1692 01:01:51.519479 12, 0x0, sum = 4
1693 01:01:51.522531 best_step = 10
1694 01:01:51.522642
1695 01:01:51.522751 ==
1696 01:01:51.526087 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 01:01:51.529315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 01:01:51.529398 ==
1699 01:01:51.532714 RX Vref Scan: 1
1700 01:01:51.532823
1701 01:01:51.532917 Set Vref Range= 32 -> 127
1702 01:01:51.533007
1703 01:01:51.536492 RX Vref 32 -> 127, step: 1
1704 01:01:51.536564
1705 01:01:51.539173 RX Delay -79 -> 252, step: 8
1706 01:01:51.539245
1707 01:01:51.542896 Set Vref, RX VrefLevel [Byte0]: 32
1708 01:01:51.546055 [Byte1]: 32
1709 01:01:51.546153
1710 01:01:51.549363 Set Vref, RX VrefLevel [Byte0]: 33
1711 01:01:51.552659 [Byte1]: 33
1712 01:01:51.555771
1713 01:01:51.555871 Set Vref, RX VrefLevel [Byte0]: 34
1714 01:01:51.559015 [Byte1]: 34
1715 01:01:51.563549
1716 01:01:51.563626 Set Vref, RX VrefLevel [Byte0]: 35
1717 01:01:51.566887 [Byte1]: 35
1718 01:01:51.570668
1719 01:01:51.570770 Set Vref, RX VrefLevel [Byte0]: 36
1720 01:01:51.574274 [Byte1]: 36
1721 01:01:51.579032
1722 01:01:51.579134 Set Vref, RX VrefLevel [Byte0]: 37
1723 01:01:51.581996 [Byte1]: 37
1724 01:01:51.586291
1725 01:01:51.586393 Set Vref, RX VrefLevel [Byte0]: 38
1726 01:01:51.589289 [Byte1]: 38
1727 01:01:51.593766
1728 01:01:51.593866 Set Vref, RX VrefLevel [Byte0]: 39
1729 01:01:51.596882 [Byte1]: 39
1730 01:01:51.601369
1731 01:01:51.601445 Set Vref, RX VrefLevel [Byte0]: 40
1732 01:01:51.604539 [Byte1]: 40
1733 01:01:51.608781
1734 01:01:51.608865 Set Vref, RX VrefLevel [Byte0]: 41
1735 01:01:51.612103 [Byte1]: 41
1736 01:01:51.616084
1737 01:01:51.616192 Set Vref, RX VrefLevel [Byte0]: 42
1738 01:01:51.619421 [Byte1]: 42
1739 01:01:51.624185
1740 01:01:51.624272 Set Vref, RX VrefLevel [Byte0]: 43
1741 01:01:51.626966 [Byte1]: 43
1742 01:01:51.631176
1743 01:01:51.631280 Set Vref, RX VrefLevel [Byte0]: 44
1744 01:01:51.634946 [Byte1]: 44
1745 01:01:51.638724
1746 01:01:51.638806 Set Vref, RX VrefLevel [Byte0]: 45
1747 01:01:51.642289 [Byte1]: 45
1748 01:01:51.646798
1749 01:01:51.646897 Set Vref, RX VrefLevel [Byte0]: 46
1750 01:01:51.650055 [Byte1]: 46
1751 01:01:51.654419
1752 01:01:51.654502 Set Vref, RX VrefLevel [Byte0]: 47
1753 01:01:51.657700 [Byte1]: 47
1754 01:01:51.661348
1755 01:01:51.661433 Set Vref, RX VrefLevel [Byte0]: 48
1756 01:01:51.665037 [Byte1]: 48
1757 01:01:51.668935
1758 01:01:51.669054 Set Vref, RX VrefLevel [Byte0]: 49
1759 01:01:51.672861 [Byte1]: 49
1760 01:01:51.676680
1761 01:01:51.676777 Set Vref, RX VrefLevel [Byte0]: 50
1762 01:01:51.679866 [Byte1]: 50
1763 01:01:51.684412
1764 01:01:51.684493 Set Vref, RX VrefLevel [Byte0]: 51
1765 01:01:51.687626 [Byte1]: 51
1766 01:01:51.691990
1767 01:01:51.692071 Set Vref, RX VrefLevel [Byte0]: 52
1768 01:01:51.694950 [Byte1]: 52
1769 01:01:51.699565
1770 01:01:51.699647 Set Vref, RX VrefLevel [Byte0]: 53
1771 01:01:51.702809 [Byte1]: 53
1772 01:01:51.706892
1773 01:01:51.706999 Set Vref, RX VrefLevel [Byte0]: 54
1774 01:01:51.710146 [Byte1]: 54
1775 01:01:51.714213
1776 01:01:51.714287 Set Vref, RX VrefLevel [Byte0]: 55
1777 01:01:51.717452 [Byte1]: 55
1778 01:01:51.722080
1779 01:01:51.722154 Set Vref, RX VrefLevel [Byte0]: 56
1780 01:01:51.724997 [Byte1]: 56
1781 01:01:51.729592
1782 01:01:51.729671 Set Vref, RX VrefLevel [Byte0]: 57
1783 01:01:51.732703 [Byte1]: 57
1784 01:01:51.736690
1785 01:01:51.736802 Set Vref, RX VrefLevel [Byte0]: 58
1786 01:01:51.740195 [Byte1]: 58
1787 01:01:51.744838
1788 01:01:51.744919 Set Vref, RX VrefLevel [Byte0]: 59
1789 01:01:51.748085 [Byte1]: 59
1790 01:01:51.751868
1791 01:01:51.751975 Set Vref, RX VrefLevel [Byte0]: 60
1792 01:01:51.755542 [Byte1]: 60
1793 01:01:51.759756
1794 01:01:51.759836 Set Vref, RX VrefLevel [Byte0]: 61
1795 01:01:51.762751 [Byte1]: 61
1796 01:01:51.767550
1797 01:01:51.767631 Set Vref, RX VrefLevel [Byte0]: 62
1798 01:01:51.770653 [Byte1]: 62
1799 01:01:51.774633
1800 01:01:51.774784 Set Vref, RX VrefLevel [Byte0]: 63
1801 01:01:51.777806 [Byte1]: 63
1802 01:01:51.782474
1803 01:01:51.782602 Set Vref, RX VrefLevel [Byte0]: 64
1804 01:01:51.785660 [Byte1]: 64
1805 01:01:51.790319
1806 01:01:51.790421 Set Vref, RX VrefLevel [Byte0]: 65
1807 01:01:51.793498 [Byte1]: 65
1808 01:01:51.797306
1809 01:01:51.797388 Set Vref, RX VrefLevel [Byte0]: 66
1810 01:01:51.801011 [Byte1]: 66
1811 01:01:51.804808
1812 01:01:51.804898 Set Vref, RX VrefLevel [Byte0]: 67
1813 01:01:51.808264 [Byte1]: 67
1814 01:01:51.812192
1815 01:01:51.812319 Set Vref, RX VrefLevel [Byte0]: 68
1816 01:01:51.815502 [Byte1]: 68
1817 01:01:51.820020
1818 01:01:51.820102 Set Vref, RX VrefLevel [Byte0]: 69
1819 01:01:51.823241 [Byte1]: 69
1820 01:01:51.827751
1821 01:01:51.827832 Set Vref, RX VrefLevel [Byte0]: 70
1822 01:01:51.830883 [Byte1]: 70
1823 01:01:51.835288
1824 01:01:51.835369 Final RX Vref Byte 0 = 57 to rank0
1825 01:01:51.838476 Final RX Vref Byte 1 = 57 to rank0
1826 01:01:51.841572 Final RX Vref Byte 0 = 57 to rank1
1827 01:01:51.845555 Final RX Vref Byte 1 = 57 to rank1==
1828 01:01:51.848619 Dram Type= 6, Freq= 0, CH_1, rank 0
1829 01:01:51.855076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1830 01:01:51.855178 ==
1831 01:01:51.855269 DQS Delay:
1832 01:01:51.855357 DQS0 = 0, DQS1 = 0
1833 01:01:51.858287 DQM Delay:
1834 01:01:51.858396 DQM0 = 96, DQM1 = 89
1835 01:01:51.861761 DQ Delay:
1836 01:01:51.865329 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1837 01:01:51.868340 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1838 01:01:51.871952 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1839 01:01:51.875593 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1840 01:01:51.875674
1841 01:01:51.875738
1842 01:01:51.881966 [DQSOSCAuto] RK0, (LSB)MR18= 0x2946, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1843 01:01:51.885431 CH1 RK0: MR19=606, MR18=2946
1844 01:01:51.892077 CH1_RK0: MR19=0x606, MR18=0x2946, DQSOSC=392, MR23=63, INC=96, DEC=64
1845 01:01:51.892159
1846 01:01:51.895516 ----->DramcWriteLeveling(PI) begin...
1847 01:01:51.895627 ==
1848 01:01:51.898578 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 01:01:51.902184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 01:01:51.902269 ==
1851 01:01:51.905555 Write leveling (Byte 0): 29 => 29
1852 01:01:51.908734 Write leveling (Byte 1): 29 => 29
1853 01:01:51.912238 DramcWriteLeveling(PI) end<-----
1854 01:01:51.912376
1855 01:01:51.912459 ==
1856 01:01:51.915170 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 01:01:51.918954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 01:01:51.919038 ==
1859 01:01:51.922290 [Gating] SW mode calibration
1860 01:01:51.928782 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1861 01:01:51.935322 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1862 01:01:51.938600 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1863 01:01:51.942500 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1864 01:01:51.948526 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 01:01:51.952264 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 01:01:51.955454 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 01:01:51.962058 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 01:01:51.965192 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 01:01:51.969010 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 01:01:51.975586 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 01:01:51.978812 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 01:01:51.982020 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 01:01:51.985604 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 01:01:51.992067 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 01:01:51.995628 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 01:01:51.998971 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 01:01:52.005506 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 01:01:52.009014 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1879 01:01:52.012185 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1880 01:01:52.018948 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:01:52.022043 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:01:52.025598 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:01:52.032437 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:01:52.035401 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:01:52.038858 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 01:01:52.045483 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 01:01:52.048764 0 9 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
1888 01:01:52.052400 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1889 01:01:52.058799 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 01:01:52.062502 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 01:01:52.065735 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 01:01:52.069487 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 01:01:52.076010 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 01:01:52.079155 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1895 01:01:52.082418 0 10 4 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 1)
1896 01:01:52.089157 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
1897 01:01:52.092244 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 01:01:52.095636 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 01:01:52.102555 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 01:01:52.105806 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 01:01:52.108916 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 01:01:52.116092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 01:01:52.119272 0 11 4 | B1->B0 | 3838 2b2b | 0 1 | (0 0) (0 0)
1904 01:01:52.122691 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1905 01:01:52.129211 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 01:01:52.132486 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 01:01:52.136172 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 01:01:52.139441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 01:01:52.146211 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 01:01:52.149493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1911 01:01:52.153007 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1912 01:01:52.159606 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 01:01:52.162736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 01:01:52.166075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 01:01:52.172760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 01:01:52.176569 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 01:01:52.179762 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 01:01:52.186699 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 01:01:52.189827 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 01:01:52.192847 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 01:01:52.196731 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 01:01:52.202949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 01:01:52.206776 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 01:01:52.209957 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 01:01:52.216372 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 01:01:52.220027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 01:01:52.223133 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1928 01:01:52.226213 Total UI for P1: 0, mck2ui 16
1929 01:01:52.229724 best dqsien dly found for B1: ( 0, 14, 2)
1930 01:01:52.236478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 01:01:52.236563 Total UI for P1: 0, mck2ui 16
1932 01:01:52.243056 best dqsien dly found for B0: ( 0, 14, 4)
1933 01:01:52.246835 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1934 01:01:52.250050 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1935 01:01:52.250134
1936 01:01:52.253886 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1937 01:01:52.256547 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1938 01:01:52.260446 [Gating] SW calibration Done
1939 01:01:52.260530 ==
1940 01:01:52.263602 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 01:01:52.266738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 01:01:52.266822 ==
1943 01:01:52.266922 RX Vref Scan: 0
1944 01:01:52.270548
1945 01:01:52.270631 RX Vref 0 -> 0, step: 1
1946 01:01:52.270715
1947 01:01:52.273649 RX Delay -130 -> 252, step: 16
1948 01:01:52.277135 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1949 01:01:52.280246 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1950 01:01:52.286838 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1951 01:01:52.290438 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1952 01:01:52.293652 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1953 01:01:52.296853 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1954 01:01:52.300223 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1955 01:01:52.307127 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1956 01:01:52.310283 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1957 01:01:52.313424 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1958 01:01:52.316723 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1959 01:01:52.319975 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1960 01:01:52.326758 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1961 01:01:52.329964 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1962 01:01:52.333849 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1963 01:01:52.337081 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1964 01:01:52.337166 ==
1965 01:01:52.340247 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 01:01:52.343795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 01:01:52.347318 ==
1968 01:01:52.347402 DQS Delay:
1969 01:01:52.347489 DQS0 = 0, DQS1 = 0
1970 01:01:52.350523 DQM Delay:
1971 01:01:52.350608 DQM0 = 92, DQM1 = 87
1972 01:01:52.353732 DQ Delay:
1973 01:01:52.357067 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1974 01:01:52.357152 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1975 01:01:52.360297 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1976 01:01:52.364093 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1977 01:01:52.367253
1978 01:01:52.367337
1979 01:01:52.367422 ==
1980 01:01:52.370496 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 01:01:52.373692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 01:01:52.373777 ==
1983 01:01:52.373863
1984 01:01:52.373943
1985 01:01:52.376867 TX Vref Scan disable
1986 01:01:52.376952 == TX Byte 0 ==
1987 01:01:52.383990 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1988 01:01:52.387198 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1989 01:01:52.387282 == TX Byte 1 ==
1990 01:01:52.393693 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 01:01:52.397561 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 01:01:52.397646 ==
1993 01:01:52.400708 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 01:01:52.403774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 01:01:52.403858 ==
1996 01:01:52.417178 TX Vref=22, minBit 2, minWin=27, winSum=446
1997 01:01:52.420790 TX Vref=24, minBit 0, minWin=27, winSum=448
1998 01:01:52.424171 TX Vref=26, minBit 2, minWin=27, winSum=450
1999 01:01:52.427645 TX Vref=28, minBit 2, minWin=27, winSum=450
2000 01:01:52.430676 TX Vref=30, minBit 0, minWin=27, winSum=450
2001 01:01:52.433947 TX Vref=32, minBit 0, minWin=27, winSum=450
2002 01:01:52.440672 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 26
2003 01:01:52.440758
2004 01:01:52.444292 Final TX Range 1 Vref 26
2005 01:01:52.444405
2006 01:01:52.444467 ==
2007 01:01:52.447599 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 01:01:52.450826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 01:01:52.450900 ==
2010 01:01:52.450960
2011 01:01:52.451018
2012 01:01:52.454017 TX Vref Scan disable
2013 01:01:52.457660 == TX Byte 0 ==
2014 01:01:52.460716 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2015 01:01:52.464665 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2016 01:01:52.467732 == TX Byte 1 ==
2017 01:01:52.471037 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2018 01:01:52.474259 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2019 01:01:52.474332
2020 01:01:52.477369 [DATLAT]
2021 01:01:52.477439 Freq=800, CH1 RK1
2022 01:01:52.477499
2023 01:01:52.481198 DATLAT Default: 0xa
2024 01:01:52.481267 0, 0xFFFF, sum = 0
2025 01:01:52.484324 1, 0xFFFF, sum = 0
2026 01:01:52.484407 2, 0xFFFF, sum = 0
2027 01:01:52.487553 3, 0xFFFF, sum = 0
2028 01:01:52.487623 4, 0xFFFF, sum = 0
2029 01:01:52.491089 5, 0xFFFF, sum = 0
2030 01:01:52.491162 6, 0xFFFF, sum = 0
2031 01:01:52.494181 7, 0xFFFF, sum = 0
2032 01:01:52.494255 8, 0xFFFF, sum = 0
2033 01:01:52.497380 9, 0x0, sum = 1
2034 01:01:52.497455 10, 0x0, sum = 2
2035 01:01:52.501218 11, 0x0, sum = 3
2036 01:01:52.501292 12, 0x0, sum = 4
2037 01:01:52.504344 best_step = 10
2038 01:01:52.504426
2039 01:01:52.504490 ==
2040 01:01:52.507736 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 01:01:52.511019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 01:01:52.511091 ==
2043 01:01:52.514269 RX Vref Scan: 0
2044 01:01:52.514338
2045 01:01:52.514399 RX Vref 0 -> 0, step: 1
2046 01:01:52.514457
2047 01:01:52.517882 RX Delay -79 -> 252, step: 8
2048 01:01:52.524276 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2049 01:01:52.527641 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2050 01:01:52.530864 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2051 01:01:52.534478 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2052 01:01:52.537555 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2053 01:01:52.541138 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2054 01:01:52.547552 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2055 01:01:52.551358 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2056 01:01:52.554715 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2057 01:01:52.557443 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2058 01:01:52.560956 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2059 01:01:52.564469 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2060 01:01:52.570985 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2061 01:01:52.574480 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2062 01:01:52.577562 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2063 01:01:52.580741 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2064 01:01:52.580813 ==
2065 01:01:52.584214 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 01:01:52.591023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 01:01:52.591104 ==
2068 01:01:52.591166 DQS Delay:
2069 01:01:52.594498 DQS0 = 0, DQS1 = 0
2070 01:01:52.594577 DQM Delay:
2071 01:01:52.594641 DQM0 = 97, DQM1 = 91
2072 01:01:52.597751 DQ Delay:
2073 01:01:52.600848 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2074 01:01:52.604808 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2075 01:01:52.608088 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2076 01:01:52.611334 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2077 01:01:52.611405
2078 01:01:52.611469
2079 01:01:52.617738 [DQSOSCAuto] RK1, (LSB)MR18= 0x420c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2080 01:01:52.621091 CH1 RK1: MR19=606, MR18=420C
2081 01:01:52.627833 CH1_RK1: MR19=0x606, MR18=0x420C, DQSOSC=393, MR23=63, INC=95, DEC=63
2082 01:01:52.631006 [RxdqsGatingPostProcess] freq 800
2083 01:01:52.634297 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 01:01:52.637581 Pre-setting of DQS Precalculation
2085 01:01:52.644734 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 01:01:52.651156 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 01:01:52.658202 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 01:01:52.658284
2089 01:01:52.658347
2090 01:01:52.661252 [Calibration Summary] 1600 Mbps
2091 01:01:52.661335 CH 0, Rank 0
2092 01:01:52.664233 SW Impedance : PASS
2093 01:01:52.668198 DUTY Scan : NO K
2094 01:01:52.668280 ZQ Calibration : PASS
2095 01:01:52.671399 Jitter Meter : NO K
2096 01:01:52.674504 CBT Training : PASS
2097 01:01:52.674591 Write leveling : PASS
2098 01:01:52.678009 RX DQS gating : PASS
2099 01:01:52.678091 RX DQ/DQS(RDDQC) : PASS
2100 01:01:52.681277 TX DQ/DQS : PASS
2101 01:01:52.684486 RX DATLAT : PASS
2102 01:01:52.684581 RX DQ/DQS(Engine): PASS
2103 01:01:52.687919 TX OE : NO K
2104 01:01:52.688001 All Pass.
2105 01:01:52.688065
2106 01:01:52.691537 CH 0, Rank 1
2107 01:01:52.691619 SW Impedance : PASS
2108 01:01:52.694813 DUTY Scan : NO K
2109 01:01:52.697918 ZQ Calibration : PASS
2110 01:01:52.698000 Jitter Meter : NO K
2111 01:01:52.701203 CBT Training : PASS
2112 01:01:52.704999 Write leveling : PASS
2113 01:01:52.705083 RX DQS gating : PASS
2114 01:01:52.708273 RX DQ/DQS(RDDQC) : PASS
2115 01:01:52.711362 TX DQ/DQS : PASS
2116 01:01:52.711453 RX DATLAT : PASS
2117 01:01:52.714950 RX DQ/DQS(Engine): PASS
2118 01:01:52.715033 TX OE : NO K
2119 01:01:52.717922 All Pass.
2120 01:01:52.718006
2121 01:01:52.718091 CH 1, Rank 0
2122 01:01:52.721817 SW Impedance : PASS
2123 01:01:52.721901 DUTY Scan : NO K
2124 01:01:52.724916 ZQ Calibration : PASS
2125 01:01:52.728042 Jitter Meter : NO K
2126 01:01:52.728150 CBT Training : PASS
2127 01:01:52.731701 Write leveling : PASS
2128 01:01:52.734962 RX DQS gating : PASS
2129 01:01:52.735047 RX DQ/DQS(RDDQC) : PASS
2130 01:01:52.738239 TX DQ/DQS : PASS
2131 01:01:52.741442 RX DATLAT : PASS
2132 01:01:52.741526 RX DQ/DQS(Engine): PASS
2133 01:01:52.744620 TX OE : NO K
2134 01:01:52.744704 All Pass.
2135 01:01:52.744788
2136 01:01:52.748410 CH 1, Rank 1
2137 01:01:52.748493 SW Impedance : PASS
2138 01:01:52.751805 DUTY Scan : NO K
2139 01:01:52.751889 ZQ Calibration : PASS
2140 01:01:52.755000 Jitter Meter : NO K
2141 01:01:52.758163 CBT Training : PASS
2142 01:01:52.758246 Write leveling : PASS
2143 01:01:52.761429 RX DQS gating : PASS
2144 01:01:52.765126 RX DQ/DQS(RDDQC) : PASS
2145 01:01:52.765209 TX DQ/DQS : PASS
2146 01:01:52.768113 RX DATLAT : PASS
2147 01:01:52.772047 RX DQ/DQS(Engine): PASS
2148 01:01:52.772155 TX OE : NO K
2149 01:01:52.775326 All Pass.
2150 01:01:52.775409
2151 01:01:52.775493 DramC Write-DBI off
2152 01:01:52.778626 PER_BANK_REFRESH: Hybrid Mode
2153 01:01:52.778709 TX_TRACKING: ON
2154 01:01:52.781685 [GetDramInforAfterCalByMRR] Vendor 6.
2155 01:01:52.788441 [GetDramInforAfterCalByMRR] Revision 606.
2156 01:01:52.792142 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 01:01:52.792268 MR0 0x3b3b
2158 01:01:52.792353 MR8 0x5151
2159 01:01:52.795360 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 01:01:52.795442
2161 01:01:52.798596 MR0 0x3b3b
2162 01:01:52.798702 MR8 0x5151
2163 01:01:52.801772 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 01:01:52.801854
2165 01:01:52.811865 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 01:01:52.815420 [FAST_K] Save calibration result to emmc
2167 01:01:52.818570 [FAST_K] Save calibration result to emmc
2168 01:01:52.821860 dram_init: config_dvfs: 1
2169 01:01:52.825104 dramc_set_vcore_voltage set vcore to 662500
2170 01:01:52.828147 Read voltage for 1200, 2
2171 01:01:52.828254 Vio18 = 0
2172 01:01:52.828377 Vcore = 662500
2173 01:01:52.831601 Vdram = 0
2174 01:01:52.831681 Vddq = 0
2175 01:01:52.831745 Vmddr = 0
2176 01:01:52.838422 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 01:01:52.841888 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 01:01:52.845078 MEM_TYPE=3, freq_sel=15
2179 01:01:52.848202 sv_algorithm_assistance_LP4_1600
2180 01:01:52.851951 ============ PULL DRAM RESETB DOWN ============
2181 01:01:52.855017 ========== PULL DRAM RESETB DOWN end =========
2182 01:01:52.861494 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 01:01:52.865411 ===================================
2184 01:01:52.865495 LPDDR4 DRAM CONFIGURATION
2185 01:01:52.868293 ===================================
2186 01:01:52.871481 EX_ROW_EN[0] = 0x0
2187 01:01:52.875186 EX_ROW_EN[1] = 0x0
2188 01:01:52.875270 LP4Y_EN = 0x0
2189 01:01:52.878399 WORK_FSP = 0x0
2190 01:01:52.878483 WL = 0x4
2191 01:01:52.881696 RL = 0x4
2192 01:01:52.881780 BL = 0x2
2193 01:01:52.884911 RPST = 0x0
2194 01:01:52.884994 RD_PRE = 0x0
2195 01:01:52.888590 WR_PRE = 0x1
2196 01:01:52.888672 WR_PST = 0x0
2197 01:01:52.891731 DBI_WR = 0x0
2198 01:01:52.891814 DBI_RD = 0x0
2199 01:01:52.895447 OTF = 0x1
2200 01:01:52.898611 ===================================
2201 01:01:52.901800 ===================================
2202 01:01:52.901883 ANA top config
2203 01:01:52.905043 ===================================
2204 01:01:52.908548 DLL_ASYNC_EN = 0
2205 01:01:52.912040 ALL_SLAVE_EN = 0
2206 01:01:52.912148 NEW_RANK_MODE = 1
2207 01:01:52.915149 DLL_IDLE_MODE = 1
2208 01:01:52.918402 LP45_APHY_COMB_EN = 1
2209 01:01:52.921618 TX_ODT_DIS = 1
2210 01:01:52.924834 NEW_8X_MODE = 1
2211 01:01:52.924919 ===================================
2212 01:01:52.928611 ===================================
2213 01:01:52.931770 data_rate = 2400
2214 01:01:52.935064 CKR = 1
2215 01:01:52.938189 DQ_P2S_RATIO = 8
2216 01:01:52.941534 ===================================
2217 01:01:52.945216 CA_P2S_RATIO = 8
2218 01:01:52.948748 DQ_CA_OPEN = 0
2219 01:01:52.948832 DQ_SEMI_OPEN = 0
2220 01:01:52.951776 CA_SEMI_OPEN = 0
2221 01:01:52.955121 CA_FULL_RATE = 0
2222 01:01:52.958256 DQ_CKDIV4_EN = 0
2223 01:01:52.961659 CA_CKDIV4_EN = 0
2224 01:01:52.965033 CA_PREDIV_EN = 0
2225 01:01:52.965108 PH8_DLY = 17
2226 01:01:52.968403 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 01:01:52.971591 DQ_AAMCK_DIV = 4
2228 01:01:52.975602 CA_AAMCK_DIV = 4
2229 01:01:52.978882 CA_ADMCK_DIV = 4
2230 01:01:52.981848 DQ_TRACK_CA_EN = 0
2231 01:01:52.981921 CA_PICK = 1200
2232 01:01:52.985815 CA_MCKIO = 1200
2233 01:01:52.988421 MCKIO_SEMI = 0
2234 01:01:52.991913 PLL_FREQ = 2366
2235 01:01:52.995328 DQ_UI_PI_RATIO = 32
2236 01:01:52.998478 CA_UI_PI_RATIO = 0
2237 01:01:53.002125 ===================================
2238 01:01:53.005278 ===================================
2239 01:01:53.008642 memory_type:LPDDR4
2240 01:01:53.008724 GP_NUM : 10
2241 01:01:53.011893 SRAM_EN : 1
2242 01:01:53.011962 MD32_EN : 0
2243 01:01:53.015035 ===================================
2244 01:01:53.018875 [ANA_INIT] >>>>>>>>>>>>>>
2245 01:01:53.022060 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 01:01:53.025237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 01:01:53.028486 ===================================
2248 01:01:53.032266 data_rate = 2400,PCW = 0X5b00
2249 01:01:53.035482 ===================================
2250 01:01:53.038751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 01:01:53.042516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 01:01:53.048954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 01:01:53.052191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 01:01:53.055347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 01:01:53.059227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 01:01:53.062387 [ANA_INIT] flow start
2257 01:01:53.065304 [ANA_INIT] PLL >>>>>>>>
2258 01:01:53.065372 [ANA_INIT] PLL <<<<<<<<
2259 01:01:53.068877 [ANA_INIT] MIDPI >>>>>>>>
2260 01:01:53.072177 [ANA_INIT] MIDPI <<<<<<<<
2261 01:01:53.072246 [ANA_INIT] DLL >>>>>>>>
2262 01:01:53.075882 [ANA_INIT] DLL <<<<<<<<
2263 01:01:53.079067 [ANA_INIT] flow end
2264 01:01:53.082218 ============ LP4 DIFF to SE enter ============
2265 01:01:53.085887 ============ LP4 DIFF to SE exit ============
2266 01:01:53.089365 [ANA_INIT] <<<<<<<<<<<<<
2267 01:01:53.092567 [Flow] Enable top DCM control >>>>>
2268 01:01:53.095981 [Flow] Enable top DCM control <<<<<
2269 01:01:53.098932 Enable DLL master slave shuffle
2270 01:01:53.102550 ==============================================================
2271 01:01:53.105747 Gating Mode config
2272 01:01:53.112273 ==============================================================
2273 01:01:53.112374 Config description:
2274 01:01:53.122250 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 01:01:53.128889 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 01:01:53.132204 SELPH_MODE 0: By rank 1: By Phase
2277 01:01:53.139320 ==============================================================
2278 01:01:53.142202 GAT_TRACK_EN = 1
2279 01:01:53.146115 RX_GATING_MODE = 2
2280 01:01:53.149261 RX_GATING_TRACK_MODE = 2
2281 01:01:53.152498 SELPH_MODE = 1
2282 01:01:53.155767 PICG_EARLY_EN = 1
2283 01:01:53.155832 VALID_LAT_VALUE = 1
2284 01:01:53.162259 ==============================================================
2285 01:01:53.166071 Enter into Gating configuration >>>>
2286 01:01:53.169313 Exit from Gating configuration <<<<
2287 01:01:53.172291 Enter into DVFS_PRE_config >>>>>
2288 01:01:53.182807 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 01:01:53.186107 Exit from DVFS_PRE_config <<<<<
2290 01:01:53.189372 Enter into PICG configuration >>>>
2291 01:01:53.192569 Exit from PICG configuration <<<<
2292 01:01:53.196148 [RX_INPUT] configuration >>>>>
2293 01:01:53.199199 [RX_INPUT] configuration <<<<<
2294 01:01:53.202898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 01:01:53.209260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 01:01:53.215735 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 01:01:53.222602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 01:01:53.229472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 01:01:53.232486 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 01:01:53.239597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 01:01:53.242674 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 01:01:53.245740 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 01:01:53.249503 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 01:01:53.252856 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 01:01:53.259350 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 01:01:53.262626 ===================================
2307 01:01:53.266082 LPDDR4 DRAM CONFIGURATION
2308 01:01:53.269519 ===================================
2309 01:01:53.269624 EX_ROW_EN[0] = 0x0
2310 01:01:53.273113 EX_ROW_EN[1] = 0x0
2311 01:01:53.273221 LP4Y_EN = 0x0
2312 01:01:53.276236 WORK_FSP = 0x0
2313 01:01:53.276362 WL = 0x4
2314 01:01:53.279506 RL = 0x4
2315 01:01:53.279584 BL = 0x2
2316 01:01:53.282975 RPST = 0x0
2317 01:01:53.283045 RD_PRE = 0x0
2318 01:01:53.285936 WR_PRE = 0x1
2319 01:01:53.286010 WR_PST = 0x0
2320 01:01:53.289763 DBI_WR = 0x0
2321 01:01:53.289835 DBI_RD = 0x0
2322 01:01:53.292931 OTF = 0x1
2323 01:01:53.296116 ===================================
2324 01:01:53.299281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 01:01:53.303098 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 01:01:53.309548 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 01:01:53.312784 ===================================
2328 01:01:53.312858 LPDDR4 DRAM CONFIGURATION
2329 01:01:53.315893 ===================================
2330 01:01:53.319157 EX_ROW_EN[0] = 0x10
2331 01:01:53.322901 EX_ROW_EN[1] = 0x0
2332 01:01:53.322970 LP4Y_EN = 0x0
2333 01:01:53.326071 WORK_FSP = 0x0
2334 01:01:53.326142 WL = 0x4
2335 01:01:53.329754 RL = 0x4
2336 01:01:53.329821 BL = 0x2
2337 01:01:53.332789 RPST = 0x0
2338 01:01:53.332856 RD_PRE = 0x0
2339 01:01:53.335947 WR_PRE = 0x1
2340 01:01:53.336018 WR_PST = 0x0
2341 01:01:53.339821 DBI_WR = 0x0
2342 01:01:53.339890 DBI_RD = 0x0
2343 01:01:53.343036 OTF = 0x1
2344 01:01:53.346210 ===================================
2345 01:01:53.352549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 01:01:53.352619 ==
2347 01:01:53.356242 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 01:01:53.359265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 01:01:53.359333 ==
2350 01:01:53.363019 [Duty_Offset_Calibration]
2351 01:01:53.363092 B0:2 B1:1 CA:1
2352 01:01:53.363154
2353 01:01:53.366174 [DutyScan_Calibration_Flow] k_type=0
2354 01:01:53.376251
2355 01:01:53.376368 ==CLK 0==
2356 01:01:53.379226 Final CLK duty delay cell = 0
2357 01:01:53.382662 [0] MAX Duty = 5156%(X100), DQS PI = 22
2358 01:01:53.385885 [0] MIN Duty = 4844%(X100), DQS PI = 48
2359 01:01:53.385960 [0] AVG Duty = 5000%(X100)
2360 01:01:53.389364
2361 01:01:53.392754 CH0 CLK Duty spec in!! Max-Min= 312%
2362 01:01:53.396006 [DutyScan_Calibration_Flow] ====Done====
2363 01:01:53.396108
2364 01:01:53.399524 [DutyScan_Calibration_Flow] k_type=1
2365 01:01:53.415071
2366 01:01:53.415153 ==DQS 0 ==
2367 01:01:53.418225 Final DQS duty delay cell = -4
2368 01:01:53.421327 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2369 01:01:53.424489 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2370 01:01:53.427549 [-4] AVG Duty = 4953%(X100)
2371 01:01:53.427617
2372 01:01:53.427677 ==DQS 1 ==
2373 01:01:53.431359 Final DQS duty delay cell = 0
2374 01:01:53.434494 [0] MAX Duty = 5156%(X100), DQS PI = 0
2375 01:01:53.438126 [0] MIN Duty = 5000%(X100), DQS PI = 34
2376 01:01:53.441054 [0] AVG Duty = 5078%(X100)
2377 01:01:53.441127
2378 01:01:53.444948 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2379 01:01:53.445015
2380 01:01:53.448270 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2381 01:01:53.451437 [DutyScan_Calibration_Flow] ====Done====
2382 01:01:53.451504
2383 01:01:53.454558 [DutyScan_Calibration_Flow] k_type=3
2384 01:01:53.471344
2385 01:01:53.471419 ==DQM 0 ==
2386 01:01:53.474622 Final DQM duty delay cell = 0
2387 01:01:53.478332 [0] MAX Duty = 5156%(X100), DQS PI = 30
2388 01:01:53.481497 [0] MIN Duty = 4875%(X100), DQS PI = 58
2389 01:01:53.484766 [0] AVG Duty = 5015%(X100)
2390 01:01:53.484835
2391 01:01:53.484895 ==DQM 1 ==
2392 01:01:53.487722 Final DQM duty delay cell = 0
2393 01:01:53.491540 [0] MAX Duty = 5093%(X100), DQS PI = 0
2394 01:01:53.494802 [0] MIN Duty = 5031%(X100), DQS PI = 14
2395 01:01:53.494875 [0] AVG Duty = 5062%(X100)
2396 01:01:53.498037
2397 01:01:53.501219 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2398 01:01:53.501294
2399 01:01:53.504720 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2400 01:01:53.508071 [DutyScan_Calibration_Flow] ====Done====
2401 01:01:53.508175
2402 01:01:53.511095 [DutyScan_Calibration_Flow] k_type=2
2403 01:01:53.527714
2404 01:01:53.527820 ==DQ 0 ==
2405 01:01:53.531285 Final DQ duty delay cell = 0
2406 01:01:53.534641 [0] MAX Duty = 5031%(X100), DQS PI = 24
2407 01:01:53.537823 [0] MIN Duty = 4875%(X100), DQS PI = 0
2408 01:01:53.537904 [0] AVG Duty = 4953%(X100)
2409 01:01:53.537968
2410 01:01:53.541008 ==DQ 1 ==
2411 01:01:53.544212 Final DQ duty delay cell = 0
2412 01:01:53.547838 [0] MAX Duty = 5093%(X100), DQS PI = 24
2413 01:01:53.551197 [0] MIN Duty = 4907%(X100), DQS PI = 36
2414 01:01:53.551305 [0] AVG Duty = 5000%(X100)
2415 01:01:53.551395
2416 01:01:53.554541 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2417 01:01:53.554617
2418 01:01:53.557993 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2419 01:01:53.564474 [DutyScan_Calibration_Flow] ====Done====
2420 01:01:53.564546 ==
2421 01:01:53.567661 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 01:01:53.571404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 01:01:53.571492 ==
2424 01:01:53.574558 [Duty_Offset_Calibration]
2425 01:01:53.574659 B0:1 B1:0 CA:0
2426 01:01:53.574747
2427 01:01:53.577549 [DutyScan_Calibration_Flow] k_type=0
2428 01:01:53.586748
2429 01:01:53.586821 ==CLK 0==
2430 01:01:53.590162 Final CLK duty delay cell = -4
2431 01:01:53.593978 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2432 01:01:53.597138 [-4] MIN Duty = 4907%(X100), DQS PI = 14
2433 01:01:53.600532 [-4] AVG Duty = 4953%(X100)
2434 01:01:53.600613
2435 01:01:53.603682 CH1 CLK Duty spec in!! Max-Min= 93%
2436 01:01:53.607128 [DutyScan_Calibration_Flow] ====Done====
2437 01:01:53.607212
2438 01:01:53.610345 [DutyScan_Calibration_Flow] k_type=1
2439 01:01:53.626684
2440 01:01:53.626767 ==DQS 0 ==
2441 01:01:53.629973 Final DQS duty delay cell = 0
2442 01:01:53.633614 [0] MAX Duty = 5094%(X100), DQS PI = 26
2443 01:01:53.636614 [0] MIN Duty = 4875%(X100), DQS PI = 0
2444 01:01:53.636696 [0] AVG Duty = 4984%(X100)
2445 01:01:53.639788
2446 01:01:53.639879 ==DQS 1 ==
2447 01:01:53.643065 Final DQS duty delay cell = 0
2448 01:01:53.646456 [0] MAX Duty = 5218%(X100), DQS PI = 18
2449 01:01:53.649877 [0] MIN Duty = 4969%(X100), DQS PI = 8
2450 01:01:53.649959 [0] AVG Duty = 5093%(X100)
2451 01:01:53.652995
2452 01:01:53.656995 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2453 01:01:53.657076
2454 01:01:53.659718 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2455 01:01:53.663658 [DutyScan_Calibration_Flow] ====Done====
2456 01:01:53.663741
2457 01:01:53.666535 [DutyScan_Calibration_Flow] k_type=3
2458 01:01:53.683082
2459 01:01:53.683169 ==DQM 0 ==
2460 01:01:53.686558 Final DQM duty delay cell = 0
2461 01:01:53.689786 [0] MAX Duty = 5187%(X100), DQS PI = 10
2462 01:01:53.692924 [0] MIN Duty = 5000%(X100), DQS PI = 62
2463 01:01:53.696255 [0] AVG Duty = 5093%(X100)
2464 01:01:53.696380
2465 01:01:53.696444 ==DQM 1 ==
2466 01:01:53.700146 Final DQM duty delay cell = 0
2467 01:01:53.702793 [0] MAX Duty = 5031%(X100), DQS PI = 16
2468 01:01:53.706596 [0] MIN Duty = 4907%(X100), DQS PI = 36
2469 01:01:53.709898 [0] AVG Duty = 4969%(X100)
2470 01:01:53.709998
2471 01:01:53.713082 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2472 01:01:53.713183
2473 01:01:53.716195 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2474 01:01:53.719912 [DutyScan_Calibration_Flow] ====Done====
2475 01:01:53.719989
2476 01:01:53.723285 [DutyScan_Calibration_Flow] k_type=2
2477 01:01:53.739022
2478 01:01:53.739103 ==DQ 0 ==
2479 01:01:53.742620 Final DQ duty delay cell = -4
2480 01:01:53.745997 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2481 01:01:53.749183 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2482 01:01:53.749302 [-4] AVG Duty = 4984%(X100)
2483 01:01:53.752450
2484 01:01:53.752538 ==DQ 1 ==
2485 01:01:53.755629 Final DQ duty delay cell = 0
2486 01:01:53.759079 [0] MAX Duty = 5125%(X100), DQS PI = 20
2487 01:01:53.763007 [0] MIN Duty = 4969%(X100), DQS PI = 10
2488 01:01:53.763083 [0] AVG Duty = 5047%(X100)
2489 01:01:53.766181
2490 01:01:53.769425 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2491 01:01:53.769554
2492 01:01:53.772650 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2493 01:01:53.775742 [DutyScan_Calibration_Flow] ====Done====
2494 01:01:53.779445 nWR fixed to 30
2495 01:01:53.779574 [ModeRegInit_LP4] CH0 RK0
2496 01:01:53.782509 [ModeRegInit_LP4] CH0 RK1
2497 01:01:53.785747 [ModeRegInit_LP4] CH1 RK0
2498 01:01:53.789039 [ModeRegInit_LP4] CH1 RK1
2499 01:01:53.789118 match AC timing 7
2500 01:01:53.792233 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 01:01:53.799067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 01:01:53.802410 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 01:01:53.805961 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 01:01:53.812657 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 01:01:53.812765 ==
2506 01:01:53.815863 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 01:01:53.818977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 01:01:53.819084 ==
2509 01:01:53.826080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 01:01:53.829092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 01:01:53.839568 [CA 0] Center 39 (8~70) winsize 63
2512 01:01:53.842670 [CA 1] Center 39 (8~70) winsize 63
2513 01:01:53.846361 [CA 2] Center 35 (5~66) winsize 62
2514 01:01:53.849069 [CA 3] Center 34 (4~65) winsize 62
2515 01:01:53.852494 [CA 4] Center 33 (3~64) winsize 62
2516 01:01:53.855673 [CA 5] Center 32 (3~62) winsize 60
2517 01:01:53.855774
2518 01:01:53.859073 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2519 01:01:53.859148
2520 01:01:53.862799 [CATrainingPosCal] consider 1 rank data
2521 01:01:53.866084 u2DelayCellTimex100 = 270/100 ps
2522 01:01:53.869519 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2523 01:01:53.872724 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2524 01:01:53.879409 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2525 01:01:53.882617 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2526 01:01:53.885951 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2527 01:01:53.889086 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2528 01:01:53.889162
2529 01:01:53.892923 CA PerBit enable=1, Macro0, CA PI delay=32
2530 01:01:53.893026
2531 01:01:53.896065 [CBTSetCACLKResult] CA Dly = 32
2532 01:01:53.896141 CS Dly: 6 (0~37)
2533 01:01:53.896204 ==
2534 01:01:53.899505 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 01:01:53.906048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 01:01:53.906129 ==
2537 01:01:53.909833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 01:01:53.916123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2539 01:01:53.925359 [CA 0] Center 38 (8~69) winsize 62
2540 01:01:53.928908 [CA 1] Center 38 (8~69) winsize 62
2541 01:01:53.931574 [CA 2] Center 35 (5~66) winsize 62
2542 01:01:53.934894 [CA 3] Center 34 (4~65) winsize 62
2543 01:01:53.938254 [CA 4] Center 33 (3~64) winsize 62
2544 01:01:53.941779 [CA 5] Center 32 (3~62) winsize 60
2545 01:01:53.941857
2546 01:01:53.945386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 01:01:53.945463
2548 01:01:53.948459 [CATrainingPosCal] consider 2 rank data
2549 01:01:53.951767 u2DelayCellTimex100 = 270/100 ps
2550 01:01:53.954886 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2551 01:01:53.958783 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2552 01:01:53.965033 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2553 01:01:53.968298 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2554 01:01:53.971753 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2555 01:01:53.975582 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2556 01:01:53.975666
2557 01:01:53.978661 CA PerBit enable=1, Macro0, CA PI delay=32
2558 01:01:53.978771
2559 01:01:53.982014 [CBTSetCACLKResult] CA Dly = 32
2560 01:01:53.982097 CS Dly: 6 (0~38)
2561 01:01:53.982163
2562 01:01:53.985092 ----->DramcWriteLeveling(PI) begin...
2563 01:01:53.988861 ==
2564 01:01:53.988945 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 01:01:53.995496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 01:01:53.995578 ==
2567 01:01:53.998505 Write leveling (Byte 0): 33 => 33
2568 01:01:54.001683 Write leveling (Byte 1): 28 => 28
2569 01:01:54.005520 DramcWriteLeveling(PI) end<-----
2570 01:01:54.005602
2571 01:01:54.005666 ==
2572 01:01:54.008640 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 01:01:54.011729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 01:01:54.011811 ==
2575 01:01:54.014987 [Gating] SW mode calibration
2576 01:01:54.021931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 01:01:54.025187 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 01:01:54.031613 0 15 0 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2579 01:01:54.034858 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2580 01:01:54.038587 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 01:01:54.045569 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 01:01:54.048758 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 01:01:54.051827 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 01:01:54.058682 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2585 01:01:54.061805 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
2586 01:01:54.065584 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2587 01:01:54.072080 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 01:01:54.075395 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 01:01:54.078415 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 01:01:54.085556 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 01:01:54.088480 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 01:01:54.091663 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2593 01:01:54.098528 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2594 01:01:54.102096 1 1 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2595 01:01:54.105145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 01:01:54.108562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 01:01:54.115326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 01:01:54.118684 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 01:01:54.121866 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 01:01:54.128881 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 01:01:54.132029 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 01:01:54.135358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 01:01:54.141815 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 01:01:54.145545 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 01:01:54.148453 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 01:01:54.155590 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 01:01:54.158819 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 01:01:54.162354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 01:01:54.169006 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 01:01:54.172214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 01:01:54.175591 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 01:01:54.182164 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 01:01:54.185304 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 01:01:54.188596 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 01:01:54.191747 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 01:01:54.198819 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 01:01:54.201930 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 01:01:54.205671 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 01:01:54.208451 Total UI for P1: 0, mck2ui 16
2620 01:01:54.211775 best dqsien dly found for B0: ( 1, 3, 26)
2621 01:01:54.218815 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 01:01:54.218941 Total UI for P1: 0, mck2ui 16
2623 01:01:54.225950 best dqsien dly found for B1: ( 1, 4, 0)
2624 01:01:54.228547 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2625 01:01:54.232080 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2626 01:01:54.232193
2627 01:01:54.235600 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2628 01:01:54.238497 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2629 01:01:54.241837 [Gating] SW calibration Done
2630 01:01:54.241949 ==
2631 01:01:54.245537 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 01:01:54.248450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 01:01:54.248565 ==
2634 01:01:54.252283 RX Vref Scan: 0
2635 01:01:54.252436
2636 01:01:54.252531 RX Vref 0 -> 0, step: 1
2637 01:01:54.252598
2638 01:01:54.255485 RX Delay -40 -> 252, step: 8
2639 01:01:54.258646 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2640 01:01:54.265150 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2641 01:01:54.268770 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2642 01:01:54.271734 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2643 01:01:54.275404 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2644 01:01:54.279139 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2645 01:01:54.282439 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2646 01:01:54.288888 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2647 01:01:54.292207 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2648 01:01:54.295520 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2649 01:01:54.299323 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2650 01:01:54.302605 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2651 01:01:54.309083 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2652 01:01:54.312174 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2653 01:01:54.315833 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2654 01:01:54.319160 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2655 01:01:54.319241 ==
2656 01:01:54.322329 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 01:01:54.328708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 01:01:54.328789 ==
2659 01:01:54.328855 DQS Delay:
2660 01:01:54.332580 DQS0 = 0, DQS1 = 0
2661 01:01:54.332678 DQM Delay:
2662 01:01:54.332744 DQM0 = 121, DQM1 = 113
2663 01:01:54.335747 DQ Delay:
2664 01:01:54.338801 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2665 01:01:54.342465 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2666 01:01:54.345566 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2667 01:01:54.349169 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2668 01:01:54.349243
2669 01:01:54.349306
2670 01:01:54.349364 ==
2671 01:01:54.352015 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 01:01:54.355553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 01:01:54.358796 ==
2674 01:01:54.358890
2675 01:01:54.358980
2676 01:01:54.359067 TX Vref Scan disable
2677 01:01:54.362533 == TX Byte 0 ==
2678 01:01:54.365896 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2679 01:01:54.368700 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2680 01:01:54.372130 == TX Byte 1 ==
2681 01:01:54.375609 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2682 01:01:54.379127 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2683 01:01:54.379239 ==
2684 01:01:54.382251 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 01:01:54.389016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 01:01:54.389135 ==
2687 01:01:54.400499 TX Vref=22, minBit 0, minWin=25, winSum=410
2688 01:01:54.403259 TX Vref=24, minBit 5, minWin=25, winSum=412
2689 01:01:54.406500 TX Vref=26, minBit 0, minWin=26, winSum=421
2690 01:01:54.409744 TX Vref=28, minBit 0, minWin=26, winSum=424
2691 01:01:54.413219 TX Vref=30, minBit 0, minWin=26, winSum=424
2692 01:01:54.416976 TX Vref=32, minBit 0, minWin=26, winSum=425
2693 01:01:54.423532 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
2694 01:01:54.423639
2695 01:01:54.426772 Final TX Range 1 Vref 32
2696 01:01:54.426874
2697 01:01:54.426973 ==
2698 01:01:54.430052 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 01:01:54.433117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 01:01:54.433224 ==
2701 01:01:54.433318
2702 01:01:54.436395
2703 01:01:54.436477 TX Vref Scan disable
2704 01:01:54.440228 == TX Byte 0 ==
2705 01:01:54.443304 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2706 01:01:54.446479 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2707 01:01:54.450165 == TX Byte 1 ==
2708 01:01:54.453131 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2709 01:01:54.456453 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2710 01:01:54.456548
2711 01:01:54.459703 [DATLAT]
2712 01:01:54.459786 Freq=1200, CH0 RK0
2713 01:01:54.459848
2714 01:01:54.463666 DATLAT Default: 0xd
2715 01:01:54.463763 0, 0xFFFF, sum = 0
2716 01:01:54.466956 1, 0xFFFF, sum = 0
2717 01:01:54.467053 2, 0xFFFF, sum = 0
2718 01:01:54.470156 3, 0xFFFF, sum = 0
2719 01:01:54.470228 4, 0xFFFF, sum = 0
2720 01:01:54.473400 5, 0xFFFF, sum = 0
2721 01:01:54.473475 6, 0xFFFF, sum = 0
2722 01:01:54.477234 7, 0xFFFF, sum = 0
2723 01:01:54.477321 8, 0xFFFF, sum = 0
2724 01:01:54.479973 9, 0xFFFF, sum = 0
2725 01:01:54.483577 10, 0xFFFF, sum = 0
2726 01:01:54.483656 11, 0xFFFF, sum = 0
2727 01:01:54.483722 12, 0x0, sum = 1
2728 01:01:54.487037 13, 0x0, sum = 2
2729 01:01:54.487135 14, 0x0, sum = 3
2730 01:01:54.490220 15, 0x0, sum = 4
2731 01:01:54.490322 best_step = 13
2732 01:01:54.490410
2733 01:01:54.490495 ==
2734 01:01:54.493791 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 01:01:54.500481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 01:01:54.500584 ==
2737 01:01:54.500677 RX Vref Scan: 1
2738 01:01:54.500764
2739 01:01:54.504015 Set Vref Range= 32 -> 127
2740 01:01:54.504111
2741 01:01:54.506942 RX Vref 32 -> 127, step: 1
2742 01:01:54.507036
2743 01:01:54.510120 RX Delay -13 -> 252, step: 4
2744 01:01:54.510219
2745 01:01:54.510310 Set Vref, RX VrefLevel [Byte0]: 32
2746 01:01:54.513383 [Byte1]: 32
2747 01:01:54.518036
2748 01:01:54.518135 Set Vref, RX VrefLevel [Byte0]: 33
2749 01:01:54.521474 [Byte1]: 33
2750 01:01:54.525901
2751 01:01:54.525975 Set Vref, RX VrefLevel [Byte0]: 34
2752 01:01:54.529647 [Byte1]: 34
2753 01:01:54.534190
2754 01:01:54.534290 Set Vref, RX VrefLevel [Byte0]: 35
2755 01:01:54.537281 [Byte1]: 35
2756 01:01:54.541719
2757 01:01:54.541817 Set Vref, RX VrefLevel [Byte0]: 36
2758 01:01:54.544955 [Byte1]: 36
2759 01:01:54.550037
2760 01:01:54.550109 Set Vref, RX VrefLevel [Byte0]: 37
2761 01:01:54.553083 [Byte1]: 37
2762 01:01:54.557494
2763 01:01:54.557594 Set Vref, RX VrefLevel [Byte0]: 38
2764 01:01:54.561272 [Byte1]: 38
2765 01:01:54.565729
2766 01:01:54.565800 Set Vref, RX VrefLevel [Byte0]: 39
2767 01:01:54.568948 [Byte1]: 39
2768 01:01:54.573504
2769 01:01:54.573576 Set Vref, RX VrefLevel [Byte0]: 40
2770 01:01:54.576674 [Byte1]: 40
2771 01:01:54.581697
2772 01:01:54.581768 Set Vref, RX VrefLevel [Byte0]: 41
2773 01:01:54.584541 [Byte1]: 41
2774 01:01:54.588984
2775 01:01:54.589060 Set Vref, RX VrefLevel [Byte0]: 42
2776 01:01:54.592802 [Byte1]: 42
2777 01:01:54.597413
2778 01:01:54.597489 Set Vref, RX VrefLevel [Byte0]: 43
2779 01:01:54.600570 [Byte1]: 43
2780 01:01:54.605103
2781 01:01:54.605202 Set Vref, RX VrefLevel [Byte0]: 44
2782 01:01:54.608435 [Byte1]: 44
2783 01:01:54.612731
2784 01:01:54.612804 Set Vref, RX VrefLevel [Byte0]: 45
2785 01:01:54.616454 [Byte1]: 45
2786 01:01:54.620927
2787 01:01:54.621024 Set Vref, RX VrefLevel [Byte0]: 46
2788 01:01:54.623928 [Byte1]: 46
2789 01:01:54.628596
2790 01:01:54.628669 Set Vref, RX VrefLevel [Byte0]: 47
2791 01:01:54.631744 [Byte1]: 47
2792 01:01:54.636493
2793 01:01:54.636593 Set Vref, RX VrefLevel [Byte0]: 48
2794 01:01:54.640171 [Byte1]: 48
2795 01:01:54.644260
2796 01:01:54.644366 Set Vref, RX VrefLevel [Byte0]: 49
2797 01:01:54.647602 [Byte1]: 49
2798 01:01:54.652255
2799 01:01:54.652379 Set Vref, RX VrefLevel [Byte0]: 50
2800 01:01:54.655870 [Byte1]: 50
2801 01:01:54.660491
2802 01:01:54.660563 Set Vref, RX VrefLevel [Byte0]: 51
2803 01:01:54.663597 [Byte1]: 51
2804 01:01:54.668098
2805 01:01:54.668172 Set Vref, RX VrefLevel [Byte0]: 52
2806 01:01:54.671272 [Byte1]: 52
2807 01:01:54.676251
2808 01:01:54.676365 Set Vref, RX VrefLevel [Byte0]: 53
2809 01:01:54.679592 [Byte1]: 53
2810 01:01:54.684047
2811 01:01:54.684123 Set Vref, RX VrefLevel [Byte0]: 54
2812 01:01:54.687118 [Byte1]: 54
2813 01:01:54.691994
2814 01:01:54.692093 Set Vref, RX VrefLevel [Byte0]: 55
2815 01:01:54.695110 [Byte1]: 55
2816 01:01:54.699479
2817 01:01:54.699581 Set Vref, RX VrefLevel [Byte0]: 56
2818 01:01:54.702819 [Byte1]: 56
2819 01:01:54.707410
2820 01:01:54.707484 Set Vref, RX VrefLevel [Byte0]: 57
2821 01:01:54.711166 [Byte1]: 57
2822 01:01:54.715538
2823 01:01:54.715613 Set Vref, RX VrefLevel [Byte0]: 58
2824 01:01:54.718700 [Byte1]: 58
2825 01:01:54.723669
2826 01:01:54.723768 Set Vref, RX VrefLevel [Byte0]: 59
2827 01:01:54.726942 [Byte1]: 59
2828 01:01:54.731445
2829 01:01:54.731558 Set Vref, RX VrefLevel [Byte0]: 60
2830 01:01:54.734683 [Byte1]: 60
2831 01:01:54.738950
2832 01:01:54.739055 Set Vref, RX VrefLevel [Byte0]: 61
2833 01:01:54.742793 [Byte1]: 61
2834 01:01:54.747108
2835 01:01:54.747216 Set Vref, RX VrefLevel [Byte0]: 62
2836 01:01:54.750285 [Byte1]: 62
2837 01:01:54.755257
2838 01:01:54.755370 Set Vref, RX VrefLevel [Byte0]: 63
2839 01:01:54.758214 [Byte1]: 63
2840 01:01:54.762892
2841 01:01:54.762973 Set Vref, RX VrefLevel [Byte0]: 64
2842 01:01:54.766475 [Byte1]: 64
2843 01:01:54.770610
2844 01:01:54.770691 Set Vref, RX VrefLevel [Byte0]: 65
2845 01:01:54.773851 [Byte1]: 65
2846 01:01:54.778630
2847 01:01:54.778711 Set Vref, RX VrefLevel [Byte0]: 66
2848 01:01:54.782035 [Byte1]: 66
2849 01:01:54.786446
2850 01:01:54.786527 Set Vref, RX VrefLevel [Byte0]: 67
2851 01:01:54.789653 [Byte1]: 67
2852 01:01:54.794659
2853 01:01:54.794740 Set Vref, RX VrefLevel [Byte0]: 68
2854 01:01:54.797461 [Byte1]: 68
2855 01:01:54.802391
2856 01:01:54.802477 Final RX Vref Byte 0 = 55 to rank0
2857 01:01:54.805735 Final RX Vref Byte 1 = 58 to rank0
2858 01:01:54.808977 Final RX Vref Byte 0 = 55 to rank1
2859 01:01:54.812145 Final RX Vref Byte 1 = 58 to rank1==
2860 01:01:54.815929 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 01:01:54.822474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 01:01:54.822557 ==
2863 01:01:54.822622 DQS Delay:
2864 01:01:54.822682 DQS0 = 0, DQS1 = 0
2865 01:01:54.825501 DQM Delay:
2866 01:01:54.825582 DQM0 = 120, DQM1 = 114
2867 01:01:54.829320 DQ Delay:
2868 01:01:54.832108 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2869 01:01:54.835877 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2870 01:01:54.838915 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =106
2871 01:01:54.842240 DQ12 =120, DQ13 =120, DQ14 =128, DQ15 =124
2872 01:01:54.842322
2873 01:01:54.842386
2874 01:01:54.849191 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2875 01:01:54.852204 CH0 RK0: MR19=404, MR18=120B
2876 01:01:54.859452 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2877 01:01:54.859534
2878 01:01:54.862467 ----->DramcWriteLeveling(PI) begin...
2879 01:01:54.862551 ==
2880 01:01:54.865843 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 01:01:54.869262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 01:01:54.872419 ==
2883 01:01:54.872501 Write leveling (Byte 0): 32 => 32
2884 01:01:54.875643 Write leveling (Byte 1): 31 => 31
2885 01:01:54.879452 DramcWriteLeveling(PI) end<-----
2886 01:01:54.879534
2887 01:01:54.879598 ==
2888 01:01:54.882838 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 01:01:54.889295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 01:01:54.889377 ==
2891 01:01:54.889443 [Gating] SW mode calibration
2892 01:01:54.899370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 01:01:54.902388 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 01:01:54.906059 0 15 0 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (0 0)
2895 01:01:54.912663 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 01:01:54.916091 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 01:01:54.919361 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 01:01:54.926208 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 01:01:54.929569 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 01:01:54.932457 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 01:01:54.939472 0 15 28 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
2902 01:01:54.942478 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 01:01:54.946199 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 01:01:54.952575 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 01:01:54.956198 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 01:01:54.959422 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 01:01:54.965826 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 01:01:54.969667 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 01:01:54.972733 1 0 28 | B1->B0 | 3b3b 3939 | 0 1 | (0 0) (0 0)
2910 01:01:54.976365 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2911 01:01:54.983029 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 01:01:54.986227 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 01:01:54.989431 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 01:01:54.995771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 01:01:54.999586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 01:01:55.002619 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 01:01:55.009628 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2918 01:01:55.013106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2919 01:01:55.016025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 01:01:55.022765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 01:01:55.025908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 01:01:55.029732 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 01:01:55.035943 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 01:01:55.039285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 01:01:55.042603 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 01:01:55.046018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 01:01:55.052856 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 01:01:55.056330 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 01:01:55.059451 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 01:01:55.066219 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 01:01:55.069420 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 01:01:55.072662 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 01:01:55.079696 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 01:01:55.082632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 01:01:55.086288 Total UI for P1: 0, mck2ui 16
2936 01:01:55.089337 best dqsien dly found for B0: ( 1, 3, 28)
2937 01:01:55.093204 Total UI for P1: 0, mck2ui 16
2938 01:01:55.096425 best dqsien dly found for B1: ( 1, 3, 28)
2939 01:01:55.099730 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2940 01:01:55.102921 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2941 01:01:55.103026
2942 01:01:55.106016 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2943 01:01:55.109849 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 01:01:55.113076 [Gating] SW calibration Done
2945 01:01:55.113154 ==
2946 01:01:55.116414 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 01:01:55.119544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 01:01:55.122704 ==
2949 01:01:55.122802 RX Vref Scan: 0
2950 01:01:55.122893
2951 01:01:55.126187 RX Vref 0 -> 0, step: 1
2952 01:01:55.126284
2953 01:01:55.126375 RX Delay -40 -> 252, step: 8
2954 01:01:55.132974 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2955 01:01:55.136726 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 01:01:55.140007 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2957 01:01:55.143065 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2958 01:01:55.146312 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2959 01:01:55.153305 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2960 01:01:55.156225 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 01:01:55.160116 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2962 01:01:55.163073 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
2963 01:01:55.166595 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2964 01:01:55.173050 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2965 01:01:55.176621 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2966 01:01:55.179780 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2967 01:01:55.183434 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
2968 01:01:55.186631 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2969 01:01:55.193551 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2970 01:01:55.193656 ==
2971 01:01:55.196795 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 01:01:55.199884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 01:01:55.200023 ==
2974 01:01:55.200115 DQS Delay:
2975 01:01:55.203497 DQS0 = 0, DQS1 = 0
2976 01:01:55.203572 DQM Delay:
2977 01:01:55.206704 DQM0 = 121, DQM1 = 113
2978 01:01:55.206803 DQ Delay:
2979 01:01:55.209827 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2980 01:01:55.213708 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2981 01:01:55.217021 DQ8 =107, DQ9 =99, DQ10 =115, DQ11 =107
2982 01:01:55.220296 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2983 01:01:55.220368
2984 01:01:55.220433
2985 01:01:55.220489 ==
2986 01:01:55.223429 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 01:01:55.230489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 01:01:55.230564 ==
2989 01:01:55.230625
2990 01:01:55.230682
2991 01:01:55.230738 TX Vref Scan disable
2992 01:01:55.233741 == TX Byte 0 ==
2993 01:01:55.237259 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2994 01:01:55.243863 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2995 01:01:55.243963 == TX Byte 1 ==
2996 01:01:55.246983 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2997 01:01:55.250112 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2998 01:01:55.254034 ==
2999 01:01:55.257348 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 01:01:55.260316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 01:01:55.260392 ==
3002 01:01:55.271773 TX Vref=22, minBit 13, minWin=24, winSum=408
3003 01:01:55.274988 TX Vref=24, minBit 1, minWin=25, winSum=414
3004 01:01:55.278177 TX Vref=26, minBit 1, minWin=25, winSum=416
3005 01:01:55.281785 TX Vref=28, minBit 0, minWin=26, winSum=424
3006 01:01:55.285253 TX Vref=30, minBit 0, minWin=26, winSum=423
3007 01:01:55.288182 TX Vref=32, minBit 0, minWin=25, winSum=421
3008 01:01:55.294931 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
3009 01:01:55.295032
3010 01:01:55.298500 Final TX Range 1 Vref 28
3011 01:01:55.298605
3012 01:01:55.298702 ==
3013 01:01:55.301850 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 01:01:55.305304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 01:01:55.305378 ==
3016 01:01:55.305440
3017 01:01:55.308504
3018 01:01:55.308577 TX Vref Scan disable
3019 01:01:55.311787 == TX Byte 0 ==
3020 01:01:55.315379 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3021 01:01:55.318508 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3022 01:01:55.321811 == TX Byte 1 ==
3023 01:01:55.324998 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3024 01:01:55.328264 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3025 01:01:55.328369
3026 01:01:55.331740 [DATLAT]
3027 01:01:55.331818 Freq=1200, CH0 RK1
3028 01:01:55.331881
3029 01:01:55.335418 DATLAT Default: 0xd
3030 01:01:55.335493 0, 0xFFFF, sum = 0
3031 01:01:55.338093 1, 0xFFFF, sum = 0
3032 01:01:55.338166 2, 0xFFFF, sum = 0
3033 01:01:55.341273 3, 0xFFFF, sum = 0
3034 01:01:55.341348 4, 0xFFFF, sum = 0
3035 01:01:55.345028 5, 0xFFFF, sum = 0
3036 01:01:55.348511 6, 0xFFFF, sum = 0
3037 01:01:55.348586 7, 0xFFFF, sum = 0
3038 01:01:55.351455 8, 0xFFFF, sum = 0
3039 01:01:55.351528 9, 0xFFFF, sum = 0
3040 01:01:55.355167 10, 0xFFFF, sum = 0
3041 01:01:55.355270 11, 0xFFFF, sum = 0
3042 01:01:55.358314 12, 0x0, sum = 1
3043 01:01:55.358415 13, 0x0, sum = 2
3044 01:01:55.361545 14, 0x0, sum = 3
3045 01:01:55.361617 15, 0x0, sum = 4
3046 01:01:55.361677 best_step = 13
3047 01:01:55.361734
3048 01:01:55.364705 ==
3049 01:01:55.367974 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 01:01:55.371734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 01:01:55.371806 ==
3052 01:01:55.371867 RX Vref Scan: 0
3053 01:01:55.371955
3054 01:01:55.374876 RX Vref 0 -> 0, step: 1
3055 01:01:55.374948
3056 01:01:55.377982 RX Delay -13 -> 252, step: 4
3057 01:01:55.381308 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3058 01:01:55.388257 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3059 01:01:55.391893 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3060 01:01:55.394894 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3061 01:01:55.398031 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3062 01:01:55.401760 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3063 01:01:55.404769 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3064 01:01:55.411953 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3065 01:01:55.414997 iDelay=195, Bit 8, Center 104 (39 ~ 170) 132
3066 01:01:55.418144 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3067 01:01:55.421944 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3068 01:01:55.425075 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3069 01:01:55.431934 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3070 01:01:55.434909 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3071 01:01:55.438639 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3072 01:01:55.441725 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3073 01:01:55.441800 ==
3074 01:01:55.446058 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 01:01:55.451621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 01:01:55.451698 ==
3077 01:01:55.451761 DQS Delay:
3078 01:01:55.451824 DQS0 = 0, DQS1 = 0
3079 01:01:55.455134 DQM Delay:
3080 01:01:55.455224 DQM0 = 121, DQM1 = 111
3081 01:01:55.458656 DQ Delay:
3082 01:01:55.461505 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3083 01:01:55.464949 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3084 01:01:55.468571 DQ8 =104, DQ9 =98, DQ10 =112, DQ11 =104
3085 01:01:55.471730 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3086 01:01:55.471829
3087 01:01:55.471918
3088 01:01:55.478253 [DQSOSCAuto] RK1, (LSB)MR18= 0xcee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3089 01:01:55.482004 CH0 RK1: MR19=403, MR18=CEE
3090 01:01:55.488447 CH0_RK1: MR19=0x403, MR18=0xCEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3091 01:01:55.491643 [RxdqsGatingPostProcess] freq 1200
3092 01:01:55.498551 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 01:01:55.501512 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 01:01:55.501585 best DQS1 dly(2T, 0.5T) = (0, 12)
3095 01:01:55.504947 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 01:01:55.508154 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3097 01:01:55.511564 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 01:01:55.514893 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 01:01:55.518326 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 01:01:55.521820 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 01:01:55.525033 Pre-setting of DQS Precalculation
3102 01:01:55.531908 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 01:01:55.531985 ==
3104 01:01:55.535166 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 01:01:55.538321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 01:01:55.538419 ==
3107 01:01:55.542111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 01:01:55.548450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 01:01:55.558131 [CA 0] Center 37 (7~68) winsize 62
3110 01:01:55.561056 [CA 1] Center 37 (7~68) winsize 62
3111 01:01:55.564505 [CA 2] Center 35 (5~65) winsize 61
3112 01:01:55.567748 [CA 3] Center 34 (4~65) winsize 62
3113 01:01:55.571125 [CA 4] Center 34 (4~64) winsize 61
3114 01:01:55.574376 [CA 5] Center 33 (3~63) winsize 61
3115 01:01:55.574487
3116 01:01:55.577688 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3117 01:01:55.577762
3118 01:01:55.581476 [CATrainingPosCal] consider 1 rank data
3119 01:01:55.584565 u2DelayCellTimex100 = 270/100 ps
3120 01:01:55.587813 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 01:01:55.591072 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 01:01:55.594937 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 01:01:55.601277 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3124 01:01:55.605077 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 01:01:55.608176 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3126 01:01:55.608275
3127 01:01:55.611700 CA PerBit enable=1, Macro0, CA PI delay=33
3128 01:01:55.611775
3129 01:01:55.615362 [CBTSetCACLKResult] CA Dly = 33
3130 01:01:55.615461 CS Dly: 7 (0~38)
3131 01:01:55.615536 ==
3132 01:01:55.618126 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 01:01:55.624896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 01:01:55.624974 ==
3135 01:01:55.628010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 01:01:55.634521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 01:01:55.643333 [CA 0] Center 37 (7~68) winsize 62
3138 01:01:55.646526 [CA 1] Center 37 (7~68) winsize 62
3139 01:01:55.649756 [CA 2] Center 35 (5~65) winsize 61
3140 01:01:55.653548 [CA 3] Center 35 (5~65) winsize 61
3141 01:01:55.656757 [CA 4] Center 35 (5~65) winsize 61
3142 01:01:55.660538 [CA 5] Center 34 (4~64) winsize 61
3143 01:01:55.660612
3144 01:01:55.663751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 01:01:55.663821
3146 01:01:55.666950 [CATrainingPosCal] consider 2 rank data
3147 01:01:55.670228 u2DelayCellTimex100 = 270/100 ps
3148 01:01:55.673496 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 01:01:55.676393 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 01:01:55.683524 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 01:01:55.686826 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3152 01:01:55.690070 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3153 01:01:55.693354 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3154 01:01:55.693455
3155 01:01:55.697077 CA PerBit enable=1, Macro0, CA PI delay=33
3156 01:01:55.697160
3157 01:01:55.700071 [CBTSetCACLKResult] CA Dly = 33
3158 01:01:55.700170 CS Dly: 8 (0~41)
3159 01:01:55.700259
3160 01:01:55.703427 ----->DramcWriteLeveling(PI) begin...
3161 01:01:55.703527 ==
3162 01:01:55.707235 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 01:01:55.713670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 01:01:55.713750 ==
3165 01:01:55.716707 Write leveling (Byte 0): 28 => 28
3166 01:01:55.720502 Write leveling (Byte 1): 28 => 28
3167 01:01:55.720601 DramcWriteLeveling(PI) end<-----
3168 01:01:55.723559
3169 01:01:55.723656 ==
3170 01:01:55.726826 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 01:01:55.730383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 01:01:55.730459 ==
3173 01:01:55.733475 [Gating] SW mode calibration
3174 01:01:55.740349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 01:01:55.743350 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 01:01:55.750205 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 01:01:55.754038 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 01:01:55.756647 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 01:01:55.763527 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 01:01:55.766771 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 01:01:55.770145 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 01:01:55.777043 0 15 24 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (0 0)
3183 01:01:55.780350 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3184 01:01:55.783552 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 01:01:55.789929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 01:01:55.793592 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 01:01:55.796651 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 01:01:55.803684 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 01:01:55.806745 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 01:01:55.810438 1 0 24 | B1->B0 | 3636 4444 | 0 0 | (1 1) (0 0)
3191 01:01:55.813394 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 01:01:55.820081 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 01:01:55.823418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 01:01:55.826941 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 01:01:55.833451 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 01:01:55.837026 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 01:01:55.840169 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 01:01:55.847061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 01:01:55.850325 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 01:01:55.853539 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 01:01:55.860256 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 01:01:55.863349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 01:01:55.867067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 01:01:55.873494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 01:01:55.876693 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 01:01:55.879988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 01:01:55.887005 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 01:01:55.890160 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 01:01:55.893513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 01:01:55.900039 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 01:01:55.903571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 01:01:55.906734 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 01:01:55.910045 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 01:01:55.916726 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 01:01:55.920083 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 01:01:55.923869 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 01:01:55.927106 Total UI for P1: 0, mck2ui 16
3218 01:01:55.930241 best dqsien dly found for B0: ( 1, 3, 26)
3219 01:01:55.934004 Total UI for P1: 0, mck2ui 16
3220 01:01:55.936865 best dqsien dly found for B1: ( 1, 3, 26)
3221 01:01:55.940328 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3222 01:01:55.943498 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3223 01:01:55.943580
3224 01:01:55.950289 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3225 01:01:55.954129 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3226 01:01:55.954211 [Gating] SW calibration Done
3227 01:01:55.957366 ==
3228 01:01:55.960553 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 01:01:55.963845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 01:01:55.963928 ==
3231 01:01:55.964025 RX Vref Scan: 0
3232 01:01:55.964107
3233 01:01:55.967282 RX Vref 0 -> 0, step: 1
3234 01:01:55.967364
3235 01:01:55.970711 RX Delay -40 -> 252, step: 8
3236 01:01:55.973811 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3237 01:01:55.977312 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3238 01:01:55.980403 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3239 01:01:55.987351 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3240 01:01:55.990647 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3241 01:01:55.993890 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3242 01:01:55.997182 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3243 01:01:56.000472 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3244 01:01:56.007112 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3245 01:01:56.010195 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3246 01:01:56.013795 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3247 01:01:56.016872 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3248 01:01:56.020039 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3249 01:01:56.026957 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3250 01:01:56.030208 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3251 01:01:56.033564 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3252 01:01:56.033646 ==
3253 01:01:56.037369 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 01:01:56.040539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 01:01:56.040622 ==
3256 01:01:56.043910 DQS Delay:
3257 01:01:56.043992 DQS0 = 0, DQS1 = 0
3258 01:01:56.047037 DQM Delay:
3259 01:01:56.047119 DQM0 = 120, DQM1 = 116
3260 01:01:56.050444 DQ Delay:
3261 01:01:56.053957 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3262 01:01:56.057047 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3263 01:01:56.060456 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3264 01:01:56.063974 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3265 01:01:56.064056
3266 01:01:56.064120
3267 01:01:56.064180 ==
3268 01:01:56.067281 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 01:01:56.070403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 01:01:56.070486 ==
3271 01:01:56.070551
3272 01:01:56.070612
3273 01:01:56.074048 TX Vref Scan disable
3274 01:01:56.076832 == TX Byte 0 ==
3275 01:01:56.080542 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3276 01:01:56.083617 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3277 01:01:56.087377 == TX Byte 1 ==
3278 01:01:56.090222 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3279 01:01:56.093519 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3280 01:01:56.093602 ==
3281 01:01:56.096931 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 01:01:56.100439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 01:01:56.103679 ==
3284 01:01:56.113770 TX Vref=22, minBit 11, minWin=24, winSum=412
3285 01:01:56.116911 TX Vref=24, minBit 9, minWin=25, winSum=419
3286 01:01:56.120559 TX Vref=26, minBit 9, minWin=24, winSum=422
3287 01:01:56.123611 TX Vref=28, minBit 1, minWin=25, winSum=426
3288 01:01:56.126804 TX Vref=30, minBit 10, minWin=25, winSum=431
3289 01:01:56.133764 TX Vref=32, minBit 11, minWin=25, winSum=429
3290 01:01:56.136982 [TxChooseVref] Worse bit 10, Min win 25, Win sum 431, Final Vref 30
3291 01:01:56.137066
3292 01:01:56.140190 Final TX Range 1 Vref 30
3293 01:01:56.140273
3294 01:01:56.140381 ==
3295 01:01:56.143322 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 01:01:56.147208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 01:01:56.149979 ==
3298 01:01:56.150060
3299 01:01:56.150124
3300 01:01:56.150185 TX Vref Scan disable
3301 01:01:56.153688 == TX Byte 0 ==
3302 01:01:56.156940 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3303 01:01:56.160152 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3304 01:01:56.163349 == TX Byte 1 ==
3305 01:01:56.166986 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3306 01:01:56.170014 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3307 01:01:56.173469
3308 01:01:56.173550 [DATLAT]
3309 01:01:56.173616 Freq=1200, CH1 RK0
3310 01:01:56.173677
3311 01:01:56.176990 DATLAT Default: 0xd
3312 01:01:56.177116 0, 0xFFFF, sum = 0
3313 01:01:56.180243 1, 0xFFFF, sum = 0
3314 01:01:56.180396 2, 0xFFFF, sum = 0
3315 01:01:56.183508 3, 0xFFFF, sum = 0
3316 01:01:56.183592 4, 0xFFFF, sum = 0
3317 01:01:56.186699 5, 0xFFFF, sum = 0
3318 01:01:56.190495 6, 0xFFFF, sum = 0
3319 01:01:56.190579 7, 0xFFFF, sum = 0
3320 01:01:56.193685 8, 0xFFFF, sum = 0
3321 01:01:56.193768 9, 0xFFFF, sum = 0
3322 01:01:56.196851 10, 0xFFFF, sum = 0
3323 01:01:56.196934 11, 0xFFFF, sum = 0
3324 01:01:56.200046 12, 0x0, sum = 1
3325 01:01:56.200129 13, 0x0, sum = 2
3326 01:01:56.203963 14, 0x0, sum = 3
3327 01:01:56.204046 15, 0x0, sum = 4
3328 01:01:56.204112 best_step = 13
3329 01:01:56.204172
3330 01:01:56.207212 ==
3331 01:01:56.210168 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 01:01:56.213610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 01:01:56.213693 ==
3334 01:01:56.213759 RX Vref Scan: 1
3335 01:01:56.213818
3336 01:01:56.216694 Set Vref Range= 32 -> 127
3337 01:01:56.216776
3338 01:01:56.220187 RX Vref 32 -> 127, step: 1
3339 01:01:56.220269
3340 01:01:56.223251 RX Delay -5 -> 252, step: 4
3341 01:01:56.223333
3342 01:01:56.226759 Set Vref, RX VrefLevel [Byte0]: 32
3343 01:01:56.230361 [Byte1]: 32
3344 01:01:56.230444
3345 01:01:56.233713 Set Vref, RX VrefLevel [Byte0]: 33
3346 01:01:56.236858 [Byte1]: 33
3347 01:01:56.236940
3348 01:01:56.240098 Set Vref, RX VrefLevel [Byte0]: 34
3349 01:01:56.243185 [Byte1]: 34
3350 01:01:56.247453
3351 01:01:56.247533 Set Vref, RX VrefLevel [Byte0]: 35
3352 01:01:56.251252 [Byte1]: 35
3353 01:01:56.255611
3354 01:01:56.255686 Set Vref, RX VrefLevel [Byte0]: 36
3355 01:01:56.258842 [Byte1]: 36
3356 01:01:56.263167
3357 01:01:56.263264 Set Vref, RX VrefLevel [Byte0]: 37
3358 01:01:56.266368 [Byte1]: 37
3359 01:01:56.271458
3360 01:01:56.271558 Set Vref, RX VrefLevel [Byte0]: 38
3361 01:01:56.274689 [Byte1]: 38
3362 01:01:56.279073
3363 01:01:56.279169 Set Vref, RX VrefLevel [Byte0]: 39
3364 01:01:56.282169 [Byte1]: 39
3365 01:01:56.286806
3366 01:01:56.286902 Set Vref, RX VrefLevel [Byte0]: 40
3367 01:01:56.290161 [Byte1]: 40
3368 01:01:56.294636
3369 01:01:56.294733 Set Vref, RX VrefLevel [Byte0]: 41
3370 01:01:56.297821 [Byte1]: 41
3371 01:01:56.302856
3372 01:01:56.302966 Set Vref, RX VrefLevel [Byte0]: 42
3373 01:01:56.306112 [Byte1]: 42
3374 01:01:56.310628
3375 01:01:56.310726 Set Vref, RX VrefLevel [Byte0]: 43
3376 01:01:56.313736 [Byte1]: 43
3377 01:01:56.318141
3378 01:01:56.318238 Set Vref, RX VrefLevel [Byte0]: 44
3379 01:01:56.321376 [Byte1]: 44
3380 01:01:56.326292
3381 01:01:56.326392 Set Vref, RX VrefLevel [Byte0]: 45
3382 01:01:56.329336 [Byte1]: 45
3383 01:01:56.334171
3384 01:01:56.334268 Set Vref, RX VrefLevel [Byte0]: 46
3385 01:01:56.337265 [Byte1]: 46
3386 01:01:56.342103
3387 01:01:56.342206 Set Vref, RX VrefLevel [Byte0]: 47
3388 01:01:56.345196 [Byte1]: 47
3389 01:01:56.349847
3390 01:01:56.349946 Set Vref, RX VrefLevel [Byte0]: 48
3391 01:01:56.353528 [Byte1]: 48
3392 01:01:56.357661
3393 01:01:56.357731 Set Vref, RX VrefLevel [Byte0]: 49
3394 01:01:56.360681 [Byte1]: 49
3395 01:01:56.365562
3396 01:01:56.365660 Set Vref, RX VrefLevel [Byte0]: 50
3397 01:01:56.368728 [Byte1]: 50
3398 01:01:56.373030
3399 01:01:56.373107 Set Vref, RX VrefLevel [Byte0]: 51
3400 01:01:56.376198 [Byte1]: 51
3401 01:01:56.380861
3402 01:01:56.380939 Set Vref, RX VrefLevel [Byte0]: 52
3403 01:01:56.384719 [Byte1]: 52
3404 01:01:56.388602
3405 01:01:56.388701 Set Vref, RX VrefLevel [Byte0]: 53
3406 01:01:56.392473 [Byte1]: 53
3407 01:01:56.396884
3408 01:01:56.396958 Set Vref, RX VrefLevel [Byte0]: 54
3409 01:01:56.400015 [Byte1]: 54
3410 01:01:56.404724
3411 01:01:56.404799 Set Vref, RX VrefLevel [Byte0]: 55
3412 01:01:56.408208 [Byte1]: 55
3413 01:01:56.412325
3414 01:01:56.412404 Set Vref, RX VrefLevel [Byte0]: 56
3415 01:01:56.415441 [Byte1]: 56
3416 01:01:56.420045
3417 01:01:56.420147 Set Vref, RX VrefLevel [Byte0]: 57
3418 01:01:56.423244 [Byte1]: 57
3419 01:01:56.428236
3420 01:01:56.428362 Set Vref, RX VrefLevel [Byte0]: 58
3421 01:01:56.431321 [Byte1]: 58
3422 01:01:56.435724
3423 01:01:56.435825 Set Vref, RX VrefLevel [Byte0]: 59
3424 01:01:56.439562 [Byte1]: 59
3425 01:01:56.444190
3426 01:01:56.444298 Set Vref, RX VrefLevel [Byte0]: 60
3427 01:01:56.447401 [Byte1]: 60
3428 01:01:56.451989
3429 01:01:56.452090 Set Vref, RX VrefLevel [Byte0]: 61
3430 01:01:56.455123 [Byte1]: 61
3431 01:01:56.459636
3432 01:01:56.459710 Set Vref, RX VrefLevel [Byte0]: 62
3433 01:01:56.462734 [Byte1]: 62
3434 01:01:56.467242
3435 01:01:56.467341 Set Vref, RX VrefLevel [Byte0]: 63
3436 01:01:56.470917 [Byte1]: 63
3437 01:01:56.475581
3438 01:01:56.475654 Set Vref, RX VrefLevel [Byte0]: 64
3439 01:01:56.478763 [Byte1]: 64
3440 01:01:56.483111
3441 01:01:56.483211 Set Vref, RX VrefLevel [Byte0]: 65
3442 01:01:56.486363 [Byte1]: 65
3443 01:01:56.490805
3444 01:01:56.490881 Set Vref, RX VrefLevel [Byte0]: 66
3445 01:01:56.494516 [Byte1]: 66
3446 01:01:56.499018
3447 01:01:56.499121 Set Vref, RX VrefLevel [Byte0]: 67
3448 01:01:56.501900 [Byte1]: 67
3449 01:01:56.506467
3450 01:01:56.506567 Set Vref, RX VrefLevel [Byte0]: 68
3451 01:01:56.510105 [Byte1]: 68
3452 01:01:56.514565
3453 01:01:56.514667 Final RX Vref Byte 0 = 53 to rank0
3454 01:01:56.517652 Final RX Vref Byte 1 = 53 to rank0
3455 01:01:56.520856 Final RX Vref Byte 0 = 53 to rank1
3456 01:01:56.524434 Final RX Vref Byte 1 = 53 to rank1==
3457 01:01:56.527671 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 01:01:56.534659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 01:01:56.534762 ==
3460 01:01:56.534854 DQS Delay:
3461 01:01:56.534941 DQS0 = 0, DQS1 = 0
3462 01:01:56.537675 DQM Delay:
3463 01:01:56.537773 DQM0 = 120, DQM1 = 117
3464 01:01:56.541405 DQ Delay:
3465 01:01:56.544424 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3466 01:01:56.547602 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3467 01:01:56.551019 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3468 01:01:56.554628 DQ12 =124, DQ13 =126, DQ14 =124, DQ15 =126
3469 01:01:56.554710
3470 01:01:56.554774
3471 01:01:56.561068 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
3472 01:01:56.564276 CH1 RK0: MR19=304, MR18=FD10
3473 01:01:56.571243 CH1_RK0: MR19=0x304, MR18=0xFD10, DQSOSC=403, MR23=63, INC=40, DEC=26
3474 01:01:56.571325
3475 01:01:56.574368 ----->DramcWriteLeveling(PI) begin...
3476 01:01:56.574451 ==
3477 01:01:56.578238 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 01:01:56.581504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 01:01:56.584498 ==
3480 01:01:56.584580 Write leveling (Byte 0): 26 => 26
3481 01:01:56.587666 Write leveling (Byte 1): 30 => 30
3482 01:01:56.591499 DramcWriteLeveling(PI) end<-----
3483 01:01:56.591582
3484 01:01:56.591646 ==
3485 01:01:56.594379 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 01:01:56.601137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 01:01:56.601219 ==
3488 01:01:56.601284 [Gating] SW mode calibration
3489 01:01:56.611200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 01:01:56.614956 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 01:01:56.618177 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 01:01:56.624512 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 01:01:56.628188 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 01:01:56.631452 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 01:01:56.638273 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 01:01:56.641311 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3497 01:01:56.645041 0 15 24 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 0)
3498 01:01:56.651680 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3499 01:01:56.654844 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 01:01:56.658530 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 01:01:56.664864 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 01:01:56.668503 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 01:01:56.671610 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 01:01:56.678303 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3505 01:01:56.681640 1 0 24 | B1->B0 | 4040 2727 | 0 0 | (0 0) (0 0)
3506 01:01:56.684725 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 01:01:56.691732 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 01:01:56.695019 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 01:01:56.698145 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 01:01:56.701377 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 01:01:56.708481 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 01:01:56.711756 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3513 01:01:56.714800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3514 01:01:56.721515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3515 01:01:56.725108 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 01:01:56.728197 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 01:01:56.735092 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 01:01:56.737936 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 01:01:56.741866 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 01:01:56.748299 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 01:01:56.751487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 01:01:56.754777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 01:01:56.761809 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 01:01:56.764843 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 01:01:56.768152 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 01:01:56.774696 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 01:01:56.778137 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 01:01:56.781123 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 01:01:56.787797 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3530 01:01:56.791077 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3531 01:01:56.794597 Total UI for P1: 0, mck2ui 16
3532 01:01:56.797710 best dqsien dly found for B1: ( 1, 3, 24)
3533 01:01:56.800901 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 01:01:56.804799 Total UI for P1: 0, mck2ui 16
3535 01:01:56.808010 best dqsien dly found for B0: ( 1, 3, 26)
3536 01:01:56.811277 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3537 01:01:56.814326 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3538 01:01:56.814407
3539 01:01:56.817530 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3540 01:01:56.824049 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3541 01:01:56.824131 [Gating] SW calibration Done
3542 01:01:56.827348 ==
3543 01:01:56.827429 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 01:01:56.834323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 01:01:56.834405 ==
3546 01:01:56.834470 RX Vref Scan: 0
3547 01:01:56.834530
3548 01:01:56.837151 RX Vref 0 -> 0, step: 1
3549 01:01:56.837233
3550 01:01:56.841005 RX Delay -40 -> 252, step: 8
3551 01:01:56.844172 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3552 01:01:56.847516 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3553 01:01:56.850617 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3554 01:01:56.857470 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3555 01:01:56.860642 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3556 01:01:56.864579 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3557 01:01:56.867258 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3558 01:01:56.870835 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3559 01:01:56.877781 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3560 01:01:56.880693 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3561 01:01:56.884209 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3562 01:01:56.887284 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3563 01:01:56.890953 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3564 01:01:56.897719 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3565 01:01:56.901130 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3566 01:01:56.904075 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3567 01:01:56.904158 ==
3568 01:01:56.907400 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 01:01:56.910494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 01:01:56.910576 ==
3571 01:01:56.913929 DQS Delay:
3572 01:01:56.914011 DQS0 = 0, DQS1 = 0
3573 01:01:56.917488 DQM Delay:
3574 01:01:56.917570 DQM0 = 121, DQM1 = 117
3575 01:01:56.920669 DQ Delay:
3576 01:01:56.923887 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3577 01:01:56.927061 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3578 01:01:56.930355 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3579 01:01:56.934225 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3580 01:01:56.934307
3581 01:01:56.934372
3582 01:01:56.934432 ==
3583 01:01:56.937319 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 01:01:56.940565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 01:01:56.940648 ==
3586 01:01:56.940712
3587 01:01:56.940772
3588 01:01:56.943688 TX Vref Scan disable
3589 01:01:56.947431 == TX Byte 0 ==
3590 01:01:56.950682 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3591 01:01:56.953815 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3592 01:01:56.957419 == TX Byte 1 ==
3593 01:01:56.960331 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3594 01:01:56.963703 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3595 01:01:56.963784 ==
3596 01:01:56.967152 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 01:01:56.973481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 01:01:56.973565 ==
3599 01:01:56.984092 TX Vref=22, minBit 9, minWin=25, winSum=420
3600 01:01:56.987200 TX Vref=24, minBit 10, minWin=25, winSum=425
3601 01:01:56.990598 TX Vref=26, minBit 2, minWin=26, winSum=429
3602 01:01:56.994114 TX Vref=28, minBit 10, minWin=26, winSum=436
3603 01:01:56.997171 TX Vref=30, minBit 9, minWin=26, winSum=436
3604 01:01:57.004409 TX Vref=32, minBit 9, minWin=26, winSum=434
3605 01:01:57.007483 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 28
3606 01:01:57.007564
3607 01:01:57.010782 Final TX Range 1 Vref 28
3608 01:01:57.010863
3609 01:01:57.010927 ==
3610 01:01:57.013984 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 01:01:57.017468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 01:01:57.020562 ==
3613 01:01:57.020644
3614 01:01:57.020707
3615 01:01:57.020766 TX Vref Scan disable
3616 01:01:57.023874 == TX Byte 0 ==
3617 01:01:57.027285 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3618 01:01:57.034168 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3619 01:01:57.034250 == TX Byte 1 ==
3620 01:01:57.037500 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3621 01:01:57.043920 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3622 01:01:57.044002
3623 01:01:57.044066 [DATLAT]
3624 01:01:57.044126 Freq=1200, CH1 RK1
3625 01:01:57.044183
3626 01:01:57.046992 DATLAT Default: 0xd
3627 01:01:57.047073 0, 0xFFFF, sum = 0
3628 01:01:57.050932 1, 0xFFFF, sum = 0
3629 01:01:57.054196 2, 0xFFFF, sum = 0
3630 01:01:57.054279 3, 0xFFFF, sum = 0
3631 01:01:57.057478 4, 0xFFFF, sum = 0
3632 01:01:57.057561 5, 0xFFFF, sum = 0
3633 01:01:57.060663 6, 0xFFFF, sum = 0
3634 01:01:57.060747 7, 0xFFFF, sum = 0
3635 01:01:57.063987 8, 0xFFFF, sum = 0
3636 01:01:57.064071 9, 0xFFFF, sum = 0
3637 01:01:57.066984 10, 0xFFFF, sum = 0
3638 01:01:57.067068 11, 0xFFFF, sum = 0
3639 01:01:57.070711 12, 0x0, sum = 1
3640 01:01:57.070794 13, 0x0, sum = 2
3641 01:01:57.073737 14, 0x0, sum = 3
3642 01:01:57.073821 15, 0x0, sum = 4
3643 01:01:57.077265 best_step = 13
3644 01:01:57.077347
3645 01:01:57.077411 ==
3646 01:01:57.080333 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 01:01:57.083908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 01:01:57.083991 ==
3649 01:01:57.084072 RX Vref Scan: 0
3650 01:01:57.087230
3651 01:01:57.087312 RX Vref 0 -> 0, step: 1
3652 01:01:57.087377
3653 01:01:57.090292 RX Delay -5 -> 252, step: 4
3654 01:01:57.093714 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3655 01:01:57.100232 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3656 01:01:57.103732 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3657 01:01:57.106641 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3658 01:01:57.110082 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3659 01:01:57.114093 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3660 01:01:57.120469 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3661 01:01:57.123566 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3662 01:01:57.126760 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3663 01:01:57.130529 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3664 01:01:57.133551 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3665 01:01:57.140030 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3666 01:01:57.143506 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3667 01:01:57.146901 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3668 01:01:57.149959 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3669 01:01:57.156856 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3670 01:01:57.156938 ==
3671 01:01:57.160162 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 01:01:57.163219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 01:01:57.163301 ==
3674 01:01:57.163394 DQS Delay:
3675 01:01:57.166506 DQS0 = 0, DQS1 = 0
3676 01:01:57.166587 DQM Delay:
3677 01:01:57.169734 DQM0 = 120, DQM1 = 118
3678 01:01:57.169816 DQ Delay:
3679 01:01:57.173370 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3680 01:01:57.176548 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3681 01:01:57.179912 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3682 01:01:57.183131 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3683 01:01:57.183212
3684 01:01:57.183276
3685 01:01:57.192901 [DQSOSCAuto] RK1, (LSB)MR18= 0xeea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3686 01:01:57.196593 CH1 RK1: MR19=403, MR18=EEA
3687 01:01:57.199528 CH1_RK1: MR19=0x403, MR18=0xEEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3688 01:01:57.202765 [RxdqsGatingPostProcess] freq 1200
3689 01:01:57.209809 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3690 01:01:57.212668 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 01:01:57.215882 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 01:01:57.219486 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 01:01:57.222823 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 01:01:57.225969 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 01:01:57.229332 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 01:01:57.232417 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 01:01:57.236170 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 01:01:57.239325 Pre-setting of DQS Precalculation
3699 01:01:57.242503 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3700 01:01:57.249429 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3701 01:01:57.255755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3702 01:01:57.259532
3703 01:01:57.259613
3704 01:01:57.259677 [Calibration Summary] 2400 Mbps
3705 01:01:57.262844 CH 0, Rank 0
3706 01:01:57.262925 SW Impedance : PASS
3707 01:01:57.266143 DUTY Scan : NO K
3708 01:01:57.269370 ZQ Calibration : PASS
3709 01:01:57.269462 Jitter Meter : NO K
3710 01:01:57.272683 CBT Training : PASS
3711 01:01:57.275703 Write leveling : PASS
3712 01:01:57.275784 RX DQS gating : PASS
3713 01:01:57.279387 RX DQ/DQS(RDDQC) : PASS
3714 01:01:57.282585 TX DQ/DQS : PASS
3715 01:01:57.282667 RX DATLAT : PASS
3716 01:01:57.285867 RX DQ/DQS(Engine): PASS
3717 01:01:57.289150 TX OE : NO K
3718 01:01:57.289231 All Pass.
3719 01:01:57.289296
3720 01:01:57.289356 CH 0, Rank 1
3721 01:01:57.292555 SW Impedance : PASS
3722 01:01:57.295666 DUTY Scan : NO K
3723 01:01:57.295748 ZQ Calibration : PASS
3724 01:01:57.298823 Jitter Meter : NO K
3725 01:01:57.302698 CBT Training : PASS
3726 01:01:57.302779 Write leveling : PASS
3727 01:01:57.305834 RX DQS gating : PASS
3728 01:01:57.305915 RX DQ/DQS(RDDQC) : PASS
3729 01:01:57.309091 TX DQ/DQS : PASS
3730 01:01:57.312593 RX DATLAT : PASS
3731 01:01:57.312675 RX DQ/DQS(Engine): PASS
3732 01:01:57.315384 TX OE : NO K
3733 01:01:57.315466 All Pass.
3734 01:01:57.315540
3735 01:01:57.319038 CH 1, Rank 0
3736 01:01:57.319119 SW Impedance : PASS
3737 01:01:57.322181 DUTY Scan : NO K
3738 01:01:57.325918 ZQ Calibration : PASS
3739 01:01:57.325999 Jitter Meter : NO K
3740 01:01:57.329310 CBT Training : PASS
3741 01:01:57.332292 Write leveling : PASS
3742 01:01:57.332390 RX DQS gating : PASS
3743 01:01:57.335633 RX DQ/DQS(RDDQC) : PASS
3744 01:01:57.339066 TX DQ/DQS : PASS
3745 01:01:57.339148 RX DATLAT : PASS
3746 01:01:57.342244 RX DQ/DQS(Engine): PASS
3747 01:01:57.345320 TX OE : NO K
3748 01:01:57.345401 All Pass.
3749 01:01:57.345465
3750 01:01:57.345525 CH 1, Rank 1
3751 01:01:57.348989 SW Impedance : PASS
3752 01:01:57.352259 DUTY Scan : NO K
3753 01:01:57.352368 ZQ Calibration : PASS
3754 01:01:57.355521 Jitter Meter : NO K
3755 01:01:57.355602 CBT Training : PASS
3756 01:01:57.358625 Write leveling : PASS
3757 01:01:57.362428 RX DQS gating : PASS
3758 01:01:57.362510 RX DQ/DQS(RDDQC) : PASS
3759 01:01:57.365556 TX DQ/DQS : PASS
3760 01:01:57.368966 RX DATLAT : PASS
3761 01:01:57.369048 RX DQ/DQS(Engine): PASS
3762 01:01:57.372228 TX OE : NO K
3763 01:01:57.372348 All Pass.
3764 01:01:57.372499
3765 01:01:57.375883 DramC Write-DBI off
3766 01:01:57.378907 PER_BANK_REFRESH: Hybrid Mode
3767 01:01:57.378996 TX_TRACKING: ON
3768 01:01:57.389114 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3769 01:01:57.392230 [FAST_K] Save calibration result to emmc
3770 01:01:57.395514 dramc_set_vcore_voltage set vcore to 650000
3771 01:01:57.398579 Read voltage for 600, 5
3772 01:01:57.398661 Vio18 = 0
3773 01:01:57.398725 Vcore = 650000
3774 01:01:57.402163 Vdram = 0
3775 01:01:57.402244 Vddq = 0
3776 01:01:57.402308 Vmddr = 0
3777 01:01:57.408749 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3778 01:01:57.411781 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3779 01:01:57.415657 MEM_TYPE=3, freq_sel=19
3780 01:01:57.418723 sv_algorithm_assistance_LP4_1600
3781 01:01:57.421737 ============ PULL DRAM RESETB DOWN ============
3782 01:01:57.428499 ========== PULL DRAM RESETB DOWN end =========
3783 01:01:57.431673 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3784 01:01:57.435536 ===================================
3785 01:01:57.438421 LPDDR4 DRAM CONFIGURATION
3786 01:01:57.441523 ===================================
3787 01:01:57.441606 EX_ROW_EN[0] = 0x0
3788 01:01:57.444986 EX_ROW_EN[1] = 0x0
3789 01:01:57.445068 LP4Y_EN = 0x0
3790 01:01:57.448713 WORK_FSP = 0x0
3791 01:01:57.448795 WL = 0x2
3792 01:01:57.451678 RL = 0x2
3793 01:01:57.451760 BL = 0x2
3794 01:01:57.455195 RPST = 0x0
3795 01:01:57.455277 RD_PRE = 0x0
3796 01:01:57.458138 WR_PRE = 0x1
3797 01:01:57.458220 WR_PST = 0x0
3798 01:01:57.461463 DBI_WR = 0x0
3799 01:01:57.464710 DBI_RD = 0x0
3800 01:01:57.464792 OTF = 0x1
3801 01:01:57.468065 ===================================
3802 01:01:57.471880 ===================================
3803 01:01:57.471963 ANA top config
3804 01:01:57.474958 ===================================
3805 01:01:57.478161 DLL_ASYNC_EN = 0
3806 01:01:57.481645 ALL_SLAVE_EN = 1
3807 01:01:57.484707 NEW_RANK_MODE = 1
3808 01:01:57.487924 DLL_IDLE_MODE = 1
3809 01:01:57.488006 LP45_APHY_COMB_EN = 1
3810 01:01:57.491538 TX_ODT_DIS = 1
3811 01:01:57.495134 NEW_8X_MODE = 1
3812 01:01:57.498478 ===================================
3813 01:01:57.501655 ===================================
3814 01:01:57.504661 data_rate = 1200
3815 01:01:57.507840 CKR = 1
3816 01:01:57.507921 DQ_P2S_RATIO = 8
3817 01:01:57.511644 ===================================
3818 01:01:57.514948 CA_P2S_RATIO = 8
3819 01:01:57.518158 DQ_CA_OPEN = 0
3820 01:01:57.521465 DQ_SEMI_OPEN = 0
3821 01:01:57.524491 CA_SEMI_OPEN = 0
3822 01:01:57.528167 CA_FULL_RATE = 0
3823 01:01:57.528248 DQ_CKDIV4_EN = 1
3824 01:01:57.531186 CA_CKDIV4_EN = 1
3825 01:01:57.534445 CA_PREDIV_EN = 0
3826 01:01:57.537653 PH8_DLY = 0
3827 01:01:57.541434 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3828 01:01:57.544630 DQ_AAMCK_DIV = 4
3829 01:01:57.544711 CA_AAMCK_DIV = 4
3830 01:01:57.547570 CA_ADMCK_DIV = 4
3831 01:01:57.550938 DQ_TRACK_CA_EN = 0
3832 01:01:57.554258 CA_PICK = 600
3833 01:01:57.557804 CA_MCKIO = 600
3834 01:01:57.560970 MCKIO_SEMI = 0
3835 01:01:57.564103 PLL_FREQ = 2288
3836 01:01:57.564184 DQ_UI_PI_RATIO = 32
3837 01:01:57.567814 CA_UI_PI_RATIO = 0
3838 01:01:57.571262 ===================================
3839 01:01:57.574193 ===================================
3840 01:01:57.577531 memory_type:LPDDR4
3841 01:01:57.580714 GP_NUM : 10
3842 01:01:57.580796 SRAM_EN : 1
3843 01:01:57.584585 MD32_EN : 0
3844 01:01:57.587701 ===================================
3845 01:01:57.590983 [ANA_INIT] >>>>>>>>>>>>>>
3846 01:01:57.591066 <<<<<< [CONFIGURE PHASE]: ANA_TX
3847 01:01:57.594009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3848 01:01:57.597284 ===================================
3849 01:01:57.600668 data_rate = 1200,PCW = 0X5800
3850 01:01:57.604179 ===================================
3851 01:01:57.607526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3852 01:01:57.614032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 01:01:57.618090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 01:01:57.624461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3855 01:01:57.627494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3856 01:01:57.631256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3857 01:01:57.634323 [ANA_INIT] flow start
3858 01:01:57.634405 [ANA_INIT] PLL >>>>>>>>
3859 01:01:57.637972 [ANA_INIT] PLL <<<<<<<<
3860 01:01:57.641063 [ANA_INIT] MIDPI >>>>>>>>
3861 01:01:57.641146 [ANA_INIT] MIDPI <<<<<<<<
3862 01:01:57.644297 [ANA_INIT] DLL >>>>>>>>
3863 01:01:57.647500 [ANA_INIT] flow end
3864 01:01:57.650715 ============ LP4 DIFF to SE enter ============
3865 01:01:57.653960 ============ LP4 DIFF to SE exit ============
3866 01:01:57.657221 [ANA_INIT] <<<<<<<<<<<<<
3867 01:01:57.660809 [Flow] Enable top DCM control >>>>>
3868 01:01:57.664324 [Flow] Enable top DCM control <<<<<
3869 01:01:57.667206 Enable DLL master slave shuffle
3870 01:01:57.670856 ==============================================================
3871 01:01:57.674144 Gating Mode config
3872 01:01:57.680436 ==============================================================
3873 01:01:57.680518 Config description:
3874 01:01:57.690617 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3875 01:01:57.697358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3876 01:01:57.703580 SELPH_MODE 0: By rank 1: By Phase
3877 01:01:57.707268 ==============================================================
3878 01:01:57.710244 GAT_TRACK_EN = 1
3879 01:01:57.713511 RX_GATING_MODE = 2
3880 01:01:57.716964 RX_GATING_TRACK_MODE = 2
3881 01:01:57.720173 SELPH_MODE = 1
3882 01:01:57.723535 PICG_EARLY_EN = 1
3883 01:01:57.727407 VALID_LAT_VALUE = 1
3884 01:01:57.730196 ==============================================================
3885 01:01:57.733445 Enter into Gating configuration >>>>
3886 01:01:57.737192 Exit from Gating configuration <<<<
3887 01:01:57.740279 Enter into DVFS_PRE_config >>>>>
3888 01:01:57.753530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3889 01:01:57.753609 Exit from DVFS_PRE_config <<<<<
3890 01:01:57.756829 Enter into PICG configuration >>>>
3891 01:01:57.760106 Exit from PICG configuration <<<<
3892 01:01:57.763514 [RX_INPUT] configuration >>>>>
3893 01:01:57.767094 [RX_INPUT] configuration <<<<<
3894 01:01:57.773789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3895 01:01:57.776736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3896 01:01:57.783215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 01:01:57.790241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 01:01:57.796590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 01:01:57.803027 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 01:01:57.806531 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3901 01:01:57.809817 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3902 01:01:57.813364 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3903 01:01:57.820091 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3904 01:01:57.822975 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3905 01:01:57.826512 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 01:01:57.829635 ===================================
3907 01:01:57.833489 LPDDR4 DRAM CONFIGURATION
3908 01:01:57.836555 ===================================
3909 01:01:57.839663 EX_ROW_EN[0] = 0x0
3910 01:01:57.839734 EX_ROW_EN[1] = 0x0
3911 01:01:57.842840 LP4Y_EN = 0x0
3912 01:01:57.842915 WORK_FSP = 0x0
3913 01:01:57.846402 WL = 0x2
3914 01:01:57.846480 RL = 0x2
3915 01:01:57.849909 BL = 0x2
3916 01:01:57.849983 RPST = 0x0
3917 01:01:57.853141 RD_PRE = 0x0
3918 01:01:57.853211 WR_PRE = 0x1
3919 01:01:57.856347 WR_PST = 0x0
3920 01:01:57.856423 DBI_WR = 0x0
3921 01:01:57.859528 DBI_RD = 0x0
3922 01:01:57.859602 OTF = 0x1
3923 01:01:57.862877 ===================================
3924 01:01:57.869717 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3925 01:01:57.872783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3926 01:01:57.876258 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 01:01:57.879467 ===================================
3928 01:01:57.882756 LPDDR4 DRAM CONFIGURATION
3929 01:01:57.886488 ===================================
3930 01:01:57.886563 EX_ROW_EN[0] = 0x10
3931 01:01:57.889366 EX_ROW_EN[1] = 0x0
3932 01:01:57.893077 LP4Y_EN = 0x0
3933 01:01:57.893158 WORK_FSP = 0x0
3934 01:01:57.896231 WL = 0x2
3935 01:01:57.896317 RL = 0x2
3936 01:01:57.899434 BL = 0x2
3937 01:01:57.899509 RPST = 0x0
3938 01:01:57.903233 RD_PRE = 0x0
3939 01:01:57.903305 WR_PRE = 0x1
3940 01:01:57.906332 WR_PST = 0x0
3941 01:01:57.906409 DBI_WR = 0x0
3942 01:01:57.909473 DBI_RD = 0x0
3943 01:01:57.909544 OTF = 0x1
3944 01:01:57.912979 ===================================
3945 01:01:57.919653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3946 01:01:57.923736 nWR fixed to 30
3947 01:01:57.927245 [ModeRegInit_LP4] CH0 RK0
3948 01:01:57.927326 [ModeRegInit_LP4] CH0 RK1
3949 01:01:57.930535 [ModeRegInit_LP4] CH1 RK0
3950 01:01:57.933982 [ModeRegInit_LP4] CH1 RK1
3951 01:01:57.934063 match AC timing 17
3952 01:01:57.940434 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3953 01:01:57.943725 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3954 01:01:57.947350 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3955 01:01:57.953502 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3956 01:01:57.956920 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3957 01:01:57.957002 ==
3958 01:01:57.960874 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 01:01:57.963644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 01:01:57.963728 ==
3961 01:01:57.970731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 01:01:57.977230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3963 01:01:57.980269 [CA 0] Center 35 (5~66) winsize 62
3964 01:01:57.983855 [CA 1] Center 35 (5~66) winsize 62
3965 01:01:57.987030 [CA 2] Center 33 (3~64) winsize 62
3966 01:01:57.990193 [CA 3] Center 33 (2~64) winsize 63
3967 01:01:57.993338 [CA 4] Center 33 (2~64) winsize 63
3968 01:01:57.996846 [CA 5] Center 32 (2~63) winsize 62
3969 01:01:57.996917
3970 01:01:58.000452 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3971 01:01:58.000530
3972 01:01:58.003690 [CATrainingPosCal] consider 1 rank data
3973 01:01:58.006955 u2DelayCellTimex100 = 270/100 ps
3974 01:01:58.010125 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3975 01:01:58.013843 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3976 01:01:58.017015 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3977 01:01:58.020059 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3978 01:01:58.023490 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3979 01:01:58.026637 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3980 01:01:58.026708
3981 01:01:58.033239 CA PerBit enable=1, Macro0, CA PI delay=32
3982 01:01:58.033317
3983 01:01:58.036813 [CBTSetCACLKResult] CA Dly = 32
3984 01:01:58.036890 CS Dly: 4 (0~35)
3985 01:01:58.036961 ==
3986 01:01:58.040358 Dram Type= 6, Freq= 0, CH_0, rank 1
3987 01:01:58.043563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 01:01:58.043640 ==
3989 01:01:58.049952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 01:01:58.057020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 01:01:58.060262 [CA 0] Center 35 (5~66) winsize 62
3992 01:01:58.063708 [CA 1] Center 35 (5~66) winsize 62
3993 01:01:58.066682 [CA 2] Center 34 (3~65) winsize 63
3994 01:01:58.069849 [CA 3] Center 33 (3~64) winsize 62
3995 01:01:58.073091 [CA 4] Center 33 (2~64) winsize 63
3996 01:01:58.076417 [CA 5] Center 32 (2~63) winsize 62
3997 01:01:58.076500
3998 01:01:58.079675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 01:01:58.079758
4000 01:01:58.083407 [CATrainingPosCal] consider 2 rank data
4001 01:01:58.086533 u2DelayCellTimex100 = 270/100 ps
4002 01:01:58.089867 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4003 01:01:58.093040 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4004 01:01:58.096878 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4005 01:01:58.099995 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4006 01:01:58.103452 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4007 01:01:58.110121 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4008 01:01:58.110200
4009 01:01:58.113214 CA PerBit enable=1, Macro0, CA PI delay=32
4010 01:01:58.113288
4011 01:01:58.116442 [CBTSetCACLKResult] CA Dly = 32
4012 01:01:58.116512 CS Dly: 5 (0~37)
4013 01:01:58.116574
4014 01:01:58.119705 ----->DramcWriteLeveling(PI) begin...
4015 01:01:58.119777 ==
4016 01:01:58.122961 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 01:01:58.129625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 01:01:58.129700 ==
4019 01:01:58.133095 Write leveling (Byte 0): 34 => 34
4020 01:01:58.133166 Write leveling (Byte 1): 31 => 31
4021 01:01:58.136105 DramcWriteLeveling(PI) end<-----
4022 01:01:58.136175
4023 01:01:58.136234 ==
4024 01:01:58.139803 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 01:01:58.146894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 01:01:58.146981 ==
4027 01:01:58.149443 [Gating] SW mode calibration
4028 01:01:58.156584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4029 01:01:58.159737 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4030 01:01:58.166022 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 01:01:58.169562 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 01:01:58.172733 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 01:01:58.179703 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
4034 01:01:58.182658 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
4035 01:01:58.186098 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 01:01:58.193012 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 01:01:58.196177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 01:01:58.199616 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 01:01:58.202652 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 01:01:58.209383 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 01:01:58.213236 0 10 12 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
4042 01:01:58.216108 0 10 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
4043 01:01:58.223092 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 01:01:58.226254 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 01:01:58.229421 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 01:01:58.236361 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 01:01:58.239327 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 01:01:58.242956 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 01:01:58.249268 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4050 01:01:58.252785 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4051 01:01:58.255902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 01:01:58.262896 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 01:01:58.266012 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 01:01:58.269230 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 01:01:58.276168 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 01:01:58.279403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 01:01:58.282607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 01:01:58.289023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 01:01:58.292744 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 01:01:58.295901 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 01:01:58.302735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 01:01:58.305547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 01:01:58.309277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 01:01:58.315602 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 01:01:58.318854 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4066 01:01:58.322221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4067 01:01:58.325894 Total UI for P1: 0, mck2ui 16
4068 01:01:58.328805 best dqsien dly found for B0: ( 0, 13, 12)
4069 01:01:58.335391 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 01:01:58.335474 Total UI for P1: 0, mck2ui 16
4071 01:01:58.339197 best dqsien dly found for B1: ( 0, 13, 16)
4072 01:01:58.345417 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4073 01:01:58.349115 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4074 01:01:58.349198
4075 01:01:58.351986 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4076 01:01:58.355908 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4077 01:01:58.358915 [Gating] SW calibration Done
4078 01:01:58.358997 ==
4079 01:01:58.362411 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 01:01:58.365462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 01:01:58.365546 ==
4082 01:01:58.368748 RX Vref Scan: 0
4083 01:01:58.368830
4084 01:01:58.368895 RX Vref 0 -> 0, step: 1
4085 01:01:58.368956
4086 01:01:58.372466 RX Delay -230 -> 252, step: 16
4087 01:01:58.375662 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4088 01:01:58.382431 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4089 01:01:58.385594 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4090 01:01:58.388809 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4091 01:01:58.392030 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4092 01:01:58.395277 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4093 01:01:58.402052 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4094 01:01:58.405161 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4095 01:01:58.409167 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4096 01:01:58.412307 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4097 01:01:58.418742 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4098 01:01:58.421923 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4099 01:01:58.425674 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4100 01:01:58.428522 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4101 01:01:58.435324 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4102 01:01:58.438503 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4103 01:01:58.438586 ==
4104 01:01:58.441632 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 01:01:58.444767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 01:01:58.444850 ==
4107 01:01:58.448217 DQS Delay:
4108 01:01:58.448336 DQS0 = 0, DQS1 = 0
4109 01:01:58.448403 DQM Delay:
4110 01:01:58.451588 DQM0 = 53, DQM1 = 46
4111 01:01:58.451701 DQ Delay:
4112 01:01:58.455077 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4113 01:01:58.458073 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4114 01:01:58.461316 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4115 01:01:58.464759 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4116 01:01:58.464841
4117 01:01:58.464906
4118 01:01:58.464966 ==
4119 01:01:58.467915 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 01:01:58.474603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 01:01:58.474686 ==
4122 01:01:58.474752
4123 01:01:58.474812
4124 01:01:58.474870 TX Vref Scan disable
4125 01:01:58.478533 == TX Byte 0 ==
4126 01:01:58.482194 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4127 01:01:58.488358 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4128 01:01:58.488440 == TX Byte 1 ==
4129 01:01:58.491512 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4130 01:01:58.498715 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4131 01:01:58.498798 ==
4132 01:01:58.502024 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 01:01:58.505119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 01:01:58.505202 ==
4135 01:01:58.505268
4136 01:01:58.505327
4137 01:01:58.508336 TX Vref Scan disable
4138 01:01:58.511477 == TX Byte 0 ==
4139 01:01:58.515765 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4140 01:01:58.518599 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4141 01:01:58.521704 == TX Byte 1 ==
4142 01:01:58.525027 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4143 01:01:58.528813 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4144 01:01:58.528896
4145 01:01:58.528961 [DATLAT]
4146 01:01:58.531808 Freq=600, CH0 RK0
4147 01:01:58.531890
4148 01:01:58.531956 DATLAT Default: 0x9
4149 01:01:58.535091 0, 0xFFFF, sum = 0
4150 01:01:58.535164 1, 0xFFFF, sum = 0
4151 01:01:58.538261 2, 0xFFFF, sum = 0
4152 01:01:58.541978 3, 0xFFFF, sum = 0
4153 01:01:58.542050 4, 0xFFFF, sum = 0
4154 01:01:58.545156 5, 0xFFFF, sum = 0
4155 01:01:58.545233 6, 0xFFFF, sum = 0
4156 01:01:58.548442 7, 0xFFFF, sum = 0
4157 01:01:58.548516 8, 0x0, sum = 1
4158 01:01:58.548578 9, 0x0, sum = 2
4159 01:01:58.551529 10, 0x0, sum = 3
4160 01:01:58.551604 11, 0x0, sum = 4
4161 01:01:58.555297 best_step = 9
4162 01:01:58.555376
4163 01:01:58.555437 ==
4164 01:01:58.558358 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 01:01:58.561540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 01:01:58.561615 ==
4167 01:01:58.565188 RX Vref Scan: 1
4168 01:01:58.565256
4169 01:01:58.565316 RX Vref 0 -> 0, step: 1
4170 01:01:58.565380
4171 01:01:58.568546 RX Delay -163 -> 252, step: 8
4172 01:01:58.568618
4173 01:01:58.571806 Set Vref, RX VrefLevel [Byte0]: 55
4174 01:01:58.574980 [Byte1]: 58
4175 01:01:58.578801
4176 01:01:58.578871 Final RX Vref Byte 0 = 55 to rank0
4177 01:01:58.582383 Final RX Vref Byte 1 = 58 to rank0
4178 01:01:58.585418 Final RX Vref Byte 0 = 55 to rank1
4179 01:01:58.588923 Final RX Vref Byte 1 = 58 to rank1==
4180 01:01:58.592128 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 01:01:58.599201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 01:01:58.599287 ==
4183 01:01:58.599353 DQS Delay:
4184 01:01:58.599413 DQS0 = 0, DQS1 = 0
4185 01:01:58.602511 DQM Delay:
4186 01:01:58.602583 DQM0 = 52, DQM1 = 47
4187 01:01:58.605613 DQ Delay:
4188 01:01:58.608743 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4189 01:01:58.612482 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4190 01:01:58.612559 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =44
4191 01:01:58.618918 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =52
4192 01:01:58.618994
4193 01:01:58.619057
4194 01:01:58.625453 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4195 01:01:58.628602 CH0 RK0: MR19=808, MR18=7366
4196 01:01:58.635552 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4197 01:01:58.635635
4198 01:01:58.638876 ----->DramcWriteLeveling(PI) begin...
4199 01:01:58.638960 ==
4200 01:01:58.642644 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 01:01:58.645810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 01:01:58.645930 ==
4203 01:01:58.649015 Write leveling (Byte 0): 34 => 34
4204 01:01:58.652097 Write leveling (Byte 1): 31 => 31
4205 01:01:58.655805 DramcWriteLeveling(PI) end<-----
4206 01:01:58.655887
4207 01:01:58.655952 ==
4208 01:01:58.659003 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 01:01:58.662139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 01:01:58.662214 ==
4211 01:01:58.665832 [Gating] SW mode calibration
4212 01:01:58.672223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 01:01:58.679001 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4214 01:01:58.682283 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 01:01:58.685309 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 01:01:58.691787 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 01:01:58.695642 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4218 01:01:58.698836 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (1 1) (0 0)
4219 01:01:58.705003 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 01:01:58.708201 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 01:01:58.711510 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 01:01:58.718764 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 01:01:58.721759 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 01:01:58.724964 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 01:01:58.731532 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4226 01:01:58.735035 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4227 01:01:58.738540 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 01:01:58.744936 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 01:01:58.748091 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 01:01:58.751801 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 01:01:58.758151 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 01:01:58.761811 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 01:01:58.764855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4234 01:01:58.771076 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 01:01:58.774912 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 01:01:58.778099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 01:01:58.784589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 01:01:58.787766 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 01:01:58.791530 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 01:01:58.797831 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 01:01:58.801018 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 01:01:58.804201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 01:01:58.810674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 01:01:58.814507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 01:01:58.817577 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 01:01:58.824014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 01:01:58.827590 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 01:01:58.830690 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 01:01:58.837609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4250 01:01:58.837687 Total UI for P1: 0, mck2ui 16
4251 01:01:58.844252 best dqsien dly found for B0: ( 0, 13, 10)
4252 01:01:58.847532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 01:01:58.850916 Total UI for P1: 0, mck2ui 16
4254 01:01:58.854201 best dqsien dly found for B1: ( 0, 13, 12)
4255 01:01:58.857206 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4256 01:01:58.860742 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4257 01:01:58.860838
4258 01:01:58.863827 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4259 01:01:58.867072 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 01:01:58.870396 [Gating] SW calibration Done
4261 01:01:58.870468 ==
4262 01:01:58.873889 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 01:01:58.877663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 01:01:58.880499 ==
4265 01:01:58.880573 RX Vref Scan: 0
4266 01:01:58.880643
4267 01:01:58.884086 RX Vref 0 -> 0, step: 1
4268 01:01:58.884160
4269 01:01:58.887189 RX Delay -230 -> 252, step: 16
4270 01:01:58.890577 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4271 01:01:58.894161 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4272 01:01:58.897579 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4273 01:01:58.900733 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4274 01:01:58.907253 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4275 01:01:58.911068 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4276 01:01:58.914311 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4277 01:01:58.917505 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4278 01:01:58.923835 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4279 01:01:58.927050 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4280 01:01:58.930768 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4281 01:01:58.933813 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4282 01:01:58.940563 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4283 01:01:58.943723 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4284 01:01:58.947030 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4285 01:01:58.950341 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4286 01:01:58.950412 ==
4287 01:01:58.954134 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 01:01:58.960521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 01:01:58.960594 ==
4290 01:01:58.960657 DQS Delay:
4291 01:01:58.963693 DQS0 = 0, DQS1 = 0
4292 01:01:58.963761 DQM Delay:
4293 01:01:58.963821 DQM0 = 51, DQM1 = 42
4294 01:01:58.966937 DQ Delay:
4295 01:01:58.970160 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4296 01:01:58.974069 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4297 01:01:58.977081 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4298 01:01:58.980062 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4299 01:01:58.980137
4300 01:01:58.980232
4301 01:01:58.980344 ==
4302 01:01:58.983568 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 01:01:58.986776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 01:01:58.986850 ==
4305 01:01:58.986919
4306 01:01:58.986977
4307 01:01:58.990629 TX Vref Scan disable
4308 01:01:58.990702 == TX Byte 0 ==
4309 01:01:58.996854 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4310 01:01:59.000575 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4311 01:01:59.000654 == TX Byte 1 ==
4312 01:01:59.006992 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4313 01:01:59.010270 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4314 01:01:59.010352 ==
4315 01:01:59.013891 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 01:01:59.016844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 01:01:59.016927 ==
4318 01:01:59.016991
4319 01:01:59.020179
4320 01:01:59.020296 TX Vref Scan disable
4321 01:01:59.023747 == TX Byte 0 ==
4322 01:01:59.027219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4323 01:01:59.030269 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4324 01:01:59.033805 == TX Byte 1 ==
4325 01:01:59.036922 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 01:01:59.040622 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 01:01:59.043606
4328 01:01:59.043686 [DATLAT]
4329 01:01:59.043750 Freq=600, CH0 RK1
4330 01:01:59.043810
4331 01:01:59.047210 DATLAT Default: 0x9
4332 01:01:59.047292 0, 0xFFFF, sum = 0
4333 01:01:59.050530 1, 0xFFFF, sum = 0
4334 01:01:59.050613 2, 0xFFFF, sum = 0
4335 01:01:59.053763 3, 0xFFFF, sum = 0
4336 01:01:59.053845 4, 0xFFFF, sum = 0
4337 01:01:59.056886 5, 0xFFFF, sum = 0
4338 01:01:59.060206 6, 0xFFFF, sum = 0
4339 01:01:59.060349 7, 0xFFFF, sum = 0
4340 01:01:59.060416 8, 0x0, sum = 1
4341 01:01:59.063938 9, 0x0, sum = 2
4342 01:01:59.064020 10, 0x0, sum = 3
4343 01:01:59.067071 11, 0x0, sum = 4
4344 01:01:59.067154 best_step = 9
4345 01:01:59.067218
4346 01:01:59.067277 ==
4347 01:01:59.070490 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 01:01:59.077006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 01:01:59.077088 ==
4350 01:01:59.077154 RX Vref Scan: 0
4351 01:01:59.077214
4352 01:01:59.079901 RX Vref 0 -> 0, step: 1
4353 01:01:59.079982
4354 01:01:59.083685 RX Delay -163 -> 252, step: 8
4355 01:01:59.086807 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4356 01:01:59.093529 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4357 01:01:59.096691 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4358 01:01:59.100515 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4359 01:01:59.103498 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4360 01:01:59.106686 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4361 01:01:59.109869 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4362 01:01:59.116937 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4363 01:01:59.119967 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4364 01:01:59.123680 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4365 01:01:59.126480 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4366 01:01:59.133228 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4367 01:01:59.136533 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4368 01:01:59.139988 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4369 01:01:59.143285 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4370 01:01:59.147090 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4371 01:01:59.150020 ==
4372 01:01:59.150101 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 01:01:59.156729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:01:59.156810 ==
4375 01:01:59.156874 DQS Delay:
4376 01:01:59.160022 DQS0 = 0, DQS1 = 0
4377 01:01:59.160103 DQM Delay:
4378 01:01:59.163375 DQM0 = 53, DQM1 = 45
4379 01:01:59.163456 DQ Delay:
4380 01:01:59.166495 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4381 01:01:59.169798 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4382 01:01:59.173200 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4383 01:01:59.176381 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4384 01:01:59.176463
4385 01:01:59.176526
4386 01:01:59.183556 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4387 01:01:59.186864 CH0 RK1: MR19=808, MR18=6425
4388 01:01:59.193124 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4389 01:01:59.196221 [RxdqsGatingPostProcess] freq 600
4390 01:01:59.203228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 01:01:59.206443 Pre-setting of DQS Precalculation
4392 01:01:59.209659 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 01:01:59.209735 ==
4394 01:01:59.212837 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 01:01:59.216006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 01:01:59.216100 ==
4397 01:01:59.223111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 01:01:59.229381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 01:01:59.232564 [CA 0] Center 35 (5~66) winsize 62
4400 01:01:59.236206 [CA 1] Center 36 (5~67) winsize 63
4401 01:01:59.239456 [CA 2] Center 34 (4~65) winsize 62
4402 01:01:59.242647 [CA 3] Center 34 (4~65) winsize 62
4403 01:01:59.245917 [CA 4] Center 34 (4~65) winsize 62
4404 01:01:59.249709 [CA 5] Center 34 (3~65) winsize 63
4405 01:01:59.249790
4406 01:01:59.252751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 01:01:59.252832
4408 01:01:59.255769 [CATrainingPosCal] consider 1 rank data
4409 01:01:59.259476 u2DelayCellTimex100 = 270/100 ps
4410 01:01:59.262794 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4411 01:01:59.265782 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4412 01:01:59.269353 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 01:01:59.272981 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4414 01:01:59.275786 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4415 01:01:59.279382 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4416 01:01:59.279463
4417 01:01:59.286108 CA PerBit enable=1, Macro0, CA PI delay=34
4418 01:01:59.286189
4419 01:01:59.289128 [CBTSetCACLKResult] CA Dly = 34
4420 01:01:59.289209 CS Dly: 5 (0~36)
4421 01:01:59.289273 ==
4422 01:01:59.292992 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 01:01:59.295945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 01:01:59.296026 ==
4425 01:01:59.302499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 01:01:59.309175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4427 01:01:59.312232 [CA 0] Center 36 (5~67) winsize 63
4428 01:01:59.315634 [CA 1] Center 36 (5~67) winsize 63
4429 01:01:59.319249 [CA 2] Center 34 (4~65) winsize 62
4430 01:01:59.322135 [CA 3] Center 34 (4~65) winsize 62
4431 01:01:59.325947 [CA 4] Center 34 (4~65) winsize 62
4432 01:01:59.329134 [CA 5] Center 34 (3~65) winsize 63
4433 01:01:59.329215
4434 01:01:59.332276 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4435 01:01:59.332397
4436 01:01:59.335508 [CATrainingPosCal] consider 2 rank data
4437 01:01:59.339266 u2DelayCellTimex100 = 270/100 ps
4438 01:01:59.342238 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4439 01:01:59.345563 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4440 01:01:59.349238 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4441 01:01:59.352561 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4442 01:01:59.355852 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 01:01:59.361993 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4444 01:01:59.362075
4445 01:01:59.365836 CA PerBit enable=1, Macro0, CA PI delay=34
4446 01:01:59.365918
4447 01:01:59.369122 [CBTSetCACLKResult] CA Dly = 34
4448 01:01:59.369203 CS Dly: 6 (0~38)
4449 01:01:59.369267
4450 01:01:59.372352 ----->DramcWriteLeveling(PI) begin...
4451 01:01:59.372435 ==
4452 01:01:59.375664 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 01:01:59.378654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 01:01:59.382593 ==
4455 01:01:59.382675 Write leveling (Byte 0): 29 => 29
4456 01:01:59.385737 Write leveling (Byte 1): 30 => 30
4457 01:01:59.389011 DramcWriteLeveling(PI) end<-----
4458 01:01:59.389092
4459 01:01:59.389156 ==
4460 01:01:59.392130 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 01:01:59.399019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 01:01:59.399102 ==
4463 01:01:59.402485 [Gating] SW mode calibration
4464 01:01:59.409129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 01:01:59.412464 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 01:01:59.418986 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 01:01:59.422077 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 01:01:59.425198 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4469 01:01:59.432404 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (0 1) (1 1)
4470 01:01:59.435363 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4471 01:01:59.438465 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 01:01:59.445349 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 01:01:59.448495 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 01:01:59.451874 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 01:01:59.454991 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 01:01:59.461935 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4477 01:01:59.465124 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4478 01:01:59.471485 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 01:01:59.474652 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 01:01:59.478536 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 01:01:59.481639 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 01:01:59.488030 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 01:01:59.491195 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 01:01:59.494941 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 01:01:59.501465 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4486 01:01:59.504590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 01:01:59.508429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 01:01:59.514575 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 01:01:59.517843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 01:01:59.521532 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 01:01:59.528136 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 01:01:59.531272 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 01:01:59.535184 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 01:01:59.541616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 01:01:59.544874 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 01:01:59.548396 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 01:01:59.554972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 01:01:59.558094 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 01:01:59.561763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 01:01:59.568038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 01:01:59.571486 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 01:01:59.574798 Total UI for P1: 0, mck2ui 16
4503 01:01:59.578273 best dqsien dly found for B0: ( 0, 13, 10)
4504 01:01:59.581680 Total UI for P1: 0, mck2ui 16
4505 01:01:59.584513 best dqsien dly found for B1: ( 0, 13, 10)
4506 01:01:59.587791 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4507 01:01:59.591621 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4508 01:01:59.591702
4509 01:01:59.594862 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4510 01:01:59.597984 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4511 01:01:59.601390 [Gating] SW calibration Done
4512 01:01:59.601472 ==
4513 01:01:59.604600 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 01:01:59.607881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 01:01:59.607966 ==
4516 01:01:59.611035 RX Vref Scan: 0
4517 01:01:59.611117
4518 01:01:59.614388 RX Vref 0 -> 0, step: 1
4519 01:01:59.614469
4520 01:01:59.614533 RX Delay -230 -> 252, step: 16
4521 01:01:59.621240 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4522 01:01:59.624690 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4523 01:01:59.628001 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4524 01:01:59.631166 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4525 01:01:59.637886 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4526 01:01:59.641414 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4527 01:01:59.644499 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4528 01:01:59.647708 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4529 01:01:59.654039 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4530 01:01:59.657453 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4531 01:01:59.661258 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4532 01:01:59.664517 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4533 01:01:59.670590 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4534 01:01:59.674143 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4535 01:01:59.677290 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4536 01:01:59.681015 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4537 01:01:59.681097 ==
4538 01:01:59.683976 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 01:01:59.691065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 01:01:59.691148 ==
4541 01:01:59.691213 DQS Delay:
4542 01:01:59.691273 DQS0 = 0, DQS1 = 0
4543 01:01:59.694333 DQM Delay:
4544 01:01:59.694415 DQM0 = 49, DQM1 = 46
4545 01:01:59.697738 DQ Delay:
4546 01:01:59.701103 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4547 01:01:59.704313 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4548 01:01:59.704409 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4549 01:01:59.710855 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4550 01:01:59.711022
4551 01:01:59.711094
4552 01:01:59.711159 ==
4553 01:01:59.714454 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 01:01:59.717574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 01:01:59.717671 ==
4556 01:01:59.717733
4557 01:01:59.717791
4558 01:01:59.720808 TX Vref Scan disable
4559 01:01:59.720877 == TX Byte 0 ==
4560 01:01:59.727266 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4561 01:01:59.730504 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4562 01:01:59.730574 == TX Byte 1 ==
4563 01:01:59.737378 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4564 01:01:59.740957 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4565 01:01:59.741033 ==
4566 01:01:59.743882 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 01:01:59.747027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 01:01:59.747115 ==
4569 01:01:59.747180
4570 01:01:59.750445
4571 01:01:59.750526 TX Vref Scan disable
4572 01:01:59.753848 == TX Byte 0 ==
4573 01:01:59.757537 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 01:01:59.764088 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 01:01:59.764170 == TX Byte 1 ==
4576 01:01:59.767363 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4577 01:01:59.774283 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4578 01:01:59.774364
4579 01:01:59.774428 [DATLAT]
4580 01:01:59.774489 Freq=600, CH1 RK0
4581 01:01:59.774547
4582 01:01:59.777226 DATLAT Default: 0x9
4583 01:01:59.777307 0, 0xFFFF, sum = 0
4584 01:01:59.780179 1, 0xFFFF, sum = 0
4585 01:01:59.780310 2, 0xFFFF, sum = 0
4586 01:01:59.784130 3, 0xFFFF, sum = 0
4587 01:01:59.784239 4, 0xFFFF, sum = 0
4588 01:01:59.787200 5, 0xFFFF, sum = 0
4589 01:01:59.790835 6, 0xFFFF, sum = 0
4590 01:01:59.790921 7, 0xFFFF, sum = 0
4591 01:01:59.790987 8, 0x0, sum = 1
4592 01:01:59.793841 9, 0x0, sum = 2
4593 01:01:59.793924 10, 0x0, sum = 3
4594 01:01:59.797000 11, 0x0, sum = 4
4595 01:01:59.797082 best_step = 9
4596 01:01:59.797145
4597 01:01:59.797205 ==
4598 01:01:59.800221 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 01:01:59.807112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 01:01:59.807195 ==
4601 01:01:59.807260 RX Vref Scan: 1
4602 01:01:59.807320
4603 01:01:59.810249 RX Vref 0 -> 0, step: 1
4604 01:01:59.810330
4605 01:01:59.813307 RX Delay -163 -> 252, step: 8
4606 01:01:59.813388
4607 01:01:59.817008 Set Vref, RX VrefLevel [Byte0]: 53
4608 01:01:59.820021 [Byte1]: 53
4609 01:01:59.820128
4610 01:01:59.823427 Final RX Vref Byte 0 = 53 to rank0
4611 01:01:59.826846 Final RX Vref Byte 1 = 53 to rank0
4612 01:01:59.830387 Final RX Vref Byte 0 = 53 to rank1
4613 01:01:59.833619 Final RX Vref Byte 1 = 53 to rank1==
4614 01:01:59.836833 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 01:01:59.840104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 01:01:59.840212 ==
4617 01:01:59.843304 DQS Delay:
4618 01:01:59.843385 DQS0 = 0, DQS1 = 0
4619 01:01:59.847043 DQM Delay:
4620 01:01:59.847124 DQM0 = 48, DQM1 = 45
4621 01:01:59.847189 DQ Delay:
4622 01:01:59.850220 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4623 01:01:59.853217 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4624 01:01:59.856593 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4625 01:01:59.860525 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4626 01:01:59.860631
4627 01:01:59.860723
4628 01:01:59.869938 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4629 01:01:59.873188 CH1 RK0: MR19=808, MR18=4B71
4630 01:01:59.876704 CH1_RK0: MR19=0x808, MR18=0x4B71, DQSOSC=388, MR23=63, INC=174, DEC=116
4631 01:01:59.876803
4632 01:01:59.883506 ----->DramcWriteLeveling(PI) begin...
4633 01:01:59.883615 ==
4634 01:01:59.886562 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 01:01:59.889853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 01:01:59.889936 ==
4637 01:01:59.893502 Write leveling (Byte 0): 29 => 29
4638 01:01:59.896718 Write leveling (Byte 1): 30 => 30
4639 01:01:59.899681 DramcWriteLeveling(PI) end<-----
4640 01:01:59.899763
4641 01:01:59.899827 ==
4642 01:01:59.903363 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 01:01:59.906677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 01:01:59.906760 ==
4645 01:01:59.909682 [Gating] SW mode calibration
4646 01:01:59.916624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4647 01:01:59.923001 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4648 01:01:59.926870 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4649 01:01:59.930117 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 01:01:59.936160 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 01:01:59.940420 0 9 12 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (1 1)
4652 01:01:59.944458 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 01:01:59.949878 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 01:01:59.953037 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 01:01:59.956201 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 01:01:59.959777 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 01:01:59.966300 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 01:01:59.969611 0 10 8 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4659 01:01:59.972869 0 10 12 | B1->B0 | 3e3e 3939 | 0 0 | (0 0) (0 0)
4660 01:01:59.979375 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 01:01:59.982938 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 01:01:59.986017 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 01:01:59.993030 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 01:01:59.996457 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 01:01:59.999525 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 01:02:00.006467 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 01:02:00.009235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 01:02:00.013019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 01:02:00.019190 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 01:02:00.022723 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 01:02:00.026031 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 01:02:00.032993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 01:02:00.036119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 01:02:00.039328 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 01:02:00.046371 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 01:02:00.049473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 01:02:00.053112 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 01:02:00.059245 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 01:02:00.062905 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 01:02:00.065969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 01:02:00.072494 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 01:02:00.076024 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 01:02:00.079842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4684 01:02:00.082927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 01:02:00.086084 Total UI for P1: 0, mck2ui 16
4686 01:02:00.089250 best dqsien dly found for B0: ( 0, 13, 12)
4687 01:02:00.092899 Total UI for P1: 0, mck2ui 16
4688 01:02:00.095922 best dqsien dly found for B1: ( 0, 13, 12)
4689 01:02:00.099312 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4690 01:02:00.106460 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4691 01:02:00.106546
4692 01:02:00.109662 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4693 01:02:00.112763 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4694 01:02:00.116309 [Gating] SW calibration Done
4695 01:02:00.116404 ==
4696 01:02:00.119689 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 01:02:00.122483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 01:02:00.122562 ==
4699 01:02:00.122625 RX Vref Scan: 0
4700 01:02:00.126119
4701 01:02:00.126194 RX Vref 0 -> 0, step: 1
4702 01:02:00.126256
4703 01:02:00.129307 RX Delay -230 -> 252, step: 16
4704 01:02:00.132544 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4705 01:02:00.138975 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4706 01:02:00.142804 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4707 01:02:00.146029 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4708 01:02:00.149295 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4709 01:02:00.152541 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4710 01:02:00.159090 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4711 01:02:00.162200 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4712 01:02:00.166239 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4713 01:02:00.169143 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4714 01:02:00.175913 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4715 01:02:00.178809 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4716 01:02:00.182176 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4717 01:02:00.185649 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4718 01:02:00.192195 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4719 01:02:00.195842 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4720 01:02:00.195924 ==
4721 01:02:00.199261 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 01:02:00.202330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 01:02:00.202413 ==
4724 01:02:00.202478 DQS Delay:
4725 01:02:00.205745 DQS0 = 0, DQS1 = 0
4726 01:02:00.205828 DQM Delay:
4727 01:02:00.209467 DQM0 = 50, DQM1 = 48
4728 01:02:00.209548 DQ Delay:
4729 01:02:00.212623 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4730 01:02:00.215615 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4731 01:02:00.218922 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4732 01:02:00.222360 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4733 01:02:00.222442
4734 01:02:00.222507
4735 01:02:00.222566 ==
4736 01:02:00.225493 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 01:02:00.228833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 01:02:00.232513 ==
4739 01:02:00.232595
4740 01:02:00.232707
4741 01:02:00.232801 TX Vref Scan disable
4742 01:02:00.235888 == TX Byte 0 ==
4743 01:02:00.239303 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4744 01:02:00.242493 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4745 01:02:00.245698 == TX Byte 1 ==
4746 01:02:00.248987 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4747 01:02:00.252177 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4748 01:02:00.256000 ==
4749 01:02:00.258622 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 01:02:00.262516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 01:02:00.262602 ==
4752 01:02:00.262666
4753 01:02:00.262726
4754 01:02:00.265660 TX Vref Scan disable
4755 01:02:00.265742 == TX Byte 0 ==
4756 01:02:00.272173 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 01:02:00.275834 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 01:02:00.275942 == TX Byte 1 ==
4759 01:02:00.282208 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4760 01:02:00.285399 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4761 01:02:00.285507
4762 01:02:00.285599 [DATLAT]
4763 01:02:00.288609 Freq=600, CH1 RK1
4764 01:02:00.288691
4765 01:02:00.288755 DATLAT Default: 0x9
4766 01:02:00.292479 0, 0xFFFF, sum = 0
4767 01:02:00.292563 1, 0xFFFF, sum = 0
4768 01:02:00.295484 2, 0xFFFF, sum = 0
4769 01:02:00.295567 3, 0xFFFF, sum = 0
4770 01:02:00.298684 4, 0xFFFF, sum = 0
4771 01:02:00.298767 5, 0xFFFF, sum = 0
4772 01:02:00.302055 6, 0xFFFF, sum = 0
4773 01:02:00.305311 7, 0xFFFF, sum = 0
4774 01:02:00.305408 8, 0x0, sum = 1
4775 01:02:00.305474 9, 0x0, sum = 2
4776 01:02:00.308360 10, 0x0, sum = 3
4777 01:02:00.308445 11, 0x0, sum = 4
4778 01:02:00.312137 best_step = 9
4779 01:02:00.312219
4780 01:02:00.312283 ==
4781 01:02:00.315176 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 01:02:00.318668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 01:02:00.318751 ==
4784 01:02:00.321890 RX Vref Scan: 0
4785 01:02:00.321971
4786 01:02:00.322036 RX Vref 0 -> 0, step: 1
4787 01:02:00.322097
4788 01:02:00.325042 RX Delay -163 -> 252, step: 8
4789 01:02:00.332341 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4790 01:02:00.335902 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4791 01:02:00.338789 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4792 01:02:00.342020 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4793 01:02:00.348590 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4794 01:02:00.351911 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4795 01:02:00.355606 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4796 01:02:00.358640 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4797 01:02:00.361827 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4798 01:02:00.368963 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4799 01:02:00.372325 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4800 01:02:00.375472 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4801 01:02:00.378617 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4802 01:02:00.382233 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4803 01:02:00.388642 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4804 01:02:00.392406 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4805 01:02:00.392488 ==
4806 01:02:00.395573 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 01:02:00.398792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 01:02:00.398874 ==
4809 01:02:00.402062 DQS Delay:
4810 01:02:00.402144 DQS0 = 0, DQS1 = 0
4811 01:02:00.402208 DQM Delay:
4812 01:02:00.405377 DQM0 = 48, DQM1 = 45
4813 01:02:00.405459 DQ Delay:
4814 01:02:00.408729 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4815 01:02:00.411763 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4816 01:02:00.414910 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4817 01:02:00.418776 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4818 01:02:00.418857
4819 01:02:00.418922
4820 01:02:00.428548 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4821 01:02:00.432057 CH1 RK1: MR19=808, MR18=6A21
4822 01:02:00.435205 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4823 01:02:00.438703 [RxdqsGatingPostProcess] freq 600
4824 01:02:00.445122 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4825 01:02:00.448419 Pre-setting of DQS Precalculation
4826 01:02:00.452000 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4827 01:02:00.458174 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4828 01:02:00.468324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4829 01:02:00.468406
4830 01:02:00.468470
4831 01:02:00.471585 [Calibration Summary] 1200 Mbps
4832 01:02:00.471667 CH 0, Rank 0
4833 01:02:00.475297 SW Impedance : PASS
4834 01:02:00.475379 DUTY Scan : NO K
4835 01:02:00.478296 ZQ Calibration : PASS
4836 01:02:00.481868 Jitter Meter : NO K
4837 01:02:00.481950 CBT Training : PASS
4838 01:02:00.484815 Write leveling : PASS
4839 01:02:00.484896 RX DQS gating : PASS
4840 01:02:00.488536 RX DQ/DQS(RDDQC) : PASS
4841 01:02:00.491606 TX DQ/DQS : PASS
4842 01:02:00.491687 RX DATLAT : PASS
4843 01:02:00.495414 RX DQ/DQS(Engine): PASS
4844 01:02:00.498757 TX OE : NO K
4845 01:02:00.498839 All Pass.
4846 01:02:00.498904
4847 01:02:00.498964 CH 0, Rank 1
4848 01:02:00.501953 SW Impedance : PASS
4849 01:02:00.505052 DUTY Scan : NO K
4850 01:02:00.505134 ZQ Calibration : PASS
4851 01:02:00.508326 Jitter Meter : NO K
4852 01:02:00.511441 CBT Training : PASS
4853 01:02:00.511529 Write leveling : PASS
4854 01:02:00.514769 RX DQS gating : PASS
4855 01:02:00.518043 RX DQ/DQS(RDDQC) : PASS
4856 01:02:00.518124 TX DQ/DQS : PASS
4857 01:02:00.521215 RX DATLAT : PASS
4858 01:02:00.524942 RX DQ/DQS(Engine): PASS
4859 01:02:00.525023 TX OE : NO K
4860 01:02:00.528482 All Pass.
4861 01:02:00.528565
4862 01:02:00.528629 CH 1, Rank 0
4863 01:02:00.531204 SW Impedance : PASS
4864 01:02:00.531286 DUTY Scan : NO K
4865 01:02:00.534413 ZQ Calibration : PASS
4866 01:02:00.538098 Jitter Meter : NO K
4867 01:02:00.538180 CBT Training : PASS
4868 01:02:00.541377 Write leveling : PASS
4869 01:02:00.541459 RX DQS gating : PASS
4870 01:02:00.544450 RX DQ/DQS(RDDQC) : PASS
4871 01:02:00.548140 TX DQ/DQS : PASS
4872 01:02:00.548252 RX DATLAT : PASS
4873 01:02:00.551342 RX DQ/DQS(Engine): PASS
4874 01:02:00.555014 TX OE : NO K
4875 01:02:00.555095 All Pass.
4876 01:02:00.555158
4877 01:02:00.555218 CH 1, Rank 1
4878 01:02:00.558062 SW Impedance : PASS
4879 01:02:00.561355 DUTY Scan : NO K
4880 01:02:00.561437 ZQ Calibration : PASS
4881 01:02:00.564560 Jitter Meter : NO K
4882 01:02:00.567934 CBT Training : PASS
4883 01:02:00.568016 Write leveling : PASS
4884 01:02:00.571450 RX DQS gating : PASS
4885 01:02:00.574515 RX DQ/DQS(RDDQC) : PASS
4886 01:02:00.574597 TX DQ/DQS : PASS
4887 01:02:00.577780 RX DATLAT : PASS
4888 01:02:00.581427 RX DQ/DQS(Engine): PASS
4889 01:02:00.581508 TX OE : NO K
4890 01:02:00.581574 All Pass.
4891 01:02:00.584550
4892 01:02:00.584631 DramC Write-DBI off
4893 01:02:00.588097 PER_BANK_REFRESH: Hybrid Mode
4894 01:02:00.588178 TX_TRACKING: ON
4895 01:02:00.598234 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4896 01:02:00.601085 [FAST_K] Save calibration result to emmc
4897 01:02:00.604430 dramc_set_vcore_voltage set vcore to 662500
4898 01:02:00.607768 Read voltage for 933, 3
4899 01:02:00.607850 Vio18 = 0
4900 01:02:00.610928 Vcore = 662500
4901 01:02:00.611009 Vdram = 0
4902 01:02:00.611074 Vddq = 0
4903 01:02:00.611135 Vmddr = 0
4904 01:02:00.618052 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4905 01:02:00.624615 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4906 01:02:00.624697 MEM_TYPE=3, freq_sel=17
4907 01:02:00.627651 sv_algorithm_assistance_LP4_1600
4908 01:02:00.631382 ============ PULL DRAM RESETB DOWN ============
4909 01:02:00.637547 ========== PULL DRAM RESETB DOWN end =========
4910 01:02:00.641327 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4911 01:02:00.644490 ===================================
4912 01:02:00.647711 LPDDR4 DRAM CONFIGURATION
4913 01:02:00.650903 ===================================
4914 01:02:00.650986 EX_ROW_EN[0] = 0x0
4915 01:02:00.654814 EX_ROW_EN[1] = 0x0
4916 01:02:00.654895 LP4Y_EN = 0x0
4917 01:02:00.657835 WORK_FSP = 0x0
4918 01:02:00.657917 WL = 0x3
4919 01:02:00.661098 RL = 0x3
4920 01:02:00.661179 BL = 0x2
4921 01:02:00.664184 RPST = 0x0
4922 01:02:00.667340 RD_PRE = 0x0
4923 01:02:00.667421 WR_PRE = 0x1
4924 01:02:00.671016 WR_PST = 0x0
4925 01:02:00.671097 DBI_WR = 0x0
4926 01:02:00.674068 DBI_RD = 0x0
4927 01:02:00.674149 OTF = 0x1
4928 01:02:00.677474 ===================================
4929 01:02:00.681126 ===================================
4930 01:02:00.684166 ANA top config
4931 01:02:00.684298 ===================================
4932 01:02:00.687733 DLL_ASYNC_EN = 0
4933 01:02:00.691302 ALL_SLAVE_EN = 1
4934 01:02:00.694517 NEW_RANK_MODE = 1
4935 01:02:00.697761 DLL_IDLE_MODE = 1
4936 01:02:00.697842 LP45_APHY_COMB_EN = 1
4937 01:02:00.700833 TX_ODT_DIS = 1
4938 01:02:00.703958 NEW_8X_MODE = 1
4939 01:02:00.707294 ===================================
4940 01:02:00.710697 ===================================
4941 01:02:00.713962 data_rate = 1866
4942 01:02:00.717162 CKR = 1
4943 01:02:00.720651 DQ_P2S_RATIO = 8
4944 01:02:00.720733 ===================================
4945 01:02:00.723880 CA_P2S_RATIO = 8
4946 01:02:00.727207 DQ_CA_OPEN = 0
4947 01:02:00.730558 DQ_SEMI_OPEN = 0
4948 01:02:00.733674 CA_SEMI_OPEN = 0
4949 01:02:00.737387 CA_FULL_RATE = 0
4950 01:02:00.737469 DQ_CKDIV4_EN = 1
4951 01:02:00.740548 CA_CKDIV4_EN = 1
4952 01:02:00.744280 CA_PREDIV_EN = 0
4953 01:02:00.747522 PH8_DLY = 0
4954 01:02:00.750744 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4955 01:02:00.754075 DQ_AAMCK_DIV = 4
4956 01:02:00.754157 CA_AAMCK_DIV = 4
4957 01:02:00.757208 CA_ADMCK_DIV = 4
4958 01:02:00.760779 DQ_TRACK_CA_EN = 0
4959 01:02:00.763947 CA_PICK = 933
4960 01:02:00.767144 CA_MCKIO = 933
4961 01:02:00.770414 MCKIO_SEMI = 0
4962 01:02:00.773665 PLL_FREQ = 3732
4963 01:02:00.773747 DQ_UI_PI_RATIO = 32
4964 01:02:00.777431 CA_UI_PI_RATIO = 0
4965 01:02:00.780575 ===================================
4966 01:02:00.783634 ===================================
4967 01:02:00.787378 memory_type:LPDDR4
4968 01:02:00.790313 GP_NUM : 10
4969 01:02:00.790395 SRAM_EN : 1
4970 01:02:00.793689 MD32_EN : 0
4971 01:02:00.797175 ===================================
4972 01:02:00.800949 [ANA_INIT] >>>>>>>>>>>>>>
4973 01:02:00.801031 <<<<<< [CONFIGURE PHASE]: ANA_TX
4974 01:02:00.803846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4975 01:02:00.807190 ===================================
4976 01:02:00.810098 data_rate = 1866,PCW = 0X8f00
4977 01:02:00.813827 ===================================
4978 01:02:00.817026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4979 01:02:00.823764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 01:02:00.830437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 01:02:00.833653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4982 01:02:00.836720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4983 01:02:00.840403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4984 01:02:00.843578 [ANA_INIT] flow start
4985 01:02:00.843659 [ANA_INIT] PLL >>>>>>>>
4986 01:02:00.846701 [ANA_INIT] PLL <<<<<<<<
4987 01:02:00.849996 [ANA_INIT] MIDPI >>>>>>>>
4988 01:02:00.850078 [ANA_INIT] MIDPI <<<<<<<<
4989 01:02:00.853726 [ANA_INIT] DLL >>>>>>>>
4990 01:02:00.856911 [ANA_INIT] flow end
4991 01:02:00.860143 ============ LP4 DIFF to SE enter ============
4992 01:02:00.863246 ============ LP4 DIFF to SE exit ============
4993 01:02:00.866337 [ANA_INIT] <<<<<<<<<<<<<
4994 01:02:00.869988 [Flow] Enable top DCM control >>>>>
4995 01:02:00.873209 [Flow] Enable top DCM control <<<<<
4996 01:02:00.876453 Enable DLL master slave shuffle
4997 01:02:00.882877 ==============================================================
4998 01:02:00.882959 Gating Mode config
4999 01:02:00.890005 ==============================================================
5000 01:02:00.890087 Config description:
5001 01:02:00.899666 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5002 01:02:00.906529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5003 01:02:00.913259 SELPH_MODE 0: By rank 1: By Phase
5004 01:02:00.916101 ==============================================================
5005 01:02:00.919446 GAT_TRACK_EN = 1
5006 01:02:00.922914 RX_GATING_MODE = 2
5007 01:02:00.926472 RX_GATING_TRACK_MODE = 2
5008 01:02:00.929444 SELPH_MODE = 1
5009 01:02:00.932873 PICG_EARLY_EN = 1
5010 01:02:00.936446 VALID_LAT_VALUE = 1
5011 01:02:00.939765 ==============================================================
5012 01:02:00.942810 Enter into Gating configuration >>>>
5013 01:02:00.946516 Exit from Gating configuration <<<<
5014 01:02:00.949677 Enter into DVFS_PRE_config >>>>>
5015 01:02:00.962704 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5016 01:02:00.966117 Exit from DVFS_PRE_config <<<<<
5017 01:02:00.969276 Enter into PICG configuration >>>>
5018 01:02:00.969357 Exit from PICG configuration <<<<
5019 01:02:00.972986 [RX_INPUT] configuration >>>>>
5020 01:02:00.975948 [RX_INPUT] configuration <<<<<
5021 01:02:00.983032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5022 01:02:00.986243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5023 01:02:00.993258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5024 01:02:00.999714 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5025 01:02:01.005870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 01:02:01.012513 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 01:02:01.016262 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5028 01:02:01.019530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5029 01:02:01.022712 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5030 01:02:01.029263 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5031 01:02:01.032760 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5032 01:02:01.035711 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 01:02:01.039458 ===================================
5034 01:02:01.042551 LPDDR4 DRAM CONFIGURATION
5035 01:02:01.045651 ===================================
5036 01:02:01.049004 EX_ROW_EN[0] = 0x0
5037 01:02:01.049077 EX_ROW_EN[1] = 0x0
5038 01:02:01.052530 LP4Y_EN = 0x0
5039 01:02:01.052607 WORK_FSP = 0x0
5040 01:02:01.055689 WL = 0x3
5041 01:02:01.055758 RL = 0x3
5042 01:02:01.059003 BL = 0x2
5043 01:02:01.059075 RPST = 0x0
5044 01:02:01.062286 RD_PRE = 0x0
5045 01:02:01.062355 WR_PRE = 0x1
5046 01:02:01.065620 WR_PST = 0x0
5047 01:02:01.065691 DBI_WR = 0x0
5048 01:02:01.069081 DBI_RD = 0x0
5049 01:02:01.069152 OTF = 0x1
5050 01:02:01.072739 ===================================
5051 01:02:01.078951 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5052 01:02:01.082546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5053 01:02:01.085936 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 01:02:01.088871 ===================================
5055 01:02:01.092554 LPDDR4 DRAM CONFIGURATION
5056 01:02:01.095696 ===================================
5057 01:02:01.098927 EX_ROW_EN[0] = 0x10
5058 01:02:01.098997 EX_ROW_EN[1] = 0x0
5059 01:02:01.102130 LP4Y_EN = 0x0
5060 01:02:01.102198 WORK_FSP = 0x0
5061 01:02:01.105938 WL = 0x3
5062 01:02:01.106014 RL = 0x3
5063 01:02:01.109316 BL = 0x2
5064 01:02:01.109388 RPST = 0x0
5065 01:02:01.112271 RD_PRE = 0x0
5066 01:02:01.112384 WR_PRE = 0x1
5067 01:02:01.115347 WR_PST = 0x0
5068 01:02:01.115416 DBI_WR = 0x0
5069 01:02:01.118891 DBI_RD = 0x0
5070 01:02:01.118966 OTF = 0x1
5071 01:02:01.122565 ===================================
5072 01:02:01.129247 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5073 01:02:01.133476 nWR fixed to 30
5074 01:02:01.136591 [ModeRegInit_LP4] CH0 RK0
5075 01:02:01.136660 [ModeRegInit_LP4] CH0 RK1
5076 01:02:01.140222 [ModeRegInit_LP4] CH1 RK0
5077 01:02:01.143266 [ModeRegInit_LP4] CH1 RK1
5078 01:02:01.143343 match AC timing 9
5079 01:02:01.150064 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5080 01:02:01.153589 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5081 01:02:01.156635 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5082 01:02:01.162996 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5083 01:02:01.166944 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5084 01:02:01.167019 ==
5085 01:02:01.169605 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 01:02:01.173300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 01:02:01.173371 ==
5088 01:02:01.179640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 01:02:01.186468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5090 01:02:01.189656 [CA 0] Center 37 (6~68) winsize 63
5091 01:02:01.193418 [CA 1] Center 37 (7~68) winsize 62
5092 01:02:01.196566 [CA 2] Center 34 (4~65) winsize 62
5093 01:02:01.199939 [CA 3] Center 34 (3~65) winsize 63
5094 01:02:01.203200 [CA 4] Center 33 (3~64) winsize 62
5095 01:02:01.206497 [CA 5] Center 32 (2~62) winsize 61
5096 01:02:01.206578
5097 01:02:01.209842 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5098 01:02:01.209922
5099 01:02:01.213122 [CATrainingPosCal] consider 1 rank data
5100 01:02:01.216263 u2DelayCellTimex100 = 270/100 ps
5101 01:02:01.220030 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5102 01:02:01.222923 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5103 01:02:01.226436 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5104 01:02:01.229895 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5105 01:02:01.232887 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5106 01:02:01.236661 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5107 01:02:01.239680
5108 01:02:01.242980 CA PerBit enable=1, Macro0, CA PI delay=32
5109 01:02:01.243047
5110 01:02:01.246145 [CBTSetCACLKResult] CA Dly = 32
5111 01:02:01.246212 CS Dly: 5 (0~36)
5112 01:02:01.246270 ==
5113 01:02:01.249917 Dram Type= 6, Freq= 0, CH_0, rank 1
5114 01:02:01.253079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 01:02:01.253147 ==
5116 01:02:01.259568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 01:02:01.266466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5118 01:02:01.269814 [CA 0] Center 37 (7~68) winsize 62
5119 01:02:01.272739 [CA 1] Center 37 (7~68) winsize 62
5120 01:02:01.276504 [CA 2] Center 34 (4~65) winsize 62
5121 01:02:01.279734 [CA 3] Center 34 (3~65) winsize 63
5122 01:02:01.282887 [CA 4] Center 33 (3~63) winsize 61
5123 01:02:01.286583 [CA 5] Center 32 (2~62) winsize 61
5124 01:02:01.286665
5125 01:02:01.289548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5126 01:02:01.289629
5127 01:02:01.292808 [CATrainingPosCal] consider 2 rank data
5128 01:02:01.295997 u2DelayCellTimex100 = 270/100 ps
5129 01:02:01.299852 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5130 01:02:01.303111 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5131 01:02:01.306319 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5132 01:02:01.309365 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5133 01:02:01.313011 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5134 01:02:01.319114 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5135 01:02:01.319196
5136 01:02:01.323004 CA PerBit enable=1, Macro0, CA PI delay=32
5137 01:02:01.323086
5138 01:02:01.325983 [CBTSetCACLKResult] CA Dly = 32
5139 01:02:01.326064 CS Dly: 5 (0~37)
5140 01:02:01.326130
5141 01:02:01.329209 ----->DramcWriteLeveling(PI) begin...
5142 01:02:01.329292 ==
5143 01:02:01.332850 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 01:02:01.339642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 01:02:01.339725 ==
5146 01:02:01.342555 Write leveling (Byte 0): 34 => 34
5147 01:02:01.342637 Write leveling (Byte 1): 31 => 31
5148 01:02:01.346072 DramcWriteLeveling(PI) end<-----
5149 01:02:01.346153
5150 01:02:01.349029 ==
5151 01:02:01.349112 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 01:02:01.355958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 01:02:01.356040 ==
5154 01:02:01.359226 [Gating] SW mode calibration
5155 01:02:01.366253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5156 01:02:01.369119 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5157 01:02:01.376036 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5158 01:02:01.379149 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 01:02:01.382509 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 01:02:01.389526 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 01:02:01.392605 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 01:02:01.395932 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 01:02:01.402300 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5164 01:02:01.405634 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (0 0) (1 0)
5165 01:02:01.408889 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5166 01:02:01.415756 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 01:02:01.419017 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 01:02:01.422209 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 01:02:01.429208 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 01:02:01.432237 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 01:02:01.435468 0 15 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5172 01:02:01.438819 0 15 28 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
5173 01:02:01.445477 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5174 01:02:01.448773 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 01:02:01.451936 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 01:02:01.458683 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 01:02:01.462207 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 01:02:01.465146 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 01:02:01.471773 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5180 01:02:01.475709 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5181 01:02:01.478884 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5182 01:02:01.485035 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 01:02:01.488322 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 01:02:01.492204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 01:02:01.498349 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 01:02:01.502047 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 01:02:01.505040 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 01:02:01.512023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 01:02:01.515300 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 01:02:01.518528 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 01:02:01.525515 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 01:02:01.528670 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 01:02:01.531802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 01:02:01.538261 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 01:02:01.542083 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 01:02:01.545489 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5197 01:02:01.551579 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 01:02:01.551661 Total UI for P1: 0, mck2ui 16
5199 01:02:01.558872 best dqsien dly found for B0: ( 1, 2, 28)
5200 01:02:01.558954 Total UI for P1: 0, mck2ui 16
5201 01:02:01.562055 best dqsien dly found for B1: ( 1, 2, 30)
5202 01:02:01.565175 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5203 01:02:01.572002 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5204 01:02:01.572081
5205 01:02:01.575389 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5206 01:02:01.578779 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5207 01:02:01.581595 [Gating] SW calibration Done
5208 01:02:01.581666 ==
5209 01:02:01.585097 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 01:02:01.588541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 01:02:01.588610 ==
5212 01:02:01.591731 RX Vref Scan: 0
5213 01:02:01.591797
5214 01:02:01.591855 RX Vref 0 -> 0, step: 1
5215 01:02:01.591914
5216 01:02:01.595222 RX Delay -80 -> 252, step: 8
5217 01:02:01.598223 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5218 01:02:01.601643 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5219 01:02:01.608412 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5220 01:02:01.611747 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5221 01:02:01.615136 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5222 01:02:01.618493 iDelay=200, Bit 5, Center 95 (8 ~ 183) 176
5223 01:02:01.622124 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5224 01:02:01.625009 iDelay=200, Bit 7, Center 111 (24 ~ 199) 176
5225 01:02:01.631713 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5226 01:02:01.634919 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5227 01:02:01.638109 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5228 01:02:01.641937 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5229 01:02:01.645177 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5230 01:02:01.648352 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5231 01:02:01.654778 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5232 01:02:01.658340 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5233 01:02:01.658413 ==
5234 01:02:01.661234 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 01:02:01.664960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 01:02:01.665034 ==
5237 01:02:01.668113 DQS Delay:
5238 01:02:01.668206 DQS0 = 0, DQS1 = 0
5239 01:02:01.668304 DQM Delay:
5240 01:02:01.671311 DQM0 = 104, DQM1 = 93
5241 01:02:01.671377 DQ Delay:
5242 01:02:01.674588 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5243 01:02:01.678449 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5244 01:02:01.681260 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5245 01:02:01.685054 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5246 01:02:01.685138
5247 01:02:01.685202
5248 01:02:01.685261 ==
5249 01:02:01.688255 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 01:02:01.694572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 01:02:01.694688 ==
5252 01:02:01.694753
5253 01:02:01.694813
5254 01:02:01.694870 TX Vref Scan disable
5255 01:02:01.698668 == TX Byte 0 ==
5256 01:02:01.702034 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5257 01:02:01.708464 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5258 01:02:01.708546 == TX Byte 1 ==
5259 01:02:01.711890 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5260 01:02:01.715390 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5261 01:02:01.718490 ==
5262 01:02:01.722038 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 01:02:01.725154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 01:02:01.725236 ==
5265 01:02:01.725300
5266 01:02:01.725358
5267 01:02:01.728782 TX Vref Scan disable
5268 01:02:01.728863 == TX Byte 0 ==
5269 01:02:01.735123 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5270 01:02:01.738401 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5271 01:02:01.738483 == TX Byte 1 ==
5272 01:02:01.745151 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5273 01:02:01.748593 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5274 01:02:01.748675
5275 01:02:01.748738 [DATLAT]
5276 01:02:01.751940 Freq=933, CH0 RK0
5277 01:02:01.752022
5278 01:02:01.752086 DATLAT Default: 0xd
5279 01:02:01.755182 0, 0xFFFF, sum = 0
5280 01:02:01.755265 1, 0xFFFF, sum = 0
5281 01:02:01.758474 2, 0xFFFF, sum = 0
5282 01:02:01.758556 3, 0xFFFF, sum = 0
5283 01:02:01.761698 4, 0xFFFF, sum = 0
5284 01:02:01.761781 5, 0xFFFF, sum = 0
5285 01:02:01.764817 6, 0xFFFF, sum = 0
5286 01:02:01.768393 7, 0xFFFF, sum = 0
5287 01:02:01.768476 8, 0xFFFF, sum = 0
5288 01:02:01.771471 9, 0xFFFF, sum = 0
5289 01:02:01.771557 10, 0x0, sum = 1
5290 01:02:01.775123 11, 0x0, sum = 2
5291 01:02:01.775206 12, 0x0, sum = 3
5292 01:02:01.775280 13, 0x0, sum = 4
5293 01:02:01.778236 best_step = 11
5294 01:02:01.778325
5295 01:02:01.778389 ==
5296 01:02:01.781250 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 01:02:01.785073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 01:02:01.785180 ==
5299 01:02:01.788195 RX Vref Scan: 1
5300 01:02:01.788307
5301 01:02:01.788374 RX Vref 0 -> 0, step: 1
5302 01:02:01.791514
5303 01:02:01.791595 RX Delay -53 -> 252, step: 4
5304 01:02:01.791658
5305 01:02:01.794730 Set Vref, RX VrefLevel [Byte0]: 55
5306 01:02:01.797906 [Byte1]: 58
5307 01:02:01.802417
5308 01:02:01.802498 Final RX Vref Byte 0 = 55 to rank0
5309 01:02:01.806074 Final RX Vref Byte 1 = 58 to rank0
5310 01:02:01.809269 Final RX Vref Byte 0 = 55 to rank1
5311 01:02:01.812506 Final RX Vref Byte 1 = 58 to rank1==
5312 01:02:01.815780 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 01:02:01.822616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 01:02:01.822698 ==
5315 01:02:01.822762 DQS Delay:
5316 01:02:01.822822 DQS0 = 0, DQS1 = 0
5317 01:02:01.825542 DQM Delay:
5318 01:02:01.825623 DQM0 = 104, DQM1 = 97
5319 01:02:01.829376 DQ Delay:
5320 01:02:01.832324 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5321 01:02:01.835959 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5322 01:02:01.839039 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5323 01:02:01.842160 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =106
5324 01:02:01.842241
5325 01:02:01.842304
5326 01:02:01.848711 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5327 01:02:01.852074 CH0 RK0: MR19=505, MR18=332B
5328 01:02:01.858859 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5329 01:02:01.858936
5330 01:02:01.862301 ----->DramcWriteLeveling(PI) begin...
5331 01:02:01.862376 ==
5332 01:02:01.865452 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 01:02:01.869155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 01:02:01.869236 ==
5335 01:02:01.872494 Write leveling (Byte 0): 34 => 34
5336 01:02:01.875286 Write leveling (Byte 1): 28 => 28
5337 01:02:01.879261 DramcWriteLeveling(PI) end<-----
5338 01:02:01.879337
5339 01:02:01.879398 ==
5340 01:02:01.882014 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 01:02:01.888963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 01:02:01.889042 ==
5343 01:02:01.889106 [Gating] SW mode calibration
5344 01:02:01.899144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5345 01:02:01.902321 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5346 01:02:01.905587 0 14 0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
5347 01:02:01.911835 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 01:02:01.915064 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 01:02:01.918903 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 01:02:01.925265 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 01:02:01.928669 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 01:02:01.931710 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 01:02:01.938655 0 14 28 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (1 0)
5354 01:02:01.941817 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5355 01:02:01.945246 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 01:02:01.952127 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 01:02:01.955276 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 01:02:01.958650 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 01:02:01.965134 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 01:02:01.968146 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5361 01:02:01.971755 0 15 28 | B1->B0 | 4040 3434 | 0 1 | (0 0) (0 0)
5362 01:02:01.978082 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5363 01:02:01.981732 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 01:02:01.985127 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 01:02:01.991487 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 01:02:01.994783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 01:02:01.998161 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 01:02:02.004967 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5369 01:02:02.008208 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5370 01:02:02.011454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 01:02:02.018408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 01:02:02.021647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 01:02:02.025024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 01:02:02.031828 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 01:02:02.034915 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 01:02:02.038549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 01:02:02.041712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 01:02:02.048073 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 01:02:02.051778 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 01:02:02.055216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 01:02:02.061068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 01:02:02.064935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 01:02:02.068184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 01:02:02.074596 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 01:02:02.078105 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5386 01:02:02.081165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5387 01:02:02.084808 Total UI for P1: 0, mck2ui 16
5388 01:02:02.087796 best dqsien dly found for B1: ( 1, 2, 28)
5389 01:02:02.094885 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 01:02:02.094966 Total UI for P1: 0, mck2ui 16
5391 01:02:02.101186 best dqsien dly found for B0: ( 1, 3, 0)
5392 01:02:02.104693 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5393 01:02:02.107695 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5394 01:02:02.107777
5395 01:02:02.111314 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5396 01:02:02.114321 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5397 01:02:02.117802 [Gating] SW calibration Done
5398 01:02:02.117883 ==
5399 01:02:02.120908 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 01:02:02.124765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 01:02:02.124847 ==
5402 01:02:02.127917 RX Vref Scan: 0
5403 01:02:02.127998
5404 01:02:02.128062 RX Vref 0 -> 0, step: 1
5405 01:02:02.128121
5406 01:02:02.130702 RX Delay -80 -> 252, step: 8
5407 01:02:02.134330 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5408 01:02:02.141254 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5409 01:02:02.144140 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5410 01:02:02.147908 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5411 01:02:02.151050 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5412 01:02:02.154255 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5413 01:02:02.157446 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5414 01:02:02.164061 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5415 01:02:02.167952 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5416 01:02:02.171018 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5417 01:02:02.174257 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5418 01:02:02.177524 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5419 01:02:02.180733 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5420 01:02:02.187310 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5421 01:02:02.191055 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5422 01:02:02.194059 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5423 01:02:02.194141 ==
5424 01:02:02.197852 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 01:02:02.201143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 01:02:02.201225 ==
5427 01:02:02.204390 DQS Delay:
5428 01:02:02.204471 DQS0 = 0, DQS1 = 0
5429 01:02:02.207560 DQM Delay:
5430 01:02:02.207642 DQM0 = 104, DQM1 = 95
5431 01:02:02.207707 DQ Delay:
5432 01:02:02.210810 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5433 01:02:02.214006 DQ4 =103, DQ5 =99, DQ6 =107, DQ7 =111
5434 01:02:02.217600 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5435 01:02:02.223903 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5436 01:02:02.223984
5437 01:02:02.224048
5438 01:02:02.224107 ==
5439 01:02:02.227165 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 01:02:02.230335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 01:02:02.230417 ==
5442 01:02:02.230482
5443 01:02:02.230542
5444 01:02:02.234117 TX Vref Scan disable
5445 01:02:02.234199 == TX Byte 0 ==
5446 01:02:02.240561 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5447 01:02:02.243763 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5448 01:02:02.243844 == TX Byte 1 ==
5449 01:02:02.250747 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5450 01:02:02.253765 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5451 01:02:02.253847 ==
5452 01:02:02.257358 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 01:02:02.260403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 01:02:02.260485 ==
5455 01:02:02.260549
5456 01:02:02.260609
5457 01:02:02.263935 TX Vref Scan disable
5458 01:02:02.267458 == TX Byte 0 ==
5459 01:02:02.270528 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5460 01:02:02.273616 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5461 01:02:02.277247 == TX Byte 1 ==
5462 01:02:02.280984 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5463 01:02:02.284145 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5464 01:02:02.284226
5465 01:02:02.287481 [DATLAT]
5466 01:02:02.287562 Freq=933, CH0 RK1
5467 01:02:02.287627
5468 01:02:02.290621 DATLAT Default: 0xb
5469 01:02:02.290702 0, 0xFFFF, sum = 0
5470 01:02:02.293586 1, 0xFFFF, sum = 0
5471 01:02:02.293669 2, 0xFFFF, sum = 0
5472 01:02:02.297034 3, 0xFFFF, sum = 0
5473 01:02:02.297117 4, 0xFFFF, sum = 0
5474 01:02:02.300645 5, 0xFFFF, sum = 0
5475 01:02:02.300728 6, 0xFFFF, sum = 0
5476 01:02:02.303762 7, 0xFFFF, sum = 0
5477 01:02:02.303844 8, 0xFFFF, sum = 0
5478 01:02:02.307733 9, 0xFFFF, sum = 0
5479 01:02:02.307816 10, 0x0, sum = 1
5480 01:02:02.310935 11, 0x0, sum = 2
5481 01:02:02.311018 12, 0x0, sum = 3
5482 01:02:02.314083 13, 0x0, sum = 4
5483 01:02:02.314167 best_step = 11
5484 01:02:02.314230
5485 01:02:02.314290 ==
5486 01:02:02.317390 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 01:02:02.324116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 01:02:02.324199 ==
5489 01:02:02.324263 RX Vref Scan: 0
5490 01:02:02.324362
5491 01:02:02.327465 RX Vref 0 -> 0, step: 1
5492 01:02:02.327546
5493 01:02:02.330660 RX Delay -45 -> 252, step: 4
5494 01:02:02.333785 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5495 01:02:02.337467 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5496 01:02:02.343860 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5497 01:02:02.347099 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5498 01:02:02.350596 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5499 01:02:02.353657 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5500 01:02:02.356925 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5501 01:02:02.363942 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5502 01:02:02.366953 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5503 01:02:02.370263 iDelay=199, Bit 9, Center 86 (7 ~ 166) 160
5504 01:02:02.373718 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5505 01:02:02.376997 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5506 01:02:02.380151 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5507 01:02:02.386820 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5508 01:02:02.390428 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5509 01:02:02.393674 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5510 01:02:02.393776 ==
5511 01:02:02.396909 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 01:02:02.400516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 01:02:02.403494 ==
5514 01:02:02.403567 DQS Delay:
5515 01:02:02.403632 DQS0 = 0, DQS1 = 0
5516 01:02:02.407037 DQM Delay:
5517 01:02:02.407117 DQM0 = 104, DQM1 = 96
5518 01:02:02.410517 DQ Delay:
5519 01:02:02.413511 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5520 01:02:02.416680 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5521 01:02:02.420655 DQ8 =88, DQ9 =86, DQ10 =96, DQ11 =90
5522 01:02:02.423833 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5523 01:02:02.423915
5524 01:02:02.423979
5525 01:02:02.430454 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5526 01:02:02.433607 CH0 RK1: MR19=505, MR18=2C05
5527 01:02:02.439948 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5528 01:02:02.443932 [RxdqsGatingPostProcess] freq 933
5529 01:02:02.446989 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5530 01:02:02.450180 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 01:02:02.453325 best DQS1 dly(2T, 0.5T) = (0, 10)
5532 01:02:02.456812 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 01:02:02.460180 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5534 01:02:02.463342 best DQS0 dly(2T, 0.5T) = (0, 11)
5535 01:02:02.466534 best DQS1 dly(2T, 0.5T) = (0, 10)
5536 01:02:02.470230 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5537 01:02:02.473479 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5538 01:02:02.476623 Pre-setting of DQS Precalculation
5539 01:02:02.479816 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5540 01:02:02.483485 ==
5541 01:02:02.486541 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 01:02:02.489658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 01:02:02.489741 ==
5544 01:02:02.496635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 01:02:02.499460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5546 01:02:02.503524 [CA 0] Center 36 (6~67) winsize 62
5547 01:02:02.507050 [CA 1] Center 36 (6~67) winsize 62
5548 01:02:02.510012 [CA 2] Center 35 (5~65) winsize 61
5549 01:02:02.513587 [CA 3] Center 34 (4~65) winsize 62
5550 01:02:02.517096 [CA 4] Center 34 (4~65) winsize 62
5551 01:02:02.520280 [CA 5] Center 33 (3~64) winsize 62
5552 01:02:02.520417
5553 01:02:02.523564 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5554 01:02:02.523676
5555 01:02:02.526872 [CATrainingPosCal] consider 1 rank data
5556 01:02:02.530191 u2DelayCellTimex100 = 270/100 ps
5557 01:02:02.533690 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5558 01:02:02.536883 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 01:02:02.543704 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5560 01:02:02.546951 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 01:02:02.550186 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 01:02:02.553393 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 01:02:02.553464
5564 01:02:02.556696 CA PerBit enable=1, Macro0, CA PI delay=33
5565 01:02:02.556784
5566 01:02:02.560394 [CBTSetCACLKResult] CA Dly = 33
5567 01:02:02.560476 CS Dly: 6 (0~37)
5568 01:02:02.563337 ==
5569 01:02:02.563419 Dram Type= 6, Freq= 0, CH_1, rank 1
5570 01:02:02.569863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 01:02:02.569944 ==
5572 01:02:02.573637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 01:02:02.579857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5574 01:02:02.583517 [CA 0] Center 37 (7~68) winsize 62
5575 01:02:02.586660 [CA 1] Center 37 (7~68) winsize 62
5576 01:02:02.590341 [CA 2] Center 35 (5~66) winsize 62
5577 01:02:02.593537 [CA 3] Center 34 (4~65) winsize 62
5578 01:02:02.596779 [CA 4] Center 34 (4~65) winsize 62
5579 01:02:02.600143 [CA 5] Center 34 (4~64) winsize 61
5580 01:02:02.600225
5581 01:02:02.603595 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5582 01:02:02.603676
5583 01:02:02.607211 [CATrainingPosCal] consider 2 rank data
5584 01:02:02.610275 u2DelayCellTimex100 = 270/100 ps
5585 01:02:02.613533 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5586 01:02:02.617167 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5587 01:02:02.623900 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5588 01:02:02.626776 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5589 01:02:02.630198 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5590 01:02:02.633781 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5591 01:02:02.633863
5592 01:02:02.637048 CA PerBit enable=1, Macro0, CA PI delay=34
5593 01:02:02.637130
5594 01:02:02.640389 [CBTSetCACLKResult] CA Dly = 34
5595 01:02:02.640470 CS Dly: 7 (0~39)
5596 01:02:02.640534
5597 01:02:02.643504 ----->DramcWriteLeveling(PI) begin...
5598 01:02:02.646805 ==
5599 01:02:02.650279 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 01:02:02.653283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 01:02:02.653358 ==
5602 01:02:02.656992 Write leveling (Byte 0): 25 => 25
5603 01:02:02.660268 Write leveling (Byte 1): 27 => 27
5604 01:02:02.663483 DramcWriteLeveling(PI) end<-----
5605 01:02:02.663565
5606 01:02:02.663628 ==
5607 01:02:02.666779 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 01:02:02.670379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 01:02:02.670461 ==
5610 01:02:02.673628 [Gating] SW mode calibration
5611 01:02:02.679880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5612 01:02:02.686496 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5613 01:02:02.690254 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 01:02:02.693387 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 01:02:02.696529 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 01:02:02.703538 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 01:02:02.706740 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 01:02:02.709870 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 01:02:02.716851 0 14 24 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (0 0)
5620 01:02:02.719902 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
5621 01:02:02.723100 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 01:02:02.729867 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 01:02:02.733094 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 01:02:02.736305 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 01:02:02.743720 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 01:02:02.746612 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 01:02:02.749654 0 15 24 | B1->B0 | 2727 3636 | 0 0 | (0 0) (1 1)
5628 01:02:02.756722 0 15 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5629 01:02:02.759676 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 01:02:02.763146 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 01:02:02.769696 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 01:02:02.772951 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 01:02:02.776352 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 01:02:02.783331 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5635 01:02:02.786552 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5636 01:02:02.789307 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5637 01:02:02.796338 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 01:02:02.800003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 01:02:02.803243 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 01:02:02.809671 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 01:02:02.812932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 01:02:02.816143 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 01:02:02.823111 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 01:02:02.826368 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 01:02:02.829495 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 01:02:02.832698 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 01:02:02.839551 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 01:02:02.843126 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 01:02:02.846320 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 01:02:02.852676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 01:02:02.856306 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5652 01:02:02.859232 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 01:02:02.862941 Total UI for P1: 0, mck2ui 16
5654 01:02:02.866117 best dqsien dly found for B0: ( 1, 2, 24)
5655 01:02:02.869338 Total UI for P1: 0, mck2ui 16
5656 01:02:02.872922 best dqsien dly found for B1: ( 1, 2, 24)
5657 01:02:02.875814 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5658 01:02:02.879267 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5659 01:02:02.882349
5660 01:02:02.885993 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5661 01:02:02.889305 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5662 01:02:02.892563 [Gating] SW calibration Done
5663 01:02:02.892634 ==
5664 01:02:02.895638 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 01:02:02.899134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 01:02:02.899208 ==
5667 01:02:02.899270 RX Vref Scan: 0
5668 01:02:02.899327
5669 01:02:02.902841 RX Vref 0 -> 0, step: 1
5670 01:02:02.902909
5671 01:02:02.905784 RX Delay -80 -> 252, step: 8
5672 01:02:02.909007 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5673 01:02:02.912186 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5674 01:02:02.919149 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5675 01:02:02.922396 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5676 01:02:02.925650 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5677 01:02:02.928738 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5678 01:02:02.932510 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5679 01:02:02.935459 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5680 01:02:02.942475 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5681 01:02:02.945648 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5682 01:02:02.948737 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5683 01:02:02.952319 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5684 01:02:02.955289 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5685 01:02:02.958537 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5686 01:02:02.965206 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5687 01:02:02.968922 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5688 01:02:02.969006 ==
5689 01:02:02.972255 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 01:02:02.975399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 01:02:02.975478 ==
5692 01:02:02.978590 DQS Delay:
5693 01:02:02.978664 DQS0 = 0, DQS1 = 0
5694 01:02:02.978726 DQM Delay:
5695 01:02:02.982142 DQM0 = 102, DQM1 = 98
5696 01:02:02.982214 DQ Delay:
5697 01:02:02.985095 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5698 01:02:02.988883 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5699 01:02:02.992103 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5700 01:02:02.995307 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5701 01:02:02.995382
5702 01:02:02.998454
5703 01:02:02.998525 ==
5704 01:02:03.001861 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 01:02:03.005050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 01:02:03.005127 ==
5707 01:02:03.005189
5708 01:02:03.005247
5709 01:02:03.008248 TX Vref Scan disable
5710 01:02:03.008360 == TX Byte 0 ==
5711 01:02:03.015566 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5712 01:02:03.018816 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5713 01:02:03.018892 == TX Byte 1 ==
5714 01:02:03.024966 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5715 01:02:03.028228 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5716 01:02:03.028352 ==
5717 01:02:03.032173 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 01:02:03.035410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 01:02:03.035493 ==
5720 01:02:03.035556
5721 01:02:03.035614
5722 01:02:03.038818 TX Vref Scan disable
5723 01:02:03.041874 == TX Byte 0 ==
5724 01:02:03.045323 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5725 01:02:03.048605 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5726 01:02:03.051808 == TX Byte 1 ==
5727 01:02:03.054908 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5728 01:02:03.058678 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5729 01:02:03.058760
5730 01:02:03.061604 [DATLAT]
5731 01:02:03.061685 Freq=933, CH1 RK0
5732 01:02:03.061749
5733 01:02:03.065415 DATLAT Default: 0xd
5734 01:02:03.065496 0, 0xFFFF, sum = 0
5735 01:02:03.068528 1, 0xFFFF, sum = 0
5736 01:02:03.068611 2, 0xFFFF, sum = 0
5737 01:02:03.071604 3, 0xFFFF, sum = 0
5738 01:02:03.071686 4, 0xFFFF, sum = 0
5739 01:02:03.075061 5, 0xFFFF, sum = 0
5740 01:02:03.075144 6, 0xFFFF, sum = 0
5741 01:02:03.078865 7, 0xFFFF, sum = 0
5742 01:02:03.078948 8, 0xFFFF, sum = 0
5743 01:02:03.081523 9, 0xFFFF, sum = 0
5744 01:02:03.081606 10, 0x0, sum = 1
5745 01:02:03.085284 11, 0x0, sum = 2
5746 01:02:03.085367 12, 0x0, sum = 3
5747 01:02:03.088317 13, 0x0, sum = 4
5748 01:02:03.088399 best_step = 11
5749 01:02:03.088464
5750 01:02:03.088524 ==
5751 01:02:03.091939 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 01:02:03.095161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 01:02:03.098488 ==
5754 01:02:03.098569 RX Vref Scan: 1
5755 01:02:03.098633
5756 01:02:03.101721 RX Vref 0 -> 0, step: 1
5757 01:02:03.101802
5758 01:02:03.101866 RX Delay -45 -> 252, step: 4
5759 01:02:03.104886
5760 01:02:03.104966 Set Vref, RX VrefLevel [Byte0]: 53
5761 01:02:03.108778 [Byte1]: 53
5762 01:02:03.113261
5763 01:02:03.113343 Final RX Vref Byte 0 = 53 to rank0
5764 01:02:03.116531 Final RX Vref Byte 1 = 53 to rank0
5765 01:02:03.120090 Final RX Vref Byte 0 = 53 to rank1
5766 01:02:03.123250 Final RX Vref Byte 1 = 53 to rank1==
5767 01:02:03.126474 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 01:02:03.133041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 01:02:03.133123 ==
5770 01:02:03.133187 DQS Delay:
5771 01:02:03.136464 DQS0 = 0, DQS1 = 0
5772 01:02:03.136545 DQM Delay:
5773 01:02:03.136609 DQM0 = 102, DQM1 = 98
5774 01:02:03.139753 DQ Delay:
5775 01:02:03.143120 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5776 01:02:03.146628 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5777 01:02:03.150118 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5778 01:02:03.153335 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =106
5779 01:02:03.153417
5780 01:02:03.153481
5781 01:02:03.159780 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5782 01:02:03.162968 CH1 RK0: MR19=505, MR18=152C
5783 01:02:03.169500 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5784 01:02:03.169582
5785 01:02:03.173278 ----->DramcWriteLeveling(PI) begin...
5786 01:02:03.173361 ==
5787 01:02:03.176439 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 01:02:03.179550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 01:02:03.179658 ==
5790 01:02:03.183188 Write leveling (Byte 0): 28 => 28
5791 01:02:03.186370 Write leveling (Byte 1): 29 => 29
5792 01:02:03.189680 DramcWriteLeveling(PI) end<-----
5793 01:02:03.189760
5794 01:02:03.189822 ==
5795 01:02:03.192834 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 01:02:03.199608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 01:02:03.199717 ==
5798 01:02:03.199809 [Gating] SW mode calibration
5799 01:02:03.209439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5800 01:02:03.212486 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5801 01:02:03.215882 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 01:02:03.222756 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 01:02:03.226723 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 01:02:03.229120 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 01:02:03.235793 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 01:02:03.239675 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 01:02:03.242730 0 14 24 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 1)
5808 01:02:03.249427 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5809 01:02:03.252479 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 01:02:03.256047 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 01:02:03.262577 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 01:02:03.266171 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 01:02:03.269423 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 01:02:03.276092 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 01:02:03.279583 0 15 24 | B1->B0 | 3535 2525 | 0 0 | (0 0) (0 0)
5816 01:02:03.282593 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5817 01:02:03.289282 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 01:02:03.292867 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 01:02:03.296101 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 01:02:03.302607 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 01:02:03.306244 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 01:02:03.309251 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 01:02:03.312964 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5824 01:02:03.319316 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5825 01:02:03.323071 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5826 01:02:03.326380 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 01:02:03.332709 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 01:02:03.335913 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 01:02:03.339228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 01:02:03.345748 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 01:02:03.349516 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 01:02:03.352627 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 01:02:03.358937 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 01:02:03.362785 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 01:02:03.365891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 01:02:03.372389 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 01:02:03.376120 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 01:02:03.379628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 01:02:03.385924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 01:02:03.389530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 01:02:03.392269 Total UI for P1: 0, mck2ui 16
5842 01:02:03.396053 best dqsien dly found for B0: ( 1, 2, 26)
5843 01:02:03.399399 Total UI for P1: 0, mck2ui 16
5844 01:02:03.402315 best dqsien dly found for B1: ( 1, 2, 26)
5845 01:02:03.406095 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5846 01:02:03.409305 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5847 01:02:03.409412
5848 01:02:03.412342 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5849 01:02:03.416059 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5850 01:02:03.418781 [Gating] SW calibration Done
5851 01:02:03.418863 ==
5852 01:02:03.422515 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 01:02:03.425700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 01:02:03.428806 ==
5855 01:02:03.428887 RX Vref Scan: 0
5856 01:02:03.428952
5857 01:02:03.432652 RX Vref 0 -> 0, step: 1
5858 01:02:03.432733
5859 01:02:03.435300 RX Delay -80 -> 252, step: 8
5860 01:02:03.439092 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5861 01:02:03.442376 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5862 01:02:03.445581 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5863 01:02:03.448599 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5864 01:02:03.451996 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5865 01:02:03.458708 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5866 01:02:03.461683 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5867 01:02:03.465305 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5868 01:02:03.468502 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5869 01:02:03.471635 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5870 01:02:03.475483 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5871 01:02:03.481778 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5872 01:02:03.485445 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5873 01:02:03.488634 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5874 01:02:03.491590 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5875 01:02:03.494879 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5876 01:02:03.498679 ==
5877 01:02:03.501656 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 01:02:03.505039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 01:02:03.505121 ==
5880 01:02:03.505186 DQS Delay:
5881 01:02:03.508581 DQS0 = 0, DQS1 = 0
5882 01:02:03.508663 DQM Delay:
5883 01:02:03.511592 DQM0 = 102, DQM1 = 99
5884 01:02:03.511674 DQ Delay:
5885 01:02:03.514992 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5886 01:02:03.518144 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5887 01:02:03.521510 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5888 01:02:03.525294 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5889 01:02:03.525376
5890 01:02:03.525440
5891 01:02:03.525500 ==
5892 01:02:03.528177 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 01:02:03.531476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 01:02:03.531559 ==
5895 01:02:03.535317
5896 01:02:03.535398
5897 01:02:03.535463 TX Vref Scan disable
5898 01:02:03.538556 == TX Byte 0 ==
5899 01:02:03.541770 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5900 01:02:03.545011 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5901 01:02:03.548324 == TX Byte 1 ==
5902 01:02:03.551491 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5903 01:02:03.554845 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5904 01:02:03.554927 ==
5905 01:02:03.558524 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 01:02:03.564912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 01:02:03.564994 ==
5908 01:02:03.565058
5909 01:02:03.565118
5910 01:02:03.565176 TX Vref Scan disable
5911 01:02:03.569168 == TX Byte 0 ==
5912 01:02:03.572499 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5913 01:02:03.576034 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5914 01:02:03.579105 == TX Byte 1 ==
5915 01:02:03.582322 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5916 01:02:03.588776 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5917 01:02:03.588860
5918 01:02:03.588925 [DATLAT]
5919 01:02:03.588984 Freq=933, CH1 RK1
5920 01:02:03.589042
5921 01:02:03.592668 DATLAT Default: 0xb
5922 01:02:03.592749 0, 0xFFFF, sum = 0
5923 01:02:03.595894 1, 0xFFFF, sum = 0
5924 01:02:03.595977 2, 0xFFFF, sum = 0
5925 01:02:03.599063 3, 0xFFFF, sum = 0
5926 01:02:03.602436 4, 0xFFFF, sum = 0
5927 01:02:03.602519 5, 0xFFFF, sum = 0
5928 01:02:03.605604 6, 0xFFFF, sum = 0
5929 01:02:03.605687 7, 0xFFFF, sum = 0
5930 01:02:03.608725 8, 0xFFFF, sum = 0
5931 01:02:03.608808 9, 0xFFFF, sum = 0
5932 01:02:03.612449 10, 0x0, sum = 1
5933 01:02:03.612533 11, 0x0, sum = 2
5934 01:02:03.615469 12, 0x0, sum = 3
5935 01:02:03.615551 13, 0x0, sum = 4
5936 01:02:03.615616 best_step = 11
5937 01:02:03.615676
5938 01:02:03.618570 ==
5939 01:02:03.622248 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 01:02:03.625709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 01:02:03.625791 ==
5942 01:02:03.625855 RX Vref Scan: 0
5943 01:02:03.625914
5944 01:02:03.628552 RX Vref 0 -> 0, step: 1
5945 01:02:03.628633
5946 01:02:03.632134 RX Delay -45 -> 252, step: 4
5947 01:02:03.635544 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5948 01:02:03.642120 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5949 01:02:03.645305 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5950 01:02:03.648619 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5951 01:02:03.651884 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5952 01:02:03.655103 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5953 01:02:03.662306 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5954 01:02:03.665559 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5955 01:02:03.668788 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5956 01:02:03.671976 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5957 01:02:03.674891 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5958 01:02:03.681825 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5959 01:02:03.685294 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5960 01:02:03.688518 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5961 01:02:03.691652 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5962 01:02:03.694985 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5963 01:02:03.695066 ==
5964 01:02:03.698427 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 01:02:03.705276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 01:02:03.705358 ==
5967 01:02:03.705422 DQS Delay:
5968 01:02:03.708289 DQS0 = 0, DQS1 = 0
5969 01:02:03.708386 DQM Delay:
5970 01:02:03.711666 DQM0 = 104, DQM1 = 101
5971 01:02:03.711748 DQ Delay:
5972 01:02:03.715196 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5973 01:02:03.718209 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5974 01:02:03.721824 DQ8 =92, DQ9 =90, DQ10 =102, DQ11 =94
5975 01:02:03.725081 DQ12 =110, DQ13 =108, DQ14 =106, DQ15 =110
5976 01:02:03.725163
5977 01:02:03.725227
5978 01:02:03.735185 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5979 01:02:03.735268 CH1 RK1: MR19=504, MR18=2BFE
5980 01:02:03.741807 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5981 01:02:03.745183 [RxdqsGatingPostProcess] freq 933
5982 01:02:03.751599 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5983 01:02:03.754736 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 01:02:03.758422 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 01:02:03.761690 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 01:02:03.765027 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 01:02:03.765116 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 01:02:03.768071 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 01:02:03.771235 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 01:02:03.774972 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 01:02:03.778180 Pre-setting of DQS Precalculation
5992 01:02:03.784531 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5993 01:02:03.791285 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5994 01:02:03.798162 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5995 01:02:03.798264
5996 01:02:03.798363
5997 01:02:03.801632 [Calibration Summary] 1866 Mbps
5998 01:02:03.801738 CH 0, Rank 0
5999 01:02:03.805065 SW Impedance : PASS
6000 01:02:03.808220 DUTY Scan : NO K
6001 01:02:03.808363 ZQ Calibration : PASS
6002 01:02:03.811477 Jitter Meter : NO K
6003 01:02:03.815208 CBT Training : PASS
6004 01:02:03.815291 Write leveling : PASS
6005 01:02:03.818332 RX DQS gating : PASS
6006 01:02:03.821479 RX DQ/DQS(RDDQC) : PASS
6007 01:02:03.821561 TX DQ/DQS : PASS
6008 01:02:03.824680 RX DATLAT : PASS
6009 01:02:03.828219 RX DQ/DQS(Engine): PASS
6010 01:02:03.828361 TX OE : NO K
6011 01:02:03.828446 All Pass.
6012 01:02:03.831284
6013 01:02:03.831367 CH 0, Rank 1
6014 01:02:03.834584 SW Impedance : PASS
6015 01:02:03.834667 DUTY Scan : NO K
6016 01:02:03.837835 ZQ Calibration : PASS
6017 01:02:03.841033 Jitter Meter : NO K
6018 01:02:03.841116 CBT Training : PASS
6019 01:02:03.844933 Write leveling : PASS
6020 01:02:03.845017 RX DQS gating : PASS
6021 01:02:03.847957 RX DQ/DQS(RDDQC) : PASS
6022 01:02:03.851195 TX DQ/DQS : PASS
6023 01:02:03.851279 RX DATLAT : PASS
6024 01:02:03.854810 RX DQ/DQS(Engine): PASS
6025 01:02:03.858215 TX OE : NO K
6026 01:02:03.858298 All Pass.
6027 01:02:03.858383
6028 01:02:03.858462 CH 1, Rank 0
6029 01:02:03.861231 SW Impedance : PASS
6030 01:02:03.864592 DUTY Scan : NO K
6031 01:02:03.864676 ZQ Calibration : PASS
6032 01:02:03.868021 Jitter Meter : NO K
6033 01:02:03.871152 CBT Training : PASS
6034 01:02:03.871236 Write leveling : PASS
6035 01:02:03.874343 RX DQS gating : PASS
6036 01:02:03.877682 RX DQ/DQS(RDDQC) : PASS
6037 01:02:03.877764 TX DQ/DQS : PASS
6038 01:02:03.880853 RX DATLAT : PASS
6039 01:02:03.884712 RX DQ/DQS(Engine): PASS
6040 01:02:03.884793 TX OE : NO K
6041 01:02:03.884858 All Pass.
6042 01:02:03.887925
6043 01:02:03.888031 CH 1, Rank 1
6044 01:02:03.891184 SW Impedance : PASS
6045 01:02:03.891265 DUTY Scan : NO K
6046 01:02:03.894145 ZQ Calibration : PASS
6047 01:02:03.894227 Jitter Meter : NO K
6048 01:02:03.897859 CBT Training : PASS
6049 01:02:03.901057 Write leveling : PASS
6050 01:02:03.901138 RX DQS gating : PASS
6051 01:02:03.904110 RX DQ/DQS(RDDQC) : PASS
6052 01:02:03.907720 TX DQ/DQS : PASS
6053 01:02:03.907802 RX DATLAT : PASS
6054 01:02:03.910910 RX DQ/DQS(Engine): PASS
6055 01:02:03.914041 TX OE : NO K
6056 01:02:03.914123 All Pass.
6057 01:02:03.914187
6058 01:02:03.917471 DramC Write-DBI off
6059 01:02:03.917553 PER_BANK_REFRESH: Hybrid Mode
6060 01:02:03.920904 TX_TRACKING: ON
6061 01:02:03.927244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6062 01:02:03.934218 [FAST_K] Save calibration result to emmc
6063 01:02:03.937729 dramc_set_vcore_voltage set vcore to 650000
6064 01:02:03.937811 Read voltage for 400, 6
6065 01:02:03.940741 Vio18 = 0
6066 01:02:03.940822 Vcore = 650000
6067 01:02:03.940887 Vdram = 0
6068 01:02:03.944491 Vddq = 0
6069 01:02:03.944571 Vmddr = 0
6070 01:02:03.947627 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6071 01:02:03.953936 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6072 01:02:03.957610 MEM_TYPE=3, freq_sel=20
6073 01:02:03.960598 sv_algorithm_assistance_LP4_800
6074 01:02:03.963861 ============ PULL DRAM RESETB DOWN ============
6075 01:02:03.967657 ========== PULL DRAM RESETB DOWN end =========
6076 01:02:03.970714 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6077 01:02:03.974092 ===================================
6078 01:02:03.977457 LPDDR4 DRAM CONFIGURATION
6079 01:02:03.980881 ===================================
6080 01:02:03.983965 EX_ROW_EN[0] = 0x0
6081 01:02:03.984046 EX_ROW_EN[1] = 0x0
6082 01:02:03.987137 LP4Y_EN = 0x0
6083 01:02:03.987219 WORK_FSP = 0x0
6084 01:02:03.990949 WL = 0x2
6085 01:02:03.991044 RL = 0x2
6086 01:02:03.994140 BL = 0x2
6087 01:02:03.994251 RPST = 0x0
6088 01:02:03.997304 RD_PRE = 0x0
6089 01:02:04.000448 WR_PRE = 0x1
6090 01:02:04.000554 WR_PST = 0x0
6091 01:02:04.004083 DBI_WR = 0x0
6092 01:02:04.004191 DBI_RD = 0x0
6093 01:02:04.007363 OTF = 0x1
6094 01:02:04.010385 ===================================
6095 01:02:04.013889 ===================================
6096 01:02:04.013997 ANA top config
6097 01:02:04.017173 ===================================
6098 01:02:04.020326 DLL_ASYNC_EN = 0
6099 01:02:04.023603 ALL_SLAVE_EN = 1
6100 01:02:04.023687 NEW_RANK_MODE = 1
6101 01:02:04.027203 DLL_IDLE_MODE = 1
6102 01:02:04.030327 LP45_APHY_COMB_EN = 1
6103 01:02:04.033707 TX_ODT_DIS = 1
6104 01:02:04.033792 NEW_8X_MODE = 1
6105 01:02:04.036910 ===================================
6106 01:02:04.040128 ===================================
6107 01:02:04.043903 data_rate = 800
6108 01:02:04.046911 CKR = 1
6109 01:02:04.050531 DQ_P2S_RATIO = 4
6110 01:02:04.053761 ===================================
6111 01:02:04.057163 CA_P2S_RATIO = 4
6112 01:02:04.060307 DQ_CA_OPEN = 0
6113 01:02:04.060392 DQ_SEMI_OPEN = 1
6114 01:02:04.063535 CA_SEMI_OPEN = 1
6115 01:02:04.067014 CA_FULL_RATE = 0
6116 01:02:04.070081 DQ_CKDIV4_EN = 0
6117 01:02:04.073838 CA_CKDIV4_EN = 1
6118 01:02:04.077051 CA_PREDIV_EN = 0
6119 01:02:04.077168 PH8_DLY = 0
6120 01:02:04.080165 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6121 01:02:04.083650 DQ_AAMCK_DIV = 0
6122 01:02:04.087204 CA_AAMCK_DIV = 0
6123 01:02:04.090412 CA_ADMCK_DIV = 4
6124 01:02:04.094017 DQ_TRACK_CA_EN = 0
6125 01:02:04.094101 CA_PICK = 800
6126 01:02:04.097358 CA_MCKIO = 400
6127 01:02:04.100542 MCKIO_SEMI = 400
6128 01:02:04.103639 PLL_FREQ = 3016
6129 01:02:04.106718 DQ_UI_PI_RATIO = 32
6130 01:02:04.110437 CA_UI_PI_RATIO = 32
6131 01:02:04.113632 ===================================
6132 01:02:04.116713 ===================================
6133 01:02:04.120277 memory_type:LPDDR4
6134 01:02:04.120400 GP_NUM : 10
6135 01:02:04.123523 SRAM_EN : 1
6136 01:02:04.123607 MD32_EN : 0
6137 01:02:04.126684 ===================================
6138 01:02:04.130387 [ANA_INIT] >>>>>>>>>>>>>>
6139 01:02:04.133609 <<<<<< [CONFIGURE PHASE]: ANA_TX
6140 01:02:04.137349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6141 01:02:04.140667 ===================================
6142 01:02:04.143552 data_rate = 800,PCW = 0X7400
6143 01:02:04.146670 ===================================
6144 01:02:04.149869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6145 01:02:04.153734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6146 01:02:04.166534 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 01:02:04.170273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6148 01:02:04.173214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6149 01:02:04.176628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6150 01:02:04.180204 [ANA_INIT] flow start
6151 01:02:04.183331 [ANA_INIT] PLL >>>>>>>>
6152 01:02:04.183413 [ANA_INIT] PLL <<<<<<<<
6153 01:02:04.186716 [ANA_INIT] MIDPI >>>>>>>>
6154 01:02:04.189754 [ANA_INIT] MIDPI <<<<<<<<
6155 01:02:04.189835 [ANA_INIT] DLL >>>>>>>>
6156 01:02:04.193036 [ANA_INIT] flow end
6157 01:02:04.196679 ============ LP4 DIFF to SE enter ============
6158 01:02:04.203189 ============ LP4 DIFF to SE exit ============
6159 01:02:04.203271 [ANA_INIT] <<<<<<<<<<<<<
6160 01:02:04.206513 [Flow] Enable top DCM control >>>>>
6161 01:02:04.209956 [Flow] Enable top DCM control <<<<<
6162 01:02:04.212932 Enable DLL master slave shuffle
6163 01:02:04.219929 ==============================================================
6164 01:02:04.220037 Gating Mode config
6165 01:02:04.226765 ==============================================================
6166 01:02:04.229962 Config description:
6167 01:02:04.236668 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6168 01:02:04.243111 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6169 01:02:04.249844 SELPH_MODE 0: By rank 1: By Phase
6170 01:02:04.256298 ==============================================================
6171 01:02:04.256394 GAT_TRACK_EN = 0
6172 01:02:04.259538 RX_GATING_MODE = 2
6173 01:02:04.262694 RX_GATING_TRACK_MODE = 2
6174 01:02:04.266358 SELPH_MODE = 1
6175 01:02:04.269474 PICG_EARLY_EN = 1
6176 01:02:04.272798 VALID_LAT_VALUE = 1
6177 01:02:04.279199 ==============================================================
6178 01:02:04.282889 Enter into Gating configuration >>>>
6179 01:02:04.286024 Exit from Gating configuration <<<<
6180 01:02:04.289245 Enter into DVFS_PRE_config >>>>>
6181 01:02:04.298920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6182 01:02:04.302813 Exit from DVFS_PRE_config <<<<<
6183 01:02:04.306010 Enter into PICG configuration >>>>
6184 01:02:04.309057 Exit from PICG configuration <<<<
6185 01:02:04.312710 [RX_INPUT] configuration >>>>>
6186 01:02:04.315659 [RX_INPUT] configuration <<<<<
6187 01:02:04.318908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6188 01:02:04.325520 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6189 01:02:04.332273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 01:02:04.335657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 01:02:04.342145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6192 01:02:04.349092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6193 01:02:04.352205 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6194 01:02:04.358940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6195 01:02:04.362146 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6196 01:02:04.365467 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6197 01:02:04.369134 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6198 01:02:04.375407 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6199 01:02:04.378653 ===================================
6200 01:02:04.378737 LPDDR4 DRAM CONFIGURATION
6201 01:02:04.381802 ===================================
6202 01:02:04.385174 EX_ROW_EN[0] = 0x0
6203 01:02:04.388917 EX_ROW_EN[1] = 0x0
6204 01:02:04.389000 LP4Y_EN = 0x0
6205 01:02:04.391813 WORK_FSP = 0x0
6206 01:02:04.391895 WL = 0x2
6207 01:02:04.395552 RL = 0x2
6208 01:02:04.395635 BL = 0x2
6209 01:02:04.398737 RPST = 0x0
6210 01:02:04.398821 RD_PRE = 0x0
6211 01:02:04.401861 WR_PRE = 0x1
6212 01:02:04.401945 WR_PST = 0x0
6213 01:02:04.405265 DBI_WR = 0x0
6214 01:02:04.405349 DBI_RD = 0x0
6215 01:02:04.409023 OTF = 0x1
6216 01:02:04.411630 ===================================
6217 01:02:04.415541 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6218 01:02:04.418723 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6219 01:02:04.425120 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 01:02:04.428305 ===================================
6221 01:02:04.428403 LPDDR4 DRAM CONFIGURATION
6222 01:02:04.431522 ===================================
6223 01:02:04.435315 EX_ROW_EN[0] = 0x10
6224 01:02:04.438751 EX_ROW_EN[1] = 0x0
6225 01:02:04.438832 LP4Y_EN = 0x0
6226 01:02:04.441606 WORK_FSP = 0x0
6227 01:02:04.441687 WL = 0x2
6228 01:02:04.445169 RL = 0x2
6229 01:02:04.445250 BL = 0x2
6230 01:02:04.448523 RPST = 0x0
6231 01:02:04.448604 RD_PRE = 0x0
6232 01:02:04.451693 WR_PRE = 0x1
6233 01:02:04.451774 WR_PST = 0x0
6234 01:02:04.455220 DBI_WR = 0x0
6235 01:02:04.455302 DBI_RD = 0x0
6236 01:02:04.458164 OTF = 0x1
6237 01:02:04.461454 ===================================
6238 01:02:04.468341 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6239 01:02:04.471586 nWR fixed to 30
6240 01:02:04.471707 [ModeRegInit_LP4] CH0 RK0
6241 01:02:04.474709 [ModeRegInit_LP4] CH0 RK1
6242 01:02:04.478256 [ModeRegInit_LP4] CH1 RK0
6243 01:02:04.478338 [ModeRegInit_LP4] CH1 RK1
6244 01:02:04.481664 match AC timing 19
6245 01:02:04.484823 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6246 01:02:04.487967 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6247 01:02:04.495051 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6248 01:02:04.497992 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6249 01:02:04.504996 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6250 01:02:04.505078 ==
6251 01:02:04.508137 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 01:02:04.511274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 01:02:04.511357 ==
6254 01:02:04.518093 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 01:02:04.521295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6256 01:02:04.525168 [CA 0] Center 36 (8~64) winsize 57
6257 01:02:04.528282 [CA 1] Center 36 (8~64) winsize 57
6258 01:02:04.531550 [CA 2] Center 36 (8~64) winsize 57
6259 01:02:04.534679 [CA 3] Center 36 (8~64) winsize 57
6260 01:02:04.538439 [CA 4] Center 36 (8~64) winsize 57
6261 01:02:04.541401 [CA 5] Center 36 (8~64) winsize 57
6262 01:02:04.541483
6263 01:02:04.544740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6264 01:02:04.544822
6265 01:02:04.548490 [CATrainingPosCal] consider 1 rank data
6266 01:02:04.551606 u2DelayCellTimex100 = 270/100 ps
6267 01:02:04.554605 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 01:02:04.558289 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 01:02:04.561546 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 01:02:04.567985 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 01:02:04.571608 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 01:02:04.574508 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 01:02:04.574589
6274 01:02:04.577978 CA PerBit enable=1, Macro0, CA PI delay=36
6275 01:02:04.578060
6276 01:02:04.581458 [CBTSetCACLKResult] CA Dly = 36
6277 01:02:04.581540 CS Dly: 1 (0~32)
6278 01:02:04.581604 ==
6279 01:02:04.584996 Dram Type= 6, Freq= 0, CH_0, rank 1
6280 01:02:04.591575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 01:02:04.591660 ==
6282 01:02:04.594589 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6283 01:02:04.601262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6284 01:02:04.604748 [CA 0] Center 36 (8~64) winsize 57
6285 01:02:04.608022 [CA 1] Center 36 (8~64) winsize 57
6286 01:02:04.610933 [CA 2] Center 36 (8~64) winsize 57
6287 01:02:04.614646 [CA 3] Center 36 (8~64) winsize 57
6288 01:02:04.618064 [CA 4] Center 36 (8~64) winsize 57
6289 01:02:04.621270 [CA 5] Center 36 (8~64) winsize 57
6290 01:02:04.621351
6291 01:02:04.624725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6292 01:02:04.624806
6293 01:02:04.627942 [CATrainingPosCal] consider 2 rank data
6294 01:02:04.631083 u2DelayCellTimex100 = 270/100 ps
6295 01:02:04.634248 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 01:02:04.637474 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 01:02:04.641295 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 01:02:04.644339 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 01:02:04.647480 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 01:02:04.650731 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 01:02:04.654051
6302 01:02:04.657734 CA PerBit enable=1, Macro0, CA PI delay=36
6303 01:02:04.657816
6304 01:02:04.660823 [CBTSetCACLKResult] CA Dly = 36
6305 01:02:04.660905 CS Dly: 1 (0~32)
6306 01:02:04.660969
6307 01:02:04.663915 ----->DramcWriteLeveling(PI) begin...
6308 01:02:04.663997 ==
6309 01:02:04.667229 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 01:02:04.670597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 01:02:04.674292 ==
6312 01:02:04.674373 Write leveling (Byte 0): 40 => 8
6313 01:02:04.677523 Write leveling (Byte 1): 40 => 8
6314 01:02:04.680523 DramcWriteLeveling(PI) end<-----
6315 01:02:04.680604
6316 01:02:04.680667 ==
6317 01:02:04.684061 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 01:02:04.690348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 01:02:04.690429 ==
6320 01:02:04.690494 [Gating] SW mode calibration
6321 01:02:04.700205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6322 01:02:04.704078 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6323 01:02:04.710599 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6324 01:02:04.713580 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 01:02:04.717380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 01:02:04.724038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 01:02:04.727334 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 01:02:04.730400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 01:02:04.736969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 01:02:04.740486 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 01:02:04.743622 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 01:02:04.746845 Total UI for P1: 0, mck2ui 16
6333 01:02:04.750295 best dqsien dly found for B0: ( 0, 14, 24)
6334 01:02:04.753285 Total UI for P1: 0, mck2ui 16
6335 01:02:04.756735 best dqsien dly found for B1: ( 0, 14, 24)
6336 01:02:04.760029 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6337 01:02:04.763212 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6338 01:02:04.763294
6339 01:02:04.766830 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6340 01:02:04.773212 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 01:02:04.773294 [Gating] SW calibration Done
6342 01:02:04.773359 ==
6343 01:02:04.776508 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 01:02:04.783070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 01:02:04.783152 ==
6346 01:02:04.783216 RX Vref Scan: 0
6347 01:02:04.783276
6348 01:02:04.786754 RX Vref 0 -> 0, step: 1
6349 01:02:04.786834
6350 01:02:04.789719 RX Delay -410 -> 252, step: 16
6351 01:02:04.793212 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6352 01:02:04.796937 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6353 01:02:04.803433 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6354 01:02:04.806539 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6355 01:02:04.809784 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6356 01:02:04.813002 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6357 01:02:04.819482 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6358 01:02:04.823292 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6359 01:02:04.826478 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6360 01:02:04.829522 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6361 01:02:04.836431 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6362 01:02:04.839423 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6363 01:02:04.843144 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6364 01:02:04.849551 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6365 01:02:04.852638 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6366 01:02:04.856068 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6367 01:02:04.856151 ==
6368 01:02:04.859274 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 01:02:04.862859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 01:02:04.862941 ==
6371 01:02:04.866297 DQS Delay:
6372 01:02:04.866378 DQS0 = 27, DQS1 = 35
6373 01:02:04.869249 DQM Delay:
6374 01:02:04.869330 DQM0 = 11, DQM1 = 11
6375 01:02:04.869393 DQ Delay:
6376 01:02:04.872711 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6377 01:02:04.876349 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6378 01:02:04.879356 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6379 01:02:04.883123 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6380 01:02:04.883204
6381 01:02:04.883268
6382 01:02:04.883327 ==
6383 01:02:04.885863 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 01:02:04.892814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 01:02:04.892896 ==
6386 01:02:04.892960
6387 01:02:04.893019
6388 01:02:04.893076 TX Vref Scan disable
6389 01:02:04.895912 == TX Byte 0 ==
6390 01:02:04.899533 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 01:02:04.902929 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 01:02:04.905845 == TX Byte 1 ==
6393 01:02:04.909383 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 01:02:04.912904 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 01:02:04.912986 ==
6396 01:02:04.916129 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 01:02:04.922538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 01:02:04.922620 ==
6399 01:02:04.922683
6400 01:02:04.922743
6401 01:02:04.922800 TX Vref Scan disable
6402 01:02:04.925794 == TX Byte 0 ==
6403 01:02:04.929651 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 01:02:04.932805 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 01:02:04.936011 == TX Byte 1 ==
6406 01:02:04.939301 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 01:02:04.942931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 01:02:04.943012
6409 01:02:04.945917 [DATLAT]
6410 01:02:04.945998 Freq=400, CH0 RK0
6411 01:02:04.946063
6412 01:02:04.949437 DATLAT Default: 0xf
6413 01:02:04.949518 0, 0xFFFF, sum = 0
6414 01:02:04.952618 1, 0xFFFF, sum = 0
6415 01:02:04.952700 2, 0xFFFF, sum = 0
6416 01:02:04.955896 3, 0xFFFF, sum = 0
6417 01:02:04.955979 4, 0xFFFF, sum = 0
6418 01:02:04.959724 5, 0xFFFF, sum = 0
6419 01:02:04.959806 6, 0xFFFF, sum = 0
6420 01:02:04.962978 7, 0xFFFF, sum = 0
6421 01:02:04.963061 8, 0xFFFF, sum = 0
6422 01:02:04.966183 9, 0xFFFF, sum = 0
6423 01:02:04.966266 10, 0xFFFF, sum = 0
6424 01:02:04.969472 11, 0xFFFF, sum = 0
6425 01:02:04.972604 12, 0xFFFF, sum = 0
6426 01:02:04.972686 13, 0x0, sum = 1
6427 01:02:04.975664 14, 0x0, sum = 2
6428 01:02:04.975746 15, 0x0, sum = 3
6429 01:02:04.975811 16, 0x0, sum = 4
6430 01:02:04.979026 best_step = 14
6431 01:02:04.979107
6432 01:02:04.979171 ==
6433 01:02:04.982488 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 01:02:04.986510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 01:02:04.986591 ==
6436 01:02:04.989175 RX Vref Scan: 1
6437 01:02:04.989257
6438 01:02:04.989321 RX Vref 0 -> 0, step: 1
6439 01:02:04.992652
6440 01:02:04.992733 RX Delay -311 -> 252, step: 8
6441 01:02:04.992797
6442 01:02:04.996002 Set Vref, RX VrefLevel [Byte0]: 55
6443 01:02:04.999115 [Byte1]: 58
6444 01:02:05.003965
6445 01:02:05.004046 Final RX Vref Byte 0 = 55 to rank0
6446 01:02:05.007951 Final RX Vref Byte 1 = 58 to rank0
6447 01:02:05.010711 Final RX Vref Byte 0 = 55 to rank1
6448 01:02:05.014165 Final RX Vref Byte 1 = 58 to rank1==
6449 01:02:05.017273 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 01:02:05.023634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 01:02:05.023719 ==
6452 01:02:05.023784 DQS Delay:
6453 01:02:05.027062 DQS0 = 28, DQS1 = 36
6454 01:02:05.027144 DQM Delay:
6455 01:02:05.030633 DQM0 = 11, DQM1 = 13
6456 01:02:05.030715 DQ Delay:
6457 01:02:05.033949 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6458 01:02:05.037106 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6459 01:02:05.037195 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6460 01:02:05.040191 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6461 01:02:05.043415
6462 01:02:05.043498
6463 01:02:05.050555 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6464 01:02:05.053389 CH0 RK0: MR19=C0C, MR18=C8B4
6465 01:02:05.060083 CH0_RK0: MR19=0xC0C, MR18=0xC8B4, DQSOSC=385, MR23=63, INC=398, DEC=265
6466 01:02:05.060165 ==
6467 01:02:05.063357 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 01:02:05.067182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 01:02:05.067268 ==
6470 01:02:05.070526 [Gating] SW mode calibration
6471 01:02:05.077052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6472 01:02:05.083914 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6473 01:02:05.086984 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6474 01:02:05.090550 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 01:02:05.096954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 01:02:05.100579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 01:02:05.103884 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 01:02:05.110477 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 01:02:05.113758 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 01:02:05.116969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 01:02:05.120532 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 01:02:05.123244 Total UI for P1: 0, mck2ui 16
6483 01:02:05.126887 best dqsien dly found for B0: ( 0, 14, 24)
6484 01:02:05.130474 Total UI for P1: 0, mck2ui 16
6485 01:02:05.133414 best dqsien dly found for B1: ( 0, 14, 24)
6486 01:02:05.136643 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6487 01:02:05.143298 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6488 01:02:05.143380
6489 01:02:05.146555 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6490 01:02:05.149982 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 01:02:05.153155 [Gating] SW calibration Done
6492 01:02:05.153237 ==
6493 01:02:05.156632 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 01:02:05.159780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 01:02:05.159862 ==
6496 01:02:05.163162 RX Vref Scan: 0
6497 01:02:05.163244
6498 01:02:05.163308 RX Vref 0 -> 0, step: 1
6499 01:02:05.163370
6500 01:02:05.166623 RX Delay -410 -> 252, step: 16
6501 01:02:05.169792 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6502 01:02:05.176304 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6503 01:02:05.180115 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6504 01:02:05.183577 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6505 01:02:05.186611 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6506 01:02:05.192945 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6507 01:02:05.196269 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6508 01:02:05.199454 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6509 01:02:05.203346 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6510 01:02:05.209646 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6511 01:02:05.212820 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6512 01:02:05.216159 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6513 01:02:05.219669 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6514 01:02:05.226171 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6515 01:02:05.229521 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6516 01:02:05.233165 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6517 01:02:05.233247 ==
6518 01:02:05.235992 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 01:02:05.242890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 01:02:05.242972 ==
6521 01:02:05.243037 DQS Delay:
6522 01:02:05.246154 DQS0 = 27, DQS1 = 35
6523 01:02:05.246236 DQM Delay:
6524 01:02:05.246300 DQM0 = 12, DQM1 = 10
6525 01:02:05.249286 DQ Delay:
6526 01:02:05.253024 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6527 01:02:05.253106 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6528 01:02:05.256397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6529 01:02:05.259540 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6530 01:02:05.259622
6531 01:02:05.259687
6532 01:02:05.263068 ==
6533 01:02:05.267090 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 01:02:05.269496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 01:02:05.269578 ==
6536 01:02:05.269642
6537 01:02:05.269701
6538 01:02:05.273088 TX Vref Scan disable
6539 01:02:05.273169 == TX Byte 0 ==
6540 01:02:05.276693 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6541 01:02:05.282793 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6542 01:02:05.282875 == TX Byte 1 ==
6543 01:02:05.286258 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6544 01:02:05.293060 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6545 01:02:05.293142 ==
6546 01:02:05.296219 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 01:02:05.299226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 01:02:05.299307 ==
6549 01:02:05.299371
6550 01:02:05.299430
6551 01:02:05.302930 TX Vref Scan disable
6552 01:02:05.303010 == TX Byte 0 ==
6553 01:02:05.306034 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6554 01:02:05.312568 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6555 01:02:05.312650 == TX Byte 1 ==
6556 01:02:05.316205 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6557 01:02:05.322572 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6558 01:02:05.322653
6559 01:02:05.322717 [DATLAT]
6560 01:02:05.322776 Freq=400, CH0 RK1
6561 01:02:05.322834
6562 01:02:05.325920 DATLAT Default: 0xe
6563 01:02:05.326000 0, 0xFFFF, sum = 0
6564 01:02:05.329365 1, 0xFFFF, sum = 0
6565 01:02:05.329448 2, 0xFFFF, sum = 0
6566 01:02:05.332571 3, 0xFFFF, sum = 0
6567 01:02:05.335868 4, 0xFFFF, sum = 0
6568 01:02:05.335950 5, 0xFFFF, sum = 0
6569 01:02:05.339509 6, 0xFFFF, sum = 0
6570 01:02:05.339590 7, 0xFFFF, sum = 0
6571 01:02:05.342557 8, 0xFFFF, sum = 0
6572 01:02:05.342649 9, 0xFFFF, sum = 0
6573 01:02:05.345702 10, 0xFFFF, sum = 0
6574 01:02:05.345784 11, 0xFFFF, sum = 0
6575 01:02:05.349418 12, 0xFFFF, sum = 0
6576 01:02:05.349499 13, 0x0, sum = 1
6577 01:02:05.352511 14, 0x0, sum = 2
6578 01:02:05.352593 15, 0x0, sum = 3
6579 01:02:05.355695 16, 0x0, sum = 4
6580 01:02:05.355787 best_step = 14
6581 01:02:05.355852
6582 01:02:05.355911 ==
6583 01:02:05.359574 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 01:02:05.362785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 01:02:05.365904 ==
6586 01:02:05.365984 RX Vref Scan: 0
6587 01:02:05.366049
6588 01:02:05.369094 RX Vref 0 -> 0, step: 1
6589 01:02:05.369175
6590 01:02:05.372645 RX Delay -311 -> 252, step: 8
6591 01:02:05.375701 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6592 01:02:05.382478 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6593 01:02:05.385477 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6594 01:02:05.388935 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6595 01:02:05.392400 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6596 01:02:05.398854 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6597 01:02:05.402634 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6598 01:02:05.405872 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6599 01:02:05.409521 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6600 01:02:05.415396 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6601 01:02:05.418540 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6602 01:02:05.421847 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6603 01:02:05.425709 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6604 01:02:05.431922 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6605 01:02:05.435394 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6606 01:02:05.438731 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6607 01:02:05.438814 ==
6608 01:02:05.441872 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 01:02:05.448977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 01:02:05.449060 ==
6611 01:02:05.449126 DQS Delay:
6612 01:02:05.451952 DQS0 = 24, DQS1 = 32
6613 01:02:05.452060 DQM Delay:
6614 01:02:05.452152 DQM0 = 8, DQM1 = 10
6615 01:02:05.455358 DQ Delay:
6616 01:02:05.458557 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6617 01:02:05.458639 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6618 01:02:05.461803 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6619 01:02:05.465586 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6620 01:02:05.465668
6621 01:02:05.465736
6622 01:02:05.475177 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6623 01:02:05.479055 CH0 RK1: MR19=C0C, MR18=BB5A
6624 01:02:05.485738 CH0_RK1: MR19=0xC0C, MR18=0xBB5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6625 01:02:05.485821 [RxdqsGatingPostProcess] freq 400
6626 01:02:05.491816 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6627 01:02:05.495043 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 01:02:05.499002 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 01:02:05.502138 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 01:02:05.505098 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 01:02:05.508545 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 01:02:05.512007 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 01:02:05.515498 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 01:02:05.518408 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 01:02:05.521873 Pre-setting of DQS Precalculation
6636 01:02:05.525182 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6637 01:02:05.525264 ==
6638 01:02:05.528272 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 01:02:05.531959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 01:02:05.535583 ==
6641 01:02:05.538661 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 01:02:05.545334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 01:02:05.548402 [CA 0] Center 36 (8~64) winsize 57
6644 01:02:05.551996 [CA 1] Center 36 (8~64) winsize 57
6645 01:02:05.555083 [CA 2] Center 36 (8~64) winsize 57
6646 01:02:05.558326 [CA 3] Center 36 (8~64) winsize 57
6647 01:02:05.561903 [CA 4] Center 36 (8~64) winsize 57
6648 01:02:05.565458 [CA 5] Center 36 (8~64) winsize 57
6649 01:02:05.565541
6650 01:02:05.568558 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 01:02:05.568641
6652 01:02:05.571811 [CATrainingPosCal] consider 1 rank data
6653 01:02:05.574957 u2DelayCellTimex100 = 270/100 ps
6654 01:02:05.578132 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 01:02:05.581322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 01:02:05.584522 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 01:02:05.588204 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 01:02:05.591375 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 01:02:05.595028 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 01:02:05.595111
6661 01:02:05.601381 CA PerBit enable=1, Macro0, CA PI delay=36
6662 01:02:05.601463
6663 01:02:05.601528 [CBTSetCACLKResult] CA Dly = 36
6664 01:02:05.604601 CS Dly: 1 (0~32)
6665 01:02:05.604683 ==
6666 01:02:05.608409 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 01:02:05.611331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 01:02:05.611414 ==
6669 01:02:05.617887 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6670 01:02:05.625105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6671 01:02:05.628302 [CA 0] Center 36 (8~64) winsize 57
6672 01:02:05.631510 [CA 1] Center 36 (8~64) winsize 57
6673 01:02:05.634513 [CA 2] Center 36 (8~64) winsize 57
6674 01:02:05.634596 [CA 3] Center 36 (8~64) winsize 57
6675 01:02:05.638044 [CA 4] Center 36 (8~64) winsize 57
6676 01:02:05.641329 [CA 5] Center 36 (8~64) winsize 57
6677 01:02:05.641412
6678 01:02:05.644642 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6679 01:02:05.647960
6680 01:02:05.651128 [CATrainingPosCal] consider 2 rank data
6681 01:02:05.651211 u2DelayCellTimex100 = 270/100 ps
6682 01:02:05.657912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 01:02:05.661306 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 01:02:05.664745 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 01:02:05.668328 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 01:02:05.671001 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 01:02:05.674504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 01:02:05.674586
6689 01:02:05.677636 CA PerBit enable=1, Macro0, CA PI delay=36
6690 01:02:05.677718
6691 01:02:05.681505 [CBTSetCACLKResult] CA Dly = 36
6692 01:02:05.684742 CS Dly: 1 (0~32)
6693 01:02:05.684824
6694 01:02:05.687984 ----->DramcWriteLeveling(PI) begin...
6695 01:02:05.688068 ==
6696 01:02:05.691132 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 01:02:05.694697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 01:02:05.694781 ==
6699 01:02:05.697823 Write leveling (Byte 0): 40 => 8
6700 01:02:05.700882 Write leveling (Byte 1): 40 => 8
6701 01:02:05.704726 DramcWriteLeveling(PI) end<-----
6702 01:02:05.704808
6703 01:02:05.704873 ==
6704 01:02:05.707874 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 01:02:05.711028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 01:02:05.711112 ==
6707 01:02:05.714276 [Gating] SW mode calibration
6708 01:02:05.721473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6709 01:02:05.728152 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6710 01:02:05.731359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6711 01:02:05.734199 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 01:02:05.741271 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 01:02:05.744322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 01:02:05.747499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 01:02:05.754375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 01:02:05.757592 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 01:02:05.760833 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 01:02:05.767933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 01:02:05.768020 Total UI for P1: 0, mck2ui 16
6720 01:02:05.770887 best dqsien dly found for B0: ( 0, 14, 24)
6721 01:02:05.774096 Total UI for P1: 0, mck2ui 16
6722 01:02:05.777767 best dqsien dly found for B1: ( 0, 14, 24)
6723 01:02:05.780899 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6724 01:02:05.787553 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6725 01:02:05.787635
6726 01:02:05.790972 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6727 01:02:05.794254 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 01:02:05.797542 [Gating] SW calibration Done
6729 01:02:05.797624 ==
6730 01:02:05.800742 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 01:02:05.804254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 01:02:05.804378 ==
6733 01:02:05.807695 RX Vref Scan: 0
6734 01:02:05.807778
6735 01:02:05.807843 RX Vref 0 -> 0, step: 1
6736 01:02:05.807903
6737 01:02:05.810640 RX Delay -410 -> 252, step: 16
6738 01:02:05.817190 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6739 01:02:05.820902 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6740 01:02:05.824205 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6741 01:02:05.827398 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6742 01:02:05.830520 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6743 01:02:05.837373 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6744 01:02:05.840585 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6745 01:02:05.844152 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6746 01:02:05.847345 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6747 01:02:05.854007 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6748 01:02:05.857128 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6749 01:02:05.860411 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6750 01:02:05.867515 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6751 01:02:05.870780 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6752 01:02:05.873925 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6753 01:02:05.877087 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6754 01:02:05.877169 ==
6755 01:02:05.880170 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 01:02:05.886946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 01:02:05.887030 ==
6758 01:02:05.887095 DQS Delay:
6759 01:02:05.890095 DQS0 = 27, DQS1 = 27
6760 01:02:05.890178 DQM Delay:
6761 01:02:05.894169 DQM0 = 11, DQM1 = 8
6762 01:02:05.894251 DQ Delay:
6763 01:02:05.896741 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6764 01:02:05.900177 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6765 01:02:05.900262 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6766 01:02:05.903486 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6767 01:02:05.903569
6768 01:02:05.907077
6769 01:02:05.907158 ==
6770 01:02:05.910212 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 01:02:05.913673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 01:02:05.913757 ==
6773 01:02:05.913822
6774 01:02:05.913882
6775 01:02:05.916831 TX Vref Scan disable
6776 01:02:05.916931 == TX Byte 0 ==
6777 01:02:05.920132 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 01:02:05.926793 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 01:02:05.926875 == TX Byte 1 ==
6780 01:02:05.929959 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 01:02:05.936987 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 01:02:05.937069 ==
6783 01:02:05.940193 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 01:02:05.943488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 01:02:05.943570 ==
6786 01:02:05.943634
6787 01:02:05.943694
6788 01:02:05.946740 TX Vref Scan disable
6789 01:02:05.946822 == TX Byte 0 ==
6790 01:02:05.950253 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 01:02:05.957035 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 01:02:05.957117 == TX Byte 1 ==
6793 01:02:05.959991 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 01:02:05.966714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 01:02:05.966795
6796 01:02:05.966858 [DATLAT]
6797 01:02:05.966918 Freq=400, CH1 RK0
6798 01:02:05.966976
6799 01:02:05.969922 DATLAT Default: 0xf
6800 01:02:05.973096 0, 0xFFFF, sum = 0
6801 01:02:05.973179 1, 0xFFFF, sum = 0
6802 01:02:05.976900 2, 0xFFFF, sum = 0
6803 01:02:05.976982 3, 0xFFFF, sum = 0
6804 01:02:05.980077 4, 0xFFFF, sum = 0
6805 01:02:05.980160 5, 0xFFFF, sum = 0
6806 01:02:05.983218 6, 0xFFFF, sum = 0
6807 01:02:05.983301 7, 0xFFFF, sum = 0
6808 01:02:05.986840 8, 0xFFFF, sum = 0
6809 01:02:05.986923 9, 0xFFFF, sum = 0
6810 01:02:05.989961 10, 0xFFFF, sum = 0
6811 01:02:05.990044 11, 0xFFFF, sum = 0
6812 01:02:05.993074 12, 0xFFFF, sum = 0
6813 01:02:05.993184 13, 0x0, sum = 1
6814 01:02:05.996298 14, 0x0, sum = 2
6815 01:02:05.996385 15, 0x0, sum = 3
6816 01:02:06.000213 16, 0x0, sum = 4
6817 01:02:06.000355 best_step = 14
6818 01:02:06.000422
6819 01:02:06.000482 ==
6820 01:02:06.003472 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 01:02:06.006692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 01:02:06.009822 ==
6823 01:02:06.009904 RX Vref Scan: 1
6824 01:02:06.009968
6825 01:02:06.013086 RX Vref 0 -> 0, step: 1
6826 01:02:06.013167
6827 01:02:06.016793 RX Delay -295 -> 252, step: 8
6828 01:02:06.016874
6829 01:02:06.019746 Set Vref, RX VrefLevel [Byte0]: 53
6830 01:02:06.023052 [Byte1]: 53
6831 01:02:06.023134
6832 01:02:06.026542 Final RX Vref Byte 0 = 53 to rank0
6833 01:02:06.029512 Final RX Vref Byte 1 = 53 to rank0
6834 01:02:06.032788 Final RX Vref Byte 0 = 53 to rank1
6835 01:02:06.036656 Final RX Vref Byte 1 = 53 to rank1==
6836 01:02:06.039481 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 01:02:06.042837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 01:02:06.042919 ==
6839 01:02:06.046588 DQS Delay:
6840 01:02:06.046670 DQS0 = 32, DQS1 = 32
6841 01:02:06.049753 DQM Delay:
6842 01:02:06.049837 DQM0 = 13, DQM1 = 11
6843 01:02:06.049903 DQ Delay:
6844 01:02:06.053101 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6845 01:02:06.056153 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6846 01:02:06.059304 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6847 01:02:06.063056 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
6848 01:02:06.063138
6849 01:02:06.063203
6850 01:02:06.072529 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ac3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6851 01:02:06.076148 CH1 RK0: MR19=C0C, MR18=8AC3
6852 01:02:06.079242 CH1_RK0: MR19=0xC0C, MR18=0x8AC3, DQSOSC=385, MR23=63, INC=398, DEC=265
6853 01:02:06.083164 ==
6854 01:02:06.086278 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 01:02:06.089410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 01:02:06.089494 ==
6857 01:02:06.092646 [Gating] SW mode calibration
6858 01:02:06.099455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6859 01:02:06.102839 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6860 01:02:06.109268 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6861 01:02:06.112508 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 01:02:06.115712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 01:02:06.122738 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 01:02:06.125796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 01:02:06.129405 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 01:02:06.135780 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 01:02:06.138935 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 01:02:06.142513 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 01:02:06.145797 Total UI for P1: 0, mck2ui 16
6870 01:02:06.149285 best dqsien dly found for B0: ( 0, 14, 24)
6871 01:02:06.152559 Total UI for P1: 0, mck2ui 16
6872 01:02:06.155710 best dqsien dly found for B1: ( 0, 14, 24)
6873 01:02:06.159229 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6874 01:02:06.162329 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6875 01:02:06.162411
6876 01:02:06.169089 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6877 01:02:06.172246 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 01:02:06.172369 [Gating] SW calibration Done
6879 01:02:06.175934 ==
6880 01:02:06.178933 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 01:02:06.182537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 01:02:06.182621 ==
6883 01:02:06.182686 RX Vref Scan: 0
6884 01:02:06.182747
6885 01:02:06.185525 RX Vref 0 -> 0, step: 1
6886 01:02:06.185607
6887 01:02:06.189161 RX Delay -410 -> 252, step: 16
6888 01:02:06.192239 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6889 01:02:06.195392 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6890 01:02:06.202282 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6891 01:02:06.205353 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6892 01:02:06.209274 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6893 01:02:06.212463 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6894 01:02:06.218923 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6895 01:02:06.222128 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6896 01:02:06.225243 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6897 01:02:06.229090 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6898 01:02:06.235265 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6899 01:02:06.238873 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6900 01:02:06.242084 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6901 01:02:06.245348 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6902 01:02:06.251988 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6903 01:02:06.255581 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6904 01:02:06.255664 ==
6905 01:02:06.258681 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 01:02:06.262325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 01:02:06.262408 ==
6908 01:02:06.265326 DQS Delay:
6909 01:02:06.265408 DQS0 = 35, DQS1 = 35
6910 01:02:06.268540 DQM Delay:
6911 01:02:06.268622 DQM0 = 19, DQM1 = 14
6912 01:02:06.268687 DQ Delay:
6913 01:02:06.272211 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6914 01:02:06.275455 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6915 01:02:06.278712 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6916 01:02:06.282020 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6917 01:02:06.282102
6918 01:02:06.282177
6919 01:02:06.282238 ==
6920 01:02:06.285450 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 01:02:06.292002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 01:02:06.292086 ==
6923 01:02:06.292151
6924 01:02:06.292211
6925 01:02:06.292268 TX Vref Scan disable
6926 01:02:06.295589 == TX Byte 0 ==
6927 01:02:06.298772 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6928 01:02:06.301928 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6929 01:02:06.305413 == TX Byte 1 ==
6930 01:02:06.308864 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6931 01:02:06.311677 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6932 01:02:06.311760 ==
6933 01:02:06.315157 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 01:02:06.321604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 01:02:06.321687 ==
6936 01:02:06.321753
6937 01:02:06.321814
6938 01:02:06.321872 TX Vref Scan disable
6939 01:02:06.325530 == TX Byte 0 ==
6940 01:02:06.328757 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6941 01:02:06.331932 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6942 01:02:06.335019 == TX Byte 1 ==
6943 01:02:06.338908 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6944 01:02:06.341852 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6945 01:02:06.341934
6946 01:02:06.344834 [DATLAT]
6947 01:02:06.344916 Freq=400, CH1 RK1
6948 01:02:06.344981
6949 01:02:06.348816 DATLAT Default: 0xe
6950 01:02:06.348897 0, 0xFFFF, sum = 0
6951 01:02:06.351987 1, 0xFFFF, sum = 0
6952 01:02:06.352070 2, 0xFFFF, sum = 0
6953 01:02:06.355124 3, 0xFFFF, sum = 0
6954 01:02:06.355207 4, 0xFFFF, sum = 0
6955 01:02:06.358178 5, 0xFFFF, sum = 0
6956 01:02:06.358261 6, 0xFFFF, sum = 0
6957 01:02:06.361731 7, 0xFFFF, sum = 0
6958 01:02:06.361814 8, 0xFFFF, sum = 0
6959 01:02:06.364924 9, 0xFFFF, sum = 0
6960 01:02:06.368584 10, 0xFFFF, sum = 0
6961 01:02:06.368667 11, 0xFFFF, sum = 0
6962 01:02:06.371662 12, 0xFFFF, sum = 0
6963 01:02:06.371745 13, 0x0, sum = 1
6964 01:02:06.374833 14, 0x0, sum = 2
6965 01:02:06.374916 15, 0x0, sum = 3
6966 01:02:06.374981 16, 0x0, sum = 4
6967 01:02:06.378110 best_step = 14
6968 01:02:06.378191
6969 01:02:06.378255 ==
6970 01:02:06.381990 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 01:02:06.385171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 01:02:06.385253 ==
6973 01:02:06.388330 RX Vref Scan: 0
6974 01:02:06.388412
6975 01:02:06.391544 RX Vref 0 -> 0, step: 1
6976 01:02:06.391625
6977 01:02:06.391689 RX Delay -311 -> 252, step: 8
6978 01:02:06.399775 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6979 01:02:06.403332 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6980 01:02:06.406462 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6981 01:02:06.409866 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6982 01:02:06.416833 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6983 01:02:06.419931 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6984 01:02:06.423394 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6985 01:02:06.426471 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6986 01:02:06.433011 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6987 01:02:06.436784 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6988 01:02:06.440069 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6989 01:02:06.443249 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6990 01:02:06.449991 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6991 01:02:06.453318 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6992 01:02:06.456526 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6993 01:02:06.460200 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6994 01:02:06.463380 ==
6995 01:02:06.466472 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 01:02:06.469536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 01:02:06.469616 ==
6998 01:02:06.469679 DQS Delay:
6999 01:02:06.473343 DQS0 = 28, DQS1 = 36
7000 01:02:06.473419 DQM Delay:
7001 01:02:06.476424 DQM0 = 10, DQM1 = 14
7002 01:02:06.476496 DQ Delay:
7003 01:02:06.479586 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7004 01:02:06.482905 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7005 01:02:06.486608 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7006 01:02:06.489938 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7007 01:02:06.490038
7008 01:02:06.490128
7009 01:02:06.496452 [DQSOSCAuto] RK1, (LSB)MR18= 0xc658, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7010 01:02:06.499567 CH1 RK1: MR19=C0C, MR18=C658
7011 01:02:06.506422 CH1_RK1: MR19=0xC0C, MR18=0xC658, DQSOSC=385, MR23=63, INC=398, DEC=265
7012 01:02:06.509346 [RxdqsGatingPostProcess] freq 400
7013 01:02:06.513090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7014 01:02:06.516199 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 01:02:06.519448 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 01:02:06.522643 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 01:02:06.526331 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 01:02:06.529391 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 01:02:06.532875 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 01:02:06.536192 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 01:02:06.539389 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 01:02:06.542569 Pre-setting of DQS Precalculation
7023 01:02:06.546298 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7024 01:02:06.556206 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7025 01:02:06.562556 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7026 01:02:06.562636
7027 01:02:06.562706
7028 01:02:06.566132 [Calibration Summary] 800 Mbps
7029 01:02:06.566231 CH 0, Rank 0
7030 01:02:06.569223 SW Impedance : PASS
7031 01:02:06.569325 DUTY Scan : NO K
7032 01:02:06.572851 ZQ Calibration : PASS
7033 01:02:06.575930 Jitter Meter : NO K
7034 01:02:06.576005 CBT Training : PASS
7035 01:02:06.579733 Write leveling : PASS
7036 01:02:06.582507 RX DQS gating : PASS
7037 01:02:06.582616 RX DQ/DQS(RDDQC) : PASS
7038 01:02:06.585887 TX DQ/DQS : PASS
7039 01:02:06.589634 RX DATLAT : PASS
7040 01:02:06.589735 RX DQ/DQS(Engine): PASS
7041 01:02:06.592857 TX OE : NO K
7042 01:02:06.592942 All Pass.
7043 01:02:06.593007
7044 01:02:06.595875 CH 0, Rank 1
7045 01:02:06.595956 SW Impedance : PASS
7046 01:02:06.599052 DUTY Scan : NO K
7047 01:02:06.602922 ZQ Calibration : PASS
7048 01:02:06.603003 Jitter Meter : NO K
7049 01:02:06.606075 CBT Training : PASS
7050 01:02:06.606158 Write leveling : NO K
7051 01:02:06.609200 RX DQS gating : PASS
7052 01:02:06.612872 RX DQ/DQS(RDDQC) : PASS
7053 01:02:06.612954 TX DQ/DQS : PASS
7054 01:02:06.615922 RX DATLAT : PASS
7055 01:02:06.619468 RX DQ/DQS(Engine): PASS
7056 01:02:06.619549 TX OE : NO K
7057 01:02:06.622904 All Pass.
7058 01:02:06.622986
7059 01:02:06.623050 CH 1, Rank 0
7060 01:02:06.626041 SW Impedance : PASS
7061 01:02:06.626154 DUTY Scan : NO K
7062 01:02:06.629293 ZQ Calibration : PASS
7063 01:02:06.632559 Jitter Meter : NO K
7064 01:02:06.632641 CBT Training : PASS
7065 01:02:06.635787 Write leveling : PASS
7066 01:02:06.638836 RX DQS gating : PASS
7067 01:02:06.638917 RX DQ/DQS(RDDQC) : PASS
7068 01:02:06.643003 TX DQ/DQS : PASS
7069 01:02:06.645846 RX DATLAT : PASS
7070 01:02:06.645928 RX DQ/DQS(Engine): PASS
7071 01:02:06.649102 TX OE : NO K
7072 01:02:06.649184 All Pass.
7073 01:02:06.649249
7074 01:02:06.652206 CH 1, Rank 1
7075 01:02:06.652297 SW Impedance : PASS
7076 01:02:06.655996 DUTY Scan : NO K
7077 01:02:06.658921 ZQ Calibration : PASS
7078 01:02:06.659002 Jitter Meter : NO K
7079 01:02:06.662158 CBT Training : PASS
7080 01:02:06.662239 Write leveling : NO K
7081 01:02:06.665790 RX DQS gating : PASS
7082 01:02:06.669083 RX DQ/DQS(RDDQC) : PASS
7083 01:02:06.669164 TX DQ/DQS : PASS
7084 01:02:06.672528 RX DATLAT : PASS
7085 01:02:06.675747 RX DQ/DQS(Engine): PASS
7086 01:02:06.675828 TX OE : NO K
7087 01:02:06.678982 All Pass.
7088 01:02:06.679063
7089 01:02:06.679127 DramC Write-DBI off
7090 01:02:06.682201 PER_BANK_REFRESH: Hybrid Mode
7091 01:02:06.682282 TX_TRACKING: ON
7092 01:02:06.692190 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7093 01:02:06.695886 [FAST_K] Save calibration result to emmc
7094 01:02:06.699058 dramc_set_vcore_voltage set vcore to 725000
7095 01:02:06.702177 Read voltage for 1600, 0
7096 01:02:06.702258 Vio18 = 0
7097 01:02:06.705379 Vcore = 725000
7098 01:02:06.705460 Vdram = 0
7099 01:02:06.705525 Vddq = 0
7100 01:02:06.709244 Vmddr = 0
7101 01:02:06.712480 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7102 01:02:06.718717 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7103 01:02:06.718799 MEM_TYPE=3, freq_sel=13
7104 01:02:06.722192 sv_algorithm_assistance_LP4_3733
7105 01:02:06.729049 ============ PULL DRAM RESETB DOWN ============
7106 01:02:06.732190 ========== PULL DRAM RESETB DOWN end =========
7107 01:02:06.735428 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7108 01:02:06.738775 ===================================
7109 01:02:06.741957 LPDDR4 DRAM CONFIGURATION
7110 01:02:06.745688 ===================================
7111 01:02:06.745770 EX_ROW_EN[0] = 0x0
7112 01:02:06.748743 EX_ROW_EN[1] = 0x0
7113 01:02:06.752155 LP4Y_EN = 0x0
7114 01:02:06.752262 WORK_FSP = 0x1
7115 01:02:06.755314 WL = 0x5
7116 01:02:06.755394 RL = 0x5
7117 01:02:06.758567 BL = 0x2
7118 01:02:06.758648 RPST = 0x0
7119 01:02:06.762460 RD_PRE = 0x0
7120 01:02:06.762542 WR_PRE = 0x1
7121 01:02:06.765666 WR_PST = 0x1
7122 01:02:06.765772 DBI_WR = 0x0
7123 01:02:06.768795 DBI_RD = 0x0
7124 01:02:06.768877 OTF = 0x1
7125 01:02:06.771866 ===================================
7126 01:02:06.775490 ===================================
7127 01:02:06.778965 ANA top config
7128 01:02:06.782057 ===================================
7129 01:02:06.782139 DLL_ASYNC_EN = 0
7130 01:02:06.785701 ALL_SLAVE_EN = 0
7131 01:02:06.788876 NEW_RANK_MODE = 1
7132 01:02:06.791934 DLL_IDLE_MODE = 1
7133 01:02:06.792016 LP45_APHY_COMB_EN = 1
7134 01:02:06.795823 TX_ODT_DIS = 0
7135 01:02:06.798777 NEW_8X_MODE = 1
7136 01:02:06.801885 ===================================
7137 01:02:06.805201 ===================================
7138 01:02:06.808734 data_rate = 3200
7139 01:02:06.811861 CKR = 1
7140 01:02:06.814976 DQ_P2S_RATIO = 8
7141 01:02:06.818412 ===================================
7142 01:02:06.818524 CA_P2S_RATIO = 8
7143 01:02:06.822140 DQ_CA_OPEN = 0
7144 01:02:06.825453 DQ_SEMI_OPEN = 0
7145 01:02:06.828738 CA_SEMI_OPEN = 0
7146 01:02:06.831672 CA_FULL_RATE = 0
7147 01:02:06.835380 DQ_CKDIV4_EN = 0
7148 01:02:06.835460 CA_CKDIV4_EN = 0
7149 01:02:06.838750 CA_PREDIV_EN = 0
7150 01:02:06.842113 PH8_DLY = 12
7151 01:02:06.845342 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7152 01:02:06.848495 DQ_AAMCK_DIV = 4
7153 01:02:06.851624 CA_AAMCK_DIV = 4
7154 01:02:06.851722 CA_ADMCK_DIV = 4
7155 01:02:06.855558 DQ_TRACK_CA_EN = 0
7156 01:02:06.858969 CA_PICK = 1600
7157 01:02:06.862286 CA_MCKIO = 1600
7158 01:02:06.865379 MCKIO_SEMI = 0
7159 01:02:06.868662 PLL_FREQ = 3068
7160 01:02:06.871736 DQ_UI_PI_RATIO = 32
7161 01:02:06.871818 CA_UI_PI_RATIO = 0
7162 01:02:06.874853 ===================================
7163 01:02:06.878072 ===================================
7164 01:02:06.881729 memory_type:LPDDR4
7165 01:02:06.884648 GP_NUM : 10
7166 01:02:06.884747 SRAM_EN : 1
7167 01:02:06.888089 MD32_EN : 0
7168 01:02:06.891758 ===================================
7169 01:02:06.895182 [ANA_INIT] >>>>>>>>>>>>>>
7170 01:02:06.898168 <<<<<< [CONFIGURE PHASE]: ANA_TX
7171 01:02:06.901388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7172 01:02:06.904561 ===================================
7173 01:02:06.904646 data_rate = 3200,PCW = 0X7600
7174 01:02:06.908526 ===================================
7175 01:02:06.914961 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7176 01:02:06.918179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7177 01:02:06.924568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 01:02:06.928043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7179 01:02:06.931334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7180 01:02:06.934566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7181 01:02:06.938197 [ANA_INIT] flow start
7182 01:02:06.941287 [ANA_INIT] PLL >>>>>>>>
7183 01:02:06.941364 [ANA_INIT] PLL <<<<<<<<
7184 01:02:06.944750 [ANA_INIT] MIDPI >>>>>>>>
7185 01:02:06.948169 [ANA_INIT] MIDPI <<<<<<<<
7186 01:02:06.948283 [ANA_INIT] DLL >>>>>>>>
7187 01:02:06.951325 [ANA_INIT] DLL <<<<<<<<
7188 01:02:06.955036 [ANA_INIT] flow end
7189 01:02:06.958240 ============ LP4 DIFF to SE enter ============
7190 01:02:06.961430 ============ LP4 DIFF to SE exit ============
7191 01:02:06.964581 [ANA_INIT] <<<<<<<<<<<<<
7192 01:02:06.967706 [Flow] Enable top DCM control >>>>>
7193 01:02:06.971610 [Flow] Enable top DCM control <<<<<
7194 01:02:06.974855 Enable DLL master slave shuffle
7195 01:02:06.977958 ==============================================================
7196 01:02:06.981041 Gating Mode config
7197 01:02:06.988122 ==============================================================
7198 01:02:06.988200 Config description:
7199 01:02:06.998105 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7200 01:02:07.004237 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7201 01:02:07.007540 SELPH_MODE 0: By rank 1: By Phase
7202 01:02:07.014462 ==============================================================
7203 01:02:07.017705 GAT_TRACK_EN = 1
7204 01:02:07.020911 RX_GATING_MODE = 2
7205 01:02:07.024295 RX_GATING_TRACK_MODE = 2
7206 01:02:07.027514 SELPH_MODE = 1
7207 01:02:07.031311 PICG_EARLY_EN = 1
7208 01:02:07.034533 VALID_LAT_VALUE = 1
7209 01:02:07.037847 ==============================================================
7210 01:02:07.040914 Enter into Gating configuration >>>>
7211 01:02:07.044515 Exit from Gating configuration <<<<
7212 01:02:07.047395 Enter into DVFS_PRE_config >>>>>
7213 01:02:07.057711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7214 01:02:07.060782 Exit from DVFS_PRE_config <<<<<
7215 01:02:07.064244 Enter into PICG configuration >>>>
7216 01:02:07.067475 Exit from PICG configuration <<<<
7217 01:02:07.070735 [RX_INPUT] configuration >>>>>
7218 01:02:07.074645 [RX_INPUT] configuration <<<<<
7219 01:02:07.080861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7220 01:02:07.084092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7221 01:02:07.091108 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 01:02:07.097305 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 01:02:07.104153 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7224 01:02:07.111169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7225 01:02:07.114216 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7226 01:02:07.117562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7227 01:02:07.120792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7228 01:02:07.127319 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7229 01:02:07.130762 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7230 01:02:07.133943 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7231 01:02:07.137634 ===================================
7232 01:02:07.140878 LPDDR4 DRAM CONFIGURATION
7233 01:02:07.144289 ===================================
7234 01:02:07.144404 EX_ROW_EN[0] = 0x0
7235 01:02:07.147660 EX_ROW_EN[1] = 0x0
7236 01:02:07.150844 LP4Y_EN = 0x0
7237 01:02:07.150942 WORK_FSP = 0x1
7238 01:02:07.153979 WL = 0x5
7239 01:02:07.154075 RL = 0x5
7240 01:02:07.157162 BL = 0x2
7241 01:02:07.157260 RPST = 0x0
7242 01:02:07.160493 RD_PRE = 0x0
7243 01:02:07.160590 WR_PRE = 0x1
7244 01:02:07.163684 WR_PST = 0x1
7245 01:02:07.163755 DBI_WR = 0x0
7246 01:02:07.167470 DBI_RD = 0x0
7247 01:02:07.167540 OTF = 0x1
7248 01:02:07.170531 ===================================
7249 01:02:07.173802 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7250 01:02:07.180650 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7251 01:02:07.183724 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 01:02:07.187074 ===================================
7253 01:02:07.190539 LPDDR4 DRAM CONFIGURATION
7254 01:02:07.193662 ===================================
7255 01:02:07.193744 EX_ROW_EN[0] = 0x10
7256 01:02:07.197038 EX_ROW_EN[1] = 0x0
7257 01:02:07.197119 LP4Y_EN = 0x0
7258 01:02:07.200459 WORK_FSP = 0x1
7259 01:02:07.200541 WL = 0x5
7260 01:02:07.203828 RL = 0x5
7261 01:02:07.203909 BL = 0x2
7262 01:02:07.207209 RPST = 0x0
7263 01:02:07.210602 RD_PRE = 0x0
7264 01:02:07.210694 WR_PRE = 0x1
7265 01:02:07.214141 WR_PST = 0x1
7266 01:02:07.214249 DBI_WR = 0x0
7267 01:02:07.217117 DBI_RD = 0x0
7268 01:02:07.217198 OTF = 0x1
7269 01:02:07.220336 ===================================
7270 01:02:07.227015 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7271 01:02:07.227097 ==
7272 01:02:07.230410 Dram Type= 6, Freq= 0, CH_0, rank 0
7273 01:02:07.233743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7274 01:02:07.233854 ==
7275 01:02:07.237204 [Duty_Offset_Calibration]
7276 01:02:07.237282 B0:2 B1:1 CA:1
7277 01:02:07.240734
7278 01:02:07.243771 [DutyScan_Calibration_Flow] k_type=0
7279 01:02:07.251827
7280 01:02:07.251901 ==CLK 0==
7281 01:02:07.255090 Final CLK duty delay cell = 0
7282 01:02:07.258345 [0] MAX Duty = 5156%(X100), DQS PI = 22
7283 01:02:07.261606 [0] MIN Duty = 4907%(X100), DQS PI = 0
7284 01:02:07.261678 [0] AVG Duty = 5031%(X100)
7285 01:02:07.265434
7286 01:02:07.268530 CH0 CLK Duty spec in!! Max-Min= 249%
7287 01:02:07.271529 [DutyScan_Calibration_Flow] ====Done====
7288 01:02:07.271596
7289 01:02:07.275324 [DutyScan_Calibration_Flow] k_type=1
7290 01:02:07.290998
7291 01:02:07.291101 ==DQS 0 ==
7292 01:02:07.294074 Final DQS duty delay cell = -4
7293 01:02:07.297989 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7294 01:02:07.301055 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7295 01:02:07.304647 [-4] AVG Duty = 4891%(X100)
7296 01:02:07.304735
7297 01:02:07.304802 ==DQS 1 ==
7298 01:02:07.307590 Final DQS duty delay cell = 0
7299 01:02:07.311086 [0] MAX Duty = 5187%(X100), DQS PI = 20
7300 01:02:07.314004 [0] MIN Duty = 5062%(X100), DQS PI = 30
7301 01:02:07.317385 [0] AVG Duty = 5124%(X100)
7302 01:02:07.317461
7303 01:02:07.320589 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7304 01:02:07.320687
7305 01:02:07.324303 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7306 01:02:07.327722 [DutyScan_Calibration_Flow] ====Done====
7307 01:02:07.327828
7308 01:02:07.330972 [DutyScan_Calibration_Flow] k_type=3
7309 01:02:07.348674
7310 01:02:07.348754 ==DQM 0 ==
7311 01:02:07.351825 Final DQM duty delay cell = 0
7312 01:02:07.355090 [0] MAX Duty = 5218%(X100), DQS PI = 32
7313 01:02:07.358851 [0] MIN Duty = 4907%(X100), DQS PI = 56
7314 01:02:07.362177 [0] AVG Duty = 5062%(X100)
7315 01:02:07.362252
7316 01:02:07.362338 ==DQM 1 ==
7317 01:02:07.365538 Final DQM duty delay cell = 0
7318 01:02:07.368558 [0] MAX Duty = 5187%(X100), DQS PI = 2
7319 01:02:07.371731 [0] MIN Duty = 5062%(X100), DQS PI = 14
7320 01:02:07.374878 [0] AVG Duty = 5124%(X100)
7321 01:02:07.374975
7322 01:02:07.378158 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7323 01:02:07.378263
7324 01:02:07.381251 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7325 01:02:07.385087 [DutyScan_Calibration_Flow] ====Done====
7326 01:02:07.385165
7327 01:02:07.388175 [DutyScan_Calibration_Flow] k_type=2
7328 01:02:07.405759
7329 01:02:07.405861 ==DQ 0 ==
7330 01:02:07.408728 Final DQ duty delay cell = 0
7331 01:02:07.411967 [0] MAX Duty = 5062%(X100), DQS PI = 24
7332 01:02:07.415746 [0] MIN Duty = 4907%(X100), DQS PI = 0
7333 01:02:07.415850 [0] AVG Duty = 4984%(X100)
7334 01:02:07.418820
7335 01:02:07.418905 ==DQ 1 ==
7336 01:02:07.421998 Final DQ duty delay cell = 0
7337 01:02:07.425719 [0] MAX Duty = 5125%(X100), DQS PI = 4
7338 01:02:07.428966 [0] MIN Duty = 4938%(X100), DQS PI = 34
7339 01:02:07.429038 [0] AVG Duty = 5031%(X100)
7340 01:02:07.429100
7341 01:02:07.432059 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7342 01:02:07.435654
7343 01:02:07.438964 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7344 01:02:07.441789 [DutyScan_Calibration_Flow] ====Done====
7345 01:02:07.441863 ==
7346 01:02:07.445305 Dram Type= 6, Freq= 0, CH_1, rank 0
7347 01:02:07.448786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7348 01:02:07.448861 ==
7349 01:02:07.452156 [Duty_Offset_Calibration]
7350 01:02:07.452251 B0:1 B1:0 CA:0
7351 01:02:07.452350
7352 01:02:07.455166 [DutyScan_Calibration_Flow] k_type=0
7353 01:02:07.464822
7354 01:02:07.464905 ==CLK 0==
7355 01:02:07.467975 Final CLK duty delay cell = -4
7356 01:02:07.471645 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7357 01:02:07.474906 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7358 01:02:07.477901 [-4] AVG Duty = 4922%(X100)
7359 01:02:07.477982
7360 01:02:07.481169 CH1 CLK Duty spec in!! Max-Min= 156%
7361 01:02:07.485186 [DutyScan_Calibration_Flow] ====Done====
7362 01:02:07.485267
7363 01:02:07.488469 [DutyScan_Calibration_Flow] k_type=1
7364 01:02:07.504890
7365 01:02:07.504970 ==DQS 0 ==
7366 01:02:07.508071 Final DQS duty delay cell = 0
7367 01:02:07.511265 [0] MAX Duty = 5094%(X100), DQS PI = 18
7368 01:02:07.515112 [0] MIN Duty = 4844%(X100), DQS PI = 44
7369 01:02:07.518370 [0] AVG Duty = 4969%(X100)
7370 01:02:07.518451
7371 01:02:07.518523 ==DQS 1 ==
7372 01:02:07.521514 Final DQS duty delay cell = 0
7373 01:02:07.524573 [0] MAX Duty = 5249%(X100), DQS PI = 18
7374 01:02:07.527795 [0] MIN Duty = 4969%(X100), DQS PI = 6
7375 01:02:07.531618 [0] AVG Duty = 5109%(X100)
7376 01:02:07.531700
7377 01:02:07.534905 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7378 01:02:07.534986
7379 01:02:07.538116 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7380 01:02:07.541216 [DutyScan_Calibration_Flow] ====Done====
7381 01:02:07.541297
7382 01:02:07.544792 [DutyScan_Calibration_Flow] k_type=3
7383 01:02:07.562055
7384 01:02:07.562136 ==DQM 0 ==
7385 01:02:07.565093 Final DQM duty delay cell = 0
7386 01:02:07.568204 [0] MAX Duty = 5187%(X100), DQS PI = 8
7387 01:02:07.571682 [0] MIN Duty = 4969%(X100), DQS PI = 48
7388 01:02:07.575332 [0] AVG Duty = 5078%(X100)
7389 01:02:07.575413
7390 01:02:07.575477 ==DQM 1 ==
7391 01:02:07.578734 Final DQM duty delay cell = 0
7392 01:02:07.581717 [0] MAX Duty = 5062%(X100), DQS PI = 16
7393 01:02:07.584795 [0] MIN Duty = 4907%(X100), DQS PI = 32
7394 01:02:07.588066 [0] AVG Duty = 4984%(X100)
7395 01:02:07.588141
7396 01:02:07.591440 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7397 01:02:07.591518
7398 01:02:07.595044 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7399 01:02:07.598499 [DutyScan_Calibration_Flow] ====Done====
7400 01:02:07.598578
7401 01:02:07.601329 [DutyScan_Calibration_Flow] k_type=2
7402 01:02:07.617755
7403 01:02:07.617837 ==DQ 0 ==
7404 01:02:07.620892 Final DQ duty delay cell = -4
7405 01:02:07.624721 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7406 01:02:07.627786 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7407 01:02:07.631367 [-4] AVG Duty = 4953%(X100)
7408 01:02:07.631448
7409 01:02:07.631512 ==DQ 1 ==
7410 01:02:07.634412 Final DQ duty delay cell = 0
7411 01:02:07.637639 [0] MAX Duty = 5125%(X100), DQS PI = 18
7412 01:02:07.640844 [0] MIN Duty = 4938%(X100), DQS PI = 8
7413 01:02:07.644588 [0] AVG Duty = 5031%(X100)
7414 01:02:07.644670
7415 01:02:07.647823 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7416 01:02:07.647905
7417 01:02:07.650885 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7418 01:02:07.653916 [DutyScan_Calibration_Flow] ====Done====
7419 01:02:07.657440 nWR fixed to 30
7420 01:02:07.660744 [ModeRegInit_LP4] CH0 RK0
7421 01:02:07.660825 [ModeRegInit_LP4] CH0 RK1
7422 01:02:07.664278 [ModeRegInit_LP4] CH1 RK0
7423 01:02:07.667672 [ModeRegInit_LP4] CH1 RK1
7424 01:02:07.667753 match AC timing 5
7425 01:02:07.674074 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7426 01:02:07.677210 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7427 01:02:07.680521 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7428 01:02:07.687047 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7429 01:02:07.690692 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7430 01:02:07.690774 [MiockJmeterHQA]
7431 01:02:07.690839
7432 01:02:07.693770 [DramcMiockJmeter] u1RxGatingPI = 0
7433 01:02:07.697545 0 : 4252, 4027
7434 01:02:07.697628 4 : 4255, 4030
7435 01:02:07.700298 8 : 4363, 4137
7436 01:02:07.700395 12 : 4253, 4027
7437 01:02:07.703801 16 : 4253, 4026
7438 01:02:07.703884 20 : 4363, 4137
7439 01:02:07.703950 24 : 4363, 4137
7440 01:02:07.706928 28 : 4252, 4027
7441 01:02:07.707010 32 : 4253, 4026
7442 01:02:07.710234 36 : 4250, 4027
7443 01:02:07.710316 40 : 4363, 4140
7444 01:02:07.713612 44 : 4250, 4027
7445 01:02:07.713696 48 : 4360, 4138
7446 01:02:07.716909 52 : 4253, 4026
7447 01:02:07.716992 56 : 4250, 4027
7448 01:02:07.717064 60 : 4250, 4027
7449 01:02:07.720560 64 : 4253, 4029
7450 01:02:07.720643 68 : 4250, 4027
7451 01:02:07.723558 72 : 4250, 4026
7452 01:02:07.723641 76 : 4363, 4140
7453 01:02:07.726854 80 : 4249, 4027
7454 01:02:07.726937 84 : 4253, 4028
7455 01:02:07.727002 88 : 4249, 84
7456 01:02:07.730211 92 : 4252, 0
7457 01:02:07.730294 96 : 4254, 0
7458 01:02:07.733651 100 : 4250, 0
7459 01:02:07.733734 104 : 4249, 0
7460 01:02:07.733800 108 : 4250, 0
7461 01:02:07.737175 112 : 4363, 0
7462 01:02:07.737258 116 : 4360, 0
7463 01:02:07.740176 120 : 4363, 0
7464 01:02:07.740258 124 : 4253, 0
7465 01:02:07.740335 128 : 4249, 0
7466 01:02:07.743762 132 : 4250, 0
7467 01:02:07.743874 136 : 4253, 0
7468 01:02:07.743970 140 : 4250, 0
7469 01:02:07.746927 144 : 4249, 0
7470 01:02:07.747038 148 : 4253, 0
7471 01:02:07.750066 152 : 4360, 0
7472 01:02:07.750148 156 : 4250, 0
7473 01:02:07.750227 160 : 4250, 0
7474 01:02:07.753374 164 : 4250, 0
7475 01:02:07.753457 168 : 4360, 0
7476 01:02:07.757174 172 : 4361, 0
7477 01:02:07.757277 176 : 4250, 0
7478 01:02:07.757373 180 : 4252, 0
7479 01:02:07.760361 184 : 4250, 0
7480 01:02:07.760470 188 : 4253, 0
7481 01:02:07.763563 192 : 4249, 0
7482 01:02:07.763636 196 : 4250, 0
7483 01:02:07.763715 200 : 4253, 0
7484 01:02:07.767163 204 : 4250, 1361
7485 01:02:07.767233 208 : 4250, 4013
7486 01:02:07.770038 212 : 4361, 4137
7487 01:02:07.770109 216 : 4250, 4027
7488 01:02:07.773474 220 : 4250, 4027
7489 01:02:07.773557 224 : 4250, 4026
7490 01:02:07.776957 228 : 4253, 4029
7491 01:02:07.777041 232 : 4250, 4027
7492 01:02:07.780254 236 : 4249, 4027
7493 01:02:07.780360 240 : 4250, 4026
7494 01:02:07.780427 244 : 4253, 4029
7495 01:02:07.783315 248 : 4249, 4027
7496 01:02:07.783398 252 : 4360, 4137
7497 01:02:07.786624 256 : 4360, 4137
7498 01:02:07.786707 260 : 4247, 4025
7499 01:02:07.789760 264 : 4363, 4140
7500 01:02:07.789842 268 : 4360, 4137
7501 01:02:07.793623 272 : 4249, 4027
7502 01:02:07.793706 276 : 4250, 4026
7503 01:02:07.796942 280 : 4253, 4029
7504 01:02:07.797025 284 : 4249, 4027
7505 01:02:07.800113 288 : 4249, 4027
7506 01:02:07.800195 292 : 4250, 4026
7507 01:02:07.803315 296 : 4252, 4030
7508 01:02:07.803397 300 : 4249, 4027
7509 01:02:07.803463 304 : 4360, 4137
7510 01:02:07.806579 308 : 4360, 4016
7511 01:02:07.806662 312 : 4250, 1848
7512 01:02:07.806729
7513 01:02:07.809885 MIOCK jitter meter ch=0
7514 01:02:07.809968
7515 01:02:07.813159 1T = (312-88) = 224 dly cells
7516 01:02:07.820000 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7517 01:02:07.820083 ==
7518 01:02:07.823110 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 01:02:07.826126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 01:02:07.826209 ==
7521 01:02:07.832685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7522 01:02:07.836186 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7523 01:02:07.839196 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7524 01:02:07.846080 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7525 01:02:07.855550 [CA 0] Center 43 (12~74) winsize 63
7526 01:02:07.858805 [CA 1] Center 43 (12~74) winsize 63
7527 01:02:07.861964 [CA 2] Center 38 (9~68) winsize 60
7528 01:02:07.865239 [CA 3] Center 38 (8~68) winsize 61
7529 01:02:07.868811 [CA 4] Center 37 (7~67) winsize 61
7530 01:02:07.872053 [CA 5] Center 36 (7~65) winsize 59
7531 01:02:07.872154
7532 01:02:07.875061 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7533 01:02:07.875167
7534 01:02:07.878652 [CATrainingPosCal] consider 1 rank data
7535 01:02:07.881939 u2DelayCellTimex100 = 290/100 ps
7536 01:02:07.888542 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7537 01:02:07.891721 CA1 delay=43 (12~74),Diff = 7 PI (23 cell)
7538 01:02:07.895528 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7539 01:02:07.898693 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7540 01:02:07.901826 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7541 01:02:07.905040 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7542 01:02:07.905110
7543 01:02:07.908881 CA PerBit enable=1, Macro0, CA PI delay=36
7544 01:02:07.908947
7545 01:02:07.912056 [CBTSetCACLKResult] CA Dly = 36
7546 01:02:07.915320 CS Dly: 9 (0~40)
7547 01:02:07.918604 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7548 01:02:07.921671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7549 01:02:07.921746 ==
7550 01:02:07.924987 Dram Type= 6, Freq= 0, CH_0, rank 1
7551 01:02:07.928212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 01:02:07.931536 ==
7553 01:02:07.935201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 01:02:07.938267 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 01:02:07.944701 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 01:02:07.948511 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 01:02:07.958520 [CA 0] Center 43 (13~73) winsize 61
7558 01:02:07.962063 [CA 1] Center 43 (13~73) winsize 61
7559 01:02:07.965413 [CA 2] Center 38 (8~68) winsize 61
7560 01:02:07.968916 [CA 3] Center 38 (8~68) winsize 61
7561 01:02:07.972163 [CA 4] Center 36 (6~66) winsize 61
7562 01:02:07.975236 [CA 5] Center 35 (6~65) winsize 60
7563 01:02:07.975306
7564 01:02:07.978466 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7565 01:02:07.978548
7566 01:02:07.981579 [CATrainingPosCal] consider 2 rank data
7567 01:02:07.985039 u2DelayCellTimex100 = 290/100 ps
7568 01:02:07.988233 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7569 01:02:07.995458 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7570 01:02:07.998085 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7571 01:02:08.001503 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7572 01:02:08.004972 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7573 01:02:08.008417 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7574 01:02:08.008494
7575 01:02:08.011590 CA PerBit enable=1, Macro0, CA PI delay=36
7576 01:02:08.011698
7577 01:02:08.014970 [CBTSetCACLKResult] CA Dly = 36
7578 01:02:08.018536 CS Dly: 10 (0~42)
7579 01:02:08.022020 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 01:02:08.025126 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 01:02:08.025208
7582 01:02:08.028280 ----->DramcWriteLeveling(PI) begin...
7583 01:02:08.028402 ==
7584 01:02:08.031585 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 01:02:08.037974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 01:02:08.038053 ==
7587 01:02:08.041582 Write leveling (Byte 0): 36 => 36
7588 01:02:08.041664 Write leveling (Byte 1): 29 => 29
7589 01:02:08.044826 DramcWriteLeveling(PI) end<-----
7590 01:02:08.044908
7591 01:02:08.044972 ==
7592 01:02:08.047908 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 01:02:08.054675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 01:02:08.054758 ==
7595 01:02:08.058082 [Gating] SW mode calibration
7596 01:02:08.064914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7597 01:02:08.068129 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7598 01:02:08.074741 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 01:02:08.077947 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7600 01:02:08.081278 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7601 01:02:08.087649 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7602 01:02:08.091109 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7603 01:02:08.094518 1 4 20 | B1->B0 | 3434 3535 | 0 1 | (0 0) (1 1)
7604 01:02:08.101376 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7605 01:02:08.104786 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7606 01:02:08.107694 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7607 01:02:08.114532 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7608 01:02:08.117611 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7609 01:02:08.121250 1 5 12 | B1->B0 | 3434 2625 | 1 1 | (1 1) (1 0)
7610 01:02:08.124345 1 5 16 | B1->B0 | 3434 2727 | 0 0 | (0 1) (0 0)
7611 01:02:08.131093 1 5 20 | B1->B0 | 2626 2424 | 0 0 | (1 0) (0 0)
7612 01:02:08.134453 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7613 01:02:08.137653 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 01:02:08.144238 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7615 01:02:08.147768 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7616 01:02:08.151234 1 6 8 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7617 01:02:08.157681 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7618 01:02:08.160850 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7619 01:02:08.164617 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 01:02:08.170956 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 01:02:08.174750 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 01:02:08.177836 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 01:02:08.184196 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 01:02:08.187517 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 01:02:08.191487 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 01:02:08.197729 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7627 01:02:08.201139 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7628 01:02:08.204242 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 01:02:08.210858 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 01:02:08.214107 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 01:02:08.217745 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 01:02:08.224597 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 01:02:08.227525 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 01:02:08.230801 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 01:02:08.234078 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 01:02:08.241064 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 01:02:08.244096 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 01:02:08.247638 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 01:02:08.254071 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 01:02:08.257214 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 01:02:08.260455 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 01:02:08.267460 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7643 01:02:08.270576 Total UI for P1: 0, mck2ui 16
7644 01:02:08.273923 best dqsien dly found for B0: ( 1, 9, 12)
7645 01:02:08.277616 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 01:02:08.280671 Total UI for P1: 0, mck2ui 16
7647 01:02:08.283840 best dqsien dly found for B1: ( 1, 9, 18)
7648 01:02:08.287091 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7649 01:02:08.290307 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7650 01:02:08.290389
7651 01:02:08.294183 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7652 01:02:08.300552 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7653 01:02:08.300664 [Gating] SW calibration Done
7654 01:02:08.300758 ==
7655 01:02:08.303800 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 01:02:08.310268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 01:02:08.310344 ==
7658 01:02:08.310407 RX Vref Scan: 0
7659 01:02:08.310466
7660 01:02:08.313989 RX Vref 0 -> 0, step: 1
7661 01:02:08.314093
7662 01:02:08.317200 RX Delay 0 -> 252, step: 8
7663 01:02:08.320420 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7664 01:02:08.323471 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7665 01:02:08.327104 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7666 01:02:08.330035 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7667 01:02:08.336575 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7668 01:02:08.340193 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7669 01:02:08.343952 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7670 01:02:08.346897 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7671 01:02:08.350096 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7672 01:02:08.356599 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7673 01:02:08.360177 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7674 01:02:08.363466 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7675 01:02:08.366541 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7676 01:02:08.373310 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7677 01:02:08.376724 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7678 01:02:08.379734 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7679 01:02:08.379816 ==
7680 01:02:08.383100 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 01:02:08.386343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 01:02:08.386425 ==
7683 01:02:08.389785 DQS Delay:
7684 01:02:08.389869 DQS0 = 0, DQS1 = 0
7685 01:02:08.392913 DQM Delay:
7686 01:02:08.392994 DQM0 = 137, DQM1 = 131
7687 01:02:08.393057 DQ Delay:
7688 01:02:08.399423 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7689 01:02:08.402893 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7690 01:02:08.406102 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7691 01:02:08.409318 DQ12 =139, DQ13 =139, DQ14 =143, DQ15 =135
7692 01:02:08.409399
7693 01:02:08.409463
7694 01:02:08.409522 ==
7695 01:02:08.413183 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 01:02:08.416211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 01:02:08.416329 ==
7698 01:02:08.416395
7699 01:02:08.416454
7700 01:02:08.419456 TX Vref Scan disable
7701 01:02:08.422527 == TX Byte 0 ==
7702 01:02:08.426263 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7703 01:02:08.429450 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7704 01:02:08.432747 == TX Byte 1 ==
7705 01:02:08.435909 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7706 01:02:08.439540 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7707 01:02:08.439621 ==
7708 01:02:08.442592 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 01:02:08.449262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 01:02:08.449349 ==
7711 01:02:08.460317
7712 01:02:08.463498 TX Vref early break, caculate TX vref
7713 01:02:08.466633 TX Vref=16, minBit 4, minWin=22, winSum=376
7714 01:02:08.469822 TX Vref=18, minBit 3, minWin=22, winSum=387
7715 01:02:08.473109 TX Vref=20, minBit 0, minWin=24, winSum=397
7716 01:02:08.476771 TX Vref=22, minBit 1, minWin=24, winSum=407
7717 01:02:08.479959 TX Vref=24, minBit 0, minWin=25, winSum=413
7718 01:02:08.486494 TX Vref=26, minBit 6, minWin=25, winSum=425
7719 01:02:08.489726 TX Vref=28, minBit 8, minWin=25, winSum=425
7720 01:02:08.493536 TX Vref=30, minBit 0, minWin=24, winSum=413
7721 01:02:08.496837 TX Vref=32, minBit 7, minWin=23, winSum=399
7722 01:02:08.503127 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 26
7723 01:02:08.503210
7724 01:02:08.506772 Final TX Range 0 Vref 26
7725 01:02:08.506889
7726 01:02:08.506954 ==
7727 01:02:08.510111 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 01:02:08.513305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 01:02:08.513388 ==
7730 01:02:08.513453
7731 01:02:08.513513
7732 01:02:08.516358 TX Vref Scan disable
7733 01:02:08.519963 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7734 01:02:08.523318 == TX Byte 0 ==
7735 01:02:08.526780 u2DelayCellOfst[0]=10 cells (3 PI)
7736 01:02:08.530323 u2DelayCellOfst[1]=13 cells (4 PI)
7737 01:02:08.533620 u2DelayCellOfst[2]=10 cells (3 PI)
7738 01:02:08.536858 u2DelayCellOfst[3]=6 cells (2 PI)
7739 01:02:08.536940 u2DelayCellOfst[4]=6 cells (2 PI)
7740 01:02:08.540067 u2DelayCellOfst[5]=0 cells (0 PI)
7741 01:02:08.543326 u2DelayCellOfst[6]=16 cells (5 PI)
7742 01:02:08.546422 u2DelayCellOfst[7]=13 cells (4 PI)
7743 01:02:08.553412 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7744 01:02:08.556393 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7745 01:02:08.556475 == TX Byte 1 ==
7746 01:02:08.559702 u2DelayCellOfst[8]=0 cells (0 PI)
7747 01:02:08.563330 u2DelayCellOfst[9]=0 cells (0 PI)
7748 01:02:08.566231 u2DelayCellOfst[10]=10 cells (3 PI)
7749 01:02:08.569480 u2DelayCellOfst[11]=3 cells (1 PI)
7750 01:02:08.573177 u2DelayCellOfst[12]=10 cells (3 PI)
7751 01:02:08.576307 u2DelayCellOfst[13]=13 cells (4 PI)
7752 01:02:08.579413 u2DelayCellOfst[14]=16 cells (5 PI)
7753 01:02:08.582999 u2DelayCellOfst[15]=10 cells (3 PI)
7754 01:02:08.586086 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7755 01:02:08.589710 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7756 01:02:08.592613 DramC Write-DBI on
7757 01:02:08.592694 ==
7758 01:02:08.596332 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 01:02:08.599446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 01:02:08.599529 ==
7761 01:02:08.599595
7762 01:02:08.599655
7763 01:02:08.602584 TX Vref Scan disable
7764 01:02:08.606358 == TX Byte 0 ==
7765 01:02:08.609562 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7766 01:02:08.612870 == TX Byte 1 ==
7767 01:02:08.616225 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7768 01:02:08.616346 DramC Write-DBI off
7769 01:02:08.616439
7770 01:02:08.619511 [DATLAT]
7771 01:02:08.619588 Freq=1600, CH0 RK0
7772 01:02:08.619652
7773 01:02:08.622582 DATLAT Default: 0xf
7774 01:02:08.622681 0, 0xFFFF, sum = 0
7775 01:02:08.626042 1, 0xFFFF, sum = 0
7776 01:02:08.626142 2, 0xFFFF, sum = 0
7777 01:02:08.629672 3, 0xFFFF, sum = 0
7778 01:02:08.629775 4, 0xFFFF, sum = 0
7779 01:02:08.633327 5, 0xFFFF, sum = 0
7780 01:02:08.633399 6, 0xFFFF, sum = 0
7781 01:02:08.635967 7, 0xFFFF, sum = 0
7782 01:02:08.636065 8, 0xFFFF, sum = 0
7783 01:02:08.639163 9, 0xFFFF, sum = 0
7784 01:02:08.642915 10, 0xFFFF, sum = 0
7785 01:02:08.642988 11, 0xFFFF, sum = 0
7786 01:02:08.645630 12, 0xFFFF, sum = 0
7787 01:02:08.645713 13, 0xFFFF, sum = 0
7788 01:02:08.649213 14, 0x0, sum = 1
7789 01:02:08.649301 15, 0x0, sum = 2
7790 01:02:08.652893 16, 0x0, sum = 3
7791 01:02:08.652977 17, 0x0, sum = 4
7792 01:02:08.653043 best_step = 15
7793 01:02:08.656108
7794 01:02:08.656205 ==
7795 01:02:08.659188 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 01:02:08.662314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 01:02:08.662389 ==
7798 01:02:08.662450 RX Vref Scan: 1
7799 01:02:08.662508
7800 01:02:08.666231 Set Vref Range= 24 -> 127
7801 01:02:08.666304
7802 01:02:08.668886 RX Vref 24 -> 127, step: 1
7803 01:02:08.668957
7804 01:02:08.672702 RX Delay 27 -> 252, step: 4
7805 01:02:08.672772
7806 01:02:08.675742 Set Vref, RX VrefLevel [Byte0]: 24
7807 01:02:08.679003 [Byte1]: 24
7808 01:02:08.679091
7809 01:02:08.682230 Set Vref, RX VrefLevel [Byte0]: 25
7810 01:02:08.685769 [Byte1]: 25
7811 01:02:08.685841
7812 01:02:08.689236 Set Vref, RX VrefLevel [Byte0]: 26
7813 01:02:08.692653 [Byte1]: 26
7814 01:02:08.695818
7815 01:02:08.695922 Set Vref, RX VrefLevel [Byte0]: 27
7816 01:02:08.699311 [Byte1]: 27
7817 01:02:08.703300
7818 01:02:08.703376 Set Vref, RX VrefLevel [Byte0]: 28
7819 01:02:08.706703 [Byte1]: 28
7820 01:02:08.710906
7821 01:02:08.710979 Set Vref, RX VrefLevel [Byte0]: 29
7822 01:02:08.714139 [Byte1]: 29
7823 01:02:08.718660
7824 01:02:08.718772 Set Vref, RX VrefLevel [Byte0]: 30
7825 01:02:08.721835 [Byte1]: 30
7826 01:02:08.726402
7827 01:02:08.726483 Set Vref, RX VrefLevel [Byte0]: 31
7828 01:02:08.729533 [Byte1]: 31
7829 01:02:08.733358
7830 01:02:08.733440 Set Vref, RX VrefLevel [Byte0]: 32
7831 01:02:08.736555 [Byte1]: 32
7832 01:02:08.741046
7833 01:02:08.741128 Set Vref, RX VrefLevel [Byte0]: 33
7834 01:02:08.744639 [Byte1]: 33
7835 01:02:08.748692
7836 01:02:08.748775 Set Vref, RX VrefLevel [Byte0]: 34
7837 01:02:08.751848 [Byte1]: 34
7838 01:02:08.756091
7839 01:02:08.756172 Set Vref, RX VrefLevel [Byte0]: 35
7840 01:02:08.759311 [Byte1]: 35
7841 01:02:08.763625
7842 01:02:08.763706 Set Vref, RX VrefLevel [Byte0]: 36
7843 01:02:08.766931 [Byte1]: 36
7844 01:02:08.771306
7845 01:02:08.771387 Set Vref, RX VrefLevel [Byte0]: 37
7846 01:02:08.774349 [Byte1]: 37
7847 01:02:08.778766
7848 01:02:08.778847 Set Vref, RX VrefLevel [Byte0]: 38
7849 01:02:08.781971 [Byte1]: 38
7850 01:02:08.786461
7851 01:02:08.786563 Set Vref, RX VrefLevel [Byte0]: 39
7852 01:02:08.789737 [Byte1]: 39
7853 01:02:08.794093
7854 01:02:08.794175 Set Vref, RX VrefLevel [Byte0]: 40
7855 01:02:08.797258 [Byte1]: 40
7856 01:02:08.801050
7857 01:02:08.801155 Set Vref, RX VrefLevel [Byte0]: 41
7858 01:02:08.804758 [Byte1]: 41
7859 01:02:08.809086
7860 01:02:08.809168 Set Vref, RX VrefLevel [Byte0]: 42
7861 01:02:08.811960 [Byte1]: 42
7862 01:02:08.816414
7863 01:02:08.816559 Set Vref, RX VrefLevel [Byte0]: 43
7864 01:02:08.819597 [Byte1]: 43
7865 01:02:08.823650
7866 01:02:08.823731 Set Vref, RX VrefLevel [Byte0]: 44
7867 01:02:08.827103 [Byte1]: 44
7868 01:02:08.831179
7869 01:02:08.831260 Set Vref, RX VrefLevel [Byte0]: 45
7870 01:02:08.835086 [Byte1]: 45
7871 01:02:08.838860
7872 01:02:08.838941 Set Vref, RX VrefLevel [Byte0]: 46
7873 01:02:08.842017 [Byte1]: 46
7874 01:02:08.846457
7875 01:02:08.846537 Set Vref, RX VrefLevel [Byte0]: 47
7876 01:02:08.849742 [Byte1]: 47
7877 01:02:08.854078
7878 01:02:08.854159 Set Vref, RX VrefLevel [Byte0]: 48
7879 01:02:08.857193 [Byte1]: 48
7880 01:02:08.861312
7881 01:02:08.861396 Set Vref, RX VrefLevel [Byte0]: 49
7882 01:02:08.865104 [Byte1]: 49
7883 01:02:08.868825
7884 01:02:08.868906 Set Vref, RX VrefLevel [Byte0]: 50
7885 01:02:08.872324 [Byte1]: 50
7886 01:02:08.876465
7887 01:02:08.876546 Set Vref, RX VrefLevel [Byte0]: 51
7888 01:02:08.879958 [Byte1]: 51
7889 01:02:08.883902
7890 01:02:08.883983 Set Vref, RX VrefLevel [Byte0]: 52
7891 01:02:08.887116 [Byte1]: 52
7892 01:02:08.891861
7893 01:02:08.891958 Set Vref, RX VrefLevel [Byte0]: 53
7894 01:02:08.895140 [Byte1]: 53
7895 01:02:08.899121
7896 01:02:08.899220 Set Vref, RX VrefLevel [Byte0]: 54
7897 01:02:08.902307 [Byte1]: 54
7898 01:02:08.906691
7899 01:02:08.906775 Set Vref, RX VrefLevel [Byte0]: 55
7900 01:02:08.909858 [Byte1]: 55
7901 01:02:08.914263
7902 01:02:08.914359 Set Vref, RX VrefLevel [Byte0]: 56
7903 01:02:08.917436 [Byte1]: 56
7904 01:02:08.921727
7905 01:02:08.921829 Set Vref, RX VrefLevel [Byte0]: 57
7906 01:02:08.924789 [Byte1]: 57
7907 01:02:08.929203
7908 01:02:08.929276 Set Vref, RX VrefLevel [Byte0]: 58
7909 01:02:08.932825 [Byte1]: 58
7910 01:02:08.936674
7911 01:02:08.936741 Set Vref, RX VrefLevel [Byte0]: 59
7912 01:02:08.940047 [Byte1]: 59
7913 01:02:08.944383
7914 01:02:08.944454 Set Vref, RX VrefLevel [Byte0]: 60
7915 01:02:08.947568 [Byte1]: 60
7916 01:02:08.952048
7917 01:02:08.952144 Set Vref, RX VrefLevel [Byte0]: 61
7918 01:02:08.955402 [Byte1]: 61
7919 01:02:08.959184
7920 01:02:08.959284 Set Vref, RX VrefLevel [Byte0]: 62
7921 01:02:08.962874 [Byte1]: 62
7922 01:02:08.967078
7923 01:02:08.967161 Set Vref, RX VrefLevel [Byte0]: 63
7924 01:02:08.970367 [Byte1]: 63
7925 01:02:08.974532
7926 01:02:08.974614 Set Vref, RX VrefLevel [Byte0]: 64
7927 01:02:08.977550 [Byte1]: 64
7928 01:02:08.981947
7929 01:02:08.982028 Set Vref, RX VrefLevel [Byte0]: 65
7930 01:02:08.985076 [Byte1]: 65
7931 01:02:08.989427
7932 01:02:08.989508 Set Vref, RX VrefLevel [Byte0]: 66
7933 01:02:08.993016 [Byte1]: 66
7934 01:02:08.996925
7935 01:02:08.997006 Set Vref, RX VrefLevel [Byte0]: 67
7936 01:02:09.000564 [Byte1]: 67
7937 01:02:09.004883
7938 01:02:09.004964 Set Vref, RX VrefLevel [Byte0]: 68
7939 01:02:09.008031 [Byte1]: 68
7940 01:02:09.011934
7941 01:02:09.012016 Set Vref, RX VrefLevel [Byte0]: 69
7942 01:02:09.015750 [Byte1]: 69
7943 01:02:09.019818
7944 01:02:09.019900 Set Vref, RX VrefLevel [Byte0]: 70
7945 01:02:09.023420 [Byte1]: 70
7946 01:02:09.027075
7947 01:02:09.027157 Set Vref, RX VrefLevel [Byte0]: 71
7948 01:02:09.030870 [Byte1]: 71
7949 01:02:09.034672
7950 01:02:09.034753 Set Vref, RX VrefLevel [Byte0]: 72
7951 01:02:09.037897 [Byte1]: 72
7952 01:02:09.042485
7953 01:02:09.042567 Set Vref, RX VrefLevel [Byte0]: 73
7954 01:02:09.045721 [Byte1]: 73
7955 01:02:09.050141
7956 01:02:09.050222 Final RX Vref Byte 0 = 56 to rank0
7957 01:02:09.053100 Final RX Vref Byte 1 = 58 to rank0
7958 01:02:09.056607 Final RX Vref Byte 0 = 56 to rank1
7959 01:02:09.060029 Final RX Vref Byte 1 = 58 to rank1==
7960 01:02:09.063318 Dram Type= 6, Freq= 0, CH_0, rank 0
7961 01:02:09.069940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 01:02:09.070022 ==
7963 01:02:09.070088 DQS Delay:
7964 01:02:09.070149 DQS0 = 0, DQS1 = 0
7965 01:02:09.073061 DQM Delay:
7966 01:02:09.073142 DQM0 = 133, DQM1 = 128
7967 01:02:09.076700 DQ Delay:
7968 01:02:09.079813 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7969 01:02:09.082858 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7970 01:02:09.086744 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =120
7971 01:02:09.089490 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7972 01:02:09.089597
7973 01:02:09.089691
7974 01:02:09.089765
7975 01:02:09.092940 [DramC_TX_OE_Calibration] TA2
7976 01:02:09.096708 Original DQ_B0 (3 6) =30, OEN = 27
7977 01:02:09.099824 Original DQ_B1 (3 6) =30, OEN = 27
7978 01:02:09.102937 24, 0x0, End_B0=24 End_B1=24
7979 01:02:09.103020 25, 0x0, End_B0=25 End_B1=25
7980 01:02:09.106841 26, 0x0, End_B0=26 End_B1=26
7981 01:02:09.109822 27, 0x0, End_B0=27 End_B1=27
7982 01:02:09.113363 28, 0x0, End_B0=28 End_B1=28
7983 01:02:09.113466 29, 0x0, End_B0=29 End_B1=29
7984 01:02:09.116618 30, 0x0, End_B0=30 End_B1=30
7985 01:02:09.119745 31, 0x4141, End_B0=30 End_B1=30
7986 01:02:09.122942 Byte0 end_step=30 best_step=27
7987 01:02:09.126776 Byte1 end_step=30 best_step=27
7988 01:02:09.129869 Byte0 TX OE(2T, 0.5T) = (3, 3)
7989 01:02:09.129972 Byte1 TX OE(2T, 0.5T) = (3, 3)
7990 01:02:09.130064
7991 01:02:09.132955
7992 01:02:09.139838 [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7993 01:02:09.142926 CH0 RK0: MR19=303, MR18=2520
7994 01:02:09.149353 CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16
7995 01:02:09.149436
7996 01:02:09.152598 ----->DramcWriteLeveling(PI) begin...
7997 01:02:09.152682 ==
7998 01:02:09.156473 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 01:02:09.159622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 01:02:09.159708 ==
8001 01:02:09.162697 Write leveling (Byte 0): 34 => 34
8002 01:02:09.166593 Write leveling (Byte 1): 28 => 28
8003 01:02:09.169373 DramcWriteLeveling(PI) end<-----
8004 01:02:09.169455
8005 01:02:09.169520 ==
8006 01:02:09.172901 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 01:02:09.175810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 01:02:09.175917 ==
8009 01:02:09.179414 [Gating] SW mode calibration
8010 01:02:09.186109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8011 01:02:09.192998 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8012 01:02:09.196202 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 01:02:09.199014 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 01:02:09.205642 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8015 01:02:09.209205 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8016 01:02:09.212694 1 4 16 | B1->B0 | 2d2d 3737 | 1 0 | (1 1) (0 0)
8017 01:02:09.219169 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8018 01:02:09.222475 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
8019 01:02:09.225589 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
8020 01:02:09.232178 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8021 01:02:09.235886 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8022 01:02:09.238999 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8023 01:02:09.245818 1 5 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8024 01:02:09.249001 1 5 16 | B1->B0 | 2c2c 2c2c | 1 1 | (1 0) (1 0)
8025 01:02:09.252168 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8026 01:02:09.258746 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8027 01:02:09.262453 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8028 01:02:09.265618 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8029 01:02:09.271938 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8030 01:02:09.275660 1 6 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8031 01:02:09.278715 1 6 12 | B1->B0 | 2424 3635 | 0 1 | (0 0) (0 0)
8032 01:02:09.285595 1 6 16 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8033 01:02:09.288632 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8034 01:02:09.292192 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 01:02:09.299042 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 01:02:09.302038 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 01:02:09.305193 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 01:02:09.311880 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 01:02:09.315268 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8040 01:02:09.318662 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8041 01:02:09.325503 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 01:02:09.328485 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 01:02:09.331980 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 01:02:09.335399 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 01:02:09.342223 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 01:02:09.345276 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 01:02:09.348899 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 01:02:09.355119 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 01:02:09.358378 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 01:02:09.362163 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 01:02:09.368600 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 01:02:09.371913 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 01:02:09.375190 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 01:02:09.381551 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 01:02:09.385330 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8056 01:02:09.388640 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8057 01:02:09.395084 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 01:02:09.398342 Total UI for P1: 0, mck2ui 16
8059 01:02:09.401481 best dqsien dly found for B0: ( 1, 9, 14)
8060 01:02:09.401564 Total UI for P1: 0, mck2ui 16
8061 01:02:09.408199 best dqsien dly found for B1: ( 1, 9, 14)
8062 01:02:09.411782 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8063 01:02:09.415271 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8064 01:02:09.415354
8065 01:02:09.418561 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8066 01:02:09.421586 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8067 01:02:09.424710 [Gating] SW calibration Done
8068 01:02:09.424792 ==
8069 01:02:09.428337 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 01:02:09.431372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 01:02:09.431455 ==
8072 01:02:09.434741 RX Vref Scan: 0
8073 01:02:09.434823
8074 01:02:09.434888 RX Vref 0 -> 0, step: 1
8075 01:02:09.434962
8076 01:02:09.438294 RX Delay 0 -> 252, step: 8
8077 01:02:09.441932 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8078 01:02:09.448200 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8079 01:02:09.451831 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8080 01:02:09.454980 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8081 01:02:09.458023 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8082 01:02:09.461280 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8083 01:02:09.468356 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8084 01:02:09.471582 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8085 01:02:09.474829 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8086 01:02:09.478106 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8087 01:02:09.481744 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8088 01:02:09.487929 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8089 01:02:09.491683 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8090 01:02:09.494862 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8091 01:02:09.498192 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8092 01:02:09.501449 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8093 01:02:09.504714 ==
8094 01:02:09.507846 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 01:02:09.511584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 01:02:09.511666 ==
8097 01:02:09.511731 DQS Delay:
8098 01:02:09.514887 DQS0 = 0, DQS1 = 0
8099 01:02:09.514970 DQM Delay:
8100 01:02:09.518372 DQM0 = 137, DQM1 = 129
8101 01:02:09.518454 DQ Delay:
8102 01:02:09.521114 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8103 01:02:09.524961 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8104 01:02:09.528123 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8105 01:02:09.531445 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8106 01:02:09.531527
8107 01:02:09.531592
8108 01:02:09.531651 ==
8109 01:02:09.534577 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 01:02:09.541462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 01:02:09.541546 ==
8112 01:02:09.541612
8113 01:02:09.541672
8114 01:02:09.541731 TX Vref Scan disable
8115 01:02:09.545011 == TX Byte 0 ==
8116 01:02:09.548560 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8117 01:02:09.551547 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8118 01:02:09.555018 == TX Byte 1 ==
8119 01:02:09.558500 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8120 01:02:09.565103 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8121 01:02:09.565186 ==
8122 01:02:09.567850 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 01:02:09.571388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 01:02:09.571471 ==
8125 01:02:09.584873
8126 01:02:09.587907 TX Vref early break, caculate TX vref
8127 01:02:09.591710 TX Vref=16, minBit 1, minWin=22, winSum=387
8128 01:02:09.594491 TX Vref=18, minBit 1, minWin=23, winSum=400
8129 01:02:09.597753 TX Vref=20, minBit 1, minWin=24, winSum=408
8130 01:02:09.600977 TX Vref=22, minBit 0, minWin=25, winSum=411
8131 01:02:09.604744 TX Vref=24, minBit 1, minWin=24, winSum=419
8132 01:02:09.611295 TX Vref=26, minBit 1, minWin=25, winSum=429
8133 01:02:09.614471 TX Vref=28, minBit 7, minWin=25, winSum=427
8134 01:02:09.617622 TX Vref=30, minBit 1, minWin=25, winSum=422
8135 01:02:09.620804 TX Vref=32, minBit 1, minWin=24, winSum=410
8136 01:02:09.624712 TX Vref=34, minBit 0, minWin=24, winSum=399
8137 01:02:09.630822 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
8138 01:02:09.630906
8139 01:02:09.634059 Final TX Range 0 Vref 26
8140 01:02:09.634142
8141 01:02:09.634208 ==
8142 01:02:09.637874 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 01:02:09.640703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 01:02:09.640787 ==
8145 01:02:09.640853
8146 01:02:09.640913
8147 01:02:09.644471 TX Vref Scan disable
8148 01:02:09.650844 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8149 01:02:09.650927 == TX Byte 0 ==
8150 01:02:09.654195 u2DelayCellOfst[0]=13 cells (4 PI)
8151 01:02:09.657534 u2DelayCellOfst[1]=16 cells (5 PI)
8152 01:02:09.660798 u2DelayCellOfst[2]=10 cells (3 PI)
8153 01:02:09.663849 u2DelayCellOfst[3]=10 cells (3 PI)
8154 01:02:09.667154 u2DelayCellOfst[4]=6 cells (2 PI)
8155 01:02:09.670609 u2DelayCellOfst[5]=0 cells (0 PI)
8156 01:02:09.673993 u2DelayCellOfst[6]=16 cells (5 PI)
8157 01:02:09.677218 u2DelayCellOfst[7]=16 cells (5 PI)
8158 01:02:09.680900 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8159 01:02:09.683919 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8160 01:02:09.687562 == TX Byte 1 ==
8161 01:02:09.687645 u2DelayCellOfst[8]=3 cells (1 PI)
8162 01:02:09.690729 u2DelayCellOfst[9]=0 cells (0 PI)
8163 01:02:09.693988 u2DelayCellOfst[10]=6 cells (2 PI)
8164 01:02:09.697291 u2DelayCellOfst[11]=3 cells (1 PI)
8165 01:02:09.700556 u2DelayCellOfst[12]=10 cells (3 PI)
8166 01:02:09.703745 u2DelayCellOfst[13]=13 cells (4 PI)
8167 01:02:09.707482 u2DelayCellOfst[14]=13 cells (4 PI)
8168 01:02:09.710859 u2DelayCellOfst[15]=10 cells (3 PI)
8169 01:02:09.714035 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8170 01:02:09.720504 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8171 01:02:09.720600 DramC Write-DBI on
8172 01:02:09.720667 ==
8173 01:02:09.723651 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 01:02:09.727489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 01:02:09.730618 ==
8176 01:02:09.730700
8177 01:02:09.730766
8178 01:02:09.730825 TX Vref Scan disable
8179 01:02:09.734399 == TX Byte 0 ==
8180 01:02:09.737615 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8181 01:02:09.740859 == TX Byte 1 ==
8182 01:02:09.743925 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8183 01:02:09.747141 DramC Write-DBI off
8184 01:02:09.747223
8185 01:02:09.747288 [DATLAT]
8186 01:02:09.747348 Freq=1600, CH0 RK1
8187 01:02:09.747438
8188 01:02:09.750617 DATLAT Default: 0xf
8189 01:02:09.750699 0, 0xFFFF, sum = 0
8190 01:02:09.754080 1, 0xFFFF, sum = 0
8191 01:02:09.757170 2, 0xFFFF, sum = 0
8192 01:02:09.757253 3, 0xFFFF, sum = 0
8193 01:02:09.760486 4, 0xFFFF, sum = 0
8194 01:02:09.760571 5, 0xFFFF, sum = 0
8195 01:02:09.764249 6, 0xFFFF, sum = 0
8196 01:02:09.764356 7, 0xFFFF, sum = 0
8197 01:02:09.767284 8, 0xFFFF, sum = 0
8198 01:02:09.767367 9, 0xFFFF, sum = 0
8199 01:02:09.770359 10, 0xFFFF, sum = 0
8200 01:02:09.770443 11, 0xFFFF, sum = 0
8201 01:02:09.773994 12, 0xFFFF, sum = 0
8202 01:02:09.774077 13, 0xFFFF, sum = 0
8203 01:02:09.777145 14, 0x0, sum = 1
8204 01:02:09.777237 15, 0x0, sum = 2
8205 01:02:09.780757 16, 0x0, sum = 3
8206 01:02:09.780841 17, 0x0, sum = 4
8207 01:02:09.783849 best_step = 15
8208 01:02:09.783930
8209 01:02:09.783995 ==
8210 01:02:09.786940 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 01:02:09.790660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 01:02:09.790743 ==
8213 01:02:09.790810 RX Vref Scan: 0
8214 01:02:09.793834
8215 01:02:09.793916 RX Vref 0 -> 0, step: 1
8216 01:02:09.793981
8217 01:02:09.797278 RX Delay 19 -> 252, step: 4
8218 01:02:09.800651 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8219 01:02:09.807282 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8220 01:02:09.810438 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8221 01:02:09.813944 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8222 01:02:09.816960 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8223 01:02:09.820595 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8224 01:02:09.826983 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8225 01:02:09.830255 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8226 01:02:09.833477 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8227 01:02:09.837115 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8228 01:02:09.840335 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8229 01:02:09.847343 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8230 01:02:09.850738 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8231 01:02:09.853942 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8232 01:02:09.856747 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8233 01:02:09.860278 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8234 01:02:09.863484 ==
8235 01:02:09.866647 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 01:02:09.870446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 01:02:09.870530 ==
8238 01:02:09.870596 DQS Delay:
8239 01:02:09.873708 DQS0 = 0, DQS1 = 0
8240 01:02:09.873791 DQM Delay:
8241 01:02:09.876922 DQM0 = 134, DQM1 = 127
8242 01:02:09.877005 DQ Delay:
8243 01:02:09.880000 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8244 01:02:09.883391 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8245 01:02:09.886800 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8246 01:02:09.890213 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8247 01:02:09.890296
8248 01:02:09.890361
8249 01:02:09.890421
8250 01:02:09.893613 [DramC_TX_OE_Calibration] TA2
8251 01:02:09.896989 Original DQ_B0 (3 6) =30, OEN = 27
8252 01:02:09.899966 Original DQ_B1 (3 6) =30, OEN = 27
8253 01:02:09.903193 24, 0x0, End_B0=24 End_B1=24
8254 01:02:09.906516 25, 0x0, End_B0=25 End_B1=25
8255 01:02:09.906599 26, 0x0, End_B0=26 End_B1=26
8256 01:02:09.910275 27, 0x0, End_B0=27 End_B1=27
8257 01:02:09.913471 28, 0x0, End_B0=28 End_B1=28
8258 01:02:09.916750 29, 0x0, End_B0=29 End_B1=29
8259 01:02:09.919914 30, 0x0, End_B0=30 End_B1=30
8260 01:02:09.919998 31, 0x4141, End_B0=30 End_B1=30
8261 01:02:09.923233 Byte0 end_step=30 best_step=27
8262 01:02:09.926457 Byte1 end_step=30 best_step=27
8263 01:02:09.929963 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 01:02:09.933659 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 01:02:09.933741
8266 01:02:09.933806
8267 01:02:09.939905 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8268 01:02:09.943172 CH0 RK1: MR19=303, MR18=220A
8269 01:02:09.949740 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8270 01:02:09.953066 [RxdqsGatingPostProcess] freq 1600
8271 01:02:09.959932 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 01:02:09.960015 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 01:02:09.963212 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 01:02:09.966344 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 01:02:09.969737 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 01:02:09.973531 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 01:02:09.976650 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 01:02:09.979583 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 01:02:09.982712 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 01:02:09.986145 Pre-setting of DQS Precalculation
8281 01:02:09.989882 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 01:02:09.989965 ==
8283 01:02:09.992939 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 01:02:09.999725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 01:02:09.999808 ==
8286 01:02:10.002726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 01:02:10.009615 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 01:02:10.012864 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 01:02:10.019108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 01:02:10.027461 [CA 0] Center 42 (12~72) winsize 61
8291 01:02:10.030643 [CA 1] Center 42 (13~72) winsize 60
8292 01:02:10.033743 [CA 2] Center 39 (10~68) winsize 59
8293 01:02:10.037265 [CA 3] Center 38 (9~67) winsize 59
8294 01:02:10.040408 [CA 4] Center 38 (9~68) winsize 60
8295 01:02:10.043900 [CA 5] Center 37 (8~67) winsize 60
8296 01:02:10.043983
8297 01:02:10.047232 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8298 01:02:10.047314
8299 01:02:10.050539 [CATrainingPosCal] consider 1 rank data
8300 01:02:10.053604 u2DelayCellTimex100 = 290/100 ps
8301 01:02:10.057375 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8302 01:02:10.063543 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8303 01:02:10.067371 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8304 01:02:10.070545 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8305 01:02:10.073757 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8306 01:02:10.076966 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8307 01:02:10.077048
8308 01:02:10.080195 CA PerBit enable=1, Macro0, CA PI delay=37
8309 01:02:10.080301
8310 01:02:10.083785 [CBTSetCACLKResult] CA Dly = 37
8311 01:02:10.086779 CS Dly: 10 (0~41)
8312 01:02:10.090296 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 01:02:10.093559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 01:02:10.093642 ==
8315 01:02:10.096653 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 01:02:10.100220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 01:02:10.104076 ==
8318 01:02:10.106794 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 01:02:10.110035 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 01:02:10.116718 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 01:02:10.120257 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 01:02:10.130667 [CA 0] Center 42 (12~72) winsize 61
8323 01:02:10.133809 [CA 1] Center 42 (13~72) winsize 60
8324 01:02:10.137077 [CA 2] Center 39 (10~68) winsize 59
8325 01:02:10.140169 [CA 3] Center 38 (9~68) winsize 60
8326 01:02:10.143808 [CA 4] Center 39 (9~69) winsize 61
8327 01:02:10.147102 [CA 5] Center 38 (9~67) winsize 59
8328 01:02:10.147174
8329 01:02:10.150247 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 01:02:10.150331
8331 01:02:10.153921 [CATrainingPosCal] consider 2 rank data
8332 01:02:10.156944 u2DelayCellTimex100 = 290/100 ps
8333 01:02:10.160693 CA0 delay=42 (12~72),Diff = 4 PI (13 cell)
8334 01:02:10.167319 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8335 01:02:10.170200 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8336 01:02:10.173784 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8337 01:02:10.177234 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8338 01:02:10.180491 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8339 01:02:10.180573
8340 01:02:10.183707 CA PerBit enable=1, Macro0, CA PI delay=38
8341 01:02:10.183790
8342 01:02:10.186847 [CBTSetCACLKResult] CA Dly = 38
8343 01:02:10.190782 CS Dly: 12 (0~45)
8344 01:02:10.193784 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 01:02:10.196996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 01:02:10.197079
8347 01:02:10.199957 ----->DramcWriteLeveling(PI) begin...
8348 01:02:10.200041 ==
8349 01:02:10.203788 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 01:02:10.209820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 01:02:10.209903 ==
8352 01:02:10.213589 Write leveling (Byte 0): 24 => 24
8353 01:02:10.213671 Write leveling (Byte 1): 27 => 27
8354 01:02:10.216749 DramcWriteLeveling(PI) end<-----
8355 01:02:10.216832
8356 01:02:10.219965 ==
8357 01:02:10.220047 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 01:02:10.226549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 01:02:10.226632 ==
8360 01:02:10.230208 [Gating] SW mode calibration
8361 01:02:10.236790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 01:02:10.240150 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 01:02:10.246544 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 01:02:10.250106 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 01:02:10.253279 1 4 8 | B1->B0 | 2322 2f2f | 1 0 | (0 0) (0 0)
8366 01:02:10.259370 1 4 12 | B1->B0 | 302f 3434 | 1 0 | (1 1) (0 0)
8367 01:02:10.263297 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 01:02:10.266418 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 01:02:10.272811 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 01:02:10.276405 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 01:02:10.279328 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 01:02:10.286423 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 01:02:10.289598 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8374 01:02:10.292478 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
8375 01:02:10.299353 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 01:02:10.302348 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 01:02:10.305481 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 01:02:10.312484 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 01:02:10.315530 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 01:02:10.319090 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 01:02:10.325956 1 6 8 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
8382 01:02:10.329129 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8383 01:02:10.332595 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 01:02:10.339222 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 01:02:10.342259 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 01:02:10.346015 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 01:02:10.352185 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 01:02:10.355820 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 01:02:10.358918 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 01:02:10.365610 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 01:02:10.368756 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 01:02:10.372579 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 01:02:10.375949 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 01:02:10.382379 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 01:02:10.385492 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 01:02:10.388769 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 01:02:10.395683 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 01:02:10.398903 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 01:02:10.402390 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 01:02:10.409171 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 01:02:10.412158 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 01:02:10.415208 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 01:02:10.422329 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 01:02:10.425379 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 01:02:10.428919 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8406 01:02:10.435813 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8407 01:02:10.438853 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 01:02:10.441987 Total UI for P1: 0, mck2ui 16
8409 01:02:10.445556 best dqsien dly found for B0: ( 1, 9, 10)
8410 01:02:10.449132 Total UI for P1: 0, mck2ui 16
8411 01:02:10.452453 best dqsien dly found for B1: ( 1, 9, 10)
8412 01:02:10.455572 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8413 01:02:10.458621 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8414 01:02:10.458704
8415 01:02:10.462339 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8416 01:02:10.465384 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8417 01:02:10.468817 [Gating] SW calibration Done
8418 01:02:10.468899 ==
8419 01:02:10.471911 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 01:02:10.475686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 01:02:10.478780 ==
8422 01:02:10.478862 RX Vref Scan: 0
8423 01:02:10.478928
8424 01:02:10.482118 RX Vref 0 -> 0, step: 1
8425 01:02:10.482201
8426 01:02:10.482266 RX Delay 0 -> 252, step: 8
8427 01:02:10.488586 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8428 01:02:10.491851 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8429 01:02:10.495064 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8430 01:02:10.498939 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8431 01:02:10.502164 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8432 01:02:10.509109 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8433 01:02:10.511649 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8434 01:02:10.515188 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8435 01:02:10.518327 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8436 01:02:10.521837 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8437 01:02:10.528547 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8438 01:02:10.532037 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8439 01:02:10.534803 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8440 01:02:10.538109 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8441 01:02:10.541512 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8442 01:02:10.548182 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8443 01:02:10.548278 ==
8444 01:02:10.551937 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 01:02:10.555171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 01:02:10.555254 ==
8447 01:02:10.555320 DQS Delay:
8448 01:02:10.558095 DQS0 = 0, DQS1 = 0
8449 01:02:10.558195 DQM Delay:
8450 01:02:10.561977 DQM0 = 136, DQM1 = 132
8451 01:02:10.562059 DQ Delay:
8452 01:02:10.565117 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8453 01:02:10.568204 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8454 01:02:10.571490 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8455 01:02:10.575109 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8456 01:02:10.577986
8457 01:02:10.578058
8458 01:02:10.578127 ==
8459 01:02:10.581352 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 01:02:10.585125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 01:02:10.585198 ==
8462 01:02:10.585260
8463 01:02:10.585318
8464 01:02:10.588107 TX Vref Scan disable
8465 01:02:10.588177 == TX Byte 0 ==
8466 01:02:10.594596 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8467 01:02:10.598368 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8468 01:02:10.598445 == TX Byte 1 ==
8469 01:02:10.605116 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8470 01:02:10.608193 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8471 01:02:10.608262 ==
8472 01:02:10.611465 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 01:02:10.614707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 01:02:10.614784 ==
8475 01:02:10.628095
8476 01:02:10.631285 TX Vref early break, caculate TX vref
8477 01:02:10.634945 TX Vref=16, minBit 0, minWin=23, winSum=381
8478 01:02:10.637975 TX Vref=18, minBit 1, minWin=23, winSum=392
8479 01:02:10.641788 TX Vref=20, minBit 1, minWin=24, winSum=402
8480 01:02:10.644972 TX Vref=22, minBit 0, minWin=25, winSum=408
8481 01:02:10.647978 TX Vref=24, minBit 1, minWin=25, winSum=422
8482 01:02:10.654468 TX Vref=26, minBit 0, minWin=26, winSum=430
8483 01:02:10.658217 TX Vref=28, minBit 6, minWin=25, winSum=426
8484 01:02:10.661365 TX Vref=30, minBit 0, minWin=25, winSum=421
8485 01:02:10.664527 TX Vref=32, minBit 0, minWin=24, winSum=415
8486 01:02:10.668120 TX Vref=34, minBit 0, minWin=24, winSum=406
8487 01:02:10.674441 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8488 01:02:10.674516
8489 01:02:10.677944 Final TX Range 0 Vref 26
8490 01:02:10.678017
8491 01:02:10.678085 ==
8492 01:02:10.681497 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 01:02:10.684567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 01:02:10.684646 ==
8495 01:02:10.684710
8496 01:02:10.684778
8497 01:02:10.687571 TX Vref Scan disable
8498 01:02:10.694128 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8499 01:02:10.694205 == TX Byte 0 ==
8500 01:02:10.698031 u2DelayCellOfst[0]=13 cells (4 PI)
8501 01:02:10.701490 u2DelayCellOfst[1]=10 cells (3 PI)
8502 01:02:10.704636 u2DelayCellOfst[2]=0 cells (0 PI)
8503 01:02:10.707890 u2DelayCellOfst[3]=6 cells (2 PI)
8504 01:02:10.711080 u2DelayCellOfst[4]=10 cells (3 PI)
8505 01:02:10.714350 u2DelayCellOfst[5]=16 cells (5 PI)
8506 01:02:10.717503 u2DelayCellOfst[6]=16 cells (5 PI)
8507 01:02:10.720695 u2DelayCellOfst[7]=6 cells (2 PI)
8508 01:02:10.724490 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8509 01:02:10.727604 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8510 01:02:10.730624 == TX Byte 1 ==
8511 01:02:10.730698 u2DelayCellOfst[8]=0 cells (0 PI)
8512 01:02:10.734468 u2DelayCellOfst[9]=3 cells (1 PI)
8513 01:02:10.737668 u2DelayCellOfst[10]=13 cells (4 PI)
8514 01:02:10.740934 u2DelayCellOfst[11]=3 cells (1 PI)
8515 01:02:10.743962 u2DelayCellOfst[12]=16 cells (5 PI)
8516 01:02:10.747479 u2DelayCellOfst[13]=16 cells (5 PI)
8517 01:02:10.750538 u2DelayCellOfst[14]=16 cells (5 PI)
8518 01:02:10.754239 u2DelayCellOfst[15]=16 cells (5 PI)
8519 01:02:10.757525 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8520 01:02:10.764119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 01:02:10.764195 DramC Write-DBI on
8522 01:02:10.764265 ==
8523 01:02:10.767186 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 01:02:10.770900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 01:02:10.774078 ==
8526 01:02:10.774149
8527 01:02:10.774211
8528 01:02:10.774269 TX Vref Scan disable
8529 01:02:10.777739 == TX Byte 0 ==
8530 01:02:10.780807 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8531 01:02:10.784370 == TX Byte 1 ==
8532 01:02:10.787227 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8533 01:02:10.790826 DramC Write-DBI off
8534 01:02:10.790901
8535 01:02:10.790963 [DATLAT]
8536 01:02:10.791022 Freq=1600, CH1 RK0
8537 01:02:10.791088
8538 01:02:10.794341 DATLAT Default: 0xf
8539 01:02:10.794451 0, 0xFFFF, sum = 0
8540 01:02:10.797671 1, 0xFFFF, sum = 0
8541 01:02:10.797747 2, 0xFFFF, sum = 0
8542 01:02:10.800945 3, 0xFFFF, sum = 0
8543 01:02:10.804485 4, 0xFFFF, sum = 0
8544 01:02:10.804554 5, 0xFFFF, sum = 0
8545 01:02:10.807152 6, 0xFFFF, sum = 0
8546 01:02:10.807226 7, 0xFFFF, sum = 0
8547 01:02:10.810935 8, 0xFFFF, sum = 0
8548 01:02:10.811013 9, 0xFFFF, sum = 0
8549 01:02:10.814301 10, 0xFFFF, sum = 0
8550 01:02:10.814374 11, 0xFFFF, sum = 0
8551 01:02:10.817499 12, 0xFFFF, sum = 0
8552 01:02:10.817569 13, 0xFFFF, sum = 0
8553 01:02:10.820770 14, 0x0, sum = 1
8554 01:02:10.820849 15, 0x0, sum = 2
8555 01:02:10.823969 16, 0x0, sum = 3
8556 01:02:10.824041 17, 0x0, sum = 4
8557 01:02:10.827167 best_step = 15
8558 01:02:10.827240
8559 01:02:10.827302 ==
8560 01:02:10.830394 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 01:02:10.834249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 01:02:10.834322 ==
8563 01:02:10.837528 RX Vref Scan: 1
8564 01:02:10.837603
8565 01:02:10.837665 Set Vref Range= 24 -> 127
8566 01:02:10.837724
8567 01:02:10.840558 RX Vref 24 -> 127, step: 1
8568 01:02:10.840644
8569 01:02:10.843895 RX Delay 27 -> 252, step: 4
8570 01:02:10.843965
8571 01:02:10.847122 Set Vref, RX VrefLevel [Byte0]: 24
8572 01:02:10.850240 [Byte1]: 24
8573 01:02:10.850310
8574 01:02:10.853840 Set Vref, RX VrefLevel [Byte0]: 25
8575 01:02:10.856949 [Byte1]: 25
8576 01:02:10.857017
8577 01:02:10.860533 Set Vref, RX VrefLevel [Byte0]: 26
8578 01:02:10.863602 [Byte1]: 26
8579 01:02:10.867406
8580 01:02:10.867482 Set Vref, RX VrefLevel [Byte0]: 27
8581 01:02:10.871036 [Byte1]: 27
8582 01:02:10.875213
8583 01:02:10.875284 Set Vref, RX VrefLevel [Byte0]: 28
8584 01:02:10.878816 [Byte1]: 28
8585 01:02:10.882522
8586 01:02:10.882591 Set Vref, RX VrefLevel [Byte0]: 29
8587 01:02:10.885795 [Byte1]: 29
8588 01:02:10.890332
8589 01:02:10.890410 Set Vref, RX VrefLevel [Byte0]: 30
8590 01:02:10.893450 [Byte1]: 30
8591 01:02:10.897762
8592 01:02:10.897836 Set Vref, RX VrefLevel [Byte0]: 31
8593 01:02:10.901238 [Byte1]: 31
8594 01:02:10.905711
8595 01:02:10.905786 Set Vref, RX VrefLevel [Byte0]: 32
8596 01:02:10.908831 [Byte1]: 32
8597 01:02:10.913087
8598 01:02:10.913157 Set Vref, RX VrefLevel [Byte0]: 33
8599 01:02:10.916044 [Byte1]: 33
8600 01:02:10.920562
8601 01:02:10.920638 Set Vref, RX VrefLevel [Byte0]: 34
8602 01:02:10.923599 [Byte1]: 34
8603 01:02:10.927971
8604 01:02:10.928051 Set Vref, RX VrefLevel [Byte0]: 35
8605 01:02:10.931330 [Byte1]: 35
8606 01:02:10.935746
8607 01:02:10.935823 Set Vref, RX VrefLevel [Byte0]: 36
8608 01:02:10.938988 [Byte1]: 36
8609 01:02:10.942755
8610 01:02:10.942830 Set Vref, RX VrefLevel [Byte0]: 37
8611 01:02:10.946002 [Byte1]: 37
8612 01:02:10.950501
8613 01:02:10.950570 Set Vref, RX VrefLevel [Byte0]: 38
8614 01:02:10.953723 [Byte1]: 38
8615 01:02:10.958052
8616 01:02:10.958120 Set Vref, RX VrefLevel [Byte0]: 39
8617 01:02:10.961034 [Byte1]: 39
8618 01:02:10.965475
8619 01:02:10.965552 Set Vref, RX VrefLevel [Byte0]: 40
8620 01:02:10.968961 [Byte1]: 40
8621 01:02:10.973304
8622 01:02:10.973385 Set Vref, RX VrefLevel [Byte0]: 41
8623 01:02:10.976513 [Byte1]: 41
8624 01:02:10.980614
8625 01:02:10.980684 Set Vref, RX VrefLevel [Byte0]: 42
8626 01:02:10.984206 [Byte1]: 42
8627 01:02:10.987935
8628 01:02:10.988010 Set Vref, RX VrefLevel [Byte0]: 43
8629 01:02:10.991157 [Byte1]: 43
8630 01:02:10.995689
8631 01:02:10.995771 Set Vref, RX VrefLevel [Byte0]: 44
8632 01:02:10.998786 [Byte1]: 44
8633 01:02:11.003060
8634 01:02:11.003141 Set Vref, RX VrefLevel [Byte0]: 45
8635 01:02:11.006480 [Byte1]: 45
8636 01:02:11.010473
8637 01:02:11.010543 Set Vref, RX VrefLevel [Byte0]: 46
8638 01:02:11.013759 [Byte1]: 46
8639 01:02:11.018589
8640 01:02:11.018663 Set Vref, RX VrefLevel [Byte0]: 47
8641 01:02:11.021763 [Byte1]: 47
8642 01:02:11.025602
8643 01:02:11.025674 Set Vref, RX VrefLevel [Byte0]: 48
8644 01:02:11.029490 [Byte1]: 48
8645 01:02:11.033235
8646 01:02:11.033316 Set Vref, RX VrefLevel [Byte0]: 49
8647 01:02:11.036661 [Byte1]: 49
8648 01:02:11.041022
8649 01:02:11.041100 Set Vref, RX VrefLevel [Byte0]: 50
8650 01:02:11.044067 [Byte1]: 50
8651 01:02:11.048540
8652 01:02:11.048622 Set Vref, RX VrefLevel [Byte0]: 51
8653 01:02:11.051617 [Byte1]: 51
8654 01:02:11.056113
8655 01:02:11.056212 Set Vref, RX VrefLevel [Byte0]: 52
8656 01:02:11.059556 [Byte1]: 52
8657 01:02:11.063323
8658 01:02:11.063405 Set Vref, RX VrefLevel [Byte0]: 53
8659 01:02:11.067047 [Byte1]: 53
8660 01:02:11.071266
8661 01:02:11.071348 Set Vref, RX VrefLevel [Byte0]: 54
8662 01:02:11.074294 [Byte1]: 54
8663 01:02:11.078500
8664 01:02:11.078582 Set Vref, RX VrefLevel [Byte0]: 55
8665 01:02:11.082121 [Byte1]: 55
8666 01:02:11.085773
8667 01:02:11.085858 Set Vref, RX VrefLevel [Byte0]: 56
8668 01:02:11.089528 [Byte1]: 56
8669 01:02:11.093505
8670 01:02:11.093587 Set Vref, RX VrefLevel [Byte0]: 57
8671 01:02:11.097145 [Byte1]: 57
8672 01:02:11.101053
8673 01:02:11.101135 Set Vref, RX VrefLevel [Byte0]: 58
8674 01:02:11.104214 [Byte1]: 58
8675 01:02:11.108557
8676 01:02:11.108640 Set Vref, RX VrefLevel [Byte0]: 59
8677 01:02:11.111794 [Byte1]: 59
8678 01:02:11.115981
8679 01:02:11.119235 Set Vref, RX VrefLevel [Byte0]: 60
8680 01:02:11.122418 [Byte1]: 60
8681 01:02:11.122501
8682 01:02:11.126182 Set Vref, RX VrefLevel [Byte0]: 61
8683 01:02:11.129345 [Byte1]: 61
8684 01:02:11.129420
8685 01:02:11.132573 Set Vref, RX VrefLevel [Byte0]: 62
8686 01:02:11.135841 [Byte1]: 62
8687 01:02:11.135915
8688 01:02:11.139065 Set Vref, RX VrefLevel [Byte0]: 63
8689 01:02:11.142336 [Byte1]: 63
8690 01:02:11.146213
8691 01:02:11.146284 Set Vref, RX VrefLevel [Byte0]: 64
8692 01:02:11.149871 [Byte1]: 64
8693 01:02:11.153533
8694 01:02:11.153614 Set Vref, RX VrefLevel [Byte0]: 65
8695 01:02:11.157268 [Byte1]: 65
8696 01:02:11.161467
8697 01:02:11.161542 Set Vref, RX VrefLevel [Byte0]: 66
8698 01:02:11.164921 [Byte1]: 66
8699 01:02:11.168675
8700 01:02:11.168757 Set Vref, RX VrefLevel [Byte0]: 67
8701 01:02:11.172321 [Byte1]: 67
8702 01:02:11.176442
8703 01:02:11.176524 Set Vref, RX VrefLevel [Byte0]: 68
8704 01:02:11.179569 [Byte1]: 68
8705 01:02:11.184118
8706 01:02:11.184204 Set Vref, RX VrefLevel [Byte0]: 69
8707 01:02:11.186935 [Byte1]: 69
8708 01:02:11.191338
8709 01:02:11.191453 Set Vref, RX VrefLevel [Byte0]: 70
8710 01:02:11.194766 [Byte1]: 70
8711 01:02:11.199001
8712 01:02:11.199084 Set Vref, RX VrefLevel [Byte0]: 71
8713 01:02:11.202219 [Byte1]: 71
8714 01:02:11.206825
8715 01:02:11.206908 Set Vref, RX VrefLevel [Byte0]: 72
8716 01:02:11.209877 [Byte1]: 72
8717 01:02:11.214102
8718 01:02:11.214185 Set Vref, RX VrefLevel [Byte0]: 73
8719 01:02:11.217146 [Byte1]: 73
8720 01:02:11.221992
8721 01:02:11.222076 Set Vref, RX VrefLevel [Byte0]: 74
8722 01:02:11.225244 [Byte1]: 74
8723 01:02:11.229244
8724 01:02:11.229326 Set Vref, RX VrefLevel [Byte0]: 75
8725 01:02:11.232261 [Byte1]: 75
8726 01:02:11.236750
8727 01:02:11.236832 Set Vref, RX VrefLevel [Byte0]: 76
8728 01:02:11.240024 [Byte1]: 76
8729 01:02:11.244516
8730 01:02:11.244598 Set Vref, RX VrefLevel [Byte0]: 77
8731 01:02:11.247574 [Byte1]: 77
8732 01:02:11.251456
8733 01:02:11.251541 Set Vref, RX VrefLevel [Byte0]: 78
8734 01:02:11.255268 [Byte1]: 78
8735 01:02:11.259446
8736 01:02:11.259528 Set Vref, RX VrefLevel [Byte0]: 79
8737 01:02:11.262762 [Byte1]: 79
8738 01:02:11.266635
8739 01:02:11.266717 Final RX Vref Byte 0 = 58 to rank0
8740 01:02:11.270591 Final RX Vref Byte 1 = 56 to rank0
8741 01:02:11.273197 Final RX Vref Byte 0 = 58 to rank1
8742 01:02:11.277035 Final RX Vref Byte 1 = 56 to rank1==
8743 01:02:11.280505 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 01:02:11.283447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 01:02:11.287185 ==
8746 01:02:11.287267 DQS Delay:
8747 01:02:11.287333 DQS0 = 0, DQS1 = 0
8748 01:02:11.290081 DQM Delay:
8749 01:02:11.290164 DQM0 = 134, DQM1 = 131
8750 01:02:11.293349 DQ Delay:
8751 01:02:11.296858 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8752 01:02:11.300232 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =134
8753 01:02:11.303517 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8754 01:02:11.306759 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8755 01:02:11.306841
8756 01:02:11.306928
8757 01:02:11.307003
8758 01:02:11.310330 [DramC_TX_OE_Calibration] TA2
8759 01:02:11.313558 Original DQ_B0 (3 6) =30, OEN = 27
8760 01:02:11.317057 Original DQ_B1 (3 6) =30, OEN = 27
8761 01:02:11.320178 24, 0x0, End_B0=24 End_B1=24
8762 01:02:11.320296 25, 0x0, End_B0=25 End_B1=25
8763 01:02:11.323397 26, 0x0, End_B0=26 End_B1=26
8764 01:02:11.326564 27, 0x0, End_B0=27 End_B1=27
8765 01:02:11.330110 28, 0x0, End_B0=28 End_B1=28
8766 01:02:11.330193 29, 0x0, End_B0=29 End_B1=29
8767 01:02:11.333232 30, 0x0, End_B0=30 End_B1=30
8768 01:02:11.336801 31, 0x4141, End_B0=30 End_B1=30
8769 01:02:11.340588 Byte0 end_step=30 best_step=27
8770 01:02:11.343802 Byte1 end_step=30 best_step=27
8771 01:02:11.346943 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 01:02:11.347026 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 01:02:11.347091
8774 01:02:11.350167
8775 01:02:11.357097 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8776 01:02:11.360339 CH1 RK0: MR19=303, MR18=1624
8777 01:02:11.366999 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8778 01:02:11.367083
8779 01:02:11.370281 ----->DramcWriteLeveling(PI) begin...
8780 01:02:11.370365 ==
8781 01:02:11.373536 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 01:02:11.376719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 01:02:11.376802 ==
8784 01:02:11.379891 Write leveling (Byte 0): 25 => 25
8785 01:02:11.383151 Write leveling (Byte 1): 27 => 27
8786 01:02:11.387080 DramcWriteLeveling(PI) end<-----
8787 01:02:11.387163
8788 01:02:11.387228 ==
8789 01:02:11.390151 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 01:02:11.393210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 01:02:11.393299 ==
8792 01:02:11.396817 [Gating] SW mode calibration
8793 01:02:11.403371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 01:02:11.410272 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 01:02:11.413489 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 01:02:11.416675 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 01:02:11.423790 1 4 8 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
8798 01:02:11.426730 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8799 01:02:11.430060 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 01:02:11.436495 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 01:02:11.439978 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 01:02:11.443678 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 01:02:11.450033 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 01:02:11.453498 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 01:02:11.456587 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
8806 01:02:11.463614 1 5 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 1)
8807 01:02:11.466707 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 01:02:11.469816 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 01:02:11.476428 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 01:02:11.479557 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 01:02:11.483505 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 01:02:11.486760 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8813 01:02:11.493329 1 6 8 | B1->B0 | 3030 2424 | 1 0 | (0 0) (0 0)
8814 01:02:11.496429 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 01:02:11.500227 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 01:02:11.506367 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 01:02:11.509832 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 01:02:11.513065 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 01:02:11.519738 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 01:02:11.522827 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8821 01:02:11.526575 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 01:02:11.533294 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8823 01:02:11.536419 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8824 01:02:11.539907 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 01:02:11.546183 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 01:02:11.550006 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 01:02:11.553113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 01:02:11.559493 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 01:02:11.562966 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 01:02:11.566323 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 01:02:11.572722 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 01:02:11.576290 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 01:02:11.579526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 01:02:11.585863 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 01:02:11.589748 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 01:02:11.593013 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8837 01:02:11.599240 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 01:02:11.602959 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8839 01:02:11.606208 Total UI for P1: 0, mck2ui 16
8840 01:02:11.609436 best dqsien dly found for B1: ( 1, 9, 6)
8841 01:02:11.612687 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 01:02:11.615809 Total UI for P1: 0, mck2ui 16
8843 01:02:11.619615 best dqsien dly found for B0: ( 1, 9, 12)
8844 01:02:11.622449 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8845 01:02:11.625732 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8846 01:02:11.625814
8847 01:02:11.629085 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8848 01:02:11.635983 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8849 01:02:11.636067 [Gating] SW calibration Done
8850 01:02:11.636133 ==
8851 01:02:11.639019 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 01:02:11.645927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 01:02:11.646011 ==
8854 01:02:11.646076 RX Vref Scan: 0
8855 01:02:11.646136
8856 01:02:11.649205 RX Vref 0 -> 0, step: 1
8857 01:02:11.649288
8858 01:02:11.652463 RX Delay 0 -> 252, step: 8
8859 01:02:11.656199 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8860 01:02:11.659347 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8861 01:02:11.662407 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8862 01:02:11.665531 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8863 01:02:11.672672 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8864 01:02:11.675775 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8865 01:02:11.678819 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8866 01:02:11.682443 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8867 01:02:11.685555 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8868 01:02:11.692179 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8869 01:02:11.695374 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8870 01:02:11.699387 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8871 01:02:11.702410 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8872 01:02:11.708768 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8873 01:02:11.711987 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8874 01:02:11.715137 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8875 01:02:11.715219 ==
8876 01:02:11.718451 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 01:02:11.722195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 01:02:11.722278 ==
8879 01:02:11.725586 DQS Delay:
8880 01:02:11.725668 DQS0 = 0, DQS1 = 0
8881 01:02:11.728585 DQM Delay:
8882 01:02:11.728668 DQM0 = 136, DQM1 = 133
8883 01:02:11.728734 DQ Delay:
8884 01:02:11.735450 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8885 01:02:11.738834 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8886 01:02:11.742040 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8887 01:02:11.745450 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8888 01:02:11.745533
8889 01:02:11.745599
8890 01:02:11.745660 ==
8891 01:02:11.748734 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 01:02:11.751770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 01:02:11.751853 ==
8894 01:02:11.751918
8895 01:02:11.751978
8896 01:02:11.755203 TX Vref Scan disable
8897 01:02:11.758766 == TX Byte 0 ==
8898 01:02:11.761745 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 01:02:11.765478 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 01:02:11.768575 == TX Byte 1 ==
8901 01:02:11.771664 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 01:02:11.774959 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8903 01:02:11.775043 ==
8904 01:02:11.778659 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 01:02:11.781789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 01:02:11.785031 ==
8907 01:02:11.797176
8908 01:02:11.800729 TX Vref early break, caculate TX vref
8909 01:02:11.803818 TX Vref=16, minBit 6, minWin=22, winSum=382
8910 01:02:11.806972 TX Vref=18, minBit 0, minWin=23, winSum=397
8911 01:02:11.810118 TX Vref=20, minBit 5, minWin=24, winSum=405
8912 01:02:11.813534 TX Vref=22, minBit 0, minWin=25, winSum=414
8913 01:02:11.816791 TX Vref=24, minBit 0, minWin=25, winSum=421
8914 01:02:11.823640 TX Vref=26, minBit 0, minWin=26, winSum=430
8915 01:02:11.826878 TX Vref=28, minBit 1, minWin=25, winSum=430
8916 01:02:11.830267 TX Vref=30, minBit 0, minWin=25, winSum=423
8917 01:02:11.833883 TX Vref=32, minBit 1, minWin=25, winSum=416
8918 01:02:11.836972 TX Vref=34, minBit 0, minWin=24, winSum=408
8919 01:02:11.840155 TX Vref=36, minBit 0, minWin=23, winSum=401
8920 01:02:11.847128 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8921 01:02:11.847205
8922 01:02:11.850578 Final TX Range 0 Vref 26
8923 01:02:11.850650
8924 01:02:11.850711 ==
8925 01:02:11.853485 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 01:02:11.856965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 01:02:11.857044 ==
8928 01:02:11.857106
8929 01:02:11.857165
8930 01:02:11.860480 TX Vref Scan disable
8931 01:02:11.867271 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8932 01:02:11.867348 == TX Byte 0 ==
8933 01:02:11.870206 u2DelayCellOfst[0]=16 cells (5 PI)
8934 01:02:11.873672 u2DelayCellOfst[1]=10 cells (3 PI)
8935 01:02:11.877213 u2DelayCellOfst[2]=0 cells (0 PI)
8936 01:02:11.879997 u2DelayCellOfst[3]=6 cells (2 PI)
8937 01:02:11.883840 u2DelayCellOfst[4]=10 cells (3 PI)
8938 01:02:11.887000 u2DelayCellOfst[5]=16 cells (5 PI)
8939 01:02:11.890215 u2DelayCellOfst[6]=16 cells (5 PI)
8940 01:02:11.893310 u2DelayCellOfst[7]=6 cells (2 PI)
8941 01:02:11.897114 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8942 01:02:11.900441 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8943 01:02:11.903589 == TX Byte 1 ==
8944 01:02:11.906847 u2DelayCellOfst[8]=0 cells (0 PI)
8945 01:02:11.906918 u2DelayCellOfst[9]=6 cells (2 PI)
8946 01:02:11.910165 u2DelayCellOfst[10]=13 cells (4 PI)
8947 01:02:11.913254 u2DelayCellOfst[11]=6 cells (2 PI)
8948 01:02:11.916521 u2DelayCellOfst[12]=16 cells (5 PI)
8949 01:02:11.920002 u2DelayCellOfst[13]=16 cells (5 PI)
8950 01:02:11.923599 u2DelayCellOfst[14]=20 cells (6 PI)
8951 01:02:11.926296 u2DelayCellOfst[15]=20 cells (6 PI)
8952 01:02:11.929633 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8953 01:02:11.936478 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8954 01:02:11.936555 DramC Write-DBI on
8955 01:02:11.936618 ==
8956 01:02:11.939882 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 01:02:11.946012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 01:02:11.946094 ==
8959 01:02:11.946160
8960 01:02:11.946221
8961 01:02:11.946289 TX Vref Scan disable
8962 01:02:11.950432 == TX Byte 0 ==
8963 01:02:11.953527 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8964 01:02:11.956615 == TX Byte 1 ==
8965 01:02:11.960137 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8966 01:02:11.963925 DramC Write-DBI off
8967 01:02:11.963999
8968 01:02:11.964068 [DATLAT]
8969 01:02:11.964131 Freq=1600, CH1 RK1
8970 01:02:11.964190
8971 01:02:11.966905 DATLAT Default: 0xf
8972 01:02:11.966982 0, 0xFFFF, sum = 0
8973 01:02:11.970421 1, 0xFFFF, sum = 0
8974 01:02:11.970501 2, 0xFFFF, sum = 0
8975 01:02:11.973473 3, 0xFFFF, sum = 0
8976 01:02:11.976923 4, 0xFFFF, sum = 0
8977 01:02:11.976996 5, 0xFFFF, sum = 0
8978 01:02:11.980412 6, 0xFFFF, sum = 0
8979 01:02:11.980485 7, 0xFFFF, sum = 0
8980 01:02:11.983271 8, 0xFFFF, sum = 0
8981 01:02:11.983351 9, 0xFFFF, sum = 0
8982 01:02:11.986627 10, 0xFFFF, sum = 0
8983 01:02:11.986700 11, 0xFFFF, sum = 0
8984 01:02:11.990130 12, 0xFFFF, sum = 0
8985 01:02:11.990206 13, 0xFFFF, sum = 0
8986 01:02:11.993731 14, 0x0, sum = 1
8987 01:02:11.993848 15, 0x0, sum = 2
8988 01:02:11.996927 16, 0x0, sum = 3
8989 01:02:11.997010 17, 0x0, sum = 4
8990 01:02:12.000138 best_step = 15
8991 01:02:12.000220
8992 01:02:12.000306 ==
8993 01:02:12.003397 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 01:02:12.006462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 01:02:12.006545 ==
8996 01:02:12.009765 RX Vref Scan: 0
8997 01:02:12.009847
8998 01:02:12.009912 RX Vref 0 -> 0, step: 1
8999 01:02:12.009973
9000 01:02:12.013599 RX Delay 19 -> 252, step: 4
9001 01:02:12.016776 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9002 01:02:12.023321 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9003 01:02:12.026667 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9004 01:02:12.029850 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9005 01:02:12.033625 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9006 01:02:12.036737 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9007 01:02:12.040158 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9008 01:02:12.046913 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9009 01:02:12.049775 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9010 01:02:12.053150 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9011 01:02:12.056591 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9012 01:02:12.059866 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9013 01:02:12.067140 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9014 01:02:12.069865 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9015 01:02:12.073455 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9016 01:02:12.077025 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9017 01:02:12.077107 ==
9018 01:02:12.080166 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 01:02:12.086705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 01:02:12.086788 ==
9021 01:02:12.086855 DQS Delay:
9022 01:02:12.089781 DQS0 = 0, DQS1 = 0
9023 01:02:12.089864 DQM Delay:
9024 01:02:12.093383 DQM0 = 134, DQM1 = 130
9025 01:02:12.093465 DQ Delay:
9026 01:02:12.096307 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9027 01:02:12.099650 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9028 01:02:12.103161 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9029 01:02:12.106291 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9030 01:02:12.106374
9031 01:02:12.106439
9032 01:02:12.106500
9033 01:02:12.109575 [DramC_TX_OE_Calibration] TA2
9034 01:02:12.113563 Original DQ_B0 (3 6) =30, OEN = 27
9035 01:02:12.116045 Original DQ_B1 (3 6) =30, OEN = 27
9036 01:02:12.119863 24, 0x0, End_B0=24 End_B1=24
9037 01:02:12.123151 25, 0x0, End_B0=25 End_B1=25
9038 01:02:12.123235 26, 0x0, End_B0=26 End_B1=26
9039 01:02:12.126490 27, 0x0, End_B0=27 End_B1=27
9040 01:02:12.129825 28, 0x0, End_B0=28 End_B1=28
9041 01:02:12.132888 29, 0x0, End_B0=29 End_B1=29
9042 01:02:12.132972 30, 0x0, End_B0=30 End_B1=30
9043 01:02:12.136138 31, 0x4545, End_B0=30 End_B1=30
9044 01:02:12.139343 Byte0 end_step=30 best_step=27
9045 01:02:12.142487 Byte1 end_step=30 best_step=27
9046 01:02:12.146251 Byte0 TX OE(2T, 0.5T) = (3, 3)
9047 01:02:12.149447 Byte1 TX OE(2T, 0.5T) = (3, 3)
9048 01:02:12.149530
9049 01:02:12.149594
9050 01:02:12.155705 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9051 01:02:12.159396 CH1 RK1: MR19=303, MR18=2106
9052 01:02:12.165886 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9053 01:02:12.169064 [RxdqsGatingPostProcess] freq 1600
9054 01:02:12.175665 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9055 01:02:12.175771 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 01:02:12.179417 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 01:02:12.182229 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 01:02:12.186249 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 01:02:12.189314 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 01:02:12.192176 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 01:02:12.195579 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 01:02:12.199277 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 01:02:12.202635 Pre-setting of DQS Precalculation
9064 01:02:12.205884 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9065 01:02:12.212623 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9066 01:02:12.222520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 01:02:12.222609
9068 01:02:12.222706
9069 01:02:12.225737 [Calibration Summary] 3200 Mbps
9070 01:02:12.225820 CH 0, Rank 0
9071 01:02:12.228951 SW Impedance : PASS
9072 01:02:12.229033 DUTY Scan : NO K
9073 01:02:12.232137 ZQ Calibration : PASS
9074 01:02:12.235438 Jitter Meter : NO K
9075 01:02:12.235541 CBT Training : PASS
9076 01:02:12.238773 Write leveling : PASS
9077 01:02:12.241976 RX DQS gating : PASS
9078 01:02:12.242061 RX DQ/DQS(RDDQC) : PASS
9079 01:02:12.245927 TX DQ/DQS : PASS
9080 01:02:12.246011 RX DATLAT : PASS
9081 01:02:12.249022 RX DQ/DQS(Engine): PASS
9082 01:02:12.252174 TX OE : PASS
9083 01:02:12.252304 All Pass.
9084 01:02:12.252387
9085 01:02:12.252448 CH 0, Rank 1
9086 01:02:12.255693 SW Impedance : PASS
9087 01:02:12.258714 DUTY Scan : NO K
9088 01:02:12.258796 ZQ Calibration : PASS
9089 01:02:12.261957 Jitter Meter : NO K
9090 01:02:12.265029 CBT Training : PASS
9091 01:02:12.265138 Write leveling : PASS
9092 01:02:12.268732 RX DQS gating : PASS
9093 01:02:12.272146 RX DQ/DQS(RDDQC) : PASS
9094 01:02:12.272229 TX DQ/DQS : PASS
9095 01:02:12.275006 RX DATLAT : PASS
9096 01:02:12.278266 RX DQ/DQS(Engine): PASS
9097 01:02:12.278349 TX OE : PASS
9098 01:02:12.282216 All Pass.
9099 01:02:12.282299
9100 01:02:12.282364 CH 1, Rank 0
9101 01:02:12.285414 SW Impedance : PASS
9102 01:02:12.285497 DUTY Scan : NO K
9103 01:02:12.288508 ZQ Calibration : PASS
9104 01:02:12.291523 Jitter Meter : NO K
9105 01:02:12.291606 CBT Training : PASS
9106 01:02:12.295298 Write leveling : PASS
9107 01:02:12.298413 RX DQS gating : PASS
9108 01:02:12.298496 RX DQ/DQS(RDDQC) : PASS
9109 01:02:12.301980 TX DQ/DQS : PASS
9110 01:02:12.305243 RX DATLAT : PASS
9111 01:02:12.305326 RX DQ/DQS(Engine): PASS
9112 01:02:12.308267 TX OE : PASS
9113 01:02:12.308388 All Pass.
9114 01:02:12.308454
9115 01:02:12.311821 CH 1, Rank 1
9116 01:02:12.311907 SW Impedance : PASS
9117 01:02:12.314700 DUTY Scan : NO K
9118 01:02:12.314783 ZQ Calibration : PASS
9119 01:02:12.318099 Jitter Meter : NO K
9120 01:02:12.321388 CBT Training : PASS
9121 01:02:12.321469 Write leveling : PASS
9122 01:02:12.324825 RX DQS gating : PASS
9123 01:02:12.328157 RX DQ/DQS(RDDQC) : PASS
9124 01:02:12.328261 TX DQ/DQS : PASS
9125 01:02:12.331706 RX DATLAT : PASS
9126 01:02:12.335002 RX DQ/DQS(Engine): PASS
9127 01:02:12.335086 TX OE : PASS
9128 01:02:12.337858 All Pass.
9129 01:02:12.337940
9130 01:02:12.338005 DramC Write-DBI on
9131 01:02:12.341428 PER_BANK_REFRESH: Hybrid Mode
9132 01:02:12.341512 TX_TRACKING: ON
9133 01:02:12.351486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9134 01:02:12.361100 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9135 01:02:12.368186 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 01:02:12.371486 [FAST_K] Save calibration result to emmc
9137 01:02:12.374700 sync common calibartion params.
9138 01:02:12.374782 sync cbt_mode0:1, 1:1
9139 01:02:12.377734 dram_init: ddr_geometry: 2
9140 01:02:12.381339 dram_init: ddr_geometry: 2
9141 01:02:12.381422 dram_init: ddr_geometry: 2
9142 01:02:12.384258 0:dram_rank_size:100000000
9143 01:02:12.388048 1:dram_rank_size:100000000
9144 01:02:12.394530 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9145 01:02:12.394613 DFS_SHUFFLE_HW_MODE: ON
9146 01:02:12.398272 dramc_set_vcore_voltage set vcore to 725000
9147 01:02:12.401497 Read voltage for 1600, 0
9148 01:02:12.401579 Vio18 = 0
9149 01:02:12.404849 Vcore = 725000
9150 01:02:12.404931 Vdram = 0
9151 01:02:12.404998 Vddq = 0
9152 01:02:12.408124 Vmddr = 0
9153 01:02:12.408207 switch to 3200 Mbps bootup
9154 01:02:12.411083 [DramcRunTimeConfig]
9155 01:02:12.411165 PHYPLL
9156 01:02:12.414915 DPM_CONTROL_AFTERK: ON
9157 01:02:12.414998 PER_BANK_REFRESH: ON
9158 01:02:12.417940 REFRESH_OVERHEAD_REDUCTION: ON
9159 01:02:12.421066 CMD_PICG_NEW_MODE: OFF
9160 01:02:12.421149 XRTWTW_NEW_MODE: ON
9161 01:02:12.424937 XRTRTR_NEW_MODE: ON
9162 01:02:12.425021 TX_TRACKING: ON
9163 01:02:12.428006 RDSEL_TRACKING: OFF
9164 01:02:12.430898 DQS Precalculation for DVFS: ON
9165 01:02:12.430982 RX_TRACKING: OFF
9166 01:02:12.434703 HW_GATING DBG: ON
9167 01:02:12.434786 ZQCS_ENABLE_LP4: ON
9168 01:02:12.437633 RX_PICG_NEW_MODE: ON
9169 01:02:12.437716 TX_PICG_NEW_MODE: ON
9170 01:02:12.441012 ENABLE_RX_DCM_DPHY: ON
9171 01:02:12.444505 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9172 01:02:12.447678 DUMMY_READ_FOR_TRACKING: OFF
9173 01:02:12.447761 !!! SPM_CONTROL_AFTERK: OFF
9174 01:02:12.451008 !!! SPM could not control APHY
9175 01:02:12.454429 IMPEDANCE_TRACKING: ON
9176 01:02:12.454511 TEMP_SENSOR: ON
9177 01:02:12.457764 HW_SAVE_FOR_SR: OFF
9178 01:02:12.460902 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9179 01:02:12.464806 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9180 01:02:12.464897 Read ODT Tracking: ON
9181 01:02:12.467961 Refresh Rate DeBounce: ON
9182 01:02:12.471090 DFS_NO_QUEUE_FLUSH: ON
9183 01:02:12.474582 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9184 01:02:12.474661 ENABLE_DFS_RUNTIME_MRW: OFF
9185 01:02:12.477686 DDR_RESERVE_NEW_MODE: ON
9186 01:02:12.480958 MR_CBT_SWITCH_FREQ: ON
9187 01:02:12.481041 =========================
9188 01:02:12.501586 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9189 01:02:12.504848 dram_init: ddr_geometry: 2
9190 01:02:12.523185 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9191 01:02:12.526512 dram_init: dram init end (result: 0)
9192 01:02:12.532912 DRAM-K: Full calibration passed in 24418 msecs
9193 01:02:12.535984 MRC: failed to locate region type 0.
9194 01:02:12.536061 DRAM rank0 size:0x100000000,
9195 01:02:12.539926 DRAM rank1 size=0x100000000
9196 01:02:12.549604 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9197 01:02:12.556177 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9198 01:02:12.562749 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9199 01:02:12.569585 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9200 01:02:12.572976 DRAM rank0 size:0x100000000,
9201 01:02:12.576186 DRAM rank1 size=0x100000000
9202 01:02:12.576258 CBMEM:
9203 01:02:12.579251 IMD: root @ 0xfffff000 254 entries.
9204 01:02:12.582773 IMD: root @ 0xffffec00 62 entries.
9205 01:02:12.585939 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9206 01:02:12.589146 WARNING: RO_VPD is uninitialized or empty.
9207 01:02:12.595852 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9208 01:02:12.603186 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9209 01:02:12.615514 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9210 01:02:12.627385 BS: romstage times (exec / console): total (unknown) / 23954 ms
9211 01:02:12.627466
9212 01:02:12.627531
9213 01:02:12.637240 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9214 01:02:12.640498 ARM64: Exception handlers installed.
9215 01:02:12.643505 ARM64: Testing exception
9216 01:02:12.647307 ARM64: Done test exception
9217 01:02:12.647381 Enumerating buses...
9218 01:02:12.650587 Show all devs... Before device enumeration.
9219 01:02:12.653560 Root Device: enabled 1
9220 01:02:12.656996 CPU_CLUSTER: 0: enabled 1
9221 01:02:12.657079 CPU: 00: enabled 1
9222 01:02:12.660581 Compare with tree...
9223 01:02:12.660652 Root Device: enabled 1
9224 01:02:12.663783 CPU_CLUSTER: 0: enabled 1
9225 01:02:12.667165 CPU: 00: enabled 1
9226 01:02:12.667237 Root Device scanning...
9227 01:02:12.670161 scan_static_bus for Root Device
9228 01:02:12.673745 CPU_CLUSTER: 0 enabled
9229 01:02:12.676779 scan_static_bus for Root Device done
9230 01:02:12.680243 scan_bus: bus Root Device finished in 8 msecs
9231 01:02:12.680381 done
9232 01:02:12.686969 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9233 01:02:12.690208 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9234 01:02:12.696950 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9235 01:02:12.700015 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9236 01:02:12.703091 Allocating resources...
9237 01:02:12.706866 Reading resources...
9238 01:02:12.709970 Root Device read_resources bus 0 link: 0
9239 01:02:12.710047 DRAM rank0 size:0x100000000,
9240 01:02:12.713431 DRAM rank1 size=0x100000000
9241 01:02:12.716459 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9242 01:02:12.720238 CPU: 00 missing read_resources
9243 01:02:12.723403 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9244 01:02:12.729748 Root Device read_resources bus 0 link: 0 done
9245 01:02:12.729830 Done reading resources.
9246 01:02:12.736653 Show resources in subtree (Root Device)...After reading.
9247 01:02:12.739799 Root Device child on link 0 CPU_CLUSTER: 0
9248 01:02:12.743186 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 01:02:12.753269 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 01:02:12.753372 CPU: 00
9251 01:02:12.756450 Root Device assign_resources, bus 0 link: 0
9252 01:02:12.759464 CPU_CLUSTER: 0 missing set_resources
9253 01:02:12.765998 Root Device assign_resources, bus 0 link: 0 done
9254 01:02:12.766077 Done setting resources.
9255 01:02:12.772865 Show resources in subtree (Root Device)...After assigning values.
9256 01:02:12.775931 Root Device child on link 0 CPU_CLUSTER: 0
9257 01:02:12.779468 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 01:02:12.789495 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 01:02:12.789599 CPU: 00
9260 01:02:12.792953 Done allocating resources.
9261 01:02:12.796411 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9262 01:02:12.799262 Enabling resources...
9263 01:02:12.799365 done.
9264 01:02:12.806157 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9265 01:02:12.806233 Initializing devices...
9266 01:02:12.809434 Root Device init
9267 01:02:12.809511 init hardware done!
9268 01:02:12.812776 0x00000018: ctrlr->caps
9269 01:02:12.815904 52.000 MHz: ctrlr->f_max
9270 01:02:12.816010 0.400 MHz: ctrlr->f_min
9271 01:02:12.819589 0x40ff8080: ctrlr->voltages
9272 01:02:12.819700 sclk: 390625
9273 01:02:12.822562 Bus Width = 1
9274 01:02:12.822640 sclk: 390625
9275 01:02:12.826124 Bus Width = 1
9276 01:02:12.826207 Early init status = 3
9277 01:02:12.832569 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9278 01:02:12.835832 in-header: 03 fc 00 00 01 00 00 00
9279 01:02:12.839306 in-data: 00
9280 01:02:12.842544 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9281 01:02:12.847790 in-header: 03 fd 00 00 00 00 00 00
9282 01:02:12.851411 in-data:
9283 01:02:12.854563 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9284 01:02:12.859005 in-header: 03 fc 00 00 01 00 00 00
9285 01:02:12.862140 in-data: 00
9286 01:02:12.865261 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9287 01:02:12.871045 in-header: 03 fd 00 00 00 00 00 00
9288 01:02:12.874102 in-data:
9289 01:02:12.877444 [SSUSB] Setting up USB HOST controller...
9290 01:02:12.880756 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9291 01:02:12.884509 [SSUSB] phy power-on done.
9292 01:02:12.887474 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9293 01:02:12.894389 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9294 01:02:12.897874 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9295 01:02:12.904462 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9296 01:02:12.911188 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9297 01:02:12.917652 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9298 01:02:12.924242 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9299 01:02:12.930989 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9300 01:02:12.931096 SPM: binary array size = 0x9dc
9301 01:02:12.937803 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9302 01:02:12.944505 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9303 01:02:12.951284 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9304 01:02:12.954346 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9305 01:02:12.957455 configure_display: Starting display init
9306 01:02:12.994617 anx7625_power_on_init: Init interface.
9307 01:02:12.997541 anx7625_disable_pd_protocol: Disabled PD feature.
9308 01:02:13.000775 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9309 01:02:13.028907 anx7625_start_dp_work: Secure OCM version=00
9310 01:02:13.032068 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9311 01:02:13.046953 sp_tx_get_edid_block: EDID Block = 1
9312 01:02:13.149332 Extracted contents:
9313 01:02:13.152934 header: 00 ff ff ff ff ff ff 00
9314 01:02:13.156012 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9315 01:02:13.159112 version: 01 04
9316 01:02:13.162794 basic params: 95 1f 11 78 0a
9317 01:02:13.165814 chroma info: 76 90 94 55 54 90 27 21 50 54
9318 01:02:13.169543 established: 00 00 00
9319 01:02:13.175952 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9320 01:02:13.179078 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9321 01:02:13.186386 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 01:02:13.192710 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9323 01:02:13.199454 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9324 01:02:13.202968 extensions: 00
9325 01:02:13.203072 checksum: fb
9326 01:02:13.203171
9327 01:02:13.205818 Manufacturer: IVO Model 57d Serial Number 0
9328 01:02:13.209367 Made week 0 of 2020
9329 01:02:13.209447 EDID version: 1.4
9330 01:02:13.212327 Digital display
9331 01:02:13.216081 6 bits per primary color channel
9332 01:02:13.216157 DisplayPort interface
9333 01:02:13.219255 Maximum image size: 31 cm x 17 cm
9334 01:02:13.222405 Gamma: 220%
9335 01:02:13.222502 Check DPMS levels
9336 01:02:13.226059 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9337 01:02:13.229268 First detailed timing is preferred timing
9338 01:02:13.232406 Established timings supported:
9339 01:02:13.235734 Standard timings supported:
9340 01:02:13.235832 Detailed timings
9341 01:02:13.242270 Hex of detail: 383680a07038204018303c0035ae10000019
9342 01:02:13.245527 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9343 01:02:13.252559 0780 0798 07c8 0820 hborder 0
9344 01:02:13.256149 0438 043b 0447 0458 vborder 0
9345 01:02:13.258920 -hsync -vsync
9346 01:02:13.259099 Did detailed timing
9347 01:02:13.262100 Hex of detail: 000000000000000000000000000000000000
9348 01:02:13.265908 Manufacturer-specified data, tag 0
9349 01:02:13.272198 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9350 01:02:13.272343 ASCII string: InfoVision
9351 01:02:13.279207 Hex of detail: 000000fe00523134304e574635205248200a
9352 01:02:13.282468 ASCII string: R140NWF5 RH
9353 01:02:13.282569 Checksum
9354 01:02:13.282661 Checksum: 0xfb (valid)
9355 01:02:13.288752 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9356 01:02:13.292240 DSI data_rate: 832800000 bps
9357 01:02:13.298604 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9358 01:02:13.301776 anx7625_parse_edid: pixelclock(138800).
9359 01:02:13.305362 hactive(1920), hsync(48), hfp(24), hbp(88)
9360 01:02:13.308801 vactive(1080), vsync(12), vfp(3), vbp(17)
9361 01:02:13.311957 anx7625_dsi_config: config dsi.
9362 01:02:13.318265 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9363 01:02:13.331616 anx7625_dsi_config: success to config DSI
9364 01:02:13.334704 anx7625_dp_start: MIPI phy setup OK.
9365 01:02:13.338232 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9366 01:02:13.341194 mtk_ddp_mode_set invalid vrefresh 60
9367 01:02:13.344758 main_disp_path_setup
9368 01:02:13.344838 ovl_layer_smi_id_en
9369 01:02:13.347964 ovl_layer_smi_id_en
9370 01:02:13.348067 ccorr_config
9371 01:02:13.348171 aal_config
9372 01:02:13.351153 gamma_config
9373 01:02:13.351251 postmask_config
9374 01:02:13.354483 dither_config
9375 01:02:13.357612 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9376 01:02:13.364183 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9377 01:02:13.367756 Root Device init finished in 555 msecs
9378 01:02:13.370810 CPU_CLUSTER: 0 init
9379 01:02:13.377986 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9380 01:02:13.381238 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9381 01:02:13.384301 APU_MBOX 0x190000b0 = 0x10001
9382 01:02:13.387569 APU_MBOX 0x190001b0 = 0x10001
9383 01:02:13.391431 APU_MBOX 0x190005b0 = 0x10001
9384 01:02:13.394671 APU_MBOX 0x190006b0 = 0x10001
9385 01:02:13.397897 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9386 01:02:13.410378 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9387 01:02:13.422620 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9388 01:02:13.429446 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9389 01:02:13.441254 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9390 01:02:13.450129 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9391 01:02:13.453460 CPU_CLUSTER: 0 init finished in 81 msecs
9392 01:02:13.456863 Devices initialized
9393 01:02:13.460208 Show all devs... After init.
9394 01:02:13.460313 Root Device: enabled 1
9395 01:02:13.463471 CPU_CLUSTER: 0: enabled 1
9396 01:02:13.467025 CPU: 00: enabled 1
9397 01:02:13.470399 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9398 01:02:13.473454 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9399 01:02:13.476835 ELOG: NV offset 0x57f000 size 0x1000
9400 01:02:13.483450 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9401 01:02:13.490009 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9402 01:02:13.493123 ELOG: Event(17) added with size 13 at 2024-01-19 00:59:34 UTC
9403 01:02:13.496423 out: cmd=0x121: 03 db 21 01 00 00 00 00
9404 01:02:13.500476 in-header: 03 04 00 00 2c 00 00 00
9405 01:02:13.513765 in-data: 5b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9406 01:02:13.520479 ELOG: Event(A1) added with size 10 at 2024-01-19 00:59:34 UTC
9407 01:02:13.527152 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9408 01:02:13.533494 ELOG: Event(A0) added with size 9 at 2024-01-19 00:59:34 UTC
9409 01:02:13.537251 elog_add_boot_reason: Logged dev mode boot
9410 01:02:13.540386 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9411 01:02:13.543578 Finalize devices...
9412 01:02:13.543655 Devices finalized
9413 01:02:13.550033 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9414 01:02:13.553399 Writing coreboot table at 0xffe64000
9415 01:02:13.556703 0. 000000000010a000-0000000000113fff: RAMSTAGE
9416 01:02:13.560241 1. 0000000040000000-00000000400fffff: RAM
9417 01:02:13.563459 2. 0000000040100000-000000004032afff: RAMSTAGE
9418 01:02:13.570074 3. 000000004032b000-00000000545fffff: RAM
9419 01:02:13.573722 4. 0000000054600000-000000005465ffff: BL31
9420 01:02:13.576658 5. 0000000054660000-00000000ffe63fff: RAM
9421 01:02:13.580223 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9422 01:02:13.586887 7. 0000000100000000-000000023fffffff: RAM
9423 01:02:13.586968 Passing 5 GPIOs to payload:
9424 01:02:13.593497 NAME | PORT | POLARITY | VALUE
9425 01:02:13.596448 EC in RW | 0x000000aa | low | undefined
9426 01:02:13.603249 EC interrupt | 0x00000005 | low | undefined
9427 01:02:13.606918 TPM interrupt | 0x000000ab | high | undefined
9428 01:02:13.610164 SD card detect | 0x00000011 | high | undefined
9429 01:02:13.616686 speaker enable | 0x00000093 | high | undefined
9430 01:02:13.619900 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9431 01:02:13.623006 in-header: 03 f9 00 00 02 00 00 00
9432 01:02:13.623116 in-data: 02 00
9433 01:02:13.626767 ADC[4]: Raw value=905096 ID=7
9434 01:02:13.629749 ADC[3]: Raw value=213441 ID=1
9435 01:02:13.629850 RAM Code: 0x71
9436 01:02:13.633132 ADC[6]: Raw value=75701 ID=0
9437 01:02:13.636441 ADC[5]: Raw value=212703 ID=1
9438 01:02:13.636544 SKU Code: 0x1
9439 01:02:13.643357 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4709
9440 01:02:13.646135 coreboot table: 964 bytes.
9441 01:02:13.649582 IMD ROOT 0. 0xfffff000 0x00001000
9442 01:02:13.653293 IMD SMALL 1. 0xffffe000 0x00001000
9443 01:02:13.656502 RO MCACHE 2. 0xffffc000 0x00001104
9444 01:02:13.659769 CONSOLE 3. 0xfff7c000 0x00080000
9445 01:02:13.663014 FMAP 4. 0xfff7b000 0x00000452
9446 01:02:13.666281 TIME STAMP 5. 0xfff7a000 0x00000910
9447 01:02:13.669454 VBOOT WORK 6. 0xfff66000 0x00014000
9448 01:02:13.673272 RAMOOPS 7. 0xffe66000 0x00100000
9449 01:02:13.676469 COREBOOT 8. 0xffe64000 0x00002000
9450 01:02:13.676538 IMD small region:
9451 01:02:13.679656 IMD ROOT 0. 0xffffec00 0x00000400
9452 01:02:13.682891 VPD 1. 0xffffeb80 0x0000006c
9453 01:02:13.686660 MMC STATUS 2. 0xffffeb60 0x00000004
9454 01:02:13.692937 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9455 01:02:13.696363 Probing TPM: done!
9456 01:02:13.699610 Connected to device vid:did:rid of 1ae0:0028:00
9457 01:02:13.709747 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9458 01:02:13.713618 Initialized TPM device CR50 revision 0
9459 01:02:13.716583 Checking cr50 for pending updates
9460 01:02:13.720079 Reading cr50 TPM mode
9461 01:02:13.728905 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9462 01:02:13.735412 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9463 01:02:13.775240 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9464 01:02:13.779120 Checking segment from ROM address 0x40100000
9465 01:02:13.782435 Checking segment from ROM address 0x4010001c
9466 01:02:13.788930 Loading segment from ROM address 0x40100000
9467 01:02:13.789011 code (compression=0)
9468 01:02:13.795750 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9469 01:02:13.805486 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9470 01:02:13.805568 it's not compressed!
9471 01:02:13.812369 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9472 01:02:13.815648 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9473 01:02:13.835631 Loading segment from ROM address 0x4010001c
9474 01:02:13.835716 Entry Point 0x80000000
9475 01:02:13.839065 Loaded segments
9476 01:02:13.842359 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9477 01:02:13.849179 Jumping to boot code at 0x80000000(0xffe64000)
9478 01:02:13.856131 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9479 01:02:13.862763 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9480 01:02:13.870593 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9481 01:02:13.873902 Checking segment from ROM address 0x40100000
9482 01:02:13.876816 Checking segment from ROM address 0x4010001c
9483 01:02:13.883929 Loading segment from ROM address 0x40100000
9484 01:02:13.884011 code (compression=1)
9485 01:02:13.890262 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9486 01:02:13.900471 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9487 01:02:13.900553 using LZMA
9488 01:02:13.908517 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9489 01:02:13.915311 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9490 01:02:13.918299 Loading segment from ROM address 0x4010001c
9491 01:02:13.918381 Entry Point 0x54601000
9492 01:02:13.922110 Loaded segments
9493 01:02:13.925428 NOTICE: MT8192 bl31_setup
9494 01:02:13.932213 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9495 01:02:13.935999 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9496 01:02:13.939273 WARNING: region 0:
9497 01:02:13.942456 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 01:02:13.942537 WARNING: region 1:
9499 01:02:13.949380 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9500 01:02:13.952281 WARNING: region 2:
9501 01:02:13.955671 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9502 01:02:13.959189 WARNING: region 3:
9503 01:02:13.962678 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 01:02:13.965702 WARNING: region 4:
9505 01:02:13.969213 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 01:02:13.972298 WARNING: region 5:
9507 01:02:13.975554 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 01:02:13.979090 WARNING: region 6:
9509 01:02:13.982903 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 01:02:13.982984 WARNING: region 7:
9511 01:02:13.989021 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 01:02:13.996101 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9513 01:02:13.999350 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9514 01:02:14.002728 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9515 01:02:14.009565 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9516 01:02:14.012689 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9517 01:02:14.015651 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9518 01:02:14.022414 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9519 01:02:14.025673 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9520 01:02:14.028918 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9521 01:02:14.035893 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9522 01:02:14.038960 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9523 01:02:14.046373 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9524 01:02:14.049218 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9525 01:02:14.052743 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9526 01:02:14.059530 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9527 01:02:14.062626 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9528 01:02:14.066126 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9529 01:02:14.072562 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9530 01:02:14.075684 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9531 01:02:14.079112 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9532 01:02:14.085775 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9533 01:02:14.089423 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9534 01:02:14.095984 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9535 01:02:14.099627 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9536 01:02:14.102745 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9537 01:02:14.109734 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9538 01:02:14.112790 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9539 01:02:14.119139 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9540 01:02:14.122779 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9541 01:02:14.126248 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9542 01:02:14.132667 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9543 01:02:14.135877 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9544 01:02:14.139097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9545 01:02:14.146008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9546 01:02:14.149257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9547 01:02:14.153013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9548 01:02:14.156127 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9549 01:02:14.162596 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9550 01:02:14.166199 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9551 01:02:14.169495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9552 01:02:14.172612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9553 01:02:14.179505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9554 01:02:14.183202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9555 01:02:14.186120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9556 01:02:14.189239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9557 01:02:14.196124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9558 01:02:14.199471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9559 01:02:14.202930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9560 01:02:14.209562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9561 01:02:14.212475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9562 01:02:14.216113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9563 01:02:14.222479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9564 01:02:14.226151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9565 01:02:14.232674 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9566 01:02:14.236435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9567 01:02:14.242937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9568 01:02:14.246626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9569 01:02:14.249841 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9570 01:02:14.256221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9571 01:02:14.259631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9572 01:02:14.266406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9573 01:02:14.269919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9574 01:02:14.276162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9575 01:02:14.279458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9576 01:02:14.283123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9577 01:02:14.289757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9578 01:02:14.292952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9579 01:02:14.299805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9580 01:02:14.303110 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9581 01:02:14.306361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9582 01:02:14.312968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9583 01:02:14.316449 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9584 01:02:14.323083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9585 01:02:14.326256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9586 01:02:14.333165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9587 01:02:14.336494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9588 01:02:14.340077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9589 01:02:14.347021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9590 01:02:14.350117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9591 01:02:14.356512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9592 01:02:14.360200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9593 01:02:14.366777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9594 01:02:14.369848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9595 01:02:14.373566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9596 01:02:14.379978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9597 01:02:14.383540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9598 01:02:14.389932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9599 01:02:14.393178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9600 01:02:14.400138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9601 01:02:14.403081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9602 01:02:14.406982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9603 01:02:14.413230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9604 01:02:14.417051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9605 01:02:14.423725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9606 01:02:14.426736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9607 01:02:14.433663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9608 01:02:14.436626 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9609 01:02:14.440080 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9610 01:02:14.443469 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9611 01:02:14.450647 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9612 01:02:14.453563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9613 01:02:14.456762 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9614 01:02:14.463512 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9615 01:02:14.467133 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9616 01:02:14.473688 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9617 01:02:14.476794 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9618 01:02:14.480530 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9619 01:02:14.487054 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9620 01:02:14.490479 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9621 01:02:14.493608 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9622 01:02:14.500560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9623 01:02:14.503921 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9624 01:02:14.510066 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9625 01:02:14.513251 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9626 01:02:14.517021 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9627 01:02:14.523650 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9628 01:02:14.527206 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9629 01:02:14.530264 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9630 01:02:14.536920 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9631 01:02:14.540171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9632 01:02:14.543964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9633 01:02:14.547205 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9634 01:02:14.553585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9635 01:02:14.557165 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9636 01:02:14.560090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9637 01:02:14.567235 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9638 01:02:14.570601 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9639 01:02:14.573910 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9640 01:02:14.580377 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9641 01:02:14.583808 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9642 01:02:14.590113 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9643 01:02:14.593658 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9644 01:02:14.597131 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9645 01:02:14.603927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9646 01:02:14.607197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9647 01:02:14.610309 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9648 01:02:14.616968 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9649 01:02:14.620633 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9650 01:02:14.627571 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9651 01:02:14.630697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9652 01:02:14.634024 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9653 01:02:14.640744 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9654 01:02:14.643699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9655 01:02:14.650622 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9656 01:02:14.653871 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9657 01:02:14.657177 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9658 01:02:14.663852 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9659 01:02:14.666923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9660 01:02:14.670705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9661 01:02:14.676950 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9662 01:02:14.680171 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9663 01:02:14.687495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9664 01:02:14.690294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9665 01:02:14.694085 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9666 01:02:14.700497 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9667 01:02:14.703835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9668 01:02:14.710696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9669 01:02:14.714239 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9670 01:02:14.717389 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9671 01:02:14.724159 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9672 01:02:14.727206 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9673 01:02:14.730441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9674 01:02:14.737500 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9675 01:02:14.740705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9676 01:02:14.747083 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9677 01:02:14.750682 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9678 01:02:14.753803 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9679 01:02:14.760122 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9680 01:02:14.763926 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9681 01:02:14.770139 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9682 01:02:14.773871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9683 01:02:14.776852 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9684 01:02:14.783818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9685 01:02:14.786980 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9686 01:02:14.790265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9687 01:02:14.797262 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9688 01:02:14.800392 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9689 01:02:14.806720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9690 01:02:14.810469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9691 01:02:14.813428 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9692 01:02:14.820193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9693 01:02:14.823479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9694 01:02:14.830391 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9695 01:02:14.833504 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9696 01:02:14.837207 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9697 01:02:14.843834 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9698 01:02:14.846948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9699 01:02:14.853314 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9700 01:02:14.856723 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9701 01:02:14.860108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9702 01:02:14.866854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9703 01:02:14.870081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9704 01:02:14.876821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9705 01:02:14.880047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9706 01:02:14.883196 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9707 01:02:14.890283 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9708 01:02:14.893453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9709 01:02:14.899826 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9710 01:02:14.903627 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9711 01:02:14.909828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9712 01:02:14.913079 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9713 01:02:14.916925 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9714 01:02:14.923248 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9715 01:02:14.926919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9716 01:02:14.933144 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9717 01:02:14.936844 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9718 01:02:14.940517 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9719 01:02:14.946691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9720 01:02:14.949914 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9721 01:02:14.956497 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9722 01:02:14.959790 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9723 01:02:14.966388 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9724 01:02:14.969544 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9725 01:02:14.973243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9726 01:02:14.979451 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9727 01:02:14.983079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9728 01:02:14.989842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9729 01:02:14.993333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9730 01:02:14.999577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9731 01:02:15.002815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9732 01:02:15.006025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9733 01:02:15.012791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9734 01:02:15.015871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9735 01:02:15.022385 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9736 01:02:15.025715 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9737 01:02:15.028980 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9738 01:02:15.036116 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9739 01:02:15.039341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9740 01:02:15.045685 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9741 01:02:15.048941 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9742 01:02:15.052752 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9743 01:02:15.055892 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9744 01:02:15.062605 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9745 01:02:15.065479 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9746 01:02:15.068932 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9747 01:02:15.075498 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9748 01:02:15.078820 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9749 01:02:15.082674 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9750 01:02:15.089020 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9751 01:02:15.091920 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9752 01:02:15.095219 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9753 01:02:15.101751 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9754 01:02:15.105394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9755 01:02:15.108962 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9756 01:02:15.115104 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9757 01:02:15.118787 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9758 01:02:15.125187 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9759 01:02:15.128335 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9760 01:02:15.131596 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9761 01:02:15.138454 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9762 01:02:15.141879 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9763 01:02:15.148760 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9764 01:02:15.152048 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9765 01:02:15.155264 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9766 01:02:15.161668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9767 01:02:15.164908 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9768 01:02:15.168720 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9769 01:02:15.175122 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9770 01:02:15.178322 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9771 01:02:15.181911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9772 01:02:15.188256 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9773 01:02:15.191521 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9774 01:02:15.198327 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9775 01:02:15.201522 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9776 01:02:15.204988 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9777 01:02:15.211496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9778 01:02:15.214767 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9779 01:02:15.218365 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9780 01:02:15.224937 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9781 01:02:15.228054 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9782 01:02:15.231483 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9783 01:02:15.234909 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9784 01:02:15.238224 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9785 01:02:15.244942 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9786 01:02:15.248491 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9787 01:02:15.251807 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9788 01:02:15.255197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9789 01:02:15.261762 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9790 01:02:15.265026 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9791 01:02:15.268187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9792 01:02:15.274599 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9793 01:02:15.278153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9794 01:02:15.281657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9795 01:02:15.287805 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9796 01:02:15.291528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9797 01:02:15.297760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9798 01:02:15.300972 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9799 01:02:15.304531 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9800 01:02:15.311007 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9801 01:02:15.314371 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9802 01:02:15.321375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9803 01:02:15.324542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9804 01:02:15.327589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9805 01:02:15.334563 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9806 01:02:15.338033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9807 01:02:15.344527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9808 01:02:15.347879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9809 01:02:15.350918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9810 01:02:15.357526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9811 01:02:15.361156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9812 01:02:15.367802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9813 01:02:15.370698 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9814 01:02:15.377380 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9815 01:02:15.381209 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9816 01:02:15.384337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9817 01:02:15.390668 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9818 01:02:15.394286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9819 01:02:15.400930 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9820 01:02:15.404162 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9821 01:02:15.407332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9822 01:02:15.414104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9823 01:02:15.417276 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9824 01:02:15.423749 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9825 01:02:15.427611 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9826 01:02:15.430567 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9827 01:02:15.437038 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9828 01:02:15.440723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9829 01:02:15.447312 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9830 01:02:15.450561 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9831 01:02:15.453694 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9832 01:02:15.460652 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9833 01:02:15.463791 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9834 01:02:15.470426 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9835 01:02:15.473815 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9836 01:02:15.477077 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9837 01:02:15.483635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9838 01:02:15.487187 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9839 01:02:15.493946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9840 01:02:15.497094 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9841 01:02:15.500103 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9842 01:02:15.507181 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9843 01:02:15.510571 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9844 01:02:15.517214 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9845 01:02:15.520476 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9846 01:02:15.526836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9847 01:02:15.530100 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9848 01:02:15.534017 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9849 01:02:15.540632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9850 01:02:15.543757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9851 01:02:15.547230 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9852 01:02:15.553429 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9853 01:02:15.557328 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9854 01:02:15.563824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9855 01:02:15.566944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9856 01:02:15.573294 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9857 01:02:15.577116 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9858 01:02:15.580403 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9859 01:02:15.587114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9860 01:02:15.590295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9861 01:02:15.596585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9862 01:02:15.600137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9863 01:02:15.603578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9864 01:02:15.610049 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9865 01:02:15.613427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9866 01:02:15.620111 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9867 01:02:15.623068 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9868 01:02:15.629843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9869 01:02:15.633392 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9870 01:02:15.636415 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9871 01:02:15.643232 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9872 01:02:15.646329 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9873 01:02:15.653165 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9874 01:02:15.656506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9875 01:02:15.663397 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9876 01:02:15.666633 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9877 01:02:15.669816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9878 01:02:15.676113 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9879 01:02:15.679731 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9880 01:02:15.686109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9881 01:02:15.689327 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9882 01:02:15.696469 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9883 01:02:15.699684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9884 01:02:15.706627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9885 01:02:15.709302 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9886 01:02:15.713052 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9887 01:02:15.719534 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9888 01:02:15.722848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9889 01:02:15.729731 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9890 01:02:15.732677 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9891 01:02:15.739255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9892 01:02:15.742775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9893 01:02:15.746117 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9894 01:02:15.752795 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9895 01:02:15.756024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9896 01:02:15.762260 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9897 01:02:15.765808 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9898 01:02:15.772244 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9899 01:02:15.775908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9900 01:02:15.782523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9901 01:02:15.785543 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9902 01:02:15.788743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9903 01:02:15.795747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9904 01:02:15.798795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9905 01:02:15.805767 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9906 01:02:15.808926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9907 01:02:15.815818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9908 01:02:15.818869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9909 01:02:15.822185 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9910 01:02:15.828551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9911 01:02:15.832332 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9912 01:02:15.838755 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9913 01:02:15.841838 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9914 01:02:15.845580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9915 01:02:15.851743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9916 01:02:15.855522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9917 01:02:15.861715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9918 01:02:15.865516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9919 01:02:15.871823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9920 01:02:15.874983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9921 01:02:15.881610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9922 01:02:15.885181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9923 01:02:15.892043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9924 01:02:15.895461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9925 01:02:15.901908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9926 01:02:15.905265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9927 01:02:15.911801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9928 01:02:15.915108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9929 01:02:15.921977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9930 01:02:15.925064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9931 01:02:15.928434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9932 01:02:15.935475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9933 01:02:15.938763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9934 01:02:15.945197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9935 01:02:15.948231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9936 01:02:15.954838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9937 01:02:15.958219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9938 01:02:15.965148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9939 01:02:15.971511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9940 01:02:15.975227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9941 01:02:15.978447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9942 01:02:15.985189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9943 01:02:15.988396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9944 01:02:15.994762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9945 01:02:15.998637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9946 01:02:16.005016 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9947 01:02:16.005101 INFO: [APUAPC] vio 0
9948 01:02:16.011942 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9949 01:02:16.015694 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9950 01:02:16.018817 INFO: [APUAPC] D0_APC_0: 0x400510
9951 01:02:16.022237 INFO: [APUAPC] D0_APC_1: 0x0
9952 01:02:16.025456 INFO: [APUAPC] D0_APC_2: 0x1540
9953 01:02:16.028910 INFO: [APUAPC] D0_APC_3: 0x0
9954 01:02:16.031939 INFO: [APUAPC] D1_APC_0: 0xffffffff
9955 01:02:16.035260 INFO: [APUAPC] D1_APC_1: 0xffffffff
9956 01:02:16.038656 INFO: [APUAPC] D1_APC_2: 0x3fffff
9957 01:02:16.042152 INFO: [APUAPC] D1_APC_3: 0x0
9958 01:02:16.045733 INFO: [APUAPC] D2_APC_0: 0xffffffff
9959 01:02:16.048501 INFO: [APUAPC] D2_APC_1: 0xffffffff
9960 01:02:16.052158 INFO: [APUAPC] D2_APC_2: 0x3fffff
9961 01:02:16.055228 INFO: [APUAPC] D2_APC_3: 0x0
9962 01:02:16.059031 INFO: [APUAPC] D3_APC_0: 0xffffffff
9963 01:02:16.062132 INFO: [APUAPC] D3_APC_1: 0xffffffff
9964 01:02:16.065133 INFO: [APUAPC] D3_APC_2: 0x3fffff
9965 01:02:16.065212 INFO: [APUAPC] D3_APC_3: 0x0
9966 01:02:16.072090 INFO: [APUAPC] D4_APC_0: 0xffffffff
9967 01:02:16.075199 INFO: [APUAPC] D4_APC_1: 0xffffffff
9968 01:02:16.078968 INFO: [APUAPC] D4_APC_2: 0x3fffff
9969 01:02:16.079050 INFO: [APUAPC] D4_APC_3: 0x0
9970 01:02:16.082096 INFO: [APUAPC] D5_APC_0: 0xffffffff
9971 01:02:16.085367 INFO: [APUAPC] D5_APC_1: 0xffffffff
9972 01:02:16.088481 INFO: [APUAPC] D5_APC_2: 0x3fffff
9973 01:02:16.092237 INFO: [APUAPC] D5_APC_3: 0x0
9974 01:02:16.095284 INFO: [APUAPC] D6_APC_0: 0xffffffff
9975 01:02:16.098491 INFO: [APUAPC] D6_APC_1: 0xffffffff
9976 01:02:16.102232 INFO: [APUAPC] D6_APC_2: 0x3fffff
9977 01:02:16.104952 INFO: [APUAPC] D6_APC_3: 0x0
9978 01:02:16.108731 INFO: [APUAPC] D7_APC_0: 0xffffffff
9979 01:02:16.112010 INFO: [APUAPC] D7_APC_1: 0xffffffff
9980 01:02:16.115252 INFO: [APUAPC] D7_APC_2: 0x3fffff
9981 01:02:16.118485 INFO: [APUAPC] D7_APC_3: 0x0
9982 01:02:16.121620 INFO: [APUAPC] D8_APC_0: 0xffffffff
9983 01:02:16.125304 INFO: [APUAPC] D8_APC_1: 0xffffffff
9984 01:02:16.128605 INFO: [APUAPC] D8_APC_2: 0x3fffff
9985 01:02:16.131860 INFO: [APUAPC] D8_APC_3: 0x0
9986 01:02:16.135070 INFO: [APUAPC] D9_APC_0: 0xffffffff
9987 01:02:16.138304 INFO: [APUAPC] D9_APC_1: 0xffffffff
9988 01:02:16.141839 INFO: [APUAPC] D9_APC_2: 0x3fffff
9989 01:02:16.144867 INFO: [APUAPC] D9_APC_3: 0x0
9990 01:02:16.148260 INFO: [APUAPC] D10_APC_0: 0xffffffff
9991 01:02:16.151648 INFO: [APUAPC] D10_APC_1: 0xffffffff
9992 01:02:16.154720 INFO: [APUAPC] D10_APC_2: 0x3fffff
9993 01:02:16.158525 INFO: [APUAPC] D10_APC_3: 0x0
9994 01:02:16.161376 INFO: [APUAPC] D11_APC_0: 0xffffffff
9995 01:02:16.164834 INFO: [APUAPC] D11_APC_1: 0xffffffff
9996 01:02:16.167930 INFO: [APUAPC] D11_APC_2: 0x3fffff
9997 01:02:16.171227 INFO: [APUAPC] D11_APC_3: 0x0
9998 01:02:16.174604 INFO: [APUAPC] D12_APC_0: 0xffffffff
9999 01:02:16.177819 INFO: [APUAPC] D12_APC_1: 0xffffffff
10000 01:02:16.181179 INFO: [APUAPC] D12_APC_2: 0x3fffff
10001 01:02:16.184556 INFO: [APUAPC] D12_APC_3: 0x0
10002 01:02:16.188260 INFO: [APUAPC] D13_APC_0: 0xffffffff
10003 01:02:16.191087 INFO: [APUAPC] D13_APC_1: 0xffffffff
10004 01:02:16.194489 INFO: [APUAPC] D13_APC_2: 0x3fffff
10005 01:02:16.198005 INFO: [APUAPC] D13_APC_3: 0x0
10006 01:02:16.201469 INFO: [APUAPC] D14_APC_0: 0xffffffff
10007 01:02:16.204243 INFO: [APUAPC] D14_APC_1: 0xffffffff
10008 01:02:16.207572 INFO: [APUAPC] D14_APC_2: 0x3fffff
10009 01:02:16.211420 INFO: [APUAPC] D14_APC_3: 0x0
10010 01:02:16.214636 INFO: [APUAPC] D15_APC_0: 0xffffffff
10011 01:02:16.217859 INFO: [APUAPC] D15_APC_1: 0xffffffff
10012 01:02:16.221188 INFO: [APUAPC] D15_APC_2: 0x3fffff
10013 01:02:16.224438 INFO: [APUAPC] D15_APC_3: 0x0
10014 01:02:16.227596 INFO: [APUAPC] APC_CON: 0x4
10015 01:02:16.231537 INFO: [NOCDAPC] D0_APC_0: 0x0
10016 01:02:16.234684 INFO: [NOCDAPC] D0_APC_1: 0x0
10017 01:02:16.237943 INFO: [NOCDAPC] D1_APC_0: 0x0
10018 01:02:16.241209 INFO: [NOCDAPC] D1_APC_1: 0xfff
10019 01:02:16.244249 INFO: [NOCDAPC] D2_APC_0: 0x0
10020 01:02:16.244380 INFO: [NOCDAPC] D2_APC_1: 0xfff
10021 01:02:16.247495 INFO: [NOCDAPC] D3_APC_0: 0x0
10022 01:02:16.250821 INFO: [NOCDAPC] D3_APC_1: 0xfff
10023 01:02:16.254089 INFO: [NOCDAPC] D4_APC_0: 0x0
10024 01:02:16.257388 INFO: [NOCDAPC] D4_APC_1: 0xfff
10025 01:02:16.261206 INFO: [NOCDAPC] D5_APC_0: 0x0
10026 01:02:16.264274 INFO: [NOCDAPC] D5_APC_1: 0xfff
10027 01:02:16.267782 INFO: [NOCDAPC] D6_APC_0: 0x0
10028 01:02:16.270752 INFO: [NOCDAPC] D6_APC_1: 0xfff
10029 01:02:16.274211 INFO: [NOCDAPC] D7_APC_0: 0x0
10030 01:02:16.277720 INFO: [NOCDAPC] D7_APC_1: 0xfff
10031 01:02:16.277794 INFO: [NOCDAPC] D8_APC_0: 0x0
10032 01:02:16.280888 INFO: [NOCDAPC] D8_APC_1: 0xfff
10033 01:02:16.283962 INFO: [NOCDAPC] D9_APC_0: 0x0
10034 01:02:16.287687 INFO: [NOCDAPC] D9_APC_1: 0xfff
10035 01:02:16.290689 INFO: [NOCDAPC] D10_APC_0: 0x0
10036 01:02:16.294098 INFO: [NOCDAPC] D10_APC_1: 0xfff
10037 01:02:16.297295 INFO: [NOCDAPC] D11_APC_0: 0x0
10038 01:02:16.300787 INFO: [NOCDAPC] D11_APC_1: 0xfff
10039 01:02:16.303794 INFO: [NOCDAPC] D12_APC_0: 0x0
10040 01:02:16.307195 INFO: [NOCDAPC] D12_APC_1: 0xfff
10041 01:02:16.310865 INFO: [NOCDAPC] D13_APC_0: 0x0
10042 01:02:16.313865 INFO: [NOCDAPC] D13_APC_1: 0xfff
10043 01:02:16.317119 INFO: [NOCDAPC] D14_APC_0: 0x0
10044 01:02:16.320445 INFO: [NOCDAPC] D14_APC_1: 0xfff
10045 01:02:16.320518 INFO: [NOCDAPC] D15_APC_0: 0x0
10046 01:02:16.323664 INFO: [NOCDAPC] D15_APC_1: 0xfff
10047 01:02:16.327186 INFO: [NOCDAPC] APC_CON: 0x4
10048 01:02:16.330496 INFO: [APUAPC] set_apusys_apc done
10049 01:02:16.333545 INFO: [DEVAPC] devapc_init done
10050 01:02:16.337356 INFO: GICv3 without legacy support detected.
10051 01:02:16.343671 INFO: ARM GICv3 driver initialized in EL3
10052 01:02:16.346867 INFO: Maximum SPI INTID supported: 639
10053 01:02:16.350740 INFO: BL31: Initializing runtime services
10054 01:02:16.357412 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10055 01:02:16.360542 INFO: SPM: enable CPC mode
10056 01:02:16.363777 INFO: mcdi ready for mcusys-off-idle and system suspend
10057 01:02:16.370031 INFO: BL31: Preparing for EL3 exit to normal world
10058 01:02:16.373810 INFO: Entry point address = 0x80000000
10059 01:02:16.373886 INFO: SPSR = 0x8
10060 01:02:16.380416
10061 01:02:16.380487
10062 01:02:16.380552
10063 01:02:16.383550 Starting depthcharge on Spherion...
10064 01:02:16.383627
10065 01:02:16.383689 Wipe memory regions:
10066 01:02:16.383748
10067 01:02:16.384538 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10068 01:02:16.384639 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10069 01:02:16.384724 Setting prompt string to ['asurada:']
10070 01:02:16.384810 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10071 01:02:16.386875 [0x00000040000000, 0x00000054600000)
10072 01:02:16.508907
10073 01:02:16.509058 [0x00000054660000, 0x00000080000000)
10074 01:02:16.769820
10075 01:02:16.769982 [0x000000821a7280, 0x000000ffe64000)
10076 01:02:17.514694
10077 01:02:17.514858 [0x00000100000000, 0x00000240000000)
10078 01:02:19.405151
10079 01:02:19.408447 Initializing XHCI USB controller at 0x11200000.
10080 01:02:20.445952
10081 01:02:20.448993 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10082 01:02:20.449248
10083 01:02:20.449441
10084 01:02:20.449653
10085 01:02:20.450156 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10087 01:02:20.550867 asurada: tftpboot 192.168.201.1 12571086/tftp-deploy-gwbojakf/kernel/image.itb 12571086/tftp-deploy-gwbojakf/kernel/cmdline
10088 01:02:20.551147 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 01:02:20.551347 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10090 01:02:20.555173 tftpboot 192.168.201.1 12571086/tftp-deploy-gwbojakf/kernel/image.ittp-deploy-gwbojakf/kernel/cmdline
10091 01:02:20.555369
10092 01:02:20.555533 Waiting for link
10093 01:02:20.715721
10094 01:02:20.715971 R8152: Initializing
10095 01:02:20.716134
10096 01:02:20.719061 Version 9 (ocp_data = 6010)
10097 01:02:20.719263
10098 01:02:20.722329 R8152: Done initializing
10099 01:02:20.722532
10100 01:02:20.722692 Adding net device
10101 01:02:22.667666
10102 01:02:22.667856 done.
10103 01:02:22.667935
10104 01:02:22.667999 MAC: 00:e0:4c:78:7a:aa
10105 01:02:22.668059
10106 01:02:22.670743 Sending DHCP discover... done.
10107 01:02:22.670832
10108 01:02:22.673994 Waiting for reply... done.
10109 01:02:22.674080
10110 01:02:22.677235 Sending DHCP request... done.
10111 01:02:22.677320
10112 01:02:22.677387 Waiting for reply... done.
10113 01:02:22.677448
10114 01:02:22.680533 My ip is 192.168.201.12
10115 01:02:22.680620
10116 01:02:22.683813 The DHCP server ip is 192.168.201.1
10117 01:02:22.683897
10118 01:02:22.687485 TFTP server IP predefined by user: 192.168.201.1
10119 01:02:22.687571
10120 01:02:22.693817 Bootfile predefined by user: 12571086/tftp-deploy-gwbojakf/kernel/image.itb
10121 01:02:22.693906
10122 01:02:22.696806 Sending tftp read request... done.
10123 01:02:22.696891
10124 01:02:22.700470 Waiting for the transfer...
10125 01:02:22.700557
10126 01:02:22.979435 00000000 ################################################################
10127 01:02:22.979584
10128 01:02:23.243395 00080000 ################################################################
10129 01:02:23.243532
10130 01:02:23.510216 00100000 ################################################################
10131 01:02:23.510349
10132 01:02:23.771654 00180000 ################################################################
10133 01:02:23.771799
10134 01:02:24.034172 00200000 ################################################################
10135 01:02:24.034318
10136 01:02:24.301422 00280000 ################################################################
10137 01:02:24.301559
10138 01:02:24.581234 00300000 ################################################################
10139 01:02:24.581377
10140 01:02:24.853534 00380000 ################################################################
10141 01:02:24.853679
10142 01:02:25.124399 00400000 ################################################################
10143 01:02:25.124533
10144 01:02:25.401634 00480000 ################################################################
10145 01:02:25.401765
10146 01:02:25.659483 00500000 ################################################################
10147 01:02:25.659618
10148 01:02:25.922465 00580000 ################################################################
10149 01:02:25.922598
10150 01:02:26.199165 00600000 ################################################################
10151 01:02:26.199308
10152 01:02:26.469458 00680000 ################################################################
10153 01:02:26.469592
10154 01:02:26.741738 00700000 ################################################################
10155 01:02:26.741890
10156 01:02:27.010137 00780000 ################################################################
10157 01:02:27.010287
10158 01:02:27.271061 00800000 ################################################################
10159 01:02:27.271209
10160 01:02:27.547466 00880000 ################################################################
10161 01:02:27.547621
10162 01:02:27.829479 00900000 ################################################################
10163 01:02:27.829635
10164 01:02:28.109960 00980000 ################################################################
10165 01:02:28.110118
10166 01:02:28.386283 00a00000 ################################################################
10167 01:02:28.386440
10168 01:02:28.674422 00a80000 ################################################################
10169 01:02:28.674602
10170 01:02:28.941808 00b00000 ################################################################
10171 01:02:28.941961
10172 01:02:29.214767 00b80000 ################################################################
10173 01:02:29.214920
10174 01:02:29.483948 00c00000 ################################################################
10175 01:02:29.484102
10176 01:02:29.760431 00c80000 ################################################################
10177 01:02:29.760586
10178 01:02:30.041708 00d00000 ################################################################
10179 01:02:30.041862
10180 01:02:30.325062 00d80000 ################################################################
10181 01:02:30.325220
10182 01:02:30.614303 00e00000 ################################################################
10183 01:02:30.614457
10184 01:02:30.900003 00e80000 ################################################################
10185 01:02:30.900163
10186 01:02:31.182765 00f00000 ################################################################
10187 01:02:31.182934
10188 01:02:31.455608 00f80000 ################################################################
10189 01:02:31.455756
10190 01:02:31.736987 01000000 ################################################################
10191 01:02:31.737141
10192 01:02:32.026660 01080000 ################################################################
10193 01:02:32.026827
10194 01:02:32.320958 01100000 ################################################################
10195 01:02:32.321113
10196 01:02:32.602969 01180000 ################################################################
10197 01:02:32.603125
10198 01:02:32.866623 01200000 ################################################################
10199 01:02:32.866777
10200 01:02:33.150309 01280000 ################################################################
10201 01:02:33.150465
10202 01:02:33.422559 01300000 ################################################################
10203 01:02:33.422715
10204 01:02:33.702665 01380000 ################################################################
10205 01:02:33.702825
10206 01:02:33.986651 01400000 ################################################################
10207 01:02:33.986806
10208 01:02:34.271619 01480000 ################################################################
10209 01:02:34.271775
10210 01:02:34.567109 01500000 ################################################################
10211 01:02:34.567263
10212 01:02:34.855943 01580000 ################################################################
10213 01:02:34.856098
10214 01:02:35.134030 01600000 ################################################################
10215 01:02:35.134211
10216 01:02:35.429283 01680000 ################################################################
10217 01:02:35.429437
10218 01:02:35.707245 01700000 ################################################################
10219 01:02:35.707399
10220 01:02:35.981066 01780000 ################################################################
10221 01:02:35.981218
10222 01:02:36.260067 01800000 ################################################################
10223 01:02:36.260223
10224 01:02:36.542017 01880000 ################################################################
10225 01:02:36.542174
10226 01:02:36.824250 01900000 ################################################################
10227 01:02:36.824453
10228 01:02:37.107173 01980000 ################################################################
10229 01:02:37.107326
10230 01:02:37.386662 01a00000 ################################################################
10231 01:02:37.386817
10232 01:02:37.674003 01a80000 ################################################################
10233 01:02:37.674160
10234 01:02:37.952714 01b00000 ################################################################
10235 01:02:37.952852
10236 01:02:38.238655 01b80000 ################################################################
10237 01:02:38.238799
10238 01:02:38.513997 01c00000 ################################################################
10239 01:02:38.514128
10240 01:02:38.522205 01c80000 ## done.
10241 01:02:38.522298
10242 01:02:38.525372 The bootfile was 29897246 bytes long.
10243 01:02:38.525459
10244 01:02:38.525536 Sending tftp read request... done.
10245 01:02:38.529035
10246 01:02:38.529157 Waiting for the transfer...
10247 01:02:38.529250
10248 01:02:38.532587 00000000 # done.
10249 01:02:38.532678
10250 01:02:38.539107 Command line loaded dynamically from TFTP file: 12571086/tftp-deploy-gwbojakf/kernel/cmdline
10251 01:02:38.539193
10252 01:02:38.562013 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10253 01:02:38.562137
10254 01:02:38.562207 Loading FIT.
10255 01:02:38.562271
10256 01:02:38.565471 Image ramdisk-1 has 17799310 bytes.
10257 01:02:38.565556
10258 01:02:38.568680 Image fdt-1 has 47278 bytes.
10259 01:02:38.568764
10260 01:02:38.572033 Image kernel-1 has 12048624 bytes.
10261 01:02:38.572120
10262 01:02:38.578898 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10263 01:02:38.578985
10264 01:02:38.598709 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10265 01:02:38.598815
10266 01:02:38.601953 Choosing best match conf-1 for compat google,spherion-rev2.
10267 01:02:38.607177
10268 01:02:38.612014 Connected to device vid:did:rid of 1ae0:0028:00
10269 01:02:38.620119
10270 01:02:38.623287 tpm_get_response: command 0x17b, return code 0x0
10271 01:02:38.623372
10272 01:02:38.627111 ec_init: CrosEC protocol v3 supported (256, 248)
10273 01:02:38.631470
10274 01:02:38.635086 tpm_cleanup: add release locality here.
10275 01:02:38.635171
10276 01:02:38.635238 Shutting down all USB controllers.
10277 01:02:38.638295
10278 01:02:38.638379 Removing current net device
10279 01:02:38.638446
10280 01:02:38.645238 Exiting depthcharge with code 4 at timestamp: 51503748
10281 01:02:38.645323
10282 01:02:38.648475 LZMA decompressing kernel-1 to 0x821a6718
10283 01:02:38.648562
10284 01:02:38.651513 LZMA decompressing kernel-1 to 0x40000000
10285 01:02:40.150246
10286 01:02:40.150388 jumping to kernel
10287 01:02:40.150847 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10288 01:02:40.150948 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10289 01:02:40.151025 Setting prompt string to ['Linux version [0-9]']
10290 01:02:40.151093 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10291 01:02:40.151160 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10292 01:02:40.231835
10293 01:02:40.235752 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10294 01:02:40.239123 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10295 01:02:40.239216 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10296 01:02:40.239288 Setting prompt string to []
10297 01:02:40.239364 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10298 01:02:40.239438 Using line separator: #'\n'#
10299 01:02:40.239497 No login prompt set.
10300 01:02:40.239559 Parsing kernel messages
10301 01:02:40.239614 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10302 01:02:40.239721 [login-action] Waiting for messages, (timeout 00:04:01)
10303 01:02:40.258737 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10304 01:02:40.261934 [ 0.000000] random: crng init done
10305 01:02:40.269119 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10306 01:02:40.272215 [ 0.000000] efi: UEFI not found.
10307 01:02:40.278232 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10308 01:02:40.284789 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10309 01:02:40.294914 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10310 01:02:40.304561 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10311 01:02:40.311453 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10312 01:02:40.318023 [ 0.000000] printk: bootconsole [mtk8250] enabled
10313 01:02:40.324752 [ 0.000000] NUMA: No NUMA configuration found
10314 01:02:40.331257 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10315 01:02:40.334789 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10316 01:02:40.337735 [ 0.000000] Zone ranges:
10317 01:02:40.344645 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10318 01:02:40.347955 [ 0.000000] DMA32 empty
10319 01:02:40.354681 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10320 01:02:40.357860 [ 0.000000] Movable zone start for each node
10321 01:02:40.361546 [ 0.000000] Early memory node ranges
10322 01:02:40.368005 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10323 01:02:40.374205 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10324 01:02:40.381628 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10325 01:02:40.384637 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10326 01:02:40.390809 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10327 01:02:40.397408 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10328 01:02:40.456491 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10329 01:02:40.463218 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10330 01:02:40.469886 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10331 01:02:40.473257 [ 0.000000] psci: probing for conduit method from DT.
10332 01:02:40.479558 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10333 01:02:40.483246 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10334 01:02:40.489819 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10335 01:02:40.492940 [ 0.000000] psci: SMC Calling Convention v1.2
10336 01:02:40.499566 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10337 01:02:40.502783 [ 0.000000] Detected VIPT I-cache on CPU0
10338 01:02:40.509666 [ 0.000000] CPU features: detected: GIC system register CPU interface
10339 01:02:40.516025 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10340 01:02:40.522799 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10341 01:02:40.529713 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10342 01:02:40.535963 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10343 01:02:40.542935 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10344 01:02:40.549164 [ 0.000000] alternatives: applying boot alternatives
10345 01:02:40.552920 [ 0.000000] Fallback order for Node 0: 0
10346 01:02:40.559347 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10347 01:02:40.562556 [ 0.000000] Policy zone: Normal
10348 01:02:40.586575 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10349 01:02:40.599065 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10350 01:02:40.609656 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10351 01:02:40.619537 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10352 01:02:40.625683 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10353 01:02:40.629163 <6>[ 0.000000] software IO TLB: area num 8.
10354 01:02:40.685866 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10355 01:02:40.835465 <6>[ 0.000000] Memory: 7949876K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402892K reserved, 32768K cma-reserved)
10356 01:02:40.842174 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10357 01:02:40.849133 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10358 01:02:40.852067 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10359 01:02:40.858656 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10360 01:02:40.865239 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10361 01:02:40.868416 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10362 01:02:40.878496 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10363 01:02:40.885070 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10364 01:02:40.888526 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10365 01:02:40.896193 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10366 01:02:40.900043 <6>[ 0.000000] GICv3: 608 SPIs implemented
10367 01:02:40.906341 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10368 01:02:40.909534 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10369 01:02:40.912736 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10370 01:02:40.923222 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10371 01:02:40.932896 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10372 01:02:40.945705 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10373 01:02:40.952147 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10374 01:02:40.961577 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10375 01:02:40.974680 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10376 01:02:40.981358 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10377 01:02:40.987761 <6>[ 0.009191] Console: colour dummy device 80x25
10378 01:02:40.997932 <6>[ 0.013919] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10379 01:02:41.004423 <6>[ 0.024425] pid_max: default: 32768 minimum: 301
10380 01:02:41.008061 <6>[ 0.029297] LSM: Security Framework initializing
10381 01:02:41.014310 <6>[ 0.034264] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 01:02:41.024866 <6>[ 0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10383 01:02:41.031277 <6>[ 0.051470] cblist_init_generic: Setting adjustable number of callback queues.
10384 01:02:41.037593 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 01:02:41.047935 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10386 01:02:41.054598 <6>[ 0.072678] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 01:02:41.057375 <6>[ 0.079082] rcu: Hierarchical SRCU implementation.
10388 01:02:41.064347 <6>[ 0.084097] rcu: Max phase no-delay instances is 1000.
10389 01:02:41.070556 <6>[ 0.091117] EFI services will not be available.
10390 01:02:41.074181 <6>[ 0.096069] smp: Bringing up secondary CPUs ...
10391 01:02:41.082669 <6>[ 0.101147] Detected VIPT I-cache on CPU1
10392 01:02:41.089246 <6>[ 0.101217] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10393 01:02:41.096021 <6>[ 0.101245] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10394 01:02:41.098981 <6>[ 0.101577] Detected VIPT I-cache on CPU2
10395 01:02:41.105145 <6>[ 0.101621] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10396 01:02:41.115211 <6>[ 0.101637] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10397 01:02:41.118924 <6>[ 0.101885] Detected VIPT I-cache on CPU3
10398 01:02:41.125289 <6>[ 0.101932] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10399 01:02:41.132257 <6>[ 0.101946] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10400 01:02:41.135332 <6>[ 0.102251] CPU features: detected: Spectre-v4
10401 01:02:41.141849 <6>[ 0.102258] CPU features: detected: Spectre-BHB
10402 01:02:41.145621 <6>[ 0.102262] Detected PIPT I-cache on CPU4
10403 01:02:41.152073 <6>[ 0.102318] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10404 01:02:41.158053 <6>[ 0.102335] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10405 01:02:41.164937 <6>[ 0.102627] Detected PIPT I-cache on CPU5
10406 01:02:41.171557 <6>[ 0.102689] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10407 01:02:41.177926 <6>[ 0.102707] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10408 01:02:41.181525 <6>[ 0.102986] Detected PIPT I-cache on CPU6
10409 01:02:41.188161 <6>[ 0.103049] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10410 01:02:41.194833 <6>[ 0.103065] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10411 01:02:41.201244 <6>[ 0.103363] Detected PIPT I-cache on CPU7
10412 01:02:41.208522 <6>[ 0.103427] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10413 01:02:41.215137 <6>[ 0.103444] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10414 01:02:41.218159 <6>[ 0.103491] smp: Brought up 1 node, 8 CPUs
10415 01:02:41.224803 <6>[ 0.244886] SMP: Total of 8 processors activated.
10416 01:02:41.227804 <6>[ 0.249807] CPU features: detected: 32-bit EL0 Support
10417 01:02:41.238444 <6>[ 0.255180] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10418 01:02:41.244454 <6>[ 0.263980] CPU features: detected: Common not Private translations
10419 01:02:41.251256 <6>[ 0.270456] CPU features: detected: CRC32 instructions
10420 01:02:41.254900 <6>[ 0.275840] CPU features: detected: RCpc load-acquire (LDAPR)
10421 01:02:41.260870 <6>[ 0.281837] CPU features: detected: LSE atomic instructions
10422 01:02:41.267647 <6>[ 0.287618] CPU features: detected: Privileged Access Never
10423 01:02:41.274112 <6>[ 0.293398] CPU features: detected: RAS Extension Support
10424 01:02:41.280892 <6>[ 0.299042] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10425 01:02:41.284044 <6>[ 0.306263] CPU: All CPU(s) started at EL2
10426 01:02:41.290955 <6>[ 0.310580] alternatives: applying system-wide alternatives
10427 01:02:41.300025 <6>[ 0.321270] devtmpfs: initialized
10428 01:02:41.315935 <6>[ 0.330248] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10429 01:02:41.322147 <6>[ 0.340209] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10430 01:02:41.328804 <6>[ 0.348440] pinctrl core: initialized pinctrl subsystem
10431 01:02:41.332693 <6>[ 0.355078] DMI not present or invalid.
10432 01:02:41.338936 <6>[ 0.359488] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10433 01:02:41.348747 <6>[ 0.366365] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10434 01:02:41.355344 <6>[ 0.373950] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10435 01:02:41.365356 <6>[ 0.382183] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10436 01:02:41.368435 <6>[ 0.390426] audit: initializing netlink subsys (disabled)
10437 01:02:41.378927 <5>[ 0.396118] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10438 01:02:41.385506 <6>[ 0.396810] thermal_sys: Registered thermal governor 'step_wise'
10439 01:02:41.392378 <6>[ 0.404085] thermal_sys: Registered thermal governor 'power_allocator'
10440 01:02:41.395351 <6>[ 0.410340] cpuidle: using governor menu
10441 01:02:41.402117 <6>[ 0.421299] NET: Registered PF_QIPCRTR protocol family
10442 01:02:41.408341 <6>[ 0.426785] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10443 01:02:41.411788 <6>[ 0.433889] ASID allocator initialised with 32768 entries
10444 01:02:41.418929 <6>[ 0.440447] Serial: AMBA PL011 UART driver
10445 01:02:41.427822 <4>[ 0.449165] Trying to register duplicate clock ID: 134
10446 01:02:41.482264 <6>[ 0.506298] KASLR enabled
10447 01:02:41.496352 <6>[ 0.513996] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10448 01:02:41.502922 <6>[ 0.521009] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10449 01:02:41.509215 <6>[ 0.527497] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10450 01:02:41.516431 <6>[ 0.534502] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10451 01:02:41.522528 <6>[ 0.540991] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10452 01:02:41.529545 <6>[ 0.547996] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10453 01:02:41.536230 <6>[ 0.554486] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10454 01:02:41.543056 <6>[ 0.561491] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10455 01:02:41.546183 <6>[ 0.568961] ACPI: Interpreter disabled.
10456 01:02:41.554181 <6>[ 0.575397] iommu: Default domain type: Translated
10457 01:02:41.561266 <6>[ 0.580511] iommu: DMA domain TLB invalidation policy: strict mode
10458 01:02:41.564211 <5>[ 0.587175] SCSI subsystem initialized
10459 01:02:41.571207 <6>[ 0.591424] usbcore: registered new interface driver usbfs
10460 01:02:41.577569 <6>[ 0.597151] usbcore: registered new interface driver hub
10461 01:02:41.580789 <6>[ 0.602703] usbcore: registered new device driver usb
10462 01:02:41.587893 <6>[ 0.608822] pps_core: LinuxPPS API ver. 1 registered
10463 01:02:41.597590 <6>[ 0.614017] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10464 01:02:41.600671 <6>[ 0.623362] PTP clock support registered
10465 01:02:41.604100 <6>[ 0.627603] EDAC MC: Ver: 3.0.0
10466 01:02:41.611985 <6>[ 0.632794] FPGA manager framework
10467 01:02:41.615345 <6>[ 0.636472] Advanced Linux Sound Architecture Driver Initialized.
10468 01:02:41.618885 <6>[ 0.643248] vgaarb: loaded
10469 01:02:41.625672 <6>[ 0.646401] clocksource: Switched to clocksource arch_sys_counter
10470 01:02:41.631835 <5>[ 0.652845] VFS: Disk quotas dquot_6.6.0
10471 01:02:41.638706 <6>[ 0.657030] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10472 01:02:41.641834 <6>[ 0.664219] pnp: PnP ACPI: disabled
10473 01:02:41.650030 <6>[ 0.670974] NET: Registered PF_INET protocol family
10474 01:02:41.659557 <6>[ 0.676578] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10475 01:02:41.670990 <6>[ 0.688905] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10476 01:02:41.681141 <6>[ 0.697720] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10477 01:02:41.687876 <6>[ 0.705691] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10478 01:02:41.694770 <6>[ 0.714393] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10479 01:02:41.706209 <6>[ 0.724129] TCP: Hash tables configured (established 65536 bind 65536)
10480 01:02:41.713341 <6>[ 0.730988] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10481 01:02:41.719455 <6>[ 0.738187] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10482 01:02:41.726161 <6>[ 0.745893] NET: Registered PF_UNIX/PF_LOCAL protocol family
10483 01:02:41.732614 <6>[ 0.752065] RPC: Registered named UNIX socket transport module.
10484 01:02:41.736355 <6>[ 0.758221] RPC: Registered udp transport module.
10485 01:02:41.742963 <6>[ 0.763153] RPC: Registered tcp transport module.
10486 01:02:41.749809 <6>[ 0.768088] RPC: Registered tcp NFSv4.1 backchannel transport module.
10487 01:02:41.752637 <6>[ 0.774752] PCI: CLS 0 bytes, default 64
10488 01:02:41.756126 <6>[ 0.779141] Unpacking initramfs...
10489 01:02:41.773021 <6>[ 0.790980] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10490 01:02:41.782956 <6>[ 0.799642] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10491 01:02:41.786136 <6>[ 0.808492] kvm [1]: IPA Size Limit: 40 bits
10492 01:02:41.793126 <6>[ 0.813023] kvm [1]: GICv3: no GICV resource entry
10493 01:02:41.795897 <6>[ 0.818044] kvm [1]: disabling GICv2 emulation
10494 01:02:41.803471 <6>[ 0.822728] kvm [1]: GIC system register CPU interface enabled
10495 01:02:41.809971 <6>[ 0.830469] kvm [1]: vgic interrupt IRQ18
10496 01:02:41.813237 <6>[ 0.834859] kvm [1]: VHE mode initialized successfully
10497 01:02:41.820179 <5>[ 0.841291] Initialise system trusted keyrings
10498 01:02:41.826399 <6>[ 0.846070] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10499 01:02:41.835180 <6>[ 0.856029] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10500 01:02:41.841446 <5>[ 0.862460] NFS: Registering the id_resolver key type
10501 01:02:41.845276 <5>[ 0.867767] Key type id_resolver registered
10502 01:02:41.851929 <5>[ 0.872181] Key type id_legacy registered
10503 01:02:41.858351 <6>[ 0.876460] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10504 01:02:41.864698 <6>[ 0.883383] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10505 01:02:41.871594 <6>[ 0.891110] 9p: Installing v9fs 9p2000 file system support
10506 01:02:41.908052 <5>[ 0.929090] Key type asymmetric registered
10507 01:02:41.911547 <5>[ 0.933422] Asymmetric key parser 'x509' registered
10508 01:02:41.921387 <6>[ 0.938565] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10509 01:02:41.924746 <6>[ 0.946180] io scheduler mq-deadline registered
10510 01:02:41.927853 <6>[ 0.950939] io scheduler kyber registered
10511 01:02:41.947309 <6>[ 0.968196] EINJ: ACPI disabled.
10512 01:02:41.979022 <4>[ 0.993775] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10513 01:02:41.988706 <4>[ 1.004422] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 01:02:42.004206 <6>[ 1.025324] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10515 01:02:42.012283 <6>[ 1.033306] printk: console [ttyS0] disabled
10516 01:02:42.039986 <6>[ 1.057961] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10517 01:02:42.047031 <6>[ 1.067438] printk: console [ttyS0] enabled
10518 01:02:42.050333 <6>[ 1.067438] printk: console [ttyS0] enabled
10519 01:02:42.056874 <6>[ 1.076353] printk: bootconsole [mtk8250] disabled
10520 01:02:42.060099 <6>[ 1.076353] printk: bootconsole [mtk8250] disabled
10521 01:02:42.066793 <6>[ 1.087651] SuperH (H)SCI(F) driver initialized
10522 01:02:42.069857 <6>[ 1.092936] msm_serial: driver initialized
10523 01:02:42.084044 <6>[ 1.101937] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10524 01:02:42.094502 <6>[ 1.110489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10525 01:02:42.100878 <6>[ 1.119032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10526 01:02:42.110978 <6>[ 1.127662] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10527 01:02:42.117405 <6>[ 1.136369] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10528 01:02:42.127052 <6>[ 1.145083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10529 01:02:42.137387 <6>[ 1.153623] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10530 01:02:42.143925 <6>[ 1.162439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10531 01:02:42.153963 <6>[ 1.170984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10532 01:02:42.165435 <6>[ 1.186820] loop: module loaded
10533 01:02:42.172319 <6>[ 1.192510] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10534 01:02:42.195220 <4>[ 1.215976] mtk-pmic-keys: Failed to locate of_node [id: -1]
10535 01:02:42.202109 <6>[ 1.223140] megasas: 07.719.03.00-rc1
10536 01:02:42.212275 <6>[ 1.233038] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10537 01:02:42.220870 <6>[ 1.241799] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10538 01:02:42.237388 <6>[ 1.258385] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10539 01:02:42.293141 <6>[ 1.307947] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10540 01:02:42.494171 <6>[ 1.515087] Freeing initrd memory: 17376K
10541 01:02:42.504370 <6>[ 1.525356] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10542 01:02:42.515338 <6>[ 1.536320] tun: Universal TUN/TAP device driver, 1.6
10543 01:02:42.518838 <6>[ 1.542386] thunder_xcv, ver 1.0
10544 01:02:42.521500 <6>[ 1.545894] thunder_bgx, ver 1.0
10545 01:02:42.525110 <6>[ 1.549393] nicpf, ver 1.0
10546 01:02:42.535639 <6>[ 1.553408] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10547 01:02:42.539073 <6>[ 1.560883] hns3: Copyright (c) 2017 Huawei Corporation.
10548 01:02:42.542274 <6>[ 1.566471] hclge is initializing
10549 01:02:42.549101 <6>[ 1.570042] e1000: Intel(R) PRO/1000 Network Driver
10550 01:02:42.555866 <6>[ 1.575171] e1000: Copyright (c) 1999-2006 Intel Corporation.
10551 01:02:42.559092 <6>[ 1.581188] e1000e: Intel(R) PRO/1000 Network Driver
10552 01:02:42.565392 <6>[ 1.586404] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10553 01:02:42.572374 <6>[ 1.592590] igb: Intel(R) Gigabit Ethernet Network Driver
10554 01:02:42.578949 <6>[ 1.598239] igb: Copyright (c) 2007-2014 Intel Corporation.
10555 01:02:42.585158 <6>[ 1.604075] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10556 01:02:42.589259 <6>[ 1.610592] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10557 01:02:42.595883 <6>[ 1.617059] sky2: driver version 1.30
10558 01:02:42.602414 <6>[ 1.622073] VFIO - User Level meta-driver version: 0.3
10559 01:02:42.609113 <6>[ 1.630283] usbcore: registered new interface driver usb-storage
10560 01:02:42.615867 <6>[ 1.636732] usbcore: registered new device driver onboard-usb-hub
10561 01:02:42.624814 <6>[ 1.645910] mt6397-rtc mt6359-rtc: registered as rtc0
10562 01:02:42.634518 <6>[ 1.651378] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:00:03 UTC (1705626003)
10563 01:02:42.637747 <6>[ 1.660941] i2c_dev: i2c /dev entries driver
10564 01:02:42.654809 <6>[ 1.672775] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10565 01:02:42.675658 <6>[ 1.696765] cpu cpu0: EM: created perf domain
10566 01:02:42.678928 <6>[ 1.701694] cpu cpu4: EM: created perf domain
10567 01:02:42.686381 <6>[ 1.707305] sdhci: Secure Digital Host Controller Interface driver
10568 01:02:42.697053 <6>[ 1.713737] sdhci: Copyright(c) Pierre Ossman
10569 01:02:42.699217 <6>[ 1.718696] Synopsys Designware Multimedia Card Interface Driver
10570 01:02:42.705753 <6>[ 1.725325] sdhci-pltfm: SDHCI platform and OF driver helper
10571 01:02:42.709451 <6>[ 1.725437] mmc0: CQHCI version 5.10
10572 01:02:42.715876 <6>[ 1.735423] ledtrig-cpu: registered to indicate activity on CPUs
10573 01:02:42.722470 <6>[ 1.742520] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 01:02:42.729118 <6>[ 1.749575] usbcore: registered new interface driver usbhid
10575 01:02:42.732923 <6>[ 1.755397] usbhid: USB HID core driver
10576 01:02:42.739665 <6>[ 1.759596] spi_master spi0: will run message pump with realtime priority
10577 01:02:42.781710 <6>[ 1.796192] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10578 01:02:42.799894 <6>[ 1.810967] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10579 01:02:42.803841 <6>[ 1.824584] mmc0: Command Queue Engine enabled
10580 01:02:42.810216 <6>[ 1.829362] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10581 01:02:42.816905 <6>[ 1.836334] cros-ec-spi spi0.0: Chrome EC device registered
10582 01:02:42.819559 <6>[ 1.836781] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 01:02:42.830175 <6>[ 1.851267] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10584 01:02:42.837145 <6>[ 1.858552] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10585 01:02:42.843637 <6>[ 1.864444] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10586 01:02:42.850985 <6>[ 1.870305] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10587 01:02:42.865361 <6>[ 1.883209] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10588 01:02:42.872857 <6>[ 1.893804] NET: Registered PF_PACKET protocol family
10589 01:02:42.875974 <6>[ 1.899201] 9pnet: Installing 9P2000 support
10590 01:02:42.882578 <5>[ 1.903768] Key type dns_resolver registered
10591 01:02:42.885781 <6>[ 1.908737] registered taskstats version 1
10592 01:02:42.893223 <5>[ 1.913138] Loading compiled-in X.509 certificates
10593 01:02:42.924246 <4>[ 1.938495] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 01:02:42.934145 <4>[ 1.949301] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 01:02:42.940751 <3>[ 1.959842] debugfs: File 'uA_load' in directory '/' already present!
10596 01:02:42.947399 <3>[ 1.966552] debugfs: File 'min_uV' in directory '/' already present!
10597 01:02:42.954565 <3>[ 1.973167] debugfs: File 'max_uV' in directory '/' already present!
10598 01:02:42.960612 <3>[ 1.979777] debugfs: File 'constraint_flags' in directory '/' already present!
10599 01:02:42.971402 <3>[ 1.989432] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10600 01:02:42.985394 <6>[ 2.006650] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10601 01:02:42.992752 <6>[ 2.013519] xhci-mtk 11200000.usb: xHCI Host Controller
10602 01:02:42.999106 <6>[ 2.019031] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10603 01:02:43.008813 <6>[ 2.026983] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10604 01:02:43.015575 <6>[ 2.036456] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10605 01:02:43.022481 <6>[ 2.042619] xhci-mtk 11200000.usb: xHCI Host Controller
10606 01:02:43.028883 <6>[ 2.048115] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10607 01:02:43.035662 <6>[ 2.055908] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10608 01:02:43.042738 <6>[ 2.063719] hub 1-0:1.0: USB hub found
10609 01:02:43.046118 <6>[ 2.067751] hub 1-0:1.0: 1 port detected
10610 01:02:43.052891 <6>[ 2.072079] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10611 01:02:43.059401 <6>[ 2.080909] hub 2-0:1.0: USB hub found
10612 01:02:43.062904 <6>[ 2.084941] hub 2-0:1.0: 1 port detected
10613 01:02:43.071819 <6>[ 2.092973] mtk-msdc 11f70000.mmc: Got CD GPIO
10614 01:02:43.088379 <6>[ 2.106197] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10615 01:02:43.095462 <6>[ 2.114406] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10616 01:02:43.104633 <4>[ 2.122464] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10617 01:02:43.115326 <6>[ 2.131997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10618 01:02:43.121560 <6>[ 2.140092] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10619 01:02:43.128223 <6>[ 2.148115] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10620 01:02:43.138274 <6>[ 2.156044] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10621 01:02:43.145270 <6>[ 2.163862] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10622 01:02:43.155355 <6>[ 2.171693] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10623 01:02:43.165264 <6>[ 2.182198] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10624 01:02:43.172161 <6>[ 2.190587] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10625 01:02:43.182012 <6>[ 2.198928] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10626 01:02:43.188416 <6>[ 2.207278] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10627 01:02:43.198345 <6>[ 2.215618] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10628 01:02:43.204676 <6>[ 2.223967] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10629 01:02:43.215552 <6>[ 2.232306] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10630 01:02:43.221647 <6>[ 2.240657] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10631 01:02:43.231984 <6>[ 2.248996] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10632 01:02:43.238741 <6>[ 2.257345] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10633 01:02:43.248331 <6>[ 2.265684] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10634 01:02:43.255301 <6>[ 2.274022] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10635 01:02:43.265034 <6>[ 2.282361] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10636 01:02:43.272239 <6>[ 2.290699] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10637 01:02:43.281537 <6>[ 2.299037] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10638 01:02:43.288176 <6>[ 2.307829] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10639 01:02:43.294852 <6>[ 2.315020] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10640 01:02:43.301754 <6>[ 2.321781] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10641 01:02:43.308364 <6>[ 2.328542] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10642 01:02:43.315506 <6>[ 2.335473] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10643 01:02:43.324857 <6>[ 2.342323] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10644 01:02:43.334915 <6>[ 2.351455] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10645 01:02:43.344641 <6>[ 2.360574] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10646 01:02:43.355003 <6>[ 2.369888] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10647 01:02:43.361088 <6>[ 2.379362] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10648 01:02:43.371163 <6>[ 2.388828] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10649 01:02:43.381031 <6>[ 2.397947] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10650 01:02:43.391149 <6>[ 2.407413] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10651 01:02:43.401464 <6>[ 2.416531] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10652 01:02:43.411133 <6>[ 2.425824] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10653 01:02:43.420961 <6>[ 2.435983] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10654 01:02:43.430702 <6>[ 2.447371] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10655 01:02:43.437457 <6>[ 2.457280] Trying to probe devices needed for running init ...
10656 01:02:43.453030 <6>[ 2.470686] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10657 01:02:43.480392 <6>[ 2.501577] hub 2-1:1.0: USB hub found
10658 01:02:43.483891 <6>[ 2.506029] hub 2-1:1.0: 3 ports detected
10659 01:02:43.491768 <6>[ 2.512905] hub 2-1:1.0: USB hub found
10660 01:02:43.495068 <6>[ 2.517381] hub 2-1:1.0: 3 ports detected
10661 01:02:43.604507 <6>[ 2.622672] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10662 01:02:43.763757 <6>[ 2.784635] hub 1-1:1.0: USB hub found
10663 01:02:43.766685 <6>[ 2.789147] hub 1-1:1.0: 4 ports detected
10664 01:02:43.776620 <6>[ 2.797818] hub 1-1:1.0: USB hub found
10665 01:02:43.779768 <6>[ 2.802318] hub 1-1:1.0: 4 ports detected
10666 01:02:43.848882 <6>[ 2.866768] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10667 01:02:44.100491 <6>[ 3.118675] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10668 01:02:44.232879 <6>[ 3.253971] hub 1-1.4:1.0: USB hub found
10669 01:02:44.236034 <6>[ 3.258585] hub 1-1.4:1.0: 2 ports detected
10670 01:02:44.244924 <6>[ 3.266277] hub 1-1.4:1.0: USB hub found
10671 01:02:44.248105 <6>[ 3.270908] hub 1-1.4:1.0: 2 ports detected
10672 01:02:44.545221 <6>[ 3.562716] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 01:02:44.736471 <6>[ 3.754714] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 01:02:55.709219 <6>[ 14.735708] ALSA device list:
10675 01:02:55.715473 <6>[ 14.738999] No soundcards found.
10676 01:02:55.723603 <6>[ 14.746908] Freeing unused kernel memory: 8448K
10677 01:02:55.727435 <6>[ 14.751922] Run /init as init process
10678 01:02:55.737845 Loading, please wait...
10679 01:02:55.758403 Starting version 247.3-7+deb11u2
10680 01:02:55.962906 <6>[ 14.982660] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10681 01:02:55.975881 <6>[ 14.998652] remoteproc remoteproc0: scp is available
10682 01:02:55.981970 <6>[ 15.005210] remoteproc remoteproc0: powering up scp
10683 01:02:55.991915 <6>[ 15.010448] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10684 01:02:55.998899 <3>[ 15.013598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 01:02:56.005444 <6>[ 15.018917] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10686 01:02:56.011674 <3>[ 15.032692] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 01:02:56.021694 <3>[ 15.040816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 01:02:56.028571 <6>[ 15.043840] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10689 01:02:56.038101 <6>[ 15.056497] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10690 01:02:56.044887 <6>[ 15.065187] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10691 01:02:56.054879 <3>[ 15.069312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 01:02:56.061540 <4>[ 15.069401] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10693 01:02:56.068630 <4>[ 15.079219] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10694 01:02:56.074933 <3>[ 15.082074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 01:02:56.081340 <6>[ 15.090291] mc: Linux media interface: v0.10
10696 01:02:56.088173 <3>[ 15.096651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 01:02:56.097668 <6>[ 15.116307] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10698 01:02:56.104447 <3>[ 15.117344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 01:02:56.114793 <3>[ 15.133078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 01:02:56.118117 <6>[ 15.134203] videodev: Linux video capture interface: v2.00
10701 01:02:56.124801 <6>[ 15.138542] usbcore: registered new device driver r8152-cfgselector
10702 01:02:56.134541 <3>[ 15.142221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 01:02:56.141496 <6>[ 15.144578] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10704 01:02:56.148428 <4>[ 15.160733] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10705 01:02:56.154447 <4>[ 15.160733] Fallback method does not support PEC.
10706 01:02:56.161727 <6>[ 15.161643] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10707 01:02:56.171809 <3>[ 15.162285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 01:02:56.178624 <3>[ 15.162292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10709 01:02:56.185801 <3>[ 15.162295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10710 01:02:56.195630 <3>[ 15.162372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 01:02:56.202605 <3>[ 15.162376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 01:02:56.212138 <3>[ 15.162379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 01:02:56.218862 <3>[ 15.162387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 01:02:56.229031 <3>[ 15.162408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 01:02:56.235740 <3>[ 15.162443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 01:02:56.245310 <6>[ 15.183364] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10717 01:02:56.252175 <6>[ 15.190898] remoteproc remoteproc0: remote processor scp is now up
10718 01:02:56.259167 <3>[ 15.193030] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 01:02:56.265405 <6>[ 15.195821] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10720 01:02:56.272074 <6>[ 15.195826] pci_bus 0000:00: root bus resource [bus 00-ff]
10721 01:02:56.278733 <6>[ 15.195831] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10722 01:02:56.288716 <6>[ 15.195833] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10723 01:02:56.295102 <6>[ 15.195860] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10724 01:02:56.302043 <6>[ 15.195873] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10725 01:02:56.309052 <6>[ 15.195938] pci 0000:00:00.0: supports D1 D2
10726 01:02:56.315292 <6>[ 15.195939] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10727 01:02:56.322186 <6>[ 15.196888] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10728 01:02:56.328675 <6>[ 15.196961] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10729 01:02:56.335439 <6>[ 15.196985] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10730 01:02:56.345338 <6>[ 15.197001] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10731 01:02:56.351898 <6>[ 15.197016] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10732 01:02:56.354891 <6>[ 15.197122] pci 0000:01:00.0: supports D1 D2
10733 01:02:56.361236 <6>[ 15.197123] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10734 01:02:56.371054 <6>[ 15.201154] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10735 01:02:56.381270 <6>[ 15.201471] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10736 01:02:56.387826 <6>[ 15.210714] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10737 01:02:56.394597 <3>[ 15.216364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 01:02:56.404194 <6>[ 15.223032] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10739 01:02:56.414032 <6>[ 15.223446] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10740 01:02:56.424175 <6>[ 15.223586] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10741 01:02:56.431595 <6>[ 15.226900] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10742 01:02:56.440592 <4>[ 15.253554] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10743 01:02:56.446977 <6>[ 15.255723] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10744 01:02:56.457581 <6>[ 15.255742] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10745 01:02:56.463908 <4>[ 15.263838] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10746 01:02:56.466874 <6>[ 15.264389] Bluetooth: Core ver 2.22
10747 01:02:56.473426 <6>[ 15.264543] NET: Registered PF_BLUETOOTH protocol family
10748 01:02:56.480111 <6>[ 15.264546] Bluetooth: HCI device and connection manager initialized
10749 01:02:56.483954 <6>[ 15.264569] Bluetooth: HCI socket layer initialized
10750 01:02:56.490504 <6>[ 15.264580] Bluetooth: L2CAP socket layer initialized
10751 01:02:56.497052 <6>[ 15.264595] Bluetooth: SCO socket layer initialized
10752 01:02:56.503427 <6>[ 15.272083] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 01:02:56.510198 <6>[ 15.272099] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 01:02:56.516725 <6>[ 15.272113] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 01:02:56.523619 <6>[ 15.273369] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10756 01:02:56.536789 <6>[ 15.274536] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10757 01:02:56.543629 <6>[ 15.274798] usbcore: registered new interface driver uvcvideo
10758 01:02:56.549824 <6>[ 15.308058] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10759 01:02:56.556473 <6>[ 15.316928] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10760 01:02:56.563487 <6>[ 15.323891] usbcore: registered new interface driver btusb
10761 01:02:56.573373 <4>[ 15.324824] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10762 01:02:56.579808 <3>[ 15.324837] Bluetooth: hci0: Failed to load firmware file (-2)
10763 01:02:56.582830 <3>[ 15.324841] Bluetooth: hci0: Failed to set up firmware (-2)
10764 01:02:56.596665 <4>[ 15.324845] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10765 01:02:56.603015 <6>[ 15.330769] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10766 01:02:56.606750 <6>[ 15.334570] r8152 2-1.3:1.0 eth0: v1.12.13
10767 01:02:56.613222 <6>[ 15.334625] usbcore: registered new interface driver r8152
10768 01:02:56.616379 <6>[ 15.364247] usbcore: registered new interface driver cdc_ether
10769 01:02:56.622792 <6>[ 15.372005] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10770 01:02:56.629487 <6>[ 15.383766] usbcore: registered new interface driver r8153_ecm
10771 01:02:56.636423 <6>[ 15.391057] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10772 01:02:56.642805 <6>[ 15.408291] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10773 01:02:56.679810 <5>[ 15.700160] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10774 01:02:56.701463 <5>[ 15.721406] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10775 01:02:56.707932 <5>[ 15.728553] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10776 01:02:56.718172 <4>[ 15.736967] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10777 01:02:56.720905 <6>[ 15.745850] cfg80211: failed to load regulatory.db
10778 01:02:56.768117 <6>[ 15.787966] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10779 01:02:56.774447 <6>[ 15.795472] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10780 01:02:56.798540 <6>[ 15.822122] mt7921e 0000:01:00.0: ASIC revision: 79610010
10781 01:02:56.901841 <6>[ 15.922034] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10782 01:02:56.905520 <6>[ 15.922034]
10783 01:02:56.908597 Begin: Loading essential drivers ... done.
10784 01:02:56.911929 Begin: Running /scripts/init-premount ... done.
10785 01:02:56.918313 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10786 01:02:56.928436 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10787 01:02:56.931499 Device /sys/class/net/enx00e04c787aaa found
10788 01:02:56.931582 done.
10789 01:02:57.014714 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10790 01:02:57.171502 <6>[ 16.191841] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10791 01:02:57.909154 <6>[ 16.932898] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10792 01:02:58.017103 <6>[ 17.040374] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10793 01:02:58.127956 IP-Config: no response after 2 secs - giving up
10794 01:02:58.167054 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10795 01:02:58.890613 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10796 01:02:58.893558 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10797 01:02:58.900046 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10798 01:02:58.906999 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10799 01:02:58.913384 host : mt8192-asurada-spherion-r0-cbg-0
10800 01:02:58.920272 domain : lava-rack
10801 01:02:58.923436 rootserver: 192.168.201.1 rootpath:
10802 01:02:58.926574 filename :
10803 01:02:59.046652 done.
10804 01:02:59.053356 Begin: Running /scripts/nfs-bottom ... done.
10805 01:02:59.074462 Begin: Running /scripts/init-bottom ... done.
10806 01:03:00.225869 <6>[ 19.249483] NET: Registered PF_INET6 protocol family
10807 01:03:00.233407 <6>[ 19.257252] Segment Routing with IPv6
10808 01:03:00.236974 <6>[ 19.261194] In-situ OAM (IOAM) with IPv6
10809 01:03:00.346003 <30>[ 19.350101] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10810 01:03:00.349657 <30>[ 19.374366] systemd[1]: Detected architecture arm64.
10811 01:03:00.369434
10812 01:03:00.372587 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10813 01:03:00.372673
10814 01:03:00.388663 <30>[ 19.412660] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10815 01:03:01.121289 <30>[ 20.142158] systemd[1]: Queued start job for default target Graphical Interface.
10816 01:03:01.153533 <30>[ 20.177073] systemd[1]: Created slice system-getty.slice.
10817 01:03:01.159548 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10818 01:03:01.180183 <30>[ 20.204038] systemd[1]: Created slice system-modprobe.slice.
10819 01:03:01.186647 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10820 01:03:01.203817 <30>[ 20.227887] systemd[1]: Created slice system-serial\x2dgetty.slice.
10821 01:03:01.214480 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10822 01:03:01.228180 <30>[ 20.251747] systemd[1]: Created slice User and Session Slice.
10823 01:03:01.234549 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10824 01:03:01.254850 <30>[ 20.275547] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10825 01:03:01.265024 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10826 01:03:01.282737 <30>[ 20.303463] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10827 01:03:01.289898 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10828 01:03:01.313668 <30>[ 20.330858] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10829 01:03:01.320007 <30>[ 20.343018] systemd[1]: Reached target Local Encrypted Volumes.
10830 01:03:01.326741 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10831 01:03:01.343019 <30>[ 20.367249] systemd[1]: Reached target Paths.
10832 01:03:01.350115 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10833 01:03:01.362609 <30>[ 20.386680] systemd[1]: Reached target Remote File Systems.
10834 01:03:01.369111 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10835 01:03:01.387525 <30>[ 20.411063] systemd[1]: Reached target Slices.
10836 01:03:01.393796 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10837 01:03:01.406695 <30>[ 20.430704] systemd[1]: Reached target Swap.
10838 01:03:01.410090 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10839 01:03:01.430587 <30>[ 20.451192] systemd[1]: Listening on initctl Compatibility Named Pipe.
10840 01:03:01.437739 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10841 01:03:01.444217 <30>[ 20.467137] systemd[1]: Listening on Journal Audit Socket.
10842 01:03:01.450548 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10843 01:03:01.468030 <30>[ 20.491796] systemd[1]: Listening on Journal Socket (/dev/log).
10844 01:03:01.474883 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10845 01:03:01.492214 <30>[ 20.515873] systemd[1]: Listening on Journal Socket.
10846 01:03:01.498436 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10847 01:03:01.515674 <30>[ 20.536229] systemd[1]: Listening on Network Service Netlink Socket.
10848 01:03:01.522114 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10849 01:03:01.536903 <30>[ 20.561005] systemd[1]: Listening on udev Control Socket.
10850 01:03:01.544082 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10851 01:03:01.559236 <30>[ 20.583129] systemd[1]: Listening on udev Kernel Socket.
10852 01:03:01.565633 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10853 01:03:01.615112 <30>[ 20.639197] systemd[1]: Mounting Huge Pages File System...
10854 01:03:01.622003 Mounting [0;1;39mHuge Pages File System[0m...
10855 01:03:01.637348 <30>[ 20.661031] systemd[1]: Mounting POSIX Message Queue File System...
10856 01:03:01.643892 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10857 01:03:01.661487 <30>[ 20.685646] systemd[1]: Mounting Kernel Debug File System...
10858 01:03:01.668335 Mounting [0;1;39mKernel Debug File System[0m...
10859 01:03:01.686289 <30>[ 20.707171] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10860 01:03:01.711234 <30>[ 20.732084] systemd[1]: Starting Create list of static device nodes for the current kernel...
10861 01:03:01.718226 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10862 01:03:01.739831 <30>[ 20.763591] systemd[1]: Starting Load Kernel Module configfs...
10863 01:03:01.745988 Starting [0;1;39mLoad Kernel Module configfs[0m...
10864 01:03:01.763331 <30>[ 20.787439] systemd[1]: Starting Load Kernel Module drm...
10865 01:03:01.770522 Starting [0;1;39mLoad Kernel Module drm[0m...
10866 01:03:01.787745 <30>[ 20.811601] systemd[1]: Starting Load Kernel Module fuse...
10867 01:03:01.794439 Starting [0;1;39mLoad Kernel Module fuse[0m...
10868 01:03:01.821970 <6>[ 20.845946] fuse: init (API version 7.37)
10869 01:03:01.831827 <30>[ 20.846749] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10870 01:03:01.863517 <30>[ 20.887418] systemd[1]: Starting Journal Service...
10871 01:03:01.867046 Starting [0;1;39mJournal Service[0m...
10872 01:03:01.891980 <30>[ 20.915579] systemd[1]: Starting Load Kernel Modules...
10873 01:03:01.897995 Starting [0;1;39mLoad Kernel Modules[0m...
10874 01:03:01.919955 <30>[ 20.940507] systemd[1]: Starting Remount Root and Kernel File Systems...
10875 01:03:01.926684 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10876 01:03:01.945242 <30>[ 20.968759] systemd[1]: Starting Coldplug All udev Devices...
10877 01:03:01.951671 Starting [0;1;39mColdplug All udev Devices[0m...
10878 01:03:01.969810 <30>[ 20.993901] systemd[1]: Mounted Huge Pages File System.
10879 01:03:01.977099 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10880 01:03:01.990397 <3>[ 21.010726] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 01:03:01.996993 <30>[ 21.020716] systemd[1]: Mounted POSIX Message Queue File System.
10882 01:03:02.003693 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10883 01:03:02.019637 <30>[ 21.042996] systemd[1]: Mounted Kernel Debug File System.
10884 01:03:02.029449 <3>[ 21.046844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 01:03:02.036103 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10886 01:03:02.055199 <30>[ 21.075535] systemd[1]: Finished Create list of static device nodes for the current kernel.
10887 01:03:02.061927 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10888 01:03:02.072241 <3>[ 21.092442] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 01:03:02.083835 <30>[ 21.108031] systemd[1]: modprobe@configfs.service: Succeeded.
10890 01:03:02.091246 <30>[ 21.115065] systemd[1]: Finished Load Kernel Module configfs.
10891 01:03:02.103048 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10892 01:03:02.114222 <3>[ 21.134916] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 01:03:02.125117 <30>[ 21.148843] systemd[1]: modprobe@drm.service: Succeeded.
10894 01:03:02.131888 <30>[ 21.155537] systemd[1]: Finished Load Kernel Module drm.
10895 01:03:02.138129 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10896 01:03:02.155429 <3>[ 21.175938] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 01:03:02.164467 <30>[ 21.188204] systemd[1]: modprobe@fuse.service: Succeeded.
10898 01:03:02.171790 <30>[ 21.195242] systemd[1]: Finished Load Kernel Module fuse.
10899 01:03:02.185178 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0<3>[ 21.205556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 01:03:02.188407 m.
10901 01:03:02.204580 <30>[ 21.228000] systemd[1]: Finished Load Kernel Modules.
10902 01:03:02.211104 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10903 01:03:02.221081 <3>[ 21.239959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 01:03:02.230974 <30>[ 21.251627] systemd[1]: Finished Remount Root and Kernel File Systems.
10905 01:03:02.237719 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10906 01:03:02.250552 <3>[ 21.271223] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 01:03:02.284190 <3>[ 21.304439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 01:03:02.298875 <30>[ 21.322630] systemd[1]: Mounting FUSE Control File System...
10909 01:03:02.306077 Mounting [0;1;39mFUSE Control File System[0m...
10910 01:03:02.316182 <3>[ 21.334912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 01:03:02.323952 <30>[ 21.347623] systemd[1]: Mounting Kernel Configuration File System...
10912 01:03:02.330952 Mounting [0;1;39mKernel Configuration File System[0m...
10913 01:03:02.358569 <30>[ 21.378909] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10914 01:03:02.368507 <30>[ 21.387958] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10915 01:03:02.399933 <30>[ 21.423745] systemd[1]: Starting Load/Save Random Seed...
10916 01:03:02.406776 Starting [0;1;39mLoad/Save Random Seed[0m...
10917 01:03:02.421881 <30>[ 21.445829] systemd[1]: Starting Apply Kernel Variables...
10918 01:03:02.428300 Starting [0;1;39mApply Kernel Variables[0m...
10919 01:03:02.451203 <30>[ 21.473705] systemd[1]: Starting Create System Users...
10920 01:03:02.467186 Startin<4>[ 21.479737] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10921 01:03:02.477090 g [0;1;39mCreat<3>[ 21.496684] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10922 01:03:02.477178 e System Users[0m...
10923 01:03:02.498276 <30>[ 21.521505] systemd[1]: Started Journal Service.
10924 01:03:02.501250 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10925 01:03:02.527482 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10926 01:03:02.539069 See 'systemctl status systemd-udev-trigger.service' for details.
10927 01:03:02.556099 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10928 01:03:02.575374 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10929 01:03:02.596556 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10930 01:03:02.616554 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10931 01:03:02.632550 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10932 01:03:02.667758 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10933 01:03:02.685128 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10934 01:03:02.717953 <46>[ 21.738992] systemd-journald[292]: Received client request to flush runtime journal.
10935 01:03:02.741060 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10936 01:03:02.755308 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10937 01:03:02.770906 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10938 01:03:02.835189 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10939 01:03:04.119820 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10940 01:03:04.171620 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10941 01:03:04.192993 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10942 01:03:04.225114 Starting [0;1;39mNetwork Service[0m...
10943 01:03:04.554729 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10944 01:03:04.583943 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10945 01:03:04.646958 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10946 01:03:04.798935 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10947 01:03:04.840826 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10948 01:03:04.875295 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10949 01:03:04.950130 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10950 01:03:04.971224 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10951 01:03:04.994649 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10952 01:03:05.014860 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10953 01:03:05.067583 Starting [0;1;39mNetwork Name Resolution[0m...
10954 01:03:05.092607 Starting [0;1;39mNetwork Time Synchronization[0m...
10955 01:03:05.112168 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10956 01:03:05.162052 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10957 01:03:05.284341 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10958 01:03:05.303085 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10959 01:03:05.325743 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10960 01:03:05.342787 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10961 01:03:05.358643 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10962 01:03:05.480580 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10963 01:03:05.524945 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10964 01:03:05.553129 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10965 01:03:05.918316 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10966 01:03:05.930340 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10967 01:03:06.185080 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10968 01:03:06.198609 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10969 01:03:06.214664 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10970 01:03:06.267086 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10971 01:03:06.362952 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10972 01:03:06.695389 Starting [0;1;39mUser Login Management[0m...
10973 01:03:06.792814 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10974 01:03:06.810802 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10975 01:03:06.829590 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10976 01:03:06.880410 Starting [0;1;39mPermit User Sessions[0m...
10977 01:03:06.936489 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10978 01:03:06.996137 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10979 01:03:07.067020 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10980 01:03:07.085064 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10981 01:03:07.102553 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10982 01:03:07.120493 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 01:03:07.139890 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10984 01:03:07.154384 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10985 01:03:07.207482 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10986 01:03:07.248580 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10987 01:03:07.315091
10988 01:03:07.315211
10989 01:03:07.318744 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10990 01:03:07.318828
10991 01:03:07.321854 debian-bullseye-arm64 login: root (automatic login)
10992 01:03:07.321937
10993 01:03:07.322016
10994 01:03:07.615116 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
10995 01:03:07.615261
10996 01:03:07.621375 The programs included with the Debian GNU/Linux system are free software;
10997 01:03:07.628405 the exact distribution terms for each program are described in the
10998 01:03:07.631464 individual files in /usr/share/doc/*/copyright.
10999 01:03:07.631547
11000 01:03:07.638258 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11001 01:03:07.641286 permitted by applicable law.
11002 01:03:08.502414 Matched prompt #10: / #
11004 01:03:08.502702 Setting prompt string to ['/ #']
11005 01:03:08.502796 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11007 01:03:08.502990 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11008 01:03:08.503079 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
11009 01:03:08.503148 Setting prompt string to ['/ #']
11010 01:03:08.503208 Forcing a shell prompt, looking for ['/ #']
11012 01:03:08.553423 / #
11013 01:03:08.553534 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11014 01:03:08.553612 Waiting using forced prompt support (timeout 00:02:30)
11015 01:03:08.558567
11016 01:03:08.558840 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11017 01:03:08.558939 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
11019 01:03:08.659297 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r'
11020 01:03:08.664057 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571086/extract-nfsrootfs-87k20i7r'
11022 01:03:08.764592 / # export NFS_SERVER_IP='192.168.201.1'
11023 01:03:08.769865 export NFS_SERVER_IP='192.168.201.1'
11024 01:03:08.770158 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11025 01:03:08.770261 end: 2.2 depthcharge-retry (duration 00:01:27) [common]
11026 01:03:08.770354 end: 2 depthcharge-action (duration 00:01:27) [common]
11027 01:03:08.770444 start: 3 lava-test-retry (timeout 00:07:52) [common]
11028 01:03:08.770532 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
11029 01:03:08.770607 Using namespace: common
11031 01:03:08.870940 / # #
11032 01:03:08.871066 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11033 01:03:08.876125 #
11034 01:03:08.876391 Using /lava-12571086
11036 01:03:08.976686 / # export SHELL=/bin/bash
11037 01:03:08.981943 export SHELL=/bin/bash
11039 01:03:09.082373 / # . /lava-12571086/environment
11040 01:03:09.088161 . /lava-12571086/environment
11042 01:03:09.193199 / # /lava-12571086/bin/lava-test-runner /lava-12571086/0
11043 01:03:09.193360 Test shell timeout: 10s (minimum of the action and connection timeout)
11044 01:03:09.198725 /lava-12571086/bin/lava-test-runner /lava-12571086/0
11045 01:03:09.414775 + export TESTRUN_ID=0_timesync-off
11046 01:03:09.418684 + TESTRUN_ID=0_timesync-off
11047 01:03:09.422479 + cd /lava-12571086/0/tests/0_timesync-off
11048 01:03:09.425149 ++ cat uuid
11049 01:03:09.425258 + UUID=12571086_1.6.2.3.1
11050 01:03:09.428455 + set +x
11051 01:03:09.431728 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12571086_1.6.2.3.1>
11052 01:03:09.432010 Received signal: <STARTRUN> 0_timesync-off 12571086_1.6.2.3.1
11053 01:03:09.432112 Starting test lava.0_timesync-off (12571086_1.6.2.3.1)
11054 01:03:09.432224 Skipping test definition patterns.
11055 01:03:09.434648 + systemctl stop systemd-timesyncd
11056 01:03:09.489713 + set +x
11057 01:03:09.492967 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12571086_1.6.2.3.1>
11058 01:03:09.493230 Received signal: <ENDRUN> 0_timesync-off 12571086_1.6.2.3.1
11059 01:03:09.493316 Ending use of test pattern.
11060 01:03:09.493379 Ending test lava.0_timesync-off (12571086_1.6.2.3.1), duration 0.06
11062 01:03:09.539999 + export TESTRUN_ID=1_kselftest-rtc
11063 01:03:09.543407 + TESTRUN_ID=1_kselftest-rtc
11064 01:03:09.546354 + cd /lava-12571086/0/tests/1_kselftest-rtc
11065 01:03:09.549633 ++ cat uuid
11066 01:03:09.549718 + UUID=12571086_1.6.2.3.5
11067 01:03:09.553472 + set +x
11068 01:03:09.556500 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12571086_1.6.2.3.5>
11069 01:03:09.556759 Received signal: <STARTRUN> 1_kselftest-rtc 12571086_1.6.2.3.5
11070 01:03:09.556831 Starting test lava.1_kselftest-rtc (12571086_1.6.2.3.5)
11071 01:03:09.556913 Skipping test definition patterns.
11072 01:03:09.559506 + cd ./automated/linux/kselftest/
11073 01:03:09.586390 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11074 01:03:09.608142 INFO: install_deps skipped
11075 01:03:09.712905 --2024-01-19 01:00:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11076 01:03:09.722251 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11077 01:03:09.854789 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11078 01:03:09.989931 HTTP request sent, awaiting response... 200 OK
11079 01:03:09.993501 Length: 2966476 (2.8M) [application/octet-stream]
11080 01:03:09.996456 Saving to: 'kselftest.tar.xz'
11081 01:03:09.996536
11082 01:03:09.996603
11083 01:03:10.255656 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11084 01:03:10.521863 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11085 01:03:10.968973 kselftest.tar.xz 7%[> ] 218.91K 413KB/s
11086 01:03:11.242658 kselftest.tar.xz 28%[====> ] 817.06K 836KB/s
11087 01:03:11.322402 kselftest.tar.xz 82%[===============> ] 2.33M 1.86MB/s
11088 01:03:11.329493 kselftest.tar.xz 100%[===================>] 2.83M 2.13MB/s in 1.3s
11089 01:03:11.329592
11090 01:03:11.586222 2024-01-19 01:00:31 (2.13 MB/s) - 'kselftest.tar.xz' saved [2966476/2966476]
11091 01:03:11.586362
11092 01:03:16.588981 skiplist:
11093 01:03:16.592490 ========================================
11094 01:03:16.595793 ========================================
11095 01:03:16.629081 rtc:rtctest
11096 01:03:16.645025 ============== Tests to run ===============
11097 01:03:16.645121 rtc:rtctest
11098 01:03:16.648836 ===========End Tests to run ===============
11099 01:03:16.651947 shardfile-rtc pass
11100 01:03:16.742368 <12>[ 35.767848] kselftest: Running tests in rtc
11101 01:03:16.751690 TAP version 13
11102 01:03:16.763782 1..1
11103 01:03:16.794576 # selftests: rtc: rtctest
11104 01:03:17.217753 # TAP version 13
11105 01:03:17.218327 # 1..8
11106 01:03:17.220545 # # Starting 8 tests from 2 test cases.
11107 01:03:17.223847 # # RUN rtc.date_read ...
11108 01:03:17.230620 # # rtctest.c:49:date_read:Current RTC date/time is 19/01/2024 01:00:37.
11109 01:03:17.233932 # # OK rtc.date_read
11110 01:03:17.237384 # ok 1 rtc.date_read
11111 01:03:17.240773 # # RUN rtc.date_read_loop ...
11112 01:03:17.250754 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11113 01:03:27.128559 <6>[ 46.158654] vpu: disabling
11114 01:03:27.131898 <6>[ 46.161760] vproc2: disabling
11115 01:03:27.135138 <6>[ 46.165086] vproc1: disabling
11116 01:03:27.138666 <6>[ 46.168396] vaud18: disabling
11117 01:03:27.145491 <6>[ 46.172102] vsram_others: disabling
11118 01:03:27.148680 <6>[ 46.176065] va09: disabling
11119 01:03:27.151960 <6>[ 46.179233] vsram_md: disabling
11120 01:03:27.155108 <6>[ 46.182796] Vgpu: disabling
11121 01:03:47.822404 # # rtctest.c:115:date_read_loop:Performed 2699 RTC time reads.
11122 01:03:47.825997 # # OK rtc.date_read_loop
11123 01:03:47.829133 # ok 2 rtc.date_read_loop
11124 01:03:47.832065 # # RUN rtc.uie_read ...
11125 01:03:50.803462 # # OK rtc.uie_read
11126 01:03:50.806021 # ok 3 rtc.uie_read
11127 01:03:50.809398 # # RUN rtc.uie_select ...
11128 01:03:53.803113 # # OK rtc.uie_select
11129 01:03:53.806049 # ok 4 rtc.uie_select
11130 01:03:53.809491 # # RUN rtc.alarm_alm_set ...
11131 01:03:53.816174 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 01:01:17.
11132 01:03:53.819569 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11133 01:03:53.826098 # # alarm_alm_set: Test terminated by assertion
11134 01:03:53.829603 # # FAIL rtc.alarm_alm_set
11135 01:03:53.829693 # not ok 5 rtc.alarm_alm_set
11136 01:03:53.836061 # # RUN rtc.alarm_wkalm_set ...
11137 01:03:53.842719 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 19/01/2024 01:01:17.
11138 01:03:56.805086 # # OK rtc.alarm_wkalm_set
11139 01:03:56.805236 # ok 6 rtc.alarm_wkalm_set
11140 01:03:56.811688 # # RUN rtc.alarm_alm_set_minute ...
11141 01:03:56.815340 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 01:02:00.
11142 01:03:56.822391 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11143 01:03:56.828199 # # alarm_alm_set_minute: Test terminated by assertion
11144 01:03:56.831601 # # FAIL rtc.alarm_alm_set_minute
11145 01:03:56.834967 # not ok 7 rtc.alarm_alm_set_minute
11146 01:03:56.838329 # # RUN rtc.alarm_wkalm_set_minute ...
11147 01:03:56.844766 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 19/01/2024 01:02:00.
11148 01:04:39.800539 # # OK rtc.alarm_wkalm_set_minute
11149 01:04:39.804049 # ok 8 rtc.alarm_wkalm_set_minute
11150 01:04:39.807004 # # FAILED: 6 / 8 tests passed.
11151 01:04:39.810264 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11152 01:04:39.813563 not ok 1 selftests: rtc: rtctest # exit=1
11153 01:04:40.394240 rtc_rtctest_rtc_date_read pass
11154 01:04:40.397947 rtc_rtctest_rtc_date_read_loop pass
11155 01:04:40.400806 rtc_rtctest_rtc_uie_read pass
11156 01:04:40.404046 rtc_rtctest_rtc_uie_select pass
11157 01:04:40.407349 rtc_rtctest_rtc_alarm_alm_set fail
11158 01:04:40.410890 rtc_rtctest_rtc_alarm_wkalm_set pass
11159 01:04:40.414204 rtc_rtctest_rtc_alarm_alm_set_minute fail
11160 01:04:40.417359 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11161 01:04:40.420555 rtc_rtctest fail
11162 01:04:40.423840 + ../../utils/send-to-lava.sh ./output/result.txt
11163 01:04:40.488033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11164 01:04:40.488329 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11166 01:04:40.532467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11167 01:04:40.532731 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11169 01:04:40.577684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11170 01:04:40.577952 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11172 01:04:40.615950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11173 01:04:40.616211 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11175 01:04:40.655720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11176 01:04:40.655979 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11178 01:04:40.697390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11179 01:04:40.697656 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11181 01:04:40.738826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11182 01:04:40.739112 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11184 01:04:40.782471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11185 01:04:40.782763 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11187 01:04:40.829362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11188 01:04:40.829627 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11190 01:04:40.871226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11191 01:04:40.871324 + set +x
11192 01:04:40.871566 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11194 01:04:40.877782 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12571086_1.6.2.3.5>
11195 01:04:40.877867 <LAVA_TEST_RUNNER EXIT>
11196 01:04:40.878105 Received signal: <ENDRUN> 1_kselftest-rtc 12571086_1.6.2.3.5
11197 01:04:40.878181 Ending use of test pattern.
11198 01:04:40.878243 Ending test lava.1_kselftest-rtc (12571086_1.6.2.3.5), duration 91.32
11200 01:04:40.878461 ok: lava_test_shell seems to have completed
11201 01:04:40.878594 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11202 01:04:40.878688 end: 3.1 lava-test-shell (duration 00:01:32) [common]
11203 01:04:40.878772 end: 3 lava-test-retry (duration 00:01:32) [common]
11204 01:04:40.878858 start: 4 finalize (timeout 00:06:20) [common]
11205 01:04:40.878951 start: 4.1 power-off (timeout 00:00:30) [common]
11206 01:04:40.879181 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11207 01:04:40.955878 >> Command sent successfully.
11208 01:04:40.958289 Returned 0 in 0 seconds
11209 01:04:41.058698 end: 4.1 power-off (duration 00:00:00) [common]
11211 01:04:41.059031 start: 4.2 read-feedback (timeout 00:06:20) [common]
11212 01:04:41.059304 Listened to connection for namespace 'common' for up to 1s
11213 01:04:41.059592 Listened to connection for namespace 'common' for up to 1s
11214 01:04:42.060244 Finalising connection for namespace 'common'
11215 01:04:42.060418 Disconnecting from shell: Finalise
11216 01:04:42.060500 / #
11217 01:04:42.160826 end: 4.2 read-feedback (duration 00:00:01) [common]
11218 01:04:42.160979 end: 4 finalize (duration 00:00:01) [common]
11219 01:04:42.161098 Cleaning after the job
11220 01:04:42.161196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/ramdisk
11221 01:04:42.164024 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/kernel
11222 01:04:42.177057 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/dtb
11223 01:04:42.177240 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/nfsrootfs
11224 01:04:42.269458 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571086/tftp-deploy-gwbojakf/modules
11225 01:04:42.277041 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571086
11226 01:04:42.925924 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571086
11227 01:04:42.926107 Job finished correctly