Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 17
- Errors: 1
- Kernel Errors: 38
- Boot result: PASS
1 00:55:13.297895 lava-dispatcher, installed at version: 2023.10
2 00:55:13.298117 start: 0 validate
3 00:55:13.298250 Start time: 2024-01-19 00:55:13.298242+00:00 (UTC)
4 00:55:13.298377 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:55:13.298507 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 00:55:13.565562 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:55:13.565728 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:13.566783 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:13.566903 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:13.836055 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:13.836234 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:14.367456 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:14.367677 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:14.370902 validate duration: 1.07
16 00:55:14.371224 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:14.371415 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:14.371548 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:14.371726 Not decompressing ramdisk as can be used compressed.
20 00:55:14.371859 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 00:55:14.371955 saving as /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/ramdisk/initrd.cpio.gz
22 00:55:14.372085 total size: 4665412 (4 MB)
23 00:55:14.373459 progress 0 % (0 MB)
24 00:55:14.376004 progress 5 % (0 MB)
25 00:55:14.378035 progress 10 % (0 MB)
26 00:55:14.380092 progress 15 % (0 MB)
27 00:55:14.382169 progress 20 % (0 MB)
28 00:55:14.384319 progress 25 % (1 MB)
29 00:55:14.386338 progress 30 % (1 MB)
30 00:55:14.388389 progress 35 % (1 MB)
31 00:55:14.390414 progress 40 % (1 MB)
32 00:55:14.392737 progress 45 % (2 MB)
33 00:55:14.394695 progress 50 % (2 MB)
34 00:55:14.396745 progress 55 % (2 MB)
35 00:55:14.398730 progress 60 % (2 MB)
36 00:55:14.400808 progress 65 % (2 MB)
37 00:55:14.402833 progress 70 % (3 MB)
38 00:55:14.404499 progress 75 % (3 MB)
39 00:55:14.405908 progress 80 % (3 MB)
40 00:55:14.407317 progress 85 % (3 MB)
41 00:55:14.408686 progress 90 % (4 MB)
42 00:55:14.410144 progress 95 % (4 MB)
43 00:55:14.411470 progress 100 % (4 MB)
44 00:55:14.411715 4 MB downloaded in 0.04 s (112.27 MB/s)
45 00:55:14.411892 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:55:14.412166 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:55:14.412251 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:55:14.412334 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:55:14.412472 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:14.412543 saving as /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/kernel/Image
52 00:55:14.412642 total size: 51532288 (49 MB)
53 00:55:14.412702 No compression specified
54 00:55:14.413970 progress 0 % (0 MB)
55 00:55:14.428751 progress 5 % (2 MB)
56 00:55:14.443249 progress 10 % (4 MB)
57 00:55:14.457413 progress 15 % (7 MB)
58 00:55:14.471529 progress 20 % (9 MB)
59 00:55:14.485383 progress 25 % (12 MB)
60 00:55:14.498991 progress 30 % (14 MB)
61 00:55:14.514359 progress 35 % (17 MB)
62 00:55:14.528693 progress 40 % (19 MB)
63 00:55:14.542403 progress 45 % (22 MB)
64 00:55:14.556454 progress 50 % (24 MB)
65 00:55:14.569826 progress 55 % (27 MB)
66 00:55:14.584116 progress 60 % (29 MB)
67 00:55:14.598463 progress 65 % (31 MB)
68 00:55:14.612906 progress 70 % (34 MB)
69 00:55:14.627103 progress 75 % (36 MB)
70 00:55:14.641383 progress 80 % (39 MB)
71 00:55:14.656452 progress 85 % (41 MB)
72 00:55:14.671247 progress 90 % (44 MB)
73 00:55:14.685904 progress 95 % (46 MB)
74 00:55:14.700908 progress 100 % (49 MB)
75 00:55:14.701215 49 MB downloaded in 0.29 s (170.31 MB/s)
76 00:55:14.701420 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:14.701785 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:14.701987 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:55:14.702157 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:55:14.702342 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:55:14.702443 saving as /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/dtb/mt8192-asurada-spherion-r0.dtb
83 00:55:14.702513 total size: 47278 (0 MB)
84 00:55:14.702591 No compression specified
85 00:55:14.704004 progress 69 % (0 MB)
86 00:55:14.704347 progress 100 % (0 MB)
87 00:55:14.704570 0 MB downloaded in 0.00 s (21.94 MB/s)
88 00:55:14.704767 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:14.705109 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:14.705225 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:55:14.705309 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:55:14.705448 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 00:55:14.705515 saving as /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/nfsrootfs/full.rootfs.tar
95 00:55:14.705574 total size: 125290964 (119 MB)
96 00:55:14.705638 Using unxz to decompress xz
97 00:55:14.710353 progress 0 % (0 MB)
98 00:55:15.046966 progress 5 % (6 MB)
99 00:55:15.392069 progress 10 % (11 MB)
100 00:55:15.751465 progress 15 % (17 MB)
101 00:55:15.943961 progress 20 % (23 MB)
102 00:55:16.120674 progress 25 % (29 MB)
103 00:55:16.498803 progress 30 % (35 MB)
104 00:55:16.872952 progress 35 % (41 MB)
105 00:55:17.279016 progress 40 % (47 MB)
106 00:55:17.667994 progress 45 % (53 MB)
107 00:55:18.070419 progress 50 % (59 MB)
108 00:55:18.443402 progress 55 % (65 MB)
109 00:55:18.820352 progress 60 % (71 MB)
110 00:55:19.178958 progress 65 % (77 MB)
111 00:55:19.562052 progress 70 % (83 MB)
112 00:55:19.957629 progress 75 % (89 MB)
113 00:55:20.397899 progress 80 % (95 MB)
114 00:55:20.833994 progress 85 % (101 MB)
115 00:55:21.096145 progress 90 % (107 MB)
116 00:55:21.456007 progress 95 % (113 MB)
117 00:55:21.832876 progress 100 % (119 MB)
118 00:55:21.838909 119 MB downloaded in 7.13 s (16.75 MB/s)
119 00:55:21.839240 end: 1.4.1 http-download (duration 00:00:07) [common]
121 00:55:21.839667 end: 1.4 download-retry (duration 00:00:07) [common]
122 00:55:21.839767 start: 1.5 download-retry (timeout 00:09:53) [common]
123 00:55:21.839859 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 00:55:21.840017 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:55:21.840107 saving as /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/modules/modules.tar
126 00:55:21.840207 total size: 8625444 (8 MB)
127 00:55:21.840305 Using unxz to decompress xz
128 00:55:21.844931 progress 0 % (0 MB)
129 00:55:21.867503 progress 5 % (0 MB)
130 00:55:21.893187 progress 10 % (0 MB)
131 00:55:21.918637 progress 15 % (1 MB)
132 00:55:21.943843 progress 20 % (1 MB)
133 00:55:21.969145 progress 25 % (2 MB)
134 00:55:21.995681 progress 30 % (2 MB)
135 00:55:22.022784 progress 35 % (2 MB)
136 00:55:22.047188 progress 40 % (3 MB)
137 00:55:22.072202 progress 45 % (3 MB)
138 00:55:22.098212 progress 50 % (4 MB)
139 00:55:22.123193 progress 55 % (4 MB)
140 00:55:22.148857 progress 60 % (4 MB)
141 00:55:22.177164 progress 65 % (5 MB)
142 00:55:22.202762 progress 70 % (5 MB)
143 00:55:22.226715 progress 75 % (6 MB)
144 00:55:22.254408 progress 80 % (6 MB)
145 00:55:22.280743 progress 85 % (7 MB)
146 00:55:22.306393 progress 90 % (7 MB)
147 00:55:22.340800 progress 95 % (7 MB)
148 00:55:22.371239 progress 100 % (8 MB)
149 00:55:22.376389 8 MB downloaded in 0.54 s (15.34 MB/s)
150 00:55:22.376667 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:55:22.376945 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:55:22.377042 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 00:55:22.377147 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 00:55:24.658416 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk
156 00:55:24.658615 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:55:24.658718 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 00:55:24.658888 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_
159 00:55:24.659019 makedir: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin
160 00:55:24.659121 makedir: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/tests
161 00:55:24.659220 makedir: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/results
162 00:55:24.659321 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-add-keys
163 00:55:24.659510 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-add-sources
164 00:55:24.659642 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-background-process-start
165 00:55:24.659772 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-background-process-stop
166 00:55:24.659901 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-common-functions
167 00:55:24.660029 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-echo-ipv4
168 00:55:24.660159 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-install-packages
169 00:55:24.660288 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-installed-packages
170 00:55:24.660414 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-os-build
171 00:55:24.660541 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-probe-channel
172 00:55:24.660668 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-probe-ip
173 00:55:24.660794 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-target-ip
174 00:55:24.660920 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-target-mac
175 00:55:24.661047 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-target-storage
176 00:55:24.661176 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-case
177 00:55:24.661307 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-event
178 00:55:24.661435 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-feedback
179 00:55:24.661562 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-raise
180 00:55:24.661687 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-reference
181 00:55:24.661815 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-runner
182 00:55:24.661941 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-set
183 00:55:24.662068 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-test-shell
184 00:55:24.662197 Updating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-install-packages (oe)
185 00:55:24.662358 Updating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/bin/lava-installed-packages (oe)
186 00:55:24.662484 Creating /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/environment
187 00:55:24.662584 LAVA metadata
188 00:55:24.662655 - LAVA_JOB_ID=12571137
189 00:55:24.662719 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:55:24.662820 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 00:55:24.662887 skipped lava-vland-overlay
192 00:55:24.662961 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:55:24.663040 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 00:55:24.663100 skipped lava-multinode-overlay
195 00:55:24.663173 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:55:24.663250 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 00:55:24.663324 Loading test definitions
198 00:55:24.663454 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 00:55:24.663525 Using /lava-12571137 at stage 0
200 00:55:24.663831 uuid=12571137_1.6.2.3.1 testdef=None
201 00:55:24.663921 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:55:24.664005 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 00:55:24.664518 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:55:24.664735 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 00:55:24.665389 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:55:24.665618 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 00:55:24.666241 runner path: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/0/tests/0_dmesg test_uuid 12571137_1.6.2.3.1
210 00:55:24.666397 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:55:24.666619 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 00:55:24.666691 Using /lava-12571137 at stage 1
214 00:55:24.667133 uuid=12571137_1.6.2.3.5 testdef=None
215 00:55:24.667253 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 00:55:24.667655 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 00:55:24.668137 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 00:55:24.668352 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 00:55:24.668992 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 00:55:24.669217 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 00:55:24.669911 runner path: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/1/tests/1_bootrr test_uuid 12571137_1.6.2.3.5
224 00:55:24.670065 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 00:55:24.670267 Creating lava-test-runner.conf files
227 00:55:24.670329 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/0 for stage 0
228 00:55:24.670420 - 0_dmesg
229 00:55:24.670500 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571137/lava-overlay-5r2osh6_/lava-12571137/1 for stage 1
230 00:55:24.670592 - 1_bootrr
231 00:55:24.670687 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 00:55:24.670772 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 00:55:24.678412 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 00:55:24.678516 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 00:55:24.678602 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 00:55:24.678688 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 00:55:24.678773 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 00:55:24.801289 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 00:55:24.801842 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 00:55:24.801962 extracting modules file /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk
241 00:55:25.027200 extracting modules file /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571137/extract-overlay-ramdisk-dxsprdiq/ramdisk
242 00:55:25.260592 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 00:55:25.260767 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 00:55:25.260863 [common] Applying overlay to NFS
245 00:55:25.260936 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571137/compress-overlay-2q0r09x6/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk
246 00:55:25.269608 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 00:55:25.269757 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 00:55:25.269883 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 00:55:25.270010 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 00:55:25.270121 Building ramdisk /var/lib/lava/dispatcher/tmp/12571137/extract-overlay-ramdisk-dxsprdiq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571137/extract-overlay-ramdisk-dxsprdiq/ramdisk
251 00:55:25.578291 >> 119414 blocks
252 00:55:27.504415 rename /var/lib/lava/dispatcher/tmp/12571137/extract-overlay-ramdisk-dxsprdiq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/ramdisk/ramdisk.cpio.gz
253 00:55:27.504991 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 00:55:27.505160 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 00:55:27.505310 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 00:55:27.505472 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/kernel/Image'
257 00:55:40.849912 Returned 0 in 13 seconds
258 00:55:40.950650 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/kernel/image.itb
259 00:55:41.332781 output: FIT description: Kernel Image image with one or more FDT blobs
260 00:55:41.333228 output: Created: Fri Jan 19 00:55:41 2024
261 00:55:41.333329 output: Image 0 (kernel-1)
262 00:55:41.333416 output: Description:
263 00:55:41.333496 output: Created: Fri Jan 19 00:55:41 2024
264 00:55:41.333578 output: Type: Kernel Image
265 00:55:41.333657 output: Compression: lzma compressed
266 00:55:41.333738 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
267 00:55:41.333812 output: Architecture: AArch64
268 00:55:41.333886 output: OS: Linux
269 00:55:41.333961 output: Load Address: 0x00000000
270 00:55:41.334038 output: Entry Point: 0x00000000
271 00:55:41.334117 output: Hash algo: crc32
272 00:55:41.334192 output: Hash value: a52aa383
273 00:55:41.334270 output: Image 1 (fdt-1)
274 00:55:41.334345 output: Description: mt8192-asurada-spherion-r0
275 00:55:41.334418 output: Created: Fri Jan 19 00:55:41 2024
276 00:55:41.334491 output: Type: Flat Device Tree
277 00:55:41.334564 output: Compression: uncompressed
278 00:55:41.334636 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 00:55:41.334709 output: Architecture: AArch64
280 00:55:41.334781 output: Hash algo: crc32
281 00:55:41.334852 output: Hash value: cc4352de
282 00:55:41.334924 output: Image 2 (ramdisk-1)
283 00:55:41.334995 output: Description: unavailable
284 00:55:41.335067 output: Created: Fri Jan 19 00:55:41 2024
285 00:55:41.335138 output: Type: RAMDisk Image
286 00:55:41.335210 output: Compression: Unknown Compression
287 00:55:41.335282 output: Data Size: 17795171 Bytes = 17378.10 KiB = 16.97 MiB
288 00:55:41.335355 output: Architecture: AArch64
289 00:55:41.335471 output: OS: Linux
290 00:55:41.335542 output: Load Address: unavailable
291 00:55:41.335614 output: Entry Point: unavailable
292 00:55:41.335686 output: Hash algo: crc32
293 00:55:41.335757 output: Hash value: 4998b3a1
294 00:55:41.335829 output: Default Configuration: 'conf-1'
295 00:55:41.335900 output: Configuration 0 (conf-1)
296 00:55:41.335972 output: Description: mt8192-asurada-spherion-r0
297 00:55:41.336044 output: Kernel: kernel-1
298 00:55:41.336116 output: Init Ramdisk: ramdisk-1
299 00:55:41.336187 output: FDT: fdt-1
300 00:55:41.336257 output: Loadables: kernel-1
301 00:55:41.336328 output:
302 00:55:41.336577 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 00:55:41.336706 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 00:55:41.336835 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 00:55:41.336959 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 00:55:41.337062 No LXC device requested
307 00:55:41.337163 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 00:55:41.337274 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 00:55:41.337377 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 00:55:41.337474 Checking files for TFTP limit of 4294967296 bytes.
311 00:55:41.338096 end: 1 tftp-deploy (duration 00:00:27) [common]
312 00:55:41.338224 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 00:55:41.338339 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 00:55:41.338494 substitutions:
315 00:55:41.338582 - {DTB}: 12571137/tftp-deploy-13ghr7el/dtb/mt8192-asurada-spherion-r0.dtb
316 00:55:41.338664 - {INITRD}: 12571137/tftp-deploy-13ghr7el/ramdisk/ramdisk.cpio.gz
317 00:55:41.338742 - {KERNEL}: 12571137/tftp-deploy-13ghr7el/kernel/Image
318 00:55:41.338820 - {LAVA_MAC}: None
319 00:55:41.338895 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk
320 00:55:41.338971 - {NFS_SERVER_IP}: 192.168.201.1
321 00:55:41.339045 - {PRESEED_CONFIG}: None
322 00:55:41.339119 - {PRESEED_LOCAL}: None
323 00:55:41.339195 - {RAMDISK}: 12571137/tftp-deploy-13ghr7el/ramdisk/ramdisk.cpio.gz
324 00:55:41.339270 - {ROOT_PART}: None
325 00:55:41.339369 - {ROOT}: None
326 00:55:41.339459 - {SERVER_IP}: 192.168.201.1
327 00:55:41.339533 - {TEE}: None
328 00:55:41.339605 Parsed boot commands:
329 00:55:41.339678 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 00:55:41.339902 Parsed boot commands: tftpboot 192.168.201.1 12571137/tftp-deploy-13ghr7el/kernel/image.itb 12571137/tftp-deploy-13ghr7el/kernel/cmdline
331 00:55:41.340018 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 00:55:41.340130 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 00:55:41.340251 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 00:55:41.340358 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 00:55:41.340454 Not connected, no need to disconnect.
336 00:55:41.340553 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 00:55:41.340661 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 00:55:41.340748 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
339 00:55:41.345482 Setting prompt string to ['lava-test: # ']
340 00:55:41.346064 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 00:55:41.346291 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 00:55:41.346501 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 00:55:41.346703 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 00:55:41.347022 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 00:55:46.486662 >> Command sent successfully.
346 00:55:46.489697 Returned 0 in 5 seconds
347 00:55:46.590140 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 00:55:46.590481 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 00:55:46.590582 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 00:55:46.590674 Setting prompt string to 'Starting depthcharge on Spherion...'
352 00:55:46.590742 Changing prompt to 'Starting depthcharge on Spherion...'
353 00:55:46.590812 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 00:55:46.591093 [Enter `^Ec?' for help]
355 00:55:46.765154
356 00:55:46.765321
357 00:55:46.765396 F0: 102B 0000
358 00:55:46.765464
359 00:55:46.765526 F3: 1001 0000 [0200]
360 00:55:46.768576
361 00:55:46.768672 F3: 1001 0000
362 00:55:46.768741
363 00:55:46.768803 F7: 102D 0000
364 00:55:46.768863
365 00:55:46.772015 F1: 0000 0000
366 00:55:46.772114
367 00:55:46.772182 V0: 0000 0000 [0001]
368 00:55:46.772249
369 00:55:46.775250 00: 0007 8000
370 00:55:46.775360
371 00:55:46.775441 01: 0000 0000
372 00:55:46.775506
373 00:55:46.778307 BP: 0C00 0209 [0000]
374 00:55:46.778396
375 00:55:46.778464 G0: 1182 0000
376 00:55:46.778528
377 00:55:46.781733 EC: 0000 0021 [4000]
378 00:55:46.781824
379 00:55:46.781891 S7: 0000 0000 [0000]
380 00:55:46.781955
381 00:55:46.785361 CC: 0000 0000 [0001]
382 00:55:46.785457
383 00:55:46.785526 T0: 0000 0040 [010F]
384 00:55:46.785595
385 00:55:46.785656 Jump to BL
386 00:55:46.788548
387 00:55:46.812098
388 00:55:46.812257
389 00:55:46.812326
390 00:55:46.818727 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 00:55:46.822365 ARM64: Exception handlers installed.
392 00:55:46.826099 ARM64: Testing exception
393 00:55:46.829038 ARM64: Done test exception
394 00:55:46.836243 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 00:55:46.846122 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 00:55:46.853465 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 00:55:46.863028 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 00:55:46.869667 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 00:55:46.879558 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 00:55:46.890266 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 00:55:46.896958 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 00:55:46.915635 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 00:55:46.918252 WDT: Last reset was cold boot
404 00:55:46.921880 SPI1(PAD0) initialized at 2873684 Hz
405 00:55:46.924918 SPI5(PAD0) initialized at 992727 Hz
406 00:55:46.927981 VBOOT: Loading verstage.
407 00:55:46.934551 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 00:55:46.938015 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 00:55:46.941287 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 00:55:46.944744 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 00:55:46.952632 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 00:55:46.960089 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 00:55:46.969857 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 00:55:46.969995
415 00:55:46.970066
416 00:55:46.979964 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 00:55:46.983082 ARM64: Exception handlers installed.
418 00:55:46.986521 ARM64: Testing exception
419 00:55:46.990408 ARM64: Done test exception
420 00:55:46.993813 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 00:55:46.996877 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 00:55:47.011087 Probing TPM: . done!
423 00:55:47.011236 TPM ready after 0 ms
424 00:55:47.019407 Connected to device vid:did:rid of 1ae0:0028:00
425 00:55:47.025629 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 00:55:47.084295 Initialized TPM device CR50 revision 0
427 00:55:47.095965 tlcl_send_startup: Startup return code is 0
428 00:55:47.096117 TPM: setup succeeded
429 00:55:47.107167 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 00:55:47.116126 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 00:55:47.128669 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 00:55:47.138263 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 00:55:47.141381 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 00:55:47.145609 in-header: 03 07 00 00 08 00 00 00
435 00:55:47.149032 in-data: aa e4 47 04 13 02 00 00
436 00:55:47.153072 Chrome EC: UHEPI supported
437 00:55:47.159589 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 00:55:47.163864 in-header: 03 95 00 00 08 00 00 00
439 00:55:47.167292 in-data: 18 20 20 08 00 00 00 00
440 00:55:47.167448 Phase 1
441 00:55:47.171127 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 00:55:47.174991 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 00:55:47.182192 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 00:55:47.186020 Recovery requested (1009000e)
445 00:55:47.193786 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 00:55:47.199189 tlcl_extend: response is 0
447 00:55:47.208869 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 00:55:47.214604 tlcl_extend: response is 0
449 00:55:47.221355 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 00:55:47.241240 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 00:55:47.247984 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 00:55:47.248151
453 00:55:47.248254
454 00:55:47.257542 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 00:55:47.260944 ARM64: Exception handlers installed.
456 00:55:47.264209 ARM64: Testing exception
457 00:55:47.264334 ARM64: Done test exception
458 00:55:47.286898 pmic_efuse_setting: Set efuses in 11 msecs
459 00:55:47.289921 pmwrap_interface_init: Select PMIF_VLD_RDY
460 00:55:47.297017 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 00:55:47.299537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 00:55:47.306497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 00:55:47.310655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 00:55:47.313855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 00:55:47.321478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 00:55:47.324925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 00:55:47.328566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 00:55:47.335945 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 00:55:47.339595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 00:55:47.343422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 00:55:47.346976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 00:55:47.350903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 00:55:47.358790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 00:55:47.366211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 00:55:47.369542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 00:55:47.376924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 00:55:47.380723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 00:55:47.387902 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 00:55:47.391677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 00:55:47.399497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 00:55:47.402897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 00:55:47.410347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 00:55:47.413819 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 00:55:47.421402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 00:55:47.424754 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 00:55:47.432230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 00:55:47.436149 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 00:55:47.439553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 00:55:47.446915 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 00:55:47.450687 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 00:55:47.453796 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 00:55:47.461120 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 00:55:47.464772 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 00:55:47.472015 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 00:55:47.475957 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 00:55:47.479661 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 00:55:47.487313 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 00:55:47.490789 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 00:55:47.494339 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 00:55:47.497671 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 00:55:47.504840 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 00:55:47.508524 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 00:55:47.511856 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 00:55:47.515596 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 00:55:47.522668 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 00:55:47.526477 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 00:55:47.530074 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 00:55:47.533351 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 00:55:47.536879 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 00:55:47.540696 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 00:55:47.548204 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 00:55:47.558756 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 00:55:47.562352 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 00:55:47.569145 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 00:55:47.580410 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 00:55:47.583835 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 00:55:47.588016 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 00:55:47.592045 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 00:55:47.600254 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
520 00:55:47.603785 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 00:55:47.611762 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 00:55:47.615128 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 00:55:47.623936 [RTC]rtc_get_frequency_meter,154: input=15, output=852
524 00:55:47.633612 [RTC]rtc_get_frequency_meter,154: input=7, output=724
525 00:55:47.643145 [RTC]rtc_get_frequency_meter,154: input=11, output=789
526 00:55:47.652429 [RTC]rtc_get_frequency_meter,154: input=13, output=821
527 00:55:47.662401 [RTC]rtc_get_frequency_meter,154: input=12, output=806
528 00:55:47.671458 [RTC]rtc_get_frequency_meter,154: input=11, output=789
529 00:55:47.681540 [RTC]rtc_get_frequency_meter,154: input=12, output=805
530 00:55:47.684674 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 00:55:47.692425 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 00:55:47.695869 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 00:55:47.699838 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 00:55:47.702871 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 00:55:47.706633 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 00:55:47.710339 ADC[4]: Raw value=904802 ID=7
537 00:55:47.714795 ADC[3]: Raw value=213916 ID=1
538 00:55:47.714936 RAM Code: 0x71
539 00:55:47.718309 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 00:55:47.726032 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 00:55:47.732569 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 00:55:47.739936 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 00:55:47.743634 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 00:55:47.747605 in-header: 03 07 00 00 08 00 00 00
545 00:55:47.747736 in-data: aa e4 47 04 13 02 00 00
546 00:55:47.750811 Chrome EC: UHEPI supported
547 00:55:47.758011 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 00:55:47.762384 in-header: 03 95 00 00 08 00 00 00
549 00:55:47.766318 in-data: 18 20 20 08 00 00 00 00
550 00:55:47.769401 MRC: failed to locate region type 0.
551 00:55:47.777016 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 00:55:47.780871 DRAM-K: Running full calibration
553 00:55:47.784187 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 00:55:47.787540 header.status = 0x0
555 00:55:47.791315 header.version = 0x6 (expected: 0x6)
556 00:55:47.795273 header.size = 0xd00 (expected: 0xd00)
557 00:55:47.795460 header.flags = 0x0
558 00:55:47.801904 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 00:55:47.819858 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 00:55:47.827373 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 00:55:47.830697 dram_init: ddr_geometry: 2
562 00:55:47.830875 [EMI] MDL number = 2
563 00:55:47.834119 [EMI] Get MDL freq = 0
564 00:55:47.834224 dram_init: ddr_type: 0
565 00:55:47.838691 is_discrete_lpddr4: 1
566 00:55:47.841895 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 00:55:47.842010
568 00:55:47.842077
569 00:55:47.842139 [Bian_co] ETT version 0.0.0.1
570 00:55:47.848871 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 00:55:47.849018
572 00:55:47.851727 dramc_set_vcore_voltage set vcore to 650000
573 00:55:47.854947 Read voltage for 800, 4
574 00:55:47.855053 Vio18 = 0
575 00:55:47.855124 Vcore = 650000
576 00:55:47.858644 Vdram = 0
577 00:55:47.858747 Vddq = 0
578 00:55:47.858815 Vmddr = 0
579 00:55:47.861760 dram_init: config_dvfs: 1
580 00:55:47.865510 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 00:55:47.872802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 00:55:47.876440 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 00:55:47.879871 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 00:55:47.883079 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 00:55:47.886943 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 00:55:47.889879 MEM_TYPE=3, freq_sel=18
587 00:55:47.893175 sv_algorithm_assistance_LP4_1600
588 00:55:47.896622 ============ PULL DRAM RESETB DOWN ============
589 00:55:47.899903 ========== PULL DRAM RESETB DOWN end =========
590 00:55:47.906610 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 00:55:47.910512 ===================================
592 00:55:47.910637 LPDDR4 DRAM CONFIGURATION
593 00:55:47.913694 ===================================
594 00:55:47.916829 EX_ROW_EN[0] = 0x0
595 00:55:47.916971 EX_ROW_EN[1] = 0x0
596 00:55:47.919694 LP4Y_EN = 0x0
597 00:55:47.919790 WORK_FSP = 0x0
598 00:55:47.923327 WL = 0x2
599 00:55:47.926489 RL = 0x2
600 00:55:47.926604 BL = 0x2
601 00:55:47.929688 RPST = 0x0
602 00:55:47.929791 RD_PRE = 0x0
603 00:55:47.932965 WR_PRE = 0x1
604 00:55:47.933070 WR_PST = 0x0
605 00:55:47.936434 DBI_WR = 0x0
606 00:55:47.936555 DBI_RD = 0x0
607 00:55:47.940541 OTF = 0x1
608 00:55:47.943325 ===================================
609 00:55:47.946028 ===================================
610 00:55:47.946132 ANA top config
611 00:55:47.949797 ===================================
612 00:55:47.952705 DLL_ASYNC_EN = 0
613 00:55:47.957435 ALL_SLAVE_EN = 1
614 00:55:47.957569 NEW_RANK_MODE = 1
615 00:55:47.959684 DLL_IDLE_MODE = 1
616 00:55:47.963704 LP45_APHY_COMB_EN = 1
617 00:55:47.966432 TX_ODT_DIS = 1
618 00:55:47.969801 NEW_8X_MODE = 1
619 00:55:47.972639 ===================================
620 00:55:47.976127 ===================================
621 00:55:47.976241 data_rate = 1600
622 00:55:47.979271 CKR = 1
623 00:55:47.982747 DQ_P2S_RATIO = 8
624 00:55:47.985930 ===================================
625 00:55:47.990137 CA_P2S_RATIO = 8
626 00:55:47.993354 DQ_CA_OPEN = 0
627 00:55:47.993511 DQ_SEMI_OPEN = 0
628 00:55:47.996672 CA_SEMI_OPEN = 0
629 00:55:48.000066 CA_FULL_RATE = 0
630 00:55:48.003020 DQ_CKDIV4_EN = 1
631 00:55:48.006340 CA_CKDIV4_EN = 1
632 00:55:48.010418 CA_PREDIV_EN = 0
633 00:55:48.010545 PH8_DLY = 0
634 00:55:48.013454 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 00:55:48.016623 DQ_AAMCK_DIV = 4
636 00:55:48.019555 CA_AAMCK_DIV = 4
637 00:55:48.022895 CA_ADMCK_DIV = 4
638 00:55:48.026530 DQ_TRACK_CA_EN = 0
639 00:55:48.026650 CA_PICK = 800
640 00:55:48.029670 CA_MCKIO = 800
641 00:55:48.033261 MCKIO_SEMI = 0
642 00:55:48.037181 PLL_FREQ = 3068
643 00:55:48.040664 DQ_UI_PI_RATIO = 32
644 00:55:48.040788 CA_UI_PI_RATIO = 0
645 00:55:48.044806 ===================================
646 00:55:48.048304 ===================================
647 00:55:48.052231 memory_type:LPDDR4
648 00:55:48.052361 GP_NUM : 10
649 00:55:48.055342 SRAM_EN : 1
650 00:55:48.059400 MD32_EN : 0
651 00:55:48.059552 ===================================
652 00:55:48.063169 [ANA_INIT] >>>>>>>>>>>>>>
653 00:55:48.066421 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 00:55:48.070657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 00:55:48.073529 ===================================
656 00:55:48.076864 data_rate = 1600,PCW = 0X7600
657 00:55:48.076985 ===================================
658 00:55:48.083563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 00:55:48.086732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 00:55:48.093551 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 00:55:48.096421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 00:55:48.099994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 00:55:48.102996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 00:55:48.106687 [ANA_INIT] flow start
665 00:55:48.109749 [ANA_INIT] PLL >>>>>>>>
666 00:55:48.109866 [ANA_INIT] PLL <<<<<<<<
667 00:55:48.113133 [ANA_INIT] MIDPI >>>>>>>>
668 00:55:48.116191 [ANA_INIT] MIDPI <<<<<<<<
669 00:55:48.116294 [ANA_INIT] DLL >>>>>>>>
670 00:55:48.119698 [ANA_INIT] flow end
671 00:55:48.122943 ============ LP4 DIFF to SE enter ============
672 00:55:48.129809 ============ LP4 DIFF to SE exit ============
673 00:55:48.129942 [ANA_INIT] <<<<<<<<<<<<<
674 00:55:48.132839 [Flow] Enable top DCM control >>>>>
675 00:55:48.136825 [Flow] Enable top DCM control <<<<<
676 00:55:48.139192 Enable DLL master slave shuffle
677 00:55:48.146042 ==============================================================
678 00:55:48.146193 Gating Mode config
679 00:55:48.152687 ==============================================================
680 00:55:48.155959 Config description:
681 00:55:48.165968 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 00:55:48.172427 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 00:55:48.175550 SELPH_MODE 0: By rank 1: By Phase
684 00:55:48.182762 ==============================================================
685 00:55:48.185556 GAT_TRACK_EN = 1
686 00:55:48.189190 RX_GATING_MODE = 2
687 00:55:48.189336 RX_GATING_TRACK_MODE = 2
688 00:55:48.192327 SELPH_MODE = 1
689 00:55:48.195338 PICG_EARLY_EN = 1
690 00:55:48.199282 VALID_LAT_VALUE = 1
691 00:55:48.205778 ==============================================================
692 00:55:48.208787 Enter into Gating configuration >>>>
693 00:55:48.212074 Exit from Gating configuration <<<<
694 00:55:48.215582 Enter into DVFS_PRE_config >>>>>
695 00:55:48.225296 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 00:55:48.228908 Exit from DVFS_PRE_config <<<<<
697 00:55:48.231937 Enter into PICG configuration >>>>
698 00:55:48.235382 Exit from PICG configuration <<<<
699 00:55:48.238618 [RX_INPUT] configuration >>>>>
700 00:55:48.242701 [RX_INPUT] configuration <<<<<
701 00:55:48.245723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 00:55:48.252184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 00:55:48.258877 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 00:55:48.262210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 00:55:48.268517 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 00:55:48.275248 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 00:55:48.278635 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 00:55:48.285676 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 00:55:48.288874 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 00:55:48.292310 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 00:55:48.295769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 00:55:48.301732 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 00:55:48.305309 ===================================
714 00:55:48.305425 LPDDR4 DRAM CONFIGURATION
715 00:55:48.309307 ===================================
716 00:55:48.311922 EX_ROW_EN[0] = 0x0
717 00:55:48.315199 EX_ROW_EN[1] = 0x0
718 00:55:48.315331 LP4Y_EN = 0x0
719 00:55:48.318933 WORK_FSP = 0x0
720 00:55:48.319030 WL = 0x2
721 00:55:48.321842 RL = 0x2
722 00:55:48.321932 BL = 0x2
723 00:55:48.325144 RPST = 0x0
724 00:55:48.325241 RD_PRE = 0x0
725 00:55:48.328597 WR_PRE = 0x1
726 00:55:48.328698 WR_PST = 0x0
727 00:55:48.331700 DBI_WR = 0x0
728 00:55:48.331799 DBI_RD = 0x0
729 00:55:48.335076 OTF = 0x1
730 00:55:48.338515 ===================================
731 00:55:48.341436 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 00:55:48.345019 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 00:55:48.351738 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 00:55:48.354812 ===================================
735 00:55:48.354927 LPDDR4 DRAM CONFIGURATION
736 00:55:48.357941 ===================================
737 00:55:48.361916 EX_ROW_EN[0] = 0x10
738 00:55:48.365097 EX_ROW_EN[1] = 0x0
739 00:55:48.365213 LP4Y_EN = 0x0
740 00:55:48.368326 WORK_FSP = 0x0
741 00:55:48.368429 WL = 0x2
742 00:55:48.371341 RL = 0x2
743 00:55:48.371487 BL = 0x2
744 00:55:48.374873 RPST = 0x0
745 00:55:48.374977 RD_PRE = 0x0
746 00:55:48.378162 WR_PRE = 0x1
747 00:55:48.378264 WR_PST = 0x0
748 00:55:48.381875 DBI_WR = 0x0
749 00:55:48.381974 DBI_RD = 0x0
750 00:55:48.385393 OTF = 0x1
751 00:55:48.388086 ===================================
752 00:55:48.394734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 00:55:48.398493 nWR fixed to 40
754 00:55:48.398617 [ModeRegInit_LP4] CH0 RK0
755 00:55:48.401550 [ModeRegInit_LP4] CH0 RK1
756 00:55:48.405152 [ModeRegInit_LP4] CH1 RK0
757 00:55:48.405262 [ModeRegInit_LP4] CH1 RK1
758 00:55:48.408148 match AC timing 13
759 00:55:48.411909 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 00:55:48.418219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 00:55:48.421493 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 00:55:48.424499 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 00:55:48.431128 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 00:55:48.431287 [EMI DOE] emi_dcm 0
765 00:55:48.438072 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 00:55:48.438202 ==
767 00:55:48.441674 Dram Type= 6, Freq= 0, CH_0, rank 0
768 00:55:48.444492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 00:55:48.444596 ==
770 00:55:48.451076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 00:55:48.454387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 00:55:48.464603 [CA 0] Center 37 (7~68) winsize 62
773 00:55:48.467974 [CA 1] Center 37 (7~68) winsize 62
774 00:55:48.471614 [CA 2] Center 34 (4~65) winsize 62
775 00:55:48.474534 [CA 3] Center 35 (4~66) winsize 63
776 00:55:48.477784 [CA 4] Center 33 (3~64) winsize 62
777 00:55:48.481716 [CA 5] Center 33 (3~64) winsize 62
778 00:55:48.481830
779 00:55:48.484478 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 00:55:48.484603
781 00:55:48.488083 [CATrainingPosCal] consider 1 rank data
782 00:55:48.491209 u2DelayCellTimex100 = 270/100 ps
783 00:55:48.494374 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 00:55:48.500977 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
785 00:55:48.504669 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 00:55:48.507556 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 00:55:48.510907 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 00:55:48.514395 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 00:55:48.514504
790 00:55:48.517581 CA PerBit enable=1, Macro0, CA PI delay=33
791 00:55:48.517678
792 00:55:48.521375 [CBTSetCACLKResult] CA Dly = 33
793 00:55:48.524105 CS Dly: 5 (0~36)
794 00:55:48.524207 ==
795 00:55:48.528157 Dram Type= 6, Freq= 0, CH_0, rank 1
796 00:55:48.531322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 00:55:48.531486 ==
798 00:55:48.537604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 00:55:48.540544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 00:55:48.551230 [CA 0] Center 38 (7~69) winsize 63
801 00:55:48.554655 [CA 1] Center 37 (7~68) winsize 62
802 00:55:48.557970 [CA 2] Center 35 (4~66) winsize 63
803 00:55:48.561354 [CA 3] Center 34 (4~65) winsize 62
804 00:55:48.564697 [CA 4] Center 34 (3~65) winsize 63
805 00:55:48.567865 [CA 5] Center 33 (3~64) winsize 62
806 00:55:48.567977
807 00:55:48.570909 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 00:55:48.571031
809 00:55:48.574326 [CATrainingPosCal] consider 2 rank data
810 00:55:48.577481 u2DelayCellTimex100 = 270/100 ps
811 00:55:48.581144 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 00:55:48.587938 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 00:55:48.590701 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 00:55:48.594255 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 00:55:48.597761 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 00:55:48.600696 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 00:55:48.600813
818 00:55:48.603949 CA PerBit enable=1, Macro0, CA PI delay=33
819 00:55:48.604048
820 00:55:48.607241 [CBTSetCACLKResult] CA Dly = 33
821 00:55:48.611164 CS Dly: 6 (0~38)
822 00:55:48.611280
823 00:55:48.614699 ----->DramcWriteLeveling(PI) begin...
824 00:55:48.614803 ==
825 00:55:48.614894 Dram Type= 6, Freq= 0, CH_0, rank 0
826 00:55:48.621667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 00:55:48.621802 ==
828 00:55:48.624979 Write leveling (Byte 0): 30 => 30
829 00:55:48.625087 Write leveling (Byte 1): 29 => 29
830 00:55:48.629054 DramcWriteLeveling(PI) end<-----
831 00:55:48.629167
832 00:55:48.629260 ==
833 00:55:48.631840 Dram Type= 6, Freq= 0, CH_0, rank 0
834 00:55:48.639092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 00:55:48.639236 ==
836 00:55:48.639336 [Gating] SW mode calibration
837 00:55:48.645985 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 00:55:48.652665 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 00:55:48.655891 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 00:55:48.662582 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
841 00:55:48.665865 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
842 00:55:48.669148 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 00:55:48.675788 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:55:48.679252 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:55:48.682414 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:55:48.689198 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:55:48.692405 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:55:48.695713 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:55:48.702277 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 00:55:48.705570 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 00:55:48.708858 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 00:55:48.715411 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:55:48.718980 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:55:48.722134 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:55:48.728747 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
856 00:55:48.731997 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 00:55:48.735712 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
858 00:55:48.742522 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:55:48.745334 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:55:48.748697 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:55:48.752501 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:55:48.759261 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:55:48.761797 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:55:48.765234 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:55:48.771690 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
866 00:55:48.776638 0 9 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
867 00:55:48.778204 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 00:55:48.784867 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 00:55:48.788953 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 00:55:48.791865 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 00:55:48.798130 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 00:55:48.801801 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
873 00:55:48.804734 0 10 8 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
874 00:55:48.811303 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
875 00:55:48.814521 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:55:48.818321 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:55:48.824936 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 00:55:48.827858 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 00:55:48.831224 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 00:55:48.838162 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
881 00:55:48.841001 0 11 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
882 00:55:48.844290 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
883 00:55:48.851479 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 00:55:48.854379 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 00:55:48.858309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 00:55:48.864855 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 00:55:48.867667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 00:55:48.871001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 00:55:48.877538 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
890 00:55:48.881374 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 00:55:48.884345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 00:55:48.890781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 00:55:48.894338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 00:55:48.898165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 00:55:48.904331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 00:55:48.907709 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 00:55:48.910892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 00:55:48.918013 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 00:55:48.921465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 00:55:48.924168 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:55:48.930924 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:55:48.934188 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:55:48.937637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:55:48.944315 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 00:55:48.947741 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
906 00:55:48.950940 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
907 00:55:48.954298 Total UI for P1: 0, mck2ui 16
908 00:55:48.957258 best dqsien dly found for B0: ( 0, 14, 6)
909 00:55:48.961033 Total UI for P1: 0, mck2ui 16
910 00:55:48.964042 best dqsien dly found for B1: ( 0, 14, 8)
911 00:55:48.967149 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
912 00:55:48.970632 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
913 00:55:48.970762
914 00:55:48.974228 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 00:55:48.980540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 00:55:48.980675 [Gating] SW calibration Done
917 00:55:48.980773 ==
918 00:55:48.983991 Dram Type= 6, Freq= 0, CH_0, rank 0
919 00:55:48.987764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 00:55:48.991737 ==
921 00:55:48.991858 RX Vref Scan: 0
922 00:55:48.991952
923 00:55:48.994165 RX Vref 0 -> 0, step: 1
924 00:55:48.994259
925 00:55:48.997819 RX Delay -130 -> 252, step: 16
926 00:55:49.001126 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
927 00:55:49.004331 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 00:55:49.007738 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 00:55:49.010942 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 00:55:49.017748 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
931 00:55:49.021043 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 00:55:49.024124 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
933 00:55:49.027396 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
934 00:55:49.030804 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
935 00:55:49.037515 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
936 00:55:49.040797 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 00:55:49.044502 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 00:55:49.047830 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 00:55:49.051342 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 00:55:49.057443 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 00:55:49.061279 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 00:55:49.061398 ==
943 00:55:49.064318 Dram Type= 6, Freq= 0, CH_0, rank 0
944 00:55:49.067385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 00:55:49.067517 ==
946 00:55:49.071017 DQS Delay:
947 00:55:49.071120 DQS0 = 0, DQS1 = 0
948 00:55:49.071188 DQM Delay:
949 00:55:49.074733 DQM0 = 89, DQM1 = 76
950 00:55:49.074837 DQ Delay:
951 00:55:49.077716 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
952 00:55:49.081231 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
953 00:55:49.083876 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
954 00:55:49.087144 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 00:55:49.087257
956 00:55:49.087325
957 00:55:49.087434 ==
958 00:55:49.090420 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:55:49.097147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:55:49.097290 ==
961 00:55:49.097363
962 00:55:49.097425
963 00:55:49.097484 TX Vref Scan disable
964 00:55:49.101729 == TX Byte 0 ==
965 00:55:49.103985 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
966 00:55:49.110674 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
967 00:55:49.110825 == TX Byte 1 ==
968 00:55:49.114650 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
969 00:55:49.120968 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
970 00:55:49.121103 ==
971 00:55:49.124072 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:55:49.127306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:55:49.127465 ==
974 00:55:49.140094 TX Vref=22, minBit 0, minWin=27, winSum=440
975 00:55:49.143037 TX Vref=24, minBit 0, minWin=27, winSum=442
976 00:55:49.146958 TX Vref=26, minBit 1, minWin=27, winSum=448
977 00:55:49.149815 TX Vref=28, minBit 1, minWin=27, winSum=449
978 00:55:49.153033 TX Vref=30, minBit 1, minWin=27, winSum=453
979 00:55:49.156740 TX Vref=32, minBit 1, minWin=27, winSum=452
980 00:55:49.163269 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
981 00:55:49.163447
982 00:55:49.166257 Final TX Range 1 Vref 30
983 00:55:49.166355
984 00:55:49.166424 ==
985 00:55:49.169877 Dram Type= 6, Freq= 0, CH_0, rank 0
986 00:55:49.173313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 00:55:49.173422 ==
988 00:55:49.176444
989 00:55:49.176553
990 00:55:49.176624 TX Vref Scan disable
991 00:55:49.179994 == TX Byte 0 ==
992 00:55:49.183098 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
993 00:55:49.186310 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
994 00:55:49.189995 == TX Byte 1 ==
995 00:55:49.193525 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
996 00:55:49.200443 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
997 00:55:49.200636
998 00:55:49.200742 [DATLAT]
999 00:55:49.200836 Freq=800, CH0 RK0
1000 00:55:49.200930
1001 00:55:49.203125 DATLAT Default: 0xa
1002 00:55:49.203237 0, 0xFFFF, sum = 0
1003 00:55:49.206651 1, 0xFFFF, sum = 0
1004 00:55:49.206785 2, 0xFFFF, sum = 0
1005 00:55:49.209646 3, 0xFFFF, sum = 0
1006 00:55:49.213532 4, 0xFFFF, sum = 0
1007 00:55:49.213678 5, 0xFFFF, sum = 0
1008 00:55:49.216623 6, 0xFFFF, sum = 0
1009 00:55:49.216750 7, 0xFFFF, sum = 0
1010 00:55:49.220029 8, 0xFFFF, sum = 0
1011 00:55:49.220151 9, 0x0, sum = 1
1012 00:55:49.222619 10, 0x0, sum = 2
1013 00:55:49.222733 11, 0x0, sum = 3
1014 00:55:49.222830 12, 0x0, sum = 4
1015 00:55:49.226331 best_step = 10
1016 00:55:49.226450
1017 00:55:49.226546 ==
1018 00:55:49.229441 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 00:55:49.232822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 00:55:49.232952 ==
1021 00:55:49.236289 RX Vref Scan: 1
1022 00:55:49.236398
1023 00:55:49.239247 Set Vref Range= 32 -> 127
1024 00:55:49.239344
1025 00:55:49.239465 RX Vref 32 -> 127, step: 1
1026 00:55:49.239569
1027 00:55:49.243288 RX Delay -111 -> 252, step: 8
1028 00:55:49.243454
1029 00:55:49.245880 Set Vref, RX VrefLevel [Byte0]: 32
1030 00:55:49.249332 [Byte1]: 32
1031 00:55:49.252716
1032 00:55:49.252828 Set Vref, RX VrefLevel [Byte0]: 33
1033 00:55:49.256372 [Byte1]: 33
1034 00:55:49.260274
1035 00:55:49.260386 Set Vref, RX VrefLevel [Byte0]: 34
1036 00:55:49.263925 [Byte1]: 34
1037 00:55:49.268185
1038 00:55:49.268304 Set Vref, RX VrefLevel [Byte0]: 35
1039 00:55:49.271873 [Byte1]: 35
1040 00:55:49.276017
1041 00:55:49.276134 Set Vref, RX VrefLevel [Byte0]: 36
1042 00:55:49.279327 [Byte1]: 36
1043 00:55:49.283074
1044 00:55:49.283224 Set Vref, RX VrefLevel [Byte0]: 37
1045 00:55:49.286711 [Byte1]: 37
1046 00:55:49.291034
1047 00:55:49.291183 Set Vref, RX VrefLevel [Byte0]: 38
1048 00:55:49.294597 [Byte1]: 38
1049 00:55:49.298931
1050 00:55:49.299086 Set Vref, RX VrefLevel [Byte0]: 39
1051 00:55:49.302813 [Byte1]: 39
1052 00:55:49.306243
1053 00:55:49.306394 Set Vref, RX VrefLevel [Byte0]: 40
1054 00:55:49.310013 [Byte1]: 40
1055 00:55:49.314678
1056 00:55:49.314834 Set Vref, RX VrefLevel [Byte0]: 41
1057 00:55:49.317681 [Byte1]: 41
1058 00:55:49.321411
1059 00:55:49.321552 Set Vref, RX VrefLevel [Byte0]: 42
1060 00:55:49.324589 [Byte1]: 42
1061 00:55:49.329277
1062 00:55:49.329419 Set Vref, RX VrefLevel [Byte0]: 43
1063 00:55:49.332553 [Byte1]: 43
1064 00:55:49.337206
1065 00:55:49.337351 Set Vref, RX VrefLevel [Byte0]: 44
1066 00:55:49.340173 [Byte1]: 44
1067 00:55:49.344488
1068 00:55:49.344631 Set Vref, RX VrefLevel [Byte0]: 45
1069 00:55:49.348109 [Byte1]: 45
1070 00:55:49.351728
1071 00:55:49.351864 Set Vref, RX VrefLevel [Byte0]: 46
1072 00:55:49.355057 [Byte1]: 46
1073 00:55:49.359562
1074 00:55:49.359707 Set Vref, RX VrefLevel [Byte0]: 47
1075 00:55:49.362618 [Byte1]: 47
1076 00:55:49.367090
1077 00:55:49.367236 Set Vref, RX VrefLevel [Byte0]: 48
1078 00:55:49.370566 [Byte1]: 48
1079 00:55:49.375241
1080 00:55:49.375426 Set Vref, RX VrefLevel [Byte0]: 49
1081 00:55:49.378954 [Byte1]: 49
1082 00:55:49.382677
1083 00:55:49.382815 Set Vref, RX VrefLevel [Byte0]: 50
1084 00:55:49.385935 [Byte1]: 50
1085 00:55:49.390364
1086 00:55:49.390507 Set Vref, RX VrefLevel [Byte0]: 51
1087 00:55:49.393579 [Byte1]: 51
1088 00:55:49.397802
1089 00:55:49.397955 Set Vref, RX VrefLevel [Byte0]: 52
1090 00:55:49.400943 [Byte1]: 52
1091 00:55:49.406016
1092 00:55:49.406174 Set Vref, RX VrefLevel [Byte0]: 53
1093 00:55:49.408761 [Byte1]: 53
1094 00:55:49.413043
1095 00:55:49.413183 Set Vref, RX VrefLevel [Byte0]: 54
1096 00:55:49.416425 [Byte1]: 54
1097 00:55:49.420869
1098 00:55:49.421019 Set Vref, RX VrefLevel [Byte0]: 55
1099 00:55:49.424466 [Byte1]: 55
1100 00:55:49.428221
1101 00:55:49.428368 Set Vref, RX VrefLevel [Byte0]: 56
1102 00:55:49.431795 [Byte1]: 56
1103 00:55:49.435973
1104 00:55:49.436124 Set Vref, RX VrefLevel [Byte0]: 57
1105 00:55:49.439539 [Byte1]: 57
1106 00:55:49.444129
1107 00:55:49.444283 Set Vref, RX VrefLevel [Byte0]: 58
1108 00:55:49.447197 [Byte1]: 58
1109 00:55:49.451436
1110 00:55:49.451608 Set Vref, RX VrefLevel [Byte0]: 59
1111 00:55:49.454709 [Byte1]: 59
1112 00:55:49.459193
1113 00:55:49.459338 Set Vref, RX VrefLevel [Byte0]: 60
1114 00:55:49.462535 [Byte1]: 60
1115 00:55:49.466729
1116 00:55:49.466883 Set Vref, RX VrefLevel [Byte0]: 61
1117 00:55:49.470154 [Byte1]: 61
1118 00:55:49.474639
1119 00:55:49.474782 Set Vref, RX VrefLevel [Byte0]: 62
1120 00:55:49.477710 [Byte1]: 62
1121 00:55:49.482174
1122 00:55:49.482319 Set Vref, RX VrefLevel [Byte0]: 63
1123 00:55:49.485480 [Byte1]: 63
1124 00:55:49.489725
1125 00:55:49.489875 Set Vref, RX VrefLevel [Byte0]: 64
1126 00:55:49.493070 [Byte1]: 64
1127 00:55:49.497200
1128 00:55:49.497361 Set Vref, RX VrefLevel [Byte0]: 65
1129 00:55:49.500458 [Byte1]: 65
1130 00:55:49.504763
1131 00:55:49.504907 Set Vref, RX VrefLevel [Byte0]: 66
1132 00:55:49.509142 [Byte1]: 66
1133 00:55:49.512264
1134 00:55:49.512395 Set Vref, RX VrefLevel [Byte0]: 67
1135 00:55:49.515756 [Byte1]: 67
1136 00:55:49.520328
1137 00:55:49.520477 Set Vref, RX VrefLevel [Byte0]: 68
1138 00:55:49.523887 [Byte1]: 68
1139 00:55:49.527714
1140 00:55:49.527855 Set Vref, RX VrefLevel [Byte0]: 69
1141 00:55:49.531219 [Byte1]: 69
1142 00:55:49.535583
1143 00:55:49.535724 Set Vref, RX VrefLevel [Byte0]: 70
1144 00:55:49.539167 [Byte1]: 70
1145 00:55:49.542964
1146 00:55:49.543100 Set Vref, RX VrefLevel [Byte0]: 71
1147 00:55:49.546286 [Byte1]: 71
1148 00:55:49.550858
1149 00:55:49.551008 Set Vref, RX VrefLevel [Byte0]: 72
1150 00:55:49.553991 [Byte1]: 72
1151 00:55:49.558157
1152 00:55:49.558303 Set Vref, RX VrefLevel [Byte0]: 73
1153 00:55:49.561739 [Byte1]: 73
1154 00:55:49.565985
1155 00:55:49.566120 Set Vref, RX VrefLevel [Byte0]: 74
1156 00:55:49.569511 [Byte1]: 74
1157 00:55:49.573859
1158 00:55:49.573999 Final RX Vref Byte 0 = 55 to rank0
1159 00:55:49.576894 Final RX Vref Byte 1 = 59 to rank0
1160 00:55:49.580478 Final RX Vref Byte 0 = 55 to rank1
1161 00:55:49.583476 Final RX Vref Byte 1 = 59 to rank1==
1162 00:55:49.586712 Dram Type= 6, Freq= 0, CH_0, rank 0
1163 00:55:49.593479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 00:55:49.593657 ==
1165 00:55:49.593760 DQS Delay:
1166 00:55:49.596481 DQS0 = 0, DQS1 = 0
1167 00:55:49.596604 DQM Delay:
1168 00:55:49.596700 DQM0 = 88, DQM1 = 76
1169 00:55:49.599971 DQ Delay:
1170 00:55:49.603347 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1171 00:55:49.606920 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1172 00:55:49.610031 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1173 00:55:49.613303 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1174 00:55:49.613437
1175 00:55:49.613533
1176 00:55:49.619861 [DQSOSCAuto] RK0, (LSB)MR18= 0x312a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1177 00:55:49.623191 CH0 RK0: MR19=606, MR18=312A
1178 00:55:49.629839 CH0_RK0: MR19=0x606, MR18=0x312A, DQSOSC=397, MR23=63, INC=93, DEC=62
1179 00:55:49.630016
1180 00:55:49.633531 ----->DramcWriteLeveling(PI) begin...
1181 00:55:49.633654 ==
1182 00:55:49.636361 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 00:55:49.639908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 00:55:49.640041 ==
1185 00:55:49.643167 Write leveling (Byte 0): 33 => 33
1186 00:55:49.646789 Write leveling (Byte 1): 26 => 26
1187 00:55:49.649969 DramcWriteLeveling(PI) end<-----
1188 00:55:49.650106
1189 00:55:49.650205 ==
1190 00:55:49.653444 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 00:55:49.656161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 00:55:49.656286 ==
1193 00:55:49.659608 [Gating] SW mode calibration
1194 00:55:49.666125 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1195 00:55:49.672895 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1196 00:55:49.676107 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1197 00:55:49.723372 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1198 00:55:49.723574 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 00:55:49.723886 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 00:55:49.723988 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 00:55:49.724471 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 00:55:49.724951 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 00:55:49.725055 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 00:55:49.725339 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 00:55:49.726106 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 00:55:49.726404 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 00:55:49.766550 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 00:55:49.766753 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 00:55:49.767170 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 00:55:49.767469 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 00:55:49.767765 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 00:55:49.768646 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 00:55:49.768751 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1214 00:55:49.769104 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1215 00:55:49.769523 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 00:55:49.770086 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:55:49.770190 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:55:49.772946 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:55:49.779463 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:55:49.782314 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:55:49.785730 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:55:49.792564 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1223 00:55:49.796159 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 00:55:49.799206 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 00:55:49.806141 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 00:55:49.808879 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 00:55:49.812374 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 00:55:49.819102 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 00:55:49.822796 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1230 00:55:49.825899 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
1231 00:55:49.832657 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1232 00:55:49.835721 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:55:49.838889 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:55:49.842316 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:55:49.848742 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:55:49.852610 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:55:49.855807 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1238 00:55:49.862445 0 11 8 | B1->B0 | 3231 4646 | 1 0 | (0 0) (0 0)
1239 00:55:49.867138 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 00:55:49.870014 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 00:55:49.873915 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 00:55:49.880748 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 00:55:49.884158 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 00:55:49.887209 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 00:55:49.891483 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1246 00:55:49.897980 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1247 00:55:49.901137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 00:55:49.904576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 00:55:49.911148 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 00:55:49.914496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 00:55:49.917373 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 00:55:49.924601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 00:55:49.927469 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 00:55:49.930827 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 00:55:49.937255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 00:55:49.940906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 00:55:49.944171 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 00:55:49.950639 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 00:55:49.953948 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 00:55:49.957305 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 00:55:49.963820 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1262 00:55:49.967285 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1263 00:55:49.970468 Total UI for P1: 0, mck2ui 16
1264 00:55:49.973879 best dqsien dly found for B0: ( 0, 14, 4)
1265 00:55:49.977257 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 00:55:49.981152 Total UI for P1: 0, mck2ui 16
1267 00:55:49.985315 best dqsien dly found for B1: ( 0, 14, 8)
1268 00:55:49.987026 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1269 00:55:49.990250 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1270 00:55:49.990356
1271 00:55:49.993835 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1272 00:55:50.000401 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1273 00:55:50.000552 [Gating] SW calibration Done
1274 00:55:50.003653 ==
1275 00:55:50.003752 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 00:55:50.010636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 00:55:50.010765 ==
1278 00:55:50.010836 RX Vref Scan: 0
1279 00:55:50.010899
1280 00:55:50.013427 RX Vref 0 -> 0, step: 1
1281 00:55:50.013515
1282 00:55:50.016756 RX Delay -130 -> 252, step: 16
1283 00:55:50.020289 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1284 00:55:50.023155 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1285 00:55:50.026601 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1286 00:55:50.033480 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1287 00:55:50.037629 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1288 00:55:50.040775 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1289 00:55:50.043004 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1290 00:55:50.046717 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1291 00:55:50.053140 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1292 00:55:50.056281 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1293 00:55:50.061070 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1294 00:55:50.062939 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1295 00:55:50.069664 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1296 00:55:50.072889 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1297 00:55:50.076402 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1298 00:55:50.079635 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1299 00:55:50.079745 ==
1300 00:55:50.083887 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 00:55:50.089798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 00:55:50.089951 ==
1303 00:55:50.090034 DQS Delay:
1304 00:55:50.090096 DQS0 = 0, DQS1 = 0
1305 00:55:50.092784 DQM Delay:
1306 00:55:50.092873 DQM0 = 86, DQM1 = 78
1307 00:55:50.096301 DQ Delay:
1308 00:55:50.099506 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1309 00:55:50.099646 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1310 00:55:50.103478 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1311 00:55:50.109907 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1312 00:55:50.110044
1313 00:55:50.110115
1314 00:55:50.110175 ==
1315 00:55:50.112744 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 00:55:50.116552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 00:55:50.116656 ==
1318 00:55:50.116724
1319 00:55:50.116784
1320 00:55:50.119661 TX Vref Scan disable
1321 00:55:50.119750 == TX Byte 0 ==
1322 00:55:50.126162 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1323 00:55:50.129947 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1324 00:55:50.130068 == TX Byte 1 ==
1325 00:55:50.136342 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1326 00:55:50.139573 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1327 00:55:50.139690 ==
1328 00:55:50.142701 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 00:55:50.145810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 00:55:50.145914 ==
1331 00:55:50.161263 TX Vref=22, minBit 0, minWin=27, winSum=439
1332 00:55:50.164111 TX Vref=24, minBit 2, minWin=27, winSum=446
1333 00:55:50.167040 TX Vref=26, minBit 2, minWin=27, winSum=450
1334 00:55:50.170504 TX Vref=28, minBit 0, minWin=28, winSum=454
1335 00:55:50.173988 TX Vref=30, minBit 9, minWin=27, winSum=451
1336 00:55:50.177232 TX Vref=32, minBit 1, minWin=27, winSum=448
1337 00:55:50.183733 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
1338 00:55:50.183874
1339 00:55:50.187244 Final TX Range 1 Vref 28
1340 00:55:50.187407
1341 00:55:50.187493 ==
1342 00:55:50.190816 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 00:55:50.194224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 00:55:50.194330 ==
1345 00:55:50.194401
1346 00:55:50.197045
1347 00:55:50.197153 TX Vref Scan disable
1348 00:55:50.201205 == TX Byte 0 ==
1349 00:55:50.203719 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1350 00:55:50.210584 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1351 00:55:50.210727 == TX Byte 1 ==
1352 00:55:50.213580 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1353 00:55:50.220451 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1354 00:55:50.220587
1355 00:55:50.220658 [DATLAT]
1356 00:55:50.220720 Freq=800, CH0 RK1
1357 00:55:50.220779
1358 00:55:50.223658 DATLAT Default: 0xa
1359 00:55:50.223746 0, 0xFFFF, sum = 0
1360 00:55:50.227276 1, 0xFFFF, sum = 0
1361 00:55:50.230425 2, 0xFFFF, sum = 0
1362 00:55:50.230525 3, 0xFFFF, sum = 0
1363 00:55:50.233502 4, 0xFFFF, sum = 0
1364 00:55:50.233597 5, 0xFFFF, sum = 0
1365 00:55:50.237162 6, 0xFFFF, sum = 0
1366 00:55:50.237266 7, 0xFFFF, sum = 0
1367 00:55:50.240708 8, 0xFFFF, sum = 0
1368 00:55:50.240805 9, 0x0, sum = 1
1369 00:55:50.244552 10, 0x0, sum = 2
1370 00:55:50.244655 11, 0x0, sum = 3
1371 00:55:50.244724 12, 0x0, sum = 4
1372 00:55:50.246920 best_step = 10
1373 00:55:50.247006
1374 00:55:50.247072 ==
1375 00:55:50.250477 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 00:55:50.253525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 00:55:50.253652 ==
1378 00:55:50.257071 RX Vref Scan: 0
1379 00:55:50.257172
1380 00:55:50.260218 RX Vref 0 -> 0, step: 1
1381 00:55:50.260308
1382 00:55:50.260374 RX Delay -95 -> 252, step: 8
1383 00:55:50.267412 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1384 00:55:50.270628 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1385 00:55:50.274061 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1386 00:55:50.276937 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1387 00:55:50.280308 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1388 00:55:50.287053 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1389 00:55:50.291256 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1390 00:55:50.293978 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1391 00:55:50.296981 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1392 00:55:50.300340 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1393 00:55:50.307092 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1394 00:55:50.310143 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1395 00:55:50.314141 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1396 00:55:50.316804 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1397 00:55:50.323470 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1398 00:55:50.326612 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1399 00:55:50.326720 ==
1400 00:55:50.330115 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 00:55:50.334316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 00:55:50.334430 ==
1403 00:55:50.337260 DQS Delay:
1404 00:55:50.337355 DQS0 = 0, DQS1 = 0
1405 00:55:50.337422 DQM Delay:
1406 00:55:50.340238 DQM0 = 86, DQM1 = 77
1407 00:55:50.340327 DQ Delay:
1408 00:55:50.343238 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1409 00:55:50.346542 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1410 00:55:50.350192 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1411 00:55:50.353331 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1412 00:55:50.353446
1413 00:55:50.353516
1414 00:55:50.363114 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1415 00:55:50.363266 CH0 RK1: MR19=606, MR18=2D28
1416 00:55:50.369947 CH0_RK1: MR19=0x606, MR18=0x2D28, DQSOSC=398, MR23=63, INC=93, DEC=62
1417 00:55:50.373192 [RxdqsGatingPostProcess] freq 800
1418 00:55:50.379647 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1419 00:55:50.383857 Pre-setting of DQS Precalculation
1420 00:55:50.386494 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1421 00:55:50.386599 ==
1422 00:55:50.390100 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 00:55:50.396837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 00:55:50.396985 ==
1425 00:55:50.399846 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 00:55:50.406121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 00:55:50.416209 [CA 0] Center 36 (6~67) winsize 62
1428 00:55:50.418919 [CA 1] Center 37 (6~68) winsize 63
1429 00:55:50.422320 [CA 2] Center 35 (5~65) winsize 61
1430 00:55:50.426161 [CA 3] Center 34 (4~65) winsize 62
1431 00:55:50.428836 [CA 4] Center 34 (4~65) winsize 62
1432 00:55:50.432276 [CA 5] Center 34 (3~65) winsize 63
1433 00:55:50.432385
1434 00:55:50.435478 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 00:55:50.435632
1436 00:55:50.438642 [CATrainingPosCal] consider 1 rank data
1437 00:55:50.442379 u2DelayCellTimex100 = 270/100 ps
1438 00:55:50.446574 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 00:55:50.452087 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1440 00:55:50.456438 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1441 00:55:50.458650 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 00:55:50.461920 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 00:55:50.465414 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1444 00:55:50.465527
1445 00:55:50.468568 CA PerBit enable=1, Macro0, CA PI delay=34
1446 00:55:50.468664
1447 00:55:50.471989 [CBTSetCACLKResult] CA Dly = 34
1448 00:55:50.472087 CS Dly: 4 (0~35)
1449 00:55:50.475609 ==
1450 00:55:50.478624 Dram Type= 6, Freq= 0, CH_1, rank 1
1451 00:55:50.481969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 00:55:50.482085 ==
1453 00:55:50.485154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 00:55:50.491681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 00:55:50.502422 [CA 0] Center 36 (6~67) winsize 62
1456 00:55:50.505721 [CA 1] Center 36 (6~67) winsize 62
1457 00:55:50.508879 [CA 2] Center 35 (4~66) winsize 63
1458 00:55:50.511678 [CA 3] Center 34 (3~65) winsize 63
1459 00:55:50.515582 [CA 4] Center 34 (4~65) winsize 62
1460 00:55:50.518359 [CA 5] Center 34 (3~65) winsize 63
1461 00:55:50.518470
1462 00:55:50.522000 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1463 00:55:50.522107
1464 00:55:50.525228 [CATrainingPosCal] consider 2 rank data
1465 00:55:50.528598 u2DelayCellTimex100 = 270/100 ps
1466 00:55:50.532742 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 00:55:50.536281 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 00:55:50.540147 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 00:55:50.543503 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 00:55:50.547961 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 00:55:50.552258 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1472 00:55:50.552391
1473 00:55:50.554994 CA PerBit enable=1, Macro0, CA PI delay=34
1474 00:55:50.555102
1475 00:55:50.558502 [CBTSetCACLKResult] CA Dly = 34
1476 00:55:50.558636 CS Dly: 5 (0~38)
1477 00:55:50.558705
1478 00:55:50.562120 ----->DramcWriteLeveling(PI) begin...
1479 00:55:50.562231 ==
1480 00:55:50.565755 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 00:55:50.572368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 00:55:50.572522 ==
1483 00:55:50.575660 Write leveling (Byte 0): 25 => 25
1484 00:55:50.578644 Write leveling (Byte 1): 29 => 29
1485 00:55:50.578751 DramcWriteLeveling(PI) end<-----
1486 00:55:50.578842
1487 00:55:50.582293 ==
1488 00:55:50.585256 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 00:55:50.588841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 00:55:50.588955 ==
1491 00:55:50.592147 [Gating] SW mode calibration
1492 00:55:50.599038 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1493 00:55:50.601857 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1494 00:55:50.608755 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1495 00:55:50.611740 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1496 00:55:50.615605 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1497 00:55:50.621757 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 00:55:50.625003 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 00:55:50.628067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 00:55:50.634811 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 00:55:50.638225 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 00:55:50.641869 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 00:55:50.648047 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 00:55:50.651202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 00:55:50.654311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 00:55:50.661623 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 00:55:50.664398 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 00:55:50.667854 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 00:55:50.674763 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 00:55:50.677579 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 00:55:50.680953 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1512 00:55:50.687556 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:55:50.690775 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:55:50.694405 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:55:50.700931 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:55:50.704602 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:55:50.707579 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:55:50.713962 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:55:50.718098 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1520 00:55:50.720795 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
1521 00:55:50.727176 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 00:55:50.730523 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 00:55:50.734499 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 00:55:50.740705 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 00:55:50.743756 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 00:55:50.747082 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 00:55:50.753924 0 10 4 | B1->B0 | 3131 3131 | 1 0 | (1 1) (0 1)
1528 00:55:50.757040 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1529 00:55:50.760633 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:55:50.767233 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:55:50.770553 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:55:50.773917 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:55:50.780869 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:55:50.783705 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:55:50.787598 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1536 00:55:50.793846 0 11 8 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
1537 00:55:50.796976 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 00:55:50.800498 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 00:55:50.803646 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 00:55:50.810453 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 00:55:50.813980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 00:55:50.817521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 00:55:50.823749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1544 00:55:50.827317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1545 00:55:50.830462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 00:55:50.837348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 00:55:50.840106 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 00:55:50.843440 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 00:55:50.850197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 00:55:50.853810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 00:55:50.856984 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 00:55:50.863716 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 00:55:50.866828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 00:55:50.870118 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 00:55:50.876546 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 00:55:50.879948 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 00:55:50.883406 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 00:55:50.890089 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 00:55:50.893153 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1560 00:55:50.896881 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 00:55:50.900011 Total UI for P1: 0, mck2ui 16
1562 00:55:50.903171 best dqsien dly found for B0: ( 0, 14, 4)
1563 00:55:50.906756 Total UI for P1: 0, mck2ui 16
1564 00:55:50.909514 best dqsien dly found for B1: ( 0, 14, 6)
1565 00:55:50.913592 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1566 00:55:50.916522 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1567 00:55:50.916629
1568 00:55:50.922925 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1569 00:55:50.926193 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1570 00:55:50.926369 [Gating] SW calibration Done
1571 00:55:50.929568 ==
1572 00:55:50.932845 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 00:55:50.936537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 00:55:50.936648 ==
1575 00:55:50.936718 RX Vref Scan: 0
1576 00:55:50.936779
1577 00:55:50.939884 RX Vref 0 -> 0, step: 1
1578 00:55:50.939974
1579 00:55:50.942984 RX Delay -130 -> 252, step: 16
1580 00:55:50.946359 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1581 00:55:50.950107 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1582 00:55:50.956633 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1583 00:55:50.959718 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1584 00:55:50.962956 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1585 00:55:50.965745 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1586 00:55:50.969751 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1587 00:55:50.976496 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1588 00:55:50.978964 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1589 00:55:50.982224 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1590 00:55:50.985555 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1591 00:55:50.989085 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1592 00:55:50.995763 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1593 00:55:50.999317 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1594 00:55:51.002139 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1595 00:55:51.005581 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1596 00:55:51.005692 ==
1597 00:55:51.008803 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 00:55:51.015653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 00:55:51.015794 ==
1600 00:55:51.015867 DQS Delay:
1601 00:55:51.019103 DQS0 = 0, DQS1 = 0
1602 00:55:51.019196 DQM Delay:
1603 00:55:51.019263 DQM0 = 87, DQM1 = 81
1604 00:55:51.022517 DQ Delay:
1605 00:55:51.025343 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1606 00:55:51.028810 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1607 00:55:51.032351 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1608 00:55:51.035320 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1609 00:55:51.035459
1610 00:55:51.035551
1611 00:55:51.035633 ==
1612 00:55:51.038667 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 00:55:51.042495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 00:55:51.042604 ==
1615 00:55:51.042698
1616 00:55:51.042781
1617 00:55:51.045516 TX Vref Scan disable
1618 00:55:51.048890 == TX Byte 0 ==
1619 00:55:51.051963 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1620 00:55:51.055129 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1621 00:55:51.059076 == TX Byte 1 ==
1622 00:55:51.061649 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1623 00:55:51.065514 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1624 00:55:51.065630 ==
1625 00:55:51.068497 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 00:55:51.071791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 00:55:51.075293 ==
1628 00:55:51.086667 TX Vref=22, minBit 0, minWin=27, winSum=440
1629 00:55:51.089770 TX Vref=24, minBit 0, minWin=27, winSum=443
1630 00:55:51.093319 TX Vref=26, minBit 0, minWin=27, winSum=446
1631 00:55:51.096479 TX Vref=28, minBit 3, minWin=27, winSum=456
1632 00:55:51.099902 TX Vref=30, minBit 2, minWin=27, winSum=455
1633 00:55:51.106187 TX Vref=32, minBit 2, minWin=27, winSum=451
1634 00:55:51.110238 [TxChooseVref] Worse bit 3, Min win 27, Win sum 456, Final Vref 28
1635 00:55:51.110388
1636 00:55:51.114169 Final TX Range 1 Vref 28
1637 00:55:51.114286
1638 00:55:51.114355 ==
1639 00:55:51.117163 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 00:55:51.120205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 00:55:51.120315 ==
1642 00:55:51.120385
1643 00:55:51.120447
1644 00:55:51.123935 TX Vref Scan disable
1645 00:55:51.127565 == TX Byte 0 ==
1646 00:55:51.130349 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1647 00:55:51.133423 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1648 00:55:51.136902 == TX Byte 1 ==
1649 00:55:51.140808 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1650 00:55:51.143679 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1651 00:55:51.143780
1652 00:55:51.146807 [DATLAT]
1653 00:55:51.146902 Freq=800, CH1 RK0
1654 00:55:51.146971
1655 00:55:51.150085 DATLAT Default: 0xa
1656 00:55:51.150180 0, 0xFFFF, sum = 0
1657 00:55:51.153310 1, 0xFFFF, sum = 0
1658 00:55:51.153436 2, 0xFFFF, sum = 0
1659 00:55:51.157266 3, 0xFFFF, sum = 0
1660 00:55:51.157374 4, 0xFFFF, sum = 0
1661 00:55:51.160186 5, 0xFFFF, sum = 0
1662 00:55:51.160279 6, 0xFFFF, sum = 0
1663 00:55:51.163536 7, 0xFFFF, sum = 0
1664 00:55:51.163630 8, 0xFFFF, sum = 0
1665 00:55:51.166923 9, 0x0, sum = 1
1666 00:55:51.167047 10, 0x0, sum = 2
1667 00:55:51.170360 11, 0x0, sum = 3
1668 00:55:51.170463 12, 0x0, sum = 4
1669 00:55:51.174781 best_step = 10
1670 00:55:51.174898
1671 00:55:51.174965 ==
1672 00:55:51.176940 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 00:55:51.180184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 00:55:51.180301 ==
1675 00:55:51.183582 RX Vref Scan: 1
1676 00:55:51.183677
1677 00:55:51.183744 Set Vref Range= 32 -> 127
1678 00:55:51.183830
1679 00:55:51.186932 RX Vref 32 -> 127, step: 1
1680 00:55:51.187052
1681 00:55:51.190295 RX Delay -95 -> 252, step: 8
1682 00:55:51.190393
1683 00:55:51.194405 Set Vref, RX VrefLevel [Byte0]: 32
1684 00:55:51.196947 [Byte1]: 32
1685 00:55:51.197049
1686 00:55:51.200293 Set Vref, RX VrefLevel [Byte0]: 33
1687 00:55:51.203637 [Byte1]: 33
1688 00:55:51.206958
1689 00:55:51.207073 Set Vref, RX VrefLevel [Byte0]: 34
1690 00:55:51.210435 [Byte1]: 34
1691 00:55:51.214519
1692 00:55:51.214641 Set Vref, RX VrefLevel [Byte0]: 35
1693 00:55:51.218142 [Byte1]: 35
1694 00:55:51.222295
1695 00:55:51.222417 Set Vref, RX VrefLevel [Byte0]: 36
1696 00:55:51.225327 [Byte1]: 36
1697 00:55:51.230251
1698 00:55:51.230378 Set Vref, RX VrefLevel [Byte0]: 37
1699 00:55:51.233326 [Byte1]: 37
1700 00:55:51.237474
1701 00:55:51.237632 Set Vref, RX VrefLevel [Byte0]: 38
1702 00:55:51.240893 [Byte1]: 38
1703 00:55:51.245361
1704 00:55:51.245495 Set Vref, RX VrefLevel [Byte0]: 39
1705 00:55:51.248165 [Byte1]: 39
1706 00:55:51.252324
1707 00:55:51.252479 Set Vref, RX VrefLevel [Byte0]: 40
1708 00:55:51.255660 [Byte1]: 40
1709 00:55:51.259959
1710 00:55:51.260130 Set Vref, RX VrefLevel [Byte0]: 41
1711 00:55:51.263643 [Byte1]: 41
1712 00:55:51.268045
1713 00:55:51.268203 Set Vref, RX VrefLevel [Byte0]: 42
1714 00:55:51.271182 [Byte1]: 42
1715 00:55:51.275494
1716 00:55:51.275614 Set Vref, RX VrefLevel [Byte0]: 43
1717 00:55:51.278887 [Byte1]: 43
1718 00:55:51.282697
1719 00:55:51.282809 Set Vref, RX VrefLevel [Byte0]: 44
1720 00:55:51.286006 [Byte1]: 44
1721 00:55:51.290400
1722 00:55:51.290524 Set Vref, RX VrefLevel [Byte0]: 45
1723 00:55:51.293901 [Byte1]: 45
1724 00:55:51.298143
1725 00:55:51.298283 Set Vref, RX VrefLevel [Byte0]: 46
1726 00:55:51.301208 [Byte1]: 46
1727 00:55:51.305825
1728 00:55:51.305960 Set Vref, RX VrefLevel [Byte0]: 47
1729 00:55:51.308864 [Byte1]: 47
1730 00:55:51.313048
1731 00:55:51.313171 Set Vref, RX VrefLevel [Byte0]: 48
1732 00:55:51.316617 [Byte1]: 48
1733 00:55:51.321066
1734 00:55:51.321213 Set Vref, RX VrefLevel [Byte0]: 49
1735 00:55:51.324187 [Byte1]: 49
1736 00:55:51.329056
1737 00:55:51.329211 Set Vref, RX VrefLevel [Byte0]: 50
1738 00:55:51.332234 [Byte1]: 50
1739 00:55:51.336158
1740 00:55:51.336292 Set Vref, RX VrefLevel [Byte0]: 51
1741 00:55:51.339519 [Byte1]: 51
1742 00:55:51.343861
1743 00:55:51.343982 Set Vref, RX VrefLevel [Byte0]: 52
1744 00:55:51.346914 [Byte1]: 52
1745 00:55:51.351542
1746 00:55:51.351670 Set Vref, RX VrefLevel [Byte0]: 53
1747 00:55:51.354633 [Byte1]: 53
1748 00:55:51.358916
1749 00:55:51.359038 Set Vref, RX VrefLevel [Byte0]: 54
1750 00:55:51.361996 [Byte1]: 54
1751 00:55:51.366767
1752 00:55:51.366889 Set Vref, RX VrefLevel [Byte0]: 55
1753 00:55:51.370005 [Byte1]: 55
1754 00:55:51.374320
1755 00:55:51.374442 Set Vref, RX VrefLevel [Byte0]: 56
1756 00:55:51.377546 [Byte1]: 56
1757 00:55:51.381736
1758 00:55:51.381850 Set Vref, RX VrefLevel [Byte0]: 57
1759 00:55:51.384731 [Byte1]: 57
1760 00:55:51.389087
1761 00:55:51.389230 Set Vref, RX VrefLevel [Byte0]: 58
1762 00:55:51.392541 [Byte1]: 58
1763 00:55:51.396909
1764 00:55:51.397032 Set Vref, RX VrefLevel [Byte0]: 59
1765 00:55:51.400011 [Byte1]: 59
1766 00:55:51.404710
1767 00:55:51.404844 Set Vref, RX VrefLevel [Byte0]: 60
1768 00:55:51.407786 [Byte1]: 60
1769 00:55:51.411880
1770 00:55:51.411997 Set Vref, RX VrefLevel [Byte0]: 61
1771 00:55:51.415316 [Byte1]: 61
1772 00:55:51.419775
1773 00:55:51.419896 Set Vref, RX VrefLevel [Byte0]: 62
1774 00:55:51.423151 [Byte1]: 62
1775 00:55:51.427340
1776 00:55:51.427494 Set Vref, RX VrefLevel [Byte0]: 63
1777 00:55:51.430984 [Byte1]: 63
1778 00:55:51.434773
1779 00:55:51.434887 Set Vref, RX VrefLevel [Byte0]: 64
1780 00:55:51.437935 [Byte1]: 64
1781 00:55:51.442779
1782 00:55:51.442903 Set Vref, RX VrefLevel [Byte0]: 65
1783 00:55:51.446087 [Byte1]: 65
1784 00:55:51.450171
1785 00:55:51.450283 Set Vref, RX VrefLevel [Byte0]: 66
1786 00:55:51.453182 [Byte1]: 66
1787 00:55:51.457806
1788 00:55:51.457932 Set Vref, RX VrefLevel [Byte0]: 67
1789 00:55:51.461343 [Byte1]: 67
1790 00:55:51.465569
1791 00:55:51.465685 Set Vref, RX VrefLevel [Byte0]: 68
1792 00:55:51.468741 [Byte1]: 68
1793 00:55:51.473369
1794 00:55:51.473491 Set Vref, RX VrefLevel [Byte0]: 69
1795 00:55:51.476165 [Byte1]: 69
1796 00:55:51.480241
1797 00:55:51.480354 Set Vref, RX VrefLevel [Byte0]: 70
1798 00:55:51.483832 [Byte1]: 70
1799 00:55:51.488373
1800 00:55:51.488487 Set Vref, RX VrefLevel [Byte0]: 71
1801 00:55:51.491337 [Byte1]: 71
1802 00:55:51.495661
1803 00:55:51.495786 Set Vref, RX VrefLevel [Byte0]: 72
1804 00:55:51.499056 [Byte1]: 72
1805 00:55:51.502991
1806 00:55:51.503114 Set Vref, RX VrefLevel [Byte0]: 73
1807 00:55:51.506449 [Byte1]: 73
1808 00:55:51.511040
1809 00:55:51.511189 Set Vref, RX VrefLevel [Byte0]: 74
1810 00:55:51.514044 [Byte1]: 74
1811 00:55:51.518313
1812 00:55:51.518427 Set Vref, RX VrefLevel [Byte0]: 75
1813 00:55:51.521559 [Byte1]: 75
1814 00:55:51.526159
1815 00:55:51.526276 Final RX Vref Byte 0 = 55 to rank0
1816 00:55:51.529570 Final RX Vref Byte 1 = 55 to rank0
1817 00:55:51.532697 Final RX Vref Byte 0 = 55 to rank1
1818 00:55:51.535681 Final RX Vref Byte 1 = 55 to rank1==
1819 00:55:51.539299 Dram Type= 6, Freq= 0, CH_1, rank 0
1820 00:55:51.545809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 00:55:51.545948 ==
1822 00:55:51.546018 DQS Delay:
1823 00:55:51.546080 DQS0 = 0, DQS1 = 0
1824 00:55:51.549435 DQM Delay:
1825 00:55:51.549537 DQM0 = 85, DQM1 = 79
1826 00:55:51.552902 DQ Delay:
1827 00:55:51.555814 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1828 00:55:51.559160 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1829 00:55:51.562570 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =72
1830 00:55:51.566047 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1831 00:55:51.566191
1832 00:55:51.566295
1833 00:55:51.572238 [DQSOSCAuto] RK0, (LSB)MR18= 0x1629, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1834 00:55:51.576521 CH1 RK0: MR19=606, MR18=1629
1835 00:55:51.582335 CH1_RK0: MR19=0x606, MR18=0x1629, DQSOSC=399, MR23=63, INC=92, DEC=61
1836 00:55:51.582468
1837 00:55:51.585769 ----->DramcWriteLeveling(PI) begin...
1838 00:55:51.585897 ==
1839 00:55:51.588894 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 00:55:51.592426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 00:55:51.592575 ==
1842 00:55:51.595548 Write leveling (Byte 0): 24 => 24
1843 00:55:51.599290 Write leveling (Byte 1): 26 => 26
1844 00:55:51.602225 DramcWriteLeveling(PI) end<-----
1845 00:55:51.602347
1846 00:55:51.602418 ==
1847 00:55:51.605934 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 00:55:51.608855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 00:55:51.608966 ==
1850 00:55:51.612245 [Gating] SW mode calibration
1851 00:55:51.618302 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1852 00:55:51.625291 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1853 00:55:51.628813 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1854 00:55:51.635498 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1855 00:55:51.638288 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1856 00:55:51.641776 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 00:55:51.648419 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 00:55:51.652171 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 00:55:51.655312 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 00:55:51.661928 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 00:55:51.664964 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 00:55:51.668662 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 00:55:51.672226 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 00:55:51.678509 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 00:55:51.681651 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 00:55:51.684916 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 00:55:51.691524 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 00:55:51.695220 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:55:51.698297 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1870 00:55:51.705284 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1871 00:55:51.708594 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:55:51.711914 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:55:51.718097 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 00:55:51.721423 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 00:55:51.724765 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:55:51.731133 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:55:51.734609 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:55:51.737866 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1879 00:55:51.744743 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1880 00:55:51.747808 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 00:55:51.751046 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 00:55:51.758027 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 00:55:51.761033 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 00:55:51.764592 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 00:55:51.770972 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1886 00:55:51.774986 0 10 4 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
1887 00:55:51.777863 0 10 8 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
1888 00:55:51.784669 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:55:51.787570 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:55:51.791225 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:55:51.797733 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:55:51.800695 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:55:51.804476 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:55:51.810971 0 11 4 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
1895 00:55:51.813989 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1896 00:55:51.817615 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 00:55:51.824359 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 00:55:51.827855 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 00:55:51.830835 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 00:55:51.837575 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 00:55:51.841190 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1902 00:55:51.844308 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1903 00:55:51.847610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1904 00:55:51.854330 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 00:55:51.857544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 00:55:51.860917 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 00:55:51.867634 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 00:55:51.870873 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 00:55:51.874272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 00:55:51.880755 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 00:55:51.884095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 00:55:51.887406 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 00:55:51.893644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 00:55:51.897597 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 00:55:51.901157 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 00:55:51.907025 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 00:55:51.910294 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1918 00:55:51.913469 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1919 00:55:51.916679 Total UI for P1: 0, mck2ui 16
1920 00:55:51.920662 best dqsien dly found for B0: ( 0, 14, 0)
1921 00:55:51.927037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 00:55:51.930609 Total UI for P1: 0, mck2ui 16
1923 00:55:51.933922 best dqsien dly found for B1: ( 0, 14, 6)
1924 00:55:51.936785 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1925 00:55:51.939995 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1926 00:55:51.940094
1927 00:55:51.943174 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1928 00:55:51.947052 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1929 00:55:51.949988 [Gating] SW calibration Done
1930 00:55:51.950085 ==
1931 00:55:51.953383 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 00:55:51.956698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 00:55:51.956793 ==
1934 00:55:51.960129 RX Vref Scan: 0
1935 00:55:51.960218
1936 00:55:51.960280 RX Vref 0 -> 0, step: 1
1937 00:55:51.960345
1938 00:55:51.963334 RX Delay -130 -> 252, step: 16
1939 00:55:51.970074 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1940 00:55:51.973178 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1941 00:55:51.977783 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1942 00:55:51.979906 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1943 00:55:51.983434 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1944 00:55:51.989437 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1945 00:55:51.993136 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1946 00:55:51.996356 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1947 00:55:52.000300 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1948 00:55:52.003225 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1949 00:55:52.009560 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1950 00:55:52.012723 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1951 00:55:52.016319 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1952 00:55:52.019387 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1953 00:55:52.022581 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1954 00:55:52.029270 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1955 00:55:52.029409 ==
1956 00:55:52.032536 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 00:55:52.036265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 00:55:52.036382 ==
1959 00:55:52.036448 DQS Delay:
1960 00:55:52.039299 DQS0 = 0, DQS1 = 0
1961 00:55:52.039453 DQM Delay:
1962 00:55:52.042513 DQM0 = 79, DQM1 = 79
1963 00:55:52.042595 DQ Delay:
1964 00:55:52.045999 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1965 00:55:52.049927 DQ4 =77, DQ5 =85, DQ6 =85, DQ7 =77
1966 00:55:52.052405 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1967 00:55:52.056006 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1968 00:55:52.056143
1969 00:55:52.056210
1970 00:55:52.056269 ==
1971 00:55:52.059450 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 00:55:52.062304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 00:55:52.062393 ==
1974 00:55:52.066114
1975 00:55:52.066202
1976 00:55:52.066262 TX Vref Scan disable
1977 00:55:52.069630 == TX Byte 0 ==
1978 00:55:52.072834 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1979 00:55:52.075711 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1980 00:55:52.079246 == TX Byte 1 ==
1981 00:55:52.082630 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1982 00:55:52.085820 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1983 00:55:52.085927 ==
1984 00:55:52.089110 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 00:55:52.095759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 00:55:52.095901 ==
1987 00:55:52.107845 TX Vref=22, minBit 1, minWin=27, winSum=445
1988 00:55:52.111519 TX Vref=24, minBit 1, minWin=27, winSum=450
1989 00:55:52.114744 TX Vref=26, minBit 1, minWin=27, winSum=449
1990 00:55:52.117638 TX Vref=28, minBit 5, minWin=27, winSum=454
1991 00:55:52.121288 TX Vref=30, minBit 4, minWin=27, winSum=453
1992 00:55:52.127868 TX Vref=32, minBit 5, minWin=27, winSum=454
1993 00:55:52.131191 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 28
1994 00:55:52.131308
1995 00:55:52.134338 Final TX Range 1 Vref 28
1996 00:55:52.134437
1997 00:55:52.134504 ==
1998 00:55:52.138548 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 00:55:52.141200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 00:55:52.141303 ==
2001 00:55:52.141372
2002 00:55:52.144752
2003 00:55:52.144851 TX Vref Scan disable
2004 00:55:52.147492 == TX Byte 0 ==
2005 00:55:52.150870 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2006 00:55:52.157662 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2007 00:55:52.157806 == TX Byte 1 ==
2008 00:55:52.161011 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2009 00:55:52.167206 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2010 00:55:52.167402
2011 00:55:52.167492 [DATLAT]
2012 00:55:52.167555 Freq=800, CH1 RK1
2013 00:55:52.167615
2014 00:55:52.170520 DATLAT Default: 0xa
2015 00:55:52.174707 0, 0xFFFF, sum = 0
2016 00:55:52.174816 1, 0xFFFF, sum = 0
2017 00:55:52.177522 2, 0xFFFF, sum = 0
2018 00:55:52.177614 3, 0xFFFF, sum = 0
2019 00:55:52.180653 4, 0xFFFF, sum = 0
2020 00:55:52.180748 5, 0xFFFF, sum = 0
2021 00:55:52.183890 6, 0xFFFF, sum = 0
2022 00:55:52.183983 7, 0xFFFF, sum = 0
2023 00:55:52.187180 8, 0xFFFF, sum = 0
2024 00:55:52.187306 9, 0x0, sum = 1
2025 00:55:52.190276 10, 0x0, sum = 2
2026 00:55:52.190368 11, 0x0, sum = 3
2027 00:55:52.193647 12, 0x0, sum = 4
2028 00:55:52.193744 best_step = 10
2029 00:55:52.193813
2030 00:55:52.193875 ==
2031 00:55:52.197004 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 00:55:52.200612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 00:55:52.200744 ==
2034 00:55:52.203639 RX Vref Scan: 0
2035 00:55:52.203759
2036 00:55:52.207083 RX Vref 0 -> 0, step: 1
2037 00:55:52.207177
2038 00:55:52.207247 RX Delay -95 -> 252, step: 8
2039 00:55:52.214121 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2040 00:55:52.218504 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2041 00:55:52.221089 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2042 00:55:52.224288 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2043 00:55:52.228046 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2044 00:55:52.234157 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2045 00:55:52.237653 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2046 00:55:52.240765 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2047 00:55:52.244147 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2048 00:55:52.247675 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2049 00:55:52.254013 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2050 00:55:52.257562 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2051 00:55:52.260506 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2052 00:55:52.264397 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2053 00:55:52.270819 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2054 00:55:52.274394 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2055 00:55:52.274518 ==
2056 00:55:52.277294 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 00:55:52.280429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 00:55:52.280533 ==
2059 00:55:52.283880 DQS Delay:
2060 00:55:52.283978 DQS0 = 0, DQS1 = 0
2061 00:55:52.284047 DQM Delay:
2062 00:55:52.287508 DQM0 = 86, DQM1 = 82
2063 00:55:52.287602 DQ Delay:
2064 00:55:52.290431 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2065 00:55:52.293877 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2066 00:55:52.297485 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2067 00:55:52.300382 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2068 00:55:52.300558
2069 00:55:52.300630
2070 00:55:52.310958 [DQSOSCAuto] RK1, (LSB)MR18= 0x243f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2071 00:55:52.311109 CH1 RK1: MR19=606, MR18=243F
2072 00:55:52.316960 CH1_RK1: MR19=0x606, MR18=0x243F, DQSOSC=393, MR23=63, INC=95, DEC=63
2073 00:55:52.320380 [RxdqsGatingPostProcess] freq 800
2074 00:55:52.327068 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2075 00:55:52.330258 Pre-setting of DQS Precalculation
2076 00:55:52.333613 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2077 00:55:52.340471 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2078 00:55:52.351474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2079 00:55:52.351625
2080 00:55:52.351695
2081 00:55:52.353458 [Calibration Summary] 1600 Mbps
2082 00:55:52.353544 CH 0, Rank 0
2083 00:55:52.356689 SW Impedance : PASS
2084 00:55:52.356781 DUTY Scan : NO K
2085 00:55:52.360427 ZQ Calibration : PASS
2086 00:55:52.363732 Jitter Meter : NO K
2087 00:55:52.363836 CBT Training : PASS
2088 00:55:52.366934 Write leveling : PASS
2089 00:55:52.367039 RX DQS gating : PASS
2090 00:55:52.370091 RX DQ/DQS(RDDQC) : PASS
2091 00:55:52.373334 TX DQ/DQS : PASS
2092 00:55:52.373455 RX DATLAT : PASS
2093 00:55:52.376862 RX DQ/DQS(Engine): PASS
2094 00:55:52.379894 TX OE : NO K
2095 00:55:52.379998 All Pass.
2096 00:55:52.380068
2097 00:55:52.380130 CH 0, Rank 1
2098 00:55:52.383175 SW Impedance : PASS
2099 00:55:52.386815 DUTY Scan : NO K
2100 00:55:52.386926 ZQ Calibration : PASS
2101 00:55:52.390656 Jitter Meter : NO K
2102 00:55:52.393824 CBT Training : PASS
2103 00:55:52.393932 Write leveling : PASS
2104 00:55:52.396851 RX DQS gating : PASS
2105 00:55:52.400152 RX DQ/DQS(RDDQC) : PASS
2106 00:55:52.400305 TX DQ/DQS : PASS
2107 00:55:52.403851 RX DATLAT : PASS
2108 00:55:52.407503 RX DQ/DQS(Engine): PASS
2109 00:55:52.407611 TX OE : NO K
2110 00:55:52.407680 All Pass.
2111 00:55:52.410293
2112 00:55:52.410383 CH 1, Rank 0
2113 00:55:52.413116 SW Impedance : PASS
2114 00:55:52.413210 DUTY Scan : NO K
2115 00:55:52.416788 ZQ Calibration : PASS
2116 00:55:52.419945 Jitter Meter : NO K
2117 00:55:52.420054 CBT Training : PASS
2118 00:55:52.423728 Write leveling : PASS
2119 00:55:52.423838 RX DQS gating : PASS
2120 00:55:52.426658 RX DQ/DQS(RDDQC) : PASS
2121 00:55:52.430148 TX DQ/DQS : PASS
2122 00:55:52.430255 RX DATLAT : PASS
2123 00:55:52.433469 RX DQ/DQS(Engine): PASS
2124 00:55:52.436742 TX OE : NO K
2125 00:55:52.436846 All Pass.
2126 00:55:52.436916
2127 00:55:52.436978 CH 1, Rank 1
2128 00:55:52.440039 SW Impedance : PASS
2129 00:55:52.443666 DUTY Scan : NO K
2130 00:55:52.443778 ZQ Calibration : PASS
2131 00:55:52.446666 Jitter Meter : NO K
2132 00:55:52.449980 CBT Training : PASS
2133 00:55:52.450093 Write leveling : PASS
2134 00:55:52.452950 RX DQS gating : PASS
2135 00:55:52.456628 RX DQ/DQS(RDDQC) : PASS
2136 00:55:52.456735 TX DQ/DQS : PASS
2137 00:55:52.460266 RX DATLAT : PASS
2138 00:55:52.463180 RX DQ/DQS(Engine): PASS
2139 00:55:52.463284 TX OE : NO K
2140 00:55:52.466258 All Pass.
2141 00:55:52.466352
2142 00:55:52.466421 DramC Write-DBI off
2143 00:55:52.469428 PER_BANK_REFRESH: Hybrid Mode
2144 00:55:52.469520 TX_TRACKING: ON
2145 00:55:52.472968 [GetDramInforAfterCalByMRR] Vendor 6.
2146 00:55:52.479496 [GetDramInforAfterCalByMRR] Revision 606.
2147 00:55:52.482844 [GetDramInforAfterCalByMRR] Revision 2 0.
2148 00:55:52.482993 MR0 0x3b3b
2149 00:55:52.483080 MR8 0x5151
2150 00:55:52.485812 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2151 00:55:52.485904
2152 00:55:52.489623 MR0 0x3b3b
2153 00:55:52.489727 MR8 0x5151
2154 00:55:52.492558 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 00:55:52.492649
2156 00:55:52.503025 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2157 00:55:52.506085 [FAST_K] Save calibration result to emmc
2158 00:55:52.509114 [FAST_K] Save calibration result to emmc
2159 00:55:52.512636 dram_init: config_dvfs: 1
2160 00:55:52.516349 dramc_set_vcore_voltage set vcore to 662500
2161 00:55:52.519532 Read voltage for 1200, 2
2162 00:55:52.519647 Vio18 = 0
2163 00:55:52.519718 Vcore = 662500
2164 00:55:52.522534 Vdram = 0
2165 00:55:52.522623 Vddq = 0
2166 00:55:52.522689 Vmddr = 0
2167 00:55:52.529187 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2168 00:55:52.532291 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2169 00:55:52.536535 MEM_TYPE=3, freq_sel=15
2170 00:55:52.539336 sv_algorithm_assistance_LP4_1600
2171 00:55:52.542292 ============ PULL DRAM RESETB DOWN ============
2172 00:55:52.546104 ========== PULL DRAM RESETB DOWN end =========
2173 00:55:52.552329 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2174 00:55:52.555780 ===================================
2175 00:55:52.555907 LPDDR4 DRAM CONFIGURATION
2176 00:55:52.559559 ===================================
2177 00:55:52.562053 EX_ROW_EN[0] = 0x0
2178 00:55:52.565789 EX_ROW_EN[1] = 0x0
2179 00:55:52.565910 LP4Y_EN = 0x0
2180 00:55:52.568641 WORK_FSP = 0x0
2181 00:55:52.568735 WL = 0x4
2182 00:55:52.572644 RL = 0x4
2183 00:55:52.572748 BL = 0x2
2184 00:55:52.576120 RPST = 0x0
2185 00:55:52.576219 RD_PRE = 0x0
2186 00:55:52.579102 WR_PRE = 0x1
2187 00:55:52.579194 WR_PST = 0x0
2188 00:55:52.582592 DBI_WR = 0x0
2189 00:55:52.582688 DBI_RD = 0x0
2190 00:55:52.585701 OTF = 0x1
2191 00:55:52.588766 ===================================
2192 00:55:52.591843 ===================================
2193 00:55:52.591952 ANA top config
2194 00:55:52.595326 ===================================
2195 00:55:52.598609 DLL_ASYNC_EN = 0
2196 00:55:52.602228 ALL_SLAVE_EN = 0
2197 00:55:52.605348 NEW_RANK_MODE = 1
2198 00:55:52.605493 DLL_IDLE_MODE = 1
2199 00:55:52.608617 LP45_APHY_COMB_EN = 1
2200 00:55:52.611918 TX_ODT_DIS = 1
2201 00:55:52.615260 NEW_8X_MODE = 1
2202 00:55:52.618616 ===================================
2203 00:55:52.621968 ===================================
2204 00:55:52.625523 data_rate = 2400
2205 00:55:52.625645 CKR = 1
2206 00:55:52.628485 DQ_P2S_RATIO = 8
2207 00:55:52.631812 ===================================
2208 00:55:52.635109 CA_P2S_RATIO = 8
2209 00:55:52.638523 DQ_CA_OPEN = 0
2210 00:55:52.641632 DQ_SEMI_OPEN = 0
2211 00:55:52.644953 CA_SEMI_OPEN = 0
2212 00:55:52.645114 CA_FULL_RATE = 0
2213 00:55:52.648233 DQ_CKDIV4_EN = 0
2214 00:55:52.652135 CA_CKDIV4_EN = 0
2215 00:55:52.655251 CA_PREDIV_EN = 0
2216 00:55:52.658407 PH8_DLY = 17
2217 00:55:52.661782 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2218 00:55:52.664685 DQ_AAMCK_DIV = 4
2219 00:55:52.664795 CA_AAMCK_DIV = 4
2220 00:55:52.668060 CA_ADMCK_DIV = 4
2221 00:55:52.672014 DQ_TRACK_CA_EN = 0
2222 00:55:52.675229 CA_PICK = 1200
2223 00:55:52.678114 CA_MCKIO = 1200
2224 00:55:52.681424 MCKIO_SEMI = 0
2225 00:55:52.684979 PLL_FREQ = 2366
2226 00:55:52.685081 DQ_UI_PI_RATIO = 32
2227 00:55:52.688268 CA_UI_PI_RATIO = 0
2228 00:55:52.691676 ===================================
2229 00:55:52.694900 ===================================
2230 00:55:52.698324 memory_type:LPDDR4
2231 00:55:52.701971 GP_NUM : 10
2232 00:55:52.702163 SRAM_EN : 1
2233 00:55:52.704704 MD32_EN : 0
2234 00:55:52.708049 ===================================
2235 00:55:52.712001 [ANA_INIT] >>>>>>>>>>>>>>
2236 00:55:52.712127 <<<<<< [CONFIGURE PHASE]: ANA_TX
2237 00:55:52.714678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2238 00:55:52.717936 ===================================
2239 00:55:52.721358 data_rate = 2400,PCW = 0X5b00
2240 00:55:52.724708 ===================================
2241 00:55:52.728072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2242 00:55:52.734548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2243 00:55:52.741143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2244 00:55:52.744382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2245 00:55:52.747575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2246 00:55:52.751372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2247 00:55:52.754112 [ANA_INIT] flow start
2248 00:55:52.754218 [ANA_INIT] PLL >>>>>>>>
2249 00:55:52.757815 [ANA_INIT] PLL <<<<<<<<
2250 00:55:52.760981 [ANA_INIT] MIDPI >>>>>>>>
2251 00:55:52.761094 [ANA_INIT] MIDPI <<<<<<<<
2252 00:55:52.765179 [ANA_INIT] DLL >>>>>>>>
2253 00:55:52.768186 [ANA_INIT] DLL <<<<<<<<
2254 00:55:52.768292 [ANA_INIT] flow end
2255 00:55:52.774668 ============ LP4 DIFF to SE enter ============
2256 00:55:52.777784 ============ LP4 DIFF to SE exit ============
2257 00:55:52.781290 [ANA_INIT] <<<<<<<<<<<<<
2258 00:55:52.784474 [Flow] Enable top DCM control >>>>>
2259 00:55:52.787543 [Flow] Enable top DCM control <<<<<
2260 00:55:52.787657 Enable DLL master slave shuffle
2261 00:55:52.793890 ==============================================================
2262 00:55:52.797741 Gating Mode config
2263 00:55:52.800874 ==============================================================
2264 00:55:52.804483 Config description:
2265 00:55:52.813762 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2266 00:55:52.820687 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2267 00:55:52.824186 SELPH_MODE 0: By rank 1: By Phase
2268 00:55:52.830324 ==============================================================
2269 00:55:52.833588 GAT_TRACK_EN = 1
2270 00:55:52.837797 RX_GATING_MODE = 2
2271 00:55:52.840196 RX_GATING_TRACK_MODE = 2
2272 00:55:52.843636 SELPH_MODE = 1
2273 00:55:52.847398 PICG_EARLY_EN = 1
2274 00:55:52.847525 VALID_LAT_VALUE = 1
2275 00:55:52.854144 ==============================================================
2276 00:55:52.857352 Enter into Gating configuration >>>>
2277 00:55:52.860284 Exit from Gating configuration <<<<
2278 00:55:52.863859 Enter into DVFS_PRE_config >>>>>
2279 00:55:52.873965 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2280 00:55:52.877261 Exit from DVFS_PRE_config <<<<<
2281 00:55:52.880599 Enter into PICG configuration >>>>
2282 00:55:52.883526 Exit from PICG configuration <<<<
2283 00:55:52.887066 [RX_INPUT] configuration >>>>>
2284 00:55:52.891594 [RX_INPUT] configuration <<<<<
2285 00:55:52.893521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2286 00:55:52.900260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2287 00:55:52.907007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2288 00:55:52.913238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2289 00:55:52.919977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 00:55:52.926683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 00:55:52.930238 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2292 00:55:52.933648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2293 00:55:52.936662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2294 00:55:52.939855 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2295 00:55:52.946495 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2296 00:55:52.950305 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2297 00:55:52.953544 ===================================
2298 00:55:52.957154 LPDDR4 DRAM CONFIGURATION
2299 00:55:52.959787 ===================================
2300 00:55:52.959881 EX_ROW_EN[0] = 0x0
2301 00:55:52.963754 EX_ROW_EN[1] = 0x0
2302 00:55:52.963844 LP4Y_EN = 0x0
2303 00:55:52.966513 WORK_FSP = 0x0
2304 00:55:52.966597 WL = 0x4
2305 00:55:52.969776 RL = 0x4
2306 00:55:52.973264 BL = 0x2
2307 00:55:52.973355 RPST = 0x0
2308 00:55:52.976909 RD_PRE = 0x0
2309 00:55:52.976997 WR_PRE = 0x1
2310 00:55:52.980054 WR_PST = 0x0
2311 00:55:52.980141 DBI_WR = 0x0
2312 00:55:52.983124 DBI_RD = 0x0
2313 00:55:52.983208 OTF = 0x1
2314 00:55:52.986496 ===================================
2315 00:55:52.990124 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2316 00:55:52.996544 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2317 00:55:52.999988 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2318 00:55:53.003651 ===================================
2319 00:55:53.006165 LPDDR4 DRAM CONFIGURATION
2320 00:55:53.010015 ===================================
2321 00:55:53.010116 EX_ROW_EN[0] = 0x10
2322 00:55:53.013124 EX_ROW_EN[1] = 0x0
2323 00:55:53.013212 LP4Y_EN = 0x0
2324 00:55:53.016513 WORK_FSP = 0x0
2325 00:55:53.016599 WL = 0x4
2326 00:55:53.019359 RL = 0x4
2327 00:55:53.019468 BL = 0x2
2328 00:55:53.022692 RPST = 0x0
2329 00:55:53.022777 RD_PRE = 0x0
2330 00:55:53.026033 WR_PRE = 0x1
2331 00:55:53.029654 WR_PST = 0x0
2332 00:55:53.029744 DBI_WR = 0x0
2333 00:55:53.033320 DBI_RD = 0x0
2334 00:55:53.033409 OTF = 0x1
2335 00:55:53.036335 ===================================
2336 00:55:53.043073 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2337 00:55:53.043223 ==
2338 00:55:53.046626 Dram Type= 6, Freq= 0, CH_0, rank 0
2339 00:55:53.049389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2340 00:55:53.049481 ==
2341 00:55:53.053185 [Duty_Offset_Calibration]
2342 00:55:53.053271 B0:2 B1:0 CA:4
2343 00:55:53.056361
2344 00:55:53.059023 [DutyScan_Calibration_Flow] k_type=0
2345 00:55:53.066579
2346 00:55:53.066735 ==CLK 0==
2347 00:55:53.069746 Final CLK duty delay cell = -4
2348 00:55:53.073512 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2349 00:55:53.076120 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2350 00:55:53.080093 [-4] AVG Duty = 4937%(X100)
2351 00:55:53.080188
2352 00:55:53.082945 CH0 CLK Duty spec in!! Max-Min= 187%
2353 00:55:53.086119 [DutyScan_Calibration_Flow] ====Done====
2354 00:55:53.086209
2355 00:55:53.089457 [DutyScan_Calibration_Flow] k_type=1
2356 00:55:53.106057
2357 00:55:53.106212 ==DQS 0 ==
2358 00:55:53.109423 Final DQS duty delay cell = 0
2359 00:55:53.112554 [0] MAX Duty = 5156%(X100), DQS PI = 14
2360 00:55:53.115815 [0] MIN Duty = 5093%(X100), DQS PI = 2
2361 00:55:53.115916 [0] AVG Duty = 5124%(X100)
2362 00:55:53.119638
2363 00:55:53.119726 ==DQS 1 ==
2364 00:55:53.122485 Final DQS duty delay cell = 0
2365 00:55:53.125705 [0] MAX Duty = 5125%(X100), DQS PI = 4
2366 00:55:53.129245 [0] MIN Duty = 5000%(X100), DQS PI = 0
2367 00:55:53.129339 [0] AVG Duty = 5062%(X100)
2368 00:55:53.132712
2369 00:55:53.135889 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2370 00:55:53.135979
2371 00:55:53.139045 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2372 00:55:53.142381 [DutyScan_Calibration_Flow] ====Done====
2373 00:55:53.142472
2374 00:55:53.145766 [DutyScan_Calibration_Flow] k_type=3
2375 00:55:53.162116
2376 00:55:53.162265 ==DQM 0 ==
2377 00:55:53.165217 Final DQM duty delay cell = 0
2378 00:55:53.168749 [0] MAX Duty = 5125%(X100), DQS PI = 20
2379 00:55:53.171895 [0] MIN Duty = 4844%(X100), DQS PI = 50
2380 00:55:53.175483 [0] AVG Duty = 4984%(X100)
2381 00:55:53.175578
2382 00:55:53.175646 ==DQM 1 ==
2383 00:55:53.179105 Final DQM duty delay cell = 0
2384 00:55:53.182063 [0] MAX Duty = 5000%(X100), DQS PI = 8
2385 00:55:53.185171 [0] MIN Duty = 4875%(X100), DQS PI = 14
2386 00:55:53.188719 [0] AVG Duty = 4937%(X100)
2387 00:55:53.188813
2388 00:55:53.191908 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2389 00:55:53.191997
2390 00:55:53.195037 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2391 00:55:53.198800 [DutyScan_Calibration_Flow] ====Done====
2392 00:55:53.198898
2393 00:55:53.201630 [DutyScan_Calibration_Flow] k_type=2
2394 00:55:53.218140
2395 00:55:53.218293 ==DQ 0 ==
2396 00:55:53.221185 Final DQ duty delay cell = -4
2397 00:55:53.224394 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2398 00:55:53.228114 [-4] MIN Duty = 4844%(X100), DQS PI = 52
2399 00:55:53.230907 [-4] AVG Duty = 4922%(X100)
2400 00:55:53.230995
2401 00:55:53.231060 ==DQ 1 ==
2402 00:55:53.234628 Final DQ duty delay cell = 0
2403 00:55:53.237838 [0] MAX Duty = 5156%(X100), DQS PI = 6
2404 00:55:53.241230 [0] MIN Duty = 4938%(X100), DQS PI = 16
2405 00:55:53.245017 [0] AVG Duty = 5047%(X100)
2406 00:55:53.245112
2407 00:55:53.247351 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2408 00:55:53.247479
2409 00:55:53.251302 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2410 00:55:53.254042 [DutyScan_Calibration_Flow] ====Done====
2411 00:55:53.254128 ==
2412 00:55:53.257406 Dram Type= 6, Freq= 0, CH_1, rank 0
2413 00:55:53.261050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2414 00:55:53.261143 ==
2415 00:55:53.264195 [Duty_Offset_Calibration]
2416 00:55:53.264281 B0:0 B1:-1 CA:3
2417 00:55:53.264348
2418 00:55:53.267269 [DutyScan_Calibration_Flow] k_type=0
2419 00:55:53.277153
2420 00:55:53.277285 ==CLK 0==
2421 00:55:53.280819 Final CLK duty delay cell = -4
2422 00:55:53.283984 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2423 00:55:53.287140 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2424 00:55:53.290481 [-4] AVG Duty = 4938%(X100)
2425 00:55:53.290581
2426 00:55:53.294111 CH1 CLK Duty spec in!! Max-Min= 124%
2427 00:55:53.297771 [DutyScan_Calibration_Flow] ====Done====
2428 00:55:53.297864
2429 00:55:53.300239 [DutyScan_Calibration_Flow] k_type=1
2430 00:55:53.316856
2431 00:55:53.317009 ==DQS 0 ==
2432 00:55:53.320342 Final DQS duty delay cell = 0
2433 00:55:53.323638 [0] MAX Duty = 5156%(X100), DQS PI = 18
2434 00:55:53.327197 [0] MIN Duty = 4907%(X100), DQS PI = 38
2435 00:55:53.331206 [0] AVG Duty = 5031%(X100)
2436 00:55:53.331300
2437 00:55:53.331392 ==DQS 1 ==
2438 00:55:53.333356 Final DQS duty delay cell = 0
2439 00:55:53.336734 [0] MAX Duty = 5156%(X100), DQS PI = 8
2440 00:55:53.340350 [0] MIN Duty = 5031%(X100), DQS PI = 20
2441 00:55:53.340442 [0] AVG Duty = 5093%(X100)
2442 00:55:53.343638
2443 00:55:53.346926 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2444 00:55:53.347018
2445 00:55:53.350028 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2446 00:55:53.353886 [DutyScan_Calibration_Flow] ====Done====
2447 00:55:53.353976
2448 00:55:53.356733 [DutyScan_Calibration_Flow] k_type=3
2449 00:55:53.373942
2450 00:55:53.374097 ==DQM 0 ==
2451 00:55:53.376687 Final DQM duty delay cell = 0
2452 00:55:53.380164 [0] MAX Duty = 5031%(X100), DQS PI = 28
2453 00:55:53.383579 [0] MIN Duty = 4813%(X100), DQS PI = 38
2454 00:55:53.387556 [0] AVG Duty = 4922%(X100)
2455 00:55:53.387660
2456 00:55:53.387728 ==DQM 1 ==
2457 00:55:53.390129 Final DQM duty delay cell = 0
2458 00:55:53.393606 [0] MAX Duty = 4969%(X100), DQS PI = 32
2459 00:55:53.396467 [0] MIN Duty = 4844%(X100), DQS PI = 0
2460 00:55:53.399857 [0] AVG Duty = 4906%(X100)
2461 00:55:53.399947
2462 00:55:53.403542 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2463 00:55:53.403673
2464 00:55:53.406440 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2465 00:55:53.410287 [DutyScan_Calibration_Flow] ====Done====
2466 00:55:53.410381
2467 00:55:53.413304 [DutyScan_Calibration_Flow] k_type=2
2468 00:55:53.429027
2469 00:55:53.429183 ==DQ 0 ==
2470 00:55:53.432374 Final DQ duty delay cell = -4
2471 00:55:53.435671 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2472 00:55:53.439251 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2473 00:55:53.442549 [-4] AVG Duty = 4937%(X100)
2474 00:55:53.442642
2475 00:55:53.442708 ==DQ 1 ==
2476 00:55:53.445505 Final DQ duty delay cell = 0
2477 00:55:53.449048 [0] MAX Duty = 5031%(X100), DQS PI = 32
2478 00:55:53.452477 [0] MIN Duty = 4844%(X100), DQS PI = 62
2479 00:55:53.455717 [0] AVG Duty = 4937%(X100)
2480 00:55:53.455816
2481 00:55:53.459054 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2482 00:55:53.459147
2483 00:55:53.462314 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2484 00:55:53.465287 [DutyScan_Calibration_Flow] ====Done====
2485 00:55:53.468770 nWR fixed to 30
2486 00:55:53.472033 [ModeRegInit_LP4] CH0 RK0
2487 00:55:53.472125 [ModeRegInit_LP4] CH0 RK1
2488 00:55:53.475302 [ModeRegInit_LP4] CH1 RK0
2489 00:55:53.478554 [ModeRegInit_LP4] CH1 RK1
2490 00:55:53.478663 match AC timing 7
2491 00:55:53.485269 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2492 00:55:53.489023 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2493 00:55:53.492061 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2494 00:55:53.499268 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2495 00:55:53.501658 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2496 00:55:53.501811 ==
2497 00:55:53.505383 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 00:55:53.508393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 00:55:53.508487 ==
2500 00:55:53.515061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 00:55:53.521895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2502 00:55:53.529424 [CA 0] Center 39 (9~70) winsize 62
2503 00:55:53.532969 [CA 1] Center 39 (9~70) winsize 62
2504 00:55:53.536214 [CA 2] Center 35 (5~66) winsize 62
2505 00:55:53.539292 [CA 3] Center 35 (5~66) winsize 62
2506 00:55:53.542607 [CA 4] Center 33 (3~64) winsize 62
2507 00:55:53.545771 [CA 5] Center 33 (3~63) winsize 61
2508 00:55:53.545871
2509 00:55:53.549622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2510 00:55:53.549714
2511 00:55:53.552765 [CATrainingPosCal] consider 1 rank data
2512 00:55:53.556074 u2DelayCellTimex100 = 270/100 ps
2513 00:55:53.559083 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2514 00:55:53.566307 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 00:55:53.569170 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 00:55:53.573207 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2517 00:55:53.575935 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2518 00:55:53.579120 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2519 00:55:53.579217
2520 00:55:53.582408 CA PerBit enable=1, Macro0, CA PI delay=33
2521 00:55:53.582499
2522 00:55:53.585465 [CBTSetCACLKResult] CA Dly = 33
2523 00:55:53.589287 CS Dly: 7 (0~38)
2524 00:55:53.589385 ==
2525 00:55:53.592540 Dram Type= 6, Freq= 0, CH_0, rank 1
2526 00:55:53.595586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 00:55:53.595680 ==
2528 00:55:53.598821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 00:55:53.605472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2530 00:55:53.615019 [CA 0] Center 39 (9~70) winsize 62
2531 00:55:53.618684 [CA 1] Center 39 (9~70) winsize 62
2532 00:55:53.622457 [CA 2] Center 35 (5~66) winsize 62
2533 00:55:53.625411 [CA 3] Center 35 (5~66) winsize 62
2534 00:55:53.628484 [CA 4] Center 34 (4~65) winsize 62
2535 00:55:53.631914 [CA 5] Center 33 (3~64) winsize 62
2536 00:55:53.632019
2537 00:55:53.635125 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2538 00:55:53.635217
2539 00:55:53.638345 [CATrainingPosCal] consider 2 rank data
2540 00:55:53.641921 u2DelayCellTimex100 = 270/100 ps
2541 00:55:53.645365 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2542 00:55:53.651546 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2543 00:55:53.654823 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2544 00:55:53.658050 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 00:55:53.661471 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2546 00:55:53.665324 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2547 00:55:53.665438
2548 00:55:53.667992 CA PerBit enable=1, Macro0, CA PI delay=33
2549 00:55:53.668082
2550 00:55:53.671708 [CBTSetCACLKResult] CA Dly = 33
2551 00:55:53.671805 CS Dly: 8 (0~41)
2552 00:55:53.671874
2553 00:55:53.678340 ----->DramcWriteLeveling(PI) begin...
2554 00:55:53.678541 ==
2555 00:55:53.681589 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 00:55:53.685121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 00:55:53.685225 ==
2558 00:55:53.688450 Write leveling (Byte 0): 31 => 31
2559 00:55:53.691294 Write leveling (Byte 1): 24 => 24
2560 00:55:53.695254 DramcWriteLeveling(PI) end<-----
2561 00:55:53.695383
2562 00:55:53.695468 ==
2563 00:55:53.698116 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 00:55:53.701337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 00:55:53.701434 ==
2566 00:55:53.704899 [Gating] SW mode calibration
2567 00:55:53.711254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2568 00:55:53.718089 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2569 00:55:53.721140 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2570 00:55:53.724486 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2571 00:55:53.731343 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 00:55:53.735031 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2573 00:55:53.738312 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 00:55:53.744388 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 00:55:53.747751 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2576 00:55:53.751018 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2577 00:55:53.758055 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
2578 00:55:53.761409 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2579 00:55:53.764717 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 00:55:53.770932 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 00:55:53.774081 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 00:55:53.777590 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 00:55:53.784210 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
2584 00:55:53.787609 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2585 00:55:53.790946 1 1 0 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2586 00:55:53.797292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 00:55:53.800825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 00:55:53.804208 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 00:55:53.810551 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 00:55:53.813926 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 00:55:53.817988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 00:55:53.824008 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2593 00:55:53.826878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2594 00:55:53.830740 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 00:55:53.836729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 00:55:53.840321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 00:55:53.843346 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 00:55:53.846743 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 00:55:53.853807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 00:55:53.856916 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 00:55:53.860414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 00:55:53.866770 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 00:55:53.870131 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 00:55:53.873193 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 00:55:53.880023 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 00:55:53.883282 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 00:55:53.886900 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 00:55:53.893322 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2609 00:55:53.896969 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2610 00:55:53.900026 Total UI for P1: 0, mck2ui 16
2611 00:55:53.903003 best dqsien dly found for B0: ( 1, 3, 28)
2612 00:55:53.907091 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 00:55:53.909798 Total UI for P1: 0, mck2ui 16
2614 00:55:53.913541 best dqsien dly found for B1: ( 1, 3, 30)
2615 00:55:53.916485 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2616 00:55:53.920154 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2617 00:55:53.920238
2618 00:55:53.926423 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2619 00:55:53.929821 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2620 00:55:53.933883 [Gating] SW calibration Done
2621 00:55:53.933975 ==
2622 00:55:53.936280 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 00:55:53.939685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 00:55:53.939805 ==
2625 00:55:53.939887 RX Vref Scan: 0
2626 00:55:53.939948
2627 00:55:53.942992 RX Vref 0 -> 0, step: 1
2628 00:55:53.943076
2629 00:55:53.946147 RX Delay -40 -> 252, step: 8
2630 00:55:53.949694 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2631 00:55:53.953245 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2632 00:55:53.959474 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2633 00:55:53.962701 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2634 00:55:53.966325 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2635 00:55:53.969798 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2636 00:55:53.972885 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2637 00:55:53.979344 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2638 00:55:53.982658 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2639 00:55:53.986088 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2640 00:55:53.989517 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2641 00:55:53.993284 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2642 00:55:53.999537 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2643 00:55:54.003047 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2644 00:55:54.005917 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2645 00:55:54.009661 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2646 00:55:54.009772 ==
2647 00:55:54.012765 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 00:55:54.019227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 00:55:54.019376 ==
2650 00:55:54.019491 DQS Delay:
2651 00:55:54.019580 DQS0 = 0, DQS1 = 0
2652 00:55:54.022432 DQM Delay:
2653 00:55:54.022531 DQM0 = 118, DQM1 = 107
2654 00:55:54.025690 DQ Delay:
2655 00:55:54.029524 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2656 00:55:54.032385 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2657 00:55:54.035641 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2658 00:55:54.039232 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2659 00:55:54.039319
2660 00:55:54.039394
2661 00:55:54.039456 ==
2662 00:55:54.042500 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 00:55:54.045977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 00:55:54.046064 ==
2665 00:55:54.049329
2666 00:55:54.049412
2667 00:55:54.049478 TX Vref Scan disable
2668 00:55:54.052370 == TX Byte 0 ==
2669 00:55:54.055848 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2670 00:55:54.059222 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2671 00:55:54.062064 == TX Byte 1 ==
2672 00:55:54.066052 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2673 00:55:54.068912 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2674 00:55:54.069028 ==
2675 00:55:54.072135 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 00:55:54.078687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 00:55:54.078779 ==
2678 00:55:54.090640 TX Vref=22, minBit 2, minWin=25, winSum=412
2679 00:55:54.093736 TX Vref=24, minBit 4, minWin=25, winSum=421
2680 00:55:54.097023 TX Vref=26, minBit 4, minWin=25, winSum=424
2681 00:55:54.100072 TX Vref=28, minBit 4, minWin=25, winSum=428
2682 00:55:54.103794 TX Vref=30, minBit 5, minWin=25, winSum=430
2683 00:55:54.107040 TX Vref=32, minBit 5, minWin=25, winSum=428
2684 00:55:54.113727 [TxChooseVref] Worse bit 5, Min win 25, Win sum 430, Final Vref 30
2685 00:55:54.113834
2686 00:55:54.116988 Final TX Range 1 Vref 30
2687 00:55:54.117075
2688 00:55:54.117141 ==
2689 00:55:54.120062 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 00:55:54.123648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 00:55:54.123752 ==
2692 00:55:54.126679
2693 00:55:54.126764
2694 00:55:54.126832 TX Vref Scan disable
2695 00:55:54.129994 == TX Byte 0 ==
2696 00:55:54.133089 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2697 00:55:54.139842 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2698 00:55:54.140002 == TX Byte 1 ==
2699 00:55:54.143201 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2700 00:55:54.150077 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2701 00:55:54.150215
2702 00:55:54.150289 [DATLAT]
2703 00:55:54.150381 Freq=1200, CH0 RK0
2704 00:55:54.150478
2705 00:55:54.153431 DATLAT Default: 0xd
2706 00:55:54.153595 0, 0xFFFF, sum = 0
2707 00:55:54.156794 1, 0xFFFF, sum = 0
2708 00:55:54.159654 2, 0xFFFF, sum = 0
2709 00:55:54.159791 3, 0xFFFF, sum = 0
2710 00:55:54.163353 4, 0xFFFF, sum = 0
2711 00:55:54.163491 5, 0xFFFF, sum = 0
2712 00:55:54.166367 6, 0xFFFF, sum = 0
2713 00:55:54.166486 7, 0xFFFF, sum = 0
2714 00:55:54.169625 8, 0xFFFF, sum = 0
2715 00:55:54.169747 9, 0xFFFF, sum = 0
2716 00:55:54.172868 10, 0xFFFF, sum = 0
2717 00:55:54.172999 11, 0xFFFF, sum = 0
2718 00:55:54.176273 12, 0x0, sum = 1
2719 00:55:54.176363 13, 0x0, sum = 2
2720 00:55:54.179264 14, 0x0, sum = 3
2721 00:55:54.179406 15, 0x0, sum = 4
2722 00:55:54.182649 best_step = 13
2723 00:55:54.182802
2724 00:55:54.182932 ==
2725 00:55:54.186168 Dram Type= 6, Freq= 0, CH_0, rank 0
2726 00:55:54.189465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2727 00:55:54.189586 ==
2728 00:55:54.189659 RX Vref Scan: 1
2729 00:55:54.193198
2730 00:55:54.193322 Set Vref Range= 32 -> 127
2731 00:55:54.193421
2732 00:55:54.196212 RX Vref 32 -> 127, step: 1
2733 00:55:54.196366
2734 00:55:54.199861 RX Delay -21 -> 252, step: 4
2735 00:55:54.199992
2736 00:55:54.202887 Set Vref, RX VrefLevel [Byte0]: 32
2737 00:55:54.205847 [Byte1]: 32
2738 00:55:54.205974
2739 00:55:54.209335 Set Vref, RX VrefLevel [Byte0]: 33
2740 00:55:54.212363 [Byte1]: 33
2741 00:55:54.216512
2742 00:55:54.216633 Set Vref, RX VrefLevel [Byte0]: 34
2743 00:55:54.220059 [Byte1]: 34
2744 00:55:54.224350
2745 00:55:54.224489 Set Vref, RX VrefLevel [Byte0]: 35
2746 00:55:54.227895 [Byte1]: 35
2747 00:55:54.232248
2748 00:55:54.232382 Set Vref, RX VrefLevel [Byte0]: 36
2749 00:55:54.235387 [Byte1]: 36
2750 00:55:54.240390
2751 00:55:54.240483 Set Vref, RX VrefLevel [Byte0]: 37
2752 00:55:54.243462 [Byte1]: 37
2753 00:55:54.248413
2754 00:55:54.248504 Set Vref, RX VrefLevel [Byte0]: 38
2755 00:55:54.251149 [Byte1]: 38
2756 00:55:54.256430
2757 00:55:54.256558 Set Vref, RX VrefLevel [Byte0]: 39
2758 00:55:54.259491 [Byte1]: 39
2759 00:55:54.264022
2760 00:55:54.264128 Set Vref, RX VrefLevel [Byte0]: 40
2761 00:55:54.267441 [Byte1]: 40
2762 00:55:54.272402
2763 00:55:54.272492 Set Vref, RX VrefLevel [Byte0]: 41
2764 00:55:54.275029 [Byte1]: 41
2765 00:55:54.279825
2766 00:55:54.279961 Set Vref, RX VrefLevel [Byte0]: 42
2767 00:55:54.284147 [Byte1]: 42
2768 00:55:54.287766
2769 00:55:54.287862 Set Vref, RX VrefLevel [Byte0]: 43
2770 00:55:54.290986 [Byte1]: 43
2771 00:55:54.295854
2772 00:55:54.295986 Set Vref, RX VrefLevel [Byte0]: 44
2773 00:55:54.299216 [Byte1]: 44
2774 00:55:54.303452
2775 00:55:54.303603 Set Vref, RX VrefLevel [Byte0]: 45
2776 00:55:54.306764 [Byte1]: 45
2777 00:55:54.312016
2778 00:55:54.312151 Set Vref, RX VrefLevel [Byte0]: 46
2779 00:55:54.315008 [Byte1]: 46
2780 00:55:54.319706
2781 00:55:54.319861 Set Vref, RX VrefLevel [Byte0]: 47
2782 00:55:54.322667 [Byte1]: 47
2783 00:55:54.327433
2784 00:55:54.327538 Set Vref, RX VrefLevel [Byte0]: 48
2785 00:55:54.330952 [Byte1]: 48
2786 00:55:54.335259
2787 00:55:54.335348 Set Vref, RX VrefLevel [Byte0]: 49
2788 00:55:54.338713 [Byte1]: 49
2789 00:55:54.343480
2790 00:55:54.343571 Set Vref, RX VrefLevel [Byte0]: 50
2791 00:55:54.346985 [Byte1]: 50
2792 00:55:54.351562
2793 00:55:54.351689 Set Vref, RX VrefLevel [Byte0]: 51
2794 00:55:54.354331 [Byte1]: 51
2795 00:55:54.359182
2796 00:55:54.359299 Set Vref, RX VrefLevel [Byte0]: 52
2797 00:55:54.362397 [Byte1]: 52
2798 00:55:54.367254
2799 00:55:54.367340 Set Vref, RX VrefLevel [Byte0]: 53
2800 00:55:54.370254 [Byte1]: 53
2801 00:55:54.374861
2802 00:55:54.374971 Set Vref, RX VrefLevel [Byte0]: 54
2803 00:55:54.378187 [Byte1]: 54
2804 00:55:54.382964
2805 00:55:54.383093 Set Vref, RX VrefLevel [Byte0]: 55
2806 00:55:54.386667 [Byte1]: 55
2807 00:55:54.391548
2808 00:55:54.391661 Set Vref, RX VrefLevel [Byte0]: 56
2809 00:55:54.394186 [Byte1]: 56
2810 00:55:54.398720
2811 00:55:54.398829 Set Vref, RX VrefLevel [Byte0]: 57
2812 00:55:54.401946 [Byte1]: 57
2813 00:55:54.406535
2814 00:55:54.406654 Set Vref, RX VrefLevel [Byte0]: 58
2815 00:55:54.410542 [Byte1]: 58
2816 00:55:54.414791
2817 00:55:54.414907 Set Vref, RX VrefLevel [Byte0]: 59
2818 00:55:54.418171 [Byte1]: 59
2819 00:55:54.422345
2820 00:55:54.422460 Set Vref, RX VrefLevel [Byte0]: 60
2821 00:55:54.425712 [Byte1]: 60
2822 00:55:54.430487
2823 00:55:54.430593 Set Vref, RX VrefLevel [Byte0]: 61
2824 00:55:54.434468 [Byte1]: 61
2825 00:55:54.438946
2826 00:55:54.439051 Set Vref, RX VrefLevel [Byte0]: 62
2827 00:55:54.442294 [Byte1]: 62
2828 00:55:54.446838
2829 00:55:54.446946 Set Vref, RX VrefLevel [Byte0]: 63
2830 00:55:54.449396 [Byte1]: 63
2831 00:55:54.454117
2832 00:55:54.454230 Set Vref, RX VrefLevel [Byte0]: 64
2833 00:55:54.457847 [Byte1]: 64
2834 00:55:54.462185
2835 00:55:54.462306 Set Vref, RX VrefLevel [Byte0]: 65
2836 00:55:54.465219 [Byte1]: 65
2837 00:55:54.470414
2838 00:55:54.470542 Set Vref, RX VrefLevel [Byte0]: 66
2839 00:55:54.473259 [Byte1]: 66
2840 00:55:54.478056
2841 00:55:54.478204 Set Vref, RX VrefLevel [Byte0]: 67
2842 00:55:54.481860 [Byte1]: 67
2843 00:55:54.485920
2844 00:55:54.486028 Set Vref, RX VrefLevel [Byte0]: 68
2845 00:55:54.489161 [Byte1]: 68
2846 00:55:54.493881
2847 00:55:54.493988 Final RX Vref Byte 0 = 51 to rank0
2848 00:55:54.497036 Final RX Vref Byte 1 = 59 to rank0
2849 00:55:54.500897 Final RX Vref Byte 0 = 51 to rank1
2850 00:55:54.504401 Final RX Vref Byte 1 = 59 to rank1==
2851 00:55:54.507243 Dram Type= 6, Freq= 0, CH_0, rank 0
2852 00:55:54.513889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 00:55:54.514008 ==
2854 00:55:54.514100 DQS Delay:
2855 00:55:54.514186 DQS0 = 0, DQS1 = 0
2856 00:55:54.517064 DQM Delay:
2857 00:55:54.517169 DQM0 = 117, DQM1 = 105
2858 00:55:54.520572 DQ Delay:
2859 00:55:54.525072 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2860 00:55:54.527877 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2861 00:55:54.530560 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2862 00:55:54.533748 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2863 00:55:54.533856
2864 00:55:54.533950
2865 00:55:54.540586 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2866 00:55:54.544049 CH0 RK0: MR19=403, MR18=FB
2867 00:55:54.550755 CH0_RK0: MR19=0x403, MR18=0xFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2868 00:55:54.550870
2869 00:55:54.553826 ----->DramcWriteLeveling(PI) begin...
2870 00:55:54.553934 ==
2871 00:55:54.556996 Dram Type= 6, Freq= 0, CH_0, rank 1
2872 00:55:54.560284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 00:55:54.560395 ==
2874 00:55:54.563718 Write leveling (Byte 0): 31 => 31
2875 00:55:54.566830 Write leveling (Byte 1): 26 => 26
2876 00:55:54.570064 DramcWriteLeveling(PI) end<-----
2877 00:55:54.570180
2878 00:55:54.570272 ==
2879 00:55:54.573725 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 00:55:54.580761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 00:55:54.580923 ==
2882 00:55:54.581017 [Gating] SW mode calibration
2883 00:55:54.590421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2884 00:55:54.593569 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2885 00:55:54.596823 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2886 00:55:54.603231 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2887 00:55:54.606602 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 00:55:54.609851 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 00:55:54.616911 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 00:55:54.620057 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 00:55:54.623593 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2892 00:55:54.629963 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2893 00:55:54.633446 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2894 00:55:54.636809 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 00:55:54.643255 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 00:55:54.646474 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 00:55:54.649781 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 00:55:54.656520 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 00:55:54.660159 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2900 00:55:54.663147 1 0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2901 00:55:54.670325 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2902 00:55:54.673319 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 00:55:54.676402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 00:55:54.683305 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 00:55:54.686642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 00:55:54.690029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 00:55:54.696516 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2908 00:55:54.699726 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2909 00:55:54.702945 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 00:55:54.709646 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 00:55:54.713138 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 00:55:54.716321 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 00:55:54.722752 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 00:55:54.726893 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 00:55:54.730160 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 00:55:54.732999 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 00:55:54.739739 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 00:55:54.742763 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 00:55:54.746224 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 00:55:54.752975 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 00:55:54.757092 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 00:55:54.759603 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 00:55:54.765939 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 00:55:54.769277 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2925 00:55:54.772708 Total UI for P1: 0, mck2ui 16
2926 00:55:54.776228 best dqsien dly found for B0: ( 1, 3, 24)
2927 00:55:54.779544 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 00:55:54.782726 Total UI for P1: 0, mck2ui 16
2929 00:55:54.785851 best dqsien dly found for B1: ( 1, 3, 28)
2930 00:55:54.789291 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2931 00:55:54.792521 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2932 00:55:54.792613
2933 00:55:54.799470 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2934 00:55:54.802712 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2935 00:55:54.802844 [Gating] SW calibration Done
2936 00:55:54.806705 ==
2937 00:55:54.809650 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 00:55:54.812555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 00:55:54.812682 ==
2940 00:55:54.812767 RX Vref Scan: 0
2941 00:55:54.812828
2942 00:55:54.815983 RX Vref 0 -> 0, step: 1
2943 00:55:54.816121
2944 00:55:54.819281 RX Delay -40 -> 252, step: 8
2945 00:55:54.823123 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2946 00:55:54.825971 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2947 00:55:54.832623 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2948 00:55:54.836227 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2949 00:55:54.839498 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2950 00:55:54.842640 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2951 00:55:54.846574 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2952 00:55:54.849327 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2953 00:55:54.856768 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2954 00:55:54.858919 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2955 00:55:54.862465 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2956 00:55:54.865964 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2957 00:55:54.869816 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2958 00:55:54.876007 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2959 00:55:54.879272 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2960 00:55:54.882907 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2961 00:55:54.883051 ==
2962 00:55:54.885791 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 00:55:54.888932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 00:55:54.892029 ==
2965 00:55:54.892170 DQS Delay:
2966 00:55:54.892275 DQS0 = 0, DQS1 = 0
2967 00:55:54.895762 DQM Delay:
2968 00:55:54.895895 DQM0 = 115, DQM1 = 109
2969 00:55:54.898690 DQ Delay:
2970 00:55:54.902028 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2971 00:55:54.905493 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =119
2972 00:55:54.909350 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2973 00:55:54.912338 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2974 00:55:54.912478
2975 00:55:54.912577
2976 00:55:54.912672 ==
2977 00:55:54.915511 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 00:55:54.918710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 00:55:54.918848 ==
2980 00:55:54.918952
2981 00:55:54.922699
2982 00:55:54.922836 TX Vref Scan disable
2983 00:55:54.925429 == TX Byte 0 ==
2984 00:55:54.928538 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2985 00:55:54.932025 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2986 00:55:54.935284 == TX Byte 1 ==
2987 00:55:54.939214 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2988 00:55:54.941892 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2989 00:55:54.942034 ==
2990 00:55:54.945160 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 00:55:54.952517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 00:55:54.952704 ==
2993 00:55:54.962599 TX Vref=22, minBit 3, minWin=24, winSum=409
2994 00:55:54.966082 TX Vref=24, minBit 2, minWin=25, winSum=415
2995 00:55:54.969780 TX Vref=26, minBit 4, minWin=25, winSum=421
2996 00:55:54.972706 TX Vref=28, minBit 1, minWin=26, winSum=423
2997 00:55:54.975931 TX Vref=30, minBit 0, minWin=26, winSum=425
2998 00:55:54.982426 TX Vref=32, minBit 14, minWin=25, winSum=421
2999 00:55:54.985877 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
3000 00:55:54.986003
3001 00:55:54.989203 Final TX Range 1 Vref 30
3002 00:55:54.989381
3003 00:55:54.989490 ==
3004 00:55:54.993058 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 00:55:54.996061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 00:55:54.996175 ==
3007 00:55:54.999130
3008 00:55:54.999241
3009 00:55:54.999337 TX Vref Scan disable
3010 00:55:55.003067 == TX Byte 0 ==
3011 00:55:55.006432 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3012 00:55:55.009398 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3013 00:55:55.012372 == TX Byte 1 ==
3014 00:55:55.015896 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3015 00:55:55.022495 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3016 00:55:55.022674
3017 00:55:55.022777 [DATLAT]
3018 00:55:55.022869 Freq=1200, CH0 RK1
3019 00:55:55.022960
3020 00:55:55.026068 DATLAT Default: 0xd
3021 00:55:55.026201 0, 0xFFFF, sum = 0
3022 00:55:55.029949 1, 0xFFFF, sum = 0
3023 00:55:55.030061 2, 0xFFFF, sum = 0
3024 00:55:55.032889 3, 0xFFFF, sum = 0
3025 00:55:55.036089 4, 0xFFFF, sum = 0
3026 00:55:55.036206 5, 0xFFFF, sum = 0
3027 00:55:55.038923 6, 0xFFFF, sum = 0
3028 00:55:55.039034 7, 0xFFFF, sum = 0
3029 00:55:55.042575 8, 0xFFFF, sum = 0
3030 00:55:55.042687 9, 0xFFFF, sum = 0
3031 00:55:55.045829 10, 0xFFFF, sum = 0
3032 00:55:55.045939 11, 0xFFFF, sum = 0
3033 00:55:55.049140 12, 0x0, sum = 1
3034 00:55:55.049249 13, 0x0, sum = 2
3035 00:55:55.052786 14, 0x0, sum = 3
3036 00:55:55.052897 15, 0x0, sum = 4
3037 00:55:55.052993 best_step = 13
3038 00:55:55.056029
3039 00:55:55.056181 ==
3040 00:55:55.058852 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 00:55:55.061988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 00:55:55.062099 ==
3043 00:55:55.062195 RX Vref Scan: 0
3044 00:55:55.062288
3045 00:55:55.066133 RX Vref 0 -> 0, step: 1
3046 00:55:55.066247
3047 00:55:55.069761 RX Delay -21 -> 252, step: 4
3048 00:55:55.072301 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
3049 00:55:55.079074 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
3050 00:55:55.082066 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
3051 00:55:55.085761 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3052 00:55:55.089086 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
3053 00:55:55.092240 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
3054 00:55:55.099545 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3055 00:55:55.102263 iDelay=191, Bit 7, Center 122 (55 ~ 190) 136
3056 00:55:55.105560 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3057 00:55:55.108754 iDelay=191, Bit 9, Center 92 (27 ~ 158) 132
3058 00:55:55.112242 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3059 00:55:55.118986 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3060 00:55:55.122189 iDelay=191, Bit 12, Center 112 (47 ~ 178) 132
3061 00:55:55.125664 iDelay=191, Bit 13, Center 112 (47 ~ 178) 132
3062 00:55:55.128827 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3063 00:55:55.131946 iDelay=191, Bit 15, Center 114 (51 ~ 178) 128
3064 00:55:55.135659 ==
3065 00:55:55.138715 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 00:55:55.141902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 00:55:55.142125 ==
3068 00:55:55.142292 DQS Delay:
3069 00:55:55.145363 DQS0 = 0, DQS1 = 0
3070 00:55:55.145511 DQM Delay:
3071 00:55:55.148643 DQM0 = 115, DQM1 = 107
3072 00:55:55.148801 DQ Delay:
3073 00:55:55.152120 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3074 00:55:55.155207 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
3075 00:55:55.158412 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3076 00:55:55.161830 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3077 00:55:55.162020
3078 00:55:55.162154
3079 00:55:55.171671 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3080 00:55:55.175093 CH0 RK1: MR19=403, MR18=1FE
3081 00:55:55.178195 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3082 00:55:55.181677 [RxdqsGatingPostProcess] freq 1200
3083 00:55:55.188242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3084 00:55:55.191606 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 00:55:55.194876 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 00:55:55.198166 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 00:55:55.201428 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 00:55:55.204791 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 00:55:55.208025 best DQS1 dly(2T, 0.5T) = (0, 11)
3090 00:55:55.211768 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 00:55:55.214429 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3092 00:55:55.218029 Pre-setting of DQS Precalculation
3093 00:55:55.221491 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3094 00:55:55.221661 ==
3095 00:55:55.224940 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 00:55:55.227975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 00:55:55.228138 ==
3098 00:55:55.234443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 00:55:55.241299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3100 00:55:55.249143 [CA 0] Center 38 (8~68) winsize 61
3101 00:55:55.252303 [CA 1] Center 38 (8~68) winsize 61
3102 00:55:55.255668 [CA 2] Center 35 (6~65) winsize 60
3103 00:55:55.258969 [CA 3] Center 34 (4~64) winsize 61
3104 00:55:55.262528 [CA 4] Center 34 (4~65) winsize 62
3105 00:55:55.265059 [CA 5] Center 33 (3~63) winsize 61
3106 00:55:55.265168
3107 00:55:55.268508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 00:55:55.268598
3109 00:55:55.272245 [CATrainingPosCal] consider 1 rank data
3110 00:55:55.275482 u2DelayCellTimex100 = 270/100 ps
3111 00:55:55.279031 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 00:55:55.285486 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3113 00:55:55.288659 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3114 00:55:55.292164 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 00:55:55.295116 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3116 00:55:55.298244 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3117 00:55:55.298333
3118 00:55:55.301819 CA PerBit enable=1, Macro0, CA PI delay=33
3119 00:55:55.301905
3120 00:55:55.304907 [CBTSetCACLKResult] CA Dly = 33
3121 00:55:55.308137 CS Dly: 5 (0~36)
3122 00:55:55.308233 ==
3123 00:55:55.311555 Dram Type= 6, Freq= 0, CH_1, rank 1
3124 00:55:55.314906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 00:55:55.314997 ==
3126 00:55:55.321604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3127 00:55:55.325136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3128 00:55:55.334297 [CA 0] Center 37 (7~68) winsize 62
3129 00:55:55.337832 [CA 1] Center 38 (8~68) winsize 61
3130 00:55:55.340951 [CA 2] Center 35 (5~65) winsize 61
3131 00:55:55.344640 [CA 3] Center 33 (3~64) winsize 62
3132 00:55:55.347485 [CA 4] Center 34 (4~64) winsize 61
3133 00:55:55.351248 [CA 5] Center 33 (3~64) winsize 62
3134 00:55:55.351358
3135 00:55:55.354586 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3136 00:55:55.354693
3137 00:55:55.358186 [CATrainingPosCal] consider 2 rank data
3138 00:55:55.361246 u2DelayCellTimex100 = 270/100 ps
3139 00:55:55.364278 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3140 00:55:55.370760 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3141 00:55:55.374798 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3142 00:55:55.377668 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 00:55:55.380656 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3144 00:55:55.384132 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3145 00:55:55.384248
3146 00:55:55.387914 CA PerBit enable=1, Macro0, CA PI delay=33
3147 00:55:55.388027
3148 00:55:55.390498 [CBTSetCACLKResult] CA Dly = 33
3149 00:55:55.394920 CS Dly: 6 (0~39)
3150 00:55:55.395035
3151 00:55:55.397798 ----->DramcWriteLeveling(PI) begin...
3152 00:55:55.397908 ==
3153 00:55:55.400755 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 00:55:55.404055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 00:55:55.404176 ==
3156 00:55:55.407297 Write leveling (Byte 0): 25 => 25
3157 00:55:55.410603 Write leveling (Byte 1): 28 => 28
3158 00:55:55.413880 DramcWriteLeveling(PI) end<-----
3159 00:55:55.413993
3160 00:55:55.414088 ==
3161 00:55:55.417491 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 00:55:55.420494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 00:55:55.420603 ==
3164 00:55:55.423681 [Gating] SW mode calibration
3165 00:55:55.432148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3166 00:55:55.437375 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3167 00:55:55.440481 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3168 00:55:55.443705 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 00:55:55.450328 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 00:55:55.453589 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 00:55:55.456743 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 00:55:55.463671 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 00:55:55.466908 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3174 00:55:55.470966 0 15 28 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
3175 00:55:55.477641 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 00:55:55.479995 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 00:55:55.483950 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 00:55:55.490204 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 00:55:55.493666 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 00:55:55.496669 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 00:55:55.503956 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3182 00:55:55.507150 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3183 00:55:55.510338 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 00:55:55.516717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 00:55:55.519859 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 00:55:55.523554 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 00:55:55.529984 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 00:55:55.533196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 00:55:55.536648 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3190 00:55:55.539736 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3191 00:55:55.546523 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 00:55:55.549839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 00:55:55.553131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 00:55:55.560567 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 00:55:55.563235 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 00:55:55.566083 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 00:55:55.572944 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 00:55:55.576477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 00:55:55.579509 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 00:55:55.586440 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 00:55:55.589771 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 00:55:55.593166 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 00:55:55.599752 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 00:55:55.602654 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 00:55:55.605854 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3206 00:55:55.612773 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3207 00:55:55.616205 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 00:55:55.619424 Total UI for P1: 0, mck2ui 16
3209 00:55:55.622704 best dqsien dly found for B0: ( 1, 3, 26)
3210 00:55:55.625819 Total UI for P1: 0, mck2ui 16
3211 00:55:55.629423 best dqsien dly found for B1: ( 1, 3, 28)
3212 00:55:55.632598 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3213 00:55:55.636277 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3214 00:55:55.636371
3215 00:55:55.639195 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 00:55:55.642453 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3217 00:55:55.645733 [Gating] SW calibration Done
3218 00:55:55.645822 ==
3219 00:55:55.649226 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 00:55:55.652768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 00:55:55.655643 ==
3222 00:55:55.655725 RX Vref Scan: 0
3223 00:55:55.655789
3224 00:55:55.659270 RX Vref 0 -> 0, step: 1
3225 00:55:55.659394
3226 00:55:55.662443 RX Delay -40 -> 252, step: 8
3227 00:55:55.665956 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3228 00:55:55.668934 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3229 00:55:55.672056 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3230 00:55:55.675719 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3231 00:55:55.682437 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3232 00:55:55.685611 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3233 00:55:55.689526 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3234 00:55:55.692369 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3235 00:55:55.696165 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3236 00:55:55.702128 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3237 00:55:55.705233 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3238 00:55:55.708640 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3239 00:55:55.711951 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3240 00:55:55.718828 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3241 00:55:55.722217 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3242 00:55:55.725519 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3243 00:55:55.725627 ==
3244 00:55:55.729187 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 00:55:55.732192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 00:55:55.732278 ==
3247 00:55:55.735084 DQS Delay:
3248 00:55:55.735192 DQS0 = 0, DQS1 = 0
3249 00:55:55.735299 DQM Delay:
3250 00:55:55.738723 DQM0 = 115, DQM1 = 112
3251 00:55:55.738811 DQ Delay:
3252 00:55:55.741860 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3253 00:55:55.745097 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3254 00:55:55.751992 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3255 00:55:55.755034 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3256 00:55:55.755124
3257 00:55:55.755229
3258 00:55:55.755290 ==
3259 00:55:55.758205 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 00:55:55.761717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 00:55:55.761825 ==
3262 00:55:55.761906
3263 00:55:55.761967
3264 00:55:55.764879 TX Vref Scan disable
3265 00:55:55.768636 == TX Byte 0 ==
3266 00:55:55.771647 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3267 00:55:55.774977 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3268 00:55:55.778205 == TX Byte 1 ==
3269 00:55:55.781598 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 00:55:55.785022 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 00:55:55.785111 ==
3272 00:55:55.788396 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 00:55:55.791648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 00:55:55.791761 ==
3275 00:55:55.805038 TX Vref=22, minBit 9, minWin=24, winSum=411
3276 00:55:55.808889 TX Vref=24, minBit 9, minWin=25, winSum=420
3277 00:55:55.811304 TX Vref=26, minBit 8, minWin=25, winSum=423
3278 00:55:55.814685 TX Vref=28, minBit 9, minWin=25, winSum=423
3279 00:55:55.818077 TX Vref=30, minBit 2, minWin=26, winSum=429
3280 00:55:55.824374 TX Vref=32, minBit 11, minWin=25, winSum=422
3281 00:55:55.827945 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3282 00:55:55.828047
3283 00:55:55.831515 Final TX Range 1 Vref 30
3284 00:55:55.831605
3285 00:55:55.831671 ==
3286 00:55:55.834641 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 00:55:55.837885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 00:55:55.837981 ==
3289 00:55:55.841175
3290 00:55:55.841263
3291 00:55:55.841328 TX Vref Scan disable
3292 00:55:55.844535 == TX Byte 0 ==
3293 00:55:55.848519 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3294 00:55:55.851253 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3295 00:55:55.854956 == TX Byte 1 ==
3296 00:55:55.858056 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3297 00:55:55.861426 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3298 00:55:55.861523
3299 00:55:55.865108 [DATLAT]
3300 00:55:55.865202 Freq=1200, CH1 RK0
3301 00:55:55.865269
3302 00:55:55.868165 DATLAT Default: 0xd
3303 00:55:55.868251 0, 0xFFFF, sum = 0
3304 00:55:55.871250 1, 0xFFFF, sum = 0
3305 00:55:55.871388 2, 0xFFFF, sum = 0
3306 00:55:55.874682 3, 0xFFFF, sum = 0
3307 00:55:55.874772 4, 0xFFFF, sum = 0
3308 00:55:55.878149 5, 0xFFFF, sum = 0
3309 00:55:55.878239 6, 0xFFFF, sum = 0
3310 00:55:55.881367 7, 0xFFFF, sum = 0
3311 00:55:55.884997 8, 0xFFFF, sum = 0
3312 00:55:55.885094 9, 0xFFFF, sum = 0
3313 00:55:55.887827 10, 0xFFFF, sum = 0
3314 00:55:55.887914 11, 0xFFFF, sum = 0
3315 00:55:55.891297 12, 0x0, sum = 1
3316 00:55:55.891428 13, 0x0, sum = 2
3317 00:55:55.894754 14, 0x0, sum = 3
3318 00:55:55.894841 15, 0x0, sum = 4
3319 00:55:55.894908 best_step = 13
3320 00:55:55.894969
3321 00:55:55.897877 ==
3322 00:55:55.901234 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 00:55:55.904903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 00:55:55.905004 ==
3325 00:55:55.905072 RX Vref Scan: 1
3326 00:55:55.905148
3327 00:55:55.907742 Set Vref Range= 32 -> 127
3328 00:55:55.907831
3329 00:55:55.910988 RX Vref 32 -> 127, step: 1
3330 00:55:55.911103
3331 00:55:55.914294 RX Delay -13 -> 252, step: 4
3332 00:55:55.914386
3333 00:55:55.917945 Set Vref, RX VrefLevel [Byte0]: 32
3334 00:55:55.921098 [Byte1]: 32
3335 00:55:55.921196
3336 00:55:55.924460 Set Vref, RX VrefLevel [Byte0]: 33
3337 00:55:55.927381 [Byte1]: 33
3338 00:55:55.931404
3339 00:55:55.931512 Set Vref, RX VrefLevel [Byte0]: 34
3340 00:55:55.934455 [Byte1]: 34
3341 00:55:55.938963
3342 00:55:55.939051 Set Vref, RX VrefLevel [Byte0]: 35
3343 00:55:55.942080 [Byte1]: 35
3344 00:55:55.946741
3345 00:55:55.946851 Set Vref, RX VrefLevel [Byte0]: 36
3346 00:55:55.950187 [Byte1]: 36
3347 00:55:55.954864
3348 00:55:55.954983 Set Vref, RX VrefLevel [Byte0]: 37
3349 00:55:55.957919 [Byte1]: 37
3350 00:55:55.962826
3351 00:55:55.962917 Set Vref, RX VrefLevel [Byte0]: 38
3352 00:55:55.966282 [Byte1]: 38
3353 00:55:55.970437
3354 00:55:55.970528 Set Vref, RX VrefLevel [Byte0]: 39
3355 00:55:55.973497 [Byte1]: 39
3356 00:55:55.978172
3357 00:55:55.978299 Set Vref, RX VrefLevel [Byte0]: 40
3358 00:55:55.981510 [Byte1]: 40
3359 00:55:55.985996
3360 00:55:55.986120 Set Vref, RX VrefLevel [Byte0]: 41
3361 00:55:55.989572 [Byte1]: 41
3362 00:55:55.993810
3363 00:55:55.993925 Set Vref, RX VrefLevel [Byte0]: 42
3364 00:55:55.998033 [Byte1]: 42
3365 00:55:56.002162
3366 00:55:56.002279 Set Vref, RX VrefLevel [Byte0]: 43
3367 00:55:56.005008 [Byte1]: 43
3368 00:55:56.010071
3369 00:55:56.010211 Set Vref, RX VrefLevel [Byte0]: 44
3370 00:55:56.012892 [Byte1]: 44
3371 00:55:56.017539
3372 00:55:56.017659 Set Vref, RX VrefLevel [Byte0]: 45
3373 00:55:56.020955 [Byte1]: 45
3374 00:55:56.025397
3375 00:55:56.025514 Set Vref, RX VrefLevel [Byte0]: 46
3376 00:55:56.028789 [Byte1]: 46
3377 00:55:56.033230
3378 00:55:56.033356 Set Vref, RX VrefLevel [Byte0]: 47
3379 00:55:56.036822 [Byte1]: 47
3380 00:55:56.041110
3381 00:55:56.041227 Set Vref, RX VrefLevel [Byte0]: 48
3382 00:55:56.044721 [Byte1]: 48
3383 00:55:56.049402
3384 00:55:56.049513 Set Vref, RX VrefLevel [Byte0]: 49
3385 00:55:56.052397 [Byte1]: 49
3386 00:55:56.057222
3387 00:55:56.057332 Set Vref, RX VrefLevel [Byte0]: 50
3388 00:55:56.060443 [Byte1]: 50
3389 00:55:56.065308
3390 00:55:56.065436 Set Vref, RX VrefLevel [Byte0]: 51
3391 00:55:56.068215 [Byte1]: 51
3392 00:55:56.072775
3393 00:55:56.072891 Set Vref, RX VrefLevel [Byte0]: 52
3394 00:55:56.076095 [Byte1]: 52
3395 00:55:56.080651
3396 00:55:56.084243 Set Vref, RX VrefLevel [Byte0]: 53
3397 00:55:56.084364 [Byte1]: 53
3398 00:55:56.088367
3399 00:55:56.088479 Set Vref, RX VrefLevel [Byte0]: 54
3400 00:55:56.091560 [Byte1]: 54
3401 00:55:56.097000
3402 00:55:56.097123 Set Vref, RX VrefLevel [Byte0]: 55
3403 00:55:56.099877 [Byte1]: 55
3404 00:55:56.104569
3405 00:55:56.104679 Set Vref, RX VrefLevel [Byte0]: 56
3406 00:55:56.108159 [Byte1]: 56
3407 00:55:56.112339
3408 00:55:56.112460 Set Vref, RX VrefLevel [Byte0]: 57
3409 00:55:56.115499 [Byte1]: 57
3410 00:55:56.120082
3411 00:55:56.120201 Set Vref, RX VrefLevel [Byte0]: 58
3412 00:55:56.123633 [Byte1]: 58
3413 00:55:56.128064
3414 00:55:56.128183 Set Vref, RX VrefLevel [Byte0]: 59
3415 00:55:56.131299 [Byte1]: 59
3416 00:55:56.135762
3417 00:55:56.135880 Set Vref, RX VrefLevel [Byte0]: 60
3418 00:55:56.139233 [Byte1]: 60
3419 00:55:56.144316
3420 00:55:56.144444 Set Vref, RX VrefLevel [Byte0]: 61
3421 00:55:56.146903 [Byte1]: 61
3422 00:55:56.151534
3423 00:55:56.151654 Set Vref, RX VrefLevel [Byte0]: 62
3424 00:55:56.155596 [Byte1]: 62
3425 00:55:56.159344
3426 00:55:56.159484 Set Vref, RX VrefLevel [Byte0]: 63
3427 00:55:56.163290 [Byte1]: 63
3428 00:55:56.167536
3429 00:55:56.167656 Set Vref, RX VrefLevel [Byte0]: 64
3430 00:55:56.170426 [Byte1]: 64
3431 00:55:56.175318
3432 00:55:56.175470 Set Vref, RX VrefLevel [Byte0]: 65
3433 00:55:56.178593 [Byte1]: 65
3434 00:55:56.183216
3435 00:55:56.183315 Final RX Vref Byte 0 = 51 to rank0
3436 00:55:56.186215 Final RX Vref Byte 1 = 52 to rank0
3437 00:55:56.189840 Final RX Vref Byte 0 = 51 to rank1
3438 00:55:56.192860 Final RX Vref Byte 1 = 52 to rank1==
3439 00:55:56.196599 Dram Type= 6, Freq= 0, CH_1, rank 0
3440 00:55:56.202791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 00:55:56.202892 ==
3442 00:55:56.202980 DQS Delay:
3443 00:55:56.205918 DQS0 = 0, DQS1 = 0
3444 00:55:56.206005 DQM Delay:
3445 00:55:56.206091 DQM0 = 115, DQM1 = 113
3446 00:55:56.209727 DQ Delay:
3447 00:55:56.212864 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3448 00:55:56.216418 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3449 00:55:56.219518 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3450 00:55:56.222930 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3451 00:55:56.223018
3452 00:55:56.223119
3453 00:55:56.233147 [DQSOSCAuto] RK0, (LSB)MR18= 0xf502, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3454 00:55:56.233272 CH1 RK0: MR19=304, MR18=F502
3455 00:55:56.239288 CH1_RK0: MR19=0x304, MR18=0xF502, DQSOSC=409, MR23=63, INC=39, DEC=26
3456 00:55:56.239429
3457 00:55:56.243137 ----->DramcWriteLeveling(PI) begin...
3458 00:55:56.243228 ==
3459 00:55:56.245986 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 00:55:56.252978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 00:55:56.253080 ==
3462 00:55:56.256188 Write leveling (Byte 0): 26 => 26
3463 00:55:56.256277 Write leveling (Byte 1): 28 => 28
3464 00:55:56.259373 DramcWriteLeveling(PI) end<-----
3465 00:55:56.259513
3466 00:55:56.262751 ==
3467 00:55:56.262855 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 00:55:56.269511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 00:55:56.269616 ==
3470 00:55:56.273267 [Gating] SW mode calibration
3471 00:55:56.279097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3472 00:55:56.282802 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3473 00:55:56.289643 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3474 00:55:56.292822 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 00:55:56.295746 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 00:55:56.302316 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 00:55:56.305876 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 00:55:56.309284 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3479 00:55:56.315617 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
3480 00:55:56.319258 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
3481 00:55:56.322147 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 00:55:56.328761 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 00:55:56.332728 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 00:55:56.335662 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 00:55:56.342506 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 00:55:56.345388 1 0 20 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
3487 00:55:56.349107 1 0 24 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
3488 00:55:56.355188 1 0 28 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3489 00:55:56.358831 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:55:56.362096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 00:55:56.368516 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 00:55:56.372107 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 00:55:56.375239 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 00:55:56.381787 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 00:55:56.384904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3496 00:55:56.388148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 00:55:56.395058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 00:55:56.398294 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 00:55:56.401239 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 00:55:56.408032 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 00:55:56.411422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 00:55:56.415054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 00:55:56.421441 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 00:55:56.425025 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 00:55:56.427845 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 00:55:56.434147 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 00:55:56.437510 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 00:55:56.441055 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 00:55:56.447987 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 00:55:56.450895 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3511 00:55:56.454711 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3512 00:55:56.461205 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3513 00:55:56.461300 Total UI for P1: 0, mck2ui 16
3514 00:55:56.467188 best dqsien dly found for B0: ( 1, 3, 22)
3515 00:55:56.471159 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 00:55:56.474670 Total UI for P1: 0, mck2ui 16
3517 00:55:56.477197 best dqsien dly found for B1: ( 1, 3, 28)
3518 00:55:56.480428 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3519 00:55:56.483550 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3520 00:55:56.483636
3521 00:55:56.487551 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3522 00:55:56.490334 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3523 00:55:56.494132 [Gating] SW calibration Done
3524 00:55:56.494217 ==
3525 00:55:56.497355 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 00:55:56.500539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 00:55:56.503611 ==
3528 00:55:56.503695 RX Vref Scan: 0
3529 00:55:56.503760
3530 00:55:56.507592 RX Vref 0 -> 0, step: 1
3531 00:55:56.507683
3532 00:55:56.510415 RX Delay -40 -> 252, step: 8
3533 00:55:56.513459 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3534 00:55:56.516588 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3535 00:55:56.520359 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3536 00:55:56.523258 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3537 00:55:56.529773 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3538 00:55:56.533176 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3539 00:55:56.536719 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3540 00:55:56.539878 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3541 00:55:56.543167 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3542 00:55:56.549822 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3543 00:55:56.552890 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3544 00:55:56.556189 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3545 00:55:56.559270 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3546 00:55:56.566207 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3547 00:55:56.569436 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3548 00:55:56.572909 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3549 00:55:56.573024 ==
3550 00:55:56.575745 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 00:55:56.579231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 00:55:56.579370 ==
3553 00:55:56.582331 DQS Delay:
3554 00:55:56.582440 DQS0 = 0, DQS1 = 0
3555 00:55:56.585758 DQM Delay:
3556 00:55:56.585868 DQM0 = 114, DQM1 = 111
3557 00:55:56.585963 DQ Delay:
3558 00:55:56.592194 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3559 00:55:56.595547 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3560 00:55:56.598660 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3561 00:55:56.602451 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3562 00:55:56.602568
3563 00:55:56.602663
3564 00:55:56.602755 ==
3565 00:55:56.605589 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 00:55:56.609176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 00:55:56.609303 ==
3568 00:55:56.609399
3569 00:55:56.609487
3570 00:55:56.612331 TX Vref Scan disable
3571 00:55:56.615659 == TX Byte 0 ==
3572 00:55:56.618419 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 00:55:56.621887 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 00:55:56.625768 == TX Byte 1 ==
3575 00:55:56.628239 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3576 00:55:56.631984 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3577 00:55:56.632093 ==
3578 00:55:56.635382 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 00:55:56.641844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 00:55:56.641963 ==
3581 00:55:56.652573 TX Vref=22, minBit 1, minWin=25, winSum=420
3582 00:55:56.655965 TX Vref=24, minBit 9, minWin=25, winSum=424
3583 00:55:56.659134 TX Vref=26, minBit 1, minWin=26, winSum=428
3584 00:55:56.662792 TX Vref=28, minBit 1, minWin=26, winSum=428
3585 00:55:56.665797 TX Vref=30, minBit 1, minWin=26, winSum=432
3586 00:55:56.671558 TX Vref=32, minBit 8, minWin=26, winSum=431
3587 00:55:56.674975 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3588 00:55:56.675097
3589 00:55:56.678329 Final TX Range 1 Vref 30
3590 00:55:56.678441
3591 00:55:56.678534 ==
3592 00:55:56.681443 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 00:55:56.685637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 00:55:56.688386 ==
3595 00:55:56.688479
3596 00:55:56.688566
3597 00:55:56.688647 TX Vref Scan disable
3598 00:55:56.691705 == TX Byte 0 ==
3599 00:55:56.695632 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3600 00:55:56.701734 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3601 00:55:56.701836 == TX Byte 1 ==
3602 00:55:56.704875 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3603 00:55:56.711476 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3604 00:55:56.711593
3605 00:55:56.711683 [DATLAT]
3606 00:55:56.711763 Freq=1200, CH1 RK1
3607 00:55:56.711843
3608 00:55:56.715259 DATLAT Default: 0xd
3609 00:55:56.715346 0, 0xFFFF, sum = 0
3610 00:55:56.718051 1, 0xFFFF, sum = 0
3611 00:55:56.721686 2, 0xFFFF, sum = 0
3612 00:55:56.721776 3, 0xFFFF, sum = 0
3613 00:55:56.724986 4, 0xFFFF, sum = 0
3614 00:55:56.725074 5, 0xFFFF, sum = 0
3615 00:55:56.728569 6, 0xFFFF, sum = 0
3616 00:55:56.728655 7, 0xFFFF, sum = 0
3617 00:55:56.731276 8, 0xFFFF, sum = 0
3618 00:55:56.731370 9, 0xFFFF, sum = 0
3619 00:55:56.735127 10, 0xFFFF, sum = 0
3620 00:55:56.735213 11, 0xFFFF, sum = 0
3621 00:55:56.738165 12, 0x0, sum = 1
3622 00:55:56.738252 13, 0x0, sum = 2
3623 00:55:56.741541 14, 0x0, sum = 3
3624 00:55:56.741629 15, 0x0, sum = 4
3625 00:55:56.744718 best_step = 13
3626 00:55:56.744802
3627 00:55:56.744888 ==
3628 00:55:56.747847 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 00:55:56.751249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 00:55:56.751335 ==
3631 00:55:56.754399 RX Vref Scan: 0
3632 00:55:56.754486
3633 00:55:56.754572 RX Vref 0 -> 0, step: 1
3634 00:55:56.754654
3635 00:55:56.757759 RX Delay -13 -> 252, step: 4
3636 00:55:56.764515 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3637 00:55:56.768029 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3638 00:55:56.770889 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3639 00:55:56.774075 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3640 00:55:56.777469 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3641 00:55:56.784500 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3642 00:55:56.787300 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3643 00:55:56.790845 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3644 00:55:56.793776 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3645 00:55:56.797134 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3646 00:55:56.803859 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3647 00:55:56.807044 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3648 00:55:56.810298 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3649 00:55:56.813600 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3650 00:55:56.820468 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3651 00:55:56.823493 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3652 00:55:56.823592 ==
3653 00:55:56.826971 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 00:55:56.830058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 00:55:56.830177 ==
3656 00:55:56.833621 DQS Delay:
3657 00:55:56.833733 DQS0 = 0, DQS1 = 0
3658 00:55:56.833828 DQM Delay:
3659 00:55:56.837075 DQM0 = 114, DQM1 = 112
3660 00:55:56.837186 DQ Delay:
3661 00:55:56.840188 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3662 00:55:56.843435 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3663 00:55:56.846561 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3664 00:55:56.852996 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3665 00:55:56.853133
3666 00:55:56.853229
3667 00:55:56.859726 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3668 00:55:56.862923 CH1 RK1: MR19=304, MR18=F90B
3669 00:55:56.869638 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3670 00:55:56.873175 [RxdqsGatingPostProcess] freq 1200
3671 00:55:56.876482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3672 00:55:56.879520 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 00:55:56.883312 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 00:55:56.886550 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 00:55:56.889632 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 00:55:56.893120 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 00:55:56.895831 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 00:55:56.899076 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 00:55:56.902623 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 00:55:56.906404 Pre-setting of DQS Precalculation
3681 00:55:56.912503 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3682 00:55:56.918751 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3683 00:55:56.925372 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3684 00:55:56.925528
3685 00:55:56.925630
3686 00:55:56.928967 [Calibration Summary] 2400 Mbps
3687 00:55:56.929078 CH 0, Rank 0
3688 00:55:56.932281 SW Impedance : PASS
3689 00:55:56.935287 DUTY Scan : NO K
3690 00:55:56.935408 ZQ Calibration : PASS
3691 00:55:56.939044 Jitter Meter : NO K
3692 00:55:56.942058 CBT Training : PASS
3693 00:55:56.942189 Write leveling : PASS
3694 00:55:56.945644 RX DQS gating : PASS
3695 00:55:56.948557 RX DQ/DQS(RDDQC) : PASS
3696 00:55:56.948675 TX DQ/DQS : PASS
3697 00:55:56.951809 RX DATLAT : PASS
3698 00:55:56.951924 RX DQ/DQS(Engine): PASS
3699 00:55:56.955563 TX OE : NO K
3700 00:55:56.955680 All Pass.
3701 00:55:56.955774
3702 00:55:56.959057 CH 0, Rank 1
3703 00:55:56.959170 SW Impedance : PASS
3704 00:55:56.961955 DUTY Scan : NO K
3705 00:55:56.964924 ZQ Calibration : PASS
3706 00:55:56.965037 Jitter Meter : NO K
3707 00:55:56.968310 CBT Training : PASS
3708 00:55:56.971679 Write leveling : PASS
3709 00:55:56.971824 RX DQS gating : PASS
3710 00:55:56.975168 RX DQ/DQS(RDDQC) : PASS
3711 00:55:56.978685 TX DQ/DQS : PASS
3712 00:55:56.978859 RX DATLAT : PASS
3713 00:55:56.981757 RX DQ/DQS(Engine): PASS
3714 00:55:56.984584 TX OE : NO K
3715 00:55:56.984724 All Pass.
3716 00:55:56.984822
3717 00:55:56.984914 CH 1, Rank 0
3718 00:55:56.988133 SW Impedance : PASS
3719 00:55:56.991138 DUTY Scan : NO K
3720 00:55:56.991252 ZQ Calibration : PASS
3721 00:55:56.994970 Jitter Meter : NO K
3722 00:55:56.998010 CBT Training : PASS
3723 00:55:56.998126 Write leveling : PASS
3724 00:55:57.001186 RX DQS gating : PASS
3725 00:55:57.004879 RX DQ/DQS(RDDQC) : PASS
3726 00:55:57.004994 TX DQ/DQS : PASS
3727 00:55:57.007924 RX DATLAT : PASS
3728 00:55:57.010950 RX DQ/DQS(Engine): PASS
3729 00:55:57.011078 TX OE : NO K
3730 00:55:57.014261 All Pass.
3731 00:55:57.014373
3732 00:55:57.014468 CH 1, Rank 1
3733 00:55:57.017528 SW Impedance : PASS
3734 00:55:57.017640 DUTY Scan : NO K
3735 00:55:57.021284 ZQ Calibration : PASS
3736 00:55:57.024021 Jitter Meter : NO K
3737 00:55:57.024134 CBT Training : PASS
3738 00:55:57.027191 Write leveling : PASS
3739 00:55:57.030811 RX DQS gating : PASS
3740 00:55:57.030929 RX DQ/DQS(RDDQC) : PASS
3741 00:55:57.034360 TX DQ/DQS : PASS
3742 00:55:57.037534 RX DATLAT : PASS
3743 00:55:57.037655 RX DQ/DQS(Engine): PASS
3744 00:55:57.040658 TX OE : NO K
3745 00:55:57.040771 All Pass.
3746 00:55:57.040864
3747 00:55:57.044194 DramC Write-DBI off
3748 00:55:57.047074 PER_BANK_REFRESH: Hybrid Mode
3749 00:55:57.047263 TX_TRACKING: ON
3750 00:55:57.056938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3751 00:55:57.060649 [FAST_K] Save calibration result to emmc
3752 00:55:57.063452 dramc_set_vcore_voltage set vcore to 650000
3753 00:55:57.067235 Read voltage for 600, 5
3754 00:55:57.067387 Vio18 = 0
3755 00:55:57.067500 Vcore = 650000
3756 00:55:57.070125 Vdram = 0
3757 00:55:57.070250 Vddq = 0
3758 00:55:57.070360 Vmddr = 0
3759 00:55:57.076617 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3760 00:55:57.080060 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3761 00:55:57.083338 MEM_TYPE=3, freq_sel=19
3762 00:55:57.086893 sv_algorithm_assistance_LP4_1600
3763 00:55:57.089924 ============ PULL DRAM RESETB DOWN ============
3764 00:55:57.093446 ========== PULL DRAM RESETB DOWN end =========
3765 00:55:57.100090 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3766 00:55:57.103290 ===================================
3767 00:55:57.106601 LPDDR4 DRAM CONFIGURATION
3768 00:55:57.109799 ===================================
3769 00:55:57.109934 EX_ROW_EN[0] = 0x0
3770 00:55:57.113107 EX_ROW_EN[1] = 0x0
3771 00:55:57.113219 LP4Y_EN = 0x0
3772 00:55:57.116552 WORK_FSP = 0x0
3773 00:55:57.116660 WL = 0x2
3774 00:55:57.119586 RL = 0x2
3775 00:55:57.119694 BL = 0x2
3776 00:55:57.123032 RPST = 0x0
3777 00:55:57.123139 RD_PRE = 0x0
3778 00:55:57.126263 WR_PRE = 0x1
3779 00:55:57.126371 WR_PST = 0x0
3780 00:55:57.129589 DBI_WR = 0x0
3781 00:55:57.132550 DBI_RD = 0x0
3782 00:55:57.132659 OTF = 0x1
3783 00:55:57.136139 ===================================
3784 00:55:57.139384 ===================================
3785 00:55:57.142714 ANA top config
3786 00:55:57.145708 ===================================
3787 00:55:57.145821 DLL_ASYNC_EN = 0
3788 00:55:57.149141 ALL_SLAVE_EN = 1
3789 00:55:57.152132 NEW_RANK_MODE = 1
3790 00:55:57.155525 DLL_IDLE_MODE = 1
3791 00:55:57.155635 LP45_APHY_COMB_EN = 1
3792 00:55:57.159546 TX_ODT_DIS = 1
3793 00:55:57.162038 NEW_8X_MODE = 1
3794 00:55:57.165539 ===================================
3795 00:55:57.168625 ===================================
3796 00:55:57.172522 data_rate = 1200
3797 00:55:57.175573 CKR = 1
3798 00:55:57.178801 DQ_P2S_RATIO = 8
3799 00:55:57.182249 ===================================
3800 00:55:57.182366 CA_P2S_RATIO = 8
3801 00:55:57.185308 DQ_CA_OPEN = 0
3802 00:55:57.189218 DQ_SEMI_OPEN = 0
3803 00:55:57.192231 CA_SEMI_OPEN = 0
3804 00:55:57.195395 CA_FULL_RATE = 0
3805 00:55:57.199075 DQ_CKDIV4_EN = 1
3806 00:55:57.199190 CA_CKDIV4_EN = 1
3807 00:55:57.202103 CA_PREDIV_EN = 0
3808 00:55:57.205085 PH8_DLY = 0
3809 00:55:57.208205 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3810 00:55:57.211573 DQ_AAMCK_DIV = 4
3811 00:55:57.214789 CA_AAMCK_DIV = 4
3812 00:55:57.214929 CA_ADMCK_DIV = 4
3813 00:55:57.218213 DQ_TRACK_CA_EN = 0
3814 00:55:57.221329 CA_PICK = 600
3815 00:55:57.224622 CA_MCKIO = 600
3816 00:55:57.228042 MCKIO_SEMI = 0
3817 00:55:57.231101 PLL_FREQ = 2288
3818 00:55:57.234530 DQ_UI_PI_RATIO = 32
3819 00:55:57.237817 CA_UI_PI_RATIO = 0
3820 00:55:57.241542 ===================================
3821 00:55:57.245332 ===================================
3822 00:55:57.245444 memory_type:LPDDR4
3823 00:55:57.247764 GP_NUM : 10
3824 00:55:57.251059 SRAM_EN : 1
3825 00:55:57.251167 MD32_EN : 0
3826 00:55:57.254536 ===================================
3827 00:55:57.257756 [ANA_INIT] >>>>>>>>>>>>>>
3828 00:55:57.261034 <<<<<< [CONFIGURE PHASE]: ANA_TX
3829 00:55:57.264424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3830 00:55:57.267660 ===================================
3831 00:55:57.271218 data_rate = 1200,PCW = 0X5800
3832 00:55:57.274057 ===================================
3833 00:55:57.277677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3834 00:55:57.281540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3835 00:55:57.288192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 00:55:57.290838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3837 00:55:57.293853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3838 00:55:57.297788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3839 00:55:57.300496 [ANA_INIT] flow start
3840 00:55:57.304377 [ANA_INIT] PLL >>>>>>>>
3841 00:55:57.304496 [ANA_INIT] PLL <<<<<<<<
3842 00:55:57.307260 [ANA_INIT] MIDPI >>>>>>>>
3843 00:55:57.310738 [ANA_INIT] MIDPI <<<<<<<<
3844 00:55:57.313950 [ANA_INIT] DLL >>>>>>>>
3845 00:55:57.314066 [ANA_INIT] flow end
3846 00:55:57.316889 ============ LP4 DIFF to SE enter ============
3847 00:55:57.323882 ============ LP4 DIFF to SE exit ============
3848 00:55:57.324013 [ANA_INIT] <<<<<<<<<<<<<
3849 00:55:57.327399 [Flow] Enable top DCM control >>>>>
3850 00:55:57.329885 [Flow] Enable top DCM control <<<<<
3851 00:55:57.333500 Enable DLL master slave shuffle
3852 00:55:57.339833 ==============================================================
3853 00:55:57.339960 Gating Mode config
3854 00:55:57.346441 ==============================================================
3855 00:55:57.350233 Config description:
3856 00:55:57.359841 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3857 00:55:57.366282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3858 00:55:57.369478 SELPH_MODE 0: By rank 1: By Phase
3859 00:55:57.376111 ==============================================================
3860 00:55:57.379231 GAT_TRACK_EN = 1
3861 00:55:57.382656 RX_GATING_MODE = 2
3862 00:55:57.386430 RX_GATING_TRACK_MODE = 2
3863 00:55:57.386547 SELPH_MODE = 1
3864 00:55:57.389373 PICG_EARLY_EN = 1
3865 00:55:57.392883 VALID_LAT_VALUE = 1
3866 00:55:57.398920 ==============================================================
3867 00:55:57.402426 Enter into Gating configuration >>>>
3868 00:55:57.405567 Exit from Gating configuration <<<<
3869 00:55:57.408852 Enter into DVFS_PRE_config >>>>>
3870 00:55:57.418750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3871 00:55:57.422026 Exit from DVFS_PRE_config <<<<<
3872 00:55:57.425955 Enter into PICG configuration >>>>
3873 00:55:57.428620 Exit from PICG configuration <<<<
3874 00:55:57.432303 [RX_INPUT] configuration >>>>>
3875 00:55:57.435522 [RX_INPUT] configuration <<<<<
3876 00:55:57.439126 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3877 00:55:57.445807 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3878 00:55:57.451892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3879 00:55:57.458748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3880 00:55:57.465519 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 00:55:57.471806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 00:55:57.475550 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3883 00:55:57.478394 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3884 00:55:57.482214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3885 00:55:57.487918 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3886 00:55:57.491197 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3887 00:55:57.494567 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3888 00:55:57.498136 ===================================
3889 00:55:57.501245 LPDDR4 DRAM CONFIGURATION
3890 00:55:57.504644 ===================================
3891 00:55:57.507959 EX_ROW_EN[0] = 0x0
3892 00:55:57.508070 EX_ROW_EN[1] = 0x0
3893 00:55:57.511069 LP4Y_EN = 0x0
3894 00:55:57.511180 WORK_FSP = 0x0
3895 00:55:57.514314 WL = 0x2
3896 00:55:57.514421 RL = 0x2
3897 00:55:57.517544 BL = 0x2
3898 00:55:57.517648 RPST = 0x0
3899 00:55:57.520838 RD_PRE = 0x0
3900 00:55:57.520946 WR_PRE = 0x1
3901 00:55:57.524248 WR_PST = 0x0
3902 00:55:57.524355 DBI_WR = 0x0
3903 00:55:57.527814 DBI_RD = 0x0
3904 00:55:57.527920 OTF = 0x1
3905 00:55:57.530670 ===================================
3906 00:55:57.537431 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3907 00:55:57.540685 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3908 00:55:57.543779 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 00:55:57.547335 ===================================
3910 00:55:57.550385 LPDDR4 DRAM CONFIGURATION
3911 00:55:57.554053 ===================================
3912 00:55:57.557060 EX_ROW_EN[0] = 0x10
3913 00:55:57.557169 EX_ROW_EN[1] = 0x0
3914 00:55:57.560327 LP4Y_EN = 0x0
3915 00:55:57.560436 WORK_FSP = 0x0
3916 00:55:57.564616 WL = 0x2
3917 00:55:57.564722 RL = 0x2
3918 00:55:57.566943 BL = 0x2
3919 00:55:57.567049 RPST = 0x0
3920 00:55:57.570406 RD_PRE = 0x0
3921 00:55:57.570512 WR_PRE = 0x1
3922 00:55:57.573644 WR_PST = 0x0
3923 00:55:57.573750 DBI_WR = 0x0
3924 00:55:57.576775 DBI_RD = 0x0
3925 00:55:57.576881 OTF = 0x1
3926 00:55:57.579950 ===================================
3927 00:55:57.586719 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3928 00:55:57.591609 nWR fixed to 30
3929 00:55:57.594953 [ModeRegInit_LP4] CH0 RK0
3930 00:55:57.595062 [ModeRegInit_LP4] CH0 RK1
3931 00:55:57.598686 [ModeRegInit_LP4] CH1 RK0
3932 00:55:57.601562 [ModeRegInit_LP4] CH1 RK1
3933 00:55:57.601670 match AC timing 17
3934 00:55:57.608101 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3935 00:55:57.611509 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3936 00:55:57.614750 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3937 00:55:57.622112 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3938 00:55:57.625011 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3939 00:55:57.625127 ==
3940 00:55:57.628031 Dram Type= 6, Freq= 0, CH_0, rank 0
3941 00:55:57.630938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 00:55:57.631047 ==
3943 00:55:57.637492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 00:55:57.644053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3945 00:55:57.647858 [CA 0] Center 36 (6~67) winsize 62
3946 00:55:57.650956 [CA 1] Center 35 (5~66) winsize 62
3947 00:55:57.654442 [CA 2] Center 34 (4~65) winsize 62
3948 00:55:57.657494 [CA 3] Center 34 (3~65) winsize 63
3949 00:55:57.660719 [CA 4] Center 33 (3~64) winsize 62
3950 00:55:57.663778 [CA 5] Center 33 (3~64) winsize 62
3951 00:55:57.663887
3952 00:55:57.667464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3953 00:55:57.667574
3954 00:55:57.670253 [CATrainingPosCal] consider 1 rank data
3955 00:55:57.673640 u2DelayCellTimex100 = 270/100 ps
3956 00:55:57.676938 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3957 00:55:57.681324 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3958 00:55:57.686823 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 00:55:57.690814 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3960 00:55:57.693713 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 00:55:57.697670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 00:55:57.697782
3963 00:55:57.700401 CA PerBit enable=1, Macro0, CA PI delay=33
3964 00:55:57.700511
3965 00:55:57.703704 [CBTSetCACLKResult] CA Dly = 33
3966 00:55:57.703813 CS Dly: 4 (0~35)
3967 00:55:57.706804 ==
3968 00:55:57.706937 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 00:55:57.713233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 00:55:57.713363 ==
3971 00:55:57.716887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 00:55:57.723199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 00:55:57.726857 [CA 0] Center 36 (6~67) winsize 62
3974 00:55:57.730221 [CA 1] Center 36 (6~67) winsize 62
3975 00:55:57.733600 [CA 2] Center 34 (4~65) winsize 62
3976 00:55:57.736920 [CA 3] Center 34 (3~65) winsize 63
3977 00:55:57.740562 [CA 4] Center 33 (3~64) winsize 62
3978 00:55:57.743445 [CA 5] Center 33 (3~64) winsize 62
3979 00:55:57.743551
3980 00:55:57.747151 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 00:55:57.747256
3982 00:55:57.750134 [CATrainingPosCal] consider 2 rank data
3983 00:55:57.753309 u2DelayCellTimex100 = 270/100 ps
3984 00:55:57.756926 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3985 00:55:57.763280 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 00:55:57.766944 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3987 00:55:57.769730 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3988 00:55:57.773230 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3989 00:55:57.776147 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 00:55:57.776255
3991 00:55:57.779694 CA PerBit enable=1, Macro0, CA PI delay=33
3992 00:55:57.779801
3993 00:55:57.782897 [CBTSetCACLKResult] CA Dly = 33
3994 00:55:57.786278 CS Dly: 4 (0~36)
3995 00:55:57.786362
3996 00:55:57.789493 ----->DramcWriteLeveling(PI) begin...
3997 00:55:57.789577 ==
3998 00:55:57.793295 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 00:55:57.796563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 00:55:57.796646 ==
4001 00:55:57.800131 Write leveling (Byte 0): 32 => 32
4002 00:55:57.803011 Write leveling (Byte 1): 32 => 32
4003 00:55:57.806407 DramcWriteLeveling(PI) end<-----
4004 00:55:57.806491
4005 00:55:57.806592 ==
4006 00:55:57.809413 Dram Type= 6, Freq= 0, CH_0, rank 0
4007 00:55:57.812697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4008 00:55:57.812784 ==
4009 00:55:57.815990 [Gating] SW mode calibration
4010 00:55:57.822833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4011 00:55:57.829121 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4012 00:55:57.832369 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 00:55:57.835565 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 00:55:57.842037 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 00:55:57.845616 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4016 00:55:57.851927 0 9 16 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
4017 00:55:57.855841 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 00:55:57.858655 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 00:55:57.865225 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 00:55:57.869058 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 00:55:57.871950 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 00:55:57.878684 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 00:55:57.881439 0 10 12 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
4024 00:55:57.885081 0 10 16 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (0 0)
4025 00:55:57.891181 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 00:55:57.895236 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 00:55:57.898440 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 00:55:57.904429 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 00:55:57.907720 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 00:55:57.911461 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 00:55:57.918034 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 00:55:57.920869 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4033 00:55:57.924272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 00:55:57.931544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 00:55:57.934170 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 00:55:57.937378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 00:55:57.944049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 00:55:57.947584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 00:55:57.950767 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 00:55:57.957134 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 00:55:57.960467 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 00:55:57.964065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 00:55:57.971056 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 00:55:57.973524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 00:55:57.976806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 00:55:57.983797 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4047 00:55:57.987225 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4048 00:55:57.990408 Total UI for P1: 0, mck2ui 16
4049 00:55:57.993399 best dqsien dly found for B0: ( 0, 13, 8)
4050 00:55:57.996902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4051 00:55:58.003230 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 00:55:58.003346 Total UI for P1: 0, mck2ui 16
4053 00:55:58.010025 best dqsien dly found for B1: ( 0, 13, 16)
4054 00:55:58.012865 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4055 00:55:58.016299 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4056 00:55:58.016386
4057 00:55:58.019587 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4058 00:55:58.022716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4059 00:55:58.026502 [Gating] SW calibration Done
4060 00:55:58.026587 ==
4061 00:55:58.029690 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 00:55:58.033307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 00:55:58.033392 ==
4064 00:55:58.036076 RX Vref Scan: 0
4065 00:55:58.036157
4066 00:55:58.036236 RX Vref 0 -> 0, step: 1
4067 00:55:58.036314
4068 00:55:58.039672 RX Delay -230 -> 252, step: 16
4069 00:55:58.045889 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4070 00:55:58.049054 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4071 00:55:58.053201 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4072 00:55:58.055880 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4073 00:55:58.062931 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4074 00:55:58.066693 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4075 00:55:58.069393 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4076 00:55:58.072698 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4077 00:55:58.076197 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4078 00:55:58.082507 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4079 00:55:58.085336 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4080 00:55:58.089038 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4081 00:55:58.092058 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4082 00:55:58.099132 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4083 00:55:58.102640 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4084 00:55:58.105620 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4085 00:55:58.105733 ==
4086 00:55:58.109892 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 00:55:58.115308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 00:55:58.115483 ==
4089 00:55:58.115643 DQS Delay:
4090 00:55:58.115752 DQS0 = 0, DQS1 = 0
4091 00:55:58.118583 DQM Delay:
4092 00:55:58.118692 DQM0 = 40, DQM1 = 33
4093 00:55:58.121820 DQ Delay:
4094 00:55:58.125396 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4095 00:55:58.128458 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4096 00:55:58.131476 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4097 00:55:58.135146 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4098 00:55:58.135259
4099 00:55:58.135353
4100 00:55:58.135486 ==
4101 00:55:58.138307 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 00:55:58.141654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 00:55:58.141766 ==
4104 00:55:58.141860
4105 00:55:58.141949
4106 00:55:58.144560 TX Vref Scan disable
4107 00:55:58.144669 == TX Byte 0 ==
4108 00:55:58.151677 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4109 00:55:58.154867 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4110 00:55:58.157698 == TX Byte 1 ==
4111 00:55:58.160925 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4112 00:55:58.164563 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4113 00:55:58.164673 ==
4114 00:55:58.167506 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 00:55:58.170794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 00:55:58.174428 ==
4117 00:55:58.174538
4118 00:55:58.174632
4119 00:55:58.174722 TX Vref Scan disable
4120 00:55:58.178231 == TX Byte 0 ==
4121 00:55:58.181245 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4122 00:55:58.188089 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4123 00:55:58.188208 == TX Byte 1 ==
4124 00:55:58.191173 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4125 00:55:58.197749 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4126 00:55:58.197862
4127 00:55:58.197956 [DATLAT]
4128 00:55:58.198048 Freq=600, CH0 RK0
4129 00:55:58.198140
4130 00:55:58.201131 DATLAT Default: 0x9
4131 00:55:58.201269 0, 0xFFFF, sum = 0
4132 00:55:58.204798 1, 0xFFFF, sum = 0
4133 00:55:58.207597 2, 0xFFFF, sum = 0
4134 00:55:58.207709 3, 0xFFFF, sum = 0
4135 00:55:58.211096 4, 0xFFFF, sum = 0
4136 00:55:58.211210 5, 0xFFFF, sum = 0
4137 00:55:58.214717 6, 0xFFFF, sum = 0
4138 00:55:58.214828 7, 0xFFFF, sum = 0
4139 00:55:58.218132 8, 0x0, sum = 1
4140 00:55:58.218243 9, 0x0, sum = 2
4141 00:55:58.218338 10, 0x0, sum = 3
4142 00:55:58.221285 11, 0x0, sum = 4
4143 00:55:58.221393 best_step = 9
4144 00:55:58.221486
4145 00:55:58.221574 ==
4146 00:55:58.224676 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 00:55:58.230952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 00:55:58.231068 ==
4149 00:55:58.231164 RX Vref Scan: 1
4150 00:55:58.231256
4151 00:55:58.234429 RX Vref 0 -> 0, step: 1
4152 00:55:58.234536
4153 00:55:58.237436 RX Delay -195 -> 252, step: 8
4154 00:55:58.237617
4155 00:55:58.240763 Set Vref, RX VrefLevel [Byte0]: 51
4156 00:55:58.244464 [Byte1]: 59
4157 00:55:58.244572
4158 00:55:58.247553 Final RX Vref Byte 0 = 51 to rank0
4159 00:55:58.250727 Final RX Vref Byte 1 = 59 to rank0
4160 00:55:58.254216 Final RX Vref Byte 0 = 51 to rank1
4161 00:55:58.257850 Final RX Vref Byte 1 = 59 to rank1==
4162 00:55:58.260925 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 00:55:58.263847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 00:55:58.267638 ==
4165 00:55:58.267747 DQS Delay:
4166 00:55:58.267842 DQS0 = 0, DQS1 = 0
4167 00:55:58.270518 DQM Delay:
4168 00:55:58.270624 DQM0 = 42, DQM1 = 32
4169 00:55:58.273900 DQ Delay:
4170 00:55:58.274008 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4171 00:55:58.277456 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4172 00:55:58.281453 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4173 00:55:58.284032 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4174 00:55:58.284141
4175 00:55:58.287131
4176 00:55:58.293557 [DQSOSCAuto] RK0, (LSB)MR18= 0x4941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4177 00:55:58.297008 CH0 RK0: MR19=808, MR18=4941
4178 00:55:58.303339 CH0_RK0: MR19=0x808, MR18=0x4941, DQSOSC=396, MR23=63, INC=167, DEC=111
4179 00:55:58.303500
4180 00:55:58.307293 ----->DramcWriteLeveling(PI) begin...
4181 00:55:58.307433 ==
4182 00:55:58.309834 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 00:55:58.313345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 00:55:58.313462 ==
4185 00:55:58.317438 Write leveling (Byte 0): 33 => 33
4186 00:55:58.320090 Write leveling (Byte 1): 32 => 32
4187 00:55:58.323206 DramcWriteLeveling(PI) end<-----
4188 00:55:58.323314
4189 00:55:58.323448 ==
4190 00:55:58.326713 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 00:55:58.330113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 00:55:58.330228 ==
4193 00:55:58.333380 [Gating] SW mode calibration
4194 00:55:58.339753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4195 00:55:58.346017 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4196 00:55:58.349300 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 00:55:58.355853 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 00:55:58.359119 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 00:55:58.362330 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
4200 00:55:58.369013 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (1 1) (0 0)
4201 00:55:58.372184 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 00:55:58.375750 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 00:55:58.383164 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 00:55:58.385725 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 00:55:58.388934 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 00:55:58.395903 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 00:55:58.398751 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4208 00:55:58.402118 0 10 16 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
4209 00:55:58.408565 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 00:55:58.411920 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 00:55:58.415260 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 00:55:58.422222 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 00:55:58.424744 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 00:55:58.428188 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 00:55:58.434849 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4216 00:55:58.438136 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4217 00:55:58.441242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 00:55:58.448011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 00:55:58.451223 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 00:55:58.454783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 00:55:58.461170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 00:55:58.464545 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 00:55:58.467547 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 00:55:58.474082 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 00:55:58.477741 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 00:55:58.480892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 00:55:58.487994 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 00:55:58.490612 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 00:55:58.494544 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 00:55:58.500876 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 00:55:58.503737 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4232 00:55:58.507129 Total UI for P1: 0, mck2ui 16
4233 00:55:58.510830 best dqsien dly found for B0: ( 0, 13, 10)
4234 00:55:58.513899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 00:55:58.516904 Total UI for P1: 0, mck2ui 16
4236 00:55:58.520172 best dqsien dly found for B1: ( 0, 13, 12)
4237 00:55:58.524128 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4238 00:55:58.530065 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4239 00:55:58.530192
4240 00:55:58.533412 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4241 00:55:58.537245 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4242 00:55:58.540242 [Gating] SW calibration Done
4243 00:55:58.540353 ==
4244 00:55:58.543566 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 00:55:58.546951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 00:55:58.547062 ==
4247 00:55:58.549786 RX Vref Scan: 0
4248 00:55:58.549894
4249 00:55:58.549987 RX Vref 0 -> 0, step: 1
4250 00:55:58.550079
4251 00:55:58.553346 RX Delay -230 -> 252, step: 16
4252 00:55:58.556323 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4253 00:55:58.563772 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4254 00:55:58.566437 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4255 00:55:58.569912 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4256 00:55:58.573030 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4257 00:55:58.579478 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4258 00:55:58.582970 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4259 00:55:58.585980 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4260 00:55:58.589561 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4261 00:55:58.596106 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4262 00:55:58.599383 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4263 00:55:58.603457 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4264 00:55:58.606086 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4265 00:55:58.612793 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4266 00:55:58.615996 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4267 00:55:58.619402 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4268 00:55:58.619535 ==
4269 00:55:58.622195 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 00:55:58.625897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 00:55:58.629264 ==
4272 00:55:58.629394 DQS Delay:
4273 00:55:58.629520 DQS0 = 0, DQS1 = 0
4274 00:55:58.632028 DQM Delay:
4275 00:55:58.632135 DQM0 = 41, DQM1 = 34
4276 00:55:58.635797 DQ Delay:
4277 00:55:58.635906 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4278 00:55:58.638830 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4279 00:55:58.642165 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4280 00:55:58.645689 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4281 00:55:58.648761
4282 00:55:58.648869
4283 00:55:58.648961 ==
4284 00:55:58.651971 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 00:55:58.655496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 00:55:58.655606 ==
4287 00:55:58.655699
4288 00:55:58.655789
4289 00:55:58.658653 TX Vref Scan disable
4290 00:55:58.658780 == TX Byte 0 ==
4291 00:55:58.665370 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4292 00:55:58.668306 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4293 00:55:58.668414 == TX Byte 1 ==
4294 00:55:58.675224 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4295 00:55:58.678269 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4296 00:55:58.678377 ==
4297 00:55:58.681904 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 00:55:58.684911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 00:55:58.685017 ==
4300 00:55:58.685108
4301 00:55:58.688059
4302 00:55:58.688161 TX Vref Scan disable
4303 00:55:58.691539 == TX Byte 0 ==
4304 00:55:58.694941 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4305 00:55:58.701598 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4306 00:55:58.701709 == TX Byte 1 ==
4307 00:55:58.704741 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4308 00:55:58.711410 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4309 00:55:58.711595
4310 00:55:58.711706 [DATLAT]
4311 00:55:58.711808 Freq=600, CH0 RK1
4312 00:55:58.711892
4313 00:55:58.715083 DATLAT Default: 0x9
4314 00:55:58.718146 0, 0xFFFF, sum = 0
4315 00:55:58.718255 1, 0xFFFF, sum = 0
4316 00:55:58.721174 2, 0xFFFF, sum = 0
4317 00:55:58.721277 3, 0xFFFF, sum = 0
4318 00:55:58.724527 4, 0xFFFF, sum = 0
4319 00:55:58.724630 5, 0xFFFF, sum = 0
4320 00:55:58.727730 6, 0xFFFF, sum = 0
4321 00:55:58.727832 7, 0xFFFF, sum = 0
4322 00:55:58.730786 8, 0x0, sum = 1
4323 00:55:58.730892 9, 0x0, sum = 2
4324 00:55:58.734134 10, 0x0, sum = 3
4325 00:55:58.734241 11, 0x0, sum = 4
4326 00:55:58.734335 best_step = 9
4327 00:55:58.734424
4328 00:55:58.737715 ==
4329 00:55:58.740746 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 00:55:58.744418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 00:55:58.744526 ==
4332 00:55:58.744619 RX Vref Scan: 0
4333 00:55:58.744709
4334 00:55:58.747322 RX Vref 0 -> 0, step: 1
4335 00:55:58.747467
4336 00:55:58.751256 RX Delay -195 -> 252, step: 8
4337 00:55:58.757447 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4338 00:55:58.760925 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4339 00:55:58.764063 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4340 00:55:58.767235 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4341 00:55:58.774005 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4342 00:55:58.776868 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4343 00:55:58.780178 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4344 00:55:58.783650 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4345 00:55:58.786647 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4346 00:55:58.793379 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4347 00:55:58.797353 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4348 00:55:58.799888 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4349 00:55:58.803397 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4350 00:55:58.810078 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4351 00:55:58.812847 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4352 00:55:58.816456 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4353 00:55:58.816563 ==
4354 00:55:58.819735 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 00:55:58.826707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 00:55:58.826821 ==
4357 00:55:58.826913 DQS Delay:
4358 00:55:58.829710 DQS0 = 0, DQS1 = 0
4359 00:55:58.829816 DQM Delay:
4360 00:55:58.829906 DQM0 = 40, DQM1 = 33
4361 00:55:58.833150 DQ Delay:
4362 00:55:58.836162 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4363 00:55:58.839512 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4364 00:55:58.842970 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4365 00:55:58.845930 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4366 00:55:58.846035
4367 00:55:58.846126
4368 00:55:58.852816 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4369 00:55:58.855768 CH0 RK1: MR19=808, MR18=3D38
4370 00:55:58.862472 CH0_RK1: MR19=0x808, MR18=0x3D38, DQSOSC=398, MR23=63, INC=165, DEC=110
4371 00:55:58.865582 [RxdqsGatingPostProcess] freq 600
4372 00:55:58.872100 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 00:55:58.872219 Pre-setting of DQS Precalculation
4374 00:55:58.878853 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 00:55:58.878968 ==
4376 00:55:58.882003 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 00:55:58.885915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 00:55:58.886020 ==
4379 00:55:58.891900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 00:55:58.898677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 00:55:58.901937 [CA 0] Center 36 (6~66) winsize 61
4382 00:55:58.905590 [CA 1] Center 35 (5~66) winsize 62
4383 00:55:58.908343 [CA 2] Center 34 (4~65) winsize 62
4384 00:55:58.911524 [CA 3] Center 34 (3~65) winsize 63
4385 00:55:58.915182 [CA 4] Center 34 (4~65) winsize 62
4386 00:55:58.920017 [CA 5] Center 34 (3~65) winsize 63
4387 00:55:58.920126
4388 00:55:58.921495 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 00:55:58.921599
4390 00:55:58.925193 [CATrainingPosCal] consider 1 rank data
4391 00:55:58.928454 u2DelayCellTimex100 = 270/100 ps
4392 00:55:58.931289 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4393 00:55:58.934891 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4394 00:55:58.938083 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 00:55:58.941457 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4396 00:55:58.945173 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 00:55:58.951464 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4398 00:55:58.951581
4399 00:55:58.955123 CA PerBit enable=1, Macro0, CA PI delay=34
4400 00:55:58.955229
4401 00:55:58.957827 [CBTSetCACLKResult] CA Dly = 34
4402 00:55:58.957935 CS Dly: 3 (0~34)
4403 00:55:58.958028 ==
4404 00:55:58.961070 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 00:55:58.964204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 00:55:58.967913 ==
4407 00:55:58.971117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 00:55:58.977652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4409 00:55:58.980686 [CA 0] Center 36 (6~66) winsize 61
4410 00:55:58.984258 [CA 1] Center 35 (5~66) winsize 62
4411 00:55:58.987324 [CA 2] Center 34 (4~65) winsize 62
4412 00:55:58.991015 [CA 3] Center 34 (3~65) winsize 63
4413 00:55:58.993797 [CA 4] Center 34 (4~65) winsize 62
4414 00:55:58.997063 [CA 5] Center 33 (3~64) winsize 62
4415 00:55:58.997166
4416 00:55:59.000375 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4417 00:55:59.000453
4418 00:55:59.003557 [CATrainingPosCal] consider 2 rank data
4419 00:55:59.007256 u2DelayCellTimex100 = 270/100 ps
4420 00:55:59.010371 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4421 00:55:59.017273 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 00:55:59.020611 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 00:55:59.023878 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4424 00:55:59.026796 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 00:55:59.030053 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 00:55:59.030152
4427 00:55:59.033722 CA PerBit enable=1, Macro0, CA PI delay=33
4428 00:55:59.033805
4429 00:55:59.036781 [CBTSetCACLKResult] CA Dly = 33
4430 00:55:59.039988 CS Dly: 4 (0~36)
4431 00:55:59.040060
4432 00:55:59.043139 ----->DramcWriteLeveling(PI) begin...
4433 00:55:59.043237 ==
4434 00:55:59.046563 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 00:55:59.049873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 00:55:59.049985 ==
4437 00:55:59.053232 Write leveling (Byte 0): 29 => 29
4438 00:55:59.056477 Write leveling (Byte 1): 29 => 29
4439 00:55:59.059749 DramcWriteLeveling(PI) end<-----
4440 00:55:59.059854
4441 00:55:59.059942 ==
4442 00:55:59.063027 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 00:55:59.065997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 00:55:59.066100 ==
4445 00:55:59.069618 [Gating] SW mode calibration
4446 00:55:59.076267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 00:55:59.082507 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 00:55:59.085988 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 00:55:59.089224 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 00:55:59.095780 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 00:55:59.100408 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4452 00:55:59.102714 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 00:55:59.108928 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 00:55:59.112445 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 00:55:59.115740 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 00:55:59.123212 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 00:55:59.125230 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 00:55:59.128779 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 00:55:59.135248 0 10 12 | B1->B0 | 3131 3737 | 0 1 | (0 0) (0 0)
4460 00:55:59.138473 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 00:55:59.142363 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 00:55:59.148365 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 00:55:59.151936 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 00:55:59.154853 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 00:55:59.161551 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 00:55:59.165062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 00:55:59.168632 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4468 00:55:59.174767 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 00:55:59.178369 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 00:55:59.181821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 00:55:59.187954 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 00:55:59.191625 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 00:55:59.195348 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 00:55:59.201374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 00:55:59.204531 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 00:55:59.207777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 00:55:59.215003 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 00:55:59.218169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 00:55:59.221021 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 00:55:59.227318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 00:55:59.230760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:55:59.237376 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 00:55:59.241017 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 00:55:59.243831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 00:55:59.247543 Total UI for P1: 0, mck2ui 16
4486 00:55:59.250795 best dqsien dly found for B0: ( 0, 13, 14)
4487 00:55:59.254137 Total UI for P1: 0, mck2ui 16
4488 00:55:59.257163 best dqsien dly found for B1: ( 0, 13, 14)
4489 00:55:59.260828 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4490 00:55:59.263932 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4491 00:55:59.264070
4492 00:55:59.267483 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4493 00:55:59.273618 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4494 00:55:59.273743 [Gating] SW calibration Done
4495 00:55:59.277011 ==
4496 00:55:59.280094 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 00:55:59.283534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 00:55:59.283614 ==
4499 00:55:59.283678 RX Vref Scan: 0
4500 00:55:59.283740
4501 00:55:59.287338 RX Vref 0 -> 0, step: 1
4502 00:55:59.287457
4503 00:55:59.290637 RX Delay -230 -> 252, step: 16
4504 00:55:59.293392 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4505 00:55:59.296416 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4506 00:55:59.302977 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4507 00:55:59.306974 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4508 00:55:59.309813 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4509 00:55:59.312761 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4510 00:55:59.319534 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4511 00:55:59.322867 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4512 00:55:59.326369 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4513 00:55:59.329509 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4514 00:55:59.335802 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4515 00:55:59.339175 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4516 00:55:59.342409 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4517 00:55:59.346025 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4518 00:55:59.352397 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4519 00:55:59.355729 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4520 00:55:59.355811 ==
4521 00:55:59.359285 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 00:55:59.362653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 00:55:59.362753 ==
4524 00:55:59.365755 DQS Delay:
4525 00:55:59.365853 DQS0 = 0, DQS1 = 0
4526 00:55:59.365946 DQM Delay:
4527 00:55:59.368885 DQM0 = 44, DQM1 = 39
4528 00:55:59.368956 DQ Delay:
4529 00:55:59.372154 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4530 00:55:59.375769 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4531 00:55:59.378839 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4532 00:55:59.382027 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4533 00:55:59.382133
4534 00:55:59.382223
4535 00:55:59.382309 ==
4536 00:55:59.385487 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 00:55:59.392172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 00:55:59.392285 ==
4539 00:55:59.392376
4540 00:55:59.392463
4541 00:55:59.392557 TX Vref Scan disable
4542 00:55:59.396107 == TX Byte 0 ==
4543 00:55:59.398824 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4544 00:55:59.405491 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4545 00:55:59.405591 == TX Byte 1 ==
4546 00:55:59.409136 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 00:55:59.415347 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 00:55:59.415482 ==
4549 00:55:59.419068 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 00:55:59.422263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 00:55:59.422372 ==
4552 00:55:59.422473
4553 00:55:59.422564
4554 00:55:59.425834 TX Vref Scan disable
4555 00:55:59.428566 == TX Byte 0 ==
4556 00:55:59.431978 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 00:55:59.435315 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 00:55:59.438495 == TX Byte 1 ==
4559 00:55:59.441883 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4560 00:55:59.444904 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4561 00:55:59.444979
4562 00:55:59.445040 [DATLAT]
4563 00:55:59.448480 Freq=600, CH1 RK0
4564 00:55:59.448553
4565 00:55:59.452107 DATLAT Default: 0x9
4566 00:55:59.452188 0, 0xFFFF, sum = 0
4567 00:55:59.454967 1, 0xFFFF, sum = 0
4568 00:55:59.455043 2, 0xFFFF, sum = 0
4569 00:55:59.458610 3, 0xFFFF, sum = 0
4570 00:55:59.458682 4, 0xFFFF, sum = 0
4571 00:55:59.462673 5, 0xFFFF, sum = 0
4572 00:55:59.462746 6, 0xFFFF, sum = 0
4573 00:55:59.465133 7, 0xFFFF, sum = 0
4574 00:55:59.465206 8, 0x0, sum = 1
4575 00:55:59.468270 9, 0x0, sum = 2
4576 00:55:59.468342 10, 0x0, sum = 3
4577 00:55:59.471398 11, 0x0, sum = 4
4578 00:55:59.471481 best_step = 9
4579 00:55:59.471541
4580 00:55:59.471635 ==
4581 00:55:59.474734 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 00:55:59.478063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 00:55:59.478171 ==
4584 00:55:59.481524 RX Vref Scan: 1
4585 00:55:59.481611
4586 00:55:59.484567 RX Vref 0 -> 0, step: 1
4587 00:55:59.484639
4588 00:55:59.488602 RX Delay -179 -> 252, step: 8
4589 00:55:59.488700
4590 00:55:59.491517 Set Vref, RX VrefLevel [Byte0]: 51
4591 00:55:59.491589 [Byte1]: 52
4592 00:55:59.496363
4593 00:55:59.496470 Final RX Vref Byte 0 = 51 to rank0
4594 00:55:59.499707 Final RX Vref Byte 1 = 52 to rank0
4595 00:55:59.502800 Final RX Vref Byte 0 = 51 to rank1
4596 00:55:59.506794 Final RX Vref Byte 1 = 52 to rank1==
4597 00:55:59.509462 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 00:55:59.516056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 00:55:59.516154 ==
4600 00:55:59.516220 DQS Delay:
4601 00:55:59.519492 DQS0 = 0, DQS1 = 0
4602 00:55:59.519565 DQM Delay:
4603 00:55:59.519627 DQM0 = 42, DQM1 = 34
4604 00:55:59.523019 DQ Delay:
4605 00:55:59.525892 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4606 00:55:59.529707 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4607 00:55:59.532343 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4608 00:55:59.535534 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4609 00:55:59.535607
4610 00:55:59.535669
4611 00:55:59.542212 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4612 00:55:59.545544 CH1 RK0: MR19=808, MR18=2F49
4613 00:55:59.552588 CH1_RK0: MR19=0x808, MR18=0x2F49, DQSOSC=396, MR23=63, INC=167, DEC=111
4614 00:55:59.552675
4615 00:55:59.555822 ----->DramcWriteLeveling(PI) begin...
4616 00:55:59.555908 ==
4617 00:55:59.558673 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 00:55:59.562043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 00:55:59.562140 ==
4620 00:55:59.565413 Write leveling (Byte 0): 31 => 31
4621 00:55:59.568445 Write leveling (Byte 1): 28 => 28
4622 00:55:59.572309 DramcWriteLeveling(PI) end<-----
4623 00:55:59.572408
4624 00:55:59.572470 ==
4625 00:55:59.575979 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 00:55:59.581769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 00:55:59.581884 ==
4628 00:55:59.581980 [Gating] SW mode calibration
4629 00:55:59.591671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4630 00:55:59.594853 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4631 00:55:59.598310 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 00:55:59.605140 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 00:55:59.607926 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4634 00:55:59.611389 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (0 0) (0 0)
4635 00:55:59.618649 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 00:55:59.621071 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 00:55:59.624486 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 00:55:59.631192 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 00:55:59.634243 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 00:55:59.637584 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 00:55:59.644833 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4642 00:55:59.647979 0 10 12 | B1->B0 | 3434 3d3d | 0 0 | (0 0) (1 1)
4643 00:55:59.650718 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4644 00:55:59.657137 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 00:55:59.660597 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 00:55:59.667402 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 00:55:59.670862 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 00:55:59.673953 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 00:55:59.680222 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 00:55:59.683889 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4651 00:55:59.687232 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 00:55:59.693717 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 00:55:59.696956 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 00:55:59.700380 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 00:55:59.706821 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 00:55:59.709840 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 00:55:59.713427 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 00:55:59.720270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 00:55:59.723345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 00:55:59.726313 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 00:55:59.729825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 00:55:59.736804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 00:55:59.739673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 00:55:59.743313 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 00:55:59.749489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4666 00:55:59.752849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4667 00:55:59.756080 Total UI for P1: 0, mck2ui 16
4668 00:55:59.759336 best dqsien dly found for B0: ( 0, 13, 8)
4669 00:55:59.763058 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 00:55:59.766002 Total UI for P1: 0, mck2ui 16
4671 00:55:59.769719 best dqsien dly found for B1: ( 0, 13, 12)
4672 00:55:59.775731 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4673 00:55:59.779593 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4674 00:55:59.779679
4675 00:55:59.782165 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4676 00:55:59.785590 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4677 00:55:59.789160 [Gating] SW calibration Done
4678 00:55:59.789243 ==
4679 00:55:59.792113 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 00:55:59.795527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 00:55:59.795610 ==
4682 00:55:59.798983 RX Vref Scan: 0
4683 00:55:59.799065
4684 00:55:59.799130 RX Vref 0 -> 0, step: 1
4685 00:55:59.799191
4686 00:55:59.802381 RX Delay -230 -> 252, step: 16
4687 00:55:59.805609 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4688 00:55:59.812527 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4689 00:55:59.815770 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4690 00:55:59.818807 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4691 00:55:59.821826 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4692 00:55:59.829082 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4693 00:55:59.831554 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4694 00:55:59.834887 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4695 00:55:59.838426 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4696 00:55:59.844830 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4697 00:55:59.848105 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4698 00:55:59.851644 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4699 00:55:59.854983 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4700 00:55:59.861770 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4701 00:55:59.864609 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4702 00:55:59.868186 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4703 00:55:59.868271 ==
4704 00:55:59.871490 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 00:55:59.874737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 00:55:59.877920 ==
4707 00:55:59.878002 DQS Delay:
4708 00:55:59.878068 DQS0 = 0, DQS1 = 0
4709 00:55:59.881517 DQM Delay:
4710 00:55:59.881598 DQM0 = 42, DQM1 = 38
4711 00:55:59.884483 DQ Delay:
4712 00:55:59.884565 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4713 00:55:59.887931 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4714 00:55:59.891106 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4715 00:55:59.894320 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4716 00:55:59.897931
4717 00:55:59.898013
4718 00:55:59.898078 ==
4719 00:55:59.900686 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 00:55:59.904428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 00:55:59.904511 ==
4722 00:55:59.904576
4723 00:55:59.904636
4724 00:55:59.907508 TX Vref Scan disable
4725 00:55:59.907589 == TX Byte 0 ==
4726 00:55:59.913971 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4727 00:55:59.917277 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4728 00:55:59.917360 == TX Byte 1 ==
4729 00:55:59.923810 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4730 00:55:59.927268 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4731 00:55:59.927415 ==
4732 00:55:59.930574 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 00:55:59.933552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 00:55:59.933657 ==
4735 00:55:59.936836
4736 00:55:59.936906
4737 00:55:59.936966 TX Vref Scan disable
4738 00:55:59.940659 == TX Byte 0 ==
4739 00:55:59.943822 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 00:55:59.950361 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 00:55:59.950464 == TX Byte 1 ==
4742 00:55:59.954534 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4743 00:55:59.960594 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4744 00:55:59.960671
4745 00:55:59.960742 [DATLAT]
4746 00:55:59.960803 Freq=600, CH1 RK1
4747 00:55:59.960861
4748 00:55:59.964038 DATLAT Default: 0x9
4749 00:55:59.967275 0, 0xFFFF, sum = 0
4750 00:55:59.967359 1, 0xFFFF, sum = 0
4751 00:55:59.970013 2, 0xFFFF, sum = 0
4752 00:55:59.970110 3, 0xFFFF, sum = 0
4753 00:55:59.973453 4, 0xFFFF, sum = 0
4754 00:55:59.973526 5, 0xFFFF, sum = 0
4755 00:55:59.976768 6, 0xFFFF, sum = 0
4756 00:55:59.976866 7, 0xFFFF, sum = 0
4757 00:55:59.980635 8, 0x0, sum = 1
4758 00:55:59.980805 9, 0x0, sum = 2
4759 00:55:59.983403 10, 0x0, sum = 3
4760 00:55:59.983485 11, 0x0, sum = 4
4761 00:55:59.983550 best_step = 9
4762 00:55:59.983611
4763 00:55:59.986503 ==
4764 00:55:59.989914 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 00:55:59.993418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 00:55:59.993500 ==
4767 00:55:59.993564 RX Vref Scan: 0
4768 00:55:59.993624
4769 00:55:59.996406 RX Vref 0 -> 0, step: 1
4770 00:55:59.996487
4771 00:55:59.999698 RX Delay -179 -> 252, step: 8
4772 00:56:00.006478 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4773 00:56:00.009444 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4774 00:56:00.012878 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4775 00:56:00.016185 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4776 00:56:00.022843 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4777 00:56:00.026602 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4778 00:56:00.029827 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4779 00:56:00.032576 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4780 00:56:00.036265 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4781 00:56:00.042514 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4782 00:56:00.046014 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4783 00:56:00.049357 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4784 00:56:00.053144 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4785 00:56:00.058921 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4786 00:56:00.062634 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4787 00:56:00.065611 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4788 00:56:00.065693 ==
4789 00:56:00.069134 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 00:56:00.075603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 00:56:00.075688 ==
4792 00:56:00.075754 DQS Delay:
4793 00:56:00.075814 DQS0 = 0, DQS1 = 0
4794 00:56:00.078756 DQM Delay:
4795 00:56:00.078836 DQM0 = 37, DQM1 = 35
4796 00:56:00.082397 DQ Delay:
4797 00:56:00.085807 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4798 00:56:00.088611 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4799 00:56:00.091709 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4800 00:56:00.095347 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4801 00:56:00.095468
4802 00:56:00.095533
4803 00:56:00.101495 [DQSOSCAuto] RK1, (LSB)MR18= 0x3055, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4804 00:56:00.104922 CH1 RK1: MR19=808, MR18=3055
4805 00:56:00.111816 CH1_RK1: MR19=0x808, MR18=0x3055, DQSOSC=393, MR23=63, INC=169, DEC=113
4806 00:56:00.114835 [RxdqsGatingPostProcess] freq 600
4807 00:56:00.121525 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 00:56:00.121608 Pre-setting of DQS Precalculation
4809 00:56:00.128353 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 00:56:00.134528 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 00:56:00.141638 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 00:56:00.141720
4813 00:56:00.141784
4814 00:56:00.145001 [Calibration Summary] 1200 Mbps
4815 00:56:00.147534 CH 0, Rank 0
4816 00:56:00.147615 SW Impedance : PASS
4817 00:56:00.151028 DUTY Scan : NO K
4818 00:56:00.154246 ZQ Calibration : PASS
4819 00:56:00.154327 Jitter Meter : NO K
4820 00:56:00.157659 CBT Training : PASS
4821 00:56:00.157740 Write leveling : PASS
4822 00:56:00.161547 RX DQS gating : PASS
4823 00:56:00.164096 RX DQ/DQS(RDDQC) : PASS
4824 00:56:00.164177 TX DQ/DQS : PASS
4825 00:56:00.167380 RX DATLAT : PASS
4826 00:56:00.170846 RX DQ/DQS(Engine): PASS
4827 00:56:00.170927 TX OE : NO K
4828 00:56:00.174233 All Pass.
4829 00:56:00.174313
4830 00:56:00.174377 CH 0, Rank 1
4831 00:56:00.177479 SW Impedance : PASS
4832 00:56:00.177560 DUTY Scan : NO K
4833 00:56:00.180803 ZQ Calibration : PASS
4834 00:56:00.184142 Jitter Meter : NO K
4835 00:56:00.184223 CBT Training : PASS
4836 00:56:00.187345 Write leveling : PASS
4837 00:56:00.190565 RX DQS gating : PASS
4838 00:56:00.190646 RX DQ/DQS(RDDQC) : PASS
4839 00:56:00.193797 TX DQ/DQS : PASS
4840 00:56:00.197391 RX DATLAT : PASS
4841 00:56:00.197472 RX DQ/DQS(Engine): PASS
4842 00:56:00.200829 TX OE : NO K
4843 00:56:00.200911 All Pass.
4844 00:56:00.200975
4845 00:56:00.204418 CH 1, Rank 0
4846 00:56:00.204500 SW Impedance : PASS
4847 00:56:00.207319 DUTY Scan : NO K
4848 00:56:00.210517 ZQ Calibration : PASS
4849 00:56:00.210598 Jitter Meter : NO K
4850 00:56:00.213464 CBT Training : PASS
4851 00:56:00.217057 Write leveling : PASS
4852 00:56:00.217139 RX DQS gating : PASS
4853 00:56:00.220159 RX DQ/DQS(RDDQC) : PASS
4854 00:56:00.223407 TX DQ/DQS : PASS
4855 00:56:00.223489 RX DATLAT : PASS
4856 00:56:00.226569 RX DQ/DQS(Engine): PASS
4857 00:56:00.230184 TX OE : NO K
4858 00:56:00.230265 All Pass.
4859 00:56:00.230330
4860 00:56:00.230390 CH 1, Rank 1
4861 00:56:00.233208 SW Impedance : PASS
4862 00:56:00.236602 DUTY Scan : NO K
4863 00:56:00.236685 ZQ Calibration : PASS
4864 00:56:00.239897 Jitter Meter : NO K
4865 00:56:00.239980 CBT Training : PASS
4866 00:56:00.243871 Write leveling : PASS
4867 00:56:00.246634 RX DQS gating : PASS
4868 00:56:00.246715 RX DQ/DQS(RDDQC) : PASS
4869 00:56:00.249919 TX DQ/DQS : PASS
4870 00:56:00.253095 RX DATLAT : PASS
4871 00:56:00.253190 RX DQ/DQS(Engine): PASS
4872 00:56:00.256293 TX OE : NO K
4873 00:56:00.256375 All Pass.
4874 00:56:00.256439
4875 00:56:00.260164 DramC Write-DBI off
4876 00:56:00.262919 PER_BANK_REFRESH: Hybrid Mode
4877 00:56:00.263000 TX_TRACKING: ON
4878 00:56:00.273040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 00:56:00.275915 [FAST_K] Save calibration result to emmc
4880 00:56:00.279407 dramc_set_vcore_voltage set vcore to 662500
4881 00:56:00.282602 Read voltage for 933, 3
4882 00:56:00.282683 Vio18 = 0
4883 00:56:00.286065 Vcore = 662500
4884 00:56:00.286145 Vdram = 0
4885 00:56:00.286209 Vddq = 0
4886 00:56:00.286269 Vmddr = 0
4887 00:56:00.292890 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 00:56:00.299871 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 00:56:00.299959 MEM_TYPE=3, freq_sel=17
4890 00:56:00.302594 sv_algorithm_assistance_LP4_1600
4891 00:56:00.305786 ============ PULL DRAM RESETB DOWN ============
4892 00:56:00.312398 ========== PULL DRAM RESETB DOWN end =========
4893 00:56:00.315652 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 00:56:00.318986 ===================================
4895 00:56:00.322415 LPDDR4 DRAM CONFIGURATION
4896 00:56:00.325679 ===================================
4897 00:56:00.325768 EX_ROW_EN[0] = 0x0
4898 00:56:00.329101 EX_ROW_EN[1] = 0x0
4899 00:56:00.329186 LP4Y_EN = 0x0
4900 00:56:00.332554 WORK_FSP = 0x0
4901 00:56:00.332645 WL = 0x3
4902 00:56:00.335352 RL = 0x3
4903 00:56:00.339042 BL = 0x2
4904 00:56:00.339129 RPST = 0x0
4905 00:56:00.342718 RD_PRE = 0x0
4906 00:56:00.342828 WR_PRE = 0x1
4907 00:56:00.345915 WR_PST = 0x0
4908 00:56:00.345999 DBI_WR = 0x0
4909 00:56:00.348712 DBI_RD = 0x0
4910 00:56:00.348820 OTF = 0x1
4911 00:56:00.352130 ===================================
4912 00:56:00.355331 ===================================
4913 00:56:00.358626 ANA top config
4914 00:56:00.362352 ===================================
4915 00:56:00.362511 DLL_ASYNC_EN = 0
4916 00:56:00.365396 ALL_SLAVE_EN = 1
4917 00:56:00.368568 NEW_RANK_MODE = 1
4918 00:56:00.372392 DLL_IDLE_MODE = 1
4919 00:56:00.372488 LP45_APHY_COMB_EN = 1
4920 00:56:00.375621 TX_ODT_DIS = 1
4921 00:56:00.379038 NEW_8X_MODE = 1
4922 00:56:00.382158 ===================================
4923 00:56:00.385556 ===================================
4924 00:56:00.388857 data_rate = 1866
4925 00:56:00.392107 CKR = 1
4926 00:56:00.395293 DQ_P2S_RATIO = 8
4927 00:56:00.398199 ===================================
4928 00:56:00.398293 CA_P2S_RATIO = 8
4929 00:56:00.401878 DQ_CA_OPEN = 0
4930 00:56:00.405122 DQ_SEMI_OPEN = 0
4931 00:56:00.408342 CA_SEMI_OPEN = 0
4932 00:56:00.411357 CA_FULL_RATE = 0
4933 00:56:00.414839 DQ_CKDIV4_EN = 1
4934 00:56:00.415009 CA_CKDIV4_EN = 1
4935 00:56:00.418120 CA_PREDIV_EN = 0
4936 00:56:00.421495 PH8_DLY = 0
4937 00:56:00.424633 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 00:56:00.428382 DQ_AAMCK_DIV = 4
4939 00:56:00.431565 CA_AAMCK_DIV = 4
4940 00:56:00.434726 CA_ADMCK_DIV = 4
4941 00:56:00.434864 DQ_TRACK_CA_EN = 0
4942 00:56:00.437949 CA_PICK = 933
4943 00:56:00.441634 CA_MCKIO = 933
4944 00:56:00.444548 MCKIO_SEMI = 0
4945 00:56:00.448089 PLL_FREQ = 3732
4946 00:56:00.450808 DQ_UI_PI_RATIO = 32
4947 00:56:00.454451 CA_UI_PI_RATIO = 0
4948 00:56:00.457794 ===================================
4949 00:56:00.461012 ===================================
4950 00:56:00.461155 memory_type:LPDDR4
4951 00:56:00.464366 GP_NUM : 10
4952 00:56:00.468183 SRAM_EN : 1
4953 00:56:00.468319 MD32_EN : 0
4954 00:56:00.470972 ===================================
4955 00:56:00.474372 [ANA_INIT] >>>>>>>>>>>>>>
4956 00:56:00.477470 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 00:56:00.480578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 00:56:00.483964 ===================================
4959 00:56:00.487080 data_rate = 1866,PCW = 0X8f00
4960 00:56:00.490794 ===================================
4961 00:56:00.493653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 00:56:00.497242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 00:56:00.503384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 00:56:00.506589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 00:56:00.513160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 00:56:00.516651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 00:56:00.516740 [ANA_INIT] flow start
4968 00:56:00.520062 [ANA_INIT] PLL >>>>>>>>
4969 00:56:00.523250 [ANA_INIT] PLL <<<<<<<<
4970 00:56:00.523332 [ANA_INIT] MIDPI >>>>>>>>
4971 00:56:00.526233 [ANA_INIT] MIDPI <<<<<<<<
4972 00:56:00.529776 [ANA_INIT] DLL >>>>>>>>
4973 00:56:00.529884 [ANA_INIT] flow end
4974 00:56:00.537115 ============ LP4 DIFF to SE enter ============
4975 00:56:00.539964 ============ LP4 DIFF to SE exit ============
4976 00:56:00.540065 [ANA_INIT] <<<<<<<<<<<<<
4977 00:56:00.543291 [Flow] Enable top DCM control >>>>>
4978 00:56:00.547039 [Flow] Enable top DCM control <<<<<
4979 00:56:00.549443 Enable DLL master slave shuffle
4980 00:56:00.556401 ==============================================================
4981 00:56:00.559149 Gating Mode config
4982 00:56:00.562686 ==============================================================
4983 00:56:00.566191 Config description:
4984 00:56:00.576285 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 00:56:00.582410 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 00:56:00.585864 SELPH_MODE 0: By rank 1: By Phase
4987 00:56:00.592431 ==============================================================
4988 00:56:00.595901 GAT_TRACK_EN = 1
4989 00:56:00.598910 RX_GATING_MODE = 2
4990 00:56:00.602360 RX_GATING_TRACK_MODE = 2
4991 00:56:00.605706 SELPH_MODE = 1
4992 00:56:00.605830 PICG_EARLY_EN = 1
4993 00:56:00.608866 VALID_LAT_VALUE = 1
4994 00:56:00.615683 ==============================================================
4995 00:56:00.619087 Enter into Gating configuration >>>>
4996 00:56:00.622193 Exit from Gating configuration <<<<
4997 00:56:00.625367 Enter into DVFS_PRE_config >>>>>
4998 00:56:00.635545 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 00:56:00.638548 Exit from DVFS_PRE_config <<<<<
5000 00:56:00.641819 Enter into PICG configuration >>>>
5001 00:56:00.645054 Exit from PICG configuration <<<<
5002 00:56:00.648359 [RX_INPUT] configuration >>>>>
5003 00:56:00.651584 [RX_INPUT] configuration <<<<<
5004 00:56:00.658645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 00:56:00.661648 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 00:56:00.668474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 00:56:00.675142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 00:56:00.681445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 00:56:00.688227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 00:56:00.691450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 00:56:00.694576 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 00:56:00.698131 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 00:56:00.704922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 00:56:00.707901 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 00:56:00.710916 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 00:56:00.714113 ===================================
5017 00:56:00.717346 LPDDR4 DRAM CONFIGURATION
5018 00:56:00.720886 ===================================
5019 00:56:00.724171 EX_ROW_EN[0] = 0x0
5020 00:56:00.724283 EX_ROW_EN[1] = 0x0
5021 00:56:00.727463 LP4Y_EN = 0x0
5022 00:56:00.727541 WORK_FSP = 0x0
5023 00:56:00.731020 WL = 0x3
5024 00:56:00.731119 RL = 0x3
5025 00:56:00.733819 BL = 0x2
5026 00:56:00.733936 RPST = 0x0
5027 00:56:00.737959 RD_PRE = 0x0
5028 00:56:00.738059 WR_PRE = 0x1
5029 00:56:00.740631 WR_PST = 0x0
5030 00:56:00.740732 DBI_WR = 0x0
5031 00:56:00.744106 DBI_RD = 0x0
5032 00:56:00.744187 OTF = 0x1
5033 00:56:00.747055 ===================================
5034 00:56:00.753890 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 00:56:00.757210 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 00:56:00.760900 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 00:56:00.763945 ===================================
5038 00:56:00.766755 LPDDR4 DRAM CONFIGURATION
5039 00:56:00.770644 ===================================
5040 00:56:00.773579 EX_ROW_EN[0] = 0x10
5041 00:56:00.773654 EX_ROW_EN[1] = 0x0
5042 00:56:00.777354 LP4Y_EN = 0x0
5043 00:56:00.777421 WORK_FSP = 0x0
5044 00:56:00.780256 WL = 0x3
5045 00:56:00.780325 RL = 0x3
5046 00:56:00.783513 BL = 0x2
5047 00:56:00.783583 RPST = 0x0
5048 00:56:00.786401 RD_PRE = 0x0
5049 00:56:00.786495 WR_PRE = 0x1
5050 00:56:00.789832 WR_PST = 0x0
5051 00:56:00.789903 DBI_WR = 0x0
5052 00:56:00.793301 DBI_RD = 0x0
5053 00:56:00.793400 OTF = 0x1
5054 00:56:00.796806 ===================================
5055 00:56:00.803233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 00:56:00.808492 nWR fixed to 30
5057 00:56:00.811317 [ModeRegInit_LP4] CH0 RK0
5058 00:56:00.811526 [ModeRegInit_LP4] CH0 RK1
5059 00:56:00.814901 [ModeRegInit_LP4] CH1 RK0
5060 00:56:00.818036 [ModeRegInit_LP4] CH1 RK1
5061 00:56:00.818158 match AC timing 9
5062 00:56:00.824550 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 00:56:00.828198 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 00:56:00.831069 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 00:56:00.838016 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 00:56:00.840904 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 00:56:00.841013 ==
5068 00:56:00.844419 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 00:56:00.847712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 00:56:00.847835 ==
5071 00:56:00.854375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 00:56:00.860493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 00:56:00.863944 [CA 0] Center 37 (7~68) winsize 62
5074 00:56:00.867244 [CA 1] Center 37 (7~68) winsize 62
5075 00:56:00.870462 [CA 2] Center 34 (4~65) winsize 62
5076 00:56:00.873680 [CA 3] Center 34 (4~65) winsize 62
5077 00:56:00.877205 [CA 4] Center 33 (3~64) winsize 62
5078 00:56:00.880393 [CA 5] Center 32 (2~63) winsize 62
5079 00:56:00.880497
5080 00:56:00.883836 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 00:56:00.883983
5082 00:56:00.887360 [CATrainingPosCal] consider 1 rank data
5083 00:56:00.890337 u2DelayCellTimex100 = 270/100 ps
5084 00:56:00.893430 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5085 00:56:00.896854 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5086 00:56:00.900244 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5087 00:56:00.907097 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5088 00:56:00.910159 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5089 00:56:00.913598 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5090 00:56:00.913696
5091 00:56:00.916418 CA PerBit enable=1, Macro0, CA PI delay=32
5092 00:56:00.916518
5093 00:56:00.919736 [CBTSetCACLKResult] CA Dly = 32
5094 00:56:00.919809 CS Dly: 5 (0~36)
5095 00:56:00.919869 ==
5096 00:56:00.923468 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 00:56:00.930411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 00:56:00.930507 ==
5099 00:56:00.933458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 00:56:00.939886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5101 00:56:00.943404 [CA 0] Center 37 (7~68) winsize 62
5102 00:56:00.946663 [CA 1] Center 37 (7~68) winsize 62
5103 00:56:00.949619 [CA 2] Center 35 (5~65) winsize 61
5104 00:56:00.953105 [CA 3] Center 34 (4~65) winsize 62
5105 00:56:00.956420 [CA 4] Center 33 (3~64) winsize 62
5106 00:56:00.960185 [CA 5] Center 32 (2~63) winsize 62
5107 00:56:00.960255
5108 00:56:00.962878 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5109 00:56:00.962943
5110 00:56:00.966312 [CATrainingPosCal] consider 2 rank data
5111 00:56:00.969866 u2DelayCellTimex100 = 270/100 ps
5112 00:56:00.973301 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5113 00:56:00.979515 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5114 00:56:00.983024 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5115 00:56:00.986172 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5116 00:56:00.989233 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5117 00:56:00.992533 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5118 00:56:00.992651
5119 00:56:00.995948 CA PerBit enable=1, Macro0, CA PI delay=32
5120 00:56:00.996081
5121 00:56:00.999445 [CBTSetCACLKResult] CA Dly = 32
5122 00:56:01.002219 CS Dly: 6 (0~39)
5123 00:56:01.002356
5124 00:56:01.005526 ----->DramcWriteLeveling(PI) begin...
5125 00:56:01.005678 ==
5126 00:56:01.009060 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 00:56:01.012208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 00:56:01.012362 ==
5129 00:56:01.015561 Write leveling (Byte 0): 31 => 31
5130 00:56:01.018903 Write leveling (Byte 1): 26 => 26
5131 00:56:01.022316 DramcWriteLeveling(PI) end<-----
5132 00:56:01.022458
5133 00:56:01.022553 ==
5134 00:56:01.025331 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 00:56:01.028436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 00:56:01.028584 ==
5137 00:56:01.031827 [Gating] SW mode calibration
5138 00:56:01.038241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 00:56:01.045288 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 00:56:01.048260 0 14 0 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
5141 00:56:01.055082 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5142 00:56:01.058175 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 00:56:01.061572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 00:56:01.068051 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 00:56:01.071350 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 00:56:01.074305 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 00:56:01.081116 0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
5148 00:56:01.084746 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
5149 00:56:01.087787 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 00:56:01.094283 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 00:56:01.097275 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 00:56:01.100934 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 00:56:01.107467 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 00:56:01.110849 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5155 00:56:01.114139 0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
5156 00:56:01.120708 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5157 00:56:01.123764 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 00:56:01.127140 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 00:56:01.133532 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 00:56:01.137095 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 00:56:01.140584 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 00:56:01.146874 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5163 00:56:01.149945 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5164 00:56:01.153324 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5165 00:56:01.160159 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5166 00:56:01.163542 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 00:56:01.166546 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 00:56:01.173651 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 00:56:01.176518 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 00:56:01.179583 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 00:56:01.186437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 00:56:01.189846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 00:56:01.192682 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 00:56:01.199570 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 00:56:01.202451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 00:56:01.205902 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 00:56:01.212561 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 00:56:01.215966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 00:56:01.219244 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5180 00:56:01.225834 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5181 00:56:01.229687 Total UI for P1: 0, mck2ui 16
5182 00:56:01.232290 best dqsien dly found for B0: ( 1, 2, 28)
5183 00:56:01.235735 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5184 00:56:01.239127 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 00:56:01.242371 Total UI for P1: 0, mck2ui 16
5186 00:56:01.245328 best dqsien dly found for B1: ( 1, 3, 4)
5187 00:56:01.249136 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5188 00:56:01.255223 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5189 00:56:01.255325
5190 00:56:01.258395 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5191 00:56:01.262308 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5192 00:56:01.265746 [Gating] SW calibration Done
5193 00:56:01.265849 ==
5194 00:56:01.268409 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 00:56:01.271789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 00:56:01.271867 ==
5197 00:56:01.275388 RX Vref Scan: 0
5198 00:56:01.275474
5199 00:56:01.275561 RX Vref 0 -> 0, step: 1
5200 00:56:01.275642
5201 00:56:01.278188 RX Delay -80 -> 252, step: 8
5202 00:56:01.281785 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5203 00:56:01.285439 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5204 00:56:01.291621 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5205 00:56:01.295113 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5206 00:56:01.298251 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5207 00:56:01.301155 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5208 00:56:01.304756 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5209 00:56:01.311321 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5210 00:56:01.314468 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5211 00:56:01.317695 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5212 00:56:01.321166 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5213 00:56:01.324228 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5214 00:56:01.330975 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5215 00:56:01.334300 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5216 00:56:01.337825 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5217 00:56:01.340851 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5218 00:56:01.340974 ==
5219 00:56:01.343751 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 00:56:01.346890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 00:56:01.350752 ==
5222 00:56:01.350851 DQS Delay:
5223 00:56:01.350948 DQS0 = 0, DQS1 = 0
5224 00:56:01.353685 DQM Delay:
5225 00:56:01.353799 DQM0 = 100, DQM1 = 88
5226 00:56:01.357113 DQ Delay:
5227 00:56:01.360338 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5228 00:56:01.363658 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5229 00:56:01.367069 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5230 00:56:01.370003 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5231 00:56:01.370115
5232 00:56:01.370235
5233 00:56:01.370356 ==
5234 00:56:01.373357 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 00:56:01.377457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 00:56:01.377574 ==
5237 00:56:01.377677
5238 00:56:01.377763
5239 00:56:01.379863 TX Vref Scan disable
5240 00:56:01.379937 == TX Byte 0 ==
5241 00:56:01.386673 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5242 00:56:01.389899 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5243 00:56:01.389999 == TX Byte 1 ==
5244 00:56:01.396739 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5245 00:56:01.399637 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5246 00:56:01.399731 ==
5247 00:56:01.402903 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 00:56:01.406362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 00:56:01.406458 ==
5250 00:56:01.409873
5251 00:56:01.409967
5252 00:56:01.410056 TX Vref Scan disable
5253 00:56:01.413423 == TX Byte 0 ==
5254 00:56:01.416606 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5255 00:56:01.423293 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5256 00:56:01.423402 == TX Byte 1 ==
5257 00:56:01.426348 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5258 00:56:01.432710 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5259 00:56:01.432787
5260 00:56:01.432849 [DATLAT]
5261 00:56:01.432907 Freq=933, CH0 RK0
5262 00:56:01.432964
5263 00:56:01.435940 DATLAT Default: 0xd
5264 00:56:01.439263 0, 0xFFFF, sum = 0
5265 00:56:01.439333 1, 0xFFFF, sum = 0
5266 00:56:01.443005 2, 0xFFFF, sum = 0
5267 00:56:01.443074 3, 0xFFFF, sum = 0
5268 00:56:01.446160 4, 0xFFFF, sum = 0
5269 00:56:01.446235 5, 0xFFFF, sum = 0
5270 00:56:01.449164 6, 0xFFFF, sum = 0
5271 00:56:01.449233 7, 0xFFFF, sum = 0
5272 00:56:01.452963 8, 0xFFFF, sum = 0
5273 00:56:01.453037 9, 0xFFFF, sum = 0
5274 00:56:01.455690 10, 0x0, sum = 1
5275 00:56:01.455756 11, 0x0, sum = 2
5276 00:56:01.459509 12, 0x0, sum = 3
5277 00:56:01.459578 13, 0x0, sum = 4
5278 00:56:01.463226 best_step = 11
5279 00:56:01.463293
5280 00:56:01.463352 ==
5281 00:56:01.465618 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 00:56:01.469191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 00:56:01.469268 ==
5284 00:56:01.469338 RX Vref Scan: 1
5285 00:56:01.472349
5286 00:56:01.472420 RX Vref 0 -> 0, step: 1
5287 00:56:01.472480
5288 00:56:01.475625 RX Delay -61 -> 252, step: 4
5289 00:56:01.475695
5290 00:56:01.478827 Set Vref, RX VrefLevel [Byte0]: 51
5291 00:56:01.481949 [Byte1]: 59
5292 00:56:01.485546
5293 00:56:01.485625 Final RX Vref Byte 0 = 51 to rank0
5294 00:56:01.488898 Final RX Vref Byte 1 = 59 to rank0
5295 00:56:01.492470 Final RX Vref Byte 0 = 51 to rank1
5296 00:56:01.495672 Final RX Vref Byte 1 = 59 to rank1==
5297 00:56:01.498929 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 00:56:01.505581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 00:56:01.505681 ==
5300 00:56:01.505772 DQS Delay:
5301 00:56:01.508821 DQS0 = 0, DQS1 = 0
5302 00:56:01.508897 DQM Delay:
5303 00:56:01.508959 DQM0 = 99, DQM1 = 88
5304 00:56:01.512135 DQ Delay:
5305 00:56:01.515535 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5306 00:56:01.518996 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5307 00:56:01.521834 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5308 00:56:01.525736 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5309 00:56:01.525813
5310 00:56:01.525919
5311 00:56:01.531944 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5312 00:56:01.535443 CH0 RK0: MR19=505, MR18=1C16
5313 00:56:01.541821 CH0_RK0: MR19=0x505, MR18=0x1C16, DQSOSC=412, MR23=63, INC=63, DEC=42
5314 00:56:01.541898
5315 00:56:01.544682 ----->DramcWriteLeveling(PI) begin...
5316 00:56:01.544754 ==
5317 00:56:01.548204 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 00:56:01.551284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 00:56:01.555154 ==
5320 00:56:01.555256 Write leveling (Byte 0): 34 => 34
5321 00:56:01.558023 Write leveling (Byte 1): 28 => 28
5322 00:56:01.562007 DramcWriteLeveling(PI) end<-----
5323 00:56:01.562105
5324 00:56:01.562193 ==
5325 00:56:01.564688 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 00:56:01.571200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 00:56:01.571301 ==
5328 00:56:01.574217 [Gating] SW mode calibration
5329 00:56:01.580982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5330 00:56:01.584461 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5331 00:56:01.591262 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5332 00:56:01.594104 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 00:56:01.597301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 00:56:01.604022 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 00:56:01.607323 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 00:56:01.610417 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 00:56:01.617227 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5338 00:56:01.620687 0 14 28 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (0 0)
5339 00:56:01.624152 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5340 00:56:01.630669 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5341 00:56:01.633517 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 00:56:01.637104 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 00:56:01.643572 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 00:56:01.647012 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 00:56:01.649883 0 15 24 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
5346 00:56:01.656842 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
5347 00:56:01.659897 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5348 00:56:01.663727 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 00:56:01.670038 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 00:56:01.673622 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 00:56:01.676583 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 00:56:01.683017 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 00:56:01.686700 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 00:56:01.689704 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5355 00:56:01.696700 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5356 00:56:01.699577 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 00:56:01.702847 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 00:56:01.709143 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 00:56:01.712734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 00:56:01.715757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 00:56:01.722398 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 00:56:01.725936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 00:56:01.728984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 00:56:01.735598 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 00:56:01.738955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 00:56:01.742655 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 00:56:01.748567 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 00:56:01.751892 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 00:56:01.755474 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5370 00:56:01.762498 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5371 00:56:01.764995 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 00:56:01.768705 Total UI for P1: 0, mck2ui 16
5373 00:56:01.771864 best dqsien dly found for B0: ( 1, 2, 26)
5374 00:56:01.775213 Total UI for P1: 0, mck2ui 16
5375 00:56:01.778386 best dqsien dly found for B1: ( 1, 2, 30)
5376 00:56:01.781582 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5377 00:56:01.784938 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5378 00:56:01.785008
5379 00:56:01.788474 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5380 00:56:01.791804 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5381 00:56:01.794960 [Gating] SW calibration Done
5382 00:56:01.795032 ==
5383 00:56:01.798054 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 00:56:01.804544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 00:56:01.804614 ==
5386 00:56:01.804674 RX Vref Scan: 0
5387 00:56:01.804730
5388 00:56:01.807976 RX Vref 0 -> 0, step: 1
5389 00:56:01.808048
5390 00:56:01.811873 RX Delay -80 -> 252, step: 8
5391 00:56:01.814659 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5392 00:56:01.817975 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5393 00:56:01.821228 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5394 00:56:01.824757 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5395 00:56:01.827768 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5396 00:56:01.834217 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5397 00:56:01.837800 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5398 00:56:01.841218 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5399 00:56:01.844103 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5400 00:56:01.847531 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5401 00:56:01.854341 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5402 00:56:01.857227 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5403 00:56:01.861297 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5404 00:56:01.864154 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5405 00:56:01.867588 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5406 00:56:01.870535 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5407 00:56:01.873944 ==
5408 00:56:01.877218 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 00:56:01.880561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 00:56:01.880634 ==
5411 00:56:01.880695 DQS Delay:
5412 00:56:01.884378 DQS0 = 0, DQS1 = 0
5413 00:56:01.884445 DQM Delay:
5414 00:56:01.887444 DQM0 = 97, DQM1 = 90
5415 00:56:01.887513 DQ Delay:
5416 00:56:01.890631 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5417 00:56:01.893633 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5418 00:56:01.896864 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =83
5419 00:56:01.900235 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5420 00:56:01.900312
5421 00:56:01.900374
5422 00:56:01.900431 ==
5423 00:56:01.903102 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 00:56:01.906411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 00:56:01.906478 ==
5426 00:56:01.909695
5427 00:56:01.909761
5428 00:56:01.909825 TX Vref Scan disable
5429 00:56:01.913579 == TX Byte 0 ==
5430 00:56:01.916458 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5431 00:56:01.920177 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5432 00:56:01.923593 == TX Byte 1 ==
5433 00:56:01.926179 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5434 00:56:01.929467 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5435 00:56:01.933129 ==
5436 00:56:01.936097 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 00:56:01.939608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 00:56:01.939686 ==
5439 00:56:01.939748
5440 00:56:01.939806
5441 00:56:01.942834 TX Vref Scan disable
5442 00:56:01.942902 == TX Byte 0 ==
5443 00:56:01.949686 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5444 00:56:01.952471 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5445 00:56:01.952546 == TX Byte 1 ==
5446 00:56:01.959264 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5447 00:56:01.962477 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5448 00:56:01.962545
5449 00:56:01.962604 [DATLAT]
5450 00:56:01.965689 Freq=933, CH0 RK1
5451 00:56:01.965754
5452 00:56:01.965823 DATLAT Default: 0xb
5453 00:56:01.969097 0, 0xFFFF, sum = 0
5454 00:56:01.972248 1, 0xFFFF, sum = 0
5455 00:56:01.972317 2, 0xFFFF, sum = 0
5456 00:56:01.975746 3, 0xFFFF, sum = 0
5457 00:56:01.975815 4, 0xFFFF, sum = 0
5458 00:56:01.978895 5, 0xFFFF, sum = 0
5459 00:56:01.978961 6, 0xFFFF, sum = 0
5460 00:56:01.982086 7, 0xFFFF, sum = 0
5461 00:56:01.982153 8, 0xFFFF, sum = 0
5462 00:56:01.985412 9, 0xFFFF, sum = 0
5463 00:56:01.985479 10, 0x0, sum = 1
5464 00:56:01.988565 11, 0x0, sum = 2
5465 00:56:01.988642 12, 0x0, sum = 3
5466 00:56:01.992019 13, 0x0, sum = 4
5467 00:56:01.992088 best_step = 11
5468 00:56:01.992146
5469 00:56:01.992209 ==
5470 00:56:01.995605 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 00:56:01.998482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 00:56:02.002265 ==
5473 00:56:02.002334 RX Vref Scan: 0
5474 00:56:02.002395
5475 00:56:02.005127 RX Vref 0 -> 0, step: 1
5476 00:56:02.005196
5477 00:56:02.005255 RX Delay -53 -> 252, step: 4
5478 00:56:02.013275 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5479 00:56:02.016495 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5480 00:56:02.019628 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5481 00:56:02.023312 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5482 00:56:02.026708 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5483 00:56:02.029954 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5484 00:56:02.036088 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5485 00:56:02.039288 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5486 00:56:02.043326 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5487 00:56:02.046148 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5488 00:56:02.049677 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5489 00:56:02.055923 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5490 00:56:02.059292 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5491 00:56:02.062294 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5492 00:56:02.065806 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5493 00:56:02.069018 iDelay=195, Bit 15, Center 94 (3 ~ 186) 184
5494 00:56:02.069085 ==
5495 00:56:02.072546 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 00:56:02.079240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 00:56:02.079329 ==
5498 00:56:02.079441 DQS Delay:
5499 00:56:02.082623 DQS0 = 0, DQS1 = 0
5500 00:56:02.082720 DQM Delay:
5501 00:56:02.085695 DQM0 = 98, DQM1 = 88
5502 00:56:02.085788 DQ Delay:
5503 00:56:02.088900 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5504 00:56:02.092140 DQ4 =102, DQ5 =88, DQ6 =108, DQ7 =106
5505 00:56:02.095219 DQ8 =82, DQ9 =76, DQ10 =88, DQ11 =82
5506 00:56:02.098635 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5507 00:56:02.098734
5508 00:56:02.098831
5509 00:56:02.105915 [DQSOSCAuto] RK1, (LSB)MR18= 0x1612, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5510 00:56:02.108487 CH0 RK1: MR19=505, MR18=1612
5511 00:56:02.115056 CH0_RK1: MR19=0x505, MR18=0x1612, DQSOSC=414, MR23=63, INC=63, DEC=42
5512 00:56:02.118407 [RxdqsGatingPostProcess] freq 933
5513 00:56:02.125217 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5514 00:56:02.128749 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 00:56:02.128825 best DQS1 dly(2T, 0.5T) = (0, 11)
5516 00:56:02.131546 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 00:56:02.134998 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5518 00:56:02.138531 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 00:56:02.141647 best DQS1 dly(2T, 0.5T) = (0, 10)
5520 00:56:02.144979 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 00:56:02.148039 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5522 00:56:02.151414 Pre-setting of DQS Precalculation
5523 00:56:02.157782 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5524 00:56:02.157864 ==
5525 00:56:02.161342 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 00:56:02.164695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 00:56:02.164776 ==
5528 00:56:02.171122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 00:56:02.177854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5530 00:56:02.180793 [CA 0] Center 36 (6~67) winsize 62
5531 00:56:02.184485 [CA 1] Center 36 (6~67) winsize 62
5532 00:56:02.188255 [CA 2] Center 34 (4~65) winsize 62
5533 00:56:02.191404 [CA 3] Center 34 (4~65) winsize 62
5534 00:56:02.194240 [CA 4] Center 34 (4~65) winsize 62
5535 00:56:02.197536 [CA 5] Center 33 (3~64) winsize 62
5536 00:56:02.197617
5537 00:56:02.201072 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5538 00:56:02.201153
5539 00:56:02.203962 [CATrainingPosCal] consider 1 rank data
5540 00:56:02.207590 u2DelayCellTimex100 = 270/100 ps
5541 00:56:02.211371 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 00:56:02.214251 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 00:56:02.217500 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5544 00:56:02.220943 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5545 00:56:02.224093 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 00:56:02.227284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 00:56:02.227370
5548 00:56:02.230687 CA PerBit enable=1, Macro0, CA PI delay=33
5549 00:56:02.234068
5550 00:56:02.234150 [CBTSetCACLKResult] CA Dly = 33
5551 00:56:02.237095 CS Dly: 5 (0~36)
5552 00:56:02.237176 ==
5553 00:56:02.240434 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 00:56:02.243809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 00:56:02.243890 ==
5556 00:56:02.250272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 00:56:02.256658 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 00:56:02.260452 [CA 0] Center 36 (6~67) winsize 62
5559 00:56:02.263712 [CA 1] Center 36 (6~67) winsize 62
5560 00:56:02.267336 [CA 2] Center 34 (4~64) winsize 61
5561 00:56:02.270112 [CA 3] Center 33 (3~64) winsize 62
5562 00:56:02.273454 [CA 4] Center 33 (3~64) winsize 62
5563 00:56:02.276430 [CA 5] Center 33 (3~64) winsize 62
5564 00:56:02.276511
5565 00:56:02.279749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 00:56:02.279829
5567 00:56:02.283355 [CATrainingPosCal] consider 2 rank data
5568 00:56:02.286363 u2DelayCellTimex100 = 270/100 ps
5569 00:56:02.289804 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 00:56:02.292927 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 00:56:02.296592 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5572 00:56:02.299975 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 00:56:02.303237 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 00:56:02.309610 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 00:56:02.309691
5576 00:56:02.312740 CA PerBit enable=1, Macro0, CA PI delay=33
5577 00:56:02.312821
5578 00:56:02.316374 [CBTSetCACLKResult] CA Dly = 33
5579 00:56:02.316454 CS Dly: 6 (0~38)
5580 00:56:02.316518
5581 00:56:02.319555 ----->DramcWriteLeveling(PI) begin...
5582 00:56:02.319637 ==
5583 00:56:02.322559 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 00:56:02.329569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 00:56:02.329650 ==
5586 00:56:02.332754 Write leveling (Byte 0): 29 => 29
5587 00:56:02.336189 Write leveling (Byte 1): 29 => 29
5588 00:56:02.336270 DramcWriteLeveling(PI) end<-----
5589 00:56:02.339263
5590 00:56:02.339343 ==
5591 00:56:02.342857 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 00:56:02.345995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 00:56:02.346076 ==
5594 00:56:02.348960 [Gating] SW mode calibration
5595 00:56:02.355604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 00:56:02.362444 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5597 00:56:02.365172 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 00:56:02.368807 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 00:56:02.375207 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 00:56:02.378666 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 00:56:02.381894 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 00:56:02.388201 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 00:56:02.391727 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5604 00:56:02.394769 0 14 28 | B1->B0 | 2b2b 2727 | 1 0 | (1 0) (0 0)
5605 00:56:02.401372 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 00:56:02.404903 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 00:56:02.407835 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 00:56:02.414809 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 00:56:02.417735 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 00:56:02.420974 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 00:56:02.427693 0 15 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
5612 00:56:02.430946 0 15 28 | B1->B0 | 3838 4242 | 0 1 | (0 0) (0 0)
5613 00:56:02.434359 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:56:02.441280 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:56:02.444140 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 00:56:02.447669 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 00:56:02.454358 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 00:56:02.457732 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 00:56:02.461093 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5620 00:56:02.467754 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5621 00:56:02.470437 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5622 00:56:02.474544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 00:56:02.480718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 00:56:02.483582 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 00:56:02.487004 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 00:56:02.493749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:56:02.497208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:56:02.500206 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:56:02.506902 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 00:56:02.510120 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 00:56:02.513653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 00:56:02.520034 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 00:56:02.523347 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 00:56:02.526810 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 00:56:02.533174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5636 00:56:02.536369 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5637 00:56:02.539652 Total UI for P1: 0, mck2ui 16
5638 00:56:02.543048 best dqsien dly found for B1: ( 1, 2, 26)
5639 00:56:02.546281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 00:56:02.549807 Total UI for P1: 0, mck2ui 16
5641 00:56:02.553309 best dqsien dly found for B0: ( 1, 2, 26)
5642 00:56:02.556618 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5643 00:56:02.559406 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5644 00:56:02.559487
5645 00:56:02.565832 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5646 00:56:02.569501 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5647 00:56:02.569582 [Gating] SW calibration Done
5648 00:56:02.572408 ==
5649 00:56:02.575878 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 00:56:02.579208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 00:56:02.579289 ==
5652 00:56:02.579354 RX Vref Scan: 0
5653 00:56:02.579460
5654 00:56:02.582691 RX Vref 0 -> 0, step: 1
5655 00:56:02.582772
5656 00:56:02.585704 RX Delay -80 -> 252, step: 8
5657 00:56:02.589179 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5658 00:56:02.592751 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5659 00:56:02.598945 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5660 00:56:02.602339 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5661 00:56:02.605283 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5662 00:56:02.608750 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5663 00:56:02.611733 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5664 00:56:02.615178 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5665 00:56:02.621993 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5666 00:56:02.624890 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5667 00:56:02.628417 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5668 00:56:02.631810 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5669 00:56:02.635007 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5670 00:56:02.641529 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5671 00:56:02.644792 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5672 00:56:02.648444 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5673 00:56:02.648526 ==
5674 00:56:02.651746 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 00:56:02.654884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 00:56:02.654967 ==
5677 00:56:02.658179 DQS Delay:
5678 00:56:02.658260 DQS0 = 0, DQS1 = 0
5679 00:56:02.658326 DQM Delay:
5680 00:56:02.661504 DQM0 = 99, DQM1 = 96
5681 00:56:02.661585 DQ Delay:
5682 00:56:02.664726 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5683 00:56:02.668102 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5684 00:56:02.671033 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5685 00:56:02.674615 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5686 00:56:02.677712
5687 00:56:02.677792
5688 00:56:02.677857 ==
5689 00:56:02.681198 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 00:56:02.684945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 00:56:02.685027 ==
5692 00:56:02.685092
5693 00:56:02.685152
5694 00:56:02.687873 TX Vref Scan disable
5695 00:56:02.687955 == TX Byte 0 ==
5696 00:56:02.694118 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5697 00:56:02.697734 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5698 00:56:02.697816 == TX Byte 1 ==
5699 00:56:02.704190 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5700 00:56:02.707978 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5701 00:56:02.708059 ==
5702 00:56:02.710717 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 00:56:02.714219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 00:56:02.714301 ==
5705 00:56:02.714365
5706 00:56:02.714425
5707 00:56:02.717682 TX Vref Scan disable
5708 00:56:02.721128 == TX Byte 0 ==
5709 00:56:02.724336 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5710 00:56:02.727219 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5711 00:56:02.730470 == TX Byte 1 ==
5712 00:56:02.734038 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5713 00:56:02.736884 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5714 00:56:02.736966
5715 00:56:02.740360 [DATLAT]
5716 00:56:02.740442 Freq=933, CH1 RK0
5717 00:56:02.740507
5718 00:56:02.743898 DATLAT Default: 0xd
5719 00:56:02.743979 0, 0xFFFF, sum = 0
5720 00:56:02.747144 1, 0xFFFF, sum = 0
5721 00:56:02.747227 2, 0xFFFF, sum = 0
5722 00:56:02.750298 3, 0xFFFF, sum = 0
5723 00:56:02.750380 4, 0xFFFF, sum = 0
5724 00:56:02.753581 5, 0xFFFF, sum = 0
5725 00:56:02.756852 6, 0xFFFF, sum = 0
5726 00:56:02.756939 7, 0xFFFF, sum = 0
5727 00:56:02.759933 8, 0xFFFF, sum = 0
5728 00:56:02.760015 9, 0xFFFF, sum = 0
5729 00:56:02.763885 10, 0x0, sum = 1
5730 00:56:02.763968 11, 0x0, sum = 2
5731 00:56:02.764033 12, 0x0, sum = 3
5732 00:56:02.766651 13, 0x0, sum = 4
5733 00:56:02.766736 best_step = 11
5734 00:56:02.766801
5735 00:56:02.770391 ==
5736 00:56:02.773145 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 00:56:02.777282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 00:56:02.777364 ==
5739 00:56:02.777429 RX Vref Scan: 1
5740 00:56:02.777490
5741 00:56:02.779961 RX Vref 0 -> 0, step: 1
5742 00:56:02.780042
5743 00:56:02.783114 RX Delay -53 -> 252, step: 4
5744 00:56:02.783196
5745 00:56:02.786459 Set Vref, RX VrefLevel [Byte0]: 51
5746 00:56:02.789730 [Byte1]: 52
5747 00:56:02.789811
5748 00:56:02.793229 Final RX Vref Byte 0 = 51 to rank0
5749 00:56:02.796803 Final RX Vref Byte 1 = 52 to rank0
5750 00:56:02.799560 Final RX Vref Byte 0 = 51 to rank1
5751 00:56:02.802575 Final RX Vref Byte 1 = 52 to rank1==
5752 00:56:02.806063 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 00:56:02.813211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 00:56:02.813309 ==
5755 00:56:02.813376 DQS Delay:
5756 00:56:02.813436 DQS0 = 0, DQS1 = 0
5757 00:56:02.816164 DQM Delay:
5758 00:56:02.816246 DQM0 = 98, DQM1 = 94
5759 00:56:02.819322 DQ Delay:
5760 00:56:02.823086 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5761 00:56:02.825960 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5762 00:56:02.829314 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =90
5763 00:56:02.832732 DQ12 =102, DQ13 =104, DQ14 =102, DQ15 =104
5764 00:56:02.832814
5765 00:56:02.832879
5766 00:56:02.839117 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5767 00:56:02.842633 CH1 RK0: MR19=505, MR18=515
5768 00:56:02.848975 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5769 00:56:02.849056
5770 00:56:02.852411 ----->DramcWriteLeveling(PI) begin...
5771 00:56:02.852494 ==
5772 00:56:02.855246 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 00:56:02.858800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 00:56:02.858882 ==
5775 00:56:02.862229 Write leveling (Byte 0): 26 => 26
5776 00:56:02.865530 Write leveling (Byte 1): 27 => 27
5777 00:56:02.868607 DramcWriteLeveling(PI) end<-----
5778 00:56:02.868689
5779 00:56:02.868753 ==
5780 00:56:02.871594 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 00:56:02.878228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 00:56:02.878310 ==
5783 00:56:02.878375 [Gating] SW mode calibration
5784 00:56:02.887985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5785 00:56:02.891498 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5786 00:56:02.898528 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 00:56:02.901566 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 00:56:02.904377 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 00:56:02.911228 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 00:56:02.914552 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 00:56:02.917759 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5792 00:56:02.924460 0 14 24 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 1)
5793 00:56:02.928086 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5794 00:56:02.931080 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 00:56:02.937599 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 00:56:02.940706 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 00:56:02.944026 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 00:56:02.950972 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 00:56:02.953964 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 00:56:02.957284 0 15 24 | B1->B0 | 2525 3333 | 0 1 | (0 0) (0 0)
5801 00:56:02.963714 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5802 00:56:02.967528 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 00:56:02.970773 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 00:56:02.977182 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 00:56:02.980575 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 00:56:02.983618 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 00:56:02.990382 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5808 00:56:02.993824 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5809 00:56:02.996843 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5810 00:56:03.003499 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 00:56:03.006714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 00:56:03.009825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 00:56:03.016524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 00:56:03.019752 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 00:56:03.023026 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 00:56:03.029962 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 00:56:03.032760 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 00:56:03.035985 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 00:56:03.042675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 00:56:03.046109 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 00:56:03.049515 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 00:56:03.055872 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 00:56:03.059389 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 00:56:03.062489 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5825 00:56:03.069448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5826 00:56:03.069529 Total UI for P1: 0, mck2ui 16
5827 00:56:03.075752 best dqsien dly found for B0: ( 1, 2, 24)
5828 00:56:03.079229 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 00:56:03.082071 Total UI for P1: 0, mck2ui 16
5830 00:56:03.085524 best dqsien dly found for B1: ( 1, 2, 28)
5831 00:56:03.089053 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5832 00:56:03.092259 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5833 00:56:03.092340
5834 00:56:03.095416 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5835 00:56:03.098742 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5836 00:56:03.102149 [Gating] SW calibration Done
5837 00:56:03.102229 ==
5838 00:56:03.105640 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 00:56:03.108986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 00:56:03.112195 ==
5841 00:56:03.112275 RX Vref Scan: 0
5842 00:56:03.112339
5843 00:56:03.115601 RX Vref 0 -> 0, step: 1
5844 00:56:03.115683
5845 00:56:03.118761 RX Delay -80 -> 252, step: 8
5846 00:56:03.122012 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5847 00:56:03.125117 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5848 00:56:03.128219 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5849 00:56:03.132031 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5850 00:56:03.134940 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5851 00:56:03.141708 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5852 00:56:03.144970 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5853 00:56:03.148248 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5854 00:56:03.151651 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5855 00:56:03.154912 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5856 00:56:03.161287 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5857 00:56:03.164847 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5858 00:56:03.167801 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5859 00:56:03.171183 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5860 00:56:03.174222 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5861 00:56:03.181337 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5862 00:56:03.181418 ==
5863 00:56:03.184162 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 00:56:03.187690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 00:56:03.187770 ==
5866 00:56:03.187835 DQS Delay:
5867 00:56:03.190907 DQS0 = 0, DQS1 = 0
5868 00:56:03.190987 DQM Delay:
5869 00:56:03.194125 DQM0 = 97, DQM1 = 94
5870 00:56:03.194206 DQ Delay:
5871 00:56:03.197367 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5872 00:56:03.200574 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5873 00:56:03.203862 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5874 00:56:03.207184 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5875 00:56:03.207264
5876 00:56:03.207327
5877 00:56:03.207423 ==
5878 00:56:03.211073 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 00:56:03.217026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 00:56:03.217107 ==
5881 00:56:03.217172
5882 00:56:03.217231
5883 00:56:03.217288 TX Vref Scan disable
5884 00:56:03.220618 == TX Byte 0 ==
5885 00:56:03.223842 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5886 00:56:03.230282 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5887 00:56:03.230368 == TX Byte 1 ==
5888 00:56:03.233617 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5889 00:56:03.240335 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5890 00:56:03.240417 ==
5891 00:56:03.243809 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 00:56:03.247132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 00:56:03.247213 ==
5894 00:56:03.247278
5895 00:56:03.247337
5896 00:56:03.250146 TX Vref Scan disable
5897 00:56:03.253007 == TX Byte 0 ==
5898 00:56:03.256470 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5899 00:56:03.260066 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5900 00:56:03.263454 == TX Byte 1 ==
5901 00:56:03.266545 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5902 00:56:03.269652 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5903 00:56:03.269732
5904 00:56:03.269797 [DATLAT]
5905 00:56:03.273073 Freq=933, CH1 RK1
5906 00:56:03.273153
5907 00:56:03.276311 DATLAT Default: 0xb
5908 00:56:03.276392 0, 0xFFFF, sum = 0
5909 00:56:03.279651 1, 0xFFFF, sum = 0
5910 00:56:03.279733 2, 0xFFFF, sum = 0
5911 00:56:03.282664 3, 0xFFFF, sum = 0
5912 00:56:03.282746 4, 0xFFFF, sum = 0
5913 00:56:03.286455 5, 0xFFFF, sum = 0
5914 00:56:03.286537 6, 0xFFFF, sum = 0
5915 00:56:03.289343 7, 0xFFFF, sum = 0
5916 00:56:03.289424 8, 0xFFFF, sum = 0
5917 00:56:03.292883 9, 0xFFFF, sum = 0
5918 00:56:03.292965 10, 0x0, sum = 1
5919 00:56:03.295788 11, 0x0, sum = 2
5920 00:56:03.295870 12, 0x0, sum = 3
5921 00:56:03.299158 13, 0x0, sum = 4
5922 00:56:03.299240 best_step = 11
5923 00:56:03.299303
5924 00:56:03.299368 ==
5925 00:56:03.302326 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 00:56:03.306202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 00:56:03.308911 ==
5928 00:56:03.308992 RX Vref Scan: 0
5929 00:56:03.309056
5930 00:56:03.312533 RX Vref 0 -> 0, step: 1
5931 00:56:03.312614
5932 00:56:03.315584 RX Delay -53 -> 252, step: 4
5933 00:56:03.319308 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5934 00:56:03.322204 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5935 00:56:03.329061 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5936 00:56:03.332474 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5937 00:56:03.335406 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5938 00:56:03.338839 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5939 00:56:03.342173 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5940 00:56:03.345581 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5941 00:56:03.352336 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5942 00:56:03.355491 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5943 00:56:03.358666 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5944 00:56:03.361976 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5945 00:56:03.365511 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5946 00:56:03.371850 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5947 00:56:03.374843 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5948 00:56:03.378749 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5949 00:56:03.378830 ==
5950 00:56:03.381884 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 00:56:03.385061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 00:56:03.385142 ==
5953 00:56:03.388219 DQS Delay:
5954 00:56:03.388299 DQS0 = 0, DQS1 = 0
5955 00:56:03.391826 DQM Delay:
5956 00:56:03.391906 DQM0 = 96, DQM1 = 92
5957 00:56:03.394998 DQ Delay:
5958 00:56:03.395079 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5959 00:56:03.398399 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5960 00:56:03.401263 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5961 00:56:03.407878 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =102
5962 00:56:03.407959
5963 00:56:03.408022
5964 00:56:03.414851 [DQSOSCAuto] RK1, (LSB)MR18= 0xe26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5965 00:56:03.418342 CH1 RK1: MR19=505, MR18=E26
5966 00:56:03.424359 CH1_RK1: MR19=0x505, MR18=0xE26, DQSOSC=409, MR23=63, INC=64, DEC=43
5967 00:56:03.427946 [RxdqsGatingPostProcess] freq 933
5968 00:56:03.431346 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5969 00:56:03.434460 best DQS0 dly(2T, 0.5T) = (0, 10)
5970 00:56:03.437575 best DQS1 dly(2T, 0.5T) = (0, 10)
5971 00:56:03.440844 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5972 00:56:03.444767 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5973 00:56:03.447729 best DQS0 dly(2T, 0.5T) = (0, 10)
5974 00:56:03.450787 best DQS1 dly(2T, 0.5T) = (0, 10)
5975 00:56:03.454287 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5976 00:56:03.457258 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5977 00:56:03.460904 Pre-setting of DQS Precalculation
5978 00:56:03.464117 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5979 00:56:03.473726 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5980 00:56:03.480810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5981 00:56:03.480891
5982 00:56:03.480955
5983 00:56:03.483695 [Calibration Summary] 1866 Mbps
5984 00:56:03.483777 CH 0, Rank 0
5985 00:56:03.487101 SW Impedance : PASS
5986 00:56:03.487171 DUTY Scan : NO K
5987 00:56:03.490513 ZQ Calibration : PASS
5988 00:56:03.493990 Jitter Meter : NO K
5989 00:56:03.494070 CBT Training : PASS
5990 00:56:03.496974 Write leveling : PASS
5991 00:56:03.500405 RX DQS gating : PASS
5992 00:56:03.500486 RX DQ/DQS(RDDQC) : PASS
5993 00:56:03.503552 TX DQ/DQS : PASS
5994 00:56:03.506881 RX DATLAT : PASS
5995 00:56:03.506962 RX DQ/DQS(Engine): PASS
5996 00:56:03.510334 TX OE : NO K
5997 00:56:03.510415 All Pass.
5998 00:56:03.510479
5999 00:56:03.513528 CH 0, Rank 1
6000 00:56:03.513608 SW Impedance : PASS
6001 00:56:03.517007 DUTY Scan : NO K
6002 00:56:03.520227 ZQ Calibration : PASS
6003 00:56:03.520304 Jitter Meter : NO K
6004 00:56:03.523030 CBT Training : PASS
6005 00:56:03.526462 Write leveling : PASS
6006 00:56:03.526532 RX DQS gating : PASS
6007 00:56:03.529654 RX DQ/DQS(RDDQC) : PASS
6008 00:56:03.533520 TX DQ/DQS : PASS
6009 00:56:03.533589 RX DATLAT : PASS
6010 00:56:03.536321 RX DQ/DQS(Engine): PASS
6011 00:56:03.539937 TX OE : NO K
6012 00:56:03.540012 All Pass.
6013 00:56:03.540071
6014 00:56:03.540128 CH 1, Rank 0
6015 00:56:03.543490 SW Impedance : PASS
6016 00:56:03.543561 DUTY Scan : NO K
6017 00:56:03.546608 ZQ Calibration : PASS
6018 00:56:03.549988 Jitter Meter : NO K
6019 00:56:03.550060 CBT Training : PASS
6020 00:56:03.552838 Write leveling : PASS
6021 00:56:03.556583 RX DQS gating : PASS
6022 00:56:03.556651 RX DQ/DQS(RDDQC) : PASS
6023 00:56:03.559620 TX DQ/DQS : PASS
6024 00:56:03.563313 RX DATLAT : PASS
6025 00:56:03.563393 RX DQ/DQS(Engine): PASS
6026 00:56:03.565980 TX OE : NO K
6027 00:56:03.566061 All Pass.
6028 00:56:03.566125
6029 00:56:03.569637 CH 1, Rank 1
6030 00:56:03.569717 SW Impedance : PASS
6031 00:56:03.572870 DUTY Scan : NO K
6032 00:56:03.575817 ZQ Calibration : PASS
6033 00:56:03.575898 Jitter Meter : NO K
6034 00:56:03.579313 CBT Training : PASS
6035 00:56:03.582385 Write leveling : PASS
6036 00:56:03.582463 RX DQS gating : PASS
6037 00:56:03.586126 RX DQ/DQS(RDDQC) : PASS
6038 00:56:03.589463 TX DQ/DQS : PASS
6039 00:56:03.589538 RX DATLAT : PASS
6040 00:56:03.592435 RX DQ/DQS(Engine): PASS
6041 00:56:03.596094 TX OE : NO K
6042 00:56:03.596168 All Pass.
6043 00:56:03.596226
6044 00:56:03.598847 DramC Write-DBI off
6045 00:56:03.598913 PER_BANK_REFRESH: Hybrid Mode
6046 00:56:03.602576 TX_TRACKING: ON
6047 00:56:03.608987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6048 00:56:03.615597 [FAST_K] Save calibration result to emmc
6049 00:56:03.619154 dramc_set_vcore_voltage set vcore to 650000
6050 00:56:03.619225 Read voltage for 400, 6
6051 00:56:03.622106 Vio18 = 0
6052 00:56:03.622215 Vcore = 650000
6053 00:56:03.622307 Vdram = 0
6054 00:56:03.625447 Vddq = 0
6055 00:56:03.625527 Vmddr = 0
6056 00:56:03.628952 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6057 00:56:03.635212 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6058 00:56:03.638743 MEM_TYPE=3, freq_sel=20
6059 00:56:03.641726 sv_algorithm_assistance_LP4_800
6060 00:56:03.645211 ============ PULL DRAM RESETB DOWN ============
6061 00:56:03.649035 ========== PULL DRAM RESETB DOWN end =========
6062 00:56:03.654974 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6063 00:56:03.658349 ===================================
6064 00:56:03.658419 LPDDR4 DRAM CONFIGURATION
6065 00:56:03.661775 ===================================
6066 00:56:03.664745 EX_ROW_EN[0] = 0x0
6067 00:56:03.664813 EX_ROW_EN[1] = 0x0
6068 00:56:03.668189 LP4Y_EN = 0x0
6069 00:56:03.671320 WORK_FSP = 0x0
6070 00:56:03.671437 WL = 0x2
6071 00:56:03.674686 RL = 0x2
6072 00:56:03.674752 BL = 0x2
6073 00:56:03.677936 RPST = 0x0
6074 00:56:03.678004 RD_PRE = 0x0
6075 00:56:03.681116 WR_PRE = 0x1
6076 00:56:03.681181 WR_PST = 0x0
6077 00:56:03.684417 DBI_WR = 0x0
6078 00:56:03.684489 DBI_RD = 0x0
6079 00:56:03.687845 OTF = 0x1
6080 00:56:03.691258 ===================================
6081 00:56:03.694335 ===================================
6082 00:56:03.694404 ANA top config
6083 00:56:03.697767 ===================================
6084 00:56:03.700848 DLL_ASYNC_EN = 0
6085 00:56:03.704399 ALL_SLAVE_EN = 1
6086 00:56:03.707427 NEW_RANK_MODE = 1
6087 00:56:03.707495 DLL_IDLE_MODE = 1
6088 00:56:03.710855 LP45_APHY_COMB_EN = 1
6089 00:56:03.714269 TX_ODT_DIS = 1
6090 00:56:03.717453 NEW_8X_MODE = 1
6091 00:56:03.720829 ===================================
6092 00:56:03.723722 ===================================
6093 00:56:03.727521 data_rate = 800
6094 00:56:03.730463 CKR = 1
6095 00:56:03.730535 DQ_P2S_RATIO = 4
6096 00:56:03.733649 ===================================
6097 00:56:03.737153 CA_P2S_RATIO = 4
6098 00:56:03.740161 DQ_CA_OPEN = 0
6099 00:56:03.743777 DQ_SEMI_OPEN = 1
6100 00:56:03.746865 CA_SEMI_OPEN = 1
6101 00:56:03.746935 CA_FULL_RATE = 0
6102 00:56:03.750079 DQ_CKDIV4_EN = 0
6103 00:56:03.753849 CA_CKDIV4_EN = 1
6104 00:56:03.756924 CA_PREDIV_EN = 0
6105 00:56:03.760325 PH8_DLY = 0
6106 00:56:03.763240 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6107 00:56:03.766466 DQ_AAMCK_DIV = 0
6108 00:56:03.766541 CA_AAMCK_DIV = 0
6109 00:56:03.769978 CA_ADMCK_DIV = 4
6110 00:56:03.773401 DQ_TRACK_CA_EN = 0
6111 00:56:03.776935 CA_PICK = 800
6112 00:56:03.779794 CA_MCKIO = 400
6113 00:56:03.783055 MCKIO_SEMI = 400
6114 00:56:03.786282 PLL_FREQ = 3016
6115 00:56:03.786357 DQ_UI_PI_RATIO = 32
6116 00:56:03.789670 CA_UI_PI_RATIO = 32
6117 00:56:03.793024 ===================================
6118 00:56:03.796645 ===================================
6119 00:56:03.799709 memory_type:LPDDR4
6120 00:56:03.802683 GP_NUM : 10
6121 00:56:03.802752 SRAM_EN : 1
6122 00:56:03.806193 MD32_EN : 0
6123 00:56:03.809693 ===================================
6124 00:56:03.812731 [ANA_INIT] >>>>>>>>>>>>>>
6125 00:56:03.815998 <<<<<< [CONFIGURE PHASE]: ANA_TX
6126 00:56:03.819708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6127 00:56:03.823037 ===================================
6128 00:56:03.823118 data_rate = 800,PCW = 0X7400
6129 00:56:03.826319 ===================================
6130 00:56:03.829500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6131 00:56:03.836048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 00:56:03.849425 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6133 00:56:03.852492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6134 00:56:03.855735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6135 00:56:03.859213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6136 00:56:03.862201 [ANA_INIT] flow start
6137 00:56:03.862317 [ANA_INIT] PLL >>>>>>>>
6138 00:56:03.865466 [ANA_INIT] PLL <<<<<<<<
6139 00:56:03.868529 [ANA_INIT] MIDPI >>>>>>>>
6140 00:56:03.871770 [ANA_INIT] MIDPI <<<<<<<<
6141 00:56:03.871850 [ANA_INIT] DLL >>>>>>>>
6142 00:56:03.875344 [ANA_INIT] flow end
6143 00:56:03.878812 ============ LP4 DIFF to SE enter ============
6144 00:56:03.881595 ============ LP4 DIFF to SE exit ============
6145 00:56:03.884986 [ANA_INIT] <<<<<<<<<<<<<
6146 00:56:03.888509 [Flow] Enable top DCM control >>>>>
6147 00:56:03.891727 [Flow] Enable top DCM control <<<<<
6148 00:56:03.895066 Enable DLL master slave shuffle
6149 00:56:03.901965 ==============================================================
6150 00:56:03.902046 Gating Mode config
6151 00:56:03.908220 ==============================================================
6152 00:56:03.908301 Config description:
6153 00:56:03.918144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6154 00:56:03.925493 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6155 00:56:03.931590 SELPH_MODE 0: By rank 1: By Phase
6156 00:56:03.934543 ==============================================================
6157 00:56:03.938203 GAT_TRACK_EN = 0
6158 00:56:03.941426 RX_GATING_MODE = 2
6159 00:56:03.944279 RX_GATING_TRACK_MODE = 2
6160 00:56:03.947903 SELPH_MODE = 1
6161 00:56:03.951095 PICG_EARLY_EN = 1
6162 00:56:03.954575 VALID_LAT_VALUE = 1
6163 00:56:03.960822 ==============================================================
6164 00:56:03.964148 Enter into Gating configuration >>>>
6165 00:56:03.967484 Exit from Gating configuration <<<<
6166 00:56:03.970545 Enter into DVFS_PRE_config >>>>>
6167 00:56:03.980627 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6168 00:56:03.984091 Exit from DVFS_PRE_config <<<<<
6169 00:56:03.987123 Enter into PICG configuration >>>>
6170 00:56:03.990232 Exit from PICG configuration <<<<
6171 00:56:03.993705 [RX_INPUT] configuration >>>>>
6172 00:56:03.993785 [RX_INPUT] configuration <<<<<
6173 00:56:04.000647 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6174 00:56:04.007110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6175 00:56:04.013722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 00:56:04.017061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 00:56:04.023498 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6178 00:56:04.030420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6179 00:56:04.033177 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6180 00:56:04.040157 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6181 00:56:04.043168 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6182 00:56:04.046332 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6183 00:56:04.049711 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6184 00:56:04.056631 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 00:56:04.059794 ===================================
6186 00:56:04.059875 LPDDR4 DRAM CONFIGURATION
6187 00:56:04.063337 ===================================
6188 00:56:04.066522 EX_ROW_EN[0] = 0x0
6189 00:56:04.069604 EX_ROW_EN[1] = 0x0
6190 00:56:04.069713 LP4Y_EN = 0x0
6191 00:56:04.072730 WORK_FSP = 0x0
6192 00:56:04.072811 WL = 0x2
6193 00:56:04.075951 RL = 0x2
6194 00:56:04.076032 BL = 0x2
6195 00:56:04.079419 RPST = 0x0
6196 00:56:04.079500 RD_PRE = 0x0
6197 00:56:04.082776 WR_PRE = 0x1
6198 00:56:04.082857 WR_PST = 0x0
6199 00:56:04.085928 DBI_WR = 0x0
6200 00:56:04.086009 DBI_RD = 0x0
6201 00:56:04.089405 OTF = 0x1
6202 00:56:04.092602 ===================================
6203 00:56:04.095771 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6204 00:56:04.099353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6205 00:56:04.105975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 00:56:04.109354 ===================================
6207 00:56:04.111936 LPDDR4 DRAM CONFIGURATION
6208 00:56:04.115768 ===================================
6209 00:56:04.115859 EX_ROW_EN[0] = 0x10
6210 00:56:04.118963 EX_ROW_EN[1] = 0x0
6211 00:56:04.119046 LP4Y_EN = 0x0
6212 00:56:04.122181 WORK_FSP = 0x0
6213 00:56:04.122262 WL = 0x2
6214 00:56:04.125356 RL = 0x2
6215 00:56:04.125479 BL = 0x2
6216 00:56:04.128522 RPST = 0x0
6217 00:56:04.128603 RD_PRE = 0x0
6218 00:56:04.131855 WR_PRE = 0x1
6219 00:56:04.135250 WR_PST = 0x0
6220 00:56:04.135331 DBI_WR = 0x0
6221 00:56:04.138707 DBI_RD = 0x0
6222 00:56:04.138789 OTF = 0x1
6223 00:56:04.141818 ===================================
6224 00:56:04.148676 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6225 00:56:04.152293 nWR fixed to 30
6226 00:56:04.155079 [ModeRegInit_LP4] CH0 RK0
6227 00:56:04.155159 [ModeRegInit_LP4] CH0 RK1
6228 00:56:04.158609 [ModeRegInit_LP4] CH1 RK0
6229 00:56:04.162049 [ModeRegInit_LP4] CH1 RK1
6230 00:56:04.162130 match AC timing 19
6231 00:56:04.168464 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6232 00:56:04.171940 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6233 00:56:04.175168 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6234 00:56:04.181608 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6235 00:56:04.185000 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6236 00:56:04.185080 ==
6237 00:56:04.188543 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 00:56:04.191924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 00:56:04.192005 ==
6240 00:56:04.198243 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6241 00:56:04.205121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6242 00:56:04.207955 [CA 0] Center 36 (8~64) winsize 57
6243 00:56:04.211295 [CA 1] Center 36 (8~64) winsize 57
6244 00:56:04.214770 [CA 2] Center 36 (8~64) winsize 57
6245 00:56:04.217997 [CA 3] Center 36 (8~64) winsize 57
6246 00:56:04.221542 [CA 4] Center 36 (8~64) winsize 57
6247 00:56:04.224576 [CA 5] Center 36 (8~64) winsize 57
6248 00:56:04.224657
6249 00:56:04.227733 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6250 00:56:04.227815
6251 00:56:04.231089 [CATrainingPosCal] consider 1 rank data
6252 00:56:04.234231 u2DelayCellTimex100 = 270/100 ps
6253 00:56:04.237744 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 00:56:04.241077 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 00:56:04.244453 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 00:56:04.247515 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:56:04.251252 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:56:04.254362 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:56:04.254442
6260 00:56:04.260721 CA PerBit enable=1, Macro0, CA PI delay=36
6261 00:56:04.260801
6262 00:56:04.260865 [CBTSetCACLKResult] CA Dly = 36
6263 00:56:04.263897 CS Dly: 1 (0~32)
6264 00:56:04.263978 ==
6265 00:56:04.267217 Dram Type= 6, Freq= 0, CH_0, rank 1
6266 00:56:04.270257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 00:56:04.270339 ==
6268 00:56:04.277396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6269 00:56:04.283288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6270 00:56:04.287126 [CA 0] Center 36 (8~64) winsize 57
6271 00:56:04.290433 [CA 1] Center 36 (8~64) winsize 57
6272 00:56:04.293292 [CA 2] Center 36 (8~64) winsize 57
6273 00:56:04.296472 [CA 3] Center 36 (8~64) winsize 57
6274 00:56:04.299799 [CA 4] Center 36 (8~64) winsize 57
6275 00:56:04.303403 [CA 5] Center 36 (8~64) winsize 57
6276 00:56:04.303498
6277 00:56:04.306595 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6278 00:56:04.306676
6279 00:56:04.310035 [CATrainingPosCal] consider 2 rank data
6280 00:56:04.313179 u2DelayCellTimex100 = 270/100 ps
6281 00:56:04.316185 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 00:56:04.319565 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 00:56:04.322689 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 00:56:04.326411 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 00:56:04.329291 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 00:56:04.332852 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 00:56:04.332929
6288 00:56:04.339448 CA PerBit enable=1, Macro0, CA PI delay=36
6289 00:56:04.339519
6290 00:56:04.342385 [CBTSetCACLKResult] CA Dly = 36
6291 00:56:04.342456 CS Dly: 1 (0~32)
6292 00:56:04.342524
6293 00:56:04.345747 ----->DramcWriteLeveling(PI) begin...
6294 00:56:04.345814 ==
6295 00:56:04.349176 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 00:56:04.352764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 00:56:04.355301 ==
6298 00:56:04.355407 Write leveling (Byte 0): 40 => 8
6299 00:56:04.358812 Write leveling (Byte 1): 40 => 8
6300 00:56:04.362581 DramcWriteLeveling(PI) end<-----
6301 00:56:04.362645
6302 00:56:04.362709 ==
6303 00:56:04.365297 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 00:56:04.372305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 00:56:04.372372 ==
6306 00:56:04.372431 [Gating] SW mode calibration
6307 00:56:04.382119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6308 00:56:04.385251 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6309 00:56:04.391767 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 00:56:04.394990 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6311 00:56:04.398377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 00:56:04.405126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 00:56:04.408051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 00:56:04.411560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 00:56:04.417956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 00:56:04.421421 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6317 00:56:04.424669 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 00:56:04.427949 Total UI for P1: 0, mck2ui 16
6319 00:56:04.431308 best dqsien dly found for B0: ( 0, 14, 24)
6320 00:56:04.434506 Total UI for P1: 0, mck2ui 16
6321 00:56:04.437951 best dqsien dly found for B1: ( 0, 14, 24)
6322 00:56:04.441375 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6323 00:56:04.444247 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6324 00:56:04.444315
6325 00:56:04.451059 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 00:56:04.454474 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6327 00:56:04.457487 [Gating] SW calibration Done
6328 00:56:04.457563 ==
6329 00:56:04.461055 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 00:56:04.464153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 00:56:04.464219 ==
6332 00:56:04.464279 RX Vref Scan: 0
6333 00:56:04.464343
6334 00:56:04.467663 RX Vref 0 -> 0, step: 1
6335 00:56:04.467727
6336 00:56:04.470924 RX Delay -410 -> 252, step: 16
6337 00:56:04.473832 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6338 00:56:04.480704 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6339 00:56:04.484184 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6340 00:56:04.487519 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6341 00:56:04.491022 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6342 00:56:04.497191 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6343 00:56:04.500768 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6344 00:56:04.503594 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6345 00:56:04.507138 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6346 00:56:04.513574 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6347 00:56:04.516925 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6348 00:56:04.520493 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6349 00:56:04.523869 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6350 00:56:04.529776 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6351 00:56:04.533823 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6352 00:56:04.536667 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6353 00:56:04.536747 ==
6354 00:56:04.540103 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 00:56:04.546534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 00:56:04.546617 ==
6357 00:56:04.546685 DQS Delay:
6358 00:56:04.549625 DQS0 = 35, DQS1 = 51
6359 00:56:04.549698 DQM Delay:
6360 00:56:04.552994 DQM0 = 5, DQM1 = 11
6361 00:56:04.553061 DQ Delay:
6362 00:56:04.556465 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6363 00:56:04.560530 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6364 00:56:04.560599 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6365 00:56:04.566316 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6366 00:56:04.566386
6367 00:56:04.566445
6368 00:56:04.566507 ==
6369 00:56:04.569376 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 00:56:04.572787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 00:56:04.572866 ==
6372 00:56:04.572926
6373 00:56:04.572983
6374 00:56:04.575776 TX Vref Scan disable
6375 00:56:04.575840 == TX Byte 0 ==
6376 00:56:04.582609 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 00:56:04.586090 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 00:56:04.586158 == TX Byte 1 ==
6379 00:56:04.589258 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 00:56:04.595799 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 00:56:04.595873 ==
6382 00:56:04.599241 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 00:56:04.602153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 00:56:04.602221 ==
6385 00:56:04.602287
6386 00:56:04.602343
6387 00:56:04.605738 TX Vref Scan disable
6388 00:56:04.605810 == TX Byte 0 ==
6389 00:56:04.611811 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 00:56:04.615456 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 00:56:04.615537 == TX Byte 1 ==
6392 00:56:04.622003 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6393 00:56:04.624998 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6394 00:56:04.625078
6395 00:56:04.625141 [DATLAT]
6396 00:56:04.628471 Freq=400, CH0 RK0
6397 00:56:04.628551
6398 00:56:04.628615 DATLAT Default: 0xf
6399 00:56:04.631675 0, 0xFFFF, sum = 0
6400 00:56:04.631756 1, 0xFFFF, sum = 0
6401 00:56:04.635051 2, 0xFFFF, sum = 0
6402 00:56:04.635132 3, 0xFFFF, sum = 0
6403 00:56:04.638700 4, 0xFFFF, sum = 0
6404 00:56:04.638781 5, 0xFFFF, sum = 0
6405 00:56:04.641981 6, 0xFFFF, sum = 0
6406 00:56:04.645208 7, 0xFFFF, sum = 0
6407 00:56:04.645289 8, 0xFFFF, sum = 0
6408 00:56:04.648213 9, 0xFFFF, sum = 0
6409 00:56:04.648294 10, 0xFFFF, sum = 0
6410 00:56:04.651626 11, 0xFFFF, sum = 0
6411 00:56:04.651707 12, 0xFFFF, sum = 0
6412 00:56:04.654622 13, 0x0, sum = 1
6413 00:56:04.654702 14, 0x0, sum = 2
6414 00:56:04.658040 15, 0x0, sum = 3
6415 00:56:04.658121 16, 0x0, sum = 4
6416 00:56:04.661357 best_step = 14
6417 00:56:04.661437
6418 00:56:04.661500 ==
6419 00:56:04.664819 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 00:56:04.667757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 00:56:04.667837 ==
6422 00:56:04.667901 RX Vref Scan: 1
6423 00:56:04.671579
6424 00:56:04.671660 RX Vref 0 -> 0, step: 1
6425 00:56:04.671725
6426 00:56:04.674319 RX Delay -343 -> 252, step: 8
6427 00:56:04.674394
6428 00:56:04.677900 Set Vref, RX VrefLevel [Byte0]: 51
6429 00:56:04.680921 [Byte1]: 59
6430 00:56:04.685208
6431 00:56:04.685283 Final RX Vref Byte 0 = 51 to rank0
6432 00:56:04.688355 Final RX Vref Byte 1 = 59 to rank0
6433 00:56:04.692013 Final RX Vref Byte 0 = 51 to rank1
6434 00:56:04.695540 Final RX Vref Byte 1 = 59 to rank1==
6435 00:56:04.698523 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 00:56:04.705030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 00:56:04.705102 ==
6438 00:56:04.705163 DQS Delay:
6439 00:56:04.708366 DQS0 = 40, DQS1 = 60
6440 00:56:04.708441 DQM Delay:
6441 00:56:04.708500 DQM0 = 6, DQM1 = 16
6442 00:56:04.711651 DQ Delay:
6443 00:56:04.714606 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6444 00:56:04.714703 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6445 00:56:04.717942 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6446 00:56:04.721632 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6447 00:56:04.724685
6448 00:56:04.724788
6449 00:56:04.731502 [DQSOSCAuto] RK0, (LSB)MR18= 0x9285, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6450 00:56:04.734712 CH0 RK0: MR19=C0C, MR18=9285
6451 00:56:04.741232 CH0_RK0: MR19=0xC0C, MR18=0x9285, DQSOSC=391, MR23=63, INC=386, DEC=257
6452 00:56:04.741304 ==
6453 00:56:04.744437 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 00:56:04.747827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 00:56:04.747902 ==
6456 00:56:04.750955 [Gating] SW mode calibration
6457 00:56:04.758023 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6458 00:56:04.764020 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6459 00:56:04.767414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 00:56:04.770634 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6461 00:56:04.777134 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 00:56:04.780480 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 00:56:04.784023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 00:56:04.790671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 00:56:04.794062 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 00:56:04.797144 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 00:56:04.804791 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 00:56:04.807331 Total UI for P1: 0, mck2ui 16
6469 00:56:04.810943 best dqsien dly found for B0: ( 0, 14, 24)
6470 00:56:04.811019 Total UI for P1: 0, mck2ui 16
6471 00:56:04.817186 best dqsien dly found for B1: ( 0, 14, 24)
6472 00:56:04.820301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6473 00:56:04.823299 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6474 00:56:04.823402
6475 00:56:04.826595 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 00:56:04.830232 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6477 00:56:04.833458 [Gating] SW calibration Done
6478 00:56:04.833534 ==
6479 00:56:04.836559 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 00:56:04.840043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 00:56:04.840126 ==
6482 00:56:04.842993 RX Vref Scan: 0
6483 00:56:04.843075
6484 00:56:04.846648 RX Vref 0 -> 0, step: 1
6485 00:56:04.846721
6486 00:56:04.846789 RX Delay -410 -> 252, step: 16
6487 00:56:04.853312 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6488 00:56:04.856825 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6489 00:56:04.859661 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6490 00:56:04.867021 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6491 00:56:04.869741 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6492 00:56:04.873086 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6493 00:56:04.876428 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6494 00:56:04.882997 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6495 00:56:04.886458 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6496 00:56:04.889523 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6497 00:56:04.892590 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6498 00:56:04.898978 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6499 00:56:04.902441 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6500 00:56:04.905934 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6501 00:56:04.912351 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6502 00:56:04.915534 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6503 00:56:04.915612 ==
6504 00:56:04.919086 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 00:56:04.922612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 00:56:04.922690 ==
6507 00:56:04.925408 DQS Delay:
6508 00:56:04.925485 DQS0 = 35, DQS1 = 51
6509 00:56:04.925548 DQM Delay:
6510 00:56:04.928885 DQM0 = 8, DQM1 = 9
6511 00:56:04.928966 DQ Delay:
6512 00:56:04.931769 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6513 00:56:04.935544 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6514 00:56:04.938654 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6515 00:56:04.941651 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6516 00:56:04.941729
6517 00:56:04.941799
6518 00:56:04.941860 ==
6519 00:56:04.945444 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 00:56:04.948495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 00:56:04.952055 ==
6522 00:56:04.952139
6523 00:56:04.952202
6524 00:56:04.952261 TX Vref Scan disable
6525 00:56:04.954815 == TX Byte 0 ==
6526 00:56:04.958215 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6527 00:56:04.961928 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6528 00:56:04.965243 == TX Byte 1 ==
6529 00:56:04.968310 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6530 00:56:04.971543 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6531 00:56:04.971612 ==
6532 00:56:04.974956 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 00:56:04.981335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 00:56:04.981411 ==
6535 00:56:04.981471
6536 00:56:04.981529
6537 00:56:04.981584 TX Vref Scan disable
6538 00:56:04.984625 == TX Byte 0 ==
6539 00:56:04.987781 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6540 00:56:04.991233 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6541 00:56:04.994722 == TX Byte 1 ==
6542 00:56:04.997509 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6543 00:56:05.000975 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6544 00:56:05.001047
6545 00:56:05.004349 [DATLAT]
6546 00:56:05.004420 Freq=400, CH0 RK1
6547 00:56:05.004481
6548 00:56:05.008190 DATLAT Default: 0xe
6549 00:56:05.008265 0, 0xFFFF, sum = 0
6550 00:56:05.010976 1, 0xFFFF, sum = 0
6551 00:56:05.011042 2, 0xFFFF, sum = 0
6552 00:56:05.014646 3, 0xFFFF, sum = 0
6553 00:56:05.014713 4, 0xFFFF, sum = 0
6554 00:56:05.017314 5, 0xFFFF, sum = 0
6555 00:56:05.017385 6, 0xFFFF, sum = 0
6556 00:56:05.020695 7, 0xFFFF, sum = 0
6557 00:56:05.020763 8, 0xFFFF, sum = 0
6558 00:56:05.024308 9, 0xFFFF, sum = 0
6559 00:56:05.027602 10, 0xFFFF, sum = 0
6560 00:56:05.027674 11, 0xFFFF, sum = 0
6561 00:56:05.030738 12, 0xFFFF, sum = 0
6562 00:56:05.030808 13, 0x0, sum = 1
6563 00:56:05.033912 14, 0x0, sum = 2
6564 00:56:05.033983 15, 0x0, sum = 3
6565 00:56:05.037140 16, 0x0, sum = 4
6566 00:56:05.037206 best_step = 14
6567 00:56:05.037264
6568 00:56:05.037320 ==
6569 00:56:05.040569 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 00:56:05.043958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 00:56:05.044025 ==
6572 00:56:05.047078 RX Vref Scan: 0
6573 00:56:05.047150
6574 00:56:05.050115 RX Vref 0 -> 0, step: 1
6575 00:56:05.050182
6576 00:56:05.050239 RX Delay -343 -> 252, step: 8
6577 00:56:05.059231 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6578 00:56:05.062924 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6579 00:56:05.065895 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6580 00:56:05.069382 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6581 00:56:05.075680 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6582 00:56:05.078890 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6583 00:56:05.081903 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6584 00:56:05.089006 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6585 00:56:05.091903 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6586 00:56:05.095158 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6587 00:56:05.098264 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6588 00:56:05.105221 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6589 00:56:05.108463 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6590 00:56:05.111979 iDelay=209, Bit 13, Center -40 (-287 ~ 208) 496
6591 00:56:05.114912 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6592 00:56:05.121474 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6593 00:56:05.121554 ==
6594 00:56:05.124780 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 00:56:05.128367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 00:56:05.128443 ==
6597 00:56:05.128512 DQS Delay:
6598 00:56:05.131354 DQS0 = 44, DQS1 = 60
6599 00:56:05.131459 DQM Delay:
6600 00:56:05.134941 DQM0 = 9, DQM1 = 15
6601 00:56:05.135007 DQ Delay:
6602 00:56:05.138251 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6603 00:56:05.141511 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6604 00:56:05.144665 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6605 00:56:05.147813 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6606 00:56:05.147880
6607 00:56:05.147946
6608 00:56:05.157946 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6609 00:56:05.158020 CH0 RK1: MR19=C0C, MR18=8E85
6610 00:56:05.164533 CH0_RK1: MR19=0xC0C, MR18=0x8E85, DQSOSC=392, MR23=63, INC=384, DEC=256
6611 00:56:05.167523 [RxdqsGatingPostProcess] freq 400
6612 00:56:05.174561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6613 00:56:05.177454 best DQS0 dly(2T, 0.5T) = (0, 10)
6614 00:56:05.180957 best DQS1 dly(2T, 0.5T) = (0, 10)
6615 00:56:05.184158 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6616 00:56:05.187255 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6617 00:56:05.190356 best DQS0 dly(2T, 0.5T) = (0, 10)
6618 00:56:05.193706 best DQS1 dly(2T, 0.5T) = (0, 10)
6619 00:56:05.197276 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6620 00:56:05.200242 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6621 00:56:05.203890 Pre-setting of DQS Precalculation
6622 00:56:05.206759 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6623 00:56:05.206827 ==
6624 00:56:05.209954 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 00:56:05.213559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 00:56:05.213632 ==
6627 00:56:05.220150 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6628 00:56:05.226513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6629 00:56:05.229931 [CA 0] Center 36 (8~64) winsize 57
6630 00:56:05.233465 [CA 1] Center 36 (8~64) winsize 57
6631 00:56:05.236539 [CA 2] Center 36 (8~64) winsize 57
6632 00:56:05.239958 [CA 3] Center 36 (8~64) winsize 57
6633 00:56:05.242902 [CA 4] Center 36 (8~64) winsize 57
6634 00:56:05.246399 [CA 5] Center 36 (8~64) winsize 57
6635 00:56:05.246472
6636 00:56:05.249746 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6637 00:56:05.249820
6638 00:56:05.252663 [CATrainingPosCal] consider 1 rank data
6639 00:56:05.256297 u2DelayCellTimex100 = 270/100 ps
6640 00:56:05.259739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 00:56:05.262632 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 00:56:05.265994 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 00:56:05.269330 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:56:05.272827 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:56:05.275726 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:56:05.275797
6647 00:56:05.282423 CA PerBit enable=1, Macro0, CA PI delay=36
6648 00:56:05.282501
6649 00:56:05.282570 [CBTSetCACLKResult] CA Dly = 36
6650 00:56:05.286115 CS Dly: 1 (0~32)
6651 00:56:05.286186 ==
6652 00:56:05.288825 Dram Type= 6, Freq= 0, CH_1, rank 1
6653 00:56:05.292433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 00:56:05.292505 ==
6655 00:56:05.298680 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6656 00:56:05.305729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6657 00:56:05.308682 [CA 0] Center 36 (8~64) winsize 57
6658 00:56:05.312338 [CA 1] Center 36 (8~64) winsize 57
6659 00:56:05.315256 [CA 2] Center 36 (8~64) winsize 57
6660 00:56:05.318524 [CA 3] Center 36 (8~64) winsize 57
6661 00:56:05.322256 [CA 4] Center 36 (8~64) winsize 57
6662 00:56:05.322342 [CA 5] Center 36 (8~64) winsize 57
6663 00:56:05.325300
6664 00:56:05.328807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6665 00:56:05.328891
6666 00:56:05.331990 [CATrainingPosCal] consider 2 rank data
6667 00:56:05.335352 u2DelayCellTimex100 = 270/100 ps
6668 00:56:05.338402 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 00:56:05.342104 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 00:56:05.345002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 00:56:05.348684 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 00:56:05.351511 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 00:56:05.355051 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 00:56:05.355127
6675 00:56:05.358422 CA PerBit enable=1, Macro0, CA PI delay=36
6676 00:56:05.361640
6677 00:56:05.361713 [CBTSetCACLKResult] CA Dly = 36
6678 00:56:05.364955 CS Dly: 1 (0~32)
6679 00:56:05.365021
6680 00:56:05.367990 ----->DramcWriteLeveling(PI) begin...
6681 00:56:05.368063 ==
6682 00:56:05.371554 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 00:56:05.374472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 00:56:05.374546 ==
6685 00:56:05.377864 Write leveling (Byte 0): 40 => 8
6686 00:56:05.380942 Write leveling (Byte 1): 40 => 8
6687 00:56:05.384693 DramcWriteLeveling(PI) end<-----
6688 00:56:05.384761
6689 00:56:05.384826 ==
6690 00:56:05.387560 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 00:56:05.391139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 00:56:05.394079 ==
6693 00:56:05.394146 [Gating] SW mode calibration
6694 00:56:05.404123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6695 00:56:05.407446 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6696 00:56:05.410721 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 00:56:05.417528 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6698 00:56:05.420615 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 00:56:05.424308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 00:56:05.430889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 00:56:05.433994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 00:56:05.436938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 00:56:05.444065 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6704 00:56:05.447334 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 00:56:05.450333 Total UI for P1: 0, mck2ui 16
6706 00:56:05.453868 best dqsien dly found for B0: ( 0, 14, 24)
6707 00:56:05.456744 Total UI for P1: 0, mck2ui 16
6708 00:56:05.460174 best dqsien dly found for B1: ( 0, 14, 24)
6709 00:56:05.463169 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6710 00:56:05.466536 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6711 00:56:05.466604
6712 00:56:05.470453 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 00:56:05.476333 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6714 00:56:05.476403 [Gating] SW calibration Done
6715 00:56:05.476464 ==
6716 00:56:05.479887 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 00:56:05.486553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 00:56:05.486628 ==
6719 00:56:05.486690 RX Vref Scan: 0
6720 00:56:05.486749
6721 00:56:05.489443 RX Vref 0 -> 0, step: 1
6722 00:56:05.489513
6723 00:56:05.493116 RX Delay -410 -> 252, step: 16
6724 00:56:05.495976 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6725 00:56:05.499557 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6726 00:56:05.505839 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6727 00:56:05.509294 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6728 00:56:05.512785 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6729 00:56:05.515720 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6730 00:56:05.522680 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6731 00:56:05.525610 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6732 00:56:05.529108 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6733 00:56:05.535571 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6734 00:56:05.539449 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6735 00:56:05.542090 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6736 00:56:05.545738 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6737 00:56:05.552246 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6738 00:56:05.555505 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6739 00:56:05.558623 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6740 00:56:05.558707 ==
6741 00:56:05.562345 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 00:56:05.568645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 00:56:05.568727 ==
6744 00:56:05.568791 DQS Delay:
6745 00:56:05.571806 DQS0 = 35, DQS1 = 51
6746 00:56:05.571878 DQM Delay:
6747 00:56:05.571947 DQM0 = 6, DQM1 = 15
6748 00:56:05.575633 DQ Delay:
6749 00:56:05.578866 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6750 00:56:05.578962 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6751 00:56:05.581753 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6752 00:56:05.585420 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =16
6753 00:56:05.585496
6754 00:56:05.588407
6755 00:56:05.588520 ==
6756 00:56:05.591748 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 00:56:05.595198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 00:56:05.595276 ==
6759 00:56:05.595340
6760 00:56:05.595446
6761 00:56:05.598164 TX Vref Scan disable
6762 00:56:05.598231 == TX Byte 0 ==
6763 00:56:05.602010 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 00:56:05.608279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 00:56:05.608362 == TX Byte 1 ==
6766 00:56:05.611447 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 00:56:05.618013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 00:56:05.618099 ==
6769 00:56:05.621210 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 00:56:05.624513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 00:56:05.624631 ==
6772 00:56:05.624699
6773 00:56:05.624758
6774 00:56:05.627837 TX Vref Scan disable
6775 00:56:05.627907 == TX Byte 0 ==
6776 00:56:05.634306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 00:56:05.637892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 00:56:05.637968 == TX Byte 1 ==
6779 00:56:05.644736 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6780 00:56:05.647690 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6781 00:56:05.647765
6782 00:56:05.647827 [DATLAT]
6783 00:56:05.650873 Freq=400, CH1 RK0
6784 00:56:05.650942
6785 00:56:05.651012 DATLAT Default: 0xf
6786 00:56:05.654249 0, 0xFFFF, sum = 0
6787 00:56:05.654318 1, 0xFFFF, sum = 0
6788 00:56:05.657384 2, 0xFFFF, sum = 0
6789 00:56:05.657454 3, 0xFFFF, sum = 0
6790 00:56:05.661057 4, 0xFFFF, sum = 0
6791 00:56:05.661131 5, 0xFFFF, sum = 0
6792 00:56:05.663892 6, 0xFFFF, sum = 0
6793 00:56:05.663959 7, 0xFFFF, sum = 0
6794 00:56:05.667236 8, 0xFFFF, sum = 0
6795 00:56:05.667331 9, 0xFFFF, sum = 0
6796 00:56:05.670672 10, 0xFFFF, sum = 0
6797 00:56:05.673979 11, 0xFFFF, sum = 0
6798 00:56:05.674047 12, 0xFFFF, sum = 0
6799 00:56:05.677503 13, 0x0, sum = 1
6800 00:56:05.677570 14, 0x0, sum = 2
6801 00:56:05.680422 15, 0x0, sum = 3
6802 00:56:05.680494 16, 0x0, sum = 4
6803 00:56:05.680552 best_step = 14
6804 00:56:05.680609
6805 00:56:05.683864 ==
6806 00:56:05.687061 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 00:56:05.690434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 00:56:05.690506 ==
6809 00:56:05.690573 RX Vref Scan: 1
6810 00:56:05.690631
6811 00:56:05.693716 RX Vref 0 -> 0, step: 1
6812 00:56:05.693781
6813 00:56:05.696751 RX Delay -343 -> 252, step: 8
6814 00:56:05.696828
6815 00:56:05.699989 Set Vref, RX VrefLevel [Byte0]: 51
6816 00:56:05.703496 [Byte1]: 52
6817 00:56:05.707205
6818 00:56:05.707303 Final RX Vref Byte 0 = 51 to rank0
6819 00:56:05.710324 Final RX Vref Byte 1 = 52 to rank0
6820 00:56:05.713945 Final RX Vref Byte 0 = 51 to rank1
6821 00:56:05.717178 Final RX Vref Byte 1 = 52 to rank1==
6822 00:56:05.720603 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 00:56:05.726875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 00:56:05.726979 ==
6825 00:56:05.727070 DQS Delay:
6826 00:56:05.730511 DQS0 = 44, DQS1 = 52
6827 00:56:05.730585 DQM Delay:
6828 00:56:05.733379 DQM0 = 11, DQM1 = 11
6829 00:56:05.733462 DQ Delay:
6830 00:56:05.736758 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6831 00:56:05.740172 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6832 00:56:05.740254 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6833 00:56:05.747237 DQ12 =20, DQ13 =24, DQ14 =16, DQ15 =16
6834 00:56:05.747318
6835 00:56:05.747391
6836 00:56:05.753194 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f95, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6837 00:56:05.756905 CH1 RK0: MR19=C0C, MR18=6F95
6838 00:56:05.763528 CH1_RK0: MR19=0xC0C, MR18=0x6F95, DQSOSC=391, MR23=63, INC=386, DEC=257
6839 00:56:05.763610 ==
6840 00:56:05.766859 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 00:56:05.769770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 00:56:05.769852 ==
6843 00:56:05.773208 [Gating] SW mode calibration
6844 00:56:05.779889 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6845 00:56:05.786679 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6846 00:56:05.789734 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 00:56:05.793034 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6848 00:56:05.799483 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 00:56:05.802979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 00:56:05.806286 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 00:56:05.812769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 00:56:05.816117 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 00:56:05.819465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6854 00:56:05.825807 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 00:56:05.829348 Total UI for P1: 0, mck2ui 16
6856 00:56:05.832517 best dqsien dly found for B0: ( 0, 14, 24)
6857 00:56:05.832598 Total UI for P1: 0, mck2ui 16
6858 00:56:05.839030 best dqsien dly found for B1: ( 0, 14, 24)
6859 00:56:05.842185 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6860 00:56:05.845767 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6861 00:56:05.845848
6862 00:56:05.849651 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 00:56:05.852129 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6864 00:56:05.855707 [Gating] SW calibration Done
6865 00:56:05.855787 ==
6866 00:56:05.858895 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 00:56:05.861782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 00:56:05.861863 ==
6869 00:56:05.865307 RX Vref Scan: 0
6870 00:56:05.865387
6871 00:56:05.868769 RX Vref 0 -> 0, step: 1
6872 00:56:05.868850
6873 00:56:05.868913 RX Delay -410 -> 252, step: 16
6874 00:56:05.875163 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6875 00:56:05.879184 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6876 00:56:05.881788 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6877 00:56:05.888511 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6878 00:56:05.892266 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6879 00:56:05.895214 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6880 00:56:05.898604 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6881 00:56:05.905036 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6882 00:56:05.908270 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6883 00:56:05.911827 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6884 00:56:05.914934 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6885 00:56:05.921773 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6886 00:56:05.924659 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6887 00:56:05.928351 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6888 00:56:05.931014 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6889 00:56:05.937658 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6890 00:56:05.937736 ==
6891 00:56:05.941216 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 00:56:05.944685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 00:56:05.944771 ==
6894 00:56:05.947887 DQS Delay:
6895 00:56:05.947968 DQS0 = 43, DQS1 = 51
6896 00:56:05.948030 DQM Delay:
6897 00:56:05.950822 DQM0 = 9, DQM1 = 14
6898 00:56:05.950894 DQ Delay:
6899 00:56:05.954078 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6900 00:56:05.957990 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6901 00:56:05.960830 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6902 00:56:05.963940 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6903 00:56:05.964021
6904 00:56:05.964083
6905 00:56:05.964141 ==
6906 00:56:05.967643 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 00:56:05.970826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 00:56:05.973759 ==
6909 00:56:05.973832
6910 00:56:05.973891
6911 00:56:05.973947 TX Vref Scan disable
6912 00:56:05.977350 == TX Byte 0 ==
6913 00:56:05.980735 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6914 00:56:05.984017 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6915 00:56:05.987089 == TX Byte 1 ==
6916 00:56:05.990454 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6917 00:56:05.994135 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6918 00:56:05.994208 ==
6919 00:56:05.996849 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 00:56:06.000408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 00:56:06.003898 ==
6922 00:56:06.003970
6923 00:56:06.004029
6924 00:56:06.004086 TX Vref Scan disable
6925 00:56:06.006888 == TX Byte 0 ==
6926 00:56:06.010280 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6927 00:56:06.013667 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6928 00:56:06.016554 == TX Byte 1 ==
6929 00:56:06.019968 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6930 00:56:06.023577 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6931 00:56:06.023651
6932 00:56:06.027065 [DATLAT]
6933 00:56:06.027131 Freq=400, CH1 RK1
6934 00:56:06.027189
6935 00:56:06.029906 DATLAT Default: 0xe
6936 00:56:06.029971 0, 0xFFFF, sum = 0
6937 00:56:06.033398 1, 0xFFFF, sum = 0
6938 00:56:06.033467 2, 0xFFFF, sum = 0
6939 00:56:06.036420 3, 0xFFFF, sum = 0
6940 00:56:06.036491 4, 0xFFFF, sum = 0
6941 00:56:06.040049 5, 0xFFFF, sum = 0
6942 00:56:06.040115 6, 0xFFFF, sum = 0
6943 00:56:06.042910 7, 0xFFFF, sum = 0
6944 00:56:06.042974 8, 0xFFFF, sum = 0
6945 00:56:06.046496 9, 0xFFFF, sum = 0
6946 00:56:06.046572 10, 0xFFFF, sum = 0
6947 00:56:06.049687 11, 0xFFFF, sum = 0
6948 00:56:06.052962 12, 0xFFFF, sum = 0
6949 00:56:06.053034 13, 0x0, sum = 1
6950 00:56:06.053096 14, 0x0, sum = 2
6951 00:56:06.056402 15, 0x0, sum = 3
6952 00:56:06.056476 16, 0x0, sum = 4
6953 00:56:06.060243 best_step = 14
6954 00:56:06.060319
6955 00:56:06.060380 ==
6956 00:56:06.062952 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 00:56:06.065986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 00:56:06.066061 ==
6959 00:56:06.069216 RX Vref Scan: 0
6960 00:56:06.069301
6961 00:56:06.072504 RX Vref 0 -> 0, step: 1
6962 00:56:06.072582
6963 00:56:06.072647 RX Delay -343 -> 252, step: 8
6964 00:56:06.081189 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6965 00:56:06.084343 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6966 00:56:06.087866 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6967 00:56:06.094535 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6968 00:56:06.097820 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6969 00:56:06.100954 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6970 00:56:06.104377 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6971 00:56:06.110989 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6972 00:56:06.114188 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6973 00:56:06.117664 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6974 00:56:06.121091 iDelay=217, Bit 10, Center -36 (-279 ~ 208) 488
6975 00:56:06.127570 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6976 00:56:06.130405 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6977 00:56:06.134136 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6978 00:56:06.137503 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6979 00:56:06.143837 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6980 00:56:06.143918 ==
6981 00:56:06.147546 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 00:56:06.150409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 00:56:06.150482 ==
6984 00:56:06.150542 DQS Delay:
6985 00:56:06.153741 DQS0 = 48, DQS1 = 52
6986 00:56:06.153812 DQM Delay:
6987 00:56:06.157413 DQM0 = 12, DQM1 = 11
6988 00:56:06.157486 DQ Delay:
6989 00:56:06.160290 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6990 00:56:06.163414 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6991 00:56:06.166615 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6992 00:56:06.170524 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6993 00:56:06.170604
6994 00:56:06.170666
6995 00:56:06.180129 [DQSOSCAuto] RK1, (LSB)MR18= 0x77ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6996 00:56:06.180209 CH1 RK1: MR19=C0C, MR18=77AE
6997 00:56:06.186861 CH1_RK1: MR19=0xC0C, MR18=0x77AE, DQSOSC=388, MR23=63, INC=392, DEC=261
6998 00:56:06.189796 [RxdqsGatingPostProcess] freq 400
6999 00:56:06.196493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7000 00:56:06.199858 best DQS0 dly(2T, 0.5T) = (0, 10)
7001 00:56:06.203042 best DQS1 dly(2T, 0.5T) = (0, 10)
7002 00:56:06.206140 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7003 00:56:06.209486 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7004 00:56:06.212990 best DQS0 dly(2T, 0.5T) = (0, 10)
7005 00:56:06.216421 best DQS1 dly(2T, 0.5T) = (0, 10)
7006 00:56:06.219257 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7007 00:56:06.222616 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7008 00:56:06.222696 Pre-setting of DQS Precalculation
7009 00:56:06.229110 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7010 00:56:06.236171 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7011 00:56:06.242258 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7012 00:56:06.242342
7013 00:56:06.242407
7014 00:56:06.245618 [Calibration Summary] 800 Mbps
7015 00:56:06.249087 CH 0, Rank 0
7016 00:56:06.249169 SW Impedance : PASS
7017 00:56:06.252592 DUTY Scan : NO K
7018 00:56:06.255375 ZQ Calibration : PASS
7019 00:56:06.255457 Jitter Meter : NO K
7020 00:56:06.258945 CBT Training : PASS
7021 00:56:06.261883 Write leveling : PASS
7022 00:56:06.261965 RX DQS gating : PASS
7023 00:56:06.265389 RX DQ/DQS(RDDQC) : PASS
7024 00:56:06.268878 TX DQ/DQS : PASS
7025 00:56:06.268960 RX DATLAT : PASS
7026 00:56:06.272181 RX DQ/DQS(Engine): PASS
7027 00:56:06.275064 TX OE : NO K
7028 00:56:06.275145 All Pass.
7029 00:56:06.275210
7030 00:56:06.275270 CH 0, Rank 1
7031 00:56:06.278517 SW Impedance : PASS
7032 00:56:06.281643 DUTY Scan : NO K
7033 00:56:06.281724 ZQ Calibration : PASS
7034 00:56:06.285152 Jitter Meter : NO K
7035 00:56:06.288525 CBT Training : PASS
7036 00:56:06.288606 Write leveling : NO K
7037 00:56:06.292421 RX DQS gating : PASS
7038 00:56:06.292502 RX DQ/DQS(RDDQC) : PASS
7039 00:56:06.294982 TX DQ/DQS : PASS
7040 00:56:06.298220 RX DATLAT : PASS
7041 00:56:06.298301 RX DQ/DQS(Engine): PASS
7042 00:56:06.301859 TX OE : NO K
7043 00:56:06.301941 All Pass.
7044 00:56:06.302006
7045 00:56:06.304759 CH 1, Rank 0
7046 00:56:06.304840 SW Impedance : PASS
7047 00:56:06.308094 DUTY Scan : NO K
7048 00:56:06.311313 ZQ Calibration : PASS
7049 00:56:06.311434 Jitter Meter : NO K
7050 00:56:06.314891 CBT Training : PASS
7051 00:56:06.317968 Write leveling : PASS
7052 00:56:06.318049 RX DQS gating : PASS
7053 00:56:06.321400 RX DQ/DQS(RDDQC) : PASS
7054 00:56:06.324408 TX DQ/DQS : PASS
7055 00:56:06.324490 RX DATLAT : PASS
7056 00:56:06.327799 RX DQ/DQS(Engine): PASS
7057 00:56:06.331055 TX OE : NO K
7058 00:56:06.331136 All Pass.
7059 00:56:06.331201
7060 00:56:06.331262 CH 1, Rank 1
7061 00:56:06.334234 SW Impedance : PASS
7062 00:56:06.337797 DUTY Scan : NO K
7063 00:56:06.337879 ZQ Calibration : PASS
7064 00:56:06.341530 Jitter Meter : NO K
7065 00:56:06.344240 CBT Training : PASS
7066 00:56:06.344360 Write leveling : NO K
7067 00:56:06.347903 RX DQS gating : PASS
7068 00:56:06.350976 RX DQ/DQS(RDDQC) : PASS
7069 00:56:06.351057 TX DQ/DQS : PASS
7070 00:56:06.354289 RX DATLAT : PASS
7071 00:56:06.357657 RX DQ/DQS(Engine): PASS
7072 00:56:06.357738 TX OE : NO K
7073 00:56:06.361097 All Pass.
7074 00:56:06.361177
7075 00:56:06.361242 DramC Write-DBI off
7076 00:56:06.364232 PER_BANK_REFRESH: Hybrid Mode
7077 00:56:06.364314 TX_TRACKING: ON
7078 00:56:06.373902 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7079 00:56:06.377565 [FAST_K] Save calibration result to emmc
7080 00:56:06.380760 dramc_set_vcore_voltage set vcore to 725000
7081 00:56:06.383741 Read voltage for 1600, 0
7082 00:56:06.383848 Vio18 = 0
7083 00:56:06.387301 Vcore = 725000
7084 00:56:06.387429 Vdram = 0
7085 00:56:06.387523 Vddq = 0
7086 00:56:06.390323 Vmddr = 0
7087 00:56:06.393629 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7088 00:56:06.400284 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7089 00:56:06.400365 MEM_TYPE=3, freq_sel=13
7090 00:56:06.403529 sv_algorithm_assistance_LP4_3733
7091 00:56:06.410718 ============ PULL DRAM RESETB DOWN ============
7092 00:56:06.413340 ========== PULL DRAM RESETB DOWN end =========
7093 00:56:06.417368 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7094 00:56:06.420156 ===================================
7095 00:56:06.423521 LPDDR4 DRAM CONFIGURATION
7096 00:56:06.426406 ===================================
7097 00:56:06.429702 EX_ROW_EN[0] = 0x0
7098 00:56:06.429780 EX_ROW_EN[1] = 0x0
7099 00:56:06.433359 LP4Y_EN = 0x0
7100 00:56:06.433439 WORK_FSP = 0x1
7101 00:56:06.436522 WL = 0x5
7102 00:56:06.436596 RL = 0x5
7103 00:56:06.439724 BL = 0x2
7104 00:56:06.439826 RPST = 0x0
7105 00:56:06.443197 RD_PRE = 0x0
7106 00:56:06.443277 WR_PRE = 0x1
7107 00:56:06.446585 WR_PST = 0x1
7108 00:56:06.446658 DBI_WR = 0x0
7109 00:56:06.449585 DBI_RD = 0x0
7110 00:56:06.449659 OTF = 0x1
7111 00:56:06.453059 ===================================
7112 00:56:06.456556 ===================================
7113 00:56:06.459455 ANA top config
7114 00:56:06.462893 ===================================
7115 00:56:06.466264 DLL_ASYNC_EN = 0
7116 00:56:06.466337 ALL_SLAVE_EN = 0
7117 00:56:06.469267 NEW_RANK_MODE = 1
7118 00:56:06.472695 DLL_IDLE_MODE = 1
7119 00:56:06.476081 LP45_APHY_COMB_EN = 1
7120 00:56:06.479084 TX_ODT_DIS = 0
7121 00:56:06.479160 NEW_8X_MODE = 1
7122 00:56:06.482438 ===================================
7123 00:56:06.486072 ===================================
7124 00:56:06.489350 data_rate = 3200
7125 00:56:06.492822 CKR = 1
7126 00:56:06.495515 DQ_P2S_RATIO = 8
7127 00:56:06.498860 ===================================
7128 00:56:06.502436 CA_P2S_RATIO = 8
7129 00:56:06.505330 DQ_CA_OPEN = 0
7130 00:56:06.505427 DQ_SEMI_OPEN = 0
7131 00:56:06.508768 CA_SEMI_OPEN = 0
7132 00:56:06.512220 CA_FULL_RATE = 0
7133 00:56:06.515514 DQ_CKDIV4_EN = 0
7134 00:56:06.519482 CA_CKDIV4_EN = 0
7135 00:56:06.521995 CA_PREDIV_EN = 0
7136 00:56:06.525339 PH8_DLY = 12
7137 00:56:06.525418 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7138 00:56:06.528433 DQ_AAMCK_DIV = 4
7139 00:56:06.532037 CA_AAMCK_DIV = 4
7140 00:56:06.535258 CA_ADMCK_DIV = 4
7141 00:56:06.538309 DQ_TRACK_CA_EN = 0
7142 00:56:06.541819 CA_PICK = 1600
7143 00:56:06.545427 CA_MCKIO = 1600
7144 00:56:06.545502 MCKIO_SEMI = 0
7145 00:56:06.548402 PLL_FREQ = 3068
7146 00:56:06.551630 DQ_UI_PI_RATIO = 32
7147 00:56:06.555457 CA_UI_PI_RATIO = 0
7148 00:56:06.558636 ===================================
7149 00:56:06.561537 ===================================
7150 00:56:06.565077 memory_type:LPDDR4
7151 00:56:06.565148 GP_NUM : 10
7152 00:56:06.568366 SRAM_EN : 1
7153 00:56:06.571408 MD32_EN : 0
7154 00:56:06.574749 ===================================
7155 00:56:06.574818 [ANA_INIT] >>>>>>>>>>>>>>
7156 00:56:06.577698 <<<<<< [CONFIGURE PHASE]: ANA_TX
7157 00:56:06.581143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7158 00:56:06.584729 ===================================
7159 00:56:06.587937 data_rate = 3200,PCW = 0X7600
7160 00:56:06.590752 ===================================
7161 00:56:06.594171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7162 00:56:06.601057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 00:56:06.607748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7164 00:56:06.610815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7165 00:56:06.614049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7166 00:56:06.617775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7167 00:56:06.620606 [ANA_INIT] flow start
7168 00:56:06.620688 [ANA_INIT] PLL >>>>>>>>
7169 00:56:06.624060 [ANA_INIT] PLL <<<<<<<<
7170 00:56:06.627235 [ANA_INIT] MIDPI >>>>>>>>
7171 00:56:06.627337 [ANA_INIT] MIDPI <<<<<<<<
7172 00:56:06.630293 [ANA_INIT] DLL >>>>>>>>
7173 00:56:06.633681 [ANA_INIT] DLL <<<<<<<<
7174 00:56:06.633793 [ANA_INIT] flow end
7175 00:56:06.640128 ============ LP4 DIFF to SE enter ============
7176 00:56:06.643931 ============ LP4 DIFF to SE exit ============
7177 00:56:06.646806 [ANA_INIT] <<<<<<<<<<<<<
7178 00:56:06.650264 [Flow] Enable top DCM control >>>>>
7179 00:56:06.653155 [Flow] Enable top DCM control <<<<<
7180 00:56:06.656525 Enable DLL master slave shuffle
7181 00:56:06.659928 ==============================================================
7182 00:56:06.663470 Gating Mode config
7183 00:56:06.666585 ==============================================================
7184 00:56:06.670107 Config description:
7185 00:56:06.679984 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7186 00:56:06.686789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7187 00:56:06.690051 SELPH_MODE 0: By rank 1: By Phase
7188 00:56:06.696397 ==============================================================
7189 00:56:06.700059 GAT_TRACK_EN = 1
7190 00:56:06.702662 RX_GATING_MODE = 2
7191 00:56:06.706116 RX_GATING_TRACK_MODE = 2
7192 00:56:06.709561 SELPH_MODE = 1
7193 00:56:06.712484 PICG_EARLY_EN = 1
7194 00:56:06.715985 VALID_LAT_VALUE = 1
7195 00:56:06.719441 ==============================================================
7196 00:56:06.722900 Enter into Gating configuration >>>>
7197 00:56:06.726019 Exit from Gating configuration <<<<
7198 00:56:06.729361 Enter into DVFS_PRE_config >>>>>
7199 00:56:06.742244 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7200 00:56:06.745365 Exit from DVFS_PRE_config <<<<<
7201 00:56:06.745455 Enter into PICG configuration >>>>
7202 00:56:06.748785 Exit from PICG configuration <<<<
7203 00:56:06.751720 [RX_INPUT] configuration >>>>>
7204 00:56:06.755235 [RX_INPUT] configuration <<<<<
7205 00:56:06.762315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7206 00:56:06.765147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7207 00:56:06.771899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 00:56:06.778232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 00:56:06.784845 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7210 00:56:06.791549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7211 00:56:06.794766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7212 00:56:06.797874 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7213 00:56:06.804499 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7214 00:56:06.807874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7215 00:56:06.811282 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7216 00:56:06.817534 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 00:56:06.820896 ===================================
7218 00:56:06.820990 LPDDR4 DRAM CONFIGURATION
7219 00:56:06.824677 ===================================
7220 00:56:06.827700 EX_ROW_EN[0] = 0x0
7221 00:56:06.827803 EX_ROW_EN[1] = 0x0
7222 00:56:06.831320 LP4Y_EN = 0x0
7223 00:56:06.831445 WORK_FSP = 0x1
7224 00:56:06.834151 WL = 0x5
7225 00:56:06.837473 RL = 0x5
7226 00:56:06.837595 BL = 0x2
7227 00:56:06.840762 RPST = 0x0
7228 00:56:06.840897 RD_PRE = 0x0
7229 00:56:06.843964 WR_PRE = 0x1
7230 00:56:06.844115 WR_PST = 0x1
7231 00:56:06.847523 DBI_WR = 0x0
7232 00:56:06.847676 DBI_RD = 0x0
7233 00:56:06.850819 OTF = 0x1
7234 00:56:06.855173 ===================================
7235 00:56:06.857321 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7236 00:56:06.860894 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7237 00:56:06.867539 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 00:56:06.870558 ===================================
7239 00:56:06.870979 LPDDR4 DRAM CONFIGURATION
7240 00:56:06.874005 ===================================
7241 00:56:06.877114 EX_ROW_EN[0] = 0x10
7242 00:56:06.880476 EX_ROW_EN[1] = 0x0
7243 00:56:06.880776 LP4Y_EN = 0x0
7244 00:56:06.883481 WORK_FSP = 0x1
7245 00:56:06.883709 WL = 0x5
7246 00:56:06.886908 RL = 0x5
7247 00:56:06.887132 BL = 0x2
7248 00:56:06.890447 RPST = 0x0
7249 00:56:06.890629 RD_PRE = 0x0
7250 00:56:06.893145 WR_PRE = 0x1
7251 00:56:06.893324 WR_PST = 0x1
7252 00:56:06.896586 DBI_WR = 0x0
7253 00:56:06.896819 DBI_RD = 0x0
7254 00:56:06.900039 OTF = 0x1
7255 00:56:06.903293 ===================================
7256 00:56:06.910023 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7257 00:56:06.910175 ==
7258 00:56:06.913243 Dram Type= 6, Freq= 0, CH_0, rank 0
7259 00:56:06.916200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7260 00:56:06.916356 ==
7261 00:56:06.919541 [Duty_Offset_Calibration]
7262 00:56:06.919693 B0:2 B1:0 CA:4
7263 00:56:06.919813
7264 00:56:06.922886 [DutyScan_Calibration_Flow] k_type=0
7265 00:56:06.933260
7266 00:56:06.933418 ==CLK 0==
7267 00:56:06.936061 Final CLK duty delay cell = -4
7268 00:56:06.940000 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7269 00:56:06.942800 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7270 00:56:06.946064 [-4] AVG Duty = 4937%(X100)
7271 00:56:06.946215
7272 00:56:06.949386 CH0 CLK Duty spec in!! Max-Min= 187%
7273 00:56:06.953119 [DutyScan_Calibration_Flow] ====Done====
7274 00:56:06.953272
7275 00:56:06.955956 [DutyScan_Calibration_Flow] k_type=1
7276 00:56:06.972926
7277 00:56:06.973148 ==DQS 0 ==
7278 00:56:06.976333 Final DQS duty delay cell = 0
7279 00:56:06.979710 [0] MAX Duty = 5218%(X100), DQS PI = 22
7280 00:56:06.982840 [0] MIN Duty = 5093%(X100), DQS PI = 4
7281 00:56:06.986358 [0] AVG Duty = 5155%(X100)
7282 00:56:06.986612
7283 00:56:06.986769 ==DQS 1 ==
7284 00:56:06.990033 Final DQS duty delay cell = 0
7285 00:56:06.993212 [0] MAX Duty = 5187%(X100), DQS PI = 2
7286 00:56:06.996655 [0] MIN Duty = 4969%(X100), DQS PI = 12
7287 00:56:07.000138 [0] AVG Duty = 5078%(X100)
7288 00:56:07.000530
7289 00:56:07.003436 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7290 00:56:07.003931
7291 00:56:07.006502 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7292 00:56:07.009416 [DutyScan_Calibration_Flow] ====Done====
7293 00:56:07.009917
7294 00:56:07.013009 [DutyScan_Calibration_Flow] k_type=3
7295 00:56:07.030962
7296 00:56:07.031529 ==DQM 0 ==
7297 00:56:07.034121 Final DQM duty delay cell = 0
7298 00:56:07.036962 [0] MAX Duty = 5124%(X100), DQS PI = 22
7299 00:56:07.040270 [0] MIN Duty = 4844%(X100), DQS PI = 56
7300 00:56:07.043706 [0] AVG Duty = 4984%(X100)
7301 00:56:07.044124
7302 00:56:07.044465 ==DQM 1 ==
7303 00:56:07.046773 Final DQM duty delay cell = 0
7304 00:56:07.050159 [0] MAX Duty = 5000%(X100), DQS PI = 2
7305 00:56:07.053552 [0] MIN Duty = 4844%(X100), DQS PI = 14
7306 00:56:07.057029 [0] AVG Duty = 4922%(X100)
7307 00:56:07.057590
7308 00:56:07.059908 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7309 00:56:07.060415
7310 00:56:07.063541 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7311 00:56:07.066796 [DutyScan_Calibration_Flow] ====Done====
7312 00:56:07.067219
7313 00:56:07.070206 [DutyScan_Calibration_Flow] k_type=2
7314 00:56:07.087775
7315 00:56:07.088287 ==DQ 0 ==
7316 00:56:07.091172 Final DQ duty delay cell = 0
7317 00:56:07.094232 [0] MAX Duty = 5156%(X100), DQS PI = 22
7318 00:56:07.098025 [0] MIN Duty = 4938%(X100), DQS PI = 12
7319 00:56:07.100408 [0] AVG Duty = 5047%(X100)
7320 00:56:07.100834
7321 00:56:07.101161 ==DQ 1 ==
7322 00:56:07.104029 Final DQ duty delay cell = 0
7323 00:56:07.107562 [0] MAX Duty = 5187%(X100), DQS PI = 4
7324 00:56:07.111039 [0] MIN Duty = 4907%(X100), DQS PI = 32
7325 00:56:07.113919 [0] AVG Duty = 5047%(X100)
7326 00:56:07.114332
7327 00:56:07.117155 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7328 00:56:07.117638
7329 00:56:07.120433 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7330 00:56:07.123843 [DutyScan_Calibration_Flow] ====Done====
7331 00:56:07.124257 ==
7332 00:56:07.127125 Dram Type= 6, Freq= 0, CH_1, rank 0
7333 00:56:07.130204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 00:56:07.130620 ==
7335 00:56:07.133519 [Duty_Offset_Calibration]
7336 00:56:07.133929 B0:0 B1:-1 CA:3
7337 00:56:07.134257
7338 00:56:07.136831 [DutyScan_Calibration_Flow] k_type=0
7339 00:56:07.147567
7340 00:56:07.148068 ==CLK 0==
7341 00:56:07.150952 Final CLK duty delay cell = -4
7342 00:56:07.153547 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7343 00:56:07.157036 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7344 00:56:07.161161 [-4] AVG Duty = 4937%(X100)
7345 00:56:07.161871
7346 00:56:07.163605 CH1 CLK Duty spec in!! Max-Min= 249%
7347 00:56:07.166468 [DutyScan_Calibration_Flow] ====Done====
7348 00:56:07.166879
7349 00:56:07.170045 [DutyScan_Calibration_Flow] k_type=1
7350 00:56:07.186726
7351 00:56:07.187227 ==DQS 0 ==
7352 00:56:07.189719 Final DQS duty delay cell = 0
7353 00:56:07.192830 [0] MAX Duty = 5187%(X100), DQS PI = 52
7354 00:56:07.195953 [0] MIN Duty = 4969%(X100), DQS PI = 6
7355 00:56:07.199580 [0] AVG Duty = 5078%(X100)
7356 00:56:07.200055
7357 00:56:07.200386 ==DQS 1 ==
7358 00:56:07.202619 Final DQS duty delay cell = -4
7359 00:56:07.205987 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7360 00:56:07.209498 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7361 00:56:07.212444 [-4] AVG Duty = 4906%(X100)
7362 00:56:07.213050
7363 00:56:07.215538 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7364 00:56:07.215953
7365 00:56:07.219200 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7366 00:56:07.222240 [DutyScan_Calibration_Flow] ====Done====
7367 00:56:07.222652
7368 00:56:07.225237 [DutyScan_Calibration_Flow] k_type=3
7369 00:56:07.244142
7370 00:56:07.244642 ==DQM 0 ==
7371 00:56:07.246611 Final DQM duty delay cell = 0
7372 00:56:07.250271 [0] MAX Duty = 5031%(X100), DQS PI = 34
7373 00:56:07.253603 [0] MIN Duty = 4782%(X100), DQS PI = 8
7374 00:56:07.256438 [0] AVG Duty = 4906%(X100)
7375 00:56:07.256849
7376 00:56:07.257177 ==DQM 1 ==
7377 00:56:07.259905 Final DQM duty delay cell = 0
7378 00:56:07.263831 [0] MAX Duty = 5000%(X100), DQS PI = 16
7379 00:56:07.266628 [0] MIN Duty = 4813%(X100), DQS PI = 28
7380 00:56:07.270038 [0] AVG Duty = 4906%(X100)
7381 00:56:07.270445
7382 00:56:07.273388 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7383 00:56:07.273813
7384 00:56:07.276592 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7385 00:56:07.279764 [DutyScan_Calibration_Flow] ====Done====
7386 00:56:07.280308
7387 00:56:07.283032 [DutyScan_Calibration_Flow] k_type=2
7388 00:56:07.300528
7389 00:56:07.301009 ==DQ 0 ==
7390 00:56:07.303825 Final DQ duty delay cell = 0
7391 00:56:07.306838 [0] MAX Duty = 5187%(X100), DQS PI = 0
7392 00:56:07.310531 [0] MIN Duty = 5031%(X100), DQS PI = 6
7393 00:56:07.311054 [0] AVG Duty = 5109%(X100)
7394 00:56:07.313896
7395 00:56:07.314304 ==DQ 1 ==
7396 00:56:07.316880 Final DQ duty delay cell = 0
7397 00:56:07.320182 [0] MAX Duty = 5031%(X100), DQS PI = 0
7398 00:56:07.323241 [0] MIN Duty = 4844%(X100), DQS PI = 28
7399 00:56:07.323696 [0] AVG Duty = 4937%(X100)
7400 00:56:07.324029
7401 00:56:07.326779 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7402 00:56:07.329902
7403 00:56:07.333323 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7404 00:56:07.336631 [DutyScan_Calibration_Flow] ====Done====
7405 00:56:07.339883 nWR fixed to 30
7406 00:56:07.340300 [ModeRegInit_LP4] CH0 RK0
7407 00:56:07.343167 [ModeRegInit_LP4] CH0 RK1
7408 00:56:07.347175 [ModeRegInit_LP4] CH1 RK0
7409 00:56:07.349780 [ModeRegInit_LP4] CH1 RK1
7410 00:56:07.350201 match AC timing 5
7411 00:56:07.356756 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7412 00:56:07.360068 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7413 00:56:07.362883 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7414 00:56:07.369886 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7415 00:56:07.372588 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7416 00:56:07.373004 [MiockJmeterHQA]
7417 00:56:07.373336
7418 00:56:07.376019 [DramcMiockJmeter] u1RxGatingPI = 0
7419 00:56:07.379489 0 : 4363, 4137
7420 00:56:07.380014 4 : 4252, 4027
7421 00:56:07.383069 8 : 4363, 4138
7422 00:56:07.383605 12 : 4363, 4138
7423 00:56:07.383952 16 : 4252, 4027
7424 00:56:07.386132 20 : 4363, 4137
7425 00:56:07.386552 24 : 4252, 4026
7426 00:56:07.389267 28 : 4252, 4027
7427 00:56:07.389774 32 : 4252, 4027
7428 00:56:07.393011 36 : 4253, 4026
7429 00:56:07.393430 40 : 4363, 4138
7430 00:56:07.396189 44 : 4252, 4027
7431 00:56:07.396626 48 : 4363, 4137
7432 00:56:07.396966 52 : 4253, 4027
7433 00:56:07.399175 56 : 4253, 4026
7434 00:56:07.399724 60 : 4252, 4027
7435 00:56:07.402650 64 : 4366, 4140
7436 00:56:07.403067 68 : 4250, 4026
7437 00:56:07.406714 72 : 4360, 4138
7438 00:56:07.407289 76 : 4252, 4030
7439 00:56:07.409374 80 : 4250, 4027
7440 00:56:07.409770 84 : 4250, 4027
7441 00:56:07.410114 88 : 4255, 4032
7442 00:56:07.412161 92 : 4360, 4138
7443 00:56:07.412584 96 : 4250, 2511
7444 00:56:07.415598 100 : 4361, 0
7445 00:56:07.416018 104 : 4250, 0
7446 00:56:07.418777 108 : 4250, 0
7447 00:56:07.419244 112 : 4250, 0
7448 00:56:07.419672 116 : 4250, 0
7449 00:56:07.422266 120 : 4250, 0
7450 00:56:07.422691 124 : 4250, 0
7451 00:56:07.425399 128 : 4250, 0
7452 00:56:07.425822 132 : 4361, 0
7453 00:56:07.426159 136 : 4360, 0
7454 00:56:07.428620 140 : 4248, 0
7455 00:56:07.429043 144 : 4250, 0
7456 00:56:07.429383 148 : 4360, 0
7457 00:56:07.432438 152 : 4361, 0
7458 00:56:07.432863 156 : 4250, 0
7459 00:56:07.435916 160 : 4250, 0
7460 00:56:07.436339 164 : 4250, 0
7461 00:56:07.436675 168 : 4250, 0
7462 00:56:07.438656 172 : 4250, 0
7463 00:56:07.439077 176 : 4250, 0
7464 00:56:07.442153 180 : 4250, 0
7465 00:56:07.442667 184 : 4361, 0
7466 00:56:07.443149 188 : 4360, 0
7467 00:56:07.445222 192 : 4248, 0
7468 00:56:07.445644 196 : 4250, 0
7469 00:56:07.448352 200 : 4361, 0
7470 00:56:07.448773 204 : 4361, 0
7471 00:56:07.449140 208 : 4250, 0
7472 00:56:07.452058 212 : 4250, 0
7473 00:56:07.452637 216 : 4250, 0
7474 00:56:07.455480 220 : 4250, 1023
7475 00:56:07.455902 224 : 4361, 4135
7476 00:56:07.458582 228 : 4252, 4029
7477 00:56:07.459000 232 : 4250, 4027
7478 00:56:07.462344 236 : 4249, 4027
7479 00:56:07.462859 240 : 4250, 4026
7480 00:56:07.463202 244 : 4250, 4027
7481 00:56:07.465473 248 : 4250, 4027
7482 00:56:07.466029 252 : 4249, 4027
7483 00:56:07.468330 256 : 4250, 4026
7484 00:56:07.468770 260 : 4250, 4027
7485 00:56:07.471799 264 : 4360, 4138
7486 00:56:07.472357 268 : 4361, 4137
7487 00:56:07.474537 272 : 4248, 4024
7488 00:56:07.474963 276 : 4361, 4137
7489 00:56:07.478132 280 : 4360, 4138
7490 00:56:07.478555 284 : 4252, 4027
7491 00:56:07.481736 288 : 4250, 4027
7492 00:56:07.482283 292 : 4250, 4026
7493 00:56:07.485122 296 : 4250, 4027
7494 00:56:07.485547 300 : 4250, 4027
7495 00:56:07.488432 304 : 4252, 4029
7496 00:56:07.488853 308 : 4250, 4026
7497 00:56:07.489192 312 : 4250, 4027
7498 00:56:07.491565 316 : 4360, 4138
7499 00:56:07.491986 320 : 4361, 4137
7500 00:56:07.495063 324 : 4250, 4026
7501 00:56:07.495516 328 : 4361, 4137
7502 00:56:07.498147 332 : 4360, 3965
7503 00:56:07.498568 336 : 4250, 1292
7504 00:56:07.498904
7505 00:56:07.501727 MIOCK jitter meter ch=0
7506 00:56:07.502237
7507 00:56:07.504446 1T = (336-100) = 236 dly cells
7508 00:56:07.511171 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7509 00:56:07.511643 ==
7510 00:56:07.514386 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 00:56:07.517761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 00:56:07.518417 ==
7513 00:56:07.524657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 00:56:07.528080 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 00:56:07.531045 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 00:56:07.537511 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 00:56:07.546636 [CA 0] Center 44 (14~74) winsize 61
7518 00:56:07.549915 [CA 1] Center 43 (13~74) winsize 62
7519 00:56:07.553054 [CA 2] Center 39 (10~68) winsize 59
7520 00:56:07.556319 [CA 3] Center 38 (9~68) winsize 60
7521 00:56:07.559824 [CA 4] Center 37 (7~67) winsize 61
7522 00:56:07.562958 [CA 5] Center 36 (6~66) winsize 61
7523 00:56:07.563532
7524 00:56:07.566385 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7525 00:56:07.566805
7526 00:56:07.572838 [CATrainingPosCal] consider 1 rank data
7527 00:56:07.573266 u2DelayCellTimex100 = 275/100 ps
7528 00:56:07.579432 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7529 00:56:07.582737 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7530 00:56:07.585453 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7531 00:56:07.588866 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7532 00:56:07.592557 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7533 00:56:07.595615 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7534 00:56:07.596036
7535 00:56:07.599070 CA PerBit enable=1, Macro0, CA PI delay=36
7536 00:56:07.599528
7537 00:56:07.602515 [CBTSetCACLKResult] CA Dly = 36
7538 00:56:07.605462 CS Dly: 11 (0~42)
7539 00:56:07.609080 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 00:56:07.612505 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 00:56:07.612926 ==
7542 00:56:07.615450 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 00:56:07.621801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 00:56:07.622227 ==
7545 00:56:07.625375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 00:56:07.632052 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 00:56:07.635416 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 00:56:07.641439 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 00:56:07.650582 [CA 0] Center 44 (14~75) winsize 62
7550 00:56:07.653743 [CA 1] Center 44 (14~74) winsize 61
7551 00:56:07.656628 [CA 2] Center 39 (10~69) winsize 60
7552 00:56:07.660477 [CA 3] Center 39 (10~68) winsize 59
7553 00:56:07.663626 [CA 4] Center 37 (7~67) winsize 61
7554 00:56:07.666593 [CA 5] Center 36 (7~66) winsize 60
7555 00:56:07.667010
7556 00:56:07.670183 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 00:56:07.673079
7558 00:56:07.676943 [CATrainingPosCal] consider 2 rank data
7559 00:56:07.677454 u2DelayCellTimex100 = 275/100 ps
7560 00:56:07.683207 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7561 00:56:07.686601 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7562 00:56:07.690075 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7563 00:56:07.693012 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7564 00:56:07.695931 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7565 00:56:07.699411 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 00:56:07.700108
7567 00:56:07.703023 CA PerBit enable=1, Macro0, CA PI delay=36
7568 00:56:07.706283
7569 00:56:07.706698 [CBTSetCACLKResult] CA Dly = 36
7570 00:56:07.709643 CS Dly: 12 (0~44)
7571 00:56:07.712726 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 00:56:07.716127 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 00:56:07.719217
7574 00:56:07.722515 ----->DramcWriteLeveling(PI) begin...
7575 00:56:07.722953 ==
7576 00:56:07.725645 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 00:56:07.728952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 00:56:07.729380 ==
7579 00:56:07.732838 Write leveling (Byte 0): 34 => 34
7580 00:56:07.735546 Write leveling (Byte 1): 27 => 27
7581 00:56:07.738949 DramcWriteLeveling(PI) end<-----
7582 00:56:07.739411
7583 00:56:07.739759 ==
7584 00:56:07.741975 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 00:56:07.745729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 00:56:07.746255 ==
7587 00:56:07.748928 [Gating] SW mode calibration
7588 00:56:07.755419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 00:56:07.762189 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 00:56:07.765682 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 00:56:07.768840 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 00:56:07.775043 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 00:56:07.778673 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7594 00:56:07.781609 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7595 00:56:07.788375 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7596 00:56:07.791841 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 00:56:07.795220 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 00:56:07.801206 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 00:56:07.804980 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 00:56:07.807983 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7601 00:56:07.814574 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 1)
7602 00:56:07.818051 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7603 00:56:07.821224 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
7604 00:56:07.827671 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
7605 00:56:07.830949 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 00:56:07.834397 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 00:56:07.840737 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 00:56:07.844738 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7609 00:56:07.847467 1 6 12 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7610 00:56:07.854439 1 6 16 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
7611 00:56:07.857509 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7612 00:56:07.860698 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 00:56:07.867441 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 00:56:07.870325 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 00:56:07.873803 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 00:56:07.880663 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 00:56:07.883785 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7618 00:56:07.887293 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7619 00:56:07.893422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7620 00:56:07.896878 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 00:56:07.900259 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 00:56:07.906594 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 00:56:07.910182 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 00:56:07.913542 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 00:56:07.920013 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 00:56:07.923176 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 00:56:07.926323 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 00:56:07.932988 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 00:56:07.936033 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 00:56:07.940103 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 00:56:07.946176 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 00:56:07.949378 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7633 00:56:07.952881 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7634 00:56:07.959141 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7635 00:56:07.962717 Total UI for P1: 0, mck2ui 16
7636 00:56:07.966213 best dqsien dly found for B0: ( 1, 9, 10)
7637 00:56:07.969572 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7638 00:56:07.972540 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7639 00:56:07.979476 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 00:56:07.982863 Total UI for P1: 0, mck2ui 16
7641 00:56:07.985616 best dqsien dly found for B1: ( 1, 9, 22)
7642 00:56:07.989200 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7643 00:56:07.992340 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7644 00:56:07.992816
7645 00:56:07.995696 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7646 00:56:07.999215 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7647 00:56:08.001914 [Gating] SW calibration Done
7648 00:56:08.002452 ==
7649 00:56:08.005270 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 00:56:08.008770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 00:56:08.011810 ==
7652 00:56:08.012369 RX Vref Scan: 0
7653 00:56:08.012859
7654 00:56:08.015127 RX Vref 0 -> 0, step: 1
7655 00:56:08.015616
7656 00:56:08.016048 RX Delay 0 -> 252, step: 8
7657 00:56:08.021731 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7658 00:56:08.025496 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7659 00:56:08.028449 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7660 00:56:08.031843 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7661 00:56:08.038160 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7662 00:56:08.041685 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7663 00:56:08.044624 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7664 00:56:08.048241 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7665 00:56:08.051814 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7666 00:56:08.058368 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7667 00:56:08.061573 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7668 00:56:08.064959 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7669 00:56:08.068570 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7670 00:56:08.071048 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7671 00:56:08.077593 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7672 00:56:08.080681 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7673 00:56:08.081107 ==
7674 00:56:08.083877 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 00:56:08.087621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 00:56:08.088139 ==
7677 00:56:08.091460 DQS Delay:
7678 00:56:08.091901 DQS0 = 0, DQS1 = 0
7679 00:56:08.094127 DQM Delay:
7680 00:56:08.094668 DQM0 = 132, DQM1 = 127
7681 00:56:08.095044 DQ Delay:
7682 00:56:08.097654 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7683 00:56:08.104015 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7684 00:56:08.107296 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7685 00:56:08.110750 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7686 00:56:08.111163
7687 00:56:08.111560
7688 00:56:08.111882 ==
7689 00:56:08.114000 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 00:56:08.117455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 00:56:08.117977 ==
7692 00:56:08.118312
7693 00:56:08.118638
7694 00:56:08.120601 TX Vref Scan disable
7695 00:56:08.123806 == TX Byte 0 ==
7696 00:56:08.127257 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7697 00:56:08.130420 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7698 00:56:08.133880 == TX Byte 1 ==
7699 00:56:08.137295 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7700 00:56:08.139864 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7701 00:56:08.140319 ==
7702 00:56:08.143678 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 00:56:08.150042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 00:56:08.150528 ==
7705 00:56:08.163504
7706 00:56:08.166867 TX Vref early break, caculate TX vref
7707 00:56:08.169832 TX Vref=16, minBit 4, minWin=22, winSum=372
7708 00:56:08.173377 TX Vref=18, minBit 1, minWin=23, winSum=379
7709 00:56:08.177032 TX Vref=20, minBit 7, minWin=23, winSum=390
7710 00:56:08.179613 TX Vref=22, minBit 1, minWin=24, winSum=402
7711 00:56:08.183117 TX Vref=24, minBit 1, minWin=25, winSum=411
7712 00:56:08.189796 TX Vref=26, minBit 2, minWin=25, winSum=421
7713 00:56:08.192670 TX Vref=28, minBit 2, minWin=25, winSum=421
7714 00:56:08.196121 TX Vref=30, minBit 1, minWin=25, winSum=420
7715 00:56:08.199687 TX Vref=32, minBit 2, minWin=24, winSum=409
7716 00:56:08.202903 TX Vref=34, minBit 1, minWin=24, winSum=402
7717 00:56:08.209273 TX Vref=36, minBit 0, minWin=23, winSum=392
7718 00:56:08.212340 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 26
7719 00:56:08.212770
7720 00:56:08.216069 Final TX Range 0 Vref 26
7721 00:56:08.216486
7722 00:56:08.216815 ==
7723 00:56:08.218864 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 00:56:08.221997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 00:56:08.225734 ==
7726 00:56:08.226145
7727 00:56:08.226474
7728 00:56:08.226779 TX Vref Scan disable
7729 00:56:08.232748 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7730 00:56:08.233192 == TX Byte 0 ==
7731 00:56:08.236201 u2DelayCellOfst[0]=14 cells (4 PI)
7732 00:56:08.239226 u2DelayCellOfst[1]=17 cells (5 PI)
7733 00:56:08.243014 u2DelayCellOfst[2]=14 cells (4 PI)
7734 00:56:08.246248 u2DelayCellOfst[3]=10 cells (3 PI)
7735 00:56:08.249580 u2DelayCellOfst[4]=10 cells (3 PI)
7736 00:56:08.252481 u2DelayCellOfst[5]=0 cells (0 PI)
7737 00:56:08.255682 u2DelayCellOfst[6]=17 cells (5 PI)
7738 00:56:08.259169 u2DelayCellOfst[7]=17 cells (5 PI)
7739 00:56:08.262956 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7740 00:56:08.265908 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7741 00:56:08.269171 == TX Byte 1 ==
7742 00:56:08.272284 u2DelayCellOfst[8]=0 cells (0 PI)
7743 00:56:08.275504 u2DelayCellOfst[9]=0 cells (0 PI)
7744 00:56:08.278952 u2DelayCellOfst[10]=3 cells (1 PI)
7745 00:56:08.282616 u2DelayCellOfst[11]=3 cells (1 PI)
7746 00:56:08.285542 u2DelayCellOfst[12]=10 cells (3 PI)
7747 00:56:08.289001 u2DelayCellOfst[13]=10 cells (3 PI)
7748 00:56:08.292280 u2DelayCellOfst[14]=14 cells (4 PI)
7749 00:56:08.295489 u2DelayCellOfst[15]=10 cells (3 PI)
7750 00:56:08.298764 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7751 00:56:08.302049 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7752 00:56:08.305400 DramC Write-DBI on
7753 00:56:08.305978 ==
7754 00:56:08.308798 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 00:56:08.311967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 00:56:08.312573 ==
7757 00:56:08.312951
7758 00:56:08.313296
7759 00:56:08.314842 TX Vref Scan disable
7760 00:56:08.318569 == TX Byte 0 ==
7761 00:56:08.321765 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7762 00:56:08.322192 == TX Byte 1 ==
7763 00:56:08.328144 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7764 00:56:08.328726 DramC Write-DBI off
7765 00:56:08.329070
7766 00:56:08.329380 [DATLAT]
7767 00:56:08.331506 Freq=1600, CH0 RK0
7768 00:56:08.332121
7769 00:56:08.334616 DATLAT Default: 0xf
7770 00:56:08.335075 0, 0xFFFF, sum = 0
7771 00:56:08.337784 1, 0xFFFF, sum = 0
7772 00:56:08.338198 2, 0xFFFF, sum = 0
7773 00:56:08.341244 3, 0xFFFF, sum = 0
7774 00:56:08.341661 4, 0xFFFF, sum = 0
7775 00:56:08.344551 5, 0xFFFF, sum = 0
7776 00:56:08.345069 6, 0xFFFF, sum = 0
7777 00:56:08.347874 7, 0xFFFF, sum = 0
7778 00:56:08.348294 8, 0xFFFF, sum = 0
7779 00:56:08.351323 9, 0xFFFF, sum = 0
7780 00:56:08.351890 10, 0xFFFF, sum = 0
7781 00:56:08.354660 11, 0xFFFF, sum = 0
7782 00:56:08.355082 12, 0xFFFF, sum = 0
7783 00:56:08.357515 13, 0xFFFF, sum = 0
7784 00:56:08.360852 14, 0x0, sum = 1
7785 00:56:08.361273 15, 0x0, sum = 2
7786 00:56:08.361606 16, 0x0, sum = 3
7787 00:56:08.364407 17, 0x0, sum = 4
7788 00:56:08.364948 best_step = 15
7789 00:56:08.365291
7790 00:56:08.365604 ==
7791 00:56:08.367882 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 00:56:08.373833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 00:56:08.374337 ==
7794 00:56:08.374668 RX Vref Scan: 1
7795 00:56:08.374973
7796 00:56:08.377146 Set Vref Range= 24 -> 127
7797 00:56:08.377556
7798 00:56:08.380873 RX Vref 24 -> 127, step: 1
7799 00:56:08.381383
7800 00:56:08.384249 RX Delay 11 -> 252, step: 4
7801 00:56:08.384782
7802 00:56:08.387538 Set Vref, RX VrefLevel [Byte0]: 24
7803 00:56:08.390563 [Byte1]: 24
7804 00:56:08.391105
7805 00:56:08.394029 Set Vref, RX VrefLevel [Byte0]: 25
7806 00:56:08.397121 [Byte1]: 25
7807 00:56:08.397534
7808 00:56:08.400436 Set Vref, RX VrefLevel [Byte0]: 26
7809 00:56:08.403528 [Byte1]: 26
7810 00:56:08.407439
7811 00:56:08.407848 Set Vref, RX VrefLevel [Byte0]: 27
7812 00:56:08.410374 [Byte1]: 27
7813 00:56:08.415326
7814 00:56:08.415912 Set Vref, RX VrefLevel [Byte0]: 28
7815 00:56:08.418170 [Byte1]: 28
7816 00:56:08.422709
7817 00:56:08.423123 Set Vref, RX VrefLevel [Byte0]: 29
7818 00:56:08.426166 [Byte1]: 29
7819 00:56:08.430160
7820 00:56:08.430572 Set Vref, RX VrefLevel [Byte0]: 30
7821 00:56:08.433399 [Byte1]: 30
7822 00:56:08.437635
7823 00:56:08.438067 Set Vref, RX VrefLevel [Byte0]: 31
7824 00:56:08.440932 [Byte1]: 31
7825 00:56:08.445516
7826 00:56:08.446027 Set Vref, RX VrefLevel [Byte0]: 32
7827 00:56:08.448522 [Byte1]: 32
7828 00:56:08.453159
7829 00:56:08.453687 Set Vref, RX VrefLevel [Byte0]: 33
7830 00:56:08.456539 [Byte1]: 33
7831 00:56:08.460502
7832 00:56:08.461011 Set Vref, RX VrefLevel [Byte0]: 34
7833 00:56:08.464266 [Byte1]: 34
7834 00:56:08.467958
7835 00:56:08.468470 Set Vref, RX VrefLevel [Byte0]: 35
7836 00:56:08.471657 [Byte1]: 35
7837 00:56:08.475970
7838 00:56:08.476605 Set Vref, RX VrefLevel [Byte0]: 36
7839 00:56:08.479419 [Byte1]: 36
7840 00:56:08.483697
7841 00:56:08.484208 Set Vref, RX VrefLevel [Byte0]: 37
7842 00:56:08.486841 [Byte1]: 37
7843 00:56:08.491515
7844 00:56:08.492034 Set Vref, RX VrefLevel [Byte0]: 38
7845 00:56:08.494380 [Byte1]: 38
7846 00:56:08.499053
7847 00:56:08.499600 Set Vref, RX VrefLevel [Byte0]: 39
7848 00:56:08.502158 [Byte1]: 39
7849 00:56:08.506385
7850 00:56:08.506938 Set Vref, RX VrefLevel [Byte0]: 40
7851 00:56:08.509492 [Byte1]: 40
7852 00:56:08.514074
7853 00:56:08.514583 Set Vref, RX VrefLevel [Byte0]: 41
7854 00:56:08.517362 [Byte1]: 41
7855 00:56:08.521270
7856 00:56:08.521816 Set Vref, RX VrefLevel [Byte0]: 42
7857 00:56:08.524945 [Byte1]: 42
7858 00:56:08.529120
7859 00:56:08.529612 Set Vref, RX VrefLevel [Byte0]: 43
7860 00:56:08.532545 [Byte1]: 43
7861 00:56:08.537235
7862 00:56:08.537750 Set Vref, RX VrefLevel [Byte0]: 44
7863 00:56:08.540034 [Byte1]: 44
7864 00:56:08.544356
7865 00:56:08.544767 Set Vref, RX VrefLevel [Byte0]: 45
7866 00:56:08.547733 [Byte1]: 45
7867 00:56:08.551968
7868 00:56:08.552446 Set Vref, RX VrefLevel [Byte0]: 46
7869 00:56:08.555429 [Byte1]: 46
7870 00:56:08.559717
7871 00:56:08.560395 Set Vref, RX VrefLevel [Byte0]: 47
7872 00:56:08.563172 [Byte1]: 47
7873 00:56:08.567326
7874 00:56:08.567904 Set Vref, RX VrefLevel [Byte0]: 48
7875 00:56:08.570265 [Byte1]: 48
7876 00:56:08.574868
7877 00:56:08.575347 Set Vref, RX VrefLevel [Byte0]: 49
7878 00:56:08.578117 [Byte1]: 49
7879 00:56:08.582442
7880 00:56:08.582921 Set Vref, RX VrefLevel [Byte0]: 50
7881 00:56:08.585436 [Byte1]: 50
7882 00:56:08.589963
7883 00:56:08.590502 Set Vref, RX VrefLevel [Byte0]: 51
7884 00:56:08.593548 [Byte1]: 51
7885 00:56:08.597741
7886 00:56:08.598158 Set Vref, RX VrefLevel [Byte0]: 52
7887 00:56:08.600800 [Byte1]: 52
7888 00:56:08.605033
7889 00:56:08.605447 Set Vref, RX VrefLevel [Byte0]: 53
7890 00:56:08.608502 [Byte1]: 53
7891 00:56:08.612731
7892 00:56:08.613239 Set Vref, RX VrefLevel [Byte0]: 54
7893 00:56:08.615743 [Byte1]: 54
7894 00:56:08.620451
7895 00:56:08.620954 Set Vref, RX VrefLevel [Byte0]: 55
7896 00:56:08.623883 [Byte1]: 55
7897 00:56:08.628080
7898 00:56:08.628567 Set Vref, RX VrefLevel [Byte0]: 56
7899 00:56:08.631300 [Byte1]: 56
7900 00:56:08.635699
7901 00:56:08.636124 Set Vref, RX VrefLevel [Byte0]: 57
7902 00:56:08.641822 [Byte1]: 57
7903 00:56:08.642300
7904 00:56:08.645262 Set Vref, RX VrefLevel [Byte0]: 58
7905 00:56:08.648213 [Byte1]: 58
7906 00:56:08.648653
7907 00:56:08.651734 Set Vref, RX VrefLevel [Byte0]: 59
7908 00:56:08.655178 [Byte1]: 59
7909 00:56:08.658291
7910 00:56:08.658771 Set Vref, RX VrefLevel [Byte0]: 60
7911 00:56:08.661796 [Byte1]: 60
7912 00:56:08.666587
7913 00:56:08.667112 Set Vref, RX VrefLevel [Byte0]: 61
7914 00:56:08.669102 [Byte1]: 61
7915 00:56:08.673543
7916 00:56:08.673955 Set Vref, RX VrefLevel [Byte0]: 62
7917 00:56:08.676773 [Byte1]: 62
7918 00:56:08.681157
7919 00:56:08.681788 Set Vref, RX VrefLevel [Byte0]: 63
7920 00:56:08.684176 [Byte1]: 63
7921 00:56:08.688931
7922 00:56:08.689444 Set Vref, RX VrefLevel [Byte0]: 64
7923 00:56:08.692629 [Byte1]: 64
7924 00:56:08.696499
7925 00:56:08.697020 Set Vref, RX VrefLevel [Byte0]: 65
7926 00:56:08.700230 [Byte1]: 65
7927 00:56:08.704195
7928 00:56:08.704603 Set Vref, RX VrefLevel [Byte0]: 66
7929 00:56:08.707241 [Byte1]: 66
7930 00:56:08.711846
7931 00:56:08.712508 Set Vref, RX VrefLevel [Byte0]: 67
7932 00:56:08.715019 [Byte1]: 67
7933 00:56:08.719096
7934 00:56:08.719717 Set Vref, RX VrefLevel [Byte0]: 68
7935 00:56:08.722340 [Byte1]: 68
7936 00:56:08.726850
7937 00:56:08.727317 Set Vref, RX VrefLevel [Byte0]: 69
7938 00:56:08.730303 [Byte1]: 69
7939 00:56:08.734251
7940 00:56:08.734661 Set Vref, RX VrefLevel [Byte0]: 70
7941 00:56:08.741008 [Byte1]: 70
7942 00:56:08.741420
7943 00:56:08.744534 Set Vref, RX VrefLevel [Byte0]: 71
7944 00:56:08.747656 [Byte1]: 71
7945 00:56:08.748065
7946 00:56:08.750756 Set Vref, RX VrefLevel [Byte0]: 72
7947 00:56:08.754321 [Byte1]: 72
7948 00:56:08.757284
7949 00:56:08.757692 Set Vref, RX VrefLevel [Byte0]: 73
7950 00:56:08.760578 [Byte1]: 73
7951 00:56:08.765316
7952 00:56:08.765726 Set Vref, RX VrefLevel [Byte0]: 74
7953 00:56:08.768326 [Byte1]: 74
7954 00:56:08.772304
7955 00:56:08.772722 Final RX Vref Byte 0 = 55 to rank0
7956 00:56:08.776039 Final RX Vref Byte 1 = 62 to rank0
7957 00:56:08.779257 Final RX Vref Byte 0 = 55 to rank1
7958 00:56:08.782095 Final RX Vref Byte 1 = 62 to rank1==
7959 00:56:08.785453 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 00:56:08.792612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 00:56:08.793207 ==
7962 00:56:08.793598 DQS Delay:
7963 00:56:08.795517 DQS0 = 0, DQS1 = 0
7964 00:56:08.796160 DQM Delay:
7965 00:56:08.796538 DQM0 = 129, DQM1 = 123
7966 00:56:08.798610 DQ Delay:
7967 00:56:08.802165 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7968 00:56:08.805354 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7969 00:56:08.808831 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7970 00:56:08.812144 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
7971 00:56:08.812575
7972 00:56:08.812913
7973 00:56:08.813307
7974 00:56:08.815584 [DramC_TX_OE_Calibration] TA2
7975 00:56:08.818774 Original DQ_B0 (3 6) =30, OEN = 27
7976 00:56:08.822105 Original DQ_B1 (3 6) =30, OEN = 27
7977 00:56:08.825223 24, 0x0, End_B0=24 End_B1=24
7978 00:56:08.828663 25, 0x0, End_B0=25 End_B1=25
7979 00:56:08.829111 26, 0x0, End_B0=26 End_B1=26
7980 00:56:08.831965 27, 0x0, End_B0=27 End_B1=27
7981 00:56:08.835084 28, 0x0, End_B0=28 End_B1=28
7982 00:56:08.838538 29, 0x0, End_B0=29 End_B1=29
7983 00:56:08.838961 30, 0x0, End_B0=30 End_B1=30
7984 00:56:08.841679 31, 0x4141, End_B0=30 End_B1=30
7985 00:56:08.844944 Byte0 end_step=30 best_step=27
7986 00:56:08.848300 Byte1 end_step=30 best_step=27
7987 00:56:08.851317 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 00:56:08.854730 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 00:56:08.855140
7990 00:56:08.855512
7991 00:56:08.861144 [DQSOSCAuto] RK0, (LSB)MR18= 0x1816, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7992 00:56:08.864658 CH0 RK0: MR19=303, MR18=1816
7993 00:56:08.870954 CH0_RK0: MR19=0x303, MR18=0x1816, DQSOSC=397, MR23=63, INC=23, DEC=15
7994 00:56:08.871400
7995 00:56:08.874325 ----->DramcWriteLeveling(PI) begin...
7996 00:56:08.874739 ==
7997 00:56:08.877811 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 00:56:08.881348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 00:56:08.881881 ==
8000 00:56:08.884162 Write leveling (Byte 0): 35 => 35
8001 00:56:08.887307 Write leveling (Byte 1): 25 => 25
8002 00:56:08.890962 DramcWriteLeveling(PI) end<-----
8003 00:56:08.891401
8004 00:56:08.891739 ==
8005 00:56:08.894345 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 00:56:08.900882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 00:56:08.901364 ==
8008 00:56:08.901699 [Gating] SW mode calibration
8009 00:56:08.910314 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 00:56:08.914088 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 00:56:08.920849 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 00:56:08.923552 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 00:56:08.926993 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8014 00:56:08.933767 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8015 00:56:08.937203 1 4 16 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
8016 00:56:08.940176 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8017 00:56:08.947039 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 00:56:08.950477 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 00:56:08.953076 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 00:56:08.960532 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 00:56:08.963033 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8022 00:56:08.966616 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 1)
8023 00:56:08.973180 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8024 00:56:08.976564 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8025 00:56:08.979910 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 00:56:08.985954 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 00:56:08.989759 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 00:56:08.992951 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8029 00:56:08.999241 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
8030 00:56:09.002847 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8031 00:56:09.006102 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8032 00:56:09.012456 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8033 00:56:09.015840 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 00:56:09.019231 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 00:56:09.025666 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 00:56:09.029442 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 00:56:09.032294 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 00:56:09.039210 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 00:56:09.042286 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 00:56:09.045826 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 00:56:09.052245 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 00:56:09.056156 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 00:56:09.058593 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 00:56:09.065588 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 00:56:09.068872 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 00:56:09.072087 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 00:56:09.078215 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 00:56:09.082082 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 00:56:09.085468 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 00:56:09.091939 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 00:56:09.095326 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 00:56:09.098090 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 00:56:09.105196 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 00:56:09.108505 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8055 00:56:09.111166 Total UI for P1: 0, mck2ui 16
8056 00:56:09.114666 best dqsien dly found for B0: ( 1, 9, 8)
8057 00:56:09.118217 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 00:56:09.124538 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 00:56:09.127928 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 00:56:09.131117 Total UI for P1: 0, mck2ui 16
8061 00:56:09.134099 best dqsien dly found for B1: ( 1, 9, 18)
8062 00:56:09.137744 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8063 00:56:09.141415 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8064 00:56:09.141833
8065 00:56:09.144180 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8066 00:56:09.147564 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8067 00:56:09.150597 [Gating] SW calibration Done
8068 00:56:09.151043 ==
8069 00:56:09.154507 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 00:56:09.160830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 00:56:09.161262 ==
8072 00:56:09.161590 RX Vref Scan: 0
8073 00:56:09.161894
8074 00:56:09.163989 RX Vref 0 -> 0, step: 1
8075 00:56:09.164414
8076 00:56:09.167242 RX Delay 0 -> 252, step: 8
8077 00:56:09.170406 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8078 00:56:09.173739 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8079 00:56:09.176962 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8080 00:56:09.180133 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8081 00:56:09.187325 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8082 00:56:09.190285 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8083 00:56:09.193616 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8084 00:56:09.197180 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 00:56:09.199993 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8086 00:56:09.206717 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8087 00:56:09.210252 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8088 00:56:09.213603 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8089 00:56:09.216314 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8090 00:56:09.223118 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8091 00:56:09.226088 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8092 00:56:09.229795 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8093 00:56:09.230205 ==
8094 00:56:09.233316 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 00:56:09.236245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 00:56:09.239343 ==
8097 00:56:09.239806 DQS Delay:
8098 00:56:09.240202 DQS0 = 0, DQS1 = 0
8099 00:56:09.242594 DQM Delay:
8100 00:56:09.243027 DQM0 = 131, DQM1 = 128
8101 00:56:09.246215 DQ Delay:
8102 00:56:09.249274 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8103 00:56:09.252753 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8104 00:56:09.256225 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8105 00:56:09.259216 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8106 00:56:09.259759
8107 00:56:09.260090
8108 00:56:09.260399 ==
8109 00:56:09.262390 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 00:56:09.265851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 00:56:09.266365 ==
8112 00:56:09.269015
8113 00:56:09.269429
8114 00:56:09.269819 TX Vref Scan disable
8115 00:56:09.272666 == TX Byte 0 ==
8116 00:56:09.275552 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8117 00:56:09.278744 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8118 00:56:09.282434 == TX Byte 1 ==
8119 00:56:09.285412 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8120 00:56:09.288903 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8121 00:56:09.292495 ==
8122 00:56:09.292986 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 00:56:09.298389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 00:56:09.298805 ==
8125 00:56:09.312937
8126 00:56:09.316669 TX Vref early break, caculate TX vref
8127 00:56:09.320172 TX Vref=16, minBit 2, minWin=23, winSum=382
8128 00:56:09.323289 TX Vref=18, minBit 8, minWin=23, winSum=387
8129 00:56:09.326196 TX Vref=20, minBit 4, minWin=24, winSum=397
8130 00:56:09.329836 TX Vref=22, minBit 10, minWin=24, winSum=401
8131 00:56:09.332612 TX Vref=24, minBit 1, minWin=25, winSum=409
8132 00:56:09.339338 TX Vref=26, minBit 8, minWin=25, winSum=414
8133 00:56:09.342956 TX Vref=28, minBit 4, minWin=25, winSum=414
8134 00:56:09.345907 TX Vref=30, minBit 1, minWin=25, winSum=408
8135 00:56:09.349095 TX Vref=32, minBit 8, minWin=24, winSum=405
8136 00:56:09.352777 TX Vref=34, minBit 1, minWin=24, winSum=396
8137 00:56:09.359251 TX Vref=36, minBit 0, minWin=24, winSum=388
8138 00:56:09.362403 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 26
8139 00:56:09.362820
8140 00:56:09.365464 Final TX Range 0 Vref 26
8141 00:56:09.365883
8142 00:56:09.366215 ==
8143 00:56:09.369016 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 00:56:09.372805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 00:56:09.375478 ==
8146 00:56:09.375902
8147 00:56:09.376232
8148 00:56:09.376541 TX Vref Scan disable
8149 00:56:09.382267 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8150 00:56:09.382787 == TX Byte 0 ==
8151 00:56:09.385899 u2DelayCellOfst[0]=10 cells (3 PI)
8152 00:56:09.388985 u2DelayCellOfst[1]=14 cells (4 PI)
8153 00:56:09.392329 u2DelayCellOfst[2]=7 cells (2 PI)
8154 00:56:09.395754 u2DelayCellOfst[3]=7 cells (2 PI)
8155 00:56:09.398772 u2DelayCellOfst[4]=7 cells (2 PI)
8156 00:56:09.402484 u2DelayCellOfst[5]=0 cells (0 PI)
8157 00:56:09.405790 u2DelayCellOfst[6]=14 cells (4 PI)
8158 00:56:09.408752 u2DelayCellOfst[7]=14 cells (4 PI)
8159 00:56:09.411988 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8160 00:56:09.415747 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8161 00:56:09.419260 == TX Byte 1 ==
8162 00:56:09.421831 u2DelayCellOfst[8]=0 cells (0 PI)
8163 00:56:09.425606 u2DelayCellOfst[9]=0 cells (0 PI)
8164 00:56:09.428647 u2DelayCellOfst[10]=3 cells (1 PI)
8165 00:56:09.432062 u2DelayCellOfst[11]=3 cells (1 PI)
8166 00:56:09.435193 u2DelayCellOfst[12]=7 cells (2 PI)
8167 00:56:09.435656 u2DelayCellOfst[13]=10 cells (3 PI)
8168 00:56:09.438673 u2DelayCellOfst[14]=10 cells (3 PI)
8169 00:56:09.442198 u2DelayCellOfst[15]=10 cells (3 PI)
8170 00:56:09.448739 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8171 00:56:09.451812 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8172 00:56:09.452231 DramC Write-DBI on
8173 00:56:09.455248 ==
8174 00:56:09.458575 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 00:56:09.461955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 00:56:09.462623 ==
8177 00:56:09.462978
8178 00:56:09.463287
8179 00:56:09.464685 TX Vref Scan disable
8180 00:56:09.465103 == TX Byte 0 ==
8181 00:56:09.471672 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8182 00:56:09.472102 == TX Byte 1 ==
8183 00:56:09.474529 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8184 00:56:09.477948 DramC Write-DBI off
8185 00:56:09.478378
8186 00:56:09.478708 [DATLAT]
8187 00:56:09.481694 Freq=1600, CH0 RK1
8188 00:56:09.482221
8189 00:56:09.482558 DATLAT Default: 0xf
8190 00:56:09.484991 0, 0xFFFF, sum = 0
8191 00:56:09.485411 1, 0xFFFF, sum = 0
8192 00:56:09.488027 2, 0xFFFF, sum = 0
8193 00:56:09.491015 3, 0xFFFF, sum = 0
8194 00:56:09.491481 4, 0xFFFF, sum = 0
8195 00:56:09.494230 5, 0xFFFF, sum = 0
8196 00:56:09.494653 6, 0xFFFF, sum = 0
8197 00:56:09.497780 7, 0xFFFF, sum = 0
8198 00:56:09.498204 8, 0xFFFF, sum = 0
8199 00:56:09.501203 9, 0xFFFF, sum = 0
8200 00:56:09.501750 10, 0xFFFF, sum = 0
8201 00:56:09.504654 11, 0xFFFF, sum = 0
8202 00:56:09.505195 12, 0xFFFF, sum = 0
8203 00:56:09.507822 13, 0xFFFF, sum = 0
8204 00:56:09.508248 14, 0x0, sum = 1
8205 00:56:09.510719 15, 0x0, sum = 2
8206 00:56:09.511153 16, 0x0, sum = 3
8207 00:56:09.514212 17, 0x0, sum = 4
8208 00:56:09.514641 best_step = 15
8209 00:56:09.514971
8210 00:56:09.515279 ==
8211 00:56:09.517510 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 00:56:09.523773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 00:56:09.524204 ==
8214 00:56:09.524659 RX Vref Scan: 0
8215 00:56:09.524987
8216 00:56:09.527417 RX Vref 0 -> 0, step: 1
8217 00:56:09.527891
8218 00:56:09.530532 RX Delay 19 -> 252, step: 4
8219 00:56:09.533965 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8220 00:56:09.537085 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8221 00:56:09.540506 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8222 00:56:09.547034 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8223 00:56:09.550477 iDelay=187, Bit 4, Center 130 (83 ~ 178) 96
8224 00:56:09.553409 iDelay=187, Bit 5, Center 120 (67 ~ 174) 108
8225 00:56:09.557040 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8226 00:56:09.560480 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8227 00:56:09.567065 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8228 00:56:09.570133 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8229 00:56:09.573865 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8230 00:56:09.576583 iDelay=187, Bit 11, Center 120 (67 ~ 174) 108
8231 00:56:09.583770 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8232 00:56:09.586693 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8233 00:56:09.589727 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8234 00:56:09.593253 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8235 00:56:09.593690 ==
8236 00:56:09.596234 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 00:56:09.603348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 00:56:09.603913 ==
8239 00:56:09.604252 DQS Delay:
8240 00:56:09.606270 DQS0 = 0, DQS1 = 0
8241 00:56:09.606683 DQM Delay:
8242 00:56:09.607017 DQM0 = 128, DQM1 = 123
8243 00:56:09.609698 DQ Delay:
8244 00:56:09.612833 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8245 00:56:09.616309 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
8246 00:56:09.619482 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8247 00:56:09.623165 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8248 00:56:09.623635
8249 00:56:09.624055
8250 00:56:09.624381
8251 00:56:09.626205 [DramC_TX_OE_Calibration] TA2
8252 00:56:09.629696 Original DQ_B0 (3 6) =30, OEN = 27
8253 00:56:09.632683 Original DQ_B1 (3 6) =30, OEN = 27
8254 00:56:09.636025 24, 0x0, End_B0=24 End_B1=24
8255 00:56:09.639817 25, 0x0, End_B0=25 End_B1=25
8256 00:56:09.640238 26, 0x0, End_B0=26 End_B1=26
8257 00:56:09.642688 27, 0x0, End_B0=27 End_B1=27
8258 00:56:09.645913 28, 0x0, End_B0=28 End_B1=28
8259 00:56:09.649306 29, 0x0, End_B0=29 End_B1=29
8260 00:56:09.649808 30, 0x0, End_B0=30 End_B1=30
8261 00:56:09.652792 31, 0x4141, End_B0=30 End_B1=30
8262 00:56:09.655776 Byte0 end_step=30 best_step=27
8263 00:56:09.659431 Byte1 end_step=30 best_step=27
8264 00:56:09.662266 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 00:56:09.665991 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 00:56:09.666474
8267 00:56:09.666803
8268 00:56:09.672663 [DQSOSCAuto] RK1, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8269 00:56:09.675950 CH0 RK1: MR19=303, MR18=1312
8270 00:56:09.682426 CH0_RK1: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8271 00:56:09.685770 [RxdqsGatingPostProcess] freq 1600
8272 00:56:09.692066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 00:56:09.692484 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 00:56:09.695464 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 00:56:09.698696 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 00:56:09.702116 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 00:56:09.705665 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 00:56:09.708986 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 00:56:09.712113 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 00:56:09.715197 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 00:56:09.718696 Pre-setting of DQS Precalculation
8282 00:56:09.722132 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 00:56:09.722626 ==
8284 00:56:09.725179 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 00:56:09.731705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 00:56:09.732197 ==
8287 00:56:09.734750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 00:56:09.741844 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 00:56:09.744695 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 00:56:09.751295 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 00:56:09.759214 [CA 0] Center 42 (12~72) winsize 61
8292 00:56:09.762712 [CA 1] Center 42 (12~72) winsize 61
8293 00:56:09.765786 [CA 2] Center 38 (9~67) winsize 59
8294 00:56:09.769224 [CA 3] Center 36 (7~66) winsize 60
8295 00:56:09.772515 [CA 4] Center 38 (8~68) winsize 61
8296 00:56:09.776033 [CA 5] Center 36 (7~66) winsize 60
8297 00:56:09.776450
8298 00:56:09.779117 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 00:56:09.779567
8300 00:56:09.785427 [CATrainingPosCal] consider 1 rank data
8301 00:56:09.785843 u2DelayCellTimex100 = 275/100 ps
8302 00:56:09.792137 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8303 00:56:09.795488 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8304 00:56:09.798741 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8305 00:56:09.802349 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 00:56:09.805405 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8307 00:56:09.808560 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 00:56:09.808974
8309 00:56:09.812030 CA PerBit enable=1, Macro0, CA PI delay=36
8310 00:56:09.812445
8311 00:56:09.815092 [CBTSetCACLKResult] CA Dly = 36
8312 00:56:09.818366 CS Dly: 8 (0~39)
8313 00:56:09.821761 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 00:56:09.825088 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 00:56:09.825511 ==
8316 00:56:09.828595 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 00:56:09.834800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 00:56:09.835228 ==
8319 00:56:09.838306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 00:56:09.845051 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 00:56:09.847932 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 00:56:09.854661 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 00:56:09.862567 [CA 0] Center 41 (11~71) winsize 61
8324 00:56:09.866258 [CA 1] Center 41 (12~71) winsize 60
8325 00:56:09.869241 [CA 2] Center 37 (8~67) winsize 60
8326 00:56:09.872158 [CA 3] Center 36 (7~66) winsize 60
8327 00:56:09.875757 [CA 4] Center 37 (7~67) winsize 61
8328 00:56:09.879726 [CA 5] Center 36 (7~66) winsize 60
8329 00:56:09.880483
8330 00:56:09.882174 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8331 00:56:09.882590
8332 00:56:09.889283 [CATrainingPosCal] consider 2 rank data
8333 00:56:09.889763 u2DelayCellTimex100 = 275/100 ps
8334 00:56:09.895618 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8335 00:56:09.899040 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8336 00:56:09.902375 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8337 00:56:09.905607 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 00:56:09.908449 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8339 00:56:09.911688 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 00:56:09.912124
8341 00:56:09.914986 CA PerBit enable=1, Macro0, CA PI delay=36
8342 00:56:09.915441
8343 00:56:09.918357 [CBTSetCACLKResult] CA Dly = 36
8344 00:56:09.921693 CS Dly: 9 (0~42)
8345 00:56:09.925171 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 00:56:09.928224 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 00:56:09.928636
8348 00:56:09.931697 ----->DramcWriteLeveling(PI) begin...
8349 00:56:09.932129 ==
8350 00:56:09.935348 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 00:56:09.941540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 00:56:09.941958 ==
8353 00:56:09.944972 Write leveling (Byte 0): 24 => 24
8354 00:56:09.948144 Write leveling (Byte 1): 27 => 27
8355 00:56:09.948556 DramcWriteLeveling(PI) end<-----
8356 00:56:09.951247
8357 00:56:09.951746 ==
8358 00:56:09.954732 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 00:56:09.958245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 00:56:09.958659 ==
8361 00:56:09.961426 [Gating] SW mode calibration
8362 00:56:09.967600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 00:56:09.971052 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 00:56:09.977856 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 00:56:09.980837 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 00:56:09.984467 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 00:56:09.991344 1 4 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
8368 00:56:09.994633 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 00:56:09.997874 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 00:56:10.004474 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 00:56:10.007575 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 00:56:10.010855 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 00:56:10.017327 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 00:56:10.020684 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 00:56:10.024094 1 5 12 | B1->B0 | 3030 2424 | 0 0 | (0 0) (1 0)
8376 00:56:10.030760 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 00:56:10.033939 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 00:56:10.036982 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 00:56:10.043826 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 00:56:10.047414 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 00:56:10.050133 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 00:56:10.056736 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8383 00:56:10.060088 1 6 12 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
8384 00:56:10.063838 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 00:56:10.070555 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 00:56:10.073488 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 00:56:10.076991 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 00:56:10.083457 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 00:56:10.086887 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 00:56:10.089664 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8391 00:56:10.096722 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 00:56:10.100053 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 00:56:10.103243 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 00:56:10.109382 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 00:56:10.112720 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 00:56:10.116410 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 00:56:10.122593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 00:56:10.126096 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 00:56:10.129549 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 00:56:10.136100 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 00:56:10.139026 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 00:56:10.142526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 00:56:10.148770 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 00:56:10.152760 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 00:56:10.155837 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 00:56:10.162614 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8407 00:56:10.165653 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8408 00:56:10.169060 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8409 00:56:10.172565 Total UI for P1: 0, mck2ui 16
8410 00:56:10.175288 best dqsien dly found for B0: ( 1, 9, 10)
8411 00:56:10.181811 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 00:56:10.185457 Total UI for P1: 0, mck2ui 16
8413 00:56:10.188384 best dqsien dly found for B1: ( 1, 9, 14)
8414 00:56:10.191739 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8415 00:56:10.194983 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8416 00:56:10.195446
8417 00:56:10.198368 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8418 00:56:10.202202 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8419 00:56:10.205031 [Gating] SW calibration Done
8420 00:56:10.205477 ==
8421 00:56:10.208345 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 00:56:10.211658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 00:56:10.214780 ==
8424 00:56:10.215278 RX Vref Scan: 0
8425 00:56:10.215712
8426 00:56:10.218245 RX Vref 0 -> 0, step: 1
8427 00:56:10.218762
8428 00:56:10.219094 RX Delay 0 -> 252, step: 8
8429 00:56:10.224807 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8430 00:56:10.228217 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8431 00:56:10.231108 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8432 00:56:10.234705 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8433 00:56:10.241171 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8434 00:56:10.244491 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8435 00:56:10.247895 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8436 00:56:10.251338 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8437 00:56:10.254511 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8438 00:56:10.260853 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8439 00:56:10.264148 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8440 00:56:10.267649 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8441 00:56:10.270634 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8442 00:56:10.277093 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8443 00:56:10.280669 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8444 00:56:10.284143 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8445 00:56:10.284571 ==
8446 00:56:10.287349 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 00:56:10.290758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 00:56:10.291269 ==
8449 00:56:10.293689 DQS Delay:
8450 00:56:10.294202 DQS0 = 0, DQS1 = 0
8451 00:56:10.297151 DQM Delay:
8452 00:56:10.297668 DQM0 = 135, DQM1 = 129
8453 00:56:10.300165 DQ Delay:
8454 00:56:10.304237 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8455 00:56:10.307271 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8456 00:56:10.310595 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8457 00:56:10.313298 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8458 00:56:10.313724
8459 00:56:10.314057
8460 00:56:10.314369 ==
8461 00:56:10.317003 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 00:56:10.320250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 00:56:10.320761 ==
8464 00:56:10.321104
8465 00:56:10.323167
8466 00:56:10.323775 TX Vref Scan disable
8467 00:56:10.326352 == TX Byte 0 ==
8468 00:56:10.329490 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8469 00:56:10.333346 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8470 00:56:10.336504 == TX Byte 1 ==
8471 00:56:10.339993 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8472 00:56:10.343308 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8473 00:56:10.343828 ==
8474 00:56:10.345991 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 00:56:10.353066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 00:56:10.353606 ==
8477 00:56:10.364814
8478 00:56:10.368040 TX Vref early break, caculate TX vref
8479 00:56:10.371425 TX Vref=16, minBit 8, minWin=21, winSum=366
8480 00:56:10.374741 TX Vref=18, minBit 8, minWin=22, winSum=379
8481 00:56:10.377773 TX Vref=20, minBit 8, minWin=23, winSum=390
8482 00:56:10.381445 TX Vref=22, minBit 8, minWin=23, winSum=400
8483 00:56:10.384351 TX Vref=24, minBit 8, minWin=23, winSum=408
8484 00:56:10.390773 TX Vref=26, minBit 5, minWin=25, winSum=417
8485 00:56:10.394629 TX Vref=28, minBit 1, minWin=25, winSum=421
8486 00:56:10.397709 TX Vref=30, minBit 0, minWin=25, winSum=414
8487 00:56:10.400891 TX Vref=32, minBit 0, minWin=24, winSum=401
8488 00:56:10.404288 TX Vref=34, minBit 1, minWin=23, winSum=396
8489 00:56:10.410883 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8490 00:56:10.411515
8491 00:56:10.414433 Final TX Range 0 Vref 28
8492 00:56:10.414992
8493 00:56:10.415405 ==
8494 00:56:10.417416 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 00:56:10.421621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 00:56:10.422179 ==
8497 00:56:10.422552
8498 00:56:10.422894
8499 00:56:10.423949 TX Vref Scan disable
8500 00:56:10.430504 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8501 00:56:10.431068 == TX Byte 0 ==
8502 00:56:10.433476 u2DelayCellOfst[0]=17 cells (5 PI)
8503 00:56:10.436973 u2DelayCellOfst[1]=10 cells (3 PI)
8504 00:56:10.439855 u2DelayCellOfst[2]=0 cells (0 PI)
8505 00:56:10.443494 u2DelayCellOfst[3]=10 cells (3 PI)
8506 00:56:10.446707 u2DelayCellOfst[4]=7 cells (2 PI)
8507 00:56:10.450336 u2DelayCellOfst[5]=21 cells (6 PI)
8508 00:56:10.454112 u2DelayCellOfst[6]=17 cells (5 PI)
8509 00:56:10.456761 u2DelayCellOfst[7]=7 cells (2 PI)
8510 00:56:10.459820 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8511 00:56:10.463572 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8512 00:56:10.466736 == TX Byte 1 ==
8513 00:56:10.470221 u2DelayCellOfst[8]=0 cells (0 PI)
8514 00:56:10.473045 u2DelayCellOfst[9]=3 cells (1 PI)
8515 00:56:10.476397 u2DelayCellOfst[10]=10 cells (3 PI)
8516 00:56:10.479548 u2DelayCellOfst[11]=7 cells (2 PI)
8517 00:56:10.479969 u2DelayCellOfst[12]=14 cells (4 PI)
8518 00:56:10.485219 u2DelayCellOfst[13]=17 cells (5 PI)
8519 00:56:10.486321 u2DelayCellOfst[14]=17 cells (5 PI)
8520 00:56:10.489390 u2DelayCellOfst[15]=17 cells (5 PI)
8521 00:56:10.496342 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8522 00:56:10.499690 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8523 00:56:10.500121 DramC Write-DBI on
8524 00:56:10.503239 ==
8525 00:56:10.503701 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 00:56:10.509462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 00:56:10.509927 ==
8528 00:56:10.510258
8529 00:56:10.510565
8530 00:56:10.512758 TX Vref Scan disable
8531 00:56:10.513173 == TX Byte 0 ==
8532 00:56:10.519165 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8533 00:56:10.519632 == TX Byte 1 ==
8534 00:56:10.522676 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8535 00:56:10.525996 DramC Write-DBI off
8536 00:56:10.526416
8537 00:56:10.526832 [DATLAT]
8538 00:56:10.529544 Freq=1600, CH1 RK0
8539 00:56:10.529972
8540 00:56:10.530312 DATLAT Default: 0xf
8541 00:56:10.532665 0, 0xFFFF, sum = 0
8542 00:56:10.533094 1, 0xFFFF, sum = 0
8543 00:56:10.535780 2, 0xFFFF, sum = 0
8544 00:56:10.536207 3, 0xFFFF, sum = 0
8545 00:56:10.539291 4, 0xFFFF, sum = 0
8546 00:56:10.539772 5, 0xFFFF, sum = 0
8547 00:56:10.542341 6, 0xFFFF, sum = 0
8548 00:56:10.545779 7, 0xFFFF, sum = 0
8549 00:56:10.546205 8, 0xFFFF, sum = 0
8550 00:56:10.548718 9, 0xFFFF, sum = 0
8551 00:56:10.549178 10, 0xFFFF, sum = 0
8552 00:56:10.552204 11, 0xFFFF, sum = 0
8553 00:56:10.552632 12, 0xFFFF, sum = 0
8554 00:56:10.555309 13, 0xFFFF, sum = 0
8555 00:56:10.555778 14, 0x0, sum = 1
8556 00:56:10.558641 15, 0x0, sum = 2
8557 00:56:10.559067 16, 0x0, sum = 3
8558 00:56:10.562090 17, 0x0, sum = 4
8559 00:56:10.562518 best_step = 15
8560 00:56:10.562857
8561 00:56:10.563167 ==
8562 00:56:10.564932 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 00:56:10.571886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 00:56:10.572335 ==
8565 00:56:10.572678 RX Vref Scan: 1
8566 00:56:10.572994
8567 00:56:10.575060 Set Vref Range= 24 -> 127
8568 00:56:10.575518
8569 00:56:10.578341 RX Vref 24 -> 127, step: 1
8570 00:56:10.578762
8571 00:56:10.579092 RX Delay 11 -> 252, step: 4
8572 00:56:10.581512
8573 00:56:10.581926 Set Vref, RX VrefLevel [Byte0]: 24
8574 00:56:10.584637 [Byte1]: 24
8575 00:56:10.589335
8576 00:56:10.589754 Set Vref, RX VrefLevel [Byte0]: 25
8577 00:56:10.592373 [Byte1]: 25
8578 00:56:10.596769
8579 00:56:10.597184 Set Vref, RX VrefLevel [Byte0]: 26
8580 00:56:10.599933 [Byte1]: 26
8581 00:56:10.604336
8582 00:56:10.604839 Set Vref, RX VrefLevel [Byte0]: 27
8583 00:56:10.607837 [Byte1]: 27
8584 00:56:10.611917
8585 00:56:10.612332 Set Vref, RX VrefLevel [Byte0]: 28
8586 00:56:10.615331 [Byte1]: 28
8587 00:56:10.619425
8588 00:56:10.619851 Set Vref, RX VrefLevel [Byte0]: 29
8589 00:56:10.622810 [Byte1]: 29
8590 00:56:10.627161
8591 00:56:10.627618 Set Vref, RX VrefLevel [Byte0]: 30
8592 00:56:10.630360 [Byte1]: 30
8593 00:56:10.634583
8594 00:56:10.635001 Set Vref, RX VrefLevel [Byte0]: 31
8595 00:56:10.637936 [Byte1]: 31
8596 00:56:10.642512
8597 00:56:10.642993 Set Vref, RX VrefLevel [Byte0]: 32
8598 00:56:10.646168 [Byte1]: 32
8599 00:56:10.649824
8600 00:56:10.650289 Set Vref, RX VrefLevel [Byte0]: 33
8601 00:56:10.653356 [Byte1]: 33
8602 00:56:10.657826
8603 00:56:10.658245 Set Vref, RX VrefLevel [Byte0]: 34
8604 00:56:10.661011 [Byte1]: 34
8605 00:56:10.665244
8606 00:56:10.665660 Set Vref, RX VrefLevel [Byte0]: 35
8607 00:56:10.668926 [Byte1]: 35
8608 00:56:10.672890
8609 00:56:10.673517 Set Vref, RX VrefLevel [Byte0]: 36
8610 00:56:10.675980 [Byte1]: 36
8611 00:56:10.680169
8612 00:56:10.680596 Set Vref, RX VrefLevel [Byte0]: 37
8613 00:56:10.683647 [Byte1]: 37
8614 00:56:10.688327
8615 00:56:10.688742 Set Vref, RX VrefLevel [Byte0]: 38
8616 00:56:10.691203 [Byte1]: 38
8617 00:56:10.695806
8618 00:56:10.696225 Set Vref, RX VrefLevel [Byte0]: 39
8619 00:56:10.699080 [Byte1]: 39
8620 00:56:10.703432
8621 00:56:10.703852 Set Vref, RX VrefLevel [Byte0]: 40
8622 00:56:10.706433 [Byte1]: 40
8623 00:56:10.710959
8624 00:56:10.711521 Set Vref, RX VrefLevel [Byte0]: 41
8625 00:56:10.714796 [Byte1]: 41
8626 00:56:10.718703
8627 00:56:10.719123 Set Vref, RX VrefLevel [Byte0]: 42
8628 00:56:10.721663 [Byte1]: 42
8629 00:56:10.726259
8630 00:56:10.726682 Set Vref, RX VrefLevel [Byte0]: 43
8631 00:56:10.729107 [Byte1]: 43
8632 00:56:10.733882
8633 00:56:10.734299 Set Vref, RX VrefLevel [Byte0]: 44
8634 00:56:10.737114 [Byte1]: 44
8635 00:56:10.741158
8636 00:56:10.741576 Set Vref, RX VrefLevel [Byte0]: 45
8637 00:56:10.744680 [Byte1]: 45
8638 00:56:10.748806
8639 00:56:10.749222 Set Vref, RX VrefLevel [Byte0]: 46
8640 00:56:10.752244 [Byte1]: 46
8641 00:56:10.756709
8642 00:56:10.757128 Set Vref, RX VrefLevel [Byte0]: 47
8643 00:56:10.759798 [Byte1]: 47
8644 00:56:10.764005
8645 00:56:10.764424 Set Vref, RX VrefLevel [Byte0]: 48
8646 00:56:10.767430 [Byte1]: 48
8647 00:56:10.771954
8648 00:56:10.772391 Set Vref, RX VrefLevel [Byte0]: 49
8649 00:56:10.775501 [Byte1]: 49
8650 00:56:10.779265
8651 00:56:10.779748 Set Vref, RX VrefLevel [Byte0]: 50
8652 00:56:10.782743 [Byte1]: 50
8653 00:56:10.786906
8654 00:56:10.787480 Set Vref, RX VrefLevel [Byte0]: 51
8655 00:56:10.790137 [Byte1]: 51
8656 00:56:10.794633
8657 00:56:10.795051 Set Vref, RX VrefLevel [Byte0]: 52
8658 00:56:10.798126 [Byte1]: 52
8659 00:56:10.802179
8660 00:56:10.802597 Set Vref, RX VrefLevel [Byte0]: 53
8661 00:56:10.805384 [Byte1]: 53
8662 00:56:10.809655
8663 00:56:10.810070 Set Vref, RX VrefLevel [Byte0]: 54
8664 00:56:10.813289 [Byte1]: 54
8665 00:56:10.817324
8666 00:56:10.817741 Set Vref, RX VrefLevel [Byte0]: 55
8667 00:56:10.820563 [Byte1]: 55
8668 00:56:10.824787
8669 00:56:10.825248 Set Vref, RX VrefLevel [Byte0]: 56
8670 00:56:10.828530 [Byte1]: 56
8671 00:56:10.832685
8672 00:56:10.833114 Set Vref, RX VrefLevel [Byte0]: 57
8673 00:56:10.836158 [Byte1]: 57
8674 00:56:10.840303
8675 00:56:10.840829 Set Vref, RX VrefLevel [Byte0]: 58
8676 00:56:10.843242 [Byte1]: 58
8677 00:56:10.847603
8678 00:56:10.848037 Set Vref, RX VrefLevel [Byte0]: 59
8679 00:56:10.851473 [Byte1]: 59
8680 00:56:10.855648
8681 00:56:10.856064 Set Vref, RX VrefLevel [Byte0]: 60
8682 00:56:10.858789 [Byte1]: 60
8683 00:56:10.863297
8684 00:56:10.863772 Set Vref, RX VrefLevel [Byte0]: 61
8685 00:56:10.866805 [Byte1]: 61
8686 00:56:10.870482
8687 00:56:10.870897 Set Vref, RX VrefLevel [Byte0]: 62
8688 00:56:10.877112 [Byte1]: 62
8689 00:56:10.877672
8690 00:56:10.880330 Set Vref, RX VrefLevel [Byte0]: 63
8691 00:56:10.883726 [Byte1]: 63
8692 00:56:10.884148
8693 00:56:10.887110 Set Vref, RX VrefLevel [Byte0]: 64
8694 00:56:10.890121 [Byte1]: 64
8695 00:56:10.893542
8696 00:56:10.893959 Set Vref, RX VrefLevel [Byte0]: 65
8697 00:56:10.897175 [Byte1]: 65
8698 00:56:10.901083
8699 00:56:10.901523 Set Vref, RX VrefLevel [Byte0]: 66
8700 00:56:10.904586 [Byte1]: 66
8701 00:56:10.908656
8702 00:56:10.909073 Set Vref, RX VrefLevel [Byte0]: 67
8703 00:56:10.912269 [Byte1]: 67
8704 00:56:10.916244
8705 00:56:10.916662 Set Vref, RX VrefLevel [Byte0]: 68
8706 00:56:10.919508 [Byte1]: 68
8707 00:56:10.923734
8708 00:56:10.924153 Set Vref, RX VrefLevel [Byte0]: 69
8709 00:56:10.927251 [Byte1]: 69
8710 00:56:10.931945
8711 00:56:10.932362 Set Vref, RX VrefLevel [Byte0]: 70
8712 00:56:10.934559 [Byte1]: 70
8713 00:56:10.939331
8714 00:56:10.939799 Final RX Vref Byte 0 = 55 to rank0
8715 00:56:10.942719 Final RX Vref Byte 1 = 61 to rank0
8716 00:56:10.945913 Final RX Vref Byte 0 = 55 to rank1
8717 00:56:10.949240 Final RX Vref Byte 1 = 61 to rank1==
8718 00:56:10.952556 Dram Type= 6, Freq= 0, CH_1, rank 0
8719 00:56:10.958754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 00:56:10.959179 ==
8721 00:56:10.959576 DQS Delay:
8722 00:56:10.962143 DQS0 = 0, DQS1 = 0
8723 00:56:10.962588 DQM Delay:
8724 00:56:10.962925 DQM0 = 132, DQM1 = 128
8725 00:56:10.965695 DQ Delay:
8726 00:56:10.969128 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =130
8727 00:56:10.972118 DQ4 =128, DQ5 =144, DQ6 =144, DQ7 =126
8728 00:56:10.975430 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8729 00:56:10.978646 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8730 00:56:10.979089
8731 00:56:10.979569
8732 00:56:10.979894
8733 00:56:10.981670 [DramC_TX_OE_Calibration] TA2
8734 00:56:10.985261 Original DQ_B0 (3 6) =30, OEN = 27
8735 00:56:10.988711 Original DQ_B1 (3 6) =30, OEN = 27
8736 00:56:10.991911 24, 0x0, End_B0=24 End_B1=24
8737 00:56:10.995023 25, 0x0, End_B0=25 End_B1=25
8738 00:56:10.995517 26, 0x0, End_B0=26 End_B1=26
8739 00:56:10.998567 27, 0x0, End_B0=27 End_B1=27
8740 00:56:11.001674 28, 0x0, End_B0=28 End_B1=28
8741 00:56:11.005089 29, 0x0, End_B0=29 End_B1=29
8742 00:56:11.005521 30, 0x0, End_B0=30 End_B1=30
8743 00:56:11.008493 31, 0x4141, End_B0=30 End_B1=30
8744 00:56:11.011432 Byte0 end_step=30 best_step=27
8745 00:56:11.015140 Byte1 end_step=30 best_step=27
8746 00:56:11.018045 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 00:56:11.021770 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 00:56:11.022190
8749 00:56:11.022562
8750 00:56:11.028313 [DQSOSCAuto] RK0, (LSB)MR18= 0xe18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8751 00:56:11.031588 CH1 RK0: MR19=303, MR18=E18
8752 00:56:11.038185 CH1_RK0: MR19=0x303, MR18=0xE18, DQSOSC=397, MR23=63, INC=23, DEC=15
8753 00:56:11.038608
8754 00:56:11.041661 ----->DramcWriteLeveling(PI) begin...
8755 00:56:11.042085 ==
8756 00:56:11.044561 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 00:56:11.047776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 00:56:11.048283 ==
8759 00:56:11.051242 Write leveling (Byte 0): 25 => 25
8760 00:56:11.055044 Write leveling (Byte 1): 25 => 25
8761 00:56:11.057794 DramcWriteLeveling(PI) end<-----
8762 00:56:11.058215
8763 00:56:11.058545 ==
8764 00:56:11.061142 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 00:56:11.064404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 00:56:11.067982 ==
8767 00:56:11.068401 [Gating] SW mode calibration
8768 00:56:11.074534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8769 00:56:11.081347 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8770 00:56:11.084513 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 00:56:11.090846 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 00:56:11.094131 1 4 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
8773 00:56:11.097360 1 4 12 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
8774 00:56:11.103784 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 00:56:11.106895 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 00:56:11.110413 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 00:56:11.117500 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 00:56:11.120615 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 00:56:11.123943 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8780 00:56:11.130368 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8781 00:56:11.133373 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8782 00:56:11.136549 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 00:56:11.143469 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 00:56:11.146670 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 00:56:11.150288 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 00:56:11.156369 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 00:56:11.159677 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8788 00:56:11.163319 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8789 00:56:11.169914 1 6 12 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8790 00:56:11.172868 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 00:56:11.176200 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 00:56:11.182979 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 00:56:11.186005 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 00:56:11.189425 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 00:56:11.196136 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 00:56:11.199469 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8797 00:56:11.202534 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8798 00:56:11.208946 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8799 00:56:11.212479 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 00:56:11.215649 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 00:56:11.222781 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 00:56:11.225444 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 00:56:11.232019 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 00:56:11.235294 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 00:56:11.238685 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 00:56:11.245334 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 00:56:11.248348 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 00:56:11.251912 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 00:56:11.258791 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 00:56:11.261821 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 00:56:11.264919 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 00:56:11.271520 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 00:56:11.274638 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8814 00:56:11.278591 Total UI for P1: 0, mck2ui 16
8815 00:56:11.281175 best dqsien dly found for B0: ( 1, 9, 6)
8816 00:56:11.284901 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8817 00:56:11.291301 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 00:56:11.291825 Total UI for P1: 0, mck2ui 16
8819 00:56:11.295201 best dqsien dly found for B1: ( 1, 9, 14)
8820 00:56:11.297894 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8821 00:56:11.304611 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8822 00:56:11.305036
8823 00:56:11.307746 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8824 00:56:11.311266 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8825 00:56:11.314465 [Gating] SW calibration Done
8826 00:56:11.314886 ==
8827 00:56:11.317905 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 00:56:11.320798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 00:56:11.321225 ==
8830 00:56:11.324445 RX Vref Scan: 0
8831 00:56:11.324862
8832 00:56:11.325198 RX Vref 0 -> 0, step: 1
8833 00:56:11.325644
8834 00:56:11.327878 RX Delay 0 -> 252, step: 8
8835 00:56:11.330865 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8836 00:56:11.337939 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8837 00:56:11.341332 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8838 00:56:11.344440 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8839 00:56:11.347989 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8840 00:56:11.351177 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8841 00:56:11.357599 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8842 00:56:11.360758 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8843 00:56:11.363676 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8844 00:56:11.366915 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8845 00:56:11.370038 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 00:56:11.376986 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8847 00:56:11.380132 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8848 00:56:11.383835 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 00:56:11.386591 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8850 00:56:11.393420 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8851 00:56:11.393958 ==
8852 00:56:11.396616 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 00:56:11.400273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 00:56:11.400696 ==
8855 00:56:11.401030 DQS Delay:
8856 00:56:11.403259 DQS0 = 0, DQS1 = 0
8857 00:56:11.403731 DQM Delay:
8858 00:56:11.406379 DQM0 = 133, DQM1 = 131
8859 00:56:11.406834 DQ Delay:
8860 00:56:11.409731 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8861 00:56:11.412930 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8862 00:56:11.416185 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8863 00:56:11.419796 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8864 00:56:11.422958
8865 00:56:11.423430
8866 00:56:11.423788 ==
8867 00:56:11.426170 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 00:56:11.429502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 00:56:11.429924 ==
8870 00:56:11.430259
8871 00:56:11.430569
8872 00:56:11.432598 TX Vref Scan disable
8873 00:56:11.433149 == TX Byte 0 ==
8874 00:56:11.439649 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8875 00:56:11.442507 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8876 00:56:11.442929 == TX Byte 1 ==
8877 00:56:11.449668 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8878 00:56:11.452536 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8879 00:56:11.452956 ==
8880 00:56:11.456061 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 00:56:11.458988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 00:56:11.459451 ==
8883 00:56:11.473723
8884 00:56:11.476904 TX Vref early break, caculate TX vref
8885 00:56:11.480410 TX Vref=16, minBit 9, minWin=21, winSum=383
8886 00:56:11.483632 TX Vref=18, minBit 9, minWin=23, winSum=391
8887 00:56:11.486968 TX Vref=20, minBit 9, minWin=23, winSum=398
8888 00:56:11.490321 TX Vref=22, minBit 9, minWin=23, winSum=404
8889 00:56:11.493242 TX Vref=24, minBit 9, minWin=24, winSum=410
8890 00:56:11.499639 TX Vref=26, minBit 5, minWin=25, winSum=422
8891 00:56:11.503242 TX Vref=28, minBit 9, minWin=24, winSum=421
8892 00:56:11.506450 TX Vref=30, minBit 5, minWin=24, winSum=417
8893 00:56:11.509768 TX Vref=32, minBit 5, minWin=24, winSum=407
8894 00:56:11.513217 TX Vref=34, minBit 5, minWin=24, winSum=403
8895 00:56:11.519812 TX Vref=36, minBit 0, minWin=23, winSum=394
8896 00:56:11.522961 [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 26
8897 00:56:11.523570
8898 00:56:11.526320 Final TX Range 0 Vref 26
8899 00:56:11.526743
8900 00:56:11.527076 ==
8901 00:56:11.529656 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 00:56:11.532490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 00:56:11.535886 ==
8904 00:56:11.536305
8905 00:56:11.536636
8906 00:56:11.536945 TX Vref Scan disable
8907 00:56:11.542959 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8908 00:56:11.543419 == TX Byte 0 ==
8909 00:56:11.545905 u2DelayCellOfst[0]=17 cells (5 PI)
8910 00:56:11.549244 u2DelayCellOfst[1]=10 cells (3 PI)
8911 00:56:11.552751 u2DelayCellOfst[2]=0 cells (0 PI)
8912 00:56:11.555700 u2DelayCellOfst[3]=7 cells (2 PI)
8913 00:56:11.559241 u2DelayCellOfst[4]=7 cells (2 PI)
8914 00:56:11.562838 u2DelayCellOfst[5]=17 cells (5 PI)
8915 00:56:11.566030 u2DelayCellOfst[6]=17 cells (5 PI)
8916 00:56:11.569255 u2DelayCellOfst[7]=3 cells (1 PI)
8917 00:56:11.572148 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8918 00:56:11.575791 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8919 00:56:11.579168 == TX Byte 1 ==
8920 00:56:11.582184 u2DelayCellOfst[8]=0 cells (0 PI)
8921 00:56:11.585568 u2DelayCellOfst[9]=3 cells (1 PI)
8922 00:56:11.589309 u2DelayCellOfst[10]=14 cells (4 PI)
8923 00:56:11.592246 u2DelayCellOfst[11]=7 cells (2 PI)
8924 00:56:11.595420 u2DelayCellOfst[12]=14 cells (4 PI)
8925 00:56:11.599629 u2DelayCellOfst[13]=17 cells (5 PI)
8926 00:56:11.602386 u2DelayCellOfst[14]=21 cells (6 PI)
8927 00:56:11.602810 u2DelayCellOfst[15]=21 cells (6 PI)
8928 00:56:11.608842 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8929 00:56:11.612224 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8930 00:56:11.615048 DramC Write-DBI on
8931 00:56:11.615512 ==
8932 00:56:11.618692 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 00:56:11.621500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 00:56:11.621938 ==
8935 00:56:11.622276
8936 00:56:11.622588
8937 00:56:11.624958 TX Vref Scan disable
8938 00:56:11.625437 == TX Byte 0 ==
8939 00:56:11.631428 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8940 00:56:11.631856 == TX Byte 1 ==
8941 00:56:11.638272 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8942 00:56:11.638764 DramC Write-DBI off
8943 00:56:11.639100
8944 00:56:11.639457 [DATLAT]
8945 00:56:11.641409 Freq=1600, CH1 RK1
8946 00:56:11.641924
8947 00:56:11.644679 DATLAT Default: 0xf
8948 00:56:11.645256 0, 0xFFFF, sum = 0
8949 00:56:11.647859 1, 0xFFFF, sum = 0
8950 00:56:11.648322 2, 0xFFFF, sum = 0
8951 00:56:11.651468 3, 0xFFFF, sum = 0
8952 00:56:11.651989 4, 0xFFFF, sum = 0
8953 00:56:11.654314 5, 0xFFFF, sum = 0
8954 00:56:11.654878 6, 0xFFFF, sum = 0
8955 00:56:11.658255 7, 0xFFFF, sum = 0
8956 00:56:11.658794 8, 0xFFFF, sum = 0
8957 00:56:11.661280 9, 0xFFFF, sum = 0
8958 00:56:11.661701 10, 0xFFFF, sum = 0
8959 00:56:11.664717 11, 0xFFFF, sum = 0
8960 00:56:11.665136 12, 0xFFFF, sum = 0
8961 00:56:11.667733 13, 0xFFFF, sum = 0
8962 00:56:11.668167 14, 0x0, sum = 1
8963 00:56:11.671121 15, 0x0, sum = 2
8964 00:56:11.671671 16, 0x0, sum = 3
8965 00:56:11.674062 17, 0x0, sum = 4
8966 00:56:11.674500 best_step = 15
8967 00:56:11.674835
8968 00:56:11.675164 ==
8969 00:56:11.677791 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 00:56:11.684350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 00:56:11.684830 ==
8972 00:56:11.685170 RX Vref Scan: 0
8973 00:56:11.685501
8974 00:56:11.687195 RX Vref 0 -> 0, step: 1
8975 00:56:11.687710
8976 00:56:11.691509 RX Delay 19 -> 252, step: 4
8977 00:56:11.694224 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8978 00:56:11.697229 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8979 00:56:11.703894 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8980 00:56:11.707352 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8981 00:56:11.710252 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8982 00:56:11.713593 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8983 00:56:11.716908 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8984 00:56:11.723409 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8985 00:56:11.727072 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8986 00:56:11.730158 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8987 00:56:11.733220 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8988 00:56:11.736803 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8989 00:56:11.743263 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8990 00:56:11.746419 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8991 00:56:11.749904 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8992 00:56:11.753166 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8993 00:56:11.756325 ==
8994 00:56:11.759781 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 00:56:11.763055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 00:56:11.763521 ==
8997 00:56:11.763958 DQS Delay:
8998 00:56:11.766063 DQS0 = 0, DQS1 = 0
8999 00:56:11.766536 DQM Delay:
9000 00:56:11.769691 DQM0 = 131, DQM1 = 128
9001 00:56:11.770192 DQ Delay:
9002 00:56:11.773092 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
9003 00:56:11.776013 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9004 00:56:11.779202 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
9005 00:56:11.782952 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9006 00:56:11.783458
9007 00:56:11.783808
9008 00:56:11.784205
9009 00:56:11.785782 [DramC_TX_OE_Calibration] TA2
9010 00:56:11.789319 Original DQ_B0 (3 6) =30, OEN = 27
9011 00:56:11.792774 Original DQ_B1 (3 6) =30, OEN = 27
9012 00:56:11.795949 24, 0x0, End_B0=24 End_B1=24
9013 00:56:11.799324 25, 0x0, End_B0=25 End_B1=25
9014 00:56:11.799787 26, 0x0, End_B0=26 End_B1=26
9015 00:56:11.802280 27, 0x0, End_B0=27 End_B1=27
9016 00:56:11.806021 28, 0x0, End_B0=28 End_B1=28
9017 00:56:11.809288 29, 0x0, End_B0=29 End_B1=29
9018 00:56:11.812359 30, 0x0, End_B0=30 End_B1=30
9019 00:56:11.815477 31, 0x4141, End_B0=30 End_B1=30
9020 00:56:11.815899 Byte0 end_step=30 best_step=27
9021 00:56:11.819128 Byte1 end_step=30 best_step=27
9022 00:56:11.822397 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 00:56:11.825368 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 00:56:11.825785
9025 00:56:11.826112
9026 00:56:11.832233 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9027 00:56:11.835274 CH1 RK1: MR19=303, MR18=101E
9028 00:56:11.842297 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
9029 00:56:11.845613 [RxdqsGatingPostProcess] freq 1600
9030 00:56:11.851962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 00:56:11.855016 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 00:56:11.858584 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 00:56:11.859001 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 00:56:11.861703 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 00:56:11.864842 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 00:56:11.868419 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 00:56:11.871859 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 00:56:11.874596 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 00:56:11.878246 Pre-setting of DQS Precalculation
9040 00:56:11.884662 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 00:56:11.891135 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 00:56:11.897604 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 00:56:11.898312
9044 00:56:11.898913
9045 00:56:11.900971 [Calibration Summary] 3200 Mbps
9046 00:56:11.901408 CH 0, Rank 0
9047 00:56:11.904495 SW Impedance : PASS
9048 00:56:11.907393 DUTY Scan : NO K
9049 00:56:11.907817 ZQ Calibration : PASS
9050 00:56:11.911070 Jitter Meter : NO K
9051 00:56:11.914098 CBT Training : PASS
9052 00:56:11.914517 Write leveling : PASS
9053 00:56:11.917914 RX DQS gating : PASS
9054 00:56:11.920942 RX DQ/DQS(RDDQC) : PASS
9055 00:56:11.921360 TX DQ/DQS : PASS
9056 00:56:11.924345 RX DATLAT : PASS
9057 00:56:11.927432 RX DQ/DQS(Engine): PASS
9058 00:56:11.927855 TX OE : PASS
9059 00:56:11.928191 All Pass.
9060 00:56:11.930770
9061 00:56:11.931185 CH 0, Rank 1
9062 00:56:11.934197 SW Impedance : PASS
9063 00:56:11.934617 DUTY Scan : NO K
9064 00:56:11.937482 ZQ Calibration : PASS
9065 00:56:11.937902 Jitter Meter : NO K
9066 00:56:11.941358 CBT Training : PASS
9067 00:56:11.944135 Write leveling : PASS
9068 00:56:11.944638 RX DQS gating : PASS
9069 00:56:11.947492 RX DQ/DQS(RDDQC) : PASS
9070 00:56:11.950498 TX DQ/DQS : PASS
9071 00:56:11.951076 RX DATLAT : PASS
9072 00:56:11.953880 RX DQ/DQS(Engine): PASS
9073 00:56:11.957513 TX OE : PASS
9074 00:56:11.958024 All Pass.
9075 00:56:11.958425
9076 00:56:11.958755 CH 1, Rank 0
9077 00:56:11.960735 SW Impedance : PASS
9078 00:56:11.963770 DUTY Scan : NO K
9079 00:56:11.964184 ZQ Calibration : PASS
9080 00:56:11.967018 Jitter Meter : NO K
9081 00:56:11.970412 CBT Training : PASS
9082 00:56:11.970825 Write leveling : PASS
9083 00:56:11.973835 RX DQS gating : PASS
9084 00:56:11.976960 RX DQ/DQS(RDDQC) : PASS
9085 00:56:11.977405 TX DQ/DQS : PASS
9086 00:56:11.980470 RX DATLAT : PASS
9087 00:56:11.983658 RX DQ/DQS(Engine): PASS
9088 00:56:11.984161 TX OE : PASS
9089 00:56:11.987181 All Pass.
9090 00:56:11.987646
9091 00:56:11.988014 CH 1, Rank 1
9092 00:56:11.990534 SW Impedance : PASS
9093 00:56:11.991081 DUTY Scan : NO K
9094 00:56:11.993493 ZQ Calibration : PASS
9095 00:56:11.996634 Jitter Meter : NO K
9096 00:56:11.997055 CBT Training : PASS
9097 00:56:12.000333 Write leveling : PASS
9098 00:56:12.003316 RX DQS gating : PASS
9099 00:56:12.003892 RX DQ/DQS(RDDQC) : PASS
9100 00:56:12.006741 TX DQ/DQS : PASS
9101 00:56:12.010230 RX DATLAT : PASS
9102 00:56:12.010646 RX DQ/DQS(Engine): PASS
9103 00:56:12.013150 TX OE : PASS
9104 00:56:12.013663 All Pass.
9105 00:56:12.014020
9106 00:56:12.016710 DramC Write-DBI on
9107 00:56:12.019840 PER_BANK_REFRESH: Hybrid Mode
9108 00:56:12.020293 TX_TRACKING: ON
9109 00:56:12.029437 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 00:56:12.036583 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 00:56:12.042623 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 00:56:12.046329 [FAST_K] Save calibration result to emmc
9113 00:56:12.049428 sync common calibartion params.
9114 00:56:12.052461 sync cbt_mode0:1, 1:1
9115 00:56:12.056110 dram_init: ddr_geometry: 2
9116 00:56:12.056526 dram_init: ddr_geometry: 2
9117 00:56:12.059223 dram_init: ddr_geometry: 2
9118 00:56:12.062439 0:dram_rank_size:100000000
9119 00:56:12.066038 1:dram_rank_size:100000000
9120 00:56:12.069201 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 00:56:12.072883 DFS_SHUFFLE_HW_MODE: ON
9122 00:56:12.075568 dramc_set_vcore_voltage set vcore to 725000
9123 00:56:12.078895 Read voltage for 1600, 0
9124 00:56:12.079307 Vio18 = 0
9125 00:56:12.079692 Vcore = 725000
9126 00:56:12.082199 Vdram = 0
9127 00:56:12.082643 Vddq = 0
9128 00:56:12.082988 Vmddr = 0
9129 00:56:12.085872 switch to 3200 Mbps bootup
9130 00:56:12.089182 [DramcRunTimeConfig]
9131 00:56:12.089596 PHYPLL
9132 00:56:12.089925 DPM_CONTROL_AFTERK: ON
9133 00:56:12.092228 PER_BANK_REFRESH: ON
9134 00:56:12.095503 REFRESH_OVERHEAD_REDUCTION: ON
9135 00:56:12.095986 CMD_PICG_NEW_MODE: OFF
9136 00:56:12.098768 XRTWTW_NEW_MODE: ON
9137 00:56:12.102064 XRTRTR_NEW_MODE: ON
9138 00:56:12.102512 TX_TRACKING: ON
9139 00:56:12.105531 RDSEL_TRACKING: OFF
9140 00:56:12.105963 DQS Precalculation for DVFS: ON
9141 00:56:12.108908 RX_TRACKING: OFF
9142 00:56:12.109342 HW_GATING DBG: ON
9143 00:56:12.111817 ZQCS_ENABLE_LP4: ON
9144 00:56:12.115096 RX_PICG_NEW_MODE: ON
9145 00:56:12.115552 TX_PICG_NEW_MODE: ON
9146 00:56:12.118705 ENABLE_RX_DCM_DPHY: ON
9147 00:56:12.121987 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 00:56:12.122430 DUMMY_READ_FOR_TRACKING: OFF
9149 00:56:12.124953 !!! SPM_CONTROL_AFTERK: OFF
9150 00:56:12.128404 !!! SPM could not control APHY
9151 00:56:12.131905 IMPEDANCE_TRACKING: ON
9152 00:56:12.132357 TEMP_SENSOR: ON
9153 00:56:12.134951 HW_SAVE_FOR_SR: OFF
9154 00:56:12.138352 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 00:56:12.141605 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 00:56:12.142044 Read ODT Tracking: ON
9157 00:56:12.145011 Refresh Rate DeBounce: ON
9158 00:56:12.148442 DFS_NO_QUEUE_FLUSH: ON
9159 00:56:12.151862 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 00:56:12.152374 ENABLE_DFS_RUNTIME_MRW: OFF
9161 00:56:12.154651 DDR_RESERVE_NEW_MODE: ON
9162 00:56:12.158368 MR_CBT_SWITCH_FREQ: ON
9163 00:56:12.158786 =========================
9164 00:56:12.178358 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 00:56:12.181191 dram_init: ddr_geometry: 2
9166 00:56:12.199901 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 00:56:12.202821 dram_init: dram init end (result: 0)
9168 00:56:12.209434 DRAM-K: Full calibration passed in 24418 msecs
9169 00:56:12.212816 MRC: failed to locate region type 0.
9170 00:56:12.213243 DRAM rank0 size:0x100000000,
9171 00:56:12.216021 DRAM rank1 size=0x100000000
9172 00:56:12.226191 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 00:56:12.232490 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 00:56:12.242422 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 00:56:12.248913 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 00:56:12.249414 DRAM rank0 size:0x100000000,
9177 00:56:12.252288 DRAM rank1 size=0x100000000
9178 00:56:12.252774 CBMEM:
9179 00:56:12.255843 IMD: root @ 0xfffff000 254 entries.
9180 00:56:12.258812 IMD: root @ 0xffffec00 62 entries.
9181 00:56:12.265432 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 00:56:12.268640 WARNING: RO_VPD is uninitialized or empty.
9183 00:56:12.271442 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 00:56:12.279925 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 00:56:12.292776 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9186 00:56:12.304169 BS: romstage times (exec / console): total (unknown) / 23946 ms
9187 00:56:12.304768
9188 00:56:12.305175
9189 00:56:12.313558 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 00:56:12.317433 ARM64: Exception handlers installed.
9191 00:56:12.320154 ARM64: Testing exception
9192 00:56:12.323618 ARM64: Done test exception
9193 00:56:12.324055 Enumerating buses...
9194 00:56:12.326972 Show all devs... Before device enumeration.
9195 00:56:12.330177 Root Device: enabled 1
9196 00:56:12.333396 CPU_CLUSTER: 0: enabled 1
9197 00:56:12.333816 CPU: 00: enabled 1
9198 00:56:12.336993 Compare with tree...
9199 00:56:12.337412 Root Device: enabled 1
9200 00:56:12.339791 CPU_CLUSTER: 0: enabled 1
9201 00:56:12.343149 CPU: 00: enabled 1
9202 00:56:12.343675 Root Device scanning...
9203 00:56:12.346790 scan_static_bus for Root Device
9204 00:56:12.349645 CPU_CLUSTER: 0 enabled
9205 00:56:12.353061 scan_static_bus for Root Device done
9206 00:56:12.356327 scan_bus: bus Root Device finished in 8 msecs
9207 00:56:12.356777 done
9208 00:56:12.362885 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 00:56:12.366441 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 00:56:12.372658 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 00:56:12.379631 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 00:56:12.380183 Allocating resources...
9213 00:56:12.382632 Reading resources...
9214 00:56:12.385862 Root Device read_resources bus 0 link: 0
9215 00:56:12.389011 DRAM rank0 size:0x100000000,
9216 00:56:12.389454 DRAM rank1 size=0x100000000
9217 00:56:12.395742 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 00:56:12.396183 CPU: 00 missing read_resources
9219 00:56:12.402591 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 00:56:12.405699 Root Device read_resources bus 0 link: 0 done
9221 00:56:12.409512 Done reading resources.
9222 00:56:12.412486 Show resources in subtree (Root Device)...After reading.
9223 00:56:12.415901 Root Device child on link 0 CPU_CLUSTER: 0
9224 00:56:12.418686 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 00:56:12.428438 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 00:56:12.428971 CPU: 00
9227 00:56:12.435231 Root Device assign_resources, bus 0 link: 0
9228 00:56:12.438541 CPU_CLUSTER: 0 missing set_resources
9229 00:56:12.441996 Root Device assign_resources, bus 0 link: 0 done
9230 00:56:12.444954 Done setting resources.
9231 00:56:12.448523 Show resources in subtree (Root Device)...After assigning values.
9232 00:56:12.455414 Root Device child on link 0 CPU_CLUSTER: 0
9233 00:56:12.458385 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 00:56:12.465448 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 00:56:12.468256 CPU: 00
9236 00:56:12.468715 Done allocating resources.
9237 00:56:12.474628 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 00:56:12.478190 Enabling resources...
9239 00:56:12.478648 done.
9240 00:56:12.481544 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 00:56:12.484779 Initializing devices...
9242 00:56:12.485246 Root Device init
9243 00:56:12.487780 init hardware done!
9244 00:56:12.491231 0x00000018: ctrlr->caps
9245 00:56:12.491722 52.000 MHz: ctrlr->f_max
9246 00:56:12.494346 0.400 MHz: ctrlr->f_min
9247 00:56:12.497616 0x40ff8080: ctrlr->voltages
9248 00:56:12.498067 sclk: 390625
9249 00:56:12.498400 Bus Width = 1
9250 00:56:12.501446 sclk: 390625
9251 00:56:12.501870 Bus Width = 1
9252 00:56:12.504503 Early init status = 3
9253 00:56:12.507762 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 00:56:12.512126 in-header: 03 fc 00 00 01 00 00 00
9255 00:56:12.515622 in-data: 00
9256 00:56:12.518514 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 00:56:12.524600 in-header: 03 fd 00 00 00 00 00 00
9258 00:56:12.527850 in-data:
9259 00:56:12.530803 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 00:56:12.535237 in-header: 03 fc 00 00 01 00 00 00
9261 00:56:12.538659 in-data: 00
9262 00:56:12.541810 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 00:56:12.547624 in-header: 03 fd 00 00 00 00 00 00
9264 00:56:12.550767 in-data:
9265 00:56:12.554323 [SSUSB] Setting up USB HOST controller...
9266 00:56:12.558253 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 00:56:12.561585 [SSUSB] phy power-on done.
9268 00:56:12.564851 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 00:56:12.570953 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 00:56:12.574254 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 00:56:12.580980 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 00:56:12.587407 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9273 00:56:12.594436 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 00:56:12.601094 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 00:56:12.607635 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9276 00:56:12.610426 SPM: binary array size = 0x9dc
9277 00:56:12.613799 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 00:56:12.620358 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 00:56:12.626802 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 00:56:12.633465 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 00:56:12.637102 configure_display: Starting display init
9282 00:56:12.671070 anx7625_power_on_init: Init interface.
9283 00:56:12.674123 anx7625_disable_pd_protocol: Disabled PD feature.
9284 00:56:12.677501 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 00:56:12.705335 anx7625_start_dp_work: Secure OCM version=00
9286 00:56:12.708961 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 00:56:12.723939 sp_tx_get_edid_block: EDID Block = 1
9288 00:56:12.826257 Extracted contents:
9289 00:56:12.829664 header: 00 ff ff ff ff ff ff 00
9290 00:56:12.832600 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 00:56:12.835771 version: 01 04
9292 00:56:12.839304 basic params: 95 1f 11 78 0a
9293 00:56:12.842929 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 00:56:12.845803 established: 00 00 00
9295 00:56:12.852362 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 00:56:12.859009 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 00:56:12.862602 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 00:56:12.868857 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 00:56:12.875553 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 00:56:12.879116 extensions: 00
9301 00:56:12.879580 checksum: fb
9302 00:56:12.879925
9303 00:56:12.885220 Manufacturer: IVO Model 57d Serial Number 0
9304 00:56:12.885644 Made week 0 of 2020
9305 00:56:12.888877 EDID version: 1.4
9306 00:56:12.889389 Digital display
9307 00:56:12.891650 6 bits per primary color channel
9308 00:56:12.894993 DisplayPort interface
9309 00:56:12.895567 Maximum image size: 31 cm x 17 cm
9310 00:56:12.898604 Gamma: 220%
9311 00:56:12.899029 Check DPMS levels
9312 00:56:12.904779 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 00:56:12.908299 First detailed timing is preferred timing
9314 00:56:12.911646 Established timings supported:
9315 00:56:12.912096 Standard timings supported:
9316 00:56:12.915108 Detailed timings
9317 00:56:12.918242 Hex of detail: 383680a07038204018303c0035ae10000019
9318 00:56:12.924681 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 00:56:12.928372 0780 0798 07c8 0820 hborder 0
9320 00:56:12.931135 0438 043b 0447 0458 vborder 0
9321 00:56:12.935251 -hsync -vsync
9322 00:56:12.935715 Did detailed timing
9323 00:56:12.941241 Hex of detail: 000000000000000000000000000000000000
9324 00:56:12.944467 Manufacturer-specified data, tag 0
9325 00:56:12.947937 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 00:56:12.950962 ASCII string: InfoVision
9327 00:56:12.954657 Hex of detail: 000000fe00523134304e574635205248200a
9328 00:56:12.957629 ASCII string: R140NWF5 RH
9329 00:56:12.958074 Checksum
9330 00:56:12.961120 Checksum: 0xfb (valid)
9331 00:56:12.963999 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 00:56:12.967453 DSI data_rate: 832800000 bps
9333 00:56:12.974316 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 00:56:12.977171 anx7625_parse_edid: pixelclock(138800).
9335 00:56:12.980531 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 00:56:12.983891 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 00:56:12.987624 anx7625_dsi_config: config dsi.
9338 00:56:12.994167 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 00:56:13.008027 anx7625_dsi_config: success to config DSI
9340 00:56:13.011523 anx7625_dp_start: MIPI phy setup OK.
9341 00:56:13.015045 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 00:56:13.017948 mtk_ddp_mode_set invalid vrefresh 60
9343 00:56:13.021403 main_disp_path_setup
9344 00:56:13.021824 ovl_layer_smi_id_en
9345 00:56:13.024564 ovl_layer_smi_id_en
9346 00:56:13.024979 ccorr_config
9347 00:56:13.025310 aal_config
9348 00:56:13.027838 gamma_config
9349 00:56:13.028321 postmask_config
9350 00:56:13.031666 dither_config
9351 00:56:13.034227 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 00:56:13.041225 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 00:56:13.044505 Root Device init finished in 555 msecs
9354 00:56:13.047331 CPU_CLUSTER: 0 init
9355 00:56:13.054585 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 00:56:13.060708 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 00:56:13.061129 APU_MBOX 0x190000b0 = 0x10001
9358 00:56:13.064143 APU_MBOX 0x190001b0 = 0x10001
9359 00:56:13.067636 APU_MBOX 0x190005b0 = 0x10001
9360 00:56:13.070564 APU_MBOX 0x190006b0 = 0x10001
9361 00:56:13.077249 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 00:56:13.087355 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9363 00:56:13.099575 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 00:56:13.106022 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 00:56:13.117700 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9366 00:56:13.126703 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 00:56:13.130262 CPU_CLUSTER: 0 init finished in 81 msecs
9368 00:56:13.133856 Devices initialized
9369 00:56:13.136880 Show all devs... After init.
9370 00:56:13.137296 Root Device: enabled 1
9371 00:56:13.140235 CPU_CLUSTER: 0: enabled 1
9372 00:56:13.143196 CPU: 00: enabled 1
9373 00:56:13.146919 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9374 00:56:13.149726 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 00:56:13.153218 ELOG: NV offset 0x57f000 size 0x1000
9376 00:56:13.160547 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9377 00:56:13.166737 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 00:56:13.170233 ELOG: Event(17) added with size 13 at 2024-01-19 00:56:14 UTC
9379 00:56:13.176684 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 00:56:13.180312 in-header: 03 2e 00 00 2c 00 00 00
9381 00:56:13.189564 in-data: 31 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 00:56:13.196373 ELOG: Event(A1) added with size 10 at 2024-01-19 00:56:14 UTC
9383 00:56:13.203095 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 00:56:13.209575 ELOG: Event(A0) added with size 9 at 2024-01-19 00:56:14 UTC
9385 00:56:13.213152 elog_add_boot_reason: Logged dev mode boot
9386 00:56:13.219408 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9387 00:56:13.219844 Finalize devices...
9388 00:56:13.222821 Devices finalized
9389 00:56:13.225873 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 00:56:13.229236 Writing coreboot table at 0xffe64000
9391 00:56:13.232284 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 00:56:13.238948 1. 0000000040000000-00000000400fffff: RAM
9393 00:56:13.242291 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 00:56:13.245749 3. 000000004032b000-00000000545fffff: RAM
9395 00:56:13.248724 4. 0000000054600000-000000005465ffff: BL31
9396 00:56:13.252197 5. 0000000054660000-00000000ffe63fff: RAM
9397 00:56:13.258887 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 00:56:13.261897 7. 0000000100000000-000000023fffffff: RAM
9399 00:56:13.265307 Passing 5 GPIOs to payload:
9400 00:56:13.268735 NAME | PORT | POLARITY | VALUE
9401 00:56:13.275223 EC in RW | 0x000000aa | low | undefined
9402 00:56:13.278356 EC interrupt | 0x00000005 | low | undefined
9403 00:56:13.285729 TPM interrupt | 0x000000ab | high | undefined
9404 00:56:13.288427 SD card detect | 0x00000011 | high | undefined
9405 00:56:13.291949 speaker enable | 0x00000093 | high | undefined
9406 00:56:13.294659 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 00:56:13.298925 in-header: 03 f9 00 00 02 00 00 00
9408 00:56:13.302772 in-data: 02 00
9409 00:56:13.306386 ADC[4]: Raw value=903694 ID=7
9410 00:56:13.306838 ADC[3]: Raw value=213916 ID=1
9411 00:56:13.309442 RAM Code: 0x71
9412 00:56:13.312536 ADC[6]: Raw value=75000 ID=0
9413 00:56:13.316473 ADC[5]: Raw value=213916 ID=1
9414 00:56:13.316879 SKU Code: 0x1
9415 00:56:13.322586 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 27f4
9416 00:56:13.323038 coreboot table: 964 bytes.
9417 00:56:13.325748 IMD ROOT 0. 0xfffff000 0x00001000
9418 00:56:13.329307 IMD SMALL 1. 0xffffe000 0x00001000
9419 00:56:13.332086 RO MCACHE 2. 0xffffc000 0x00001104
9420 00:56:13.335428 CONSOLE 3. 0xfff7c000 0x00080000
9421 00:56:13.338963 FMAP 4. 0xfff7b000 0x00000452
9422 00:56:13.342361 TIME STAMP 5. 0xfff7a000 0x00000910
9423 00:56:13.345445 VBOOT WORK 6. 0xfff66000 0x00014000
9424 00:56:13.348804 RAMOOPS 7. 0xffe66000 0x00100000
9425 00:56:13.351943 COREBOOT 8. 0xffe64000 0x00002000
9426 00:56:13.355410 IMD small region:
9427 00:56:13.359156 IMD ROOT 0. 0xffffec00 0x00000400
9428 00:56:13.361759 VPD 1. 0xffffeb80 0x0000006c
9429 00:56:13.365712 MMC STATUS 2. 0xffffeb60 0x00000004
9430 00:56:13.371825 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9431 00:56:13.372241 Probing TPM: done!
9432 00:56:13.378592 Connected to device vid:did:rid of 1ae0:0028:00
9433 00:56:13.385609 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9434 00:56:13.388731 Initialized TPM device CR50 revision 0
9435 00:56:13.391894 Checking cr50 for pending updates
9436 00:56:13.397257 Reading cr50 TPM mode
9437 00:56:13.406037 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 00:56:13.412316 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 00:56:13.452411 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9440 00:56:13.456068 Checking segment from ROM address 0x40100000
9441 00:56:13.459506 Checking segment from ROM address 0x4010001c
9442 00:56:13.465655 Loading segment from ROM address 0x40100000
9443 00:56:13.466069 code (compression=0)
9444 00:56:13.476075 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 00:56:13.482387 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 00:56:13.482804 it's not compressed!
9447 00:56:13.489418 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 00:56:13.495669 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 00:56:13.513040 Loading segment from ROM address 0x4010001c
9450 00:56:13.513458 Entry Point 0x80000000
9451 00:56:13.516271 Loaded segments
9452 00:56:13.519750 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 00:56:13.526172 Jumping to boot code at 0x80000000(0xffe64000)
9454 00:56:13.532921 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 00:56:13.539302 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 00:56:13.547674 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9457 00:56:13.550583 Checking segment from ROM address 0x40100000
9458 00:56:13.554406 Checking segment from ROM address 0x4010001c
9459 00:56:13.560576 Loading segment from ROM address 0x40100000
9460 00:56:13.561009 code (compression=1)
9461 00:56:13.567492 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 00:56:13.577556 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 00:56:13.578014 using LZMA
9464 00:56:13.585862 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 00:56:13.592522 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 00:56:13.595602 Loading segment from ROM address 0x4010001c
9467 00:56:13.596048 Entry Point 0x54601000
9468 00:56:13.598952 Loaded segments
9469 00:56:13.602532 NOTICE: MT8192 bl31_setup
9470 00:56:13.609399 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 00:56:13.613499 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 00:56:13.616115 WARNING: region 0:
9473 00:56:13.619752 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 00:56:13.620174 WARNING: region 1:
9475 00:56:13.626170 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 00:56:13.629480 WARNING: region 2:
9477 00:56:13.633089 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 00:56:13.636118 WARNING: region 3:
9479 00:56:13.639053 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 00:56:13.642896 WARNING: region 4:
9481 00:56:13.649128 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 00:56:13.649544 WARNING: region 5:
9483 00:56:13.652502 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 00:56:13.655849 WARNING: region 6:
9485 00:56:13.659319 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 00:56:13.662226 WARNING: region 7:
9487 00:56:13.665847 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 00:56:13.672819 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 00:56:13.676089 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 00:56:13.679129 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 00:56:13.685821 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 00:56:13.689234 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 00:56:13.692928 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 00:56:13.699463 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 00:56:13.702416 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 00:56:13.709257 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 00:56:13.712485 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 00:56:13.716166 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 00:56:13.722779 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 00:56:13.725819 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 00:56:13.732558 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 00:56:13.735415 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 00:56:13.739060 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 00:56:13.745911 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 00:56:13.748539 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 00:56:13.752049 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 00:56:13.758493 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 00:56:13.761846 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 00:56:13.768830 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 00:56:13.771803 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 00:56:13.775260 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 00:56:13.782091 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 00:56:13.785755 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 00:56:13.792031 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 00:56:13.795506 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 00:56:13.798689 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 00:56:13.805082 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 00:56:13.808438 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 00:56:13.815339 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 00:56:13.818250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 00:56:13.822122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 00:56:13.825182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 00:56:13.831925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 00:56:13.834901 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 00:56:13.838317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 00:56:13.841903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 00:56:13.848597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 00:56:13.851922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 00:56:13.855408 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 00:56:13.858200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 00:56:13.864844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 00:56:13.868410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 00:56:13.871905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 00:56:13.874791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 00:56:13.881792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 00:56:13.884808 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 00:56:13.891524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 00:56:13.895160 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 00:56:13.898110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 00:56:13.904944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 00:56:13.907820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 00:56:13.915081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 00:56:13.918606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 00:56:13.925506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 00:56:13.927933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 00:56:13.931134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 00:56:13.938084 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 00:56:13.941201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 00:56:13.947939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 00:56:13.950998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 00:56:13.957923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 00:56:13.960887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 00:56:13.967960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 00:56:13.970989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 00:56:13.974138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 00:56:13.981028 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 00:56:13.984795 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 00:56:13.991310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 00:56:13.994513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 00:56:14.000937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 00:56:14.004232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 00:56:14.007392 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 00:56:14.014156 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 00:56:14.017544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 00:56:14.024326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 00:56:14.027870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 00:56:14.033853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 00:56:14.037175 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 00:56:14.043925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 00:56:14.047672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 00:56:14.050656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 00:56:14.057457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 00:56:14.060458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 00:56:14.067638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 00:56:14.070472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 00:56:14.077554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 00:56:14.081310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 00:56:14.084412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 00:56:14.090568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 00:56:14.094051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 00:56:14.100684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 00:56:14.103864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 00:56:14.110547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 00:56:14.113995 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 00:56:14.116855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 00:56:14.120216 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 00:56:14.126995 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 00:56:14.130472 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 00:56:14.133520 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 00:56:14.140577 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 00:56:14.143328 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 00:56:14.150206 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 00:56:14.153519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 00:56:14.157021 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 00:56:14.163660 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 00:56:14.166655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 00:56:14.173380 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 00:56:14.176440 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 00:56:14.180125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 00:56:14.186684 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 00:56:14.189969 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 00:56:14.196893 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 00:56:14.199909 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 00:56:14.203356 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 00:56:14.209925 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 00:56:14.213152 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 00:56:14.216391 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 00:56:14.219721 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 00:56:14.226555 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 00:56:14.229844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 00:56:14.233309 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 00:56:14.239528 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 00:56:14.242991 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 00:56:14.246595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 00:56:14.253362 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 00:56:14.256261 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 00:56:14.263102 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 00:56:14.266562 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 00:56:14.269602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 00:56:14.276387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 00:56:14.279951 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 00:56:14.286378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 00:56:14.289258 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 00:56:14.292853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 00:56:14.299389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 00:56:14.302828 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 00:56:14.306260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 00:56:14.312635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 00:56:14.315929 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 00:56:14.322595 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 00:56:14.325985 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 00:56:14.329378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 00:56:14.336048 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 00:56:14.339694 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 00:56:14.346241 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 00:56:14.349061 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 00:56:14.352584 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 00:56:14.358908 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 00:56:14.362318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 00:56:14.369080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 00:56:14.372528 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 00:56:14.375847 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 00:56:14.382587 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 00:56:14.385346 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 00:56:14.392293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 00:56:14.395672 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 00:56:14.399082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 00:56:14.405308 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 00:56:14.408870 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 00:56:14.415594 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 00:56:14.419208 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 00:56:14.422408 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 00:56:14.428917 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 00:56:14.432114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 00:56:14.438549 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 00:56:14.441818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 00:56:14.444871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 00:56:14.451341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 00:56:14.455166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 00:56:14.461464 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 00:56:14.464468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 00:56:14.467900 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 00:56:14.474867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 00:56:14.477805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 00:56:14.484687 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 00:56:14.487767 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 00:56:14.491075 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 00:56:14.498088 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 00:56:14.501129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 00:56:14.507433 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 00:56:14.510861 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 00:56:14.514368 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 00:56:14.520556 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 00:56:14.524061 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 00:56:14.530307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 00:56:14.534207 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 00:56:14.540649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 00:56:14.543697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 00:56:14.546767 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 00:56:14.553833 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 00:56:14.556728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 00:56:14.563279 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 00:56:14.567055 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 00:56:14.573432 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 00:56:14.576293 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 00:56:14.579920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 00:56:14.586666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 00:56:14.589646 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 00:56:14.596758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 00:56:14.599494 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 00:56:14.606550 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 00:56:14.609258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 00:56:14.612722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 00:56:14.619681 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 00:56:14.622547 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 00:56:14.629189 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 00:56:14.632595 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 00:56:14.638905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 00:56:14.642363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 00:56:14.645626 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 00:56:14.652297 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 00:56:14.655526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 00:56:14.662010 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 00:56:14.665486 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 00:56:14.671870 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 00:56:14.675468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 00:56:14.678754 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 00:56:14.684849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 00:56:14.688340 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 00:56:14.695241 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 00:56:14.698019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 00:56:14.704909 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 00:56:14.708561 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 00:56:14.711544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 00:56:14.717813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 00:56:14.721525 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 00:56:14.724880 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 00:56:14.730938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 00:56:14.734408 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 00:56:14.737634 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 00:56:14.740786 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 00:56:14.747857 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 00:56:14.750792 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 00:56:14.757172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 00:56:14.760576 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 00:56:14.763935 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 00:56:14.770534 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 00:56:14.773964 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 00:56:14.780590 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 00:56:14.783982 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 00:56:14.786725 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 00:56:14.793346 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 00:56:14.796778 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 00:56:14.800316 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 00:56:14.807256 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 00:56:14.809830 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 00:56:14.813165 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 00:56:14.819865 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 00:56:14.822743 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 00:56:14.829627 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 00:56:14.833214 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 00:56:14.836343 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 00:56:14.842650 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 00:56:14.846001 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 00:56:14.852541 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 00:56:14.855845 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 00:56:14.858970 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 00:56:14.865873 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 00:56:14.868927 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 00:56:14.875850 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 00:56:14.879090 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 00:56:14.882024 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 00:56:14.888658 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 00:56:14.891979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 00:56:14.895443 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 00:56:14.901994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 00:56:14.905059 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 00:56:14.908522 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 00:56:14.912226 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 00:56:14.918350 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 00:56:14.921781 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 00:56:14.925351 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 00:56:14.928518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 00:56:14.935044 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 00:56:14.938860 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 00:56:14.941590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 00:56:14.944543 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 00:56:14.951711 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 00:56:14.954749 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 00:56:14.958369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 00:56:14.964629 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 00:56:14.967560 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 00:56:14.974601 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 00:56:14.977515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 00:56:14.984113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 00:56:14.987946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 00:56:14.990879 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 00:56:14.997349 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 00:56:15.000789 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 00:56:15.007346 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 00:56:15.010707 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 00:56:15.017342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 00:56:15.020285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 00:56:15.023922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 00:56:15.030553 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 00:56:15.033752 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 00:56:15.040349 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 00:56:15.043547 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 00:56:15.047061 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 00:56:15.053900 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 00:56:15.056843 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 00:56:15.063242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 00:56:15.066493 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 00:56:15.073505 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 00:56:15.076498 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 00:56:15.079892 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 00:56:15.086300 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 00:56:15.089770 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 00:56:15.096384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 00:56:15.099331 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 00:56:15.102946 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 00:56:15.109163 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 00:56:15.112542 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 00:56:15.119588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 00:56:15.122559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 00:56:15.129277 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 00:56:15.132297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 00:56:15.139208 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 00:56:15.142297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 00:56:15.145729 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 00:56:15.152048 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 00:56:15.155477 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 00:56:15.161972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 00:56:15.165556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 00:56:15.168624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 00:56:15.175216 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 00:56:15.178512 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 00:56:15.185127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 00:56:15.188584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 00:56:15.191455 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 00:56:15.198116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 00:56:15.201461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 00:56:15.208586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 00:56:15.211667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 00:56:15.215110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 00:56:15.221476 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 00:56:15.225126 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 00:56:15.231631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 00:56:15.234359 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 00:56:15.241048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 00:56:15.244592 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 00:56:15.251283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 00:56:15.254798 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 00:56:15.257955 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 00:56:15.264340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 00:56:15.267742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 00:56:15.273959 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 00:56:15.277169 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 00:56:15.280731 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 00:56:15.287244 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 00:56:15.290584 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 00:56:15.297004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 00:56:15.300571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 00:56:15.306983 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 00:56:15.310552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 00:56:15.316723 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 00:56:15.320103 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 00:56:15.323483 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 00:56:15.329879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 00:56:15.332981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 00:56:15.339784 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 00:56:15.343339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 00:56:15.349962 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 00:56:15.353007 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 00:56:15.359670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 00:56:15.362926 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 00:56:15.366304 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 00:56:15.372630 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 00:56:15.375983 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 00:56:15.382787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 00:56:15.386312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 00:56:15.392435 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 00:56:15.396000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 00:56:15.402133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 00:56:15.405542 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 00:56:15.409166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 00:56:15.415644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 00:56:15.418800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 00:56:15.425579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 00:56:15.428504 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 00:56:15.434992 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 00:56:15.438437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 00:56:15.442261 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 00:56:15.448635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 00:56:15.451970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 00:56:15.458320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 00:56:15.461860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 00:56:15.468088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 00:56:15.471385 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 00:56:15.478287 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 00:56:15.481382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 00:56:15.488163 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 00:56:15.491414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 00:56:15.494885 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 00:56:15.501934 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 00:56:15.504774 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 00:56:15.511663 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 00:56:15.514613 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 00:56:15.521152 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 00:56:15.524558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 00:56:15.527515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 00:56:15.534191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 00:56:15.537787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 00:56:15.544231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 00:56:15.547734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 00:56:15.554218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 00:56:15.557727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 00:56:15.563902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 00:56:15.566952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 00:56:15.574185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 00:56:15.577072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 00:56:15.583474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 00:56:15.586849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 00:56:15.593570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 00:56:15.596915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 00:56:15.603439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 00:56:15.606682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 00:56:15.613791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 00:56:15.616438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 00:56:15.623309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 00:56:15.626623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 00:56:15.632987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 00:56:15.636279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 00:56:15.642856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 00:56:15.646133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 00:56:15.652890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 00:56:15.656340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 00:56:15.662935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 00:56:15.666045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 00:56:15.672998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 00:56:15.676158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 00:56:15.682598 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 00:56:15.683016 INFO: [APUAPC] vio 0
9924 00:56:15.689266 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 00:56:15.692767 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 00:56:15.695730 INFO: [APUAPC] D0_APC_0: 0x400510
9927 00:56:15.699141 INFO: [APUAPC] D0_APC_1: 0x0
9928 00:56:15.702488 INFO: [APUAPC] D0_APC_2: 0x1540
9929 00:56:15.705905 INFO: [APUAPC] D0_APC_3: 0x0
9930 00:56:15.708946 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 00:56:15.712755 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 00:56:15.716167 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 00:56:15.719189 INFO: [APUAPC] D1_APC_3: 0x0
9934 00:56:15.722121 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 00:56:15.725657 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 00:56:15.729203 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 00:56:15.731931 INFO: [APUAPC] D2_APC_3: 0x0
9938 00:56:15.735198 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 00:56:15.738493 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 00:56:15.741969 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 00:56:15.745740 INFO: [APUAPC] D3_APC_3: 0x0
9942 00:56:15.748487 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 00:56:15.751918 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 00:56:15.755101 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 00:56:15.758564 INFO: [APUAPC] D4_APC_3: 0x0
9946 00:56:15.761940 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 00:56:15.764859 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 00:56:15.768630 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 00:56:15.771805 INFO: [APUAPC] D5_APC_3: 0x0
9950 00:56:15.774677 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 00:56:15.778697 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 00:56:15.781507 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 00:56:15.784923 INFO: [APUAPC] D6_APC_3: 0x0
9954 00:56:15.787865 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 00:56:15.791464 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 00:56:15.794464 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 00:56:15.794880 INFO: [APUAPC] D7_APC_3: 0x0
9958 00:56:15.801063 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 00:56:15.804416 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 00:56:15.807785 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 00:56:15.808197 INFO: [APUAPC] D8_APC_3: 0x0
9962 00:56:15.810891 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 00:56:15.817874 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 00:56:15.820933 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 00:56:15.821358 INFO: [APUAPC] D9_APC_3: 0x0
9966 00:56:15.824249 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 00:56:15.831197 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 00:56:15.834037 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 00:56:15.834458 INFO: [APUAPC] D10_APC_3: 0x0
9970 00:56:15.837513 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 00:56:15.844226 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 00:56:15.847236 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 00:56:15.847677 INFO: [APUAPC] D11_APC_3: 0x0
9974 00:56:15.854324 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 00:56:15.857293 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 00:56:15.860415 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 00:56:15.863768 INFO: [APUAPC] D12_APC_3: 0x0
9978 00:56:15.867030 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 00:56:15.870382 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 00:56:15.873532 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 00:56:15.877252 INFO: [APUAPC] D13_APC_3: 0x0
9982 00:56:15.880214 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 00:56:15.883383 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 00:56:15.887118 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 00:56:15.890573 INFO: [APUAPC] D14_APC_3: 0x0
9986 00:56:15.893533 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 00:56:15.896542 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 00:56:15.900092 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 00:56:15.903357 INFO: [APUAPC] D15_APC_3: 0x0
9990 00:56:15.906694 INFO: [APUAPC] APC_CON: 0x4
9991 00:56:15.907116 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 00:56:15.910127 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 00:56:15.913460 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 00:56:15.916604 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 00:56:15.919825 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 00:56:15.923341 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 00:56:15.926224 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 00:56:15.929716 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 00:56:15.933056 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 00:56:15.935953 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 00:56:15.939430 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 00:56:15.942885 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 00:56:15.943300 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 00:56:15.945759 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 00:56:15.949176 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 00:56:15.952888 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 00:56:15.956074 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 00:56:15.958942 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 00:56:15.962507 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 00:56:15.965917 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 00:56:15.969455 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 00:56:15.972199 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 00:56:15.975814 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 00:56:15.979341 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 00:56:15.982352 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 00:56:15.985649 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 00:56:15.986075 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 00:56:15.989011 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 00:56:15.991959 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 00:56:15.995316 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 00:56:15.998532 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 00:56:16.001900 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 00:56:16.005070 INFO: [NOCDAPC] APC_CON: 0x4
10024 00:56:16.008660 INFO: [APUAPC] set_apusys_apc done
10025 00:56:16.012227 INFO: [DEVAPC] devapc_init done
10026 00:56:16.015072 INFO: GICv3 without legacy support detected.
10027 00:56:16.018388 INFO: ARM GICv3 driver initialized in EL3
10028 00:56:16.025164 INFO: Maximum SPI INTID supported: 639
10029 00:56:16.028404 INFO: BL31: Initializing runtime services
10030 00:56:16.034814 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 00:56:16.035232 INFO: SPM: enable CPC mode
10032 00:56:16.041527 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 00:56:16.045062 INFO: BL31: Preparing for EL3 exit to normal world
10034 00:56:16.051674 INFO: Entry point address = 0x80000000
10035 00:56:16.052216 INFO: SPSR = 0x8
10036 00:56:16.057486
10037 00:56:16.057899
10038 00:56:16.058229
10039 00:56:16.060936 Starting depthcharge on Spherion...
10040 00:56:16.061360
10041 00:56:16.061692 Wipe memory regions:
10042 00:56:16.062005
10043 00:56:16.064419 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10044 00:56:16.064913 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 00:56:16.066390 Setting prompt string to ['asurada:']
10046 00:56:16.066799 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 00:56:16.067523 [0x00000040000000, 0x00000054600000)
10048 00:56:16.186614
10049 00:56:16.187117 [0x00000054660000, 0x00000080000000)
10050 00:56:16.446745
10051 00:56:16.447246 [0x000000821a7280, 0x000000ffe64000)
10052 00:56:17.191320
10053 00:56:17.191878 [0x00000100000000, 0x00000240000000)
10054 00:56:19.081137
10055 00:56:19.084612 Initializing XHCI USB controller at 0x11200000.
10056 00:56:20.121851
10057 00:56:20.125551 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 00:56:20.125638
10059 00:56:20.125704
10060 00:56:20.125767
10061 00:56:20.126046 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 00:56:20.226336 asurada: tftpboot 192.168.201.1 12571137/tftp-deploy-13ghr7el/kernel/image.itb 12571137/tftp-deploy-13ghr7el/kernel/cmdline
10064 00:56:20.226465 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 00:56:20.226553 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 00:56:20.230675 tftpboot 192.168.201.1 12571137/tftp-deploy-13ghr7el/kernel/image.ittp-deploy-13ghr7el/kernel/cmdline
10067 00:56:20.230759
10068 00:56:20.230824 Waiting for link
10069 00:56:20.391301
10070 00:56:20.391466 R8152: Initializing
10071 00:56:20.391535
10072 00:56:20.394259 Version 6 (ocp_data = 5c30)
10073 00:56:20.394342
10074 00:56:20.397667 R8152: Done initializing
10075 00:56:20.397748
10076 00:56:20.397813 Adding net device
10077 00:56:22.441823
10078 00:56:22.441956 done.
10079 00:56:22.442025
10080 00:56:22.442115 MAC: 00:24:32:30:7c:7b
10081 00:56:22.442179
10082 00:56:22.445551 Sending DHCP discover... done.
10083 00:56:22.445626
10084 00:56:27.735800 Waiting for reply... done.
10085 00:56:27.735963
10086 00:56:27.736060 Sending DHCP request... done.
10087 00:56:27.739139
10088 00:56:27.739220 Waiting for reply... done.
10089 00:56:27.739287
10090 00:56:27.742256 My ip is 192.168.201.14
10091 00:56:27.742338
10092 00:56:27.745663 The DHCP server ip is 192.168.201.1
10093 00:56:27.745745
10094 00:56:27.748619 TFTP server IP predefined by user: 192.168.201.1
10095 00:56:27.748739
10096 00:56:27.755497 Bootfile predefined by user: 12571137/tftp-deploy-13ghr7el/kernel/image.itb
10097 00:56:27.755580
10098 00:56:27.759235 Sending tftp read request... done.
10099 00:56:27.759318
10100 00:56:27.761942 Waiting for the transfer...
10101 00:56:27.762025
10102 00:56:28.309341 00000000 ################################################################
10103 00:56:28.309510
10104 00:56:28.875984 00080000 ################################################################
10105 00:56:28.876155
10106 00:56:29.424859 00100000 ################################################################
10107 00:56:29.425016
10108 00:56:29.958274 00180000 ################################################################
10109 00:56:29.958407
10110 00:56:30.490868 00200000 ################################################################
10111 00:56:30.491001
10112 00:56:31.037572 00280000 ################################################################
10113 00:56:31.037707
10114 00:56:31.578891 00300000 ################################################################
10115 00:56:31.579058
10116 00:56:32.104880 00380000 ################################################################
10117 00:56:32.105030
10118 00:56:32.634469 00400000 ################################################################
10119 00:56:32.634618
10120 00:56:33.168815 00480000 ################################################################
10121 00:56:33.168959
10122 00:56:33.716895 00500000 ################################################################
10123 00:56:33.717061
10124 00:56:34.265926 00580000 ################################################################
10125 00:56:34.266067
10126 00:56:34.821511 00600000 ################################################################
10127 00:56:34.821641
10128 00:56:35.381755 00680000 ################################################################
10129 00:56:35.381891
10130 00:56:35.970117 00700000 ################################################################
10131 00:56:35.970269
10132 00:56:36.569189 00780000 ################################################################
10133 00:56:36.569330
10134 00:56:37.148423 00800000 ################################################################
10135 00:56:37.148558
10136 00:56:37.698897 00880000 ################################################################
10137 00:56:37.699034
10138 00:56:38.241961 00900000 ################################################################
10139 00:56:38.242091
10140 00:56:38.796454 00980000 ################################################################
10141 00:56:38.796587
10142 00:56:39.360545 00a00000 ################################################################
10143 00:56:39.360675
10144 00:56:39.939600 00a80000 ################################################################
10145 00:56:39.939732
10146 00:56:40.516820 00b00000 ################################################################
10147 00:56:40.516956
10148 00:56:41.062372 00b80000 ################################################################
10149 00:56:41.062507
10150 00:56:41.623182 00c00000 ################################################################
10151 00:56:41.623342
10152 00:56:42.201694 00c80000 ################################################################
10153 00:56:42.201834
10154 00:56:42.786247 00d00000 ################################################################
10155 00:56:42.786385
10156 00:56:43.344662 00d80000 ################################################################
10157 00:56:43.344798
10158 00:56:43.898616 00e00000 ################################################################
10159 00:56:43.898751
10160 00:56:44.457281 00e80000 ################################################################
10161 00:56:44.457409
10162 00:56:44.994193 00f00000 ################################################################
10163 00:56:44.994365
10164 00:56:45.549031 00f80000 ################################################################
10165 00:56:45.549347
10166 00:56:46.221046 01000000 ################################################################
10167 00:56:46.221551
10168 00:56:46.857305 01080000 ################################################################
10169 00:56:46.857454
10170 00:56:47.486276 01100000 ################################################################
10171 00:56:47.486406
10172 00:56:48.132098 01180000 ################################################################
10173 00:56:48.132235
10174 00:56:48.789941 01200000 ################################################################
10175 00:56:48.790432
10176 00:56:49.449560 01280000 ################################################################
10177 00:56:49.450052
10178 00:56:50.048597 01300000 ################################################################
10179 00:56:50.048734
10180 00:56:50.631343 01380000 ################################################################
10181 00:56:50.631515
10182 00:56:51.280180 01400000 ################################################################
10183 00:56:51.280737
10184 00:56:51.954947 01480000 ################################################################
10185 00:56:51.955485
10186 00:56:52.507358 01500000 ################################################################
10187 00:56:52.507541
10188 00:56:53.172112 01580000 ################################################################
10189 00:56:53.172605
10190 00:56:53.847795 01600000 ################################################################
10191 00:56:53.848283
10192 00:56:54.522969 01680000 ################################################################
10193 00:56:54.523497
10194 00:56:55.222824 01700000 ################################################################
10195 00:56:55.223334
10196 00:56:55.916817 01780000 ################################################################
10197 00:56:55.917333
10198 00:56:56.584103 01800000 ################################################################
10199 00:56:56.584615
10200 00:56:57.270446 01880000 ################################################################
10201 00:56:57.270780
10202 00:56:57.891075 01900000 ################################################################
10203 00:56:57.891224
10204 00:56:58.422364 01980000 ################################################################
10205 00:56:58.422513
10206 00:56:59.007357 01a00000 ################################################################
10207 00:56:59.007756
10208 00:56:59.604185 01a80000 ################################################################
10209 00:56:59.604335
10210 00:57:00.208893 01b00000 ################################################################
10211 00:57:00.209040
10212 00:57:00.835832 01b80000 ################################################################
10213 00:57:00.835966
10214 00:57:01.461358 01c00000 ################################################################
10215 00:57:01.462042
10216 00:57:01.472190 01c80000 ## done.
10217 00:57:01.472770
10218 00:57:01.475133 The bootfile was 29893106 bytes long.
10219 00:57:01.475722
10220 00:57:01.478209 Sending tftp read request... done.
10221 00:57:01.478788
10222 00:57:01.482784 Waiting for the transfer...
10223 00:57:01.483482
10224 00:57:01.483974 00000000 # done.
10225 00:57:01.484495
10226 00:57:01.489676 Command line loaded dynamically from TFTP file: 12571137/tftp-deploy-13ghr7el/kernel/cmdline
10227 00:57:01.490344
10228 00:57:01.512613 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10229 00:57:01.512931
10230 00:57:01.513172 Loading FIT.
10231 00:57:01.515737
10232 00:57:01.516036 Image ramdisk-1 has 17795171 bytes.
10233 00:57:01.516276
10234 00:57:01.518618 Image fdt-1 has 47278 bytes.
10235 00:57:01.518919
10236 00:57:01.522303 Image kernel-1 has 12048624 bytes.
10237 00:57:01.522615
10238 00:57:01.532329 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10239 00:57:01.532633
10240 00:57:01.548483 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10241 00:57:01.548930
10242 00:57:01.555222 Choosing best match conf-1 for compat google,spherion-rev2.
10243 00:57:01.559219
10244 00:57:01.563229 Connected to device vid:did:rid of 1ae0:0028:00
10245 00:57:01.571448
10246 00:57:01.573526 tpm_get_response: command 0x17b, return code 0x0
10247 00:57:01.573950
10248 00:57:01.580191 ec_init: CrosEC protocol v3 supported (256, 248)
10249 00:57:01.580746
10250 00:57:01.583476 tpm_cleanup: add release locality here.
10251 00:57:01.583890
10252 00:57:01.586686 Shutting down all USB controllers.
10253 00:57:01.587065
10254 00:57:01.590166 Removing current net device
10255 00:57:01.590672
10256 00:57:01.597124 Exiting depthcharge with code 4 at timestamp: 74780218
10257 00:57:01.597701
10258 00:57:01.600367 LZMA decompressing kernel-1 to 0x821a6718
10259 00:57:01.600932
10260 00:57:01.603440 LZMA decompressing kernel-1 to 0x40000000
10261 00:57:03.101395
10262 00:57:03.102016 jumping to kernel
10263 00:57:03.105173 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10264 00:57:03.105830 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10265 00:57:03.106369 Setting prompt string to ['Linux version [0-9]']
10266 00:57:03.106886 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10267 00:57:03.107444 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10268 00:57:03.183080
10269 00:57:03.186180 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10270 00:57:03.189926 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10271 00:57:03.190608 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10272 00:57:03.191233 Setting prompt string to []
10273 00:57:03.191932 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10274 00:57:03.192589 Using line separator: #'\n'#
10275 00:57:03.193162 No login prompt set.
10276 00:57:03.193748 Parsing kernel messages
10277 00:57:03.194303 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10278 00:57:03.195410 [login-action] Waiting for messages, (timeout 00:03:38)
10279 00:57:03.208783 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10280 00:57:03.211814 [ 0.000000] random: crng init done
10281 00:57:03.218852 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10282 00:57:03.221813 [ 0.000000] efi: UEFI not found.
10283 00:57:03.228489 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10284 00:57:03.238180 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10285 00:57:03.248265 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10286 00:57:03.254974 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10287 00:57:03.261066 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10288 00:57:03.268176 [ 0.000000] printk: bootconsole [mtk8250] enabled
10289 00:57:03.274600 [ 0.000000] NUMA: No NUMA configuration found
10290 00:57:03.281346 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10291 00:57:03.287576 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10292 00:57:03.287811 [ 0.000000] Zone ranges:
10293 00:57:03.294079 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10294 00:57:03.297443 [ 0.000000] DMA32 empty
10295 00:57:03.304555 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10296 00:57:03.308076 [ 0.000000] Movable zone start for each node
10297 00:57:03.311430 [ 0.000000] Early memory node ranges
10298 00:57:03.317716 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10299 00:57:03.324110 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10300 00:57:03.330804 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10301 00:57:03.337491 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10302 00:57:03.343950 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10303 00:57:03.350112 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10304 00:57:03.407510 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10305 00:57:03.413821 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10306 00:57:03.420232 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10307 00:57:03.423469 [ 0.000000] psci: probing for conduit method from DT.
10308 00:57:03.430896 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10309 00:57:03.433826 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10310 00:57:03.440020 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10311 00:57:03.443130 [ 0.000000] psci: SMC Calling Convention v1.2
10312 00:57:03.450379 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10313 00:57:03.453419 [ 0.000000] Detected VIPT I-cache on CPU0
10314 00:57:03.460085 [ 0.000000] CPU features: detected: GIC system register CPU interface
10315 00:57:03.466802 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10316 00:57:03.473439 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10317 00:57:03.479734 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10318 00:57:03.489572 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10319 00:57:03.496376 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10320 00:57:03.499299 [ 0.000000] alternatives: applying boot alternatives
10321 00:57:03.505993 [ 0.000000] Fallback order for Node 0: 0
10322 00:57:03.512973 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10323 00:57:03.516311 [ 0.000000] Policy zone: Normal
10324 00:57:03.539048 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10325 00:57:03.548784 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10326 00:57:03.559855 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10327 00:57:03.569939 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10328 00:57:03.576417 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10329 00:57:03.579608 <6>[ 0.000000] software IO TLB: area num 8.
10330 00:57:03.636704 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10331 00:57:03.785659 <6>[ 0.000000] Memory: 7949880K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402888K reserved, 32768K cma-reserved)
10332 00:57:03.792574 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10333 00:57:03.798794 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10334 00:57:03.801879 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10335 00:57:03.809008 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10336 00:57:03.815491 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10337 00:57:03.819734 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10338 00:57:03.828669 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10339 00:57:03.835470 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10340 00:57:03.842058 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10341 00:57:03.848118 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10342 00:57:03.851825 <6>[ 0.000000] GICv3: 608 SPIs implemented
10343 00:57:03.854601 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10344 00:57:03.861220 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10345 00:57:03.864741 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10346 00:57:03.871573 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10347 00:57:03.884456 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10348 00:57:03.897936 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10349 00:57:03.904693 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10350 00:57:03.912722 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10351 00:57:03.925752 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10352 00:57:03.931927 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10353 00:57:03.938508 <6>[ 0.009184] Console: colour dummy device 80x25
10354 00:57:03.948911 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10355 00:57:03.955218 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10356 00:57:03.958259 <6>[ 0.029223] LSM: Security Framework initializing
10357 00:57:03.964956 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10358 00:57:03.974701 <6>[ 0.041976] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10359 00:57:03.984701 <6>[ 0.051447] cblist_init_generic: Setting adjustable number of callback queues.
10360 00:57:03.987659 <6>[ 0.058888] cblist_init_generic: Setting shift to 3 and lim to 1.
10361 00:57:03.997676 <6>[ 0.065267] cblist_init_generic: Setting adjustable number of callback queues.
10362 00:57:04.004978 <6>[ 0.072693] cblist_init_generic: Setting shift to 3 and lim to 1.
10363 00:57:04.007468 <6>[ 0.079134] rcu: Hierarchical SRCU implementation.
10364 00:57:04.013990 <6>[ 0.084150] rcu: Max phase no-delay instances is 1000.
10365 00:57:04.020912 <6>[ 0.091209] EFI services will not be available.
10366 00:57:04.024515 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10367 00:57:04.032978 <6>[ 0.101226] Detected VIPT I-cache on CPU1
10368 00:57:04.040050 <6>[ 0.101294] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10369 00:57:04.046306 <6>[ 0.101325] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10370 00:57:04.049648 <6>[ 0.101663] Detected VIPT I-cache on CPU2
10371 00:57:04.059786 <6>[ 0.101717] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10372 00:57:04.066112 <6>[ 0.101735] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10373 00:57:04.069490 <6>[ 0.101996] Detected VIPT I-cache on CPU3
10374 00:57:04.075891 <6>[ 0.102043] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10375 00:57:04.082535 <6>[ 0.102056] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10376 00:57:04.089201 <6>[ 0.102344] CPU features: detected: Spectre-v4
10377 00:57:04.092743 <6>[ 0.102349] CPU features: detected: Spectre-BHB
10378 00:57:04.095666 <6>[ 0.102354] Detected PIPT I-cache on CPU4
10379 00:57:04.102655 <6>[ 0.102404] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10380 00:57:04.111803 <6>[ 0.102419] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10381 00:57:04.115264 <6>[ 0.102705] Detected PIPT I-cache on CPU5
10382 00:57:04.121823 <6>[ 0.102767] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10383 00:57:04.128861 <6>[ 0.102785] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10384 00:57:04.132143 <6>[ 0.103069] Detected PIPT I-cache on CPU6
10385 00:57:04.141738 <6>[ 0.103132] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10386 00:57:04.148310 <6>[ 0.103148] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10387 00:57:04.151505 <6>[ 0.103443] Detected PIPT I-cache on CPU7
10388 00:57:04.158204 <6>[ 0.103509] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10389 00:57:04.164666 <6>[ 0.103525] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10390 00:57:04.167937 <6>[ 0.103573] smp: Brought up 1 node, 8 CPUs
10391 00:57:04.174472 <6>[ 0.244962] SMP: Total of 8 processors activated.
10392 00:57:04.180849 <6>[ 0.249882] CPU features: detected: 32-bit EL0 Support
10393 00:57:04.187826 <6>[ 0.255278] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10394 00:57:04.194286 <6>[ 0.264078] CPU features: detected: Common not Private translations
10395 00:57:04.201278 <6>[ 0.270594] CPU features: detected: CRC32 instructions
10396 00:57:04.207864 <6>[ 0.275945] CPU features: detected: RCpc load-acquire (LDAPR)
10397 00:57:04.210592 <6>[ 0.281942] CPU features: detected: LSE atomic instructions
10398 00:57:04.217461 <6>[ 0.287724] CPU features: detected: Privileged Access Never
10399 00:57:04.223892 <6>[ 0.293503] CPU features: detected: RAS Extension Support
10400 00:57:04.230668 <6>[ 0.299112] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10401 00:57:04.233802 <6>[ 0.306330] CPU: All CPU(s) started at EL2
10402 00:57:04.240268 <6>[ 0.310646] alternatives: applying system-wide alternatives
10403 00:57:04.251143 <6>[ 0.321367] devtmpfs: initialized
10404 00:57:04.266804 <6>[ 0.330326] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10405 00:57:04.273012 <6>[ 0.340286] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10406 00:57:04.279931 <6>[ 0.348498] pinctrl core: initialized pinctrl subsystem
10407 00:57:04.283195 <6>[ 0.355141] DMI not present or invalid.
10408 00:57:04.289721 <6>[ 0.359554] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10409 00:57:04.299512 <6>[ 0.366433] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10410 00:57:04.306251 <6>[ 0.374016] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10411 00:57:04.315892 <6>[ 0.382245] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10412 00:57:04.322238 <6>[ 0.390488] audit: initializing netlink subsys (disabled)
10413 00:57:04.329044 <5>[ 0.396183] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10414 00:57:04.335748 <6>[ 0.396880] thermal_sys: Registered thermal governor 'step_wise'
10415 00:57:04.342363 <6>[ 0.404151] thermal_sys: Registered thermal governor 'power_allocator'
10416 00:57:04.345322 <6>[ 0.410406] cpuidle: using governor menu
10417 00:57:04.352022 <6>[ 0.421364] NET: Registered PF_QIPCRTR protocol family
10418 00:57:04.358433 <6>[ 0.426849] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10419 00:57:04.365207 <6>[ 0.433954] ASID allocator initialised with 32768 entries
10420 00:57:04.368851 <6>[ 0.440513] Serial: AMBA PL011 UART driver
10421 00:57:04.378634 <4>[ 0.449291] Trying to register duplicate clock ID: 134
10422 00:57:04.434751 <6>[ 0.508533] KASLR enabled
10423 00:57:04.448913 <6>[ 0.516317] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10424 00:57:04.455842 <6>[ 0.523329] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10425 00:57:04.462959 <6>[ 0.529815] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10426 00:57:04.469268 <6>[ 0.536822] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10427 00:57:04.476078 <6>[ 0.543311] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10428 00:57:04.482457 <6>[ 0.550314] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10429 00:57:04.488946 <6>[ 0.556799] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10430 00:57:04.495457 <6>[ 0.563802] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10431 00:57:04.498673 <6>[ 0.571312] ACPI: Interpreter disabled.
10432 00:57:04.507152 <6>[ 0.577744] iommu: Default domain type: Translated
10433 00:57:04.514151 <6>[ 0.582857] iommu: DMA domain TLB invalidation policy: strict mode
10434 00:57:04.516917 <5>[ 0.589519] SCSI subsystem initialized
10435 00:57:04.524166 <6>[ 0.593689] usbcore: registered new interface driver usbfs
10436 00:57:04.530371 <6>[ 0.599422] usbcore: registered new interface driver hub
10437 00:57:04.533859 <6>[ 0.604972] usbcore: registered new device driver usb
10438 00:57:04.540459 <6>[ 0.611077] pps_core: LinuxPPS API ver. 1 registered
10439 00:57:04.550326 <6>[ 0.616271] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10440 00:57:04.553753 <6>[ 0.625619] PTP clock support registered
10441 00:57:04.556546 <6>[ 0.629862] EDAC MC: Ver: 3.0.0
10442 00:57:04.564697 <6>[ 0.635025] FPGA manager framework
10443 00:57:04.570723 <6>[ 0.638701] Advanced Linux Sound Architecture Driver Initialized.
10444 00:57:04.574280 <6>[ 0.645478] vgaarb: loaded
10445 00:57:04.580542 <6>[ 0.648632] clocksource: Switched to clocksource arch_sys_counter
10446 00:57:04.583925 <5>[ 0.655072] VFS: Disk quotas dquot_6.6.0
10447 00:57:04.590798 <6>[ 0.659258] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10448 00:57:04.593997 <6>[ 0.666450] pnp: PnP ACPI: disabled
10449 00:57:04.602828 <6>[ 0.673174] NET: Registered PF_INET protocol family
10450 00:57:04.612366 <6>[ 0.678760] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10451 00:57:04.623870 <6>[ 0.691076] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10452 00:57:04.633488 <6>[ 0.699891] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10453 00:57:04.640217 <6>[ 0.707860] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10454 00:57:04.649903 <6>[ 0.716558] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10455 00:57:04.656766 <6>[ 0.726308] TCP: Hash tables configured (established 65536 bind 65536)
10456 00:57:04.663167 <6>[ 0.733169] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10457 00:57:04.673173 <6>[ 0.740368] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10458 00:57:04.679524 <6>[ 0.748071] NET: Registered PF_UNIX/PF_LOCAL protocol family
10459 00:57:04.686238 <6>[ 0.754216] RPC: Registered named UNIX socket transport module.
10460 00:57:04.689496 <6>[ 0.760370] RPC: Registered udp transport module.
10461 00:57:04.695841 <6>[ 0.765302] RPC: Registered tcp transport module.
10462 00:57:04.702805 <6>[ 0.770234] RPC: Registered tcp NFSv4.1 backchannel transport module.
10463 00:57:04.705824 <6>[ 0.776898] PCI: CLS 0 bytes, default 64
10464 00:57:04.709347 <6>[ 0.781294] Unpacking initramfs...
10465 00:57:04.718903 <6>[ 0.785019] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10466 00:57:04.725664 <6>[ 0.793656] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10467 00:57:04.732671 <6>[ 0.802484] kvm [1]: IPA Size Limit: 40 bits
10468 00:57:04.735591 <6>[ 0.807015] kvm [1]: GICv3: no GICV resource entry
10469 00:57:04.741925 <6>[ 0.812038] kvm [1]: disabling GICv2 emulation
10470 00:57:04.745747 <6>[ 0.816724] kvm [1]: GIC system register CPU interface enabled
10471 00:57:04.752257 <6>[ 0.822884] kvm [1]: vgic interrupt IRQ18
10472 00:57:04.758743 <6>[ 0.828682] kvm [1]: VHE mode initialized successfully
10473 00:57:04.765625 <5>[ 0.835102] Initialise system trusted keyrings
10474 00:57:04.772121 <6>[ 0.839873] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10475 00:57:04.779656 <6>[ 0.850090] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10476 00:57:04.786235 <5>[ 0.856470] NFS: Registering the id_resolver key type
10477 00:57:04.789559 <5>[ 0.861778] Key type id_resolver registered
10478 00:57:04.795834 <5>[ 0.866192] Key type id_legacy registered
10479 00:57:04.802478 <6>[ 0.870468] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10480 00:57:04.809187 <6>[ 0.877389] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10481 00:57:04.815759 <6>[ 0.885112] 9p: Installing v9fs 9p2000 file system support
10482 00:57:04.852407 <5>[ 0.922836] Key type asymmetric registered
10483 00:57:04.855698 <5>[ 0.927169] Asymmetric key parser 'x509' registered
10484 00:57:04.865692 <6>[ 0.932312] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10485 00:57:04.869029 <6>[ 0.939930] io scheduler mq-deadline registered
10486 00:57:04.871926 <6>[ 0.944693] io scheduler kyber registered
10487 00:57:04.891571 <6>[ 0.961931] EINJ: ACPI disabled.
10488 00:57:04.923504 <4>[ 0.987611] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10489 00:57:04.933614 <4>[ 0.998232] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10490 00:57:04.949241 <6>[ 1.019135] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10491 00:57:04.956590 <6>[ 1.027123] printk: console [ttyS0] disabled
10492 00:57:04.984414 <6>[ 1.051787] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10493 00:57:04.991179 <6>[ 1.061264] printk: console [ttyS0] enabled
10494 00:57:04.994485 <6>[ 1.061264] printk: console [ttyS0] enabled
10495 00:57:05.000840 <6>[ 1.070158] printk: bootconsole [mtk8250] disabled
10496 00:57:05.004183 <6>[ 1.070158] printk: bootconsole [mtk8250] disabled
10497 00:57:05.011070 <6>[ 1.081422] SuperH (H)SCI(F) driver initialized
10498 00:57:05.014120 <6>[ 1.086682] msm_serial: driver initialized
10499 00:57:05.028579 <6>[ 1.095568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10500 00:57:05.038112 <6>[ 1.104114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10501 00:57:05.045060 <6>[ 1.112657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10502 00:57:05.054932 <6>[ 1.121291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10503 00:57:05.064798 <6>[ 1.129998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10504 00:57:05.071470 <6>[ 1.138712] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10505 00:57:05.081131 <6>[ 1.147253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10506 00:57:05.087724 <6>[ 1.156059] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10507 00:57:05.099747 <6>[ 1.164605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10508 00:57:05.109659 <6>[ 1.180168] loop: module loaded
10509 00:57:05.115994 <6>[ 1.186209] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10510 00:57:05.138365 <4>[ 1.208971] mtk-pmic-keys: Failed to locate of_node [id: -1]
10511 00:57:05.145579 <6>[ 1.215789] megasas: 07.719.03.00-rc1
10512 00:57:05.154578 <6>[ 1.225435] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10513 00:57:05.162026 <6>[ 1.232005] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10514 00:57:05.177540 <6>[ 1.247881] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10515 00:57:05.233353 <6>[ 1.297164] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10516 00:57:05.458416 <6>[ 1.528877] Freeing initrd memory: 17372K
10517 00:57:05.468547 <6>[ 1.539122] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10518 00:57:05.479861 <6>[ 1.549950] tun: Universal TUN/TAP device driver, 1.6
10519 00:57:05.482760 <6>[ 1.556015] thunder_xcv, ver 1.0
10520 00:57:05.486500 <6>[ 1.559519] thunder_bgx, ver 1.0
10521 00:57:05.489565 <6>[ 1.563015] nicpf, ver 1.0
10522 00:57:05.499495 <6>[ 1.567036] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10523 00:57:05.503267 <6>[ 1.574512] hns3: Copyright (c) 2017 Huawei Corporation.
10524 00:57:05.509773 <6>[ 1.580099] hclge is initializing
10525 00:57:05.513738 <6>[ 1.583673] e1000: Intel(R) PRO/1000 Network Driver
10526 00:57:05.519620 <6>[ 1.588802] e1000: Copyright (c) 1999-2006 Intel Corporation.
10527 00:57:05.522774 <6>[ 1.594813] e1000e: Intel(R) PRO/1000 Network Driver
10528 00:57:05.529647 <6>[ 1.600030] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10529 00:57:05.536129 <6>[ 1.606217] igb: Intel(R) Gigabit Ethernet Network Driver
10530 00:57:05.542771 <6>[ 1.611867] igb: Copyright (c) 2007-2014 Intel Corporation.
10531 00:57:05.549421 <6>[ 1.617702] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10532 00:57:05.555962 <6>[ 1.624220] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10533 00:57:05.560081 <6>[ 1.630676] sky2: driver version 1.30
10534 00:57:05.565974 <6>[ 1.635661] VFIO - User Level meta-driver version: 0.3
10535 00:57:05.573970 <6>[ 1.643880] usbcore: registered new interface driver usb-storage
10536 00:57:05.579869 <6>[ 1.650331] usbcore: registered new device driver onboard-usb-hub
10537 00:57:05.589089 <6>[ 1.659459] mt6397-rtc mt6359-rtc: registered as rtc0
10538 00:57:05.598810 <6>[ 1.664940] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T00:57:06 UTC (1705625826)
10539 00:57:05.602376 <6>[ 1.674525] i2c_dev: i2c /dev entries driver
10540 00:57:05.618884 <6>[ 1.686191] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10541 00:57:05.640104 <6>[ 1.710176] cpu cpu0: EM: created perf domain
10542 00:57:05.642903 <6>[ 1.715104] cpu cpu4: EM: created perf domain
10543 00:57:05.650282 <6>[ 1.720650] sdhci: Secure Digital Host Controller Interface driver
10544 00:57:05.656687 <6>[ 1.727080] sdhci: Copyright(c) Pierre Ossman
10545 00:57:05.663305 <6>[ 1.732034] Synopsys Designware Multimedia Card Interface Driver
10546 00:57:05.670289 <6>[ 1.738670] sdhci-pltfm: SDHCI platform and OF driver helper
10547 00:57:05.673274 <6>[ 1.738719] mmc0: CQHCI version 5.10
10548 00:57:05.680435 <6>[ 1.748605] ledtrig-cpu: registered to indicate activity on CPUs
10549 00:57:05.687038 <6>[ 1.755528] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10550 00:57:05.693936 <6>[ 1.762580] usbcore: registered new interface driver usbhid
10551 00:57:05.696742 <6>[ 1.768403] usbhid: USB HID core driver
10552 00:57:05.703207 <6>[ 1.772605] spi_master spi0: will run message pump with realtime priority
10553 00:57:05.746103 <6>[ 1.810049] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10554 00:57:05.764898 <6>[ 1.825090] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10555 00:57:05.767951 <6>[ 1.839852] mmc0: Command Queue Engine enabled
10556 00:57:05.775272 <6>[ 1.844603] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10557 00:57:05.781567 <6>[ 1.851314] cros-ec-spi spi0.0: Chrome EC device registered
10558 00:57:05.785041 <6>[ 1.851840] mmcblk0: mmc0:0001 DA4128 116 GiB
10559 00:57:05.795442 <6>[ 1.866080] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10560 00:57:05.803432 <6>[ 1.873621] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10561 00:57:05.810296 <6>[ 1.879452] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10562 00:57:05.816528 <6>[ 1.885512] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10563 00:57:05.831447 <6>[ 1.898913] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10564 00:57:05.838790 <6>[ 1.909479] NET: Registered PF_PACKET protocol family
10565 00:57:05.842522 <6>[ 1.914871] 9pnet: Installing 9P2000 support
10566 00:57:05.848290 <5>[ 1.919447] Key type dns_resolver registered
10567 00:57:05.851884 <6>[ 1.924449] registered taskstats version 1
10568 00:57:05.858274 <5>[ 1.928823] Loading compiled-in X.509 certificates
10569 00:57:05.889078 <4>[ 1.953343] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 00:57:05.898766 <4>[ 1.964131] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 00:57:05.905265 <3>[ 1.974667] debugfs: File 'uA_load' in directory '/' already present!
10572 00:57:05.912146 <3>[ 1.981366] debugfs: File 'min_uV' in directory '/' already present!
10573 00:57:05.918719 <3>[ 1.987973] debugfs: File 'max_uV' in directory '/' already present!
10574 00:57:05.924989 <3>[ 1.994580] debugfs: File 'constraint_flags' in directory '/' already present!
10575 00:57:05.936495 <3>[ 2.004267] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10576 00:57:05.945812 <6>[ 2.016739] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10577 00:57:05.952651 <6>[ 2.023444] xhci-mtk 11200000.usb: xHCI Host Controller
10578 00:57:05.958925 <6>[ 2.028935] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10579 00:57:05.969460 <6>[ 2.036779] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10580 00:57:05.976076 <6>[ 2.046177] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10581 00:57:05.982774 <6>[ 2.052238] xhci-mtk 11200000.usb: xHCI Host Controller
10582 00:57:05.989114 <6>[ 2.057714] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10583 00:57:05.995300 <6>[ 2.065360] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10584 00:57:06.002248 <6>[ 2.072987] hub 1-0:1.0: USB hub found
10585 00:57:06.005396 <6>[ 2.076996] hub 1-0:1.0: 1 port detected
10586 00:57:06.012336 <6>[ 2.081250] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10587 00:57:06.019289 <6>[ 2.089780] hub 2-0:1.0: USB hub found
10588 00:57:06.022086 <6>[ 2.093784] hub 2-0:1.0: 1 port detected
10589 00:57:06.031344 <6>[ 2.102165] mtk-msdc 11f70000.mmc: Got CD GPIO
10590 00:57:06.041102 <6>[ 2.108537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10591 00:57:06.047931 <6>[ 2.116572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10592 00:57:06.057592 <4>[ 2.124476] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10593 00:57:06.067857 <6>[ 2.133996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10594 00:57:06.074323 <6>[ 2.142073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10595 00:57:06.080607 <6>[ 2.150219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10596 00:57:06.091127 <6>[ 2.158171] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10597 00:57:06.097826 <6>[ 2.165989] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10598 00:57:06.107579 <6>[ 2.173807] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10599 00:57:06.117578 <6>[ 2.184204] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10600 00:57:06.123865 <6>[ 2.192595] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10601 00:57:06.133812 <6>[ 2.200938] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10602 00:57:06.140689 <6>[ 2.209278] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10603 00:57:06.150113 <6>[ 2.217616] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10604 00:57:06.157152 <6>[ 2.225957] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10605 00:57:06.166971 <6>[ 2.234296] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10606 00:57:06.173296 <6>[ 2.242636] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10607 00:57:06.183444 <6>[ 2.250983] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10608 00:57:06.192981 <6>[ 2.259323] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10609 00:57:06.200256 <6>[ 2.267664] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10610 00:57:06.210234 <6>[ 2.276002] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10611 00:57:06.216790 <6>[ 2.284341] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10612 00:57:06.226804 <6>[ 2.292682] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10613 00:57:06.233441 <6>[ 2.301021] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10614 00:57:06.240224 <6>[ 2.309880] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10615 00:57:06.246656 <6>[ 2.317215] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10616 00:57:06.253941 <6>[ 2.324186] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10617 00:57:06.263858 <6>[ 2.331060] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10618 00:57:06.270599 <6>[ 2.338134] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10619 00:57:06.277189 <6>[ 2.344997] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10620 00:57:06.287172 <6>[ 2.354125] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10621 00:57:06.296813 <6>[ 2.363244] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10622 00:57:06.306433 <6>[ 2.372546] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10623 00:57:06.317288 <6>[ 2.382015] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10624 00:57:06.326592 <6>[ 2.391481] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10625 00:57:06.333051 <6>[ 2.400600] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10626 00:57:06.343257 <6>[ 2.410065] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10627 00:57:06.353162 <6>[ 2.419183] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10628 00:57:06.362901 <6>[ 2.428477] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10629 00:57:06.372753 <6>[ 2.438637] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10630 00:57:06.382749 <6>[ 2.450113] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10631 00:57:06.389563 <6>[ 2.459873] Trying to probe devices needed for running init ...
10632 00:57:06.413706 <6>[ 2.481106] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10633 00:57:06.441039 <6>[ 2.511678] hub 2-1:1.0: USB hub found
10634 00:57:06.443963 <6>[ 2.516108] hub 2-1:1.0: 3 ports detected
10635 00:57:06.451711 <6>[ 2.522604] hub 2-1:1.0: USB hub found
10636 00:57:06.455540 <6>[ 2.526956] hub 2-1:1.0: 3 ports detected
10637 00:57:06.565460 <6>[ 2.632859] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10638 00:57:06.720747 <6>[ 2.791070] hub 1-1:1.0: USB hub found
10639 00:57:06.723805 <6>[ 2.795580] hub 1-1:1.0: 4 ports detected
10640 00:57:06.733624 <6>[ 2.804354] hub 1-1:1.0: USB hub found
10641 00:57:06.736764 <6>[ 2.808779] hub 1-1:1.0: 4 ports detected
10642 00:57:06.797551 <6>[ 2.864985] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10643 00:57:07.057288 <6>[ 3.124901] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10644 00:57:07.190164 <6>[ 3.260898] hub 1-1.4:1.0: USB hub found
10645 00:57:07.193798 <6>[ 3.265569] hub 1-1.4:1.0: 2 ports detected
10646 00:57:07.203972 <6>[ 3.274191] hub 1-1.4:1.0: USB hub found
10647 00:57:07.206619 <6>[ 3.278843] hub 1-1.4:1.0: 2 ports detected
10648 00:57:07.505357 <6>[ 3.572931] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10649 00:57:07.697322 <6>[ 3.764928] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10650 00:57:18.690027 <6>[ 14.765903] ALSA device list:
10651 00:57:18.696315 <6>[ 14.769199] No soundcards found.
10652 00:57:18.704417 <6>[ 14.777131] Freeing unused kernel memory: 8448K
10653 00:57:18.707812 <6>[ 14.782122] Run /init as init process
10654 00:57:18.719464 Loading, please wait...
10655 00:57:18.739928 Starting version 247.3-7+deb11u2
10656 00:57:19.008194 <6>[ 15.077519] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10657 00:57:19.039165 <3>[ 15.108093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 00:57:19.045225 <3>[ 15.116231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 00:57:19.056529 <6>[ 15.116464] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10660 00:57:19.058531 <6>[ 15.116549] remoteproc remoteproc0: scp is available
10661 00:57:19.065286 <6>[ 15.116672] remoteproc remoteproc0: powering up scp
10662 00:57:19.071961 <6>[ 15.116680] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10663 00:57:19.079088 <6>[ 15.116705] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10664 00:57:19.082231 <6>[ 15.117696] mc: Linux media interface: v0.10
10665 00:57:19.091945 <3>[ 15.124327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 00:57:19.101848 <6>[ 15.131925] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10667 00:57:19.108266 <6>[ 15.136654] usbcore: registered new device driver r8152-cfgselector
10668 00:57:19.115529 <4>[ 15.136748] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10669 00:57:19.122221 <4>[ 15.137573] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10670 00:57:19.128756 <3>[ 15.140750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 00:57:19.139178 <3>[ 15.140763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 00:57:19.145136 <3>[ 15.140770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 00:57:19.154792 <3>[ 15.140780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 00:57:19.161932 <3>[ 15.140787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 00:57:19.171597 <6>[ 15.142279] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10676 00:57:19.178333 <3>[ 15.142834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 00:57:19.188196 <6>[ 15.149455] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10678 00:57:19.191814 <6>[ 15.169583] videodev: Linux video capture interface: v2.00
10679 00:57:19.201605 <4>[ 15.177564] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10680 00:57:19.204774 <4>[ 15.177564] Fallback method does not support PEC.
10681 00:57:19.214509 <3>[ 15.178106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 00:57:19.224261 <3>[ 15.194647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 00:57:19.230905 <3>[ 15.199127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 00:57:19.240743 <6>[ 15.209369] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10685 00:57:19.250686 <3>[ 15.215200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 00:57:19.256941 <3>[ 15.215463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 00:57:19.267833 <6>[ 15.223743] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10688 00:57:19.273978 <3>[ 15.231655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 00:57:19.283985 <6>[ 15.240929] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 00:57:19.290535 <3>[ 15.248284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 00:57:19.297564 <3>[ 15.248291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 00:57:19.307074 <3>[ 15.248294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 00:57:19.313821 <3>[ 15.248328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 00:57:19.320737 <6>[ 15.265910] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10695 00:57:19.330805 <6>[ 15.269916] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10696 00:57:19.337064 <6>[ 15.269916] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10697 00:57:19.343458 <6>[ 15.269924] remoteproc remoteproc0: remote processor scp is now up
10698 00:57:19.350331 <6>[ 15.283484] pci_bus 0000:00: root bus resource [bus 00-ff]
10699 00:57:19.357035 <6>[ 15.283490] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 00:57:19.366971 <6>[ 15.283493] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10701 00:57:19.373131 <6>[ 15.283532] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10702 00:57:19.383581 <6>[ 15.294646] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10703 00:57:19.389689 <6>[ 15.300363] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10704 00:57:19.399894 <4>[ 15.313419] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10705 00:57:19.403046 <6>[ 15.318740] pci 0000:00:00.0: supports D1 D2
10706 00:57:19.413491 <6>[ 15.324413] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10707 00:57:19.419605 <4>[ 15.326651] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10708 00:57:19.429686 <6>[ 15.327497] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10709 00:57:19.436395 <6>[ 15.335001] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10710 00:57:19.439293 <6>[ 15.335788] Bluetooth: Core ver 2.22
10711 00:57:19.442900 <6>[ 15.335863] NET: Registered PF_BLUETOOTH protocol family
10712 00:57:19.449381 <6>[ 15.335865] Bluetooth: HCI device and connection manager initialized
10713 00:57:19.456133 <6>[ 15.335898] Bluetooth: HCI socket layer initialized
10714 00:57:19.462827 <6>[ 15.335908] Bluetooth: L2CAP socket layer initialized
10715 00:57:19.465965 <6>[ 15.335921] Bluetooth: SCO socket layer initialized
10716 00:57:19.472267 <6>[ 15.369353] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10717 00:57:19.482535 <3>[ 15.376364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 00:57:19.489275 <6>[ 15.377535] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10719 00:57:19.495739 <6>[ 15.377755] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10720 00:57:19.505672 <6>[ 15.377788] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10721 00:57:19.512259 <6>[ 15.377814] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10722 00:57:19.518681 <6>[ 15.377829] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10723 00:57:19.522148 <6>[ 15.377950] pci 0000:01:00.0: supports D1 D2
10724 00:57:19.531830 <6>[ 15.377952] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10725 00:57:19.535258 <6>[ 15.385275] usbcore: registered new interface driver btusb
10726 00:57:19.548790 <6>[ 15.385973] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10727 00:57:19.554790 <6>[ 15.386126] usbcore: registered new interface driver uvcvideo
10728 00:57:19.564953 <4>[ 15.388789] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10729 00:57:19.571763 <3>[ 15.388799] Bluetooth: hci0: Failed to load firmware file (-2)
10730 00:57:19.578111 <3>[ 15.388803] Bluetooth: hci0: Failed to set up firmware (-2)
10731 00:57:19.588130 <4>[ 15.388807] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10732 00:57:19.594706 <6>[ 15.388807] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10733 00:57:19.601606 <6>[ 15.388859] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10734 00:57:19.611285 <6>[ 15.388864] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10735 00:57:19.617796 <6>[ 15.388873] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10736 00:57:19.627753 <6>[ 15.388886] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10737 00:57:19.634120 <6>[ 15.388898] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10738 00:57:19.641148 <6>[ 15.388911] pci 0000:00:00.0: PCI bridge to [bus 01]
10739 00:57:19.647577 <6>[ 15.388917] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10740 00:57:19.651004 <6>[ 15.388917] r8152 2-1.3:1.0 eth0: v1.12.13
10741 00:57:19.657221 <6>[ 15.388971] usbcore: registered new interface driver r8152
10742 00:57:19.664326 <6>[ 15.389101] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10743 00:57:19.670570 <6>[ 15.390174] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10744 00:57:19.677134 <6>[ 15.390321] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10745 00:57:19.683959 <6>[ 15.400490] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10746 00:57:19.687492 <6>[ 15.407840] usbcore: registered new interface driver cdc_ether
10747 00:57:19.697099 <5>[ 15.416500] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10748 00:57:19.703751 <6>[ 15.427511] usbcore: registered new interface driver r8153_ecm
10749 00:57:19.710136 <5>[ 15.444511] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10750 00:57:19.717202 <6>[ 15.459931] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10751 00:57:19.723564 <5>[ 15.467910] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10752 00:57:19.755736 <4>[ 15.825033] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10753 00:57:19.763056 <6>[ 15.833925] cfg80211: failed to load regulatory.db
10754 00:57:19.798461 <6>[ 15.867660] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10755 00:57:19.804906 <6>[ 15.875163] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10756 00:57:19.828923 <6>[ 15.901816] mt7921e 0000:01:00.0: ASIC revision: 79610010
10757 00:57:19.931317 <6>[ 16.000290] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10758 00:57:19.933924 <6>[ 16.000290]
10759 00:57:19.950408 Begin: Loading essential drivers ... done.
10760 00:57:19.953440 Begin: Running /scripts/init-premount ... done.
10761 00:57:19.960465 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10762 00:57:19.969968 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10763 00:57:19.973568 Device /sys/class/net/enx002432307c7b found
10764 00:57:19.973700 done.
10765 00:57:20.023412 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10766 00:57:20.201759 <6>[ 16.271059] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10767 00:57:20.947561 <6>[ 17.020258] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10768 00:57:21.045123 <6>[ 17.117616] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10769 00:57:21.092155 IP-Config: no response after 2 secs - giving up
10770 00:57:21.152132 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10771 00:57:21.172276 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10772 00:57:21.886956 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10773 00:57:21.893560 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10774 00:57:21.899973 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10775 00:57:21.906347 host : mt8192-asurada-spherion-r0-cbg-2
10776 00:57:21.913173 domain : lava-rack
10777 00:57:21.920156 rootserver: 192.168.201.1 rootpath:
10778 00:57:21.920244 filename :
10779 00:57:22.019563 done.
10780 00:57:22.026652 Begin: Running /scripts/nfs-bottom ... done.
10781 00:57:22.048826 Begin: Running /scripts/init-bottom ... done.
10782 00:57:23.272632 <6>[ 19.345719] NET: Registered PF_INET6 protocol family
10783 00:57:23.280057 <6>[ 19.352978] Segment Routing with IPv6
10784 00:57:23.283284 <6>[ 19.356979] In-situ OAM (IOAM) with IPv6
10785 00:57:23.414947 <30>[ 19.468436] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10786 00:57:23.421468 <30>[ 19.492893] systemd[1]: Detected architecture arm64.
10787 00:57:23.441937
10788 00:57:23.444917 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10789 00:57:23.445038
10790 00:57:23.462383 <30>[ 19.535565] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10791 00:57:24.300702 <30>[ 20.370183] systemd[1]: Queued start job for default target Graphical Interface.
10792 00:57:24.346196 <30>[ 20.419240] systemd[1]: Created slice system-getty.slice.
10793 00:57:24.352855 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10794 00:57:24.369012 <30>[ 20.442269] systemd[1]: Created slice system-modprobe.slice.
10795 00:57:24.375436 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10796 00:57:24.393312 <30>[ 20.466139] systemd[1]: Created slice system-serial\x2dgetty.slice.
10797 00:57:24.403020 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10798 00:57:24.417086 <30>[ 20.490016] systemd[1]: Created slice User and Session Slice.
10799 00:57:24.423358 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10800 00:57:24.444512 <30>[ 20.513772] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10801 00:57:24.454038 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10802 00:57:24.471833 <30>[ 20.541582] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10803 00:57:24.478315 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10804 00:57:24.503025 <30>[ 20.569494] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10805 00:57:24.509717 <30>[ 20.581768] systemd[1]: Reached target Local Encrypted Volumes.
10806 00:57:24.515945 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10807 00:57:24.532297 <30>[ 20.605404] systemd[1]: Reached target Paths.
10808 00:57:24.538995 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10809 00:57:24.551580 <30>[ 20.624911] systemd[1]: Reached target Remote File Systems.
10810 00:57:24.558099 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10811 00:57:24.575953 <30>[ 20.649288] systemd[1]: Reached target Slices.
10812 00:57:24.582716 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10813 00:57:24.596111 <30>[ 20.668929] systemd[1]: Reached target Swap.
10814 00:57:24.599246 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10815 00:57:24.619886 <30>[ 20.689453] systemd[1]: Listening on initctl Compatibility Named Pipe.
10816 00:57:24.626128 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10817 00:57:24.632871 <30>[ 20.705661] systemd[1]: Listening on Journal Audit Socket.
10818 00:57:24.639396 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10819 00:57:24.657172 <30>[ 20.730197] systemd[1]: Listening on Journal Socket (/dev/log).
10820 00:57:24.663640 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10821 00:57:24.680671 <30>[ 20.753508] systemd[1]: Listening on Journal Socket.
10822 00:57:24.686842 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10823 00:57:24.704430 <30>[ 20.774466] systemd[1]: Listening on Network Service Netlink Socket.
10824 00:57:24.711110 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10825 00:57:24.726822 <30>[ 20.799895] systemd[1]: Listening on udev Control Socket.
10826 00:57:24.733085 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10827 00:57:24.748037 <30>[ 20.821362] systemd[1]: Listening on udev Kernel Socket.
10828 00:57:24.754737 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10829 00:57:24.811993 <30>[ 20.885078] systemd[1]: Mounting Huge Pages File System...
10830 00:57:24.818792 Mounting [0;1;39mHuge Pages File System[0m...
10831 00:57:24.836306 <30>[ 20.909314] systemd[1]: Mounting POSIX Message Queue File System...
10832 00:57:24.842861 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10833 00:57:24.864633 <30>[ 20.937416] systemd[1]: Mounting Kernel Debug File System...
10834 00:57:24.871149 Mounting [0;1;39mKernel Debug File System[0m...
10835 00:57:24.887220 <30>[ 20.957390] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10836 00:57:24.932043 <30>[ 21.001644] systemd[1]: Starting Create list of static device nodes for the current kernel...
10837 00:57:24.938389 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10838 00:57:24.964312 <30>[ 21.037557] systemd[1]: Starting Load Kernel Module configfs...
10839 00:57:24.971339 Starting [0;1;39mLoad Kernel Module configfs[0m...
10840 00:57:24.991295 <30>[ 21.064157] systemd[1]: Starting Load Kernel Module drm...
10841 00:57:24.997787 Starting [0;1;39mLoad Kernel Module drm[0m...
10842 00:57:25.015326 <30>[ 21.088334] systemd[1]: Starting Load Kernel Module fuse...
10843 00:57:25.021610 Starting [0;1;39mLoad Kernel Module fuse[0m...
10844 00:57:25.062778 <30>[ 21.132720] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10845 00:57:25.069290 <6>[ 21.133785] fuse: init (API version 7.37)
10846 00:57:25.108179 <30>[ 21.181492] systemd[1]: Starting Journal Service...
10847 00:57:25.114585 Starting [0;1;39mJournal Service[0m...
10848 00:57:25.139028 <30>[ 21.212696] systemd[1]: Starting Load Kernel Modules...
10849 00:57:25.146073 Starting [0;1;39mLoad Kernel Modules[0m...
10850 00:57:25.165724 <30>[ 21.235853] systemd[1]: Starting Remount Root and Kernel File Systems...
10851 00:57:25.172314 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10852 00:57:25.191502 <30>[ 21.264906] systemd[1]: Starting Coldplug All udev Devices...
10853 00:57:25.198304 Starting [0;1;39mColdplug All udev Devices[0m...
10854 00:57:25.215620 <30>[ 21.288481] systemd[1]: Mounted Huge Pages File System.
10855 00:57:25.222107 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10856 00:57:25.236164 <30>[ 21.309385] systemd[1]: Mounted POSIX Message Queue File System.
10857 00:57:25.242722 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10858 00:57:25.260683 <30>[ 21.333654] systemd[1]: Mounted Kernel Debug File System.
10859 00:57:25.267125 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10860 00:57:25.289474 <30>[ 21.359546] systemd[1]: Finished Create list of static device nodes for the current kernel.
10861 00:57:25.299638 <3>[ 21.368474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 00:57:25.306071 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10863 00:57:25.320988 <30>[ 21.394420] systemd[1]: modprobe@configfs.service: Succeeded.
10864 00:57:25.328780 <30>[ 21.402079] systemd[1]: Finished Load Kernel Module configfs.
10865 00:57:25.335696 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10866 00:57:25.346823 <3>[ 21.416340] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 00:57:25.353315 <30>[ 21.426051] systemd[1]: modprobe@drm.service: Succeeded.
10868 00:57:25.359583 <30>[ 21.432554] systemd[1]: Finished Load Kernel Module drm.
10869 00:57:25.366227 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10870 00:57:25.381902 <30>[ 21.454094] systemd[1]: modprobe@fuse.service: Succeeded.
10871 00:57:25.391924 <3>[ 21.459799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 00:57:25.394789 <30>[ 21.462134] systemd[1]: Finished Load Kernel Module fuse.
10873 00:57:25.401514 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10874 00:57:25.419632 <3>[ 21.489526] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 00:57:25.426869 <30>[ 21.490491] systemd[1]: Finished Load Kernel Modules.
10876 00:57:25.432923 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10877 00:57:25.449547 <30>[ 21.519094] systemd[1]: Finished Remount Root and Kernel File Systems.
10878 00:57:25.455968 <3>[ 21.519324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 00:57:25.462839 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10880 00:57:25.485406 <3>[ 21.555292] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 00:57:25.518319 <3>[ 21.587569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 00:57:25.524266 <30>[ 21.589321] systemd[1]: Mounting FUSE Control File System...
10883 00:57:25.530870 Mounting [0;1;39mFUSE Control File System[0m...
10884 00:57:25.547574 <3>[ 21.617388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 00:57:25.554337 <30>[ 21.621708] systemd[1]: Mounting Kernel Configuration File System...
10886 00:57:25.560838 Mounting [0;1;39mKernel Configuration File System[0m...
10887 00:57:25.579969 <3>[ 21.649456] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 00:57:25.589671 <30>[ 21.654662] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10889 00:57:25.599270 <30>[ 21.667279] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10890 00:57:25.614176 <3>[ 21.684290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 00:57:25.632452 <30>[ 21.705682] systemd[1]: Starting Load/Save Random Seed...
10892 00:57:25.639262 Starting [0;1;39mLoad/Save Random Seed[0m...
10893 00:57:25.654739 <30>[ 21.727731] systemd[1]: Starting Apply Kernel Variables...
10894 00:57:25.661196 Starting [0;1;39mApply Kernel Variables[0m...
10895 00:57:25.681778 <4>[ 21.744494] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10896 00:57:25.691261 <3>[ 21.760386] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10897 00:57:25.698251 <30>[ 21.771638] systemd[1]: Starting Create System Users...
10898 00:57:25.704822 Starting [0;1;39mCreate System Users[0m...
10899 00:57:25.721328 <30>[ 21.794798] systemd[1]: Started Journal Service.
10900 00:57:25.727962 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10901 00:57:25.747408 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10902 00:57:25.763873 See 'systemctl status systemd-udev-trigger.service' for details.
10903 00:57:25.780800 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10904 00:57:25.799068 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10905 00:57:25.812552 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10906 00:57:25.830110 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10907 00:57:25.845631 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10908 00:57:25.901139 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10909 00:57:25.918345 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10910 00:57:25.954492 <46>[ 22.024775] systemd-journald[294]: Received client request to flush runtime journal.
10911 00:57:26.628641 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10912 00:57:26.640612 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10913 00:57:26.655684 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10914 00:57:26.708351 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10915 00:57:27.359169 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10916 00:57:27.388700 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10917 00:57:27.487323 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10918 00:57:27.560665 Starting [0;1;39mNetwork Service[0m...
10919 00:57:27.721263 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10920 00:57:27.788071 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10921 00:57:27.808764 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10922 00:57:28.260167 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10923 00:57:28.279368 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10924 00:57:28.295946 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10925 00:57:28.328851 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10926 00:57:28.380189 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10927 00:57:28.409017 Starting [0;1;39mNetwork Time Synchronization[0m...
10928 00:57:28.427757 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10929 00:57:28.443918 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10930 00:57:28.464947 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10931 00:57:28.540556 Starting [0;1;39mNetwork Name Resolution[0m...
10932 00:57:28.560238 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10933 00:57:28.576658 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10934 00:57:28.591550 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10935 00:57:28.613335 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10936 00:57:28.633125 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10937 00:57:28.660394 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10938 00:57:28.866604 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10939 00:57:29.312520 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10940 00:57:29.405797 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10941 00:57:29.423096 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10942 00:57:29.435324 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10943 00:57:29.687566 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10944 00:57:29.703202 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10945 00:57:29.719452 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10946 00:57:29.760317 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10947 00:57:29.821009 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10948 00:57:29.928224 Starting [0;1;39mUser Login Management[0m...
10949 00:57:30.416004 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10950 00:57:30.432422 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10951 00:57:30.447715 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10952 00:57:30.467009 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10953 00:57:30.499858 Starting [0;1;39mPermit User Sessions[0m...
10954 00:57:30.516248 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10955 00:57:30.539623 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10956 00:57:30.553081 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10957 00:57:30.573208 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10958 00:57:30.592697 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10959 00:57:30.608088 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10960 00:57:30.623172 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10961 00:57:30.680680 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10962 00:57:30.725176 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10963 00:57:30.772388
10964 00:57:30.772517
10965 00:57:30.775129 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10966 00:57:30.775252
10967 00:57:30.778488 debian-bullseye-arm64 login: root (automatic login)
10968 00:57:30.778565
10969 00:57:30.778628
10970 00:57:31.136890 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
10971 00:57:31.137018
10972 00:57:31.143212 The programs included with the Debian GNU/Linux system are free software;
10973 00:57:31.149814 the exact distribution terms for each program are described in the
10974 00:57:31.153118 individual files in /usr/share/doc/*/copyright.
10975 00:57:31.153202
10976 00:57:31.159526 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10977 00:57:31.163029 permitted by applicable law.
10978 00:57:31.261367 Matched prompt #10: / #
10980 00:57:31.261653 Setting prompt string to ['/ #']
10981 00:57:31.261746 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10983 00:57:31.261940 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10984 00:57:31.262027 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
10985 00:57:31.262095 Setting prompt string to ['/ #']
10986 00:57:31.262155 Forcing a shell prompt, looking for ['/ #']
10988 00:57:31.312369 / #
10989 00:57:31.312488 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10990 00:57:31.312568 Waiting using forced prompt support (timeout 00:02:30)
10991 00:57:31.317295
10992 00:57:31.317572 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10993 00:57:31.317662 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
10995 00:57:31.418003 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk'
10996 00:57:31.423230 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571137/extract-nfsrootfs-3ybsqxdk'
10998 00:57:31.523816 / # export NFS_SERVER_IP='192.168.201.1'
10999 00:57:31.529324 export NFS_SERVER_IP='192.168.201.1'
11000 00:57:31.529614 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11001 00:57:31.529713 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11002 00:57:31.529802 end: 2 depthcharge-action (duration 00:01:50) [common]
11003 00:57:31.529891 start: 3 lava-test-retry (timeout 00:01:00) [common]
11004 00:57:31.529975 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11005 00:57:31.530051 Using namespace: common
11007 00:57:31.630398 / # #
11008 00:57:31.630562 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11009 00:57:31.635589 #
11010 00:57:31.635919 Using /lava-12571137
11012 00:57:31.736262 / # export SHELL=/bin/sh
11013 00:57:31.741611 export SHELL=/bin/sh
11015 00:57:31.842083 / # . /lava-12571137/environment
11016 00:57:31.847715 . /lava-12571137/environment
11018 00:57:31.952857 / # /lava-12571137/bin/lava-test-runner /lava-12571137/0
11019 00:57:31.952987 Test shell timeout: 10s (minimum of the action and connection timeout)
11020 00:57:31.957991 /lava-12571137/bin/lava-test-runner /lava-12571137/0
11021 00:57:32.214430 + export TESTRUN_ID=0_dmesg
11022 00:57:32.217296 + cd /lava-12571137/0/tests/0_dmesg
11023 00:57:32.220357 + cat uuid
11024 00:57:32.237474 + UUID=12571137_<8>[ 28.308408] <LAVA_SIGNAL_STARTRUN 0_dmesg 12571137_1.6.2.3.1>
11025 00:57:32.237557 1.6.2.3.1
11026 00:57:32.237624 + set +x
11027 00:57:32.237903 Received signal: <STARTRUN> 0_dmesg 12571137_1.6.2.3.1
11028 00:57:32.238003 Starting test lava.0_dmesg (12571137_1.6.2.3.1)
11029 00:57:32.238122 Skipping test definition patterns.
11030 00:57:32.244037 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11031 00:57:32.363913 <8>[ 28.433756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11032 00:57:32.364219 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11034 00:57:32.445383 <8>[ 28.516409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11035 00:57:32.445681 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11037 00:57:32.528930 <8>[ 28.599852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11038 00:57:32.529232 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11040 00:57:32.535578 <8>[ 28.609637] <LAVA_SIGNAL_ENDRUN 0_dmesg 12571137_1.6.2.3.1>
11041 00:57:32.535662 + set +x
11042 00:57:32.535900 Received signal: <ENDRUN> 0_dmesg 12571137_1.6.2.3.1
11043 00:57:32.535981 Ending use of test pattern.
11044 00:57:32.536047 Ending test lava.0_dmesg (12571137_1.6.2.3.1), duration 0.30
11046 00:57:32.540554 <LAVA_TEST_RUNNER EXIT>
11047 00:57:32.540807 ok: lava_test_shell seems to have completed
11048 00:57:32.540912 alert: pass
crit: pass
emerg: pass
11049 00:57:32.540999 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11050 00:57:32.541085 end: 3 lava-test-retry (duration 00:00:01) [common]
11051 00:57:32.541167 start: 4 lava-test-retry (timeout 00:01:00) [common]
11052 00:57:32.541248 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11053 00:57:32.541312 Using namespace: common
11055 00:57:32.641593 / # #
11056 00:57:32.641724 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11057 00:57:32.641863 Using /lava-12571137
11059 00:57:32.742207 export SHELL=/bin/sh
11060 00:57:32.742376 #
11062 00:57:32.842873 / # export SHELL=/bin/sh. /lava-12571137/environment
11063 00:57:32.843049
11065 00:57:32.943652 / # . /lava-12571137/environment/lava-12571137/bin/lava-test-runner /lava-12571137/1
11066 00:57:32.943790 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 00:57:32.943939
11068 00:57:32.948654 / # /lava-12571137/bin/lava-test-runner /lava-12571137/1
11069 00:57:33.086575 + export TESTRUN_ID=1_bootrr
11070 00:57:33.090024 + cd /lava-12571137/1/tests/1_bootrr
11071 00:57:33.093587 + cat uuid
11072 00:57:33.107810 + UUID=12571137_1.<8>[ 29.178964] <LAVA_SIGNAL_STARTRUN 1_bootrr 12571137_1.6.2.3.5>
11073 00:57:33.107894 6.2.3.5
11074 00:57:33.107961 + set +x
11075 00:57:33.108196 Received signal: <STARTRUN> 1_bootrr 12571137_1.6.2.3.5
11076 00:57:33.108266 Starting test lava.1_bootrr (12571137_1.6.2.3.5)
11077 00:57:33.108346 Skipping test definition patterns.
11078 00:57:33.121337 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12571137/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11079 00:57:33.124803 + cd /opt/bootrr/libexec/bootrr
11080 00:57:33.124875 + sh helpers/bootrr-auto
11081 00:57:33.208594 /lava-12571137/1/../bin/lava-test-case
11082 00:57:33.246170 <8>[ 29.317249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11083 00:57:33.246446 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11085 00:57:33.296792 /lava-12571137/1/../bin/lava-test-case
11086 00:57:33.327668 <8>[ 29.398721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11087 00:57:33.327949 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11089 00:57:33.355868 /lava-12571137/1/../bin/lava-test-case
11090 00:57:33.386365 <8>[ 29.457220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11091 00:57:33.386638 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11093 00:57:33.452213 /lava-12571137/1/../bin/lava-test-case
11094 00:57:33.481692 <8>[ 29.552531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11095 00:57:33.481983 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11097 00:57:33.521679 /lava-12571137/1/../bin/lava-test-case
11098 00:57:33.552932 <8>[ 29.624033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11099 00:57:33.553205 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11101 00:57:33.589829 /lava-12571137/1/../bin/lava-test-case
11102 00:57:33.619558 <8>[ 29.690301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11103 00:57:33.619871 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11105 00:57:33.659501 /lava-12571137/1/../bin/lava-test-case
11106 00:57:33.694209 <8>[ 29.765170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11107 00:57:33.694479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11109 00:57:33.739717 /lava-12571137/1/../bin/lava-test-case
11110 00:57:33.770363 <8>[ 29.841183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11111 00:57:33.770646 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11113 00:57:33.794730 /lava-12571137/1/../bin/lava-test-case
11114 00:57:33.827903 <8>[ 29.898933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11115 00:57:33.828170 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11117 00:57:33.864662 /lava-12571137/1/../bin/lava-test-case
11118 00:57:33.893526 <8>[ 29.964154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11119 00:57:33.893792 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11121 00:57:33.917248 /lava-12571137/1/../bin/lava-test-case
11122 00:57:33.945166 <8>[ 30.016242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11123 00:57:33.945427 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11125 00:57:33.981248 /lava-12571137/1/../bin/lava-test-case
11126 00:57:34.015262 <8>[ 30.085935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11127 00:57:34.015532 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11129 00:57:34.062491 /lava-12571137/1/../bin/lava-test-case
11130 00:57:34.090126 <8>[ 30.160367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11131 00:57:34.090391 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11133 00:57:34.125657 /lava-12571137/1/../bin/lava-test-case
11134 00:57:34.156264 <8>[ 30.226776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11135 00:57:34.156534 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11137 00:57:34.196258 /lava-12571137/1/../bin/lava-test-case
11138 00:57:34.227139 <8>[ 30.298233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11139 00:57:34.227419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11141 00:57:34.252685 /lava-12571137/1/../bin/lava-test-case
11142 00:57:34.280438 <8>[ 30.351352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11143 00:57:34.280708 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11145 00:57:34.320570 /lava-12571137/1/../bin/lava-test-case
11146 00:57:34.353435 <8>[ 30.424253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11147 00:57:34.353723 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11149 00:57:34.383055 /lava-12571137/1/../bin/lava-test-case
11150 00:57:34.414510 <8>[ 30.485589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11151 00:57:34.414783 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11153 00:57:34.454914 /lava-12571137/1/../bin/lava-test-case
11154 00:57:34.487602 <8>[ 30.558777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11155 00:57:34.487879 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11157 00:57:34.511730 /lava-12571137/1/../bin/lava-test-case
11158 00:57:34.544205 <8>[ 30.614902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11159 00:57:34.544481 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11161 00:57:34.581475 /lava-12571137/1/../bin/lava-test-case
11162 00:57:34.612907 <8>[ 30.684202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11163 00:57:34.613205 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11165 00:57:34.636563 /lava-12571137/1/../bin/lava-test-case
11166 00:57:34.666578 <8>[ 30.737496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11167 00:57:34.666865 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11169 00:57:34.710376 /lava-12571137/1/../bin/lava-test-case
11170 00:57:34.741957 <8>[ 30.812370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11171 00:57:34.742228 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11173 00:57:34.766580 /lava-12571137/1/../bin/lava-test-case
11174 00:57:34.799083 <8>[ 30.870216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11175 00:57:34.799417 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11177 00:57:34.836495 /lava-12571137/1/../bin/lava-test-case
11178 00:57:34.865447 <8>[ 30.936498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11179 00:57:34.865729 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11181 00:57:34.903047 /lava-12571137/1/../bin/lava-test-case
11182 00:57:34.936746 <8>[ 31.007494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11183 00:57:34.937025 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11185 00:57:34.960766 /lava-12571137/1/../bin/lava-test-case
11186 00:57:34.992553 <8>[ 31.063601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11187 00:57:34.992823 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11189 00:57:35.035018 /lava-12571137/1/../bin/lava-test-case
11190 00:57:35.067949 <8>[ 31.138755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11191 00:57:35.068233 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11193 00:57:35.090968 /lava-12571137/1/../bin/lava-test-case
11194 00:57:35.119754 <8>[ 31.190256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11195 00:57:35.120034 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11197 00:57:35.157238 /lava-12571137/1/../bin/lava-test-case
11198 00:57:35.186940 <8>[ 31.257971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11199 00:57:35.187218 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11201 00:57:35.220232 /lava-12571137/1/../bin/lava-test-case
11202 00:57:35.248811 <8>[ 31.319587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11203 00:57:35.249083 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11205 00:57:35.284410 /lava-12571137/1/../bin/lava-test-case
11206 00:57:35.313901 <8>[ 31.384941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11207 00:57:35.314174 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11209 00:57:35.347869 /lava-12571137/1/../bin/lava-test-case
11210 00:57:35.379799 <8>[ 31.450651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11211 00:57:35.380080 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11213 00:57:35.409821 /lava-12571137/1/../bin/lava-test-case
11214 00:57:35.439275 <8>[ 31.510578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11215 00:57:35.439568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11217 00:57:35.478266 /lava-12571137/1/../bin/lava-test-case
11218 00:57:35.508575 <8>[ 31.579753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11219 00:57:35.508847 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11221 00:57:35.545511 /lava-12571137/1/../bin/lava-test-case
11222 00:57:35.575180 <8>[ 31.646385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11223 00:57:35.575479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11225 00:57:35.601889 /lava-12571137/1/../bin/lava-test-case
11226 00:57:35.634000 <8>[ 31.705432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11227 00:57:35.634328 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11229 00:57:35.675989 /lava-12571137/1/../bin/lava-test-case
11230 00:57:35.707956 <8>[ 31.778583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11231 00:57:35.708242 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11233 00:57:35.736353 /lava-12571137/1/../bin/lava-test-case
11234 00:57:35.765492 <8>[ 31.836535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11235 00:57:35.765763 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11237 00:57:35.802095 /lava-12571137/1/../bin/lava-test-case
11238 00:57:35.833911 <8>[ 31.904946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11239 00:57:35.834175 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11241 00:57:35.856984 /lava-12571137/1/../bin/lava-test-case
11242 00:57:35.888155 <8>[ 31.959365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11243 00:57:35.888422 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11245 00:57:35.924676 /lava-12571137/1/../bin/lava-test-case
11246 00:57:35.957566 <8>[ 32.028831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11247 00:57:35.957831 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11249 00:57:35.981383 /lava-12571137/1/../bin/lava-test-case
11250 00:57:36.011246 <8>[ 32.082506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11251 00:57:36.011510 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11253 00:57:36.051866 /lava-12571137/1/../bin/lava-test-case
11254 00:57:36.087238 <8>[ 32.158571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11255 00:57:36.087583 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11257 00:57:36.113309 /lava-12571137/1/../bin/lava-test-case
11258 00:57:36.148512 <8>[ 32.219488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11259 00:57:36.148782 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11261 00:57:36.187649 /lava-12571137/1/../bin/lava-test-case
11262 00:57:36.220348 <8>[ 32.291573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11263 00:57:36.220623 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11265 00:57:36.244416 /lava-12571137/1/../bin/lava-test-case
11266 00:57:36.274006 <8>[ 32.344823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11267 00:57:36.274322 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11269 00:57:36.311480 /lava-12571137/1/../bin/lava-test-case
11270 00:57:36.342621 <8>[ 32.413858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11271 00:57:36.342919 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11273 00:57:36.370693 /lava-12571137/1/../bin/lava-test-case
11274 00:57:36.401998 <8>[ 32.472825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11275 00:57:36.402270 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11277 00:57:36.438624 /lava-12571137/1/../bin/lava-test-case
11278 00:57:36.470781 <8>[ 32.541719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11279 00:57:36.471063 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11281 00:57:36.506232 /lava-12571137/1/../bin/lava-test-case
11282 00:57:36.538885 <8>[ 32.610101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11283 00:57:36.539153 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11285 00:57:36.562000 /lava-12571137/1/../bin/lava-test-case
11286 00:57:36.592201 <8>[ 32.662965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11287 00:57:36.592470 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11289 00:57:36.631699 /lava-12571137/1/../bin/lava-test-case
11290 00:57:36.661802 <8>[ 32.733282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11291 00:57:36.662089 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11293 00:57:36.692457 /lava-12571137/1/../bin/lava-test-case
11294 00:57:36.722007 <8>[ 32.793270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11295 00:57:36.722297 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11297 00:57:36.757710 /lava-12571137/1/../bin/lava-test-case
11298 00:57:36.789083 <8>[ 32.860637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11299 00:57:36.789383 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11301 00:57:36.826957 /lava-12571137/1/../bin/lava-test-case
11302 00:57:36.860412 <8>[ 32.931553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11303 00:57:36.860715 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11305 00:57:36.900065 /lava-12571137/1/../bin/lava-test-case
11306 00:57:36.931462 <8>[ 33.002839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11307 00:57:36.931746 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11309 00:57:36.967471 /lava-12571137/1/../bin/lava-test-case
11310 00:57:36.997276 <8>[ 33.068473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11311 00:57:36.997580 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11313 00:57:37.040753 /lava-12571137/1/../bin/lava-test-case
11314 00:57:37.071661 <8>[ 33.142866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11315 00:57:37.071987 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11317 00:57:37.095854 /lava-12571137/1/../bin/lava-test-case
11318 00:57:37.128660 <8>[ 33.200199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11319 00:57:37.128930 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11321 00:57:37.165802 /lava-12571137/1/../bin/lava-test-case
11322 00:57:37.197124 <8>[ 33.268448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11323 00:57:37.197396 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11325 00:57:37.236729 /lava-12571137/1/../bin/lava-test-case
11326 00:57:37.268424 <8>[ 33.339687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11327 00:57:37.268700 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11329 00:57:37.292900 /lava-12571137/1/../bin/lava-test-case
11330 00:57:37.327291 <8>[ 33.398738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11331 00:57:37.327617 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11333 00:57:37.372584 /lava-12571137/1/../bin/lava-test-case
11334 00:57:37.405184 <8>[ 33.476651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11335 00:57:37.405487 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11337 00:57:37.428897 /lava-12571137/1/../bin/lava-test-case
11338 00:57:37.458322 <8>[ 33.529860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11339 00:57:37.458638 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11341 00:57:37.497541 /lava-12571137/1/../bin/lava-test-case
11342 00:57:37.529529 <8>[ 33.600872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11343 00:57:37.529821 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11345 00:57:37.552159 /lava-12571137/1/../bin/lava-test-case
11346 00:57:37.584139 <8>[ 33.655608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11347 00:57:37.584467 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11349 00:57:37.622280 /lava-12571137/1/../bin/lava-test-case
11350 00:57:37.655179 <8>[ 33.726288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11351 00:57:37.655526 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11353 00:57:37.699737 /lava-12571137/1/../bin/lava-test-case
11354 00:57:37.730193 <8>[ 33.801536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11355 00:57:37.730476 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11357 00:57:37.769785 /lava-12571137/1/../bin/lava-test-case
11358 00:57:37.801423 <8>[ 33.873067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11359 00:57:37.801743 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11361 00:57:37.839350 /lava-12571137/1/../bin/lava-test-case
11362 00:57:37.869383 <8>[ 33.940687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11363 00:57:37.869718 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11365 00:57:37.905981 /lava-12571137/1/../bin/lava-test-case
11366 00:57:37.938613 <8>[ 34.009953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11367 00:57:37.938915 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11369 00:57:37.975555 /lava-12571137/1/../bin/lava-test-case
11370 00:57:38.006235 <8>[ 34.077143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11371 00:57:38.006509 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11373 00:57:38.049652 /lava-12571137/1/../bin/lava-test-case
11374 00:57:38.082002 <8>[ 34.153153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11375 00:57:38.082285 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11377 00:57:38.118621 /lava-12571137/1/../bin/lava-test-case
11378 00:57:38.150251 <8>[ 34.221924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11379 00:57:38.150526 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11381 00:57:38.186546 /lava-12571137/1/../bin/lava-test-case
11382 00:57:38.219043 <8>[ 34.290262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11383 00:57:38.219317 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11385 00:57:38.256852 /lava-12571137/1/../bin/lava-test-case
11386 00:57:38.289733 <8>[ 34.361185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11387 00:57:38.290010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11389 00:57:38.325773 /lava-12571137/1/../bin/lava-test-case
11390 00:57:38.353587 <8>[ 34.425217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11391 00:57:38.353849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11393 00:57:38.396122 /lava-12571137/1/../bin/lava-test-case
11394 00:57:38.425053 <8>[ 34.496724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11395 00:57:38.425372 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11397 00:57:38.463266 /lava-12571137/1/../bin/lava-test-case
11398 00:57:38.493199 <8>[ 34.564563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11399 00:57:38.493512 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11401 00:57:38.531807 /lava-12571137/1/../bin/lava-test-case
11402 00:57:38.564818 <8>[ 34.636158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11403 00:57:38.565146 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11405 00:57:38.606188 /lava-12571137/1/../bin/lava-test-case
11406 00:57:38.635779 <8>[ 34.707095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11407 00:57:38.636082 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11409 00:57:38.659498 /lava-12571137/1/../bin/lava-test-case
11410 00:57:38.690864 <8>[ 34.762603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11411 00:57:38.691173 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11413 00:57:38.733494 /lava-12571137/1/../bin/lava-test-case
11414 00:57:38.764090 <8>[ 34.835463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11415 00:57:38.764399 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11417 00:57:38.787295 /lava-12571137/1/../bin/lava-test-case
11418 00:57:38.817078 <8>[ 34.888583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11419 00:57:38.817377 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11421 00:57:38.855641 /lava-12571137/1/../bin/lava-test-case
11422 00:57:38.887629 <8>[ 34.958681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11423 00:57:38.887966 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11425 00:57:38.911303 /lava-12571137/1/../bin/lava-test-case
11426 00:57:38.941193 <8>[ 35.012766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11427 00:57:38.941495 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11429 00:57:38.978735 /lava-12571137/1/../bin/lava-test-case
11430 00:57:39.009469 <8>[ 35.080759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11431 00:57:39.009779 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11433 00:57:39.033831 /lava-12571137/1/../bin/lava-test-case
11434 00:57:39.070221 <8>[ 35.141815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11435 00:57:39.070543 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11437 00:57:39.109181 /lava-12571137/1/../bin/lava-test-case
11438 00:57:39.141496 <8>[ 35.212738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11439 00:57:39.141804 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11441 00:57:39.165967 /lava-12571137/1/../bin/lava-test-case
11442 00:57:39.197486 <8>[ 35.268956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11443 00:57:39.197784 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11445 00:57:39.235914 /lava-12571137/1/../bin/lava-test-case
11446 00:57:39.266443 <8>[ 35.338022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11447 00:57:39.266721 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11449 00:57:39.289640 /lava-12571137/1/../bin/lava-test-case
11450 00:57:39.328458 <8>[ 35.399999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11451 00:57:39.328735 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11453 00:57:39.373396 /lava-12571137/1/../bin/lava-test-case
11454 00:57:39.406598 <8>[ 35.478138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11455 00:57:39.406873 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11457 00:57:39.444645 /lava-12571137/1/../bin/lava-test-case
11458 00:57:39.477711 <8>[ 35.549271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11459 00:57:39.477995 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11461 00:57:39.504351 /lava-12571137/1/../bin/lava-test-case
11462 00:57:39.533948 <8>[ 35.605331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11463 00:57:39.534210 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11465 00:57:39.572250 /lava-12571137/1/../bin/lava-test-case
11466 00:57:39.601958 <8>[ 35.673727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11467 00:57:39.602226 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11469 00:57:39.625561 /lava-12571137/1/../bin/lava-test-case
11470 00:57:39.658478 <8>[ 35.730115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11471 00:57:39.658754 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11473 00:57:39.700664 /lava-12571137/1/../bin/lava-test-case
11474 00:57:39.732190 <8>[ 35.803883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11475 00:57:39.732468 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11477 00:57:39.754635 /lava-12571137/1/../bin/lava-test-case
11478 00:57:39.787725 <8>[ 35.859305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11479 00:57:39.787999 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11481 00:57:40.846760 /lava-12571137/1/../bin/lava-test-case
11482 00:57:40.876267 <8>[ 36.948113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11483 00:57:40.876557 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11485 00:57:40.899482 /lava-12571137/1/../bin/lava-test-case
11486 00:57:40.933076 <8>[ 37.004601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11487 00:57:40.933344 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11489 00:57:41.981656 /lava-12571137/1/../bin/lava-test-case
11490 00:57:42.013010 <8>[ 38.084858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11491 00:57:42.013334 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11493 00:57:42.034234 /lava-12571137/1/../bin/lava-test-case
11494 00:57:42.063074 <8>[ 38.134643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11495 00:57:42.063413 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11497 00:57:43.112218 /lava-12571137/1/../bin/lava-test-case
11498 00:57:43.145100 <8>[ 39.217039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11499 00:57:43.145427 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11501 00:57:43.168735 /lava-12571137/1/../bin/lava-test-case
11502 00:57:43.196878 <8>[ 39.268861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11503 00:57:43.197219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11505 00:57:44.247783 /lava-12571137/1/../bin/lava-test-case
11506 00:57:44.282310 <8>[ 40.354441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11507 00:57:44.282640 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11509 00:57:44.304107 /lava-12571137/1/../bin/lava-test-case
11510 00:57:44.333029 <8>[ 40.404474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11511 00:57:44.333396 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11513 00:57:45.381308 /lava-12571137/1/../bin/lava-test-case
11514 00:57:45.417699 <8>[ 41.489349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11515 00:57:45.418035 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11517 00:57:45.442166 /lava-12571137/1/../bin/lava-test-case
11518 00:57:45.473473 <8>[ 41.545787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11519 00:57:45.473848 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11521 00:57:46.527582 /lava-12571137/1/../bin/lava-test-case
11522 00:57:46.562052 <8>[ 42.633839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11523 00:57:46.562384 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11525 00:57:46.586233 /lava-12571137/1/../bin/lava-test-case
11526 00:57:46.618150 <8>[ 42.690497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11527 00:57:46.618491 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11529 00:57:47.667925 /lava-12571137/1/../bin/lava-test-case
11530 00:57:47.701344 <8>[ 43.774064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11531 00:57:47.701677 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11533 00:57:47.727186 /lava-12571137/1/../bin/lava-test-case
11534 00:57:47.760718 <8>[ 43.832877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11535 00:57:47.761066 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11537 00:57:47.784523 /lava-12571137/1/../bin/lava-test-case
11538 00:57:47.813187 <8>[ 43.885803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11539 00:57:47.813518 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11541 00:57:48.864500 /lava-12571137/1/../bin/lava-test-case
11542 00:57:48.898585 <8>[ 44.971021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11543 00:57:48.898915 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11545 00:57:48.923301 /lava-12571137/1/../bin/lava-test-case
11546 00:57:48.957004 <8>[ 45.029433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11547 00:57:48.957304 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11549 00:57:48.996144 /lava-12571137/1/../bin/lava-test-case
11550 00:57:49.027681 <8>[ 45.100339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11551 00:57:49.028006 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11553 00:57:49.053603 /lava-12571137/1/../bin/lava-test-case
11554 00:57:49.085667 <8>[ 45.157860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11555 00:57:49.085998 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11557 00:57:49.128329 /lava-12571137/1/../bin/lava-test-case
11558 00:57:49.158757 <8>[ 45.231438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11559 00:57:49.159083 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11561 00:57:49.205801 /lava-12571137/1/../bin/lava-test-case
11562 00:57:49.237934 <8>[ 45.310715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11563 00:57:49.238254 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11565 00:57:49.278844 /lava-12571137/1/../bin/lava-test-case
11566 00:57:49.310508 <8>[ 45.382959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11567 00:57:49.310819 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11569 00:57:49.335219 /lava-12571137/1/../bin/lava-test-case
11570 00:57:49.368954 <8>[ 45.441398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11571 00:57:49.369245 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11573 00:57:49.408555 /lava-12571137/1/../bin/lava-test-case
11574 00:57:49.443297 <8>[ 45.515936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11575 00:57:49.443659 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11577 00:57:49.485458 /lava-12571137/1/../bin/lava-test-case
11578 00:57:49.520363 <8>[ 45.593196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11579 00:57:49.520684 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11581 00:57:49.551084 /lava-12571137/1/../bin/lava-test-case
11582 00:57:49.583876 <8>[ 45.656585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11583 00:57:49.584200 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11585 00:57:49.624030 /lava-12571137/1/../bin/lava-test-case
11586 00:57:49.657641 <8>[ 45.730101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11587 00:57:49.657967 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11589 00:57:49.683543 /lava-12571137/1/../bin/lava-test-case
11590 00:57:49.714024 <8>[ 45.786432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11591 00:57:49.714355 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11593 00:57:49.751886 /lava-12571137/1/../bin/lava-test-case
11594 00:57:49.784326 <8>[ 45.857129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11595 00:57:49.784675 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11597 00:57:49.807854 /lava-12571137/1/../bin/lava-test-case
11598 00:57:49.835724 <8>[ 45.908459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11599 00:57:49.836044 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11601 00:57:49.880858 /lava-12571137/1/../bin/lava-test-case
11602 00:57:49.911577 <8>[ 45.984557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11603 00:57:49.911908 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11605 00:57:49.936682 /lava-12571137/1/../bin/lava-test-case
11606 00:57:49.970827 <8>[ 46.043618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11607 00:57:49.971155 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11609 00:57:50.010936 /lava-12571137/1/../bin/lava-test-case
11610 00:57:50.041687 <8>[ 46.114629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11611 00:57:50.042019 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11613 00:57:50.066750 /lava-12571137/1/../bin/lava-test-case
11614 00:57:50.081616 <6>[ 46.160941] vpu: disabling
11615 00:57:50.085227 <6>[ 46.164153] vproc2: disabling
11616 00:57:50.088318 <6>[ 46.167592] vproc1: disabling
11617 00:57:50.091560 <6>[ 46.171037] vaud18: disabling
11618 00:57:50.098590 <6>[ 46.174715] vsram_others: disabling
11619 00:57:50.102641 <6>[ 46.178821] va09: disabling
11620 00:57:50.105209 <6>[ 46.182096] vsram_md: disabling
11621 00:57:50.108854 <6>[ 46.185803] Vgpu: disabling
11622 00:57:50.118896 <8>[ 46.191672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11623 00:57:50.119181 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11625 00:57:50.157079 /lava-12571137/1/../bin/lava-test-case
11626 00:57:50.190491 <8>[ 46.263438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11627 00:57:50.190818 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11629 00:57:50.230471 /lava-12571137/1/../bin/lava-test-case
11630 00:57:50.260117 <8>[ 46.333047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11631 00:57:50.260450 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11633 00:57:51.317517 /lava-12571137/1/../bin/lava-test-case
11634 00:57:51.349593 <8>[ 47.422719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11635 00:57:51.349922 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11637 00:57:52.402199 /lava-12571137/1/../bin/lava-test-case
11638 00:57:52.434232 <8>[ 48.507199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11639 00:57:52.434559 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11641 00:57:52.461389 /lava-12571137/1/../bin/lava-test-case
11642 00:57:52.493194 <8>[ 48.565808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11643 00:57:52.493509 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11645 00:57:52.533006 /lava-12571137/1/../bin/lava-test-case
11646 00:57:52.566783 <8>[ 48.639897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11647 00:57:52.567110 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11649 00:57:52.590456 /lava-12571137/1/../bin/lava-test-case
11650 00:57:52.622882 <8>[ 48.695705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11651 00:57:52.623202 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11653 00:57:52.662553 /lava-12571137/1/../bin/lava-test-case
11654 00:57:52.694541 <8>[ 48.767614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11655 00:57:52.694857 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11657 00:57:52.726219 /lava-12571137/1/../bin/lava-test-case
11658 00:57:52.756872 <8>[ 48.830111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11659 00:57:52.757179 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11661 00:57:52.790970 /lava-12571137/1/../bin/lava-test-case
11662 00:57:52.825440 <8>[ 48.898250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11663 00:57:52.825783 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11665 00:57:52.849163 /lava-12571137/1/../bin/lava-test-case
11666 00:57:52.882935 <8>[ 48.956021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11667 00:57:52.883285 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11669 00:57:52.924045 /lava-12571137/1/../bin/lava-test-case
11670 00:57:52.957305 <8>[ 49.030650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11671 00:57:52.957628 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11673 00:57:52.984256 /lava-12571137/1/../bin/lava-test-case
11674 00:57:53.018783 <8>[ 49.091635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11675 00:57:53.019112 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11677 00:57:53.065285 /lava-12571137/1/../bin/lava-test-case
11678 00:57:53.100867 <8>[ 49.174103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11679 00:57:53.101204 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11681 00:57:53.124233 /lava-12571137/1/../bin/lava-test-case
11682 00:57:53.156771 <8>[ 49.229874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11683 00:57:53.157095 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11685 00:57:53.197662 /lava-12571137/1/../bin/lava-test-case
11686 00:57:53.231724 <8>[ 49.304863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11687 00:57:53.232028 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11689 00:57:53.258426 /lava-12571137/1/../bin/lava-test-case
11690 00:57:53.291204 <8>[ 49.364436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11691 00:57:53.291514 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11693 00:57:53.334250 /lava-12571137/1/../bin/lava-test-case
11694 00:57:53.367650 <8>[ 49.440595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11695 00:57:53.368025 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11697 00:57:53.398843 /lava-12571137/1/../bin/lava-test-case
11698 00:57:53.430369 <8>[ 49.503485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11699 00:57:53.430667 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11701 00:57:53.472417 /lava-12571137/1/../bin/lava-test-case
11702 00:57:53.505436 <8>[ 49.578114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11703 00:57:53.505754 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11705 00:57:53.528996 /lava-12571137/1/../bin/lava-test-case
11706 00:57:53.561767 <8>[ 49.634916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11707 00:57:53.562076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11709 00:57:53.600396 /lava-12571137/1/../bin/lava-test-case
11710 00:57:53.637547 <8>[ 49.710881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11711 00:57:53.637845 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11713 00:57:53.662696 /lava-12571137/1/../bin/lava-test-case
11714 00:57:53.697056 <8>[ 49.770144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11715 00:57:53.697663 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11717 00:57:53.749063 /lava-12571137/1/../bin/lava-test-case
11718 00:57:53.785186 <8>[ 49.858454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11719 00:57:53.785498 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11721 00:57:54.826512 /lava-12571137/1/../bin/lava-test-case
11722 00:57:54.863608 <8>[ 50.936352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11723 00:57:54.864354 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11725 00:57:55.908392 /lava-12571137/1/../bin/lava-test-case
11726 00:57:55.948766 <8>[ 52.021792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11727 00:57:55.949490 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11728 00:57:55.949935 Bad test result: blocked
11729 00:57:55.975408 /lava-12571137/1/../bin/lava-test-case
11730 00:57:56.013769 <8>[ 52.086510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11731 00:57:56.014536 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11733 00:57:57.072202 /lava-12571137/1/../bin/lava-test-case
11734 00:57:57.106204 <8>[ 53.179797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11735 00:57:57.106569 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11737 00:57:57.129165 /lava-12571137/1/../bin/lava-test-case
11738 00:57:57.162760 <8>[ 53.236291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11739 00:57:57.163103 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11741 00:57:57.197880 /lava-12571137/1/../bin/lava-test-case
11742 00:57:57.229278 <8>[ 53.302868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11743 00:57:57.229563 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11745 00:57:57.264620 /lava-12571137/1/../bin/lava-test-case
11746 00:57:57.296026 <8>[ 53.369439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11747 00:57:57.296764 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11749 00:57:57.321217 /lava-12571137/1/../bin/lava-test-case
11750 00:57:57.355723 <8>[ 53.429082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11751 00:57:57.356417 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11753 00:57:57.407550 /lava-12571137/1/../bin/lava-test-case
11754 00:57:57.449035 <8>[ 53.522125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11755 00:57:57.449756 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11757 00:57:57.477256 /lava-12571137/1/../bin/lava-test-case
11758 00:57:57.509842 <8>[ 53.583338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11759 00:57:57.510131 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11761 00:57:58.563474 /lava-12571137/1/../bin/lava-test-case
11762 00:57:58.603692 <8>[ 54.677186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11763 00:57:58.604413 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11765 00:57:58.631173 /lava-12571137/1/../bin/lava-test-case
11766 00:57:58.669999 <8>[ 54.743526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11767 00:57:58.670711 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11769 00:57:59.731692 /lava-12571137/1/../bin/lava-test-case
11770 00:57:59.771466 <8>[ 55.845036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11771 00:57:59.772225 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11773 00:57:59.799920 /lava-12571137/1/../bin/lava-test-case
11774 00:57:59.838330 <8>[ 55.911631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11775 00:57:59.839247 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11777 00:58:00.901439 /lava-12571137/1/../bin/lava-test-case
11778 00:58:00.945940 <8>[ 57.019364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11779 00:58:00.946760 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11781 00:58:00.972449 /lava-12571137/1/../bin/lava-test-case
11782 00:58:01.012612 <8>[ 57.085860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11783 00:58:01.013431 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11785 00:58:02.072340 /lava-12571137/1/../bin/lava-test-case
11786 00:58:02.114019 <8>[ 58.187791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11787 00:58:02.114327 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11789 00:58:02.138507 /lava-12571137/1/../bin/lava-test-case
11790 00:58:02.173299 <8>[ 58.247125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11791 00:58:02.173606 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11793 00:58:02.211229 /lava-12571137/1/../bin/lava-test-case
11794 00:58:02.246364 <8>[ 58.320220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11795 00:58:02.246668 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11797 00:58:02.282006 /lava-12571137/1/../bin/lava-test-case
11798 00:58:02.312276 <8>[ 58.386223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11799 00:58:02.312594 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11801 00:58:02.334804 /lava-12571137/1/../bin/lava-test-case
11802 00:58:02.366424 <8>[ 58.440489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11803 00:58:02.366737 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11805 00:58:02.413652 /lava-12571137/1/../bin/lava-test-case
11806 00:58:02.452782 <8>[ 58.526549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11807 00:58:02.453198 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11809 00:58:02.475852 /lava-12571137/1/../bin/lava-test-case
11810 00:58:02.508646 <8>[ 58.582599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11811 00:58:02.508987 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11813 00:58:02.551500 /lava-12571137/1/../bin/lava-test-case
11814 00:58:02.591976 <8>[ 58.665713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11815 00:58:02.592747 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11817 00:58:02.622273 /lava-12571137/1/../bin/lava-test-case
11818 00:58:02.664493 <8>[ 58.738346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11819 00:58:02.665316 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11821 00:58:02.714305 /lava-12571137/1/../bin/lava-test-case
11822 00:58:02.754588 <8>[ 58.827741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11823 00:58:02.755418 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11825 00:58:02.770654 + <8>[ 58.847376] <LAVA_SIGNAL_ENDRUN 1_bootrr 12571137_1.6.2.3.5>
11826 00:58:02.771490 Received signal: <ENDRUN> 1_bootrr 12571137_1.6.2.3.5
11827 00:58:02.771892 Ending use of test pattern.
11828 00:58:02.772214 Ending test lava.1_bootrr (12571137_1.6.2.3.5), duration 29.66
11830 00:58:02.773739 set +x
11831 00:58:02.779475 <LAVA_TEST_RUNNER EXIT>
11832 00:58:02.780151 ok: lava_test_shell seems to have completed
11833 00:58:02.785148 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11834 00:58:02.785871 end: 4.1 lava-test-shell (duration 00:00:30) [common]
11835 00:58:02.786313 end: 4 lava-test-retry (duration 00:00:30) [common]
11836 00:58:02.786819 start: 5 finalize (timeout 00:07:12) [common]
11837 00:58:02.787417 start: 5.1 power-off (timeout 00:00:30) [common]
11838 00:58:02.788302 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11839 00:58:02.907027 >> Command sent successfully.
11840 00:58:02.911047 Returned 0 in 0 seconds
11841 00:58:03.011934 end: 5.1 power-off (duration 00:00:00) [common]
11843 00:58:03.013775 start: 5.2 read-feedback (timeout 00:07:11) [common]
11844 00:58:03.015160 Listened to connection for namespace 'common' for up to 1s
11845 00:58:04.015478 Finalising connection for namespace 'common'
11846 00:58:04.015653 Disconnecting from shell: Finalise
11847 00:58:04.015732 / #
11848 00:58:04.116055 end: 5.2 read-feedback (duration 00:00:01) [common]
11849 00:58:04.116196 end: 5 finalize (duration 00:00:01) [common]
11850 00:58:04.116304 Cleaning after the job
11851 00:58:04.116404 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/ramdisk
11852 00:58:04.118856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/kernel
11853 00:58:04.131906 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/dtb
11854 00:58:04.132094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/nfsrootfs
11855 00:58:04.205005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571137/tftp-deploy-13ghr7el/modules
11856 00:58:04.212353 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571137
11857 00:58:04.593917 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571137
11858 00:58:04.594098 Job finished correctly