Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 12
- Errors: 1
- Kernel Errors: 32
- Boot result: PASS
1 00:59:02.832832 lava-dispatcher, installed at version: 2023.10
2 00:59:02.833045 start: 0 validate
3 00:59:02.833175 Start time: 2024-01-19 00:59:02.833167+00:00 (UTC)
4 00:59:02.833287 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:59:02.833423 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:59:03.102204 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:59:03.102393 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:59:03.371929 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:59:03.372694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:59:03.644254 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:59:03.645121 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:59:03.913728 validate duration: 1.08
14 00:59:03.914010 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:59:03.914105 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:59:03.914192 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:59:03.914317 Not decompressing ramdisk as can be used compressed.
18 00:59:03.914400 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 00:59:03.914467 saving as /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/ramdisk/rootfs.cpio.gz
20 00:59:03.914534 total size: 34390042 (32 MB)
21 00:59:03.915664 progress 0 % (0 MB)
22 00:59:03.925147 progress 5 % (1 MB)
23 00:59:03.934296 progress 10 % (3 MB)
24 00:59:03.943664 progress 15 % (4 MB)
25 00:59:03.952293 progress 20 % (6 MB)
26 00:59:03.960998 progress 25 % (8 MB)
27 00:59:03.969690 progress 30 % (9 MB)
28 00:59:03.978404 progress 35 % (11 MB)
29 00:59:03.987012 progress 40 % (13 MB)
30 00:59:03.995821 progress 45 % (14 MB)
31 00:59:04.004637 progress 50 % (16 MB)
32 00:59:04.013713 progress 55 % (18 MB)
33 00:59:04.022512 progress 60 % (19 MB)
34 00:59:04.031431 progress 65 % (21 MB)
35 00:59:04.040314 progress 70 % (22 MB)
36 00:59:04.049244 progress 75 % (24 MB)
37 00:59:04.058093 progress 80 % (26 MB)
38 00:59:04.067177 progress 85 % (27 MB)
39 00:59:04.075758 progress 90 % (29 MB)
40 00:59:04.084342 progress 95 % (31 MB)
41 00:59:04.092908 progress 100 % (32 MB)
42 00:59:04.093103 32 MB downloaded in 0.18 s (183.67 MB/s)
43 00:59:04.093277 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:59:04.093551 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:59:04.093654 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:59:04.093754 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:59:04.093907 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:59:04.093985 saving as /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/kernel/Image
50 00:59:04.094084 total size: 51532288 (49 MB)
51 00:59:04.094182 No compression specified
52 00:59:04.095863 progress 0 % (0 MB)
53 00:59:04.109280 progress 5 % (2 MB)
54 00:59:04.122755 progress 10 % (4 MB)
55 00:59:04.135789 progress 15 % (7 MB)
56 00:59:04.149096 progress 20 % (9 MB)
57 00:59:04.162488 progress 25 % (12 MB)
58 00:59:04.175649 progress 30 % (14 MB)
59 00:59:04.188897 progress 35 % (17 MB)
60 00:59:04.202143 progress 40 % (19 MB)
61 00:59:04.215606 progress 45 % (22 MB)
62 00:59:04.229057 progress 50 % (24 MB)
63 00:59:04.242254 progress 55 % (27 MB)
64 00:59:04.255548 progress 60 % (29 MB)
65 00:59:04.269116 progress 65 % (31 MB)
66 00:59:04.282238 progress 70 % (34 MB)
67 00:59:04.295358 progress 75 % (36 MB)
68 00:59:04.308461 progress 80 % (39 MB)
69 00:59:04.321836 progress 85 % (41 MB)
70 00:59:04.335133 progress 90 % (44 MB)
71 00:59:04.348212 progress 95 % (46 MB)
72 00:59:04.360852 progress 100 % (49 MB)
73 00:59:04.361066 49 MB downloaded in 0.27 s (184.08 MB/s)
74 00:59:04.361233 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:59:04.361577 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:59:04.361738 start: 1.3 download-retry (timeout 00:10:00) [common]
78 00:59:04.361939 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 00:59:04.362094 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:59:04.362192 saving as /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/dtb/mt8192-asurada-spherion-r0.dtb
81 00:59:04.362291 total size: 47278 (0 MB)
82 00:59:04.362389 No compression specified
83 00:59:04.364050 progress 69 % (0 MB)
84 00:59:04.364353 progress 100 % (0 MB)
85 00:59:04.364543 0 MB downloaded in 0.00 s (20.04 MB/s)
86 00:59:04.364690 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:59:04.364981 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:59:04.365080 start: 1.4 download-retry (timeout 00:10:00) [common]
90 00:59:04.365178 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 00:59:04.365311 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:59:04.365407 saving as /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/modules/modules.tar
93 00:59:04.365504 total size: 8625444 (8 MB)
94 00:59:04.365602 Using unxz to decompress xz
95 00:59:04.370104 progress 0 % (0 MB)
96 00:59:04.390760 progress 5 % (0 MB)
97 00:59:04.413939 progress 10 % (0 MB)
98 00:59:04.437055 progress 15 % (1 MB)
99 00:59:04.460070 progress 20 % (1 MB)
100 00:59:04.483645 progress 25 % (2 MB)
101 00:59:04.509251 progress 30 % (2 MB)
102 00:59:04.535378 progress 35 % (2 MB)
103 00:59:04.558514 progress 40 % (3 MB)
104 00:59:04.582370 progress 45 % (3 MB)
105 00:59:04.607181 progress 50 % (4 MB)
106 00:59:04.631443 progress 55 % (4 MB)
107 00:59:04.655901 progress 60 % (4 MB)
108 00:59:04.682953 progress 65 % (5 MB)
109 00:59:04.707360 progress 70 % (5 MB)
110 00:59:04.730646 progress 75 % (6 MB)
111 00:59:04.757366 progress 80 % (6 MB)
112 00:59:04.783327 progress 85 % (7 MB)
113 00:59:04.808805 progress 90 % (7 MB)
114 00:59:04.841197 progress 95 % (7 MB)
115 00:59:04.870185 progress 100 % (8 MB)
116 00:59:04.875099 8 MB downloaded in 0.51 s (16.14 MB/s)
117 00:59:04.875337 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:59:04.875595 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:59:04.875687 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:59:04.875781 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:59:04.875862 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:59:04.875952 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:59:04.876175 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst
125 00:59:04.876306 makedir: /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin
126 00:59:04.876414 makedir: /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/tests
127 00:59:04.876515 makedir: /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/results
128 00:59:04.876632 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-add-keys
129 00:59:04.876815 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-add-sources
130 00:59:04.876948 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-background-process-start
131 00:59:04.877075 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-background-process-stop
132 00:59:04.877200 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-common-functions
133 00:59:04.877324 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-echo-ipv4
134 00:59:04.877448 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-install-packages
135 00:59:04.877570 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-installed-packages
136 00:59:04.877692 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-os-build
137 00:59:04.877816 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-probe-channel
138 00:59:04.877940 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-probe-ip
139 00:59:04.878062 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-target-ip
140 00:59:04.878185 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-target-mac
141 00:59:04.878307 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-target-storage
142 00:59:04.878433 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-case
143 00:59:04.878560 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-event
144 00:59:04.878684 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-feedback
145 00:59:04.878807 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-raise
146 00:59:04.878930 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-reference
147 00:59:04.879053 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-runner
148 00:59:04.879176 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-set
149 00:59:04.879304 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-test-shell
150 00:59:04.879430 Updating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-install-packages (oe)
151 00:59:04.879580 Updating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/bin/lava-installed-packages (oe)
152 00:59:04.879718 Creating /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/environment
153 00:59:04.879830 LAVA metadata
154 00:59:04.879904 - LAVA_JOB_ID=12571112
155 00:59:04.879970 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:59:04.880068 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:59:04.880133 skipped lava-vland-overlay
158 00:59:04.880205 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:59:04.880282 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:59:04.880346 skipped lava-multinode-overlay
161 00:59:04.880418 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:59:04.880500 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:59:04.880574 Loading test definitions
164 00:59:04.880663 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:59:04.880783 Using /lava-12571112 at stage 0
166 00:59:04.881085 uuid=12571112_1.5.2.3.1 testdef=None
167 00:59:04.881171 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:59:04.881255 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:59:04.881790 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:59:04.882007 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:59:04.882600 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:59:04.882824 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:59:04.883681 runner path: /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/0/tests/0_cros-ec test_uuid 12571112_1.5.2.3.1
176 00:59:04.883832 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:59:04.884037 Creating lava-test-runner.conf files
179 00:59:04.884098 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571112/lava-overlay-wh9d9jst/lava-12571112/0 for stage 0
180 00:59:04.884183 - 0_cros-ec
181 00:59:04.884279 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:59:04.884362 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:59:04.891034 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:59:04.891139 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:59:04.891223 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:59:04.891307 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:59:04.891396 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:59:05.869118 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:59:05.869522 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:59:05.869636 extracting modules file /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571112/extract-overlay-ramdisk-v16sodqb/ramdisk
191 00:59:06.094642 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:59:06.094810 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:59:06.094906 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571112/compress-overlay-57ju8_ty/overlay-1.5.2.4.tar.gz to ramdisk
194 00:59:06.094977 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571112/compress-overlay-57ju8_ty/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571112/extract-overlay-ramdisk-v16sodqb/ramdisk
195 00:59:06.101459 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:59:06.101569 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:59:06.101656 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:59:06.101740 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:59:06.101814 Building ramdisk /var/lib/lava/dispatcher/tmp/12571112/extract-overlay-ramdisk-v16sodqb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571112/extract-overlay-ramdisk-v16sodqb/ramdisk
200 00:59:06.887739 >> 271082 blocks
201 00:59:11.553532 rename /var/lib/lava/dispatcher/tmp/12571112/extract-overlay-ramdisk-v16sodqb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/ramdisk/ramdisk.cpio.gz
202 00:59:11.553997 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:59:11.554119 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 00:59:11.554226 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 00:59:11.554335 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/kernel/Image'
206 00:59:23.872092 Returned 0 in 12 seconds
207 00:59:23.973122 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/kernel/image.itb
208 00:59:24.713399 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:59:24.713864 output: Created: Fri Jan 19 00:59:24 2024
210 00:59:24.713960 output: Image 0 (kernel-1)
211 00:59:24.714027 output: Description:
212 00:59:24.714087 output: Created: Fri Jan 19 00:59:24 2024
213 00:59:24.714147 output: Type: Kernel Image
214 00:59:24.714204 output: Compression: lzma compressed
215 00:59:24.714263 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
216 00:59:24.714321 output: Architecture: AArch64
217 00:59:24.714377 output: OS: Linux
218 00:59:24.714434 output: Load Address: 0x00000000
219 00:59:24.714492 output: Entry Point: 0x00000000
220 00:59:24.714549 output: Hash algo: crc32
221 00:59:24.714607 output: Hash value: a52aa383
222 00:59:24.714659 output: Image 1 (fdt-1)
223 00:59:24.714712 output: Description: mt8192-asurada-spherion-r0
224 00:59:24.714764 output: Created: Fri Jan 19 00:59:24 2024
225 00:59:24.714815 output: Type: Flat Device Tree
226 00:59:24.714867 output: Compression: uncompressed
227 00:59:24.714918 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 00:59:24.714970 output: Architecture: AArch64
229 00:59:24.715022 output: Hash algo: crc32
230 00:59:24.715073 output: Hash value: cc4352de
231 00:59:24.715124 output: Image 2 (ramdisk-1)
232 00:59:24.715175 output: Description: unavailable
233 00:59:24.715226 output: Created: Fri Jan 19 00:59:24 2024
234 00:59:24.715277 output: Type: RAMDisk Image
235 00:59:24.715328 output: Compression: Unknown Compression
236 00:59:24.715378 output: Data Size: 47532431 Bytes = 46418.39 KiB = 45.33 MiB
237 00:59:24.715431 output: Architecture: AArch64
238 00:59:24.715482 output: OS: Linux
239 00:59:24.715532 output: Load Address: unavailable
240 00:59:24.715583 output: Entry Point: unavailable
241 00:59:24.715634 output: Hash algo: crc32
242 00:59:24.715685 output: Hash value: b3a0a7d5
243 00:59:24.715737 output: Default Configuration: 'conf-1'
244 00:59:24.715787 output: Configuration 0 (conf-1)
245 00:59:24.715839 output: Description: mt8192-asurada-spherion-r0
246 00:59:24.715889 output: Kernel: kernel-1
247 00:59:24.715941 output: Init Ramdisk: ramdisk-1
248 00:59:24.715991 output: FDT: fdt-1
249 00:59:24.716042 output: Loadables: kernel-1
250 00:59:24.716093 output:
251 00:59:24.716284 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 00:59:24.716379 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 00:59:24.716485 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 00:59:24.716572 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 00:59:24.716648 No LXC device requested
256 00:59:24.716749 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:59:24.716843 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 00:59:24.716919 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:59:24.716990 Checking files for TFTP limit of 4294967296 bytes.
260 00:59:24.717478 end: 1 tftp-deploy (duration 00:00:21) [common]
261 00:59:24.717581 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:59:24.717670 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:59:24.717789 substitutions:
264 00:59:24.717853 - {DTB}: 12571112/tftp-deploy-nlza_r_g/dtb/mt8192-asurada-spherion-r0.dtb
265 00:59:24.717915 - {INITRD}: 12571112/tftp-deploy-nlza_r_g/ramdisk/ramdisk.cpio.gz
266 00:59:24.717972 - {KERNEL}: 12571112/tftp-deploy-nlza_r_g/kernel/Image
267 00:59:24.718027 - {LAVA_MAC}: None
268 00:59:24.718081 - {PRESEED_CONFIG}: None
269 00:59:24.718135 - {PRESEED_LOCAL}: None
270 00:59:24.718188 - {RAMDISK}: 12571112/tftp-deploy-nlza_r_g/ramdisk/ramdisk.cpio.gz
271 00:59:24.718240 - {ROOT_PART}: None
272 00:59:24.718293 - {ROOT}: None
273 00:59:24.718345 - {SERVER_IP}: 192.168.201.1
274 00:59:24.718397 - {TEE}: None
275 00:59:24.718449 Parsed boot commands:
276 00:59:24.718518 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:59:24.718773 Parsed boot commands: tftpboot 192.168.201.1 12571112/tftp-deploy-nlza_r_g/kernel/image.itb 12571112/tftp-deploy-nlza_r_g/kernel/cmdline
278 00:59:24.718862 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:59:24.718946 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:59:24.719040 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:59:24.719123 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:59:24.719193 Not connected, no need to disconnect.
283 00:59:24.719267 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:59:24.719344 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:59:24.719406 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 00:59:24.723461 Setting prompt string to ['lava-test: # ']
287 00:59:24.723834 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:59:24.723960 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:59:24.724087 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:59:24.724204 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:59:24.724438 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 00:59:29.874074 >> Command sent successfully.
293 00:59:29.885592 Returned 0 in 5 seconds
294 00:59:29.987073 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 00:59:29.988596 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 00:59:29.989213 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 00:59:29.989706 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:59:29.990092 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:59:29.990465 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:59:29.991819 [Enter `^Ec?' for help]
302 00:59:30.159718
303 00:59:30.160296
304 00:59:30.160780 F0: 102B 0000
305 00:59:30.161189
306 00:59:30.161667 F3: 1001 0000 [0200]
307 00:59:30.162319
308 00:59:30.163178 F3: 1001 0000
309 00:59:30.163555
310 00:59:30.163888 F7: 102D 0000
311 00:59:30.164216
312 00:59:30.164566 F1: 0000 0000
313 00:59:30.166406
314 00:59:30.166923 V0: 0000 0000 [0001]
315 00:59:30.167310
316 00:59:30.167651 00: 0007 8000
317 00:59:30.167990
318 00:59:30.169975 01: 0000 0000
319 00:59:30.170446
320 00:59:30.170844 BP: 0C00 0209 [0000]
321 00:59:30.171190
322 00:59:30.173516 G0: 1182 0000
323 00:59:30.173986
324 00:59:30.174364 EC: 0000 0021 [4000]
325 00:59:30.174708
326 00:59:30.177216 S7: 0000 0000 [0000]
327 00:59:30.177686
328 00:59:30.178057 CC: 0000 0000 [0001]
329 00:59:30.178401
330 00:59:30.180814 T0: 0000 0040 [010F]
331 00:59:30.181292
332 00:59:30.181664 Jump to BL
333 00:59:30.182011
334 00:59:30.206419
335 00:59:30.207315
336 00:59:30.207716
337 00:59:30.213799 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 00:59:30.216948 ARM64: Exception handlers installed.
339 00:59:30.220653 ARM64: Testing exception
340 00:59:30.223699 ARM64: Done test exception
341 00:59:30.230230 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 00:59:30.239661 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 00:59:30.246880 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 00:59:30.257703 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 00:59:30.264201 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 00:59:30.273810 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 00:59:30.284967 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 00:59:30.291417 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 00:59:30.308944 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 00:59:30.312291 WDT: Last reset was cold boot
351 00:59:30.315257 SPI1(PAD0) initialized at 2873684 Hz
352 00:59:30.319329 SPI5(PAD0) initialized at 992727 Hz
353 00:59:30.322360 VBOOT: Loading verstage.
354 00:59:30.329315 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 00:59:30.332185 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 00:59:30.335692 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 00:59:30.338937 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 00:59:30.346257 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 00:59:30.353048 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 00:59:30.363879 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 00:59:30.364446
362 00:59:30.364890
363 00:59:30.374521 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 00:59:30.377426 ARM64: Exception handlers installed.
365 00:59:30.380299 ARM64: Testing exception
366 00:59:30.380866 ARM64: Done test exception
367 00:59:30.387000 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 00:59:30.390446 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 00:59:30.404873 Probing TPM: . done!
370 00:59:30.405516 TPM ready after 0 ms
371 00:59:30.411406 Connected to device vid:did:rid of 1ae0:0028:00
372 00:59:30.418044 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 00:59:30.421072 Initialized TPM device CR50 revision 0
374 00:59:30.472007 tlcl_send_startup: Startup return code is 0
375 00:59:30.472455 TPM: setup succeeded
376 00:59:30.483674 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 00:59:30.493214 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:59:30.503078 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 00:59:30.512525 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 00:59:30.515993 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 00:59:30.518713 in-header: 03 07 00 00 08 00 00 00
382 00:59:30.521594 in-data: aa e4 47 04 13 02 00 00
383 00:59:30.525008 Chrome EC: UHEPI supported
384 00:59:30.531708 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 00:59:30.534721 in-header: 03 9d 00 00 08 00 00 00
386 00:59:30.538364 in-data: 10 20 20 08 00 00 00 00
387 00:59:30.538825 Phase 1
388 00:59:30.541599 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 00:59:30.548167 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 00:59:30.555100 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 00:59:30.558483 Recovery requested (1009000e)
392 00:59:30.564683 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:59:30.570866 tlcl_extend: response is 0
394 00:59:30.578629 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:59:30.583822 tlcl_extend: response is 0
396 00:59:30.590774 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:59:30.613111 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 00:59:30.619790 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:59:30.620366
400 00:59:30.620771
401 00:59:30.629527 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:59:30.633423 ARM64: Exception handlers installed.
403 00:59:30.633995 ARM64: Testing exception
404 00:59:30.636201 ARM64: Done test exception
405 00:59:30.657864 pmic_efuse_setting: Set efuses in 11 msecs
406 00:59:30.661040 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:59:30.667830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:59:30.670819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:59:30.674139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:59:30.681543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:59:30.684597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:59:30.692362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:59:30.696328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:59:30.698870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:59:30.706189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:59:30.708685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:59:30.715993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:59:30.719735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:59:30.722989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:59:30.729990 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:59:30.735440 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:59:30.742274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:59:30.745560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:59:30.753942 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:59:30.756813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:59:30.764210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:59:30.770977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:59:30.773428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:59:30.780485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:59:30.786715 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:59:30.789928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:59:30.796743 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:59:30.799877 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:59:30.806978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:59:30.810870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:59:30.817257 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:59:30.821095 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:59:30.826589 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:59:30.831439 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:59:30.837168 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:59:30.839965 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:59:30.846874 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:59:30.850284 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:59:30.857515 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:59:30.860512 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:59:30.864702 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:59:30.870118 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:59:30.873622 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:59:30.877240 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:59:30.883761 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:59:30.886453 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:59:30.890786 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:59:30.893415 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:59:30.900249 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:59:30.903948 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:59:30.907250 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:59:30.910310 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:59:30.920025 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 00:59:30.928438 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:59:30.933700 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:59:30.940823 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:59:30.950717 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:59:30.953413 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:59:30.957426 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:59:30.963811 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:59:30.970950 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x10
467 00:59:30.977588 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:59:30.981003 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 00:59:30.984843 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:59:30.994309 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 00:59:31.004508 [RTC]rtc_get_frequency_meter,154: input=23, output=950
472 00:59:31.013718 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 00:59:31.022980 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 00:59:31.032359 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 00:59:31.041522 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 00:59:31.051856 [RTC]rtc_get_frequency_meter,154: input=17, output=811
477 00:59:31.054802 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 00:59:31.062156 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 00:59:31.065610 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 00:59:31.068593 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 00:59:31.075648 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 00:59:31.078525 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 00:59:31.081576 ADC[4]: Raw value=669695 ID=5
484 00:59:31.082141 ADC[3]: Raw value=212549 ID=1
485 00:59:31.085190 RAM Code: 0x51
486 00:59:31.088367 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 00:59:31.094828 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 00:59:31.102012 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 00:59:31.108688 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 00:59:31.112258 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 00:59:31.115643 in-header: 03 07 00 00 08 00 00 00
492 00:59:31.118688 in-data: aa e4 47 04 13 02 00 00
493 00:59:31.122018 Chrome EC: UHEPI supported
494 00:59:31.129249 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 00:59:31.132883 in-header: 03 d5 00 00 08 00 00 00
496 00:59:31.135163 in-data: 98 20 60 08 00 00 00 00
497 00:59:31.138037 MRC: failed to locate region type 0.
498 00:59:31.145979 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 00:59:31.146568 DRAM-K: Running full calibration
500 00:59:31.151703 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 00:59:31.155014 header.status = 0x0
502 00:59:31.158293 header.version = 0x6 (expected: 0x6)
503 00:59:31.161392 header.size = 0xd00 (expected: 0xd00)
504 00:59:31.161879 header.flags = 0x0
505 00:59:31.167930 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 00:59:31.187107 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 00:59:31.192986 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 00:59:31.196431 dram_init: ddr_geometry: 0
509 00:59:31.199850 [EMI] MDL number = 0
510 00:59:31.200430 [EMI] Get MDL freq = 0
511 00:59:31.203338 dram_init: ddr_type: 0
512 00:59:31.203922 is_discrete_lpddr4: 1
513 00:59:31.206943 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 00:59:31.207716
515 00:59:31.208127
516 00:59:31.209985 [Bian_co] ETT version 0.0.0.1
517 00:59:31.213699 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 00:59:31.214328
519 00:59:31.220538 dramc_set_vcore_voltage set vcore to 650000
520 00:59:31.221179 Read voltage for 800, 4
521 00:59:31.223681 Vio18 = 0
522 00:59:31.224152 Vcore = 650000
523 00:59:31.224530 Vdram = 0
524 00:59:31.227179 Vddq = 0
525 00:59:31.227753 Vmddr = 0
526 00:59:31.231615 dram_init: config_dvfs: 1
527 00:59:31.233889 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 00:59:31.240211 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 00:59:31.243676 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 00:59:31.247471 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 00:59:31.250286 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 00:59:31.253632 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 00:59:31.257230 MEM_TYPE=3, freq_sel=18
534 00:59:31.260257 sv_algorithm_assistance_LP4_1600
535 00:59:31.264055 ============ PULL DRAM RESETB DOWN ============
536 00:59:31.266962 ========== PULL DRAM RESETB DOWN end =========
537 00:59:31.273684 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 00:59:31.277484 ===================================
539 00:59:31.277956 LPDDR4 DRAM CONFIGURATION
540 00:59:31.280574 ===================================
541 00:59:31.283891 EX_ROW_EN[0] = 0x0
542 00:59:31.286643 EX_ROW_EN[1] = 0x0
543 00:59:31.287231 LP4Y_EN = 0x0
544 00:59:31.290422 WORK_FSP = 0x0
545 00:59:31.290960 WL = 0x2
546 00:59:31.293971 RL = 0x2
547 00:59:31.294447 BL = 0x2
548 00:59:31.297550 RPST = 0x0
549 00:59:31.298020 RD_PRE = 0x0
550 00:59:31.300017 WR_PRE = 0x1
551 00:59:31.300638 WR_PST = 0x0
552 00:59:31.303461 DBI_WR = 0x0
553 00:59:31.304168 DBI_RD = 0x0
554 00:59:31.307416 OTF = 0x1
555 00:59:31.310281 ===================================
556 00:59:31.313869 ===================================
557 00:59:31.314345 ANA top config
558 00:59:31.317310 ===================================
559 00:59:31.320293 DLL_ASYNC_EN = 0
560 00:59:31.324509 ALL_SLAVE_EN = 1
561 00:59:31.325141 NEW_RANK_MODE = 1
562 00:59:31.326380 DLL_IDLE_MODE = 1
563 00:59:31.330012 LP45_APHY_COMB_EN = 1
564 00:59:31.333343 TX_ODT_DIS = 1
565 00:59:31.336975 NEW_8X_MODE = 1
566 00:59:31.340845 ===================================
567 00:59:31.341324 ===================================
568 00:59:31.343963 data_rate = 1600
569 00:59:31.347149 CKR = 1
570 00:59:31.350454 DQ_P2S_RATIO = 8
571 00:59:31.353269 ===================================
572 00:59:31.356901 CA_P2S_RATIO = 8
573 00:59:31.360923 DQ_CA_OPEN = 0
574 00:59:31.364439 DQ_SEMI_OPEN = 0
575 00:59:31.365066 CA_SEMI_OPEN = 0
576 00:59:31.367333 CA_FULL_RATE = 0
577 00:59:31.370286 DQ_CKDIV4_EN = 1
578 00:59:31.373414 CA_CKDIV4_EN = 1
579 00:59:31.377290 CA_PREDIV_EN = 0
580 00:59:31.377865 PH8_DLY = 0
581 00:59:31.380272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 00:59:31.383423 DQ_AAMCK_DIV = 4
583 00:59:31.386659 CA_AAMCK_DIV = 4
584 00:59:31.389997 CA_ADMCK_DIV = 4
585 00:59:31.393689 DQ_TRACK_CA_EN = 0
586 00:59:31.394430 CA_PICK = 800
587 00:59:31.396784 CA_MCKIO = 800
588 00:59:31.400182 MCKIO_SEMI = 0
589 00:59:31.403409 PLL_FREQ = 3068
590 00:59:31.407126 DQ_UI_PI_RATIO = 32
591 00:59:31.410013 CA_UI_PI_RATIO = 0
592 00:59:31.413914 ===================================
593 00:59:31.416869 ===================================
594 00:59:31.417443 memory_type:LPDDR4
595 00:59:31.420110 GP_NUM : 10
596 00:59:31.423449 SRAM_EN : 1
597 00:59:31.424023 MD32_EN : 0
598 00:59:31.426958 ===================================
599 00:59:31.430685 [ANA_INIT] >>>>>>>>>>>>>>
600 00:59:31.433597 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 00:59:31.436767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 00:59:31.440900 ===================================
603 00:59:31.443809 data_rate = 1600,PCW = 0X7600
604 00:59:31.448226 ===================================
605 00:59:31.449997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 00:59:31.453460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 00:59:31.460471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 00:59:31.463300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 00:59:31.466770 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 00:59:31.470014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 00:59:31.473686 [ANA_INIT] flow start
612 00:59:31.476771 [ANA_INIT] PLL >>>>>>>>
613 00:59:31.477245 [ANA_INIT] PLL <<<<<<<<
614 00:59:31.480473 [ANA_INIT] MIDPI >>>>>>>>
615 00:59:31.483832 [ANA_INIT] MIDPI <<<<<<<<
616 00:59:31.487197 [ANA_INIT] DLL >>>>>>>>
617 00:59:31.487826 [ANA_INIT] flow end
618 00:59:31.489849 ============ LP4 DIFF to SE enter ============
619 00:59:31.496701 ============ LP4 DIFF to SE exit ============
620 00:59:31.497270 [ANA_INIT] <<<<<<<<<<<<<
621 00:59:31.500201 [Flow] Enable top DCM control >>>>>
622 00:59:31.503287 [Flow] Enable top DCM control <<<<<
623 00:59:31.506738 Enable DLL master slave shuffle
624 00:59:31.513055 ==============================================================
625 00:59:31.513571 Gating Mode config
626 00:59:31.519744 ==============================================================
627 00:59:31.523066 Config description:
628 00:59:31.534558 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 00:59:31.536780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 00:59:31.543722 SELPH_MODE 0: By rank 1: By Phase
631 00:59:31.550289 ==============================================================
632 00:59:31.550862 GAT_TRACK_EN = 1
633 00:59:31.553131 RX_GATING_MODE = 2
634 00:59:31.556672 RX_GATING_TRACK_MODE = 2
635 00:59:31.559998 SELPH_MODE = 1
636 00:59:31.563600 PICG_EARLY_EN = 1
637 00:59:31.567268 VALID_LAT_VALUE = 1
638 00:59:31.573669 ==============================================================
639 00:59:31.576649 Enter into Gating configuration >>>>
640 00:59:31.579912 Exit from Gating configuration <<<<
641 00:59:31.584164 Enter into DVFS_PRE_config >>>>>
642 00:59:31.594173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 00:59:31.596478 Exit from DVFS_PRE_config <<<<<
644 00:59:31.599987 Enter into PICG configuration >>>>
645 00:59:31.603353 Exit from PICG configuration <<<<
646 00:59:31.607009 [RX_INPUT] configuration >>>>>
647 00:59:31.607586 [RX_INPUT] configuration <<<<<
648 00:59:31.613317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 00:59:31.619842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 00:59:31.623650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 00:59:31.630638 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 00:59:31.636430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 00:59:31.642972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 00:59:31.646588 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 00:59:31.649833 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 00:59:31.656306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 00:59:31.661136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 00:59:31.663015 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 00:59:31.669606 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 00:59:31.672878 ===================================
661 00:59:31.673453 LPDDR4 DRAM CONFIGURATION
662 00:59:31.676493 ===================================
663 00:59:31.679375 EX_ROW_EN[0] = 0x0
664 00:59:31.679855 EX_ROW_EN[1] = 0x0
665 00:59:31.682648 LP4Y_EN = 0x0
666 00:59:31.686258 WORK_FSP = 0x0
667 00:59:31.686835 WL = 0x2
668 00:59:31.689645 RL = 0x2
669 00:59:31.690220 BL = 0x2
670 00:59:31.693105 RPST = 0x0
671 00:59:31.693585 RD_PRE = 0x0
672 00:59:31.696073 WR_PRE = 0x1
673 00:59:31.696822 WR_PST = 0x0
674 00:59:31.699825 DBI_WR = 0x0
675 00:59:31.700409 DBI_RD = 0x0
676 00:59:31.703239 OTF = 0x1
677 00:59:31.706820 ===================================
678 00:59:31.709664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 00:59:31.712443 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 00:59:31.716372 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 00:59:31.719837 ===================================
682 00:59:31.722622 LPDDR4 DRAM CONFIGURATION
683 00:59:31.726890 ===================================
684 00:59:31.730526 EX_ROW_EN[0] = 0x10
685 00:59:31.731113 EX_ROW_EN[1] = 0x0
686 00:59:31.732582 LP4Y_EN = 0x0
687 00:59:31.733102 WORK_FSP = 0x0
688 00:59:31.736357 WL = 0x2
689 00:59:31.736979 RL = 0x2
690 00:59:31.740119 BL = 0x2
691 00:59:31.740618 RPST = 0x0
692 00:59:31.742665 RD_PRE = 0x0
693 00:59:31.743142 WR_PRE = 0x1
694 00:59:31.746797 WR_PST = 0x0
695 00:59:31.749750 DBI_WR = 0x0
696 00:59:31.750489 DBI_RD = 0x0
697 00:59:31.752899 OTF = 0x1
698 00:59:31.756387 ===================================
699 00:59:31.759542 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 00:59:31.764919 nWR fixed to 40
701 00:59:31.768764 [ModeRegInit_LP4] CH0 RK0
702 00:59:31.769341 [ModeRegInit_LP4] CH0 RK1
703 00:59:31.771835 [ModeRegInit_LP4] CH1 RK0
704 00:59:31.774975 [ModeRegInit_LP4] CH1 RK1
705 00:59:31.775547 match AC timing 12
706 00:59:31.781876 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 00:59:31.784985 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 00:59:31.788172 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 00:59:31.794677 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 00:59:31.797781 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 00:59:31.798260 [EMI DOE] emi_dcm 0
712 00:59:31.804302 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 00:59:31.804931 ==
714 00:59:31.807839 Dram Type= 6, Freq= 0, CH_0, rank 0
715 00:59:31.811494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 00:59:31.811977 ==
717 00:59:31.818906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 00:59:31.824096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 00:59:31.831949 [CA 0] Center 37 (7~68) winsize 62
720 00:59:31.835200 [CA 1] Center 37 (7~68) winsize 62
721 00:59:31.838621 [CA 2] Center 35 (5~66) winsize 62
722 00:59:31.842974 [CA 3] Center 35 (4~66) winsize 63
723 00:59:31.845204 [CA 4] Center 34 (4~65) winsize 62
724 00:59:31.848876 [CA 5] Center 34 (3~65) winsize 63
725 00:59:31.849449
726 00:59:31.851934 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 00:59:31.852515
728 00:59:31.855458 [CATrainingPosCal] consider 1 rank data
729 00:59:31.858503 u2DelayCellTimex100 = 270/100 ps
730 00:59:31.861379 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 00:59:31.868324 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 00:59:31.871450 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 00:59:31.875304 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 00:59:31.878864 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 00:59:31.881986 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
736 00:59:31.882573
737 00:59:31.885221 CA PerBit enable=1, Macro0, CA PI delay=34
738 00:59:31.885811
739 00:59:31.888437 [CBTSetCACLKResult] CA Dly = 34
740 00:59:31.888949 CS Dly: 5 (0~36)
741 00:59:31.891991 ==
742 00:59:31.892571 Dram Type= 6, Freq= 0, CH_0, rank 1
743 00:59:31.898061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 00:59:31.898542 ==
745 00:59:31.901856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 00:59:31.908982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 00:59:31.918278 [CA 0] Center 37 (7~68) winsize 62
748 00:59:31.921262 [CA 1] Center 37 (6~68) winsize 63
749 00:59:31.924940 [CA 2] Center 35 (5~66) winsize 62
750 00:59:31.927650 [CA 3] Center 35 (5~65) winsize 61
751 00:59:31.931398 [CA 4] Center 34 (3~65) winsize 63
752 00:59:31.934892 [CA 5] Center 34 (3~65) winsize 63
753 00:59:31.935376
754 00:59:31.937619 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 00:59:31.938158
756 00:59:31.941030 [CATrainingPosCal] consider 2 rank data
757 00:59:31.944791 u2DelayCellTimex100 = 270/100 ps
758 00:59:31.947672 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 00:59:31.952059 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 00:59:31.957732 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 00:59:31.960892 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
762 00:59:31.964598 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
763 00:59:31.968012 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
764 00:59:31.968593
765 00:59:31.970881 CA PerBit enable=1, Macro0, CA PI delay=34
766 00:59:31.971467
767 00:59:31.974505 [CBTSetCACLKResult] CA Dly = 34
768 00:59:31.975088 CS Dly: 5 (0~37)
769 00:59:31.975469
770 00:59:31.977525 ----->DramcWriteLeveling(PI) begin...
771 00:59:31.981212 ==
772 00:59:31.984171 Dram Type= 6, Freq= 0, CH_0, rank 0
773 00:59:31.987570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 00:59:31.988049 ==
775 00:59:31.991215 Write leveling (Byte 0): 30 => 30
776 00:59:31.994286 Write leveling (Byte 1): 30 => 30
777 00:59:31.997803 DramcWriteLeveling(PI) end<-----
778 00:59:31.998406
779 00:59:31.999071 ==
780 00:59:32.001505 Dram Type= 6, Freq= 0, CH_0, rank 0
781 00:59:32.004553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 00:59:32.005186 ==
783 00:59:32.007526 [Gating] SW mode calibration
784 00:59:32.014239 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 00:59:32.017555 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 00:59:32.024080 0 6 0 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
787 00:59:32.027749 0 6 4 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
788 00:59:32.030928 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:59:32.037480 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:59:32.040471 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:59:32.044391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:59:32.050541 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:59:32.054198 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:59:32.057493 0 7 0 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
795 00:59:32.064457 0 7 4 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
796 00:59:32.067452 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 00:59:32.070972 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 00:59:32.077388 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 00:59:32.081435 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 00:59:32.084304 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 00:59:32.091189 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 00:59:32.094330 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 00:59:32.097586 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
804 00:59:32.104394 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 00:59:32.107532 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 00:59:32.111399 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 00:59:32.117421 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 00:59:32.120383 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 00:59:32.124833 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 00:59:32.130355 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 00:59:32.135203 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 00:59:32.136942 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 00:59:32.141112 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 00:59:32.147275 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 00:59:32.151094 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 00:59:32.154229 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 00:59:32.161089 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 00:59:32.164446 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
819 00:59:32.166969 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
820 00:59:32.170587 Total UI for P1: 0, mck2ui 16
821 00:59:32.174387 best dqsien dly found for B1: ( 0, 10, 2)
822 00:59:32.181398 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 00:59:32.181987 Total UI for P1: 0, mck2ui 16
824 00:59:32.187349 best dqsien dly found for B0: ( 0, 10, 2)
825 00:59:32.190731 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
826 00:59:32.193644 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
827 00:59:32.194229
828 00:59:32.197374 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 00:59:32.200653 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
830 00:59:32.204787 [Gating] SW calibration Done
831 00:59:32.205370 ==
832 00:59:32.208076 Dram Type= 6, Freq= 0, CH_0, rank 0
833 00:59:32.211802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 00:59:32.212506 ==
835 00:59:32.213028 RX Vref Scan: 0
836 00:59:32.215432
837 00:59:32.216011 RX Vref 0 -> 0, step: 1
838 00:59:32.216391
839 00:59:32.218918 RX Delay -130 -> 252, step: 16
840 00:59:32.221254 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
841 00:59:32.224245 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 00:59:32.231787 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
843 00:59:32.234635 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
844 00:59:32.237973 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 00:59:32.241506 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
846 00:59:32.244171 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
847 00:59:32.251211 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
848 00:59:32.255583 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
849 00:59:32.258075 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
850 00:59:32.261356 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
851 00:59:32.265100 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 00:59:32.271308 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
853 00:59:32.274511 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
854 00:59:32.278132 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 00:59:32.281244 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
856 00:59:32.281827 ==
857 00:59:32.284561 Dram Type= 6, Freq= 0, CH_0, rank 0
858 00:59:32.292769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 00:59:32.293363 ==
860 00:59:32.293750 DQS Delay:
861 00:59:32.294108 DQS0 = 0, DQS1 = 0
862 00:59:32.294808 DQM Delay:
863 00:59:32.295178 DQM0 = 84, DQM1 = 75
864 00:59:32.297680 DQ Delay:
865 00:59:32.300842 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
866 00:59:32.301537 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
867 00:59:32.304265 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
868 00:59:32.311383 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
869 00:59:32.311974
870 00:59:32.312352
871 00:59:32.313007 ==
872 00:59:32.315391 Dram Type= 6, Freq= 0, CH_0, rank 0
873 00:59:32.317822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 00:59:32.318302 ==
875 00:59:32.318684
876 00:59:32.319034
877 00:59:32.321047 TX Vref Scan disable
878 00:59:32.321520 == TX Byte 0 ==
879 00:59:32.327890 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
880 00:59:32.331709 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
881 00:59:32.332298 == TX Byte 1 ==
882 00:59:32.337746 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
883 00:59:32.341498 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
884 00:59:32.342082 ==
885 00:59:32.344386 Dram Type= 6, Freq= 0, CH_0, rank 0
886 00:59:32.348635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 00:59:32.349272 ==
888 00:59:32.361441 TX Vref=22, minBit 0, minWin=27, winSum=444
889 00:59:32.365211 TX Vref=24, minBit 0, minWin=27, winSum=447
890 00:59:32.368073 TX Vref=26, minBit 4, minWin=27, winSum=451
891 00:59:32.371780 TX Vref=28, minBit 2, minWin=28, winSum=457
892 00:59:32.375249 TX Vref=30, minBit 0, minWin=28, winSum=456
893 00:59:32.378468 TX Vref=32, minBit 0, minWin=27, winSum=452
894 00:59:32.385394 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
895 00:59:32.385981
896 00:59:32.388948 Final TX Range 1 Vref 28
897 00:59:32.389448
898 00:59:32.389826 ==
899 00:59:32.391752 Dram Type= 6, Freq= 0, CH_0, rank 0
900 00:59:32.394565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 00:59:32.395080 ==
902 00:59:32.395655
903 00:59:32.398020
904 00:59:32.398509 TX Vref Scan disable
905 00:59:32.401422 == TX Byte 0 ==
906 00:59:32.404695 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
907 00:59:32.408645 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
908 00:59:32.411683 == TX Byte 1 ==
909 00:59:32.414919 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 00:59:32.419008 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 00:59:32.421413
912 00:59:32.421885 [DATLAT]
913 00:59:32.422260 Freq=800, CH0 RK0
914 00:59:32.422613
915 00:59:32.424775 DATLAT Default: 0xa
916 00:59:32.425247 0, 0xFFFF, sum = 0
917 00:59:32.427863 1, 0xFFFF, sum = 0
918 00:59:32.428357 2, 0xFFFF, sum = 0
919 00:59:32.432123 3, 0xFFFF, sum = 0
920 00:59:32.432758 4, 0xFFFF, sum = 0
921 00:59:32.434759 5, 0xFFFF, sum = 0
922 00:59:32.435238 6, 0xFFFF, sum = 0
923 00:59:32.438188 7, 0xFFFF, sum = 0
924 00:59:32.438664 8, 0x0, sum = 1
925 00:59:32.441336 9, 0x0, sum = 2
926 00:59:32.441924 10, 0x0, sum = 3
927 00:59:32.444940 11, 0x0, sum = 4
928 00:59:32.445519 best_step = 9
929 00:59:32.445897
930 00:59:32.446248 ==
931 00:59:32.448055 Dram Type= 6, Freq= 0, CH_0, rank 0
932 00:59:32.454847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 00:59:32.455427 ==
934 00:59:32.455812 RX Vref Scan: 1
935 00:59:32.456164
936 00:59:32.457776 Set Vref Range= 32 -> 127
937 00:59:32.458385
938 00:59:32.461276 RX Vref 32 -> 127, step: 1
939 00:59:32.461746
940 00:59:32.462118 RX Delay -111 -> 252, step: 8
941 00:59:32.464761
942 00:59:32.465339 Set Vref, RX VrefLevel [Byte0]: 32
943 00:59:32.467753 [Byte1]: 32
944 00:59:32.472373
945 00:59:32.472985 Set Vref, RX VrefLevel [Byte0]: 33
946 00:59:32.476070 [Byte1]: 33
947 00:59:32.480282
948 00:59:32.480900 Set Vref, RX VrefLevel [Byte0]: 34
949 00:59:32.483401 [Byte1]: 34
950 00:59:32.487801
951 00:59:32.488384 Set Vref, RX VrefLevel [Byte0]: 35
952 00:59:32.491200 [Byte1]: 35
953 00:59:32.495332
954 00:59:32.495858 Set Vref, RX VrefLevel [Byte0]: 36
955 00:59:32.498454 [Byte1]: 36
956 00:59:32.503000
957 00:59:32.503469 Set Vref, RX VrefLevel [Byte0]: 37
958 00:59:32.506445 [Byte1]: 37
959 00:59:32.510859
960 00:59:32.511434 Set Vref, RX VrefLevel [Byte0]: 38
961 00:59:32.513312 [Byte1]: 38
962 00:59:32.518224
963 00:59:32.518818 Set Vref, RX VrefLevel [Byte0]: 39
964 00:59:32.521224 [Byte1]: 39
965 00:59:32.525685
966 00:59:32.526176 Set Vref, RX VrefLevel [Byte0]: 40
967 00:59:32.528876 [Byte1]: 40
968 00:59:32.533502
969 00:59:32.534074 Set Vref, RX VrefLevel [Byte0]: 41
970 00:59:32.536579 [Byte1]: 41
971 00:59:32.541251
972 00:59:32.541825 Set Vref, RX VrefLevel [Byte0]: 42
973 00:59:32.545976 [Byte1]: 42
974 00:59:32.548563
975 00:59:32.549108 Set Vref, RX VrefLevel [Byte0]: 43
976 00:59:32.552081 [Byte1]: 43
977 00:59:32.556516
978 00:59:32.557159 Set Vref, RX VrefLevel [Byte0]: 44
979 00:59:32.560207 [Byte1]: 44
980 00:59:32.564434
981 00:59:32.565112 Set Vref, RX VrefLevel [Byte0]: 45
982 00:59:32.568489 [Byte1]: 45
983 00:59:32.571461
984 00:59:32.572042 Set Vref, RX VrefLevel [Byte0]: 46
985 00:59:32.575130 [Byte1]: 46
986 00:59:32.581045
987 00:59:32.581517 Set Vref, RX VrefLevel [Byte0]: 47
988 00:59:32.582370 [Byte1]: 47
989 00:59:32.586709
990 00:59:32.587280 Set Vref, RX VrefLevel [Byte0]: 48
991 00:59:32.589711 [Byte1]: 48
992 00:59:32.594503
993 00:59:32.594972 Set Vref, RX VrefLevel [Byte0]: 49
994 00:59:32.598231 [Byte1]: 49
995 00:59:32.601661
996 00:59:32.602130 Set Vref, RX VrefLevel [Byte0]: 50
997 00:59:32.606492 [Byte1]: 50
998 00:59:32.609544
999 00:59:32.610011 Set Vref, RX VrefLevel [Byte0]: 51
1000 00:59:32.613826 [Byte1]: 51
1001 00:59:32.617840
1002 00:59:32.618305 Set Vref, RX VrefLevel [Byte0]: 52
1003 00:59:32.620569 [Byte1]: 52
1004 00:59:32.625147
1005 00:59:32.625719 Set Vref, RX VrefLevel [Byte0]: 53
1006 00:59:32.628146 [Byte1]: 53
1007 00:59:32.633099
1008 00:59:32.633673 Set Vref, RX VrefLevel [Byte0]: 54
1009 00:59:32.636189 [Byte1]: 54
1010 00:59:32.640316
1011 00:59:32.641004 Set Vref, RX VrefLevel [Byte0]: 55
1012 00:59:32.643822 [Byte1]: 55
1013 00:59:32.647760
1014 00:59:32.648336 Set Vref, RX VrefLevel [Byte0]: 56
1015 00:59:32.651412 [Byte1]: 56
1016 00:59:32.656219
1017 00:59:32.656848 Set Vref, RX VrefLevel [Byte0]: 57
1018 00:59:32.659484 [Byte1]: 57
1019 00:59:32.663409
1020 00:59:32.664019 Set Vref, RX VrefLevel [Byte0]: 58
1021 00:59:32.666840 [Byte1]: 58
1022 00:59:32.671350
1023 00:59:32.671920 Set Vref, RX VrefLevel [Byte0]: 59
1024 00:59:32.674787 [Byte1]: 59
1025 00:59:32.678775
1026 00:59:32.679341 Set Vref, RX VrefLevel [Byte0]: 60
1027 00:59:32.682462 [Byte1]: 60
1028 00:59:32.686370
1029 00:59:32.686830 Set Vref, RX VrefLevel [Byte0]: 61
1030 00:59:32.689702 [Byte1]: 61
1031 00:59:32.694212
1032 00:59:32.694731 Set Vref, RX VrefLevel [Byte0]: 62
1033 00:59:32.698543 [Byte1]: 62
1034 00:59:32.701526
1035 00:59:32.701985 Set Vref, RX VrefLevel [Byte0]: 63
1036 00:59:32.704892 [Byte1]: 63
1037 00:59:32.709258
1038 00:59:32.709821 Set Vref, RX VrefLevel [Byte0]: 64
1039 00:59:32.712776 [Byte1]: 64
1040 00:59:32.716700
1041 00:59:32.717309 Set Vref, RX VrefLevel [Byte0]: 65
1042 00:59:32.720016 [Byte1]: 65
1043 00:59:32.724940
1044 00:59:32.725496 Set Vref, RX VrefLevel [Byte0]: 66
1045 00:59:32.727613 [Byte1]: 66
1046 00:59:32.731944
1047 00:59:32.732506 Set Vref, RX VrefLevel [Byte0]: 67
1048 00:59:32.735680 [Byte1]: 67
1049 00:59:32.739782
1050 00:59:32.740351 Set Vref, RX VrefLevel [Byte0]: 68
1051 00:59:32.742956 [Byte1]: 68
1052 00:59:32.748258
1053 00:59:32.748756 Set Vref, RX VrefLevel [Byte0]: 69
1054 00:59:32.750822 [Byte1]: 69
1055 00:59:32.755759
1056 00:59:32.756328 Set Vref, RX VrefLevel [Byte0]: 70
1057 00:59:32.758403 [Byte1]: 70
1058 00:59:32.762519
1059 00:59:32.763088 Set Vref, RX VrefLevel [Byte0]: 71
1060 00:59:32.766018 [Byte1]: 71
1061 00:59:32.770457
1062 00:59:32.771019 Set Vref, RX VrefLevel [Byte0]: 72
1063 00:59:32.773477 [Byte1]: 72
1064 00:59:32.777895
1065 00:59:32.781502 Set Vref, RX VrefLevel [Byte0]: 73
1066 00:59:32.781971 [Byte1]: 73
1067 00:59:32.785522
1068 00:59:32.786085 Final RX Vref Byte 0 = 53 to rank0
1069 00:59:32.789663 Final RX Vref Byte 1 = 51 to rank0
1070 00:59:32.792689 Final RX Vref Byte 0 = 53 to rank1
1071 00:59:32.796451 Final RX Vref Byte 1 = 51 to rank1==
1072 00:59:32.798694 Dram Type= 6, Freq= 0, CH_0, rank 0
1073 00:59:32.805860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1074 00:59:32.806328 ==
1075 00:59:32.806697 DQS Delay:
1076 00:59:32.807039 DQS0 = 0, DQS1 = 0
1077 00:59:32.809090 DQM Delay:
1078 00:59:32.809551 DQM0 = 83, DQM1 = 73
1079 00:59:32.812029 DQ Delay:
1080 00:59:32.815631 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1081 00:59:32.816093 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1082 00:59:32.818864 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1083 00:59:32.825668 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1084 00:59:32.826218
1085 00:59:32.826583
1086 00:59:32.832441 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1087 00:59:32.836228 CH0 RK0: MR19=606, MR18=3C3C
1088 00:59:32.842854 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1089 00:59:32.843422
1090 00:59:32.845211 ----->DramcWriteLeveling(PI) begin...
1091 00:59:32.845677 ==
1092 00:59:32.848884 Dram Type= 6, Freq= 0, CH_0, rank 1
1093 00:59:32.852421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1094 00:59:32.853018 ==
1095 00:59:32.855819 Write leveling (Byte 0): 28 => 28
1096 00:59:32.859042 Write leveling (Byte 1): 28 => 28
1097 00:59:32.862450 DramcWriteLeveling(PI) end<-----
1098 00:59:32.863012
1099 00:59:32.863370 ==
1100 00:59:32.866138 Dram Type= 6, Freq= 0, CH_0, rank 1
1101 00:59:32.869079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1102 00:59:32.869645 ==
1103 00:59:32.872202 [Gating] SW mode calibration
1104 00:59:32.878743 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1105 00:59:32.885342 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1106 00:59:32.888679 0 6 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1107 00:59:32.892214 0 6 4 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
1108 00:59:32.899056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 00:59:32.902182 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 00:59:32.905212 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 00:59:32.912500 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 00:59:32.915828 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 00:59:32.918669 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 00:59:32.925719 0 7 0 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
1115 00:59:32.929264 0 7 4 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1116 00:59:32.931787 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 00:59:32.939050 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 00:59:32.942257 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 00:59:32.945836 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 00:59:32.952325 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 00:59:32.955271 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 00:59:32.958881 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1123 00:59:32.965339 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 00:59:32.968595 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 00:59:32.972352 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 00:59:32.979011 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 00:59:32.981851 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 00:59:32.985475 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 00:59:32.988552 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 00:59:32.995543 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 00:59:32.998128 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 00:59:33.001569 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 00:59:33.008303 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 00:59:33.011620 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 00:59:33.014717 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 00:59:33.021747 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 00:59:33.025065 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 00:59:33.028037 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1139 00:59:33.034716 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 00:59:33.038453 Total UI for P1: 0, mck2ui 16
1141 00:59:33.041563 best dqsien dly found for B0: ( 0, 10, 0)
1142 00:59:33.042136 Total UI for P1: 0, mck2ui 16
1143 00:59:33.048756 best dqsien dly found for B1: ( 0, 10, 0)
1144 00:59:33.052042 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1145 00:59:33.055035 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1146 00:59:33.055609
1147 00:59:33.058324 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1148 00:59:33.062041 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1149 00:59:33.065078 [Gating] SW calibration Done
1150 00:59:33.065648 ==
1151 00:59:33.068849 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 00:59:33.072135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1153 00:59:33.072746 ==
1154 00:59:33.075064 RX Vref Scan: 0
1155 00:59:33.075632
1156 00:59:33.076005 RX Vref 0 -> 0, step: 1
1157 00:59:33.076351
1158 00:59:33.078093 RX Delay -130 -> 252, step: 16
1159 00:59:33.082317 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1160 00:59:33.125668 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1161 00:59:33.126254 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1162 00:59:33.127008 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1163 00:59:33.127400 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1164 00:59:33.127801 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1165 00:59:33.128141 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1166 00:59:33.128464 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1167 00:59:33.128820 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1168 00:59:33.129213 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1169 00:59:33.129535 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1170 00:59:33.129848 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1171 00:59:33.151250 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1172 00:59:33.152399 iDelay=222, Bit 13, Center 69 (-50 ~ 189) 240
1173 00:59:33.152954 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1174 00:59:33.153455 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1175 00:59:33.153908 ==
1176 00:59:33.154260 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 00:59:33.156806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1178 00:59:33.157367 ==
1179 00:59:33.157739 DQS Delay:
1180 00:59:33.158250 DQS0 = 0, DQS1 = 0
1181 00:59:33.158641 DQM Delay:
1182 00:59:33.159617 DQM0 = 81, DQM1 = 69
1183 00:59:33.160069 DQ Delay:
1184 00:59:33.161883 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1185 00:59:33.165180 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1186 00:59:33.168851 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1187 00:59:33.172302 DQ12 =77, DQ13 =69, DQ14 =85, DQ15 =77
1188 00:59:33.172903
1189 00:59:33.173278
1190 00:59:33.173618 ==
1191 00:59:33.174720 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 00:59:33.179001 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1193 00:59:33.179570 ==
1194 00:59:33.179937
1195 00:59:33.180276
1196 00:59:33.181386 TX Vref Scan disable
1197 00:59:33.181847 == TX Byte 0 ==
1198 00:59:33.188017 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1199 00:59:33.192093 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1200 00:59:33.192662 == TX Byte 1 ==
1201 00:59:33.198580 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1202 00:59:33.201715 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1203 00:59:33.202295 ==
1204 00:59:33.205227 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 00:59:33.208417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1206 00:59:33.208914 ==
1207 00:59:33.223497 TX Vref=22, minBit 0, minWin=27, winSum=441
1208 00:59:33.225312 TX Vref=24, minBit 3, minWin=27, winSum=446
1209 00:59:33.230859 TX Vref=26, minBit 13, minWin=27, winSum=450
1210 00:59:33.232435 TX Vref=28, minBit 2, minWin=28, winSum=459
1211 00:59:33.236174 TX Vref=30, minBit 2, minWin=28, winSum=457
1212 00:59:33.239485 TX Vref=32, minBit 2, minWin=28, winSum=459
1213 00:59:33.246020 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1214 00:59:33.246650
1215 00:59:33.248977 Final TX Range 1 Vref 28
1216 00:59:33.249443
1217 00:59:33.249805 ==
1218 00:59:33.252340 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 00:59:33.255908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 00:59:33.256479 ==
1221 00:59:33.256907
1222 00:59:33.258918
1223 00:59:33.259433 TX Vref Scan disable
1224 00:59:33.262461 == TX Byte 0 ==
1225 00:59:33.265454 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1226 00:59:33.269531 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1227 00:59:33.272594 == TX Byte 1 ==
1228 00:59:33.275601 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1229 00:59:33.278795 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1230 00:59:33.282226
1231 00:59:33.282789 [DATLAT]
1232 00:59:33.283158 Freq=800, CH0 RK1
1233 00:59:33.283504
1234 00:59:33.285632 DATLAT Default: 0x9
1235 00:59:33.286093 0, 0xFFFF, sum = 0
1236 00:59:33.288974 1, 0xFFFF, sum = 0
1237 00:59:33.289544 2, 0xFFFF, sum = 0
1238 00:59:33.293053 3, 0xFFFF, sum = 0
1239 00:59:33.293632 4, 0xFFFF, sum = 0
1240 00:59:33.295177 5, 0xFFFF, sum = 0
1241 00:59:33.298891 6, 0xFFFF, sum = 0
1242 00:59:33.299460 7, 0xFFFF, sum = 0
1243 00:59:33.299836 8, 0x0, sum = 1
1244 00:59:33.302518 9, 0x0, sum = 2
1245 00:59:33.302990 10, 0x0, sum = 3
1246 00:59:33.305536 11, 0x0, sum = 4
1247 00:59:33.306008 best_step = 9
1248 00:59:33.306374
1249 00:59:33.306714 ==
1250 00:59:33.309290 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 00:59:33.315764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1252 00:59:33.316318 ==
1253 00:59:33.316683 RX Vref Scan: 0
1254 00:59:33.317096
1255 00:59:33.320020 RX Vref 0 -> 0, step: 1
1256 00:59:33.320581
1257 00:59:33.323271 RX Delay -111 -> 252, step: 8
1258 00:59:33.326871 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1259 00:59:33.329089 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1260 00:59:33.336067 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1261 00:59:33.339060 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1262 00:59:33.342400 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1263 00:59:33.345445 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1264 00:59:33.348632 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1265 00:59:33.356415 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1266 00:59:33.358580 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1267 00:59:33.362677 iDelay=217, Bit 9, Center 60 (-47 ~ 168) 216
1268 00:59:33.365468 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1269 00:59:33.368878 iDelay=217, Bit 11, Center 68 (-39 ~ 176) 216
1270 00:59:33.375418 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1271 00:59:33.379005 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1272 00:59:33.382128 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1273 00:59:33.385633 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1274 00:59:33.386150 ==
1275 00:59:33.389159 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 00:59:33.395263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 00:59:33.395839 ==
1278 00:59:33.396215 DQS Delay:
1279 00:59:33.396557 DQS0 = 0, DQS1 = 0
1280 00:59:33.399334 DQM Delay:
1281 00:59:33.399893 DQM0 = 85, DQM1 = 74
1282 00:59:33.401981 DQ Delay:
1283 00:59:33.405152 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =80
1284 00:59:33.405618 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1285 00:59:33.408662 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
1286 00:59:33.412449 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1287 00:59:33.414969
1288 00:59:33.415502
1289 00:59:33.421920 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1290 00:59:33.425381 CH0 RK1: MR19=606, MR18=4141
1291 00:59:33.432538 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1292 00:59:33.436289 [RxdqsGatingPostProcess] freq 800
1293 00:59:33.438647 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1294 00:59:33.442413 Pre-setting of DQS Precalculation
1295 00:59:33.445473 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1296 00:59:33.448593 ==
1297 00:59:33.451807 Dram Type= 6, Freq= 0, CH_1, rank 0
1298 00:59:33.455378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 00:59:33.455838 ==
1300 00:59:33.458406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1301 00:59:33.465337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1302 00:59:33.475340 [CA 0] Center 36 (6~67) winsize 62
1303 00:59:33.478135 [CA 1] Center 36 (6~67) winsize 62
1304 00:59:33.481672 [CA 2] Center 34 (4~65) winsize 62
1305 00:59:33.484805 [CA 3] Center 34 (4~64) winsize 61
1306 00:59:33.488638 [CA 4] Center 33 (3~64) winsize 62
1307 00:59:33.492197 [CA 5] Center 33 (3~64) winsize 62
1308 00:59:33.492803
1309 00:59:33.495029 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1310 00:59:33.495489
1311 00:59:33.498403 [CATrainingPosCal] consider 1 rank data
1312 00:59:33.501493 u2DelayCellTimex100 = 270/100 ps
1313 00:59:33.505100 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1314 00:59:33.511230 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1315 00:59:33.514615 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 00:59:33.518633 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1317 00:59:33.521220 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1318 00:59:33.525492 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1319 00:59:33.525951
1320 00:59:33.528596 CA PerBit enable=1, Macro0, CA PI delay=33
1321 00:59:33.529138
1322 00:59:33.531191 [CBTSetCACLKResult] CA Dly = 33
1323 00:59:33.531648 CS Dly: 4 (0~35)
1324 00:59:33.535679 ==
1325 00:59:33.536238 Dram Type= 6, Freq= 0, CH_1, rank 1
1326 00:59:33.541890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 00:59:33.542452 ==
1328 00:59:33.544868 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1329 00:59:33.551358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1330 00:59:33.561585 [CA 0] Center 36 (5~67) winsize 63
1331 00:59:33.564543 [CA 1] Center 36 (5~67) winsize 63
1332 00:59:33.568286 [CA 2] Center 34 (4~65) winsize 62
1333 00:59:33.570753 [CA 3] Center 33 (3~64) winsize 62
1334 00:59:33.574248 [CA 4] Center 33 (3~63) winsize 61
1335 00:59:33.577814 [CA 5] Center 33 (3~63) winsize 61
1336 00:59:33.578374
1337 00:59:33.581521 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1338 00:59:33.582078
1339 00:59:33.584174 [CATrainingPosCal] consider 2 rank data
1340 00:59:33.587955 u2DelayCellTimex100 = 270/100 ps
1341 00:59:33.591214 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1342 00:59:33.594232 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1343 00:59:33.601311 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 00:59:33.604416 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1345 00:59:33.607732 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1346 00:59:33.610735 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1347 00:59:33.611195
1348 00:59:33.614013 CA PerBit enable=1, Macro0, CA PI delay=33
1349 00:59:33.614581
1350 00:59:33.617311 [CBTSetCACLKResult] CA Dly = 33
1351 00:59:33.617771 CS Dly: 4 (0~36)
1352 00:59:33.618136
1353 00:59:33.620524 ----->DramcWriteLeveling(PI) begin...
1354 00:59:33.624049 ==
1355 00:59:33.627532 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 00:59:33.630364 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 00:59:33.630842 ==
1358 00:59:33.635076 Write leveling (Byte 0): 25 => 25
1359 00:59:33.637032 Write leveling (Byte 1): 24 => 24
1360 00:59:33.640323 DramcWriteLeveling(PI) end<-----
1361 00:59:33.640846
1362 00:59:33.641217 ==
1363 00:59:33.644184 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 00:59:33.647304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 00:59:33.647774 ==
1366 00:59:33.651290 [Gating] SW mode calibration
1367 00:59:33.658111 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1368 00:59:33.660414 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1369 00:59:33.667618 0 6 0 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
1370 00:59:33.671051 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1371 00:59:33.674209 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 00:59:33.680674 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 00:59:33.684128 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 00:59:33.687111 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 00:59:33.694143 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 00:59:33.697248 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1377 00:59:33.701296 0 7 0 | B1->B0 | 2f2f 4444 | 1 0 | (0 0) (0 0)
1378 00:59:33.707121 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1379 00:59:33.710824 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 00:59:33.714189 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 00:59:33.721022 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 00:59:33.724412 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 00:59:33.727312 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 00:59:33.734238 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1385 00:59:33.737028 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1386 00:59:33.740643 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1387 00:59:33.747508 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 00:59:33.750985 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 00:59:33.753544 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 00:59:33.757429 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 00:59:33.763444 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 00:59:33.767345 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 00:59:33.771231 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 00:59:33.776958 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 00:59:33.781135 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 00:59:33.784312 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 00:59:33.790350 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 00:59:33.794196 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 00:59:33.797413 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 00:59:33.803945 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1401 00:59:33.807750 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1402 00:59:33.811122 Total UI for P1: 0, mck2ui 16
1403 00:59:33.814397 best dqsien dly found for B1: ( 0, 9, 30)
1404 00:59:33.816986 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1405 00:59:33.821321 Total UI for P1: 0, mck2ui 16
1406 00:59:33.823823 best dqsien dly found for B0: ( 0, 9, 30)
1407 00:59:33.828219 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1408 00:59:33.830330 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1409 00:59:33.830794
1410 00:59:33.837397 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1411 00:59:33.841230 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1412 00:59:33.843744 [Gating] SW calibration Done
1413 00:59:33.844309 ==
1414 00:59:33.847260 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 00:59:33.851447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1416 00:59:33.852019 ==
1417 00:59:33.852388 RX Vref Scan: 0
1418 00:59:33.852763
1419 00:59:33.854025 RX Vref 0 -> 0, step: 1
1420 00:59:33.854486
1421 00:59:33.856627 RX Delay -130 -> 252, step: 16
1422 00:59:33.860159 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1423 00:59:33.863606 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1424 00:59:33.870195 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1425 00:59:33.873359 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1426 00:59:33.876859 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1427 00:59:33.880356 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1428 00:59:33.883469 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1429 00:59:33.890889 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1430 00:59:33.894109 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1431 00:59:33.897620 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1432 00:59:33.900648 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1433 00:59:33.904250 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1434 00:59:33.910462 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1435 00:59:33.913401 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1436 00:59:33.916792 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1437 00:59:33.920650 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1438 00:59:33.921274 ==
1439 00:59:33.923942 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 00:59:33.926937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1441 00:59:33.930084 ==
1442 00:59:33.930550 DQS Delay:
1443 00:59:33.930916 DQS0 = 0, DQS1 = 0
1444 00:59:33.933437 DQM Delay:
1445 00:59:33.933903 DQM0 = 81, DQM1 = 71
1446 00:59:33.936893 DQ Delay:
1447 00:59:33.937359 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1448 00:59:33.940362 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1449 00:59:33.943908 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1450 00:59:33.947024 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1451 00:59:33.947685
1452 00:59:33.950201
1453 00:59:33.950664 ==
1454 00:59:33.953725 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 00:59:33.957807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1456 00:59:33.958380 ==
1457 00:59:33.958753
1458 00:59:33.959092
1459 00:59:33.961096 TX Vref Scan disable
1460 00:59:33.961562 == TX Byte 0 ==
1461 00:59:33.966964 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1462 00:59:33.970911 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1463 00:59:33.971381 == TX Byte 1 ==
1464 00:59:33.977463 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1465 00:59:33.980478 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1466 00:59:33.981099 ==
1467 00:59:33.983358 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 00:59:33.987122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1469 00:59:33.987694 ==
1470 00:59:34.001471 TX Vref=22, minBit 0, minWin=28, winSum=450
1471 00:59:34.003752 TX Vref=24, minBit 2, minWin=28, winSum=454
1472 00:59:34.006625 TX Vref=26, minBit 0, minWin=28, winSum=455
1473 00:59:34.009806 TX Vref=28, minBit 3, minWin=28, winSum=458
1474 00:59:34.013961 TX Vref=30, minBit 2, minWin=28, winSum=459
1475 00:59:34.017432 TX Vref=32, minBit 2, minWin=28, winSum=456
1476 00:59:34.023677 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1477 00:59:34.024246
1478 00:59:34.026663 Final TX Range 1 Vref 30
1479 00:59:34.027231
1480 00:59:34.027595 ==
1481 00:59:34.029836 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 00:59:34.034241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 00:59:34.034830 ==
1484 00:59:34.035262
1485 00:59:34.036619
1486 00:59:34.037128 TX Vref Scan disable
1487 00:59:34.039904 == TX Byte 0 ==
1488 00:59:34.043682 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1489 00:59:34.050302 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1490 00:59:34.050868 == TX Byte 1 ==
1491 00:59:34.053710 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1492 00:59:34.056968 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1493 00:59:34.061054
1494 00:59:34.061617 [DATLAT]
1495 00:59:34.061984 Freq=800, CH1 RK0
1496 00:59:34.062329
1497 00:59:34.063849 DATLAT Default: 0xa
1498 00:59:34.064320 0, 0xFFFF, sum = 0
1499 00:59:34.066517 1, 0xFFFF, sum = 0
1500 00:59:34.067088 2, 0xFFFF, sum = 0
1501 00:59:34.070099 3, 0xFFFF, sum = 0
1502 00:59:34.070569 4, 0xFFFF, sum = 0
1503 00:59:34.074101 5, 0xFFFF, sum = 0
1504 00:59:34.078643 6, 0xFFFF, sum = 0
1505 00:59:34.079215 7, 0xFFFF, sum = 0
1506 00:59:34.079588 8, 0x0, sum = 1
1507 00:59:34.080285 9, 0x0, sum = 2
1508 00:59:34.080649 10, 0x0, sum = 3
1509 00:59:34.083500 11, 0x0, sum = 4
1510 00:59:34.084080 best_step = 9
1511 00:59:34.084447
1512 00:59:34.084820 ==
1513 00:59:34.086386 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 00:59:34.093123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1515 00:59:34.093677 ==
1516 00:59:34.094045 RX Vref Scan: 1
1517 00:59:34.094384
1518 00:59:34.096887 Set Vref Range= 32 -> 127
1519 00:59:34.097451
1520 00:59:34.099773 RX Vref 32 -> 127, step: 1
1521 00:59:34.100235
1522 00:59:34.103389 RX Delay -111 -> 252, step: 8
1523 00:59:34.103973
1524 00:59:34.106542 Set Vref, RX VrefLevel [Byte0]: 32
1525 00:59:34.109361 [Byte1]: 32
1526 00:59:34.109825
1527 00:59:34.112856 Set Vref, RX VrefLevel [Byte0]: 33
1528 00:59:34.116216 [Byte1]: 33
1529 00:59:34.116674
1530 00:59:34.119815 Set Vref, RX VrefLevel [Byte0]: 34
1531 00:59:34.123291 [Byte1]: 34
1532 00:59:34.123856
1533 00:59:34.126615 Set Vref, RX VrefLevel [Byte0]: 35
1534 00:59:34.129576 [Byte1]: 35
1535 00:59:34.135215
1536 00:59:34.135781 Set Vref, RX VrefLevel [Byte0]: 36
1537 00:59:34.136736 [Byte1]: 36
1538 00:59:34.141976
1539 00:59:34.142572 Set Vref, RX VrefLevel [Byte0]: 37
1540 00:59:34.145113 [Byte1]: 37
1541 00:59:34.149390
1542 00:59:34.149954 Set Vref, RX VrefLevel [Byte0]: 38
1543 00:59:34.152305 [Byte1]: 38
1544 00:59:34.157471
1545 00:59:34.158036 Set Vref, RX VrefLevel [Byte0]: 39
1546 00:59:34.160390 [Byte1]: 39
1547 00:59:34.164460
1548 00:59:34.165079 Set Vref, RX VrefLevel [Byte0]: 40
1549 00:59:34.167970 [Byte1]: 40
1550 00:59:34.172966
1551 00:59:34.173530 Set Vref, RX VrefLevel [Byte0]: 41
1552 00:59:34.176101 [Byte1]: 41
1553 00:59:34.180191
1554 00:59:34.180800 Set Vref, RX VrefLevel [Byte0]: 42
1555 00:59:34.184745 [Byte1]: 42
1556 00:59:34.188006
1557 00:59:34.188624 Set Vref, RX VrefLevel [Byte0]: 43
1558 00:59:34.190842 [Byte1]: 43
1559 00:59:34.195497
1560 00:59:34.196107 Set Vref, RX VrefLevel [Byte0]: 44
1561 00:59:34.198304 [Byte1]: 44
1562 00:59:34.202552
1563 00:59:34.203129 Set Vref, RX VrefLevel [Byte0]: 45
1564 00:59:34.207307 [Byte1]: 45
1565 00:59:34.210636
1566 00:59:34.211092 Set Vref, RX VrefLevel [Byte0]: 46
1567 00:59:34.213401 [Byte1]: 46
1568 00:59:34.217977
1569 00:59:34.218545 Set Vref, RX VrefLevel [Byte0]: 47
1570 00:59:34.221537 [Byte1]: 47
1571 00:59:34.225808
1572 00:59:34.226388 Set Vref, RX VrefLevel [Byte0]: 48
1573 00:59:34.228960 [Byte1]: 48
1574 00:59:34.233203
1575 00:59:34.233769 Set Vref, RX VrefLevel [Byte0]: 49
1576 00:59:34.237475 [Byte1]: 49
1577 00:59:34.241020
1578 00:59:34.241582 Set Vref, RX VrefLevel [Byte0]: 50
1579 00:59:34.244611 [Byte1]: 50
1580 00:59:34.248566
1581 00:59:34.249177 Set Vref, RX VrefLevel [Byte0]: 51
1582 00:59:34.252081 [Byte1]: 51
1583 00:59:34.256234
1584 00:59:34.256842 Set Vref, RX VrefLevel [Byte0]: 52
1585 00:59:34.260352 [Byte1]: 52
1586 00:59:34.263940
1587 00:59:34.264505 Set Vref, RX VrefLevel [Byte0]: 53
1588 00:59:34.267676 [Byte1]: 53
1589 00:59:34.272421
1590 00:59:34.273033 Set Vref, RX VrefLevel [Byte0]: 54
1591 00:59:34.275363 [Byte1]: 54
1592 00:59:34.279522
1593 00:59:34.280085 Set Vref, RX VrefLevel [Byte0]: 55
1594 00:59:34.282611 [Byte1]: 55
1595 00:59:34.287039
1596 00:59:34.287601 Set Vref, RX VrefLevel [Byte0]: 56
1597 00:59:34.290210 [Byte1]: 56
1598 00:59:34.296580
1599 00:59:34.297200 Set Vref, RX VrefLevel [Byte0]: 57
1600 00:59:34.297923 [Byte1]: 57
1601 00:59:34.302273
1602 00:59:34.302834 Set Vref, RX VrefLevel [Byte0]: 58
1603 00:59:34.308451 [Byte1]: 58
1604 00:59:34.309091
1605 00:59:34.312227 Set Vref, RX VrefLevel [Byte0]: 59
1606 00:59:34.315202 [Byte1]: 59
1607 00:59:34.315664
1608 00:59:34.318302 Set Vref, RX VrefLevel [Byte0]: 60
1609 00:59:34.321864 [Byte1]: 60
1610 00:59:34.325115
1611 00:59:34.325572 Set Vref, RX VrefLevel [Byte0]: 61
1612 00:59:34.328978 [Byte1]: 61
1613 00:59:34.333290
1614 00:59:34.333711 Set Vref, RX VrefLevel [Byte0]: 62
1615 00:59:34.336052 [Byte1]: 62
1616 00:59:34.340448
1617 00:59:34.341011 Set Vref, RX VrefLevel [Byte0]: 63
1618 00:59:34.344043 [Byte1]: 63
1619 00:59:34.348044
1620 00:59:34.348460 Set Vref, RX VrefLevel [Byte0]: 64
1621 00:59:34.351746 [Byte1]: 64
1622 00:59:34.356364
1623 00:59:34.356925 Set Vref, RX VrefLevel [Byte0]: 65
1624 00:59:34.359198 [Byte1]: 65
1625 00:59:34.363658
1626 00:59:34.364222 Set Vref, RX VrefLevel [Byte0]: 66
1627 00:59:34.367028 [Byte1]: 66
1628 00:59:34.370792
1629 00:59:34.371211 Set Vref, RX VrefLevel [Byte0]: 67
1630 00:59:34.374565 [Byte1]: 67
1631 00:59:34.379297
1632 00:59:34.379823 Set Vref, RX VrefLevel [Byte0]: 68
1633 00:59:34.382963 [Byte1]: 68
1634 00:59:34.386486
1635 00:59:34.387006 Set Vref, RX VrefLevel [Byte0]: 69
1636 00:59:34.391045 [Byte1]: 69
1637 00:59:34.393485
1638 00:59:34.393924 Set Vref, RX VrefLevel [Byte0]: 70
1639 00:59:34.397892 [Byte1]: 70
1640 00:59:34.401840
1641 00:59:34.402416 Set Vref, RX VrefLevel [Byte0]: 71
1642 00:59:34.405171 [Byte1]: 71
1643 00:59:34.409201
1644 00:59:34.409670 Set Vref, RX VrefLevel [Byte0]: 72
1645 00:59:34.412273 [Byte1]: 72
1646 00:59:34.416462
1647 00:59:34.417035 Set Vref, RX VrefLevel [Byte0]: 73
1648 00:59:34.420173 [Byte1]: 73
1649 00:59:34.425415
1650 00:59:34.425932 Set Vref, RX VrefLevel [Byte0]: 74
1651 00:59:34.428013 [Byte1]: 74
1652 00:59:34.432006
1653 00:59:34.432422 Set Vref, RX VrefLevel [Byte0]: 75
1654 00:59:34.435775 [Byte1]: 75
1655 00:59:34.441107
1656 00:59:34.441632 Set Vref, RX VrefLevel [Byte0]: 76
1657 00:59:34.443727 [Byte1]: 76
1658 00:59:34.447581
1659 00:59:34.448102 Final RX Vref Byte 0 = 58 to rank0
1660 00:59:34.451355 Final RX Vref Byte 1 = 60 to rank0
1661 00:59:34.454020 Final RX Vref Byte 0 = 58 to rank1
1662 00:59:34.457429 Final RX Vref Byte 1 = 60 to rank1==
1663 00:59:34.461924 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 00:59:34.467994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1665 00:59:34.468530 ==
1666 00:59:34.468957 DQS Delay:
1667 00:59:34.469277 DQS0 = 0, DQS1 = 0
1668 00:59:34.471385 DQM Delay:
1669 00:59:34.471905 DQM0 = 80, DQM1 = 71
1670 00:59:34.473806 DQ Delay:
1671 00:59:34.477905 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1672 00:59:34.478424 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1673 00:59:34.480845 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1674 00:59:34.483754 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1675 00:59:34.487879
1676 00:59:34.488405
1677 00:59:34.494206 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1678 00:59:34.497947 CH1 RK0: MR19=606, MR18=5656
1679 00:59:34.504844 CH1_RK0: MR19=0x606, MR18=0x5656, DQSOSC=388, MR23=63, INC=98, DEC=65
1680 00:59:34.505366
1681 00:59:34.507864 ----->DramcWriteLeveling(PI) begin...
1682 00:59:34.508341 ==
1683 00:59:34.510367 Dram Type= 6, Freq= 0, CH_1, rank 1
1684 00:59:34.514298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1685 00:59:34.514828 ==
1686 00:59:34.517413 Write leveling (Byte 0): 25 => 25
1687 00:59:34.521145 Write leveling (Byte 1): 24 => 24
1688 00:59:34.523732 DramcWriteLeveling(PI) end<-----
1689 00:59:34.524254
1690 00:59:34.524587 ==
1691 00:59:34.527123 Dram Type= 6, Freq= 0, CH_1, rank 1
1692 00:59:34.532575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1693 00:59:34.533153 ==
1694 00:59:34.533976 [Gating] SW mode calibration
1695 00:59:34.541829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1696 00:59:34.547352 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1697 00:59:34.550979 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
1698 00:59:34.554727 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 00:59:34.561862 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 00:59:34.564217 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 00:59:34.567590 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 00:59:34.574136 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 00:59:34.577365 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 00:59:34.581302 0 6 28 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
1705 00:59:34.587064 0 7 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
1706 00:59:34.590706 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 00:59:34.594026 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 00:59:34.600425 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 00:59:34.604077 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 00:59:34.607257 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 00:59:34.614296 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 00:59:34.616927 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1713 00:59:34.621208 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 00:59:34.624195 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 00:59:34.630598 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 00:59:34.634130 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 00:59:34.637334 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 00:59:34.643835 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 00:59:34.646706 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 00:59:34.650469 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 00:59:34.657211 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 00:59:34.660308 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 00:59:34.663771 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 00:59:34.671122 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 00:59:34.674094 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 00:59:34.677453 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 00:59:34.683776 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 00:59:34.687089 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1729 00:59:34.690539 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1730 00:59:34.694525 Total UI for P1: 0, mck2ui 16
1731 00:59:34.697403 best dqsien dly found for B0: ( 0, 9, 28)
1732 00:59:34.703883 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1733 00:59:34.704454 Total UI for P1: 0, mck2ui 16
1734 00:59:34.707055 best dqsien dly found for B1: ( 0, 9, 30)
1735 00:59:34.713464 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1736 00:59:34.717056 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1737 00:59:34.717675
1738 00:59:34.722034 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1739 00:59:34.724042 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1740 00:59:34.727809 [Gating] SW calibration Done
1741 00:59:34.728377 ==
1742 00:59:34.730562 Dram Type= 6, Freq= 0, CH_1, rank 1
1743 00:59:34.733968 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1744 00:59:34.734430 ==
1745 00:59:34.737187 RX Vref Scan: 0
1746 00:59:34.737644
1747 00:59:34.738007 RX Vref 0 -> 0, step: 1
1748 00:59:34.738349
1749 00:59:34.740689 RX Delay -130 -> 252, step: 16
1750 00:59:34.743367 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1751 00:59:34.750407 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1752 00:59:34.754450 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1753 00:59:34.757462 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1754 00:59:34.761749 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1755 00:59:34.763628 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1756 00:59:34.770618 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1757 00:59:34.774140 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1758 00:59:34.777244 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1759 00:59:34.780467 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1760 00:59:34.783824 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1761 00:59:34.790527 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1762 00:59:34.793431 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1763 00:59:34.797011 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1764 00:59:34.800502 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1765 00:59:34.803895 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1766 00:59:34.806847 ==
1767 00:59:34.807373 Dram Type= 6, Freq= 0, CH_1, rank 1
1768 00:59:34.813446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1769 00:59:34.813866 ==
1770 00:59:34.814193 DQS Delay:
1771 00:59:34.817204 DQS0 = 0, DQS1 = 0
1772 00:59:34.817617 DQM Delay:
1773 00:59:34.820166 DQM0 = 82, DQM1 = 70
1774 00:59:34.820581 DQ Delay:
1775 00:59:34.823792 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1776 00:59:34.827500 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1777 00:59:34.831855 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1778 00:59:34.833646 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1779 00:59:34.834065
1780 00:59:34.834394
1781 00:59:34.834874 ==
1782 00:59:34.836911 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 00:59:34.840950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1784 00:59:34.841475 ==
1785 00:59:34.841809
1786 00:59:34.842116
1787 00:59:34.844829 TX Vref Scan disable
1788 00:59:34.845374 == TX Byte 0 ==
1789 00:59:34.850387 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1790 00:59:34.853518 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1791 00:59:34.853935 == TX Byte 1 ==
1792 00:59:34.860320 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1793 00:59:34.863734 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1794 00:59:34.864152 ==
1795 00:59:34.867277 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 00:59:34.870987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1797 00:59:34.871512 ==
1798 00:59:34.885512 TX Vref=22, minBit 10, minWin=27, winSum=451
1799 00:59:34.887844 TX Vref=24, minBit 0, minWin=28, winSum=450
1800 00:59:34.891642 TX Vref=26, minBit 0, minWin=28, winSum=455
1801 00:59:34.894372 TX Vref=28, minBit 0, minWin=28, winSum=460
1802 00:59:34.897995 TX Vref=30, minBit 0, minWin=28, winSum=459
1803 00:59:34.904256 TX Vref=32, minBit 0, minWin=28, winSum=455
1804 00:59:34.907950 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 28
1805 00:59:34.908413
1806 00:59:34.911036 Final TX Range 1 Vref 28
1807 00:59:34.911697
1808 00:59:34.912078 ==
1809 00:59:34.914425 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 00:59:34.917747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1811 00:59:34.918214 ==
1812 00:59:34.920818
1813 00:59:34.921279
1814 00:59:34.921640 TX Vref Scan disable
1815 00:59:34.924177 == TX Byte 0 ==
1816 00:59:34.928156 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1817 00:59:34.931629 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1818 00:59:34.934196 == TX Byte 1 ==
1819 00:59:34.938514 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1820 00:59:34.941477 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1821 00:59:34.944183
1822 00:59:34.944639 [DATLAT]
1823 00:59:34.945073 Freq=800, CH1 RK1
1824 00:59:34.945424
1825 00:59:34.947950 DATLAT Default: 0x9
1826 00:59:34.948511 0, 0xFFFF, sum = 0
1827 00:59:34.951336 1, 0xFFFF, sum = 0
1828 00:59:34.951804 2, 0xFFFF, sum = 0
1829 00:59:34.954761 3, 0xFFFF, sum = 0
1830 00:59:34.955228 4, 0xFFFF, sum = 0
1831 00:59:34.958269 5, 0xFFFF, sum = 0
1832 00:59:34.961541 6, 0xFFFF, sum = 0
1833 00:59:34.962115 7, 0xFFFF, sum = 0
1834 00:59:34.962533 8, 0x0, sum = 1
1835 00:59:34.964481 9, 0x0, sum = 2
1836 00:59:34.964984 10, 0x0, sum = 3
1837 00:59:34.967873 11, 0x0, sum = 4
1838 00:59:34.968441 best_step = 9
1839 00:59:34.968845
1840 00:59:34.969187 ==
1841 00:59:34.971113 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 00:59:34.979392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 00:59:34.979961 ==
1844 00:59:34.980486 RX Vref Scan: 0
1845 00:59:34.980897
1846 00:59:34.981580 RX Vref 0 -> 0, step: 1
1847 00:59:34.981941
1848 00:59:34.984446 RX Delay -111 -> 252, step: 8
1849 00:59:34.987926 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1850 00:59:34.991168 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1851 00:59:34.998035 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1852 00:59:35.001243 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1853 00:59:35.004703 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1854 00:59:35.007494 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1855 00:59:35.011557 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1856 00:59:35.018292 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1857 00:59:35.020822 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1858 00:59:35.023995 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1859 00:59:35.027409 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1860 00:59:35.031121 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1861 00:59:35.037678 iDelay=217, Bit 12, Center 84 (-39 ~ 208) 248
1862 00:59:35.040434 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1863 00:59:35.044007 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1864 00:59:35.048573 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1865 00:59:35.049205 ==
1866 00:59:35.050540 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 00:59:35.057803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 00:59:35.058391 ==
1869 00:59:35.058764 DQS Delay:
1870 00:59:35.059104 DQS0 = 0, DQS1 = 0
1871 00:59:35.061031 DQM Delay:
1872 00:59:35.061594 DQM0 = 82, DQM1 = 71
1873 00:59:35.064173 DQ Delay:
1874 00:59:35.067047 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1875 00:59:35.070993 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1876 00:59:35.071564 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1877 00:59:35.077362 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1878 00:59:35.077940
1879 00:59:35.078305
1880 00:59:35.084037 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1881 00:59:35.087403 CH1 RK1: MR19=606, MR18=3636
1882 00:59:35.093999 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1883 00:59:35.097402 [RxdqsGatingPostProcess] freq 800
1884 00:59:35.101260 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1885 00:59:35.104253 Pre-setting of DQS Precalculation
1886 00:59:35.110476 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1887 00:59:35.117301 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1888 00:59:35.123776 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1889 00:59:35.124353
1890 00:59:35.124772
1891 00:59:35.127775 [Calibration Summary] 1600 Mbps
1892 00:59:35.128342 CH 0, Rank 0
1893 00:59:35.131215 SW Impedance : PASS
1894 00:59:35.131778 DUTY Scan : NO K
1895 00:59:35.134106 ZQ Calibration : PASS
1896 00:59:35.137680 Jitter Meter : NO K
1897 00:59:35.138256 CBT Training : PASS
1898 00:59:35.140825 Write leveling : PASS
1899 00:59:35.143892 RX DQS gating : PASS
1900 00:59:35.144353 RX DQ/DQS(RDDQC) : PASS
1901 00:59:35.147708 TX DQ/DQS : PASS
1902 00:59:35.150829 RX DATLAT : PASS
1903 00:59:35.151292 RX DQ/DQS(Engine): PASS
1904 00:59:35.153992 TX OE : NO K
1905 00:59:35.154453 All Pass.
1906 00:59:35.154816
1907 00:59:35.157554 CH 0, Rank 1
1908 00:59:35.158116 SW Impedance : PASS
1909 00:59:35.161304 DUTY Scan : NO K
1910 00:59:35.164172 ZQ Calibration : PASS
1911 00:59:35.164633 Jitter Meter : NO K
1912 00:59:35.167643 CBT Training : PASS
1913 00:59:35.168214 Write leveling : PASS
1914 00:59:35.171245 RX DQS gating : PASS
1915 00:59:35.174573 RX DQ/DQS(RDDQC) : PASS
1916 00:59:35.175140 TX DQ/DQS : PASS
1917 00:59:35.177849 RX DATLAT : PASS
1918 00:59:35.181031 RX DQ/DQS(Engine): PASS
1919 00:59:35.181493 TX OE : NO K
1920 00:59:35.184119 All Pass.
1921 00:59:35.184578
1922 00:59:35.184974 CH 1, Rank 0
1923 00:59:35.187515 SW Impedance : PASS
1924 00:59:35.188076 DUTY Scan : NO K
1925 00:59:35.191400 ZQ Calibration : PASS
1926 00:59:35.194077 Jitter Meter : NO K
1927 00:59:35.194640 CBT Training : PASS
1928 00:59:35.197606 Write leveling : PASS
1929 00:59:35.201005 RX DQS gating : PASS
1930 00:59:35.201570 RX DQ/DQS(RDDQC) : PASS
1931 00:59:35.203859 TX DQ/DQS : PASS
1932 00:59:35.207072 RX DATLAT : PASS
1933 00:59:35.207635 RX DQ/DQS(Engine): PASS
1934 00:59:35.211291 TX OE : NO K
1935 00:59:35.211857 All Pass.
1936 00:59:35.212225
1937 00:59:35.213921 CH 1, Rank 1
1938 00:59:35.214499 SW Impedance : PASS
1939 00:59:35.216805 DUTY Scan : NO K
1940 00:59:35.220479 ZQ Calibration : PASS
1941 00:59:35.220997 Jitter Meter : NO K
1942 00:59:35.224032 CBT Training : PASS
1943 00:59:35.224638 Write leveling : PASS
1944 00:59:35.227259 RX DQS gating : PASS
1945 00:59:35.230231 RX DQ/DQS(RDDQC) : PASS
1946 00:59:35.230794 TX DQ/DQS : PASS
1947 00:59:35.233561 RX DATLAT : PASS
1948 00:59:35.236864 RX DQ/DQS(Engine): PASS
1949 00:59:35.237429 TX OE : NO K
1950 00:59:35.240347 All Pass.
1951 00:59:35.240958
1952 00:59:35.241325 DramC Write-DBI off
1953 00:59:35.243882 PER_BANK_REFRESH: Hybrid Mode
1954 00:59:35.247224 TX_TRACKING: ON
1955 00:59:35.250823 [GetDramInforAfterCalByMRR] Vendor 6.
1956 00:59:35.253290 [GetDramInforAfterCalByMRR] Revision 606.
1957 00:59:35.256947 [GetDramInforAfterCalByMRR] Revision 2 0.
1958 00:59:35.257599 MR0 0x3939
1959 00:59:35.257981 MR8 0x1111
1960 00:59:35.263790 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 00:59:35.264344
1962 00:59:35.264741 MR0 0x3939
1963 00:59:35.265106 MR8 0x1111
1964 00:59:35.267036 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1965 00:59:35.267646
1966 00:59:35.277122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1967 00:59:35.280485 [FAST_K] Save calibration result to emmc
1968 00:59:35.283641 [FAST_K] Save calibration result to emmc
1969 00:59:35.286880 dram_init: config_dvfs: 1
1970 00:59:35.290666 dramc_set_vcore_voltage set vcore to 662500
1971 00:59:35.293631 Read voltage for 1200, 2
1972 00:59:35.294197 Vio18 = 0
1973 00:59:35.294567 Vcore = 662500
1974 00:59:35.296906 Vdram = 0
1975 00:59:35.297365 Vddq = 0
1976 00:59:35.297728 Vmddr = 0
1977 00:59:35.303369 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1978 00:59:35.306789 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1979 00:59:35.310680 MEM_TYPE=3, freq_sel=15
1980 00:59:35.313558 sv_algorithm_assistance_LP4_1600
1981 00:59:35.316392 ============ PULL DRAM RESETB DOWN ============
1982 00:59:35.320177 ========== PULL DRAM RESETB DOWN end =========
1983 00:59:35.326715 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1984 00:59:35.330236 ===================================
1985 00:59:35.333100 LPDDR4 DRAM CONFIGURATION
1986 00:59:35.336763 ===================================
1987 00:59:35.337333 EX_ROW_EN[0] = 0x0
1988 00:59:35.340005 EX_ROW_EN[1] = 0x0
1989 00:59:35.340459 LP4Y_EN = 0x0
1990 00:59:35.343576 WORK_FSP = 0x0
1991 00:59:35.344130 WL = 0x4
1992 00:59:35.346581 RL = 0x4
1993 00:59:35.347060 BL = 0x2
1994 00:59:35.350310 RPST = 0x0
1995 00:59:35.350894 RD_PRE = 0x0
1996 00:59:35.354118 WR_PRE = 0x1
1997 00:59:35.354578 WR_PST = 0x0
1998 00:59:35.356625 DBI_WR = 0x0
1999 00:59:35.357223 DBI_RD = 0x0
2000 00:59:35.360427 OTF = 0x1
2001 00:59:35.363772 ===================================
2002 00:59:35.368259 ===================================
2003 00:59:35.368869 ANA top config
2004 00:59:35.372897 ===================================
2005 00:59:35.374388 DLL_ASYNC_EN = 0
2006 00:59:35.376979 ALL_SLAVE_EN = 0
2007 00:59:35.380279 NEW_RANK_MODE = 1
2008 00:59:35.380887 DLL_IDLE_MODE = 1
2009 00:59:35.383540 LP45_APHY_COMB_EN = 1
2010 00:59:35.386600 TX_ODT_DIS = 1
2011 00:59:35.389852 NEW_8X_MODE = 1
2012 00:59:35.393551 ===================================
2013 00:59:35.396780 ===================================
2014 00:59:35.400391 data_rate = 2400
2015 00:59:35.401006 CKR = 1
2016 00:59:35.403735 DQ_P2S_RATIO = 8
2017 00:59:35.406725 ===================================
2018 00:59:35.410019 CA_P2S_RATIO = 8
2019 00:59:35.413988 DQ_CA_OPEN = 0
2020 00:59:35.416690 DQ_SEMI_OPEN = 0
2021 00:59:35.419626 CA_SEMI_OPEN = 0
2022 00:59:35.420088 CA_FULL_RATE = 0
2023 00:59:35.423151 DQ_CKDIV4_EN = 0
2024 00:59:35.426966 CA_CKDIV4_EN = 0
2025 00:59:35.430174 CA_PREDIV_EN = 0
2026 00:59:35.432914 PH8_DLY = 17
2027 00:59:35.436605 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2028 00:59:35.437224 DQ_AAMCK_DIV = 4
2029 00:59:35.439958 CA_AAMCK_DIV = 4
2030 00:59:35.443608 CA_ADMCK_DIV = 4
2031 00:59:35.446258 DQ_TRACK_CA_EN = 0
2032 00:59:35.450078 CA_PICK = 1200
2033 00:59:35.453057 CA_MCKIO = 1200
2034 00:59:35.456284 MCKIO_SEMI = 0
2035 00:59:35.456897 PLL_FREQ = 2366
2036 00:59:35.460109 DQ_UI_PI_RATIO = 32
2037 00:59:35.462685 CA_UI_PI_RATIO = 0
2038 00:59:35.466579 ===================================
2039 00:59:35.469392 ===================================
2040 00:59:35.473431 memory_type:LPDDR4
2041 00:59:35.476599 GP_NUM : 10
2042 00:59:35.477215 SRAM_EN : 1
2043 00:59:35.479744 MD32_EN : 0
2044 00:59:35.482912 ===================================
2045 00:59:35.483477 [ANA_INIT] >>>>>>>>>>>>>>
2046 00:59:35.486744 <<<<<< [CONFIGURE PHASE]: ANA_TX
2047 00:59:35.489319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2048 00:59:35.492606 ===================================
2049 00:59:35.496063 data_rate = 2400,PCW = 0X5b00
2050 00:59:35.499688 ===================================
2051 00:59:35.503012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2052 00:59:35.509426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2053 00:59:35.513101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2054 00:59:35.519868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2055 00:59:35.522812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2056 00:59:35.526113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2057 00:59:35.529340 [ANA_INIT] flow start
2058 00:59:35.529801 [ANA_INIT] PLL >>>>>>>>
2059 00:59:35.533349 [ANA_INIT] PLL <<<<<<<<
2060 00:59:35.536529 [ANA_INIT] MIDPI >>>>>>>>
2061 00:59:35.537142 [ANA_INIT] MIDPI <<<<<<<<
2062 00:59:35.539908 [ANA_INIT] DLL >>>>>>>>
2063 00:59:35.543484 [ANA_INIT] DLL <<<<<<<<
2064 00:59:35.544048 [ANA_INIT] flow end
2065 00:59:35.546723 ============ LP4 DIFF to SE enter ============
2066 00:59:35.553114 ============ LP4 DIFF to SE exit ============
2067 00:59:35.553670 [ANA_INIT] <<<<<<<<<<<<<
2068 00:59:35.556228 [Flow] Enable top DCM control >>>>>
2069 00:59:35.559578 [Flow] Enable top DCM control <<<<<
2070 00:59:35.563446 Enable DLL master slave shuffle
2071 00:59:35.569683 ==============================================================
2072 00:59:35.570247 Gating Mode config
2073 00:59:35.576441 ==============================================================
2074 00:59:35.579291 Config description:
2075 00:59:35.589459 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2076 00:59:35.596444 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2077 00:59:35.600109 SELPH_MODE 0: By rank 1: By Phase
2078 00:59:35.605958 ==============================================================
2079 00:59:35.609736 GAT_TRACK_EN = 1
2080 00:59:35.610301 RX_GATING_MODE = 2
2081 00:59:35.612884 RX_GATING_TRACK_MODE = 2
2082 00:59:35.616073 SELPH_MODE = 1
2083 00:59:35.619202 PICG_EARLY_EN = 1
2084 00:59:35.623668 VALID_LAT_VALUE = 1
2085 00:59:35.630031 ==============================================================
2086 00:59:35.633885 Enter into Gating configuration >>>>
2087 00:59:35.636782 Exit from Gating configuration <<<<
2088 00:59:35.640040 Enter into DVFS_PRE_config >>>>>
2089 00:59:35.649922 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2090 00:59:35.653652 Exit from DVFS_PRE_config <<<<<
2091 00:59:35.656062 Enter into PICG configuration >>>>
2092 00:59:35.660260 Exit from PICG configuration <<<<
2093 00:59:35.662775 [RX_INPUT] configuration >>>>>
2094 00:59:35.666354 [RX_INPUT] configuration <<<<<
2095 00:59:35.669628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2096 00:59:35.676181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2097 00:59:35.682645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2098 00:59:35.686075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2099 00:59:35.692515 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2100 00:59:35.699596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2101 00:59:35.702835 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2102 00:59:35.705644 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2103 00:59:35.712557 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2104 00:59:35.715897 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2105 00:59:35.718966 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2106 00:59:35.726564 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2107 00:59:35.729019 ===================================
2108 00:59:35.729501 LPDDR4 DRAM CONFIGURATION
2109 00:59:35.733686 ===================================
2110 00:59:35.736463 EX_ROW_EN[0] = 0x0
2111 00:59:35.739429 EX_ROW_EN[1] = 0x0
2112 00:59:35.739908 LP4Y_EN = 0x0
2113 00:59:35.742785 WORK_FSP = 0x0
2114 00:59:35.743262 WL = 0x4
2115 00:59:35.746214 RL = 0x4
2116 00:59:35.746801 BL = 0x2
2117 00:59:35.749340 RPST = 0x0
2118 00:59:35.749820 RD_PRE = 0x0
2119 00:59:35.753164 WR_PRE = 0x1
2120 00:59:35.753747 WR_PST = 0x0
2121 00:59:35.755789 DBI_WR = 0x0
2122 00:59:35.756374 DBI_RD = 0x0
2123 00:59:35.759597 OTF = 0x1
2124 00:59:35.762385 ===================================
2125 00:59:35.765898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2126 00:59:35.769264 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2127 00:59:35.772386 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2128 00:59:35.776424 ===================================
2129 00:59:35.779588 LPDDR4 DRAM CONFIGURATION
2130 00:59:35.782918 ===================================
2131 00:59:35.785404 EX_ROW_EN[0] = 0x10
2132 00:59:35.785884 EX_ROW_EN[1] = 0x0
2133 00:59:35.789270 LP4Y_EN = 0x0
2134 00:59:35.789853 WORK_FSP = 0x0
2135 00:59:35.792810 WL = 0x4
2136 00:59:35.793250 RL = 0x4
2137 00:59:35.796136 BL = 0x2
2138 00:59:35.796616 RPST = 0x0
2139 00:59:35.800441 RD_PRE = 0x0
2140 00:59:35.802742 WR_PRE = 0x1
2141 00:59:35.803329 WR_PST = 0x0
2142 00:59:35.805821 DBI_WR = 0x0
2143 00:59:35.806407 DBI_RD = 0x0
2144 00:59:35.808825 OTF = 0x1
2145 00:59:35.812474 ===================================
2146 00:59:35.815390 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2147 00:59:35.818833 ==
2148 00:59:35.821972 Dram Type= 6, Freq= 0, CH_0, rank 0
2149 00:59:35.826011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2150 00:59:35.826601 ==
2151 00:59:35.828849 [Duty_Offset_Calibration]
2152 00:59:35.829329 B0:0 B1:2 CA:1
2153 00:59:35.829815
2154 00:59:35.832479 [DutyScan_Calibration_Flow] k_type=0
2155 00:59:35.841545
2156 00:59:35.842124 ==CLK 0==
2157 00:59:35.845346 Final CLK duty delay cell = 0
2158 00:59:35.849127 [0] MAX Duty = 5093%(X100), DQS PI = 12
2159 00:59:35.851905 [0] MIN Duty = 4938%(X100), DQS PI = 52
2160 00:59:35.852386 [0] AVG Duty = 5015%(X100)
2161 00:59:35.855130
2162 00:59:35.858626 CH0 CLK Duty spec in!! Max-Min= 155%
2163 00:59:35.861719 [DutyScan_Calibration_Flow] ====Done====
2164 00:59:35.862198
2165 00:59:35.865442 [DutyScan_Calibration_Flow] k_type=1
2166 00:59:35.881603
2167 00:59:35.882200 ==DQS 0 ==
2168 00:59:35.884370 Final DQS duty delay cell = 0
2169 00:59:35.887574 [0] MAX Duty = 5125%(X100), DQS PI = 30
2170 00:59:35.891520 [0] MIN Duty = 5031%(X100), DQS PI = 4
2171 00:59:35.892131 [0] AVG Duty = 5078%(X100)
2172 00:59:35.894737
2173 00:59:35.895323 ==DQS 1 ==
2174 00:59:35.898209 Final DQS duty delay cell = 0
2175 00:59:35.901678 [0] MAX Duty = 5062%(X100), DQS PI = 58
2176 00:59:35.904388 [0] MIN Duty = 4906%(X100), DQS PI = 14
2177 00:59:35.905013 [0] AVG Duty = 4984%(X100)
2178 00:59:35.907991
2179 00:59:35.911452 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2180 00:59:35.911935
2181 00:59:35.914194 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2182 00:59:35.918077 [DutyScan_Calibration_Flow] ====Done====
2183 00:59:35.918553
2184 00:59:35.921097 [DutyScan_Calibration_Flow] k_type=3
2185 00:59:35.938597
2186 00:59:35.939153 ==DQM 0 ==
2187 00:59:35.941268 Final DQM duty delay cell = 0
2188 00:59:35.944261 [0] MAX Duty = 5156%(X100), DQS PI = 20
2189 00:59:35.948021 [0] MIN Duty = 4969%(X100), DQS PI = 54
2190 00:59:35.951100 [0] AVG Duty = 5062%(X100)
2191 00:59:35.951679
2192 00:59:35.952045 ==DQM 1 ==
2193 00:59:35.954045 Final DQM duty delay cell = 0
2194 00:59:35.957060 [0] MAX Duty = 5000%(X100), DQS PI = 56
2195 00:59:35.961096 [0] MIN Duty = 4844%(X100), DQS PI = 0
2196 00:59:35.964484 [0] AVG Duty = 4922%(X100)
2197 00:59:35.965312
2198 00:59:35.967247 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2199 00:59:35.967813
2200 00:59:35.971047 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2201 00:59:35.974612 [DutyScan_Calibration_Flow] ====Done====
2202 00:59:35.975182
2203 00:59:35.977234 [DutyScan_Calibration_Flow] k_type=2
2204 00:59:35.992368
2205 00:59:35.992967 ==DQ 0 ==
2206 00:59:35.996529 Final DQ duty delay cell = -4
2207 00:59:35.999060 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2208 00:59:36.002821 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2209 00:59:36.006701 [-4] AVG Duty = 4937%(X100)
2210 00:59:36.007264
2211 00:59:36.007629 ==DQ 1 ==
2212 00:59:36.008693 Final DQ duty delay cell = -4
2213 00:59:36.012316 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2214 00:59:36.016328 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2215 00:59:36.019148 [-4] AVG Duty = 4984%(X100)
2216 00:59:36.019606
2217 00:59:36.021999 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2218 00:59:36.022457
2219 00:59:36.025776 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2220 00:59:36.028755 [DutyScan_Calibration_Flow] ====Done====
2221 00:59:36.029227 ==
2222 00:59:36.032159 Dram Type= 6, Freq= 0, CH_1, rank 0
2223 00:59:36.035623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2224 00:59:36.036188 ==
2225 00:59:36.038951 [Duty_Offset_Calibration]
2226 00:59:36.039506 B0:0 B1:5 CA:-5
2227 00:59:36.039870
2228 00:59:36.042337 [DutyScan_Calibration_Flow] k_type=0
2229 00:59:36.053749
2230 00:59:36.054307 ==CLK 0==
2231 00:59:36.055814 Final CLK duty delay cell = 0
2232 00:59:36.059817 [0] MAX Duty = 5094%(X100), DQS PI = 24
2233 00:59:36.062736 [0] MIN Duty = 4875%(X100), DQS PI = 46
2234 00:59:36.065645 [0] AVG Duty = 4984%(X100)
2235 00:59:36.066102
2236 00:59:36.069242 CH1 CLK Duty spec in!! Max-Min= 219%
2237 00:59:36.072412 [DutyScan_Calibration_Flow] ====Done====
2238 00:59:36.072924
2239 00:59:36.076301 [DutyScan_Calibration_Flow] k_type=1
2240 00:59:36.091328
2241 00:59:36.091888 ==DQS 0 ==
2242 00:59:36.094791 Final DQS duty delay cell = 0
2243 00:59:36.098849 [0] MAX Duty = 5125%(X100), DQS PI = 16
2244 00:59:36.101248 [0] MIN Duty = 4875%(X100), DQS PI = 40
2245 00:59:36.105624 [0] AVG Duty = 5000%(X100)
2246 00:59:36.106181
2247 00:59:36.106542 ==DQS 1 ==
2248 00:59:36.107666 Final DQS duty delay cell = -4
2249 00:59:36.111455 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2250 00:59:36.114949 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2251 00:59:36.118037 [-4] AVG Duty = 4969%(X100)
2252 00:59:36.118898
2253 00:59:36.121317 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2254 00:59:36.121804
2255 00:59:36.125385 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2256 00:59:36.128176 [DutyScan_Calibration_Flow] ====Done====
2257 00:59:36.128772
2258 00:59:36.131402 [DutyScan_Calibration_Flow] k_type=3
2259 00:59:36.146761
2260 00:59:36.147316 ==DQM 0 ==
2261 00:59:36.149728 Final DQM duty delay cell = -4
2262 00:59:36.153223 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2263 00:59:36.157046 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2264 00:59:36.160135 [-4] AVG Duty = 4953%(X100)
2265 00:59:36.160687
2266 00:59:36.161173 ==DQM 1 ==
2267 00:59:36.163286 Final DQM duty delay cell = -4
2268 00:59:36.167190 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2269 00:59:36.170210 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2270 00:59:36.173637 [-4] AVG Duty = 5000%(X100)
2271 00:59:36.174184
2272 00:59:36.176687 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2273 00:59:36.177320
2274 00:59:36.179838 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2275 00:59:36.183216 [DutyScan_Calibration_Flow] ====Done====
2276 00:59:36.183775
2277 00:59:36.186152 [DutyScan_Calibration_Flow] k_type=2
2278 00:59:36.204453
2279 00:59:36.205112 ==DQ 0 ==
2280 00:59:36.207709 Final DQ duty delay cell = 0
2281 00:59:36.210138 [0] MAX Duty = 5062%(X100), DQS PI = 0
2282 00:59:36.213902 [0] MIN Duty = 4969%(X100), DQS PI = 42
2283 00:59:36.214464 [0] AVG Duty = 5015%(X100)
2284 00:59:36.214830
2285 00:59:36.217071 ==DQ 1 ==
2286 00:59:36.220676 Final DQ duty delay cell = 0
2287 00:59:36.224035 [0] MAX Duty = 5031%(X100), DQS PI = 8
2288 00:59:36.227585 [0] MIN Duty = 4907%(X100), DQS PI = 0
2289 00:59:36.228148 [0] AVG Duty = 4969%(X100)
2290 00:59:36.228509
2291 00:59:36.231502 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2292 00:59:36.232063
2293 00:59:36.234483 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2294 00:59:36.240371 [DutyScan_Calibration_Flow] ====Done====
2295 00:59:36.243637 nWR fixed to 30
2296 00:59:36.244094 [ModeRegInit_LP4] CH0 RK0
2297 00:59:36.247430 [ModeRegInit_LP4] CH0 RK1
2298 00:59:36.250231 [ModeRegInit_LP4] CH1 RK0
2299 00:59:36.250687 [ModeRegInit_LP4] CH1 RK1
2300 00:59:36.253221 match AC timing 6
2301 00:59:36.256592 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2302 00:59:36.260048 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2303 00:59:36.267456 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2304 00:59:36.270860 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2305 00:59:36.276530 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2306 00:59:36.277020 ==
2307 00:59:36.280230 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 00:59:36.283618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2309 00:59:36.284178 ==
2310 00:59:36.290281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2311 00:59:36.297170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2312 00:59:36.303740 [CA 0] Center 39 (9~70) winsize 62
2313 00:59:36.306506 [CA 1] Center 39 (8~70) winsize 63
2314 00:59:36.310217 [CA 2] Center 36 (5~67) winsize 63
2315 00:59:36.314652 [CA 3] Center 35 (4~66) winsize 63
2316 00:59:36.316702 [CA 4] Center 34 (3~65) winsize 63
2317 00:59:36.320281 [CA 5] Center 33 (3~64) winsize 62
2318 00:59:36.320786
2319 00:59:36.323506 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2320 00:59:36.323961
2321 00:59:36.326701 [CATrainingPosCal] consider 1 rank data
2322 00:59:36.330495 u2DelayCellTimex100 = 270/100 ps
2323 00:59:36.332932 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2324 00:59:36.336774 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2325 00:59:36.342957 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2326 00:59:36.346817 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2327 00:59:36.350377 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2328 00:59:36.353369 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2329 00:59:36.353826
2330 00:59:36.356831 CA PerBit enable=1, Macro0, CA PI delay=33
2331 00:59:36.357383
2332 00:59:36.360060 [CBTSetCACLKResult] CA Dly = 33
2333 00:59:36.360704 CS Dly: 7 (0~38)
2334 00:59:36.363507 ==
2335 00:59:36.364068 Dram Type= 6, Freq= 0, CH_0, rank 1
2336 00:59:36.371097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2337 00:59:36.371660 ==
2338 00:59:36.373149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2339 00:59:36.380268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2340 00:59:36.389022 [CA 0] Center 39 (8~70) winsize 63
2341 00:59:36.392384 [CA 1] Center 39 (8~70) winsize 63
2342 00:59:36.395523 [CA 2] Center 35 (5~66) winsize 62
2343 00:59:36.398872 [CA 3] Center 35 (4~66) winsize 63
2344 00:59:36.402517 [CA 4] Center 33 (3~64) winsize 62
2345 00:59:36.406122 [CA 5] Center 33 (3~64) winsize 62
2346 00:59:36.406683
2347 00:59:36.409387 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2348 00:59:36.409948
2349 00:59:36.412516 [CATrainingPosCal] consider 2 rank data
2350 00:59:36.415236 u2DelayCellTimex100 = 270/100 ps
2351 00:59:36.418869 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2352 00:59:36.422633 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2353 00:59:36.428674 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2354 00:59:36.431966 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2355 00:59:36.434977 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2356 00:59:36.438754 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2357 00:59:36.439235
2358 00:59:36.442649 CA PerBit enable=1, Macro0, CA PI delay=33
2359 00:59:36.443129
2360 00:59:36.445147 [CBTSetCACLKResult] CA Dly = 33
2361 00:59:36.445630 CS Dly: 7 (0~39)
2362 00:59:36.448772
2363 00:59:36.452063 ----->DramcWriteLeveling(PI) begin...
2364 00:59:36.452548 ==
2365 00:59:36.455455 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 00:59:36.458751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2367 00:59:36.459329 ==
2368 00:59:36.461580 Write leveling (Byte 0): 27 => 27
2369 00:59:36.465640 Write leveling (Byte 1): 26 => 26
2370 00:59:36.468216 DramcWriteLeveling(PI) end<-----
2371 00:59:36.468841
2372 00:59:36.469337 ==
2373 00:59:36.472019 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 00:59:36.475037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2375 00:59:36.475650 ==
2376 00:59:36.478070 [Gating] SW mode calibration
2377 00:59:36.484777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2378 00:59:36.491942 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2379 00:59:36.495282 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 00:59:36.498171 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2381 00:59:36.504669 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 00:59:36.508589 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2383 00:59:36.511800 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 00:59:36.517751 0 11 20 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (1 0)
2385 00:59:36.521408 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 00:59:36.524512 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 00:59:36.531524 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2388 00:59:36.534445 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 00:59:36.538140 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 00:59:36.541416 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 00:59:36.547958 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 00:59:36.551033 0 12 20 | B1->B0 | 3737 3b3b | 0 0 | (0 0) (0 0)
2393 00:59:36.555111 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 00:59:36.561411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 00:59:36.566310 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 00:59:36.568356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 00:59:36.574565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 00:59:36.578117 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 00:59:36.581076 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 00:59:36.587887 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2401 00:59:36.591495 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 00:59:36.594912 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 00:59:36.601664 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 00:59:36.604808 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 00:59:36.607854 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 00:59:36.614418 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 00:59:36.618282 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 00:59:36.621481 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 00:59:36.627918 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 00:59:36.631370 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 00:59:36.634807 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 00:59:36.637843 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 00:59:36.644461 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 00:59:36.648685 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 00:59:36.652323 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 00:59:36.658171 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2417 00:59:36.661590 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2418 00:59:36.665226 Total UI for P1: 0, mck2ui 16
2419 00:59:36.668124 best dqsien dly found for B0: ( 0, 15, 20)
2420 00:59:36.671779 Total UI for P1: 0, mck2ui 16
2421 00:59:36.674667 best dqsien dly found for B1: ( 0, 15, 20)
2422 00:59:36.678568 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2423 00:59:36.681900 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2424 00:59:36.682459
2425 00:59:36.685201 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2426 00:59:36.687875 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2427 00:59:36.691233 [Gating] SW calibration Done
2428 00:59:36.691793 ==
2429 00:59:36.694585 Dram Type= 6, Freq= 0, CH_0, rank 0
2430 00:59:36.701604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2431 00:59:36.702163 ==
2432 00:59:36.702530 RX Vref Scan: 0
2433 00:59:36.702875
2434 00:59:36.704658 RX Vref 0 -> 0, step: 1
2435 00:59:36.705255
2436 00:59:36.708085 RX Delay -40 -> 252, step: 8
2437 00:59:36.712849 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2438 00:59:36.715074 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2439 00:59:36.718061 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2440 00:59:36.721415 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2441 00:59:36.728003 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2442 00:59:36.731454 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2443 00:59:36.734716 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2444 00:59:36.738377 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2445 00:59:36.741153 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2446 00:59:36.747579 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2447 00:59:36.751067 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2448 00:59:36.754953 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2449 00:59:36.758186 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2450 00:59:36.761370 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2451 00:59:36.767796 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2452 00:59:36.771335 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2453 00:59:36.771904 ==
2454 00:59:36.774278 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 00:59:36.778625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2456 00:59:36.779196 ==
2457 00:59:36.781470 DQS Delay:
2458 00:59:36.782039 DQS0 = 0, DQS1 = 0
2459 00:59:36.782405 DQM Delay:
2460 00:59:36.784309 DQM0 = 115, DQM1 = 106
2461 00:59:36.784799 DQ Delay:
2462 00:59:36.787892 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2463 00:59:36.791625 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2464 00:59:36.795072 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2465 00:59:36.801420 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2466 00:59:36.802162
2467 00:59:36.802611
2468 00:59:36.802960 ==
2469 00:59:36.804218 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 00:59:36.808521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2471 00:59:36.809147 ==
2472 00:59:36.809520
2473 00:59:36.809860
2474 00:59:36.811042 TX Vref Scan disable
2475 00:59:36.811503 == TX Byte 0 ==
2476 00:59:36.818989 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2477 00:59:36.821079 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2478 00:59:36.821541 == TX Byte 1 ==
2479 00:59:36.828003 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2480 00:59:36.831003 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2481 00:59:36.831569 ==
2482 00:59:36.834720 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 00:59:36.838797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2484 00:59:36.839263 ==
2485 00:59:36.850384 TX Vref=22, minBit 9, minWin=25, winSum=417
2486 00:59:36.854401 TX Vref=24, minBit 8, minWin=25, winSum=423
2487 00:59:36.857004 TX Vref=26, minBit 9, minWin=25, winSum=427
2488 00:59:36.860393 TX Vref=28, minBit 12, minWin=25, winSum=430
2489 00:59:36.863705 TX Vref=30, minBit 5, minWin=26, winSum=435
2490 00:59:36.869890 TX Vref=32, minBit 3, minWin=26, winSum=427
2491 00:59:36.873228 [TxChooseVref] Worse bit 5, Min win 26, Win sum 435, Final Vref 30
2492 00:59:36.873805
2493 00:59:36.877225 Final TX Range 1 Vref 30
2494 00:59:36.877800
2495 00:59:36.878291 ==
2496 00:59:36.880407 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 00:59:36.883615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 00:59:36.884095 ==
2499 00:59:36.886750
2500 00:59:36.887318
2501 00:59:36.887807 TX Vref Scan disable
2502 00:59:36.890043 == TX Byte 0 ==
2503 00:59:36.893229 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2504 00:59:36.896199 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2505 00:59:36.900187 == TX Byte 1 ==
2506 00:59:36.903624 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2507 00:59:36.906971 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2508 00:59:36.909617
2509 00:59:36.910183 [DATLAT]
2510 00:59:36.910780 Freq=1200, CH0 RK0
2511 00:59:36.911312
2512 00:59:36.913104 DATLAT Default: 0xd
2513 00:59:36.913568 0, 0xFFFF, sum = 0
2514 00:59:36.917654 1, 0xFFFF, sum = 0
2515 00:59:36.918226 2, 0xFFFF, sum = 0
2516 00:59:36.920289 3, 0xFFFF, sum = 0
2517 00:59:36.920906 4, 0xFFFF, sum = 0
2518 00:59:36.924020 5, 0xFFFF, sum = 0
2519 00:59:36.924520 6, 0xFFFF, sum = 0
2520 00:59:36.926623 7, 0xFFFF, sum = 0
2521 00:59:36.930095 8, 0xFFFF, sum = 0
2522 00:59:36.930773 9, 0xFFFF, sum = 0
2523 00:59:36.933572 10, 0xFFFF, sum = 0
2524 00:59:36.934056 11, 0x0, sum = 1
2525 00:59:36.934550 12, 0x0, sum = 2
2526 00:59:36.937123 13, 0x0, sum = 3
2527 00:59:36.937611 14, 0x0, sum = 4
2528 00:59:36.939794 best_step = 12
2529 00:59:36.940353
2530 00:59:36.940766 ==
2531 00:59:36.943726 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 00:59:36.946485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 00:59:36.946953 ==
2534 00:59:36.950368 RX Vref Scan: 1
2535 00:59:36.950954
2536 00:59:36.951342 Set Vref Range= 32 -> 127
2537 00:59:36.953431
2538 00:59:36.953896 RX Vref 32 -> 127, step: 1
2539 00:59:36.954266
2540 00:59:36.957107 RX Delay -21 -> 252, step: 4
2541 00:59:36.957665
2542 00:59:36.960521 Set Vref, RX VrefLevel [Byte0]: 32
2543 00:59:36.963470 [Byte1]: 32
2544 00:59:36.966700
2545 00:59:36.967241 Set Vref, RX VrefLevel [Byte0]: 33
2546 00:59:36.970320 [Byte1]: 33
2547 00:59:36.974696
2548 00:59:36.975253 Set Vref, RX VrefLevel [Byte0]: 34
2549 00:59:36.977840 [Byte1]: 34
2550 00:59:36.983237
2551 00:59:36.983790 Set Vref, RX VrefLevel [Byte0]: 35
2552 00:59:36.985787 [Byte1]: 35
2553 00:59:36.990703
2554 00:59:36.991258 Set Vref, RX VrefLevel [Byte0]: 36
2555 00:59:36.993774 [Byte1]: 36
2556 00:59:36.998390
2557 00:59:36.998944 Set Vref, RX VrefLevel [Byte0]: 37
2558 00:59:37.002021 [Byte1]: 37
2559 00:59:37.006651
2560 00:59:37.007207 Set Vref, RX VrefLevel [Byte0]: 38
2561 00:59:37.010030 [Byte1]: 38
2562 00:59:37.014569
2563 00:59:37.015176 Set Vref, RX VrefLevel [Byte0]: 39
2564 00:59:37.017842 [Byte1]: 39
2565 00:59:37.022011
2566 00:59:37.022569 Set Vref, RX VrefLevel [Byte0]: 40
2567 00:59:37.025856 [Byte1]: 40
2568 00:59:37.031172
2569 00:59:37.031731 Set Vref, RX VrefLevel [Byte0]: 41
2570 00:59:37.033196 [Byte1]: 41
2571 00:59:37.038144
2572 00:59:37.038702 Set Vref, RX VrefLevel [Byte0]: 42
2573 00:59:37.041271 [Byte1]: 42
2574 00:59:37.046225
2575 00:59:37.046784 Set Vref, RX VrefLevel [Byte0]: 43
2576 00:59:37.049349 [Byte1]: 43
2577 00:59:37.053712
2578 00:59:37.054268 Set Vref, RX VrefLevel [Byte0]: 44
2579 00:59:37.056953 [Byte1]: 44
2580 00:59:37.062387
2581 00:59:37.062947 Set Vref, RX VrefLevel [Byte0]: 45
2582 00:59:37.065113 [Byte1]: 45
2583 00:59:37.069610
2584 00:59:37.070168 Set Vref, RX VrefLevel [Byte0]: 46
2585 00:59:37.072932 [Byte1]: 46
2586 00:59:37.077617
2587 00:59:37.078173 Set Vref, RX VrefLevel [Byte0]: 47
2588 00:59:37.081264 [Byte1]: 47
2589 00:59:37.085629
2590 00:59:37.086367 Set Vref, RX VrefLevel [Byte0]: 48
2591 00:59:37.089052 [Byte1]: 48
2592 00:59:37.093853
2593 00:59:37.094412 Set Vref, RX VrefLevel [Byte0]: 49
2594 00:59:37.096976 [Byte1]: 49
2595 00:59:37.101339
2596 00:59:37.101890 Set Vref, RX VrefLevel [Byte0]: 50
2597 00:59:37.104760 [Byte1]: 50
2598 00:59:37.109230
2599 00:59:37.109782 Set Vref, RX VrefLevel [Byte0]: 51
2600 00:59:37.112604 [Byte1]: 51
2601 00:59:37.118127
2602 00:59:37.118684 Set Vref, RX VrefLevel [Byte0]: 52
2603 00:59:37.120812 [Byte1]: 52
2604 00:59:37.125374
2605 00:59:37.125841 Set Vref, RX VrefLevel [Byte0]: 53
2606 00:59:37.129026 [Byte1]: 53
2607 00:59:37.132886
2608 00:59:37.133502 Set Vref, RX VrefLevel [Byte0]: 54
2609 00:59:37.136486 [Byte1]: 54
2610 00:59:37.140791
2611 00:59:37.141349 Set Vref, RX VrefLevel [Byte0]: 55
2612 00:59:37.144480 [Byte1]: 55
2613 00:59:37.149269
2614 00:59:37.149822 Set Vref, RX VrefLevel [Byte0]: 56
2615 00:59:37.152128 [Byte1]: 56
2616 00:59:37.157439
2617 00:59:37.157907 Set Vref, RX VrefLevel [Byte0]: 57
2618 00:59:37.160171 [Byte1]: 57
2619 00:59:37.165335
2620 00:59:37.165889 Set Vref, RX VrefLevel [Byte0]: 58
2621 00:59:37.168083 [Byte1]: 58
2622 00:59:37.172827
2623 00:59:37.173292 Set Vref, RX VrefLevel [Byte0]: 59
2624 00:59:37.175969 [Byte1]: 59
2625 00:59:37.181075
2626 00:59:37.181633 Set Vref, RX VrefLevel [Byte0]: 60
2627 00:59:37.184067 [Byte1]: 60
2628 00:59:37.188673
2629 00:59:37.189255 Set Vref, RX VrefLevel [Byte0]: 61
2630 00:59:37.192533 [Byte1]: 61
2631 00:59:37.196632
2632 00:59:37.197378 Set Vref, RX VrefLevel [Byte0]: 62
2633 00:59:37.199359 [Byte1]: 62
2634 00:59:37.204839
2635 00:59:37.205555 Set Vref, RX VrefLevel [Byte0]: 63
2636 00:59:37.208012 [Byte1]: 63
2637 00:59:37.212170
2638 00:59:37.212767 Set Vref, RX VrefLevel [Byte0]: 64
2639 00:59:37.215744 [Byte1]: 64
2640 00:59:37.220485
2641 00:59:37.221107 Set Vref, RX VrefLevel [Byte0]: 65
2642 00:59:37.223966 [Byte1]: 65
2643 00:59:37.227945
2644 00:59:37.228405 Set Vref, RX VrefLevel [Byte0]: 66
2645 00:59:37.231572 [Byte1]: 66
2646 00:59:37.235752
2647 00:59:37.236309 Final RX Vref Byte 0 = 48 to rank0
2648 00:59:37.239688 Final RX Vref Byte 1 = 50 to rank0
2649 00:59:37.243589 Final RX Vref Byte 0 = 48 to rank1
2650 00:59:37.246207 Final RX Vref Byte 1 = 50 to rank1==
2651 00:59:37.249062 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 00:59:37.255958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2653 00:59:37.256559 ==
2654 00:59:37.257000 DQS Delay:
2655 00:59:37.257355 DQS0 = 0, DQS1 = 0
2656 00:59:37.259392 DQM Delay:
2657 00:59:37.259945 DQM0 = 114, DQM1 = 106
2658 00:59:37.262795 DQ Delay:
2659 00:59:37.266115 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =110
2660 00:59:37.269402 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2661 00:59:37.272845 DQ8 =96, DQ9 =88, DQ10 =106, DQ11 =98
2662 00:59:37.275840 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2663 00:59:37.276403
2664 00:59:37.276823
2665 00:59:37.283264 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2666 00:59:37.286488 CH0 RK0: MR19=404, MR18=808
2667 00:59:37.293433 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2668 00:59:37.293995
2669 00:59:37.296589 ----->DramcWriteLeveling(PI) begin...
2670 00:59:37.297251 ==
2671 00:59:37.299030 Dram Type= 6, Freq= 0, CH_0, rank 1
2672 00:59:37.302622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2673 00:59:37.303183 ==
2674 00:59:37.306016 Write leveling (Byte 0): 27 => 27
2675 00:59:37.308930 Write leveling (Byte 1): 25 => 25
2676 00:59:37.312639 DramcWriteLeveling(PI) end<-----
2677 00:59:37.313272
2678 00:59:37.313642 ==
2679 00:59:37.316154 Dram Type= 6, Freq= 0, CH_0, rank 1
2680 00:59:37.322556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2681 00:59:37.323117 ==
2682 00:59:37.323485 [Gating] SW mode calibration
2683 00:59:37.332919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2684 00:59:37.335929 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2685 00:59:37.339749 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2686 00:59:37.345619 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2687 00:59:37.348799 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2688 00:59:37.352677 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2689 00:59:37.359080 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2690 00:59:37.362521 0 11 20 | B1->B0 | 2f2f 2727 | 1 1 | (1 0) (0 0)
2691 00:59:37.365801 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 00:59:37.372494 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 00:59:37.376164 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2694 00:59:37.379553 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2695 00:59:37.386482 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2696 00:59:37.388987 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 00:59:37.393025 0 12 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2698 00:59:37.399706 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2699 00:59:37.402945 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 00:59:37.406948 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2701 00:59:37.412551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2702 00:59:37.415453 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2703 00:59:37.419019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2704 00:59:37.425823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 00:59:37.429234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2706 00:59:37.432428 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2707 00:59:37.436423 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 00:59:37.442504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 00:59:37.445795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 00:59:37.448752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 00:59:37.455677 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 00:59:37.459848 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 00:59:37.462392 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 00:59:37.468618 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 00:59:37.472371 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 00:59:37.475559 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 00:59:37.482563 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 00:59:37.485546 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 00:59:37.488972 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 00:59:37.494969 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 00:59:37.498662 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2722 00:59:37.502002 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2723 00:59:37.505931 Total UI for P1: 0, mck2ui 16
2724 00:59:37.508344 best dqsien dly found for B0: ( 0, 15, 16)
2725 00:59:37.516121 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2726 00:59:37.516678 Total UI for P1: 0, mck2ui 16
2727 00:59:37.519673 best dqsien dly found for B1: ( 0, 15, 20)
2728 00:59:37.525528 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2729 00:59:37.528819 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2730 00:59:37.529291
2731 00:59:37.532102 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2732 00:59:37.535395 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2733 00:59:37.539828 [Gating] SW calibration Done
2734 00:59:37.540388 ==
2735 00:59:37.542170 Dram Type= 6, Freq= 0, CH_0, rank 1
2736 00:59:37.545036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2737 00:59:37.545503 ==
2738 00:59:37.548574 RX Vref Scan: 0
2739 00:59:37.549187
2740 00:59:37.549559 RX Vref 0 -> 0, step: 1
2741 00:59:37.549905
2742 00:59:37.552798 RX Delay -40 -> 252, step: 8
2743 00:59:37.554958 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2744 00:59:37.562103 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2745 00:59:37.565483 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2746 00:59:37.568789 iDelay=200, Bit 3, Center 103 (32 ~ 175) 144
2747 00:59:37.572300 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2748 00:59:37.575282 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2749 00:59:37.581945 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2750 00:59:37.585255 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2751 00:59:37.588791 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2752 00:59:37.591927 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2753 00:59:37.594764 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2754 00:59:37.598595 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2755 00:59:37.605126 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2756 00:59:37.608481 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2757 00:59:37.612459 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2758 00:59:37.615088 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2759 00:59:37.615648 ==
2760 00:59:37.618966 Dram Type= 6, Freq= 0, CH_0, rank 1
2761 00:59:37.626205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2762 00:59:37.626766 ==
2763 00:59:37.627156 DQS Delay:
2764 00:59:37.628827 DQS0 = 0, DQS1 = 0
2765 00:59:37.629290 DQM Delay:
2766 00:59:37.629654 DQM0 = 112, DQM1 = 106
2767 00:59:37.632137 DQ Delay:
2768 00:59:37.635281 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =103
2769 00:59:37.638204 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2770 00:59:37.641647 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2771 00:59:37.645722 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2772 00:59:37.646189
2773 00:59:37.646552
2774 00:59:37.646890 ==
2775 00:59:37.648821 Dram Type= 6, Freq= 0, CH_0, rank 1
2776 00:59:37.651852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2777 00:59:37.655176 ==
2778 00:59:37.655782
2779 00:59:37.656155
2780 00:59:37.656498 TX Vref Scan disable
2781 00:59:37.658657 == TX Byte 0 ==
2782 00:59:37.662445 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2783 00:59:37.665303 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2784 00:59:37.668268 == TX Byte 1 ==
2785 00:59:37.671944 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2786 00:59:37.675393 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2787 00:59:37.675957 ==
2788 00:59:37.679159 Dram Type= 6, Freq= 0, CH_0, rank 1
2789 00:59:37.685902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2790 00:59:37.686463 ==
2791 00:59:37.695942 TX Vref=22, minBit 9, minWin=25, winSum=418
2792 00:59:37.699357 TX Vref=24, minBit 9, minWin=25, winSum=421
2793 00:59:37.703084 TX Vref=26, minBit 10, minWin=25, winSum=425
2794 00:59:37.706161 TX Vref=28, minBit 10, minWin=25, winSum=428
2795 00:59:37.709509 TX Vref=30, minBit 8, minWin=26, winSum=434
2796 00:59:37.716143 TX Vref=32, minBit 8, minWin=26, winSum=432
2797 00:59:37.719717 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2798 00:59:37.720280
2799 00:59:37.723020 Final TX Range 1 Vref 30
2800 00:59:37.723577
2801 00:59:37.723945 ==
2802 00:59:37.725907 Dram Type= 6, Freq= 0, CH_0, rank 1
2803 00:59:37.729301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2804 00:59:37.729769 ==
2805 00:59:37.732280
2806 00:59:37.732779
2807 00:59:37.733171 TX Vref Scan disable
2808 00:59:37.736095 == TX Byte 0 ==
2809 00:59:37.739339 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2810 00:59:37.742979 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2811 00:59:37.746156 == TX Byte 1 ==
2812 00:59:37.748899 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2813 00:59:37.752519 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2814 00:59:37.756177
2815 00:59:37.756781 [DATLAT]
2816 00:59:37.757162 Freq=1200, CH0 RK1
2817 00:59:37.757507
2818 00:59:37.759414 DATLAT Default: 0xc
2819 00:59:37.759970 0, 0xFFFF, sum = 0
2820 00:59:37.762546 1, 0xFFFF, sum = 0
2821 00:59:37.763017 2, 0xFFFF, sum = 0
2822 00:59:37.765592 3, 0xFFFF, sum = 0
2823 00:59:37.766111 4, 0xFFFF, sum = 0
2824 00:59:37.769019 5, 0xFFFF, sum = 0
2825 00:59:37.772749 6, 0xFFFF, sum = 0
2826 00:59:37.773318 7, 0xFFFF, sum = 0
2827 00:59:37.775665 8, 0xFFFF, sum = 0
2828 00:59:37.776228 9, 0xFFFF, sum = 0
2829 00:59:37.779726 10, 0xFFFF, sum = 0
2830 00:59:37.780291 11, 0x0, sum = 1
2831 00:59:37.782981 12, 0x0, sum = 2
2832 00:59:37.783548 13, 0x0, sum = 3
2833 00:59:37.783926 14, 0x0, sum = 4
2834 00:59:37.786771 best_step = 12
2835 00:59:37.787327
2836 00:59:37.787698 ==
2837 00:59:37.789469 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 00:59:37.792179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2839 00:59:37.792789 ==
2840 00:59:37.795889 RX Vref Scan: 0
2841 00:59:37.796450
2842 00:59:37.798909 RX Vref 0 -> 0, step: 1
2843 00:59:37.799466
2844 00:59:37.799833 RX Delay -21 -> 252, step: 4
2845 00:59:37.806155 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2846 00:59:37.809848 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2847 00:59:37.812815 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2848 00:59:37.816209 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2849 00:59:37.820053 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2850 00:59:37.826148 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2851 00:59:37.830082 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
2852 00:59:37.832847 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2853 00:59:37.836158 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2854 00:59:37.839949 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2855 00:59:37.845972 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
2856 00:59:37.849128 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2857 00:59:37.853210 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2858 00:59:37.856620 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2859 00:59:37.859561 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2860 00:59:37.866440 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2861 00:59:37.867003 ==
2862 00:59:37.869146 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 00:59:37.873183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2864 00:59:37.873744 ==
2865 00:59:37.874117 DQS Delay:
2866 00:59:37.875995 DQS0 = 0, DQS1 = 0
2867 00:59:37.876556 DQM Delay:
2868 00:59:37.879418 DQM0 = 114, DQM1 = 105
2869 00:59:37.879881 DQ Delay:
2870 00:59:37.882887 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2871 00:59:37.885772 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =122
2872 00:59:37.889318 DQ8 =92, DQ9 =90, DQ10 =112, DQ11 =96
2873 00:59:37.893945 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
2874 00:59:37.894505
2875 00:59:37.895872
2876 00:59:37.902492 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2877 00:59:37.906097 CH0 RK1: MR19=404, MR18=D0D
2878 00:59:37.909167 CH0_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2879 00:59:37.912441 [RxdqsGatingPostProcess] freq 1200
2880 00:59:37.919094 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2881 00:59:37.922741 Pre-setting of DQS Precalculation
2882 00:59:37.926533 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2883 00:59:37.929187 ==
2884 00:59:37.932308 Dram Type= 6, Freq= 0, CH_1, rank 0
2885 00:59:37.936029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2886 00:59:37.936503 ==
2887 00:59:37.938832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2888 00:59:37.945785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2889 00:59:37.955272 [CA 0] Center 37 (7~68) winsize 62
2890 00:59:37.957946 [CA 1] Center 37 (7~68) winsize 62
2891 00:59:37.961398 [CA 2] Center 34 (4~65) winsize 62
2892 00:59:37.965010 [CA 3] Center 33 (3~64) winsize 62
2893 00:59:37.967945 [CA 4] Center 32 (2~63) winsize 62
2894 00:59:37.971057 [CA 5] Center 32 (2~62) winsize 61
2895 00:59:37.971758
2896 00:59:37.974841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2897 00:59:37.975405
2898 00:59:37.977743 [CATrainingPosCal] consider 1 rank data
2899 00:59:37.981641 u2DelayCellTimex100 = 270/100 ps
2900 00:59:37.984436 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2901 00:59:37.987716 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2902 00:59:37.994429 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2903 00:59:37.997678 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2904 00:59:38.001084 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2905 00:59:38.004265 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2906 00:59:38.004771
2907 00:59:38.007959 CA PerBit enable=1, Macro0, CA PI delay=32
2908 00:59:38.008478
2909 00:59:38.010996 [CBTSetCACLKResult] CA Dly = 32
2910 00:59:38.011468 CS Dly: 5 (0~36)
2911 00:59:38.011948 ==
2912 00:59:38.014789 Dram Type= 6, Freq= 0, CH_1, rank 1
2913 00:59:38.021788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2914 00:59:38.022260 ==
2915 00:59:38.024615 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2916 00:59:38.030991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2917 00:59:38.039376 [CA 0] Center 37 (7~68) winsize 62
2918 00:59:38.043399 [CA 1] Center 37 (7~68) winsize 62
2919 00:59:38.046183 [CA 2] Center 34 (3~65) winsize 63
2920 00:59:38.049507 [CA 3] Center 33 (3~64) winsize 62
2921 00:59:38.052570 [CA 4] Center 32 (2~63) winsize 62
2922 00:59:38.056054 [CA 5] Center 32 (2~63) winsize 62
2923 00:59:38.056211
2924 00:59:38.059199 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2925 00:59:38.059356
2926 00:59:38.063220 [CATrainingPosCal] consider 2 rank data
2927 00:59:38.065929 u2DelayCellTimex100 = 270/100 ps
2928 00:59:38.069428 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2929 00:59:38.072491 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2930 00:59:38.079542 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2931 00:59:38.082559 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2932 00:59:38.085997 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2933 00:59:38.089363 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2934 00:59:38.089520
2935 00:59:38.092941 CA PerBit enable=1, Macro0, CA PI delay=32
2936 00:59:38.093099
2937 00:59:38.095910 [CBTSetCACLKResult] CA Dly = 32
2938 00:59:38.096067 CS Dly: 6 (0~38)
2939 00:59:38.096192
2940 00:59:38.099195 ----->DramcWriteLeveling(PI) begin...
2941 00:59:38.102549 ==
2942 00:59:38.105953 Dram Type= 6, Freq= 0, CH_1, rank 0
2943 00:59:38.109226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2944 00:59:38.109386 ==
2945 00:59:38.113233 Write leveling (Byte 0): 20 => 20
2946 00:59:38.115653 Write leveling (Byte 1): 20 => 20
2947 00:59:38.119401 DramcWriteLeveling(PI) end<-----
2948 00:59:38.119564
2949 00:59:38.119727 ==
2950 00:59:38.122679 Dram Type= 6, Freq= 0, CH_1, rank 0
2951 00:59:38.127280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2952 00:59:38.127418 ==
2953 00:59:38.129331 [Gating] SW mode calibration
2954 00:59:38.135853 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2955 00:59:38.139439 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2956 00:59:38.146095 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 00:59:38.149026 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 00:59:38.152748 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 00:59:38.159896 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2960 00:59:38.162343 0 11 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 1)
2961 00:59:38.165673 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 00:59:38.172266 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 00:59:38.176517 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 00:59:38.178917 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 00:59:38.185765 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 00:59:38.189302 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 00:59:38.193115 0 12 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2968 00:59:38.199561 0 12 16 | B1->B0 | 3535 4444 | 1 0 | (1 1) (0 0)
2969 00:59:38.202565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 00:59:38.206533 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 00:59:38.212836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:59:38.215431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 00:59:38.218969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 00:59:38.225644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 00:59:38.229028 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 00:59:38.232391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2977 00:59:38.239607 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2978 00:59:38.242682 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 00:59:38.246250 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:59:38.252547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:59:38.255921 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 00:59:38.258980 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 00:59:38.265802 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:59:38.269272 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:59:38.272477 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:59:38.276279 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:59:38.282566 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:59:38.286173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:59:38.289262 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:59:38.295593 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:59:38.299661 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:59:38.303078 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2993 00:59:38.309971 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2994 00:59:38.313646 Total UI for P1: 0, mck2ui 16
2995 00:59:38.316177 best dqsien dly found for B0: ( 0, 15, 16)
2996 00:59:38.319218 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2997 00:59:38.322638 Total UI for P1: 0, mck2ui 16
2998 00:59:38.326324 best dqsien dly found for B1: ( 0, 15, 20)
2999 00:59:38.329429 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3000 00:59:38.333858 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3001 00:59:38.334446
3002 00:59:38.335817 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3003 00:59:38.338901 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3004 00:59:38.342902 [Gating] SW calibration Done
3005 00:59:38.343460 ==
3006 00:59:38.345512 Dram Type= 6, Freq= 0, CH_1, rank 0
3007 00:59:38.349169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3008 00:59:38.352341 ==
3009 00:59:38.352765 RX Vref Scan: 0
3010 00:59:38.353123
3011 00:59:38.355883 RX Vref 0 -> 0, step: 1
3012 00:59:38.356486
3013 00:59:38.360491 RX Delay -40 -> 252, step: 8
3014 00:59:38.363899 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3015 00:59:38.365742 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3016 00:59:38.369549 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3017 00:59:38.372625 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3018 00:59:38.379493 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3019 00:59:38.382521 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3020 00:59:38.385566 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3021 00:59:38.389523 iDelay=208, Bit 7, Center 111 (32 ~ 191) 160
3022 00:59:38.392413 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3023 00:59:38.396107 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3024 00:59:38.402801 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3025 00:59:38.405681 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3026 00:59:38.409725 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3027 00:59:38.412746 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3028 00:59:38.418974 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3029 00:59:38.423273 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3030 00:59:38.423833 ==
3031 00:59:38.425727 Dram Type= 6, Freq= 0, CH_1, rank 0
3032 00:59:38.429203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3033 00:59:38.429672 ==
3034 00:59:38.432032 DQS Delay:
3035 00:59:38.432500 DQS0 = 0, DQS1 = 0
3036 00:59:38.432936 DQM Delay:
3037 00:59:38.435484 DQM0 = 115, DQM1 = 108
3038 00:59:38.436017 DQ Delay:
3039 00:59:38.438898 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3040 00:59:38.442095 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =111
3041 00:59:38.445842 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3042 00:59:38.452073 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3043 00:59:38.452534
3044 00:59:38.453009
3045 00:59:38.453391 ==
3046 00:59:38.455649 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 00:59:38.459088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3048 00:59:38.459645 ==
3049 00:59:38.460007
3050 00:59:38.460342
3051 00:59:38.462149 TX Vref Scan disable
3052 00:59:38.462706 == TX Byte 0 ==
3053 00:59:38.469502 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3054 00:59:38.472604 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3055 00:59:38.473224 == TX Byte 1 ==
3056 00:59:38.479121 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3057 00:59:38.482603 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3058 00:59:38.483163 ==
3059 00:59:38.485544 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 00:59:38.489222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3061 00:59:38.489781 ==
3062 00:59:38.501167 TX Vref=22, minBit 3, minWin=25, winSum=414
3063 00:59:38.504789 TX Vref=24, minBit 9, minWin=25, winSum=419
3064 00:59:38.507594 TX Vref=26, minBit 0, minWin=26, winSum=422
3065 00:59:38.511164 TX Vref=28, minBit 0, minWin=26, winSum=427
3066 00:59:38.514333 TX Vref=30, minBit 0, minWin=26, winSum=427
3067 00:59:38.518118 TX Vref=32, minBit 0, minWin=26, winSum=427
3068 00:59:38.524442 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
3069 00:59:38.525046
3070 00:59:38.527914 Final TX Range 1 Vref 28
3071 00:59:38.528376
3072 00:59:38.528780 ==
3073 00:59:38.531879 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 00:59:38.534925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3075 00:59:38.535488 ==
3076 00:59:38.535855
3077 00:59:38.538073
3078 00:59:38.538532 TX Vref Scan disable
3079 00:59:38.541106 == TX Byte 0 ==
3080 00:59:38.544869 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3081 00:59:38.547959 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3082 00:59:38.550986 == TX Byte 1 ==
3083 00:59:38.554723 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3084 00:59:38.558349 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3085 00:59:38.558828
3086 00:59:38.560872 [DATLAT]
3087 00:59:38.561425 Freq=1200, CH1 RK0
3088 00:59:38.561834
3089 00:59:38.564504 DATLAT Default: 0xd
3090 00:59:38.565121 0, 0xFFFF, sum = 0
3091 00:59:38.568796 1, 0xFFFF, sum = 0
3092 00:59:38.569491 2, 0xFFFF, sum = 0
3093 00:59:38.571251 3, 0xFFFF, sum = 0
3094 00:59:38.571716 4, 0xFFFF, sum = 0
3095 00:59:38.574454 5, 0xFFFF, sum = 0
3096 00:59:38.574971 6, 0xFFFF, sum = 0
3097 00:59:38.577658 7, 0xFFFF, sum = 0
3098 00:59:38.578220 8, 0xFFFF, sum = 0
3099 00:59:38.581402 9, 0xFFFF, sum = 0
3100 00:59:38.584454 10, 0xFFFF, sum = 0
3101 00:59:38.585059 11, 0x0, sum = 1
3102 00:59:38.585434 12, 0x0, sum = 2
3103 00:59:38.587989 13, 0x0, sum = 3
3104 00:59:38.588453 14, 0x0, sum = 4
3105 00:59:38.591118 best_step = 12
3106 00:59:38.591674
3107 00:59:38.592040 ==
3108 00:59:38.594777 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 00:59:38.597938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3110 00:59:38.598496 ==
3111 00:59:38.601059 RX Vref Scan: 1
3112 00:59:38.601598
3113 00:59:38.602139 Set Vref Range= 32 -> 127
3114 00:59:38.604102
3115 00:59:38.604558 RX Vref 32 -> 127, step: 1
3116 00:59:38.605033
3117 00:59:38.607592 RX Delay -29 -> 252, step: 4
3118 00:59:38.608051
3119 00:59:38.612238 Set Vref, RX VrefLevel [Byte0]: 32
3120 00:59:38.614300 [Byte1]: 32
3121 00:59:38.617442
3122 00:59:38.617899 Set Vref, RX VrefLevel [Byte0]: 33
3123 00:59:38.620624 [Byte1]: 33
3124 00:59:38.625406
3125 00:59:38.625962 Set Vref, RX VrefLevel [Byte0]: 34
3126 00:59:38.628680 [Byte1]: 34
3127 00:59:38.633689
3128 00:59:38.634149 Set Vref, RX VrefLevel [Byte0]: 35
3129 00:59:38.636901 [Byte1]: 35
3130 00:59:38.642038
3131 00:59:38.642592 Set Vref, RX VrefLevel [Byte0]: 36
3132 00:59:38.644241 [Byte1]: 36
3133 00:59:38.649459
3134 00:59:38.650013 Set Vref, RX VrefLevel [Byte0]: 37
3135 00:59:38.652515 [Byte1]: 37
3136 00:59:38.657307
3137 00:59:38.657767 Set Vref, RX VrefLevel [Byte0]: 38
3138 00:59:38.660825 [Byte1]: 38
3139 00:59:38.664939
3140 00:59:38.668540 Set Vref, RX VrefLevel [Byte0]: 39
3141 00:59:38.671765 [Byte1]: 39
3142 00:59:38.672226
3143 00:59:38.675554 Set Vref, RX VrefLevel [Byte0]: 40
3144 00:59:38.678055 [Byte1]: 40
3145 00:59:38.678616
3146 00:59:38.682328 Set Vref, RX VrefLevel [Byte0]: 41
3147 00:59:38.685178 [Byte1]: 41
3148 00:59:38.689316
3149 00:59:38.689874 Set Vref, RX VrefLevel [Byte0]: 42
3150 00:59:38.693118 [Byte1]: 42
3151 00:59:38.697706
3152 00:59:38.698267 Set Vref, RX VrefLevel [Byte0]: 43
3153 00:59:38.700855 [Byte1]: 43
3154 00:59:38.705186
3155 00:59:38.705640 Set Vref, RX VrefLevel [Byte0]: 44
3156 00:59:38.708133 [Byte1]: 44
3157 00:59:38.713186
3158 00:59:38.713736 Set Vref, RX VrefLevel [Byte0]: 45
3159 00:59:38.716200 [Byte1]: 45
3160 00:59:38.720943
3161 00:59:38.721493 Set Vref, RX VrefLevel [Byte0]: 46
3162 00:59:38.724077 [Byte1]: 46
3163 00:59:38.729199
3164 00:59:38.729653 Set Vref, RX VrefLevel [Byte0]: 47
3165 00:59:38.732296 [Byte1]: 47
3166 00:59:38.736686
3167 00:59:38.737191 Set Vref, RX VrefLevel [Byte0]: 48
3168 00:59:38.739798 [Byte1]: 48
3169 00:59:38.744495
3170 00:59:38.745108 Set Vref, RX VrefLevel [Byte0]: 49
3171 00:59:38.748083 [Byte1]: 49
3172 00:59:38.752815
3173 00:59:38.753370 Set Vref, RX VrefLevel [Byte0]: 50
3174 00:59:38.755760 [Byte1]: 50
3175 00:59:38.760504
3176 00:59:38.761029 Set Vref, RX VrefLevel [Byte0]: 51
3177 00:59:38.764584 [Byte1]: 51
3178 00:59:38.768289
3179 00:59:38.768782 Set Vref, RX VrefLevel [Byte0]: 52
3180 00:59:38.771719 [Byte1]: 52
3181 00:59:38.776204
3182 00:59:38.776656 Set Vref, RX VrefLevel [Byte0]: 53
3183 00:59:38.779903 [Byte1]: 53
3184 00:59:38.785144
3185 00:59:38.785698 Set Vref, RX VrefLevel [Byte0]: 54
3186 00:59:38.788071 [Byte1]: 54
3187 00:59:38.792637
3188 00:59:38.793145 Set Vref, RX VrefLevel [Byte0]: 55
3189 00:59:38.796543 [Byte1]: 55
3190 00:59:38.800923
3191 00:59:38.801382 Set Vref, RX VrefLevel [Byte0]: 56
3192 00:59:38.804010 [Byte1]: 56
3193 00:59:38.808398
3194 00:59:38.808927 Set Vref, RX VrefLevel [Byte0]: 57
3195 00:59:38.811746 [Byte1]: 57
3196 00:59:38.817377
3197 00:59:38.817928 Set Vref, RX VrefLevel [Byte0]: 58
3198 00:59:38.820036 [Byte1]: 58
3199 00:59:38.824431
3200 00:59:38.825049 Set Vref, RX VrefLevel [Byte0]: 59
3201 00:59:38.828309 [Byte1]: 59
3202 00:59:38.832828
3203 00:59:38.833565 Set Vref, RX VrefLevel [Byte0]: 60
3204 00:59:38.835636 [Byte1]: 60
3205 00:59:38.840084
3206 00:59:38.840643 Set Vref, RX VrefLevel [Byte0]: 61
3207 00:59:38.844381 [Byte1]: 61
3208 00:59:38.848872
3209 00:59:38.849435 Set Vref, RX VrefLevel [Byte0]: 62
3210 00:59:38.851427 [Byte1]: 62
3211 00:59:38.856781
3212 00:59:38.857352 Set Vref, RX VrefLevel [Byte0]: 63
3213 00:59:38.859176 [Byte1]: 63
3214 00:59:38.864149
3215 00:59:38.864703 Set Vref, RX VrefLevel [Byte0]: 64
3216 00:59:38.867346 [Byte1]: 64
3217 00:59:38.872159
3218 00:59:38.872615 Set Vref, RX VrefLevel [Byte0]: 65
3219 00:59:38.875755 [Byte1]: 65
3220 00:59:38.879936
3221 00:59:38.880493 Final RX Vref Byte 0 = 57 to rank0
3222 00:59:38.883685 Final RX Vref Byte 1 = 48 to rank0
3223 00:59:38.886808 Final RX Vref Byte 0 = 57 to rank1
3224 00:59:38.890138 Final RX Vref Byte 1 = 48 to rank1==
3225 00:59:38.893246 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 00:59:38.900079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3227 00:59:38.900636 ==
3228 00:59:38.901065 DQS Delay:
3229 00:59:38.902951 DQS0 = 0, DQS1 = 0
3230 00:59:38.903407 DQM Delay:
3231 00:59:38.903766 DQM0 = 115, DQM1 = 104
3232 00:59:38.906405 DQ Delay:
3233 00:59:38.910537 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3234 00:59:38.913474 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3235 00:59:38.916461 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3236 00:59:38.920234 DQ12 =112, DQ13 =114, DQ14 =114, DQ15 =114
3237 00:59:38.920690
3238 00:59:38.921100
3239 00:59:38.926536 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3240 00:59:38.929346 CH1 RK0: MR19=404, MR18=1717
3241 00:59:38.936596 CH1_RK0: MR19=0x404, MR18=0x1717, DQSOSC=401, MR23=63, INC=40, DEC=27
3242 00:59:38.937120
3243 00:59:38.939690 ----->DramcWriteLeveling(PI) begin...
3244 00:59:38.940254 ==
3245 00:59:38.943218 Dram Type= 6, Freq= 0, CH_1, rank 1
3246 00:59:38.947002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3247 00:59:38.949613 ==
3248 00:59:38.950069 Write leveling (Byte 0): 20 => 20
3249 00:59:38.953416 Write leveling (Byte 1): 22 => 22
3250 00:59:38.957375 DramcWriteLeveling(PI) end<-----
3251 00:59:38.957927
3252 00:59:38.958287 ==
3253 00:59:38.959701 Dram Type= 6, Freq= 0, CH_1, rank 1
3254 00:59:38.966853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3255 00:59:38.967449 ==
3256 00:59:38.967852 [Gating] SW mode calibration
3257 00:59:38.977124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3258 00:59:38.979604 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3259 00:59:38.983139 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3260 00:59:38.989710 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3261 00:59:38.992989 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3262 00:59:38.996687 0 11 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3263 00:59:39.003640 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3264 00:59:39.006422 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3265 00:59:39.009411 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 00:59:39.016424 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 00:59:39.019759 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 00:59:39.023003 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 00:59:39.029756 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3270 00:59:39.033633 0 12 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
3271 00:59:39.036476 0 12 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3272 00:59:39.043509 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 00:59:39.046592 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 00:59:39.050765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 00:59:39.056973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 00:59:39.059925 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 00:59:39.063614 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 00:59:39.069791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3279 00:59:39.073036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3280 00:59:39.077072 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 00:59:39.080374 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 00:59:39.087328 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 00:59:39.090222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 00:59:39.093135 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 00:59:39.100554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 00:59:39.103099 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 00:59:39.106818 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 00:59:39.113658 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 00:59:39.117083 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 00:59:39.119966 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 00:59:39.126595 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 00:59:39.129961 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 00:59:39.133028 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 00:59:39.139605 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3295 00:59:39.143298 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3296 00:59:39.147355 Total UI for P1: 0, mck2ui 16
3297 00:59:39.149380 best dqsien dly found for B0: ( 0, 15, 12)
3298 00:59:39.153512 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3299 00:59:39.156579 Total UI for P1: 0, mck2ui 16
3300 00:59:39.160145 best dqsien dly found for B1: ( 0, 15, 16)
3301 00:59:39.163391 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3302 00:59:39.166895 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3303 00:59:39.167321
3304 00:59:39.169827 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3305 00:59:39.177002 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3306 00:59:39.177635 [Gating] SW calibration Done
3307 00:59:39.177939 ==
3308 00:59:39.181148 Dram Type= 6, Freq= 0, CH_1, rank 1
3309 00:59:39.186485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3310 00:59:39.186944 ==
3311 00:59:39.187301 RX Vref Scan: 0
3312 00:59:39.187812
3313 00:59:39.189476 RX Vref 0 -> 0, step: 1
3314 00:59:39.189928
3315 00:59:39.193472 RX Delay -40 -> 252, step: 8
3316 00:59:39.196766 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3317 00:59:39.199795 iDelay=208, Bit 1, Center 111 (32 ~ 191) 160
3318 00:59:39.203496 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3319 00:59:39.209567 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3320 00:59:39.213729 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3321 00:59:39.217156 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3322 00:59:39.219961 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3323 00:59:39.223333 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3324 00:59:39.229936 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3325 00:59:39.232828 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3326 00:59:39.236023 iDelay=208, Bit 10, Center 103 (32 ~ 175) 144
3327 00:59:39.240335 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3328 00:59:39.243512 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3329 00:59:39.249692 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3330 00:59:39.252871 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3331 00:59:39.255910 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3332 00:59:39.256319 ==
3333 00:59:39.259496 Dram Type= 6, Freq= 0, CH_1, rank 1
3334 00:59:39.262888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3335 00:59:39.263344 ==
3336 00:59:39.266601 DQS Delay:
3337 00:59:39.267153 DQS0 = 0, DQS1 = 0
3338 00:59:39.269501 DQM Delay:
3339 00:59:39.269951 DQM0 = 116, DQM1 = 105
3340 00:59:39.270308 DQ Delay:
3341 00:59:39.272822 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3342 00:59:39.280617 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3343 00:59:39.283257 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3344 00:59:39.286235 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3345 00:59:39.286687
3346 00:59:39.287040
3347 00:59:39.287371 ==
3348 00:59:39.290005 Dram Type= 6, Freq= 0, CH_1, rank 1
3349 00:59:39.293480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3350 00:59:39.294038 ==
3351 00:59:39.294396
3352 00:59:39.294727
3353 00:59:39.295903 TX Vref Scan disable
3354 00:59:39.296355 == TX Byte 0 ==
3355 00:59:39.303676 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3356 00:59:39.306767 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3357 00:59:39.307325 == TX Byte 1 ==
3358 00:59:39.313347 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3359 00:59:39.316540 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3360 00:59:39.317152 ==
3361 00:59:39.319553 Dram Type= 6, Freq= 0, CH_1, rank 1
3362 00:59:39.322999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3363 00:59:39.323455 ==
3364 00:59:39.335535 TX Vref=22, minBit 9, minWin=25, winSum=423
3365 00:59:39.338855 TX Vref=24, minBit 4, minWin=26, winSum=428
3366 00:59:39.342250 TX Vref=26, minBit 4, minWin=26, winSum=429
3367 00:59:39.345414 TX Vref=28, minBit 3, minWin=26, winSum=430
3368 00:59:39.349341 TX Vref=30, minBit 8, minWin=26, winSum=435
3369 00:59:39.355338 TX Vref=32, minBit 8, minWin=26, winSum=432
3370 00:59:39.358611 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3371 00:59:39.359065
3372 00:59:39.362050 Final TX Range 1 Vref 30
3373 00:59:39.362619
3374 00:59:39.362975 ==
3375 00:59:39.365809 Dram Type= 6, Freq= 0, CH_1, rank 1
3376 00:59:39.368658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3377 00:59:39.369155 ==
3378 00:59:39.372041
3379 00:59:39.372490
3380 00:59:39.372894 TX Vref Scan disable
3381 00:59:39.375704 == TX Byte 0 ==
3382 00:59:39.378786 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3383 00:59:39.382138 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3384 00:59:39.385369 == TX Byte 1 ==
3385 00:59:39.388591 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3386 00:59:39.392100 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3387 00:59:39.396041
3388 00:59:39.396587 [DATLAT]
3389 00:59:39.397009 Freq=1200, CH1 RK1
3390 00:59:39.397348
3391 00:59:39.399618 DATLAT Default: 0xc
3392 00:59:39.400165 0, 0xFFFF, sum = 0
3393 00:59:39.402058 1, 0xFFFF, sum = 0
3394 00:59:39.402517 2, 0xFFFF, sum = 0
3395 00:59:39.406112 3, 0xFFFF, sum = 0
3396 00:59:39.406667 4, 0xFFFF, sum = 0
3397 00:59:39.409325 5, 0xFFFF, sum = 0
3398 00:59:39.412840 6, 0xFFFF, sum = 0
3399 00:59:39.413398 7, 0xFFFF, sum = 0
3400 00:59:39.416318 8, 0xFFFF, sum = 0
3401 00:59:39.416924 9, 0xFFFF, sum = 0
3402 00:59:39.419260 10, 0xFFFF, sum = 0
3403 00:59:39.419820 11, 0x0, sum = 1
3404 00:59:39.422351 12, 0x0, sum = 2
3405 00:59:39.423097 13, 0x0, sum = 3
3406 00:59:39.423710 14, 0x0, sum = 4
3407 00:59:39.426299 best_step = 12
3408 00:59:39.426926
3409 00:59:39.427497 ==
3410 00:59:39.428521 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 00:59:39.432403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3412 00:59:39.432920 ==
3413 00:59:39.435434 RX Vref Scan: 0
3414 00:59:39.435981
3415 00:59:39.438559 RX Vref 0 -> 0, step: 1
3416 00:59:39.439021
3417 00:59:39.439388 RX Delay -29 -> 252, step: 4
3418 00:59:39.445684 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3419 00:59:39.449455 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3420 00:59:39.452316 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3421 00:59:39.455692 iDelay=199, Bit 3, Center 114 (47 ~ 182) 136
3422 00:59:39.458971 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3423 00:59:39.465560 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3424 00:59:39.469137 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3425 00:59:39.472321 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3426 00:59:39.477413 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3427 00:59:39.479844 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3428 00:59:39.486012 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3429 00:59:39.489106 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3430 00:59:39.492794 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3431 00:59:39.495753 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3432 00:59:39.498825 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3433 00:59:39.506323 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3434 00:59:39.506897 ==
3435 00:59:39.508824 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 00:59:39.512794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3437 00:59:39.513367 ==
3438 00:59:39.513737 DQS Delay:
3439 00:59:39.515668 DQS0 = 0, DQS1 = 0
3440 00:59:39.516231 DQM Delay:
3441 00:59:39.519291 DQM0 = 115, DQM1 = 104
3442 00:59:39.519861 DQ Delay:
3443 00:59:39.522245 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3444 00:59:39.525668 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =114
3445 00:59:39.529178 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3446 00:59:39.532146 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3447 00:59:39.532741
3448 00:59:39.533137
3449 00:59:39.542797 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3450 00:59:39.545658 CH1 RK1: MR19=404, MR18=909
3451 00:59:39.548907 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3452 00:59:39.552165 [RxdqsGatingPostProcess] freq 1200
3453 00:59:39.558797 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3454 00:59:39.562349 Pre-setting of DQS Precalculation
3455 00:59:39.565519 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3456 00:59:39.575582 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3457 00:59:39.581895 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3458 00:59:39.582458
3459 00:59:39.582828
3460 00:59:39.585623 [Calibration Summary] 2400 Mbps
3461 00:59:39.586185 CH 0, Rank 0
3462 00:59:39.589261 SW Impedance : PASS
3463 00:59:39.589818 DUTY Scan : NO K
3464 00:59:39.592182 ZQ Calibration : PASS
3465 00:59:39.595484 Jitter Meter : NO K
3466 00:59:39.596045 CBT Training : PASS
3467 00:59:39.598419 Write leveling : PASS
3468 00:59:39.602235 RX DQS gating : PASS
3469 00:59:39.602795 RX DQ/DQS(RDDQC) : PASS
3470 00:59:39.605406 TX DQ/DQS : PASS
3471 00:59:39.609474 RX DATLAT : PASS
3472 00:59:39.610033 RX DQ/DQS(Engine): PASS
3473 00:59:39.611898 TX OE : NO K
3474 00:59:39.612360 All Pass.
3475 00:59:39.612766
3476 00:59:39.615132 CH 0, Rank 1
3477 00:59:39.615593 SW Impedance : PASS
3478 00:59:39.619039 DUTY Scan : NO K
3479 00:59:39.622339 ZQ Calibration : PASS
3480 00:59:39.622889 Jitter Meter : NO K
3481 00:59:39.626223 CBT Training : PASS
3482 00:59:39.626777 Write leveling : PASS
3483 00:59:39.628294 RX DQS gating : PASS
3484 00:59:39.632259 RX DQ/DQS(RDDQC) : PASS
3485 00:59:39.632870 TX DQ/DQS : PASS
3486 00:59:39.635522 RX DATLAT : PASS
3487 00:59:39.638529 RX DQ/DQS(Engine): PASS
3488 00:59:39.638995 TX OE : NO K
3489 00:59:39.642486 All Pass.
3490 00:59:39.643042
3491 00:59:39.643413 CH 1, Rank 0
3492 00:59:39.645627 SW Impedance : PASS
3493 00:59:39.646090 DUTY Scan : NO K
3494 00:59:39.648808 ZQ Calibration : PASS
3495 00:59:39.652684 Jitter Meter : NO K
3496 00:59:39.653298 CBT Training : PASS
3497 00:59:39.655133 Write leveling : PASS
3498 00:59:39.658458 RX DQS gating : PASS
3499 00:59:39.658936 RX DQ/DQS(RDDQC) : PASS
3500 00:59:39.661787 TX DQ/DQS : PASS
3501 00:59:39.665041 RX DATLAT : PASS
3502 00:59:39.665504 RX DQ/DQS(Engine): PASS
3503 00:59:39.668309 TX OE : NO K
3504 00:59:39.668928 All Pass.
3505 00:59:39.669307
3506 00:59:39.671552 CH 1, Rank 1
3507 00:59:39.672013 SW Impedance : PASS
3508 00:59:39.675469 DUTY Scan : NO K
3509 00:59:39.676026 ZQ Calibration : PASS
3510 00:59:39.678653 Jitter Meter : NO K
3511 00:59:39.681801 CBT Training : PASS
3512 00:59:39.682265 Write leveling : PASS
3513 00:59:39.685386 RX DQS gating : PASS
3514 00:59:39.688431 RX DQ/DQS(RDDQC) : PASS
3515 00:59:39.689244 TX DQ/DQS : PASS
3516 00:59:39.691985 RX DATLAT : PASS
3517 00:59:39.694855 RX DQ/DQS(Engine): PASS
3518 00:59:39.695401 TX OE : NO K
3519 00:59:39.698628 All Pass.
3520 00:59:39.699185
3521 00:59:39.699556 DramC Write-DBI off
3522 00:59:39.701581 PER_BANK_REFRESH: Hybrid Mode
3523 00:59:39.702047 TX_TRACKING: ON
3524 00:59:39.712495 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3525 00:59:39.715150 [FAST_K] Save calibration result to emmc
3526 00:59:39.718966 dramc_set_vcore_voltage set vcore to 650000
3527 00:59:39.721293 Read voltage for 600, 5
3528 00:59:39.721755 Vio18 = 0
3529 00:59:39.725288 Vcore = 650000
3530 00:59:39.725746 Vdram = 0
3531 00:59:39.726110 Vddq = 0
3532 00:59:39.728590 Vmddr = 0
3533 00:59:39.731913 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3534 00:59:39.738040 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3535 00:59:39.738614 MEM_TYPE=3, freq_sel=19
3536 00:59:39.743695 sv_algorithm_assistance_LP4_1600
3537 00:59:39.748394 ============ PULL DRAM RESETB DOWN ============
3538 00:59:39.752024 ========== PULL DRAM RESETB DOWN end =========
3539 00:59:39.755083 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3540 00:59:39.758090 ===================================
3541 00:59:39.761425 LPDDR4 DRAM CONFIGURATION
3542 00:59:39.765133 ===================================
3543 00:59:39.765693 EX_ROW_EN[0] = 0x0
3544 00:59:39.768747 EX_ROW_EN[1] = 0x0
3545 00:59:39.771636 LP4Y_EN = 0x0
3546 00:59:39.772097 WORK_FSP = 0x0
3547 00:59:39.775490 WL = 0x2
3548 00:59:39.776043 RL = 0x2
3549 00:59:39.778441 BL = 0x2
3550 00:59:39.779001 RPST = 0x0
3551 00:59:39.781768 RD_PRE = 0x0
3552 00:59:39.782230 WR_PRE = 0x1
3553 00:59:39.785124 WR_PST = 0x0
3554 00:59:39.785699 DBI_WR = 0x0
3555 00:59:39.788465 DBI_RD = 0x0
3556 00:59:39.789078 OTF = 0x1
3557 00:59:39.791712 ===================================
3558 00:59:39.795188 ===================================
3559 00:59:39.798300 ANA top config
3560 00:59:39.801675 ===================================
3561 00:59:39.802236 DLL_ASYNC_EN = 0
3562 00:59:39.805116 ALL_SLAVE_EN = 1
3563 00:59:39.808366 NEW_RANK_MODE = 1
3564 00:59:39.811928 DLL_IDLE_MODE = 1
3565 00:59:39.812490 LP45_APHY_COMB_EN = 1
3566 00:59:39.815221 TX_ODT_DIS = 1
3567 00:59:39.817904 NEW_8X_MODE = 1
3568 00:59:39.821310 ===================================
3569 00:59:39.825432 ===================================
3570 00:59:39.827803 data_rate = 1200
3571 00:59:39.831270 CKR = 1
3572 00:59:39.835978 DQ_P2S_RATIO = 8
3573 00:59:39.837845 ===================================
3574 00:59:39.838313 CA_P2S_RATIO = 8
3575 00:59:39.841068 DQ_CA_OPEN = 0
3576 00:59:39.844383 DQ_SEMI_OPEN = 0
3577 00:59:39.848094 CA_SEMI_OPEN = 0
3578 00:59:39.851703 CA_FULL_RATE = 0
3579 00:59:39.856161 DQ_CKDIV4_EN = 1
3580 00:59:39.856784 CA_CKDIV4_EN = 1
3581 00:59:39.857737 CA_PREDIV_EN = 0
3582 00:59:39.861731 PH8_DLY = 0
3583 00:59:39.864423 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3584 00:59:39.867819 DQ_AAMCK_DIV = 4
3585 00:59:39.871145 CA_AAMCK_DIV = 4
3586 00:59:39.871716 CA_ADMCK_DIV = 4
3587 00:59:39.874918 DQ_TRACK_CA_EN = 0
3588 00:59:39.878118 CA_PICK = 600
3589 00:59:39.881517 CA_MCKIO = 600
3590 00:59:39.884513 MCKIO_SEMI = 0
3591 00:59:39.887944 PLL_FREQ = 2288
3592 00:59:39.891546 DQ_UI_PI_RATIO = 32
3593 00:59:39.892117 CA_UI_PI_RATIO = 0
3594 00:59:39.894353 ===================================
3595 00:59:39.898336 ===================================
3596 00:59:39.901407 memory_type:LPDDR4
3597 00:59:39.904781 GP_NUM : 10
3598 00:59:39.905354 SRAM_EN : 1
3599 00:59:39.907750 MD32_EN : 0
3600 00:59:39.911027 ===================================
3601 00:59:39.914036 [ANA_INIT] >>>>>>>>>>>>>>
3602 00:59:39.917508 <<<<<< [CONFIGURE PHASE]: ANA_TX
3603 00:59:39.920412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3604 00:59:39.923792 ===================================
3605 00:59:39.924404 data_rate = 1200,PCW = 0X5800
3606 00:59:39.927940 ===================================
3607 00:59:39.930614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3608 00:59:39.938521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3609 00:59:39.944323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3610 00:59:39.947728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3611 00:59:39.950568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3612 00:59:39.954919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3613 00:59:39.957097 [ANA_INIT] flow start
3614 00:59:39.961032 [ANA_INIT] PLL >>>>>>>>
3615 00:59:39.961592 [ANA_INIT] PLL <<<<<<<<
3616 00:59:39.964700 [ANA_INIT] MIDPI >>>>>>>>
3617 00:59:39.967162 [ANA_INIT] MIDPI <<<<<<<<
3618 00:59:39.967627 [ANA_INIT] DLL >>>>>>>>
3619 00:59:39.970666 [ANA_INIT] flow end
3620 00:59:39.973416 ============ LP4 DIFF to SE enter ============
3621 00:59:39.977390 ============ LP4 DIFF to SE exit ============
3622 00:59:39.980471 [ANA_INIT] <<<<<<<<<<<<<
3623 00:59:39.983146 [Flow] Enable top DCM control >>>>>
3624 00:59:39.987693 [Flow] Enable top DCM control <<<<<
3625 00:59:39.990073 Enable DLL master slave shuffle
3626 00:59:39.997189 ==============================================================
3627 00:59:39.997752 Gating Mode config
3628 00:59:40.003939 ==============================================================
3629 00:59:40.004498 Config description:
3630 00:59:40.014059 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3631 00:59:40.020514 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3632 00:59:40.027262 SELPH_MODE 0: By rank 1: By Phase
3633 00:59:40.030429 ==============================================================
3634 00:59:40.033647 GAT_TRACK_EN = 1
3635 00:59:40.036410 RX_GATING_MODE = 2
3636 00:59:40.040156 RX_GATING_TRACK_MODE = 2
3637 00:59:40.043289 SELPH_MODE = 1
3638 00:59:40.046534 PICG_EARLY_EN = 1
3639 00:59:40.050324 VALID_LAT_VALUE = 1
3640 00:59:40.056197 ==============================================================
3641 00:59:40.060134 Enter into Gating configuration >>>>
3642 00:59:40.063503 Exit from Gating configuration <<<<
3643 00:59:40.067058 Enter into DVFS_PRE_config >>>>>
3644 00:59:40.076882 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3645 00:59:40.080940 Exit from DVFS_PRE_config <<<<<
3646 00:59:40.084332 Enter into PICG configuration >>>>
3647 00:59:40.086096 Exit from PICG configuration <<<<
3648 00:59:40.089734 [RX_INPUT] configuration >>>>>
3649 00:59:40.090295 [RX_INPUT] configuration <<<<<
3650 00:59:40.096073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3651 00:59:40.102494 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3652 00:59:40.109417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3653 00:59:40.112885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3654 00:59:40.119445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3655 00:59:40.126634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3656 00:59:40.129289 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3657 00:59:40.136162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3658 00:59:40.139099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3659 00:59:40.142271 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3660 00:59:40.146055 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3661 00:59:40.152129 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3662 00:59:40.156211 ===================================
3663 00:59:40.156835 LPDDR4 DRAM CONFIGURATION
3664 00:59:40.158588 ===================================
3665 00:59:40.162147 EX_ROW_EN[0] = 0x0
3666 00:59:40.165535 EX_ROW_EN[1] = 0x0
3667 00:59:40.166004 LP4Y_EN = 0x0
3668 00:59:40.168788 WORK_FSP = 0x0
3669 00:59:40.169256 WL = 0x2
3670 00:59:40.172042 RL = 0x2
3671 00:59:40.172497 BL = 0x2
3672 00:59:40.175999 RPST = 0x0
3673 00:59:40.176677 RD_PRE = 0x0
3674 00:59:40.179689 WR_PRE = 0x1
3675 00:59:40.180143 WR_PST = 0x0
3676 00:59:40.182091 DBI_WR = 0x0
3677 00:59:40.182542 DBI_RD = 0x0
3678 00:59:40.185517 OTF = 0x1
3679 00:59:40.189166 ===================================
3680 00:59:40.192057 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3681 00:59:40.196032 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3682 00:59:40.202807 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3683 00:59:40.205243 ===================================
3684 00:59:40.205724 LPDDR4 DRAM CONFIGURATION
3685 00:59:40.208199 ===================================
3686 00:59:40.211634 EX_ROW_EN[0] = 0x10
3687 00:59:40.215294 EX_ROW_EN[1] = 0x0
3688 00:59:40.215750 LP4Y_EN = 0x0
3689 00:59:40.218691 WORK_FSP = 0x0
3690 00:59:40.219251 WL = 0x2
3691 00:59:40.221866 RL = 0x2
3692 00:59:40.222423 BL = 0x2
3693 00:59:40.225451 RPST = 0x0
3694 00:59:40.225907 RD_PRE = 0x0
3695 00:59:40.228286 WR_PRE = 0x1
3696 00:59:40.228765 WR_PST = 0x0
3697 00:59:40.231623 DBI_WR = 0x0
3698 00:59:40.232357 DBI_RD = 0x0
3699 00:59:40.234947 OTF = 0x1
3700 00:59:40.238016 ===================================
3701 00:59:40.245351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3702 00:59:40.248105 nWR fixed to 30
3703 00:59:40.248582 [ModeRegInit_LP4] CH0 RK0
3704 00:59:40.251374 [ModeRegInit_LP4] CH0 RK1
3705 00:59:40.255493 [ModeRegInit_LP4] CH1 RK0
3706 00:59:40.257864 [ModeRegInit_LP4] CH1 RK1
3707 00:59:40.258321 match AC timing 16
3708 00:59:40.265106 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3709 00:59:40.268444 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3710 00:59:40.271539 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3711 00:59:40.278507 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3712 00:59:40.281749 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3713 00:59:40.282310 ==
3714 00:59:40.284535 Dram Type= 6, Freq= 0, CH_0, rank 0
3715 00:59:40.288022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3716 00:59:40.288586 ==
3717 00:59:40.294677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3718 00:59:40.302986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3719 00:59:40.304471 [CA 0] Center 35 (5~66) winsize 62
3720 00:59:40.308631 [CA 1] Center 35 (5~66) winsize 62
3721 00:59:40.311152 [CA 2] Center 34 (4~65) winsize 62
3722 00:59:40.315364 [CA 3] Center 34 (3~65) winsize 63
3723 00:59:40.317964 [CA 4] Center 33 (3~64) winsize 62
3724 00:59:40.321644 [CA 5] Center 33 (3~64) winsize 62
3725 00:59:40.322205
3726 00:59:40.324999 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3727 00:59:40.325558
3728 00:59:40.328123 [CATrainingPosCal] consider 1 rank data
3729 00:59:40.331157 u2DelayCellTimex100 = 270/100 ps
3730 00:59:40.334374 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3731 00:59:40.338337 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3732 00:59:40.341156 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3733 00:59:40.344695 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3734 00:59:40.347515 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3735 00:59:40.351008 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3736 00:59:40.351620
3737 00:59:40.358402 CA PerBit enable=1, Macro0, CA PI delay=33
3738 00:59:40.358868
3739 00:59:40.360491 [CBTSetCACLKResult] CA Dly = 33
3740 00:59:40.360993 CS Dly: 6 (0~37)
3741 00:59:40.361368 ==
3742 00:59:40.363952 Dram Type= 6, Freq= 0, CH_0, rank 1
3743 00:59:40.367367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3744 00:59:40.367927 ==
3745 00:59:40.374039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3746 00:59:40.380518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3747 00:59:40.383932 [CA 0] Center 36 (6~66) winsize 61
3748 00:59:40.387098 [CA 1] Center 35 (5~66) winsize 62
3749 00:59:40.390141 [CA 2] Center 34 (4~65) winsize 62
3750 00:59:40.393657 [CA 3] Center 34 (4~65) winsize 62
3751 00:59:40.397280 [CA 4] Center 33 (3~64) winsize 62
3752 00:59:40.400365 [CA 5] Center 33 (3~64) winsize 62
3753 00:59:40.400968
3754 00:59:40.404310 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3755 00:59:40.404920
3756 00:59:40.407420 [CATrainingPosCal] consider 2 rank data
3757 00:59:40.410490 u2DelayCellTimex100 = 270/100 ps
3758 00:59:40.414217 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3759 00:59:40.416837 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3760 00:59:40.420436 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3761 00:59:40.423793 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3762 00:59:40.430369 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3763 00:59:40.434359 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3764 00:59:40.434912
3765 00:59:40.437064 CA PerBit enable=1, Macro0, CA PI delay=33
3766 00:59:40.437617
3767 00:59:40.440113 [CBTSetCACLKResult] CA Dly = 33
3768 00:59:40.440663 CS Dly: 5 (0~36)
3769 00:59:40.441076
3770 00:59:40.443519 ----->DramcWriteLeveling(PI) begin...
3771 00:59:40.443990 ==
3772 00:59:40.447108 Dram Type= 6, Freq= 0, CH_0, rank 0
3773 00:59:40.454811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3774 00:59:40.455372 ==
3775 00:59:40.456522 Write leveling (Byte 0): 31 => 31
3776 00:59:40.457030 Write leveling (Byte 1): 31 => 31
3777 00:59:40.460581 DramcWriteLeveling(PI) end<-----
3778 00:59:40.461200
3779 00:59:40.463492 ==
3780 00:59:40.463979 Dram Type= 6, Freq= 0, CH_0, rank 0
3781 00:59:40.470419 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3782 00:59:40.470976 ==
3783 00:59:40.474252 [Gating] SW mode calibration
3784 00:59:40.480275 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3785 00:59:40.483813 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3786 00:59:40.490421 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3787 00:59:40.493966 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3788 00:59:40.496691 0 5 8 | B1->B0 | 3333 2e2e | 1 1 | (1 0) (1 1)
3789 00:59:40.503459 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3790 00:59:40.506450 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 00:59:40.510950 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 00:59:40.516463 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 00:59:40.520469 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 00:59:40.523278 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 00:59:40.530468 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 00:59:40.532945 0 6 8 | B1->B0 | 2f2f 3232 | 1 0 | (0 0) (0 0)
3797 00:59:40.536452 0 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3798 00:59:40.543062 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 00:59:40.546681 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 00:59:40.550175 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 00:59:40.557748 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 00:59:40.559291 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 00:59:40.562778 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 00:59:40.569931 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3805 00:59:40.572773 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 00:59:40.575782 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 00:59:40.579547 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 00:59:40.585670 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 00:59:40.590000 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 00:59:40.593700 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 00:59:40.599435 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 00:59:40.602728 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 00:59:40.606842 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 00:59:40.612923 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 00:59:40.615750 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 00:59:40.619853 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 00:59:40.625265 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 00:59:40.629044 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 00:59:40.632784 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 00:59:40.639057 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3821 00:59:40.641883 Total UI for P1: 0, mck2ui 16
3822 00:59:40.645875 best dqsien dly found for B0: ( 0, 9, 6)
3823 00:59:40.648478 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3824 00:59:40.652079 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3825 00:59:40.655214 Total UI for P1: 0, mck2ui 16
3826 00:59:40.658965 best dqsien dly found for B1: ( 0, 9, 10)
3827 00:59:40.662064 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3828 00:59:40.665359 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3829 00:59:40.668591
3830 00:59:40.672189 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3831 00:59:40.674943 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3832 00:59:40.678374 [Gating] SW calibration Done
3833 00:59:40.678930 ==
3834 00:59:40.681906 Dram Type= 6, Freq= 0, CH_0, rank 0
3835 00:59:40.685252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3836 00:59:40.685811 ==
3837 00:59:40.688794 RX Vref Scan: 0
3838 00:59:40.689348
3839 00:59:40.689715 RX Vref 0 -> 0, step: 1
3840 00:59:40.690060
3841 00:59:40.691222 RX Delay -230 -> 252, step: 16
3842 00:59:40.695154 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3843 00:59:40.701318 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3844 00:59:40.704815 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3845 00:59:40.709026 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3846 00:59:40.711530 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3847 00:59:40.718284 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3848 00:59:40.721688 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3849 00:59:40.724868 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3850 00:59:40.728155 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3851 00:59:40.731384 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3852 00:59:40.737809 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3853 00:59:40.741369 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3854 00:59:40.744583 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3855 00:59:40.748138 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3856 00:59:40.754538 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3857 00:59:40.757877 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3858 00:59:40.758338 ==
3859 00:59:40.760885 Dram Type= 6, Freq= 0, CH_0, rank 0
3860 00:59:40.764871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3861 00:59:40.765434 ==
3862 00:59:40.767880 DQS Delay:
3863 00:59:40.768448 DQS0 = 0, DQS1 = 0
3864 00:59:40.768860 DQM Delay:
3865 00:59:40.771252 DQM0 = 39, DQM1 = 33
3866 00:59:40.771706 DQ Delay:
3867 00:59:40.774810 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3868 00:59:40.777088 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3869 00:59:40.781650 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3870 00:59:40.784239 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3871 00:59:40.784836
3872 00:59:40.785220
3873 00:59:40.785554 ==
3874 00:59:40.788829 Dram Type= 6, Freq= 0, CH_0, rank 0
3875 00:59:40.794034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3876 00:59:40.794599 ==
3877 00:59:40.794961
3878 00:59:40.795294
3879 00:59:40.795613 TX Vref Scan disable
3880 00:59:40.799669 == TX Byte 0 ==
3881 00:59:40.801715 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3882 00:59:40.807748 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3883 00:59:40.808310 == TX Byte 1 ==
3884 00:59:40.811627 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3885 00:59:40.818248 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3886 00:59:40.818795 ==
3887 00:59:40.822056 Dram Type= 6, Freq= 0, CH_0, rank 0
3888 00:59:40.824399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3889 00:59:40.825003 ==
3890 00:59:40.825370
3891 00:59:40.825706
3892 00:59:40.827993 TX Vref Scan disable
3893 00:59:40.831630 == TX Byte 0 ==
3894 00:59:40.834461 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3895 00:59:40.837856 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3896 00:59:40.841353 == TX Byte 1 ==
3897 00:59:40.843976 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3898 00:59:40.847868 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3899 00:59:40.848430
3900 00:59:40.848849 [DATLAT]
3901 00:59:40.850575 Freq=600, CH0 RK0
3902 00:59:40.851031
3903 00:59:40.854038 DATLAT Default: 0x9
3904 00:59:40.854507 0, 0xFFFF, sum = 0
3905 00:59:40.859068 1, 0xFFFF, sum = 0
3906 00:59:40.859633 2, 0xFFFF, sum = 0
3907 00:59:40.861103 3, 0xFFFF, sum = 0
3908 00:59:40.861566 4, 0xFFFF, sum = 0
3909 00:59:40.863935 5, 0xFFFF, sum = 0
3910 00:59:40.864410 6, 0xFFFF, sum = 0
3911 00:59:40.867108 7, 0x0, sum = 1
3912 00:59:40.867568 8, 0x0, sum = 2
3913 00:59:40.870488 9, 0x0, sum = 3
3914 00:59:40.870950 10, 0x0, sum = 4
3915 00:59:40.871318 best_step = 8
3916 00:59:40.871649
3917 00:59:40.873754 ==
3918 00:59:40.874210 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 00:59:40.881677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3920 00:59:40.882238 ==
3921 00:59:40.882601 RX Vref Scan: 1
3922 00:59:40.882941
3923 00:59:40.883758 RX Vref 0 -> 0, step: 1
3924 00:59:40.884213
3925 00:59:40.887168 RX Delay -195 -> 252, step: 8
3926 00:59:40.887739
3927 00:59:40.890338 Set Vref, RX VrefLevel [Byte0]: 48
3928 00:59:40.894601 [Byte1]: 50
3929 00:59:40.895161
3930 00:59:40.898542 Final RX Vref Byte 0 = 48 to rank0
3931 00:59:40.901269 Final RX Vref Byte 1 = 50 to rank0
3932 00:59:40.903673 Final RX Vref Byte 0 = 48 to rank1
3933 00:59:40.907176 Final RX Vref Byte 1 = 50 to rank1==
3934 00:59:40.910739 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 00:59:40.914629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 00:59:40.915189 ==
3937 00:59:40.916797 DQS Delay:
3938 00:59:40.917254 DQS0 = 0, DQS1 = 0
3939 00:59:40.920510 DQM Delay:
3940 00:59:40.921002 DQM0 = 40, DQM1 = 30
3941 00:59:40.923814 DQ Delay:
3942 00:59:40.924368 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3943 00:59:40.926914 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
3944 00:59:40.930189 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3945 00:59:40.933620 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
3946 00:59:40.934187
3947 00:59:40.936620
3948 00:59:40.943421 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3949 00:59:40.947041 CH0 RK0: MR19=808, MR18=5959
3950 00:59:40.953866 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
3951 00:59:40.954329
3952 00:59:40.956487 ----->DramcWriteLeveling(PI) begin...
3953 00:59:40.957000 ==
3954 00:59:40.959848 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 00:59:40.963798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 00:59:40.964258 ==
3957 00:59:40.966956 Write leveling (Byte 0): 30 => 30
3958 00:59:40.970678 Write leveling (Byte 1): 30 => 30
3959 00:59:40.973848 DramcWriteLeveling(PI) end<-----
3960 00:59:40.974408
3961 00:59:40.974865 ==
3962 00:59:40.976652 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 00:59:40.980621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 00:59:40.981240 ==
3965 00:59:40.983327 [Gating] SW mode calibration
3966 00:59:40.990723 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3967 00:59:40.996557 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3968 00:59:41.000020 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 00:59:41.003660 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 00:59:41.010014 0 5 8 | B1->B0 | 3434 3232 | 0 0 | (1 1) (0 0)
3971 00:59:41.013345 0 5 12 | B1->B0 | 2525 2525 | 0 0 | (1 1) (0 0)
3972 00:59:41.016380 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 00:59:41.023337 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 00:59:41.027112 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 00:59:41.029285 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 00:59:41.036886 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 00:59:41.039524 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 00:59:41.043086 0 6 8 | B1->B0 | 2d2d 3333 | 0 0 | (1 1) (0 0)
3979 00:59:41.049582 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3980 00:59:41.053315 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 00:59:41.057054 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 00:59:41.062838 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 00:59:41.065815 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 00:59:41.069416 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 00:59:41.075774 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 00:59:41.079983 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3987 00:59:41.083250 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3988 00:59:41.089245 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 00:59:41.092364 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 00:59:41.096018 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 00:59:41.102378 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 00:59:41.105684 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 00:59:41.109169 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 00:59:41.115751 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:59:41.118602 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:59:41.122648 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:59:41.129694 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:59:41.132465 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 00:59:41.135578 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 00:59:41.142034 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 00:59:41.145879 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4002 00:59:41.148536 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4003 00:59:41.152225 Total UI for P1: 0, mck2ui 16
4004 00:59:41.156778 best dqsien dly found for B0: ( 0, 9, 6)
4005 00:59:41.161985 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:59:41.162559 Total UI for P1: 0, mck2ui 16
4007 00:59:41.169524 best dqsien dly found for B1: ( 0, 9, 6)
4008 00:59:41.172610 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4009 00:59:41.174961 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4010 00:59:41.175633
4011 00:59:41.178281 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4012 00:59:41.182743 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4013 00:59:41.185069 [Gating] SW calibration Done
4014 00:59:41.185534 ==
4015 00:59:41.188301 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 00:59:41.191733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4017 00:59:41.192295 ==
4018 00:59:41.194917 RX Vref Scan: 0
4019 00:59:41.195380
4020 00:59:41.195741 RX Vref 0 -> 0, step: 1
4021 00:59:41.196081
4022 00:59:41.198788 RX Delay -230 -> 252, step: 16
4023 00:59:41.201821 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4024 00:59:41.208439 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4025 00:59:41.211284 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4026 00:59:41.215430 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4027 00:59:41.218195 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4028 00:59:41.224936 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4029 00:59:41.228933 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4030 00:59:41.231365 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4031 00:59:41.234445 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4032 00:59:41.241332 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4033 00:59:41.244664 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4034 00:59:41.247739 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4035 00:59:41.251639 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4036 00:59:41.257545 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4037 00:59:41.261134 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4038 00:59:41.265484 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4039 00:59:41.266045 ==
4040 00:59:41.267518 Dram Type= 6, Freq= 0, CH_0, rank 1
4041 00:59:41.271213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4042 00:59:41.271679 ==
4043 00:59:41.274365 DQS Delay:
4044 00:59:41.275056 DQS0 = 0, DQS1 = 0
4045 00:59:41.277284 DQM Delay:
4046 00:59:41.277746 DQM0 = 43, DQM1 = 33
4047 00:59:41.278113 DQ Delay:
4048 00:59:41.281231 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4049 00:59:41.284329 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4050 00:59:41.287219 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4051 00:59:41.290857 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4052 00:59:41.291415
4053 00:59:41.291780
4054 00:59:41.294361 ==
4055 00:59:41.297236 Dram Type= 6, Freq= 0, CH_0, rank 1
4056 00:59:41.300410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4057 00:59:41.300921 ==
4058 00:59:41.301297
4059 00:59:41.301642
4060 00:59:41.303622 TX Vref Scan disable
4061 00:59:41.304085 == TX Byte 0 ==
4062 00:59:41.311110 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4063 00:59:41.313690 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4064 00:59:41.314206 == TX Byte 1 ==
4065 00:59:41.320636 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4066 00:59:41.323692 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4067 00:59:41.324159 ==
4068 00:59:41.327343 Dram Type= 6, Freq= 0, CH_0, rank 1
4069 00:59:41.330747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4070 00:59:41.331214 ==
4071 00:59:41.331583
4072 00:59:41.332003
4073 00:59:41.333710 TX Vref Scan disable
4074 00:59:41.337268 == TX Byte 0 ==
4075 00:59:41.340456 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 00:59:41.343854 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 00:59:41.346914 == TX Byte 1 ==
4078 00:59:41.350134 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4079 00:59:41.353157 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4080 00:59:41.353668
4081 00:59:41.357061 [DATLAT]
4082 00:59:41.357520 Freq=600, CH0 RK1
4083 00:59:41.357889
4084 00:59:41.359875 DATLAT Default: 0x8
4085 00:59:41.360333 0, 0xFFFF, sum = 0
4086 00:59:41.364035 1, 0xFFFF, sum = 0
4087 00:59:41.364600 2, 0xFFFF, sum = 0
4088 00:59:41.366505 3, 0xFFFF, sum = 0
4089 00:59:41.366971 4, 0xFFFF, sum = 0
4090 00:59:41.370286 5, 0xFFFF, sum = 0
4091 00:59:41.370766 6, 0xFFFF, sum = 0
4092 00:59:41.373209 7, 0x0, sum = 1
4093 00:59:41.373677 8, 0x0, sum = 2
4094 00:59:41.376294 9, 0x0, sum = 3
4095 00:59:41.376808 10, 0x0, sum = 4
4096 00:59:41.380070 best_step = 8
4097 00:59:41.380625
4098 00:59:41.381053 ==
4099 00:59:41.383520 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 00:59:41.386327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 00:59:41.386888 ==
4102 00:59:41.390033 RX Vref Scan: 0
4103 00:59:41.390593
4104 00:59:41.390960 RX Vref 0 -> 0, step: 1
4105 00:59:41.391304
4106 00:59:41.392653 RX Delay -179 -> 252, step: 8
4107 00:59:41.400498 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4108 00:59:41.403845 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4109 00:59:41.406832 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4110 00:59:41.409795 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4111 00:59:41.417654 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4112 00:59:41.421088 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4113 00:59:41.422841 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4114 00:59:41.426838 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4115 00:59:41.430366 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4116 00:59:41.436736 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4117 00:59:41.440121 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4118 00:59:41.442914 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4119 00:59:41.446240 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4120 00:59:41.453225 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4121 00:59:41.456229 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4122 00:59:41.460194 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4123 00:59:41.460789 ==
4124 00:59:41.463068 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 00:59:41.470688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4126 00:59:41.471247 ==
4127 00:59:41.471614 DQS Delay:
4128 00:59:41.471955 DQS0 = 0, DQS1 = 0
4129 00:59:41.472832 DQM Delay:
4130 00:59:41.473291 DQM0 = 40, DQM1 = 32
4131 00:59:41.475730 DQ Delay:
4132 00:59:41.479841 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4133 00:59:41.483216 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4134 00:59:41.486606 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4135 00:59:41.490121 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4136 00:59:41.490677
4137 00:59:41.491044
4138 00:59:41.496068 [DQSOSCAuto] RK1, (LSB)MR18= 0x6666, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4139 00:59:41.499579 CH0 RK1: MR19=808, MR18=6666
4140 00:59:41.506087 CH0_RK1: MR19=0x808, MR18=0x6666, DQSOSC=390, MR23=63, INC=172, DEC=114
4141 00:59:41.510263 [RxdqsGatingPostProcess] freq 600
4142 00:59:41.512208 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4143 00:59:41.516576 Pre-setting of DQS Precalculation
4144 00:59:41.522615 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4145 00:59:41.523182 ==
4146 00:59:41.526211 Dram Type= 6, Freq= 0, CH_1, rank 0
4147 00:59:41.529586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4148 00:59:41.530149 ==
4149 00:59:41.535863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4150 00:59:41.542174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4151 00:59:41.546028 [CA 0] Center 35 (5~66) winsize 62
4152 00:59:41.549618 [CA 1] Center 35 (5~66) winsize 62
4153 00:59:41.552153 [CA 2] Center 33 (3~64) winsize 62
4154 00:59:41.555540 [CA 3] Center 33 (3~64) winsize 62
4155 00:59:41.558938 [CA 4] Center 33 (2~64) winsize 63
4156 00:59:41.559503 [CA 5] Center 33 (2~64) winsize 63
4157 00:59:41.562335
4158 00:59:41.565432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4159 00:59:41.565898
4160 00:59:41.568650 [CATrainingPosCal] consider 1 rank data
4161 00:59:41.572311 u2DelayCellTimex100 = 270/100 ps
4162 00:59:41.575250 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4163 00:59:41.579405 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4164 00:59:41.582303 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4165 00:59:41.585393 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4166 00:59:41.589122 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4167 00:59:41.591709 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4168 00:59:41.592273
4169 00:59:41.595570 CA PerBit enable=1, Macro0, CA PI delay=33
4170 00:59:41.598060
4171 00:59:41.598520 [CBTSetCACLKResult] CA Dly = 33
4172 00:59:41.602248 CS Dly: 4 (0~35)
4173 00:59:41.602808 ==
4174 00:59:41.604990 Dram Type= 6, Freq= 0, CH_1, rank 1
4175 00:59:41.608116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4176 00:59:41.608687 ==
4177 00:59:41.614854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4178 00:59:41.622599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4179 00:59:41.624806 [CA 0] Center 35 (5~66) winsize 62
4180 00:59:41.628312 [CA 1] Center 34 (4~65) winsize 62
4181 00:59:41.631452 [CA 2] Center 33 (3~64) winsize 62
4182 00:59:41.634543 [CA 3] Center 33 (3~64) winsize 62
4183 00:59:41.638397 [CA 4] Center 32 (2~63) winsize 62
4184 00:59:41.641492 [CA 5] Center 32 (2~63) winsize 62
4185 00:59:41.642050
4186 00:59:41.645087 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4187 00:59:41.645550
4188 00:59:41.648340 [CATrainingPosCal] consider 2 rank data
4189 00:59:41.650945 u2DelayCellTimex100 = 270/100 ps
4190 00:59:41.654464 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4191 00:59:41.658533 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4192 00:59:41.661283 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4193 00:59:41.664369 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4194 00:59:41.667912 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4195 00:59:41.674359 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4196 00:59:41.674902
4197 00:59:41.678067 CA PerBit enable=1, Macro0, CA PI delay=32
4198 00:59:41.678626
4199 00:59:41.681195 [CBTSetCACLKResult] CA Dly = 32
4200 00:59:41.681653 CS Dly: 5 (0~37)
4201 00:59:41.682015
4202 00:59:41.685735 ----->DramcWriteLeveling(PI) begin...
4203 00:59:41.686304 ==
4204 00:59:41.688980 Dram Type= 6, Freq= 0, CH_1, rank 0
4205 00:59:41.690871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4206 00:59:41.694629 ==
4207 00:59:41.697412 Write leveling (Byte 0): 29 => 29
4208 00:59:41.697877 Write leveling (Byte 1): 29 => 29
4209 00:59:41.701702 DramcWriteLeveling(PI) end<-----
4210 00:59:41.702258
4211 00:59:41.702622 ==
4212 00:59:41.704446 Dram Type= 6, Freq= 0, CH_1, rank 0
4213 00:59:41.711023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4214 00:59:41.711582 ==
4215 00:59:41.714998 [Gating] SW mode calibration
4216 00:59:41.720923 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4217 00:59:41.724092 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4218 00:59:41.730772 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 00:59:41.734435 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4220 00:59:41.736869 0 5 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
4221 00:59:41.744394 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 00:59:41.748203 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 00:59:41.750295 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 00:59:41.756801 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 00:59:41.760345 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 00:59:41.763788 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 00:59:41.770270 0 6 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4228 00:59:41.773471 0 6 8 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (0 0)
4229 00:59:41.777202 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 00:59:41.784271 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 00:59:41.786688 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 00:59:41.790027 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 00:59:41.797304 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 00:59:41.800200 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 00:59:41.803747 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4236 00:59:41.810442 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4237 00:59:41.813270 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4238 00:59:41.817183 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 00:59:41.823351 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 00:59:41.826845 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 00:59:41.830424 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 00:59:41.836697 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 00:59:41.839532 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 00:59:41.843027 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 00:59:41.849391 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 00:59:41.852538 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 00:59:41.857644 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 00:59:41.863004 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 00:59:41.866131 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 00:59:41.869061 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 00:59:41.876478 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 00:59:41.879775 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4253 00:59:41.883296 Total UI for P1: 0, mck2ui 16
4254 00:59:41.885867 best dqsien dly found for B0: ( 0, 9, 6)
4255 00:59:41.889214 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 00:59:41.892970 Total UI for P1: 0, mck2ui 16
4257 00:59:41.895921 best dqsien dly found for B1: ( 0, 9, 8)
4258 00:59:41.899697 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4259 00:59:41.902569 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4260 00:59:41.903128
4261 00:59:41.906008 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4262 00:59:41.909476 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4263 00:59:41.913091 [Gating] SW calibration Done
4264 00:59:41.913647 ==
4265 00:59:41.916035 Dram Type= 6, Freq= 0, CH_1, rank 0
4266 00:59:41.922806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4267 00:59:41.923365 ==
4268 00:59:41.923730 RX Vref Scan: 0
4269 00:59:41.924070
4270 00:59:41.925959 RX Vref 0 -> 0, step: 1
4271 00:59:41.926515
4272 00:59:41.929178 RX Delay -230 -> 252, step: 16
4273 00:59:41.932812 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4274 00:59:41.935173 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4275 00:59:41.939441 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4276 00:59:41.945624 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4277 00:59:41.948837 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4278 00:59:41.952114 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4279 00:59:41.955732 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4280 00:59:41.961728 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4281 00:59:41.965267 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4282 00:59:41.968430 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4283 00:59:41.972888 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4284 00:59:41.978671 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4285 00:59:41.981757 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4286 00:59:41.985062 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4287 00:59:41.988812 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4288 00:59:41.995624 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4289 00:59:41.996187 ==
4290 00:59:41.998397 Dram Type= 6, Freq= 0, CH_1, rank 0
4291 00:59:42.001714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4292 00:59:42.002182 ==
4293 00:59:42.002548 DQS Delay:
4294 00:59:42.005251 DQS0 = 0, DQS1 = 0
4295 00:59:42.005711 DQM Delay:
4296 00:59:42.008134 DQM0 = 37, DQM1 = 32
4297 00:59:42.008595 DQ Delay:
4298 00:59:42.011715 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4299 00:59:42.014688 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4300 00:59:42.018679 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4301 00:59:42.021490 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4302 00:59:42.021953
4303 00:59:42.022317
4304 00:59:42.022650 ==
4305 00:59:42.025385 Dram Type= 6, Freq= 0, CH_1, rank 0
4306 00:59:42.028786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4307 00:59:42.029342 ==
4308 00:59:42.029711
4309 00:59:42.030051
4310 00:59:42.031852 TX Vref Scan disable
4311 00:59:42.035556 == TX Byte 0 ==
4312 00:59:42.038214 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4313 00:59:42.042055 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4314 00:59:42.045949 == TX Byte 1 ==
4315 00:59:42.048585 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4316 00:59:42.051385 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4317 00:59:42.051927 ==
4318 00:59:42.054893 Dram Type= 6, Freq= 0, CH_1, rank 0
4319 00:59:42.061516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4320 00:59:42.062114 ==
4321 00:59:42.062487
4322 00:59:42.062829
4323 00:59:42.063157 TX Vref Scan disable
4324 00:59:42.065992 == TX Byte 0 ==
4325 00:59:42.069347 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4326 00:59:42.072351 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4327 00:59:42.076567 == TX Byte 1 ==
4328 00:59:42.079410 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4329 00:59:42.083031 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4330 00:59:42.086002
4331 00:59:42.086560 [DATLAT]
4332 00:59:42.086923 Freq=600, CH1 RK0
4333 00:59:42.087267
4334 00:59:42.088682 DATLAT Default: 0x9
4335 00:59:42.089196 0, 0xFFFF, sum = 0
4336 00:59:42.092623 1, 0xFFFF, sum = 0
4337 00:59:42.093265 2, 0xFFFF, sum = 0
4338 00:59:42.095938 3, 0xFFFF, sum = 0
4339 00:59:42.096498 4, 0xFFFF, sum = 0
4340 00:59:42.099826 5, 0xFFFF, sum = 0
4341 00:59:42.102819 6, 0xFFFF, sum = 0
4342 00:59:42.103399 7, 0x0, sum = 1
4343 00:59:42.103777 8, 0x0, sum = 2
4344 00:59:42.105904 9, 0x0, sum = 3
4345 00:59:42.106471 10, 0x0, sum = 4
4346 00:59:42.109026 best_step = 8
4347 00:59:42.109483
4348 00:59:42.109846 ==
4349 00:59:42.112110 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 00:59:42.115722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 00:59:42.116282 ==
4352 00:59:42.118569 RX Vref Scan: 1
4353 00:59:42.119032
4354 00:59:42.119394 RX Vref 0 -> 0, step: 1
4355 00:59:42.119736
4356 00:59:42.122537 RX Delay -195 -> 252, step: 8
4357 00:59:42.123091
4358 00:59:42.125311 Set Vref, RX VrefLevel [Byte0]: 57
4359 00:59:42.128761 [Byte1]: 48
4360 00:59:42.132987
4361 00:59:42.133537 Final RX Vref Byte 0 = 57 to rank0
4362 00:59:42.135900 Final RX Vref Byte 1 = 48 to rank0
4363 00:59:42.139432 Final RX Vref Byte 0 = 57 to rank1
4364 00:59:42.142787 Final RX Vref Byte 1 = 48 to rank1==
4365 00:59:42.145729 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 00:59:42.152742 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4367 00:59:42.153302 ==
4368 00:59:42.153671 DQS Delay:
4369 00:59:42.155959 DQS0 = 0, DQS1 = 0
4370 00:59:42.156530 DQM Delay:
4371 00:59:42.156965 DQM0 = 37, DQM1 = 30
4372 00:59:42.159407 DQ Delay:
4373 00:59:42.162267 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4374 00:59:42.165981 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4375 00:59:42.169150 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4376 00:59:42.172445 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4377 00:59:42.173058
4378 00:59:42.173431
4379 00:59:42.179039 [DQSOSCAuto] RK0, (LSB)MR18= 0x7171, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4380 00:59:42.183388 CH1 RK0: MR19=808, MR18=7171
4381 00:59:42.189136 CH1_RK0: MR19=0x808, MR18=0x7171, DQSOSC=388, MR23=63, INC=174, DEC=116
4382 00:59:42.189679
4383 00:59:42.192026 ----->DramcWriteLeveling(PI) begin...
4384 00:59:42.192490 ==
4385 00:59:42.196639 Dram Type= 6, Freq= 0, CH_1, rank 1
4386 00:59:42.198762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 00:59:42.199246 ==
4388 00:59:42.202081 Write leveling (Byte 0): 26 => 26
4389 00:59:42.206098 Write leveling (Byte 1): 26 => 26
4390 00:59:42.209119 DramcWriteLeveling(PI) end<-----
4391 00:59:42.209676
4392 00:59:42.210038 ==
4393 00:59:42.212975 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 00:59:42.216331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 00:59:42.217004 ==
4396 00:59:42.218599 [Gating] SW mode calibration
4397 00:59:42.226408 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4398 00:59:42.232267 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4399 00:59:42.235414 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 00:59:42.242372 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4401 00:59:42.245105 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4402 00:59:42.248980 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 00:59:42.255462 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 00:59:42.259100 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 00:59:42.263022 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 00:59:42.268311 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 00:59:42.272334 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 00:59:42.275382 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4409 00:59:42.281442 0 6 8 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4410 00:59:42.285483 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 00:59:42.288583 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 00:59:42.295012 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 00:59:42.299308 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 00:59:42.301445 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 00:59:42.308356 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 00:59:42.312348 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 00:59:42.314793 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4418 00:59:42.319070 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 00:59:42.324651 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 00:59:42.328145 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 00:59:42.331657 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 00:59:42.337892 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 00:59:42.341697 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 00:59:42.345357 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 00:59:42.351314 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:59:42.354295 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:59:42.357516 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:59:42.364330 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:59:42.367945 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:59:42.371410 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:59:42.377670 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:59:42.380742 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:59:42.384566 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4434 00:59:42.387630 Total UI for P1: 0, mck2ui 16
4435 00:59:42.390737 best dqsien dly found for B0: ( 0, 9, 6)
4436 00:59:42.398023 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 00:59:42.398584 Total UI for P1: 0, mck2ui 16
4438 00:59:42.405633 best dqsien dly found for B1: ( 0, 9, 8)
4439 00:59:42.407204 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4440 00:59:42.410703 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4441 00:59:42.411267
4442 00:59:42.413779 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4443 00:59:42.417621 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4444 00:59:42.420900 [Gating] SW calibration Done
4445 00:59:42.421362 ==
4446 00:59:42.424136 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 00:59:42.428422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4448 00:59:42.429036 ==
4449 00:59:42.430815 RX Vref Scan: 0
4450 00:59:42.431273
4451 00:59:42.431634 RX Vref 0 -> 0, step: 1
4452 00:59:42.431973
4453 00:59:42.433810 RX Delay -230 -> 252, step: 16
4454 00:59:42.441346 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4455 00:59:42.443581 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4456 00:59:42.447262 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4457 00:59:42.451067 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4458 00:59:42.455295 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4459 00:59:42.461294 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4460 00:59:42.463412 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4461 00:59:42.466917 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4462 00:59:42.470894 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4463 00:59:42.477552 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4464 00:59:42.480014 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4465 00:59:42.483844 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4466 00:59:42.487842 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4467 00:59:42.494512 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4468 00:59:42.497370 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4469 00:59:42.500385 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4470 00:59:42.500992 ==
4471 00:59:42.503614 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 00:59:42.506537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4473 00:59:42.509884 ==
4474 00:59:42.510478 DQS Delay:
4475 00:59:42.510978 DQS0 = 0, DQS1 = 0
4476 00:59:42.513376 DQM Delay:
4477 00:59:42.513844 DQM0 = 41, DQM1 = 34
4478 00:59:42.517091 DQ Delay:
4479 00:59:42.517649 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4480 00:59:42.520053 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4481 00:59:42.523235 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4482 00:59:42.527019 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4483 00:59:42.527579
4484 00:59:42.529885
4485 00:59:42.530346 ==
4486 00:59:42.533146 Dram Type= 6, Freq= 0, CH_1, rank 1
4487 00:59:42.536493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4488 00:59:42.537109 ==
4489 00:59:42.537487
4490 00:59:42.537865
4491 00:59:42.539916 TX Vref Scan disable
4492 00:59:42.540471 == TX Byte 0 ==
4493 00:59:42.546500 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4494 00:59:42.549919 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4495 00:59:42.550480 == TX Byte 1 ==
4496 00:59:42.556158 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4497 00:59:42.560656 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4498 00:59:42.561278 ==
4499 00:59:42.563410 Dram Type= 6, Freq= 0, CH_1, rank 1
4500 00:59:42.566737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4501 00:59:42.567301 ==
4502 00:59:42.567671
4503 00:59:42.568011
4504 00:59:42.569430 TX Vref Scan disable
4505 00:59:42.573820 == TX Byte 0 ==
4506 00:59:42.576532 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4507 00:59:42.579839 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4508 00:59:42.583762 == TX Byte 1 ==
4509 00:59:42.586448 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4510 00:59:42.590079 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4511 00:59:42.590549
4512 00:59:42.593445 [DATLAT]
4513 00:59:42.594004 Freq=600, CH1 RK1
4514 00:59:42.594377
4515 00:59:42.596660 DATLAT Default: 0x8
4516 00:59:42.597265 0, 0xFFFF, sum = 0
4517 00:59:42.600046 1, 0xFFFF, sum = 0
4518 00:59:42.600611 2, 0xFFFF, sum = 0
4519 00:59:42.603256 3, 0xFFFF, sum = 0
4520 00:59:42.603726 4, 0xFFFF, sum = 0
4521 00:59:42.606731 5, 0xFFFF, sum = 0
4522 00:59:42.607203 6, 0xFFFF, sum = 0
4523 00:59:42.610142 7, 0x0, sum = 1
4524 00:59:42.610715 8, 0x0, sum = 2
4525 00:59:42.612951 9, 0x0, sum = 3
4526 00:59:42.613640 10, 0x0, sum = 4
4527 00:59:42.616417 best_step = 8
4528 00:59:42.617043
4529 00:59:42.617421 ==
4530 00:59:42.619639 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 00:59:42.623522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 00:59:42.624098 ==
4533 00:59:42.624470 RX Vref Scan: 0
4534 00:59:42.627817
4535 00:59:42.628378 RX Vref 0 -> 0, step: 1
4536 00:59:42.628791
4537 00:59:42.629493 RX Delay -195 -> 252, step: 8
4538 00:59:42.636658 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4539 00:59:42.639812 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4540 00:59:42.643086 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4541 00:59:42.645963 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4542 00:59:42.652936 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4543 00:59:42.656256 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4544 00:59:42.659437 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4545 00:59:42.663227 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4546 00:59:42.669324 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4547 00:59:42.672463 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4548 00:59:42.676321 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4549 00:59:42.679030 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4550 00:59:42.682839 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4551 00:59:42.689330 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4552 00:59:42.692346 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4553 00:59:42.695702 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4554 00:59:42.696270 ==
4555 00:59:42.698872 Dram Type= 6, Freq= 0, CH_1, rank 1
4556 00:59:42.705468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4557 00:59:42.706035 ==
4558 00:59:42.706406 DQS Delay:
4559 00:59:42.710078 DQS0 = 0, DQS1 = 0
4560 00:59:42.710631 DQM Delay:
4561 00:59:42.710999 DQM0 = 37, DQM1 = 28
4562 00:59:42.712289 DQ Delay:
4563 00:59:42.715404 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4564 00:59:42.718300 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4565 00:59:42.722394 DQ8 =12, DQ9 =12, DQ10 =28, DQ11 =20
4566 00:59:42.725647 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4567 00:59:42.726207
4568 00:59:42.726576
4569 00:59:42.732305 [DQSOSCAuto] RK1, (LSB)MR18= 0x5555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4570 00:59:42.736430 CH1 RK1: MR19=808, MR18=5555
4571 00:59:42.742026 CH1_RK1: MR19=0x808, MR18=0x5555, DQSOSC=393, MR23=63, INC=169, DEC=113
4572 00:59:42.744890 [RxdqsGatingPostProcess] freq 600
4573 00:59:42.748446 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4574 00:59:42.752408 Pre-setting of DQS Precalculation
4575 00:59:42.758580 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4576 00:59:42.764589 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4577 00:59:42.772012 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4578 00:59:42.772605
4579 00:59:42.773121
4580 00:59:42.774523 [Calibration Summary] 1200 Mbps
4581 00:59:42.777841 CH 0, Rank 0
4582 00:59:42.778313 SW Impedance : PASS
4583 00:59:42.781547 DUTY Scan : NO K
4584 00:59:42.785172 ZQ Calibration : PASS
4585 00:59:42.785740 Jitter Meter : NO K
4586 00:59:42.787803 CBT Training : PASS
4587 00:59:42.788375 Write leveling : PASS
4588 00:59:42.792449 RX DQS gating : PASS
4589 00:59:42.794729 RX DQ/DQS(RDDQC) : PASS
4590 00:59:42.795200 TX DQ/DQS : PASS
4591 00:59:42.797943 RX DATLAT : PASS
4592 00:59:42.800953 RX DQ/DQS(Engine): PASS
4593 00:59:42.801427 TX OE : NO K
4594 00:59:42.804325 All Pass.
4595 00:59:42.805092
4596 00:59:42.805578 CH 0, Rank 1
4597 00:59:42.807487 SW Impedance : PASS
4598 00:59:42.807961 DUTY Scan : NO K
4599 00:59:42.811133 ZQ Calibration : PASS
4600 00:59:42.814381 Jitter Meter : NO K
4601 00:59:42.814954 CBT Training : PASS
4602 00:59:42.817644 Write leveling : PASS
4603 00:59:42.821072 RX DQS gating : PASS
4604 00:59:42.821643 RX DQ/DQS(RDDQC) : PASS
4605 00:59:42.823831 TX DQ/DQS : PASS
4606 00:59:42.827822 RX DATLAT : PASS
4607 00:59:42.828421 RX DQ/DQS(Engine): PASS
4608 00:59:42.830524 TX OE : NO K
4609 00:59:42.830999 All Pass.
4610 00:59:42.831361
4611 00:59:42.834081 CH 1, Rank 0
4612 00:59:42.834714 SW Impedance : PASS
4613 00:59:42.837567 DUTY Scan : NO K
4614 00:59:42.840821 ZQ Calibration : PASS
4615 00:59:42.841375 Jitter Meter : NO K
4616 00:59:42.844670 CBT Training : PASS
4617 00:59:42.845287 Write leveling : PASS
4618 00:59:42.847555 RX DQS gating : PASS
4619 00:59:42.850997 RX DQ/DQS(RDDQC) : PASS
4620 00:59:42.851486 TX DQ/DQS : PASS
4621 00:59:42.853610 RX DATLAT : PASS
4622 00:59:42.856774 RX DQ/DQS(Engine): PASS
4623 00:59:42.857240 TX OE : NO K
4624 00:59:42.860684 All Pass.
4625 00:59:42.861191
4626 00:59:42.861554 CH 1, Rank 1
4627 00:59:42.863520 SW Impedance : PASS
4628 00:59:42.863973 DUTY Scan : NO K
4629 00:59:42.867510 ZQ Calibration : PASS
4630 00:59:42.870585 Jitter Meter : NO K
4631 00:59:42.871043 CBT Training : PASS
4632 00:59:42.874797 Write leveling : PASS
4633 00:59:42.877302 RX DQS gating : PASS
4634 00:59:42.877757 RX DQ/DQS(RDDQC) : PASS
4635 00:59:42.880786 TX DQ/DQS : PASS
4636 00:59:42.883462 RX DATLAT : PASS
4637 00:59:42.883914 RX DQ/DQS(Engine): PASS
4638 00:59:42.886966 TX OE : NO K
4639 00:59:42.887423 All Pass.
4640 00:59:42.887780
4641 00:59:42.889938 DramC Write-DBI off
4642 00:59:42.893933 PER_BANK_REFRESH: Hybrid Mode
4643 00:59:42.894490 TX_TRACKING: ON
4644 00:59:42.903908 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4645 00:59:42.906834 [FAST_K] Save calibration result to emmc
4646 00:59:42.911073 dramc_set_vcore_voltage set vcore to 662500
4647 00:59:42.913538 Read voltage for 933, 3
4648 00:59:42.913996 Vio18 = 0
4649 00:59:42.914359 Vcore = 662500
4650 00:59:42.917246 Vdram = 0
4651 00:59:42.917805 Vddq = 0
4652 00:59:42.918169 Vmddr = 0
4653 00:59:42.925614 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4654 00:59:42.926687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4655 00:59:42.929856 MEM_TYPE=3, freq_sel=17
4656 00:59:42.932932 sv_algorithm_assistance_LP4_1600
4657 00:59:42.936494 ============ PULL DRAM RESETB DOWN ============
4658 00:59:42.939524 ========== PULL DRAM RESETB DOWN end =========
4659 00:59:42.946794 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4660 00:59:42.949372 ===================================
4661 00:59:42.953285 LPDDR4 DRAM CONFIGURATION
4662 00:59:42.956329 ===================================
4663 00:59:42.957224 EX_ROW_EN[0] = 0x0
4664 00:59:42.959830 EX_ROW_EN[1] = 0x0
4665 00:59:42.960403 LP4Y_EN = 0x0
4666 00:59:42.963019 WORK_FSP = 0x0
4667 00:59:42.963573 WL = 0x3
4668 00:59:42.966649 RL = 0x3
4669 00:59:42.967107 BL = 0x2
4670 00:59:42.969204 RPST = 0x0
4671 00:59:42.969658 RD_PRE = 0x0
4672 00:59:42.972959 WR_PRE = 0x1
4673 00:59:42.973515 WR_PST = 0x0
4674 00:59:42.976494 DBI_WR = 0x0
4675 00:59:42.977165 DBI_RD = 0x0
4676 00:59:42.979183 OTF = 0x1
4677 00:59:42.982693 ===================================
4678 00:59:42.985756 ===================================
4679 00:59:42.986316 ANA top config
4680 00:59:42.989695 ===================================
4681 00:59:42.992652 DLL_ASYNC_EN = 0
4682 00:59:42.997013 ALL_SLAVE_EN = 1
4683 00:59:42.999291 NEW_RANK_MODE = 1
4684 00:59:43.003053 DLL_IDLE_MODE = 1
4685 00:59:43.003608 LP45_APHY_COMB_EN = 1
4686 00:59:43.005790 TX_ODT_DIS = 1
4687 00:59:43.008919 NEW_8X_MODE = 1
4688 00:59:43.012475 ===================================
4689 00:59:43.016080 ===================================
4690 00:59:43.019563 data_rate = 1866
4691 00:59:43.022563 CKR = 1
4692 00:59:43.023121 DQ_P2S_RATIO = 8
4693 00:59:43.025495 ===================================
4694 00:59:43.028876 CA_P2S_RATIO = 8
4695 00:59:43.032170 DQ_CA_OPEN = 0
4696 00:59:43.035696 DQ_SEMI_OPEN = 0
4697 00:59:43.038955 CA_SEMI_OPEN = 0
4698 00:59:43.042429 CA_FULL_RATE = 0
4699 00:59:43.042891 DQ_CKDIV4_EN = 1
4700 00:59:43.046022 CA_CKDIV4_EN = 1
4701 00:59:43.049096 CA_PREDIV_EN = 0
4702 00:59:43.052271 PH8_DLY = 0
4703 00:59:43.057490 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4704 00:59:43.058795 DQ_AAMCK_DIV = 4
4705 00:59:43.059271 CA_AAMCK_DIV = 4
4706 00:59:43.062690 CA_ADMCK_DIV = 4
4707 00:59:43.065624 DQ_TRACK_CA_EN = 0
4708 00:59:43.068890 CA_PICK = 933
4709 00:59:43.072776 CA_MCKIO = 933
4710 00:59:43.075080 MCKIO_SEMI = 0
4711 00:59:43.078984 PLL_FREQ = 3732
4712 00:59:43.079646 DQ_UI_PI_RATIO = 32
4713 00:59:43.082766 CA_UI_PI_RATIO = 0
4714 00:59:43.085198 ===================================
4715 00:59:43.088575 ===================================
4716 00:59:43.091921 memory_type:LPDDR4
4717 00:59:43.095116 GP_NUM : 10
4718 00:59:43.095676 SRAM_EN : 1
4719 00:59:43.098684 MD32_EN : 0
4720 00:59:43.101928 ===================================
4721 00:59:43.105905 [ANA_INIT] >>>>>>>>>>>>>>
4722 00:59:43.106464 <<<<<< [CONFIGURE PHASE]: ANA_TX
4723 00:59:43.109181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4724 00:59:43.112355 ===================================
4725 00:59:43.115328 data_rate = 1866,PCW = 0X8f00
4726 00:59:43.119839 ===================================
4727 00:59:43.122923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4728 00:59:43.128588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4729 00:59:43.136770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4730 00:59:43.137747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4731 00:59:43.141428 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4732 00:59:43.145171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4733 00:59:43.148074 [ANA_INIT] flow start
4734 00:59:43.148629 [ANA_INIT] PLL >>>>>>>>
4735 00:59:43.151449 [ANA_INIT] PLL <<<<<<<<
4736 00:59:43.155434 [ANA_INIT] MIDPI >>>>>>>>
4737 00:59:43.157784 [ANA_INIT] MIDPI <<<<<<<<
4738 00:59:43.158510 [ANA_INIT] DLL >>>>>>>>
4739 00:59:43.160906 [ANA_INIT] flow end
4740 00:59:43.166234 ============ LP4 DIFF to SE enter ============
4741 00:59:43.167964 ============ LP4 DIFF to SE exit ============
4742 00:59:43.171809 [ANA_INIT] <<<<<<<<<<<<<
4743 00:59:43.174658 [Flow] Enable top DCM control >>>>>
4744 00:59:43.177527 [Flow] Enable top DCM control <<<<<
4745 00:59:43.180935 Enable DLL master slave shuffle
4746 00:59:43.188076 ==============================================================
4747 00:59:43.188634 Gating Mode config
4748 00:59:43.194573 ==============================================================
4749 00:59:43.195131 Config description:
4750 00:59:43.204397 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4751 00:59:43.211231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4752 00:59:43.217695 SELPH_MODE 0: By rank 1: By Phase
4753 00:59:43.221024 ==============================================================
4754 00:59:43.224640 GAT_TRACK_EN = 1
4755 00:59:43.227933 RX_GATING_MODE = 2
4756 00:59:43.230887 RX_GATING_TRACK_MODE = 2
4757 00:59:43.234382 SELPH_MODE = 1
4758 00:59:43.237653 PICG_EARLY_EN = 1
4759 00:59:43.241235 VALID_LAT_VALUE = 1
4760 00:59:43.247544 ==============================================================
4761 00:59:43.250660 Enter into Gating configuration >>>>
4762 00:59:43.253943 Exit from Gating configuration <<<<
4763 00:59:43.254409 Enter into DVFS_PRE_config >>>>>
4764 00:59:43.267035 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4765 00:59:43.270304 Exit from DVFS_PRE_config <<<<<
4766 00:59:43.274419 Enter into PICG configuration >>>>
4767 00:59:43.278407 Exit from PICG configuration <<<<
4768 00:59:43.278876 [RX_INPUT] configuration >>>>>
4769 00:59:43.281397 [RX_INPUT] configuration <<<<<
4770 00:59:43.287604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4771 00:59:43.291074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4772 00:59:43.297539 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4773 00:59:43.304910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4774 00:59:43.310894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4775 00:59:43.317149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4776 00:59:43.320994 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4777 00:59:43.323877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4778 00:59:43.330396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4779 00:59:43.333862 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4780 00:59:43.337019 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4781 00:59:43.342914 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4782 00:59:43.346674 ===================================
4783 00:59:43.347235 LPDDR4 DRAM CONFIGURATION
4784 00:59:43.349933 ===================================
4785 00:59:43.353260 EX_ROW_EN[0] = 0x0
4786 00:59:43.353813 EX_ROW_EN[1] = 0x0
4787 00:59:43.356944 LP4Y_EN = 0x0
4788 00:59:43.357521 WORK_FSP = 0x0
4789 00:59:43.359607 WL = 0x3
4790 00:59:43.363265 RL = 0x3
4791 00:59:43.363844 BL = 0x2
4792 00:59:43.367811 RPST = 0x0
4793 00:59:43.368369 RD_PRE = 0x0
4794 00:59:43.369837 WR_PRE = 0x1
4795 00:59:43.370302 WR_PST = 0x0
4796 00:59:43.373033 DBI_WR = 0x0
4797 00:59:43.373497 DBI_RD = 0x0
4798 00:59:43.376113 OTF = 0x1
4799 00:59:43.380420 ===================================
4800 00:59:43.382791 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4801 00:59:43.386359 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4802 00:59:43.390423 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4803 00:59:43.393043 ===================================
4804 00:59:43.395909 LPDDR4 DRAM CONFIGURATION
4805 00:59:43.399928 ===================================
4806 00:59:43.403149 EX_ROW_EN[0] = 0x10
4807 00:59:43.403315 EX_ROW_EN[1] = 0x0
4808 00:59:43.405575 LP4Y_EN = 0x0
4809 00:59:43.405737 WORK_FSP = 0x0
4810 00:59:43.409963 WL = 0x3
4811 00:59:43.410128 RL = 0x3
4812 00:59:43.412678 BL = 0x2
4813 00:59:43.416528 RPST = 0x0
4814 00:59:43.416698 RD_PRE = 0x0
4815 00:59:43.419681 WR_PRE = 0x1
4816 00:59:43.419853 WR_PST = 0x0
4817 00:59:43.422543 DBI_WR = 0x0
4818 00:59:43.422719 DBI_RD = 0x0
4819 00:59:43.425782 OTF = 0x1
4820 00:59:43.429296 ===================================
4821 00:59:43.432899 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4822 00:59:43.437983 nWR fixed to 30
4823 00:59:43.440964 [ModeRegInit_LP4] CH0 RK0
4824 00:59:43.441178 [ModeRegInit_LP4] CH0 RK1
4825 00:59:43.445219 [ModeRegInit_LP4] CH1 RK0
4826 00:59:43.448104 [ModeRegInit_LP4] CH1 RK1
4827 00:59:43.448348 match AC timing 8
4828 00:59:43.454605 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4829 00:59:43.457783 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4830 00:59:43.461429 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4831 00:59:43.467781 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4832 00:59:43.471108 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4833 00:59:43.471686 ==
4834 00:59:43.475094 Dram Type= 6, Freq= 0, CH_0, rank 0
4835 00:59:43.477950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4836 00:59:43.478418 ==
4837 00:59:43.484416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4838 00:59:43.491477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4839 00:59:43.496060 [CA 0] Center 38 (8~69) winsize 62
4840 00:59:43.497662 [CA 1] Center 38 (8~69) winsize 62
4841 00:59:43.501139 [CA 2] Center 36 (6~67) winsize 62
4842 00:59:43.504895 [CA 3] Center 36 (6~67) winsize 62
4843 00:59:43.507758 [CA 4] Center 34 (4~65) winsize 62
4844 00:59:43.512069 [CA 5] Center 34 (4~65) winsize 62
4845 00:59:43.512629
4846 00:59:43.514710 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4847 00:59:43.515267
4848 00:59:43.518072 [CATrainingPosCal] consider 1 rank data
4849 00:59:43.522532 u2DelayCellTimex100 = 270/100 ps
4850 00:59:43.523824 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4851 00:59:43.527891 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4852 00:59:43.531409 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4853 00:59:43.535639 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4854 00:59:43.541035 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4855 00:59:43.544383 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4856 00:59:43.545015
4857 00:59:43.549077 CA PerBit enable=1, Macro0, CA PI delay=34
4858 00:59:43.549636
4859 00:59:43.550738 [CBTSetCACLKResult] CA Dly = 34
4860 00:59:43.551202 CS Dly: 7 (0~38)
4861 00:59:43.551566 ==
4862 00:59:43.553985 Dram Type= 6, Freq= 0, CH_0, rank 1
4863 00:59:43.560544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4864 00:59:43.561138 ==
4865 00:59:43.564074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4866 00:59:43.570190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4867 00:59:43.573532 [CA 0] Center 38 (8~69) winsize 62
4868 00:59:43.577305 [CA 1] Center 38 (8~69) winsize 62
4869 00:59:43.581284 [CA 2] Center 36 (5~67) winsize 63
4870 00:59:43.583631 [CA 3] Center 35 (5~66) winsize 62
4871 00:59:43.587305 [CA 4] Center 34 (4~65) winsize 62
4872 00:59:43.589945 [CA 5] Center 34 (4~65) winsize 62
4873 00:59:43.590409
4874 00:59:43.593923 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4875 00:59:43.594487
4876 00:59:43.597497 [CATrainingPosCal] consider 2 rank data
4877 00:59:43.600294 u2DelayCellTimex100 = 270/100 ps
4878 00:59:43.603804 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4879 00:59:43.606774 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4880 00:59:43.610755 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4881 00:59:43.616947 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4882 00:59:43.620197 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4883 00:59:43.623824 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4884 00:59:43.624392
4885 00:59:43.626551 CA PerBit enable=1, Macro0, CA PI delay=34
4886 00:59:43.627011
4887 00:59:43.630411 [CBTSetCACLKResult] CA Dly = 34
4888 00:59:43.630973 CS Dly: 7 (0~39)
4889 00:59:43.631343
4890 00:59:43.636847 ----->DramcWriteLeveling(PI) begin...
4891 00:59:43.637422 ==
4892 00:59:43.639753 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 00:59:43.643555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 00:59:43.644125 ==
4895 00:59:43.647545 Write leveling (Byte 0): 30 => 30
4896 00:59:43.649590 Write leveling (Byte 1): 26 => 26
4897 00:59:43.652973 DramcWriteLeveling(PI) end<-----
4898 00:59:43.653530
4899 00:59:43.653896 ==
4900 00:59:43.656442 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 00:59:43.660218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 00:59:43.660961 ==
4903 00:59:43.663145 [Gating] SW mode calibration
4904 00:59:43.669796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4905 00:59:43.676455 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4906 00:59:43.679954 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 00:59:43.682858 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 00:59:43.689702 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 00:59:43.692885 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 00:59:43.696266 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 00:59:43.703232 0 10 20 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
4912 00:59:43.706716 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
4913 00:59:43.709081 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 00:59:43.716405 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 00:59:43.719270 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 00:59:43.724037 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 00:59:43.728825 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 00:59:43.732799 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 00:59:43.735638 0 11 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4920 00:59:43.741989 0 11 24 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4921 00:59:43.746168 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 00:59:43.749420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 00:59:43.755643 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 00:59:43.759425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 00:59:43.762132 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 00:59:43.768940 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4927 00:59:43.772834 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4928 00:59:43.775638 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 00:59:43.781623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 00:59:43.785043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 00:59:43.788318 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 00:59:43.795411 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 00:59:43.798822 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 00:59:43.802004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 00:59:43.804694 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 00:59:43.812476 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 00:59:43.815782 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 00:59:43.818203 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 00:59:43.825955 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 00:59:43.829064 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 00:59:43.834835 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 00:59:43.838333 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 00:59:43.841032 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 00:59:43.844491 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4945 00:59:43.847998 Total UI for P1: 0, mck2ui 16
4946 00:59:43.851240 best dqsien dly found for B1: ( 0, 14, 22)
4947 00:59:43.858910 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4948 00:59:43.861577 Total UI for P1: 0, mck2ui 16
4949 00:59:43.865378 best dqsien dly found for B0: ( 0, 14, 24)
4950 00:59:43.868065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
4951 00:59:43.871334 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4952 00:59:43.871896
4953 00:59:43.874684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
4954 00:59:43.878230 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4955 00:59:43.880667 [Gating] SW calibration Done
4956 00:59:43.881335 ==
4957 00:59:43.884437 Dram Type= 6, Freq= 0, CH_0, rank 0
4958 00:59:43.887719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4959 00:59:43.891065 ==
4960 00:59:43.891539 RX Vref Scan: 0
4961 00:59:43.891902
4962 00:59:43.893954 RX Vref 0 -> 0, step: 1
4963 00:59:43.894409
4964 00:59:43.896953 RX Delay -80 -> 252, step: 8
4965 00:59:43.900543 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4966 00:59:43.903970 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4967 00:59:43.907657 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4968 00:59:43.910336 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4969 00:59:43.914224 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4970 00:59:43.921324 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4971 00:59:43.924002 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4972 00:59:43.927161 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4973 00:59:43.930457 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4974 00:59:43.933559 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
4975 00:59:43.942501 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4976 00:59:43.943901 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
4977 00:59:43.947316 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4978 00:59:43.949971 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4979 00:59:43.954183 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4980 00:59:43.957504 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4981 00:59:43.960423 ==
4982 00:59:43.963835 Dram Type= 6, Freq= 0, CH_0, rank 0
4983 00:59:43.968016 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4984 00:59:43.968574 ==
4985 00:59:43.969021 DQS Delay:
4986 00:59:43.970588 DQS0 = 0, DQS1 = 0
4987 00:59:43.971040 DQM Delay:
4988 00:59:43.973311 DQM0 = 96, DQM1 = 85
4989 00:59:43.973766 DQ Delay:
4990 00:59:43.977351 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4991 00:59:43.980293 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
4992 00:59:43.983950 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
4993 00:59:43.986931 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
4994 00:59:43.987492
4995 00:59:43.987854
4996 00:59:43.988186 ==
4997 00:59:43.989925 Dram Type= 6, Freq= 0, CH_0, rank 0
4998 00:59:43.994070 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4999 00:59:43.994629 ==
5000 00:59:43.994991
5001 00:59:43.995327
5002 00:59:43.996262 TX Vref Scan disable
5003 00:59:44.001344 == TX Byte 0 ==
5004 00:59:44.003651 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5005 00:59:44.007350 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5006 00:59:44.010067 == TX Byte 1 ==
5007 00:59:44.013146 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5008 00:59:44.016532 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5009 00:59:44.017128 ==
5010 00:59:44.019673 Dram Type= 6, Freq= 0, CH_0, rank 0
5011 00:59:44.026436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5012 00:59:44.027167 ==
5013 00:59:44.027541
5014 00:59:44.027875
5015 00:59:44.028202 TX Vref Scan disable
5016 00:59:44.030483 == TX Byte 0 ==
5017 00:59:44.033504 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5018 00:59:44.041331 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5019 00:59:44.042010 == TX Byte 1 ==
5020 00:59:44.043557 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5021 00:59:44.050196 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5022 00:59:44.050768
5023 00:59:44.051130 [DATLAT]
5024 00:59:44.051466 Freq=933, CH0 RK0
5025 00:59:44.051790
5026 00:59:44.053632 DATLAT Default: 0xd
5027 00:59:44.054088 0, 0xFFFF, sum = 0
5028 00:59:44.057254 1, 0xFFFF, sum = 0
5029 00:59:44.060177 2, 0xFFFF, sum = 0
5030 00:59:44.060643 3, 0xFFFF, sum = 0
5031 00:59:44.063203 4, 0xFFFF, sum = 0
5032 00:59:44.063672 5, 0xFFFF, sum = 0
5033 00:59:44.066703 6, 0xFFFF, sum = 0
5034 00:59:44.067175 7, 0xFFFF, sum = 0
5035 00:59:44.069985 8, 0xFFFF, sum = 0
5036 00:59:44.070491 9, 0xFFFF, sum = 0
5037 00:59:44.074927 10, 0x0, sum = 1
5038 00:59:44.075488 11, 0x0, sum = 2
5039 00:59:44.076358 12, 0x0, sum = 3
5040 00:59:44.076814 13, 0x0, sum = 4
5041 00:59:44.077187 best_step = 11
5042 00:59:44.080074
5043 00:59:44.080636 ==
5044 00:59:44.083141 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 00:59:44.087202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5046 00:59:44.087756 ==
5047 00:59:44.088123 RX Vref Scan: 1
5048 00:59:44.088466
5049 00:59:44.089623 RX Vref 0 -> 0, step: 1
5050 00:59:44.090087
5051 00:59:44.093569 RX Delay -77 -> 252, step: 4
5052 00:59:44.094126
5053 00:59:44.097455 Set Vref, RX VrefLevel [Byte0]: 48
5054 00:59:44.100032 [Byte1]: 50
5055 00:59:44.103066
5056 00:59:44.103625 Final RX Vref Byte 0 = 48 to rank0
5057 00:59:44.106907 Final RX Vref Byte 1 = 50 to rank0
5058 00:59:44.110071 Final RX Vref Byte 0 = 48 to rank1
5059 00:59:44.113320 Final RX Vref Byte 1 = 50 to rank1==
5060 00:59:44.116247 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 00:59:44.123108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5062 00:59:44.123689 ==
5063 00:59:44.124062 DQS Delay:
5064 00:59:44.126191 DQS0 = 0, DQS1 = 0
5065 00:59:44.126654 DQM Delay:
5066 00:59:44.127038 DQM0 = 96, DQM1 = 88
5067 00:59:44.129377 DQ Delay:
5068 00:59:44.132899 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5069 00:59:44.136152 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =102
5070 00:59:44.139407 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =80
5071 00:59:44.142802 DQ12 =94, DQ13 =96, DQ14 =100, DQ15 =100
5072 00:59:44.143266
5073 00:59:44.143630
5074 00:59:44.149346 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5075 00:59:44.153172 CH0 RK0: MR19=505, MR18=1F1F
5076 00:59:44.159329 CH0_RK0: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5077 00:59:44.159796
5078 00:59:44.162535 ----->DramcWriteLeveling(PI) begin...
5079 00:59:44.163024 ==
5080 00:59:44.166467 Dram Type= 6, Freq= 0, CH_0, rank 1
5081 00:59:44.168788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5082 00:59:44.169256 ==
5083 00:59:44.172540 Write leveling (Byte 0): 29 => 29
5084 00:59:44.176456 Write leveling (Byte 1): 27 => 27
5085 00:59:44.178745 DramcWriteLeveling(PI) end<-----
5086 00:59:44.179215
5087 00:59:44.179582 ==
5088 00:59:44.183193 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 00:59:44.189233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5090 00:59:44.189790 ==
5091 00:59:44.190163 [Gating] SW mode calibration
5092 00:59:44.198679 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5093 00:59:44.202615 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5094 00:59:44.205224 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 00:59:44.212377 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 00:59:44.215486 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 00:59:44.218571 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 00:59:44.225523 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 00:59:44.230418 0 10 20 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
5100 00:59:44.232556 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 00:59:44.239596 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 00:59:44.242218 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 00:59:44.246033 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 00:59:44.252034 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 00:59:44.254686 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 00:59:44.258403 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5107 00:59:44.265602 0 11 20 | B1->B0 | 2929 3636 | 1 0 | (0 0) (1 1)
5108 00:59:44.268303 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5109 00:59:44.271402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 00:59:44.278332 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 00:59:44.281404 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 00:59:44.284749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 00:59:44.291536 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 00:59:44.294894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 00:59:44.299198 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5116 00:59:44.304669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 00:59:44.308212 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 00:59:44.311642 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 00:59:44.317928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 00:59:44.321519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 00:59:44.324489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 00:59:44.331667 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 00:59:44.334899 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 00:59:44.337610 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:59:44.344936 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:59:44.347961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:59:44.351804 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:59:44.358175 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:59:44.360911 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 00:59:44.363821 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 00:59:44.371985 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5132 00:59:44.373984 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:59:44.377447 Total UI for P1: 0, mck2ui 16
5134 00:59:44.381154 best dqsien dly found for B0: ( 0, 14, 20)
5135 00:59:44.384689 Total UI for P1: 0, mck2ui 16
5136 00:59:44.388637 best dqsien dly found for B1: ( 0, 14, 20)
5137 00:59:44.391044 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5138 00:59:44.394070 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5139 00:59:44.394633
5140 00:59:44.397343 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5141 00:59:44.401182 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5142 00:59:44.404525 [Gating] SW calibration Done
5143 00:59:44.405156 ==
5144 00:59:44.407031 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 00:59:44.410890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5146 00:59:44.414497 ==
5147 00:59:44.415059 RX Vref Scan: 0
5148 00:59:44.415432
5149 00:59:44.417123 RX Vref 0 -> 0, step: 1
5150 00:59:44.417589
5151 00:59:44.420630 RX Delay -80 -> 252, step: 8
5152 00:59:44.423352 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5153 00:59:44.427376 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5154 00:59:44.430684 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5155 00:59:44.433620 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5156 00:59:44.437041 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5157 00:59:44.443403 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5158 00:59:44.447733 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5159 00:59:44.450144 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5160 00:59:44.453336 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5161 00:59:44.456649 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5162 00:59:44.463207 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5163 00:59:44.467048 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5164 00:59:44.470380 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5165 00:59:44.473030 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5166 00:59:44.476985 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5167 00:59:44.480233 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5168 00:59:44.483602 ==
5169 00:59:44.486605 Dram Type= 6, Freq= 0, CH_0, rank 1
5170 00:59:44.490539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5171 00:59:44.491213 ==
5172 00:59:44.491593 DQS Delay:
5173 00:59:44.493285 DQS0 = 0, DQS1 = 0
5174 00:59:44.493748 DQM Delay:
5175 00:59:44.496405 DQM0 = 95, DQM1 = 85
5176 00:59:44.497031 DQ Delay:
5177 00:59:44.500689 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5178 00:59:44.503233 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5179 00:59:44.506953 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =75
5180 00:59:44.510195 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5181 00:59:44.510657
5182 00:59:44.511021
5183 00:59:44.511358 ==
5184 00:59:44.513048 Dram Type= 6, Freq= 0, CH_0, rank 1
5185 00:59:44.516195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5186 00:59:44.516765 ==
5187 00:59:44.517156
5188 00:59:44.519667
5189 00:59:44.520126 TX Vref Scan disable
5190 00:59:44.523355 == TX Byte 0 ==
5191 00:59:44.526674 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5192 00:59:44.529724 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5193 00:59:44.533333 == TX Byte 1 ==
5194 00:59:44.536133 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5195 00:59:44.538979 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5196 00:59:44.539441 ==
5197 00:59:44.543446 Dram Type= 6, Freq= 0, CH_0, rank 1
5198 00:59:44.549560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5199 00:59:44.550024 ==
5200 00:59:44.550442
5201 00:59:44.550778
5202 00:59:44.551098 TX Vref Scan disable
5203 00:59:44.554050 == TX Byte 0 ==
5204 00:59:44.556815 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5205 00:59:44.564228 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5206 00:59:44.564870 == TX Byte 1 ==
5207 00:59:44.566248 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5208 00:59:44.572870 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5209 00:59:44.573359
5210 00:59:44.573721 [DATLAT]
5211 00:59:44.574064 Freq=933, CH0 RK1
5212 00:59:44.574391
5213 00:59:44.576528 DATLAT Default: 0xb
5214 00:59:44.580175 0, 0xFFFF, sum = 0
5215 00:59:44.580694 1, 0xFFFF, sum = 0
5216 00:59:44.584138 2, 0xFFFF, sum = 0
5217 00:59:44.584658 3, 0xFFFF, sum = 0
5218 00:59:44.586337 4, 0xFFFF, sum = 0
5219 00:59:44.586759 5, 0xFFFF, sum = 0
5220 00:59:44.590368 6, 0xFFFF, sum = 0
5221 00:59:44.590886 7, 0xFFFF, sum = 0
5222 00:59:44.592958 8, 0xFFFF, sum = 0
5223 00:59:44.593384 9, 0xFFFF, sum = 0
5224 00:59:44.597188 10, 0x0, sum = 1
5225 00:59:44.597824 11, 0x0, sum = 2
5226 00:59:44.599666 12, 0x0, sum = 3
5227 00:59:44.600224 13, 0x0, sum = 4
5228 00:59:44.604086 best_step = 11
5229 00:59:44.604600
5230 00:59:44.604992 ==
5231 00:59:44.606777 Dram Type= 6, Freq= 0, CH_0, rank 1
5232 00:59:44.609887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5233 00:59:44.610309 ==
5234 00:59:44.610640 RX Vref Scan: 0
5235 00:59:44.610946
5236 00:59:44.612653 RX Vref 0 -> 0, step: 1
5237 00:59:44.613101
5238 00:59:44.616674 RX Delay -69 -> 252, step: 4
5239 00:59:44.623204 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5240 00:59:44.626966 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5241 00:59:44.629279 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5242 00:59:44.633216 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5243 00:59:44.636313 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5244 00:59:44.640572 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5245 00:59:44.646227 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5246 00:59:44.649637 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5247 00:59:44.653399 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5248 00:59:44.656759 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5249 00:59:44.660255 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5250 00:59:44.665881 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5251 00:59:44.669309 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5252 00:59:44.672589 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5253 00:59:44.676184 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5254 00:59:44.680095 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5255 00:59:44.680608 ==
5256 00:59:44.682350 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 00:59:44.689327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5258 00:59:44.689839 ==
5259 00:59:44.690173 DQS Delay:
5260 00:59:44.692377 DQS0 = 0, DQS1 = 0
5261 00:59:44.692930 DQM Delay:
5262 00:59:44.693270 DQM0 = 97, DQM1 = 86
5263 00:59:44.696566 DQ Delay:
5264 00:59:44.698611 DQ0 =92, DQ1 =98, DQ2 =98, DQ3 =90
5265 00:59:44.702364 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =108
5266 00:59:44.706594 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5267 00:59:44.708864 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5268 00:59:44.709382
5269 00:59:44.709715
5270 00:59:44.715244 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5271 00:59:44.718746 CH0 RK1: MR19=505, MR18=2F2F
5272 00:59:44.725647 CH0_RK1: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5273 00:59:44.728957 [RxdqsGatingPostProcess] freq 933
5274 00:59:44.735535 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5275 00:59:44.736069 Pre-setting of DQS Precalculation
5276 00:59:44.742142 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5277 00:59:44.742658 ==
5278 00:59:44.744946 Dram Type= 6, Freq= 0, CH_1, rank 0
5279 00:59:44.749351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5280 00:59:44.749871 ==
5281 00:59:44.755144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5282 00:59:44.762143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5283 00:59:44.765333 [CA 0] Center 37 (7~68) winsize 62
5284 00:59:44.767957 [CA 1] Center 37 (6~68) winsize 63
5285 00:59:44.772389 [CA 2] Center 35 (5~65) winsize 61
5286 00:59:44.774919 [CA 3] Center 34 (4~65) winsize 62
5287 00:59:44.777991 [CA 4] Center 33 (3~64) winsize 62
5288 00:59:44.781576 [CA 5] Center 33 (3~63) winsize 61
5289 00:59:44.781994
5290 00:59:44.784655 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5291 00:59:44.785116
5292 00:59:44.787892 [CATrainingPosCal] consider 1 rank data
5293 00:59:44.791385 u2DelayCellTimex100 = 270/100 ps
5294 00:59:44.795307 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5295 00:59:44.798294 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5296 00:59:44.801442 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5297 00:59:44.804417 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5298 00:59:44.807984 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5299 00:59:44.814463 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5300 00:59:44.815084
5301 00:59:44.818014 CA PerBit enable=1, Macro0, CA PI delay=33
5302 00:59:44.818527
5303 00:59:44.822695 [CBTSetCACLKResult] CA Dly = 33
5304 00:59:44.823207 CS Dly: 5 (0~36)
5305 00:59:44.823535 ==
5306 00:59:44.824448 Dram Type= 6, Freq= 0, CH_1, rank 1
5307 00:59:44.827868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5308 00:59:44.830985 ==
5309 00:59:44.834188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5310 00:59:44.840937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5311 00:59:44.844284 [CA 0] Center 37 (6~68) winsize 63
5312 00:59:44.847980 [CA 1] Center 37 (6~68) winsize 63
5313 00:59:44.851055 [CA 2] Center 34 (4~65) winsize 62
5314 00:59:44.854369 [CA 3] Center 34 (4~65) winsize 62
5315 00:59:44.857638 [CA 4] Center 33 (3~64) winsize 62
5316 00:59:44.860837 [CA 5] Center 33 (2~64) winsize 63
5317 00:59:44.861299
5318 00:59:44.864158 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5319 00:59:44.864770
5320 00:59:44.867469 [CATrainingPosCal] consider 2 rank data
5321 00:59:44.870860 u2DelayCellTimex100 = 270/100 ps
5322 00:59:44.874707 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5323 00:59:44.877413 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5324 00:59:44.880683 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5325 00:59:44.887207 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5326 00:59:44.890868 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5327 00:59:44.894212 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5328 00:59:44.894776
5329 00:59:44.897532 CA PerBit enable=1, Macro0, CA PI delay=33
5330 00:59:44.898097
5331 00:59:44.900442 [CBTSetCACLKResult] CA Dly = 33
5332 00:59:44.901059 CS Dly: 5 (0~37)
5333 00:59:44.901429
5334 00:59:44.904084 ----->DramcWriteLeveling(PI) begin...
5335 00:59:44.904652 ==
5336 00:59:44.907701 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 00:59:44.913792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 00:59:44.914365 ==
5339 00:59:44.917329 Write leveling (Byte 0): 27 => 27
5340 00:59:44.920365 Write leveling (Byte 1): 24 => 24
5341 00:59:44.924036 DramcWriteLeveling(PI) end<-----
5342 00:59:44.924598
5343 00:59:44.925013 ==
5344 00:59:44.926982 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 00:59:44.930737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 00:59:44.931204 ==
5347 00:59:44.934605 [Gating] SW mode calibration
5348 00:59:44.940484 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 00:59:44.943804 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5350 00:59:44.950293 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 00:59:44.953407 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 00:59:44.956475 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 00:59:44.963432 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 00:59:44.967130 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5355 00:59:44.970504 0 10 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5356 00:59:44.976600 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5357 00:59:44.980149 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 00:59:44.983079 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 00:59:44.990192 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 00:59:44.992797 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 00:59:44.996038 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 00:59:45.003461 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5363 00:59:45.006693 0 11 20 | B1->B0 | 2b2b 3d3d | 0 1 | (0 0) (0 0)
5364 00:59:45.010090 0 11 24 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5365 00:59:45.017644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 00:59:45.019636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 00:59:45.023640 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 00:59:45.029945 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 00:59:45.033199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 00:59:45.036011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5371 00:59:45.042632 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 00:59:45.046193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 00:59:45.049358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 00:59:45.056269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 00:59:45.059905 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 00:59:45.062426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 00:59:45.069231 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 00:59:45.072924 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 00:59:45.076081 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 00:59:45.082802 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 00:59:45.086022 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 00:59:45.089332 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 00:59:45.096000 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 00:59:45.099005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 00:59:45.102396 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 00:59:45.108947 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5387 00:59:45.112658 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5388 00:59:45.115918 Total UI for P1: 0, mck2ui 16
5389 00:59:45.118685 best dqsien dly found for B0: ( 0, 14, 16)
5390 00:59:45.122173 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5391 00:59:45.129596 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 00:59:45.130160 Total UI for P1: 0, mck2ui 16
5393 00:59:45.132604 best dqsien dly found for B1: ( 0, 14, 20)
5394 00:59:45.139579 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5395 00:59:45.142004 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5396 00:59:45.142567
5397 00:59:45.145152 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5398 00:59:45.149089 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5399 00:59:45.152370 [Gating] SW calibration Done
5400 00:59:45.152977 ==
5401 00:59:45.156025 Dram Type= 6, Freq= 0, CH_1, rank 0
5402 00:59:45.158935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5403 00:59:45.159731 ==
5404 00:59:45.162187 RX Vref Scan: 0
5405 00:59:45.162645
5406 00:59:45.163006 RX Vref 0 -> 0, step: 1
5407 00:59:45.163342
5408 00:59:45.165393 RX Delay -80 -> 252, step: 8
5409 00:59:45.168496 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5410 00:59:45.175264 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5411 00:59:45.179446 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5412 00:59:45.182092 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5413 00:59:45.185247 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5414 00:59:45.188553 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5415 00:59:45.192147 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5416 00:59:45.198456 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5417 00:59:45.202184 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5418 00:59:45.205072 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5419 00:59:45.208297 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5420 00:59:45.211288 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5421 00:59:45.218658 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5422 00:59:45.221671 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5423 00:59:45.225250 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5424 00:59:45.227857 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5425 00:59:45.228419 ==
5426 00:59:45.231570 Dram Type= 6, Freq= 0, CH_1, rank 0
5427 00:59:45.237506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5428 00:59:45.238059 ==
5429 00:59:45.238427 DQS Delay:
5430 00:59:45.240830 DQS0 = 0, DQS1 = 0
5431 00:59:45.241385 DQM Delay:
5432 00:59:45.241752 DQM0 = 95, DQM1 = 88
5433 00:59:45.244573 DQ Delay:
5434 00:59:45.248071 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5435 00:59:45.251576 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5436 00:59:45.254812 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5437 00:59:45.257386 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5438 00:59:45.257936
5439 00:59:45.258303
5440 00:59:45.258642 ==
5441 00:59:45.260858 Dram Type= 6, Freq= 0, CH_1, rank 0
5442 00:59:45.264568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5443 00:59:45.265185 ==
5444 00:59:45.265613
5445 00:59:45.265960
5446 00:59:45.266990 TX Vref Scan disable
5447 00:59:45.270559 == TX Byte 0 ==
5448 00:59:45.273984 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5449 00:59:45.277114 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5450 00:59:45.280435 == TX Byte 1 ==
5451 00:59:45.284096 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5452 00:59:45.287436 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5453 00:59:45.288096 ==
5454 00:59:45.290793 Dram Type= 6, Freq= 0, CH_1, rank 0
5455 00:59:45.293875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5456 00:59:45.294338 ==
5457 00:59:45.298590
5458 00:59:45.299142
5459 00:59:45.299502 TX Vref Scan disable
5460 00:59:45.300557 == TX Byte 0 ==
5461 00:59:45.304406 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5462 00:59:45.311518 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5463 00:59:45.312078 == TX Byte 1 ==
5464 00:59:45.314008 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5465 00:59:45.320492 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5466 00:59:45.321081
5467 00:59:45.321450 [DATLAT]
5468 00:59:45.322013 Freq=933, CH1 RK0
5469 00:59:45.322379
5470 00:59:45.323857 DATLAT Default: 0xd
5471 00:59:45.324322 0, 0xFFFF, sum = 0
5472 00:59:45.327227 1, 0xFFFF, sum = 0
5473 00:59:45.327691 2, 0xFFFF, sum = 0
5474 00:59:45.330449 3, 0xFFFF, sum = 0
5475 00:59:45.334432 4, 0xFFFF, sum = 0
5476 00:59:45.334994 5, 0xFFFF, sum = 0
5477 00:59:45.337340 6, 0xFFFF, sum = 0
5478 00:59:45.337800 7, 0xFFFF, sum = 0
5479 00:59:45.341664 8, 0xFFFF, sum = 0
5480 00:59:45.342219 9, 0xFFFF, sum = 0
5481 00:59:45.344238 10, 0x0, sum = 1
5482 00:59:45.344837 11, 0x0, sum = 2
5483 00:59:45.347041 12, 0x0, sum = 3
5484 00:59:45.347606 13, 0x0, sum = 4
5485 00:59:45.347977 best_step = 11
5486 00:59:45.348310
5487 00:59:45.352157 ==
5488 00:59:45.353365 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 00:59:45.358032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5490 00:59:45.358595 ==
5491 00:59:45.358960 RX Vref Scan: 1
5492 00:59:45.359298
5493 00:59:45.361095 RX Vref 0 -> 0, step: 1
5494 00:59:45.361550
5495 00:59:45.364078 RX Delay -69 -> 252, step: 4
5496 00:59:45.364535
5497 00:59:45.366803 Set Vref, RX VrefLevel [Byte0]: 57
5498 00:59:45.369967 [Byte1]: 48
5499 00:59:45.370456
5500 00:59:45.373682 Final RX Vref Byte 0 = 57 to rank0
5501 00:59:45.376570 Final RX Vref Byte 1 = 48 to rank0
5502 00:59:45.380323 Final RX Vref Byte 0 = 57 to rank1
5503 00:59:45.384287 Final RX Vref Byte 1 = 48 to rank1==
5504 00:59:45.386589 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 00:59:45.389763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5506 00:59:45.393166 ==
5507 00:59:45.393622 DQS Delay:
5508 00:59:45.393983 DQS0 = 0, DQS1 = 0
5509 00:59:45.397243 DQM Delay:
5510 00:59:45.397695 DQM0 = 93, DQM1 = 88
5511 00:59:45.400240 DQ Delay:
5512 00:59:45.403581 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5513 00:59:45.407529 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5514 00:59:45.408081 DQ8 =70, DQ9 =78, DQ10 =90, DQ11 =80
5515 00:59:45.413604 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =98
5516 00:59:45.414145
5517 00:59:45.414505
5518 00:59:45.420447 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5519 00:59:45.423677 CH1 RK0: MR19=505, MR18=3333
5520 00:59:45.429969 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5521 00:59:45.430536
5522 00:59:45.433303 ----->DramcWriteLeveling(PI) begin...
5523 00:59:45.433766 ==
5524 00:59:45.436466 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 00:59:45.439849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 00:59:45.440400 ==
5527 00:59:45.443551 Write leveling (Byte 0): 24 => 24
5528 00:59:45.446383 Write leveling (Byte 1): 26 => 26
5529 00:59:45.449892 DramcWriteLeveling(PI) end<-----
5530 00:59:45.450448
5531 00:59:45.450810 ==
5532 00:59:45.453132 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 00:59:45.456532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 00:59:45.457132 ==
5535 00:59:45.459890 [Gating] SW mode calibration
5536 00:59:45.466936 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 00:59:45.473276 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5538 00:59:45.475810 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 00:59:45.482584 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 00:59:45.486660 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 00:59:45.489139 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 00:59:45.496827 0 10 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
5543 00:59:45.500206 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5544 00:59:45.502499 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 00:59:45.509388 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 00:59:45.512506 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 00:59:45.516005 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 00:59:45.522173 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 00:59:45.525502 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5550 00:59:45.529988 0 11 16 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
5551 00:59:45.535311 0 11 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5552 00:59:45.538703 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 00:59:45.542572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 00:59:45.548860 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 00:59:45.553487 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 00:59:45.556242 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 00:59:45.562465 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 00:59:45.565030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 00:59:45.569359 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5560 00:59:45.574931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 00:59:45.579832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 00:59:45.581614 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 00:59:45.588157 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 00:59:45.591825 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 00:59:45.595125 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 00:59:45.598459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 00:59:45.604949 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 00:59:45.608375 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 00:59:45.612598 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 00:59:45.618710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 00:59:45.621923 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 00:59:45.625061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 00:59:45.631169 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5574 00:59:45.634713 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5575 00:59:45.637824 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5576 00:59:45.642093 Total UI for P1: 0, mck2ui 16
5577 00:59:45.644738 best dqsien dly found for B0: ( 0, 14, 14)
5578 00:59:45.651776 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 00:59:45.655046 Total UI for P1: 0, mck2ui 16
5580 00:59:45.657923 best dqsien dly found for B1: ( 0, 14, 18)
5581 00:59:45.661368 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5582 00:59:45.664765 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5583 00:59:45.665226
5584 00:59:45.667856 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5585 00:59:45.671005 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5586 00:59:45.675546 [Gating] SW calibration Done
5587 00:59:45.676105 ==
5588 00:59:45.677598 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 00:59:45.682170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5590 00:59:45.682728 ==
5591 00:59:45.685170 RX Vref Scan: 0
5592 00:59:45.685626
5593 00:59:45.687356 RX Vref 0 -> 0, step: 1
5594 00:59:45.687811
5595 00:59:45.688171 RX Delay -80 -> 252, step: 8
5596 00:59:45.694102 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5597 00:59:45.699296 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5598 00:59:45.701136 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5599 00:59:45.704426 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5600 00:59:45.707827 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5601 00:59:45.711420 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5602 00:59:45.717520 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5603 00:59:45.720694 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5604 00:59:45.724939 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5605 00:59:45.727447 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5606 00:59:45.731110 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5607 00:59:45.737569 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5608 00:59:45.740849 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5609 00:59:45.744227 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5610 00:59:45.746847 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5611 00:59:45.750563 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5612 00:59:45.751137 ==
5613 00:59:45.754334 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 00:59:45.761780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5615 00:59:45.762394 ==
5616 00:59:45.762789 DQS Delay:
5617 00:59:45.763973 DQS0 = 0, DQS1 = 0
5618 00:59:45.764427 DQM Delay:
5619 00:59:45.764832 DQM0 = 96, DQM1 = 86
5620 00:59:45.767352 DQ Delay:
5621 00:59:45.770202 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5622 00:59:45.773747 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5623 00:59:45.777096 DQ8 =71, DQ9 =75, DQ10 =83, DQ11 =75
5624 00:59:45.780408 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5625 00:59:45.781019
5626 00:59:45.781386
5627 00:59:45.781722 ==
5628 00:59:45.783245 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 00:59:45.787499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5630 00:59:45.788059 ==
5631 00:59:45.788422
5632 00:59:45.788815
5633 00:59:45.790201 TX Vref Scan disable
5634 00:59:45.793714 == TX Byte 0 ==
5635 00:59:45.796918 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5636 00:59:45.800128 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5637 00:59:45.803807 == TX Byte 1 ==
5638 00:59:45.806872 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5639 00:59:45.810591 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5640 00:59:45.811153 ==
5641 00:59:45.813285 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 00:59:45.816670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 00:59:45.819846 ==
5644 00:59:45.820400
5645 00:59:45.820853
5646 00:59:45.821256 TX Vref Scan disable
5647 00:59:45.823968 == TX Byte 0 ==
5648 00:59:45.827708 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5649 00:59:45.833813 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5650 00:59:45.834377 == TX Byte 1 ==
5651 00:59:45.836971 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5652 00:59:45.843860 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5653 00:59:45.844425
5654 00:59:45.844830 [DATLAT]
5655 00:59:45.845176 Freq=933, CH1 RK1
5656 00:59:45.845495
5657 00:59:45.847159 DATLAT Default: 0xb
5658 00:59:45.847613 0, 0xFFFF, sum = 0
5659 00:59:45.850783 1, 0xFFFF, sum = 0
5660 00:59:45.851353 2, 0xFFFF, sum = 0
5661 00:59:45.853552 3, 0xFFFF, sum = 0
5662 00:59:45.857287 4, 0xFFFF, sum = 0
5663 00:59:45.857863 5, 0xFFFF, sum = 0
5664 00:59:45.860017 6, 0xFFFF, sum = 0
5665 00:59:45.860481 7, 0xFFFF, sum = 0
5666 00:59:45.863167 8, 0xFFFF, sum = 0
5667 00:59:45.863631 9, 0xFFFF, sum = 0
5668 00:59:45.867377 10, 0x0, sum = 1
5669 00:59:45.867944 11, 0x0, sum = 2
5670 00:59:45.868315 12, 0x0, sum = 3
5671 00:59:45.870186 13, 0x0, sum = 4
5672 00:59:45.870696 best_step = 11
5673 00:59:45.871060
5674 00:59:45.871393 ==
5675 00:59:45.873221 Dram Type= 6, Freq= 0, CH_1, rank 1
5676 00:59:45.880346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5677 00:59:45.880959 ==
5678 00:59:45.881332 RX Vref Scan: 0
5679 00:59:45.881669
5680 00:59:45.883239 RX Vref 0 -> 0, step: 1
5681 00:59:45.883694
5682 00:59:45.886594 RX Delay -77 -> 252, step: 4
5683 00:59:45.889733 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5684 00:59:45.896824 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5685 00:59:45.899839 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5686 00:59:45.903223 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5687 00:59:45.906902 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5688 00:59:45.909836 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5689 00:59:45.913427 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5690 00:59:45.920409 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5691 00:59:45.924328 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5692 00:59:45.926772 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5693 00:59:45.930128 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5694 00:59:45.933925 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5695 00:59:45.939986 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5696 00:59:45.943132 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5697 00:59:45.946274 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5698 00:59:45.949968 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5699 00:59:45.950519 ==
5700 00:59:45.953373 Dram Type= 6, Freq= 0, CH_1, rank 1
5701 00:59:45.956673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5702 00:59:45.959751 ==
5703 00:59:45.960309 DQS Delay:
5704 00:59:45.960675 DQS0 = 0, DQS1 = 0
5705 00:59:45.963057 DQM Delay:
5706 00:59:45.963611 DQM0 = 96, DQM1 = 87
5707 00:59:45.966671 DQ Delay:
5708 00:59:45.969492 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5709 00:59:45.973117 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =96
5710 00:59:45.975996 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5711 00:59:45.979335 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5712 00:59:45.979799
5713 00:59:45.980165
5714 00:59:45.986092 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5715 00:59:45.990318 CH1 RK1: MR19=505, MR18=2525
5716 00:59:45.996380 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5717 00:59:45.999101 [RxdqsGatingPostProcess] freq 933
5718 00:59:46.002348 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5719 00:59:46.005586 Pre-setting of DQS Precalculation
5720 00:59:46.012645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5721 00:59:46.018759 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5722 00:59:46.025722 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5723 00:59:46.026283
5724 00:59:46.026719
5725 00:59:46.029191 [Calibration Summary] 1866 Mbps
5726 00:59:46.029647 CH 0, Rank 0
5727 00:59:46.032345 SW Impedance : PASS
5728 00:59:46.036021 DUTY Scan : NO K
5729 00:59:46.036579 ZQ Calibration : PASS
5730 00:59:46.039666 Jitter Meter : NO K
5731 00:59:46.042027 CBT Training : PASS
5732 00:59:46.042586 Write leveling : PASS
5733 00:59:46.045325 RX DQS gating : PASS
5734 00:59:46.048328 RX DQ/DQS(RDDQC) : PASS
5735 00:59:46.048820 TX DQ/DQS : PASS
5736 00:59:46.052466 RX DATLAT : PASS
5737 00:59:46.055901 RX DQ/DQS(Engine): PASS
5738 00:59:46.056458 TX OE : NO K
5739 00:59:46.059207 All Pass.
5740 00:59:46.059763
5741 00:59:46.060121 CH 0, Rank 1
5742 00:59:46.061888 SW Impedance : PASS
5743 00:59:46.062451 DUTY Scan : NO K
5744 00:59:46.065207 ZQ Calibration : PASS
5745 00:59:46.068875 Jitter Meter : NO K
5746 00:59:46.069432 CBT Training : PASS
5747 00:59:46.071697 Write leveling : PASS
5748 00:59:46.074826 RX DQS gating : PASS
5749 00:59:46.075282 RX DQ/DQS(RDDQC) : PASS
5750 00:59:46.078514 TX DQ/DQS : PASS
5751 00:59:46.078975 RX DATLAT : PASS
5752 00:59:46.082002 RX DQ/DQS(Engine): PASS
5753 00:59:46.085698 TX OE : NO K
5754 00:59:46.086157 All Pass.
5755 00:59:46.086519
5756 00:59:46.086852 CH 1, Rank 0
5757 00:59:46.088223 SW Impedance : PASS
5758 00:59:46.091808 DUTY Scan : NO K
5759 00:59:46.092407 ZQ Calibration : PASS
5760 00:59:46.095823 Jitter Meter : NO K
5761 00:59:46.098500 CBT Training : PASS
5762 00:59:46.099233 Write leveling : PASS
5763 00:59:46.102086 RX DQS gating : PASS
5764 00:59:46.104738 RX DQ/DQS(RDDQC) : PASS
5765 00:59:46.105198 TX DQ/DQS : PASS
5766 00:59:46.108230 RX DATLAT : PASS
5767 00:59:46.111610 RX DQ/DQS(Engine): PASS
5768 00:59:46.112168 TX OE : NO K
5769 00:59:46.115383 All Pass.
5770 00:59:46.115941
5771 00:59:46.116300 CH 1, Rank 1
5772 00:59:46.118313 SW Impedance : PASS
5773 00:59:46.118880 DUTY Scan : NO K
5774 00:59:46.121826 ZQ Calibration : PASS
5775 00:59:46.124594 Jitter Meter : NO K
5776 00:59:46.125076 CBT Training : PASS
5777 00:59:46.128770 Write leveling : PASS
5778 00:59:46.132276 RX DQS gating : PASS
5779 00:59:46.132873 RX DQ/DQS(RDDQC) : PASS
5780 00:59:46.134685 TX DQ/DQS : PASS
5781 00:59:46.135244 RX DATLAT : PASS
5782 00:59:46.138288 RX DQ/DQS(Engine): PASS
5783 00:59:46.141987 TX OE : NO K
5784 00:59:46.142543 All Pass.
5785 00:59:46.142904
5786 00:59:46.145186 DramC Write-DBI off
5787 00:59:46.145642 PER_BANK_REFRESH: Hybrid Mode
5788 00:59:46.149457 TX_TRACKING: ON
5789 00:59:46.158238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5790 00:59:46.161078 [FAST_K] Save calibration result to emmc
5791 00:59:46.165077 dramc_set_vcore_voltage set vcore to 650000
5792 00:59:46.165631 Read voltage for 400, 6
5793 00:59:46.168696 Vio18 = 0
5794 00:59:46.169298 Vcore = 650000
5795 00:59:46.169660 Vdram = 0
5796 00:59:46.171652 Vddq = 0
5797 00:59:46.172203 Vmddr = 0
5798 00:59:46.178258 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5799 00:59:46.181277 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5800 00:59:46.184547 MEM_TYPE=3, freq_sel=20
5801 00:59:46.188241 sv_algorithm_assistance_LP4_800
5802 00:59:46.191102 ============ PULL DRAM RESETB DOWN ============
5803 00:59:46.194792 ========== PULL DRAM RESETB DOWN end =========
5804 00:59:46.202115 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5805 00:59:46.204938 ===================================
5806 00:59:46.205505 LPDDR4 DRAM CONFIGURATION
5807 00:59:46.207927 ===================================
5808 00:59:46.211811 EX_ROW_EN[0] = 0x0
5809 00:59:46.212376 EX_ROW_EN[1] = 0x0
5810 00:59:46.214979 LP4Y_EN = 0x0
5811 00:59:46.217997 WORK_FSP = 0x0
5812 00:59:46.218562 WL = 0x2
5813 00:59:46.221129 RL = 0x2
5814 00:59:46.221696 BL = 0x2
5815 00:59:46.223901 RPST = 0x0
5816 00:59:46.224357 RD_PRE = 0x0
5817 00:59:46.228007 WR_PRE = 0x1
5818 00:59:46.228572 WR_PST = 0x0
5819 00:59:46.231039 DBI_WR = 0x0
5820 00:59:46.231642 DBI_RD = 0x0
5821 00:59:46.234128 OTF = 0x1
5822 00:59:46.237749 ===================================
5823 00:59:46.240769 ===================================
5824 00:59:46.241330 ANA top config
5825 00:59:46.244300 ===================================
5826 00:59:46.247227 DLL_ASYNC_EN = 0
5827 00:59:46.251365 ALL_SLAVE_EN = 1
5828 00:59:46.254753 NEW_RANK_MODE = 1
5829 00:59:46.255339 DLL_IDLE_MODE = 1
5830 00:59:46.257545 LP45_APHY_COMB_EN = 1
5831 00:59:46.260510 TX_ODT_DIS = 1
5832 00:59:46.264051 NEW_8X_MODE = 1
5833 00:59:46.267238 ===================================
5834 00:59:46.270989 ===================================
5835 00:59:46.271570 data_rate = 800
5836 00:59:46.273781 CKR = 1
5837 00:59:46.277489 DQ_P2S_RATIO = 4
5838 00:59:46.280408 ===================================
5839 00:59:46.284632 CA_P2S_RATIO = 4
5840 00:59:46.287499 DQ_CA_OPEN = 0
5841 00:59:46.290435 DQ_SEMI_OPEN = 1
5842 00:59:46.290910 CA_SEMI_OPEN = 1
5843 00:59:46.294260 CA_FULL_RATE = 0
5844 00:59:46.296868 DQ_CKDIV4_EN = 0
5845 00:59:46.300302 CA_CKDIV4_EN = 1
5846 00:59:46.303987 CA_PREDIV_EN = 0
5847 00:59:46.307252 PH8_DLY = 0
5848 00:59:46.307834 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5849 00:59:46.310434 DQ_AAMCK_DIV = 0
5850 00:59:46.314076 CA_AAMCK_DIV = 0
5851 00:59:46.317533 CA_ADMCK_DIV = 4
5852 00:59:46.320636 DQ_TRACK_CA_EN = 0
5853 00:59:46.323582 CA_PICK = 800
5854 00:59:46.326936 CA_MCKIO = 400
5855 00:59:46.327519 MCKIO_SEMI = 400
5856 00:59:46.330084 PLL_FREQ = 3016
5857 00:59:46.333670 DQ_UI_PI_RATIO = 32
5858 00:59:46.337332 CA_UI_PI_RATIO = 32
5859 00:59:46.340407 ===================================
5860 00:59:46.343873 ===================================
5861 00:59:46.346942 memory_type:LPDDR4
5862 00:59:46.347502 GP_NUM : 10
5863 00:59:46.350144 SRAM_EN : 1
5864 00:59:46.353718 MD32_EN : 0
5865 00:59:46.357000 ===================================
5866 00:59:46.357564 [ANA_INIT] >>>>>>>>>>>>>>
5867 00:59:46.360571 <<<<<< [CONFIGURE PHASE]: ANA_TX
5868 00:59:46.364825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5869 00:59:46.368458 ===================================
5870 00:59:46.370400 data_rate = 800,PCW = 0X7400
5871 00:59:46.373742 ===================================
5872 00:59:46.376614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5873 00:59:46.383563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5874 00:59:46.393720 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5875 00:59:46.400086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5876 00:59:46.403091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5877 00:59:46.406813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5878 00:59:46.407275 [ANA_INIT] flow start
5879 00:59:46.410413 [ANA_INIT] PLL >>>>>>>>
5880 00:59:46.412928 [ANA_INIT] PLL <<<<<<<<
5881 00:59:46.413387 [ANA_INIT] MIDPI >>>>>>>>
5882 00:59:46.416639 [ANA_INIT] MIDPI <<<<<<<<
5883 00:59:46.419772 [ANA_INIT] DLL >>>>>>>>
5884 00:59:46.420338 [ANA_INIT] flow end
5885 00:59:46.426955 ============ LP4 DIFF to SE enter ============
5886 00:59:46.429689 ============ LP4 DIFF to SE exit ============
5887 00:59:46.433557 [ANA_INIT] <<<<<<<<<<<<<
5888 00:59:46.436955 [Flow] Enable top DCM control >>>>>
5889 00:59:46.439948 [Flow] Enable top DCM control <<<<<
5890 00:59:46.440502 Enable DLL master slave shuffle
5891 00:59:46.446966 ==============================================================
5892 00:59:46.449615 Gating Mode config
5893 00:59:46.453097 ==============================================================
5894 00:59:46.455848 Config description:
5895 00:59:46.466426 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5896 00:59:46.473302 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5897 00:59:46.476411 SELPH_MODE 0: By rank 1: By Phase
5898 00:59:46.482760 ==============================================================
5899 00:59:46.486260 GAT_TRACK_EN = 0
5900 00:59:46.488900 RX_GATING_MODE = 2
5901 00:59:46.492689 RX_GATING_TRACK_MODE = 2
5902 00:59:46.495917 SELPH_MODE = 1
5903 00:59:46.496470 PICG_EARLY_EN = 1
5904 00:59:46.499491 VALID_LAT_VALUE = 1
5905 00:59:46.505588 ==============================================================
5906 00:59:46.509239 Enter into Gating configuration >>>>
5907 00:59:46.512537 Exit from Gating configuration <<<<
5908 00:59:46.515520 Enter into DVFS_PRE_config >>>>>
5909 00:59:46.525249 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5910 00:59:46.528442 Exit from DVFS_PRE_config <<<<<
5911 00:59:46.531969 Enter into PICG configuration >>>>
5912 00:59:46.535316 Exit from PICG configuration <<<<
5913 00:59:46.538275 [RX_INPUT] configuration >>>>>
5914 00:59:46.541439 [RX_INPUT] configuration <<<<<
5915 00:59:46.548368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5916 00:59:46.552341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5917 00:59:46.558880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5918 00:59:46.565047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5919 00:59:46.571788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5920 00:59:46.578378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5921 00:59:46.582175 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5922 00:59:46.585240 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5923 00:59:46.587780 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5924 00:59:46.594755 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5925 00:59:46.598059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5926 00:59:46.601047 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5927 00:59:46.604887 ===================================
5928 00:59:46.608537 LPDDR4 DRAM CONFIGURATION
5929 00:59:46.611319 ===================================
5930 00:59:46.614480 EX_ROW_EN[0] = 0x0
5931 00:59:46.615112 EX_ROW_EN[1] = 0x0
5932 00:59:46.617419 LP4Y_EN = 0x0
5933 00:59:46.617879 WORK_FSP = 0x0
5934 00:59:46.621103 WL = 0x2
5935 00:59:46.621657 RL = 0x2
5936 00:59:46.624528 BL = 0x2
5937 00:59:46.625123 RPST = 0x0
5938 00:59:46.628148 RD_PRE = 0x0
5939 00:59:46.628745 WR_PRE = 0x1
5940 00:59:46.631285 WR_PST = 0x0
5941 00:59:46.631842 DBI_WR = 0x0
5942 00:59:46.634227 DBI_RD = 0x0
5943 00:59:46.634687 OTF = 0x1
5944 00:59:46.637773 ===================================
5945 00:59:46.640963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5946 00:59:46.648429 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5947 00:59:46.651747 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5948 00:59:46.653862 ===================================
5949 00:59:46.657685 LPDDR4 DRAM CONFIGURATION
5950 00:59:46.661010 ===================================
5951 00:59:46.664622 EX_ROW_EN[0] = 0x10
5952 00:59:46.665120 EX_ROW_EN[1] = 0x0
5953 00:59:46.667319 LP4Y_EN = 0x0
5954 00:59:46.667776 WORK_FSP = 0x0
5955 00:59:46.671308 WL = 0x2
5956 00:59:46.671927 RL = 0x2
5957 00:59:46.673890 BL = 0x2
5958 00:59:46.674448 RPST = 0x0
5959 00:59:46.677203 RD_PRE = 0x0
5960 00:59:46.677809 WR_PRE = 0x1
5961 00:59:46.680244 WR_PST = 0x0
5962 00:59:46.680700 DBI_WR = 0x0
5963 00:59:46.684060 DBI_RD = 0x0
5964 00:59:46.684612 OTF = 0x1
5965 00:59:46.686961 ===================================
5966 00:59:46.693819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5967 00:59:46.698792 nWR fixed to 30
5968 00:59:46.702117 [ModeRegInit_LP4] CH0 RK0
5969 00:59:46.702679 [ModeRegInit_LP4] CH0 RK1
5970 00:59:46.705248 [ModeRegInit_LP4] CH1 RK0
5971 00:59:46.708286 [ModeRegInit_LP4] CH1 RK1
5972 00:59:46.708891 match AC timing 18
5973 00:59:46.715011 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5974 00:59:46.718148 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5975 00:59:46.721435 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5976 00:59:46.727864 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5977 00:59:46.731770 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5978 00:59:46.732328 ==
5979 00:59:46.734395 Dram Type= 6, Freq= 0, CH_0, rank 0
5980 00:59:46.738087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5981 00:59:46.738556 ==
5982 00:59:46.744875 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5983 00:59:46.751587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5984 00:59:46.754310 [CA 0] Center 36 (8~64) winsize 57
5985 00:59:46.758024 [CA 1] Center 36 (8~64) winsize 57
5986 00:59:46.760883 [CA 2] Center 36 (8~64) winsize 57
5987 00:59:46.764643 [CA 3] Center 36 (8~64) winsize 57
5988 00:59:46.767706 [CA 4] Center 36 (8~64) winsize 57
5989 00:59:46.768216 [CA 5] Center 36 (8~64) winsize 57
5990 00:59:46.770841
5991 00:59:46.774740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5992 00:59:46.775300
5993 00:59:46.778628 [CATrainingPosCal] consider 1 rank data
5994 00:59:46.781396 u2DelayCellTimex100 = 270/100 ps
5995 00:59:46.784018 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 00:59:46.787676 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 00:59:46.791037 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 00:59:46.794345 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 00:59:46.797584 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 00:59:46.801111 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 00:59:46.801570
6002 00:59:46.803813 CA PerBit enable=1, Macro0, CA PI delay=36
6003 00:59:46.804272
6004 00:59:46.807351 [CBTSetCACLKResult] CA Dly = 36
6005 00:59:46.811651 CS Dly: 1 (0~32)
6006 00:59:46.812199 ==
6007 00:59:46.814980 Dram Type= 6, Freq= 0, CH_0, rank 1
6008 00:59:46.817499 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6009 00:59:46.817961 ==
6010 00:59:46.824359 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6011 00:59:46.830678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6012 00:59:46.831224 [CA 0] Center 36 (8~64) winsize 57
6013 00:59:46.833838 [CA 1] Center 36 (8~64) winsize 57
6014 00:59:46.837776 [CA 2] Center 36 (8~64) winsize 57
6015 00:59:46.840758 [CA 3] Center 36 (8~64) winsize 57
6016 00:59:46.843708 [CA 4] Center 36 (8~64) winsize 57
6017 00:59:46.847973 [CA 5] Center 36 (8~64) winsize 57
6018 00:59:46.848531
6019 00:59:46.850755 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6020 00:59:46.851209
6021 00:59:46.853979 [CATrainingPosCal] consider 2 rank data
6022 00:59:46.857156 u2DelayCellTimex100 = 270/100 ps
6023 00:59:46.860271 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 00:59:46.867196 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 00:59:46.871412 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 00:59:46.873306 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 00:59:46.877089 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 00:59:46.880087 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 00:59:46.880546
6030 00:59:46.883957 CA PerBit enable=1, Macro0, CA PI delay=36
6031 00:59:46.884412
6032 00:59:46.887123 [CBTSetCACLKResult] CA Dly = 36
6033 00:59:46.890239 CS Dly: 1 (0~32)
6034 00:59:46.890796
6035 00:59:46.893452 ----->DramcWriteLeveling(PI) begin...
6036 00:59:46.893922 ==
6037 00:59:46.896667 Dram Type= 6, Freq= 0, CH_0, rank 0
6038 00:59:46.900455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6039 00:59:46.901085 ==
6040 00:59:46.903694 Write leveling (Byte 0): 32 => 0
6041 00:59:46.906704 Write leveling (Byte 1): 32 => 0
6042 00:59:46.910359 DramcWriteLeveling(PI) end<-----
6043 00:59:46.910920
6044 00:59:46.911285 ==
6045 00:59:46.913010 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 00:59:46.916783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 00:59:46.917265 ==
6048 00:59:46.920164 [Gating] SW mode calibration
6049 00:59:46.926353 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6050 00:59:46.933489 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6051 00:59:46.936349 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6052 00:59:46.940010 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6053 00:59:46.946894 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6054 00:59:46.949793 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6055 00:59:46.953550 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6056 00:59:46.959933 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6057 00:59:46.963419 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6058 00:59:46.966340 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6059 00:59:46.973110 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6060 00:59:46.973679 Total UI for P1: 0, mck2ui 16
6061 00:59:46.979836 best dqsien dly found for B0: ( 0, 10, 16)
6062 00:59:46.980391 Total UI for P1: 0, mck2ui 16
6063 00:59:46.982889 best dqsien dly found for B1: ( 0, 10, 24)
6064 00:59:46.989970 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6065 00:59:46.992945 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6066 00:59:46.993405
6067 00:59:46.995872 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6068 00:59:46.999828 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6069 00:59:47.002871 [Gating] SW calibration Done
6070 00:59:47.003428 ==
6071 00:59:47.006301 Dram Type= 6, Freq= 0, CH_0, rank 0
6072 00:59:47.009059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6073 00:59:47.009522 ==
6074 00:59:47.012853 RX Vref Scan: 0
6075 00:59:47.013408
6076 00:59:47.013774 RX Vref 0 -> 0, step: 1
6077 00:59:47.014118
6078 00:59:47.015694 RX Delay -410 -> 252, step: 16
6079 00:59:47.022510 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6080 00:59:47.025938 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6081 00:59:47.028930 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6082 00:59:47.032508 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6083 00:59:47.038989 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6084 00:59:47.043260 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6085 00:59:47.046321 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6086 00:59:47.048905 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6087 00:59:47.056529 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6088 00:59:47.059137 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6089 00:59:47.061947 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6090 00:59:47.065348 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6091 00:59:47.072260 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6092 00:59:47.075375 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6093 00:59:47.079718 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6094 00:59:47.085435 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6095 00:59:47.085987 ==
6096 00:59:47.088934 Dram Type= 6, Freq= 0, CH_0, rank 0
6097 00:59:47.092164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6098 00:59:47.092627 ==
6099 00:59:47.093032 DQS Delay:
6100 00:59:47.095396 DQS0 = 43, DQS1 = 59
6101 00:59:47.095961 DQM Delay:
6102 00:59:47.099004 DQM0 = 5, DQM1 = 14
6103 00:59:47.099572 DQ Delay:
6104 00:59:47.102099 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6105 00:59:47.105483 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6106 00:59:47.108343 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6107 00:59:47.112578 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6108 00:59:47.113188
6109 00:59:47.113551
6110 00:59:47.113889 ==
6111 00:59:47.115118 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 00:59:47.118106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 00:59:47.118620 ==
6114 00:59:47.118999
6115 00:59:47.119345
6116 00:59:47.121587 TX Vref Scan disable
6117 00:59:47.122150 == TX Byte 0 ==
6118 00:59:47.128702 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6119 00:59:47.132153 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6120 00:59:47.132762 == TX Byte 1 ==
6121 00:59:47.138166 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6122 00:59:47.142096 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6123 00:59:47.142662 ==
6124 00:59:47.144843 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 00:59:47.148930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 00:59:47.149497 ==
6127 00:59:47.149883
6128 00:59:47.150419
6129 00:59:47.152859 TX Vref Scan disable
6130 00:59:47.155365 == TX Byte 0 ==
6131 00:59:47.157897 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 00:59:47.161884 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 00:59:47.165400 == TX Byte 1 ==
6134 00:59:47.169459 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 00:59:47.171113 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 00:59:47.171573
6137 00:59:47.172029 [DATLAT]
6138 00:59:47.175483 Freq=400, CH0 RK0
6139 00:59:47.176051
6140 00:59:47.177733 DATLAT Default: 0xf
6141 00:59:47.178192 0, 0xFFFF, sum = 0
6142 00:59:47.181024 1, 0xFFFF, sum = 0
6143 00:59:47.181502 2, 0xFFFF, sum = 0
6144 00:59:47.185117 3, 0xFFFF, sum = 0
6145 00:59:47.185584 4, 0xFFFF, sum = 0
6146 00:59:47.188107 5, 0xFFFF, sum = 0
6147 00:59:47.188782 6, 0xFFFF, sum = 0
6148 00:59:47.192008 7, 0xFFFF, sum = 0
6149 00:59:47.192578 8, 0xFFFF, sum = 0
6150 00:59:47.194658 9, 0xFFFF, sum = 0
6151 00:59:47.195232 10, 0xFFFF, sum = 0
6152 00:59:47.197968 11, 0xFFFF, sum = 0
6153 00:59:47.198543 12, 0x0, sum = 1
6154 00:59:47.200851 13, 0x0, sum = 2
6155 00:59:47.201319 14, 0x0, sum = 3
6156 00:59:47.204419 15, 0x0, sum = 4
6157 00:59:47.204936 best_step = 13
6158 00:59:47.205305
6159 00:59:47.205642 ==
6160 00:59:47.207489 Dram Type= 6, Freq= 0, CH_0, rank 0
6161 00:59:47.213797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6162 00:59:47.214260 ==
6163 00:59:47.214622 RX Vref Scan: 1
6164 00:59:47.214992
6165 00:59:47.217450 RX Vref 0 -> 0, step: 1
6166 00:59:47.217911
6167 00:59:47.221366 RX Delay -359 -> 252, step: 8
6168 00:59:47.221928
6169 00:59:47.223878 Set Vref, RX VrefLevel [Byte0]: 48
6170 00:59:47.227237 [Byte1]: 50
6171 00:59:47.227697
6172 00:59:47.230646 Final RX Vref Byte 0 = 48 to rank0
6173 00:59:47.233690 Final RX Vref Byte 1 = 50 to rank0
6174 00:59:47.237912 Final RX Vref Byte 0 = 48 to rank1
6175 00:59:47.241408 Final RX Vref Byte 1 = 50 to rank1==
6176 00:59:47.243593 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 00:59:47.247907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 00:59:47.250916 ==
6179 00:59:47.251378 DQS Delay:
6180 00:59:47.251740 DQS0 = 52, DQS1 = 68
6181 00:59:47.254260 DQM Delay:
6182 00:59:47.254823 DQM0 = 9, DQM1 = 17
6183 00:59:47.258108 DQ Delay:
6184 00:59:47.258673 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6185 00:59:47.260766 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6186 00:59:47.264555 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6187 00:59:47.267546 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6188 00:59:47.268117
6189 00:59:47.268489
6190 00:59:47.277297 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f9f, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6191 00:59:47.280555 CH0 RK0: MR19=C0C, MR18=9F9F
6192 00:59:47.284484 CH0_RK0: MR19=0xC0C, MR18=0x9F9F, DQSOSC=389, MR23=63, INC=390, DEC=260
6193 00:59:47.287019 ==
6194 00:59:47.290605 Dram Type= 6, Freq= 0, CH_0, rank 1
6195 00:59:47.293998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6196 00:59:47.294462 ==
6197 00:59:47.297490 [Gating] SW mode calibration
6198 00:59:47.303841 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6199 00:59:47.307665 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6200 00:59:47.313622 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6201 00:59:47.316676 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6202 00:59:47.320306 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6203 00:59:47.326773 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6204 00:59:47.330138 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6205 00:59:47.333339 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6206 00:59:47.339843 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6207 00:59:47.343934 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6208 00:59:47.346847 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6209 00:59:47.350086 Total UI for P1: 0, mck2ui 16
6210 00:59:47.353471 best dqsien dly found for B0: ( 0, 10, 16)
6211 00:59:47.356666 Total UI for P1: 0, mck2ui 16
6212 00:59:47.361186 best dqsien dly found for B1: ( 0, 10, 16)
6213 00:59:47.363327 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6214 00:59:47.366800 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6215 00:59:47.370377
6216 00:59:47.373262 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6217 00:59:47.376662 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6218 00:59:47.379815 [Gating] SW calibration Done
6219 00:59:47.380325 ==
6220 00:59:47.382743 Dram Type= 6, Freq= 0, CH_0, rank 1
6221 00:59:47.387664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6222 00:59:47.388375 ==
6223 00:59:47.389456 RX Vref Scan: 0
6224 00:59:47.389913
6225 00:59:47.390276 RX Vref 0 -> 0, step: 1
6226 00:59:47.390613
6227 00:59:47.392874 RX Delay -410 -> 252, step: 16
6228 00:59:47.396590 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6229 00:59:47.403443 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6230 00:59:47.407012 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6231 00:59:47.409911 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6232 00:59:47.412928 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6233 00:59:47.420398 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6234 00:59:47.423694 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6235 00:59:47.426283 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6236 00:59:47.429727 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6237 00:59:47.435977 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6238 00:59:47.439389 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6239 00:59:47.443092 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6240 00:59:47.446235 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6241 00:59:47.452891 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6242 00:59:47.456322 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6243 00:59:47.459247 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6244 00:59:47.459802 ==
6245 00:59:47.463000 Dram Type= 6, Freq= 0, CH_0, rank 1
6246 00:59:47.469322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6247 00:59:47.469880 ==
6248 00:59:47.470246 DQS Delay:
6249 00:59:47.472811 DQS0 = 43, DQS1 = 59
6250 00:59:47.473274 DQM Delay:
6251 00:59:47.473641 DQM0 = 7, DQM1 = 14
6252 00:59:47.476889 DQ Delay:
6253 00:59:47.479329 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6254 00:59:47.479879 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6255 00:59:47.483188 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6256 00:59:47.485734 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6257 00:59:47.486275
6258 00:59:47.486642
6259 00:59:47.489241 ==
6260 00:59:47.493252 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 00:59:47.495833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6262 00:59:47.496439 ==
6263 00:59:47.496870
6264 00:59:47.497221
6265 00:59:47.499580 TX Vref Scan disable
6266 00:59:47.500036 == TX Byte 0 ==
6267 00:59:47.502166 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6268 00:59:47.509181 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6269 00:59:47.509740 == TX Byte 1 ==
6270 00:59:47.513037 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6271 00:59:47.516524 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6272 00:59:47.519081 ==
6273 00:59:47.523643 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 00:59:47.525904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 00:59:47.526466 ==
6276 00:59:47.526834
6277 00:59:47.527174
6278 00:59:47.529081 TX Vref Scan disable
6279 00:59:47.529646 == TX Byte 0 ==
6280 00:59:47.532303 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6281 00:59:47.539631 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6282 00:59:47.540195 == TX Byte 1 ==
6283 00:59:47.542668 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6284 00:59:47.549227 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6285 00:59:47.549784
6286 00:59:47.550148 [DATLAT]
6287 00:59:47.550488 Freq=400, CH0 RK1
6288 00:59:47.550833
6289 00:59:47.552693 DATLAT Default: 0xd
6290 00:59:47.553185 0, 0xFFFF, sum = 0
6291 00:59:47.555831 1, 0xFFFF, sum = 0
6292 00:59:47.556245 2, 0xFFFF, sum = 0
6293 00:59:47.558844 3, 0xFFFF, sum = 0
6294 00:59:47.562741 4, 0xFFFF, sum = 0
6295 00:59:47.563208 5, 0xFFFF, sum = 0
6296 00:59:47.565383 6, 0xFFFF, sum = 0
6297 00:59:47.565864 7, 0xFFFF, sum = 0
6298 00:59:47.568613 8, 0xFFFF, sum = 0
6299 00:59:47.569170 9, 0xFFFF, sum = 0
6300 00:59:47.572333 10, 0xFFFF, sum = 0
6301 00:59:47.572829 11, 0xFFFF, sum = 0
6302 00:59:47.575224 12, 0x0, sum = 1
6303 00:59:47.575642 13, 0x0, sum = 2
6304 00:59:47.578801 14, 0x0, sum = 3
6305 00:59:47.579219 15, 0x0, sum = 4
6306 00:59:47.581977 best_step = 13
6307 00:59:47.582405
6308 00:59:47.582732 ==
6309 00:59:47.586136 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 00:59:47.589047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6311 00:59:47.589459 ==
6312 00:59:47.589784 RX Vref Scan: 0
6313 00:59:47.590091
6314 00:59:47.592135 RX Vref 0 -> 0, step: 1
6315 00:59:47.592647
6316 00:59:47.596206 RX Delay -359 -> 252, step: 8
6317 00:59:47.603237 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6318 00:59:47.606411 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6319 00:59:47.609242 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6320 00:59:47.613122 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6321 00:59:47.620197 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6322 00:59:47.623440 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6323 00:59:47.625790 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6324 00:59:47.629304 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6325 00:59:47.636191 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6326 00:59:47.639390 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6327 00:59:47.642641 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6328 00:59:47.646385 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6329 00:59:47.652903 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6330 00:59:47.655966 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6331 00:59:47.659630 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6332 00:59:47.666647 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6333 00:59:47.667163 ==
6334 00:59:47.669471 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 00:59:47.672944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 00:59:47.673463 ==
6337 00:59:47.673796 DQS Delay:
6338 00:59:47.676095 DQS0 = 52, DQS1 = 64
6339 00:59:47.676605 DQM Delay:
6340 00:59:47.678888 DQM0 = 10, DQM1 = 14
6341 00:59:47.679297 DQ Delay:
6342 00:59:47.682556 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6343 00:59:47.685820 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6344 00:59:47.688995 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6345 00:59:47.692690 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6346 00:59:47.693148
6347 00:59:47.693476
6348 00:59:47.699275 [DQSOSCAuto] RK1, (LSB)MR18= 0xb7b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6349 00:59:47.702894 CH0 RK1: MR19=C0C, MR18=B7B7
6350 00:59:47.709423 CH0_RK1: MR19=0xC0C, MR18=0xB7B7, DQSOSC=387, MR23=63, INC=394, DEC=262
6351 00:59:47.712281 [RxdqsGatingPostProcess] freq 400
6352 00:59:47.718769 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6353 00:59:47.719282 Pre-setting of DQS Precalculation
6354 00:59:47.726217 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6355 00:59:47.726722 ==
6356 00:59:47.729184 Dram Type= 6, Freq= 0, CH_1, rank 0
6357 00:59:47.732691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6358 00:59:47.733258 ==
6359 00:59:47.739410 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6360 00:59:47.745588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6361 00:59:47.748995 [CA 0] Center 36 (8~64) winsize 57
6362 00:59:47.752130 [CA 1] Center 36 (8~64) winsize 57
6363 00:59:47.755505 [CA 2] Center 36 (8~64) winsize 57
6364 00:59:47.758537 [CA 3] Center 36 (8~64) winsize 57
6365 00:59:47.758956 [CA 4] Center 36 (8~64) winsize 57
6366 00:59:47.762617 [CA 5] Center 36 (8~64) winsize 57
6367 00:59:47.763135
6368 00:59:47.768680 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6369 00:59:47.769171
6370 00:59:47.772300 [CATrainingPosCal] consider 1 rank data
6371 00:59:47.775098 u2DelayCellTimex100 = 270/100 ps
6372 00:59:47.778002 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 00:59:47.781654 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 00:59:47.784669 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 00:59:47.788105 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 00:59:47.792528 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 00:59:47.795009 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 00:59:47.795526
6379 00:59:47.798169 CA PerBit enable=1, Macro0, CA PI delay=36
6380 00:59:47.798699
6381 00:59:47.802193 [CBTSetCACLKResult] CA Dly = 36
6382 00:59:47.805077 CS Dly: 1 (0~32)
6383 00:59:47.805495 ==
6384 00:59:47.808775 Dram Type= 6, Freq= 0, CH_1, rank 1
6385 00:59:47.811747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6386 00:59:47.812264 ==
6387 00:59:47.818261 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6388 00:59:47.824568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6389 00:59:47.827815 [CA 0] Center 36 (8~64) winsize 57
6390 00:59:47.828374 [CA 1] Center 36 (8~64) winsize 57
6391 00:59:47.831224 [CA 2] Center 36 (8~64) winsize 57
6392 00:59:47.834686 [CA 3] Center 36 (8~64) winsize 57
6393 00:59:47.838654 [CA 4] Center 36 (8~64) winsize 57
6394 00:59:47.841095 [CA 5] Center 36 (8~64) winsize 57
6395 00:59:47.841512
6396 00:59:47.844347 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6397 00:59:47.847880
6398 00:59:47.850911 [CATrainingPosCal] consider 2 rank data
6399 00:59:47.851327 u2DelayCellTimex100 = 270/100 ps
6400 00:59:47.858240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 00:59:47.860852 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 00:59:47.863852 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 00:59:47.867055 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 00:59:47.870866 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 00:59:47.874084 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 00:59:47.874629
6407 00:59:47.877438 CA PerBit enable=1, Macro0, CA PI delay=36
6408 00:59:47.877895
6409 00:59:47.881061 [CBTSetCACLKResult] CA Dly = 36
6410 00:59:47.884408 CS Dly: 1 (0~32)
6411 00:59:47.885030
6412 00:59:47.887172 ----->DramcWriteLeveling(PI) begin...
6413 00:59:47.887636 ==
6414 00:59:47.890944 Dram Type= 6, Freq= 0, CH_1, rank 0
6415 00:59:47.894753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 00:59:47.895313 ==
6417 00:59:47.897195 Write leveling (Byte 0): 32 => 0
6418 00:59:47.900807 Write leveling (Byte 1): 32 => 0
6419 00:59:47.903726 DramcWriteLeveling(PI) end<-----
6420 00:59:47.904301
6421 00:59:47.904661 ==
6422 00:59:47.906984 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 00:59:47.910637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 00:59:47.911100 ==
6425 00:59:47.913814 [Gating] SW mode calibration
6426 00:59:47.920886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 00:59:47.928370 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6428 00:59:47.930964 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 00:59:47.933582 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 00:59:47.941116 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 00:59:47.943550 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6432 00:59:47.947059 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 00:59:47.953192 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 00:59:47.956905 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 00:59:47.960855 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6436 00:59:47.966837 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 00:59:47.967382 Total UI for P1: 0, mck2ui 16
6438 00:59:47.973476 best dqsien dly found for B0: ( 0, 10, 16)
6439 00:59:47.974042 Total UI for P1: 0, mck2ui 16
6440 00:59:47.980301 best dqsien dly found for B1: ( 0, 10, 16)
6441 00:59:47.983442 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6442 00:59:47.987132 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6443 00:59:47.987783
6444 00:59:47.990001 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6445 00:59:47.993428 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6446 00:59:47.997219 [Gating] SW calibration Done
6447 00:59:47.997674 ==
6448 00:59:48.000123 Dram Type= 6, Freq= 0, CH_1, rank 0
6449 00:59:48.003636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6450 00:59:48.004199 ==
6451 00:59:48.006727 RX Vref Scan: 0
6452 00:59:48.007183
6453 00:59:48.007546 RX Vref 0 -> 0, step: 1
6454 00:59:48.007882
6455 00:59:48.010612 RX Delay -410 -> 252, step: 16
6456 00:59:48.017023 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6457 00:59:48.020303 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6458 00:59:48.023667 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6459 00:59:48.026419 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6460 00:59:48.033156 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6461 00:59:48.036242 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6462 00:59:48.040007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6463 00:59:48.043261 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6464 00:59:48.049527 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6465 00:59:48.052895 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6466 00:59:48.056864 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6467 00:59:48.059428 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6468 00:59:48.066955 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6469 00:59:48.069735 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6470 00:59:48.073137 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6471 00:59:48.075992 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6472 00:59:48.079803 ==
6473 00:59:48.082938 Dram Type= 6, Freq= 0, CH_1, rank 0
6474 00:59:48.086912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6475 00:59:48.087414 ==
6476 00:59:48.088020 DQS Delay:
6477 00:59:48.089812 DQS0 = 43, DQS1 = 59
6478 00:59:48.090302 DQM Delay:
6479 00:59:48.093678 DQM0 = 6, DQM1 = 15
6480 00:59:48.094246 DQ Delay:
6481 00:59:48.096211 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6482 00:59:48.100097 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6483 00:59:48.103024 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6484 00:59:48.106090 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6485 00:59:48.106175
6486 00:59:48.106260
6487 00:59:48.106340 ==
6488 00:59:48.109355 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 00:59:48.112490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 00:59:48.112575 ==
6491 00:59:48.112676
6492 00:59:48.112804
6493 00:59:48.115530 TX Vref Scan disable
6494 00:59:48.115620 == TX Byte 0 ==
6495 00:59:48.123000 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6496 00:59:48.125913 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6497 00:59:48.126348 == TX Byte 1 ==
6498 00:59:48.133366 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6499 00:59:48.135845 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6500 00:59:48.136279 ==
6501 00:59:48.139096 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 00:59:48.142873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 00:59:48.143311 ==
6504 00:59:48.143753
6505 00:59:48.144168
6506 00:59:48.146425 TX Vref Scan disable
6507 00:59:48.149104 == TX Byte 0 ==
6508 00:59:48.152344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 00:59:48.155930 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 00:59:48.159264 == TX Byte 1 ==
6511 00:59:48.162954 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 00:59:48.166229 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 00:59:48.166660
6514 00:59:48.167100 [DATLAT]
6515 00:59:48.168901 Freq=400, CH1 RK0
6516 00:59:48.169337
6517 00:59:48.169775 DATLAT Default: 0xf
6518 00:59:48.172561 0, 0xFFFF, sum = 0
6519 00:59:48.176012 1, 0xFFFF, sum = 0
6520 00:59:48.176540 2, 0xFFFF, sum = 0
6521 00:59:48.179280 3, 0xFFFF, sum = 0
6522 00:59:48.179815 4, 0xFFFF, sum = 0
6523 00:59:48.182306 5, 0xFFFF, sum = 0
6524 00:59:48.182830 6, 0xFFFF, sum = 0
6525 00:59:48.185374 7, 0xFFFF, sum = 0
6526 00:59:48.185829 8, 0xFFFF, sum = 0
6527 00:59:48.188812 9, 0xFFFF, sum = 0
6528 00:59:48.189252 10, 0xFFFF, sum = 0
6529 00:59:48.192153 11, 0xFFFF, sum = 0
6530 00:59:48.192680 12, 0x0, sum = 1
6531 00:59:48.196405 13, 0x0, sum = 2
6532 00:59:48.196992 14, 0x0, sum = 3
6533 00:59:48.199420 15, 0x0, sum = 4
6534 00:59:48.199947 best_step = 13
6535 00:59:48.200397
6536 00:59:48.200940 ==
6537 00:59:48.201974 Dram Type= 6, Freq= 0, CH_1, rank 0
6538 00:59:48.205898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6539 00:59:48.208577 ==
6540 00:59:48.209071 RX Vref Scan: 1
6541 00:59:48.209520
6542 00:59:48.213265 RX Vref 0 -> 0, step: 1
6543 00:59:48.213797
6544 00:59:48.215713 RX Delay -359 -> 252, step: 8
6545 00:59:48.216147
6546 00:59:48.218607 Set Vref, RX VrefLevel [Byte0]: 57
6547 00:59:48.222491 [Byte1]: 48
6548 00:59:48.223024
6549 00:59:48.225057 Final RX Vref Byte 0 = 57 to rank0
6550 00:59:48.229289 Final RX Vref Byte 1 = 48 to rank0
6551 00:59:48.231957 Final RX Vref Byte 0 = 57 to rank1
6552 00:59:48.235282 Final RX Vref Byte 1 = 48 to rank1==
6553 00:59:48.238647 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 00:59:48.241998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 00:59:48.242458 ==
6556 00:59:48.245331 DQS Delay:
6557 00:59:48.245786 DQS0 = 48, DQS1 = 64
6558 00:59:48.249067 DQM Delay:
6559 00:59:48.249524 DQM0 = 7, DQM1 = 16
6560 00:59:48.251997 DQ Delay:
6561 00:59:48.252451 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6562 00:59:48.255370 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6563 00:59:48.258949 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6564 00:59:48.262103 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6565 00:59:48.262665
6566 00:59:48.263025
6567 00:59:48.271419 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6568 00:59:48.275715 CH1 RK0: MR19=C0C, MR18=D0D0
6569 00:59:48.278037 CH1_RK0: MR19=0xC0C, MR18=0xD0D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6570 00:59:48.281486 ==
6571 00:59:48.284676 Dram Type= 6, Freq= 0, CH_1, rank 1
6572 00:59:48.288643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6573 00:59:48.289165 ==
6574 00:59:48.291999 [Gating] SW mode calibration
6575 00:59:48.298610 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6576 00:59:48.301104 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6577 00:59:48.308325 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6578 00:59:48.311919 0 7 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
6579 00:59:48.314375 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6580 00:59:48.321186 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6581 00:59:48.324626 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6582 00:59:48.327478 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6583 00:59:48.334304 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6584 00:59:48.337873 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6585 00:59:48.341354 Total UI for P1: 0, mck2ui 16
6586 00:59:48.344398 best dqsien dly found for B0: ( 0, 10, 8)
6587 00:59:48.347405 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6588 00:59:48.351684 Total UI for P1: 0, mck2ui 16
6589 00:59:48.354347 best dqsien dly found for B1: ( 0, 10, 16)
6590 00:59:48.357314 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6591 00:59:48.361921 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6592 00:59:48.362476
6593 00:59:48.367663 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6594 00:59:48.370680 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6595 00:59:48.374713 [Gating] SW calibration Done
6596 00:59:48.375417 ==
6597 00:59:48.377365 Dram Type= 6, Freq= 0, CH_1, rank 1
6598 00:59:48.381561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6599 00:59:48.382121 ==
6600 00:59:48.382490 RX Vref Scan: 0
6601 00:59:48.382836
6602 00:59:48.384052 RX Vref 0 -> 0, step: 1
6603 00:59:48.384515
6604 00:59:48.387295 RX Delay -410 -> 252, step: 16
6605 00:59:48.391293 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6606 00:59:48.398080 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6607 00:59:48.400633 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6608 00:59:48.403843 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6609 00:59:48.407140 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6610 00:59:48.413642 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6611 00:59:48.417344 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6612 00:59:48.420272 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6613 00:59:48.424334 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6614 00:59:48.430585 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6615 00:59:48.433755 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6616 00:59:48.437238 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6617 00:59:48.440429 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6618 00:59:48.447315 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6619 00:59:48.450694 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6620 00:59:48.453630 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6621 00:59:48.454099 ==
6622 00:59:48.457785 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 00:59:48.463333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6624 00:59:48.463895 ==
6625 00:59:48.464267 DQS Delay:
6626 00:59:48.466685 DQS0 = 43, DQS1 = 59
6627 00:59:48.467147 DQM Delay:
6628 00:59:48.467517 DQM0 = 9, DQM1 = 18
6629 00:59:48.469791 DQ Delay:
6630 00:59:48.474050 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6631 00:59:48.474609 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6632 00:59:48.477202 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6633 00:59:48.481039 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6634 00:59:48.481501
6635 00:59:48.481866
6636 00:59:48.484231 ==
6637 00:59:48.486384 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 00:59:48.489542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6639 00:59:48.490045 ==
6640 00:59:48.490495
6641 00:59:48.490852
6642 00:59:48.492888 TX Vref Scan disable
6643 00:59:48.493351 == TX Byte 0 ==
6644 00:59:48.496098 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6645 00:59:48.502984 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6646 00:59:48.503559 == TX Byte 1 ==
6647 00:59:48.505936 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6648 00:59:48.513571 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6649 00:59:48.514129 ==
6650 00:59:48.515998 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 00:59:48.520396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 00:59:48.521010 ==
6653 00:59:48.521387
6654 00:59:48.521730
6655 00:59:48.523228 TX Vref Scan disable
6656 00:59:48.523694 == TX Byte 0 ==
6657 00:59:48.526108 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6658 00:59:48.533068 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6659 00:59:48.533627 == TX Byte 1 ==
6660 00:59:48.537097 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6661 00:59:48.543059 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6662 00:59:48.543621
6663 00:59:48.543987 [DATLAT]
6664 00:59:48.544329 Freq=400, CH1 RK1
6665 00:59:48.544662
6666 00:59:48.546492 DATLAT Default: 0xd
6667 00:59:48.549265 0, 0xFFFF, sum = 0
6668 00:59:48.549837 1, 0xFFFF, sum = 0
6669 00:59:48.553269 2, 0xFFFF, sum = 0
6670 00:59:48.553897 3, 0xFFFF, sum = 0
6671 00:59:48.556356 4, 0xFFFF, sum = 0
6672 00:59:48.556864 5, 0xFFFF, sum = 0
6673 00:59:48.559444 6, 0xFFFF, sum = 0
6674 00:59:48.560014 7, 0xFFFF, sum = 0
6675 00:59:48.563219 8, 0xFFFF, sum = 0
6676 00:59:48.563795 9, 0xFFFF, sum = 0
6677 00:59:48.565742 10, 0xFFFF, sum = 0
6678 00:59:48.566217 11, 0xFFFF, sum = 0
6679 00:59:48.569251 12, 0x0, sum = 1
6680 00:59:48.569817 13, 0x0, sum = 2
6681 00:59:48.572685 14, 0x0, sum = 3
6682 00:59:48.573296 15, 0x0, sum = 4
6683 00:59:48.576077 best_step = 13
6684 00:59:48.576631
6685 00:59:48.577045 ==
6686 00:59:48.578770 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 00:59:48.582131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6688 00:59:48.582693 ==
6689 00:59:48.585948 RX Vref Scan: 0
6690 00:59:48.586511
6691 00:59:48.586886 RX Vref 0 -> 0, step: 1
6692 00:59:48.587234
6693 00:59:48.589260 RX Delay -359 -> 252, step: 8
6694 00:59:48.598515 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6695 00:59:48.599916 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6696 00:59:48.603676 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6697 00:59:48.609529 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6698 00:59:48.613122 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6699 00:59:48.616755 iDelay=217, Bit 5, Center -32 (-279 ~ 216) 496
6700 00:59:48.620218 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6701 00:59:48.626889 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6702 00:59:48.629659 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6703 00:59:48.633070 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6704 00:59:48.636940 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6705 00:59:48.642868 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6706 00:59:48.646430 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6707 00:59:48.649875 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6708 00:59:48.653077 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6709 00:59:48.660069 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6710 00:59:48.660628 ==
6711 00:59:48.663042 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 00:59:48.666294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 00:59:48.666855 ==
6714 00:59:48.667224 DQS Delay:
6715 00:59:48.669695 DQS0 = 48, DQS1 = 64
6716 00:59:48.670155 DQM Delay:
6717 00:59:48.673062 DQM0 = 9, DQM1 = 15
6718 00:59:48.673623 DQ Delay:
6719 00:59:48.675902 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6720 00:59:48.678728 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6721 00:59:48.683576 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6722 00:59:48.685630 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6723 00:59:48.686094
6724 00:59:48.686455
6725 00:59:48.692229 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6726 00:59:48.695877 CH1 RK1: MR19=C0C, MR18=B5B5
6727 00:59:48.704598 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6728 00:59:48.706116 [RxdqsGatingPostProcess] freq 400
6729 00:59:48.712727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6730 00:59:48.715931 Pre-setting of DQS Precalculation
6731 00:59:48.719487 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6732 00:59:48.725631 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6733 00:59:48.733592 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6734 00:59:48.735173
6735 00:59:48.735630
6736 00:59:48.736008 [Calibration Summary] 800 Mbps
6737 00:59:48.738969 CH 0, Rank 0
6738 00:59:48.739521 SW Impedance : PASS
6739 00:59:48.742085 DUTY Scan : NO K
6740 00:59:48.745735 ZQ Calibration : PASS
6741 00:59:48.746289 Jitter Meter : NO K
6742 00:59:48.749304 CBT Training : PASS
6743 00:59:48.752325 Write leveling : PASS
6744 00:59:48.752903 RX DQS gating : PASS
6745 00:59:48.755064 RX DQ/DQS(RDDQC) : PASS
6746 00:59:48.759164 TX DQ/DQS : PASS
6747 00:59:48.759723 RX DATLAT : PASS
6748 00:59:48.761747 RX DQ/DQS(Engine): PASS
6749 00:59:48.765657 TX OE : NO K
6750 00:59:48.766222 All Pass.
6751 00:59:48.766591
6752 00:59:48.766930 CH 0, Rank 1
6753 00:59:48.768592 SW Impedance : PASS
6754 00:59:48.771889 DUTY Scan : NO K
6755 00:59:48.772446 ZQ Calibration : PASS
6756 00:59:48.775571 Jitter Meter : NO K
6757 00:59:48.776174 CBT Training : PASS
6758 00:59:48.778663 Write leveling : NO K
6759 00:59:48.782027 RX DQS gating : PASS
6760 00:59:48.782488 RX DQ/DQS(RDDQC) : PASS
6761 00:59:48.785061 TX DQ/DQS : PASS
6762 00:59:48.788916 RX DATLAT : PASS
6763 00:59:48.789642 RX DQ/DQS(Engine): PASS
6764 00:59:48.791766 TX OE : NO K
6765 00:59:48.792229 All Pass.
6766 00:59:48.792595
6767 00:59:48.794873 CH 1, Rank 0
6768 00:59:48.795347 SW Impedance : PASS
6769 00:59:48.798221 DUTY Scan : NO K
6770 00:59:48.802248 ZQ Calibration : PASS
6771 00:59:48.802804 Jitter Meter : NO K
6772 00:59:48.804824 CBT Training : PASS
6773 00:59:48.808816 Write leveling : PASS
6774 00:59:48.809366 RX DQS gating : PASS
6775 00:59:48.812148 RX DQ/DQS(RDDQC) : PASS
6776 00:59:48.815065 TX DQ/DQS : PASS
6777 00:59:48.815624 RX DATLAT : PASS
6778 00:59:48.819011 RX DQ/DQS(Engine): PASS
6779 00:59:48.821607 TX OE : NO K
6780 00:59:48.822092 All Pass.
6781 00:59:48.822459
6782 00:59:48.822800 CH 1, Rank 1
6783 00:59:48.824311 SW Impedance : PASS
6784 00:59:48.827995 DUTY Scan : NO K
6785 00:59:48.828549 ZQ Calibration : PASS
6786 00:59:48.831533 Jitter Meter : NO K
6787 00:59:48.835108 CBT Training : PASS
6788 00:59:48.835668 Write leveling : NO K
6789 00:59:48.838147 RX DQS gating : PASS
6790 00:59:48.841601 RX DQ/DQS(RDDQC) : PASS
6791 00:59:48.842159 TX DQ/DQS : PASS
6792 00:59:48.845081 RX DATLAT : PASS
6793 00:59:48.845542 RX DQ/DQS(Engine): PASS
6794 00:59:48.848553 TX OE : NO K
6795 00:59:48.849050 All Pass.
6796 00:59:48.849505
6797 00:59:48.851943 DramC Write-DBI off
6798 00:59:48.855026 PER_BANK_REFRESH: Hybrid Mode
6799 00:59:48.855489 TX_TRACKING: ON
6800 00:59:48.864924 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6801 00:59:48.867890 [FAST_K] Save calibration result to emmc
6802 00:59:48.872033 dramc_set_vcore_voltage set vcore to 725000
6803 00:59:48.874574 Read voltage for 1600, 0
6804 00:59:48.875132 Vio18 = 0
6805 00:59:48.878280 Vcore = 725000
6806 00:59:48.878837 Vdram = 0
6807 00:59:48.879205 Vddq = 0
6808 00:59:48.879545 Vmddr = 0
6809 00:59:48.884368 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6810 00:59:48.890508 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6811 00:59:48.891250 MEM_TYPE=3, freq_sel=13
6812 00:59:48.894596 sv_algorithm_assistance_LP4_3733
6813 00:59:48.897860 ============ PULL DRAM RESETB DOWN ============
6814 00:59:48.904626 ========== PULL DRAM RESETB DOWN end =========
6815 00:59:48.907384 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6816 00:59:48.911797 ===================================
6817 00:59:48.914683 LPDDR4 DRAM CONFIGURATION
6818 00:59:48.918248 ===================================
6819 00:59:48.918821 EX_ROW_EN[0] = 0x0
6820 00:59:48.921325 EX_ROW_EN[1] = 0x0
6821 00:59:48.921785 LP4Y_EN = 0x0
6822 00:59:48.924277 WORK_FSP = 0x1
6823 00:59:48.924775 WL = 0x5
6824 00:59:48.928083 RL = 0x5
6825 00:59:48.928645 BL = 0x2
6826 00:59:48.931341 RPST = 0x0
6827 00:59:48.934196 RD_PRE = 0x0
6828 00:59:48.934655 WR_PRE = 0x1
6829 00:59:48.937861 WR_PST = 0x1
6830 00:59:48.938372 DBI_WR = 0x0
6831 00:59:48.940414 DBI_RD = 0x0
6832 00:59:48.940913 OTF = 0x1
6833 00:59:48.944881 ===================================
6834 00:59:48.947802 ===================================
6835 00:59:48.951168 ANA top config
6836 00:59:48.954125 ===================================
6837 00:59:48.955017 DLL_ASYNC_EN = 0
6838 00:59:48.957050 ALL_SLAVE_EN = 0
6839 00:59:48.961266 NEW_RANK_MODE = 1
6840 00:59:48.963839 DLL_IDLE_MODE = 1
6841 00:59:48.964392 LP45_APHY_COMB_EN = 1
6842 00:59:48.967975 TX_ODT_DIS = 0
6843 00:59:48.970482 NEW_8X_MODE = 1
6844 00:59:48.974231 ===================================
6845 00:59:48.977298 ===================================
6846 00:59:48.981187 data_rate = 3200
6847 00:59:48.984649 CKR = 1
6848 00:59:48.987472 DQ_P2S_RATIO = 8
6849 00:59:48.990260 ===================================
6850 00:59:48.990914 CA_P2S_RATIO = 8
6851 00:59:48.994405 DQ_CA_OPEN = 0
6852 00:59:48.997185 DQ_SEMI_OPEN = 0
6853 00:59:49.000304 CA_SEMI_OPEN = 0
6854 00:59:49.003636 CA_FULL_RATE = 0
6855 00:59:49.006921 DQ_CKDIV4_EN = 0
6856 00:59:49.007490 CA_CKDIV4_EN = 0
6857 00:59:49.010287 CA_PREDIV_EN = 0
6858 00:59:49.014004 PH8_DLY = 12
6859 00:59:49.016815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6860 00:59:49.020248 DQ_AAMCK_DIV = 4
6861 00:59:49.023792 CA_AAMCK_DIV = 4
6862 00:59:49.024352 CA_ADMCK_DIV = 4
6863 00:59:49.026960 DQ_TRACK_CA_EN = 0
6864 00:59:49.029581 CA_PICK = 1600
6865 00:59:49.033086 CA_MCKIO = 1600
6866 00:59:49.036434 MCKIO_SEMI = 0
6867 00:59:49.039643 PLL_FREQ = 3068
6868 00:59:49.043087 DQ_UI_PI_RATIO = 32
6869 00:59:49.046928 CA_UI_PI_RATIO = 0
6870 00:59:49.051524 ===================================
6871 00:59:49.052961 ===================================
6872 00:59:49.053428 memory_type:LPDDR4
6873 00:59:49.055919 GP_NUM : 10
6874 00:59:49.059948 SRAM_EN : 1
6875 00:59:49.060514 MD32_EN : 0
6876 00:59:49.062870 ===================================
6877 00:59:49.066029 [ANA_INIT] >>>>>>>>>>>>>>
6878 00:59:49.069682 <<<<<< [CONFIGURE PHASE]: ANA_TX
6879 00:59:49.073088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6880 00:59:49.076208 ===================================
6881 00:59:49.079675 data_rate = 3200,PCW = 0X7600
6882 00:59:49.083384 ===================================
6883 00:59:49.085843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6884 00:59:49.089374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6885 00:59:49.096114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6886 00:59:49.099565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6887 00:59:49.103408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6888 00:59:49.105659 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6889 00:59:49.109349 [ANA_INIT] flow start
6890 00:59:49.111989 [ANA_INIT] PLL >>>>>>>>
6891 00:59:49.112453 [ANA_INIT] PLL <<<<<<<<
6892 00:59:49.115474 [ANA_INIT] MIDPI >>>>>>>>
6893 00:59:49.119035 [ANA_INIT] MIDPI <<<<<<<<
6894 00:59:49.123151 [ANA_INIT] DLL >>>>>>>>
6895 00:59:49.123716 [ANA_INIT] DLL <<<<<<<<
6896 00:59:49.126037 [ANA_INIT] flow end
6897 00:59:49.128758 ============ LP4 DIFF to SE enter ============
6898 00:59:49.132702 ============ LP4 DIFF to SE exit ============
6899 00:59:49.135742 [ANA_INIT] <<<<<<<<<<<<<
6900 00:59:49.139148 [Flow] Enable top DCM control >>>>>
6901 00:59:49.142743 [Flow] Enable top DCM control <<<<<
6902 00:59:49.145241 Enable DLL master slave shuffle
6903 00:59:49.152056 ==============================================================
6904 00:59:49.152617 Gating Mode config
6905 00:59:49.158430 ==============================================================
6906 00:59:49.159020 Config description:
6907 00:59:49.168888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6908 00:59:49.175229 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6909 00:59:49.181390 SELPH_MODE 0: By rank 1: By Phase
6910 00:59:49.184947 ==============================================================
6911 00:59:49.188116 GAT_TRACK_EN = 1
6912 00:59:49.191546 RX_GATING_MODE = 2
6913 00:59:49.195455 RX_GATING_TRACK_MODE = 2
6914 00:59:49.198370 SELPH_MODE = 1
6915 00:59:49.201694 PICG_EARLY_EN = 1
6916 00:59:49.205422 VALID_LAT_VALUE = 1
6917 00:59:49.212178 ==============================================================
6918 00:59:49.215370 Enter into Gating configuration >>>>
6919 00:59:49.218598 Exit from Gating configuration <<<<
6920 00:59:49.221436 Enter into DVFS_PRE_config >>>>>
6921 00:59:49.232202 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6922 00:59:49.234628 Exit from DVFS_PRE_config <<<<<
6923 00:59:49.238496 Enter into PICG configuration >>>>
6924 00:59:49.241359 Exit from PICG configuration <<<<
6925 00:59:49.245002 [RX_INPUT] configuration >>>>>
6926 00:59:49.245558 [RX_INPUT] configuration <<<<<
6927 00:59:49.251601 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6928 00:59:49.257818 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6929 00:59:49.261959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6930 00:59:49.268139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6931 00:59:49.274327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6932 00:59:49.281111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6933 00:59:49.284435 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6934 00:59:49.288333 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6935 00:59:49.294331 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6936 00:59:49.297573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6937 00:59:49.301116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6938 00:59:49.307834 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6939 00:59:49.311273 ===================================
6940 00:59:49.311834 LPDDR4 DRAM CONFIGURATION
6941 00:59:49.314153 ===================================
6942 00:59:49.317866 EX_ROW_EN[0] = 0x0
6943 00:59:49.318427 EX_ROW_EN[1] = 0x0
6944 00:59:49.320899 LP4Y_EN = 0x0
6945 00:59:49.321356 WORK_FSP = 0x1
6946 00:59:49.324328 WL = 0x5
6947 00:59:49.324962 RL = 0x5
6948 00:59:49.327591 BL = 0x2
6949 00:59:49.331281 RPST = 0x0
6950 00:59:49.331839 RD_PRE = 0x0
6951 00:59:49.333687 WR_PRE = 0x1
6952 00:59:49.334183 WR_PST = 0x1
6953 00:59:49.337353 DBI_WR = 0x0
6954 00:59:49.337911 DBI_RD = 0x0
6955 00:59:49.340650 OTF = 0x1
6956 00:59:49.345310 ===================================
6957 00:59:49.347689 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6958 00:59:49.350439 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6959 00:59:49.353672 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6960 00:59:49.357066 ===================================
6961 00:59:49.361072 LPDDR4 DRAM CONFIGURATION
6962 00:59:49.363949 ===================================
6963 00:59:49.367188 EX_ROW_EN[0] = 0x10
6964 00:59:49.367747 EX_ROW_EN[1] = 0x0
6965 00:59:49.371130 LP4Y_EN = 0x0
6966 00:59:49.371685 WORK_FSP = 0x1
6967 00:59:49.375994 WL = 0x5
6968 00:59:49.376550 RL = 0x5
6969 00:59:49.377391 BL = 0x2
6970 00:59:49.380973 RPST = 0x0
6971 00:59:49.381521 RD_PRE = 0x0
6972 00:59:49.383183 WR_PRE = 0x1
6973 00:59:49.383637 WR_PST = 0x1
6974 00:59:49.387339 DBI_WR = 0x0
6975 00:59:49.387897 DBI_RD = 0x0
6976 00:59:49.389935 OTF = 0x1
6977 00:59:49.393797 ===================================
6978 00:59:49.397018 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6979 00:59:49.400627 ==
6980 00:59:49.404013 Dram Type= 6, Freq= 0, CH_0, rank 0
6981 00:59:49.406995 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6982 00:59:49.407548 ==
6983 00:59:49.411086 [Duty_Offset_Calibration]
6984 00:59:49.411634 B0:0 B1:2 CA:1
6985 00:59:49.411998
6986 00:59:49.413191 [DutyScan_Calibration_Flow] k_type=0
6987 00:59:49.423605
6988 00:59:49.424157 ==CLK 0==
6989 00:59:49.427363 Final CLK duty delay cell = 0
6990 00:59:49.430076 [0] MAX Duty = 5187%(X100), DQS PI = 24
6991 00:59:49.433804 [0] MIN Duty = 4938%(X100), DQS PI = 54
6992 00:59:49.437237 [0] AVG Duty = 5062%(X100)
6993 00:59:49.437825
6994 00:59:49.440113 CH0 CLK Duty spec in!! Max-Min= 249%
6995 00:59:49.443283 [DutyScan_Calibration_Flow] ====Done====
6996 00:59:49.443841
6997 00:59:49.446555 [DutyScan_Calibration_Flow] k_type=1
6998 00:59:49.463195
6999 00:59:49.463745 ==DQS 0 ==
7000 00:59:49.466735 Final DQS duty delay cell = 0
7001 00:59:49.470139 [0] MAX Duty = 5156%(X100), DQS PI = 32
7002 00:59:49.473468 [0] MIN Duty = 5031%(X100), DQS PI = 8
7003 00:59:49.474022 [0] AVG Duty = 5093%(X100)
7004 00:59:49.477312
7005 00:59:49.477870 ==DQS 1 ==
7006 00:59:49.480290 Final DQS duty delay cell = 0
7007 00:59:49.483092 [0] MAX Duty = 5031%(X100), DQS PI = 2
7008 00:59:49.487147 [0] MIN Duty = 4876%(X100), DQS PI = 18
7009 00:59:49.487608 [0] AVG Duty = 4953%(X100)
7010 00:59:49.489643
7011 00:59:49.493137 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7012 00:59:49.493727
7013 00:59:49.496243 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7014 00:59:49.500939 [DutyScan_Calibration_Flow] ====Done====
7015 00:59:49.501398
7016 00:59:49.502833 [DutyScan_Calibration_Flow] k_type=3
7017 00:59:49.520889
7018 00:59:49.521440 ==DQM 0 ==
7019 00:59:49.523757 Final DQM duty delay cell = 0
7020 00:59:49.527133 [0] MAX Duty = 5187%(X100), DQS PI = 24
7021 00:59:49.530352 [0] MIN Duty = 4907%(X100), DQS PI = 42
7022 00:59:49.534200 [0] AVG Duty = 5047%(X100)
7023 00:59:49.534758
7024 00:59:49.535127 ==DQM 1 ==
7025 00:59:49.537165 Final DQM duty delay cell = 0
7026 00:59:49.540771 [0] MAX Duty = 5031%(X100), DQS PI = 4
7027 00:59:49.543732 [0] MIN Duty = 4782%(X100), DQS PI = 14
7028 00:59:49.547464 [0] AVG Duty = 4906%(X100)
7029 00:59:49.548018
7030 00:59:49.550600 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7031 00:59:49.551154
7032 00:59:49.553345 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7033 00:59:49.557504 [DutyScan_Calibration_Flow] ====Done====
7034 00:59:49.557963
7035 00:59:49.560387 [DutyScan_Calibration_Flow] k_type=2
7036 00:59:49.577067
7037 00:59:49.577621 ==DQ 0 ==
7038 00:59:49.580392 Final DQ duty delay cell = 0
7039 00:59:49.583535 [0] MAX Duty = 5218%(X100), DQS PI = 18
7040 00:59:49.587064 [0] MIN Duty = 4938%(X100), DQS PI = 56
7041 00:59:49.587586 [0] AVG Duty = 5078%(X100)
7042 00:59:49.590555
7043 00:59:49.591110 ==DQ 1 ==
7044 00:59:49.593660 Final DQ duty delay cell = -4
7045 00:59:49.597001 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7046 00:59:49.600398 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7047 00:59:49.601104 [-4] AVG Duty = 4969%(X100)
7048 00:59:49.603368
7049 00:59:49.607159 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7050 00:59:49.607716
7051 00:59:49.610437 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7052 00:59:49.613865 [DutyScan_Calibration_Flow] ====Done====
7053 00:59:49.614329 ==
7054 00:59:49.617468 Dram Type= 6, Freq= 0, CH_1, rank 0
7055 00:59:49.620078 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7056 00:59:49.620648 ==
7057 00:59:49.623285 [Duty_Offset_Calibration]
7058 00:59:49.623846 B0:0 B1:4 CA:-5
7059 00:59:49.624213
7060 00:59:49.626885 [DutyScan_Calibration_Flow] k_type=0
7061 00:59:49.637475
7062 00:59:49.638028 ==CLK 0==
7063 00:59:49.641049 Final CLK duty delay cell = 0
7064 00:59:49.644694 [0] MAX Duty = 5156%(X100), DQS PI = 20
7065 00:59:49.647694 [0] MIN Duty = 4906%(X100), DQS PI = 50
7066 00:59:49.650949 [0] AVG Duty = 5031%(X100)
7067 00:59:49.651500
7068 00:59:49.654458 CH1 CLK Duty spec in!! Max-Min= 250%
7069 00:59:49.657042 [DutyScan_Calibration_Flow] ====Done====
7070 00:59:49.657503
7071 00:59:49.660674 [DutyScan_Calibration_Flow] k_type=1
7072 00:59:49.677587
7073 00:59:49.678209 ==DQS 0 ==
7074 00:59:49.679682 Final DQS duty delay cell = 0
7075 00:59:49.683083 [0] MAX Duty = 5187%(X100), DQS PI = 20
7076 00:59:49.686056 [0] MIN Duty = 4876%(X100), DQS PI = 42
7077 00:59:49.689711 [0] AVG Duty = 5031%(X100)
7078 00:59:49.690271
7079 00:59:49.690640 ==DQS 1 ==
7080 00:59:49.692653 Final DQS duty delay cell = -4
7081 00:59:49.696368 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7082 00:59:49.699695 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7083 00:59:49.703109 [-4] AVG Duty = 4922%(X100)
7084 00:59:49.703670
7085 00:59:49.707406 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7086 00:59:49.707981
7087 00:59:49.709472 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7088 00:59:49.713131 [DutyScan_Calibration_Flow] ====Done====
7089 00:59:49.713885
7090 00:59:49.716135 [DutyScan_Calibration_Flow] k_type=3
7091 00:59:49.732226
7092 00:59:49.732824 ==DQM 0 ==
7093 00:59:49.735849 Final DQM duty delay cell = -4
7094 00:59:49.739017 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7095 00:59:49.742712 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7096 00:59:49.745658 [-4] AVG Duty = 4922%(X100)
7097 00:59:49.746139
7098 00:59:49.746506 ==DQM 1 ==
7099 00:59:49.749205 Final DQM duty delay cell = -4
7100 00:59:49.751851 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7101 00:59:49.756163 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7102 00:59:49.759048 [-4] AVG Duty = 4984%(X100)
7103 00:59:49.759607
7104 00:59:49.762057 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7105 00:59:49.762618
7106 00:59:49.765327 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7107 00:59:49.768670 [DutyScan_Calibration_Flow] ====Done====
7108 00:59:49.769280
7109 00:59:49.772298 [DutyScan_Calibration_Flow] k_type=2
7110 00:59:49.789665
7111 00:59:49.790228 ==DQ 0 ==
7112 00:59:49.792824 Final DQ duty delay cell = 0
7113 00:59:49.797241 [0] MAX Duty = 5093%(X100), DQS PI = 34
7114 00:59:49.800150 [0] MIN Duty = 4969%(X100), DQS PI = 44
7115 00:59:49.800879 [0] AVG Duty = 5031%(X100)
7116 00:59:49.801421
7117 00:59:49.802748 ==DQ 1 ==
7118 00:59:49.807310 Final DQ duty delay cell = 0
7119 00:59:49.810125 [0] MAX Duty = 5031%(X100), DQS PI = 4
7120 00:59:49.813892 [0] MIN Duty = 4876%(X100), DQS PI = 28
7121 00:59:49.814454 [0] AVG Duty = 4953%(X100)
7122 00:59:49.814827
7123 00:59:49.816036 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7124 00:59:49.816417
7125 00:59:49.824517 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7126 00:59:49.826032 [DutyScan_Calibration_Flow] ====Done====
7127 00:59:49.830151 nWR fixed to 30
7128 00:59:49.830728 [ModeRegInit_LP4] CH0 RK0
7129 00:59:49.832855 [ModeRegInit_LP4] CH0 RK1
7130 00:59:49.836203 [ModeRegInit_LP4] CH1 RK0
7131 00:59:49.836816 [ModeRegInit_LP4] CH1 RK1
7132 00:59:49.839241 match AC timing 4
7133 00:59:49.842819 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7134 00:59:49.849611 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7135 00:59:49.852347 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7136 00:59:49.859404 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7137 00:59:49.863448 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7138 00:59:49.864014 [MiockJmeterHQA]
7139 00:59:49.864383
7140 00:59:49.866468 [DramcMiockJmeter] u1RxGatingPI = 0
7141 00:59:49.869197 0 : 4363, 4137
7142 00:59:49.869763 4 : 4363, 4137
7143 00:59:49.872542 8 : 4363, 4137
7144 00:59:49.873336 12 : 4363, 4138
7145 00:59:49.873778 16 : 4366, 4140
7146 00:59:49.875944 20 : 4257, 4029
7147 00:59:49.876411 24 : 4252, 4027
7148 00:59:49.879499 28 : 4253, 4027
7149 00:59:49.880065 32 : 4363, 4137
7150 00:59:49.882167 36 : 4252, 4027
7151 00:59:49.882639 40 : 4362, 4137
7152 00:59:49.883012 44 : 4252, 4027
7153 00:59:49.885606 48 : 4252, 4027
7154 00:59:49.886092 52 : 4253, 4026
7155 00:59:49.888991 56 : 4255, 4029
7156 00:59:49.889550 60 : 4361, 4137
7157 00:59:49.891912 64 : 4250, 4027
7158 00:59:49.892377 68 : 4360, 4137
7159 00:59:49.895562 72 : 4250, 4026
7160 00:59:49.896040 76 : 4249, 4027
7161 00:59:49.899141 80 : 4250, 4026
7162 00:59:49.899612 84 : 4361, 4138
7163 00:59:49.899983 88 : 4250, 4027
7164 00:59:49.902489 92 : 4361, 4138
7165 00:59:49.902958 96 : 4250, 4027
7166 00:59:49.905716 100 : 4250, 1975
7167 00:59:49.906283 104 : 4363, 0
7168 00:59:49.908939 108 : 4250, 0
7169 00:59:49.909511 112 : 4250, 0
7170 00:59:49.909886 116 : 4363, 0
7171 00:59:49.912386 120 : 4361, 0
7172 00:59:49.913031 124 : 4250, 0
7173 00:59:49.913417 128 : 4250, 0
7174 00:59:49.916582 132 : 4249, 0
7175 00:59:49.917213 136 : 4253, 0
7176 00:59:49.918475 140 : 4250, 0
7177 00:59:49.918941 144 : 4249, 0
7178 00:59:49.919312 148 : 4252, 0
7179 00:59:49.921833 152 : 4360, 0
7180 00:59:49.922299 156 : 4361, 0
7181 00:59:49.925316 160 : 4363, 0
7182 00:59:49.925784 164 : 4250, 0
7183 00:59:49.926156 168 : 4361, 0
7184 00:59:49.928529 172 : 4249, 0
7185 00:59:49.929025 176 : 4250, 0
7186 00:59:49.931975 180 : 4250, 0
7187 00:59:49.932442 184 : 4249, 0
7188 00:59:49.932873 188 : 4252, 0
7189 00:59:49.935125 192 : 4361, 0
7190 00:59:49.935590 196 : 4249, 0
7191 00:59:49.938615 200 : 4250, 0
7192 00:59:49.939194 204 : 4252, 0
7193 00:59:49.939567 208 : 4361, 0
7194 00:59:49.941407 212 : 4360, 0
7195 00:59:49.941875 216 : 4250, 0
7196 00:59:49.945651 220 : 4250, 368
7197 00:59:49.946215 224 : 4252, 3889
7198 00:59:49.948650 228 : 4360, 4138
7199 00:59:49.949249 232 : 4250, 4027
7200 00:59:49.949626 236 : 4250, 4026
7201 00:59:49.951348 240 : 4250, 4027
7202 00:59:49.951813 244 : 4250, 4027
7203 00:59:49.955137 248 : 4249, 4027
7204 00:59:49.955714 252 : 4250, 4026
7205 00:59:49.958094 256 : 4250, 4027
7206 00:59:49.958563 260 : 4252, 4030
7207 00:59:49.961677 264 : 4250, 4027
7208 00:59:49.962252 268 : 4360, 4138
7209 00:59:49.965412 272 : 4361, 4137
7210 00:59:49.965979 276 : 4250, 4027
7211 00:59:49.969064 280 : 4363, 4140
7212 00:59:49.969673 284 : 4361, 4138
7213 00:59:49.972153 288 : 4250, 4026
7214 00:59:49.972621 292 : 4250, 4027
7215 00:59:49.973071 296 : 4252, 4029
7216 00:59:49.974805 300 : 4250, 4027
7217 00:59:49.975370 304 : 4250, 4026
7218 00:59:49.978514 308 : 4250, 4027
7219 00:59:49.979096 312 : 4253, 4029
7220 00:59:49.981443 316 : 4250, 4026
7221 00:59:49.981913 320 : 4360, 4137
7222 00:59:49.984434 324 : 4361, 4137
7223 00:59:49.984950 328 : 4249, 4027
7224 00:59:49.988610 332 : 4363, 4140
7225 00:59:49.989248 336 : 4360, 4071
7226 00:59:49.991436 340 : 4250, 2218
7227 00:59:49.991904 344 : 4250, 0
7228 00:59:49.992276
7229 00:59:49.994381 MIOCK jitter meter ch=0
7230 00:59:49.994844
7231 00:59:49.998014 1T = (344-100) = 244 dly cells
7232 00:59:50.001483 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 266/100 ps
7233 00:59:50.001952 ==
7234 00:59:50.004487 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 00:59:50.010905 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7236 00:59:50.011443 ==
7237 00:59:50.014559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7238 00:59:50.021422 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7239 00:59:50.024516 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7240 00:59:50.030808 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7241 00:59:50.038273 [CA 0] Center 41 (11~72) winsize 62
7242 00:59:50.041790 [CA 1] Center 41 (11~72) winsize 62
7243 00:59:50.044833 [CA 2] Center 37 (7~67) winsize 61
7244 00:59:50.048104 [CA 3] Center 37 (7~67) winsize 61
7245 00:59:50.051378 [CA 4] Center 35 (5~66) winsize 62
7246 00:59:50.054643 [CA 5] Center 35 (5~65) winsize 61
7247 00:59:50.055107
7248 00:59:50.058024 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7249 00:59:50.058485
7250 00:59:50.061160 [CATrainingPosCal] consider 1 rank data
7251 00:59:50.064893 u2DelayCellTimex100 = 266/100 ps
7252 00:59:50.068109 CA0 delay=41 (11~72),Diff = 6 PI (22 cell)
7253 00:59:50.074500 CA1 delay=41 (11~72),Diff = 6 PI (22 cell)
7254 00:59:50.078407 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7255 00:59:50.081677 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7256 00:59:50.084892 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7257 00:59:50.087892 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7258 00:59:50.088447
7259 00:59:50.091710 CA PerBit enable=1, Macro0, CA PI delay=35
7260 00:59:50.092270
7261 00:59:50.095076 [CBTSetCACLKResult] CA Dly = 35
7262 00:59:50.097753 CS Dly: 11 (0~42)
7263 00:59:50.101461 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7264 00:59:50.105441 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7265 00:59:50.105907 ==
7266 00:59:50.107502 Dram Type= 6, Freq= 0, CH_0, rank 1
7267 00:59:50.111191 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7268 00:59:50.111654 ==
7269 00:59:50.117591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7270 00:59:50.121776 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7271 00:59:50.130330 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7272 00:59:50.131424 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7273 00:59:50.141505 [CA 0] Center 42 (12~73) winsize 62
7274 00:59:50.144246 [CA 1] Center 42 (12~73) winsize 62
7275 00:59:50.148877 [CA 2] Center 38 (9~68) winsize 60
7276 00:59:50.150331 [CA 3] Center 37 (8~67) winsize 60
7277 00:59:50.154080 [CA 4] Center 36 (6~66) winsize 61
7278 00:59:50.157876 [CA 5] Center 36 (6~66) winsize 61
7279 00:59:50.158473
7280 00:59:50.160704 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7281 00:59:50.161353
7282 00:59:50.163921 [CATrainingPosCal] consider 2 rank data
7283 00:59:50.167549 u2DelayCellTimex100 = 266/100 ps
7284 00:59:50.174085 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7285 00:59:50.177231 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7286 00:59:50.180699 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7287 00:59:50.183443 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7288 00:59:50.187004 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7289 00:59:50.190639 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7290 00:59:50.191195
7291 00:59:50.193435 CA PerBit enable=1, Macro0, CA PI delay=35
7292 00:59:50.193899
7293 00:59:50.196572 [CBTSetCACLKResult] CA Dly = 35
7294 00:59:50.200326 CS Dly: 11 (0~42)
7295 00:59:50.203584 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7296 00:59:50.207116 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7297 00:59:50.207573
7298 00:59:50.210548 ----->DramcWriteLeveling(PI) begin...
7299 00:59:50.211011 ==
7300 00:59:50.213173 Dram Type= 6, Freq= 0, CH_0, rank 0
7301 00:59:50.220310 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7302 00:59:50.220926 ==
7303 00:59:50.223510 Write leveling (Byte 0): 29 => 29
7304 00:59:50.227255 Write leveling (Byte 1): 28 => 28
7305 00:59:50.227817 DramcWriteLeveling(PI) end<-----
7306 00:59:50.228179
7307 00:59:50.229902 ==
7308 00:59:50.233306 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 00:59:50.237262 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7310 00:59:50.237818 ==
7311 00:59:50.239851 [Gating] SW mode calibration
7312 00:59:50.246639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7313 00:59:50.250195 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7314 00:59:50.256288 0 12 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7315 00:59:50.259939 0 12 4 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
7316 00:59:50.263213 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 00:59:50.270025 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7318 00:59:50.272807 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 00:59:50.277151 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 00:59:50.282501 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7321 00:59:50.285898 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 00:59:50.290033 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7323 00:59:50.296677 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7324 00:59:50.299795 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 00:59:50.302864 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 00:59:50.309275 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 00:59:50.312675 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 00:59:50.315934 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 00:59:50.322286 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 00:59:50.325951 0 14 0 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7331 00:59:50.329129 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
7332 00:59:50.335378 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 00:59:50.339333 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 00:59:50.342161 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 00:59:50.349388 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 00:59:50.352675 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 00:59:50.355251 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7338 00:59:50.361997 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7339 00:59:50.365425 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7340 00:59:50.368568 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7341 00:59:50.375434 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 00:59:50.378401 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 00:59:50.381924 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 00:59:50.388285 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 00:59:50.391285 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 00:59:50.394955 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 00:59:50.402488 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 00:59:50.404823 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 00:59:50.408923 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 00:59:50.414710 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 00:59:50.417793 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 00:59:50.421778 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 00:59:50.428344 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 00:59:50.431206 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7355 00:59:50.434311 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7356 00:59:50.441640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7357 00:59:50.442202 Total UI for P1: 0, mck2ui 16
7358 00:59:50.449237 best dqsien dly found for B0: ( 1, 1, 2)
7359 00:59:50.451016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7360 00:59:50.456161 Total UI for P1: 0, mck2ui 16
7361 00:59:50.457733 best dqsien dly found for B1: ( 1, 1, 6)
7362 00:59:50.461525 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7363 00:59:50.465486 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7364 00:59:50.466049
7365 00:59:50.467489 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7366 00:59:50.471103 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7367 00:59:50.474548 [Gating] SW calibration Done
7368 00:59:50.475122 ==
7369 00:59:50.478450 Dram Type= 6, Freq= 0, CH_0, rank 0
7370 00:59:50.481188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7371 00:59:50.483963 ==
7372 00:59:50.484516 RX Vref Scan: 0
7373 00:59:50.484931
7374 00:59:50.487600 RX Vref 0 -> 0, step: 1
7375 00:59:50.488158
7376 00:59:50.488527 RX Delay 0 -> 252, step: 8
7377 00:59:50.494081 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7378 00:59:50.497044 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7379 00:59:50.500816 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7380 00:59:50.504070 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7381 00:59:50.508000 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7382 00:59:50.514498 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7383 00:59:50.517032 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7384 00:59:50.521053 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7385 00:59:50.524040 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7386 00:59:50.527354 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7387 00:59:50.533823 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7388 00:59:50.537373 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7389 00:59:50.540637 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7390 00:59:50.544161 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7391 00:59:50.551487 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7392 00:59:50.553552 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7393 00:59:50.554012 ==
7394 00:59:50.557380 Dram Type= 6, Freq= 0, CH_0, rank 0
7395 00:59:50.560442 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7396 00:59:50.561063 ==
7397 00:59:50.561436 DQS Delay:
7398 00:59:50.564329 DQS0 = 0, DQS1 = 0
7399 00:59:50.564841 DQM Delay:
7400 00:59:50.567432 DQM0 = 130, DQM1 = 124
7401 00:59:50.567984 DQ Delay:
7402 00:59:50.570746 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7403 00:59:50.574221 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7404 00:59:50.576752 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7405 00:59:50.583599 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7406 00:59:50.584160
7407 00:59:50.584526
7408 00:59:50.584911 ==
7409 00:59:50.586853 Dram Type= 6, Freq= 0, CH_0, rank 0
7410 00:59:50.590726 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7411 00:59:50.591288 ==
7412 00:59:50.591661
7413 00:59:50.591998
7414 00:59:50.593367 TX Vref Scan disable
7415 00:59:50.593827 == TX Byte 0 ==
7416 00:59:50.599683 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7417 00:59:50.603586 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7418 00:59:50.604298 == TX Byte 1 ==
7419 00:59:50.609974 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7420 00:59:50.612916 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7421 00:59:50.613377 ==
7422 00:59:50.616325 Dram Type= 6, Freq= 0, CH_0, rank 0
7423 00:59:50.620136 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7424 00:59:50.620696 ==
7425 00:59:50.633946
7426 00:59:50.636937 TX Vref early break, caculate TX vref
7427 00:59:50.640410 TX Vref=16, minBit 8, minWin=22, winSum=376
7428 00:59:50.643553 TX Vref=18, minBit 8, minWin=22, winSum=385
7429 00:59:50.646272 TX Vref=20, minBit 2, minWin=24, winSum=394
7430 00:59:50.650652 TX Vref=22, minBit 8, minWin=24, winSum=401
7431 00:59:50.654218 TX Vref=24, minBit 11, minWin=24, winSum=408
7432 00:59:50.660102 TX Vref=26, minBit 7, minWin=25, winSum=416
7433 00:59:50.663317 TX Vref=28, minBit 0, minWin=25, winSum=420
7434 00:59:50.666980 TX Vref=30, minBit 1, minWin=25, winSum=411
7435 00:59:50.669921 TX Vref=32, minBit 6, minWin=24, winSum=406
7436 00:59:50.673600 TX Vref=34, minBit 0, minWin=24, winSum=396
7437 00:59:50.679685 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
7438 00:59:50.680311
7439 00:59:50.682921 Final TX Range 0 Vref 28
7440 00:59:50.683483
7441 00:59:50.683935 ==
7442 00:59:50.686415 Dram Type= 6, Freq= 0, CH_0, rank 0
7443 00:59:50.689534 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7444 00:59:50.690009 ==
7445 00:59:50.690425
7446 00:59:50.690763
7447 00:59:50.692976 TX Vref Scan disable
7448 00:59:50.699580 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7449 00:59:50.700065 == TX Byte 0 ==
7450 00:59:50.703122 u2DelayCellOfst[0]=14 cells (4 PI)
7451 00:59:50.705936 u2DelayCellOfst[1]=18 cells (5 PI)
7452 00:59:50.710052 u2DelayCellOfst[2]=14 cells (4 PI)
7453 00:59:50.712777 u2DelayCellOfst[3]=11 cells (3 PI)
7454 00:59:50.716166 u2DelayCellOfst[4]=7 cells (2 PI)
7455 00:59:50.720121 u2DelayCellOfst[5]=0 cells (0 PI)
7456 00:59:50.722993 u2DelayCellOfst[6]=18 cells (5 PI)
7457 00:59:50.726624 u2DelayCellOfst[7]=22 cells (6 PI)
7458 00:59:50.729399 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7459 00:59:50.732890 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7460 00:59:50.736289 == TX Byte 1 ==
7461 00:59:50.736887 u2DelayCellOfst[8]=3 cells (1 PI)
7462 00:59:50.739512 u2DelayCellOfst[9]=0 cells (0 PI)
7463 00:59:50.743135 u2DelayCellOfst[10]=11 cells (3 PI)
7464 00:59:50.746143 u2DelayCellOfst[11]=3 cells (1 PI)
7465 00:59:50.749543 u2DelayCellOfst[12]=11 cells (3 PI)
7466 00:59:50.753100 u2DelayCellOfst[13]=14 cells (4 PI)
7467 00:59:50.756167 u2DelayCellOfst[14]=18 cells (5 PI)
7468 00:59:50.759681 u2DelayCellOfst[15]=14 cells (4 PI)
7469 00:59:50.762936 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7470 00:59:50.769449 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7471 00:59:50.770005 DramC Write-DBI on
7472 00:59:50.770369 ==
7473 00:59:50.772878 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 00:59:50.779389 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7475 00:59:50.779948 ==
7476 00:59:50.780335
7477 00:59:50.780677
7478 00:59:50.781050 TX Vref Scan disable
7479 00:59:50.783249 == TX Byte 0 ==
7480 00:59:50.786331 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7481 00:59:50.789314 == TX Byte 1 ==
7482 00:59:50.793304 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7483 00:59:50.796582 DramC Write-DBI off
7484 00:59:50.797120
7485 00:59:50.797487 [DATLAT]
7486 00:59:50.797827 Freq=1600, CH0 RK0
7487 00:59:50.798158
7488 00:59:50.800223 DATLAT Default: 0xf
7489 00:59:50.800741 0, 0xFFFF, sum = 0
7490 00:59:50.802854 1, 0xFFFF, sum = 0
7491 00:59:50.806386 2, 0xFFFF, sum = 0
7492 00:59:50.806946 3, 0xFFFF, sum = 0
7493 00:59:50.809262 4, 0xFFFF, sum = 0
7494 00:59:50.809740 5, 0xFFFF, sum = 0
7495 00:59:50.812360 6, 0xFFFF, sum = 0
7496 00:59:50.812868 7, 0xFFFF, sum = 0
7497 00:59:50.816381 8, 0xFFFF, sum = 0
7498 00:59:50.816912 9, 0xFFFF, sum = 0
7499 00:59:50.819846 10, 0xFFFF, sum = 0
7500 00:59:50.820430 11, 0xFFFF, sum = 0
7501 00:59:50.822786 12, 0xBFF, sum = 0
7502 00:59:50.823371 13, 0x0, sum = 1
7503 00:59:50.826063 14, 0x0, sum = 2
7504 00:59:50.826529 15, 0x0, sum = 3
7505 00:59:50.830437 16, 0x0, sum = 4
7506 00:59:50.831006 best_step = 14
7507 00:59:50.831375
7508 00:59:50.831721 ==
7509 00:59:50.832776 Dram Type= 6, Freq= 0, CH_0, rank 0
7510 00:59:50.836308 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7511 00:59:50.838909 ==
7512 00:59:50.839368 RX Vref Scan: 1
7513 00:59:50.839731
7514 00:59:50.842312 Set Vref Range= 24 -> 127
7515 00:59:50.842793
7516 00:59:50.846036 RX Vref 24 -> 127, step: 1
7517 00:59:50.846594
7518 00:59:50.847246 RX Delay 11 -> 252, step: 4
7519 00:59:50.847782
7520 00:59:50.849039 Set Vref, RX VrefLevel [Byte0]: 24
7521 00:59:50.853034 [Byte1]: 24
7522 00:59:50.856419
7523 00:59:50.857030 Set Vref, RX VrefLevel [Byte0]: 25
7524 00:59:50.859739 [Byte1]: 25
7525 00:59:50.863728
7526 00:59:50.864296 Set Vref, RX VrefLevel [Byte0]: 26
7527 00:59:50.866949 [Byte1]: 26
7528 00:59:50.872662
7529 00:59:50.873270 Set Vref, RX VrefLevel [Byte0]: 27
7530 00:59:50.875146 [Byte1]: 27
7531 00:59:50.878963
7532 00:59:50.879512 Set Vref, RX VrefLevel [Byte0]: 28
7533 00:59:50.882490 [Byte1]: 28
7534 00:59:50.886622
7535 00:59:50.887180 Set Vref, RX VrefLevel [Byte0]: 29
7536 00:59:50.889676 [Byte1]: 29
7537 00:59:50.894134
7538 00:59:50.894792 Set Vref, RX VrefLevel [Byte0]: 30
7539 00:59:50.898483 [Byte1]: 30
7540 00:59:50.901660
7541 00:59:50.902118 Set Vref, RX VrefLevel [Byte0]: 31
7542 00:59:50.906112 [Byte1]: 31
7543 00:59:50.909553
7544 00:59:50.910102 Set Vref, RX VrefLevel [Byte0]: 32
7545 00:59:50.912865 [Byte1]: 32
7546 00:59:50.917413
7547 00:59:50.917967 Set Vref, RX VrefLevel [Byte0]: 33
7548 00:59:50.920573 [Byte1]: 33
7549 00:59:50.925081
7550 00:59:50.925632 Set Vref, RX VrefLevel [Byte0]: 34
7551 00:59:50.927818 [Byte1]: 34
7552 00:59:50.932312
7553 00:59:50.932914 Set Vref, RX VrefLevel [Byte0]: 35
7554 00:59:50.935412 [Byte1]: 35
7555 00:59:50.940019
7556 00:59:50.940566 Set Vref, RX VrefLevel [Byte0]: 36
7557 00:59:50.943330 [Byte1]: 36
7558 00:59:50.947698
7559 00:59:50.948561 Set Vref, RX VrefLevel [Byte0]: 37
7560 00:59:50.951036 [Byte1]: 37
7561 00:59:50.955514
7562 00:59:50.956066 Set Vref, RX VrefLevel [Byte0]: 38
7563 00:59:50.959043 [Byte1]: 38
7564 00:59:50.962765
7565 00:59:50.963313 Set Vref, RX VrefLevel [Byte0]: 39
7566 00:59:50.966278 [Byte1]: 39
7567 00:59:50.970670
7568 00:59:50.971226 Set Vref, RX VrefLevel [Byte0]: 40
7569 00:59:50.973610 [Byte1]: 40
7570 00:59:50.978534
7571 00:59:50.979084 Set Vref, RX VrefLevel [Byte0]: 41
7572 00:59:50.981282 [Byte1]: 41
7573 00:59:50.985892
7574 00:59:50.986439 Set Vref, RX VrefLevel [Byte0]: 42
7575 00:59:50.989419 [Byte1]: 42
7576 00:59:50.993673
7577 00:59:50.994222 Set Vref, RX VrefLevel [Byte0]: 43
7578 00:59:50.997647 [Byte1]: 43
7579 00:59:51.000675
7580 00:59:51.001280 Set Vref, RX VrefLevel [Byte0]: 44
7581 00:59:51.005270 [Byte1]: 44
7582 00:59:51.009042
7583 00:59:51.009603 Set Vref, RX VrefLevel [Byte0]: 45
7584 00:59:51.012674 [Byte1]: 45
7585 00:59:51.016163
7586 00:59:51.016783 Set Vref, RX VrefLevel [Byte0]: 46
7587 00:59:51.019192 [Byte1]: 46
7588 00:59:51.023809
7589 00:59:51.024392 Set Vref, RX VrefLevel [Byte0]: 47
7590 00:59:51.028518 [Byte1]: 47
7591 00:59:51.031774
7592 00:59:51.032335 Set Vref, RX VrefLevel [Byte0]: 48
7593 00:59:51.034341 [Byte1]: 48
7594 00:59:51.039377
7595 00:59:51.039938 Set Vref, RX VrefLevel [Byte0]: 49
7596 00:59:51.042109 [Byte1]: 49
7597 00:59:51.046572
7598 00:59:51.047152 Set Vref, RX VrefLevel [Byte0]: 50
7599 00:59:51.050028 [Byte1]: 50
7600 00:59:51.055324
7601 00:59:51.055886 Set Vref, RX VrefLevel [Byte0]: 51
7602 00:59:51.057176 [Byte1]: 51
7603 00:59:51.061473
7604 00:59:51.061933 Set Vref, RX VrefLevel [Byte0]: 52
7605 00:59:51.065370 [Byte1]: 52
7606 00:59:51.069836
7607 00:59:51.070396 Set Vref, RX VrefLevel [Byte0]: 53
7608 00:59:51.072781 [Byte1]: 53
7609 00:59:51.077503
7610 00:59:51.078070 Set Vref, RX VrefLevel [Byte0]: 54
7611 00:59:51.080473 [Byte1]: 54
7612 00:59:51.084359
7613 00:59:51.084962 Set Vref, RX VrefLevel [Byte0]: 55
7614 00:59:51.088054 [Byte1]: 55
7615 00:59:51.092263
7616 00:59:51.092879 Set Vref, RX VrefLevel [Byte0]: 56
7617 00:59:51.094959 [Byte1]: 56
7618 00:59:51.100034
7619 00:59:51.100602 Set Vref, RX VrefLevel [Byte0]: 57
7620 00:59:51.102799 [Byte1]: 57
7621 00:59:51.107443
7622 00:59:51.108004 Set Vref, RX VrefLevel [Byte0]: 58
7623 00:59:51.110944 [Byte1]: 58
7624 00:59:51.115749
7625 00:59:51.116313 Set Vref, RX VrefLevel [Byte0]: 59
7626 00:59:51.118601 [Byte1]: 59
7627 00:59:51.123252
7628 00:59:51.123814 Set Vref, RX VrefLevel [Byte0]: 60
7629 00:59:51.125826 [Byte1]: 60
7630 00:59:51.130254
7631 00:59:51.130820 Set Vref, RX VrefLevel [Byte0]: 61
7632 00:59:51.133579 [Byte1]: 61
7633 00:59:51.138295
7634 00:59:51.138855 Set Vref, RX VrefLevel [Byte0]: 62
7635 00:59:51.141231 [Byte1]: 62
7636 00:59:51.145756
7637 00:59:51.146319 Set Vref, RX VrefLevel [Byte0]: 63
7638 00:59:51.148820 [Byte1]: 63
7639 00:59:51.152667
7640 00:59:51.153209 Set Vref, RX VrefLevel [Byte0]: 64
7641 00:59:51.156289 [Byte1]: 64
7642 00:59:51.161137
7643 00:59:51.161596 Set Vref, RX VrefLevel [Byte0]: 65
7644 00:59:51.163929 [Byte1]: 65
7645 00:59:51.168171
7646 00:59:51.168776 Set Vref, RX VrefLevel [Byte0]: 66
7647 00:59:51.172537 [Byte1]: 66
7648 00:59:51.175851
7649 00:59:51.176307 Set Vref, RX VrefLevel [Byte0]: 67
7650 00:59:51.179373 [Byte1]: 67
7651 00:59:51.183818
7652 00:59:51.184277 Set Vref, RX VrefLevel [Byte0]: 68
7653 00:59:51.186896 [Byte1]: 68
7654 00:59:51.191805
7655 00:59:51.192358 Set Vref, RX VrefLevel [Byte0]: 69
7656 00:59:51.195250 [Byte1]: 69
7657 00:59:51.199486
7658 00:59:51.199963 Set Vref, RX VrefLevel [Byte0]: 70
7659 00:59:51.201992 [Byte1]: 70
7660 00:59:51.206352
7661 00:59:51.206967 Set Vref, RX VrefLevel [Byte0]: 71
7662 00:59:51.209936 [Byte1]: 71
7663 00:59:51.213677
7664 00:59:51.214232 Set Vref, RX VrefLevel [Byte0]: 72
7665 00:59:51.217342 [Byte1]: 72
7666 00:59:51.222952
7667 00:59:51.223507 Set Vref, RX VrefLevel [Byte0]: 73
7668 00:59:51.226463 [Byte1]: 73
7669 00:59:51.229523
7670 00:59:51.230080 Set Vref, RX VrefLevel [Byte0]: 74
7671 00:59:51.232670 [Byte1]: 74
7672 00:59:51.237142
7673 00:59:51.237700 Final RX Vref Byte 0 = 53 to rank0
7674 00:59:51.240218 Final RX Vref Byte 1 = 55 to rank0
7675 00:59:51.243519 Final RX Vref Byte 0 = 53 to rank1
7676 00:59:51.247080 Final RX Vref Byte 1 = 55 to rank1==
7677 00:59:51.251535 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 00:59:51.256901 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7679 00:59:51.257467 ==
7680 00:59:51.257839 DQS Delay:
7681 00:59:51.258183 DQS0 = 0, DQS1 = 0
7682 00:59:51.260112 DQM Delay:
7683 00:59:51.260646 DQM0 = 126, DQM1 = 121
7684 00:59:51.263569 DQ Delay:
7685 00:59:51.266858 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7686 00:59:51.270248 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7687 00:59:51.273245 DQ8 =112, DQ9 =104, DQ10 =122, DQ11 =112
7688 00:59:51.276853 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7689 00:59:51.277338
7690 00:59:51.277702
7691 00:59:51.278041
7692 00:59:51.280267 [DramC_TX_OE_Calibration] TA2
7693 00:59:51.283580 Original DQ_B0 (3 6) =30, OEN = 27
7694 00:59:51.286570 Original DQ_B1 (3 6) =30, OEN = 27
7695 00:59:51.289709 24, 0x0, End_B0=24 End_B1=24
7696 00:59:51.290176 25, 0x0, End_B0=25 End_B1=25
7697 00:59:51.293215 26, 0x0, End_B0=26 End_B1=26
7698 00:59:51.296067 27, 0x0, End_B0=27 End_B1=27
7699 00:59:51.300113 28, 0x0, End_B0=28 End_B1=28
7700 00:59:51.303589 29, 0x0, End_B0=29 End_B1=29
7701 00:59:51.304080 30, 0x0, End_B0=30 End_B1=30
7702 00:59:51.306417 31, 0x4141, End_B0=30 End_B1=30
7703 00:59:51.310632 Byte0 end_step=30 best_step=27
7704 00:59:51.312839 Byte1 end_step=30 best_step=27
7705 00:59:51.316435 Byte0 TX OE(2T, 0.5T) = (3, 3)
7706 00:59:51.319515 Byte1 TX OE(2T, 0.5T) = (3, 3)
7707 00:59:51.320073
7708 00:59:51.320451
7709 00:59:51.326478 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7710 00:59:51.330069 CH0 RK0: MR19=303, MR18=1919
7711 00:59:51.336274 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7712 00:59:51.336863
7713 00:59:51.340260 ----->DramcWriteLeveling(PI) begin...
7714 00:59:51.340871 ==
7715 00:59:51.343058 Dram Type= 6, Freq= 0, CH_0, rank 1
7716 00:59:51.346232 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7717 00:59:51.346797 ==
7718 00:59:51.349366 Write leveling (Byte 0): 28 => 28
7719 00:59:51.352948 Write leveling (Byte 1): 27 => 27
7720 00:59:51.356216 DramcWriteLeveling(PI) end<-----
7721 00:59:51.356819
7722 00:59:51.357285 ==
7723 00:59:51.359343 Dram Type= 6, Freq= 0, CH_0, rank 1
7724 00:59:51.362388 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7725 00:59:51.362852 ==
7726 00:59:51.366106 [Gating] SW mode calibration
7727 00:59:51.372509 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7728 00:59:51.379081 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7729 00:59:51.382197 0 12 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7730 00:59:51.389482 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7731 00:59:51.392284 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7732 00:59:51.396238 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 00:59:51.401933 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 00:59:51.405212 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 00:59:51.409410 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7736 00:59:51.415447 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7737 00:59:51.419329 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)
7738 00:59:51.422132 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7739 00:59:51.429166 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7740 00:59:51.432683 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 00:59:51.435042 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 00:59:51.442328 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 00:59:51.445413 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 00:59:51.449129 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 00:59:51.455270 0 14 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7746 00:59:51.458502 0 14 4 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
7747 00:59:51.461941 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7748 00:59:51.469244 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 00:59:51.471882 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 00:59:51.475170 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 00:59:51.481973 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 00:59:51.485466 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7753 00:59:51.488457 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7754 00:59:51.492067 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7755 00:59:51.498251 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 00:59:51.501406 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 00:59:51.504742 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 00:59:51.511542 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 00:59:51.515137 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 00:59:51.517955 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 00:59:51.525188 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 00:59:51.528093 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 00:59:51.531258 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 00:59:51.537633 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 00:59:51.541180 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 00:59:51.545052 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 00:59:51.550895 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 00:59:51.554005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7769 00:59:51.557694 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7770 00:59:51.564232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7771 00:59:51.568062 Total UI for P1: 0, mck2ui 16
7772 00:59:51.571888 best dqsien dly found for B0: ( 1, 0, 30)
7773 00:59:51.574789 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7774 00:59:51.578341 Total UI for P1: 0, mck2ui 16
7775 00:59:51.580847 best dqsien dly found for B1: ( 1, 1, 2)
7776 00:59:51.584376 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7777 00:59:51.587775 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7778 00:59:51.588334
7779 00:59:51.591119 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7780 00:59:51.594582 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7781 00:59:51.597906 [Gating] SW calibration Done
7782 00:59:51.598368 ==
7783 00:59:51.600792 Dram Type= 6, Freq= 0, CH_0, rank 1
7784 00:59:51.604027 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7785 00:59:51.607675 ==
7786 00:59:51.608285 RX Vref Scan: 0
7787 00:59:51.608654
7788 00:59:51.611201 RX Vref 0 -> 0, step: 1
7789 00:59:51.611760
7790 00:59:51.613861 RX Delay 0 -> 252, step: 8
7791 00:59:51.617499 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7792 00:59:51.621249 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7793 00:59:51.623870 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7794 00:59:51.627420 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7795 00:59:51.634356 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7796 00:59:51.637268 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7797 00:59:51.640489 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7798 00:59:51.644257 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7799 00:59:51.647339 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7800 00:59:51.655164 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7801 00:59:51.657345 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7802 00:59:51.660561 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7803 00:59:51.663906 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7804 00:59:51.667229 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7805 00:59:51.673674 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7806 00:59:51.676926 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7807 00:59:51.677515 ==
7808 00:59:51.681350 Dram Type= 6, Freq= 0, CH_0, rank 1
7809 00:59:51.683578 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7810 00:59:51.684040 ==
7811 00:59:51.686873 DQS Delay:
7812 00:59:51.687406 DQS0 = 0, DQS1 = 0
7813 00:59:51.687769 DQM Delay:
7814 00:59:51.689718 DQM0 = 131, DQM1 = 124
7815 00:59:51.690177 DQ Delay:
7816 00:59:51.693314 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7817 00:59:51.696783 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7818 00:59:51.703616 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7819 00:59:51.706219 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7820 00:59:51.706737
7821 00:59:51.707107
7822 00:59:51.707444 ==
7823 00:59:51.710411 Dram Type= 6, Freq= 0, CH_0, rank 1
7824 00:59:51.713584 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7825 00:59:51.714049 ==
7826 00:59:51.714415
7827 00:59:51.714756
7828 00:59:51.716665 TX Vref Scan disable
7829 00:59:51.717175 == TX Byte 0 ==
7830 00:59:51.723632 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7831 00:59:51.726744 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7832 00:59:51.729856 == TX Byte 1 ==
7833 00:59:51.733245 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7834 00:59:51.736511 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7835 00:59:51.737111 ==
7836 00:59:51.740117 Dram Type= 6, Freq= 0, CH_0, rank 1
7837 00:59:51.742887 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7838 00:59:51.743449 ==
7839 00:59:51.757552
7840 00:59:51.761085 TX Vref early break, caculate TX vref
7841 00:59:51.764427 TX Vref=16, minBit 9, minWin=21, winSum=377
7842 00:59:51.767196 TX Vref=18, minBit 1, minWin=23, winSum=390
7843 00:59:51.770984 TX Vref=20, minBit 9, minWin=22, winSum=394
7844 00:59:51.773637 TX Vref=22, minBit 8, minWin=23, winSum=401
7845 00:59:51.776897 TX Vref=24, minBit 2, minWin=25, winSum=413
7846 00:59:51.783636 TX Vref=26, minBit 8, minWin=25, winSum=418
7847 00:59:51.786582 TX Vref=28, minBit 8, minWin=24, winSum=421
7848 00:59:51.789986 TX Vref=30, minBit 8, minWin=24, winSum=414
7849 00:59:51.793343 TX Vref=32, minBit 8, minWin=23, winSum=402
7850 00:59:51.796990 TX Vref=34, minBit 8, minWin=23, winSum=394
7851 00:59:51.803670 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 26
7852 00:59:51.804232
7853 00:59:51.807276 Final TX Range 0 Vref 26
7854 00:59:51.807738
7855 00:59:51.808100 ==
7856 00:59:51.810612 Dram Type= 6, Freq= 0, CH_0, rank 1
7857 00:59:51.813170 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7858 00:59:51.813633 ==
7859 00:59:51.814001
7860 00:59:51.814337
7861 00:59:51.816648 TX Vref Scan disable
7862 00:59:51.823286 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
7863 00:59:51.823844 == TX Byte 0 ==
7864 00:59:51.826432 u2DelayCellOfst[0]=11 cells (3 PI)
7865 00:59:51.829422 u2DelayCellOfst[1]=18 cells (5 PI)
7866 00:59:51.833042 u2DelayCellOfst[2]=11 cells (3 PI)
7867 00:59:51.836823 u2DelayCellOfst[3]=11 cells (3 PI)
7868 00:59:51.839760 u2DelayCellOfst[4]=7 cells (2 PI)
7869 00:59:51.843360 u2DelayCellOfst[5]=0 cells (0 PI)
7870 00:59:51.846457 u2DelayCellOfst[6]=18 cells (5 PI)
7871 00:59:51.850270 u2DelayCellOfst[7]=18 cells (5 PI)
7872 00:59:51.852984 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7873 00:59:51.856356 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7874 00:59:51.859758 == TX Byte 1 ==
7875 00:59:51.860273 u2DelayCellOfst[8]=3 cells (1 PI)
7876 00:59:51.863547 u2DelayCellOfst[9]=0 cells (0 PI)
7877 00:59:51.866301 u2DelayCellOfst[10]=7 cells (2 PI)
7878 00:59:51.871034 u2DelayCellOfst[11]=3 cells (1 PI)
7879 00:59:51.872857 u2DelayCellOfst[12]=14 cells (4 PI)
7880 00:59:51.877248 u2DelayCellOfst[13]=14 cells (4 PI)
7881 00:59:51.879696 u2DelayCellOfst[14]=18 cells (5 PI)
7882 00:59:51.883922 u2DelayCellOfst[15]=14 cells (4 PI)
7883 00:59:51.885969 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7884 00:59:51.892690 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7885 00:59:51.893227 DramC Write-DBI on
7886 00:59:51.893560 ==
7887 00:59:51.896596 Dram Type= 6, Freq= 0, CH_0, rank 1
7888 00:59:51.900352 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7889 00:59:51.902552 ==
7890 00:59:51.902970
7891 00:59:51.903300
7892 00:59:51.903607 TX Vref Scan disable
7893 00:59:51.906551 == TX Byte 0 ==
7894 00:59:51.909424 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7895 00:59:51.912987 == TX Byte 1 ==
7896 00:59:51.916138 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7897 00:59:51.920108 DramC Write-DBI off
7898 00:59:51.920629
7899 00:59:51.921015 [DATLAT]
7900 00:59:51.921329 Freq=1600, CH0 RK1
7901 00:59:51.921631
7902 00:59:51.922656 DATLAT Default: 0xe
7903 00:59:51.923073 0, 0xFFFF, sum = 0
7904 00:59:51.925935 1, 0xFFFF, sum = 0
7905 00:59:51.929688 2, 0xFFFF, sum = 0
7906 00:59:51.930209 3, 0xFFFF, sum = 0
7907 00:59:51.933198 4, 0xFFFF, sum = 0
7908 00:59:51.933909 5, 0xFFFF, sum = 0
7909 00:59:51.936052 6, 0xFFFF, sum = 0
7910 00:59:51.936573 7, 0xFFFF, sum = 0
7911 00:59:51.940072 8, 0xFFFF, sum = 0
7912 00:59:51.940600 9, 0xFFFF, sum = 0
7913 00:59:51.942820 10, 0xFFFF, sum = 0
7914 00:59:51.943246 11, 0xFFFF, sum = 0
7915 00:59:51.946069 12, 0x8FFF, sum = 0
7916 00:59:51.946594 13, 0x0, sum = 1
7917 00:59:51.948891 14, 0x0, sum = 2
7918 00:59:51.949314 15, 0x0, sum = 3
7919 00:59:51.952494 16, 0x0, sum = 4
7920 00:59:51.953070 best_step = 14
7921 00:59:51.953408
7922 00:59:51.953718 ==
7923 00:59:51.955991 Dram Type= 6, Freq= 0, CH_0, rank 1
7924 00:59:51.962615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7925 00:59:51.963195 ==
7926 00:59:51.963536 RX Vref Scan: 0
7927 00:59:51.963848
7928 00:59:51.966046 RX Vref 0 -> 0, step: 1
7929 00:59:51.966462
7930 00:59:51.968995 RX Delay 11 -> 252, step: 4
7931 00:59:51.972517 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7932 00:59:51.976892 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7933 00:59:51.979401 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7934 00:59:51.986350 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7935 00:59:51.989337 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7936 00:59:51.992600 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7937 00:59:51.995906 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7938 00:59:51.998489 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7939 00:59:52.005603 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7940 00:59:52.008347 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7941 00:59:52.013442 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7942 00:59:52.015624 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7943 00:59:52.021780 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7944 00:59:52.024872 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7945 00:59:52.028576 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7946 00:59:52.031934 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7947 00:59:52.032397 ==
7948 00:59:52.034908 Dram Type= 6, Freq= 0, CH_0, rank 1
7949 00:59:52.041730 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7950 00:59:52.042292 ==
7951 00:59:52.042666 DQS Delay:
7952 00:59:52.043010 DQS0 = 0, DQS1 = 0
7953 00:59:52.044831 DQM Delay:
7954 00:59:52.045382 DQM0 = 129, DQM1 = 120
7955 00:59:52.048177 DQ Delay:
7956 00:59:52.051724 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7957 00:59:52.054813 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7958 00:59:52.058155 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7959 00:59:52.061893 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7960 00:59:52.062464
7961 00:59:52.062988
7962 00:59:52.063360
7963 00:59:52.065105 [DramC_TX_OE_Calibration] TA2
7964 00:59:52.067938 Original DQ_B0 (3 6) =30, OEN = 27
7965 00:59:52.071568 Original DQ_B1 (3 6) =30, OEN = 27
7966 00:59:52.074372 24, 0x0, End_B0=24 End_B1=24
7967 00:59:52.074839 25, 0x0, End_B0=25 End_B1=25
7968 00:59:52.077837 26, 0x0, End_B0=26 End_B1=26
7969 00:59:52.081669 27, 0x0, End_B0=27 End_B1=27
7970 00:59:52.084616 28, 0x0, End_B0=28 End_B1=28
7971 00:59:52.088076 29, 0x0, End_B0=29 End_B1=29
7972 00:59:52.088638 30, 0x0, End_B0=30 End_B1=30
7973 00:59:52.091144 31, 0x4141, End_B0=30 End_B1=30
7974 00:59:52.096027 Byte0 end_step=30 best_step=27
7975 00:59:52.098263 Byte1 end_step=30 best_step=27
7976 00:59:52.101900 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 00:59:52.104516 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 00:59:52.105001
7979 00:59:52.105363
7980 00:59:52.110952 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
7981 00:59:52.114452 CH0 RK1: MR19=303, MR18=2424
7982 00:59:52.121347 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
7983 00:59:52.123957 [RxdqsGatingPostProcess] freq 1600
7984 00:59:52.127138 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7985 00:59:52.131615 Pre-setting of DQS Precalculation
7986 00:59:52.136960 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7987 00:59:52.137504 ==
7988 00:59:52.140629 Dram Type= 6, Freq= 0, CH_1, rank 0
7989 00:59:52.143488 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7990 00:59:52.143913 ==
7991 00:59:52.150652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7992 00:59:52.153777 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7993 00:59:52.157021 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7994 00:59:52.163143 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7995 00:59:52.172283 [CA 0] Center 41 (11~71) winsize 61
7996 00:59:52.175909 [CA 1] Center 40 (10~70) winsize 61
7997 00:59:52.178628 [CA 2] Center 36 (6~66) winsize 61
7998 00:59:52.182180 [CA 3] Center 35 (6~65) winsize 60
7999 00:59:52.185905 [CA 4] Center 33 (4~63) winsize 60
8000 00:59:52.188985 [CA 5] Center 33 (4~63) winsize 60
8001 00:59:52.189545
8002 00:59:52.192010 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8003 00:59:52.192571
8004 00:59:52.195721 [CATrainingPosCal] consider 1 rank data
8005 00:59:52.198523 u2DelayCellTimex100 = 266/100 ps
8006 00:59:52.205620 CA0 delay=41 (11~71),Diff = 8 PI (29 cell)
8007 00:59:52.208607 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8008 00:59:52.211892 CA2 delay=36 (6~66),Diff = 3 PI (11 cell)
8009 00:59:52.215817 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8010 00:59:52.219067 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8011 00:59:52.221588 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8012 00:59:52.222051
8013 00:59:52.226247 CA PerBit enable=1, Macro0, CA PI delay=33
8014 00:59:52.226710
8015 00:59:52.228452 [CBTSetCACLKResult] CA Dly = 33
8016 00:59:52.232800 CS Dly: 9 (0~40)
8017 00:59:52.235169 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8018 00:59:52.239249 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8019 00:59:52.239766 ==
8020 00:59:52.242029 Dram Type= 6, Freq= 0, CH_1, rank 1
8021 00:59:52.248572 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8022 00:59:52.249166 ==
8023 00:59:52.252400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8024 00:59:52.255100 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8025 00:59:52.262050 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8026 00:59:52.268407 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8027 00:59:52.275067 [CA 0] Center 40 (10~70) winsize 61
8028 00:59:52.278163 [CA 1] Center 39 (9~70) winsize 62
8029 00:59:52.281586 [CA 2] Center 35 (6~65) winsize 60
8030 00:59:52.284518 [CA 3] Center 35 (6~65) winsize 60
8031 00:59:52.288142 [CA 4] Center 32 (3~62) winsize 60
8032 00:59:52.291491 [CA 5] Center 33 (3~63) winsize 61
8033 00:59:52.291971
8034 00:59:52.294415 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8035 00:59:52.294833
8036 00:59:52.298048 [CATrainingPosCal] consider 2 rank data
8037 00:59:52.301251 u2DelayCellTimex100 = 266/100 ps
8038 00:59:52.305087 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8039 00:59:52.311502 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8040 00:59:52.315581 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8041 00:59:52.318381 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8042 00:59:52.321796 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8043 00:59:52.324208 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8044 00:59:52.324753
8045 00:59:52.328367 CA PerBit enable=1, Macro0, CA PI delay=33
8046 00:59:52.329036
8047 00:59:52.331030 [CBTSetCACLKResult] CA Dly = 33
8048 00:59:52.334540 CS Dly: 9 (0~41)
8049 00:59:52.338294 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8050 00:59:52.340912 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8051 00:59:52.341332
8052 00:59:52.344362 ----->DramcWriteLeveling(PI) begin...
8053 00:59:52.344925 ==
8054 00:59:52.347915 Dram Type= 6, Freq= 0, CH_1, rank 0
8055 00:59:52.351991 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8056 00:59:52.354094 ==
8057 00:59:52.354613 Write leveling (Byte 0): 23 => 23
8058 00:59:52.357623 Write leveling (Byte 1): 21 => 21
8059 00:59:52.360606 DramcWriteLeveling(PI) end<-----
8060 00:59:52.361147
8061 00:59:52.361480 ==
8062 00:59:52.363996 Dram Type= 6, Freq= 0, CH_1, rank 0
8063 00:59:52.370753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8064 00:59:52.371279 ==
8065 00:59:52.374447 [Gating] SW mode calibration
8066 00:59:52.380535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8067 00:59:52.384625 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8068 00:59:52.390609 0 12 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8069 00:59:52.393757 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 00:59:52.397056 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 00:59:52.404345 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 00:59:52.407369 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 00:59:52.410448 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 00:59:52.417654 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8075 00:59:52.420544 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8076 00:59:52.423806 0 13 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8077 00:59:52.430722 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8078 00:59:52.434041 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 00:59:52.437499 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 00:59:52.440913 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 00:59:52.446687 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 00:59:52.450330 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 00:59:52.453948 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8084 00:59:52.460337 0 14 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8085 00:59:52.463470 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 00:59:52.466936 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 00:59:52.473768 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 00:59:52.476686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 00:59:52.480560 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 00:59:52.487217 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 00:59:52.490384 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8092 00:59:52.493030 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 00:59:52.499896 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 00:59:52.503737 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 00:59:52.506361 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 00:59:52.513097 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 00:59:52.516314 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 00:59:52.519911 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 00:59:52.526043 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 00:59:52.529685 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 00:59:52.533292 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 00:59:52.540515 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 00:59:52.543359 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 00:59:52.546571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 00:59:52.553029 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 00:59:52.556819 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 00:59:52.560121 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 00:59:52.565577 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 00:59:52.569863 Total UI for P1: 0, mck2ui 16
8110 00:59:52.572249 best dqsien dly found for B0: ( 1, 0, 26)
8111 00:59:52.576575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 00:59:52.579448 Total UI for P1: 0, mck2ui 16
8113 00:59:52.582466 best dqsien dly found for B1: ( 1, 1, 0)
8114 00:59:52.586155 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8115 00:59:52.589406 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8116 00:59:52.589961
8117 00:59:52.592842 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8118 00:59:52.595439 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8119 00:59:52.599187 [Gating] SW calibration Done
8120 00:59:52.599645 ==
8121 00:59:52.602384 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 00:59:52.606040 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 00:59:52.609077 ==
8124 00:59:52.609533 RX Vref Scan: 0
8125 00:59:52.609892
8126 00:59:52.612161 RX Vref 0 -> 0, step: 1
8127 00:59:52.612617
8128 00:59:52.615995 RX Delay 0 -> 252, step: 8
8129 00:59:52.619074 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8130 00:59:52.622254 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8131 00:59:52.625545 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8132 00:59:52.628925 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8133 00:59:52.635542 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8134 00:59:52.638679 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8135 00:59:52.641892 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8136 00:59:52.645935 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8137 00:59:52.648969 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8138 00:59:52.655423 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8139 00:59:52.659519 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8140 00:59:52.661657 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8141 00:59:52.664997 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8142 00:59:52.668598 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8143 00:59:52.675250 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8144 00:59:52.678652 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8145 00:59:52.679209 ==
8146 00:59:52.682204 Dram Type= 6, Freq= 0, CH_1, rank 0
8147 00:59:52.684922 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8148 00:59:52.685478 ==
8149 00:59:52.688602 DQS Delay:
8150 00:59:52.689212 DQS0 = 0, DQS1 = 0
8151 00:59:52.689584 DQM Delay:
8152 00:59:52.691737 DQM0 = 130, DQM1 = 125
8153 00:59:52.692297 DQ Delay:
8154 00:59:52.694867 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8155 00:59:52.698338 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8156 00:59:52.704881 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8157 00:59:52.708460 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8158 00:59:52.709083
8159 00:59:52.709457
8160 00:59:52.709902 ==
8161 00:59:52.711311 Dram Type= 6, Freq= 0, CH_1, rank 0
8162 00:59:52.714975 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8163 00:59:52.715538 ==
8164 00:59:52.716039
8165 00:59:52.716398
8166 00:59:52.718138 TX Vref Scan disable
8167 00:59:52.721387 == TX Byte 0 ==
8168 00:59:52.726129 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8169 00:59:52.728308 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8170 00:59:52.731323 == TX Byte 1 ==
8171 00:59:52.734355 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8172 00:59:52.738199 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8173 00:59:52.738759 ==
8174 00:59:52.741285 Dram Type= 6, Freq= 0, CH_1, rank 0
8175 00:59:52.744511 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8176 00:59:52.747691 ==
8177 00:59:52.758639
8178 00:59:52.761978 TX Vref early break, caculate TX vref
8179 00:59:52.765105 TX Vref=16, minBit 3, minWin=21, winSum=367
8180 00:59:52.768410 TX Vref=18, minBit 0, minWin=22, winSum=378
8181 00:59:52.771773 TX Vref=20, minBit 3, minWin=22, winSum=389
8182 00:59:52.775621 TX Vref=22, minBit 0, minWin=23, winSum=396
8183 00:59:52.778443 TX Vref=24, minBit 0, minWin=24, winSum=404
8184 00:59:52.785082 TX Vref=26, minBit 3, minWin=24, winSum=410
8185 00:59:52.788215 TX Vref=28, minBit 3, minWin=24, winSum=413
8186 00:59:52.791991 TX Vref=30, minBit 3, minWin=24, winSum=406
8187 00:59:52.794760 TX Vref=32, minBit 3, minWin=23, winSum=398
8188 00:59:52.798870 TX Vref=34, minBit 0, minWin=23, winSum=389
8189 00:59:52.804938 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 28
8190 00:59:52.805492
8191 00:59:52.807960 Final TX Range 0 Vref 28
8192 00:59:52.808513
8193 00:59:52.808923 ==
8194 00:59:52.811522 Dram Type= 6, Freq= 0, CH_1, rank 0
8195 00:59:52.815008 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8196 00:59:52.815568 ==
8197 00:59:52.815933
8198 00:59:52.816269
8199 00:59:52.817905 TX Vref Scan disable
8200 00:59:52.824407 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8201 00:59:52.824991 == TX Byte 0 ==
8202 00:59:52.828688 u2DelayCellOfst[0]=14 cells (4 PI)
8203 00:59:52.830856 u2DelayCellOfst[1]=11 cells (3 PI)
8204 00:59:52.834512 u2DelayCellOfst[2]=0 cells (0 PI)
8205 00:59:52.837887 u2DelayCellOfst[3]=7 cells (2 PI)
8206 00:59:52.841132 u2DelayCellOfst[4]=7 cells (2 PI)
8207 00:59:52.845645 u2DelayCellOfst[5]=14 cells (4 PI)
8208 00:59:52.847881 u2DelayCellOfst[6]=14 cells (4 PI)
8209 00:59:52.851548 u2DelayCellOfst[7]=3 cells (1 PI)
8210 00:59:52.854051 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8211 00:59:52.858374 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8212 00:59:52.861185 == TX Byte 1 ==
8213 00:59:52.864093 u2DelayCellOfst[8]=0 cells (0 PI)
8214 00:59:52.864759 u2DelayCellOfst[9]=3 cells (1 PI)
8215 00:59:52.867639 u2DelayCellOfst[10]=11 cells (3 PI)
8216 00:59:52.870478 u2DelayCellOfst[11]=3 cells (1 PI)
8217 00:59:52.874221 u2DelayCellOfst[12]=14 cells (4 PI)
8218 00:59:52.877452 u2DelayCellOfst[13]=22 cells (6 PI)
8219 00:59:52.880625 u2DelayCellOfst[14]=18 cells (5 PI)
8220 00:59:52.884004 u2DelayCellOfst[15]=18 cells (5 PI)
8221 00:59:52.887160 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8222 00:59:52.894182 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8223 00:59:52.894744 DramC Write-DBI on
8224 00:59:52.895109 ==
8225 00:59:52.897688 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 00:59:52.903656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8227 00:59:52.904218 ==
8228 00:59:52.904586
8229 00:59:52.904991
8230 00:59:52.905319 TX Vref Scan disable
8231 00:59:52.907730 == TX Byte 0 ==
8232 00:59:52.911091 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8233 00:59:52.914991 == TX Byte 1 ==
8234 00:59:52.918256 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8235 00:59:52.920902 DramC Write-DBI off
8236 00:59:52.921481
8237 00:59:52.921852 [DATLAT]
8238 00:59:52.922194 Freq=1600, CH1 RK0
8239 00:59:52.922528
8240 00:59:52.924195 DATLAT Default: 0xf
8241 00:59:52.924651 0, 0xFFFF, sum = 0
8242 00:59:52.927604 1, 0xFFFF, sum = 0
8243 00:59:52.928175 2, 0xFFFF, sum = 0
8244 00:59:52.930898 3, 0xFFFF, sum = 0
8245 00:59:52.934222 4, 0xFFFF, sum = 0
8246 00:59:52.934784 5, 0xFFFF, sum = 0
8247 00:59:52.938124 6, 0xFFFF, sum = 0
8248 00:59:52.938691 7, 0xFFFF, sum = 0
8249 00:59:52.940688 8, 0xFFFF, sum = 0
8250 00:59:52.941197 9, 0xFFFF, sum = 0
8251 00:59:52.944144 10, 0xFFFF, sum = 0
8252 00:59:52.944754 11, 0xFFFF, sum = 0
8253 00:59:52.947476 12, 0xF7F, sum = 0
8254 00:59:52.948039 13, 0x0, sum = 1
8255 00:59:52.950957 14, 0x0, sum = 2
8256 00:59:52.951520 15, 0x0, sum = 3
8257 00:59:52.953951 16, 0x0, sum = 4
8258 00:59:52.954413 best_step = 14
8259 00:59:52.954772
8260 00:59:52.955105 ==
8261 00:59:52.957289 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 00:59:52.960929 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 00:59:52.963838 ==
8264 00:59:52.964415 RX Vref Scan: 1
8265 00:59:52.964840
8266 00:59:52.967884 Set Vref Range= 24 -> 127
8267 00:59:52.968339
8268 00:59:52.970572 RX Vref 24 -> 127, step: 1
8269 00:59:52.971030
8270 00:59:52.971432 RX Delay 3 -> 252, step: 4
8271 00:59:52.971789
8272 00:59:52.973463 Set Vref, RX VrefLevel [Byte0]: 24
8273 00:59:52.977501 [Byte1]: 24
8274 00:59:52.980968
8275 00:59:52.981516 Set Vref, RX VrefLevel [Byte0]: 25
8276 00:59:52.984176 [Byte1]: 25
8277 00:59:52.989091
8278 00:59:52.989645 Set Vref, RX VrefLevel [Byte0]: 26
8279 00:59:52.992217 [Byte1]: 26
8280 00:59:52.996599
8281 00:59:52.997207 Set Vref, RX VrefLevel [Byte0]: 27
8282 00:59:52.999668 [Byte1]: 27
8283 00:59:53.003836
8284 00:59:53.004392 Set Vref, RX VrefLevel [Byte0]: 28
8285 00:59:53.007059 [Byte1]: 28
8286 00:59:53.011918
8287 00:59:53.012477 Set Vref, RX VrefLevel [Byte0]: 29
8288 00:59:53.014342 [Byte1]: 29
8289 00:59:53.019594
8290 00:59:53.020151 Set Vref, RX VrefLevel [Byte0]: 30
8291 00:59:53.022599 [Byte1]: 30
8292 00:59:53.027652
8293 00:59:53.028135 Set Vref, RX VrefLevel [Byte0]: 31
8294 00:59:53.029757 [Byte1]: 31
8295 00:59:53.033977
8296 00:59:53.034476 Set Vref, RX VrefLevel [Byte0]: 32
8297 00:59:53.038146 [Byte1]: 32
8298 00:59:53.042291
8299 00:59:53.042702 Set Vref, RX VrefLevel [Byte0]: 33
8300 00:59:53.045057 [Byte1]: 33
8301 00:59:53.049595
8302 00:59:53.050120 Set Vref, RX VrefLevel [Byte0]: 34
8303 00:59:53.053198 [Byte1]: 34
8304 00:59:53.057314
8305 00:59:53.057827 Set Vref, RX VrefLevel [Byte0]: 35
8306 00:59:53.060639 [Byte1]: 35
8307 00:59:53.065268
8308 00:59:53.065937 Set Vref, RX VrefLevel [Byte0]: 36
8309 00:59:53.068872 [Byte1]: 36
8310 00:59:53.073091
8311 00:59:53.073600 Set Vref, RX VrefLevel [Byte0]: 37
8312 00:59:53.076490 [Byte1]: 37
8313 00:59:53.079897
8314 00:59:53.080307 Set Vref, RX VrefLevel [Byte0]: 38
8315 00:59:53.083530 [Byte1]: 38
8316 00:59:53.088142
8317 00:59:53.088690 Set Vref, RX VrefLevel [Byte0]: 39
8318 00:59:53.090984 [Byte1]: 39
8319 00:59:53.095702
8320 00:59:53.096218 Set Vref, RX VrefLevel [Byte0]: 40
8321 00:59:53.098877 [Byte1]: 40
8322 00:59:53.103152
8323 00:59:53.103660 Set Vref, RX VrefLevel [Byte0]: 41
8324 00:59:53.107394 [Byte1]: 41
8325 00:59:53.112396
8326 00:59:53.112931 Set Vref, RX VrefLevel [Byte0]: 42
8327 00:59:53.114297 [Byte1]: 42
8328 00:59:53.119143
8329 00:59:53.119650 Set Vref, RX VrefLevel [Byte0]: 43
8330 00:59:53.122206 [Byte1]: 43
8331 00:59:53.127006
8332 00:59:53.127570 Set Vref, RX VrefLevel [Byte0]: 44
8333 00:59:53.129610 [Byte1]: 44
8334 00:59:53.134048
8335 00:59:53.134497 Set Vref, RX VrefLevel [Byte0]: 45
8336 00:59:53.138296 [Byte1]: 45
8337 00:59:53.141563
8338 00:59:53.142034 Set Vref, RX VrefLevel [Byte0]: 46
8339 00:59:53.144919 [Byte1]: 46
8340 00:59:53.149930
8341 00:59:53.150640 Set Vref, RX VrefLevel [Byte0]: 47
8342 00:59:53.152058 [Byte1]: 47
8343 00:59:53.156863
8344 00:59:53.160106 Set Vref, RX VrefLevel [Byte0]: 48
8345 00:59:53.163792 [Byte1]: 48
8346 00:59:53.164347
8347 00:59:53.166273 Set Vref, RX VrefLevel [Byte0]: 49
8348 00:59:53.169954 [Byte1]: 49
8349 00:59:53.170500
8350 00:59:53.173747 Set Vref, RX VrefLevel [Byte0]: 50
8351 00:59:53.176278 [Byte1]: 50
8352 00:59:53.180376
8353 00:59:53.180979 Set Vref, RX VrefLevel [Byte0]: 51
8354 00:59:53.183980 [Byte1]: 51
8355 00:59:53.187846
8356 00:59:53.188393 Set Vref, RX VrefLevel [Byte0]: 52
8357 00:59:53.190854 [Byte1]: 52
8358 00:59:53.194868
8359 00:59:53.195456 Set Vref, RX VrefLevel [Byte0]: 53
8360 00:59:53.198546 [Byte1]: 53
8361 00:59:53.202657
8362 00:59:53.203170 Set Vref, RX VrefLevel [Byte0]: 54
8363 00:59:53.206054 [Byte1]: 54
8364 00:59:53.210690
8365 00:59:53.211251 Set Vref, RX VrefLevel [Byte0]: 55
8366 00:59:53.213664 [Byte1]: 55
8367 00:59:53.217862
8368 00:59:53.218312 Set Vref, RX VrefLevel [Byte0]: 56
8369 00:59:53.221189 [Byte1]: 56
8370 00:59:53.226429
8371 00:59:53.226896 Set Vref, RX VrefLevel [Byte0]: 57
8372 00:59:53.229312 [Byte1]: 57
8373 00:59:53.233095
8374 00:59:53.233547 Set Vref, RX VrefLevel [Byte0]: 58
8375 00:59:53.236308 [Byte1]: 58
8376 00:59:53.242070
8377 00:59:53.242581 Set Vref, RX VrefLevel [Byte0]: 59
8378 00:59:53.244215 [Byte1]: 59
8379 00:59:53.249693
8380 00:59:53.250202 Set Vref, RX VrefLevel [Byte0]: 60
8381 00:59:53.252365 [Byte1]: 60
8382 00:59:53.256403
8383 00:59:53.256982 Set Vref, RX VrefLevel [Byte0]: 61
8384 00:59:53.259582 [Byte1]: 61
8385 00:59:53.264087
8386 00:59:53.264596 Set Vref, RX VrefLevel [Byte0]: 62
8387 00:59:53.267145 [Byte1]: 62
8388 00:59:53.272104
8389 00:59:53.272614 Set Vref, RX VrefLevel [Byte0]: 63
8390 00:59:53.274919 [Byte1]: 63
8391 00:59:53.279388
8392 00:59:53.279907 Set Vref, RX VrefLevel [Byte0]: 64
8393 00:59:53.282840 [Byte1]: 64
8394 00:59:53.286880
8395 00:59:53.287305 Set Vref, RX VrefLevel [Byte0]: 65
8396 00:59:53.290136 [Byte1]: 65
8397 00:59:53.294939
8398 00:59:53.295448 Set Vref, RX VrefLevel [Byte0]: 66
8399 00:59:53.297653 [Byte1]: 66
8400 00:59:53.302860
8401 00:59:53.303268 Set Vref, RX VrefLevel [Byte0]: 67
8402 00:59:53.305440 [Byte1]: 67
8403 00:59:53.309785
8404 00:59:53.310311 Set Vref, RX VrefLevel [Byte0]: 68
8405 00:59:53.313398 [Byte1]: 68
8406 00:59:53.318215
8407 00:59:53.318630 Set Vref, RX VrefLevel [Byte0]: 69
8408 00:59:53.320876 [Byte1]: 69
8409 00:59:53.325424
8410 00:59:53.325954 Set Vref, RX VrefLevel [Byte0]: 70
8411 00:59:53.328939 [Byte1]: 70
8412 00:59:53.332805
8413 00:59:53.333329 Set Vref, RX VrefLevel [Byte0]: 71
8414 00:59:53.336579 [Byte1]: 71
8415 00:59:53.341046
8416 00:59:53.341615 Final RX Vref Byte 0 = 60 to rank0
8417 00:59:53.344609 Final RX Vref Byte 1 = 57 to rank0
8418 00:59:53.348305 Final RX Vref Byte 0 = 60 to rank1
8419 00:59:53.351635 Final RX Vref Byte 1 = 57 to rank1==
8420 00:59:53.353479 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 00:59:53.360806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8422 00:59:53.361394 ==
8423 00:59:53.361889 DQS Delay:
8424 00:59:53.363920 DQS0 = 0, DQS1 = 0
8425 00:59:53.364506 DQM Delay:
8426 00:59:53.365051 DQM0 = 128, DQM1 = 122
8427 00:59:53.366590 DQ Delay:
8428 00:59:53.370704 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
8429 00:59:53.373480 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =124
8430 00:59:53.376823 DQ8 =106, DQ9 =112, DQ10 =126, DQ11 =110
8431 00:59:53.380192 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132
8432 00:59:53.380670
8433 00:59:53.381199
8434 00:59:53.381661
8435 00:59:53.383474 [DramC_TX_OE_Calibration] TA2
8436 00:59:53.386502 Original DQ_B0 (3 6) =30, OEN = 27
8437 00:59:53.389577 Original DQ_B1 (3 6) =30, OEN = 27
8438 00:59:53.393184 24, 0x0, End_B0=24 End_B1=24
8439 00:59:53.393762 25, 0x0, End_B0=25 End_B1=25
8440 00:59:53.396247 26, 0x0, End_B0=26 End_B1=26
8441 00:59:53.399513 27, 0x0, End_B0=27 End_B1=27
8442 00:59:53.402941 28, 0x0, End_B0=28 End_B1=28
8443 00:59:53.406352 29, 0x0, End_B0=29 End_B1=29
8444 00:59:53.406818 30, 0x0, End_B0=30 End_B1=30
8445 00:59:53.410489 31, 0x4545, End_B0=30 End_B1=30
8446 00:59:53.413131 Byte0 end_step=30 best_step=27
8447 00:59:53.416077 Byte1 end_step=30 best_step=27
8448 00:59:53.420262 Byte0 TX OE(2T, 0.5T) = (3, 3)
8449 00:59:53.423587 Byte1 TX OE(2T, 0.5T) = (3, 3)
8450 00:59:53.424223
8451 00:59:53.424602
8452 00:59:53.429521 [DQSOSCAuto] RK0, (LSB)MR18= 0x2929, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8453 00:59:53.433405 CH1 RK0: MR19=303, MR18=2929
8454 00:59:53.439576 CH1_RK0: MR19=0x303, MR18=0x2929, DQSOSC=389, MR23=63, INC=24, DEC=16
8455 00:59:53.440151
8456 00:59:53.442701 ----->DramcWriteLeveling(PI) begin...
8457 00:59:53.443275 ==
8458 00:59:53.446618 Dram Type= 6, Freq= 0, CH_1, rank 1
8459 00:59:53.450257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8460 00:59:53.450826 ==
8461 00:59:53.453316 Write leveling (Byte 0): 20 => 20
8462 00:59:53.456422 Write leveling (Byte 1): 19 => 19
8463 00:59:53.459390 DramcWriteLeveling(PI) end<-----
8464 00:59:53.459962
8465 00:59:53.460332 ==
8466 00:59:53.462732 Dram Type= 6, Freq= 0, CH_1, rank 1
8467 00:59:53.465671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8468 00:59:53.469299 ==
8469 00:59:53.469768 [Gating] SW mode calibration
8470 00:59:53.478623 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8471 00:59:53.482353 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8472 00:59:53.485602 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 00:59:53.492876 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 00:59:53.495393 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 00:59:53.498421 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 00:59:53.505560 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 00:59:53.508868 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8478 00:59:53.512438 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8479 00:59:53.518612 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8480 00:59:53.522013 0 13 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
8481 00:59:53.525093 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 00:59:53.531980 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 00:59:53.535704 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 00:59:53.538599 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 00:59:53.545673 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 00:59:53.548308 0 13 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8487 00:59:53.551821 0 13 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8488 00:59:53.558610 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 00:59:53.561632 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 00:59:53.565674 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 00:59:53.571620 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 00:59:53.575240 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 00:59:53.577799 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8494 00:59:53.585013 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8495 00:59:53.588102 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8496 00:59:53.592139 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8497 00:59:53.598142 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 00:59:53.601055 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 00:59:53.604260 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 00:59:53.611744 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 00:59:53.615019 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 00:59:53.617965 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 00:59:53.624284 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 00:59:53.627760 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 00:59:53.631445 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 00:59:53.638073 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 00:59:53.640968 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 00:59:53.644625 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 00:59:53.650970 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 00:59:53.654960 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8511 00:59:53.657976 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8512 00:59:53.661587 Total UI for P1: 0, mck2ui 16
8513 00:59:53.664113 best dqsien dly found for B0: ( 1, 0, 24)
8514 00:59:53.671485 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8515 00:59:53.674506 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8516 00:59:53.677616 Total UI for P1: 0, mck2ui 16
8517 00:59:53.680998 best dqsien dly found for B1: ( 1, 0, 30)
8518 00:59:53.684033 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8519 00:59:53.687212 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8520 00:59:53.687770
8521 00:59:53.690903 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8522 00:59:53.693925 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8523 00:59:53.697703 [Gating] SW calibration Done
8524 00:59:53.698262 ==
8525 00:59:53.700860 Dram Type= 6, Freq= 0, CH_1, rank 1
8526 00:59:53.703996 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8527 00:59:53.704476 ==
8528 00:59:53.707512 RX Vref Scan: 0
8529 00:59:53.708067
8530 00:59:53.710719 RX Vref 0 -> 0, step: 1
8531 00:59:53.711280
8532 00:59:53.711644 RX Delay 0 -> 252, step: 8
8533 00:59:53.716911 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8534 00:59:53.720290 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8535 00:59:53.723690 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8536 00:59:53.727087 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8537 00:59:53.730604 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8538 00:59:53.736887 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8539 00:59:53.740878 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8540 00:59:53.743482 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8541 00:59:53.747530 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8542 00:59:53.749869 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8543 00:59:53.756669 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8544 00:59:53.760270 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8545 00:59:53.763742 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8546 00:59:53.766753 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8547 00:59:53.773218 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8548 00:59:53.777826 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8549 00:59:53.778397 ==
8550 00:59:53.780264 Dram Type= 6, Freq= 0, CH_1, rank 1
8551 00:59:53.783314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8552 00:59:53.783873 ==
8553 00:59:53.786104 DQS Delay:
8554 00:59:53.786564 DQS0 = 0, DQS1 = 0
8555 00:59:53.787022 DQM Delay:
8556 00:59:53.789791 DQM0 = 131, DQM1 = 124
8557 00:59:53.790350 DQ Delay:
8558 00:59:53.793147 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8559 00:59:53.796447 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8560 00:59:53.799482 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8561 00:59:53.806449 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8562 00:59:53.807014
8563 00:59:53.807386
8564 00:59:53.807724 ==
8565 00:59:53.810097 Dram Type= 6, Freq= 0, CH_1, rank 1
8566 00:59:53.813392 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8567 00:59:53.813859 ==
8568 00:59:53.814227
8569 00:59:53.814568
8570 00:59:53.816512 TX Vref Scan disable
8571 00:59:53.817024 == TX Byte 0 ==
8572 00:59:53.823471 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8573 00:59:53.827067 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8574 00:59:53.827638 == TX Byte 1 ==
8575 00:59:53.833122 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8576 00:59:53.836947 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8577 00:59:53.837507 ==
8578 00:59:53.839009 Dram Type= 6, Freq= 0, CH_1, rank 1
8579 00:59:53.843417 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8580 00:59:53.843984 ==
8581 00:59:53.857407
8582 00:59:53.861518 TX Vref early break, caculate TX vref
8583 00:59:53.863801 TX Vref=16, minBit 2, minWin=23, winSum=388
8584 00:59:53.867339 TX Vref=18, minBit 1, minWin=23, winSum=389
8585 00:59:53.870469 TX Vref=20, minBit 0, minWin=24, winSum=402
8586 00:59:53.874165 TX Vref=22, minBit 3, minWin=24, winSum=408
8587 00:59:53.877209 TX Vref=24, minBit 3, minWin=24, winSum=416
8588 00:59:53.883669 TX Vref=26, minBit 1, minWin=25, winSum=425
8589 00:59:53.887232 TX Vref=28, minBit 0, minWin=26, winSum=426
8590 00:59:53.890469 TX Vref=30, minBit 0, minWin=25, winSum=419
8591 00:59:53.894671 TX Vref=32, minBit 0, minWin=25, winSum=418
8592 00:59:53.897664 TX Vref=34, minBit 0, minWin=24, winSum=408
8593 00:59:53.900113 TX Vref=36, minBit 0, minWin=24, winSum=400
8594 00:59:53.907008 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8595 00:59:53.907571
8596 00:59:53.910263 Final TX Range 0 Vref 28
8597 00:59:53.910726
8598 00:59:53.911089 ==
8599 00:59:53.913647 Dram Type= 6, Freq= 0, CH_1, rank 1
8600 00:59:53.917339 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8601 00:59:53.917926 ==
8602 00:59:53.918294
8603 00:59:53.919918
8604 00:59:53.920377 TX Vref Scan disable
8605 00:59:53.926967 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =266/100 ps
8606 00:59:53.927522 == TX Byte 0 ==
8607 00:59:53.930183 u2DelayCellOfst[0]=18 cells (5 PI)
8608 00:59:53.933812 u2DelayCellOfst[1]=11 cells (3 PI)
8609 00:59:53.936969 u2DelayCellOfst[2]=0 cells (0 PI)
8610 00:59:53.940527 u2DelayCellOfst[3]=7 cells (2 PI)
8611 00:59:53.943859 u2DelayCellOfst[4]=7 cells (2 PI)
8612 00:59:53.948226 u2DelayCellOfst[5]=14 cells (4 PI)
8613 00:59:53.950397 u2DelayCellOfst[6]=14 cells (4 PI)
8614 00:59:53.953189 u2DelayCellOfst[7]=3 cells (1 PI)
8615 00:59:53.957034 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8616 00:59:53.959920 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8617 00:59:53.963288 == TX Byte 1 ==
8618 00:59:53.966336 u2DelayCellOfst[8]=0 cells (0 PI)
8619 00:59:53.970234 u2DelayCellOfst[9]=7 cells (2 PI)
8620 00:59:53.973985 u2DelayCellOfst[10]=7 cells (2 PI)
8621 00:59:53.974547 u2DelayCellOfst[11]=3 cells (1 PI)
8622 00:59:53.976402 u2DelayCellOfst[12]=14 cells (4 PI)
8623 00:59:53.979707 u2DelayCellOfst[13]=18 cells (5 PI)
8624 00:59:53.982678 u2DelayCellOfst[14]=18 cells (5 PI)
8625 00:59:53.986415 u2DelayCellOfst[15]=18 cells (5 PI)
8626 00:59:53.992774 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8627 00:59:53.995927 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8628 00:59:53.996393 DramC Write-DBI on
8629 00:59:53.999652 ==
8630 00:59:54.000215 Dram Type= 6, Freq= 0, CH_1, rank 1
8631 00:59:54.007794 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8632 00:59:54.008397 ==
8633 00:59:54.008818
8634 00:59:54.009168
8635 00:59:54.009859 TX Vref Scan disable
8636 00:59:54.010235 == TX Byte 0 ==
8637 00:59:54.016089 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8638 00:59:54.016557 == TX Byte 1 ==
8639 00:59:54.019321 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8640 00:59:54.022586 DramC Write-DBI off
8641 00:59:54.023150
8642 00:59:54.023517 [DATLAT]
8643 00:59:54.025677 Freq=1600, CH1 RK1
8644 00:59:54.026137
8645 00:59:54.026503 DATLAT Default: 0xe
8646 00:59:54.029789 0, 0xFFFF, sum = 0
8647 00:59:54.030259 1, 0xFFFF, sum = 0
8648 00:59:54.032106 2, 0xFFFF, sum = 0
8649 00:59:54.032575 3, 0xFFFF, sum = 0
8650 00:59:54.035779 4, 0xFFFF, sum = 0
8651 00:59:54.036353 5, 0xFFFF, sum = 0
8652 00:59:54.039329 6, 0xFFFF, sum = 0
8653 00:59:54.039905 7, 0xFFFF, sum = 0
8654 00:59:54.042061 8, 0xFFFF, sum = 0
8655 00:59:54.042530 9, 0xFFFF, sum = 0
8656 00:59:54.045481 10, 0xFFFF, sum = 0
8657 00:59:54.048861 11, 0xFFFF, sum = 0
8658 00:59:54.049438 12, 0xFFF, sum = 0
8659 00:59:54.052558 13, 0x0, sum = 1
8660 00:59:54.053179 14, 0x0, sum = 2
8661 00:59:54.055606 15, 0x0, sum = 3
8662 00:59:54.056175 16, 0x0, sum = 4
8663 00:59:54.056552 best_step = 14
8664 00:59:54.056940
8665 00:59:54.059086 ==
8666 00:59:54.062363 Dram Type= 6, Freq= 0, CH_1, rank 1
8667 00:59:54.066061 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8668 00:59:54.066630 ==
8669 00:59:54.066996 RX Vref Scan: 0
8670 00:59:54.067334
8671 00:59:54.069103 RX Vref 0 -> 0, step: 1
8672 00:59:54.069567
8673 00:59:54.072379 RX Delay 3 -> 252, step: 4
8674 00:59:54.075768 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8675 00:59:54.078912 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8676 00:59:54.084995 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8677 00:59:54.088598 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8678 00:59:54.091553 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8679 00:59:54.095172 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8680 00:59:54.098224 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8681 00:59:54.105626 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8682 00:59:54.108631 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8683 00:59:54.113308 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8684 00:59:54.115673 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8685 00:59:54.118303 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8686 00:59:54.125156 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8687 00:59:54.128605 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8688 00:59:54.131580 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8689 00:59:54.135021 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8690 00:59:54.138297 ==
8691 00:59:54.138861 Dram Type= 6, Freq= 0, CH_1, rank 1
8692 00:59:54.144334 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8693 00:59:54.144841 ==
8694 00:59:54.145219 DQS Delay:
8695 00:59:54.148501 DQS0 = 0, DQS1 = 0
8696 00:59:54.149007 DQM Delay:
8697 00:59:54.151272 DQM0 = 127, DQM1 = 122
8698 00:59:54.151734 DQ Delay:
8699 00:59:54.155868 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =124
8700 00:59:54.157915 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8701 00:59:54.161439 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8702 00:59:54.164816 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8703 00:59:54.165250
8704 00:59:54.165608
8705 00:59:54.165946
8706 00:59:54.168209 [DramC_TX_OE_Calibration] TA2
8707 00:59:54.171871 Original DQ_B0 (3 6) =30, OEN = 27
8708 00:59:54.174698 Original DQ_B1 (3 6) =30, OEN = 27
8709 00:59:54.178204 24, 0x0, End_B0=24 End_B1=24
8710 00:59:54.181107 25, 0x0, End_B0=25 End_B1=25
8711 00:59:54.181723 26, 0x0, End_B0=26 End_B1=26
8712 00:59:54.184335 27, 0x0, End_B0=27 End_B1=27
8713 00:59:54.187672 28, 0x0, End_B0=28 End_B1=28
8714 00:59:54.191421 29, 0x0, End_B0=29 End_B1=29
8715 00:59:54.191896 30, 0x0, End_B0=30 End_B1=30
8716 00:59:54.194335 31, 0x4141, End_B0=30 End_B1=30
8717 00:59:54.197673 Byte0 end_step=30 best_step=27
8718 00:59:54.200810 Byte1 end_step=30 best_step=27
8719 00:59:54.205573 Byte0 TX OE(2T, 0.5T) = (3, 3)
8720 00:59:54.208054 Byte1 TX OE(2T, 0.5T) = (3, 3)
8721 00:59:54.208520
8722 00:59:54.208928
8723 00:59:54.214342 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8724 00:59:54.218287 CH1 RK1: MR19=303, MR18=1F1F
8725 00:59:54.225548 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8726 00:59:54.227460 [RxdqsGatingPostProcess] freq 1600
8727 00:59:54.234393 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8728 00:59:54.234965 Pre-setting of DQS Precalculation
8729 00:59:54.241349 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8730 00:59:54.247559 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8731 00:59:54.255139 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8732 00:59:54.255715
8733 00:59:54.256084
8734 00:59:54.258022 [Calibration Summary] 3200 Mbps
8735 00:59:54.260938 CH 0, Rank 0
8736 00:59:54.261501 SW Impedance : PASS
8737 00:59:54.264240 DUTY Scan : NO K
8738 00:59:54.267863 ZQ Calibration : PASS
8739 00:59:54.268478 Jitter Meter : NO K
8740 00:59:54.270618 CBT Training : PASS
8741 00:59:54.274203 Write leveling : PASS
8742 00:59:54.274763 RX DQS gating : PASS
8743 00:59:54.277587 RX DQ/DQS(RDDQC) : PASS
8744 00:59:54.280519 TX DQ/DQS : PASS
8745 00:59:54.281146 RX DATLAT : PASS
8746 00:59:54.283735 RX DQ/DQS(Engine): PASS
8747 00:59:54.284289 TX OE : PASS
8748 00:59:54.287172 All Pass.
8749 00:59:54.287672
8750 00:59:54.288038 CH 0, Rank 1
8751 00:59:54.290611 SW Impedance : PASS
8752 00:59:54.293767 DUTY Scan : NO K
8753 00:59:54.294227 ZQ Calibration : PASS
8754 00:59:54.296574 Jitter Meter : NO K
8755 00:59:54.297140 CBT Training : PASS
8756 00:59:54.300000 Write leveling : PASS
8757 00:59:54.303050 RX DQS gating : PASS
8758 00:59:54.303704 RX DQ/DQS(RDDQC) : PASS
8759 00:59:54.306708 TX DQ/DQS : PASS
8760 00:59:54.310210 RX DATLAT : PASS
8761 00:59:54.310752 RX DQ/DQS(Engine): PASS
8762 00:59:54.313040 TX OE : PASS
8763 00:59:54.313499 All Pass.
8764 00:59:54.313859
8765 00:59:54.316636 CH 1, Rank 0
8766 00:59:54.317353 SW Impedance : PASS
8767 00:59:54.320211 DUTY Scan : NO K
8768 00:59:54.323455 ZQ Calibration : PASS
8769 00:59:54.324018 Jitter Meter : NO K
8770 00:59:54.326920 CBT Training : PASS
8771 00:59:54.329683 Write leveling : PASS
8772 00:59:54.330141 RX DQS gating : PASS
8773 00:59:54.333240 RX DQ/DQS(RDDQC) : PASS
8774 00:59:54.336557 TX DQ/DQS : PASS
8775 00:59:54.337177 RX DATLAT : PASS
8776 00:59:54.339625 RX DQ/DQS(Engine): PASS
8777 00:59:54.343810 TX OE : PASS
8778 00:59:54.344268 All Pass.
8779 00:59:54.344628
8780 00:59:54.345040 CH 1, Rank 1
8781 00:59:54.346859 SW Impedance : PASS
8782 00:59:54.349679 DUTY Scan : NO K
8783 00:59:54.350138 ZQ Calibration : PASS
8784 00:59:54.352871 Jitter Meter : NO K
8785 00:59:54.356431 CBT Training : PASS
8786 00:59:54.357058 Write leveling : PASS
8787 00:59:54.359183 RX DQS gating : PASS
8788 00:59:54.363054 RX DQ/DQS(RDDQC) : PASS
8789 00:59:54.363734 TX DQ/DQS : PASS
8790 00:59:54.366094 RX DATLAT : PASS
8791 00:59:54.366657 RX DQ/DQS(Engine): PASS
8792 00:59:54.369636 TX OE : PASS
8793 00:59:54.370146 All Pass.
8794 00:59:54.370508
8795 00:59:54.372608 DramC Write-DBI on
8796 00:59:54.376764 PER_BANK_REFRESH: Hybrid Mode
8797 00:59:54.377223 TX_TRACKING: ON
8798 00:59:54.385919 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8799 00:59:54.393416 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8800 00:59:54.399499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8801 00:59:54.406432 [FAST_K] Save calibration result to emmc
8802 00:59:54.407066 sync common calibartion params.
8803 00:59:54.409322 sync cbt_mode0:0, 1:0
8804 00:59:54.412433 dram_init: ddr_geometry: 0
8805 00:59:54.415913 dram_init: ddr_geometry: 0
8806 00:59:54.416466 dram_init: ddr_geometry: 0
8807 00:59:54.419150 0:dram_rank_size:80000000
8808 00:59:54.422820 1:dram_rank_size:80000000
8809 00:59:54.425941 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8810 00:59:54.429060 DFS_SHUFFLE_HW_MODE: ON
8811 00:59:54.432926 dramc_set_vcore_voltage set vcore to 725000
8812 00:59:54.436042 Read voltage for 1600, 0
8813 00:59:54.436609 Vio18 = 0
8814 00:59:54.437037 Vcore = 725000
8815 00:59:54.439331 Vdram = 0
8816 00:59:54.439899 Vddq = 0
8817 00:59:54.440270 Vmddr = 0
8818 00:59:54.443269 switch to 3200 Mbps bootup
8819 00:59:54.445908 [DramcRunTimeConfig]
8820 00:59:54.446375 PHYPLL
8821 00:59:54.446742 DPM_CONTROL_AFTERK: ON
8822 00:59:54.449184 PER_BANK_REFRESH: ON
8823 00:59:54.452220 REFRESH_OVERHEAD_REDUCTION: ON
8824 00:59:54.452832 CMD_PICG_NEW_MODE: OFF
8825 00:59:54.456383 XRTWTW_NEW_MODE: ON
8826 00:59:54.458498 XRTRTR_NEW_MODE: ON
8827 00:59:54.458966 TX_TRACKING: ON
8828 00:59:54.462751 RDSEL_TRACKING: OFF
8829 00:59:54.463321 DQS Precalculation for DVFS: ON
8830 00:59:54.466295 RX_TRACKING: OFF
8831 00:59:54.466761 HW_GATING DBG: ON
8832 00:59:54.468545 ZQCS_ENABLE_LP4: ON
8833 00:59:54.472427 RX_PICG_NEW_MODE: ON
8834 00:59:54.473046 TX_PICG_NEW_MODE: ON
8835 00:59:54.475047 ENABLE_RX_DCM_DPHY: ON
8836 00:59:54.479032 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8837 00:59:54.479601 DUMMY_READ_FOR_TRACKING: OFF
8838 00:59:54.481705 !!! SPM_CONTROL_AFTERK: OFF
8839 00:59:54.484888 !!! SPM could not control APHY
8840 00:59:54.488515 IMPEDANCE_TRACKING: ON
8841 00:59:54.489132 TEMP_SENSOR: ON
8842 00:59:54.492278 HW_SAVE_FOR_SR: OFF
8843 00:59:54.494921 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8844 00:59:54.499034 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8845 00:59:54.499609 Read ODT Tracking: ON
8846 00:59:54.501651 Refresh Rate DeBounce: ON
8847 00:59:54.505568 DFS_NO_QUEUE_FLUSH: ON
8848 00:59:54.508765 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8849 00:59:54.509341 ENABLE_DFS_RUNTIME_MRW: OFF
8850 00:59:54.512429 DDR_RESERVE_NEW_MODE: ON
8851 00:59:54.515249 MR_CBT_SWITCH_FREQ: ON
8852 00:59:54.515810 =========================
8853 00:59:54.536364 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8854 00:59:54.538513 dram_init: ddr_geometry: 0
8855 00:59:54.556953 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8856 00:59:54.559439 dram_init: dram init end (result: 0)
8857 00:59:54.566774 DRAM-K: Full calibration passed in 23408 msecs
8858 00:59:54.570009 MRC: failed to locate region type 0.
8859 00:59:54.570569 DRAM rank0 size:0x80000000,
8860 00:59:54.572970 DRAM rank1 size=0x80000000
8861 00:59:54.583311 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8862 00:59:54.589197 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8863 00:59:54.596850 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8864 00:59:54.602549 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8865 00:59:54.605447 DRAM rank0 size:0x80000000,
8866 00:59:54.609201 DRAM rank1 size=0x80000000
8867 00:59:54.609761 CBMEM:
8868 00:59:54.612372 IMD: root @ 0xfffff000 254 entries.
8869 00:59:54.616225 IMD: root @ 0xffffec00 62 entries.
8870 00:59:54.618716 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8871 00:59:54.622516 WARNING: RO_VPD is uninitialized or empty.
8872 00:59:54.628985 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8873 00:59:54.636442 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8874 00:59:54.649010 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8875 00:59:54.660003 BS: romstage times (exec / console): total (unknown) / 22953 ms
8876 00:59:54.660568
8877 00:59:54.661011
8878 00:59:54.670575 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8879 00:59:54.673801 ARM64: Exception handlers installed.
8880 00:59:54.676698 ARM64: Testing exception
8881 00:59:54.677300 ARM64: Done test exception
8882 00:59:54.680452 Enumerating buses...
8883 00:59:54.683405 Show all devs... Before device enumeration.
8884 00:59:54.687075 Root Device: enabled 1
8885 00:59:54.690554 CPU_CLUSTER: 0: enabled 1
8886 00:59:54.691117 CPU: 00: enabled 1
8887 00:59:54.693456 Compare with tree...
8888 00:59:54.694011 Root Device: enabled 1
8889 00:59:54.697111 CPU_CLUSTER: 0: enabled 1
8890 00:59:54.700492 CPU: 00: enabled 1
8891 00:59:54.701087 Root Device scanning...
8892 00:59:54.703072 scan_static_bus for Root Device
8893 00:59:54.706576 CPU_CLUSTER: 0 enabled
8894 00:59:54.709832 scan_static_bus for Root Device done
8895 00:59:54.713167 scan_bus: bus Root Device finished in 8 msecs
8896 00:59:54.713728 done
8897 00:59:54.719746 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8898 00:59:54.722538 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8899 00:59:54.729330 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8900 00:59:54.732805 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8901 00:59:54.736289 Allocating resources...
8902 00:59:54.739250 Reading resources...
8903 00:59:54.742609 Root Device read_resources bus 0 link: 0
8904 00:59:54.743168 DRAM rank0 size:0x80000000,
8905 00:59:54.746474 DRAM rank1 size=0x80000000
8906 00:59:54.749341 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8907 00:59:54.752614 CPU: 00 missing read_resources
8908 00:59:54.756056 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8909 00:59:54.762320 Root Device read_resources bus 0 link: 0 done
8910 00:59:54.762873 Done reading resources.
8911 00:59:54.769712 Show resources in subtree (Root Device)...After reading.
8912 00:59:54.772811 Root Device child on link 0 CPU_CLUSTER: 0
8913 00:59:54.775990 CPU_CLUSTER: 0 child on link 0 CPU: 00
8914 00:59:54.786057 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8915 00:59:54.786621 CPU: 00
8916 00:59:54.789442 Root Device assign_resources, bus 0 link: 0
8917 00:59:54.792001 CPU_CLUSTER: 0 missing set_resources
8918 00:59:54.799696 Root Device assign_resources, bus 0 link: 0 done
8919 00:59:54.800260 Done setting resources.
8920 00:59:54.805694 Show resources in subtree (Root Device)...After assigning values.
8921 00:59:54.809960 Root Device child on link 0 CPU_CLUSTER: 0
8922 00:59:54.812126 CPU_CLUSTER: 0 child on link 0 CPU: 00
8923 00:59:54.822770 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8924 00:59:54.823327 CPU: 00
8925 00:59:54.826813 Done allocating resources.
8926 00:59:54.828569 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8927 00:59:54.832637 Enabling resources...
8928 00:59:54.833265 done.
8929 00:59:54.838842 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8930 00:59:54.839389 Initializing devices...
8931 00:59:54.842231 Root Device init
8932 00:59:54.842789 init hardware done!
8933 00:59:54.845035 0x00000018: ctrlr->caps
8934 00:59:54.848414 52.000 MHz: ctrlr->f_max
8935 00:59:54.848941 0.400 MHz: ctrlr->f_min
8936 00:59:54.851600 0x40ff8080: ctrlr->voltages
8937 00:59:54.855361 sclk: 390625
8938 00:59:54.855919 Bus Width = 1
8939 00:59:54.856287 sclk: 390625
8940 00:59:54.858491 Bus Width = 1
8941 00:59:54.859051 Early init status = 3
8942 00:59:54.865084 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8943 00:59:54.868534 in-header: 03 fc 00 00 01 00 00 00
8944 00:59:54.871435 in-data: 00
8945 00:59:54.874821 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8946 00:59:54.878791 in-header: 03 fd 00 00 00 00 00 00
8947 00:59:54.882136 in-data:
8948 00:59:54.885324 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8949 00:59:54.889005 in-header: 03 fc 00 00 01 00 00 00
8950 00:59:54.892038 in-data: 00
8951 00:59:54.895382 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8952 00:59:54.900171 in-header: 03 fd 00 00 00 00 00 00
8953 00:59:54.903357 in-data:
8954 00:59:54.906427 [SSUSB] Setting up USB HOST controller...
8955 00:59:54.910672 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8956 00:59:54.913437 [SSUSB] phy power-on done.
8957 00:59:54.917574 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8958 00:59:54.923245 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8959 00:59:54.926850 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8960 00:59:54.932987 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8961 00:59:54.940033 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8962 00:59:54.947368 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8963 00:59:54.952999 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8964 00:59:54.959405 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8965 00:59:54.962957 SPM: binary array size = 0x9dc
8966 00:59:54.966166 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8967 00:59:54.972690 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8968 00:59:54.979515 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8969 00:59:54.986278 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8970 00:59:54.989066 configure_display: Starting display init
8971 00:59:55.023827 anx7625_power_on_init: Init interface.
8972 00:59:55.027071 anx7625_disable_pd_protocol: Disabled PD feature.
8973 00:59:55.029557 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8974 00:59:55.057759 anx7625_start_dp_work: Secure OCM version=00
8975 00:59:55.061725 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8976 00:59:55.076187 sp_tx_get_edid_block: EDID Block = 1
8977 00:59:55.178355 Extracted contents:
8978 00:59:55.182090 header: 00 ff ff ff ff ff ff 00
8979 00:59:55.185596 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8980 00:59:55.188279 version: 01 04
8981 00:59:55.191616 basic params: 95 1f 11 78 0a
8982 00:59:55.194903 chroma info: 76 90 94 55 54 90 27 21 50 54
8983 00:59:55.197695 established: 00 00 00
8984 00:59:55.204633 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8985 00:59:55.211275 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8986 00:59:55.214147 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8987 00:59:55.220926 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8988 00:59:55.227699 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8989 00:59:55.231635 extensions: 00
8990 00:59:55.232192 checksum: fb
8991 00:59:55.232562
8992 00:59:55.237888 Manufacturer: IVO Model 57d Serial Number 0
8993 00:59:55.238448 Made week 0 of 2020
8994 00:59:55.241348 EDID version: 1.4
8995 00:59:55.241811 Digital display
8996 00:59:55.244513 6 bits per primary color channel
8997 00:59:55.247906 DisplayPort interface
8998 00:59:55.248462 Maximum image size: 31 cm x 17 cm
8999 00:59:55.250430 Gamma: 220%
9000 00:59:55.250987 Check DPMS levels
9001 00:59:55.257256 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9002 00:59:55.260124 First detailed timing is preferred timing
9003 00:59:55.264057 Established timings supported:
9004 00:59:55.264628 Standard timings supported:
9005 00:59:55.266727 Detailed timings
9006 00:59:55.270530 Hex of detail: 383680a07038204018303c0035ae10000019
9007 00:59:55.277206 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9008 00:59:55.280374 0780 0798 07c8 0820 hborder 0
9009 00:59:55.283825 0438 043b 0447 0458 vborder 0
9010 00:59:55.287532 -hsync -vsync
9011 00:59:55.288093 Did detailed timing
9012 00:59:55.293603 Hex of detail: 000000000000000000000000000000000000
9013 00:59:55.297553 Manufacturer-specified data, tag 0
9014 00:59:55.300178 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9015 00:59:55.303501 ASCII string: InfoVision
9016 00:59:55.307485 Hex of detail: 000000fe00523134304e574635205248200a
9017 00:59:55.310373 ASCII string: R140NWF5 RH
9018 00:59:55.310946 Checksum
9019 00:59:55.313340 Checksum: 0xfb (valid)
9020 00:59:55.316861 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9021 00:59:55.320092 DSI data_rate: 832800000 bps
9022 00:59:55.326223 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9023 00:59:55.330220 anx7625_parse_edid: pixelclock(138800).
9024 00:59:55.332896 hactive(1920), hsync(48), hfp(24), hbp(88)
9025 00:59:55.336428 vactive(1080), vsync(12), vfp(3), vbp(17)
9026 00:59:55.339978 anx7625_dsi_config: config dsi.
9027 00:59:55.346661 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9028 00:59:55.361134 anx7625_dsi_config: success to config DSI
9029 00:59:55.364464 anx7625_dp_start: MIPI phy setup OK.
9030 00:59:55.367414 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9031 00:59:55.370043 mtk_ddp_mode_set invalid vrefresh 60
9032 00:59:55.373348 main_disp_path_setup
9033 00:59:55.373806 ovl_layer_smi_id_en
9034 00:59:55.377164 ovl_layer_smi_id_en
9035 00:59:55.377721 ccorr_config
9036 00:59:55.378082 aal_config
9037 00:59:55.379742 gamma_config
9038 00:59:55.380246 postmask_config
9039 00:59:55.383328 dither_config
9040 00:59:55.387198 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9041 00:59:55.393541 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9042 00:59:55.396943 Root Device init finished in 551 msecs
9043 00:59:55.399797 CPU_CLUSTER: 0 init
9044 00:59:55.406640 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9045 00:59:55.413629 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9046 00:59:55.414189 APU_MBOX 0x190000b0 = 0x10001
9047 00:59:55.416080 APU_MBOX 0x190001b0 = 0x10001
9048 00:59:55.419565 APU_MBOX 0x190005b0 = 0x10001
9049 00:59:55.423146 APU_MBOX 0x190006b0 = 0x10001
9050 00:59:55.429339 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9051 00:59:55.439464 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9052 00:59:55.451483 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9053 00:59:55.458491 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9054 00:59:55.470183 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9055 00:59:55.479009 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9056 00:59:55.482254 CPU_CLUSTER: 0 init finished in 81 msecs
9057 00:59:55.485562 Devices initialized
9058 00:59:55.489071 Show all devs... After init.
9059 00:59:55.489650 Root Device: enabled 1
9060 00:59:55.492543 CPU_CLUSTER: 0: enabled 1
9061 00:59:55.495471 CPU: 00: enabled 1
9062 00:59:55.498859 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9063 00:59:55.501866 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9064 00:59:55.505398 ELOG: NV offset 0x57f000 size 0x1000
9065 00:59:55.512220 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9066 00:59:55.518919 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9067 00:59:55.522204 ELOG: Event(17) added with size 13 at 2024-01-19 00:59:55 UTC
9068 00:59:55.525010 out: cmd=0x121: 03 db 21 01 00 00 00 00
9069 00:59:55.529115 in-header: 03 0d 00 00 2c 00 00 00
9070 00:59:55.543392 in-data: 56 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9071 00:59:55.548985 ELOG: Event(A1) added with size 10 at 2024-01-19 00:59:55 UTC
9072 00:59:55.556553 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9073 00:59:55.562278 ELOG: Event(A0) added with size 9 at 2024-01-19 00:59:55 UTC
9074 00:59:55.565435 elog_add_boot_reason: Logged dev mode boot
9075 00:59:55.569406 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9076 00:59:55.571957 Finalize devices...
9077 00:59:55.572564 Devices finalized
9078 00:59:55.580102 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9079 00:59:55.582118 Writing coreboot table at 0xffe64000
9080 00:59:55.585801 0. 000000000010a000-0000000000113fff: RAMSTAGE
9081 00:59:55.589149 1. 0000000040000000-00000000400fffff: RAM
9082 00:59:55.596122 2. 0000000040100000-000000004032afff: RAMSTAGE
9083 00:59:55.598856 3. 000000004032b000-00000000545fffff: RAM
9084 00:59:55.602043 4. 0000000054600000-000000005465ffff: BL31
9085 00:59:55.605829 5. 0000000054660000-00000000ffe63fff: RAM
9086 00:59:55.612152 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9087 00:59:55.615206 7. 0000000100000000-000000013fffffff: RAM
9088 00:59:55.618662 Passing 5 GPIOs to payload:
9089 00:59:55.622178 NAME | PORT | POLARITY | VALUE
9090 00:59:55.625055 EC in RW | 0x000000aa | low | undefined
9091 00:59:55.632030 EC interrupt | 0x00000005 | low | undefined
9092 00:59:55.635555 TPM interrupt | 0x000000ab | high | undefined
9093 00:59:55.641463 SD card detect | 0x00000011 | high | undefined
9094 00:59:55.644841 speaker enable | 0x00000093 | high | undefined
9095 00:59:55.648938 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9096 00:59:55.652163 in-header: 03 f8 00 00 02 00 00 00
9097 00:59:55.654962 in-data: 03 00
9098 00:59:55.655526 ADC[4]: Raw value=669695 ID=5
9099 00:59:55.659052 ADC[3]: Raw value=212180 ID=1
9100 00:59:55.661997 RAM Code: 0x51
9101 00:59:55.662562 ADC[6]: Raw value=74410 ID=0
9102 00:59:55.664904 ADC[5]: Raw value=211444 ID=1
9103 00:59:55.668038 SKU Code: 0x1
9104 00:59:55.671652 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2791
9105 00:59:55.674647 coreboot table: 964 bytes.
9106 00:59:55.678736 IMD ROOT 0. 0xfffff000 0x00001000
9107 00:59:55.682137 IMD SMALL 1. 0xffffe000 0x00001000
9108 00:59:55.685103 RO MCACHE 2. 0xffffc000 0x00001104
9109 00:59:55.689044 CONSOLE 3. 0xfff7c000 0x00080000
9110 00:59:55.692241 FMAP 4. 0xfff7b000 0x00000452
9111 00:59:55.694730 TIME STAMP 5. 0xfff7a000 0x00000910
9112 00:59:55.698014 VBOOT WORK 6. 0xfff66000 0x00014000
9113 00:59:55.701472 RAMOOPS 7. 0xffe66000 0x00100000
9114 00:59:55.705308 COREBOOT 8. 0xffe64000 0x00002000
9115 00:59:55.705773 IMD small region:
9116 00:59:55.711260 IMD ROOT 0. 0xffffec00 0x00000400
9117 00:59:55.715263 VPD 1. 0xffffeb80 0x0000006c
9118 00:59:55.718126 MMC STATUS 2. 0xffffeb60 0x00000004
9119 00:59:55.721909 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9120 00:59:55.724601 Probing TPM: done!
9121 00:59:55.728282 Connected to device vid:did:rid of 1ae0:0028:00
9122 00:59:55.737915 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9123 00:59:55.741517 Initialized TPM device CR50 revision 0
9124 00:59:55.744701 Checking cr50 for pending updates
9125 00:59:55.748324 Reading cr50 TPM mode
9126 00:59:55.757459 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9127 00:59:55.764439 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9128 00:59:55.803970 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9129 00:59:55.807896 Checking segment from ROM address 0x40100000
9130 00:59:55.810883 Checking segment from ROM address 0x4010001c
9131 00:59:55.817613 Loading segment from ROM address 0x40100000
9132 00:59:55.818182 code (compression=0)
9133 00:59:55.827403 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9134 00:59:55.833867 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9135 00:59:55.834443 it's not compressed!
9136 00:59:55.840887 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9137 00:59:55.843743 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9138 00:59:55.864518 Loading segment from ROM address 0x4010001c
9139 00:59:55.865154 Entry Point 0x80000000
9140 00:59:55.868347 Loaded segments
9141 00:59:55.871259 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9142 00:59:55.877847 Jumping to boot code at 0x80000000(0xffe64000)
9143 00:59:55.884432 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9144 00:59:55.890824 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9145 00:59:55.899509 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9146 00:59:55.902278 Checking segment from ROM address 0x40100000
9147 00:59:55.906467 Checking segment from ROM address 0x4010001c
9148 00:59:55.912844 Loading segment from ROM address 0x40100000
9149 00:59:55.913415 code (compression=1)
9150 00:59:55.919029 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9151 00:59:55.928697 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9152 00:59:55.929287 using LZMA
9153 00:59:55.938243 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9154 00:59:55.943982 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9155 00:59:55.947240 Loading segment from ROM address 0x4010001c
9156 00:59:55.947806 Entry Point 0x54601000
9157 00:59:55.950593 Loaded segments
9158 00:59:55.953557 NOTICE: MT8192 bl31_setup
9159 00:59:55.960800 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9160 00:59:55.964074 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9161 00:59:55.967235 WARNING: region 0:
9162 00:59:55.970358 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9163 00:59:55.970828 WARNING: region 1:
9164 00:59:55.977648 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9165 00:59:55.981394 WARNING: region 2:
9166 00:59:55.984023 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9167 00:59:55.987574 WARNING: region 3:
9168 00:59:55.991041 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9169 00:59:55.993876 WARNING: region 4:
9170 00:59:56.000990 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9171 00:59:56.001566 WARNING: region 5:
9172 00:59:56.003863 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9173 00:59:56.007393 WARNING: region 6:
9174 00:59:56.011201 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9175 00:59:56.014490 WARNING: region 7:
9176 00:59:56.017343 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9177 00:59:56.023838 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9178 00:59:56.027317 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9179 00:59:56.030739 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9180 00:59:56.037462 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9181 00:59:56.040522 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9182 00:59:56.043903 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9183 00:59:56.051025 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9184 00:59:56.054257 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9185 00:59:56.060330 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9186 00:59:56.064359 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9187 00:59:56.067305 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9188 00:59:56.073954 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9189 00:59:56.076732 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9190 00:59:56.081439 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9191 00:59:56.087054 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9192 00:59:56.090761 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9193 00:59:56.097436 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9194 00:59:56.100325 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9195 00:59:56.103677 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9196 00:59:56.111227 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9197 00:59:56.113786 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9198 00:59:56.117269 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9199 00:59:56.123509 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9200 00:59:56.127518 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9201 00:59:56.133496 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9202 00:59:56.136787 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9203 00:59:56.140271 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9204 00:59:56.147671 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9205 00:59:56.150555 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9206 00:59:56.157664 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9207 00:59:56.160112 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9208 00:59:56.164074 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9209 00:59:56.170495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9210 00:59:56.174078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9211 00:59:56.177451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9212 00:59:56.180133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9213 00:59:56.186970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9214 00:59:56.190388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9215 00:59:56.193219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9216 00:59:56.197401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9217 00:59:56.203604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9218 00:59:56.206490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9219 00:59:56.210462 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9220 00:59:56.213616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9221 00:59:56.219953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9222 00:59:56.223615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9223 00:59:56.226752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9224 00:59:56.234135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9225 00:59:56.236936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9226 00:59:56.240918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9227 00:59:56.246675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9228 00:59:56.249562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9229 00:59:56.257673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9230 00:59:56.260358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9231 00:59:56.266492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9232 00:59:56.269459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9233 00:59:56.273381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9234 00:59:56.279776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9235 00:59:56.283594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9236 00:59:56.289631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9237 00:59:56.294093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9238 00:59:56.300254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9239 00:59:56.303675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9240 00:59:56.306526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9241 00:59:56.313675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9242 00:59:56.317066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9243 00:59:56.323524 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9244 00:59:56.326285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9245 00:59:56.333631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9246 00:59:56.337416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9247 00:59:56.339882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9248 00:59:56.346702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9249 00:59:56.349987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9250 00:59:56.357129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9251 00:59:56.359832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9252 00:59:56.367120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9253 00:59:56.370869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9254 00:59:56.373954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9255 00:59:56.380448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9256 00:59:56.384468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9257 00:59:56.390795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9258 00:59:56.393031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9259 00:59:56.400018 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9260 00:59:56.403643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9261 00:59:56.407105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9262 00:59:56.413225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9263 00:59:56.416694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9264 00:59:56.423549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9265 00:59:56.426963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9266 00:59:56.433482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9267 00:59:56.436845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9268 00:59:56.443268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9269 00:59:56.446502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9270 00:59:56.449994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9271 00:59:56.456942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9272 00:59:56.460258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9273 00:59:56.466532 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9274 00:59:56.470199 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9275 00:59:56.473591 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9276 00:59:56.476865 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9277 00:59:56.480947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9278 00:59:56.487390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9279 00:59:56.489992 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9280 00:59:56.496442 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9281 00:59:56.499929 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9282 00:59:56.503405 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9283 00:59:56.509947 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9284 00:59:56.513987 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9285 00:59:56.520249 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9286 00:59:56.523243 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9287 00:59:56.526682 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9288 00:59:56.532999 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9289 00:59:56.536313 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9290 00:59:56.544007 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9291 00:59:56.547024 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9292 00:59:56.549577 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9293 00:59:56.556814 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9294 00:59:56.559411 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9295 00:59:56.563256 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9296 00:59:56.570100 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9297 00:59:56.573950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9298 00:59:56.575891 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9299 00:59:56.580232 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9300 00:59:56.586528 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9301 00:59:56.589454 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9302 00:59:56.592611 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9303 00:59:56.599819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9304 00:59:56.602554 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9305 00:59:56.609658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9306 00:59:56.613086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9307 00:59:56.616276 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9308 00:59:56.622638 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9309 00:59:56.626257 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9310 00:59:56.629665 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9311 00:59:56.636106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9312 00:59:56.639483 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9313 00:59:56.646338 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9314 00:59:56.649697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9315 00:59:56.653405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9316 00:59:56.659770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9317 00:59:56.664008 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9318 00:59:56.670588 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9319 00:59:56.673876 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9320 00:59:56.676373 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9321 00:59:56.683404 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9322 00:59:56.686539 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9323 00:59:56.689901 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9324 00:59:56.696542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9325 00:59:56.699893 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9326 00:59:56.706726 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9327 00:59:56.710115 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9328 00:59:56.713010 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9329 00:59:56.719876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9330 00:59:56.723181 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9331 00:59:56.729906 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9332 00:59:56.733435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9333 00:59:56.737232 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9334 00:59:56.743358 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9335 00:59:56.746316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9336 00:59:56.750378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9337 00:59:56.757650 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9338 00:59:56.759815 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9339 00:59:56.766755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9340 00:59:56.769989 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9341 00:59:56.773397 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9342 00:59:56.779866 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9343 00:59:56.782914 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9344 00:59:56.789346 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9345 00:59:56.793247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9346 00:59:56.796591 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9347 00:59:56.803315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9348 00:59:56.806567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9349 00:59:56.812552 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9350 00:59:56.816400 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9351 00:59:56.819280 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9352 00:59:56.825995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9353 00:59:56.829131 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9354 00:59:56.835475 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9355 00:59:56.840190 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9356 00:59:56.842316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9357 00:59:56.848878 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9358 00:59:56.853087 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9359 00:59:56.859233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9360 00:59:56.862429 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9361 00:59:56.866308 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9362 00:59:56.872344 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9363 00:59:56.875226 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9364 00:59:56.882820 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9365 00:59:56.885896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9366 00:59:56.889395 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9367 00:59:56.895097 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9368 00:59:56.899342 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9369 00:59:56.905152 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9370 00:59:56.908831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9371 00:59:56.912231 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9372 00:59:56.918767 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9373 00:59:56.921963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9374 00:59:56.928582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9375 00:59:56.931569 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9376 00:59:56.938239 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9377 00:59:56.941677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9378 00:59:56.945444 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9379 00:59:56.952541 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9380 00:59:56.955606 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9381 00:59:56.961668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9382 00:59:56.965443 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9383 00:59:56.971497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9384 00:59:56.974890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9385 00:59:56.978176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9386 00:59:56.984819 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9387 00:59:56.988597 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9388 00:59:56.994366 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9389 00:59:56.998673 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9390 00:59:57.004956 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9391 00:59:57.008103 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9392 00:59:57.011079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9393 00:59:57.017566 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9394 00:59:57.021567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9395 00:59:57.028274 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9396 00:59:57.031530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9397 00:59:57.037458 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9398 00:59:57.040569 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9399 00:59:57.043911 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9400 00:59:57.050159 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9401 00:59:57.054023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9402 00:59:57.060598 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9403 00:59:57.063921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9404 00:59:57.070452 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9405 00:59:57.074064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9406 00:59:57.076825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9407 00:59:57.080435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9408 00:59:57.086850 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9409 00:59:57.090683 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9410 00:59:57.094214 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9411 00:59:57.096916 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9412 00:59:57.102818 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9413 00:59:57.107072 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9414 00:59:57.113199 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9415 00:59:57.118278 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9416 00:59:57.120243 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9417 00:59:57.126777 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9418 00:59:57.129833 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9419 00:59:57.133399 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9420 00:59:57.140289 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9421 00:59:57.144057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9422 00:59:57.150019 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9423 00:59:57.153052 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9424 00:59:57.157049 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9425 00:59:57.162702 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9426 00:59:57.166401 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9427 00:59:57.169463 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9428 00:59:57.176129 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9429 00:59:57.179554 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9430 00:59:57.183823 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9431 00:59:57.189649 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9432 00:59:57.192443 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9433 00:59:57.198911 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9434 00:59:57.203462 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9435 00:59:57.205633 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9436 00:59:57.213123 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9437 00:59:57.215783 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9438 00:59:57.222164 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9439 00:59:57.225289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9440 00:59:57.228958 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9441 00:59:57.235711 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9442 00:59:57.238743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9443 00:59:57.242120 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9444 00:59:57.249116 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9445 00:59:57.252265 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9446 00:59:57.256007 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9447 00:59:57.259203 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9448 00:59:57.265483 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9449 00:59:57.269270 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9450 00:59:57.272005 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9451 00:59:57.275640 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9452 00:59:57.282125 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9453 00:59:57.285023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9454 00:59:57.288094 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9455 00:59:57.291640 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9456 00:59:57.297947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9457 00:59:57.302270 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9458 00:59:57.305263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9459 00:59:57.311316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9460 00:59:57.315082 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9461 00:59:57.321996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9462 00:59:57.325256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9463 00:59:57.331317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9464 00:59:57.335369 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9465 00:59:57.337987 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9466 00:59:57.344376 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9467 00:59:57.348064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9468 00:59:57.354431 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9469 00:59:57.357334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9470 00:59:57.362039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9471 00:59:57.368061 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9472 00:59:57.371393 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9473 00:59:57.377846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9474 00:59:57.381032 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9475 00:59:57.384066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9476 00:59:57.390365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9477 00:59:57.393725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9478 00:59:57.400556 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9479 00:59:57.404477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9480 00:59:57.410687 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9481 00:59:57.413970 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9482 00:59:57.417249 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9483 00:59:57.425312 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9484 00:59:57.426894 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9485 00:59:57.434032 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9486 00:59:57.437074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9487 00:59:57.440047 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9488 00:59:57.447495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9489 00:59:57.451295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9490 00:59:57.456853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9491 00:59:57.459980 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9492 00:59:57.464017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9493 00:59:57.471383 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9494 00:59:57.473134 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9495 00:59:57.480149 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9496 00:59:57.483293 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9497 00:59:57.489727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9498 00:59:57.493167 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9499 00:59:57.496962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9500 00:59:57.503138 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9501 00:59:57.507363 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9502 00:59:57.513280 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9503 00:59:57.516893 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9504 00:59:57.523050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9505 00:59:57.526226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9506 00:59:57.530094 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9507 00:59:57.536253 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9508 00:59:57.539427 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9509 00:59:57.546303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9510 00:59:57.549128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9511 00:59:57.552638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9512 00:59:57.559239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9513 00:59:57.562413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9514 00:59:57.569223 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9515 00:59:57.572954 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9516 00:59:57.576278 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9517 00:59:57.583587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9518 00:59:57.585815 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9519 00:59:57.593560 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9520 00:59:57.595620 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9521 00:59:57.602757 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9522 00:59:57.605772 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9523 00:59:57.609324 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9524 00:59:57.616339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9525 00:59:57.619228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9526 00:59:57.625291 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9527 00:59:57.628971 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9528 00:59:57.631785 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9529 00:59:57.639162 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9530 00:59:57.641837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9531 00:59:57.648322 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9532 00:59:57.651615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9533 00:59:57.658046 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9534 00:59:57.661054 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9535 00:59:57.664562 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9536 00:59:57.671777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9537 00:59:57.674732 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9538 00:59:57.681433 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9539 00:59:57.684721 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9540 00:59:57.691421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9541 00:59:57.694505 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9542 00:59:57.701045 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9543 00:59:57.704531 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9544 00:59:57.707724 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9545 00:59:57.714410 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9546 00:59:57.717592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9547 00:59:57.725398 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9548 00:59:57.728195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9549 00:59:57.734955 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9550 00:59:57.737665 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9551 00:59:57.740891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9552 00:59:57.747841 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9553 00:59:57.750780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9554 00:59:57.757594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9555 00:59:57.761547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9556 00:59:57.767500 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9557 00:59:57.770743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9558 00:59:57.777456 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9559 00:59:57.780850 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9560 00:59:57.788270 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9561 00:59:57.790622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9562 00:59:57.794158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9563 00:59:57.800853 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9564 00:59:57.804230 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9565 00:59:57.810224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9566 00:59:57.813623 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9567 00:59:57.820827 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9568 00:59:57.824349 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9569 00:59:57.827604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9570 00:59:57.834058 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9571 00:59:57.836868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9572 00:59:57.843984 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9573 00:59:57.847124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9574 00:59:57.853815 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9575 00:59:57.857142 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9576 00:59:57.864554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9577 00:59:57.866862 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9578 00:59:57.870302 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9579 00:59:57.876993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9580 00:59:57.880860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9581 00:59:57.886596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9582 00:59:57.889735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9583 00:59:57.896336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9584 00:59:57.899454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9585 00:59:57.906275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9586 00:59:57.909553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9587 00:59:57.912912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9588 00:59:57.919602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9589 00:59:57.923299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9590 00:59:57.929779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9591 00:59:57.932938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9592 00:59:57.939848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9593 00:59:57.942182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9594 00:59:57.949812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9595 00:59:57.952535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9596 00:59:57.959696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9597 00:59:57.962908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9598 00:59:57.968918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9599 00:59:57.972536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9600 00:59:57.979045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9601 00:59:57.982543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9602 00:59:57.990057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9603 00:59:57.992098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9604 00:59:57.999054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9605 00:59:58.002013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9606 00:59:58.009044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9607 00:59:58.012037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9608 00:59:58.019106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9609 00:59:58.022235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9610 00:59:58.028878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9611 00:59:58.032137 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9612 00:59:58.035492 INFO: [APUAPC] vio 0
9613 00:59:58.038916 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9614 00:59:58.045974 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9615 00:59:58.048638 INFO: [APUAPC] D0_APC_0: 0x400510
9616 00:59:58.052104 INFO: [APUAPC] D0_APC_1: 0x0
9617 00:59:58.055151 INFO: [APUAPC] D0_APC_2: 0x1540
9618 00:59:58.055726 INFO: [APUAPC] D0_APC_3: 0x0
9619 00:59:58.058525 INFO: [APUAPC] D1_APC_0: 0xffffffff
9620 00:59:58.065111 INFO: [APUAPC] D1_APC_1: 0xffffffff
9621 00:59:58.068380 INFO: [APUAPC] D1_APC_2: 0x3fffff
9622 00:59:58.069015 INFO: [APUAPC] D1_APC_3: 0x0
9623 00:59:58.071396 INFO: [APUAPC] D2_APC_0: 0xffffffff
9624 00:59:58.074810 INFO: [APUAPC] D2_APC_1: 0xffffffff
9625 00:59:58.079114 INFO: [APUAPC] D2_APC_2: 0x3fffff
9626 00:59:58.082413 INFO: [APUAPC] D2_APC_3: 0x0
9627 00:59:58.085120 INFO: [APUAPC] D3_APC_0: 0xffffffff
9628 00:59:58.088366 INFO: [APUAPC] D3_APC_1: 0xffffffff
9629 00:59:58.091030 INFO: [APUAPC] D3_APC_2: 0x3fffff
9630 00:59:58.094316 INFO: [APUAPC] D3_APC_3: 0x0
9631 00:59:58.097708 INFO: [APUAPC] D4_APC_0: 0xffffffff
9632 00:59:58.101311 INFO: [APUAPC] D4_APC_1: 0xffffffff
9633 00:59:58.104832 INFO: [APUAPC] D4_APC_2: 0x3fffff
9634 00:59:58.108901 INFO: [APUAPC] D4_APC_3: 0x0
9635 00:59:58.112059 INFO: [APUAPC] D5_APC_0: 0xffffffff
9636 00:59:58.115017 INFO: [APUAPC] D5_APC_1: 0xffffffff
9637 00:59:58.117574 INFO: [APUAPC] D5_APC_2: 0x3fffff
9638 00:59:58.121910 INFO: [APUAPC] D5_APC_3: 0x0
9639 00:59:58.125027 INFO: [APUAPC] D6_APC_0: 0xffffffff
9640 00:59:58.127855 INFO: [APUAPC] D6_APC_1: 0xffffffff
9641 00:59:58.130843 INFO: [APUAPC] D6_APC_2: 0x3fffff
9642 00:59:58.134713 INFO: [APUAPC] D6_APC_3: 0x0
9643 00:59:58.139312 INFO: [APUAPC] D7_APC_0: 0xffffffff
9644 00:59:58.141932 INFO: [APUAPC] D7_APC_1: 0xffffffff
9645 00:59:58.144225 INFO: [APUAPC] D7_APC_2: 0x3fffff
9646 00:59:58.148569 INFO: [APUAPC] D7_APC_3: 0x0
9647 00:59:58.151572 INFO: [APUAPC] D8_APC_0: 0xffffffff
9648 00:59:58.155573 INFO: [APUAPC] D8_APC_1: 0xffffffff
9649 00:59:58.157476 INFO: [APUAPC] D8_APC_2: 0x3fffff
9650 00:59:58.161354 INFO: [APUAPC] D8_APC_3: 0x0
9651 00:59:58.164634 INFO: [APUAPC] D9_APC_0: 0xffffffff
9652 00:59:58.167276 INFO: [APUAPC] D9_APC_1: 0xffffffff
9653 00:59:58.170927 INFO: [APUAPC] D9_APC_2: 0x3fffff
9654 00:59:58.174338 INFO: [APUAPC] D9_APC_3: 0x0
9655 00:59:58.177826 INFO: [APUAPC] D10_APC_0: 0xffffffff
9656 00:59:58.180830 INFO: [APUAPC] D10_APC_1: 0xffffffff
9657 00:59:58.184499 INFO: [APUAPC] D10_APC_2: 0x3fffff
9658 00:59:58.187146 INFO: [APUAPC] D10_APC_3: 0x0
9659 00:59:58.190484 INFO: [APUAPC] D11_APC_0: 0xffffffff
9660 00:59:58.194939 INFO: [APUAPC] D11_APC_1: 0xffffffff
9661 00:59:58.197400 INFO: [APUAPC] D11_APC_2: 0x3fffff
9662 00:59:58.200241 INFO: [APUAPC] D11_APC_3: 0x0
9663 00:59:58.203911 INFO: [APUAPC] D12_APC_0: 0xffffffff
9664 00:59:58.207738 INFO: [APUAPC] D12_APC_1: 0xffffffff
9665 00:59:58.210519 INFO: [APUAPC] D12_APC_2: 0x3fffff
9666 00:59:58.214130 INFO: [APUAPC] D12_APC_3: 0x0
9667 00:59:58.217325 INFO: [APUAPC] D13_APC_0: 0xffffffff
9668 00:59:58.220255 INFO: [APUAPC] D13_APC_1: 0xffffffff
9669 00:59:58.224331 INFO: [APUAPC] D13_APC_2: 0x3fffff
9670 00:59:58.227184 INFO: [APUAPC] D13_APC_3: 0x0
9671 00:59:58.230634 INFO: [APUAPC] D14_APC_0: 0xffffffff
9672 00:59:58.234197 INFO: [APUAPC] D14_APC_1: 0xffffffff
9673 00:59:58.237217 INFO: [APUAPC] D14_APC_2: 0x3fffff
9674 00:59:58.240811 INFO: [APUAPC] D14_APC_3: 0x0
9675 00:59:58.243598 INFO: [APUAPC] D15_APC_0: 0xffffffff
9676 00:59:58.247521 INFO: [APUAPC] D15_APC_1: 0xffffffff
9677 00:59:58.250514 INFO: [APUAPC] D15_APC_2: 0x3fffff
9678 00:59:58.254594 INFO: [APUAPC] D15_APC_3: 0x0
9679 00:59:58.256639 INFO: [APUAPC] APC_CON: 0x4
9680 00:59:58.260604 INFO: [NOCDAPC] D0_APC_0: 0x0
9681 00:59:58.264124 INFO: [NOCDAPC] D0_APC_1: 0x0
9682 00:59:58.264875 INFO: [NOCDAPC] D1_APC_0: 0x0
9683 00:59:58.268293 INFO: [NOCDAPC] D1_APC_1: 0xfff
9684 00:59:58.270704 INFO: [NOCDAPC] D2_APC_0: 0x0
9685 00:59:58.273960 INFO: [NOCDAPC] D2_APC_1: 0xfff
9686 00:59:58.276929 INFO: [NOCDAPC] D3_APC_0: 0x0
9687 00:59:58.280051 INFO: [NOCDAPC] D3_APC_1: 0xfff
9688 00:59:58.283825 INFO: [NOCDAPC] D4_APC_0: 0x0
9689 00:59:58.286988 INFO: [NOCDAPC] D4_APC_1: 0xfff
9690 00:59:58.290272 INFO: [NOCDAPC] D5_APC_0: 0x0
9691 00:59:58.293721 INFO: [NOCDAPC] D5_APC_1: 0xfff
9692 00:59:58.296927 INFO: [NOCDAPC] D6_APC_0: 0x0
9693 00:59:58.297486 INFO: [NOCDAPC] D6_APC_1: 0xfff
9694 00:59:58.300470 INFO: [NOCDAPC] D7_APC_0: 0x0
9695 00:59:58.304504 INFO: [NOCDAPC] D7_APC_1: 0xfff
9696 00:59:58.307701 INFO: [NOCDAPC] D8_APC_0: 0x0
9697 00:59:58.310756 INFO: [NOCDAPC] D8_APC_1: 0xfff
9698 00:59:58.313540 INFO: [NOCDAPC] D9_APC_0: 0x0
9699 00:59:58.316827 INFO: [NOCDAPC] D9_APC_1: 0xfff
9700 00:59:58.319705 INFO: [NOCDAPC] D10_APC_0: 0x0
9701 00:59:58.323304 INFO: [NOCDAPC] D10_APC_1: 0xfff
9702 00:59:58.326907 INFO: [NOCDAPC] D11_APC_0: 0x0
9703 00:59:58.329858 INFO: [NOCDAPC] D11_APC_1: 0xfff
9704 00:59:58.333645 INFO: [NOCDAPC] D12_APC_0: 0x0
9705 00:59:58.336526 INFO: [NOCDAPC] D12_APC_1: 0xfff
9706 00:59:58.340148 INFO: [NOCDAPC] D13_APC_0: 0x0
9707 00:59:58.340702 INFO: [NOCDAPC] D13_APC_1: 0xfff
9708 00:59:58.343206 INFO: [NOCDAPC] D14_APC_0: 0x0
9709 00:59:58.346312 INFO: [NOCDAPC] D14_APC_1: 0xfff
9710 00:59:58.350383 INFO: [NOCDAPC] D15_APC_0: 0x0
9711 00:59:58.352822 INFO: [NOCDAPC] D15_APC_1: 0xfff
9712 00:59:58.356381 INFO: [NOCDAPC] APC_CON: 0x4
9713 00:59:58.359825 INFO: [APUAPC] set_apusys_apc done
9714 00:59:58.363819 INFO: [DEVAPC] devapc_init done
9715 00:59:58.366588 INFO: GICv3 without legacy support detected.
9716 00:59:58.369495 INFO: ARM GICv3 driver initialized in EL3
9717 00:59:58.376279 INFO: Maximum SPI INTID supported: 639
9718 00:59:58.379675 INFO: BL31: Initializing runtime services
9719 00:59:58.387048 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9720 00:59:58.387607 INFO: SPM: enable CPC mode
9721 00:59:58.393008 INFO: mcdi ready for mcusys-off-idle and system suspend
9722 00:59:58.396559 INFO: BL31: Preparing for EL3 exit to normal world
9723 00:59:58.403670 INFO: Entry point address = 0x80000000
9724 00:59:58.404235 INFO: SPSR = 0x8
9725 00:59:58.408433
9726 00:59:58.409064
9727 00:59:58.409553
9728 00:59:58.412284 Starting depthcharge on Spherion...
9729 00:59:58.412832
9730 00:59:58.413318 Wipe memory regions:
9731 00:59:58.413775
9732 00:59:58.416769 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9733 00:59:58.417402 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9734 00:59:58.417900 Setting prompt string to ['asurada:']
9735 00:59:58.418413 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9736 00:59:58.419338 [0x00000040000000, 0x00000054600000)
9737 00:59:58.539354
9738 00:59:58.539927 [0x00000054660000, 0x00000080000000)
9739 00:59:58.797734
9740 00:59:58.797959 [0x000000821a7280, 0x000000ffe64000)
9741 00:59:59.543279
9742 00:59:59.543857 [0x00000100000000, 0x00000140000000)
9743 00:59:59.924584
9744 00:59:59.927514 Initializing XHCI USB controller at 0x11200000.
9745 01:00:00.964956
9746 01:00:00.968862 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9747 01:00:00.969427
9748 01:00:00.969912
9749 01:00:00.970366
9750 01:00:00.971284 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9752 01:00:01.072642 asurada: tftpboot 192.168.201.1 12571112/tftp-deploy-nlza_r_g/kernel/image.itb 12571112/tftp-deploy-nlza_r_g/kernel/cmdline
9753 01:00:01.073369 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9754 01:00:01.073951 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9755 01:00:01.078971 tftpboot 192.168.201.1 12571112/tftp-deploy-nlza_r_g/kernel/image.itp-deploy-nlza_r_g/kernel/cmdline
9756 01:00:01.079555
9757 01:00:01.080109 Waiting for link
9758 01:00:01.239584
9759 01:00:01.240157 R8152: Initializing
9760 01:00:01.240651
9761 01:00:01.243076 Version 9 (ocp_data = 6010)
9762 01:00:01.243648
9763 01:00:01.245484 R8152: Done initializing
9764 01:00:01.245958
9765 01:00:01.246435 Adding net device
9766 01:00:03.253444
9767 01:00:03.254353 done.
9768 01:00:03.255041
9769 01:00:03.255569 MAC: 00:e0:4c:68:03:bd
9770 01:00:03.256033
9771 01:00:03.256754 Sending DHCP discover... done.
9772 01:00:03.257383
9773 01:00:03.259207 Waiting for reply... done.
9774 01:00:03.259665
9775 01:00:03.262768 Sending DHCP request... done.
9776 01:00:03.262922
9777 01:00:03.262992 Waiting for reply... done.
9778 01:00:03.263054
9779 01:00:03.265693 My ip is 192.168.201.16
9780 01:00:03.265893
9781 01:00:03.269346 The DHCP server ip is 192.168.201.1
9782 01:00:03.269510
9783 01:00:03.272348 TFTP server IP predefined by user: 192.168.201.1
9784 01:00:03.272519
9785 01:00:03.278999 Bootfile predefined by user: 12571112/tftp-deploy-nlza_r_g/kernel/image.itb
9786 01:00:03.279177
9787 01:00:03.282845 Sending tftp read request... done.
9788 01:00:03.283114
9789 01:00:03.285631 Waiting for the transfer...
9790 01:00:03.285819
9791 01:00:03.577370 00000000 ################################################################
9792 01:00:03.577524
9793 01:00:03.873921 00080000 ################################################################
9794 01:00:03.874061
9795 01:00:04.165769 00100000 ################################################################
9796 01:00:04.165912
9797 01:00:04.449259 00180000 ################################################################
9798 01:00:04.449405
9799 01:00:04.826068 00200000 ################################################################
9800 01:00:04.826578
9801 01:00:05.247243 00280000 ################################################################
9802 01:00:05.247772
9803 01:00:05.640570 00300000 ################################################################
9804 01:00:05.641130
9805 01:00:06.035718 00380000 ################################################################
9806 01:00:06.036281
9807 01:00:06.422085 00400000 ################################################################
9808 01:00:06.422645
9809 01:00:06.764088 00480000 ################################################################
9810 01:00:06.764229
9811 01:00:07.053809 00500000 ################################################################
9812 01:00:07.053950
9813 01:00:07.341374 00580000 ################################################################
9814 01:00:07.341515
9815 01:00:07.643811 00600000 ################################################################
9816 01:00:07.643957
9817 01:00:07.943250 00680000 ################################################################
9818 01:00:07.943390
9819 01:00:08.280835 00700000 ################################################################
9820 01:00:08.281343
9821 01:00:08.580944 00780000 ################################################################
9822 01:00:08.581090
9823 01:00:08.875346 00800000 ################################################################
9824 01:00:08.875486
9825 01:00:09.174013 00880000 ################################################################
9826 01:00:09.174155
9827 01:00:09.467246 00900000 ################################################################
9828 01:00:09.467381
9829 01:00:09.762056 00980000 ################################################################
9830 01:00:09.762198
9831 01:00:10.059181 00a00000 ################################################################
9832 01:00:10.059323
9833 01:00:10.350360 00a80000 ################################################################
9834 01:00:10.350504
9835 01:00:10.651432 00b00000 ################################################################
9836 01:00:10.651574
9837 01:00:10.946908 00b80000 ################################################################
9838 01:00:10.947053
9839 01:00:11.247295 00c00000 ################################################################
9840 01:00:11.247436
9841 01:00:11.549670 00c80000 ################################################################
9842 01:00:11.549811
9843 01:00:11.863600 00d00000 ################################################################
9844 01:00:11.864158
9845 01:00:12.257079 00d80000 ################################################################
9846 01:00:12.257598
9847 01:00:12.656578 00e00000 ################################################################
9848 01:00:12.657137
9849 01:00:13.065398 00e80000 ################################################################
9850 01:00:13.065915
9851 01:00:13.432056 00f00000 ################################################################
9852 01:00:13.432575
9853 01:00:13.809764 00f80000 ################################################################
9854 01:00:13.810321
9855 01:00:14.187833 01000000 ################################################################
9856 01:00:14.188394
9857 01:00:14.576851 01080000 ################################################################
9858 01:00:14.576997
9859 01:00:14.948197 01100000 ################################################################
9860 01:00:14.948345
9861 01:00:15.202036 01180000 ################################################################
9862 01:00:15.202176
9863 01:00:15.495308 01200000 ################################################################
9864 01:00:15.495446
9865 01:00:15.791431 01280000 ################################################################
9866 01:00:15.791572
9867 01:00:16.046110 01300000 ################################################################
9868 01:00:16.046246
9869 01:00:16.294820 01380000 ################################################################
9870 01:00:16.294950
9871 01:00:16.544947 01400000 ################################################################
9872 01:00:16.545086
9873 01:00:16.792871 01480000 ################################################################
9874 01:00:16.793004
9875 01:00:17.043321 01500000 ################################################################
9876 01:00:17.043464
9877 01:00:17.307358 01580000 ################################################################
9878 01:00:17.307500
9879 01:00:17.587480 01600000 ################################################################
9880 01:00:17.587619
9881 01:00:17.874194 01680000 ################################################################
9882 01:00:17.874331
9883 01:00:18.197993 01700000 ################################################################
9884 01:00:18.198498
9885 01:00:18.585237 01780000 ################################################################
9886 01:00:18.585781
9887 01:00:18.938930 01800000 ################################################################
9888 01:00:18.939566
9889 01:00:19.247364 01880000 ################################################################
9890 01:00:19.247536
9891 01:00:19.501840 01900000 ################################################################
9892 01:00:19.502008
9893 01:00:19.767146 01980000 ################################################################
9894 01:00:19.767285
9895 01:00:20.063511 01a00000 ################################################################
9896 01:00:20.063652
9897 01:00:20.432702 01a80000 ################################################################
9898 01:00:20.433275
9899 01:00:20.836541 01b00000 ################################################################
9900 01:00:20.837118
9901 01:00:21.244154 01b80000 ################################################################
9902 01:00:21.244777
9903 01:00:21.529358 01c00000 ################################################################
9904 01:00:21.529496
9905 01:00:21.821499 01c80000 ################################################################
9906 01:00:21.821651
9907 01:00:22.118669 01d00000 ################################################################
9908 01:00:22.118837
9909 01:00:22.404135 01d80000 ################################################################
9910 01:00:22.404277
9911 01:00:22.765353 01e00000 ################################################################
9912 01:00:22.765879
9913 01:00:23.182349 01e80000 ################################################################
9914 01:00:23.182498
9915 01:00:23.567326 01f00000 ################################################################
9916 01:00:23.567848
9917 01:00:23.948821 01f80000 ################################################################
9918 01:00:23.949385
9919 01:00:24.340106 02000000 ################################################################
9920 01:00:24.340636
9921 01:00:24.723969 02080000 ################################################################
9922 01:00:24.724525
9923 01:00:25.098021 02100000 ################################################################
9924 01:00:25.098592
9925 01:00:25.488457 02180000 ################################################################
9926 01:00:25.489059
9927 01:00:25.885433 02200000 ################################################################
9928 01:00:25.886047
9929 01:00:26.188877 02280000 ################################################################
9930 01:00:26.189023
9931 01:00:26.491970 02300000 ################################################################
9932 01:00:26.492108
9933 01:00:26.785407 02380000 ################################################################
9934 01:00:26.785550
9935 01:00:27.081069 02400000 ################################################################
9936 01:00:27.081217
9937 01:00:27.409162 02480000 ################################################################
9938 01:00:27.409691
9939 01:00:27.750480 02500000 ################################################################
9940 01:00:27.750614
9941 01:00:28.038411 02580000 ################################################################
9942 01:00:28.038558
9943 01:00:28.336614 02600000 ################################################################
9944 01:00:28.336812
9945 01:00:28.629603 02680000 ################################################################
9946 01:00:28.629740
9947 01:00:28.927351 02700000 ################################################################
9948 01:00:28.927505
9949 01:00:29.269937 02780000 ################################################################
9950 01:00:29.270087
9951 01:00:29.594712 02800000 ################################################################
9952 01:00:29.595273
9953 01:00:29.981674 02880000 ################################################################
9954 01:00:29.982323
9955 01:00:30.345057 02900000 ################################################################
9956 01:00:30.345201
9957 01:00:30.634505 02980000 ################################################################
9958 01:00:30.634655
9959 01:00:30.937414 02a00000 ################################################################
9960 01:00:30.937557
9961 01:00:31.240254 02a80000 ################################################################
9962 01:00:31.240389
9963 01:00:31.583111 02b00000 ################################################################
9964 01:00:31.583709
9965 01:00:31.907629 02b80000 ################################################################
9966 01:00:31.907774
9967 01:00:32.262827 02c00000 ################################################################
9968 01:00:32.263453
9969 01:00:32.650977 02c80000 ################################################################
9970 01:00:32.651499
9971 01:00:32.969222 02d00000 ################################################################
9972 01:00:32.969394
9973 01:00:33.269854 02d80000 ################################################################
9974 01:00:33.270001
9975 01:00:33.565727 02e00000 ################################################################
9976 01:00:33.565869
9977 01:00:33.852731 02e80000 ################################################################
9978 01:00:33.852870
9979 01:00:34.146984 02f00000 ################################################################
9980 01:00:34.147125
9981 01:00:34.440479 02f80000 ################################################################
9982 01:00:34.440615
9983 01:00:34.734841 03000000 ################################################################
9984 01:00:34.734984
9985 01:00:35.034684 03080000 ################################################################
9986 01:00:35.034822
9987 01:00:35.320000 03100000 ################################################################
9988 01:00:35.320132
9989 01:00:35.606555 03180000 ################################################################
9990 01:00:35.606691
9991 01:00:35.899377 03200000 ################################################################
9992 01:00:35.899522
9993 01:00:36.273964 03280000 ################################################################
9994 01:00:36.274479
9995 01:00:36.603667 03300000 ################################################################
9996 01:00:36.603809
9997 01:00:36.903964 03380000 ################################################################
9998 01:00:36.904107
9999 01:00:37.189655 03400000 ################################################################
10000 01:00:37.189796
10001 01:00:37.481680 03480000 ################################################################
10002 01:00:37.481821
10003 01:00:37.776333 03500000 ################################################################
10004 01:00:37.776476
10005 01:00:38.061761 03580000 ################################################################
10006 01:00:38.061903
10007 01:00:38.352187 03600000 ################################################################
10008 01:00:38.352331
10009 01:00:38.649315 03680000 ################################################################
10010 01:00:38.649452
10011 01:00:38.984786 03700000 ################################################################
10012 01:00:38.985338
10013 01:00:39.367275 03780000 ################################################################
10014 01:00:39.367413
10015 01:00:39.721778 03800000 ################################################################
10016 01:00:39.722279
10017 01:00:40.014919 03880000 ################################################ done.
10018 01:00:40.015435
10019 01:00:40.018104 The bootfile was 59630366 bytes long.
10020 01:00:40.018528
10021 01:00:40.021749 Sending tftp read request... done.
10022 01:00:40.022207
10023 01:00:40.024827 Waiting for the transfer...
10024 01:00:40.025247
10025 01:00:40.025577 00000000 # done.
10026 01:00:40.025900
10027 01:00:40.035055 Command line loaded dynamically from TFTP file: 12571112/tftp-deploy-nlza_r_g/kernel/cmdline
10028 01:00:40.035479
10029 01:00:40.048230 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10030 01:00:40.048801
10031 01:00:40.049228 Loading FIT.
10032 01:00:40.049549
10033 01:00:40.051248 Image ramdisk-1 has 47532431 bytes.
10034 01:00:40.051664
10035 01:00:40.054584 Image fdt-1 has 47278 bytes.
10036 01:00:40.055008
10037 01:00:40.058060 Image kernel-1 has 12048624 bytes.
10038 01:00:40.058480
10039 01:00:40.064916 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10040 01:00:40.068490
10041 01:00:40.085687 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10042 01:00:40.086134
10043 01:00:40.087699 Choosing best match conf-1 for compat google,spherion-rev3.
10044 01:00:40.093236
10045 01:00:40.098100 Connected to device vid:did:rid of 1ae0:0028:00
10046 01:00:40.104690
10047 01:00:40.108685 tpm_get_response: command 0x17b, return code 0x0
10048 01:00:40.109269
10049 01:00:40.111418 ec_init: CrosEC protocol v3 supported (256, 248)
10050 01:00:40.115272
10051 01:00:40.118607 tpm_cleanup: add release locality here.
10052 01:00:40.119128
10053 01:00:40.119459 Shutting down all USB controllers.
10054 01:00:40.122185
10055 01:00:40.122602 Removing current net device
10056 01:00:40.122956
10057 01:00:40.128911 Exiting depthcharge with code 4 at timestamp: 69919086
10058 01:00:40.129434
10059 01:00:40.132186 LZMA decompressing kernel-1 to 0x821a6718
10060 01:00:40.132776
10061 01:00:40.135212 LZMA decompressing kernel-1 to 0x40000000
10062 01:00:41.633020
10063 01:00:41.633598 jumping to kernel
10064 01:00:41.635980 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10065 01:00:41.636529 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10066 01:00:41.637002 Setting prompt string to ['Linux version [0-9]']
10067 01:00:41.637384 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 01:00:41.637763 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10069 01:00:41.683141
10070 01:00:41.685967 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10071 01:00:41.690630 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10072 01:00:41.691204 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10073 01:00:41.691600 Setting prompt string to []
10074 01:00:41.692026 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10075 01:00:41.692474 Using line separator: #'\n'#
10076 01:00:41.692978 No login prompt set.
10077 01:00:41.693519 Parsing kernel messages
10078 01:00:41.693860 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10079 01:00:41.694426 [login-action] Waiting for messages, (timeout 00:03:43)
10080 01:00:41.710181 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10081 01:00:41.713323 [ 0.000000] random: crng init done
10082 01:00:41.719925 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10083 01:00:41.722357 [ 0.000000] efi: UEFI not found.
10084 01:00:41.729415 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10085 01:00:41.736427 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10086 01:00:41.745810 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10087 01:00:41.755491 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10088 01:00:41.762402 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10089 01:00:41.768703 [ 0.000000] printk: bootconsole [mtk8250] enabled
10090 01:00:41.775624 [ 0.000000] NUMA: No NUMA configuration found
10091 01:00:41.782517 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10092 01:00:41.785062 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10093 01:00:41.788323 [ 0.000000] Zone ranges:
10094 01:00:41.795364 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10095 01:00:41.798059 [ 0.000000] DMA32 empty
10096 01:00:41.805388 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10097 01:00:41.809148 [ 0.000000] Movable zone start for each node
10098 01:00:41.811906 [ 0.000000] Early memory node ranges
10099 01:00:41.818589 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10100 01:00:41.825104 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10101 01:00:41.832027 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10102 01:00:41.837797 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10103 01:00:41.844962 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10104 01:00:41.850796 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10105 01:00:41.881105 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10106 01:00:41.889561 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10107 01:00:41.894508 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10108 01:00:41.897328 [ 0.000000] psci: probing for conduit method from DT.
10109 01:00:41.904835 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10110 01:00:41.907500 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10111 01:00:41.914385 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10112 01:00:41.917371 [ 0.000000] psci: SMC Calling Convention v1.2
10113 01:00:41.924182 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10114 01:00:41.927316 [ 0.000000] Detected VIPT I-cache on CPU0
10115 01:00:41.934240 [ 0.000000] CPU features: detected: GIC system register CPU interface
10116 01:00:41.940474 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10117 01:00:41.946903 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10118 01:00:41.954602 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10119 01:00:41.963599 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10120 01:00:41.970100 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10121 01:00:41.973760 [ 0.000000] alternatives: applying boot alternatives
10122 01:00:41.980253 [ 0.000000] Fallback order for Node 0: 0
10123 01:00:41.986800 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10124 01:00:41.989582 [ 0.000000] Policy zone: Normal
10125 01:00:42.003553 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10126 01:00:42.014700 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10127 01:00:42.023950 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10128 01:00:42.033551 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10129 01:00:42.040601 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10130 01:00:42.043654 <6>[ 0.000000] software IO TLB: area num 8.
10131 01:00:42.100176 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10132 01:00:42.179407 <6>[ 0.000000] Memory: 3806424K/4191232K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 352040K reserved, 32768K cma-reserved)
10133 01:00:42.186448 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10134 01:00:42.192938 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10135 01:00:42.195954 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10136 01:00:42.202606 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10137 01:00:42.209286 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10138 01:00:42.212619 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10139 01:00:42.222401 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10140 01:00:42.229382 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10141 01:00:42.235589 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10142 01:00:42.242039 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10143 01:00:42.245763 <6>[ 0.000000] GICv3: 608 SPIs implemented
10144 01:00:42.249285 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10145 01:00:42.255571 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10146 01:00:42.258529 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10147 01:00:42.265460 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10148 01:00:42.278343 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10149 01:00:42.291753 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10150 01:00:42.298313 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10151 01:00:42.306292 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10152 01:00:42.319821 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10153 01:00:42.325983 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10154 01:00:42.332792 <6>[ 0.009180] Console: colour dummy device 80x25
10155 01:00:42.342257 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10156 01:00:42.349020 <6>[ 0.024378] pid_max: default: 32768 minimum: 301
10157 01:00:42.352578 <6>[ 0.029249] LSM: Security Framework initializing
10158 01:00:42.358974 <6>[ 0.034161] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10159 01:00:42.369070 <6>[ 0.041767] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10160 01:00:42.375456 <6>[ 0.050988] cblist_init_generic: Setting adjustable number of callback queues.
10161 01:00:42.382243 <6>[ 0.058474] cblist_init_generic: Setting shift to 3 and lim to 1.
10162 01:00:42.392158 <6>[ 0.064853] cblist_init_generic: Setting adjustable number of callback queues.
10163 01:00:42.398343 <6>[ 0.072325] cblist_init_generic: Setting shift to 3 and lim to 1.
10164 01:00:42.401829 <6>[ 0.078728] rcu: Hierarchical SRCU implementation.
10165 01:00:42.408878 <6>[ 0.083744] rcu: Max phase no-delay instances is 1000.
10166 01:00:42.414973 <6>[ 0.090762] EFI services will not be available.
10167 01:00:42.419001 <6>[ 0.095741] smp: Bringing up secondary CPUs ...
10168 01:00:42.427348 <6>[ 0.100788] Detected VIPT I-cache on CPU1
10169 01:00:42.434338 <6>[ 0.100855] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10170 01:00:42.439867 <6>[ 0.100884] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10171 01:00:42.443123 <6>[ 0.101213] Detected VIPT I-cache on CPU2
10172 01:00:42.453187 <6>[ 0.101260] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10173 01:00:42.459451 <6>[ 0.101275] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10174 01:00:42.463228 <6>[ 0.101531] Detected VIPT I-cache on CPU3
10175 01:00:42.470076 <6>[ 0.101577] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10176 01:00:42.475896 <6>[ 0.101591] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10177 01:00:42.479179 <6>[ 0.101894] CPU features: detected: Spectre-v4
10178 01:00:42.485820 <6>[ 0.101901] CPU features: detected: Spectre-BHB
10179 01:00:42.489189 <6>[ 0.101905] Detected PIPT I-cache on CPU4
10180 01:00:42.495935 <6>[ 0.101963] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10181 01:00:42.502571 <6>[ 0.101978] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10182 01:00:42.510252 <6>[ 0.102266] Detected PIPT I-cache on CPU5
10183 01:00:42.515190 <6>[ 0.102329] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10184 01:00:42.522119 <6>[ 0.102346] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10185 01:00:42.525429 <6>[ 0.102622] Detected PIPT I-cache on CPU6
10186 01:00:42.532204 <6>[ 0.102682] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10187 01:00:42.538283 <6>[ 0.102698] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10188 01:00:42.544881 <6>[ 0.102997] Detected PIPT I-cache on CPU7
10189 01:00:42.552173 <6>[ 0.103062] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10190 01:00:42.558543 <6>[ 0.103078] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10191 01:00:42.562030 <6>[ 0.103125] smp: Brought up 1 node, 8 CPUs
10192 01:00:42.568281 <6>[ 0.244253] SMP: Total of 8 processors activated.
10193 01:00:42.571803 <6>[ 0.249173] CPU features: detected: 32-bit EL0 Support
10194 01:00:42.581757 <6>[ 0.254536] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10195 01:00:42.588218 <6>[ 0.263336] CPU features: detected: Common not Private translations
10196 01:00:42.595220 <6>[ 0.269812] CPU features: detected: CRC32 instructions
10197 01:00:42.601153 <6>[ 0.275164] CPU features: detected: RCpc load-acquire (LDAPR)
10198 01:00:42.604556 <6>[ 0.281123] CPU features: detected: LSE atomic instructions
10199 01:00:42.610951 <6>[ 0.286940] CPU features: detected: Privileged Access Never
10200 01:00:42.617918 <6>[ 0.292720] CPU features: detected: RAS Extension Support
10201 01:00:42.623932 <6>[ 0.298364] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10202 01:00:42.628141 <6>[ 0.305582] CPU: All CPU(s) started at EL2
10203 01:00:42.633610 <6>[ 0.309899] alternatives: applying system-wide alternatives
10204 01:00:42.643389 <6>[ 0.319809] devtmpfs: initialized
10205 01:00:42.658242 <6>[ 0.327991] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10206 01:00:42.664863 <6>[ 0.337951] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10207 01:00:42.671584 <6>[ 0.346201] pinctrl core: initialized pinctrl subsystem
10208 01:00:42.675496 <6>[ 0.352845] DMI not present or invalid.
10209 01:00:42.680971 <6>[ 0.357164] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10210 01:00:42.691955 <6>[ 0.364018] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10211 01:00:42.698188 <6>[ 0.371467] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10212 01:00:42.708615 <6>[ 0.379557] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10213 01:00:42.711431 <6>[ 0.387710] audit: initializing netlink subsys (disabled)
10214 01:00:42.721146 <5>[ 0.393403] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10215 01:00:42.727123 <6>[ 0.394091] thermal_sys: Registered thermal governor 'step_wise'
10216 01:00:42.733549 <6>[ 0.401370] thermal_sys: Registered thermal governor 'power_allocator'
10217 01:00:42.736701 <6>[ 0.407624] cpuidle: using governor menu
10218 01:00:42.743748 <6>[ 0.418580] NET: Registered PF_QIPCRTR protocol family
10219 01:00:42.751868 <6>[ 0.424038] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10220 01:00:42.754904 <6>[ 0.431141] ASID allocator initialised with 32768 entries
10221 01:00:42.761039 <6>[ 0.437679] Serial: AMBA PL011 UART driver
10222 01:00:42.770376 <4>[ 0.446395] Trying to register duplicate clock ID: 134
10223 01:00:42.824409 <6>[ 0.503670] KASLR enabled
10224 01:00:42.838023 <6>[ 0.511393] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10225 01:00:42.844881 <6>[ 0.518405] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10226 01:00:42.851622 <6>[ 0.524892] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10227 01:00:42.857714 <6>[ 0.531898] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10228 01:00:42.864313 <6>[ 0.538386] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10229 01:00:42.870847 <6>[ 0.545389] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10230 01:00:42.877266 <6>[ 0.551876] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10231 01:00:42.884394 <6>[ 0.558882] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10232 01:00:42.887239 <6>[ 0.566383] ACPI: Interpreter disabled.
10233 01:00:42.896043 <6>[ 0.572787] iommu: Default domain type: Translated
10234 01:00:42.902460 <6>[ 0.577898] iommu: DMA domain TLB invalidation policy: strict mode
10235 01:00:42.905948 <5>[ 0.584559] SCSI subsystem initialized
10236 01:00:42.913316 <6>[ 0.588719] usbcore: registered new interface driver usbfs
10237 01:00:42.919998 <6>[ 0.594448] usbcore: registered new interface driver hub
10238 01:00:42.922977 <6>[ 0.600002] usbcore: registered new device driver usb
10239 01:00:42.929527 <6>[ 0.606097] pps_core: LinuxPPS API ver. 1 registered
10240 01:00:42.939965 <6>[ 0.611292] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10241 01:00:42.942716 <6>[ 0.620640] PTP clock support registered
10242 01:00:42.945627 <6>[ 0.624881] EDAC MC: Ver: 3.0.0
10243 01:00:42.953367 <6>[ 0.630032] FPGA manager framework
10244 01:00:42.959816 <6>[ 0.633712] Advanced Linux Sound Architecture Driver Initialized.
10245 01:00:42.963727 <6>[ 0.640483] vgaarb: loaded
10246 01:00:42.969461 <6>[ 0.643625] clocksource: Switched to clocksource arch_sys_counter
10247 01:00:42.973375 <5>[ 0.650062] VFS: Disk quotas dquot_6.6.0
10248 01:00:42.979942 <6>[ 0.654244] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10249 01:00:42.983153 <6>[ 0.661434] pnp: PnP ACPI: disabled
10250 01:00:42.991410 <6>[ 0.668142] NET: Registered PF_INET protocol family
10251 01:00:42.999151 <6>[ 0.673523] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10252 01:00:43.009919 <6>[ 0.683531] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10253 01:00:43.020221 <6>[ 0.692314] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10254 01:00:43.026690 <6>[ 0.700278] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10255 01:00:43.033462 <6>[ 0.708681] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10256 01:00:43.043987 <6>[ 0.717333] TCP: Hash tables configured (established 32768 bind 32768)
10257 01:00:43.050551 <6>[ 0.724191] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10258 01:00:43.057834 <6>[ 0.731210] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10259 01:00:43.063553 <6>[ 0.738731] NET: Registered PF_UNIX/PF_LOCAL protocol family
10260 01:00:43.070438 <6>[ 0.744872] RPC: Registered named UNIX socket transport module.
10261 01:00:43.073841 <6>[ 0.751027] RPC: Registered udp transport module.
10262 01:00:43.080582 <6>[ 0.755960] RPC: Registered tcp transport module.
10263 01:00:43.087452 <6>[ 0.760892] RPC: Registered tcp NFSv4.1 backchannel transport module.
10264 01:00:43.090420 <6>[ 0.767555] PCI: CLS 0 bytes, default 64
10265 01:00:43.093306 <6>[ 0.771950] Unpacking initramfs...
10266 01:00:43.103114 <6>[ 0.775635] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10267 01:00:43.110796 <6>[ 0.784268] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10268 01:00:43.116481 <6>[ 0.793030] kvm [1]: IPA Size Limit: 40 bits
10269 01:00:43.119777 <6>[ 0.797557] kvm [1]: GICv3: no GICV resource entry
10270 01:00:43.126361 <6>[ 0.802580] kvm [1]: disabling GICv2 emulation
10271 01:00:43.132811 <6>[ 0.807265] kvm [1]: GIC system register CPU interface enabled
10272 01:00:43.136324 <6>[ 0.813430] kvm [1]: vgic interrupt IRQ18
10273 01:00:43.142740 <6>[ 0.817790] kvm [1]: VHE mode initialized successfully
10274 01:00:43.146357 <5>[ 0.824259] Initialise system trusted keyrings
10275 01:00:43.152550 <6>[ 0.829103] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10276 01:00:43.162274 <6>[ 0.839303] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10277 01:00:43.169047 <5>[ 0.845709] NFS: Registering the id_resolver key type
10278 01:00:43.172254 <5>[ 0.851007] Key type id_resolver registered
10279 01:00:43.179014 <5>[ 0.855422] Key type id_legacy registered
10280 01:00:43.185282 <6>[ 0.859697] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10281 01:00:43.192793 <6>[ 0.866617] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10282 01:00:43.199786 <6>[ 0.874356] 9p: Installing v9fs 9p2000 file system support
10283 01:00:43.234958 <5>[ 0.911791] Key type asymmetric registered
10284 01:00:43.238360 <5>[ 0.916122] Asymmetric key parser 'x509' registered
10285 01:00:43.248919 <6>[ 0.921267] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10286 01:00:43.251540 <6>[ 0.928880] io scheduler mq-deadline registered
10287 01:00:43.254834 <6>[ 0.933641] io scheduler kyber registered
10288 01:00:43.274376 <6>[ 0.950728] EINJ: ACPI disabled.
10289 01:00:43.306306 <4>[ 0.976108] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10290 01:00:43.315940 <4>[ 0.986739] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10291 01:00:43.331018 <6>[ 1.007477] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10292 01:00:43.338586 <6>[ 1.015527] printk: console [ttyS0] disabled
10293 01:00:43.367381 <6>[ 1.040171] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10294 01:00:43.373705 <6>[ 1.049645] printk: console [ttyS0] enabled
10295 01:00:43.376526 <6>[ 1.049645] printk: console [ttyS0] enabled
10296 01:00:43.383085 <6>[ 1.058543] printk: bootconsole [mtk8250] disabled
10297 01:00:43.387230 <6>[ 1.058543] printk: bootconsole [mtk8250] disabled
10298 01:00:43.393815 <6>[ 1.069825] SuperH (H)SCI(F) driver initialized
10299 01:00:43.396596 <6>[ 1.075116] msm_serial: driver initialized
10300 01:00:43.411069 <6>[ 1.084094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10301 01:00:43.421396 <6>[ 1.092640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10302 01:00:43.427417 <6>[ 1.101184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10303 01:00:43.437407 <6>[ 1.109814] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10304 01:00:43.446909 <6>[ 1.118523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10305 01:00:43.453661 <6>[ 1.127238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10306 01:00:43.463594 <6>[ 1.135779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10307 01:00:43.470402 <6>[ 1.144589] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10308 01:00:43.480027 <6>[ 1.153134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10309 01:00:43.492046 <6>[ 1.168950] loop: module loaded
10310 01:00:43.498982 <6>[ 1.174926] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10311 01:00:43.521681 <4>[ 1.198277] mtk-pmic-keys: Failed to locate of_node [id: -1]
10312 01:00:43.528866 <6>[ 1.205241] megasas: 07.719.03.00-rc1
10313 01:00:43.538021 <6>[ 1.214781] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10314 01:00:43.546511 <6>[ 1.223018] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10315 01:00:43.563864 <6>[ 1.239747] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10316 01:00:43.620286 <6>[ 1.289730] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10317 01:00:45.109849 <6>[ 2.786933] Freeing initrd memory: 46412K
10318 01:00:45.120420 <6>[ 2.797148] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10319 01:00:45.130973 <6>[ 2.808177] tun: Universal TUN/TAP device driver, 1.6
10320 01:00:45.134744 <6>[ 2.814251] thunder_xcv, ver 1.0
10321 01:00:45.138045 <6>[ 2.817758] thunder_bgx, ver 1.0
10322 01:00:45.140644 <6>[ 2.821253] nicpf, ver 1.0
10323 01:00:45.151233 <6>[ 2.825272] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10324 01:00:45.154690 <6>[ 2.832748] hns3: Copyright (c) 2017 Huawei Corporation.
10325 01:00:45.161429 <6>[ 2.838335] hclge is initializing
10326 01:00:45.164522 <6>[ 2.841914] e1000: Intel(R) PRO/1000 Network Driver
10327 01:00:45.171683 <6>[ 2.847043] e1000: Copyright (c) 1999-2006 Intel Corporation.
10328 01:00:45.175239 <6>[ 2.853059] e1000e: Intel(R) PRO/1000 Network Driver
10329 01:00:45.181666 <6>[ 2.858274] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10330 01:00:45.187692 <6>[ 2.864464] igb: Intel(R) Gigabit Ethernet Network Driver
10331 01:00:45.194384 <6>[ 2.870114] igb: Copyright (c) 2007-2014 Intel Corporation.
10332 01:00:45.201359 <6>[ 2.875948] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10333 01:00:45.208168 <6>[ 2.882470] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10334 01:00:45.211992 <6>[ 2.888935] sky2: driver version 1.30
10335 01:00:45.218156 <6>[ 2.893919] VFIO - User Level meta-driver version: 0.3
10336 01:00:45.225260 <6>[ 2.902180] usbcore: registered new interface driver usb-storage
10337 01:00:45.231560 <6>[ 2.908624] usbcore: registered new device driver onboard-usb-hub
10338 01:00:45.241113 <6>[ 2.917807] mt6397-rtc mt6359-rtc: registered as rtc0
10339 01:00:45.250581 <6>[ 2.923265] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:00:45 UTC (1705626045)
10340 01:00:45.253982 <6>[ 2.932850] i2c_dev: i2c /dev entries driver
10341 01:00:45.270332 <6>[ 2.944444] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10342 01:00:45.292223 <6>[ 2.968441] cpu cpu0: EM: created perf domain
10343 01:00:45.294981 <6>[ 2.973332] cpu cpu4: EM: created perf domain
10344 01:00:45.301790 <6>[ 2.978880] sdhci: Secure Digital Host Controller Interface driver
10345 01:00:45.308396 <6>[ 2.985310] sdhci: Copyright(c) Pierre Ossman
10346 01:00:45.315214 <6>[ 2.990240] Synopsys Designware Multimedia Card Interface Driver
10347 01:00:45.321525 <6>[ 2.996834] sdhci-pltfm: SDHCI platform and OF driver helper
10348 01:00:45.325254 <6>[ 2.996920] mmc0: CQHCI version 5.10
10349 01:00:45.332169 <6>[ 3.007050] ledtrig-cpu: registered to indicate activity on CPUs
10350 01:00:45.338740 <6>[ 3.014093] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10351 01:00:45.345633 <6>[ 3.021111] usbcore: registered new interface driver usbhid
10352 01:00:45.348620 <6>[ 3.026932] usbhid: USB HID core driver
10353 01:00:45.355400 <6>[ 3.031132] spi_master spi0: will run message pump with realtime priority
10354 01:00:45.397464 <6>[ 3.067566] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10355 01:00:45.417165 <6>[ 3.083446] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10356 01:00:45.423275 <6>[ 3.098309] cros-ec-spi spi0.0: Chrome EC device registered
10357 01:00:45.426213 <6>[ 3.098333] mmc0: Command Queue Engine enabled
10358 01:00:45.433023 <6>[ 3.108887] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10359 01:00:45.439705 <6>[ 3.116336] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10360 01:00:45.449357 <6>[ 3.126194] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10361 01:00:45.458134 <6>[ 3.133757] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10362 01:00:45.467009 <6>[ 3.137091] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10363 01:00:45.469639 <6>[ 3.139611] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10364 01:00:45.476748 <6>[ 3.149167] NET: Registered PF_PACKET protocol family
10365 01:00:45.483369 <6>[ 3.154195] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10366 01:00:45.486684 <6>[ 3.158863] 9pnet: Installing 9P2000 support
10367 01:00:45.493320 <5>[ 3.169883] Key type dns_resolver registered
10368 01:00:45.497356 <6>[ 3.174875] registered taskstats version 1
10369 01:00:45.503497 <5>[ 3.179256] Loading compiled-in X.509 certificates
10370 01:00:45.531105 <4>[ 3.200846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10371 01:00:45.541023 <4>[ 3.211542] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10372 01:00:45.547058 <3>[ 3.222075] debugfs: File 'uA_load' in directory '/' already present!
10373 01:00:45.553969 <3>[ 3.228852] debugfs: File 'min_uV' in directory '/' already present!
10374 01:00:45.559933 <3>[ 3.235470] debugfs: File 'max_uV' in directory '/' already present!
10375 01:00:45.566763 <3>[ 3.242078] debugfs: File 'constraint_flags' in directory '/' already present!
10376 01:00:45.578121 <3>[ 3.251330] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10377 01:00:45.586545 <6>[ 3.263417] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10378 01:00:45.593511 <6>[ 3.270267] xhci-mtk 11200000.usb: xHCI Host Controller
10379 01:00:45.600170 <6>[ 3.275759] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10380 01:00:45.610095 <6>[ 3.283612] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10381 01:00:45.616949 <6>[ 3.293058] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10382 01:00:45.623432 <6>[ 3.299164] xhci-mtk 11200000.usb: xHCI Host Controller
10383 01:00:45.630015 <6>[ 3.304644] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10384 01:00:45.636437 <6>[ 3.312295] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10385 01:00:45.643268 <6>[ 3.319913] hub 1-0:1.0: USB hub found
10386 01:00:45.646697 <6>[ 3.323938] hub 1-0:1.0: 1 port detected
10387 01:00:45.656674 <6>[ 3.328191] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10388 01:00:45.659714 <6>[ 3.336845] hub 2-0:1.0: USB hub found
10389 01:00:45.662560 <6>[ 3.340889] hub 2-0:1.0: 1 port detected
10390 01:00:45.671506 <6>[ 3.348455] mtk-msdc 11f70000.mmc: Got CD GPIO
10391 01:00:45.681806 <6>[ 3.355810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10392 01:00:45.689093 <6>[ 3.363843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10393 01:00:45.698360 <4>[ 3.371768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10394 01:00:45.708821 <6>[ 3.381291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10395 01:00:45.715141 <6>[ 3.389368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10396 01:00:45.722391 <6>[ 3.397409] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10397 01:00:45.731874 <6>[ 3.405344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10398 01:00:45.738463 <6>[ 3.413162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10399 01:00:45.747847 <6>[ 3.420979] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10400 01:00:45.759276 <6>[ 3.431322] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10401 01:00:45.765139 <6>[ 3.439717] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10402 01:00:45.774771 <6>[ 3.448072] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10403 01:00:45.781584 <6>[ 3.456410] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10404 01:00:45.790932 <6>[ 3.464748] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10405 01:00:45.798033 <6>[ 3.473086] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10406 01:00:45.808201 <6>[ 3.481423] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10407 01:00:45.817311 <6>[ 3.489761] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10408 01:00:45.824265 <6>[ 3.498099] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10409 01:00:45.834403 <6>[ 3.506437] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10410 01:00:45.842475 <6>[ 3.514775] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10411 01:00:45.850807 <6>[ 3.523113] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10412 01:00:45.857656 <6>[ 3.531451] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10413 01:00:45.866998 <6>[ 3.539789] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10414 01:00:45.873824 <6>[ 3.548128] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10415 01:00:45.880679 <6>[ 3.556852] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10416 01:00:45.886664 <6>[ 3.563992] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10417 01:00:45.893571 <6>[ 3.570734] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10418 01:00:45.903899 <6>[ 3.577461] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10419 01:00:45.910197 <6>[ 3.584369] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10420 01:00:45.917287 <6>[ 3.591216] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10421 01:00:45.927413 <6>[ 3.600349] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10422 01:00:45.937141 <6>[ 3.609470] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10423 01:00:45.946708 <6>[ 3.618765] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10424 01:00:45.956628 <6>[ 3.628231] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10425 01:00:45.966584 <6>[ 3.637697] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10426 01:00:45.973246 <6>[ 3.646815] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10427 01:00:45.982814 <6>[ 3.656280] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10428 01:00:45.993846 <6>[ 3.665404] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10429 01:00:46.003724 <6>[ 3.674697] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10430 01:00:46.012928 <6>[ 3.684856] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10431 01:00:46.022815 <6>[ 3.696415] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10432 01:00:46.075416 <6>[ 3.747764] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10433 01:00:46.229618 <6>[ 3.905787] hub 1-1:1.0: USB hub found
10434 01:00:46.231627 <6>[ 3.910282] hub 1-1:1.0: 4 ports detected
10435 01:00:46.242045 <6>[ 3.918746] hub 1-1:1.0: USB hub found
10436 01:00:46.244826 <6>[ 3.923128] hub 1-1:1.0: 4 ports detected
10437 01:00:46.354824 <6>[ 4.028170] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10438 01:00:46.380274 <6>[ 4.057623] hub 2-1:1.0: USB hub found
10439 01:00:46.383761 <6>[ 4.062113] hub 2-1:1.0: 3 ports detected
10440 01:00:46.393812 <6>[ 4.070257] hub 2-1:1.0: USB hub found
10441 01:00:46.396558 <6>[ 4.074715] hub 2-1:1.0: 3 ports detected
10442 01:00:46.569584 <6>[ 4.243920] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10443 01:00:46.703236 <6>[ 4.379590] hub 1-1.4:1.0: USB hub found
10444 01:00:46.705703 <6>[ 4.384269] hub 1-1.4:1.0: 2 ports detected
10445 01:00:46.715861 <6>[ 4.391530] hub 1-1.4:1.0: USB hub found
10446 01:00:46.717244 <6>[ 4.396140] hub 1-1.4:1.0: 2 ports detected
10447 01:00:46.782267 <6>[ 4.456137] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10448 01:00:47.014103 <6>[ 4.687935] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10449 01:00:47.206762 <6>[ 4.879911] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10450 01:00:58.307633 <6>[ 15.988935] ALSA device list:
10451 01:00:58.313985 <6>[ 15.992231] No soundcards found.
10452 01:00:58.321771 <6>[ 16.000103] Freeing unused kernel memory: 8448K
10453 01:00:58.324812 <6>[ 16.005087] Run /init as init process
10454 01:00:58.373479 <6>[ 16.051901] NET: Registered PF_INET6 protocol family
10455 01:00:58.379963 <6>[ 16.058165] Segment Routing with IPv6
10456 01:00:58.383137 <6>[ 16.062122] In-situ OAM (IOAM) with IPv6
10457 01:00:58.418142 <30>[ 16.076923] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10458 01:00:58.421541 <30>[ 16.100665] systemd[1]: Detected architecture arm64.
10459 01:00:58.422012
10460 01:00:58.428276 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10461 01:00:58.428901
10462 01:00:58.441455 <30>[ 16.119986] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10463 01:00:58.592006 <30>[ 16.267245] systemd[1]: Queued start job for default target Graphical Interface.
10464 01:00:58.642123 <30>[ 16.320973] systemd[1]: Created slice system-getty.slice.
10465 01:00:58.649097 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10466 01:00:58.666896 <30>[ 16.344218] systemd[1]: Created slice system-modprobe.slice.
10467 01:00:58.672406 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10468 01:00:58.690138 <30>[ 16.368783] systemd[1]: Created slice system-serial\x2dgetty.slice.
10469 01:00:58.700190 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10470 01:00:58.714464 <30>[ 16.393015] systemd[1]: Created slice User and Session Slice.
10471 01:00:58.721668 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10472 01:00:58.745369 <30>[ 16.420255] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10473 01:00:58.755206 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10474 01:00:58.773675 <30>[ 16.448611] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10475 01:00:58.779889 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10476 01:00:58.804460 <30>[ 16.476412] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10477 01:00:58.810653 <30>[ 16.488689] systemd[1]: Reached target Local Encrypted Volumes.
10478 01:00:58.818042 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10479 01:00:58.834151 <30>[ 16.512462] systemd[1]: Reached target Paths.
10480 01:00:58.840796 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10481 01:00:58.853539 <30>[ 16.531908] systemd[1]: Reached target Remote File Systems.
10482 01:00:58.859705 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10483 01:00:58.878111 <30>[ 16.556273] systemd[1]: Reached target Slices.
10484 01:00:58.884136 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10485 01:00:58.897359 <30>[ 16.575937] systemd[1]: Reached target Swap.
10486 01:00:58.901214 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10487 01:00:58.921872 <30>[ 16.596425] systemd[1]: Listening on initctl Compatibility Named Pipe.
10488 01:00:58.927744 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10489 01:00:58.934076 <30>[ 16.611704] systemd[1]: Listening on Journal Audit Socket.
10490 01:00:58.940891 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10491 01:00:58.953618 <30>[ 16.632392] systemd[1]: Listening on Journal Socket (/dev/log).
10492 01:00:58.960502 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10493 01:00:58.978637 <30>[ 16.657180] systemd[1]: Listening on Journal Socket.
10494 01:00:58.985189 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10495 01:00:59.001527 <30>[ 16.676657] systemd[1]: Listening on Network Service Netlink Socket.
10496 01:00:59.008054 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10497 01:00:59.022780 <30>[ 16.701115] systemd[1]: Listening on udev Control Socket.
10498 01:00:59.029349 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10499 01:00:59.046692 <30>[ 16.724974] systemd[1]: Listening on udev Kernel Socket.
10500 01:00:59.052668 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10501 01:00:59.109658 <30>[ 16.788171] systemd[1]: Mounting Huge Pages File System...
10502 01:00:59.115855 Mounting [0;1;39mHuge Pages File System[0m...
10503 01:00:59.136242 <30>[ 16.813886] systemd[1]: Mounting POSIX Message Queue File System...
10504 01:00:59.141795 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10505 01:00:59.165079 <30>[ 16.843770] systemd[1]: Mounting Kernel Debug File System...
10506 01:00:59.171547 Mounting [0;1;39mKernel Debug File System[0m...
10507 01:00:59.189120 <30>[ 16.864018] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10508 01:00:59.201344 <30>[ 16.876749] systemd[1]: Starting Create list of static device nodes for the current kernel...
10509 01:00:59.208259 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10510 01:00:59.245529 <30>[ 16.924256] systemd[1]: Starting Load Kernel Module configfs...
10511 01:00:59.252182 Starting [0;1;39mLoad Kernel Module configfs[0m...
10512 01:00:59.270065 <30>[ 16.948536] systemd[1]: Starting Load Kernel Module drm...
10513 01:00:59.276702 Starting [0;1;39mLoad Kernel Module drm[0m...
10514 01:00:59.293006 <30>[ 16.968315] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10515 01:00:59.325351 <30>[ 17.004268] systemd[1]: Starting Journal Service...
10516 01:00:59.329184 Starting [0;1;39mJournal Service[0m...
10517 01:00:59.348547 <30>[ 17.026768] systemd[1]: Starting Load Kernel Modules...
10518 01:00:59.355380 Starting [0;1;39mLoad Kernel Modules[0m...
10519 01:00:59.378210 <30>[ 17.052674] systemd[1]: Starting Remount Root and Kernel File Systems...
10520 01:00:59.384162 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10521 01:00:59.414519 <30>[ 17.092359] systemd[1]: Starting Coldplug All udev Devices...
10522 01:00:59.420798 Starting [0;1;39mColdplug All udev Devices[0m...
10523 01:00:59.437093 <30>[ 17.115391] systemd[1]: Started Journal Service.
10524 01:00:59.444073 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10525 01:00:59.461694 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10526 01:00:59.478956 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10527 01:00:59.494648 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10528 01:00:59.515667 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10529 01:00:59.531152 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10530 01:00:59.549900 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10531 01:00:59.567177 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10532 01:00:59.587576 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10533 01:00:59.601372 See 'systemctl status systemd-remount-fs.service' for details.
10534 01:00:59.643534 Mounting [0;1;39mKernel Configuration File System[0m...
10535 01:00:59.664972 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10536 01:00:59.688602 <46>[ 17.363553] systemd-journald[186]: Received client request to flush runtime journal.
10537 01:00:59.718627 Starting [0;1;39mLoad/Save Random Seed[0m...
10538 01:00:59.738030 Starting [0;1;39mApply Kernel Variables[0m...
10539 01:00:59.758208 Starting [0;1;39mCreate System Users[0m...
10540 01:00:59.782419 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10541 01:00:59.802925 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10542 01:00:59.822308 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10543 01:00:59.836022 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10544 01:00:59.851041 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10545 01:00:59.867209 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10546 01:00:59.902566 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10547 01:00:59.922033 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10548 01:00:59.934064 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10549 01:00:59.949580 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10550 01:01:00.002116 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10551 01:01:00.032225 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10552 01:01:00.051562 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10553 01:01:00.071890 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10554 01:01:00.115499 Starting [0;1;39mNetwork Service[0m...
10555 01:01:00.141393 Starting [0;1;39mNetwork Time Synchronization[0m...
10556 01:01:00.168250 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10557 01:01:00.201393 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10558 01:01:00.215856 <6>[ 17.891439] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10559 01:01:00.235538 <6>[ 17.914206] remoteproc remoteproc0: scp is available
10560 01:01:00.242248 [[0;32m OK [<6>[ 17.921152] remoteproc remoteproc0: powering up scp
10561 01:01:00.252263 0m] Started [0;<6>[ 17.922513] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10562 01:01:00.262116 1;39mNetwork Tim<6>[ 17.926586] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10563 01:01:00.272477 e Synchronizatio<6>[ 17.935583] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10564 01:01:00.273097 n[0m.
10565 01:01:00.278564 <6>[ 17.955465] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10566 01:01:00.288358 <6>[ 17.955685] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10567 01:01:00.292337 <6>[ 17.958983] usbcore: registered new device driver r8152-cfgselector
10568 01:01:00.302270 [[0;32m OK [<3>[ 17.978503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10569 01:01:00.312044 0m] Finished [0<3>[ 17.987254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10570 01:01:00.322090 ;1;39mUpdate UTM<4>[ 17.987495] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10571 01:01:00.328819 <3>[ 17.996649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10572 01:01:00.339082 P about System B<3>[ 18.005273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10573 01:01:00.348597 oot/Shutdown[0m<4>[ 18.023305] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10574 01:01:00.349240 .
10575 01:01:00.355084 <3>[ 18.023373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10576 01:01:00.366032 <3>[ 18.039985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10577 01:01:00.372530 <3>[ 18.048459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10578 01:01:00.382082 <6>[ 18.049193] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10579 01:01:00.385020 <6>[ 18.054835] mc: Linux media interface: v0.10
10580 01:01:00.395024 <3>[ 18.056609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10581 01:01:00.401223 <3>[ 18.056672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 01:01:00.411972 <3>[ 18.056722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10583 01:01:00.418442 <3>[ 18.056727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10584 01:01:00.424549 <3>[ 18.056731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10585 01:01:00.434597 <3>[ 18.056830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10586 01:01:00.440846 <3>[ 18.056834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10587 01:01:00.451786 <3>[ 18.056837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10588 01:01:00.457946 <3>[ 18.056841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10589 01:01:00.468101 <3>[ 18.056845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10590 01:01:00.474902 <3>[ 18.056890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10591 01:01:00.481609 <6>[ 18.065386] videodev: Linux video capture interface: v2.00
10592 01:01:00.487693 <6>[ 18.087512] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10593 01:01:00.494986 <6>[ 18.087525] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10594 01:01:00.505111 <4>[ 18.105187] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10595 01:01:00.510962 <4>[ 18.105187] Fallback method does not support PEC.
10596 01:01:00.518317 <6>[ 18.107368] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10597 01:01:00.520769 <6>[ 18.107376] pci_bus 0000:00: root bus resource [bus 00-ff]
10598 01:01:00.531671 <6>[ 18.107383] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10599 01:01:00.540836 <6>[ 18.107389] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10600 01:01:00.544319 <6>[ 18.107428] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10601 01:01:00.554151 <6>[ 18.107455] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10602 01:01:00.558022 <6>[ 18.107543] pci 0000:00:00.0: supports D1 D2
10603 01:01:00.564661 <6>[ 18.107547] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10604 01:01:00.574502 <6>[ 18.109816] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10605 01:01:00.580774 <6>[ 18.109964] remoteproc remoteproc0: remote processor scp is now up
10606 01:01:00.587493 <6>[ 18.110914] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10607 01:01:00.594518 <6>[ 18.110950] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10608 01:01:00.600507 <6>[ 18.110973] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10609 01:01:00.608081 <6>[ 18.110992] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10610 01:01:00.611318 <6>[ 18.111141] pci 0000:01:00.0: supports D1 D2
10611 01:01:00.618251 <6>[ 18.111147] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10612 01:01:00.628845 <3>[ 18.133413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 01:01:00.635181 <6>[ 18.139948] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10614 01:01:00.645957 <6>[ 18.146388] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10615 01:01:00.652793 <6>[ 18.151389] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10616 01:01:00.660278 <6>[ 18.151545] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10617 01:01:00.670879 <6>[ 18.153841] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10618 01:01:00.677712 <6>[ 18.158731] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10619 01:01:00.687114 <6>[ 18.164423] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10620 01:01:00.697678 <6>[ 18.172955] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10621 01:01:00.703842 <6>[ 18.180181] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10622 01:01:00.714471 <6>[ 18.193994] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10623 01:01:00.720616 <6>[ 18.200527] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10624 01:01:00.723713 <6>[ 18.230794] Bluetooth: Core ver 2.22
10625 01:01:00.733735 <6>[ 18.237087] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10626 01:01:00.736945 <6>[ 18.241638] NET: Registered PF_BLUETOOTH protocol family
10627 01:01:00.743950 <6>[ 18.248462] pci 0000:00:00.0: PCI bridge to [bus 01]
10628 01:01:00.750975 <6>[ 18.256691] Bluetooth: HCI device and connection manager initialized
10629 01:01:00.758212 <6>[ 18.263239] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10630 01:01:00.765093 <6>[ 18.268442] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10631 01:01:00.771879 <6>[ 18.269395] Bluetooth: HCI socket layer initialized
10632 01:01:00.778317 <6>[ 18.277085] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10633 01:01:00.785350 <6>[ 18.277659] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10634 01:01:00.794434 <6>[ 18.278629] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10635 01:01:00.801750 <6>[ 18.278732] usbcore: registered new interface driver uvcvideo
10636 01:01:00.808414 <6>[ 18.284343] Bluetooth: L2CAP socket layer initialized
10637 01:01:00.815056 <6>[ 18.292473] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10638 01:01:00.818389 <6>[ 18.296427] Bluetooth: SCO socket layer initialized
10639 01:01:00.827919 <3>[ 18.296750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 01:01:00.834848 <6>[ 18.297391] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10641 01:01:00.841136 <6>[ 18.303535] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10642 01:01:00.848564 <3>[ 18.321961] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 01:01:00.854827 <3>[ 18.322852] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10644 01:01:00.861447 <6>[ 18.329023] r8152 2-1.3:1.0 eth0: v1.12.13
10645 01:01:00.868836 <3>[ 18.331584] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 01:01:00.878872 <3>[ 18.347075] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 01:01:00.882565 <6>[ 18.353111] usbcore: registered new interface driver r8152
10648 01:01:00.892234 <5>[ 18.356284] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10649 01:01:00.899401 <5>[ 18.366485] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10650 01:01:00.907169 <3>[ 18.381332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10651 01:01:00.916402 <5>[ 18.387732] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10652 01:01:00.923137 <6>[ 18.388329] usbcore: registered new interface driver btusb
10653 01:01:00.933359 <4>[ 18.389339] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10654 01:01:00.939108 <3>[ 18.389346] Bluetooth: hci0: Failed to load firmware file (-2)
10655 01:01:00.943256 <3>[ 18.389349] Bluetooth: hci0: Failed to set up firmware (-2)
10656 01:01:00.952940 <4>[ 18.389352] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10657 01:01:00.959334 <6>[ 18.404662] usbcore: registered new interface driver cdc_ether
10658 01:01:00.968957 <4>[ 18.408357] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10659 01:01:00.979096 <3>[ 18.414596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10660 01:01:00.982614 <6>[ 18.422008] usbcore: registered new interface driver r8153_ecm
10661 01:01:00.989001 <6>[ 18.427063] cfg80211: failed to load regulatory.db
10662 01:01:00.999023 <3>[ 18.438087] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 01:01:01.006000 <6>[ 18.466915] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10664 01:01:01.013059 <3>[ 18.486622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 01:01:01.018970 <6>[ 18.506700] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10666 01:01:01.025697 <6>[ 18.703884] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10667 01:01:01.031618 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10668 01:01:01.044936 <6>[ 18.723926] mt7921e 0000:01:00.0: ASIC revision: 79610010
10669 01:01:01.110055 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10670 01:01:01.125697 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10671 01:01:01.143122 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10672 01:01:01.153444 <6>[ 18.827305] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10673 01:01:01.154027 <6>[ 18.827305]
10674 01:01:01.159752 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10675 01:01:01.177014 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10676 01:01:01.209509 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10677 01:01:01.235778 Starting [0;1;39mNetwork Name Resolution[0m...
10678 01:01:01.259335 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10679 01:01:01.274919 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10680 01:01:01.293734 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10681 01:01:01.313320 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10682 01:01:01.329352 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10683 01:01:01.354431 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10684 01:01:01.369596 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10685 01:01:01.389999 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10686 01:01:01.421863 <6>[ 19.097706] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10687 01:01:01.441813 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10688 01:01:01.471987 Starting [0;1;39mUser Login Management[0m...
10689 01:01:01.488735 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10690 01:01:01.505913 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10691 01:01:01.522120 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10692 01:01:01.542138 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10693 01:01:01.560919 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10694 01:01:01.590642 Starting [0;1;39mPermit User Sessions[0m...
10695 01:01:01.608276 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10696 01:01:01.615927 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10697 01:01:01.627237 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10698 01:01:01.645455 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10699 01:01:01.661767 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10700 01:01:01.677812 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10701 01:01:01.693668 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10702 01:01:01.746559 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10703 01:01:01.781067 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10704 01:01:01.833082
10705 01:01:01.833646
10706 01:01:01.836278 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10707 01:01:01.836890
10708 01:01:01.839639 debian-bullseye-arm64 login: root (automatic login)
10709 01:01:01.840217
10710 01:01:01.840757
10711 01:01:01.854272 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
10712 01:01:01.854848
10713 01:01:01.860613 The programs included with the Debian GNU/Linux system are free software;
10714 01:01:01.867747 the exact distribution terms for each program are described in the
10715 01:01:01.871038 individual files in /usr/share/doc/*/copyright.
10716 01:01:01.871614
10717 01:01:01.877291 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10718 01:01:01.880592 permitted by applicable law.
10719 01:01:01.882366 Matched prompt #10: / #
10721 01:01:01.883628 Setting prompt string to ['/ #']
10722 01:01:01.884216 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10724 01:01:01.885516 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10725 01:01:01.886102 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
10726 01:01:01.886529 Setting prompt string to ['/ #']
10727 01:01:01.886964 Forcing a shell prompt, looking for ['/ #']
10729 01:01:01.938111 / #
10730 01:01:01.938794 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10731 01:01:01.939387 Waiting using forced prompt support (timeout 00:02:30)
10732 01:01:01.945312
10733 01:01:01.946281 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10734 01:01:01.946878 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
10735 01:01:01.947474 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10736 01:01:01.948023 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
10737 01:01:01.948583 end: 2 depthcharge-action (duration 00:01:37) [common]
10738 01:01:01.949234 start: 3 lava-test-retry (timeout 00:05:00) [common]
10739 01:01:01.949814 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10740 01:01:01.950267 Using namespace: common
10742 01:01:02.051908 / # #
10743 01:01:02.052606 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10744 01:01:02.059111 #
10745 01:01:02.060032 Using /lava-12571112
10747 01:01:02.161653 / # export SHELL=/bin/sh
10748 01:01:02.168298 export SHELL=/bin/sh
10750 01:01:02.270034 / # . /lava-12571112/environment
10751 01:01:02.270870 <6>[ 19.886454] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10752 01:01:02.271299 <6>[ 19.894218] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10753 01:01:02.271859 . /lava-12571112/environment<6>[ 19.947057] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10754 01:01:02.313342
10756 01:01:02.415343 / # /lava-12571112/bin/lava-test-runner /lava-12571112/0
10757 01:01:02.415996 Test shell timeout: 10s (minimum of the action and connection timeout)
10758 01:01:02.422114 /lava-12571112/bin/lava-test-runner /lava-12571112/0
10759 01:01:02.448620 + export TESTRUN<8>[ 20.125063] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12571112_1.5.2.3.1>
10760 01:01:02.449266 _ID=0_cros-ec
10761 01:01:02.450061 Received signal: <STARTRUN> 0_cros-ec 12571112_1.5.2.3.1
10762 01:01:02.450488 Starting test lava.0_cros-ec (12571112_1.5.2.3.1)
10763 01:01:02.451070 Skipping test definition patterns.
10764 01:01:02.451723 + cd /lava-12571112/0/tests/0_cros-ec
10765 01:01:02.455336 + cat uuid
10766 01:01:02.455911 + UUID=12571112_1.5.2.3.1
10767 01:01:02.456407 + set +x
10768 01:01:02.461611 + python3 -m cros.runners.lava_runner -v
10769 01:01:02.788604 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10770 01:01:02.796421 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10771 01:01:02.798777
10772 01:01:02.802492 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10774 01:01:02.805261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10775 01:01:02.811768 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10776 01:01:02.818926 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10777 01:01:02.819504
10778 01:01:02.828918 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
10779 01:01:02.829541 Bad test result: ski<8
10780 01:01:02.832349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.509769] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12571112_1.5.2.3.1>
10781 01:01:02.833264 Received signal: <ENDRUN> 0_cros-ec 12571112_1.5.2.3.1
10782 01:01:02.833733 Ending use of test pattern.
10783 01:01:02.834086 Ending test lava.0_cros-ec (12571112_1.5.2.3.1), duration 0.38
10785 01:01:02.835700 p>
10786 01:01:02.838673 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10787 01:01:02.845008 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10788 01:01:02.845583
10789 01:01:02.851458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10790 01:01:02.852332 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10792 01:01:02.858126 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10793 01:01:02.864454 Checks the standard ABI for the main Embedded Controller. ... ok
10794 01:01:02.865058
10795 01:01:02.868281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10796 01:01:02.869203 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10798 01:01:02.874461 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10799 01:01:02.881616 Checks the main Embedded controller character device. ... ok
10800 01:01:02.882200
10801 01:01:02.884438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10802 01:01:02.885332 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10804 01:01:02.890895 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10805 01:01:02.898129 Checks basic comunication with the main Embedded controller. ... ok
10806 01:01:02.898708
10807 01:01:02.904317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10808 01:01:02.905224 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10810 01:01:02.907499 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10811 01:01:02.917426 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10812 01:01:02.917987
10813 01:01:02.921174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10814 01:01:02.922058 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10816 01:01:02.926990 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10817 01:01:02.934480 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10818 01:01:02.935060
10819 01:01:02.940915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10820 01:01:02.941784 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10822 01:01:02.947807 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
10823 01:01:02.953319 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10824 01:01:02.953882
10825 01:01:02.960239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10826 01:01:02.961162 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10828 01:01:02.962973 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10829 01:01:02.973422 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10830 01:01:02.974002
10831 01:01:02.976552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10832 01:01:02.977479 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10834 01:01:02.984022 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10835 01:01:02.993942 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10836 01:01:02.994521
10837 01:01:02.996463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10838 01:01:02.997403 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10840 01:01:03.002828 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10841 01:01:03.009384 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10842 01:01:03.009873
10843 01:01:03.016605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10844 01:01:03.017525 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10846 01:01:03.022584 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10847 01:01:03.029309 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10848 01:01:03.029793
10849 01:01:03.036256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10850 01:01:03.037173 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10852 01:01:03.042698 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
10853 01:01:03.049716 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10854 01:01:03.050298
10855 01:01:03.056240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10856 01:01:03.057151 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10858 01:01:03.062492 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
10859 01:01:03.069293 Check the cros battery ABI. ... skipped 'No BAT found'
10860 01:01:03.069870
10861 01:01:03.075745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10862 01:01:03.076628 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10864 01:01:03.082267 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
10865 01:01:03.088870 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10866 01:01:03.089441
10867 01:01:03.096165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10868 01:01:03.097075 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10870 01:01:03.098481 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
10871 01:01:03.105888 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10872 01:01:03.109087
10873 01:01:03.111837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10874 01:01:03.112595 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10876 01:01:03.119128 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
10877 01:01:03.124821 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10878 01:01:03.125304
10879 01:01:03.132085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
10880 01:01:03.132659
10881 01:01:03.133489 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
10883 01:01:03.138437 ----------------------------------------------------------------------
10884 01:01:03.141456 Ran 18 tests in 0.006s
10885 01:01:03.141936
10886 01:01:03.142423 OK (skipped=15)
10887 01:01:03.144562 + set +x
10888 01:01:03.145099 <LAVA_TEST_RUNNER EXIT>
10889 01:01:03.145867 ok: lava_test_shell seems to have completed
10890 01:01:03.146934 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10891 01:01:03.147513 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10892 01:01:03.148055 end: 3 lava-test-retry (duration 00:00:01) [common]
10893 01:01:03.148637 start: 4 finalize (timeout 00:08:01) [common]
10894 01:01:03.149266 start: 4.1 power-off (timeout 00:00:30) [common]
10895 01:01:03.150186 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10896 01:01:03.240600 >> Command sent successfully.
10897 01:01:03.252910 Returned 0 in 0 seconds
10898 01:01:03.354457 end: 4.1 power-off (duration 00:00:00) [common]
10900 01:01:03.356590 start: 4.2 read-feedback (timeout 00:08:01) [common]
10901 01:01:03.358343 Listened to connection for namespace 'common' for up to 1s
10902 01:01:04.358877 Finalising connection for namespace 'common'
10903 01:01:04.359610 Disconnecting from shell: Finalise
10904 01:01:04.360120 / #
10905 01:01:04.461278 end: 4.2 read-feedback (duration 00:00:01) [common]
10906 01:01:04.462032 end: 4 finalize (duration 00:00:01) [common]
10907 01:01:04.462869 Cleaning after the job
10908 01:01:04.463422 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/ramdisk
10909 01:01:04.492822 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/kernel
10910 01:01:04.509988 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/dtb
10911 01:01:04.510260 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571112/tftp-deploy-nlza_r_g/modules
10912 01:01:04.519992 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571112
10913 01:01:04.638901 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571112
10914 01:01:04.639084 Job finished correctly