Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 16
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 00:55:19.466284 lava-dispatcher, installed at version: 2023.10
2 00:55:19.466517 start: 0 validate
3 00:55:19.466655 Start time: 2024-01-19 00:55:19.466648+00:00 (UTC)
4 00:55:19.466778 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:55:19.466910 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 00:55:19.735716 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:55:19.735907 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:19.994094 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:19.994289 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:56.649193 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:56.649950 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:57.181099 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:57.181832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:57.448774 validate duration: 37.98
16 00:55:57.449026 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:57.449150 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:57.449236 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:57.449357 Not decompressing ramdisk as can be used compressed.
20 00:55:57.449440 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 00:55:57.449504 saving as /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/ramdisk/initrd.cpio.gz
22 00:55:57.449570 total size: 5628325 (5 MB)
23 00:56:00.161898 progress 0 % (0 MB)
24 00:56:00.172008 progress 5 % (0 MB)
25 00:56:00.181642 progress 10 % (0 MB)
26 00:56:00.189893 progress 15 % (0 MB)
27 00:56:00.197126 progress 20 % (1 MB)
28 00:56:00.199246 progress 25 % (1 MB)
29 00:56:00.200887 progress 30 % (1 MB)
30 00:56:00.202422 progress 35 % (1 MB)
31 00:56:00.203917 progress 40 % (2 MB)
32 00:56:00.205469 progress 45 % (2 MB)
33 00:56:00.206853 progress 50 % (2 MB)
34 00:56:00.208469 progress 55 % (2 MB)
35 00:56:00.210090 progress 60 % (3 MB)
36 00:56:00.211484 progress 65 % (3 MB)
37 00:56:00.213101 progress 70 % (3 MB)
38 00:56:00.214494 progress 75 % (4 MB)
39 00:56:00.216102 progress 80 % (4 MB)
40 00:56:00.217496 progress 85 % (4 MB)
41 00:56:00.219091 progress 90 % (4 MB)
42 00:56:00.220685 progress 95 % (5 MB)
43 00:56:00.222132 progress 100 % (5 MB)
44 00:56:00.222351 5 MB downloaded in 2.77 s (1.94 MB/s)
45 00:56:00.222513 end: 1.1.1 http-download (duration 00:00:03) [common]
47 00:56:00.222780 end: 1.1 download-retry (duration 00:00:03) [common]
48 00:56:00.222881 start: 1.2 download-retry (timeout 00:09:57) [common]
49 00:56:00.222979 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 00:56:00.223122 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:56:00.223197 saving as /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/kernel/Image
52 00:56:00.223294 total size: 51532288 (49 MB)
53 00:56:00.223393 No compression specified
54 00:56:00.224990 progress 0 % (0 MB)
55 00:56:00.238919 progress 5 % (2 MB)
56 00:56:00.252400 progress 10 % (4 MB)
57 00:56:00.265933 progress 15 % (7 MB)
58 00:56:00.279805 progress 20 % (9 MB)
59 00:56:00.293785 progress 25 % (12 MB)
60 00:56:00.307112 progress 30 % (14 MB)
61 00:56:00.320726 progress 35 % (17 MB)
62 00:56:00.335237 progress 40 % (19 MB)
63 00:56:00.349113 progress 45 % (22 MB)
64 00:56:00.362776 progress 50 % (24 MB)
65 00:56:00.376265 progress 55 % (27 MB)
66 00:56:00.389613 progress 60 % (29 MB)
67 00:56:00.403113 progress 65 % (31 MB)
68 00:56:00.416542 progress 70 % (34 MB)
69 00:56:00.429940 progress 75 % (36 MB)
70 00:56:00.443656 progress 80 % (39 MB)
71 00:56:00.457160 progress 85 % (41 MB)
72 00:56:00.470890 progress 90 % (44 MB)
73 00:56:00.484149 progress 95 % (46 MB)
74 00:56:00.497232 progress 100 % (49 MB)
75 00:56:00.497485 49 MB downloaded in 0.27 s (179.24 MB/s)
76 00:56:00.497659 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:56:00.497921 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:56:00.498029 start: 1.3 download-retry (timeout 00:09:57) [common]
80 00:56:00.498128 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 00:56:00.498284 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:56:00.498383 saving as /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/dtb/mt8192-asurada-spherion-r0.dtb
83 00:56:00.498482 total size: 47278 (0 MB)
84 00:56:00.498581 No compression specified
85 00:56:00.500214 progress 69 % (0 MB)
86 00:56:00.500496 progress 100 % (0 MB)
87 00:56:00.500663 0 MB downloaded in 0.00 s (20.70 MB/s)
88 00:56:00.500803 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:56:00.501055 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:56:00.501160 start: 1.4 download-retry (timeout 00:09:57) [common]
92 00:56:00.501256 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 00:56:00.501390 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 00:56:00.501486 saving as /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/nfsrootfs/full.rootfs.tar
95 00:56:00.501583 total size: 198084472 (188 MB)
96 00:56:00.501682 Using unxz to decompress xz
97 00:56:00.506258 progress 0 % (0 MB)
98 00:56:01.100351 progress 5 % (9 MB)
99 00:56:01.618249 progress 10 % (18 MB)
100 00:56:02.217184 progress 15 % (28 MB)
101 00:56:02.515920 progress 20 % (37 MB)
102 00:56:02.994485 progress 25 % (47 MB)
103 00:56:03.596296 progress 30 % (56 MB)
104 00:56:04.166107 progress 35 % (66 MB)
105 00:56:04.759341 progress 40 % (75 MB)
106 00:56:05.380615 progress 45 % (85 MB)
107 00:56:06.009323 progress 50 % (94 MB)
108 00:56:06.639060 progress 55 % (103 MB)
109 00:56:07.317515 progress 60 % (113 MB)
110 00:56:07.747799 progress 65 % (122 MB)
111 00:56:07.865001 progress 70 % (132 MB)
112 00:56:08.021769 progress 75 % (141 MB)
113 00:56:08.104104 progress 80 % (151 MB)
114 00:56:08.154480 progress 85 % (160 MB)
115 00:56:08.256831 progress 90 % (170 MB)
116 00:56:08.648507 progress 95 % (179 MB)
117 00:56:09.266632 progress 100 % (188 MB)
118 00:56:09.271316 188 MB downloaded in 8.77 s (21.54 MB/s)
119 00:56:09.271746 end: 1.4.1 http-download (duration 00:00:09) [common]
121 00:56:09.272164 end: 1.4 download-retry (duration 00:00:09) [common]
122 00:56:09.272297 start: 1.5 download-retry (timeout 00:09:48) [common]
123 00:56:09.272425 start: 1.5.1 http-download (timeout 00:09:48) [common]
124 00:56:09.272674 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:56:09.272831 saving as /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/modules/modules.tar
126 00:56:09.272941 total size: 8625444 (8 MB)
127 00:56:09.273044 Using unxz to decompress xz
128 00:56:09.278634 progress 0 % (0 MB)
129 00:56:09.300247 progress 5 % (0 MB)
130 00:56:09.324162 progress 10 % (0 MB)
131 00:56:09.348350 progress 15 % (1 MB)
132 00:56:09.372774 progress 20 % (1 MB)
133 00:56:09.397543 progress 25 % (2 MB)
134 00:56:09.423945 progress 30 % (2 MB)
135 00:56:09.450955 progress 35 % (2 MB)
136 00:56:09.476388 progress 40 % (3 MB)
137 00:56:09.503138 progress 45 % (3 MB)
138 00:56:09.530020 progress 50 % (4 MB)
139 00:56:09.556520 progress 55 % (4 MB)
140 00:56:09.583388 progress 60 % (4 MB)
141 00:56:09.613240 progress 65 % (5 MB)
142 00:56:09.640628 progress 70 % (5 MB)
143 00:56:09.666274 progress 75 % (6 MB)
144 00:56:09.695417 progress 80 % (6 MB)
145 00:56:09.723365 progress 85 % (7 MB)
146 00:56:09.750278 progress 90 % (7 MB)
147 00:56:09.783573 progress 95 % (7 MB)
148 00:56:09.814581 progress 100 % (8 MB)
149 00:56:09.820025 8 MB downloaded in 0.55 s (15.04 MB/s)
150 00:56:09.820455 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:56:09.820905 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:56:09.821052 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 00:56:09.821209 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 00:56:13.573660 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx
156 00:56:13.573876 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:56:13.573983 start: 1.6.2 lava-overlay (timeout 00:09:44) [common]
158 00:56:13.574168 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b
159 00:56:13.574305 makedir: /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin
160 00:56:13.574411 makedir: /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/tests
161 00:56:13.574512 makedir: /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/results
162 00:56:13.574615 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-add-keys
163 00:56:13.574764 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-add-sources
164 00:56:13.574896 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-background-process-start
165 00:56:13.575027 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-background-process-stop
166 00:56:13.575154 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-common-functions
167 00:56:13.575279 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-echo-ipv4
168 00:56:13.575405 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-install-packages
169 00:56:13.575530 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-installed-packages
170 00:56:13.575653 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-os-build
171 00:56:13.575960 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-probe-channel
172 00:56:13.576087 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-probe-ip
173 00:56:13.576214 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-target-ip
174 00:56:13.576340 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-target-mac
175 00:56:13.576465 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-target-storage
176 00:56:13.576593 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-case
177 00:56:13.576723 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-event
178 00:56:13.576849 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-feedback
179 00:56:13.576975 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-raise
180 00:56:13.577103 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-reference
181 00:56:13.577230 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-runner
182 00:56:13.577356 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-set
183 00:56:13.577482 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-test-shell
184 00:56:13.577609 Updating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-add-keys (debian)
185 00:56:13.577765 Updating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-add-sources (debian)
186 00:56:13.577909 Updating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-install-packages (debian)
187 00:56:13.578051 Updating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-installed-packages (debian)
188 00:56:13.578191 Updating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/bin/lava-os-build (debian)
189 00:56:13.578315 Creating /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/environment
190 00:56:13.578417 LAVA metadata
191 00:56:13.578490 - LAVA_JOB_ID=12571069
192 00:56:13.578554 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:56:13.578661 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 00:56:13.578729 skipped lava-vland-overlay
195 00:56:13.578803 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:56:13.578884 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 00:56:13.578946 skipped lava-multinode-overlay
198 00:56:13.579033 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:56:13.579112 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 00:56:13.579186 Loading test definitions
201 00:56:13.579278 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 00:56:13.579349 Using /lava-12571069 at stage 0
203 00:56:13.579638 uuid=12571069_1.6.2.3.1 testdef=None
204 00:56:13.579768 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:56:13.579853 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 00:56:13.580371 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:56:13.580587 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 00:56:13.581188 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:56:13.581415 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 00:56:13.581954 runner path: /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/0/tests/0_timesync-off test_uuid 12571069_1.6.2.3.1
213 00:56:13.582109 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:56:13.582329 start: 1.6.2.3.5 git-repo-action (timeout 00:09:44) [common]
216 00:56:13.582400 Using /lava-12571069 at stage 0
217 00:56:13.582496 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:56:13.582575 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/0/tests/1_kselftest-alsa'
219 00:56:17.870637 Running '/usr/bin/git checkout kernelci.org
220 00:56:18.020623 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 00:56:18.021387 uuid=12571069_1.6.2.3.5 testdef=None
222 00:56:18.021557 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 00:56:18.021806 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 00:56:18.022581 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:56:18.022813 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 00:56:18.023830 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:56:18.024065 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 00:56:18.024995 runner path: /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/0/tests/1_kselftest-alsa test_uuid 12571069_1.6.2.3.5
232 00:56:18.025088 BOARD='mt8192-asurada-spherion-r0'
233 00:56:18.025153 BRANCH='cip'
234 00:56:18.025213 SKIPFILE='/dev/null'
235 00:56:18.025270 SKIP_INSTALL='True'
236 00:56:18.025325 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:56:18.025382 TST_CASENAME=''
238 00:56:18.025437 TST_CMDFILES='alsa'
239 00:56:18.025580 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:56:18.025783 Creating lava-test-runner.conf files
242 00:56:18.025846 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571069/lava-overlay-43yqos9b/lava-12571069/0 for stage 0
243 00:56:18.025939 - 0_timesync-off
244 00:56:18.026008 - 1_kselftest-alsa
245 00:56:18.026111 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 00:56:18.026199 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 00:56:25.678935 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:56:25.679088 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 00:56:25.679178 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:56:25.679275 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 00:56:25.679365 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 00:56:25.851913 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:56:25.852301 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 00:56:25.852508 extracting modules file /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx
255 00:56:26.076139 extracting modules file /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571069/extract-overlay-ramdisk-aw0t8lbv/ramdisk
256 00:56:26.305141 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:56:26.305314 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 00:56:26.305410 [common] Applying overlay to NFS
259 00:56:26.305482 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571069/compress-overlay-lorjh3rl/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx
260 00:56:27.236422 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:56:27.236583 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 00:56:27.236673 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:56:27.236760 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 00:56:27.236838 Building ramdisk /var/lib/lava/dispatcher/tmp/12571069/extract-overlay-ramdisk-aw0t8lbv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571069/extract-overlay-ramdisk-aw0t8lbv/ramdisk
265 00:56:27.598781 >> 130539 blocks
266 00:56:29.641048 rename /var/lib/lava/dispatcher/tmp/12571069/extract-overlay-ramdisk-aw0t8lbv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/ramdisk/ramdisk.cpio.gz
267 00:56:29.641524 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:56:29.641675 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 00:56:29.641809 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 00:56:29.641923 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/kernel/Image'
271 00:56:43.465375 Returned 0 in 13 seconds
272 00:56:43.566010 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/kernel/image.itb
273 00:56:43.954639 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:56:43.955027 output: Created: Fri Jan 19 00:56:43 2024
275 00:56:43.955113 output: Image 0 (kernel-1)
276 00:56:43.955178 output: Description:
277 00:56:43.955241 output: Created: Fri Jan 19 00:56:43 2024
278 00:56:43.955301 output: Type: Kernel Image
279 00:56:43.955362 output: Compression: lzma compressed
280 00:56:43.955421 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
281 00:56:43.955480 output: Architecture: AArch64
282 00:56:43.955539 output: OS: Linux
283 00:56:43.955597 output: Load Address: 0x00000000
284 00:56:43.955659 output: Entry Point: 0x00000000
285 00:56:43.955760 output: Hash algo: crc32
286 00:56:43.955818 output: Hash value: a52aa383
287 00:56:43.955876 output: Image 1 (fdt-1)
288 00:56:43.955933 output: Description: mt8192-asurada-spherion-r0
289 00:56:43.955988 output: Created: Fri Jan 19 00:56:43 2024
290 00:56:43.956044 output: Type: Flat Device Tree
291 00:56:43.956097 output: Compression: uncompressed
292 00:56:43.956150 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 00:56:43.956237 output: Architecture: AArch64
294 00:56:43.956325 output: Hash algo: crc32
295 00:56:43.956410 output: Hash value: cc4352de
296 00:56:43.956492 output: Image 2 (ramdisk-1)
297 00:56:43.956549 output: Description: unavailable
298 00:56:43.956608 output: Created: Fri Jan 19 00:56:43 2024
299 00:56:43.956665 output: Type: RAMDisk Image
300 00:56:43.956718 output: Compression: Unknown Compression
301 00:56:43.956773 output: Data Size: 18767814 Bytes = 18327.94 KiB = 17.90 MiB
302 00:56:43.956855 output: Architecture: AArch64
303 00:56:43.956913 output: OS: Linux
304 00:56:43.956966 output: Load Address: unavailable
305 00:56:43.957019 output: Entry Point: unavailable
306 00:56:43.957071 output: Hash algo: crc32
307 00:56:43.957124 output: Hash value: e6ccd5c1
308 00:56:43.957176 output: Default Configuration: 'conf-1'
309 00:56:43.957232 output: Configuration 0 (conf-1)
310 00:56:43.957286 output: Description: mt8192-asurada-spherion-r0
311 00:56:43.957339 output: Kernel: kernel-1
312 00:56:43.957392 output: Init Ramdisk: ramdisk-1
313 00:56:43.957445 output: FDT: fdt-1
314 00:56:43.957497 output: Loadables: kernel-1
315 00:56:43.957553 output:
316 00:56:43.957762 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:56:43.957862 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:56:43.957968 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 00:56:43.958062 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
320 00:56:43.958146 No LXC device requested
321 00:56:43.958225 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:56:43.958306 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
323 00:56:43.958385 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:56:43.958455 Checking files for TFTP limit of 4294967296 bytes.
325 00:56:43.958982 end: 1 tftp-deploy (duration 00:00:47) [common]
326 00:56:43.959089 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:56:43.959182 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:56:43.959316 substitutions:
329 00:56:43.959388 - {DTB}: 12571069/tftp-deploy-y3atqli7/dtb/mt8192-asurada-spherion-r0.dtb
330 00:56:43.959452 - {INITRD}: 12571069/tftp-deploy-y3atqli7/ramdisk/ramdisk.cpio.gz
331 00:56:43.959516 - {KERNEL}: 12571069/tftp-deploy-y3atqli7/kernel/Image
332 00:56:43.959577 - {LAVA_MAC}: None
333 00:56:43.959634 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx
334 00:56:43.959731 - {NFS_SERVER_IP}: 192.168.201.1
335 00:56:43.959789 - {PRESEED_CONFIG}: None
336 00:56:43.959848 - {PRESEED_LOCAL}: None
337 00:56:43.959903 - {RAMDISK}: 12571069/tftp-deploy-y3atqli7/ramdisk/ramdisk.cpio.gz
338 00:56:43.959957 - {ROOT_PART}: None
339 00:56:43.960011 - {ROOT}: None
340 00:56:43.960065 - {SERVER_IP}: 192.168.201.1
341 00:56:43.960121 - {TEE}: None
342 00:56:43.960175 Parsed boot commands:
343 00:56:43.960230 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:56:43.960419 Parsed boot commands: tftpboot 192.168.201.1 12571069/tftp-deploy-y3atqli7/kernel/image.itb 12571069/tftp-deploy-y3atqli7/kernel/cmdline
345 00:56:43.960509 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:56:43.960592 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:56:43.960716 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:56:43.960808 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:56:43.960881 Not connected, no need to disconnect.
350 00:56:43.960954 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:56:43.961039 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:56:43.961107 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 00:56:43.965405 Setting prompt string to ['lava-test: # ']
354 00:56:43.965791 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:56:43.965903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:56:43.966020 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:56:43.966128 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:56:43.966364 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 00:56:49.096661 >> Command sent successfully.
360 00:56:49.098981 Returned 0 in 5 seconds
361 00:56:49.199348 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 00:56:49.199700 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 00:56:49.199826 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 00:56:49.199924 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:56:49.199990 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:56:49.200064 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:56:49.200328 [Enter `^Ec?' for help]
369 00:56:49.374044
370 00:56:49.374269
371 00:56:49.374372 F0: 102B 0000
372 00:56:49.374581
373 00:56:49.374705 F3: 1001 0000 [0200]
374 00:56:49.378145
375 00:56:49.378252 F3: 1001 0000
376 00:56:49.378346
377 00:56:49.378437 F7: 102D 0000
378 00:56:49.378526
379 00:56:49.380678 F1: 0000 0000
380 00:56:49.380779
381 00:56:49.380872 V0: 0000 0000 [0001]
382 00:56:49.380961
383 00:56:49.384473 00: 0007 8000
384 00:56:49.384552
385 00:56:49.384614 01: 0000 0000
386 00:56:49.384677
387 00:56:49.387315 BP: 0C00 0209 [0000]
388 00:56:49.387428
389 00:56:49.387525 G0: 1182 0000
390 00:56:49.387616
391 00:56:49.390804 EC: 0000 0021 [4000]
392 00:56:49.390871
393 00:56:49.390934 S7: 0000 0000 [0000]
394 00:56:49.390995
395 00:56:49.394372 CC: 0000 0000 [0001]
396 00:56:49.394471
397 00:56:49.394559 T0: 0000 0040 [010F]
398 00:56:49.394648
399 00:56:49.394733 Jump to BL
400 00:56:49.398005
401 00:56:49.420910
402 00:56:49.421019
403 00:56:49.421112
404 00:56:49.428538 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 00:56:49.432538 ARM64: Exception handlers installed.
406 00:56:49.435417 ARM64: Testing exception
407 00:56:49.439093 ARM64: Done test exception
408 00:56:49.446658 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 00:56:49.456473 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 00:56:49.463011 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 00:56:49.473154 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 00:56:49.479296 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 00:56:49.485944 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 00:56:49.497385 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 00:56:49.504051 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 00:56:49.524390 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 00:56:49.527946 WDT: Last reset was cold boot
418 00:56:49.530467 SPI1(PAD0) initialized at 2873684 Hz
419 00:56:49.534262 SPI5(PAD0) initialized at 992727 Hz
420 00:56:49.537557 VBOOT: Loading verstage.
421 00:56:49.544176 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 00:56:49.546976 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 00:56:49.550515 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 00:56:49.554124 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 00:56:49.561355 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 00:56:49.568176 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 00:56:49.579309 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 00:56:49.579416
429 00:56:49.579520
430 00:56:49.589203 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 00:56:49.592588 ARM64: Exception handlers installed.
432 00:56:49.595761 ARM64: Testing exception
433 00:56:49.595868 ARM64: Done test exception
434 00:56:49.602121 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 00:56:49.605569 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 00:56:49.620074 Probing TPM: . done!
437 00:56:49.620159 TPM ready after 0 ms
438 00:56:49.627046 Connected to device vid:did:rid of 1ae0:0028:00
439 00:56:49.633126 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 00:56:49.674522 Initialized TPM device CR50 revision 0
441 00:56:49.685713 tlcl_send_startup: Startup return code is 0
442 00:56:49.685830 TPM: setup succeeded
443 00:56:49.697097 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 00:56:49.705876 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:56:49.716029 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 00:56:49.724820 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 00:56:49.728212 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 00:56:49.731474 in-header: 03 07 00 00 08 00 00 00
449 00:56:49.734721 in-data: aa e4 47 04 13 02 00 00
450 00:56:49.737854 Chrome EC: UHEPI supported
451 00:56:49.744645 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 00:56:49.747829 in-header: 03 ad 00 00 08 00 00 00
453 00:56:49.751366 in-data: 00 20 20 08 00 00 00 00
454 00:56:49.751442 Phase 1
455 00:56:49.757720 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 00:56:49.760955 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 00:56:49.768057 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 00:56:49.771054 Recovery requested (1009000e)
459 00:56:49.774997 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 00:56:49.784225 tlcl_extend: response is 0
461 00:56:49.792253 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 00:56:49.797405 tlcl_extend: response is 0
463 00:56:49.803645 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 00:56:49.824226 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 00:56:49.831434 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 00:56:49.831517
467 00:56:49.831582
468 00:56:49.841899 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 00:56:49.844821 ARM64: Exception handlers installed.
470 00:56:49.848088 ARM64: Testing exception
471 00:56:49.848176 ARM64: Done test exception
472 00:56:49.870281 pmic_efuse_setting: Set efuses in 11 msecs
473 00:56:49.873706 pmwrap_interface_init: Select PMIF_VLD_RDY
474 00:56:49.877761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 00:56:49.884405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 00:56:49.887233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 00:56:49.893935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 00:56:49.897646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 00:56:49.904435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 00:56:49.908370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 00:56:49.914771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 00:56:49.918734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 00:56:49.921235 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 00:56:49.928236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 00:56:49.931024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 00:56:49.934410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 00:56:49.941414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 00:56:49.948552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 00:56:49.954772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 00:56:49.958050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 00:56:49.964947 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 00:56:49.971034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 00:56:49.977685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 00:56:49.981480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 00:56:49.988685 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 00:56:49.992067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 00:56:49.999144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 00:56:50.002607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 00:56:50.008672 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 00:56:50.016133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 00:56:50.019283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 00:56:50.023114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 00:56:50.029436 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 00:56:50.032834 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 00:56:50.040246 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 00:56:50.043277 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 00:56:50.050100 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 00:56:50.053525 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 00:56:50.060129 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 00:56:50.063622 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 00:56:50.067884 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 00:56:50.074828 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 00:56:50.078038 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 00:56:50.082180 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 00:56:50.085109 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 00:56:50.092093 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 00:56:50.094999 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 00:56:50.098475 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 00:56:50.105349 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 00:56:50.108717 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 00:56:50.111678 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 00:56:50.118602 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 00:56:50.121599 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 00:56:50.124982 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 00:56:50.131802 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 00:56:50.141821 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 00:56:50.145117 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 00:56:50.155240 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 00:56:50.161590 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 00:56:50.168271 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 00:56:50.171353 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:56:50.174620 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 00:56:50.182740 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x14
534 00:56:50.189922 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 00:56:50.192522 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 00:56:50.199067 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 00:56:50.207074 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 00:56:50.216606 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 00:56:50.226326 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 00:56:50.235569 [RTC]rtc_get_frequency_meter,154: input=13, output=804
541 00:56:50.245535 [RTC]rtc_get_frequency_meter,154: input=12, output=789
542 00:56:50.254455 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 00:56:50.264344 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 00:56:50.267479 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 00:56:50.274801 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 00:56:50.278187 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 00:56:50.281639 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 00:56:50.287987 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 00:56:50.291596 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 00:56:50.294490 ADC[4]: Raw value=901922 ID=7
551 00:56:50.294565 ADC[3]: Raw value=214021 ID=1
552 00:56:50.297795 RAM Code: 0x71
553 00:56:50.301421 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 00:56:50.308002 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 00:56:50.314268 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 00:56:50.321196 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 00:56:50.325175 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 00:56:50.327962 in-header: 03 07 00 00 08 00 00 00
559 00:56:50.331155 in-data: aa e4 47 04 13 02 00 00
560 00:56:50.334274 Chrome EC: UHEPI supported
561 00:56:50.340869 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 00:56:50.344223 in-header: 03 dd 00 00 08 00 00 00
563 00:56:50.347595 in-data: 90 20 60 08 00 00 00 00
564 00:56:50.351201 MRC: failed to locate region type 0.
565 00:56:50.357779 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 00:56:50.361249 DRAM-K: Running full calibration
567 00:56:50.368202 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 00:56:50.368286 header.status = 0x0
569 00:56:50.371036 header.version = 0x6 (expected: 0x6)
570 00:56:50.374773 header.size = 0xd00 (expected: 0xd00)
571 00:56:50.377758 header.flags = 0x0
572 00:56:50.384399 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 00:56:50.400957 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 00:56:50.407532 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 00:56:50.411492 dram_init: ddr_geometry: 2
576 00:56:50.414362 [EMI] MDL number = 2
577 00:56:50.414493 [EMI] Get MDL freq = 0
578 00:56:50.418076 dram_init: ddr_type: 0
579 00:56:50.418179 is_discrete_lpddr4: 1
580 00:56:50.420955 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 00:56:50.421055
582 00:56:50.421185
583 00:56:50.424483 [Bian_co] ETT version 0.0.0.1
584 00:56:50.431089 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 00:56:50.431198
586 00:56:50.434484 dramc_set_vcore_voltage set vcore to 650000
587 00:56:50.437788 Read voltage for 800, 4
588 00:56:50.437890 Vio18 = 0
589 00:56:50.437982 Vcore = 650000
590 00:56:50.441562 Vdram = 0
591 00:56:50.441661 Vddq = 0
592 00:56:50.441751 Vmddr = 0
593 00:56:50.444307 dram_init: config_dvfs: 1
594 00:56:50.447595 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 00:56:50.454114 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 00:56:50.458443 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 00:56:50.460642 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 00:56:50.464588 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 00:56:50.467485 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 00:56:50.471159 MEM_TYPE=3, freq_sel=18
601 00:56:50.474287 sv_algorithm_assistance_LP4_1600
602 00:56:50.477275 ============ PULL DRAM RESETB DOWN ============
603 00:56:50.484537 ========== PULL DRAM RESETB DOWN end =========
604 00:56:50.487503 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 00:56:50.490809 ===================================
606 00:56:50.493994 LPDDR4 DRAM CONFIGURATION
607 00:56:50.497201 ===================================
608 00:56:50.497274 EX_ROW_EN[0] = 0x0
609 00:56:50.500927 EX_ROW_EN[1] = 0x0
610 00:56:50.500996 LP4Y_EN = 0x0
611 00:56:50.504236 WORK_FSP = 0x0
612 00:56:50.504334 WL = 0x2
613 00:56:50.507583 RL = 0x2
614 00:56:50.507698 BL = 0x2
615 00:56:50.510570 RPST = 0x0
616 00:56:50.510666 RD_PRE = 0x0
617 00:56:50.514055 WR_PRE = 0x1
618 00:56:50.517743 WR_PST = 0x0
619 00:56:50.517813 DBI_WR = 0x0
620 00:56:50.520910 DBI_RD = 0x0
621 00:56:50.520978 OTF = 0x1
622 00:56:50.523830 ===================================
623 00:56:50.527458 ===================================
624 00:56:50.527527 ANA top config
625 00:56:50.530987 ===================================
626 00:56:50.533828 DLL_ASYNC_EN = 0
627 00:56:50.537252 ALL_SLAVE_EN = 1
628 00:56:50.540726 NEW_RANK_MODE = 1
629 00:56:50.544086 DLL_IDLE_MODE = 1
630 00:56:50.544157 LP45_APHY_COMB_EN = 1
631 00:56:50.547958 TX_ODT_DIS = 1
632 00:56:50.550200 NEW_8X_MODE = 1
633 00:56:50.553531 ===================================
634 00:56:50.557505 ===================================
635 00:56:50.560104 data_rate = 1600
636 00:56:50.563728 CKR = 1
637 00:56:50.563807 DQ_P2S_RATIO = 8
638 00:56:50.566957 ===================================
639 00:56:50.570159 CA_P2S_RATIO = 8
640 00:56:50.574042 DQ_CA_OPEN = 0
641 00:56:50.577023 DQ_SEMI_OPEN = 0
642 00:56:50.580499 CA_SEMI_OPEN = 0
643 00:56:50.583572 CA_FULL_RATE = 0
644 00:56:50.583701 DQ_CKDIV4_EN = 1
645 00:56:50.587016 CA_CKDIV4_EN = 1
646 00:56:50.590074 CA_PREDIV_EN = 0
647 00:56:50.593648 PH8_DLY = 0
648 00:56:50.597062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 00:56:50.600700 DQ_AAMCK_DIV = 4
650 00:56:50.600773 CA_AAMCK_DIV = 4
651 00:56:50.603692 CA_ADMCK_DIV = 4
652 00:56:50.607096 DQ_TRACK_CA_EN = 0
653 00:56:50.610104 CA_PICK = 800
654 00:56:50.614008 CA_MCKIO = 800
655 00:56:50.617241 MCKIO_SEMI = 0
656 00:56:50.619912 PLL_FREQ = 3068
657 00:56:50.619991 DQ_UI_PI_RATIO = 32
658 00:56:50.623619 CA_UI_PI_RATIO = 0
659 00:56:50.627196 ===================================
660 00:56:50.630282 ===================================
661 00:56:50.633545 memory_type:LPDDR4
662 00:56:50.636785 GP_NUM : 10
663 00:56:50.636863 SRAM_EN : 1
664 00:56:50.640168 MD32_EN : 0
665 00:56:50.643624 ===================================
666 00:56:50.643736 [ANA_INIT] >>>>>>>>>>>>>>
667 00:56:50.646882 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 00:56:50.650052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 00:56:50.653560 ===================================
670 00:56:50.657056 data_rate = 1600,PCW = 0X7600
671 00:56:50.660228 ===================================
672 00:56:50.663217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 00:56:50.669842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:56:50.676503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 00:56:50.679449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 00:56:50.682839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:56:50.686114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 00:56:50.689553 [ANA_INIT] flow start
679 00:56:50.689627 [ANA_INIT] PLL >>>>>>>>
680 00:56:50.692931 [ANA_INIT] PLL <<<<<<<<
681 00:56:50.696750 [ANA_INIT] MIDPI >>>>>>>>
682 00:56:50.696827 [ANA_INIT] MIDPI <<<<<<<<
683 00:56:50.699997 [ANA_INIT] DLL >>>>>>>>
684 00:56:50.703215 [ANA_INIT] flow end
685 00:56:50.706070 ============ LP4 DIFF to SE enter ============
686 00:56:50.709470 ============ LP4 DIFF to SE exit ============
687 00:56:50.713219 [ANA_INIT] <<<<<<<<<<<<<
688 00:56:50.715786 [Flow] Enable top DCM control >>>>>
689 00:56:50.719327 [Flow] Enable top DCM control <<<<<
690 00:56:50.722922 Enable DLL master slave shuffle
691 00:56:50.728944 ==============================================================
692 00:56:50.729024 Gating Mode config
693 00:56:50.735972 ==============================================================
694 00:56:50.736078 Config description:
695 00:56:50.746017 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 00:56:50.752332 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 00:56:50.759124 SELPH_MODE 0: By rank 1: By Phase
698 00:56:50.762575 ==============================================================
699 00:56:50.765783 GAT_TRACK_EN = 1
700 00:56:50.769095 RX_GATING_MODE = 2
701 00:56:50.772598 RX_GATING_TRACK_MODE = 2
702 00:56:50.775616 SELPH_MODE = 1
703 00:56:50.778901 PICG_EARLY_EN = 1
704 00:56:50.782687 VALID_LAT_VALUE = 1
705 00:56:50.786178 ==============================================================
706 00:56:50.788955 Enter into Gating configuration >>>>
707 00:56:50.792469 Exit from Gating configuration <<<<
708 00:56:50.795353 Enter into DVFS_PRE_config >>>>>
709 00:56:50.809013 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 00:56:50.813190 Exit from DVFS_PRE_config <<<<<
711 00:56:50.815233 Enter into PICG configuration >>>>
712 00:56:50.819074 Exit from PICG configuration <<<<
713 00:56:50.819178 [RX_INPUT] configuration >>>>>
714 00:56:50.821930 [RX_INPUT] configuration <<<<<
715 00:56:50.828621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 00:56:50.832754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 00:56:50.839292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 00:56:50.846130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 00:56:50.853342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 00:56:50.857167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 00:56:50.863793 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 00:56:50.867430 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 00:56:50.871559 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 00:56:50.874777 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 00:56:50.878581 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 00:56:50.881792 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 00:56:50.885832 ===================================
728 00:56:50.889652 LPDDR4 DRAM CONFIGURATION
729 00:56:50.893293 ===================================
730 00:56:50.893424 EX_ROW_EN[0] = 0x0
731 00:56:50.896735 EX_ROW_EN[1] = 0x0
732 00:56:50.896815 LP4Y_EN = 0x0
733 00:56:50.900241 WORK_FSP = 0x0
734 00:56:50.900315 WL = 0x2
735 00:56:50.904322 RL = 0x2
736 00:56:50.904422 BL = 0x2
737 00:56:50.907693 RPST = 0x0
738 00:56:50.907783 RD_PRE = 0x0
739 00:56:50.911227 WR_PRE = 0x1
740 00:56:50.911303 WR_PST = 0x0
741 00:56:50.914920 DBI_WR = 0x0
742 00:56:50.914994 DBI_RD = 0x0
743 00:56:50.918700 OTF = 0x1
744 00:56:50.918801 ===================================
745 00:56:50.922446 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 00:56:50.930157 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 00:56:50.933102 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 00:56:50.936902 ===================================
749 00:56:50.936982 LPDDR4 DRAM CONFIGURATION
750 00:56:50.940813 ===================================
751 00:56:50.944012 EX_ROW_EN[0] = 0x10
752 00:56:50.944089 EX_ROW_EN[1] = 0x0
753 00:56:50.948105 LP4Y_EN = 0x0
754 00:56:50.948182 WORK_FSP = 0x0
755 00:56:50.951252 WL = 0x2
756 00:56:50.951371 RL = 0x2
757 00:56:50.955656 BL = 0x2
758 00:56:50.955766 RPST = 0x0
759 00:56:50.959141 RD_PRE = 0x0
760 00:56:50.959253 WR_PRE = 0x1
761 00:56:50.962642 WR_PST = 0x0
762 00:56:50.962737 DBI_WR = 0x0
763 00:56:50.966463 DBI_RD = 0x0
764 00:56:50.966583 OTF = 0x1
765 00:56:50.970112 ===================================
766 00:56:50.976725 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 00:56:50.980460 nWR fixed to 40
768 00:56:50.980558 [ModeRegInit_LP4] CH0 RK0
769 00:56:50.984265 [ModeRegInit_LP4] CH0 RK1
770 00:56:50.988159 [ModeRegInit_LP4] CH1 RK0
771 00:56:50.988266 [ModeRegInit_LP4] CH1 RK1
772 00:56:50.992338 match AC timing 13
773 00:56:50.995461 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 00:56:50.999058 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 00:56:51.002003 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 00:56:51.009795 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 00:56:51.012517 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 00:56:51.015941 [EMI DOE] emi_dcm 0
779 00:56:51.019391 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 00:56:51.019488 ==
781 00:56:51.022745 Dram Type= 6, Freq= 0, CH_0, rank 0
782 00:56:51.025792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 00:56:51.025863 ==
784 00:56:51.032957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 00:56:51.038868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 00:56:51.047163 [CA 0] Center 37 (6~68) winsize 63
787 00:56:51.050083 [CA 1] Center 36 (6~67) winsize 62
788 00:56:51.053871 [CA 2] Center 34 (4~65) winsize 62
789 00:56:51.057052 [CA 3] Center 34 (4~65) winsize 62
790 00:56:51.060530 [CA 4] Center 33 (3~64) winsize 62
791 00:56:51.063859 [CA 5] Center 33 (3~64) winsize 62
792 00:56:51.063946
793 00:56:51.066908 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 00:56:51.067011
795 00:56:51.070104 [CATrainingPosCal] consider 1 rank data
796 00:56:51.073297 u2DelayCellTimex100 = 270/100 ps
797 00:56:51.076927 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 00:56:51.083578 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 00:56:51.086743 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 00:56:51.090251 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 00:56:51.093606 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 00:56:51.096724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 00:56:51.096828
804 00:56:51.100346 CA PerBit enable=1, Macro0, CA PI delay=33
805 00:56:51.100439
806 00:56:51.102995 [CBTSetCACLKResult] CA Dly = 33
807 00:56:51.106636 CS Dly: 6 (0~37)
808 00:56:51.106742 ==
809 00:56:51.109668 Dram Type= 6, Freq= 0, CH_0, rank 1
810 00:56:51.112882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 00:56:51.112960 ==
812 00:56:51.119969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 00:56:51.123499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 00:56:51.133060 [CA 0] Center 37 (6~68) winsize 63
815 00:56:51.136167 [CA 1] Center 37 (7~68) winsize 62
816 00:56:51.140244 [CA 2] Center 34 (4~65) winsize 62
817 00:56:51.143584 [CA 3] Center 34 (4~65) winsize 62
818 00:56:51.146310 [CA 4] Center 33 (3~64) winsize 62
819 00:56:51.149801 [CA 5] Center 33 (3~64) winsize 62
820 00:56:51.149876
821 00:56:51.153485 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 00:56:51.153566
823 00:56:51.156422 [CATrainingPosCal] consider 2 rank data
824 00:56:51.159966 u2DelayCellTimex100 = 270/100 ps
825 00:56:51.163216 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 00:56:51.169433 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 00:56:51.172730 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 00:56:51.176209 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 00:56:51.179845 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 00:56:51.183474 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 00:56:51.183616
832 00:56:51.187044 CA PerBit enable=1, Macro0, CA PI delay=33
833 00:56:51.187142
834 00:56:51.191447 [CBTSetCACLKResult] CA Dly = 33
835 00:56:51.191546 CS Dly: 6 (0~38)
836 00:56:51.191637
837 00:56:51.194740 ----->DramcWriteLeveling(PI) begin...
838 00:56:51.194815 ==
839 00:56:51.198536 Dram Type= 6, Freq= 0, CH_0, rank 0
840 00:56:51.201696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 00:56:51.201796 ==
842 00:56:51.205328 Write leveling (Byte 0): 33 => 33
843 00:56:51.208724 Write leveling (Byte 1): 28 => 28
844 00:56:51.212610 DramcWriteLeveling(PI) end<-----
845 00:56:51.212684
846 00:56:51.212753 ==
847 00:56:51.215266 Dram Type= 6, Freq= 0, CH_0, rank 0
848 00:56:51.218919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 00:56:51.219021 ==
850 00:56:51.222216 [Gating] SW mode calibration
851 00:56:51.228914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 00:56:51.235431 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 00:56:51.238743 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 00:56:51.242116 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 00:56:51.248725 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 00:56:51.252132 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:56:51.255854 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:56:51.261969 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:56:51.265184 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:56:51.268470 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:56:51.275101 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:56:51.278305 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:56:51.282275 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:56:51.288746 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:56:51.291955 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:56:51.295378 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:56:51.301896 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 00:56:51.305518 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 00:56:51.308500 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:56:51.314984 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 00:56:51.318220 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 00:56:51.321650 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 00:56:51.328493 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:56:51.331712 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:56:51.334655 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 00:56:51.341499 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 00:56:51.344464 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 00:56:51.349034 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 00:56:51.354711 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
880 00:56:51.358202 0 9 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
881 00:56:51.361160 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:56:51.368564 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 00:56:51.371474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 00:56:51.374706 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 00:56:51.378228 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 00:56:51.384479 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
887 00:56:51.388095 0 10 8 | B1->B0 | 3333 2828 | 0 0 | (0 1) (1 0)
888 00:56:51.390952 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
889 00:56:51.397746 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:56:51.400947 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:56:51.404109 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 00:56:51.410931 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 00:56:51.414469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 00:56:51.417796 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
895 00:56:51.424016 0 11 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (1 1)
896 00:56:51.427829 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
897 00:56:51.430946 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:56:51.437933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:56:51.440792 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 00:56:51.443912 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 00:56:51.450698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 00:56:51.454854 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 00:56:51.457488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
904 00:56:51.464009 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:56:51.467395 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:56:51.471220 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:56:51.477307 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:56:51.480488 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:56:51.483788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:56:51.490412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:56:51.493993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:56:51.496898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:56:51.503770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:56:51.507098 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 00:56:51.510337 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 00:56:51.516856 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 00:56:51.520539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 00:56:51.524379 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 00:56:51.530547 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 00:56:51.533632 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 00:56:51.536944 Total UI for P1: 0, mck2ui 16
922 00:56:51.540550 best dqsien dly found for B0: ( 0, 14, 8)
923 00:56:51.543873 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 00:56:51.546964 Total UI for P1: 0, mck2ui 16
925 00:56:51.550104 best dqsien dly found for B1: ( 0, 14, 12)
926 00:56:51.553572 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 00:56:51.556951 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 00:56:51.557047
929 00:56:51.560217 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 00:56:51.566801 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 00:56:51.566906 [Gating] SW calibration Done
932 00:56:51.567002 ==
933 00:56:51.570673 Dram Type= 6, Freq= 0, CH_0, rank 0
934 00:56:51.577339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 00:56:51.577441 ==
936 00:56:51.577534 RX Vref Scan: 0
937 00:56:51.577625
938 00:56:51.580693 RX Vref 0 -> 0, step: 1
939 00:56:51.580788
940 00:56:51.583980 RX Delay -130 -> 252, step: 16
941 00:56:51.587552 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 00:56:51.590558 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 00:56:51.594008 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 00:56:51.597113 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 00:56:51.603547 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 00:56:51.606925 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 00:56:51.610551 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 00:56:51.613641 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 00:56:51.617198 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 00:56:51.623306 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
951 00:56:51.626775 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 00:56:51.630193 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 00:56:51.633746 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 00:56:51.640481 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
955 00:56:51.643656 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 00:56:51.646707 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 00:56:51.646804 ==
958 00:56:51.650359 Dram Type= 6, Freq= 0, CH_0, rank 0
959 00:56:51.653540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 00:56:51.653642 ==
961 00:56:51.656570 DQS Delay:
962 00:56:51.656671 DQS0 = 0, DQS1 = 0
963 00:56:51.660785 DQM Delay:
964 00:56:51.660890 DQM0 = 85, DQM1 = 75
965 00:56:51.660982 DQ Delay:
966 00:56:51.664249 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 00:56:51.667650 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
968 00:56:51.671297 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
969 00:56:51.674609 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
970 00:56:51.674704
971 00:56:51.674780
972 00:56:51.674840 ==
973 00:56:51.678955 Dram Type= 6, Freq= 0, CH_0, rank 0
974 00:56:51.682057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 00:56:51.682155 ==
976 00:56:51.682243
977 00:56:51.682333
978 00:56:51.685693 TX Vref Scan disable
979 00:56:51.685790 == TX Byte 0 ==
980 00:56:51.693940 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 00:56:51.697240 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 00:56:51.697343 == TX Byte 1 ==
983 00:56:51.700973 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
984 00:56:51.704154 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
985 00:56:51.707818 ==
986 00:56:51.707920 Dram Type= 6, Freq= 0, CH_0, rank 0
987 00:56:51.714317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 00:56:51.714419 ==
989 00:56:51.726849 TX Vref=22, minBit 5, minWin=27, winSum=444
990 00:56:51.730635 TX Vref=24, minBit 8, minWin=27, winSum=441
991 00:56:51.733415 TX Vref=26, minBit 4, minWin=27, winSum=445
992 00:56:51.736759 TX Vref=28, minBit 8, minWin=27, winSum=447
993 00:56:51.740290 TX Vref=30, minBit 8, minWin=27, winSum=446
994 00:56:51.743404 TX Vref=32, minBit 4, minWin=27, winSum=444
995 00:56:51.749907 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
996 00:56:51.749990
997 00:56:51.753426 Final TX Range 1 Vref 28
998 00:56:51.753504
999 00:56:51.753569 ==
1000 00:56:51.756565 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 00:56:51.760086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 00:56:51.760163 ==
1003 00:56:51.760232
1004 00:56:51.760321
1005 00:56:51.763112 TX Vref Scan disable
1006 00:56:51.767042 == TX Byte 0 ==
1007 00:56:51.770492 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 00:56:51.774420 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 00:56:51.778085 == TX Byte 1 ==
1010 00:56:51.781695 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1011 00:56:51.785160 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1012 00:56:51.785262
1013 00:56:51.785358 [DATLAT]
1014 00:56:51.788894 Freq=800, CH0 RK0
1015 00:56:51.788968
1016 00:56:51.789030 DATLAT Default: 0xa
1017 00:56:51.792863 0, 0xFFFF, sum = 0
1018 00:56:51.792943 1, 0xFFFF, sum = 0
1019 00:56:51.796131 2, 0xFFFF, sum = 0
1020 00:56:51.796236 3, 0xFFFF, sum = 0
1021 00:56:51.799334 4, 0xFFFF, sum = 0
1022 00:56:51.799437 5, 0xFFFF, sum = 0
1023 00:56:51.802766 6, 0xFFFF, sum = 0
1024 00:56:51.802869 7, 0xFFFF, sum = 0
1025 00:56:51.805694 8, 0xFFFF, sum = 0
1026 00:56:51.805795 9, 0x0, sum = 1
1027 00:56:51.809193 10, 0x0, sum = 2
1028 00:56:51.809292 11, 0x0, sum = 3
1029 00:56:51.812511 12, 0x0, sum = 4
1030 00:56:51.812605 best_step = 10
1031 00:56:51.812693
1032 00:56:51.812779 ==
1033 00:56:51.816207 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 00:56:51.819370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 00:56:51.819513 ==
1036 00:56:51.823182 RX Vref Scan: 1
1037 00:56:51.823278
1038 00:56:51.826042 Set Vref Range= 32 -> 127
1039 00:56:51.826140
1040 00:56:51.826231 RX Vref 32 -> 127, step: 1
1041 00:56:51.829450
1042 00:56:51.829547 RX Delay -111 -> 252, step: 8
1043 00:56:51.829636
1044 00:56:51.832394 Set Vref, RX VrefLevel [Byte0]: 32
1045 00:56:51.835643 [Byte1]: 32
1046 00:56:51.839474
1047 00:56:51.839573 Set Vref, RX VrefLevel [Byte0]: 33
1048 00:56:51.842959 [Byte1]: 33
1049 00:56:51.847229
1050 00:56:51.847329 Set Vref, RX VrefLevel [Byte0]: 34
1051 00:56:51.850827 [Byte1]: 34
1052 00:56:51.854820
1053 00:56:51.854920 Set Vref, RX VrefLevel [Byte0]: 35
1054 00:56:51.858061 [Byte1]: 35
1055 00:56:51.862399
1056 00:56:51.865917 Set Vref, RX VrefLevel [Byte0]: 36
1057 00:56:51.866032 [Byte1]: 36
1058 00:56:51.870144
1059 00:56:51.870245 Set Vref, RX VrefLevel [Byte0]: 37
1060 00:56:51.873522 [Byte1]: 37
1061 00:56:51.877679
1062 00:56:51.877782 Set Vref, RX VrefLevel [Byte0]: 38
1063 00:56:51.880991 [Byte1]: 38
1064 00:56:51.885654
1065 00:56:51.885754 Set Vref, RX VrefLevel [Byte0]: 39
1066 00:56:51.889037 [Byte1]: 39
1067 00:56:51.892967
1068 00:56:51.893042 Set Vref, RX VrefLevel [Byte0]: 40
1069 00:56:51.899286 [Byte1]: 40
1070 00:56:51.899388
1071 00:56:51.903293 Set Vref, RX VrefLevel [Byte0]: 41
1072 00:56:51.906085 [Byte1]: 41
1073 00:56:51.906185
1074 00:56:51.909242 Set Vref, RX VrefLevel [Byte0]: 42
1075 00:56:51.912681 [Byte1]: 42
1076 00:56:51.916213
1077 00:56:51.916313 Set Vref, RX VrefLevel [Byte0]: 43
1078 00:56:51.919015 [Byte1]: 43
1079 00:56:51.924448
1080 00:56:51.924549 Set Vref, RX VrefLevel [Byte0]: 44
1081 00:56:51.926991 [Byte1]: 44
1082 00:56:51.931212
1083 00:56:51.931302 Set Vref, RX VrefLevel [Byte0]: 45
1084 00:56:51.934395 [Byte1]: 45
1085 00:56:51.939188
1086 00:56:51.939262 Set Vref, RX VrefLevel [Byte0]: 46
1087 00:56:51.942110 [Byte1]: 46
1088 00:56:51.946672
1089 00:56:51.946770 Set Vref, RX VrefLevel [Byte0]: 47
1090 00:56:51.949907 [Byte1]: 47
1091 00:56:51.954472
1092 00:56:51.954569 Set Vref, RX VrefLevel [Byte0]: 48
1093 00:56:51.957345 [Byte1]: 48
1094 00:56:51.961971
1095 00:56:51.962072 Set Vref, RX VrefLevel [Byte0]: 49
1096 00:56:51.965109 [Byte1]: 49
1097 00:56:51.969384
1098 00:56:51.969487 Set Vref, RX VrefLevel [Byte0]: 50
1099 00:56:51.972905 [Byte1]: 50
1100 00:56:51.977033
1101 00:56:51.977134 Set Vref, RX VrefLevel [Byte0]: 51
1102 00:56:51.981058 [Byte1]: 51
1103 00:56:51.985086
1104 00:56:51.985187 Set Vref, RX VrefLevel [Byte0]: 52
1105 00:56:51.987982 [Byte1]: 52
1106 00:56:51.992337
1107 00:56:51.992439 Set Vref, RX VrefLevel [Byte0]: 53
1108 00:56:51.995832 [Byte1]: 53
1109 00:56:52.000043
1110 00:56:52.000116 Set Vref, RX VrefLevel [Byte0]: 54
1111 00:56:52.003573 [Byte1]: 54
1112 00:56:52.007702
1113 00:56:52.007802 Set Vref, RX VrefLevel [Byte0]: 55
1114 00:56:52.011229 [Byte1]: 55
1115 00:56:52.015552
1116 00:56:52.015650 Set Vref, RX VrefLevel [Byte0]: 56
1117 00:56:52.019060 [Byte1]: 56
1118 00:56:52.023230
1119 00:56:52.023330 Set Vref, RX VrefLevel [Byte0]: 57
1120 00:56:52.026517 [Byte1]: 57
1121 00:56:52.030545
1122 00:56:52.030645 Set Vref, RX VrefLevel [Byte0]: 58
1123 00:56:52.034249 [Byte1]: 58
1124 00:56:52.038552
1125 00:56:52.038655 Set Vref, RX VrefLevel [Byte0]: 59
1126 00:56:52.041893 [Byte1]: 59
1127 00:56:52.046208
1128 00:56:52.046283 Set Vref, RX VrefLevel [Byte0]: 60
1129 00:56:52.049308 [Byte1]: 60
1130 00:56:52.053557
1131 00:56:52.053656 Set Vref, RX VrefLevel [Byte0]: 61
1132 00:56:52.056737 [Byte1]: 61
1133 00:56:52.061351
1134 00:56:52.061453 Set Vref, RX VrefLevel [Byte0]: 62
1135 00:56:52.064964 [Byte1]: 62
1136 00:56:52.069238
1137 00:56:52.069338 Set Vref, RX VrefLevel [Byte0]: 63
1138 00:56:52.071994 [Byte1]: 63
1139 00:56:52.076814
1140 00:56:52.076912 Set Vref, RX VrefLevel [Byte0]: 64
1141 00:56:52.079800 [Byte1]: 64
1142 00:56:52.084755
1143 00:56:52.084830 Set Vref, RX VrefLevel [Byte0]: 65
1144 00:56:52.087990 [Byte1]: 65
1145 00:56:52.091995
1146 00:56:52.092094 Set Vref, RX VrefLevel [Byte0]: 66
1147 00:56:52.095178 [Byte1]: 66
1148 00:56:52.099980
1149 00:56:52.100062 Set Vref, RX VrefLevel [Byte0]: 67
1150 00:56:52.103330 [Byte1]: 67
1151 00:56:52.107540
1152 00:56:52.107643 Set Vref, RX VrefLevel [Byte0]: 68
1153 00:56:52.110658 [Byte1]: 68
1154 00:56:52.116415
1155 00:56:52.116541 Set Vref, RX VrefLevel [Byte0]: 69
1156 00:56:52.118928 [Byte1]: 69
1157 00:56:52.123175
1158 00:56:52.123276 Set Vref, RX VrefLevel [Byte0]: 70
1159 00:56:52.126141 [Byte1]: 70
1160 00:56:52.130377
1161 00:56:52.130482 Set Vref, RX VrefLevel [Byte0]: 71
1162 00:56:52.133636 [Byte1]: 71
1163 00:56:52.138327
1164 00:56:52.138407 Set Vref, RX VrefLevel [Byte0]: 72
1165 00:56:52.141387 [Byte1]: 72
1166 00:56:52.145753
1167 00:56:52.145828 Set Vref, RX VrefLevel [Byte0]: 73
1168 00:56:52.148946 [Byte1]: 73
1169 00:56:52.153238
1170 00:56:52.153317 Set Vref, RX VrefLevel [Byte0]: 74
1171 00:56:52.156901 [Byte1]: 74
1172 00:56:52.160552
1173 00:56:52.160654 Set Vref, RX VrefLevel [Byte0]: 75
1174 00:56:52.164582 [Byte1]: 75
1175 00:56:52.168924
1176 00:56:52.169027 Set Vref, RX VrefLevel [Byte0]: 76
1177 00:56:52.171807 [Byte1]: 76
1178 00:56:52.176626
1179 00:56:52.176727 Set Vref, RX VrefLevel [Byte0]: 77
1180 00:56:52.179338 [Byte1]: 77
1181 00:56:52.183811
1182 00:56:52.183890 Set Vref, RX VrefLevel [Byte0]: 78
1183 00:56:52.187014 [Byte1]: 78
1184 00:56:52.191367
1185 00:56:52.191471 Set Vref, RX VrefLevel [Byte0]: 79
1186 00:56:52.194686 [Byte1]: 79
1187 00:56:52.199249
1188 00:56:52.199327 Set Vref, RX VrefLevel [Byte0]: 80
1189 00:56:52.202660 [Byte1]: 80
1190 00:56:52.206806
1191 00:56:52.206910 Final RX Vref Byte 0 = 61 to rank0
1192 00:56:52.210950 Final RX Vref Byte 1 = 51 to rank0
1193 00:56:52.213747 Final RX Vref Byte 0 = 61 to rank1
1194 00:56:52.217459 Final RX Vref Byte 1 = 51 to rank1==
1195 00:56:52.221676 Dram Type= 6, Freq= 0, CH_0, rank 0
1196 00:56:52.225778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 00:56:52.225882 ==
1198 00:56:52.225973 DQS Delay:
1199 00:56:52.228764 DQS0 = 0, DQS1 = 0
1200 00:56:52.228860 DQM Delay:
1201 00:56:52.232773 DQM0 = 86, DQM1 = 76
1202 00:56:52.232874 DQ Delay:
1203 00:56:52.236559 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1204 00:56:52.239955 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1205 00:56:52.240030 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1206 00:56:52.243460 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1207 00:56:52.243559
1208 00:56:52.247457
1209 00:56:52.254047 [DQSOSCAuto] RK0, (LSB)MR18= 0x492a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1210 00:56:52.257816 CH0 RK0: MR19=606, MR18=492A
1211 00:56:52.261094 CH0_RK0: MR19=0x606, MR18=0x492A, DQSOSC=391, MR23=63, INC=96, DEC=64
1212 00:56:52.261198
1213 00:56:52.264972 ----->DramcWriteLeveling(PI) begin...
1214 00:56:52.265077 ==
1215 00:56:52.269109 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 00:56:52.272663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 00:56:52.272766 ==
1218 00:56:52.276549 Write leveling (Byte 0): 35 => 35
1219 00:56:52.279916 Write leveling (Byte 1): 29 => 29
1220 00:56:52.284070 DramcWriteLeveling(PI) end<-----
1221 00:56:52.284177
1222 00:56:52.284248 ==
1223 00:56:52.287130 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 00:56:52.291131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 00:56:52.291237 ==
1226 00:56:52.294373 [Gating] SW mode calibration
1227 00:56:52.338467 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1228 00:56:52.339057 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1229 00:56:52.339664 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 00:56:52.339963 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1231 00:56:52.340044 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1232 00:56:52.340111 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:56:52.340359 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:56:52.340895 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:56:52.341479 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:56:52.382381 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:56:52.382500 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:56:52.382904 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 00:56:52.383471 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 00:56:52.384196 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 00:56:52.384454 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 00:56:52.384547 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 00:56:52.384652 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 00:56:52.384752 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 00:56:52.385379 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 00:56:52.426381 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1247 00:56:52.426491 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1248 00:56:52.427171 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1249 00:56:52.427581 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:56:52.428453 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:56:52.428704 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:56:52.428771 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:56:52.428844 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:56:52.429614 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 00:56:52.429891 0 9 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
1256 00:56:52.448379 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1257 00:56:52.448453 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 00:56:52.449144 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 00:56:52.449459 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 00:56:52.450474 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 00:56:52.453323 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 00:56:52.456609 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 00:56:52.460414 0 10 8 | B1->B0 | 2f2f 2727 | 1 1 | (1 1) (1 1)
1264 00:56:52.463949 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1265 00:56:52.467781 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 00:56:52.471759 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 00:56:52.478730 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 00:56:52.482340 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 00:56:52.486028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 00:56:52.489237 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1271 00:56:52.492776 0 11 8 | B1->B0 | 2f2f 3838 | 0 0 | (0 0) (1 1)
1272 00:56:52.500612 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1273 00:56:52.504320 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 00:56:52.507701 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 00:56:52.511520 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 00:56:52.515341 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 00:56:52.521977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 00:56:52.526082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 00:56:52.530198 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1280 00:56:52.533752 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 00:56:52.537359 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 00:56:52.540861 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 00:56:52.548383 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 00:56:52.552522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 00:56:52.556115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 00:56:52.559952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 00:56:52.567230 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 00:56:52.570919 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 00:56:52.574148 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 00:56:52.577639 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 00:56:52.581089 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 00:56:52.588360 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 00:56:52.592052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 00:56:52.595081 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 00:56:52.598725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1296 00:56:52.605358 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1297 00:56:52.605440 Total UI for P1: 0, mck2ui 16
1298 00:56:52.612330 best dqsien dly found for B0: ( 0, 14, 8)
1299 00:56:52.612409 Total UI for P1: 0, mck2ui 16
1300 00:56:52.615859 best dqsien dly found for B1: ( 0, 14, 8)
1301 00:56:52.622579 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1302 00:56:52.625946 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1303 00:56:52.626040
1304 00:56:52.629031 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 00:56:52.632179 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1306 00:56:52.635417 [Gating] SW calibration Done
1307 00:56:52.635488 ==
1308 00:56:52.638825 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 00:56:52.642618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 00:56:52.642711 ==
1311 00:56:52.645700 RX Vref Scan: 0
1312 00:56:52.645794
1313 00:56:52.645883 RX Vref 0 -> 0, step: 1
1314 00:56:52.645968
1315 00:56:52.649664 RX Delay -130 -> 252, step: 16
1316 00:56:52.652559 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 00:56:52.658700 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1318 00:56:52.662399 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1319 00:56:52.665251 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 00:56:52.668314 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 00:56:52.671926 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 00:56:52.675405 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1323 00:56:52.681873 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1324 00:56:52.685330 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 00:56:52.688769 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1326 00:56:52.692105 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 00:56:52.698821 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 00:56:52.701880 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 00:56:52.704882 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 00:56:52.709072 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 00:56:52.711562 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1332 00:56:52.715133 ==
1333 00:56:52.718375 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 00:56:52.721407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 00:56:52.721504 ==
1336 00:56:52.721592 DQS Delay:
1337 00:56:52.725140 DQS0 = 0, DQS1 = 0
1338 00:56:52.725240 DQM Delay:
1339 00:56:52.728539 DQM0 = 83, DQM1 = 77
1340 00:56:52.728633 DQ Delay:
1341 00:56:52.731396 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1342 00:56:52.735150 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1343 00:56:52.738394 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1344 00:56:52.741448 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1345 00:56:52.741522
1346 00:56:52.741583
1347 00:56:52.741641 ==
1348 00:56:52.744883 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 00:56:52.748495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 00:56:52.748572 ==
1351 00:56:52.748638
1352 00:56:52.748696
1353 00:56:52.751642 TX Vref Scan disable
1354 00:56:52.755047 == TX Byte 0 ==
1355 00:56:52.758736 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1356 00:56:52.761575 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1357 00:56:52.765037 == TX Byte 1 ==
1358 00:56:52.768059 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1359 00:56:52.771464 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1360 00:56:52.771566 ==
1361 00:56:52.775033 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 00:56:52.778201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 00:56:52.781325 ==
1364 00:56:52.793728 TX Vref=22, minBit 3, minWin=27, winSum=441
1365 00:56:52.797016 TX Vref=24, minBit 3, minWin=27, winSum=447
1366 00:56:52.800418 TX Vref=26, minBit 5, minWin=27, winSum=447
1367 00:56:52.804130 TX Vref=28, minBit 6, minWin=27, winSum=446
1368 00:56:52.806839 TX Vref=30, minBit 9, minWin=27, winSum=447
1369 00:56:52.813434 TX Vref=32, minBit 6, minWin=27, winSum=442
1370 00:56:52.816522 [TxChooseVref] Worse bit 3, Min win 27, Win sum 447, Final Vref 24
1371 00:56:52.816601
1372 00:56:52.819900 Final TX Range 1 Vref 24
1373 00:56:52.819976
1374 00:56:52.820037 ==
1375 00:56:52.823614 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 00:56:52.826754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 00:56:52.826855 ==
1378 00:56:52.829730
1379 00:56:52.829806
1380 00:56:52.829884 TX Vref Scan disable
1381 00:56:52.833486 == TX Byte 0 ==
1382 00:56:52.836705 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1383 00:56:52.843851 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1384 00:56:52.843931 == TX Byte 1 ==
1385 00:56:52.846648 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1386 00:56:52.853434 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1387 00:56:52.853512
1388 00:56:52.853576 [DATLAT]
1389 00:56:52.853635 Freq=800, CH0 RK1
1390 00:56:52.853692
1391 00:56:52.857083 DATLAT Default: 0xa
1392 00:56:52.857165 0, 0xFFFF, sum = 0
1393 00:56:52.859983 1, 0xFFFF, sum = 0
1394 00:56:52.860063 2, 0xFFFF, sum = 0
1395 00:56:52.863938 3, 0xFFFF, sum = 0
1396 00:56:52.866638 4, 0xFFFF, sum = 0
1397 00:56:52.866719 5, 0xFFFF, sum = 0
1398 00:56:52.870065 6, 0xFFFF, sum = 0
1399 00:56:52.870145 7, 0xFFFF, sum = 0
1400 00:56:52.873833 8, 0xFFFF, sum = 0
1401 00:56:52.873913 9, 0x0, sum = 1
1402 00:56:52.876368 10, 0x0, sum = 2
1403 00:56:52.876451 11, 0x0, sum = 3
1404 00:56:52.876529 12, 0x0, sum = 4
1405 00:56:52.879952 best_step = 10
1406 00:56:52.880023
1407 00:56:52.880083 ==
1408 00:56:52.883325 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 00:56:52.886799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 00:56:52.886871 ==
1411 00:56:52.889707 RX Vref Scan: 0
1412 00:56:52.889776
1413 00:56:52.889834 RX Vref 0 -> 0, step: 1
1414 00:56:52.893176
1415 00:56:52.893249 RX Delay -111 -> 252, step: 8
1416 00:56:52.900213 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1417 00:56:52.903608 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1418 00:56:52.907161 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1419 00:56:52.910215 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1420 00:56:52.913458 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1421 00:56:52.920647 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1422 00:56:52.923622 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1423 00:56:52.926571 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1424 00:56:52.929686 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1425 00:56:52.933378 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1426 00:56:52.939951 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1427 00:56:52.943389 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1428 00:56:52.946436 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1429 00:56:52.949823 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1430 00:56:52.956405 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1431 00:56:52.959837 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1432 00:56:52.959917 ==
1433 00:56:52.963333 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 00:56:52.966807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 00:56:52.966888 ==
1436 00:56:52.969673 DQS Delay:
1437 00:56:52.969756 DQS0 = 0, DQS1 = 0
1438 00:56:52.969819 DQM Delay:
1439 00:56:52.973635 DQM0 = 84, DQM1 = 77
1440 00:56:52.973705 DQ Delay:
1441 00:56:52.976242 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =80
1442 00:56:52.979528 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1443 00:56:52.982610 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1444 00:56:52.986046 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 00:56:52.986122
1446 00:56:52.986190
1447 00:56:52.995953 [DQSOSCAuto] RK1, (LSB)MR18= 0x4108, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1448 00:56:53.000082 CH0 RK1: MR19=606, MR18=4108
1449 00:56:53.002826 CH0_RK1: MR19=0x606, MR18=0x4108, DQSOSC=393, MR23=63, INC=95, DEC=63
1450 00:56:53.006214 [RxdqsGatingPostProcess] freq 800
1451 00:56:53.013050 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 00:56:53.015866 Pre-setting of DQS Precalculation
1453 00:56:53.019494 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 00:56:53.019563 ==
1455 00:56:53.022718 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 00:56:53.029179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 00:56:53.029254 ==
1458 00:56:53.032516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 00:56:53.039397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 00:56:53.048408 [CA 0] Center 36 (6~67) winsize 62
1461 00:56:53.051720 [CA 1] Center 36 (6~67) winsize 62
1462 00:56:53.055508 [CA 2] Center 34 (4~65) winsize 62
1463 00:56:53.059020 [CA 3] Center 34 (3~65) winsize 63
1464 00:56:53.061857 [CA 4] Center 34 (4~65) winsize 62
1465 00:56:53.065296 [CA 5] Center 34 (3~65) winsize 63
1466 00:56:53.065376
1467 00:56:53.068894 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 00:56:53.069033
1469 00:56:53.071851 [CATrainingPosCal] consider 1 rank data
1470 00:56:53.075156 u2DelayCellTimex100 = 270/100 ps
1471 00:56:53.078223 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 00:56:53.085149 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 00:56:53.088520 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 00:56:53.091948 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 00:56:53.094930 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 00:56:53.098507 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 00:56:53.098587
1478 00:56:53.101546 CA PerBit enable=1, Macro0, CA PI delay=34
1479 00:56:53.101627
1480 00:56:53.105032 [CBTSetCACLKResult] CA Dly = 34
1481 00:56:53.105112 CS Dly: 4 (0~35)
1482 00:56:53.108540 ==
1483 00:56:53.111727 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 00:56:53.114667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 00:56:53.114785 ==
1486 00:56:53.121231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 00:56:53.124530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 00:56:53.135427 [CA 0] Center 36 (6~67) winsize 62
1489 00:56:53.138202 [CA 1] Center 36 (6~67) winsize 62
1490 00:56:53.141265 [CA 2] Center 34 (4~65) winsize 62
1491 00:56:53.144688 [CA 3] Center 34 (3~65) winsize 63
1492 00:56:53.147575 [CA 4] Center 34 (4~65) winsize 62
1493 00:56:53.150980 [CA 5] Center 34 (3~65) winsize 63
1494 00:56:53.151060
1495 00:56:53.154370 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1496 00:56:53.154451
1497 00:56:53.157535 [CATrainingPosCal] consider 2 rank data
1498 00:56:53.160798 u2DelayCellTimex100 = 270/100 ps
1499 00:56:53.164235 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 00:56:53.170983 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1501 00:56:53.174353 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 00:56:53.177401 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1503 00:56:53.180733 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 00:56:53.184198 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1505 00:56:53.184274
1506 00:56:53.187477 CA PerBit enable=1, Macro0, CA PI delay=34
1507 00:56:53.187552
1508 00:56:53.190973 [CBTSetCACLKResult] CA Dly = 34
1509 00:56:53.194268 CS Dly: 5 (0~38)
1510 00:56:53.194360
1511 00:56:53.197635 ----->DramcWriteLeveling(PI) begin...
1512 00:56:53.197707 ==
1513 00:56:53.200645 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 00:56:53.203973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 00:56:53.204048 ==
1516 00:56:53.206912 Write leveling (Byte 0): 28 => 28
1517 00:56:53.210758 Write leveling (Byte 1): 28 => 28
1518 00:56:53.213544 DramcWriteLeveling(PI) end<-----
1519 00:56:53.213616
1520 00:56:53.213676 ==
1521 00:56:53.217210 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 00:56:53.220866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 00:56:53.220937 ==
1524 00:56:53.223603 [Gating] SW mode calibration
1525 00:56:53.230533 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 00:56:53.236954 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 00:56:53.240748 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1528 00:56:53.243389 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1529 00:56:53.249999 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:56:53.253970 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:56:53.257070 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:56:53.263282 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:56:53.266808 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:56:53.270283 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:56:53.276598 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 00:56:53.280062 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 00:56:53.283504 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 00:56:53.289645 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 00:56:53.293004 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 00:56:53.296675 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 00:56:53.303357 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 00:56:53.306428 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 00:56:53.309718 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1544 00:56:53.316323 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1545 00:56:53.319315 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:56:53.323194 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:56:53.329572 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:56:53.332864 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:56:53.336417 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:56:53.342826 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 00:56:53.345704 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 00:56:53.349435 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 00:56:53.355806 0 9 8 | B1->B0 | 2c2c 3434 | 1 0 | (1 1) (0 0)
1554 00:56:53.359404 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 00:56:53.362703 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 00:56:53.368941 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 00:56:53.372376 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 00:56:53.375520 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 00:56:53.382249 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 00:56:53.385129 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1561 00:56:53.388835 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1562 00:56:53.395261 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 00:56:53.398533 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 00:56:53.401742 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 00:56:53.408577 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 00:56:53.412114 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 00:56:53.415426 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 00:56:53.422351 0 11 4 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
1569 00:56:53.425241 0 11 8 | B1->B0 | 3838 4444 | 1 0 | (0 0) (0 0)
1570 00:56:53.428416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 00:56:53.435341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 00:56:53.438474 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 00:56:53.441897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 00:56:53.447962 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 00:56:53.452188 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:56:53.454984 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1577 00:56:53.461520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 00:56:53.464708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 00:56:53.468310 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 00:56:53.474545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 00:56:53.478179 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 00:56:53.481546 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 00:56:53.488108 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 00:56:53.491001 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 00:56:53.494518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 00:56:53.501016 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 00:56:53.504344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 00:56:53.507689 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 00:56:53.514223 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 00:56:53.517397 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 00:56:53.520844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 00:56:53.527414 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1593 00:56:53.530960 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1594 00:56:53.534044 Total UI for P1: 0, mck2ui 16
1595 00:56:53.537861 best dqsien dly found for B0: ( 0, 14, 4)
1596 00:56:53.540647 Total UI for P1: 0, mck2ui 16
1597 00:56:53.544559 best dqsien dly found for B1: ( 0, 14, 6)
1598 00:56:53.547550 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1599 00:56:53.551016 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1600 00:56:53.551129
1601 00:56:53.554132 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1602 00:56:53.557081 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1603 00:56:53.561104 [Gating] SW calibration Done
1604 00:56:53.561179 ==
1605 00:56:53.564201 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 00:56:53.567380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 00:56:53.567477 ==
1608 00:56:53.570675 RX Vref Scan: 0
1609 00:56:53.570748
1610 00:56:53.574123 RX Vref 0 -> 0, step: 1
1611 00:56:53.574194
1612 00:56:53.574253 RX Delay -130 -> 252, step: 16
1613 00:56:53.580480 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1614 00:56:53.583819 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1615 00:56:53.587148 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1616 00:56:53.590793 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1617 00:56:53.593791 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1618 00:56:53.600709 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1619 00:56:53.603552 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1620 00:56:53.607023 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1621 00:56:53.610366 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1622 00:56:53.617358 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1623 00:56:53.620516 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1624 00:56:53.623865 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1625 00:56:53.626880 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1626 00:56:53.630062 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1627 00:56:53.636535 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1628 00:56:53.640058 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1629 00:56:53.640145 ==
1630 00:56:53.643555 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 00:56:53.646837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 00:56:53.646916 ==
1633 00:56:53.649797 DQS Delay:
1634 00:56:53.649894 DQS0 = 0, DQS1 = 0
1635 00:56:53.649959 DQM Delay:
1636 00:56:53.653045 DQM0 = 89, DQM1 = 79
1637 00:56:53.653127 DQ Delay:
1638 00:56:53.656581 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1639 00:56:53.659841 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1640 00:56:53.664092 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1641 00:56:53.666682 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1642 00:56:53.666763
1643 00:56:53.666827
1644 00:56:53.666887 ==
1645 00:56:53.669925 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 00:56:53.676341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 00:56:53.676423 ==
1648 00:56:53.676487
1649 00:56:53.676547
1650 00:56:53.679612 TX Vref Scan disable
1651 00:56:53.679735 == TX Byte 0 ==
1652 00:56:53.682928 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1653 00:56:53.689538 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1654 00:56:53.689619 == TX Byte 1 ==
1655 00:56:53.692827 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1656 00:56:53.699502 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1657 00:56:53.699583 ==
1658 00:56:53.703067 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 00:56:53.705957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 00:56:53.706039 ==
1661 00:56:53.719536 TX Vref=22, minBit 8, minWin=27, winSum=443
1662 00:56:53.722796 TX Vref=24, minBit 8, minWin=27, winSum=449
1663 00:56:53.726280 TX Vref=26, minBit 10, minWin=27, winSum=450
1664 00:56:53.729217 TX Vref=28, minBit 10, minWin=27, winSum=450
1665 00:56:53.732800 TX Vref=30, minBit 10, minWin=27, winSum=448
1666 00:56:53.738827 TX Vref=32, minBit 8, minWin=27, winSum=446
1667 00:56:53.742674 [TxChooseVref] Worse bit 10, Min win 27, Win sum 450, Final Vref 26
1668 00:56:53.742748
1669 00:56:53.745883 Final TX Range 1 Vref 26
1670 00:56:53.745958
1671 00:56:53.746024 ==
1672 00:56:53.749106 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 00:56:53.752402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 00:56:53.755858 ==
1675 00:56:53.755929
1676 00:56:53.756016
1677 00:56:53.756108 TX Vref Scan disable
1678 00:56:53.759618 == TX Byte 0 ==
1679 00:56:53.763037 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1680 00:56:53.766219 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1681 00:56:53.769244 == TX Byte 1 ==
1682 00:56:53.772753 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1683 00:56:53.780505 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1684 00:56:53.780581
1685 00:56:53.780644 [DATLAT]
1686 00:56:53.780704 Freq=800, CH1 RK0
1687 00:56:53.780766
1688 00:56:53.783430 DATLAT Default: 0xa
1689 00:56:53.783503 0, 0xFFFF, sum = 0
1690 00:56:53.786346 1, 0xFFFF, sum = 0
1691 00:56:53.789309 2, 0xFFFF, sum = 0
1692 00:56:53.789407 3, 0xFFFF, sum = 0
1693 00:56:53.792562 4, 0xFFFF, sum = 0
1694 00:56:53.792645 5, 0xFFFF, sum = 0
1695 00:56:53.795825 6, 0xFFFF, sum = 0
1696 00:56:53.795900 7, 0xFFFF, sum = 0
1697 00:56:53.798836 8, 0xFFFF, sum = 0
1698 00:56:53.798926 9, 0x0, sum = 1
1699 00:56:53.802335 10, 0x0, sum = 2
1700 00:56:53.802438 11, 0x0, sum = 3
1701 00:56:53.805825 12, 0x0, sum = 4
1702 00:56:53.805930 best_step = 10
1703 00:56:53.806029
1704 00:56:53.806116 ==
1705 00:56:53.808774 Dram Type= 6, Freq= 0, CH_1, rank 0
1706 00:56:53.812580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1707 00:56:53.812656 ==
1708 00:56:53.815358 RX Vref Scan: 1
1709 00:56:53.815468
1710 00:56:53.819074 Set Vref Range= 32 -> 127
1711 00:56:53.819175
1712 00:56:53.819263 RX Vref 32 -> 127, step: 1
1713 00:56:53.819365
1714 00:56:53.822038 RX Delay -95 -> 252, step: 8
1715 00:56:53.822137
1716 00:56:53.825540 Set Vref, RX VrefLevel [Byte0]: 32
1717 00:56:53.828823 [Byte1]: 32
1718 00:56:53.832452
1719 00:56:53.832552 Set Vref, RX VrefLevel [Byte0]: 33
1720 00:56:53.835478 [Byte1]: 33
1721 00:56:53.839756
1722 00:56:53.839855 Set Vref, RX VrefLevel [Byte0]: 34
1723 00:56:53.843025 [Byte1]: 34
1724 00:56:53.847414
1725 00:56:53.847489 Set Vref, RX VrefLevel [Byte0]: 35
1726 00:56:53.850391 [Byte1]: 35
1727 00:56:53.854786
1728 00:56:53.854859 Set Vref, RX VrefLevel [Byte0]: 36
1729 00:56:53.858260 [Byte1]: 36
1730 00:56:53.862621
1731 00:56:53.862698 Set Vref, RX VrefLevel [Byte0]: 37
1732 00:56:53.866084 [Byte1]: 37
1733 00:56:53.869947
1734 00:56:53.870019 Set Vref, RX VrefLevel [Byte0]: 38
1735 00:56:53.873533 [Byte1]: 38
1736 00:56:53.877960
1737 00:56:53.878036 Set Vref, RX VrefLevel [Byte0]: 39
1738 00:56:53.881186 [Byte1]: 39
1739 00:56:53.885313
1740 00:56:53.885390 Set Vref, RX VrefLevel [Byte0]: 40
1741 00:56:53.888492 [Byte1]: 40
1742 00:56:53.892867
1743 00:56:53.892939 Set Vref, RX VrefLevel [Byte0]: 41
1744 00:56:53.896329 [Byte1]: 41
1745 00:56:53.900650
1746 00:56:53.900724 Set Vref, RX VrefLevel [Byte0]: 42
1747 00:56:53.904631 [Byte1]: 42
1748 00:56:53.908010
1749 00:56:53.908088 Set Vref, RX VrefLevel [Byte0]: 43
1750 00:56:53.911863 [Byte1]: 43
1751 00:56:53.916068
1752 00:56:53.916141 Set Vref, RX VrefLevel [Byte0]: 44
1753 00:56:53.919157 [Byte1]: 44
1754 00:56:53.923628
1755 00:56:53.923750 Set Vref, RX VrefLevel [Byte0]: 45
1756 00:56:53.926753 [Byte1]: 45
1757 00:56:53.930896
1758 00:56:53.930971 Set Vref, RX VrefLevel [Byte0]: 46
1759 00:56:53.934590 [Byte1]: 46
1760 00:56:53.938587
1761 00:56:53.938683 Set Vref, RX VrefLevel [Byte0]: 47
1762 00:56:53.942559 [Byte1]: 47
1763 00:56:53.946561
1764 00:56:53.946661 Set Vref, RX VrefLevel [Byte0]: 48
1765 00:56:53.949312 [Byte1]: 48
1766 00:56:53.954053
1767 00:56:53.954129 Set Vref, RX VrefLevel [Byte0]: 49
1768 00:56:53.956977 [Byte1]: 49
1769 00:56:53.961255
1770 00:56:53.961333 Set Vref, RX VrefLevel [Byte0]: 50
1771 00:56:53.965014 [Byte1]: 50
1772 00:56:53.968764
1773 00:56:53.968841 Set Vref, RX VrefLevel [Byte0]: 51
1774 00:56:53.972305 [Byte1]: 51
1775 00:56:53.976429
1776 00:56:53.976502 Set Vref, RX VrefLevel [Byte0]: 52
1777 00:56:53.979911 [Byte1]: 52
1778 00:56:53.984001
1779 00:56:53.984108 Set Vref, RX VrefLevel [Byte0]: 53
1780 00:56:53.987524 [Byte1]: 53
1781 00:56:53.991823
1782 00:56:53.991902 Set Vref, RX VrefLevel [Byte0]: 54
1783 00:56:53.995036 [Byte1]: 54
1784 00:56:53.999260
1785 00:56:53.999336 Set Vref, RX VrefLevel [Byte0]: 55
1786 00:56:54.002634 [Byte1]: 55
1787 00:56:54.007084
1788 00:56:54.007158 Set Vref, RX VrefLevel [Byte0]: 56
1789 00:56:54.010357 [Byte1]: 56
1790 00:56:54.014386
1791 00:56:54.014460 Set Vref, RX VrefLevel [Byte0]: 57
1792 00:56:54.018016 [Byte1]: 57
1793 00:56:54.022138
1794 00:56:54.022223 Set Vref, RX VrefLevel [Byte0]: 58
1795 00:56:54.025425 [Byte1]: 58
1796 00:56:54.029769
1797 00:56:54.029843 Set Vref, RX VrefLevel [Byte0]: 59
1798 00:56:54.033125 [Byte1]: 59
1799 00:56:54.037644
1800 00:56:54.037722 Set Vref, RX VrefLevel [Byte0]: 60
1801 00:56:54.040749 [Byte1]: 60
1802 00:56:54.045164
1803 00:56:54.045236 Set Vref, RX VrefLevel [Byte0]: 61
1804 00:56:54.048484 [Byte1]: 61
1805 00:56:54.052728
1806 00:56:54.052801 Set Vref, RX VrefLevel [Byte0]: 62
1807 00:56:54.055594 [Byte1]: 62
1808 00:56:54.060360
1809 00:56:54.060438 Set Vref, RX VrefLevel [Byte0]: 63
1810 00:56:54.063913 [Byte1]: 63
1811 00:56:54.067608
1812 00:56:54.067707 Set Vref, RX VrefLevel [Byte0]: 64
1813 00:56:54.071234 [Byte1]: 64
1814 00:56:54.075570
1815 00:56:54.075642 Set Vref, RX VrefLevel [Byte0]: 65
1816 00:56:54.078606 [Byte1]: 65
1817 00:56:54.083279
1818 00:56:54.083351 Set Vref, RX VrefLevel [Byte0]: 66
1819 00:56:54.086212 [Byte1]: 66
1820 00:56:54.090532
1821 00:56:54.090605 Set Vref, RX VrefLevel [Byte0]: 67
1822 00:56:54.093731 [Byte1]: 67
1823 00:56:54.098353
1824 00:56:54.098431 Set Vref, RX VrefLevel [Byte0]: 68
1825 00:56:54.101589 [Byte1]: 68
1826 00:56:54.105798
1827 00:56:54.105875 Set Vref, RX VrefLevel [Byte0]: 69
1828 00:56:54.108839 [Byte1]: 69
1829 00:56:54.113384
1830 00:56:54.113459 Set Vref, RX VrefLevel [Byte0]: 70
1831 00:56:54.116390 [Byte1]: 70
1832 00:56:54.120784
1833 00:56:54.120861 Set Vref, RX VrefLevel [Byte0]: 71
1834 00:56:54.124448 [Byte1]: 71
1835 00:56:54.128204
1836 00:56:54.128284 Set Vref, RX VrefLevel [Byte0]: 72
1837 00:56:54.131918 [Byte1]: 72
1838 00:56:54.135797
1839 00:56:54.135872 Set Vref, RX VrefLevel [Byte0]: 73
1840 00:56:54.139618 [Byte1]: 73
1841 00:56:54.143727
1842 00:56:54.143819 Set Vref, RX VrefLevel [Byte0]: 74
1843 00:56:54.146656 [Byte1]: 74
1844 00:56:54.151431
1845 00:56:54.151503 Set Vref, RX VrefLevel [Byte0]: 75
1846 00:56:54.154869 [Byte1]: 75
1847 00:56:54.158736
1848 00:56:54.158814 Set Vref, RX VrefLevel [Byte0]: 76
1849 00:56:54.162037 [Byte1]: 76
1850 00:56:54.166858
1851 00:56:54.166937 Set Vref, RX VrefLevel [Byte0]: 77
1852 00:56:54.169840 [Byte1]: 77
1853 00:56:54.174091
1854 00:56:54.174168 Final RX Vref Byte 0 = 55 to rank0
1855 00:56:54.177727 Final RX Vref Byte 1 = 64 to rank0
1856 00:56:54.180694 Final RX Vref Byte 0 = 55 to rank1
1857 00:56:54.183834 Final RX Vref Byte 1 = 64 to rank1==
1858 00:56:54.187174 Dram Type= 6, Freq= 0, CH_1, rank 0
1859 00:56:54.193931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 00:56:54.194009 ==
1861 00:56:54.194074 DQS Delay:
1862 00:56:54.194138 DQS0 = 0, DQS1 = 0
1863 00:56:54.197436 DQM Delay:
1864 00:56:54.197514 DQM0 = 86, DQM1 = 79
1865 00:56:54.200975 DQ Delay:
1866 00:56:54.203733 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1867 00:56:54.207612 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1868 00:56:54.210427 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1869 00:56:54.213728 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1870 00:56:54.213803
1871 00:56:54.213866
1872 00:56:54.220682 [DQSOSCAuto] RK0, (LSB)MR18= 0x3622, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1873 00:56:54.223717 CH1 RK0: MR19=606, MR18=3622
1874 00:56:54.230539 CH1_RK0: MR19=0x606, MR18=0x3622, DQSOSC=396, MR23=63, INC=94, DEC=62
1875 00:56:54.230617
1876 00:56:54.233428 ----->DramcWriteLeveling(PI) begin...
1877 00:56:54.233532 ==
1878 00:56:54.237072 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 00:56:54.240274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 00:56:54.240350 ==
1881 00:56:54.243538 Write leveling (Byte 0): 28 => 28
1882 00:56:54.247799 Write leveling (Byte 1): 29 => 29
1883 00:56:54.250694 DramcWriteLeveling(PI) end<-----
1884 00:56:54.250768
1885 00:56:54.250834 ==
1886 00:56:54.253627 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 00:56:54.256947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 00:56:54.257022 ==
1889 00:56:54.260091 [Gating] SW mode calibration
1890 00:56:54.266661 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1891 00:56:54.273581 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1892 00:56:54.276852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1893 00:56:54.283784 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1894 00:56:54.286658 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1895 00:56:54.290402 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 00:56:54.293562 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 00:56:54.300150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:56:54.303309 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:56:54.306882 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:56:54.313756 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:56:54.317277 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:56:54.320584 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:56:54.326712 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:56:54.330358 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:56:54.333772 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:56:54.339884 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 00:56:54.343282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 00:56:54.346699 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 00:56:54.352956 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1910 00:56:54.356246 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 00:56:54.359809 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 00:56:54.366298 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 00:56:54.369976 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:56:54.373171 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 00:56:54.379748 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:56:54.382858 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:56:54.386749 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:56:54.392949 0 9 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
1919 00:56:54.396570 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 00:56:54.399428 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 00:56:54.406368 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 00:56:54.409793 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 00:56:54.413170 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 00:56:54.419321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 00:56:54.422733 0 10 4 | B1->B0 | 2f2f 3232 | 0 1 | (0 1) (1 1)
1926 00:56:54.426216 0 10 8 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (1 0)
1927 00:56:54.433137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 00:56:54.436143 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 00:56:54.439460 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 00:56:54.445912 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 00:56:54.449525 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 00:56:54.452923 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 00:56:54.456049 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
1934 00:56:54.462966 0 11 8 | B1->B0 | 3d3d 3434 | 0 0 | (0 0) (1 1)
1935 00:56:54.465822 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 00:56:54.472701 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 00:56:54.475771 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 00:56:54.479132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 00:56:54.483004 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 00:56:54.489251 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 00:56:54.492228 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1942 00:56:54.496134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1943 00:56:54.502362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 00:56:54.505628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 00:56:54.509652 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 00:56:54.516074 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 00:56:54.519194 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 00:56:54.522870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 00:56:54.529538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 00:56:54.532377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 00:56:54.535934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 00:56:54.542663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 00:56:54.545697 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 00:56:54.549612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 00:56:54.555959 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 00:56:54.559251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 00:56:54.562234 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1958 00:56:54.569182 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1959 00:56:54.569287 Total UI for P1: 0, mck2ui 16
1960 00:56:54.572299 best dqsien dly found for B0: ( 0, 14, 4)
1961 00:56:54.575772 Total UI for P1: 0, mck2ui 16
1962 00:56:54.579178 best dqsien dly found for B1: ( 0, 14, 4)
1963 00:56:54.585408 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1964 00:56:54.589085 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1965 00:56:54.589157
1966 00:56:54.591947 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1967 00:56:54.595487 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1968 00:56:54.598713 [Gating] SW calibration Done
1969 00:56:54.598844 ==
1970 00:56:54.602123 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 00:56:54.605713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 00:56:54.605809 ==
1973 00:56:54.608701 RX Vref Scan: 0
1974 00:56:54.608780
1975 00:56:54.608841 RX Vref 0 -> 0, step: 1
1976 00:56:54.608900
1977 00:56:54.612035 RX Delay -130 -> 252, step: 16
1978 00:56:54.615036 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1979 00:56:54.622172 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1980 00:56:54.625399 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1981 00:56:54.629118 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1982 00:56:54.631814 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1983 00:56:54.635445 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1984 00:56:54.641980 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1985 00:56:54.645070 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1986 00:56:54.648636 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1987 00:56:54.651541 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1988 00:56:54.655323 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1989 00:56:54.661802 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1990 00:56:54.664919 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1991 00:56:54.668227 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1992 00:56:54.671635 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1993 00:56:54.674820 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1994 00:56:54.678699 ==
1995 00:56:54.681963 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 00:56:54.685520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 00:56:54.685618 ==
1998 00:56:54.685713 DQS Delay:
1999 00:56:54.688264 DQS0 = 0, DQS1 = 0
2000 00:56:54.688334 DQM Delay:
2001 00:56:54.691822 DQM0 = 88, DQM1 = 81
2002 00:56:54.691910 DQ Delay:
2003 00:56:54.695000 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
2004 00:56:54.698456 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2005 00:56:54.702275 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
2006 00:56:54.704724 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2007 00:56:54.704795
2008 00:56:54.704856
2009 00:56:54.704914 ==
2010 00:56:54.708070 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 00:56:54.711858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 00:56:54.711932 ==
2013 00:56:54.711999
2014 00:56:54.712089
2015 00:56:54.714765 TX Vref Scan disable
2016 00:56:54.718664 == TX Byte 0 ==
2017 00:56:54.721165 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2018 00:56:54.724562 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2019 00:56:54.728194 == TX Byte 1 ==
2020 00:56:54.731541 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2021 00:56:54.734541 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2022 00:56:54.734635 ==
2023 00:56:54.738270 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 00:56:54.744451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 00:56:54.744530 ==
2026 00:56:54.756144 TX Vref=22, minBit 8, minWin=27, winSum=446
2027 00:56:54.759795 TX Vref=24, minBit 9, minWin=26, winSum=445
2028 00:56:54.762555 TX Vref=26, minBit 8, minWin=27, winSum=449
2029 00:56:54.766360 TX Vref=28, minBit 8, minWin=27, winSum=450
2030 00:56:54.769808 TX Vref=30, minBit 8, minWin=27, winSum=449
2031 00:56:54.776192 TX Vref=32, minBit 8, minWin=27, winSum=449
2032 00:56:54.779626 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
2033 00:56:54.779768
2034 00:56:54.782624 Final TX Range 1 Vref 28
2035 00:56:54.782698
2036 00:56:54.782759 ==
2037 00:56:54.786057 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 00:56:54.789524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 00:56:54.789599 ==
2040 00:56:54.792513
2041 00:56:54.792586
2042 00:56:54.792647 TX Vref Scan disable
2043 00:56:54.796500 == TX Byte 0 ==
2044 00:56:54.799277 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2045 00:56:54.806001 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2046 00:56:54.806079 == TX Byte 1 ==
2047 00:56:54.809445 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2048 00:56:54.815825 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2049 00:56:54.815906
2050 00:56:54.815970 [DATLAT]
2051 00:56:54.816029 Freq=800, CH1 RK1
2052 00:56:54.816088
2053 00:56:54.819185 DATLAT Default: 0xa
2054 00:56:54.822474 0, 0xFFFF, sum = 0
2055 00:56:54.822552 1, 0xFFFF, sum = 0
2056 00:56:54.825930 2, 0xFFFF, sum = 0
2057 00:56:54.826008 3, 0xFFFF, sum = 0
2058 00:56:54.829386 4, 0xFFFF, sum = 0
2059 00:56:54.829461 5, 0xFFFF, sum = 0
2060 00:56:54.832350 6, 0xFFFF, sum = 0
2061 00:56:54.832424 7, 0xFFFF, sum = 0
2062 00:56:54.835823 8, 0xFFFF, sum = 0
2063 00:56:54.835904 9, 0x0, sum = 1
2064 00:56:54.838960 10, 0x0, sum = 2
2065 00:56:54.839033 11, 0x0, sum = 3
2066 00:56:54.841902 12, 0x0, sum = 4
2067 00:56:54.841970 best_step = 10
2068 00:56:54.842033
2069 00:56:54.842089 ==
2070 00:56:54.845382 Dram Type= 6, Freq= 0, CH_1, rank 1
2071 00:56:54.848992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2072 00:56:54.851793 ==
2073 00:56:54.851862 RX Vref Scan: 0
2074 00:56:54.851948
2075 00:56:54.855607 RX Vref 0 -> 0, step: 1
2076 00:56:54.855705
2077 00:56:54.855785 RX Delay -95 -> 252, step: 8
2078 00:56:54.862891 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2079 00:56:54.866205 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2080 00:56:54.869249 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2081 00:56:54.872798 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2082 00:56:54.879358 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2083 00:56:54.882690 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2084 00:56:54.885700 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2085 00:56:54.889602 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2086 00:56:54.892594 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2087 00:56:54.899394 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2088 00:56:54.902353 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2089 00:56:54.906246 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2090 00:56:54.909031 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2091 00:56:54.912766 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2092 00:56:54.918984 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2093 00:56:54.922480 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2094 00:56:54.922553 ==
2095 00:56:54.925716 Dram Type= 6, Freq= 0, CH_1, rank 1
2096 00:56:54.928673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2097 00:56:54.928774 ==
2098 00:56:54.932169 DQS Delay:
2099 00:56:54.932242 DQS0 = 0, DQS1 = 0
2100 00:56:54.932303 DQM Delay:
2101 00:56:54.935565 DQM0 = 87, DQM1 = 79
2102 00:56:54.935647 DQ Delay:
2103 00:56:54.939232 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2104 00:56:54.942407 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2105 00:56:54.945556 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2106 00:56:54.948831 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2107 00:56:54.948908
2108 00:56:54.948969
2109 00:56:54.959087 [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2110 00:56:54.962156 CH1 RK1: MR19=606, MR18=1911
2111 00:56:54.965209 CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60
2112 00:56:54.969148 [RxdqsGatingPostProcess] freq 800
2113 00:56:54.975203 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2114 00:56:54.979263 Pre-setting of DQS Precalculation
2115 00:56:54.982244 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2116 00:56:54.992018 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2117 00:56:54.998497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2118 00:56:54.998574
2119 00:56:54.998637
2120 00:56:55.001874 [Calibration Summary] 1600 Mbps
2121 00:56:55.001948 CH 0, Rank 0
2122 00:56:55.005735 SW Impedance : PASS
2123 00:56:55.005808 DUTY Scan : NO K
2124 00:56:55.009354 ZQ Calibration : PASS
2125 00:56:55.012008 Jitter Meter : NO K
2126 00:56:55.012082 CBT Training : PASS
2127 00:56:55.015223 Write leveling : PASS
2128 00:56:55.019057 RX DQS gating : PASS
2129 00:56:55.019132 RX DQ/DQS(RDDQC) : PASS
2130 00:56:55.021835 TX DQ/DQS : PASS
2131 00:56:55.021902 RX DATLAT : PASS
2132 00:56:55.025494 RX DQ/DQS(Engine): PASS
2133 00:56:55.029065 TX OE : NO K
2134 00:56:55.029138 All Pass.
2135 00:56:55.029203
2136 00:56:55.029261 CH 0, Rank 1
2137 00:56:55.032284 SW Impedance : PASS
2138 00:56:55.035108 DUTY Scan : NO K
2139 00:56:55.035180 ZQ Calibration : PASS
2140 00:56:55.038469 Jitter Meter : NO K
2141 00:56:55.041890 CBT Training : PASS
2142 00:56:55.041991 Write leveling : PASS
2143 00:56:55.045076 RX DQS gating : PASS
2144 00:56:55.048704 RX DQ/DQS(RDDQC) : PASS
2145 00:56:55.048781 TX DQ/DQS : PASS
2146 00:56:55.052139 RX DATLAT : PASS
2147 00:56:55.055033 RX DQ/DQS(Engine): PASS
2148 00:56:55.055105 TX OE : NO K
2149 00:56:55.058877 All Pass.
2150 00:56:55.058944
2151 00:56:55.059065 CH 1, Rank 0
2152 00:56:55.061740 SW Impedance : PASS
2153 00:56:55.061818 DUTY Scan : NO K
2154 00:56:55.065056 ZQ Calibration : PASS
2155 00:56:55.068994 Jitter Meter : NO K
2156 00:56:55.069069 CBT Training : PASS
2157 00:56:55.071454 Write leveling : PASS
2158 00:56:55.075299 RX DQS gating : PASS
2159 00:56:55.075376 RX DQ/DQS(RDDQC) : PASS
2160 00:56:55.078179 TX DQ/DQS : PASS
2161 00:56:55.078261 RX DATLAT : PASS
2162 00:56:55.081699 RX DQ/DQS(Engine): PASS
2163 00:56:55.085007 TX OE : NO K
2164 00:56:55.085085 All Pass.
2165 00:56:55.085147
2166 00:56:55.085207 CH 1, Rank 1
2167 00:56:55.088001 SW Impedance : PASS
2168 00:56:55.091360 DUTY Scan : NO K
2169 00:56:55.091459 ZQ Calibration : PASS
2170 00:56:55.094911 Jitter Meter : NO K
2171 00:56:55.098707 CBT Training : PASS
2172 00:56:55.098804 Write leveling : PASS
2173 00:56:55.101654 RX DQS gating : PASS
2174 00:56:55.104636 RX DQ/DQS(RDDQC) : PASS
2175 00:56:55.104706 TX DQ/DQS : PASS
2176 00:56:55.108009 RX DATLAT : PASS
2177 00:56:55.111659 RX DQ/DQS(Engine): PASS
2178 00:56:55.111755 TX OE : NO K
2179 00:56:55.114963 All Pass.
2180 00:56:55.115057
2181 00:56:55.115144 DramC Write-DBI off
2182 00:56:55.118298 PER_BANK_REFRESH: Hybrid Mode
2183 00:56:55.118374 TX_TRACKING: ON
2184 00:56:55.121487 [GetDramInforAfterCalByMRR] Vendor 6.
2185 00:56:55.128249 [GetDramInforAfterCalByMRR] Revision 606.
2186 00:56:55.131154 [GetDramInforAfterCalByMRR] Revision 2 0.
2187 00:56:55.131226 MR0 0x3b3b
2188 00:56:55.131318 MR8 0x5151
2189 00:56:55.134489 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 00:56:55.134563
2191 00:56:55.138203 MR0 0x3b3b
2192 00:56:55.138297 MR8 0x5151
2193 00:56:55.141156 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2194 00:56:55.141225
2195 00:56:55.151404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2196 00:56:55.154849 [FAST_K] Save calibration result to emmc
2197 00:56:55.158360 [FAST_K] Save calibration result to emmc
2198 00:56:55.161260 dram_init: config_dvfs: 1
2199 00:56:55.164546 dramc_set_vcore_voltage set vcore to 662500
2200 00:56:55.167953 Read voltage for 1200, 2
2201 00:56:55.168030 Vio18 = 0
2202 00:56:55.168093 Vcore = 662500
2203 00:56:55.171811 Vdram = 0
2204 00:56:55.171879 Vddq = 0
2205 00:56:55.171939 Vmddr = 0
2206 00:56:55.178267 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2207 00:56:55.181068 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2208 00:56:55.184323 MEM_TYPE=3, freq_sel=15
2209 00:56:55.187879 sv_algorithm_assistance_LP4_1600
2210 00:56:55.191296 ============ PULL DRAM RESETB DOWN ============
2211 00:56:55.194626 ========== PULL DRAM RESETB DOWN end =========
2212 00:56:55.201354 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2213 00:56:55.204179 ===================================
2214 00:56:55.204272 LPDDR4 DRAM CONFIGURATION
2215 00:56:55.207763 ===================================
2216 00:56:55.210778 EX_ROW_EN[0] = 0x0
2217 00:56:55.214210 EX_ROW_EN[1] = 0x0
2218 00:56:55.214280 LP4Y_EN = 0x0
2219 00:56:55.218187 WORK_FSP = 0x0
2220 00:56:55.218282 WL = 0x4
2221 00:56:55.221175 RL = 0x4
2222 00:56:55.221269 BL = 0x2
2223 00:56:55.224411 RPST = 0x0
2224 00:56:55.224499 RD_PRE = 0x0
2225 00:56:55.227268 WR_PRE = 0x1
2226 00:56:55.227334 WR_PST = 0x0
2227 00:56:55.230685 DBI_WR = 0x0
2228 00:56:55.230753 DBI_RD = 0x0
2229 00:56:55.234488 OTF = 0x1
2230 00:56:55.237203 ===================================
2231 00:56:55.240518 ===================================
2232 00:56:55.240591 ANA top config
2233 00:56:55.243886 ===================================
2234 00:56:55.247728 DLL_ASYNC_EN = 0
2235 00:56:55.250589 ALL_SLAVE_EN = 0
2236 00:56:55.254050 NEW_RANK_MODE = 1
2237 00:56:55.254127 DLL_IDLE_MODE = 1
2238 00:56:55.257495 LP45_APHY_COMB_EN = 1
2239 00:56:55.260795 TX_ODT_DIS = 1
2240 00:56:55.263912 NEW_8X_MODE = 1
2241 00:56:55.267626 ===================================
2242 00:56:55.270591 ===================================
2243 00:56:55.274426 data_rate = 2400
2244 00:56:55.277554 CKR = 1
2245 00:56:55.277627 DQ_P2S_RATIO = 8
2246 00:56:55.280443 ===================================
2247 00:56:55.283881 CA_P2S_RATIO = 8
2248 00:56:55.287569 DQ_CA_OPEN = 0
2249 00:56:55.290321 DQ_SEMI_OPEN = 0
2250 00:56:55.293553 CA_SEMI_OPEN = 0
2251 00:56:55.293629 CA_FULL_RATE = 0
2252 00:56:55.296753 DQ_CKDIV4_EN = 0
2253 00:56:55.300028 CA_CKDIV4_EN = 0
2254 00:56:55.303318 CA_PREDIV_EN = 0
2255 00:56:55.307249 PH8_DLY = 17
2256 00:56:55.310316 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2257 00:56:55.313636 DQ_AAMCK_DIV = 4
2258 00:56:55.313720 CA_AAMCK_DIV = 4
2259 00:56:55.316622 CA_ADMCK_DIV = 4
2260 00:56:55.320083 DQ_TRACK_CA_EN = 0
2261 00:56:55.323944 CA_PICK = 1200
2262 00:56:55.326573 CA_MCKIO = 1200
2263 00:56:55.329977 MCKIO_SEMI = 0
2264 00:56:55.333464 PLL_FREQ = 2366
2265 00:56:55.333536 DQ_UI_PI_RATIO = 32
2266 00:56:55.336892 CA_UI_PI_RATIO = 0
2267 00:56:55.340715 ===================================
2268 00:56:55.343829 ===================================
2269 00:56:55.347342 memory_type:LPDDR4
2270 00:56:55.350056 GP_NUM : 10
2271 00:56:55.350128 SRAM_EN : 1
2272 00:56:55.353323 MD32_EN : 0
2273 00:56:55.356536 ===================================
2274 00:56:55.356605 [ANA_INIT] >>>>>>>>>>>>>>
2275 00:56:55.360102 <<<<<< [CONFIGURE PHASE]: ANA_TX
2276 00:56:55.363209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2277 00:56:55.366520 ===================================
2278 00:56:55.369834 data_rate = 2400,PCW = 0X5b00
2279 00:56:55.373465 ===================================
2280 00:56:55.376533 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2281 00:56:55.383479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2282 00:56:55.389909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2283 00:56:55.393430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2284 00:56:55.396757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2285 00:56:55.399565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2286 00:56:55.403075 [ANA_INIT] flow start
2287 00:56:55.403150 [ANA_INIT] PLL >>>>>>>>
2288 00:56:55.406434 [ANA_INIT] PLL <<<<<<<<
2289 00:56:55.409749 [ANA_INIT] MIDPI >>>>>>>>
2290 00:56:55.409846 [ANA_INIT] MIDPI <<<<<<<<
2291 00:56:55.413000 [ANA_INIT] DLL >>>>>>>>
2292 00:56:55.416384 [ANA_INIT] DLL <<<<<<<<
2293 00:56:55.416459 [ANA_INIT] flow end
2294 00:56:55.422824 ============ LP4 DIFF to SE enter ============
2295 00:56:55.426046 ============ LP4 DIFF to SE exit ============
2296 00:56:55.429427 [ANA_INIT] <<<<<<<<<<<<<
2297 00:56:55.433000 [Flow] Enable top DCM control >>>>>
2298 00:56:55.436208 [Flow] Enable top DCM control <<<<<
2299 00:56:55.436307 Enable DLL master slave shuffle
2300 00:56:55.442815 ==============================================================
2301 00:56:55.445890 Gating Mode config
2302 00:56:55.449649 ==============================================================
2303 00:56:55.452664 Config description:
2304 00:56:55.462591 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2305 00:56:55.469041 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2306 00:56:55.472478 SELPH_MODE 0: By rank 1: By Phase
2307 00:56:55.479215 ==============================================================
2308 00:56:55.482657 GAT_TRACK_EN = 1
2309 00:56:55.485703 RX_GATING_MODE = 2
2310 00:56:55.489467 RX_GATING_TRACK_MODE = 2
2311 00:56:55.492234 SELPH_MODE = 1
2312 00:56:55.492309 PICG_EARLY_EN = 1
2313 00:56:55.495983 VALID_LAT_VALUE = 1
2314 00:56:55.502378 ==============================================================
2315 00:56:55.505964 Enter into Gating configuration >>>>
2316 00:56:55.509113 Exit from Gating configuration <<<<
2317 00:56:55.512386 Enter into DVFS_PRE_config >>>>>
2318 00:56:55.522685 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2319 00:56:55.525490 Exit from DVFS_PRE_config <<<<<
2320 00:56:55.529375 Enter into PICG configuration >>>>
2321 00:56:55.532339 Exit from PICG configuration <<<<
2322 00:56:55.535527 [RX_INPUT] configuration >>>>>
2323 00:56:55.539197 [RX_INPUT] configuration <<<<<
2324 00:56:55.542356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2325 00:56:55.548916 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2326 00:56:55.555685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2327 00:56:55.562195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2328 00:56:55.568806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2329 00:56:55.574943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2330 00:56:55.578503 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2331 00:56:55.581766 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2332 00:56:55.585507 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2333 00:56:55.591454 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2334 00:56:55.595118 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2335 00:56:55.599779 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 00:56:55.601841 ===================================
2337 00:56:55.605002 LPDDR4 DRAM CONFIGURATION
2338 00:56:55.608904 ===================================
2339 00:56:55.608974 EX_ROW_EN[0] = 0x0
2340 00:56:55.611721 EX_ROW_EN[1] = 0x0
2341 00:56:55.611836 LP4Y_EN = 0x0
2342 00:56:55.615422 WORK_FSP = 0x0
2343 00:56:55.615517 WL = 0x4
2344 00:56:55.618596 RL = 0x4
2345 00:56:55.618690 BL = 0x2
2346 00:56:55.621423 RPST = 0x0
2347 00:56:55.624840 RD_PRE = 0x0
2348 00:56:55.624910 WR_PRE = 0x1
2349 00:56:55.628237 WR_PST = 0x0
2350 00:56:55.628311 DBI_WR = 0x0
2351 00:56:55.631878 DBI_RD = 0x0
2352 00:56:55.631945 OTF = 0x1
2353 00:56:55.635048 ===================================
2354 00:56:55.638038 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2355 00:56:55.645319 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2356 00:56:55.648213 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2357 00:56:55.651097 ===================================
2358 00:56:55.654418 LPDDR4 DRAM CONFIGURATION
2359 00:56:55.658535 ===================================
2360 00:56:55.658633 EX_ROW_EN[0] = 0x10
2361 00:56:55.661383 EX_ROW_EN[1] = 0x0
2362 00:56:55.661474 LP4Y_EN = 0x0
2363 00:56:55.664779 WORK_FSP = 0x0
2364 00:56:55.667803 WL = 0x4
2365 00:56:55.667909 RL = 0x4
2366 00:56:55.670941 BL = 0x2
2367 00:56:55.671037 RPST = 0x0
2368 00:56:55.674866 RD_PRE = 0x0
2369 00:56:55.674960 WR_PRE = 0x1
2370 00:56:55.678058 WR_PST = 0x0
2371 00:56:55.678130 DBI_WR = 0x0
2372 00:56:55.681141 DBI_RD = 0x0
2373 00:56:55.681212 OTF = 0x1
2374 00:56:55.684686 ===================================
2375 00:56:55.691345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2376 00:56:55.691446 ==
2377 00:56:55.694397 Dram Type= 6, Freq= 0, CH_0, rank 0
2378 00:56:55.697857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 00:56:55.697959 ==
2380 00:56:55.701179 [Duty_Offset_Calibration]
2381 00:56:55.704581 B0:1 B1:-1 CA:0
2382 00:56:55.704658
2383 00:56:55.707996 [DutyScan_Calibration_Flow] k_type=0
2384 00:56:55.715808
2385 00:56:55.715915 ==CLK 0==
2386 00:56:55.719160 Final CLK duty delay cell = 0
2387 00:56:55.722280 [0] MAX Duty = 5094%(X100), DQS PI = 16
2388 00:56:55.725793 [0] MIN Duty = 4875%(X100), DQS PI = 8
2389 00:56:55.725887 [0] AVG Duty = 4984%(X100)
2390 00:56:55.729580
2391 00:56:55.732691 CH0 CLK Duty spec in!! Max-Min= 219%
2392 00:56:55.735567 [DutyScan_Calibration_Flow] ====Done====
2393 00:56:55.735634
2394 00:56:55.739147 [DutyScan_Calibration_Flow] k_type=1
2395 00:56:55.753767
2396 00:56:55.753867 ==DQS 0 ==
2397 00:56:55.756647 Final DQS duty delay cell = -4
2398 00:56:55.760321 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2399 00:56:55.763436 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2400 00:56:55.766579 [-4] AVG Duty = 4968%(X100)
2401 00:56:55.766677
2402 00:56:55.766752 ==DQS 1 ==
2403 00:56:55.769991 Final DQS duty delay cell = -4
2404 00:56:55.773468 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2405 00:56:55.776527 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2406 00:56:55.780117 [-4] AVG Duty = 4938%(X100)
2407 00:56:55.780191
2408 00:56:55.782925 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2409 00:56:55.782997
2410 00:56:55.786661 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2411 00:56:55.789990 [DutyScan_Calibration_Flow] ====Done====
2412 00:56:55.790093
2413 00:56:55.793715 [DutyScan_Calibration_Flow] k_type=3
2414 00:56:55.811872
2415 00:56:55.811992 ==DQM 0 ==
2416 00:56:55.814649 Final DQM duty delay cell = 0
2417 00:56:55.817958 [0] MAX Duty = 5062%(X100), DQS PI = 38
2418 00:56:55.821252 [0] MIN Duty = 4875%(X100), DQS PI = 8
2419 00:56:55.824813 [0] AVG Duty = 4968%(X100)
2420 00:56:55.824886
2421 00:56:55.824947 ==DQM 1 ==
2422 00:56:55.828271 Final DQM duty delay cell = 4
2423 00:56:55.831122 [4] MAX Duty = 5187%(X100), DQS PI = 16
2424 00:56:55.834858 [4] MIN Duty = 5000%(X100), DQS PI = 24
2425 00:56:55.838270 [4] AVG Duty = 5093%(X100)
2426 00:56:55.838343
2427 00:56:55.841303 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2428 00:56:55.841379
2429 00:56:55.844683 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2430 00:56:55.847815 [DutyScan_Calibration_Flow] ====Done====
2431 00:56:55.847912
2432 00:56:55.851563 [DutyScan_Calibration_Flow] k_type=2
2433 00:56:55.866687
2434 00:56:55.866784 ==DQ 0 ==
2435 00:56:55.869972 Final DQ duty delay cell = -4
2436 00:56:55.872928 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2437 00:56:55.876377 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2438 00:56:55.879508 [-4] AVG Duty = 4969%(X100)
2439 00:56:55.879602
2440 00:56:55.879724 ==DQ 1 ==
2441 00:56:55.883211 Final DQ duty delay cell = -4
2442 00:56:55.886249 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2443 00:56:55.889475 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2444 00:56:55.893048 [-4] AVG Duty = 4938%(X100)
2445 00:56:55.893118
2446 00:56:55.896253 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2447 00:56:55.896351
2448 00:56:55.899353 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2449 00:56:55.903193 [DutyScan_Calibration_Flow] ====Done====
2450 00:56:55.903261 ==
2451 00:56:55.905985 Dram Type= 6, Freq= 0, CH_1, rank 0
2452 00:56:55.909740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 00:56:55.909832 ==
2454 00:56:55.912503 [Duty_Offset_Calibration]
2455 00:56:55.915799 B0:-1 B1:1 CA:1
2456 00:56:55.915895
2457 00:56:55.919075 [DutyScan_Calibration_Flow] k_type=0
2458 00:56:55.927383
2459 00:56:55.927478 ==CLK 0==
2460 00:56:55.930227 Final CLK duty delay cell = 0
2461 00:56:55.934116 [0] MAX Duty = 5187%(X100), DQS PI = 22
2462 00:56:55.937909 [0] MIN Duty = 4969%(X100), DQS PI = 60
2463 00:56:55.938002 [0] AVG Duty = 5078%(X100)
2464 00:56:55.940889
2465 00:56:55.944164 CH1 CLK Duty spec in!! Max-Min= 218%
2466 00:56:55.946999 [DutyScan_Calibration_Flow] ====Done====
2467 00:56:55.947097
2468 00:56:55.950283 [DutyScan_Calibration_Flow] k_type=1
2469 00:56:55.966709
2470 00:56:55.966796 ==DQS 0 ==
2471 00:56:55.969925 Final DQS duty delay cell = 0
2472 00:56:55.972908 [0] MAX Duty = 5125%(X100), DQS PI = 48
2473 00:56:55.976613 [0] MIN Duty = 4907%(X100), DQS PI = 8
2474 00:56:55.976687 [0] AVG Duty = 5016%(X100)
2475 00:56:55.979542
2476 00:56:55.979612 ==DQS 1 ==
2477 00:56:55.982844 Final DQS duty delay cell = 0
2478 00:56:55.986534 [0] MAX Duty = 5062%(X100), DQS PI = 8
2479 00:56:55.989802 [0] MIN Duty = 4969%(X100), DQS PI = 56
2480 00:56:55.989875 [0] AVG Duty = 5015%(X100)
2481 00:56:55.992784
2482 00:56:55.996120 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2483 00:56:55.996189
2484 00:56:55.999983 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2485 00:56:56.002923 [DutyScan_Calibration_Flow] ====Done====
2486 00:56:56.002994
2487 00:56:56.006123 [DutyScan_Calibration_Flow] k_type=3
2488 00:56:56.022411
2489 00:56:56.022492 ==DQM 0 ==
2490 00:56:56.025350 Final DQM duty delay cell = -4
2491 00:56:56.028539 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2492 00:56:56.031811 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2493 00:56:56.035170 [-4] AVG Duty = 4953%(X100)
2494 00:56:56.035238
2495 00:56:56.035321 ==DQM 1 ==
2496 00:56:56.038775 Final DQM duty delay cell = 0
2497 00:56:56.042330 [0] MAX Duty = 5156%(X100), DQS PI = 2
2498 00:56:56.045591 [0] MIN Duty = 5000%(X100), DQS PI = 28
2499 00:56:56.048374 [0] AVG Duty = 5078%(X100)
2500 00:56:56.048465
2501 00:56:56.052112 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2502 00:56:56.052182
2503 00:56:56.055326 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2504 00:56:56.058673 [DutyScan_Calibration_Flow] ====Done====
2505 00:56:56.058746
2506 00:56:56.061731 [DutyScan_Calibration_Flow] k_type=2
2507 00:56:56.078516
2508 00:56:56.078598 ==DQ 0 ==
2509 00:56:56.082181 Final DQ duty delay cell = 0
2510 00:56:56.085158 [0] MAX Duty = 5218%(X100), DQS PI = 30
2511 00:56:56.088643 [0] MIN Duty = 4907%(X100), DQS PI = 6
2512 00:56:56.088715 [0] AVG Duty = 5062%(X100)
2513 00:56:56.088780
2514 00:56:56.091821 ==DQ 1 ==
2515 00:56:56.095218 Final DQ duty delay cell = 0
2516 00:56:56.098509 [0] MAX Duty = 5124%(X100), DQS PI = 12
2517 00:56:56.101780 [0] MIN Duty = 4969%(X100), DQS PI = 0
2518 00:56:56.101858 [0] AVG Duty = 5046%(X100)
2519 00:56:56.101920
2520 00:56:56.105024 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2521 00:56:56.109020
2522 00:56:56.112178 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2523 00:56:56.115041 [DutyScan_Calibration_Flow] ====Done====
2524 00:56:56.118590 nWR fixed to 30
2525 00:56:56.118668 [ModeRegInit_LP4] CH0 RK0
2526 00:56:56.121964 [ModeRegInit_LP4] CH0 RK1
2527 00:56:56.124817 [ModeRegInit_LP4] CH1 RK0
2528 00:56:56.128875 [ModeRegInit_LP4] CH1 RK1
2529 00:56:56.128963 match AC timing 7
2530 00:56:56.131501 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2531 00:56:56.138583 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2532 00:56:56.141695 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2533 00:56:56.148212 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2534 00:56:56.151434 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2535 00:56:56.151507 ==
2536 00:56:56.154781 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 00:56:56.158399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 00:56:56.158478 ==
2539 00:56:56.165071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 00:56:56.171771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2541 00:56:56.178221 [CA 0] Center 39 (9~70) winsize 62
2542 00:56:56.182110 [CA 1] Center 39 (9~70) winsize 62
2543 00:56:56.184896 [CA 2] Center 35 (5~66) winsize 62
2544 00:56:56.188530 [CA 3] Center 35 (5~65) winsize 61
2545 00:56:56.191820 [CA 4] Center 33 (3~64) winsize 62
2546 00:56:56.194811 [CA 5] Center 33 (4~63) winsize 60
2547 00:56:56.194885
2548 00:56:56.198561 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2549 00:56:56.198677
2550 00:56:56.201711 [CATrainingPosCal] consider 1 rank data
2551 00:56:56.205494 u2DelayCellTimex100 = 270/100 ps
2552 00:56:56.208684 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2553 00:56:56.211704 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2554 00:56:56.218502 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 00:56:56.221748 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2556 00:56:56.224989 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2557 00:56:56.228391 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2558 00:56:56.228490
2559 00:56:56.231513 CA PerBit enable=1, Macro0, CA PI delay=33
2560 00:56:56.231583
2561 00:56:56.235022 [CBTSetCACLKResult] CA Dly = 33
2562 00:56:56.235102 CS Dly: 8 (0~39)
2563 00:56:56.238049 ==
2564 00:56:56.238129 Dram Type= 6, Freq= 0, CH_0, rank 1
2565 00:56:56.244849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 00:56:56.244928 ==
2567 00:56:56.248448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2568 00:56:56.254728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2569 00:56:56.264282 [CA 0] Center 39 (8~70) winsize 63
2570 00:56:56.267596 [CA 1] Center 39 (9~70) winsize 62
2571 00:56:56.270887 [CA 2] Center 35 (5~66) winsize 62
2572 00:56:56.273714 [CA 3] Center 34 (4~65) winsize 62
2573 00:56:56.277265 [CA 4] Center 33 (3~64) winsize 62
2574 00:56:56.280497 [CA 5] Center 33 (3~63) winsize 61
2575 00:56:56.280574
2576 00:56:56.283999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2577 00:56:56.284071
2578 00:56:56.287161 [CATrainingPosCal] consider 2 rank data
2579 00:56:56.290578 u2DelayCellTimex100 = 270/100 ps
2580 00:56:56.294081 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2581 00:56:56.297184 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2582 00:56:56.304128 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2583 00:56:56.307359 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2584 00:56:56.311099 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2585 00:56:56.314146 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2586 00:56:56.314245
2587 00:56:56.317737 CA PerBit enable=1, Macro0, CA PI delay=33
2588 00:56:56.317813
2589 00:56:56.320792 [CBTSetCACLKResult] CA Dly = 33
2590 00:56:56.320865 CS Dly: 9 (0~41)
2591 00:56:56.320926
2592 00:56:56.323808 ----->DramcWriteLeveling(PI) begin...
2593 00:56:56.327518 ==
2594 00:56:56.330926 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 00:56:56.333608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 00:56:56.333728 ==
2597 00:56:56.337156 Write leveling (Byte 0): 34 => 34
2598 00:56:56.340279 Write leveling (Byte 1): 30 => 30
2599 00:56:56.343531 DramcWriteLeveling(PI) end<-----
2600 00:56:56.343630
2601 00:56:56.343745 ==
2602 00:56:56.347187 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 00:56:56.349982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 00:56:56.350056 ==
2605 00:56:56.353715 [Gating] SW mode calibration
2606 00:56:56.360658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2607 00:56:56.367199 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2608 00:56:56.370561 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2609 00:56:56.373499 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2610 00:56:56.380455 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 00:56:56.383388 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 00:56:56.387056 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 00:56:56.393808 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 00:56:56.396881 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 00:56:56.400102 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2616 00:56:56.406696 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2617 00:56:56.410402 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 00:56:56.413514 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 00:56:56.420185 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 00:56:56.423155 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 00:56:56.426717 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 00:56:56.433336 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 00:56:56.436328 1 0 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2624 00:56:56.440365 1 1 0 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
2625 00:56:56.442866 1 1 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2626 00:56:56.449870 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 00:56:56.452827 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 00:56:56.456394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 00:56:56.463220 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 00:56:56.466104 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 00:56:56.469474 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2632 00:56:56.476796 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2633 00:56:56.479655 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2634 00:56:56.483162 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 00:56:56.489886 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 00:56:56.492633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 00:56:56.496090 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 00:56:56.503174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 00:56:56.506146 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 00:56:56.509221 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 00:56:56.515923 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 00:56:56.519331 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 00:56:56.522492 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 00:56:56.529237 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 00:56:56.532922 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 00:56:56.535350 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2647 00:56:56.542046 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2648 00:56:56.545792 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2649 00:56:56.549610 Total UI for P1: 0, mck2ui 16
2650 00:56:56.552528 best dqsien dly found for B0: ( 1, 3, 26)
2651 00:56:56.555645 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2652 00:56:56.559073 Total UI for P1: 0, mck2ui 16
2653 00:56:56.562739 best dqsien dly found for B1: ( 1, 4, 0)
2654 00:56:56.565788 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2655 00:56:56.569219 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2656 00:56:56.569302
2657 00:56:56.575618 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2658 00:56:56.578792 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2659 00:56:56.578873 [Gating] SW calibration Done
2660 00:56:56.581904 ==
2661 00:56:56.585412 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 00:56:56.589002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 00:56:56.589138 ==
2664 00:56:56.589235 RX Vref Scan: 0
2665 00:56:56.589321
2666 00:56:56.592141 RX Vref 0 -> 0, step: 1
2667 00:56:56.592223
2668 00:56:56.595489 RX Delay -40 -> 252, step: 8
2669 00:56:56.598583 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2670 00:56:56.602165 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2671 00:56:56.605302 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2672 00:56:56.612104 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2673 00:56:56.615242 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2674 00:56:56.618497 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2675 00:56:56.621929 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2676 00:56:56.625290 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2677 00:56:56.632381 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2678 00:56:56.635221 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2679 00:56:56.639001 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2680 00:56:56.642144 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2681 00:56:56.645024 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2682 00:56:56.652139 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2683 00:56:56.655424 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2684 00:56:56.658582 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2685 00:56:56.658664 ==
2686 00:56:56.661766 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 00:56:56.665264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 00:56:56.668422 ==
2689 00:56:56.668503 DQS Delay:
2690 00:56:56.668568 DQS0 = 0, DQS1 = 0
2691 00:56:56.671534 DQM Delay:
2692 00:56:56.671643 DQM0 = 119, DQM1 = 107
2693 00:56:56.675057 DQ Delay:
2694 00:56:56.677891 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2695 00:56:56.681386 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2696 00:56:56.684896 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2697 00:56:56.688460 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2698 00:56:56.688557
2699 00:56:56.688637
2700 00:56:56.688697 ==
2701 00:56:56.691733 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 00:56:56.694588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 00:56:56.694670 ==
2704 00:56:56.694734
2705 00:56:56.698230
2706 00:56:56.698311 TX Vref Scan disable
2707 00:56:56.701641 == TX Byte 0 ==
2708 00:56:56.704916 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2709 00:56:56.707955 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2710 00:56:56.711180 == TX Byte 1 ==
2711 00:56:56.714777 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2712 00:56:56.718684 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2713 00:56:56.718765 ==
2714 00:56:56.721216 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 00:56:56.727796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 00:56:56.727877 ==
2717 00:56:56.738820 TX Vref=22, minBit 7, minWin=25, winSum=416
2718 00:56:56.742302 TX Vref=24, minBit 1, minWin=26, winSum=423
2719 00:56:56.745226 TX Vref=26, minBit 4, minWin=26, winSum=433
2720 00:56:56.748686 TX Vref=28, minBit 12, minWin=26, winSum=436
2721 00:56:56.751884 TX Vref=30, minBit 12, minWin=26, winSum=434
2722 00:56:56.758677 TX Vref=32, minBit 4, minWin=26, winSum=435
2723 00:56:56.762077 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 28
2724 00:56:56.762200
2725 00:56:56.765749 Final TX Range 1 Vref 28
2726 00:56:56.765847
2727 00:56:56.765947 ==
2728 00:56:56.768420 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 00:56:56.771731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 00:56:56.774736 ==
2731 00:56:56.774819
2732 00:56:56.774883
2733 00:56:56.774942 TX Vref Scan disable
2734 00:56:56.778698 == TX Byte 0 ==
2735 00:56:56.781717 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2736 00:56:56.789201 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2737 00:56:56.789283 == TX Byte 1 ==
2738 00:56:56.792000 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2739 00:56:56.798517 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2740 00:56:56.798598
2741 00:56:56.798662 [DATLAT]
2742 00:56:56.798721 Freq=1200, CH0 RK0
2743 00:56:56.798779
2744 00:56:56.801906 DATLAT Default: 0xd
2745 00:56:56.801986 0, 0xFFFF, sum = 0
2746 00:56:56.805048 1, 0xFFFF, sum = 0
2747 00:56:56.808430 2, 0xFFFF, sum = 0
2748 00:56:56.808511 3, 0xFFFF, sum = 0
2749 00:56:56.811686 4, 0xFFFF, sum = 0
2750 00:56:56.811769 5, 0xFFFF, sum = 0
2751 00:56:56.814961 6, 0xFFFF, sum = 0
2752 00:56:56.815075 7, 0xFFFF, sum = 0
2753 00:56:56.818342 8, 0xFFFF, sum = 0
2754 00:56:56.818424 9, 0xFFFF, sum = 0
2755 00:56:56.821234 10, 0xFFFF, sum = 0
2756 00:56:56.821316 11, 0xFFFF, sum = 0
2757 00:56:56.824549 12, 0x0, sum = 1
2758 00:56:56.824631 13, 0x0, sum = 2
2759 00:56:56.828234 14, 0x0, sum = 3
2760 00:56:56.828314 15, 0x0, sum = 4
2761 00:56:56.831220 best_step = 13
2762 00:56:56.831301
2763 00:56:56.831366 ==
2764 00:56:56.834938 Dram Type= 6, Freq= 0, CH_0, rank 0
2765 00:56:56.837837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2766 00:56:56.837918 ==
2767 00:56:56.841216 RX Vref Scan: 1
2768 00:56:56.841295
2769 00:56:56.841359 Set Vref Range= 32 -> 127
2770 00:56:56.841418
2771 00:56:56.844562 RX Vref 32 -> 127, step: 1
2772 00:56:56.844642
2773 00:56:56.847887 RX Delay -21 -> 252, step: 4
2774 00:56:56.847983
2775 00:56:56.851423 Set Vref, RX VrefLevel [Byte0]: 32
2776 00:56:56.854530 [Byte1]: 32
2777 00:56:56.854611
2778 00:56:56.857499 Set Vref, RX VrefLevel [Byte0]: 33
2779 00:56:56.861280 [Byte1]: 33
2780 00:56:56.865284
2781 00:56:56.865365 Set Vref, RX VrefLevel [Byte0]: 34
2782 00:56:56.868367 [Byte1]: 34
2783 00:56:56.873611
2784 00:56:56.873690 Set Vref, RX VrefLevel [Byte0]: 35
2785 00:56:56.876219 [Byte1]: 35
2786 00:56:56.881391
2787 00:56:56.881471 Set Vref, RX VrefLevel [Byte0]: 36
2788 00:56:56.884698 [Byte1]: 36
2789 00:56:56.889222
2790 00:56:56.889302 Set Vref, RX VrefLevel [Byte0]: 37
2791 00:56:56.891890 [Byte1]: 37
2792 00:56:56.896905
2793 00:56:56.896984 Set Vref, RX VrefLevel [Byte0]: 38
2794 00:56:56.900203 [Byte1]: 38
2795 00:56:56.904915
2796 00:56:56.904997 Set Vref, RX VrefLevel [Byte0]: 39
2797 00:56:56.907851 [Byte1]: 39
2798 00:56:56.912644
2799 00:56:56.912741 Set Vref, RX VrefLevel [Byte0]: 40
2800 00:56:56.915826 [Byte1]: 40
2801 00:56:56.920394
2802 00:56:56.920474 Set Vref, RX VrefLevel [Byte0]: 41
2803 00:56:56.924402 [Byte1]: 41
2804 00:56:56.928589
2805 00:56:56.928687 Set Vref, RX VrefLevel [Byte0]: 42
2806 00:56:56.931885 [Byte1]: 42
2807 00:56:56.936735
2808 00:56:56.936816 Set Vref, RX VrefLevel [Byte0]: 43
2809 00:56:56.939603 [Byte1]: 43
2810 00:56:56.944342
2811 00:56:56.944422 Set Vref, RX VrefLevel [Byte0]: 44
2812 00:56:56.947786 [Byte1]: 44
2813 00:56:56.952079
2814 00:56:56.952176 Set Vref, RX VrefLevel [Byte0]: 45
2815 00:56:56.955801 [Byte1]: 45
2816 00:56:56.960154
2817 00:56:56.960234 Set Vref, RX VrefLevel [Byte0]: 46
2818 00:56:56.963662 [Byte1]: 46
2819 00:56:56.967938
2820 00:56:56.968018 Set Vref, RX VrefLevel [Byte0]: 47
2821 00:56:56.971704 [Byte1]: 47
2822 00:56:56.976129
2823 00:56:56.976208 Set Vref, RX VrefLevel [Byte0]: 48
2824 00:56:56.979300 [Byte1]: 48
2825 00:56:56.983886
2826 00:56:56.983983 Set Vref, RX VrefLevel [Byte0]: 49
2827 00:56:56.987328 [Byte1]: 49
2828 00:56:56.992009
2829 00:56:56.992106 Set Vref, RX VrefLevel [Byte0]: 50
2830 00:56:56.995100 [Byte1]: 50
2831 00:56:56.999825
2832 00:56:56.999921 Set Vref, RX VrefLevel [Byte0]: 51
2833 00:56:57.003204 [Byte1]: 51
2834 00:56:57.007594
2835 00:56:57.007683 Set Vref, RX VrefLevel [Byte0]: 52
2836 00:56:57.010827 [Byte1]: 52
2837 00:56:57.015845
2838 00:56:57.015943 Set Vref, RX VrefLevel [Byte0]: 53
2839 00:56:57.018945 [Byte1]: 53
2840 00:56:57.023838
2841 00:56:57.023918 Set Vref, RX VrefLevel [Byte0]: 54
2842 00:56:57.026912 [Byte1]: 54
2843 00:56:57.031987
2844 00:56:57.032067 Set Vref, RX VrefLevel [Byte0]: 55
2845 00:56:57.035251 [Byte1]: 55
2846 00:56:57.039762
2847 00:56:57.039854 Set Vref, RX VrefLevel [Byte0]: 56
2848 00:56:57.042674 [Byte1]: 56
2849 00:56:57.047509
2850 00:56:57.047606 Set Vref, RX VrefLevel [Byte0]: 57
2851 00:56:57.050554 [Byte1]: 57
2852 00:56:57.055440
2853 00:56:57.055537 Set Vref, RX VrefLevel [Byte0]: 58
2854 00:56:57.058829 [Byte1]: 58
2855 00:56:57.063573
2856 00:56:57.063654 Set Vref, RX VrefLevel [Byte0]: 59
2857 00:56:57.066538 [Byte1]: 59
2858 00:56:57.071380
2859 00:56:57.071459 Set Vref, RX VrefLevel [Byte0]: 60
2860 00:56:57.074395 [Byte1]: 60
2861 00:56:57.079421
2862 00:56:57.079500 Set Vref, RX VrefLevel [Byte0]: 61
2863 00:56:57.082606 [Byte1]: 61
2864 00:56:57.087126
2865 00:56:57.087205 Set Vref, RX VrefLevel [Byte0]: 62
2866 00:56:57.090103 [Byte1]: 62
2867 00:56:57.095065
2868 00:56:57.095145 Set Vref, RX VrefLevel [Byte0]: 63
2869 00:56:57.098742 [Byte1]: 63
2870 00:56:57.102771
2871 00:56:57.102867 Set Vref, RX VrefLevel [Byte0]: 64
2872 00:56:57.106075 [Byte1]: 64
2873 00:56:57.110709
2874 00:56:57.110789 Set Vref, RX VrefLevel [Byte0]: 65
2875 00:56:57.116027 [Byte1]: 65
2876 00:56:57.118754
2877 00:56:57.118834 Set Vref, RX VrefLevel [Byte0]: 66
2878 00:56:57.122631 [Byte1]: 66
2879 00:56:57.126453
2880 00:56:57.126533 Set Vref, RX VrefLevel [Byte0]: 67
2881 00:56:57.130589 [Byte1]: 67
2882 00:56:57.134723
2883 00:56:57.134816 Set Vref, RX VrefLevel [Byte0]: 68
2884 00:56:57.138303 [Byte1]: 68
2885 00:56:57.142332
2886 00:56:57.142412 Set Vref, RX VrefLevel [Byte0]: 69
2887 00:56:57.145671 [Byte1]: 69
2888 00:56:57.150506
2889 00:56:57.150585 Set Vref, RX VrefLevel [Byte0]: 70
2890 00:56:57.154134 [Byte1]: 70
2891 00:56:57.158774
2892 00:56:57.158853 Set Vref, RX VrefLevel [Byte0]: 71
2893 00:56:57.161764 [Byte1]: 71
2894 00:56:57.166207
2895 00:56:57.166289 Set Vref, RX VrefLevel [Byte0]: 72
2896 00:56:57.169412 [Byte1]: 72
2897 00:56:57.174449
2898 00:56:57.177747 Set Vref, RX VrefLevel [Byte0]: 73
2899 00:56:57.181168 [Byte1]: 73
2900 00:56:57.181283
2901 00:56:57.183892 Set Vref, RX VrefLevel [Byte0]: 74
2902 00:56:57.187624 [Byte1]: 74
2903 00:56:57.187733
2904 00:56:57.190546 Set Vref, RX VrefLevel [Byte0]: 75
2905 00:56:57.194099 [Byte1]: 75
2906 00:56:57.198293
2907 00:56:57.198405 Set Vref, RX VrefLevel [Byte0]: 76
2908 00:56:57.201192 [Byte1]: 76
2909 00:56:57.205983
2910 00:56:57.206054 Set Vref, RX VrefLevel [Byte0]: 77
2911 00:56:57.209583 [Byte1]: 77
2912 00:56:57.214565
2913 00:56:57.214662 Set Vref, RX VrefLevel [Byte0]: 78
2914 00:56:57.217543 [Byte1]: 78
2915 00:56:57.221582
2916 00:56:57.221662 Final RX Vref Byte 0 = 59 to rank0
2917 00:56:57.225357 Final RX Vref Byte 1 = 49 to rank0
2918 00:56:57.228076 Final RX Vref Byte 0 = 59 to rank1
2919 00:56:57.231662 Final RX Vref Byte 1 = 49 to rank1==
2920 00:56:57.234821 Dram Type= 6, Freq= 0, CH_0, rank 0
2921 00:56:57.241436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 00:56:57.241518 ==
2923 00:56:57.241581 DQS Delay:
2924 00:56:57.245663 DQS0 = 0, DQS1 = 0
2925 00:56:57.245743 DQM Delay:
2926 00:56:57.245807 DQM0 = 119, DQM1 = 106
2927 00:56:57.248507 DQ Delay:
2928 00:56:57.251530 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2929 00:56:57.254967 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2930 00:56:57.258512 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2931 00:56:57.261582 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2932 00:56:57.261662
2933 00:56:57.261743
2934 00:56:57.268299 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2935 00:56:57.271396 CH0 RK0: MR19=403, MR18=EFA
2936 00:56:57.278572 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2937 00:56:57.278679
2938 00:56:57.281745 ----->DramcWriteLeveling(PI) begin...
2939 00:56:57.281852 ==
2940 00:56:57.284593 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 00:56:57.288279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 00:56:57.291353 ==
2943 00:56:57.291450 Write leveling (Byte 0): 33 => 33
2944 00:56:57.295146 Write leveling (Byte 1): 30 => 30
2945 00:56:57.298489 DramcWriteLeveling(PI) end<-----
2946 00:56:57.298591
2947 00:56:57.298706 ==
2948 00:56:57.301757 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 00:56:57.307941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 00:56:57.308017 ==
2951 00:56:57.308079 [Gating] SW mode calibration
2952 00:56:57.318028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2953 00:56:57.321488 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2954 00:56:57.328315 0 15 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
2955 00:56:57.331468 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2956 00:56:57.334438 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 00:56:57.337753 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 00:56:57.344655 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 00:56:57.347805 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2960 00:56:57.351213 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2961 00:56:57.357951 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2962 00:56:57.361013 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2963 00:56:57.364875 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2964 00:56:57.371027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 00:56:57.374892 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 00:56:57.377624 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 00:56:57.384754 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 00:56:57.387977 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 00:56:57.390883 1 0 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2970 00:56:57.397736 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2971 00:56:57.400970 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:56:57.404017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 00:56:57.411161 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 00:56:57.413960 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 00:56:57.417754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 00:56:57.424165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 00:56:57.427217 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2978 00:56:57.431070 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 00:56:57.437017 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 00:56:57.440528 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 00:56:57.444180 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 00:56:57.450437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 00:56:57.454068 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 00:56:57.457020 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 00:56:57.463602 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 00:56:57.467072 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 00:56:57.470700 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 00:56:57.477092 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 00:56:57.480100 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 00:56:57.483686 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 00:56:57.490550 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 00:56:57.493667 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2993 00:56:57.496929 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2994 00:56:57.503818 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2995 00:56:57.503945 Total UI for P1: 0, mck2ui 16
2996 00:56:57.510468 best dqsien dly found for B0: ( 1, 3, 26)
2997 00:56:57.513507 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2998 00:56:57.517173 Total UI for P1: 0, mck2ui 16
2999 00:56:57.520179 best dqsien dly found for B1: ( 1, 3, 30)
3000 00:56:57.523213 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3001 00:56:57.527101 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3002 00:56:57.527182
3003 00:56:57.529879 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3004 00:56:57.533583 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3005 00:56:57.537148 [Gating] SW calibration Done
3006 00:56:57.537228 ==
3007 00:56:57.540028 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 00:56:57.543304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 00:56:57.543385 ==
3010 00:56:57.546793 RX Vref Scan: 0
3011 00:56:57.546874
3012 00:56:57.550457 RX Vref 0 -> 0, step: 1
3013 00:56:57.550537
3014 00:56:57.550601 RX Delay -40 -> 252, step: 8
3015 00:56:57.556820 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3016 00:56:57.560269 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3017 00:56:57.563292 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3018 00:56:57.566363 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3019 00:56:57.570086 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3020 00:56:57.576537 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3021 00:56:57.579826 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3022 00:56:57.582928 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3023 00:56:57.586501 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3024 00:56:57.589659 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3025 00:56:57.596044 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3026 00:56:57.599307 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3027 00:56:57.603004 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3028 00:56:57.606037 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3029 00:56:57.612523 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3030 00:56:57.615962 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3031 00:56:57.616042 ==
3032 00:56:57.619849 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 00:56:57.623010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 00:56:57.623106 ==
3035 00:56:57.623193 DQS Delay:
3036 00:56:57.625878 DQS0 = 0, DQS1 = 0
3037 00:56:57.625950 DQM Delay:
3038 00:56:57.629621 DQM0 = 116, DQM1 = 108
3039 00:56:57.629715 DQ Delay:
3040 00:56:57.633448 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3041 00:56:57.636055 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3042 00:56:57.639362 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3043 00:56:57.646128 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3044 00:56:57.646231
3045 00:56:57.646329
3046 00:56:57.646393 ==
3047 00:56:57.649333 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 00:56:57.652341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 00:56:57.652413 ==
3050 00:56:57.652474
3051 00:56:57.652531
3052 00:56:57.655893 TX Vref Scan disable
3053 00:56:57.655965 == TX Byte 0 ==
3054 00:56:57.662908 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3055 00:56:57.665621 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3056 00:56:57.665689 == TX Byte 1 ==
3057 00:56:57.672406 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3058 00:56:57.676388 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3059 00:56:57.676462 ==
3060 00:56:57.678902 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 00:56:57.682221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 00:56:57.682317 ==
3063 00:56:57.695189 TX Vref=22, minBit 7, minWin=25, winSum=420
3064 00:56:57.698856 TX Vref=24, minBit 5, minWin=25, winSum=423
3065 00:56:57.701800 TX Vref=26, minBit 1, minWin=26, winSum=424
3066 00:56:57.704937 TX Vref=28, minBit 1, minWin=26, winSum=432
3067 00:56:57.708145 TX Vref=30, minBit 10, minWin=26, winSum=436
3068 00:56:57.715311 TX Vref=32, minBit 10, minWin=26, winSum=433
3069 00:56:57.718781 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 30
3070 00:56:57.718878
3071 00:56:57.721464 Final TX Range 1 Vref 30
3072 00:56:57.721540
3073 00:56:57.721606 ==
3074 00:56:57.725124 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 00:56:57.728547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 00:56:57.731567 ==
3077 00:56:57.731666
3078 00:56:57.731776
3079 00:56:57.731857 TX Vref Scan disable
3080 00:56:57.735393 == TX Byte 0 ==
3081 00:56:57.738499 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3082 00:56:57.745208 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3083 00:56:57.745285 == TX Byte 1 ==
3084 00:56:57.748370 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3085 00:56:57.755255 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3086 00:56:57.755356
3087 00:56:57.755423 [DATLAT]
3088 00:56:57.755482 Freq=1200, CH0 RK1
3089 00:56:57.755579
3090 00:56:57.758339 DATLAT Default: 0xd
3091 00:56:57.758414 0, 0xFFFF, sum = 0
3092 00:56:57.761643 1, 0xFFFF, sum = 0
3093 00:56:57.764827 2, 0xFFFF, sum = 0
3094 00:56:57.764904 3, 0xFFFF, sum = 0
3095 00:56:57.767991 4, 0xFFFF, sum = 0
3096 00:56:57.768060 5, 0xFFFF, sum = 0
3097 00:56:57.771609 6, 0xFFFF, sum = 0
3098 00:56:57.771715 7, 0xFFFF, sum = 0
3099 00:56:57.774660 8, 0xFFFF, sum = 0
3100 00:56:57.774731 9, 0xFFFF, sum = 0
3101 00:56:57.778170 10, 0xFFFF, sum = 0
3102 00:56:57.778266 11, 0xFFFF, sum = 0
3103 00:56:57.781245 12, 0x0, sum = 1
3104 00:56:57.781313 13, 0x0, sum = 2
3105 00:56:57.785067 14, 0x0, sum = 3
3106 00:56:57.785166 15, 0x0, sum = 4
3107 00:56:57.787843 best_step = 13
3108 00:56:57.787911
3109 00:56:57.787970 ==
3110 00:56:57.791551 Dram Type= 6, Freq= 0, CH_0, rank 1
3111 00:56:57.794453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 00:56:57.794546 ==
3113 00:56:57.797611 RX Vref Scan: 0
3114 00:56:57.797680
3115 00:56:57.797740 RX Vref 0 -> 0, step: 1
3116 00:56:57.797796
3117 00:56:57.801085 RX Delay -21 -> 252, step: 4
3118 00:56:57.807784 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3119 00:56:57.810805 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3120 00:56:57.814399 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3121 00:56:57.817697 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3122 00:56:57.820935 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3123 00:56:57.827473 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3124 00:56:57.830657 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3125 00:56:57.834081 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3126 00:56:57.837828 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3127 00:56:57.840599 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3128 00:56:57.847364 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3129 00:56:57.850779 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3130 00:56:57.853952 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3131 00:56:57.857421 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3132 00:56:57.860771 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3133 00:56:57.867491 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3134 00:56:57.867572 ==
3135 00:56:57.870557 Dram Type= 6, Freq= 0, CH_0, rank 1
3136 00:56:57.873688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 00:56:57.873769 ==
3138 00:56:57.873833 DQS Delay:
3139 00:56:57.877185 DQS0 = 0, DQS1 = 0
3140 00:56:57.877265 DQM Delay:
3141 00:56:57.880222 DQM0 = 116, DQM1 = 108
3142 00:56:57.880337 DQ Delay:
3143 00:56:57.883655 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3144 00:56:57.886925 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3145 00:56:57.890724 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3146 00:56:57.894164 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3147 00:56:57.897046
3148 00:56:57.897115
3149 00:56:57.904135 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 405 ps
3150 00:56:57.906953 CH0 RK1: MR19=403, MR18=BE5
3151 00:56:57.913618 CH0_RK1: MR19=0x403, MR18=0xBE5, DQSOSC=405, MR23=63, INC=39, DEC=26
3152 00:56:57.916592 [RxdqsGatingPostProcess] freq 1200
3153 00:56:57.920252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3154 00:56:57.923501 best DQS0 dly(2T, 0.5T) = (0, 11)
3155 00:56:57.926575 best DQS1 dly(2T, 0.5T) = (0, 12)
3156 00:56:57.929637 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3157 00:56:57.933144 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3158 00:56:57.936629 best DQS0 dly(2T, 0.5T) = (0, 11)
3159 00:56:57.940316 best DQS1 dly(2T, 0.5T) = (0, 11)
3160 00:56:57.942936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3161 00:56:57.946338 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3162 00:56:57.949830 Pre-setting of DQS Precalculation
3163 00:56:57.953327 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3164 00:56:57.953428 ==
3165 00:56:57.956708 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 00:56:57.959935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 00:56:57.963251 ==
3168 00:56:57.966211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3169 00:56:57.972820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3170 00:56:57.981258 [CA 0] Center 37 (7~68) winsize 62
3171 00:56:57.984464 [CA 1] Center 37 (7~68) winsize 62
3172 00:56:57.988018 [CA 2] Center 34 (4~64) winsize 61
3173 00:56:57.991142 [CA 3] Center 33 (3~64) winsize 62
3174 00:56:57.994692 [CA 4] Center 34 (4~64) winsize 61
3175 00:56:57.997742 [CA 5] Center 33 (3~64) winsize 62
3176 00:56:57.997812
3177 00:56:58.001401 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3178 00:56:58.001500
3179 00:56:58.004390 [CATrainingPosCal] consider 1 rank data
3180 00:56:58.008011 u2DelayCellTimex100 = 270/100 ps
3181 00:56:58.011048 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3182 00:56:58.017548 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3183 00:56:58.021072 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 00:56:58.024522 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3185 00:56:58.027525 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 00:56:58.031006 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3187 00:56:58.031077
3188 00:56:58.034435 CA PerBit enable=1, Macro0, CA PI delay=33
3189 00:56:58.034564
3190 00:56:58.037821 [CBTSetCACLKResult] CA Dly = 33
3191 00:56:58.037932 CS Dly: 6 (0~37)
3192 00:56:58.041090 ==
3193 00:56:58.044291 Dram Type= 6, Freq= 0, CH_1, rank 1
3194 00:56:58.047823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 00:56:58.047924 ==
3196 00:56:58.051300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3197 00:56:58.057569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3198 00:56:58.066958 [CA 0] Center 37 (7~67) winsize 61
3199 00:56:58.070033 [CA 1] Center 38 (8~68) winsize 61
3200 00:56:58.073702 [CA 2] Center 34 (4~65) winsize 62
3201 00:56:58.076736 [CA 3] Center 33 (3~64) winsize 62
3202 00:56:58.079956 [CA 4] Center 34 (4~65) winsize 62
3203 00:56:58.083343 [CA 5] Center 33 (3~64) winsize 62
3204 00:56:58.083435
3205 00:56:58.086915 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3206 00:56:58.086984
3207 00:56:58.089794 [CATrainingPosCal] consider 2 rank data
3208 00:56:58.093420 u2DelayCellTimex100 = 270/100 ps
3209 00:56:58.096423 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3210 00:56:58.102948 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3211 00:56:58.106765 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3212 00:56:58.109655 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3213 00:56:58.113472 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3214 00:56:58.116417 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3215 00:56:58.116498
3216 00:56:58.119849 CA PerBit enable=1, Macro0, CA PI delay=33
3217 00:56:58.119930
3218 00:56:58.122920 [CBTSetCACLKResult] CA Dly = 33
3219 00:56:58.126744 CS Dly: 7 (0~40)
3220 00:56:58.126824
3221 00:56:58.129738 ----->DramcWriteLeveling(PI) begin...
3222 00:56:58.129819 ==
3223 00:56:58.132763 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 00:56:58.136563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 00:56:58.136644 ==
3226 00:56:58.139663 Write leveling (Byte 0): 24 => 24
3227 00:56:58.143123 Write leveling (Byte 1): 28 => 28
3228 00:56:58.146125 DramcWriteLeveling(PI) end<-----
3229 00:56:58.146205
3230 00:56:58.146268 ==
3231 00:56:58.149754 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 00:56:58.153033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 00:56:58.153112 ==
3234 00:56:58.156193 [Gating] SW mode calibration
3235 00:56:58.162987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3236 00:56:58.169088 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3237 00:56:58.172396 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3238 00:56:58.175855 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 00:56:58.182409 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 00:56:58.185515 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3241 00:56:58.188957 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3242 00:56:58.195540 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3243 00:56:58.199279 0 15 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
3244 00:56:58.202192 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3245 00:56:58.209150 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 00:56:58.212720 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 00:56:58.216139 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 00:56:58.222214 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 00:56:58.225714 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3250 00:56:58.228995 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3251 00:56:58.235032 1 0 24 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
3252 00:56:58.238538 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3253 00:56:58.241949 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 00:56:58.248468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 00:56:58.251523 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 00:56:58.255133 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 00:56:58.261924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3258 00:56:58.264828 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 00:56:58.268354 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3260 00:56:58.275385 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3261 00:56:58.278453 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 00:56:58.281491 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 00:56:58.288369 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 00:56:58.291643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 00:56:58.295073 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 00:56:58.301666 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 00:56:58.304494 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 00:56:58.308195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 00:56:58.314973 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 00:56:58.317735 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 00:56:58.321360 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 00:56:58.328362 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 00:56:58.331146 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 00:56:58.334252 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 00:56:58.341565 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3276 00:56:58.344778 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3277 00:56:58.347536 Total UI for P1: 0, mck2ui 16
3278 00:56:58.351341 best dqsien dly found for B0: ( 1, 3, 24)
3279 00:56:58.354193 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 00:56:58.357473 Total UI for P1: 0, mck2ui 16
3281 00:56:58.360913 best dqsien dly found for B1: ( 1, 3, 28)
3282 00:56:58.364369 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3283 00:56:58.367820 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3284 00:56:58.367889
3285 00:56:58.371283 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3286 00:56:58.377604 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3287 00:56:58.377678 [Gating] SW calibration Done
3288 00:56:58.377744 ==
3289 00:56:58.381121 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 00:56:58.387907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 00:56:58.387984 ==
3292 00:56:58.388097 RX Vref Scan: 0
3293 00:56:58.388159
3294 00:56:58.390747 RX Vref 0 -> 0, step: 1
3295 00:56:58.390876
3296 00:56:58.394234 RX Delay -40 -> 252, step: 8
3297 00:56:58.397701 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3298 00:56:58.400843 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3299 00:56:58.404379 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3300 00:56:58.411124 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3301 00:56:58.414024 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3302 00:56:58.417454 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3303 00:56:58.420396 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3304 00:56:58.424144 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3305 00:56:58.430748 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3306 00:56:58.433685 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3307 00:56:58.437414 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3308 00:56:58.440966 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3309 00:56:58.444419 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3310 00:56:58.450447 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3311 00:56:58.453955 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3312 00:56:58.456963 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3313 00:56:58.457030 ==
3314 00:56:58.460507 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 00:56:58.463754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 00:56:58.463825 ==
3317 00:56:58.467128 DQS Delay:
3318 00:56:58.467196 DQS0 = 0, DQS1 = 0
3319 00:56:58.470731 DQM Delay:
3320 00:56:58.470799 DQM0 = 117, DQM1 = 109
3321 00:56:58.470864 DQ Delay:
3322 00:56:58.477234 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3323 00:56:58.480382 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3324 00:56:58.483602 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3325 00:56:58.487011 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3326 00:56:58.487084
3327 00:56:58.487145
3328 00:56:58.487203 ==
3329 00:56:58.490625 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 00:56:58.493965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 00:56:58.494043 ==
3332 00:56:58.494105
3333 00:56:58.494162
3334 00:56:58.497396 TX Vref Scan disable
3335 00:56:58.500042 == TX Byte 0 ==
3336 00:56:58.503727 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3337 00:56:58.506981 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3338 00:56:58.510225 == TX Byte 1 ==
3339 00:56:58.513564 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3340 00:56:58.516507 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3341 00:56:58.516587 ==
3342 00:56:58.520170 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 00:56:58.523359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 00:56:58.526895 ==
3345 00:56:58.537241 TX Vref=22, minBit 8, minWin=25, winSum=419
3346 00:56:58.540098 TX Vref=24, minBit 8, minWin=25, winSum=420
3347 00:56:58.543319 TX Vref=26, minBit 8, minWin=25, winSum=428
3348 00:56:58.547141 TX Vref=28, minBit 9, minWin=26, winSum=434
3349 00:56:58.549983 TX Vref=30, minBit 11, minWin=25, winSum=431
3350 00:56:58.556737 TX Vref=32, minBit 9, minWin=25, winSum=428
3351 00:56:58.560453 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3352 00:56:58.560534
3353 00:56:58.563234 Final TX Range 1 Vref 28
3354 00:56:58.563314
3355 00:56:58.563378 ==
3356 00:56:58.566617 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 00:56:58.570400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 00:56:58.570481 ==
3359 00:56:58.573484
3360 00:56:58.573564
3361 00:56:58.573626 TX Vref Scan disable
3362 00:56:58.576539 == TX Byte 0 ==
3363 00:56:58.580040 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3364 00:56:58.586919 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3365 00:56:58.586999 == TX Byte 1 ==
3366 00:56:58.589719 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3367 00:56:58.596976 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3368 00:56:58.597101
3369 00:56:58.597178 [DATLAT]
3370 00:56:58.597237 Freq=1200, CH1 RK0
3371 00:56:58.597294
3372 00:56:58.599707 DATLAT Default: 0xd
3373 00:56:58.599801 0, 0xFFFF, sum = 0
3374 00:56:58.603457 1, 0xFFFF, sum = 0
3375 00:56:58.606460 2, 0xFFFF, sum = 0
3376 00:56:58.606541 3, 0xFFFF, sum = 0
3377 00:56:58.609754 4, 0xFFFF, sum = 0
3378 00:56:58.609835 5, 0xFFFF, sum = 0
3379 00:56:58.613138 6, 0xFFFF, sum = 0
3380 00:56:58.613219 7, 0xFFFF, sum = 0
3381 00:56:58.616236 8, 0xFFFF, sum = 0
3382 00:56:58.616316 9, 0xFFFF, sum = 0
3383 00:56:58.619760 10, 0xFFFF, sum = 0
3384 00:56:58.619860 11, 0xFFFF, sum = 0
3385 00:56:58.623187 12, 0x0, sum = 1
3386 00:56:58.623268 13, 0x0, sum = 2
3387 00:56:58.626516 14, 0x0, sum = 3
3388 00:56:58.626596 15, 0x0, sum = 4
3389 00:56:58.629796 best_step = 13
3390 00:56:58.629876
3391 00:56:58.629939 ==
3392 00:56:58.633055 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 00:56:58.636542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 00:56:58.636623 ==
3395 00:56:58.636686 RX Vref Scan: 1
3396 00:56:58.639491
3397 00:56:58.639599 Set Vref Range= 32 -> 127
3398 00:56:58.639697
3399 00:56:58.643037 RX Vref 32 -> 127, step: 1
3400 00:56:58.643116
3401 00:56:58.646747 RX Delay -21 -> 252, step: 4
3402 00:56:58.646827
3403 00:56:58.649559 Set Vref, RX VrefLevel [Byte0]: 32
3404 00:56:58.652959 [Byte1]: 32
3405 00:56:58.653040
3406 00:56:58.656305 Set Vref, RX VrefLevel [Byte0]: 33
3407 00:56:58.659089 [Byte1]: 33
3408 00:56:58.663126
3409 00:56:58.663206 Set Vref, RX VrefLevel [Byte0]: 34
3410 00:56:58.667018 [Byte1]: 34
3411 00:56:58.671059
3412 00:56:58.671143 Set Vref, RX VrefLevel [Byte0]: 35
3413 00:56:58.674472 [Byte1]: 35
3414 00:56:58.679124
3415 00:56:58.679205 Set Vref, RX VrefLevel [Byte0]: 36
3416 00:56:58.682320 [Byte1]: 36
3417 00:56:58.687570
3418 00:56:58.687697 Set Vref, RX VrefLevel [Byte0]: 37
3419 00:56:58.691017 [Byte1]: 37
3420 00:56:58.695334
3421 00:56:58.695412 Set Vref, RX VrefLevel [Byte0]: 38
3422 00:56:58.698203 [Byte1]: 38
3423 00:56:58.702604
3424 00:56:58.702685 Set Vref, RX VrefLevel [Byte0]: 39
3425 00:56:58.705973 [Byte1]: 39
3426 00:56:58.710581
3427 00:56:58.710663 Set Vref, RX VrefLevel [Byte0]: 40
3428 00:56:58.713950 [Byte1]: 40
3429 00:56:58.718783
3430 00:56:58.718863 Set Vref, RX VrefLevel [Byte0]: 41
3431 00:56:58.721850 [Byte1]: 41
3432 00:56:58.726364
3433 00:56:58.729599 Set Vref, RX VrefLevel [Byte0]: 42
3434 00:56:58.733088 [Byte1]: 42
3435 00:56:58.733174
3436 00:56:58.736299 Set Vref, RX VrefLevel [Byte0]: 43
3437 00:56:58.740754 [Byte1]: 43
3438 00:56:58.740834
3439 00:56:58.742754 Set Vref, RX VrefLevel [Byte0]: 44
3440 00:56:58.746268 [Byte1]: 44
3441 00:56:58.751157
3442 00:56:58.751238 Set Vref, RX VrefLevel [Byte0]: 45
3443 00:56:58.753420 [Byte1]: 45
3444 00:56:58.759012
3445 00:56:58.759092 Set Vref, RX VrefLevel [Byte0]: 46
3446 00:56:58.761731 [Byte1]: 46
3447 00:56:58.766012
3448 00:56:58.766093 Set Vref, RX VrefLevel [Byte0]: 47
3449 00:56:58.769556 [Byte1]: 47
3450 00:56:58.774452
3451 00:56:58.774532 Set Vref, RX VrefLevel [Byte0]: 48
3452 00:56:58.777343 [Byte1]: 48
3453 00:56:58.781926
3454 00:56:58.782064 Set Vref, RX VrefLevel [Byte0]: 49
3455 00:56:58.785350 [Byte1]: 49
3456 00:56:58.790190
3457 00:56:58.790286 Set Vref, RX VrefLevel [Byte0]: 50
3458 00:56:58.793528 [Byte1]: 50
3459 00:56:58.798193
3460 00:56:58.798289 Set Vref, RX VrefLevel [Byte0]: 51
3461 00:56:58.801409 [Byte1]: 51
3462 00:56:58.806011
3463 00:56:58.806107 Set Vref, RX VrefLevel [Byte0]: 52
3464 00:56:58.808850 [Byte1]: 52
3465 00:56:58.813658
3466 00:56:58.813738 Set Vref, RX VrefLevel [Byte0]: 53
3467 00:56:58.816651 [Byte1]: 53
3468 00:56:58.821487
3469 00:56:58.821567 Set Vref, RX VrefLevel [Byte0]: 54
3470 00:56:58.825077 [Byte1]: 54
3471 00:56:58.829732
3472 00:56:58.829812 Set Vref, RX VrefLevel [Byte0]: 55
3473 00:56:58.833008 [Byte1]: 55
3474 00:56:58.837472
3475 00:56:58.837552 Set Vref, RX VrefLevel [Byte0]: 56
3476 00:56:58.840678 [Byte1]: 56
3477 00:56:58.845657
3478 00:56:58.845740 Set Vref, RX VrefLevel [Byte0]: 57
3479 00:56:58.848455 [Byte1]: 57
3480 00:56:58.853104
3481 00:56:58.853186 Set Vref, RX VrefLevel [Byte0]: 58
3482 00:56:58.856284 [Byte1]: 58
3483 00:56:58.861165
3484 00:56:58.861245 Set Vref, RX VrefLevel [Byte0]: 59
3485 00:56:58.864413 [Byte1]: 59
3486 00:56:58.868952
3487 00:56:58.869032 Set Vref, RX VrefLevel [Byte0]: 60
3488 00:56:58.872445 [Byte1]: 60
3489 00:56:58.876884
3490 00:56:58.876964 Set Vref, RX VrefLevel [Byte0]: 61
3491 00:56:58.880585 [Byte1]: 61
3492 00:56:58.885012
3493 00:56:58.885091 Set Vref, RX VrefLevel [Byte0]: 62
3494 00:56:58.887945 [Byte1]: 62
3495 00:56:58.892716
3496 00:56:58.892796 Set Vref, RX VrefLevel [Byte0]: 63
3497 00:56:58.896344 [Byte1]: 63
3498 00:56:58.901081
3499 00:56:58.901160 Set Vref, RX VrefLevel [Byte0]: 64
3500 00:56:58.904621 [Byte1]: 64
3501 00:56:58.908649
3502 00:56:58.908728 Set Vref, RX VrefLevel [Byte0]: 65
3503 00:56:58.911949 [Byte1]: 65
3504 00:56:58.916701
3505 00:56:58.916780 Set Vref, RX VrefLevel [Byte0]: 66
3506 00:56:58.920129 [Byte1]: 66
3507 00:56:58.924460
3508 00:56:58.924539 Set Vref, RX VrefLevel [Byte0]: 67
3509 00:56:58.928289 [Byte1]: 67
3510 00:56:58.932821
3511 00:56:58.932901 Set Vref, RX VrefLevel [Byte0]: 68
3512 00:56:58.935806 [Byte1]: 68
3513 00:56:58.940515
3514 00:56:58.940595 Set Vref, RX VrefLevel [Byte0]: 69
3515 00:56:58.943491 [Byte1]: 69
3516 00:56:58.948019
3517 00:56:58.948099 Final RX Vref Byte 0 = 48 to rank0
3518 00:56:58.951386 Final RX Vref Byte 1 = 61 to rank0
3519 00:56:58.955198 Final RX Vref Byte 0 = 48 to rank1
3520 00:56:58.958314 Final RX Vref Byte 1 = 61 to rank1==
3521 00:56:58.962079 Dram Type= 6, Freq= 0, CH_1, rank 0
3522 00:56:58.967975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 00:56:58.968057 ==
3524 00:56:58.968121 DQS Delay:
3525 00:56:58.968181 DQS0 = 0, DQS1 = 0
3526 00:56:58.971655 DQM Delay:
3527 00:56:58.971758 DQM0 = 116, DQM1 = 112
3528 00:56:58.975006 DQ Delay:
3529 00:56:58.978067 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3530 00:56:58.981737 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3531 00:56:58.984986 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3532 00:56:58.988054 DQ12 =120, DQ13 =120, DQ14 =122, DQ15 =122
3533 00:56:58.988168
3534 00:56:58.988233
3535 00:56:58.994850 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3536 00:56:58.997983 CH1 RK0: MR19=403, MR18=3F7
3537 00:56:59.004659 CH1_RK0: MR19=0x403, MR18=0x3F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3538 00:56:59.004741
3539 00:56:59.008151 ----->DramcWriteLeveling(PI) begin...
3540 00:56:59.008235 ==
3541 00:56:59.011334 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 00:56:59.014730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 00:56:59.017850 ==
3544 00:56:59.017930 Write leveling (Byte 0): 25 => 25
3545 00:56:59.021336 Write leveling (Byte 1): 28 => 28
3546 00:56:59.024738 DramcWriteLeveling(PI) end<-----
3547 00:56:59.024819
3548 00:56:59.024883 ==
3549 00:56:59.027891 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 00:56:59.034263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 00:56:59.034344 ==
3552 00:56:59.037738 [Gating] SW mode calibration
3553 00:56:59.044882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3554 00:56:59.047667 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3555 00:56:59.054217 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3556 00:56:59.058175 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3557 00:56:59.061330 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3558 00:56:59.067482 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3559 00:56:59.071128 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 00:56:59.074010 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 00:56:59.081184 0 15 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
3562 00:56:59.084287 0 15 28 | B1->B0 | 2424 2a2a | 0 0 | (1 0) (0 0)
3563 00:56:59.087504 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3564 00:56:59.093691 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3565 00:56:59.098106 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3566 00:56:59.100670 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3567 00:56:59.107227 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 00:56:59.110468 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 00:56:59.114127 1 0 24 | B1->B0 | 3c3c 2a29 | 0 1 | (0 0) (0 0)
3570 00:56:59.120485 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3571 00:56:59.123835 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 00:56:59.127097 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3573 00:56:59.130440 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3574 00:56:59.137047 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 00:56:59.140226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 00:56:59.144081 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 00:56:59.150388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3578 00:56:59.153352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3579 00:56:59.160554 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 00:56:59.163407 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 00:56:59.166500 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 00:56:59.169943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 00:56:59.176380 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 00:56:59.179916 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 00:56:59.183411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 00:56:59.189815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 00:56:59.193187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 00:56:59.196366 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 00:56:59.203006 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 00:56:59.206931 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 00:56:59.212534 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 00:56:59.215938 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 00:56:59.219188 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3594 00:56:59.225883 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3595 00:56:59.228903 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3596 00:56:59.232154 Total UI for P1: 0, mck2ui 16
3597 00:56:59.235951 best dqsien dly found for B0: ( 1, 3, 28)
3598 00:56:59.238795 Total UI for P1: 0, mck2ui 16
3599 00:56:59.242389 best dqsien dly found for B1: ( 1, 3, 26)
3600 00:56:59.245415 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3601 00:56:59.248818 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3602 00:56:59.248899
3603 00:56:59.252276 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3604 00:56:59.255312 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3605 00:56:59.258702 [Gating] SW calibration Done
3606 00:56:59.258781 ==
3607 00:56:59.261962 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 00:56:59.265588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 00:56:59.269067 ==
3610 00:56:59.269147 RX Vref Scan: 0
3611 00:56:59.269211
3612 00:56:59.271847 RX Vref 0 -> 0, step: 1
3613 00:56:59.271974
3614 00:56:59.275069 RX Delay -40 -> 252, step: 8
3615 00:56:59.278209 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3616 00:56:59.281825 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3617 00:56:59.285050 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3618 00:56:59.288451 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3619 00:56:59.294856 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3620 00:56:59.298482 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3621 00:56:59.301785 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3622 00:56:59.304858 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3623 00:56:59.308307 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3624 00:56:59.314637 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3625 00:56:59.318061 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3626 00:56:59.321071 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3627 00:56:59.324796 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3628 00:56:59.328094 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3629 00:56:59.334132 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3630 00:56:59.337963 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3631 00:56:59.338044 ==
3632 00:56:59.341588 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 00:56:59.344432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 00:56:59.344514 ==
3635 00:56:59.347830 DQS Delay:
3636 00:56:59.347911 DQS0 = 0, DQS1 = 0
3637 00:56:59.350912 DQM Delay:
3638 00:56:59.350992 DQM0 = 117, DQM1 = 110
3639 00:56:59.351056 DQ Delay:
3640 00:56:59.357157 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3641 00:56:59.360457 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3642 00:56:59.364099 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3643 00:56:59.367298 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3644 00:56:59.367379
3645 00:56:59.367443
3646 00:56:59.367502 ==
3647 00:56:59.370741 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 00:56:59.373665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 00:56:59.373746 ==
3650 00:56:59.373809
3651 00:56:59.373869
3652 00:56:59.376927 TX Vref Scan disable
3653 00:56:59.380451 == TX Byte 0 ==
3654 00:56:59.383709 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3655 00:56:59.387240 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3656 00:56:59.390360 == TX Byte 1 ==
3657 00:56:59.393788 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3658 00:56:59.396898 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3659 00:56:59.396979 ==
3660 00:56:59.399860 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 00:56:59.406442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 00:56:59.406526 ==
3663 00:56:59.417284 TX Vref=22, minBit 9, minWin=25, winSum=423
3664 00:56:59.420554 TX Vref=24, minBit 8, minWin=25, winSum=426
3665 00:56:59.423719 TX Vref=26, minBit 9, minWin=26, winSum=435
3666 00:56:59.426760 TX Vref=28, minBit 9, minWin=26, winSum=433
3667 00:56:59.430511 TX Vref=30, minBit 9, minWin=26, winSum=436
3668 00:56:59.437007 TX Vref=32, minBit 8, minWin=26, winSum=433
3669 00:56:59.440392 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3670 00:56:59.440474
3671 00:56:59.443695 Final TX Range 1 Vref 30
3672 00:56:59.443791
3673 00:56:59.443873 ==
3674 00:56:59.446752 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 00:56:59.450002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 00:56:59.453326 ==
3677 00:56:59.453431
3678 00:56:59.453529
3679 00:56:59.453591 TX Vref Scan disable
3680 00:56:59.457102 == TX Byte 0 ==
3681 00:56:59.459992 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3682 00:56:59.466427 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3683 00:56:59.466507 == TX Byte 1 ==
3684 00:56:59.470013 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3685 00:56:59.476741 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3686 00:56:59.476821
3687 00:56:59.476885 [DATLAT]
3688 00:56:59.476945 Freq=1200, CH1 RK1
3689 00:56:59.477003
3690 00:56:59.479788 DATLAT Default: 0xd
3691 00:56:59.483384 0, 0xFFFF, sum = 0
3692 00:56:59.483465 1, 0xFFFF, sum = 0
3693 00:56:59.486737 2, 0xFFFF, sum = 0
3694 00:56:59.486845 3, 0xFFFF, sum = 0
3695 00:56:59.489931 4, 0xFFFF, sum = 0
3696 00:56:59.490060 5, 0xFFFF, sum = 0
3697 00:56:59.493071 6, 0xFFFF, sum = 0
3698 00:56:59.493163 7, 0xFFFF, sum = 0
3699 00:56:59.496862 8, 0xFFFF, sum = 0
3700 00:56:59.496936 9, 0xFFFF, sum = 0
3701 00:56:59.500111 10, 0xFFFF, sum = 0
3702 00:56:59.500186 11, 0xFFFF, sum = 0
3703 00:56:59.502976 12, 0x0, sum = 1
3704 00:56:59.503050 13, 0x0, sum = 2
3705 00:56:59.506431 14, 0x0, sum = 3
3706 00:56:59.506505 15, 0x0, sum = 4
3707 00:56:59.509622 best_step = 13
3708 00:56:59.509702
3709 00:56:59.509766 ==
3710 00:56:59.513240 Dram Type= 6, Freq= 0, CH_1, rank 1
3711 00:56:59.516386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3712 00:56:59.516466 ==
3713 00:56:59.519951 RX Vref Scan: 0
3714 00:56:59.520032
3715 00:56:59.520095 RX Vref 0 -> 0, step: 1
3716 00:56:59.520155
3717 00:56:59.523173 RX Delay -21 -> 252, step: 4
3718 00:56:59.529636 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3719 00:56:59.532777 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3720 00:56:59.536582 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3721 00:56:59.539611 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3722 00:56:59.542674 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3723 00:56:59.549506 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3724 00:56:59.552831 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3725 00:56:59.556736 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3726 00:56:59.558906 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3727 00:56:59.562345 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3728 00:56:59.568962 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3729 00:56:59.572239 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3730 00:56:59.575812 iDelay=199, Bit 12, Center 118 (55 ~ 182) 128
3731 00:56:59.578715 iDelay=199, Bit 13, Center 118 (55 ~ 182) 128
3732 00:56:59.585463 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3733 00:56:59.589010 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3734 00:56:59.589110 ==
3735 00:56:59.592235 Dram Type= 6, Freq= 0, CH_1, rank 1
3736 00:56:59.595119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3737 00:56:59.595220 ==
3738 00:56:59.598795 DQS Delay:
3739 00:56:59.598871 DQS0 = 0, DQS1 = 0
3740 00:56:59.598932 DQM Delay:
3741 00:56:59.602786 DQM0 = 117, DQM1 = 111
3742 00:56:59.602886 DQ Delay:
3743 00:56:59.605142 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3744 00:56:59.608390 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3745 00:56:59.614859 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =102
3746 00:56:59.618433 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =120
3747 00:56:59.618505
3748 00:56:59.618567
3749 00:56:59.625042 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3750 00:56:59.628616 CH1 RK1: MR19=303, MR18=F6F1
3751 00:56:59.634870 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3752 00:56:59.637998 [RxdqsGatingPostProcess] freq 1200
3753 00:56:59.644987 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3754 00:56:59.645064 best DQS0 dly(2T, 0.5T) = (0, 11)
3755 00:56:59.648198 best DQS1 dly(2T, 0.5T) = (0, 11)
3756 00:56:59.651751 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3757 00:56:59.654727 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3758 00:56:59.658129 best DQS0 dly(2T, 0.5T) = (0, 11)
3759 00:56:59.661318 best DQS1 dly(2T, 0.5T) = (0, 11)
3760 00:56:59.664561 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3761 00:56:59.667467 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3762 00:56:59.671102 Pre-setting of DQS Precalculation
3763 00:56:59.677605 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3764 00:56:59.684391 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3765 00:56:59.690872 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3766 00:56:59.690949
3767 00:56:59.691014
3768 00:56:59.693960 [Calibration Summary] 2400 Mbps
3769 00:56:59.694034 CH 0, Rank 0
3770 00:56:59.697636 SW Impedance : PASS
3771 00:56:59.700871 DUTY Scan : NO K
3772 00:56:59.700947 ZQ Calibration : PASS
3773 00:56:59.703935 Jitter Meter : NO K
3774 00:56:59.707624 CBT Training : PASS
3775 00:56:59.707747 Write leveling : PASS
3776 00:56:59.710957 RX DQS gating : PASS
3777 00:56:59.711045 RX DQ/DQS(RDDQC) : PASS
3778 00:56:59.714294 TX DQ/DQS : PASS
3779 00:56:59.717637 RX DATLAT : PASS
3780 00:56:59.717733 RX DQ/DQS(Engine): PASS
3781 00:56:59.720624 TX OE : NO K
3782 00:56:59.720696 All Pass.
3783 00:56:59.720763
3784 00:56:59.724545 CH 0, Rank 1
3785 00:56:59.724620 SW Impedance : PASS
3786 00:56:59.727459 DUTY Scan : NO K
3787 00:56:59.731026 ZQ Calibration : PASS
3788 00:56:59.731095 Jitter Meter : NO K
3789 00:56:59.733763 CBT Training : PASS
3790 00:56:59.737118 Write leveling : PASS
3791 00:56:59.737189 RX DQS gating : PASS
3792 00:56:59.740436 RX DQ/DQS(RDDQC) : PASS
3793 00:56:59.743576 TX DQ/DQS : PASS
3794 00:56:59.743691 RX DATLAT : PASS
3795 00:56:59.747148 RX DQ/DQS(Engine): PASS
3796 00:56:59.750752 TX OE : NO K
3797 00:56:59.750826 All Pass.
3798 00:56:59.750888
3799 00:56:59.750953 CH 1, Rank 0
3800 00:56:59.753642 SW Impedance : PASS
3801 00:56:59.757060 DUTY Scan : NO K
3802 00:56:59.757131 ZQ Calibration : PASS
3803 00:56:59.760374 Jitter Meter : NO K
3804 00:56:59.763525 CBT Training : PASS
3805 00:56:59.763623 Write leveling : PASS
3806 00:56:59.767646 RX DQS gating : PASS
3807 00:56:59.770289 RX DQ/DQS(RDDQC) : PASS
3808 00:56:59.770358 TX DQ/DQS : PASS
3809 00:56:59.773425 RX DATLAT : PASS
3810 00:56:59.773499 RX DQ/DQS(Engine): PASS
3811 00:56:59.777086 TX OE : NO K
3812 00:56:59.777157 All Pass.
3813 00:56:59.777218
3814 00:56:59.780159 CH 1, Rank 1
3815 00:56:59.780231 SW Impedance : PASS
3816 00:56:59.784070 DUTY Scan : NO K
3817 00:56:59.786466 ZQ Calibration : PASS
3818 00:56:59.786608 Jitter Meter : NO K
3819 00:56:59.789972 CBT Training : PASS
3820 00:56:59.793257 Write leveling : PASS
3821 00:56:59.793335 RX DQS gating : PASS
3822 00:56:59.796644 RX DQ/DQS(RDDQC) : PASS
3823 00:56:59.799737 TX DQ/DQS : PASS
3824 00:56:59.799835 RX DATLAT : PASS
3825 00:56:59.803410 RX DQ/DQS(Engine): PASS
3826 00:56:59.806205 TX OE : NO K
3827 00:56:59.806300 All Pass.
3828 00:56:59.806390
3829 00:56:59.809659 DramC Write-DBI off
3830 00:56:59.809758 PER_BANK_REFRESH: Hybrid Mode
3831 00:56:59.813507 TX_TRACKING: ON
3832 00:56:59.822615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3833 00:56:59.826338 [FAST_K] Save calibration result to emmc
3834 00:56:59.829801 dramc_set_vcore_voltage set vcore to 650000
3835 00:56:59.829872 Read voltage for 600, 5
3836 00:56:59.832834 Vio18 = 0
3837 00:56:59.832908 Vcore = 650000
3838 00:56:59.832978 Vdram = 0
3839 00:56:59.836319 Vddq = 0
3840 00:56:59.836391 Vmddr = 0
3841 00:56:59.839531 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3842 00:56:59.846170 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3843 00:56:59.849768 MEM_TYPE=3, freq_sel=19
3844 00:56:59.852856 sv_algorithm_assistance_LP4_1600
3845 00:56:59.856113 ============ PULL DRAM RESETB DOWN ============
3846 00:56:59.859096 ========== PULL DRAM RESETB DOWN end =========
3847 00:56:59.865989 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 00:56:59.869906 ===================================
3849 00:56:59.869980 LPDDR4 DRAM CONFIGURATION
3850 00:56:59.872392 ===================================
3851 00:56:59.875866 EX_ROW_EN[0] = 0x0
3852 00:56:59.879449 EX_ROW_EN[1] = 0x0
3853 00:56:59.879520 LP4Y_EN = 0x0
3854 00:56:59.882540 WORK_FSP = 0x0
3855 00:56:59.882636 WL = 0x2
3856 00:56:59.886198 RL = 0x2
3857 00:56:59.886293 BL = 0x2
3858 00:56:59.889805 RPST = 0x0
3859 00:56:59.889879 RD_PRE = 0x0
3860 00:56:59.892447 WR_PRE = 0x1
3861 00:56:59.892523 WR_PST = 0x0
3862 00:56:59.895737 DBI_WR = 0x0
3863 00:56:59.895833 DBI_RD = 0x0
3864 00:56:59.898843 OTF = 0x1
3865 00:56:59.902687 ===================================
3866 00:56:59.906137 ===================================
3867 00:56:59.906235 ANA top config
3868 00:56:59.909069 ===================================
3869 00:56:59.912271 DLL_ASYNC_EN = 0
3870 00:56:59.915450 ALL_SLAVE_EN = 1
3871 00:56:59.918954 NEW_RANK_MODE = 1
3872 00:56:59.919027 DLL_IDLE_MODE = 1
3873 00:56:59.922372 LP45_APHY_COMB_EN = 1
3874 00:56:59.925399 TX_ODT_DIS = 1
3875 00:56:59.928637 NEW_8X_MODE = 1
3876 00:56:59.931853 ===================================
3877 00:56:59.935308 ===================================
3878 00:56:59.938374 data_rate = 1200
3879 00:56:59.938448 CKR = 1
3880 00:56:59.941994 DQ_P2S_RATIO = 8
3881 00:56:59.945065 ===================================
3882 00:56:59.948598 CA_P2S_RATIO = 8
3883 00:56:59.951596 DQ_CA_OPEN = 0
3884 00:56:59.955204 DQ_SEMI_OPEN = 0
3885 00:56:59.958557 CA_SEMI_OPEN = 0
3886 00:56:59.958628 CA_FULL_RATE = 0
3887 00:56:59.961815 DQ_CKDIV4_EN = 1
3888 00:56:59.964857 CA_CKDIV4_EN = 1
3889 00:56:59.968356 CA_PREDIV_EN = 0
3890 00:56:59.971314 PH8_DLY = 0
3891 00:56:59.975975 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3892 00:56:59.976051 DQ_AAMCK_DIV = 4
3893 00:56:59.978070 CA_AAMCK_DIV = 4
3894 00:56:59.981417 CA_ADMCK_DIV = 4
3895 00:56:59.985064 DQ_TRACK_CA_EN = 0
3896 00:56:59.988178 CA_PICK = 600
3897 00:56:59.991090 CA_MCKIO = 600
3898 00:56:59.994809 MCKIO_SEMI = 0
3899 00:56:59.994880 PLL_FREQ = 2288
3900 00:56:59.998215 DQ_UI_PI_RATIO = 32
3901 00:57:00.001985 CA_UI_PI_RATIO = 0
3902 00:57:00.004677 ===================================
3903 00:57:00.007746 ===================================
3904 00:57:00.011391 memory_type:LPDDR4
3905 00:57:00.011489 GP_NUM : 10
3906 00:57:00.014665 SRAM_EN : 1
3907 00:57:00.018017 MD32_EN : 0
3908 00:57:00.021205 ===================================
3909 00:57:00.021278 [ANA_INIT] >>>>>>>>>>>>>>
3910 00:57:00.024864 <<<<<< [CONFIGURE PHASE]: ANA_TX
3911 00:57:00.027644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3912 00:57:00.031036 ===================================
3913 00:57:00.034390 data_rate = 1200,PCW = 0X5800
3914 00:57:00.037893 ===================================
3915 00:57:00.041047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3916 00:57:00.047551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3917 00:57:00.054243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3918 00:57:00.057635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3919 00:57:00.060597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3920 00:57:00.064165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3921 00:57:00.067631 [ANA_INIT] flow start
3922 00:57:00.067749 [ANA_INIT] PLL >>>>>>>>
3923 00:57:00.070458 [ANA_INIT] PLL <<<<<<<<
3924 00:57:00.073825 [ANA_INIT] MIDPI >>>>>>>>
3925 00:57:00.073905 [ANA_INIT] MIDPI <<<<<<<<
3926 00:57:00.077330 [ANA_INIT] DLL >>>>>>>>
3927 00:57:00.080622 [ANA_INIT] flow end
3928 00:57:00.083962 ============ LP4 DIFF to SE enter ============
3929 00:57:00.087549 ============ LP4 DIFF to SE exit ============
3930 00:57:00.090532 [ANA_INIT] <<<<<<<<<<<<<
3931 00:57:00.093596 [Flow] Enable top DCM control >>>>>
3932 00:57:00.097065 [Flow] Enable top DCM control <<<<<
3933 00:57:00.100059 Enable DLL master slave shuffle
3934 00:57:00.104019 ==============================================================
3935 00:57:00.107000 Gating Mode config
3936 00:57:00.113481 ==============================================================
3937 00:57:00.113563 Config description:
3938 00:57:00.123471 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3939 00:57:00.129975 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3940 00:57:00.137093 SELPH_MODE 0: By rank 1: By Phase
3941 00:57:00.140131 ==============================================================
3942 00:57:00.143051 GAT_TRACK_EN = 1
3943 00:57:00.146774 RX_GATING_MODE = 2
3944 00:57:00.149733 RX_GATING_TRACK_MODE = 2
3945 00:57:00.153750 SELPH_MODE = 1
3946 00:57:00.156258 PICG_EARLY_EN = 1
3947 00:57:00.159510 VALID_LAT_VALUE = 1
3948 00:57:00.163163 ==============================================================
3949 00:57:00.169841 Enter into Gating configuration >>>>
3950 00:57:00.172988 Exit from Gating configuration <<<<
3951 00:57:00.173070 Enter into DVFS_PRE_config >>>>>
3952 00:57:00.186048 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3953 00:57:00.189451 Exit from DVFS_PRE_config <<<<<
3954 00:57:00.192830 Enter into PICG configuration >>>>
3955 00:57:00.196522 Exit from PICG configuration <<<<
3956 00:57:00.196603 [RX_INPUT] configuration >>>>>
3957 00:57:00.199533 [RX_INPUT] configuration <<<<<
3958 00:57:00.205903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3959 00:57:00.212896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3960 00:57:00.215760 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3961 00:57:00.222162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3962 00:57:00.229092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3963 00:57:00.235543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3964 00:57:00.238996 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3965 00:57:00.241977 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3966 00:57:00.248631 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3967 00:57:00.252313 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3968 00:57:00.255309 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3969 00:57:00.261736 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3970 00:57:00.264861 ===================================
3971 00:57:00.264976 LPDDR4 DRAM CONFIGURATION
3972 00:57:00.268318 ===================================
3973 00:57:00.271864 EX_ROW_EN[0] = 0x0
3974 00:57:00.274798 EX_ROW_EN[1] = 0x0
3975 00:57:00.274894 LP4Y_EN = 0x0
3976 00:57:00.277923 WORK_FSP = 0x0
3977 00:57:00.278004 WL = 0x2
3978 00:57:00.281393 RL = 0x2
3979 00:57:00.281473 BL = 0x2
3980 00:57:00.284450 RPST = 0x0
3981 00:57:00.284529 RD_PRE = 0x0
3982 00:57:00.287805 WR_PRE = 0x1
3983 00:57:00.287884 WR_PST = 0x0
3984 00:57:00.291355 DBI_WR = 0x0
3985 00:57:00.291435 DBI_RD = 0x0
3986 00:57:00.294727 OTF = 0x1
3987 00:57:00.298363 ===================================
3988 00:57:00.301429 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3989 00:57:00.305065 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3990 00:57:00.311005 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3991 00:57:00.314844 ===================================
3992 00:57:00.314925 LPDDR4 DRAM CONFIGURATION
3993 00:57:00.318279 ===================================
3994 00:57:00.321036 EX_ROW_EN[0] = 0x10
3995 00:57:00.324301 EX_ROW_EN[1] = 0x0
3996 00:57:00.324381 LP4Y_EN = 0x0
3997 00:57:00.327722 WORK_FSP = 0x0
3998 00:57:00.327803 WL = 0x2
3999 00:57:00.331246 RL = 0x2
4000 00:57:00.331327 BL = 0x2
4001 00:57:00.334337 RPST = 0x0
4002 00:57:00.334418 RD_PRE = 0x0
4003 00:57:00.337426 WR_PRE = 0x1
4004 00:57:00.337564 WR_PST = 0x0
4005 00:57:00.340708 DBI_WR = 0x0
4006 00:57:00.340789 DBI_RD = 0x0
4007 00:57:00.344302 OTF = 0x1
4008 00:57:00.347807 ===================================
4009 00:57:00.354040 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4010 00:57:00.357046 nWR fixed to 30
4011 00:57:00.360304 [ModeRegInit_LP4] CH0 RK0
4012 00:57:00.360384 [ModeRegInit_LP4] CH0 RK1
4013 00:57:00.363937 [ModeRegInit_LP4] CH1 RK0
4014 00:57:00.367589 [ModeRegInit_LP4] CH1 RK1
4015 00:57:00.367718 match AC timing 17
4016 00:57:00.373892 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4017 00:57:00.377244 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4018 00:57:00.380433 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4019 00:57:00.387070 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4020 00:57:00.390093 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4021 00:57:00.390175 ==
4022 00:57:00.393608 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 00:57:00.396911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 00:57:00.396993 ==
4025 00:57:00.403487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4026 00:57:00.410438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4027 00:57:00.413137 [CA 0] Center 36 (6~66) winsize 61
4028 00:57:00.417052 [CA 1] Center 36 (6~66) winsize 61
4029 00:57:00.420102 [CA 2] Center 34 (3~65) winsize 63
4030 00:57:00.423391 [CA 3] Center 34 (3~65) winsize 63
4031 00:57:00.426320 [CA 4] Center 33 (3~64) winsize 62
4032 00:57:00.429822 [CA 5] Center 33 (3~64) winsize 62
4033 00:57:00.429903
4034 00:57:00.432967 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4035 00:57:00.433048
4036 00:57:00.436376 [CATrainingPosCal] consider 1 rank data
4037 00:57:00.439907 u2DelayCellTimex100 = 270/100 ps
4038 00:57:00.443262 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4039 00:57:00.446548 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4040 00:57:00.449566 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4041 00:57:00.453171 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4042 00:57:00.456107 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4043 00:57:00.462670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4044 00:57:00.462751
4045 00:57:00.466076 CA PerBit enable=1, Macro0, CA PI delay=33
4046 00:57:00.466157
4047 00:57:00.469501 [CBTSetCACLKResult] CA Dly = 33
4048 00:57:00.469582 CS Dly: 5 (0~36)
4049 00:57:00.469647 ==
4050 00:57:00.472733 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 00:57:00.479461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 00:57:00.479542 ==
4053 00:57:00.482639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4054 00:57:00.489236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4055 00:57:00.492497 [CA 0] Center 36 (6~66) winsize 61
4056 00:57:00.495840 [CA 1] Center 36 (6~66) winsize 61
4057 00:57:00.498833 [CA 2] Center 33 (3~64) winsize 62
4058 00:57:00.502307 [CA 3] Center 33 (3~64) winsize 62
4059 00:57:00.505811 [CA 4] Center 33 (2~64) winsize 63
4060 00:57:00.509138 [CA 5] Center 33 (2~64) winsize 63
4061 00:57:00.509221
4062 00:57:00.512111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4063 00:57:00.512191
4064 00:57:00.515942 [CATrainingPosCal] consider 2 rank data
4065 00:57:00.518858 u2DelayCellTimex100 = 270/100 ps
4066 00:57:00.522103 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4067 00:57:00.528786 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4068 00:57:00.532160 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4069 00:57:00.535369 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4070 00:57:00.539180 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4071 00:57:00.541980 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4072 00:57:00.542077
4073 00:57:00.545576 CA PerBit enable=1, Macro0, CA PI delay=33
4074 00:57:00.545656
4075 00:57:00.548527 [CBTSetCACLKResult] CA Dly = 33
4076 00:57:00.548607 CS Dly: 5 (0~37)
4077 00:57:00.552302
4078 00:57:00.555262 ----->DramcWriteLeveling(PI) begin...
4079 00:57:00.555374 ==
4080 00:57:00.558689 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 00:57:00.561573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 00:57:00.561672 ==
4083 00:57:00.564810 Write leveling (Byte 0): 33 => 33
4084 00:57:00.568322 Write leveling (Byte 1): 29 => 29
4085 00:57:00.571517 DramcWriteLeveling(PI) end<-----
4086 00:57:00.571627
4087 00:57:00.571758 ==
4088 00:57:00.575098 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 00:57:00.578276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 00:57:00.578417 ==
4091 00:57:00.581520 [Gating] SW mode calibration
4092 00:57:00.588542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4093 00:57:00.594891 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4094 00:57:00.598412 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4095 00:57:00.601876 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4096 00:57:00.608129 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4097 00:57:00.610992 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4098 00:57:00.615421 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4099 00:57:00.621125 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 00:57:00.624814 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4101 00:57:00.627786 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4102 00:57:00.634375 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 00:57:00.638261 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 00:57:00.641111 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 00:57:00.647994 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4106 00:57:00.651359 0 10 16 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
4107 00:57:00.654290 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 00:57:00.660579 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4109 00:57:00.664058 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4110 00:57:00.667492 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 00:57:00.674209 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 00:57:00.677616 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 00:57:00.680835 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 00:57:00.687906 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 00:57:00.690233 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 00:57:00.694113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 00:57:00.700451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 00:57:00.703824 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 00:57:00.707032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 00:57:00.713678 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 00:57:00.716871 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 00:57:00.720107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 00:57:00.726797 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 00:57:00.729812 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 00:57:00.733329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 00:57:00.739978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 00:57:00.743325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 00:57:00.746830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 00:57:00.753251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4130 00:57:00.757198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4131 00:57:00.760031 Total UI for P1: 0, mck2ui 16
4132 00:57:00.763167 best dqsien dly found for B0: ( 0, 13, 14)
4133 00:57:00.766649 Total UI for P1: 0, mck2ui 16
4134 00:57:00.769865 best dqsien dly found for B1: ( 0, 13, 12)
4135 00:57:00.773042 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4136 00:57:00.776424 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4137 00:57:00.776529
4138 00:57:00.779860 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4139 00:57:00.783546 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4140 00:57:00.786410 [Gating] SW calibration Done
4141 00:57:00.786524 ==
4142 00:57:00.789528 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 00:57:00.792912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 00:57:00.795965 ==
4145 00:57:00.796045 RX Vref Scan: 0
4146 00:57:00.796109
4147 00:57:00.799433 RX Vref 0 -> 0, step: 1
4148 00:57:00.799513
4149 00:57:00.802902 RX Delay -230 -> 252, step: 16
4150 00:57:00.806222 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4151 00:57:00.809220 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4152 00:57:00.812581 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4153 00:57:00.819521 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4154 00:57:00.822664 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4155 00:57:00.825834 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4156 00:57:00.829523 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4157 00:57:00.832731 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4158 00:57:00.839167 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4159 00:57:00.843043 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4160 00:57:00.845674 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4161 00:57:00.849011 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4162 00:57:00.855553 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4163 00:57:00.858924 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4164 00:57:00.862232 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4165 00:57:00.866186 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4166 00:57:00.869021 ==
4167 00:57:00.872053 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 00:57:00.876025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 00:57:00.876138 ==
4170 00:57:00.876203 DQS Delay:
4171 00:57:00.878739 DQS0 = 0, DQS1 = 0
4172 00:57:00.878820 DQM Delay:
4173 00:57:00.881778 DQM0 = 42, DQM1 = 30
4174 00:57:00.881859 DQ Delay:
4175 00:57:00.885801 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4176 00:57:00.888896 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4177 00:57:00.891691 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4178 00:57:00.895356 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4179 00:57:00.895436
4180 00:57:00.895501
4181 00:57:00.895561 ==
4182 00:57:00.899090 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 00:57:00.901900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 00:57:00.901997 ==
4185 00:57:00.902074
4186 00:57:00.902166
4187 00:57:00.905151 TX Vref Scan disable
4188 00:57:00.908691 == TX Byte 0 ==
4189 00:57:00.911955 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4190 00:57:00.915014 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4191 00:57:00.918169 == TX Byte 1 ==
4192 00:57:00.921513 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4193 00:57:00.924840 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4194 00:57:00.924950 ==
4195 00:57:00.928550 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 00:57:00.934593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 00:57:00.934677 ==
4198 00:57:00.934744
4199 00:57:00.934805
4200 00:57:00.934864 TX Vref Scan disable
4201 00:57:00.939847 == TX Byte 0 ==
4202 00:57:00.943039 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4203 00:57:00.949138 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4204 00:57:00.949221 == TX Byte 1 ==
4205 00:57:00.952354 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4206 00:57:00.959070 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4207 00:57:00.959186
4208 00:57:00.959286 [DATLAT]
4209 00:57:00.959375 Freq=600, CH0 RK0
4210 00:57:00.959462
4211 00:57:00.962531 DATLAT Default: 0x9
4212 00:57:00.962614 0, 0xFFFF, sum = 0
4213 00:57:00.965932 1, 0xFFFF, sum = 0
4214 00:57:00.969076 2, 0xFFFF, sum = 0
4215 00:57:00.969160 3, 0xFFFF, sum = 0
4216 00:57:00.972510 4, 0xFFFF, sum = 0
4217 00:57:00.972594 5, 0xFFFF, sum = 0
4218 00:57:00.975570 6, 0xFFFF, sum = 0
4219 00:57:00.975654 7, 0xFFFF, sum = 0
4220 00:57:00.978667 8, 0x0, sum = 1
4221 00:57:00.978752 9, 0x0, sum = 2
4222 00:57:00.978820 10, 0x0, sum = 3
4223 00:57:00.982550 11, 0x0, sum = 4
4224 00:57:00.982634 best_step = 9
4225 00:57:00.982700
4226 00:57:00.985861 ==
4227 00:57:00.985971 Dram Type= 6, Freq= 0, CH_0, rank 0
4228 00:57:00.991922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 00:57:00.992006 ==
4230 00:57:00.992071 RX Vref Scan: 1
4231 00:57:00.992134
4232 00:57:00.995460 RX Vref 0 -> 0, step: 1
4233 00:57:00.995543
4234 00:57:00.998574 RX Delay -195 -> 252, step: 8
4235 00:57:00.998682
4236 00:57:01.002439 Set Vref, RX VrefLevel [Byte0]: 59
4237 00:57:01.005106 [Byte1]: 49
4238 00:57:01.005212
4239 00:57:01.008565 Final RX Vref Byte 0 = 59 to rank0
4240 00:57:01.011543 Final RX Vref Byte 1 = 49 to rank0
4241 00:57:01.014993 Final RX Vref Byte 0 = 59 to rank1
4242 00:57:01.018126 Final RX Vref Byte 1 = 49 to rank1==
4243 00:57:01.021344 Dram Type= 6, Freq= 0, CH_0, rank 0
4244 00:57:01.028353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 00:57:01.028432 ==
4246 00:57:01.028497 DQS Delay:
4247 00:57:01.028559 DQS0 = 0, DQS1 = 0
4248 00:57:01.031167 DQM Delay:
4249 00:57:01.031266 DQM0 = 43, DQM1 = 32
4250 00:57:01.034455 DQ Delay:
4251 00:57:01.037812 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4252 00:57:01.041519 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4253 00:57:01.044585 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4254 00:57:01.048035 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4255 00:57:01.048114
4256 00:57:01.048179
4257 00:57:01.054352 [DQSOSCAuto] RK0, (LSB)MR18= 0x663c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4258 00:57:01.057430 CH0 RK0: MR19=808, MR18=663C
4259 00:57:01.064373 CH0_RK0: MR19=0x808, MR18=0x663C, DQSOSC=390, MR23=63, INC=172, DEC=114
4260 00:57:01.064458
4261 00:57:01.067945 ----->DramcWriteLeveling(PI) begin...
4262 00:57:01.068051 ==
4263 00:57:01.070932 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 00:57:01.074195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 00:57:01.074302 ==
4266 00:57:01.078036 Write leveling (Byte 0): 31 => 31
4267 00:57:01.080495 Write leveling (Byte 1): 31 => 31
4268 00:57:01.083753 DramcWriteLeveling(PI) end<-----
4269 00:57:01.083832
4270 00:57:01.083897 ==
4271 00:57:01.087502 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 00:57:01.090330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 00:57:01.093816 ==
4274 00:57:01.093922 [Gating] SW mode calibration
4275 00:57:01.103747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4276 00:57:01.106969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4277 00:57:01.110787 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4278 00:57:01.116846 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4279 00:57:01.120185 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4280 00:57:01.123513 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4281 00:57:01.129899 0 9 16 | B1->B0 | 2e2e 2a2a | 0 0 | (1 1) (0 0)
4282 00:57:01.133680 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 00:57:01.136775 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 00:57:01.143224 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 00:57:01.146868 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 00:57:01.149673 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 00:57:01.156560 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 00:57:01.159710 0 10 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4289 00:57:01.162900 0 10 16 | B1->B0 | 3c3c 4040 | 1 0 | (0 0) (0 0)
4290 00:57:01.169837 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 00:57:01.172958 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 00:57:01.176564 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 00:57:01.183530 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 00:57:01.186446 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 00:57:01.189802 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 00:57:01.196037 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 00:57:01.199605 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4298 00:57:01.202585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 00:57:01.209893 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 00:57:01.212703 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:57:01.216076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:57:01.222821 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:57:01.226072 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:57:01.229522 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:57:01.235712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 00:57:01.239451 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 00:57:01.242259 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 00:57:01.249157 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 00:57:01.253062 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 00:57:01.255697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 00:57:01.262238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 00:57:01.265892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4313 00:57:01.269030 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4314 00:57:01.272148 Total UI for P1: 0, mck2ui 16
4315 00:57:01.275566 best dqsien dly found for B0: ( 0, 13, 12)
4316 00:57:01.282119 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4317 00:57:01.282205 Total UI for P1: 0, mck2ui 16
4318 00:57:01.288421 best dqsien dly found for B1: ( 0, 13, 14)
4319 00:57:01.291977 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4320 00:57:01.295447 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4321 00:57:01.295560
4322 00:57:01.298858 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4323 00:57:01.301578 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4324 00:57:01.305468 [Gating] SW calibration Done
4325 00:57:01.305551 ==
4326 00:57:01.308745 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 00:57:01.311643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 00:57:01.311734 ==
4329 00:57:01.315520 RX Vref Scan: 0
4330 00:57:01.315603
4331 00:57:01.315675 RX Vref 0 -> 0, step: 1
4332 00:57:01.318313
4333 00:57:01.318422 RX Delay -230 -> 252, step: 16
4334 00:57:01.324551 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4335 00:57:01.328169 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4336 00:57:01.331185 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4337 00:57:01.334996 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4338 00:57:01.341650 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4339 00:57:01.344593 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4340 00:57:01.348398 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4341 00:57:01.351213 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4342 00:57:01.354829 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4343 00:57:01.360970 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4344 00:57:01.364810 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4345 00:57:01.367548 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4346 00:57:01.371087 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4347 00:57:01.377450 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4348 00:57:01.381263 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4349 00:57:01.384026 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4350 00:57:01.384106 ==
4351 00:57:01.387547 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 00:57:01.394227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 00:57:01.394333 ==
4354 00:57:01.394430 DQS Delay:
4355 00:57:01.397207 DQS0 = 0, DQS1 = 0
4356 00:57:01.397292 DQM Delay:
4357 00:57:01.397358 DQM0 = 44, DQM1 = 37
4358 00:57:01.400801 DQ Delay:
4359 00:57:01.404257 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4360 00:57:01.407392 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4361 00:57:01.410539 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4362 00:57:01.414072 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4363 00:57:01.414183
4364 00:57:01.414283
4365 00:57:01.414372 ==
4366 00:57:01.417359 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 00:57:01.420423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 00:57:01.420527 ==
4369 00:57:01.420620
4370 00:57:01.420711
4371 00:57:01.423732 TX Vref Scan disable
4372 00:57:01.426991 == TX Byte 0 ==
4373 00:57:01.430036 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4374 00:57:01.433791 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4375 00:57:01.436738 == TX Byte 1 ==
4376 00:57:01.440259 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4377 00:57:01.443324 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4378 00:57:01.443423 ==
4379 00:57:01.447024 Dram Type= 6, Freq= 0, CH_0, rank 1
4380 00:57:01.449916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 00:57:01.453720 ==
4382 00:57:01.453795
4383 00:57:01.453861
4384 00:57:01.453922 TX Vref Scan disable
4385 00:57:01.457565 == TX Byte 0 ==
4386 00:57:01.460300 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4387 00:57:01.467488 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4388 00:57:01.467571 == TX Byte 1 ==
4389 00:57:01.470109 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4390 00:57:01.477264 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4391 00:57:01.477348
4392 00:57:01.477413 [DATLAT]
4393 00:57:01.477474 Freq=600, CH0 RK1
4394 00:57:01.477535
4395 00:57:01.480109 DATLAT Default: 0x9
4396 00:57:01.480191 0, 0xFFFF, sum = 0
4397 00:57:01.483290 1, 0xFFFF, sum = 0
4398 00:57:01.486707 2, 0xFFFF, sum = 0
4399 00:57:01.486790 3, 0xFFFF, sum = 0
4400 00:57:01.490284 4, 0xFFFF, sum = 0
4401 00:57:01.490368 5, 0xFFFF, sum = 0
4402 00:57:01.493527 6, 0xFFFF, sum = 0
4403 00:57:01.493612 7, 0xFFFF, sum = 0
4404 00:57:01.496658 8, 0x0, sum = 1
4405 00:57:01.496740 9, 0x0, sum = 2
4406 00:57:01.499798 10, 0x0, sum = 3
4407 00:57:01.499908 11, 0x0, sum = 4
4408 00:57:01.499998 best_step = 9
4409 00:57:01.500061
4410 00:57:01.503418 ==
4411 00:57:01.506652 Dram Type= 6, Freq= 0, CH_0, rank 1
4412 00:57:01.510250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 00:57:01.510332 ==
4414 00:57:01.510398 RX Vref Scan: 0
4415 00:57:01.510461
4416 00:57:01.512890 RX Vref 0 -> 0, step: 1
4417 00:57:01.512972
4418 00:57:01.516339 RX Delay -179 -> 252, step: 8
4419 00:57:01.523235 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4420 00:57:01.526461 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4421 00:57:01.529516 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4422 00:57:01.533391 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4423 00:57:01.536995 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4424 00:57:01.542799 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4425 00:57:01.546040 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4426 00:57:01.549314 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4427 00:57:01.552765 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4428 00:57:01.559387 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4429 00:57:01.562692 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4430 00:57:01.566055 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4431 00:57:01.569664 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4432 00:57:01.575804 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4433 00:57:01.579372 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4434 00:57:01.582586 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4435 00:57:01.582668 ==
4436 00:57:01.585987 Dram Type= 6, Freq= 0, CH_0, rank 1
4437 00:57:01.589133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 00:57:01.592532 ==
4439 00:57:01.592617 DQS Delay:
4440 00:57:01.592689 DQS0 = 0, DQS1 = 0
4441 00:57:01.595340 DQM Delay:
4442 00:57:01.595448 DQM0 = 41, DQM1 = 37
4443 00:57:01.598808 DQ Delay:
4444 00:57:01.601881 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4445 00:57:01.601963 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4446 00:57:01.605396 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4447 00:57:01.611917 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4448 00:57:01.611999
4449 00:57:01.612064
4450 00:57:01.618815 [DQSOSCAuto] RK1, (LSB)MR18= 0x6619, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4451 00:57:01.622250 CH0 RK1: MR19=808, MR18=6619
4452 00:57:01.628456 CH0_RK1: MR19=0x808, MR18=0x6619, DQSOSC=390, MR23=63, INC=172, DEC=114
4453 00:57:01.632327 [RxdqsGatingPostProcess] freq 600
4454 00:57:01.635239 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4455 00:57:01.638164 Pre-setting of DQS Precalculation
4456 00:57:01.645362 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4457 00:57:01.645445 ==
4458 00:57:01.648884 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 00:57:01.651962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 00:57:01.652045 ==
4461 00:57:01.658036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4462 00:57:01.665145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4463 00:57:01.667955 [CA 0] Center 35 (5~66) winsize 62
4464 00:57:01.671550 [CA 1] Center 36 (6~66) winsize 61
4465 00:57:01.674605 [CA 2] Center 34 (3~65) winsize 63
4466 00:57:01.678082 [CA 3] Center 33 (3~64) winsize 62
4467 00:57:01.681780 [CA 4] Center 34 (4~64) winsize 61
4468 00:57:01.684763 [CA 5] Center 33 (3~64) winsize 62
4469 00:57:01.684846
4470 00:57:01.688124 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4471 00:57:01.688206
4472 00:57:01.691299 [CATrainingPosCal] consider 1 rank data
4473 00:57:01.694641 u2DelayCellTimex100 = 270/100 ps
4474 00:57:01.697755 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4475 00:57:01.701120 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4476 00:57:01.704457 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4477 00:57:01.707417 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 00:57:01.710965 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4479 00:57:01.714260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4480 00:57:01.714348
4481 00:57:01.720822 CA PerBit enable=1, Macro0, CA PI delay=33
4482 00:57:01.720908
4483 00:57:01.720977 [CBTSetCACLKResult] CA Dly = 33
4484 00:57:01.724263 CS Dly: 5 (0~36)
4485 00:57:01.724346 ==
4486 00:57:01.727651 Dram Type= 6, Freq= 0, CH_1, rank 1
4487 00:57:01.731093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 00:57:01.731178 ==
4489 00:57:01.737655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4490 00:57:01.744288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4491 00:57:01.747421 [CA 0] Center 35 (5~66) winsize 62
4492 00:57:01.751272 [CA 1] Center 36 (6~66) winsize 61
4493 00:57:01.754401 [CA 2] Center 34 (4~65) winsize 62
4494 00:57:01.757299 [CA 3] Center 34 (3~65) winsize 63
4495 00:57:01.761104 [CA 4] Center 34 (4~65) winsize 62
4496 00:57:01.763930 [CA 5] Center 34 (3~65) winsize 63
4497 00:57:01.764008
4498 00:57:01.767292 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4499 00:57:01.767392
4500 00:57:01.770803 [CATrainingPosCal] consider 2 rank data
4501 00:57:01.773855 u2DelayCellTimex100 = 270/100 ps
4502 00:57:01.777325 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4503 00:57:01.780243 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4504 00:57:01.783836 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4505 00:57:01.787675 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4506 00:57:01.790272 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4507 00:57:01.797283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4508 00:57:01.797367
4509 00:57:01.800150 CA PerBit enable=1, Macro0, CA PI delay=33
4510 00:57:01.800224
4511 00:57:01.803862 [CBTSetCACLKResult] CA Dly = 33
4512 00:57:01.803963 CS Dly: 5 (0~37)
4513 00:57:01.804055
4514 00:57:01.807261 ----->DramcWriteLeveling(PI) begin...
4515 00:57:01.807359 ==
4516 00:57:01.810383 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 00:57:01.817256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 00:57:01.817338 ==
4519 00:57:01.820622 Write leveling (Byte 0): 29 => 29
4520 00:57:01.820699 Write leveling (Byte 1): 30 => 30
4521 00:57:01.823464 DramcWriteLeveling(PI) end<-----
4522 00:57:01.823565
4523 00:57:01.826508 ==
4524 00:57:01.826606 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 00:57:01.832890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 00:57:01.832971 ==
4527 00:57:01.836690 [Gating] SW mode calibration
4528 00:57:01.843517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4529 00:57:01.846360 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4530 00:57:01.853284 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4531 00:57:01.856594 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4532 00:57:01.859795 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4533 00:57:01.866151 0 9 12 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 1)
4534 00:57:01.869789 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 00:57:01.873195 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4536 00:57:01.879129 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4537 00:57:01.882471 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4538 00:57:01.885668 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4539 00:57:01.893326 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4540 00:57:01.896278 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4541 00:57:01.899313 0 10 12 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
4542 00:57:01.905898 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4543 00:57:01.908857 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 00:57:01.912700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4545 00:57:01.918671 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4546 00:57:01.922197 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4547 00:57:01.925791 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 00:57:01.932701 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 00:57:01.935196 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 00:57:01.939098 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 00:57:01.945371 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 00:57:01.948568 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 00:57:01.952167 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 00:57:01.958257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 00:57:01.961848 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 00:57:01.965148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 00:57:01.971491 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 00:57:01.975077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 00:57:01.978042 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 00:57:01.984619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 00:57:01.988084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 00:57:01.991705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 00:57:01.998590 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 00:57:02.001377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 00:57:02.004753 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4566 00:57:02.007942 Total UI for P1: 0, mck2ui 16
4567 00:57:02.010905 best dqsien dly found for B0: ( 0, 13, 10)
4568 00:57:02.018182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4569 00:57:02.018286 Total UI for P1: 0, mck2ui 16
4570 00:57:02.024881 best dqsien dly found for B1: ( 0, 13, 12)
4571 00:57:02.027532 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4572 00:57:02.031020 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4573 00:57:02.031120
4574 00:57:02.033967 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4575 00:57:02.037650 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4576 00:57:02.040592 [Gating] SW calibration Done
4577 00:57:02.040689 ==
4578 00:57:02.043837 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 00:57:02.047192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 00:57:02.047283 ==
4581 00:57:02.050868 RX Vref Scan: 0
4582 00:57:02.050945
4583 00:57:02.053744 RX Vref 0 -> 0, step: 1
4584 00:57:02.053820
4585 00:57:02.053884 RX Delay -230 -> 252, step: 16
4586 00:57:02.060468 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4587 00:57:02.063802 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4588 00:57:02.067146 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4589 00:57:02.070447 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4590 00:57:02.077347 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4591 00:57:02.080463 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4592 00:57:02.083527 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4593 00:57:02.087158 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4594 00:57:02.094003 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4595 00:57:02.097002 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4596 00:57:02.100000 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4597 00:57:02.103363 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4598 00:57:02.110177 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4599 00:57:02.113549 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4600 00:57:02.116690 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4601 00:57:02.119730 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4602 00:57:02.119804 ==
4603 00:57:02.123065 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 00:57:02.129961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 00:57:02.130043 ==
4606 00:57:02.130110 DQS Delay:
4607 00:57:02.133039 DQS0 = 0, DQS1 = 0
4608 00:57:02.133133 DQM Delay:
4609 00:57:02.133222 DQM0 = 46, DQM1 = 36
4610 00:57:02.136453 DQ Delay:
4611 00:57:02.139461 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4612 00:57:02.143128 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4613 00:57:02.146015 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4614 00:57:02.150031 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4615 00:57:02.150106
4616 00:57:02.150174
4617 00:57:02.150234 ==
4618 00:57:02.152906 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 00:57:02.156132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 00:57:02.156205 ==
4621 00:57:02.156268
4622 00:57:02.156329
4623 00:57:02.159505 TX Vref Scan disable
4624 00:57:02.159609 == TX Byte 0 ==
4625 00:57:02.166107 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4626 00:57:02.169803 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4627 00:57:02.172891 == TX Byte 1 ==
4628 00:57:02.176457 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4629 00:57:02.179100 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4630 00:57:02.179174 ==
4631 00:57:02.182656 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 00:57:02.185800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 00:57:02.189188 ==
4634 00:57:02.189292
4635 00:57:02.189384
4636 00:57:02.189474 TX Vref Scan disable
4637 00:57:02.193055 == TX Byte 0 ==
4638 00:57:02.196539 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4639 00:57:02.203284 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4640 00:57:02.203382 == TX Byte 1 ==
4641 00:57:02.206059 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4642 00:57:02.212597 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4643 00:57:02.212699
4644 00:57:02.212792 [DATLAT]
4645 00:57:02.212884 Freq=600, CH1 RK0
4646 00:57:02.212971
4647 00:57:02.215765 DATLAT Default: 0x9
4648 00:57:02.219633 0, 0xFFFF, sum = 0
4649 00:57:02.219739 1, 0xFFFF, sum = 0
4650 00:57:02.222552 2, 0xFFFF, sum = 0
4651 00:57:02.222654 3, 0xFFFF, sum = 0
4652 00:57:02.225663 4, 0xFFFF, sum = 0
4653 00:57:02.225763 5, 0xFFFF, sum = 0
4654 00:57:02.228923 6, 0xFFFF, sum = 0
4655 00:57:02.228994 7, 0xFFFF, sum = 0
4656 00:57:02.232469 8, 0x0, sum = 1
4657 00:57:02.232543 9, 0x0, sum = 2
4658 00:57:02.235616 10, 0x0, sum = 3
4659 00:57:02.235731 11, 0x0, sum = 4
4660 00:57:02.235825 best_step = 9
4661 00:57:02.235913
4662 00:57:02.239019 ==
4663 00:57:02.242253 Dram Type= 6, Freq= 0, CH_1, rank 0
4664 00:57:02.245869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 00:57:02.245977 ==
4666 00:57:02.246072 RX Vref Scan: 1
4667 00:57:02.246161
4668 00:57:02.249072 RX Vref 0 -> 0, step: 1
4669 00:57:02.249231
4670 00:57:02.252341 RX Delay -195 -> 252, step: 8
4671 00:57:02.252444
4672 00:57:02.255846 Set Vref, RX VrefLevel [Byte0]: 48
4673 00:57:02.259820 [Byte1]: 61
4674 00:57:02.259902
4675 00:57:02.262058 Final RX Vref Byte 0 = 48 to rank0
4676 00:57:02.265588 Final RX Vref Byte 1 = 61 to rank0
4677 00:57:02.268633 Final RX Vref Byte 0 = 48 to rank1
4678 00:57:02.272415 Final RX Vref Byte 1 = 61 to rank1==
4679 00:57:02.275886 Dram Type= 6, Freq= 0, CH_1, rank 0
4680 00:57:02.278814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 00:57:02.282134 ==
4682 00:57:02.282239 DQS Delay:
4683 00:57:02.282330 DQS0 = 0, DQS1 = 0
4684 00:57:02.285204 DQM Delay:
4685 00:57:02.285293 DQM0 = 46, DQM1 = 37
4686 00:57:02.288497 DQ Delay:
4687 00:57:02.292054 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4688 00:57:02.295181 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4689 00:57:02.298324 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4690 00:57:02.301293 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4691 00:57:02.301395
4692 00:57:02.301489
4693 00:57:02.308690 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f35, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4694 00:57:02.311323 CH1 RK0: MR19=808, MR18=4F35
4695 00:57:02.318055 CH1_RK0: MR19=0x808, MR18=0x4F35, DQSOSC=394, MR23=63, INC=168, DEC=112
4696 00:57:02.318159
4697 00:57:02.321185 ----->DramcWriteLeveling(PI) begin...
4698 00:57:02.321260 ==
4699 00:57:02.324548 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 00:57:02.327933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 00:57:02.328010 ==
4702 00:57:02.331009 Write leveling (Byte 0): 30 => 30
4703 00:57:02.334686 Write leveling (Byte 1): 30 => 30
4704 00:57:02.337633 DramcWriteLeveling(PI) end<-----
4705 00:57:02.337707
4706 00:57:02.337770 ==
4707 00:57:02.340918 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 00:57:02.344561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 00:57:02.348278 ==
4710 00:57:02.348361 [Gating] SW mode calibration
4711 00:57:02.354755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4712 00:57:02.360943 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4713 00:57:02.364216 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4714 00:57:02.371045 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4715 00:57:02.374135 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4716 00:57:02.377515 0 9 12 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
4717 00:57:02.384284 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4718 00:57:02.387152 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 00:57:02.390631 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4720 00:57:02.397527 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4721 00:57:02.400472 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4722 00:57:02.403814 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4723 00:57:02.410563 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4724 00:57:02.413798 0 10 12 | B1->B0 | 3333 2929 | 0 0 | (1 1) (0 0)
4725 00:57:02.417364 0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
4726 00:57:02.424097 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 00:57:02.427094 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4728 00:57:02.430706 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 00:57:02.436892 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4730 00:57:02.440256 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 00:57:02.443499 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 00:57:02.450117 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4733 00:57:02.453415 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 00:57:02.456947 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 00:57:02.463044 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 00:57:02.466590 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 00:57:02.470092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 00:57:02.476394 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 00:57:02.479652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 00:57:02.483446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 00:57:02.489685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 00:57:02.492993 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 00:57:02.495906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 00:57:02.502830 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 00:57:02.505705 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 00:57:02.509007 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 00:57:02.515965 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 00:57:02.518829 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4749 00:57:02.522559 Total UI for P1: 0, mck2ui 16
4750 00:57:02.525721 best dqsien dly found for B1: ( 0, 13, 10)
4751 00:57:02.529006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4752 00:57:02.532192 Total UI for P1: 0, mck2ui 16
4753 00:57:02.535535 best dqsien dly found for B0: ( 0, 13, 12)
4754 00:57:02.538497 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4755 00:57:02.542135 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4756 00:57:02.545175
4757 00:57:02.548893 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4758 00:57:02.552220 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4759 00:57:02.555093 [Gating] SW calibration Done
4760 00:57:02.555190 ==
4761 00:57:02.558647 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 00:57:02.561870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 00:57:02.561970 ==
4764 00:57:02.562060 RX Vref Scan: 0
4765 00:57:02.564896
4766 00:57:02.564966 RX Vref 0 -> 0, step: 1
4767 00:57:02.565027
4768 00:57:02.568651 RX Delay -230 -> 252, step: 16
4769 00:57:02.571504 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4770 00:57:02.578310 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4771 00:57:02.581774 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4772 00:57:02.584872 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4773 00:57:02.588828 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4774 00:57:02.591388 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4775 00:57:02.598467 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4776 00:57:02.601438 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4777 00:57:02.604665 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4778 00:57:02.608204 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4779 00:57:02.614831 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4780 00:57:02.617843 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4781 00:57:02.621094 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4782 00:57:02.624261 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4783 00:57:02.631012 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4784 00:57:02.634771 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4785 00:57:02.634873 ==
4786 00:57:02.637728 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 00:57:02.640862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 00:57:02.640938 ==
4789 00:57:02.644565 DQS Delay:
4790 00:57:02.644665 DQS0 = 0, DQS1 = 0
4791 00:57:02.647526 DQM Delay:
4792 00:57:02.647600 DQM0 = 44, DQM1 = 36
4793 00:57:02.647662 DQ Delay:
4794 00:57:02.651056 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4795 00:57:02.654150 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4796 00:57:02.657764 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4797 00:57:02.660785 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4798 00:57:02.660858
4799 00:57:02.660921
4800 00:57:02.663974 ==
4801 00:57:02.664048 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 00:57:02.670361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 00:57:02.670466 ==
4804 00:57:02.670561
4805 00:57:02.670652
4806 00:57:02.673702 TX Vref Scan disable
4807 00:57:02.673800 == TX Byte 0 ==
4808 00:57:02.680485 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4809 00:57:02.683851 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4810 00:57:02.683933 == TX Byte 1 ==
4811 00:57:02.690840 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4812 00:57:02.693715 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4813 00:57:02.693819 ==
4814 00:57:02.696854 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 00:57:02.700651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 00:57:02.700761 ==
4817 00:57:02.700854
4818 00:57:02.700943
4819 00:57:02.703631 TX Vref Scan disable
4820 00:57:02.707214 == TX Byte 0 ==
4821 00:57:02.710234 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4822 00:57:02.713547 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4823 00:57:02.716575 == TX Byte 1 ==
4824 00:57:02.720234 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4825 00:57:02.723622 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4826 00:57:02.723737
4827 00:57:02.726873 [DATLAT]
4828 00:57:02.726971 Freq=600, CH1 RK1
4829 00:57:02.727072
4830 00:57:02.730083 DATLAT Default: 0x9
4831 00:57:02.730186 0, 0xFFFF, sum = 0
4832 00:57:02.733529 1, 0xFFFF, sum = 0
4833 00:57:02.733627 2, 0xFFFF, sum = 0
4834 00:57:02.736928 3, 0xFFFF, sum = 0
4835 00:57:02.737005 4, 0xFFFF, sum = 0
4836 00:57:02.739801 5, 0xFFFF, sum = 0
4837 00:57:02.743194 6, 0xFFFF, sum = 0
4838 00:57:02.743268 7, 0xFFFF, sum = 0
4839 00:57:02.743345 8, 0x0, sum = 1
4840 00:57:02.746535 9, 0x0, sum = 2
4841 00:57:02.746617 10, 0x0, sum = 3
4842 00:57:02.749554 11, 0x0, sum = 4
4843 00:57:02.749642 best_step = 9
4844 00:57:02.749734
4845 00:57:02.749821 ==
4846 00:57:02.753342 Dram Type= 6, Freq= 0, CH_1, rank 1
4847 00:57:02.759901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4848 00:57:02.759977 ==
4849 00:57:02.760045 RX Vref Scan: 0
4850 00:57:02.760114
4851 00:57:02.762861 RX Vref 0 -> 0, step: 1
4852 00:57:02.762945
4853 00:57:02.766241 RX Delay -195 -> 252, step: 8
4854 00:57:02.769665 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4855 00:57:02.775863 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4856 00:57:02.779194 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4857 00:57:02.782849 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4858 00:57:02.786165 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4859 00:57:02.792317 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4860 00:57:02.795766 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4861 00:57:02.798959 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4862 00:57:02.802365 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4863 00:57:02.805724 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4864 00:57:02.812669 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4865 00:57:02.815488 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4866 00:57:02.819378 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4867 00:57:02.822705 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4868 00:57:02.828659 iDelay=213, Bit 14, Center 48 (-107 ~ 204) 312
4869 00:57:02.832109 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4870 00:57:02.832194 ==
4871 00:57:02.835235 Dram Type= 6, Freq= 0, CH_1, rank 1
4872 00:57:02.838546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4873 00:57:02.838652 ==
4874 00:57:02.841791 DQS Delay:
4875 00:57:02.841891 DQS0 = 0, DQS1 = 0
4876 00:57:02.845531 DQM Delay:
4877 00:57:02.845605 DQM0 = 45, DQM1 = 37
4878 00:57:02.845705 DQ Delay:
4879 00:57:02.849027 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4880 00:57:02.852170 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4881 00:57:02.855445 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4882 00:57:02.858376 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4883 00:57:02.858486
4884 00:57:02.858578
4885 00:57:02.868125 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4886 00:57:02.871745 CH1 RK1: MR19=808, MR18=2D22
4887 00:57:02.878267 CH1_RK1: MR19=0x808, MR18=0x2D22, DQSOSC=401, MR23=63, INC=163, DEC=108
4888 00:57:02.878345 [RxdqsGatingPostProcess] freq 600
4889 00:57:02.884988 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4890 00:57:02.888485 Pre-setting of DQS Precalculation
4891 00:57:02.891897 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4892 00:57:02.901270 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4893 00:57:02.907919 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4894 00:57:02.908000
4895 00:57:02.908083
4896 00:57:02.911309 [Calibration Summary] 1200 Mbps
4897 00:57:02.911412 CH 0, Rank 0
4898 00:57:02.914967 SW Impedance : PASS
4899 00:57:02.915068 DUTY Scan : NO K
4900 00:57:02.917934 ZQ Calibration : PASS
4901 00:57:02.921550 Jitter Meter : NO K
4902 00:57:02.921656 CBT Training : PASS
4903 00:57:02.925015 Write leveling : PASS
4904 00:57:02.927692 RX DQS gating : PASS
4905 00:57:02.927765 RX DQ/DQS(RDDQC) : PASS
4906 00:57:02.931307 TX DQ/DQS : PASS
4907 00:57:02.934516 RX DATLAT : PASS
4908 00:57:02.934615 RX DQ/DQS(Engine): PASS
4909 00:57:02.938105 TX OE : NO K
4910 00:57:02.938203 All Pass.
4911 00:57:02.938302
4912 00:57:02.941069 CH 0, Rank 1
4913 00:57:02.941164 SW Impedance : PASS
4914 00:57:02.944228 DUTY Scan : NO K
4915 00:57:02.947816 ZQ Calibration : PASS
4916 00:57:02.947916 Jitter Meter : NO K
4917 00:57:02.951064 CBT Training : PASS
4918 00:57:02.954326 Write leveling : PASS
4919 00:57:02.954426 RX DQS gating : PASS
4920 00:57:02.957546 RX DQ/DQS(RDDQC) : PASS
4921 00:57:02.960889 TX DQ/DQS : PASS
4922 00:57:02.960971 RX DATLAT : PASS
4923 00:57:02.964439 RX DQ/DQS(Engine): PASS
4924 00:57:02.967427 TX OE : NO K
4925 00:57:02.967528 All Pass.
4926 00:57:02.967630
4927 00:57:02.967715 CH 1, Rank 0
4928 00:57:02.971019 SW Impedance : PASS
4929 00:57:02.974503 DUTY Scan : NO K
4930 00:57:02.974577 ZQ Calibration : PASS
4931 00:57:02.977289 Jitter Meter : NO K
4932 00:57:02.981107 CBT Training : PASS
4933 00:57:02.981191 Write leveling : PASS
4934 00:57:02.984244 RX DQS gating : PASS
4935 00:57:02.984358 RX DQ/DQS(RDDQC) : PASS
4936 00:57:02.987364 TX DQ/DQS : PASS
4937 00:57:02.990706 RX DATLAT : PASS
4938 00:57:02.990786 RX DQ/DQS(Engine): PASS
4939 00:57:02.993896 TX OE : NO K
4940 00:57:02.993998 All Pass.
4941 00:57:02.994093
4942 00:57:02.997357 CH 1, Rank 1
4943 00:57:02.997457 SW Impedance : PASS
4944 00:57:03.000232 DUTY Scan : NO K
4945 00:57:03.003338 ZQ Calibration : PASS
4946 00:57:03.003440 Jitter Meter : NO K
4947 00:57:03.007045 CBT Training : PASS
4948 00:57:03.010290 Write leveling : PASS
4949 00:57:03.010391 RX DQS gating : PASS
4950 00:57:03.013672 RX DQ/DQS(RDDQC) : PASS
4951 00:57:03.016856 TX DQ/DQS : PASS
4952 00:57:03.016935 RX DATLAT : PASS
4953 00:57:03.019867 RX DQ/DQS(Engine): PASS
4954 00:57:03.023550 TX OE : NO K
4955 00:57:03.023653 All Pass.
4956 00:57:03.023731
4957 00:57:03.026484 DramC Write-DBI off
4958 00:57:03.026584 PER_BANK_REFRESH: Hybrid Mode
4959 00:57:03.030164 TX_TRACKING: ON
4960 00:57:03.036551 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4961 00:57:03.043177 [FAST_K] Save calibration result to emmc
4962 00:57:03.046692 dramc_set_vcore_voltage set vcore to 662500
4963 00:57:03.046796 Read voltage for 933, 3
4964 00:57:03.049894 Vio18 = 0
4965 00:57:03.049996 Vcore = 662500
4966 00:57:03.050087 Vdram = 0
4967 00:57:03.054044 Vddq = 0
4968 00:57:03.054146 Vmddr = 0
4969 00:57:03.056232 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4970 00:57:03.062654 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4971 00:57:03.066319 MEM_TYPE=3, freq_sel=17
4972 00:57:03.070055 sv_algorithm_assistance_LP4_1600
4973 00:57:03.072656 ============ PULL DRAM RESETB DOWN ============
4974 00:57:03.076064 ========== PULL DRAM RESETB DOWN end =========
4975 00:57:03.082899 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 00:57:03.086109 ===================================
4977 00:57:03.086215 LPDDR4 DRAM CONFIGURATION
4978 00:57:03.088882 ===================================
4979 00:57:03.092428 EX_ROW_EN[0] = 0x0
4980 00:57:03.095860 EX_ROW_EN[1] = 0x0
4981 00:57:03.095968 LP4Y_EN = 0x0
4982 00:57:03.098807 WORK_FSP = 0x0
4983 00:57:03.098882 WL = 0x3
4984 00:57:03.102591 RL = 0x3
4985 00:57:03.102692 BL = 0x2
4986 00:57:03.105396 RPST = 0x0
4987 00:57:03.105499 RD_PRE = 0x0
4988 00:57:03.108828 WR_PRE = 0x1
4989 00:57:03.108906 WR_PST = 0x0
4990 00:57:03.111944 DBI_WR = 0x0
4991 00:57:03.112021 DBI_RD = 0x0
4992 00:57:03.115464 OTF = 0x1
4993 00:57:03.118994 ===================================
4994 00:57:03.121964 ===================================
4995 00:57:03.122039 ANA top config
4996 00:57:03.125248 ===================================
4997 00:57:03.128580 DLL_ASYNC_EN = 0
4998 00:57:03.132196 ALL_SLAVE_EN = 1
4999 00:57:03.135013 NEW_RANK_MODE = 1
5000 00:57:03.135112 DLL_IDLE_MODE = 1
5001 00:57:03.138301 LP45_APHY_COMB_EN = 1
5002 00:57:03.141828 TX_ODT_DIS = 1
5003 00:57:03.145337 NEW_8X_MODE = 1
5004 00:57:03.148381 ===================================
5005 00:57:03.151782 ===================================
5006 00:57:03.154973 data_rate = 1866
5007 00:57:03.158124 CKR = 1
5008 00:57:03.158200 DQ_P2S_RATIO = 8
5009 00:57:03.161861 ===================================
5010 00:57:03.164631 CA_P2S_RATIO = 8
5011 00:57:03.168253 DQ_CA_OPEN = 0
5012 00:57:03.171502 DQ_SEMI_OPEN = 0
5013 00:57:03.174639 CA_SEMI_OPEN = 0
5014 00:57:03.174736 CA_FULL_RATE = 0
5015 00:57:03.177918 DQ_CKDIV4_EN = 1
5016 00:57:03.181320 CA_CKDIV4_EN = 1
5017 00:57:03.184606 CA_PREDIV_EN = 0
5018 00:57:03.187865 PH8_DLY = 0
5019 00:57:03.191413 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5020 00:57:03.194403 DQ_AAMCK_DIV = 4
5021 00:57:03.194503 CA_AAMCK_DIV = 4
5022 00:57:03.197673 CA_ADMCK_DIV = 4
5023 00:57:03.201216 DQ_TRACK_CA_EN = 0
5024 00:57:03.204694 CA_PICK = 933
5025 00:57:03.207973 CA_MCKIO = 933
5026 00:57:03.211254 MCKIO_SEMI = 0
5027 00:57:03.214632 PLL_FREQ = 3732
5028 00:57:03.214735 DQ_UI_PI_RATIO = 32
5029 00:57:03.217946 CA_UI_PI_RATIO = 0
5030 00:57:03.221185 ===================================
5031 00:57:03.224237 ===================================
5032 00:57:03.227559 memory_type:LPDDR4
5033 00:57:03.230646 GP_NUM : 10
5034 00:57:03.230749 SRAM_EN : 1
5035 00:57:03.233893 MD32_EN : 0
5036 00:57:03.237230 ===================================
5037 00:57:03.240776 [ANA_INIT] >>>>>>>>>>>>>>
5038 00:57:03.240881 <<<<<< [CONFIGURE PHASE]: ANA_TX
5039 00:57:03.244137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5040 00:57:03.247041 ===================================
5041 00:57:03.250793 data_rate = 1866,PCW = 0X8f00
5042 00:57:03.253743 ===================================
5043 00:57:03.257298 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5044 00:57:03.264060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5045 00:57:03.270288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5046 00:57:03.273741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5047 00:57:03.277227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5048 00:57:03.280565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5049 00:57:03.283507 [ANA_INIT] flow start
5050 00:57:03.283607 [ANA_INIT] PLL >>>>>>>>
5051 00:57:03.286891 [ANA_INIT] PLL <<<<<<<<
5052 00:57:03.290168 [ANA_INIT] MIDPI >>>>>>>>
5053 00:57:03.293503 [ANA_INIT] MIDPI <<<<<<<<
5054 00:57:03.293608 [ANA_INIT] DLL >>>>>>>>
5055 00:57:03.296890 [ANA_INIT] flow end
5056 00:57:03.300149 ============ LP4 DIFF to SE enter ============
5057 00:57:03.303403 ============ LP4 DIFF to SE exit ============
5058 00:57:03.306331 [ANA_INIT] <<<<<<<<<<<<<
5059 00:57:03.309722 [Flow] Enable top DCM control >>>>>
5060 00:57:03.313030 [Flow] Enable top DCM control <<<<<
5061 00:57:03.316152 Enable DLL master slave shuffle
5062 00:57:03.322632 ==============================================================
5063 00:57:03.322737 Gating Mode config
5064 00:57:03.329460 ==============================================================
5065 00:57:03.329565 Config description:
5066 00:57:03.339567 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5067 00:57:03.346475 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5068 00:57:03.352863 SELPH_MODE 0: By rank 1: By Phase
5069 00:57:03.355855 ==============================================================
5070 00:57:03.359096 GAT_TRACK_EN = 1
5071 00:57:03.362511 RX_GATING_MODE = 2
5072 00:57:03.366193 RX_GATING_TRACK_MODE = 2
5073 00:57:03.369644 SELPH_MODE = 1
5074 00:57:03.372266 PICG_EARLY_EN = 1
5075 00:57:03.375828 VALID_LAT_VALUE = 1
5076 00:57:03.382423 ==============================================================
5077 00:57:03.385837 Enter into Gating configuration >>>>
5078 00:57:03.389105 Exit from Gating configuration <<<<
5079 00:57:03.392224 Enter into DVFS_PRE_config >>>>>
5080 00:57:03.402498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5081 00:57:03.405432 Exit from DVFS_PRE_config <<<<<
5082 00:57:03.408411 Enter into PICG configuration >>>>
5083 00:57:03.411700 Exit from PICG configuration <<<<
5084 00:57:03.415233 [RX_INPUT] configuration >>>>>
5085 00:57:03.418768 [RX_INPUT] configuration <<<<<
5086 00:57:03.422225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5087 00:57:03.428600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5088 00:57:03.435057 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5089 00:57:03.441414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5090 00:57:03.444916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5091 00:57:03.451384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5092 00:57:03.454820 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5093 00:57:03.461845 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5094 00:57:03.465299 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5095 00:57:03.468272 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5096 00:57:03.471490 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5097 00:57:03.477867 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5098 00:57:03.481734 ===================================
5099 00:57:03.481835 LPDDR4 DRAM CONFIGURATION
5100 00:57:03.484375 ===================================
5101 00:57:03.488091 EX_ROW_EN[0] = 0x0
5102 00:57:03.491509 EX_ROW_EN[1] = 0x0
5103 00:57:03.491611 LP4Y_EN = 0x0
5104 00:57:03.494250 WORK_FSP = 0x0
5105 00:57:03.494356 WL = 0x3
5106 00:57:03.497628 RL = 0x3
5107 00:57:03.497725 BL = 0x2
5108 00:57:03.501340 RPST = 0x0
5109 00:57:03.501418 RD_PRE = 0x0
5110 00:57:03.504504 WR_PRE = 0x1
5111 00:57:03.504576 WR_PST = 0x0
5112 00:57:03.507446 DBI_WR = 0x0
5113 00:57:03.507540 DBI_RD = 0x0
5114 00:57:03.510985 OTF = 0x1
5115 00:57:03.513935 ===================================
5116 00:57:03.517235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5117 00:57:03.520904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5118 00:57:03.527503 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5119 00:57:03.530676 ===================================
5120 00:57:03.534154 LPDDR4 DRAM CONFIGURATION
5121 00:57:03.537210 ===================================
5122 00:57:03.537313 EX_ROW_EN[0] = 0x10
5123 00:57:03.541060 EX_ROW_EN[1] = 0x0
5124 00:57:03.541161 LP4Y_EN = 0x0
5125 00:57:03.543922 WORK_FSP = 0x0
5126 00:57:03.544024 WL = 0x3
5127 00:57:03.547291 RL = 0x3
5128 00:57:03.547369 BL = 0x2
5129 00:57:03.550341 RPST = 0x0
5130 00:57:03.550443 RD_PRE = 0x0
5131 00:57:03.554128 WR_PRE = 0x1
5132 00:57:03.554203 WR_PST = 0x0
5133 00:57:03.557107 DBI_WR = 0x0
5134 00:57:03.557183 DBI_RD = 0x0
5135 00:57:03.560437 OTF = 0x1
5136 00:57:03.563623 ===================================
5137 00:57:03.570349 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5138 00:57:03.573945 nWR fixed to 30
5139 00:57:03.577204 [ModeRegInit_LP4] CH0 RK0
5140 00:57:03.577316 [ModeRegInit_LP4] CH0 RK1
5141 00:57:03.580235 [ModeRegInit_LP4] CH1 RK0
5142 00:57:03.584090 [ModeRegInit_LP4] CH1 RK1
5143 00:57:03.584203 match AC timing 9
5144 00:57:03.590042 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5145 00:57:03.593442 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5146 00:57:03.596878 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5147 00:57:03.603660 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5148 00:57:03.606897 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5149 00:57:03.606974 ==
5150 00:57:03.609882 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 00:57:03.613017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 00:57:03.613133 ==
5153 00:57:03.619873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5154 00:57:03.626739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5155 00:57:03.629502 [CA 0] Center 37 (7~68) winsize 62
5156 00:57:03.632997 [CA 1] Center 37 (7~68) winsize 62
5157 00:57:03.636755 [CA 2] Center 34 (4~65) winsize 62
5158 00:57:03.639592 [CA 3] Center 35 (5~65) winsize 61
5159 00:57:03.643249 [CA 4] Center 33 (3~64) winsize 62
5160 00:57:03.646228 [CA 5] Center 33 (3~63) winsize 61
5161 00:57:03.646342
5162 00:57:03.649435 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5163 00:57:03.649525
5164 00:57:03.652885 [CATrainingPosCal] consider 1 rank data
5165 00:57:03.655887 u2DelayCellTimex100 = 270/100 ps
5166 00:57:03.659203 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5167 00:57:03.662839 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5168 00:57:03.665802 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5169 00:57:03.669584 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5170 00:57:03.676218 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5171 00:57:03.679556 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5172 00:57:03.679662
5173 00:57:03.682336 CA PerBit enable=1, Macro0, CA PI delay=33
5174 00:57:03.682437
5175 00:57:03.685761 [CBTSetCACLKResult] CA Dly = 33
5176 00:57:03.685864 CS Dly: 7 (0~38)
5177 00:57:03.685958 ==
5178 00:57:03.689588 Dram Type= 6, Freq= 0, CH_0, rank 1
5179 00:57:03.695959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 00:57:03.696038 ==
5181 00:57:03.699257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5182 00:57:03.705760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5183 00:57:03.708744 [CA 0] Center 37 (7~68) winsize 62
5184 00:57:03.712278 [CA 1] Center 37 (7~68) winsize 62
5185 00:57:03.716291 [CA 2] Center 34 (4~65) winsize 62
5186 00:57:03.718949 [CA 3] Center 34 (4~65) winsize 62
5187 00:57:03.722174 [CA 4] Center 33 (3~64) winsize 62
5188 00:57:03.725582 [CA 5] Center 32 (2~63) winsize 62
5189 00:57:03.725689
5190 00:57:03.728566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5191 00:57:03.728643
5192 00:57:03.732280 [CATrainingPosCal] consider 2 rank data
5193 00:57:03.735595 u2DelayCellTimex100 = 270/100 ps
5194 00:57:03.739126 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5195 00:57:03.742148 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5196 00:57:03.748868 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5197 00:57:03.751839 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5198 00:57:03.755559 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5199 00:57:03.758974 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5200 00:57:03.759074
5201 00:57:03.762037 CA PerBit enable=1, Macro0, CA PI delay=33
5202 00:57:03.762136
5203 00:57:03.765516 [CBTSetCACLKResult] CA Dly = 33
5204 00:57:03.765615 CS Dly: 7 (0~39)
5205 00:57:03.768489
5206 00:57:03.771575 ----->DramcWriteLeveling(PI) begin...
5207 00:57:03.771679 ==
5208 00:57:03.775276 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 00:57:03.778151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 00:57:03.778253 ==
5211 00:57:03.781691 Write leveling (Byte 0): 36 => 36
5212 00:57:03.784898 Write leveling (Byte 1): 29 => 29
5213 00:57:03.788408 DramcWriteLeveling(PI) end<-----
5214 00:57:03.788491
5215 00:57:03.788557 ==
5216 00:57:03.791559 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 00:57:03.794755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 00:57:03.794839 ==
5219 00:57:03.798443 [Gating] SW mode calibration
5220 00:57:03.804909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5221 00:57:03.811266 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5222 00:57:03.814344 0 14 0 | B1->B0 | 2322 3131 | 1 0 | (0 0) (0 0)
5223 00:57:03.817930 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 00:57:03.824950 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5225 00:57:03.828041 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5226 00:57:03.830960 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5227 00:57:03.837679 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5228 00:57:03.841278 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5229 00:57:03.844108 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5230 00:57:03.851107 0 15 0 | B1->B0 | 3131 2525 | 0 0 | (1 0) (0 0)
5231 00:57:03.854288 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5232 00:57:03.857376 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5233 00:57:03.864475 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5234 00:57:03.867247 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5235 00:57:03.870840 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5236 00:57:03.877826 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5237 00:57:03.880652 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5238 00:57:03.883918 1 0 0 | B1->B0 | 3535 4343 | 0 0 | (1 1) (0 0)
5239 00:57:03.890511 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 00:57:03.894027 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 00:57:03.897211 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5242 00:57:03.903615 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5243 00:57:03.907021 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 00:57:03.910515 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 00:57:03.917071 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 00:57:03.920789 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5247 00:57:03.923717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 00:57:03.930483 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 00:57:03.934095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 00:57:03.937477 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 00:57:03.943071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 00:57:03.946461 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 00:57:03.950157 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 00:57:03.956742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 00:57:03.959819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 00:57:03.963507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 00:57:03.969901 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 00:57:03.973273 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 00:57:03.976253 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 00:57:03.983139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 00:57:03.986643 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5262 00:57:03.989369 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5263 00:57:03.992956 Total UI for P1: 0, mck2ui 16
5264 00:57:03.996282 best dqsien dly found for B0: ( 1, 2, 28)
5265 00:57:04.002694 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5266 00:57:04.002794 Total UI for P1: 0, mck2ui 16
5267 00:57:04.009379 best dqsien dly found for B1: ( 1, 3, 0)
5268 00:57:04.012929 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5269 00:57:04.016031 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5270 00:57:04.016134
5271 00:57:04.019655 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5272 00:57:04.022377 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5273 00:57:04.025942 [Gating] SW calibration Done
5274 00:57:04.026015 ==
5275 00:57:04.029253 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 00:57:04.032466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 00:57:04.032546 ==
5278 00:57:04.035792 RX Vref Scan: 0
5279 00:57:04.035866
5280 00:57:04.035928 RX Vref 0 -> 0, step: 1
5281 00:57:04.035988
5282 00:57:04.039416 RX Delay -80 -> 252, step: 8
5283 00:57:04.042143 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5284 00:57:04.049563 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5285 00:57:04.052207 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5286 00:57:04.055750 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5287 00:57:04.059258 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5288 00:57:04.062144 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5289 00:57:04.065603 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5290 00:57:04.072280 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5291 00:57:04.075598 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5292 00:57:04.078484 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5293 00:57:04.081890 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5294 00:57:04.085230 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5295 00:57:04.092000 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5296 00:57:04.095428 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5297 00:57:04.098300 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5298 00:57:04.101874 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5299 00:57:04.101975 ==
5300 00:57:04.105056 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 00:57:04.108459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 00:57:04.111547 ==
5303 00:57:04.111650 DQS Delay:
5304 00:57:04.111754 DQS0 = 0, DQS1 = 0
5305 00:57:04.115630 DQM Delay:
5306 00:57:04.115726 DQM0 = 98, DQM1 = 86
5307 00:57:04.118910 DQ Delay:
5308 00:57:04.119009 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5309 00:57:04.121709 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5310 00:57:04.125227 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5311 00:57:04.131879 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5312 00:57:04.131977
5313 00:57:04.132070
5314 00:57:04.132138 ==
5315 00:57:04.134837 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 00:57:04.138024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 00:57:04.138124 ==
5318 00:57:04.138216
5319 00:57:04.138305
5320 00:57:04.141624 TX Vref Scan disable
5321 00:57:04.141720 == TX Byte 0 ==
5322 00:57:04.148037 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5323 00:57:04.151176 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5324 00:57:04.151277 == TX Byte 1 ==
5325 00:57:04.157577 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5326 00:57:04.161242 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5327 00:57:04.161345 ==
5328 00:57:04.164706 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 00:57:04.167794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 00:57:04.167866 ==
5331 00:57:04.167933
5332 00:57:04.171352
5333 00:57:04.171449 TX Vref Scan disable
5334 00:57:04.174218 == TX Byte 0 ==
5335 00:57:04.177561 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5336 00:57:04.184110 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5337 00:57:04.184188 == TX Byte 1 ==
5338 00:57:04.187560 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5339 00:57:04.193749 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5340 00:57:04.193853
5341 00:57:04.193945 [DATLAT]
5342 00:57:04.194036 Freq=933, CH0 RK0
5343 00:57:04.194126
5344 00:57:04.197182 DATLAT Default: 0xd
5345 00:57:04.200779 0, 0xFFFF, sum = 0
5346 00:57:04.200855 1, 0xFFFF, sum = 0
5347 00:57:04.203883 2, 0xFFFF, sum = 0
5348 00:57:04.203955 3, 0xFFFF, sum = 0
5349 00:57:04.207401 4, 0xFFFF, sum = 0
5350 00:57:04.207500 5, 0xFFFF, sum = 0
5351 00:57:04.210216 6, 0xFFFF, sum = 0
5352 00:57:04.210315 7, 0xFFFF, sum = 0
5353 00:57:04.213709 8, 0xFFFF, sum = 0
5354 00:57:04.213786 9, 0xFFFF, sum = 0
5355 00:57:04.217254 10, 0x0, sum = 1
5356 00:57:04.217333 11, 0x0, sum = 2
5357 00:57:04.220039 12, 0x0, sum = 3
5358 00:57:04.220112 13, 0x0, sum = 4
5359 00:57:04.223444 best_step = 11
5360 00:57:04.223538
5361 00:57:04.223624 ==
5362 00:57:04.227316 Dram Type= 6, Freq= 0, CH_0, rank 0
5363 00:57:04.230383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 00:57:04.230469 ==
5365 00:57:04.230529 RX Vref Scan: 1
5366 00:57:04.233599
5367 00:57:04.233667 RX Vref 0 -> 0, step: 1
5368 00:57:04.233756
5369 00:57:04.236909 RX Delay -61 -> 252, step: 4
5370 00:57:04.237005
5371 00:57:04.239744 Set Vref, RX VrefLevel [Byte0]: 59
5372 00:57:04.243261 [Byte1]: 49
5373 00:57:04.246887
5374 00:57:04.246986 Final RX Vref Byte 0 = 59 to rank0
5375 00:57:04.249979 Final RX Vref Byte 1 = 49 to rank0
5376 00:57:04.253469 Final RX Vref Byte 0 = 59 to rank1
5377 00:57:04.256600 Final RX Vref Byte 1 = 49 to rank1==
5378 00:57:04.260244 Dram Type= 6, Freq= 0, CH_0, rank 0
5379 00:57:04.266478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 00:57:04.266583 ==
5381 00:57:04.266678 DQS Delay:
5382 00:57:04.269963 DQS0 = 0, DQS1 = 0
5383 00:57:04.270036 DQM Delay:
5384 00:57:04.270102 DQM0 = 97, DQM1 = 86
5385 00:57:04.273031 DQ Delay:
5386 00:57:04.276260 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5387 00:57:04.280059 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5388 00:57:04.283074 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5389 00:57:04.286787 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =94
5390 00:57:04.286862
5391 00:57:04.286924
5392 00:57:04.293205 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 407 ps
5393 00:57:04.296216 CH0 RK0: MR19=505, MR18=2F16
5394 00:57:04.302671 CH0_RK0: MR19=0x505, MR18=0x2F16, DQSOSC=407, MR23=63, INC=65, DEC=43
5395 00:57:04.302767
5396 00:57:04.306292 ----->DramcWriteLeveling(PI) begin...
5397 00:57:04.306387 ==
5398 00:57:04.309351 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 00:57:04.312467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 00:57:04.312565 ==
5401 00:57:04.315701 Write leveling (Byte 0): 33 => 33
5402 00:57:04.319722 Write leveling (Byte 1): 33 => 33
5403 00:57:04.322596 DramcWriteLeveling(PI) end<-----
5404 00:57:04.322665
5405 00:57:04.322744 ==
5406 00:57:04.326099 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 00:57:04.332613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 00:57:04.332712 ==
5409 00:57:04.332805 [Gating] SW mode calibration
5410 00:57:04.342228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5411 00:57:04.345566 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5412 00:57:04.352000 0 14 0 | B1->B0 | 2827 3434 | 1 0 | (1 1) (0 0)
5413 00:57:04.355595 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 00:57:04.358682 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 00:57:04.361965 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 00:57:04.369086 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5417 00:57:04.371770 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 00:57:04.375268 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 00:57:04.381924 0 14 28 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
5420 00:57:04.385105 0 15 0 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
5421 00:57:04.388765 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5422 00:57:04.395069 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 00:57:04.398670 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 00:57:04.401612 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5425 00:57:04.408185 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 00:57:04.411547 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 00:57:04.414966 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
5428 00:57:04.422086 1 0 0 | B1->B0 | 3b3b 403f | 0 1 | (0 0) (0 0)
5429 00:57:04.424459 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 00:57:04.428242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 00:57:04.434507 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 00:57:04.438088 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 00:57:04.441467 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 00:57:04.447539 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 00:57:04.450824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5436 00:57:04.454741 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5437 00:57:04.461071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:57:04.464296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:57:04.467357 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:57:04.474463 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:57:04.477415 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:57:04.481155 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:57:04.487580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:57:04.490958 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 00:57:04.494775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 00:57:04.500641 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 00:57:04.503807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 00:57:04.507497 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 00:57:04.514036 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 00:57:04.517162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 00:57:04.520523 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5452 00:57:04.527032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5453 00:57:04.530120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5454 00:57:04.533720 Total UI for P1: 0, mck2ui 16
5455 00:57:04.537202 best dqsien dly found for B0: ( 1, 2, 30)
5456 00:57:04.540053 Total UI for P1: 0, mck2ui 16
5457 00:57:04.543434 best dqsien dly found for B1: ( 1, 3, 2)
5458 00:57:04.546614 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5459 00:57:04.550192 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5460 00:57:04.550292
5461 00:57:04.553823 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5462 00:57:04.556994 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5463 00:57:04.560062 [Gating] SW calibration Done
5464 00:57:04.560133 ==
5465 00:57:04.563149 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 00:57:04.569889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 00:57:04.569968 ==
5468 00:57:04.570038 RX Vref Scan: 0
5469 00:57:04.570102
5470 00:57:04.573117 RX Vref 0 -> 0, step: 1
5471 00:57:04.573187
5472 00:57:04.576441 RX Delay -80 -> 252, step: 8
5473 00:57:04.579796 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5474 00:57:04.582986 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5475 00:57:04.586549 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5476 00:57:04.589986 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5477 00:57:04.596008 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5478 00:57:04.599254 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5479 00:57:04.603404 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5480 00:57:04.606210 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5481 00:57:04.609351 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5482 00:57:04.612516 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5483 00:57:04.619576 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5484 00:57:04.622636 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5485 00:57:04.626103 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5486 00:57:04.629410 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5487 00:57:04.632579 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5488 00:57:04.639148 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5489 00:57:04.639235 ==
5490 00:57:04.642148 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 00:57:04.645859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 00:57:04.645944 ==
5493 00:57:04.646028 DQS Delay:
5494 00:57:04.648930 DQS0 = 0, DQS1 = 0
5495 00:57:04.649009 DQM Delay:
5496 00:57:04.651846 DQM0 = 97, DQM1 = 87
5497 00:57:04.651927 DQ Delay:
5498 00:57:04.655147 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5499 00:57:04.658819 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5500 00:57:04.662038 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5501 00:57:04.666128 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5502 00:57:04.666214
5503 00:57:04.666297
5504 00:57:04.666376 ==
5505 00:57:04.668470 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 00:57:04.675365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 00:57:04.675445 ==
5508 00:57:04.675547
5509 00:57:04.675652
5510 00:57:04.675738 TX Vref Scan disable
5511 00:57:04.678250 == TX Byte 0 ==
5512 00:57:04.681886 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5513 00:57:04.688512 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5514 00:57:04.688593 == TX Byte 1 ==
5515 00:57:04.691973 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5516 00:57:04.698496 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5517 00:57:04.698584 ==
5518 00:57:04.701596 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 00:57:04.704875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 00:57:04.704960 ==
5521 00:57:04.705044
5522 00:57:04.705122
5523 00:57:04.708192 TX Vref Scan disable
5524 00:57:04.708298 == TX Byte 0 ==
5525 00:57:04.714960 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5526 00:57:04.718096 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5527 00:57:04.718172 == TX Byte 1 ==
5528 00:57:04.725170 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5529 00:57:04.728111 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5530 00:57:04.728185
5531 00:57:04.728247 [DATLAT]
5532 00:57:04.731246 Freq=933, CH0 RK1
5533 00:57:04.731316
5534 00:57:04.731376 DATLAT Default: 0xb
5535 00:57:04.734651 0, 0xFFFF, sum = 0
5536 00:57:04.738080 1, 0xFFFF, sum = 0
5537 00:57:04.738156 2, 0xFFFF, sum = 0
5538 00:57:04.741188 3, 0xFFFF, sum = 0
5539 00:57:04.741309 4, 0xFFFF, sum = 0
5540 00:57:04.744554 5, 0xFFFF, sum = 0
5541 00:57:04.744662 6, 0xFFFF, sum = 0
5542 00:57:04.747754 7, 0xFFFF, sum = 0
5543 00:57:04.747832 8, 0xFFFF, sum = 0
5544 00:57:04.751380 9, 0xFFFF, sum = 0
5545 00:57:04.751484 10, 0x0, sum = 1
5546 00:57:04.754584 11, 0x0, sum = 2
5547 00:57:04.754677 12, 0x0, sum = 3
5548 00:57:04.757968 13, 0x0, sum = 4
5549 00:57:04.758043 best_step = 11
5550 00:57:04.758105
5551 00:57:04.758178 ==
5552 00:57:04.761042 Dram Type= 6, Freq= 0, CH_0, rank 1
5553 00:57:04.764372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 00:57:04.764448 ==
5555 00:57:04.767975 RX Vref Scan: 0
5556 00:57:04.768060
5557 00:57:04.770928 RX Vref 0 -> 0, step: 1
5558 00:57:04.770997
5559 00:57:04.771056 RX Delay -61 -> 252, step: 4
5560 00:57:04.778849 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5561 00:57:04.782506 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5562 00:57:04.786014 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5563 00:57:04.788825 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5564 00:57:04.791883 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5565 00:57:04.798742 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5566 00:57:04.802061 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5567 00:57:04.805371 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5568 00:57:04.808307 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5569 00:57:04.811986 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5570 00:57:04.818324 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5571 00:57:04.821653 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5572 00:57:04.825398 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5573 00:57:04.828370 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5574 00:57:04.831306 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5575 00:57:04.838334 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5576 00:57:04.838438 ==
5577 00:57:04.841379 Dram Type= 6, Freq= 0, CH_0, rank 1
5578 00:57:04.844727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 00:57:04.844809 ==
5580 00:57:04.844873 DQS Delay:
5581 00:57:04.848050 DQS0 = 0, DQS1 = 0
5582 00:57:04.848124 DQM Delay:
5583 00:57:04.851476 DQM0 = 95, DQM1 = 86
5584 00:57:04.851580 DQ Delay:
5585 00:57:04.854274 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5586 00:57:04.858373 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5587 00:57:04.861050 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5588 00:57:04.864849 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =92
5589 00:57:04.864949
5590 00:57:04.865073
5591 00:57:04.874370 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5592 00:57:04.874471 CH0 RK1: MR19=504, MR18=27F7
5593 00:57:04.881462 CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5594 00:57:04.884258 [RxdqsGatingPostProcess] freq 933
5595 00:57:04.890740 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5596 00:57:04.894395 best DQS0 dly(2T, 0.5T) = (0, 10)
5597 00:57:04.897380 best DQS1 dly(2T, 0.5T) = (0, 11)
5598 00:57:04.901052 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5599 00:57:04.903889 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5600 00:57:04.907303 best DQS0 dly(2T, 0.5T) = (0, 10)
5601 00:57:04.907402 best DQS1 dly(2T, 0.5T) = (0, 11)
5602 00:57:04.911170 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5603 00:57:04.913864 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5604 00:57:04.917084 Pre-setting of DQS Precalculation
5605 00:57:04.923905 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5606 00:57:04.924004 ==
5607 00:57:04.927423 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 00:57:04.930221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 00:57:04.930334 ==
5610 00:57:04.936910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5611 00:57:04.944061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5612 00:57:04.946798 [CA 0] Center 36 (6~67) winsize 62
5613 00:57:04.949941 [CA 1] Center 36 (6~67) winsize 62
5614 00:57:04.953459 [CA 2] Center 34 (4~65) winsize 62
5615 00:57:04.956660 [CA 3] Center 33 (3~64) winsize 62
5616 00:57:04.960053 [CA 4] Center 34 (4~64) winsize 61
5617 00:57:04.964011 [CA 5] Center 33 (3~64) winsize 62
5618 00:57:04.964084
5619 00:57:04.966647 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5620 00:57:04.966731
5621 00:57:04.970548 [CATrainingPosCal] consider 1 rank data
5622 00:57:04.973758 u2DelayCellTimex100 = 270/100 ps
5623 00:57:04.976307 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5624 00:57:04.979530 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5625 00:57:04.983261 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5626 00:57:04.986367 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5627 00:57:04.989802 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5628 00:57:04.993203 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5629 00:57:04.996467
5630 00:57:04.999569 CA PerBit enable=1, Macro0, CA PI delay=33
5631 00:57:04.999677
5632 00:57:05.003322 [CBTSetCACLKResult] CA Dly = 33
5633 00:57:05.003421 CS Dly: 6 (0~37)
5634 00:57:05.003510 ==
5635 00:57:05.005990 Dram Type= 6, Freq= 0, CH_1, rank 1
5636 00:57:05.009301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 00:57:05.012579 ==
5638 00:57:05.016426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5639 00:57:05.022977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5640 00:57:05.025665 [CA 0] Center 36 (6~67) winsize 62
5641 00:57:05.029162 [CA 1] Center 37 (7~67) winsize 61
5642 00:57:05.032967 [CA 2] Center 34 (4~65) winsize 62
5643 00:57:05.035749 [CA 3] Center 33 (3~64) winsize 62
5644 00:57:05.038812 [CA 4] Center 34 (3~65) winsize 63
5645 00:57:05.042637 [CA 5] Center 33 (3~64) winsize 62
5646 00:57:05.042745
5647 00:57:05.045323 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5648 00:57:05.045433
5649 00:57:05.048995 [CATrainingPosCal] consider 2 rank data
5650 00:57:05.052162 u2DelayCellTimex100 = 270/100 ps
5651 00:57:05.055662 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5652 00:57:05.059049 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5653 00:57:05.061784 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5654 00:57:05.068708 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5655 00:57:05.071741 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5656 00:57:05.075122 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5657 00:57:05.075233
5658 00:57:05.078570 CA PerBit enable=1, Macro0, CA PI delay=33
5659 00:57:05.078669
5660 00:57:05.081567 [CBTSetCACLKResult] CA Dly = 33
5661 00:57:05.081681 CS Dly: 7 (0~39)
5662 00:57:05.081773
5663 00:57:05.085057 ----->DramcWriteLeveling(PI) begin...
5664 00:57:05.088235 ==
5665 00:57:05.091317 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 00:57:05.094890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 00:57:05.094965 ==
5668 00:57:05.097928 Write leveling (Byte 0): 24 => 24
5669 00:57:05.101518 Write leveling (Byte 1): 29 => 29
5670 00:57:05.105542 DramcWriteLeveling(PI) end<-----
5671 00:57:05.105652
5672 00:57:05.105742 ==
5673 00:57:05.108127 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 00:57:05.111214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 00:57:05.111320 ==
5676 00:57:05.114736 [Gating] SW mode calibration
5677 00:57:05.121408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5678 00:57:05.127422 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5679 00:57:05.130866 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5680 00:57:05.134495 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5681 00:57:05.140779 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5682 00:57:05.144276 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5683 00:57:05.147811 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5684 00:57:05.154870 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5685 00:57:05.157694 0 14 24 | B1->B0 | 3333 3232 | 1 0 | (1 0) (0 0)
5686 00:57:05.160741 0 14 28 | B1->B0 | 2f2f 2929 | 0 1 | (0 1) (1 0)
5687 00:57:05.167408 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5688 00:57:05.170874 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5689 00:57:05.174177 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5690 00:57:05.180917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5691 00:57:05.183900 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5692 00:57:05.186723 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5693 00:57:05.193452 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5694 00:57:05.196727 0 15 28 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
5695 00:57:05.200129 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5696 00:57:05.207171 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5697 00:57:05.210345 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 00:57:05.213325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 00:57:05.219538 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5700 00:57:05.223193 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5701 00:57:05.226667 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5702 00:57:05.233097 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5703 00:57:05.236330 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 00:57:05.240099 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 00:57:05.246198 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 00:57:05.249266 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 00:57:05.252655 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 00:57:05.259161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 00:57:05.262827 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 00:57:05.265791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 00:57:05.272217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 00:57:05.275738 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 00:57:05.278885 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 00:57:05.285374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 00:57:05.289199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 00:57:05.292054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5717 00:57:05.298451 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5718 00:57:05.301985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5719 00:57:05.304957 Total UI for P1: 0, mck2ui 16
5720 00:57:05.308472 best dqsien dly found for B0: ( 1, 2, 22)
5721 00:57:05.311994 Total UI for P1: 0, mck2ui 16
5722 00:57:05.315426 best dqsien dly found for B1: ( 1, 2, 26)
5723 00:57:05.318464 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5724 00:57:05.321953 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5725 00:57:05.322053
5726 00:57:05.324912 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5727 00:57:05.331772 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5728 00:57:05.331872 [Gating] SW calibration Done
5729 00:57:05.331936 ==
5730 00:57:05.334874 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 00:57:05.341514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 00:57:05.341594 ==
5733 00:57:05.341659 RX Vref Scan: 0
5734 00:57:05.341745
5735 00:57:05.344785 RX Vref 0 -> 0, step: 1
5736 00:57:05.344871
5737 00:57:05.348222 RX Delay -80 -> 252, step: 8
5738 00:57:05.351146 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5739 00:57:05.354932 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5740 00:57:05.358217 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5741 00:57:05.361090 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5742 00:57:05.367709 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5743 00:57:05.370988 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5744 00:57:05.374681 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5745 00:57:05.377915 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5746 00:57:05.380947 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5747 00:57:05.387369 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5748 00:57:05.391064 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5749 00:57:05.394397 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5750 00:57:05.397324 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5751 00:57:05.400640 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5752 00:57:05.407420 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5753 00:57:05.410896 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5754 00:57:05.411008 ==
5755 00:57:05.414024 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 00:57:05.417310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 00:57:05.417385 ==
5758 00:57:05.420855 DQS Delay:
5759 00:57:05.420929 DQS0 = 0, DQS1 = 0
5760 00:57:05.420992 DQM Delay:
5761 00:57:05.423878 DQM0 = 101, DQM1 = 90
5762 00:57:05.423953 DQ Delay:
5763 00:57:05.427636 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5764 00:57:05.430596 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5765 00:57:05.433802 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5766 00:57:05.436933 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =103
5767 00:57:05.437007
5768 00:57:05.437070
5769 00:57:05.437135 ==
5770 00:57:05.440118 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 00:57:05.447246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 00:57:05.447356 ==
5773 00:57:05.447451
5774 00:57:05.447519
5775 00:57:05.450262 TX Vref Scan disable
5776 00:57:05.450333 == TX Byte 0 ==
5777 00:57:05.453852 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5778 00:57:05.460272 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5779 00:57:05.460351 == TX Byte 1 ==
5780 00:57:05.463385 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5781 00:57:05.470267 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5782 00:57:05.470362 ==
5783 00:57:05.473423 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 00:57:05.476829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 00:57:05.476907 ==
5786 00:57:05.476970
5787 00:57:05.477036
5788 00:57:05.479974 TX Vref Scan disable
5789 00:57:05.483340 == TX Byte 0 ==
5790 00:57:05.486842 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5791 00:57:05.489878 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5792 00:57:05.493325 == TX Byte 1 ==
5793 00:57:05.496008 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5794 00:57:05.499465 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5795 00:57:05.499540
5796 00:57:05.502545 [DATLAT]
5797 00:57:05.502617 Freq=933, CH1 RK0
5798 00:57:05.502680
5799 00:57:05.506530 DATLAT Default: 0xd
5800 00:57:05.506631 0, 0xFFFF, sum = 0
5801 00:57:05.509368 1, 0xFFFF, sum = 0
5802 00:57:05.509446 2, 0xFFFF, sum = 0
5803 00:57:05.512614 3, 0xFFFF, sum = 0
5804 00:57:05.512698 4, 0xFFFF, sum = 0
5805 00:57:05.516195 5, 0xFFFF, sum = 0
5806 00:57:05.516302 6, 0xFFFF, sum = 0
5807 00:57:05.519554 7, 0xFFFF, sum = 0
5808 00:57:05.519644 8, 0xFFFF, sum = 0
5809 00:57:05.522499 9, 0xFFFF, sum = 0
5810 00:57:05.522574 10, 0x0, sum = 1
5811 00:57:05.525887 11, 0x0, sum = 2
5812 00:57:05.525986 12, 0x0, sum = 3
5813 00:57:05.529221 13, 0x0, sum = 4
5814 00:57:05.529295 best_step = 11
5815 00:57:05.529356
5816 00:57:05.529415 ==
5817 00:57:05.532732 Dram Type= 6, Freq= 0, CH_1, rank 0
5818 00:57:05.539192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 00:57:05.539309 ==
5820 00:57:05.539402 RX Vref Scan: 1
5821 00:57:05.539491
5822 00:57:05.542114 RX Vref 0 -> 0, step: 1
5823 00:57:05.542212
5824 00:57:05.545355 RX Delay -61 -> 252, step: 4
5825 00:57:05.545470
5826 00:57:05.549285 Set Vref, RX VrefLevel [Byte0]: 48
5827 00:57:05.552330 [Byte1]: 61
5828 00:57:05.552413
5829 00:57:05.555412 Final RX Vref Byte 0 = 48 to rank0
5830 00:57:05.559377 Final RX Vref Byte 1 = 61 to rank0
5831 00:57:05.562118 Final RX Vref Byte 0 = 48 to rank1
5832 00:57:05.565532 Final RX Vref Byte 1 = 61 to rank1==
5833 00:57:05.568824 Dram Type= 6, Freq= 0, CH_1, rank 0
5834 00:57:05.571948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 00:57:05.572057 ==
5836 00:57:05.575824 DQS Delay:
5837 00:57:05.575932 DQS0 = 0, DQS1 = 0
5838 00:57:05.579119 DQM Delay:
5839 00:57:05.579208 DQM0 = 101, DQM1 = 95
5840 00:57:05.579304 DQ Delay:
5841 00:57:05.581934 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5842 00:57:05.585435 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5843 00:57:05.588719 DQ8 =86, DQ9 =88, DQ10 =94, DQ11 =88
5844 00:57:05.595897 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5845 00:57:05.595974
5846 00:57:05.596040
5847 00:57:05.601979 [DQSOSCAuto] RK0, (LSB)MR18= 0x1808, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5848 00:57:05.605340 CH1 RK0: MR19=505, MR18=1808
5849 00:57:05.611840 CH1_RK0: MR19=0x505, MR18=0x1808, DQSOSC=414, MR23=63, INC=63, DEC=42
5850 00:57:05.611918
5851 00:57:05.614861 ----->DramcWriteLeveling(PI) begin...
5852 00:57:05.614947 ==
5853 00:57:05.618778 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 00:57:05.621973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 00:57:05.622046 ==
5856 00:57:05.625261 Write leveling (Byte 0): 27 => 27
5857 00:57:05.628155 Write leveling (Byte 1): 30 => 30
5858 00:57:05.631475 DramcWriteLeveling(PI) end<-----
5859 00:57:05.631553
5860 00:57:05.631617 ==
5861 00:57:05.635023 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 00:57:05.638840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 00:57:05.638914 ==
5864 00:57:05.641775 [Gating] SW mode calibration
5865 00:57:05.648061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5866 00:57:05.654946 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5867 00:57:05.658430 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5868 00:57:05.664679 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 00:57:05.667837 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5870 00:57:05.671138 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5871 00:57:05.678219 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5872 00:57:05.680826 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5873 00:57:05.684515 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5874 00:57:05.691168 0 14 28 | B1->B0 | 2828 2f2f | 0 0 | (1 0) (0 1)
5875 00:57:05.693899 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 00:57:05.697332 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5877 00:57:05.703964 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 00:57:05.707358 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5879 00:57:05.710821 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5880 00:57:05.717232 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5881 00:57:05.720634 0 15 24 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
5882 00:57:05.723704 0 15 28 | B1->B0 | 4141 3030 | 0 0 | (0 0) (1 1)
5883 00:57:05.730602 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 00:57:05.733871 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 00:57:05.737156 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 00:57:05.743625 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5887 00:57:05.747091 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5888 00:57:05.750323 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 00:57:05.757083 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5890 00:57:05.760096 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5891 00:57:05.763261 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 00:57:05.770353 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 00:57:05.773640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 00:57:05.776640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 00:57:05.783068 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 00:57:05.786942 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 00:57:05.789779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 00:57:05.796664 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 00:57:05.799632 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 00:57:05.803686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 00:57:05.809919 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 00:57:05.812865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 00:57:05.816701 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 00:57:05.823001 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 00:57:05.826309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5906 00:57:05.829347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5907 00:57:05.836101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5908 00:57:05.836193 Total UI for P1: 0, mck2ui 16
5909 00:57:05.842724 best dqsien dly found for B0: ( 1, 2, 28)
5910 00:57:05.842803 Total UI for P1: 0, mck2ui 16
5911 00:57:05.845924 best dqsien dly found for B1: ( 1, 2, 26)
5912 00:57:05.852494 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5913 00:57:05.856020 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5914 00:57:05.856090
5915 00:57:05.859278 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5916 00:57:05.862652 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5917 00:57:05.865787 [Gating] SW calibration Done
5918 00:57:05.865859 ==
5919 00:57:05.869178 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 00:57:05.872687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 00:57:05.872760 ==
5922 00:57:05.875963 RX Vref Scan: 0
5923 00:57:05.876040
5924 00:57:05.876103 RX Vref 0 -> 0, step: 1
5925 00:57:05.876161
5926 00:57:05.879769 RX Delay -80 -> 252, step: 8
5927 00:57:05.883163 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5928 00:57:05.888809 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5929 00:57:05.892083 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5930 00:57:05.895469 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5931 00:57:05.898586 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5932 00:57:05.902169 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5933 00:57:05.905550 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5934 00:57:05.912427 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5935 00:57:05.915133 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5936 00:57:05.919297 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5937 00:57:05.922198 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5938 00:57:05.925438 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5939 00:57:05.932103 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5940 00:57:05.934911 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5941 00:57:05.938505 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5942 00:57:05.941592 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5943 00:57:05.941691 ==
5944 00:57:05.944969 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 00:57:05.948215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 00:57:05.951666 ==
5947 00:57:05.951759 DQS Delay:
5948 00:57:05.951839 DQS0 = 0, DQS1 = 0
5949 00:57:05.955192 DQM Delay:
5950 00:57:05.955291 DQM0 = 100, DQM1 = 91
5951 00:57:05.958126 DQ Delay:
5952 00:57:05.961703 DQ0 =107, DQ1 =91, DQ2 =91, DQ3 =99
5953 00:57:05.964658 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5954 00:57:05.968045 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5955 00:57:05.971701 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5956 00:57:05.971790
5957 00:57:05.971853
5958 00:57:05.971912 ==
5959 00:57:05.974647 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 00:57:05.978062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 00:57:05.978135 ==
5962 00:57:05.978195
5963 00:57:05.978251
5964 00:57:05.981540 TX Vref Scan disable
5965 00:57:05.981621 == TX Byte 0 ==
5966 00:57:05.987915 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5967 00:57:05.991059 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5968 00:57:05.994654 == TX Byte 1 ==
5969 00:57:05.997698 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5970 00:57:06.001410 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5971 00:57:06.001491 ==
5972 00:57:06.004628 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 00:57:06.007876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 00:57:06.011191 ==
5975 00:57:06.011271
5976 00:57:06.011335
5977 00:57:06.011394 TX Vref Scan disable
5978 00:57:06.014594 == TX Byte 0 ==
5979 00:57:06.018305 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5980 00:57:06.024624 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5981 00:57:06.024704 == TX Byte 1 ==
5982 00:57:06.027714 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5983 00:57:06.034397 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5984 00:57:06.034477
5985 00:57:06.034541 [DATLAT]
5986 00:57:06.034601 Freq=933, CH1 RK1
5987 00:57:06.034659
5988 00:57:06.037827 DATLAT Default: 0xb
5989 00:57:06.037907 0, 0xFFFF, sum = 0
5990 00:57:06.040978 1, 0xFFFF, sum = 0
5991 00:57:06.044371 2, 0xFFFF, sum = 0
5992 00:57:06.044452 3, 0xFFFF, sum = 0
5993 00:57:06.047607 4, 0xFFFF, sum = 0
5994 00:57:06.047754 5, 0xFFFF, sum = 0
5995 00:57:06.050819 6, 0xFFFF, sum = 0
5996 00:57:06.050917 7, 0xFFFF, sum = 0
5997 00:57:06.054274 8, 0xFFFF, sum = 0
5998 00:57:06.054389 9, 0xFFFF, sum = 0
5999 00:57:06.057409 10, 0x0, sum = 1
6000 00:57:06.057509 11, 0x0, sum = 2
6001 00:57:06.060553 12, 0x0, sum = 3
6002 00:57:06.060634 13, 0x0, sum = 4
6003 00:57:06.064451 best_step = 11
6004 00:57:06.064520
6005 00:57:06.064591 ==
6006 00:57:06.067196 Dram Type= 6, Freq= 0, CH_1, rank 1
6007 00:57:06.070450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6008 00:57:06.070521 ==
6009 00:57:06.070606 RX Vref Scan: 0
6010 00:57:06.070692
6011 00:57:06.073758 RX Vref 0 -> 0, step: 1
6012 00:57:06.073859
6013 00:57:06.077298 RX Delay -61 -> 252, step: 4
6014 00:57:06.083959 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6015 00:57:06.086754 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6016 00:57:06.090141 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6017 00:57:06.093248 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6018 00:57:06.097069 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6019 00:57:06.099904 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6020 00:57:06.107025 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6021 00:57:06.110447 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6022 00:57:06.113629 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6023 00:57:06.116898 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6024 00:57:06.120181 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6025 00:57:06.126607 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6026 00:57:06.129540 iDelay=207, Bit 12, Center 106 (19 ~ 194) 176
6027 00:57:06.132898 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6028 00:57:06.136926 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6029 00:57:06.143050 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6030 00:57:06.143122 ==
6031 00:57:06.145959 Dram Type= 6, Freq= 0, CH_1, rank 1
6032 00:57:06.149735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6033 00:57:06.149805 ==
6034 00:57:06.149866 DQS Delay:
6035 00:57:06.152907 DQS0 = 0, DQS1 = 0
6036 00:57:06.152975 DQM Delay:
6037 00:57:06.155913 DQM0 = 100, DQM1 = 94
6038 00:57:06.155987 DQ Delay:
6039 00:57:06.159562 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6040 00:57:06.162719 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
6041 00:57:06.165990 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =84
6042 00:57:06.169265 DQ12 =106, DQ13 =100, DQ14 =100, DQ15 =102
6043 00:57:06.169339
6044 00:57:06.169399
6045 00:57:06.179164 [DQSOSCAuto] RK1, (LSB)MR18= 0x903, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6046 00:57:06.179246 CH1 RK1: MR19=505, MR18=903
6047 00:57:06.186112 CH1_RK1: MR19=0x505, MR18=0x903, DQSOSC=419, MR23=63, INC=61, DEC=41
6048 00:57:06.188948 [RxdqsGatingPostProcess] freq 933
6049 00:57:06.195460 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6050 00:57:06.198982 best DQS0 dly(2T, 0.5T) = (0, 10)
6051 00:57:06.202418 best DQS1 dly(2T, 0.5T) = (0, 10)
6052 00:57:06.205775 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6053 00:57:06.208970 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6054 00:57:06.212101 best DQS0 dly(2T, 0.5T) = (0, 10)
6055 00:57:06.212179 best DQS1 dly(2T, 0.5T) = (0, 10)
6056 00:57:06.215323 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6057 00:57:06.218635 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6058 00:57:06.221863 Pre-setting of DQS Precalculation
6059 00:57:06.229309 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6060 00:57:06.235295 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6061 00:57:06.241880 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6062 00:57:06.241970
6063 00:57:06.242033
6064 00:57:06.245107 [Calibration Summary] 1866 Mbps
6065 00:57:06.248391 CH 0, Rank 0
6066 00:57:06.248467 SW Impedance : PASS
6067 00:57:06.251551 DUTY Scan : NO K
6068 00:57:06.254641 ZQ Calibration : PASS
6069 00:57:06.254709 Jitter Meter : NO K
6070 00:57:06.258450 CBT Training : PASS
6071 00:57:06.261299 Write leveling : PASS
6072 00:57:06.261369 RX DQS gating : PASS
6073 00:57:06.264711 RX DQ/DQS(RDDQC) : PASS
6074 00:57:06.267993 TX DQ/DQS : PASS
6075 00:57:06.268061 RX DATLAT : PASS
6076 00:57:06.271894 RX DQ/DQS(Engine): PASS
6077 00:57:06.271961 TX OE : NO K
6078 00:57:06.274739 All Pass.
6079 00:57:06.274804
6080 00:57:06.274863 CH 0, Rank 1
6081 00:57:06.278591 SW Impedance : PASS
6082 00:57:06.278658 DUTY Scan : NO K
6083 00:57:06.281247 ZQ Calibration : PASS
6084 00:57:06.285116 Jitter Meter : NO K
6085 00:57:06.285192 CBT Training : PASS
6086 00:57:06.288106 Write leveling : PASS
6087 00:57:06.291559 RX DQS gating : PASS
6088 00:57:06.291678 RX DQ/DQS(RDDQC) : PASS
6089 00:57:06.294750 TX DQ/DQS : PASS
6090 00:57:06.298080 RX DATLAT : PASS
6091 00:57:06.298163 RX DQ/DQS(Engine): PASS
6092 00:57:06.301201 TX OE : NO K
6093 00:57:06.301283 All Pass.
6094 00:57:06.301348
6095 00:57:06.304178 CH 1, Rank 0
6096 00:57:06.304259 SW Impedance : PASS
6097 00:57:06.307817 DUTY Scan : NO K
6098 00:57:06.310735 ZQ Calibration : PASS
6099 00:57:06.310817 Jitter Meter : NO K
6100 00:57:06.314201 CBT Training : PASS
6101 00:57:06.317157 Write leveling : PASS
6102 00:57:06.317250 RX DQS gating : PASS
6103 00:57:06.320988 RX DQ/DQS(RDDQC) : PASS
6104 00:57:06.323856 TX DQ/DQS : PASS
6105 00:57:06.323937 RX DATLAT : PASS
6106 00:57:06.327445 RX DQ/DQS(Engine): PASS
6107 00:57:06.330377 TX OE : NO K
6108 00:57:06.330458 All Pass.
6109 00:57:06.330522
6110 00:57:06.330582 CH 1, Rank 1
6111 00:57:06.333928 SW Impedance : PASS
6112 00:57:06.337078 DUTY Scan : NO K
6113 00:57:06.337160 ZQ Calibration : PASS
6114 00:57:06.340533 Jitter Meter : NO K
6115 00:57:06.343516 CBT Training : PASS
6116 00:57:06.343629 Write leveling : PASS
6117 00:57:06.347215 RX DQS gating : PASS
6118 00:57:06.350382 RX DQ/DQS(RDDQC) : PASS
6119 00:57:06.350463 TX DQ/DQS : PASS
6120 00:57:06.353455 RX DATLAT : PASS
6121 00:57:06.356979 RX DQ/DQS(Engine): PASS
6122 00:57:06.357061 TX OE : NO K
6123 00:57:06.360103 All Pass.
6124 00:57:06.360184
6125 00:57:06.360247 DramC Write-DBI off
6126 00:57:06.363599 PER_BANK_REFRESH: Hybrid Mode
6127 00:57:06.363730 TX_TRACKING: ON
6128 00:57:06.373355 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6129 00:57:06.376862 [FAST_K] Save calibration result to emmc
6130 00:57:06.379896 dramc_set_vcore_voltage set vcore to 650000
6131 00:57:06.383257 Read voltage for 400, 6
6132 00:57:06.383339 Vio18 = 0
6133 00:57:06.386643 Vcore = 650000
6134 00:57:06.386724 Vdram = 0
6135 00:57:06.386788 Vddq = 0
6136 00:57:06.386882 Vmddr = 0
6137 00:57:06.393394 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6138 00:57:06.399603 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6139 00:57:06.399728 MEM_TYPE=3, freq_sel=20
6140 00:57:06.402844 sv_algorithm_assistance_LP4_800
6141 00:57:06.406043 ============ PULL DRAM RESETB DOWN ============
6142 00:57:06.413053 ========== PULL DRAM RESETB DOWN end =========
6143 00:57:06.416231 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 00:57:06.420071 ===================================
6145 00:57:06.423235 LPDDR4 DRAM CONFIGURATION
6146 00:57:06.426195 ===================================
6147 00:57:06.426277 EX_ROW_EN[0] = 0x0
6148 00:57:06.429507 EX_ROW_EN[1] = 0x0
6149 00:57:06.432946 LP4Y_EN = 0x0
6150 00:57:06.433028 WORK_FSP = 0x0
6151 00:57:06.435668 WL = 0x2
6152 00:57:06.435790 RL = 0x2
6153 00:57:06.439054 BL = 0x2
6154 00:57:06.439173 RPST = 0x0
6155 00:57:06.442817 RD_PRE = 0x0
6156 00:57:06.442944 WR_PRE = 0x1
6157 00:57:06.445907 WR_PST = 0x0
6158 00:57:06.446014 DBI_WR = 0x0
6159 00:57:06.449040 DBI_RD = 0x0
6160 00:57:06.449142 OTF = 0x1
6161 00:57:06.452100 ===================================
6162 00:57:06.455426 ===================================
6163 00:57:06.459114 ANA top config
6164 00:57:06.462311 ===================================
6165 00:57:06.465316 DLL_ASYNC_EN = 0
6166 00:57:06.465398 ALL_SLAVE_EN = 1
6167 00:57:06.469040 NEW_RANK_MODE = 1
6168 00:57:06.472437 DLL_IDLE_MODE = 1
6169 00:57:06.475425 LP45_APHY_COMB_EN = 1
6170 00:57:06.475527 TX_ODT_DIS = 1
6171 00:57:06.478918 NEW_8X_MODE = 1
6172 00:57:06.482109 ===================================
6173 00:57:06.484958 ===================================
6174 00:57:06.488756 data_rate = 800
6175 00:57:06.491947 CKR = 1
6176 00:57:06.495591 DQ_P2S_RATIO = 4
6177 00:57:06.498693 ===================================
6178 00:57:06.502053 CA_P2S_RATIO = 4
6179 00:57:06.502200 DQ_CA_OPEN = 0
6180 00:57:06.505050 DQ_SEMI_OPEN = 1
6181 00:57:06.508539 CA_SEMI_OPEN = 1
6182 00:57:06.511532 CA_FULL_RATE = 0
6183 00:57:06.515019 DQ_CKDIV4_EN = 0
6184 00:57:06.518482 CA_CKDIV4_EN = 1
6185 00:57:06.518563 CA_PREDIV_EN = 0
6186 00:57:06.521928 PH8_DLY = 0
6187 00:57:06.524901 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6188 00:57:06.528129 DQ_AAMCK_DIV = 0
6189 00:57:06.531868 CA_AAMCK_DIV = 0
6190 00:57:06.535463 CA_ADMCK_DIV = 4
6191 00:57:06.535545 DQ_TRACK_CA_EN = 0
6192 00:57:06.538191 CA_PICK = 800
6193 00:57:06.541504 CA_MCKIO = 400
6194 00:57:06.544494 MCKIO_SEMI = 400
6195 00:57:06.547634 PLL_FREQ = 3016
6196 00:57:06.551624 DQ_UI_PI_RATIO = 32
6197 00:57:06.555007 CA_UI_PI_RATIO = 32
6198 00:57:06.557801 ===================================
6199 00:57:06.561147 ===================================
6200 00:57:06.564226 memory_type:LPDDR4
6201 00:57:06.564300 GP_NUM : 10
6202 00:57:06.567706 SRAM_EN : 1
6203 00:57:06.567825 MD32_EN : 0
6204 00:57:06.570958 ===================================
6205 00:57:06.574210 [ANA_INIT] >>>>>>>>>>>>>>
6206 00:57:06.577831 <<<<<< [CONFIGURE PHASE]: ANA_TX
6207 00:57:06.581026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6208 00:57:06.584989 ===================================
6209 00:57:06.587482 data_rate = 800,PCW = 0X7400
6210 00:57:06.591175 ===================================
6211 00:57:06.594702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6212 00:57:06.600911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6213 00:57:06.610520 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6214 00:57:06.614236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6215 00:57:06.617377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6216 00:57:06.620386 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6217 00:57:06.623793 [ANA_INIT] flow start
6218 00:57:06.627299 [ANA_INIT] PLL >>>>>>>>
6219 00:57:06.627403 [ANA_INIT] PLL <<<<<<<<
6220 00:57:06.630253 [ANA_INIT] MIDPI >>>>>>>>
6221 00:57:06.633818 [ANA_INIT] MIDPI <<<<<<<<
6222 00:57:06.637206 [ANA_INIT] DLL >>>>>>>>
6223 00:57:06.637303 [ANA_INIT] flow end
6224 00:57:06.640215 ============ LP4 DIFF to SE enter ============
6225 00:57:06.647035 ============ LP4 DIFF to SE exit ============
6226 00:57:06.647142 [ANA_INIT] <<<<<<<<<<<<<
6227 00:57:06.650307 [Flow] Enable top DCM control >>>>>
6228 00:57:06.653401 [Flow] Enable top DCM control <<<<<
6229 00:57:06.657111 Enable DLL master slave shuffle
6230 00:57:06.663292 ==============================================================
6231 00:57:06.663389 Gating Mode config
6232 00:57:06.670114 ==============================================================
6233 00:57:06.673839 Config description:
6234 00:57:06.683362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6235 00:57:06.689929 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6236 00:57:06.693342 SELPH_MODE 0: By rank 1: By Phase
6237 00:57:06.699564 ==============================================================
6238 00:57:06.703245 GAT_TRACK_EN = 0
6239 00:57:06.706478 RX_GATING_MODE = 2
6240 00:57:06.709572 RX_GATING_TRACK_MODE = 2
6241 00:57:06.709653 SELPH_MODE = 1
6242 00:57:06.713031 PICG_EARLY_EN = 1
6243 00:57:06.716074 VALID_LAT_VALUE = 1
6244 00:57:06.723132 ==============================================================
6245 00:57:06.725957 Enter into Gating configuration >>>>
6246 00:57:06.729846 Exit from Gating configuration <<<<
6247 00:57:06.732598 Enter into DVFS_PRE_config >>>>>
6248 00:57:06.742671 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6249 00:57:06.746183 Exit from DVFS_PRE_config <<<<<
6250 00:57:06.749120 Enter into PICG configuration >>>>
6251 00:57:06.752426 Exit from PICG configuration <<<<
6252 00:57:06.755492 [RX_INPUT] configuration >>>>>
6253 00:57:06.758955 [RX_INPUT] configuration <<<<<
6254 00:57:06.762377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6255 00:57:06.768861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6256 00:57:06.775385 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6257 00:57:06.781960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6258 00:57:06.788704 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6259 00:57:06.795125 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6260 00:57:06.798847 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6261 00:57:06.801822 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6262 00:57:06.804940 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6263 00:57:06.811943 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6264 00:57:06.815540 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6265 00:57:06.818442 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6266 00:57:06.821472 ===================================
6267 00:57:06.825181 LPDDR4 DRAM CONFIGURATION
6268 00:57:06.828027 ===================================
6269 00:57:06.828108 EX_ROW_EN[0] = 0x0
6270 00:57:06.831620 EX_ROW_EN[1] = 0x0
6271 00:57:06.831737 LP4Y_EN = 0x0
6272 00:57:06.835143 WORK_FSP = 0x0
6273 00:57:06.838404 WL = 0x2
6274 00:57:06.838484 RL = 0x2
6275 00:57:06.841322 BL = 0x2
6276 00:57:06.841402 RPST = 0x0
6277 00:57:06.844786 RD_PRE = 0x0
6278 00:57:06.844866 WR_PRE = 0x1
6279 00:57:06.848646 WR_PST = 0x0
6280 00:57:06.848727 DBI_WR = 0x0
6281 00:57:06.851283 DBI_RD = 0x0
6282 00:57:06.851362 OTF = 0x1
6283 00:57:06.854745 ===================================
6284 00:57:06.858034 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6285 00:57:06.864786 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6286 00:57:06.867975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6287 00:57:06.871422 ===================================
6288 00:57:06.874475 LPDDR4 DRAM CONFIGURATION
6289 00:57:06.878008 ===================================
6290 00:57:06.878089 EX_ROW_EN[0] = 0x10
6291 00:57:06.880806 EX_ROW_EN[1] = 0x0
6292 00:57:06.884524 LP4Y_EN = 0x0
6293 00:57:06.884605 WORK_FSP = 0x0
6294 00:57:06.888277 WL = 0x2
6295 00:57:06.888357 RL = 0x2
6296 00:57:06.890951 BL = 0x2
6297 00:57:06.891031 RPST = 0x0
6298 00:57:06.894451 RD_PRE = 0x0
6299 00:57:06.894532 WR_PRE = 0x1
6300 00:57:06.897767 WR_PST = 0x0
6301 00:57:06.897848 DBI_WR = 0x0
6302 00:57:06.900725 DBI_RD = 0x0
6303 00:57:06.900804 OTF = 0x1
6304 00:57:06.904170 ===================================
6305 00:57:06.911514 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6306 00:57:06.915279 nWR fixed to 30
6307 00:57:06.918603 [ModeRegInit_LP4] CH0 RK0
6308 00:57:06.918684 [ModeRegInit_LP4] CH0 RK1
6309 00:57:06.921682 [ModeRegInit_LP4] CH1 RK0
6310 00:57:06.924976 [ModeRegInit_LP4] CH1 RK1
6311 00:57:06.925056 match AC timing 19
6312 00:57:06.931722 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6313 00:57:06.934564 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6314 00:57:06.938218 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6315 00:57:06.944711 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6316 00:57:06.948216 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6317 00:57:06.948296 ==
6318 00:57:06.951149 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 00:57:06.954866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 00:57:06.954947 ==
6321 00:57:06.960997 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6322 00:57:06.967688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6323 00:57:06.970685 [CA 0] Center 36 (8~64) winsize 57
6324 00:57:06.974081 [CA 1] Center 36 (8~64) winsize 57
6325 00:57:06.977298 [CA 2] Center 36 (8~64) winsize 57
6326 00:57:06.980460 [CA 3] Center 36 (8~64) winsize 57
6327 00:57:06.984169 [CA 4] Center 36 (8~64) winsize 57
6328 00:57:06.988044 [CA 5] Center 36 (8~64) winsize 57
6329 00:57:06.988125
6330 00:57:06.990886 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6331 00:57:06.990966
6332 00:57:06.993808 [CATrainingPosCal] consider 1 rank data
6333 00:57:06.997567 u2DelayCellTimex100 = 270/100 ps
6334 00:57:07.001043 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 00:57:07.003944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 00:57:07.007210 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 00:57:07.010304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:57:07.013965 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 00:57:07.017150 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 00:57:07.017231
6341 00:57:07.023785 CA PerBit enable=1, Macro0, CA PI delay=36
6342 00:57:07.023865
6343 00:57:07.023929 [CBTSetCACLKResult] CA Dly = 36
6344 00:57:07.027235 CS Dly: 1 (0~32)
6345 00:57:07.027315 ==
6346 00:57:07.030165 Dram Type= 6, Freq= 0, CH_0, rank 1
6347 00:57:07.033520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 00:57:07.033602 ==
6349 00:57:07.040103 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6350 00:57:07.046863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6351 00:57:07.050223 [CA 0] Center 36 (8~64) winsize 57
6352 00:57:07.053083 [CA 1] Center 36 (8~64) winsize 57
6353 00:57:07.056558 [CA 2] Center 36 (8~64) winsize 57
6354 00:57:07.060001 [CA 3] Center 36 (8~64) winsize 57
6355 00:57:07.063218 [CA 4] Center 36 (8~64) winsize 57
6356 00:57:07.063298 [CA 5] Center 36 (8~64) winsize 57
6357 00:57:07.066710
6358 00:57:07.070014 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6359 00:57:07.070095
6360 00:57:07.073167 [CATrainingPosCal] consider 2 rank data
6361 00:57:07.076575 u2DelayCellTimex100 = 270/100 ps
6362 00:57:07.079904 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 00:57:07.082906 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 00:57:07.086045 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6365 00:57:07.089647 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6366 00:57:07.093133 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 00:57:07.096000 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 00:57:07.096080
6369 00:57:07.099265 CA PerBit enable=1, Macro0, CA PI delay=36
6370 00:57:07.099345
6371 00:57:07.103293 [CBTSetCACLKResult] CA Dly = 36
6372 00:57:07.105889 CS Dly: 1 (0~32)
6373 00:57:07.105968
6374 00:57:07.109350 ----->DramcWriteLeveling(PI) begin...
6375 00:57:07.109432 ==
6376 00:57:07.112959 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 00:57:07.116021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 00:57:07.116101 ==
6379 00:57:07.119563 Write leveling (Byte 0): 40 => 8
6380 00:57:07.122265 Write leveling (Byte 1): 32 => 0
6381 00:57:07.126474 DramcWriteLeveling(PI) end<-----
6382 00:57:07.126554
6383 00:57:07.126617 ==
6384 00:57:07.129004 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 00:57:07.132556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 00:57:07.132637 ==
6387 00:57:07.135942 [Gating] SW mode calibration
6388 00:57:07.142146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6389 00:57:07.148764 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6390 00:57:07.152187 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6391 00:57:07.158548 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6392 00:57:07.162116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6393 00:57:07.165166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6394 00:57:07.171962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6395 00:57:07.175889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6396 00:57:07.178039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6397 00:57:07.184911 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6398 00:57:07.188351 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6399 00:57:07.191594 Total UI for P1: 0, mck2ui 16
6400 00:57:07.194617 best dqsien dly found for B0: ( 0, 14, 24)
6401 00:57:07.197952 Total UI for P1: 0, mck2ui 16
6402 00:57:07.201398 best dqsien dly found for B1: ( 0, 14, 24)
6403 00:57:07.204958 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6404 00:57:07.208416 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6405 00:57:07.208496
6406 00:57:07.211805 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6407 00:57:07.218547 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6408 00:57:07.218628 [Gating] SW calibration Done
6409 00:57:07.218718 ==
6410 00:57:07.221525 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 00:57:07.228143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 00:57:07.228223 ==
6413 00:57:07.228286 RX Vref Scan: 0
6414 00:57:07.228346
6415 00:57:07.231127 RX Vref 0 -> 0, step: 1
6416 00:57:07.231207
6417 00:57:07.234688 RX Delay -410 -> 252, step: 16
6418 00:57:07.237740 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6419 00:57:07.240943 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6420 00:57:07.248084 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6421 00:57:07.250591 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6422 00:57:07.254102 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6423 00:57:07.257302 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6424 00:57:07.263801 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6425 00:57:07.267497 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6426 00:57:07.270414 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6427 00:57:07.274257 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6428 00:57:07.280542 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6429 00:57:07.283993 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6430 00:57:07.287028 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6431 00:57:07.293878 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6432 00:57:07.296988 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6433 00:57:07.299931 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6434 00:57:07.300011 ==
6435 00:57:07.303472 Dram Type= 6, Freq= 0, CH_0, rank 0
6436 00:57:07.306745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6437 00:57:07.310061 ==
6438 00:57:07.310142 DQS Delay:
6439 00:57:07.310207 DQS0 = 43, DQS1 = 59
6440 00:57:07.313004 DQM Delay:
6441 00:57:07.313085 DQM0 = 9, DQM1 = 13
6442 00:57:07.316725 DQ Delay:
6443 00:57:07.316809 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6444 00:57:07.319803 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6445 00:57:07.323047 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6446 00:57:07.326409 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6447 00:57:07.326491
6448 00:57:07.326555
6449 00:57:07.329979 ==
6450 00:57:07.333052 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 00:57:07.336557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 00:57:07.336639 ==
6453 00:57:07.336704
6454 00:57:07.336764
6455 00:57:07.339855 TX Vref Scan disable
6456 00:57:07.339936 == TX Byte 0 ==
6457 00:57:07.342756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6458 00:57:07.349941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6459 00:57:07.350023 == TX Byte 1 ==
6460 00:57:07.353066 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6461 00:57:07.359379 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6462 00:57:07.359460 ==
6463 00:57:07.362777 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 00:57:07.366163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 00:57:07.366244 ==
6466 00:57:07.366309
6467 00:57:07.366367
6468 00:57:07.369416 TX Vref Scan disable
6469 00:57:07.369497 == TX Byte 0 ==
6470 00:57:07.376198 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6471 00:57:07.379402 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6472 00:57:07.379483 == TX Byte 1 ==
6473 00:57:07.385905 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6474 00:57:07.389085 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6475 00:57:07.389166
6476 00:57:07.389231 [DATLAT]
6477 00:57:07.392506 Freq=400, CH0 RK0
6478 00:57:07.392587
6479 00:57:07.392651 DATLAT Default: 0xf
6480 00:57:07.396231 0, 0xFFFF, sum = 0
6481 00:57:07.396314 1, 0xFFFF, sum = 0
6482 00:57:07.398973 2, 0xFFFF, sum = 0
6483 00:57:07.399055 3, 0xFFFF, sum = 0
6484 00:57:07.402471 4, 0xFFFF, sum = 0
6485 00:57:07.402554 5, 0xFFFF, sum = 0
6486 00:57:07.405696 6, 0xFFFF, sum = 0
6487 00:57:07.405779 7, 0xFFFF, sum = 0
6488 00:57:07.408676 8, 0xFFFF, sum = 0
6489 00:57:07.408759 9, 0xFFFF, sum = 0
6490 00:57:07.411969 10, 0xFFFF, sum = 0
6491 00:57:07.415559 11, 0xFFFF, sum = 0
6492 00:57:07.415642 12, 0xFFFF, sum = 0
6493 00:57:07.418492 13, 0x0, sum = 1
6494 00:57:07.418575 14, 0x0, sum = 2
6495 00:57:07.422536 15, 0x0, sum = 3
6496 00:57:07.422619 16, 0x0, sum = 4
6497 00:57:07.422684 best_step = 14
6498 00:57:07.422744
6499 00:57:07.425184 ==
6500 00:57:07.428914 Dram Type= 6, Freq= 0, CH_0, rank 0
6501 00:57:07.432116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 00:57:07.432198 ==
6503 00:57:07.432263 RX Vref Scan: 1
6504 00:57:07.432324
6505 00:57:07.435091 RX Vref 0 -> 0, step: 1
6506 00:57:07.435172
6507 00:57:07.438974 RX Delay -359 -> 252, step: 8
6508 00:57:07.439060
6509 00:57:07.441772 Set Vref, RX VrefLevel [Byte0]: 59
6510 00:57:07.444905 [Byte1]: 49
6511 00:57:07.448773
6512 00:57:07.448854 Final RX Vref Byte 0 = 59 to rank0
6513 00:57:07.452289 Final RX Vref Byte 1 = 49 to rank0
6514 00:57:07.455536 Final RX Vref Byte 0 = 59 to rank1
6515 00:57:07.458985 Final RX Vref Byte 1 = 49 to rank1==
6516 00:57:07.462259 Dram Type= 6, Freq= 0, CH_0, rank 0
6517 00:57:07.468882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 00:57:07.468964 ==
6519 00:57:07.469028 DQS Delay:
6520 00:57:07.471937 DQS0 = 48, DQS1 = 60
6521 00:57:07.472019 DQM Delay:
6522 00:57:07.472083 DQM0 = 12, DQM1 = 12
6523 00:57:07.475204 DQ Delay:
6524 00:57:07.478715 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6525 00:57:07.482457 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6526 00:57:07.482560 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6527 00:57:07.489140 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6528 00:57:07.489220
6529 00:57:07.489283
6530 00:57:07.495515 [DQSOSCAuto] RK0, (LSB)MR18= 0xc587, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6531 00:57:07.498444 CH0 RK0: MR19=C0C, MR18=C587
6532 00:57:07.505482 CH0_RK0: MR19=0xC0C, MR18=0xC587, DQSOSC=385, MR23=63, INC=398, DEC=265
6533 00:57:07.505565 ==
6534 00:57:07.508647 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 00:57:07.511803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 00:57:07.511885 ==
6537 00:57:07.515370 [Gating] SW mode calibration
6538 00:57:07.521618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6539 00:57:07.528220 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6540 00:57:07.531195 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6541 00:57:07.534862 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6542 00:57:07.541255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6543 00:57:07.544671 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6544 00:57:07.547963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 00:57:07.554171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 00:57:07.557986 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6547 00:57:07.560809 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6548 00:57:07.567211 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6549 00:57:07.570997 Total UI for P1: 0, mck2ui 16
6550 00:57:07.574221 best dqsien dly found for B0: ( 0, 14, 24)
6551 00:57:07.578211 Total UI for P1: 0, mck2ui 16
6552 00:57:07.580890 best dqsien dly found for B1: ( 0, 14, 24)
6553 00:57:07.583635 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6554 00:57:07.587114 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6555 00:57:07.587196
6556 00:57:07.590387 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6557 00:57:07.593907 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6558 00:57:07.597274 [Gating] SW calibration Done
6559 00:57:07.597356 ==
6560 00:57:07.600323 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 00:57:07.603816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 00:57:07.606758 ==
6563 00:57:07.606840 RX Vref Scan: 0
6564 00:57:07.606904
6565 00:57:07.610001 RX Vref 0 -> 0, step: 1
6566 00:57:07.610082
6567 00:57:07.613803 RX Delay -410 -> 252, step: 16
6568 00:57:07.617036 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6569 00:57:07.619826 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6570 00:57:07.623557 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6571 00:57:07.629859 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6572 00:57:07.633399 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6573 00:57:07.636535 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6574 00:57:07.640572 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6575 00:57:07.646510 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6576 00:57:07.650027 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6577 00:57:07.653126 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6578 00:57:07.656552 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6579 00:57:07.663393 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6580 00:57:07.666168 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6581 00:57:07.669814 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6582 00:57:07.676637 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6583 00:57:07.679473 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6584 00:57:07.679546 ==
6585 00:57:07.683478 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 00:57:07.685997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 00:57:07.686092 ==
6588 00:57:07.689509 DQS Delay:
6589 00:57:07.689591 DQS0 = 43, DQS1 = 51
6590 00:57:07.689656 DQM Delay:
6591 00:57:07.692591 DQM0 = 11, DQM1 = 9
6592 00:57:07.692698 DQ Delay:
6593 00:57:07.695996 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6594 00:57:07.699430 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6595 00:57:07.702830 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6596 00:57:07.706076 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6597 00:57:07.706157
6598 00:57:07.706221
6599 00:57:07.706281 ==
6600 00:57:07.708962 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 00:57:07.713002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 00:57:07.716023 ==
6603 00:57:07.716105
6604 00:57:07.716170
6605 00:57:07.716229 TX Vref Scan disable
6606 00:57:07.719242 == TX Byte 0 ==
6607 00:57:07.722449 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6608 00:57:07.725455 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6609 00:57:07.728684 == TX Byte 1 ==
6610 00:57:07.732256 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6611 00:57:07.735527 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6612 00:57:07.735635 ==
6613 00:57:07.738872 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 00:57:07.742537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 00:57:07.745676 ==
6616 00:57:07.745758
6617 00:57:07.745822
6618 00:57:07.745882 TX Vref Scan disable
6619 00:57:07.748906 == TX Byte 0 ==
6620 00:57:07.751992 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6621 00:57:07.755729 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6622 00:57:07.758448 == TX Byte 1 ==
6623 00:57:07.761757 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6624 00:57:07.765612 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6625 00:57:07.765694
6626 00:57:07.768977 [DATLAT]
6627 00:57:07.769059 Freq=400, CH0 RK1
6628 00:57:07.769124
6629 00:57:07.771755 DATLAT Default: 0xe
6630 00:57:07.771836 0, 0xFFFF, sum = 0
6631 00:57:07.775168 1, 0xFFFF, sum = 0
6632 00:57:07.775250 2, 0xFFFF, sum = 0
6633 00:57:07.778674 3, 0xFFFF, sum = 0
6634 00:57:07.778758 4, 0xFFFF, sum = 0
6635 00:57:07.781871 5, 0xFFFF, sum = 0
6636 00:57:07.781955 6, 0xFFFF, sum = 0
6637 00:57:07.785315 7, 0xFFFF, sum = 0
6638 00:57:07.785398 8, 0xFFFF, sum = 0
6639 00:57:07.788624 9, 0xFFFF, sum = 0
6640 00:57:07.788706 10, 0xFFFF, sum = 0
6641 00:57:07.791604 11, 0xFFFF, sum = 0
6642 00:57:07.795235 12, 0xFFFF, sum = 0
6643 00:57:07.795344 13, 0x0, sum = 1
6644 00:57:07.798761 14, 0x0, sum = 2
6645 00:57:07.798843 15, 0x0, sum = 3
6646 00:57:07.798909 16, 0x0, sum = 4
6647 00:57:07.801706 best_step = 14
6648 00:57:07.801787
6649 00:57:07.801851 ==
6650 00:57:07.804974 Dram Type= 6, Freq= 0, CH_0, rank 1
6651 00:57:07.807950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 00:57:07.808032 ==
6653 00:57:07.811955 RX Vref Scan: 0
6654 00:57:07.812037
6655 00:57:07.814499 RX Vref 0 -> 0, step: 1
6656 00:57:07.814580
6657 00:57:07.814644 RX Delay -343 -> 252, step: 8
6658 00:57:07.823194 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6659 00:57:07.826313 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6660 00:57:07.829546 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6661 00:57:07.836402 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6662 00:57:07.839563 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6663 00:57:07.843080 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6664 00:57:07.845928 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6665 00:57:07.852600 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6666 00:57:07.856237 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6667 00:57:07.859825 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6668 00:57:07.862293 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6669 00:57:07.869086 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6670 00:57:07.872376 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6671 00:57:07.875904 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6672 00:57:07.882199 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6673 00:57:07.885523 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6674 00:57:07.885604 ==
6675 00:57:07.888767 Dram Type= 6, Freq= 0, CH_0, rank 1
6676 00:57:07.892513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 00:57:07.892595 ==
6678 00:57:07.895244 DQS Delay:
6679 00:57:07.895354 DQS0 = 44, DQS1 = 60
6680 00:57:07.895432 DQM Delay:
6681 00:57:07.898708 DQM0 = 7, DQM1 = 14
6682 00:57:07.898788 DQ Delay:
6683 00:57:07.901932 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6684 00:57:07.905640 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6685 00:57:07.908759 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6686 00:57:07.911510 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =20
6687 00:57:07.911591
6688 00:57:07.911655
6689 00:57:07.922070 [DQSOSCAuto] RK1, (LSB)MR18= 0xb943, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6690 00:57:07.922152 CH0 RK1: MR19=C0C, MR18=B943
6691 00:57:07.928382 CH0_RK1: MR19=0xC0C, MR18=0xB943, DQSOSC=386, MR23=63, INC=396, DEC=264
6692 00:57:07.931943 [RxdqsGatingPostProcess] freq 400
6693 00:57:07.938596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6694 00:57:07.941259 best DQS0 dly(2T, 0.5T) = (0, 10)
6695 00:57:07.944886 best DQS1 dly(2T, 0.5T) = (0, 10)
6696 00:57:07.948119 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6697 00:57:07.951548 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6698 00:57:07.954584 best DQS0 dly(2T, 0.5T) = (0, 10)
6699 00:57:07.957568 best DQS1 dly(2T, 0.5T) = (0, 10)
6700 00:57:07.960960 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6701 00:57:07.964455 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6702 00:57:07.964536 Pre-setting of DQS Precalculation
6703 00:57:07.971244 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6704 00:57:07.971326 ==
6705 00:57:07.974079 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 00:57:07.977619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 00:57:07.977701 ==
6708 00:57:07.984543 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6709 00:57:07.991069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6710 00:57:07.993925 [CA 0] Center 36 (8~64) winsize 57
6711 00:57:07.997930 [CA 1] Center 36 (8~64) winsize 57
6712 00:57:08.000522 [CA 2] Center 36 (8~64) winsize 57
6713 00:57:08.004308 [CA 3] Center 36 (8~64) winsize 57
6714 00:57:08.006995 [CA 4] Center 36 (8~64) winsize 57
6715 00:57:08.007076 [CA 5] Center 36 (8~64) winsize 57
6716 00:57:08.010824
6717 00:57:08.013847 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6718 00:57:08.013928
6719 00:57:08.017051 [CATrainingPosCal] consider 1 rank data
6720 00:57:08.020632 u2DelayCellTimex100 = 270/100 ps
6721 00:57:08.023733 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 00:57:08.026997 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 00:57:08.030364 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 00:57:08.033566 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:57:08.037131 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 00:57:08.040294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 00:57:08.040376
6728 00:57:08.043634 CA PerBit enable=1, Macro0, CA PI delay=36
6729 00:57:08.043773
6730 00:57:08.046841 [CBTSetCACLKResult] CA Dly = 36
6731 00:57:08.050387 CS Dly: 1 (0~32)
6732 00:57:08.050468 ==
6733 00:57:08.053457 Dram Type= 6, Freq= 0, CH_1, rank 1
6734 00:57:08.056841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 00:57:08.056923 ==
6736 00:57:08.063407 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6737 00:57:08.069952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6738 00:57:08.073027 [CA 0] Center 36 (8~64) winsize 57
6739 00:57:08.076744 [CA 1] Center 36 (8~64) winsize 57
6740 00:57:08.079728 [CA 2] Center 36 (8~64) winsize 57
6741 00:57:08.079809 [CA 3] Center 36 (8~64) winsize 57
6742 00:57:08.083025 [CA 4] Center 36 (8~64) winsize 57
6743 00:57:08.086563 [CA 5] Center 36 (8~64) winsize 57
6744 00:57:08.086644
6745 00:57:08.093017 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6746 00:57:08.093098
6747 00:57:08.096249 [CATrainingPosCal] consider 2 rank data
6748 00:57:08.099536 u2DelayCellTimex100 = 270/100 ps
6749 00:57:08.102522 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 00:57:08.105866 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 00:57:08.109094 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6752 00:57:08.113061 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6753 00:57:08.116176 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 00:57:08.119231 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6755 00:57:08.119312
6756 00:57:08.122839 CA PerBit enable=1, Macro0, CA PI delay=36
6757 00:57:08.122920
6758 00:57:08.125873 [CBTSetCACLKResult] CA Dly = 36
6759 00:57:08.129047 CS Dly: 1 (0~32)
6760 00:57:08.129127
6761 00:57:08.132366 ----->DramcWriteLeveling(PI) begin...
6762 00:57:08.132449 ==
6763 00:57:08.135810 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 00:57:08.139145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 00:57:08.139226 ==
6766 00:57:08.142351 Write leveling (Byte 0): 40 => 8
6767 00:57:08.146067 Write leveling (Byte 1): 32 => 0
6768 00:57:08.149425 DramcWriteLeveling(PI) end<-----
6769 00:57:08.149506
6770 00:57:08.149570 ==
6771 00:57:08.152396 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 00:57:08.155317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 00:57:08.155402 ==
6774 00:57:08.158971 [Gating] SW mode calibration
6775 00:57:08.165665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6776 00:57:08.171939 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6777 00:57:08.175298 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6778 00:57:08.182633 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6779 00:57:08.184930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6780 00:57:08.188600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6781 00:57:08.195223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6782 00:57:08.198123 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6783 00:57:08.201431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6784 00:57:08.208047 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6785 00:57:08.211659 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6786 00:57:08.214787 Total UI for P1: 0, mck2ui 16
6787 00:57:08.217887 best dqsien dly found for B0: ( 0, 14, 24)
6788 00:57:08.221923 Total UI for P1: 0, mck2ui 16
6789 00:57:08.224257 best dqsien dly found for B1: ( 0, 14, 24)
6790 00:57:08.227953 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6791 00:57:08.230921 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6792 00:57:08.231001
6793 00:57:08.234356 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6794 00:57:08.238054 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6795 00:57:08.240989 [Gating] SW calibration Done
6796 00:57:08.241070 ==
6797 00:57:08.244286 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 00:57:08.251396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 00:57:08.251477 ==
6800 00:57:08.251542 RX Vref Scan: 0
6801 00:57:08.251623
6802 00:57:08.254129 RX Vref 0 -> 0, step: 1
6803 00:57:08.254210
6804 00:57:08.257526 RX Delay -410 -> 252, step: 16
6805 00:57:08.261006 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6806 00:57:08.264303 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6807 00:57:08.267620 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6808 00:57:08.273910 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6809 00:57:08.277506 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6810 00:57:08.280921 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6811 00:57:08.287240 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6812 00:57:08.290309 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6813 00:57:08.294015 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6814 00:57:08.297140 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6815 00:57:08.304058 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6816 00:57:08.307365 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6817 00:57:08.310723 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6818 00:57:08.314554 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6819 00:57:08.320344 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6820 00:57:08.323923 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6821 00:57:08.324004 ==
6822 00:57:08.326862 Dram Type= 6, Freq= 0, CH_1, rank 0
6823 00:57:08.330340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6824 00:57:08.330421 ==
6825 00:57:08.333518 DQS Delay:
6826 00:57:08.333599 DQS0 = 43, DQS1 = 51
6827 00:57:08.337060 DQM Delay:
6828 00:57:08.337141 DQM0 = 12, DQM1 = 14
6829 00:57:08.337205 DQ Delay:
6830 00:57:08.340268 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6831 00:57:08.343643 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6832 00:57:08.347426 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6833 00:57:08.350087 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6834 00:57:08.350167
6835 00:57:08.350231
6836 00:57:08.350291 ==
6837 00:57:08.353541 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 00:57:08.360030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 00:57:08.360112 ==
6840 00:57:08.360177
6841 00:57:08.360236
6842 00:57:08.360293 TX Vref Scan disable
6843 00:57:08.363569 == TX Byte 0 ==
6844 00:57:08.366640 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6845 00:57:08.370225 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6846 00:57:08.373695 == TX Byte 1 ==
6847 00:57:08.376609 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6848 00:57:08.379915 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6849 00:57:08.380005 ==
6850 00:57:08.383374 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 00:57:08.389932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 00:57:08.390013 ==
6853 00:57:08.390077
6854 00:57:08.390136
6855 00:57:08.393175 TX Vref Scan disable
6856 00:57:08.393255 == TX Byte 0 ==
6857 00:57:08.396018 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6858 00:57:08.402625 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6859 00:57:08.402705 == TX Byte 1 ==
6860 00:57:08.406761 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6861 00:57:08.412626 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6862 00:57:08.412706
6863 00:57:08.412770 [DATLAT]
6864 00:57:08.412830 Freq=400, CH1 RK0
6865 00:57:08.412889
6866 00:57:08.415865 DATLAT Default: 0xf
6867 00:57:08.415945 0, 0xFFFF, sum = 0
6868 00:57:08.419090 1, 0xFFFF, sum = 0
6869 00:57:08.422648 2, 0xFFFF, sum = 0
6870 00:57:08.422730 3, 0xFFFF, sum = 0
6871 00:57:08.426021 4, 0xFFFF, sum = 0
6872 00:57:08.426102 5, 0xFFFF, sum = 0
6873 00:57:08.429337 6, 0xFFFF, sum = 0
6874 00:57:08.429418 7, 0xFFFF, sum = 0
6875 00:57:08.433163 8, 0xFFFF, sum = 0
6876 00:57:08.433244 9, 0xFFFF, sum = 0
6877 00:57:08.436034 10, 0xFFFF, sum = 0
6878 00:57:08.436116 11, 0xFFFF, sum = 0
6879 00:57:08.439547 12, 0xFFFF, sum = 0
6880 00:57:08.439628 13, 0x0, sum = 1
6881 00:57:08.442526 14, 0x0, sum = 2
6882 00:57:08.442607 15, 0x0, sum = 3
6883 00:57:08.445809 16, 0x0, sum = 4
6884 00:57:08.445891 best_step = 14
6885 00:57:08.445954
6886 00:57:08.446014 ==
6887 00:57:08.449543 Dram Type= 6, Freq= 0, CH_1, rank 0
6888 00:57:08.452744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 00:57:08.455636 ==
6890 00:57:08.455771 RX Vref Scan: 1
6891 00:57:08.455863
6892 00:57:08.459278 RX Vref 0 -> 0, step: 1
6893 00:57:08.459358
6894 00:57:08.462039 RX Delay -343 -> 252, step: 8
6895 00:57:08.462148
6896 00:57:08.465751 Set Vref, RX VrefLevel [Byte0]: 48
6897 00:57:08.469117 [Byte1]: 61
6898 00:57:08.469198
6899 00:57:08.472997 Final RX Vref Byte 0 = 48 to rank0
6900 00:57:08.475608 Final RX Vref Byte 1 = 61 to rank0
6901 00:57:08.479259 Final RX Vref Byte 0 = 48 to rank1
6902 00:57:08.482590 Final RX Vref Byte 1 = 61 to rank1==
6903 00:57:08.485705 Dram Type= 6, Freq= 0, CH_1, rank 0
6904 00:57:08.488968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 00:57:08.491978 ==
6906 00:57:08.492055 DQS Delay:
6907 00:57:08.492118 DQS0 = 44, DQS1 = 56
6908 00:57:08.495173 DQM Delay:
6909 00:57:08.495243 DQM0 = 7, DQM1 = 12
6910 00:57:08.498658 DQ Delay:
6911 00:57:08.498727 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6912 00:57:08.501724 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6913 00:57:08.505298 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6914 00:57:08.508680 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6915 00:57:08.508761
6916 00:57:08.508825
6917 00:57:08.518073 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6918 00:57:08.521604 CH1 RK0: MR19=C0C, MR18=9A71
6919 00:57:08.528435 CH1_RK0: MR19=0xC0C, MR18=0x9A71, DQSOSC=390, MR23=63, INC=388, DEC=258
6920 00:57:08.528517 ==
6921 00:57:08.531698 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 00:57:08.535309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 00:57:08.535390 ==
6924 00:57:08.538115 [Gating] SW mode calibration
6925 00:57:08.544597 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6926 00:57:08.548365 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6927 00:57:08.554696 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6928 00:57:08.558193 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6929 00:57:08.561215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6930 00:57:08.567815 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6931 00:57:08.571136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6932 00:57:08.574557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6933 00:57:08.581181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6934 00:57:08.584930 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6935 00:57:08.587933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6936 00:57:08.590616 Total UI for P1: 0, mck2ui 16
6937 00:57:08.594484 best dqsien dly found for B0: ( 0, 14, 24)
6938 00:57:08.597308 Total UI for P1: 0, mck2ui 16
6939 00:57:08.600600 best dqsien dly found for B1: ( 0, 14, 24)
6940 00:57:08.604210 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6941 00:57:08.610893 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6942 00:57:08.610974
6943 00:57:08.614314 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6944 00:57:08.617335 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6945 00:57:08.620324 [Gating] SW calibration Done
6946 00:57:08.620405 ==
6947 00:57:08.623701 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 00:57:08.627126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 00:57:08.627207 ==
6950 00:57:08.630593 RX Vref Scan: 0
6951 00:57:08.630673
6952 00:57:08.630737 RX Vref 0 -> 0, step: 1
6953 00:57:08.630796
6954 00:57:08.633858 RX Delay -410 -> 252, step: 16
6955 00:57:08.640543 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6956 00:57:08.643698 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6957 00:57:08.647315 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6958 00:57:08.650291 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6959 00:57:08.656722 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6960 00:57:08.660401 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6961 00:57:08.663203 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6962 00:57:08.666835 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6963 00:57:08.673005 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6964 00:57:08.676387 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6965 00:57:08.679989 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6966 00:57:08.683279 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6967 00:57:08.689685 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6968 00:57:08.693100 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6969 00:57:08.696018 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6970 00:57:08.702690 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6971 00:57:08.702823 ==
6972 00:57:08.705925 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 00:57:08.709684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 00:57:08.709767 ==
6975 00:57:08.709846 DQS Delay:
6976 00:57:08.712780 DQS0 = 51, DQS1 = 59
6977 00:57:08.712862 DQM Delay:
6978 00:57:08.716303 DQM0 = 19, DQM1 = 21
6979 00:57:08.716384 DQ Delay:
6980 00:57:08.719689 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6981 00:57:08.723270 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6982 00:57:08.726229 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6983 00:57:08.729379 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6984 00:57:08.729466
6985 00:57:08.729584
6986 00:57:08.729675 ==
6987 00:57:08.732356 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 00:57:08.736383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 00:57:08.736511 ==
6990 00:57:08.736606
6991 00:57:08.736697
6992 00:57:08.739297 TX Vref Scan disable
6993 00:57:08.742381 == TX Byte 0 ==
6994 00:57:08.746113 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6995 00:57:08.749015 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6996 00:57:08.752215 == TX Byte 1 ==
6997 00:57:08.755599 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6998 00:57:08.758962 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6999 00:57:08.759043 ==
7000 00:57:08.762214 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 00:57:08.765611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 00:57:08.765693 ==
7003 00:57:08.768966
7004 00:57:08.769047
7005 00:57:08.769112 TX Vref Scan disable
7006 00:57:08.772068 == TX Byte 0 ==
7007 00:57:08.776651 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7008 00:57:08.778485 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7009 00:57:08.782029 == TX Byte 1 ==
7010 00:57:08.785494 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
7011 00:57:08.788840 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
7012 00:57:08.788922
7013 00:57:08.788987 [DATLAT]
7014 00:57:08.792060 Freq=400, CH1 RK1
7015 00:57:08.792142
7016 00:57:08.795851 DATLAT Default: 0xe
7017 00:57:08.795933 0, 0xFFFF, sum = 0
7018 00:57:08.798475 1, 0xFFFF, sum = 0
7019 00:57:08.798558 2, 0xFFFF, sum = 0
7020 00:57:08.802673 3, 0xFFFF, sum = 0
7021 00:57:08.802755 4, 0xFFFF, sum = 0
7022 00:57:08.805077 5, 0xFFFF, sum = 0
7023 00:57:08.805160 6, 0xFFFF, sum = 0
7024 00:57:08.808641 7, 0xFFFF, sum = 0
7025 00:57:08.808728 8, 0xFFFF, sum = 0
7026 00:57:08.811842 9, 0xFFFF, sum = 0
7027 00:57:08.811918 10, 0xFFFF, sum = 0
7028 00:57:08.815282 11, 0xFFFF, sum = 0
7029 00:57:08.815353 12, 0xFFFF, sum = 0
7030 00:57:08.819030 13, 0x0, sum = 1
7031 00:57:08.819141 14, 0x0, sum = 2
7032 00:57:08.821891 15, 0x0, sum = 3
7033 00:57:08.821993 16, 0x0, sum = 4
7034 00:57:08.825129 best_step = 14
7035 00:57:08.825236
7036 00:57:08.825331 ==
7037 00:57:08.828513 Dram Type= 6, Freq= 0, CH_1, rank 1
7038 00:57:08.832050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7039 00:57:08.832137 ==
7040 00:57:08.834686 RX Vref Scan: 0
7041 00:57:08.834768
7042 00:57:08.834833 RX Vref 0 -> 0, step: 1
7043 00:57:08.834895
7044 00:57:08.838187 RX Delay -359 -> 252, step: 8
7045 00:57:08.846284 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7046 00:57:08.849913 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7047 00:57:08.852718 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7048 00:57:08.859250 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7049 00:57:08.862628 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7050 00:57:08.865664 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7051 00:57:08.869304 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7052 00:57:08.875905 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7053 00:57:08.878899 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7054 00:57:08.882618 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7055 00:57:08.886010 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7056 00:57:08.892528 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7057 00:57:08.896039 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
7058 00:57:08.898870 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7059 00:57:08.902006 iDelay=225, Bit 14, Center -36 (-287 ~ 216) 504
7060 00:57:08.908789 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7061 00:57:08.908870 ==
7062 00:57:08.912088 Dram Type= 6, Freq= 0, CH_1, rank 1
7063 00:57:08.915703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7064 00:57:08.915809 ==
7065 00:57:08.915903 DQS Delay:
7066 00:57:08.918566 DQS0 = 48, DQS1 = 60
7067 00:57:08.918663 DQM Delay:
7068 00:57:08.922232 DQM0 = 12, DQM1 = 15
7069 00:57:08.922331 DQ Delay:
7070 00:57:08.925554 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7071 00:57:08.928696 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7072 00:57:08.931689 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7073 00:57:08.934984 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
7074 00:57:08.935065
7075 00:57:08.935128
7076 00:57:08.945297 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7077 00:57:08.945404 CH1 RK1: MR19=C0C, MR18=6A59
7078 00:57:08.951410 CH1_RK1: MR19=0xC0C, MR18=0x6A59, DQSOSC=396, MR23=63, INC=376, DEC=251
7079 00:57:08.954960 [RxdqsGatingPostProcess] freq 400
7080 00:57:08.961928 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7081 00:57:08.964925 best DQS0 dly(2T, 0.5T) = (0, 10)
7082 00:57:08.968545 best DQS1 dly(2T, 0.5T) = (0, 10)
7083 00:57:08.971312 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7084 00:57:08.975160 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7085 00:57:08.978494 best DQS0 dly(2T, 0.5T) = (0, 10)
7086 00:57:08.978575 best DQS1 dly(2T, 0.5T) = (0, 10)
7087 00:57:08.981422 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7088 00:57:08.984873 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7089 00:57:08.988874 Pre-setting of DQS Precalculation
7090 00:57:08.995144 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7091 00:57:09.001163 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7092 00:57:09.008374 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7093 00:57:09.008455
7094 00:57:09.008519
7095 00:57:09.011406 [Calibration Summary] 800 Mbps
7096 00:57:09.014275 CH 0, Rank 0
7097 00:57:09.014356 SW Impedance : PASS
7098 00:57:09.017469 DUTY Scan : NO K
7099 00:57:09.020979 ZQ Calibration : PASS
7100 00:57:09.021059 Jitter Meter : NO K
7101 00:57:09.024414 CBT Training : PASS
7102 00:57:09.024494 Write leveling : PASS
7103 00:57:09.027921 RX DQS gating : PASS
7104 00:57:09.031286 RX DQ/DQS(RDDQC) : PASS
7105 00:57:09.031392 TX DQ/DQS : PASS
7106 00:57:09.034394 RX DATLAT : PASS
7107 00:57:09.037397 RX DQ/DQS(Engine): PASS
7108 00:57:09.037470 TX OE : NO K
7109 00:57:09.040715 All Pass.
7110 00:57:09.040795
7111 00:57:09.040858 CH 0, Rank 1
7112 00:57:09.044079 SW Impedance : PASS
7113 00:57:09.044187 DUTY Scan : NO K
7114 00:57:09.047337 ZQ Calibration : PASS
7115 00:57:09.050867 Jitter Meter : NO K
7116 00:57:09.050948 CBT Training : PASS
7117 00:57:09.053863 Write leveling : NO K
7118 00:57:09.057943 RX DQS gating : PASS
7119 00:57:09.058027 RX DQ/DQS(RDDQC) : PASS
7120 00:57:09.061096 TX DQ/DQS : PASS
7121 00:57:09.064156 RX DATLAT : PASS
7122 00:57:09.064230 RX DQ/DQS(Engine): PASS
7123 00:57:09.067509 TX OE : NO K
7124 00:57:09.067608 All Pass.
7125 00:57:09.067704
7126 00:57:09.070867 CH 1, Rank 0
7127 00:57:09.070962 SW Impedance : PASS
7128 00:57:09.073657 DUTY Scan : NO K
7129 00:57:09.077413 ZQ Calibration : PASS
7130 00:57:09.077496 Jitter Meter : NO K
7131 00:57:09.080864 CBT Training : PASS
7132 00:57:09.083905 Write leveling : PASS
7133 00:57:09.083986 RX DQS gating : PASS
7134 00:57:09.087366 RX DQ/DQS(RDDQC) : PASS
7135 00:57:09.087462 TX DQ/DQS : PASS
7136 00:57:09.090439 RX DATLAT : PASS
7137 00:57:09.094037 RX DQ/DQS(Engine): PASS
7138 00:57:09.094134 TX OE : NO K
7139 00:57:09.097004 All Pass.
7140 00:57:09.097108
7141 00:57:09.097187 CH 1, Rank 1
7142 00:57:09.101090 SW Impedance : PASS
7143 00:57:09.101172 DUTY Scan : NO K
7144 00:57:09.103852 ZQ Calibration : PASS
7145 00:57:09.106564 Jitter Meter : NO K
7146 00:57:09.106659 CBT Training : PASS
7147 00:57:09.110763 Write leveling : NO K
7148 00:57:09.113321 RX DQS gating : PASS
7149 00:57:09.113402 RX DQ/DQS(RDDQC) : PASS
7150 00:57:09.116969 TX DQ/DQS : PASS
7151 00:57:09.119921 RX DATLAT : PASS
7152 00:57:09.120003 RX DQ/DQS(Engine): PASS
7153 00:57:09.123043 TX OE : NO K
7154 00:57:09.123125 All Pass.
7155 00:57:09.123190
7156 00:57:09.126713 DramC Write-DBI off
7157 00:57:09.129692 PER_BANK_REFRESH: Hybrid Mode
7158 00:57:09.129773 TX_TRACKING: ON
7159 00:57:09.139852 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7160 00:57:09.142746 [FAST_K] Save calibration result to emmc
7161 00:57:09.146496 dramc_set_vcore_voltage set vcore to 725000
7162 00:57:09.149919 Read voltage for 1600, 0
7163 00:57:09.149994 Vio18 = 0
7164 00:57:09.152498 Vcore = 725000
7165 00:57:09.152572 Vdram = 0
7166 00:57:09.152655 Vddq = 0
7167 00:57:09.152715 Vmddr = 0
7168 00:57:09.159420 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7169 00:57:09.165999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7170 00:57:09.166081 MEM_TYPE=3, freq_sel=13
7171 00:57:09.169409 sv_algorithm_assistance_LP4_3733
7172 00:57:09.172708 ============ PULL DRAM RESETB DOWN ============
7173 00:57:09.179455 ========== PULL DRAM RESETB DOWN end =========
7174 00:57:09.182253 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 00:57:09.185860 ===================================
7176 00:57:09.189058 LPDDR4 DRAM CONFIGURATION
7177 00:57:09.192615 ===================================
7178 00:57:09.192696 EX_ROW_EN[0] = 0x0
7179 00:57:09.195878 EX_ROW_EN[1] = 0x0
7180 00:57:09.195959 LP4Y_EN = 0x0
7181 00:57:09.199217 WORK_FSP = 0x1
7182 00:57:09.202006 WL = 0x5
7183 00:57:09.202087 RL = 0x5
7184 00:57:09.205854 BL = 0x2
7185 00:57:09.205926 RPST = 0x0
7186 00:57:09.209114 RD_PRE = 0x0
7187 00:57:09.209195 WR_PRE = 0x1
7188 00:57:09.212364 WR_PST = 0x1
7189 00:57:09.212444 DBI_WR = 0x0
7190 00:57:09.215443 DBI_RD = 0x0
7191 00:57:09.215515 OTF = 0x1
7192 00:57:09.218413 ===================================
7193 00:57:09.222101 ===================================
7194 00:57:09.225098 ANA top config
7195 00:57:09.228604 ===================================
7196 00:57:09.228713 DLL_ASYNC_EN = 0
7197 00:57:09.231533 ALL_SLAVE_EN = 0
7198 00:57:09.234779 NEW_RANK_MODE = 1
7199 00:57:09.238169 DLL_IDLE_MODE = 1
7200 00:57:09.241404 LP45_APHY_COMB_EN = 1
7201 00:57:09.241485 TX_ODT_DIS = 0
7202 00:57:09.245047 NEW_8X_MODE = 1
7203 00:57:09.248365 ===================================
7204 00:57:09.251437 ===================================
7205 00:57:09.254904 data_rate = 3200
7206 00:57:09.257870 CKR = 1
7207 00:57:09.261621 DQ_P2S_RATIO = 8
7208 00:57:09.264533 ===================================
7209 00:57:09.267610 CA_P2S_RATIO = 8
7210 00:57:09.267717 DQ_CA_OPEN = 0
7211 00:57:09.270980 DQ_SEMI_OPEN = 0
7212 00:57:09.274485 CA_SEMI_OPEN = 0
7213 00:57:09.277593 CA_FULL_RATE = 0
7214 00:57:09.280998 DQ_CKDIV4_EN = 0
7215 00:57:09.284428 CA_CKDIV4_EN = 0
7216 00:57:09.284509 CA_PREDIV_EN = 0
7217 00:57:09.287393 PH8_DLY = 12
7218 00:57:09.290791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7219 00:57:09.295153 DQ_AAMCK_DIV = 4
7220 00:57:09.297680 CA_AAMCK_DIV = 4
7221 00:57:09.301608 CA_ADMCK_DIV = 4
7222 00:57:09.301688 DQ_TRACK_CA_EN = 0
7223 00:57:09.304598 CA_PICK = 1600
7224 00:57:09.307608 CA_MCKIO = 1600
7225 00:57:09.310837 MCKIO_SEMI = 0
7226 00:57:09.314108 PLL_FREQ = 3068
7227 00:57:09.317608 DQ_UI_PI_RATIO = 32
7228 00:57:09.320852 CA_UI_PI_RATIO = 0
7229 00:57:09.324136 ===================================
7230 00:57:09.327253 ===================================
7231 00:57:09.330386 memory_type:LPDDR4
7232 00:57:09.330467 GP_NUM : 10
7233 00:57:09.333942 SRAM_EN : 1
7234 00:57:09.334023 MD32_EN : 0
7235 00:57:09.337605 ===================================
7236 00:57:09.340631 [ANA_INIT] >>>>>>>>>>>>>>
7237 00:57:09.343922 <<<<<< [CONFIGURE PHASE]: ANA_TX
7238 00:57:09.346977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7239 00:57:09.350646 ===================================
7240 00:57:09.353648 data_rate = 3200,PCW = 0X7600
7241 00:57:09.357332 ===================================
7242 00:57:09.360043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7243 00:57:09.363783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7244 00:57:09.370451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7245 00:57:09.377136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7246 00:57:09.380195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7247 00:57:09.383408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7248 00:57:09.383511 [ANA_INIT] flow start
7249 00:57:09.387131 [ANA_INIT] PLL >>>>>>>>
7250 00:57:09.390150 [ANA_INIT] PLL <<<<<<<<
7251 00:57:09.390232 [ANA_INIT] MIDPI >>>>>>>>
7252 00:57:09.393228 [ANA_INIT] MIDPI <<<<<<<<
7253 00:57:09.396516 [ANA_INIT] DLL >>>>>>>>
7254 00:57:09.396597 [ANA_INIT] DLL <<<<<<<<
7255 00:57:09.399984 [ANA_INIT] flow end
7256 00:57:09.403371 ============ LP4 DIFF to SE enter ============
7257 00:57:09.409626 ============ LP4 DIFF to SE exit ============
7258 00:57:09.409708 [ANA_INIT] <<<<<<<<<<<<<
7259 00:57:09.412873 [Flow] Enable top DCM control >>>>>
7260 00:57:09.416166 [Flow] Enable top DCM control <<<<<
7261 00:57:09.419866 Enable DLL master slave shuffle
7262 00:57:09.426245 ==============================================================
7263 00:57:09.426328 Gating Mode config
7264 00:57:09.432989 ==============================================================
7265 00:57:09.436331 Config description:
7266 00:57:09.446074 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7267 00:57:09.452474 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7268 00:57:09.456370 SELPH_MODE 0: By rank 1: By Phase
7269 00:57:09.462336 ==============================================================
7270 00:57:09.465874 GAT_TRACK_EN = 1
7271 00:57:09.465985 RX_GATING_MODE = 2
7272 00:57:09.469221 RX_GATING_TRACK_MODE = 2
7273 00:57:09.472304 SELPH_MODE = 1
7274 00:57:09.475826 PICG_EARLY_EN = 1
7275 00:57:09.479304 VALID_LAT_VALUE = 1
7276 00:57:09.485752 ==============================================================
7277 00:57:09.489223 Enter into Gating configuration >>>>
7278 00:57:09.491860 Exit from Gating configuration <<<<
7279 00:57:09.495453 Enter into DVFS_PRE_config >>>>>
7280 00:57:09.505595 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7281 00:57:09.508733 Exit from DVFS_PRE_config <<<<<
7282 00:57:09.511821 Enter into PICG configuration >>>>
7283 00:57:09.515493 Exit from PICG configuration <<<<
7284 00:57:09.518511 [RX_INPUT] configuration >>>>>
7285 00:57:09.522209 [RX_INPUT] configuration <<<<<
7286 00:57:09.525031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7287 00:57:09.531572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7288 00:57:09.538561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7289 00:57:09.545297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7290 00:57:09.548350 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7291 00:57:09.555053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7292 00:57:09.561484 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7293 00:57:09.565200 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7294 00:57:09.568518 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7295 00:57:09.571647 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7296 00:57:09.574524 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7297 00:57:09.581865 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7298 00:57:09.584716 ===================================
7299 00:57:09.587713 LPDDR4 DRAM CONFIGURATION
7300 00:57:09.591043 ===================================
7301 00:57:09.591124 EX_ROW_EN[0] = 0x0
7302 00:57:09.594856 EX_ROW_EN[1] = 0x0
7303 00:57:09.594974 LP4Y_EN = 0x0
7304 00:57:09.598555 WORK_FSP = 0x1
7305 00:57:09.598636 WL = 0x5
7306 00:57:09.601042 RL = 0x5
7307 00:57:09.601123 BL = 0x2
7308 00:57:09.604461 RPST = 0x0
7309 00:57:09.604542 RD_PRE = 0x0
7310 00:57:09.607899 WR_PRE = 0x1
7311 00:57:09.611093 WR_PST = 0x1
7312 00:57:09.611202 DBI_WR = 0x0
7313 00:57:09.614302 DBI_RD = 0x0
7314 00:57:09.614426 OTF = 0x1
7315 00:57:09.617770 ===================================
7316 00:57:09.621082 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7317 00:57:09.627522 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7318 00:57:09.630926 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7319 00:57:09.634594 ===================================
7320 00:57:09.637696 LPDDR4 DRAM CONFIGURATION
7321 00:57:09.640546 ===================================
7322 00:57:09.640627 EX_ROW_EN[0] = 0x10
7323 00:57:09.643832 EX_ROW_EN[1] = 0x0
7324 00:57:09.643912 LP4Y_EN = 0x0
7325 00:57:09.647436 WORK_FSP = 0x1
7326 00:57:09.647517 WL = 0x5
7327 00:57:09.650513 RL = 0x5
7328 00:57:09.650593 BL = 0x2
7329 00:57:09.654040 RPST = 0x0
7330 00:57:09.654137 RD_PRE = 0x0
7331 00:57:09.657284 WR_PRE = 0x1
7332 00:57:09.660799 WR_PST = 0x1
7333 00:57:09.660880 DBI_WR = 0x0
7334 00:57:09.663979 DBI_RD = 0x0
7335 00:57:09.664101 OTF = 0x1
7336 00:57:09.667129 ===================================
7337 00:57:09.673438 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7338 00:57:09.673543 ==
7339 00:57:09.677019 Dram Type= 6, Freq= 0, CH_0, rank 0
7340 00:57:09.680163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7341 00:57:09.680245 ==
7342 00:57:09.683896 [Duty_Offset_Calibration]
7343 00:57:09.686844 B0:1 B1:-1 CA:0
7344 00:57:09.686926
7345 00:57:09.689777 [DutyScan_Calibration_Flow] k_type=0
7346 00:57:09.698543
7347 00:57:09.698624 ==CLK 0==
7348 00:57:09.701809 Final CLK duty delay cell = 0
7349 00:57:09.705396 [0] MAX Duty = 5125%(X100), DQS PI = 20
7350 00:57:09.708354 [0] MIN Duty = 4907%(X100), DQS PI = 6
7351 00:57:09.712096 [0] AVG Duty = 5016%(X100)
7352 00:57:09.712178
7353 00:57:09.714749 CH0 CLK Duty spec in!! Max-Min= 218%
7354 00:57:09.718151 [DutyScan_Calibration_Flow] ====Done====
7355 00:57:09.718234
7356 00:57:09.721614 [DutyScan_Calibration_Flow] k_type=1
7357 00:57:09.737927
7358 00:57:09.738011 ==DQS 0 ==
7359 00:57:09.741180 Final DQS duty delay cell = -4
7360 00:57:09.744382 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7361 00:57:09.747768 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7362 00:57:09.751004 [-4] AVG Duty = 4906%(X100)
7363 00:57:09.751086
7364 00:57:09.751152 ==DQS 1 ==
7365 00:57:09.754340 Final DQS duty delay cell = 0
7366 00:57:09.757279 [0] MAX Duty = 5156%(X100), DQS PI = 0
7367 00:57:09.761074 [0] MIN Duty = 5031%(X100), DQS PI = 16
7368 00:57:09.764282 [0] AVG Duty = 5093%(X100)
7369 00:57:09.764363
7370 00:57:09.767631 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7371 00:57:09.767720
7372 00:57:09.771007 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7373 00:57:09.773770 [DutyScan_Calibration_Flow] ====Done====
7374 00:57:09.773852
7375 00:57:09.777029 [DutyScan_Calibration_Flow] k_type=3
7376 00:57:09.795259
7377 00:57:09.795388 ==DQM 0 ==
7378 00:57:09.798864 Final DQM duty delay cell = 0
7379 00:57:09.801660 [0] MAX Duty = 5124%(X100), DQS PI = 22
7380 00:57:09.805147 [0] MIN Duty = 4907%(X100), DQS PI = 8
7381 00:57:09.808302 [0] AVG Duty = 5015%(X100)
7382 00:57:09.808383
7383 00:57:09.808447 ==DQM 1 ==
7384 00:57:09.811880 Final DQM duty delay cell = 0
7385 00:57:09.814748 [0] MAX Duty = 5031%(X100), DQS PI = 52
7386 00:57:09.818399 [0] MIN Duty = 4813%(X100), DQS PI = 20
7387 00:57:09.821604 [0] AVG Duty = 4922%(X100)
7388 00:57:09.821684
7389 00:57:09.825168 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7390 00:57:09.825318
7391 00:57:09.828167 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7392 00:57:09.831903 [DutyScan_Calibration_Flow] ====Done====
7393 00:57:09.832033
7394 00:57:09.834607 [DutyScan_Calibration_Flow] k_type=2
7395 00:57:09.852043
7396 00:57:09.852127 ==DQ 0 ==
7397 00:57:09.855152 Final DQ duty delay cell = -4
7398 00:57:09.858225 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7399 00:57:09.861516 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7400 00:57:09.864734 [-4] AVG Duty = 4953%(X100)
7401 00:57:09.864808
7402 00:57:09.864871 ==DQ 1 ==
7403 00:57:09.867883 Final DQ duty delay cell = 0
7404 00:57:09.871482 [0] MAX Duty = 5125%(X100), DQS PI = 4
7405 00:57:09.874507 [0] MIN Duty = 5000%(X100), DQS PI = 34
7406 00:57:09.878216 [0] AVG Duty = 5062%(X100)
7407 00:57:09.878289
7408 00:57:09.881328 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7409 00:57:09.881401
7410 00:57:09.884669 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7411 00:57:09.887533 [DutyScan_Calibration_Flow] ====Done====
7412 00:57:09.887621 ==
7413 00:57:09.891378 Dram Type= 6, Freq= 0, CH_1, rank 0
7414 00:57:09.894481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7415 00:57:09.894596 ==
7416 00:57:09.897739 [Duty_Offset_Calibration]
7417 00:57:09.897841 B0:-1 B1:1 CA:2
7418 00:57:09.897905
7419 00:57:09.901537 [DutyScan_Calibration_Flow] k_type=0
7420 00:57:09.912129
7421 00:57:09.912212 ==CLK 0==
7422 00:57:09.915786 Final CLK duty delay cell = 0
7423 00:57:09.918487 [0] MAX Duty = 5187%(X100), DQS PI = 24
7424 00:57:09.922006 [0] MIN Duty = 4969%(X100), DQS PI = 62
7425 00:57:09.925477 [0] AVG Duty = 5078%(X100)
7426 00:57:09.925560
7427 00:57:09.928266 CH1 CLK Duty spec in!! Max-Min= 218%
7428 00:57:09.932103 [DutyScan_Calibration_Flow] ====Done====
7429 00:57:09.932187
7430 00:57:09.935044 [DutyScan_Calibration_Flow] k_type=1
7431 00:57:09.951953
7432 00:57:09.952036 ==DQS 0 ==
7433 00:57:09.955056 Final DQS duty delay cell = 0
7434 00:57:09.958849 [0] MAX Duty = 5156%(X100), DQS PI = 20
7435 00:57:09.961596 [0] MIN Duty = 4907%(X100), DQS PI = 10
7436 00:57:09.964900 [0] AVG Duty = 5031%(X100)
7437 00:57:09.964982
7438 00:57:09.965048 ==DQS 1 ==
7439 00:57:09.968545 Final DQS duty delay cell = 0
7440 00:57:09.972122 [0] MAX Duty = 5093%(X100), DQS PI = 22
7441 00:57:09.975168 [0] MIN Duty = 4969%(X100), DQS PI = 56
7442 00:57:09.978371 [0] AVG Duty = 5031%(X100)
7443 00:57:09.978454
7444 00:57:09.981363 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7445 00:57:09.981447
7446 00:57:09.985541 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7447 00:57:09.988387 [DutyScan_Calibration_Flow] ====Done====
7448 00:57:09.988471
7449 00:57:09.991575 [DutyScan_Calibration_Flow] k_type=3
7450 00:57:10.009233
7451 00:57:10.009316 ==DQM 0 ==
7452 00:57:10.012576 Final DQM duty delay cell = 0
7453 00:57:10.015404 [0] MAX Duty = 5218%(X100), DQS PI = 18
7454 00:57:10.018781 [0] MIN Duty = 5031%(X100), DQS PI = 8
7455 00:57:10.022127 [0] AVG Duty = 5124%(X100)
7456 00:57:10.022209
7457 00:57:10.022292 ==DQM 1 ==
7458 00:57:10.025237 Final DQM duty delay cell = 0
7459 00:57:10.028961 [0] MAX Duty = 5125%(X100), DQS PI = 0
7460 00:57:10.032046 [0] MIN Duty = 4969%(X100), DQS PI = 32
7461 00:57:10.035010 [0] AVG Duty = 5047%(X100)
7462 00:57:10.035094
7463 00:57:10.038346 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7464 00:57:10.038431
7465 00:57:10.041665 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7466 00:57:10.045094 [DutyScan_Calibration_Flow] ====Done====
7467 00:57:10.045178
7468 00:57:10.048347 [DutyScan_Calibration_Flow] k_type=2
7469 00:57:10.065776
7470 00:57:10.065860 ==DQ 0 ==
7471 00:57:10.069374 Final DQ duty delay cell = 0
7472 00:57:10.072444 [0] MAX Duty = 5187%(X100), DQS PI = 32
7473 00:57:10.076140 [0] MIN Duty = 4906%(X100), DQS PI = 10
7474 00:57:10.076226 [0] AVG Duty = 5046%(X100)
7475 00:57:10.078937
7476 00:57:10.079018 ==DQ 1 ==
7477 00:57:10.082799 Final DQ duty delay cell = 0
7478 00:57:10.085995 [0] MAX Duty = 5156%(X100), DQS PI = 8
7479 00:57:10.088799 [0] MIN Duty = 4969%(X100), DQS PI = 56
7480 00:57:10.088881 [0] AVG Duty = 5062%(X100)
7481 00:57:10.088945
7482 00:57:10.092023 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7483 00:57:10.095573
7484 00:57:10.098833 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7485 00:57:10.102137 [DutyScan_Calibration_Flow] ====Done====
7486 00:57:10.105339 nWR fixed to 30
7487 00:57:10.105412 [ModeRegInit_LP4] CH0 RK0
7488 00:57:10.108932 [ModeRegInit_LP4] CH0 RK1
7489 00:57:10.111780 [ModeRegInit_LP4] CH1 RK0
7490 00:57:10.114963 [ModeRegInit_LP4] CH1 RK1
7491 00:57:10.115061 match AC timing 5
7492 00:57:10.121524 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7493 00:57:10.124939 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7494 00:57:10.128497 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7495 00:57:10.134647 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7496 00:57:10.138167 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7497 00:57:10.138248 [MiockJmeterHQA]
7498 00:57:10.138312
7499 00:57:10.142087 [DramcMiockJmeter] u1RxGatingPI = 0
7500 00:57:10.144723 0 : 4363, 4138
7501 00:57:10.144804 4 : 4252, 4027
7502 00:57:10.147895 8 : 4363, 4138
7503 00:57:10.148009 12 : 4252, 4027
7504 00:57:10.148074 16 : 4363, 4137
7505 00:57:10.151688 20 : 4253, 4027
7506 00:57:10.151784 24 : 4250, 4026
7507 00:57:10.154652 28 : 4252, 4027
7508 00:57:10.154733 32 : 4252, 4029
7509 00:57:10.158081 36 : 4250, 4026
7510 00:57:10.158163 40 : 4363, 4138
7511 00:57:10.161242 44 : 4360, 4138
7512 00:57:10.161323 48 : 4250, 4027
7513 00:57:10.161409 52 : 4252, 4030
7514 00:57:10.164510 56 : 4250, 4027
7515 00:57:10.164592 60 : 4250, 4027
7516 00:57:10.167839 64 : 4252, 4029
7517 00:57:10.167977 68 : 4361, 4137
7518 00:57:10.171256 72 : 4250, 4027
7519 00:57:10.171337 76 : 4250, 4027
7520 00:57:10.174165 80 : 4250, 4027
7521 00:57:10.174247 84 : 4252, 4029
7522 00:57:10.174311 88 : 4250, 4027
7523 00:57:10.177711 92 : 4360, 735
7524 00:57:10.177793 96 : 4252, 0
7525 00:57:10.180971 100 : 4363, 0
7526 00:57:10.181053 104 : 4253, 0
7527 00:57:10.181118 108 : 4250, 0
7528 00:57:10.184709 112 : 4250, 0
7529 00:57:10.184791 116 : 4250, 0
7530 00:57:10.187788 120 : 4250, 0
7531 00:57:10.187869 124 : 4250, 0
7532 00:57:10.187934 128 : 4252, 0
7533 00:57:10.191263 132 : 4250, 0
7534 00:57:10.191374 136 : 4250, 0
7535 00:57:10.194310 140 : 4253, 0
7536 00:57:10.194473 144 : 4360, 0
7537 00:57:10.194559 148 : 4361, 0
7538 00:57:10.197926 152 : 4250, 0
7539 00:57:10.198054 156 : 4249, 0
7540 00:57:10.200796 160 : 4250, 0
7541 00:57:10.200878 164 : 4250, 0
7542 00:57:10.200943 168 : 4249, 0
7543 00:57:10.204301 172 : 4249, 0
7544 00:57:10.204398 176 : 4250, 0
7545 00:57:10.204477 180 : 4250, 0
7546 00:57:10.207546 184 : 4249, 0
7547 00:57:10.207658 188 : 4250, 0
7548 00:57:10.210929 192 : 4253, 0
7549 00:57:10.211011 196 : 4249, 0
7550 00:57:10.211076 200 : 4250, 0
7551 00:57:10.213967 204 : 4363, 0
7552 00:57:10.214093 208 : 4249, 0
7553 00:57:10.217558 212 : 4360, 0
7554 00:57:10.217639 216 : 4361, 0
7555 00:57:10.217704 220 : 4250, 0
7556 00:57:10.221278 224 : 4250, 154
7557 00:57:10.221360 228 : 4252, 3221
7558 00:57:10.224153 232 : 4360, 4137
7559 00:57:10.224263 236 : 4361, 4137
7560 00:57:10.227144 240 : 4250, 4027
7561 00:57:10.227235 244 : 4252, 4030
7562 00:57:10.230651 248 : 4363, 4140
7563 00:57:10.230779 252 : 4250, 4026
7564 00:57:10.234282 256 : 4250, 4027
7565 00:57:10.234363 260 : 4249, 4027
7566 00:57:10.237445 264 : 4252, 4029
7567 00:57:10.237526 268 : 4250, 4027
7568 00:57:10.237592 272 : 4252, 4027
7569 00:57:10.240927 276 : 4363, 4138
7570 00:57:10.241008 280 : 4250, 4027
7571 00:57:10.243833 284 : 4250, 4026
7572 00:57:10.243914 288 : 4361, 4137
7573 00:57:10.247348 292 : 4250, 4027
7574 00:57:10.247429 296 : 4250, 4027
7575 00:57:10.251155 300 : 4363, 4140
7576 00:57:10.251237 304 : 4250, 4026
7577 00:57:10.254095 308 : 4250, 4027
7578 00:57:10.254176 312 : 4249, 4027
7579 00:57:10.257042 316 : 4253, 4029
7580 00:57:10.257124 320 : 4250, 4027
7581 00:57:10.260259 324 : 4250, 4027
7582 00:57:10.260340 328 : 4360, 4138
7583 00:57:10.260405 332 : 4250, 4027
7584 00:57:10.263548 336 : 4250, 3953
7585 00:57:10.263629 340 : 4361, 2377
7586 00:57:10.267275 344 : 4250, 268
7587 00:57:10.267356
7588 00:57:10.270630 MIOCK jitter meter ch=0
7589 00:57:10.270710
7590 00:57:10.270774 1T = (344-92) = 252 dly cells
7591 00:57:10.276858 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7592 00:57:10.276939 ==
7593 00:57:10.280660 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 00:57:10.283983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 00:57:10.287118 ==
7596 00:57:10.290086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7597 00:57:10.293843 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7598 00:57:10.300126 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7599 00:57:10.306779 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7600 00:57:10.314188 [CA 0] Center 43 (12~74) winsize 63
7601 00:57:10.317892 [CA 1] Center 42 (12~73) winsize 62
7602 00:57:10.320593 [CA 2] Center 38 (9~68) winsize 60
7603 00:57:10.324010 [CA 3] Center 38 (8~68) winsize 61
7604 00:57:10.327650 [CA 4] Center 36 (7~66) winsize 60
7605 00:57:10.330460 [CA 5] Center 35 (6~65) winsize 60
7606 00:57:10.330540
7607 00:57:10.333892 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7608 00:57:10.333973
7609 00:57:10.340733 [CATrainingPosCal] consider 1 rank data
7610 00:57:10.340814 u2DelayCellTimex100 = 258/100 ps
7611 00:57:10.347237 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7612 00:57:10.350263 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7613 00:57:10.353805 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7614 00:57:10.356990 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7615 00:57:10.360142 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7616 00:57:10.363569 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7617 00:57:10.363650
7618 00:57:10.366643 CA PerBit enable=1, Macro0, CA PI delay=35
7619 00:57:10.366723
7620 00:57:10.369899 [CBTSetCACLKResult] CA Dly = 35
7621 00:57:10.373415 CS Dly: 11 (0~42)
7622 00:57:10.377173 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7623 00:57:10.380147 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7624 00:57:10.380227 ==
7625 00:57:10.383273 Dram Type= 6, Freq= 0, CH_0, rank 1
7626 00:57:10.389582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 00:57:10.389662 ==
7628 00:57:10.393266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7629 00:57:10.399507 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7630 00:57:10.403238 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7631 00:57:10.409537 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7632 00:57:10.417952 [CA 0] Center 42 (12~73) winsize 62
7633 00:57:10.421006 [CA 1] Center 43 (13~73) winsize 61
7634 00:57:10.424782 [CA 2] Center 37 (8~67) winsize 60
7635 00:57:10.427545 [CA 3] Center 37 (7~67) winsize 61
7636 00:57:10.430903 [CA 4] Center 35 (6~65) winsize 60
7637 00:57:10.434157 [CA 5] Center 35 (5~65) winsize 61
7638 00:57:10.434237
7639 00:57:10.437200 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7640 00:57:10.437281
7641 00:57:10.443956 [CATrainingPosCal] consider 2 rank data
7642 00:57:10.444035 u2DelayCellTimex100 = 258/100 ps
7643 00:57:10.450378 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7644 00:57:10.454013 CA1 delay=43 (13~73),Diff = 8 PI (30 cell)
7645 00:57:10.456789 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7646 00:57:10.460418 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7647 00:57:10.463550 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7648 00:57:10.467419 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7649 00:57:10.467499
7650 00:57:10.470334 CA PerBit enable=1, Macro0, CA PI delay=35
7651 00:57:10.470414
7652 00:57:10.473459 [CBTSetCACLKResult] CA Dly = 35
7653 00:57:10.476850 CS Dly: 12 (0~44)
7654 00:57:10.479989 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7655 00:57:10.483167 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7656 00:57:10.483247
7657 00:57:10.486362 ----->DramcWriteLeveling(PI) begin...
7658 00:57:10.489570 ==
7659 00:57:10.492985 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 00:57:10.496550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 00:57:10.496629 ==
7662 00:57:10.499783 Write leveling (Byte 0): 33 => 33
7663 00:57:10.502817 Write leveling (Byte 1): 26 => 26
7664 00:57:10.506616 DramcWriteLeveling(PI) end<-----
7665 00:57:10.506697
7666 00:57:10.506760 ==
7667 00:57:10.509699 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 00:57:10.512772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 00:57:10.512852 ==
7670 00:57:10.516256 [Gating] SW mode calibration
7671 00:57:10.523161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7672 00:57:10.529208 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7673 00:57:10.533462 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 00:57:10.535974 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 00:57:10.542703 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7676 00:57:10.545604 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7677 00:57:10.549142 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7678 00:57:10.555546 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7679 00:57:10.559015 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7680 00:57:10.562555 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7681 00:57:10.568541 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7682 00:57:10.572123 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7683 00:57:10.575789 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7684 00:57:10.582455 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7685 00:57:10.585638 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7686 00:57:10.588850 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7687 00:57:10.595412 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7688 00:57:10.598925 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7689 00:57:10.602224 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7690 00:57:10.608446 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7691 00:57:10.611459 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7692 00:57:10.615140 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7693 00:57:10.621912 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7694 00:57:10.624934 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7695 00:57:10.628167 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7696 00:57:10.634665 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7697 00:57:10.637844 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 00:57:10.641823 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7699 00:57:10.648373 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 00:57:10.651603 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7701 00:57:10.654376 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7702 00:57:10.661256 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7703 00:57:10.664344 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7704 00:57:10.667568 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 00:57:10.674411 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 00:57:10.677670 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 00:57:10.680879 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 00:57:10.687245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 00:57:10.690966 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 00:57:10.694157 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 00:57:10.700777 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 00:57:10.703725 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 00:57:10.707097 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 00:57:10.713851 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 00:57:10.717318 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7716 00:57:10.720361 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7717 00:57:10.727348 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7718 00:57:10.730547 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7719 00:57:10.733534 Total UI for P1: 0, mck2ui 16
7720 00:57:10.737341 best dqsien dly found for B0: ( 1, 9, 12)
7721 00:57:10.740061 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7722 00:57:10.747149 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7723 00:57:10.747251 Total UI for P1: 0, mck2ui 16
7724 00:57:10.753010 best dqsien dly found for B1: ( 1, 9, 22)
7725 00:57:10.756972 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7726 00:57:10.759906 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7727 00:57:10.759986
7728 00:57:10.763793 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7729 00:57:10.766476 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7730 00:57:10.769781 [Gating] SW calibration Done
7731 00:57:10.769861 ==
7732 00:57:10.773117 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 00:57:10.776266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 00:57:10.776347 ==
7735 00:57:10.779400 RX Vref Scan: 0
7736 00:57:10.779480
7737 00:57:10.782770 RX Vref 0 -> 0, step: 1
7738 00:57:10.782850
7739 00:57:10.782914 RX Delay 0 -> 252, step: 8
7740 00:57:10.790045 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7741 00:57:10.792707 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7742 00:57:10.796320 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7743 00:57:10.799205 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7744 00:57:10.802609 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7745 00:57:10.809128 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7746 00:57:10.812260 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7747 00:57:10.815592 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7748 00:57:10.819259 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7749 00:57:10.822534 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7750 00:57:10.829276 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7751 00:57:10.832500 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7752 00:57:10.835643 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7753 00:57:10.838757 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7754 00:57:10.845305 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7755 00:57:10.849275 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7756 00:57:10.849356 ==
7757 00:57:10.852397 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 00:57:10.855597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 00:57:10.855743 ==
7760 00:57:10.855836 DQS Delay:
7761 00:57:10.858496 DQS0 = 0, DQS1 = 0
7762 00:57:10.858607 DQM Delay:
7763 00:57:10.861958 DQM0 = 134, DQM1 = 126
7764 00:57:10.862047 DQ Delay:
7765 00:57:10.865426 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7766 00:57:10.868539 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =143
7767 00:57:10.871760 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7768 00:57:10.878527 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7769 00:57:10.878633
7770 00:57:10.878734
7771 00:57:10.878822 ==
7772 00:57:10.881560 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 00:57:10.884722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 00:57:10.884804 ==
7775 00:57:10.884868
7776 00:57:10.884928
7777 00:57:10.887958 TX Vref Scan disable
7778 00:57:10.888038 == TX Byte 0 ==
7779 00:57:10.894844 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7780 00:57:10.898453 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7781 00:57:10.898536 == TX Byte 1 ==
7782 00:57:10.904598 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7783 00:57:10.908383 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7784 00:57:10.908463 ==
7785 00:57:10.911097 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 00:57:10.915029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 00:57:10.915110 ==
7788 00:57:10.927726
7789 00:57:10.931325 TX Vref early break, caculate TX vref
7790 00:57:10.934585 TX Vref=16, minBit 4, minWin=21, winSum=366
7791 00:57:10.937581 TX Vref=18, minBit 1, minWin=23, winSum=379
7792 00:57:10.941174 TX Vref=20, minBit 1, minWin=24, winSum=390
7793 00:57:10.944741 TX Vref=22, minBit 1, minWin=24, winSum=398
7794 00:57:10.947691 TX Vref=24, minBit 4, minWin=24, winSum=408
7795 00:57:10.954444 TX Vref=26, minBit 4, minWin=25, winSum=417
7796 00:57:10.958173 TX Vref=28, minBit 0, minWin=25, winSum=419
7797 00:57:10.960928 TX Vref=30, minBit 4, minWin=24, winSum=405
7798 00:57:10.964414 TX Vref=32, minBit 4, minWin=23, winSum=396
7799 00:57:10.970843 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7800 00:57:10.970924
7801 00:57:10.974068 Final TX Range 0 Vref 28
7802 00:57:10.974149
7803 00:57:10.974213 ==
7804 00:57:10.977820 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 00:57:10.980477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 00:57:10.980559 ==
7807 00:57:10.980624
7808 00:57:10.980683
7809 00:57:10.984265 TX Vref Scan disable
7810 00:57:10.991015 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7811 00:57:10.991095 == TX Byte 0 ==
7812 00:57:10.994432 u2DelayCellOfst[0]=15 cells (4 PI)
7813 00:57:10.996901 u2DelayCellOfst[1]=18 cells (5 PI)
7814 00:57:11.000718 u2DelayCellOfst[2]=15 cells (4 PI)
7815 00:57:11.003809 u2DelayCellOfst[3]=15 cells (4 PI)
7816 00:57:11.006927 u2DelayCellOfst[4]=11 cells (3 PI)
7817 00:57:11.010601 u2DelayCellOfst[5]=0 cells (0 PI)
7818 00:57:11.013807 u2DelayCellOfst[6]=18 cells (5 PI)
7819 00:57:11.016755 u2DelayCellOfst[7]=22 cells (6 PI)
7820 00:57:11.020437 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7821 00:57:11.023414 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7822 00:57:11.027178 == TX Byte 1 ==
7823 00:57:11.027259 u2DelayCellOfst[8]=0 cells (0 PI)
7824 00:57:11.030474 u2DelayCellOfst[9]=3 cells (1 PI)
7825 00:57:11.033656 u2DelayCellOfst[10]=7 cells (2 PI)
7826 00:57:11.037161 u2DelayCellOfst[11]=3 cells (1 PI)
7827 00:57:11.040368 u2DelayCellOfst[12]=15 cells (4 PI)
7828 00:57:11.043398 u2DelayCellOfst[13]=15 cells (4 PI)
7829 00:57:11.046972 u2DelayCellOfst[14]=18 cells (5 PI)
7830 00:57:11.049997 u2DelayCellOfst[15]=15 cells (4 PI)
7831 00:57:11.053895 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7832 00:57:11.060345 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7833 00:57:11.060426 DramC Write-DBI on
7834 00:57:11.060489 ==
7835 00:57:11.063592 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 00:57:11.067307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 00:57:11.069938 ==
7838 00:57:11.070019
7839 00:57:11.070082
7840 00:57:11.070140 TX Vref Scan disable
7841 00:57:11.073508 == TX Byte 0 ==
7842 00:57:11.076953 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7843 00:57:11.080442 == TX Byte 1 ==
7844 00:57:11.083563 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7845 00:57:11.087135 DramC Write-DBI off
7846 00:57:11.087216
7847 00:57:11.087279 [DATLAT]
7848 00:57:11.087339 Freq=1600, CH0 RK0
7849 00:57:11.087396
7850 00:57:11.090002 DATLAT Default: 0xf
7851 00:57:11.093437 0, 0xFFFF, sum = 0
7852 00:57:11.093520 1, 0xFFFF, sum = 0
7853 00:57:11.097045 2, 0xFFFF, sum = 0
7854 00:57:11.097127 3, 0xFFFF, sum = 0
7855 00:57:11.100309 4, 0xFFFF, sum = 0
7856 00:57:11.100390 5, 0xFFFF, sum = 0
7857 00:57:11.103823 6, 0xFFFF, sum = 0
7858 00:57:11.103904 7, 0xFFFF, sum = 0
7859 00:57:11.106590 8, 0xFFFF, sum = 0
7860 00:57:11.106671 9, 0xFFFF, sum = 0
7861 00:57:11.109798 10, 0xFFFF, sum = 0
7862 00:57:11.109880 11, 0xFFFF, sum = 0
7863 00:57:11.113084 12, 0xFFFF, sum = 0
7864 00:57:11.113166 13, 0xFFFF, sum = 0
7865 00:57:11.117309 14, 0x0, sum = 1
7866 00:57:11.117391 15, 0x0, sum = 2
7867 00:57:11.119610 16, 0x0, sum = 3
7868 00:57:11.119720 17, 0x0, sum = 4
7869 00:57:11.122937 best_step = 15
7870 00:57:11.123017
7871 00:57:11.123080 ==
7872 00:57:11.126357 Dram Type= 6, Freq= 0, CH_0, rank 0
7873 00:57:11.129999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7874 00:57:11.130080 ==
7875 00:57:11.132934 RX Vref Scan: 1
7876 00:57:11.133014
7877 00:57:11.133078 Set Vref Range= 24 -> 127
7878 00:57:11.133137
7879 00:57:11.136797 RX Vref 24 -> 127, step: 1
7880 00:57:11.136952
7881 00:57:11.139462 RX Delay 11 -> 252, step: 4
7882 00:57:11.139542
7883 00:57:11.142916 Set Vref, RX VrefLevel [Byte0]: 24
7884 00:57:11.146069 [Byte1]: 24
7885 00:57:11.146150
7886 00:57:11.149566 Set Vref, RX VrefLevel [Byte0]: 25
7887 00:57:11.153224 [Byte1]: 25
7888 00:57:11.156073
7889 00:57:11.156152 Set Vref, RX VrefLevel [Byte0]: 26
7890 00:57:11.159549 [Byte1]: 26
7891 00:57:11.164262
7892 00:57:11.164341 Set Vref, RX VrefLevel [Byte0]: 27
7893 00:57:11.167440 [Byte1]: 27
7894 00:57:11.171456
7895 00:57:11.171566 Set Vref, RX VrefLevel [Byte0]: 28
7896 00:57:11.174657 [Byte1]: 28
7897 00:57:11.179348
7898 00:57:11.179427 Set Vref, RX VrefLevel [Byte0]: 29
7899 00:57:11.182715 [Byte1]: 29
7900 00:57:11.187235
7901 00:57:11.187314 Set Vref, RX VrefLevel [Byte0]: 30
7902 00:57:11.190107 [Byte1]: 30
7903 00:57:11.194903
7904 00:57:11.194982 Set Vref, RX VrefLevel [Byte0]: 31
7905 00:57:11.197743 [Byte1]: 31
7906 00:57:11.202337
7907 00:57:11.202420 Set Vref, RX VrefLevel [Byte0]: 32
7908 00:57:11.205372 [Byte1]: 32
7909 00:57:11.209854
7910 00:57:11.209933 Set Vref, RX VrefLevel [Byte0]: 33
7911 00:57:11.212711 [Byte1]: 33
7912 00:57:11.217311
7913 00:57:11.217389 Set Vref, RX VrefLevel [Byte0]: 34
7914 00:57:11.220613 [Byte1]: 34
7915 00:57:11.224827
7916 00:57:11.224910 Set Vref, RX VrefLevel [Byte0]: 35
7917 00:57:11.228026 [Byte1]: 35
7918 00:57:11.232293
7919 00:57:11.232373 Set Vref, RX VrefLevel [Byte0]: 36
7920 00:57:11.236108 [Byte1]: 36
7921 00:57:11.240202
7922 00:57:11.240284 Set Vref, RX VrefLevel [Byte0]: 37
7923 00:57:11.243652 [Byte1]: 37
7924 00:57:11.248038
7925 00:57:11.248118 Set Vref, RX VrefLevel [Byte0]: 38
7926 00:57:11.250801 [Byte1]: 38
7927 00:57:11.255637
7928 00:57:11.255738 Set Vref, RX VrefLevel [Byte0]: 39
7929 00:57:11.258795 [Byte1]: 39
7930 00:57:11.262919
7931 00:57:11.262999 Set Vref, RX VrefLevel [Byte0]: 40
7932 00:57:11.266446 [Byte1]: 40
7933 00:57:11.270792
7934 00:57:11.270872 Set Vref, RX VrefLevel [Byte0]: 41
7935 00:57:11.274095 [Byte1]: 41
7936 00:57:11.278296
7937 00:57:11.278377 Set Vref, RX VrefLevel [Byte0]: 42
7938 00:57:11.281897 [Byte1]: 42
7939 00:57:11.285926
7940 00:57:11.286006 Set Vref, RX VrefLevel [Byte0]: 43
7941 00:57:11.289715 [Byte1]: 43
7942 00:57:11.293933
7943 00:57:11.294013 Set Vref, RX VrefLevel [Byte0]: 44
7944 00:57:11.296980 [Byte1]: 44
7945 00:57:11.301507
7946 00:57:11.301587 Set Vref, RX VrefLevel [Byte0]: 45
7947 00:57:11.304649 [Byte1]: 45
7948 00:57:11.308902
7949 00:57:11.308982 Set Vref, RX VrefLevel [Byte0]: 46
7950 00:57:11.311816 [Byte1]: 46
7951 00:57:11.316426
7952 00:57:11.316506 Set Vref, RX VrefLevel [Byte0]: 47
7953 00:57:11.319454 [Byte1]: 47
7954 00:57:11.324092
7955 00:57:11.324172 Set Vref, RX VrefLevel [Byte0]: 48
7956 00:57:11.327203 [Byte1]: 48
7957 00:57:11.331776
7958 00:57:11.331855 Set Vref, RX VrefLevel [Byte0]: 49
7959 00:57:11.334648 [Byte1]: 49
7960 00:57:11.338927
7961 00:57:11.339006 Set Vref, RX VrefLevel [Byte0]: 50
7962 00:57:11.342547 [Byte1]: 50
7963 00:57:11.346474
7964 00:57:11.346553 Set Vref, RX VrefLevel [Byte0]: 51
7965 00:57:11.349811 [Byte1]: 51
7966 00:57:11.354176
7967 00:57:11.354255 Set Vref, RX VrefLevel [Byte0]: 52
7968 00:57:11.358324 [Byte1]: 52
7969 00:57:11.362328
7970 00:57:11.362411 Set Vref, RX VrefLevel [Byte0]: 53
7971 00:57:11.365153 [Byte1]: 53
7972 00:57:11.370019
7973 00:57:11.370099 Set Vref, RX VrefLevel [Byte0]: 54
7974 00:57:11.373081 [Byte1]: 54
7975 00:57:11.376900
7976 00:57:11.376980 Set Vref, RX VrefLevel [Byte0]: 55
7977 00:57:11.380185 [Byte1]: 55
7978 00:57:11.384726
7979 00:57:11.384827 Set Vref, RX VrefLevel [Byte0]: 56
7980 00:57:11.388042 [Byte1]: 56
7981 00:57:11.392243
7982 00:57:11.392349 Set Vref, RX VrefLevel [Byte0]: 57
7983 00:57:11.395666 [Byte1]: 57
7984 00:57:11.399872
7985 00:57:11.399952 Set Vref, RX VrefLevel [Byte0]: 58
7986 00:57:11.403219 [Byte1]: 58
7987 00:57:11.408286
7988 00:57:11.408370 Set Vref, RX VrefLevel [Byte0]: 59
7989 00:57:11.410664 [Byte1]: 59
7990 00:57:11.415567
7991 00:57:11.415648 Set Vref, RX VrefLevel [Byte0]: 60
7992 00:57:11.418294 [Byte1]: 60
7993 00:57:11.423169
7994 00:57:11.423249 Set Vref, RX VrefLevel [Byte0]: 61
7995 00:57:11.429229 [Byte1]: 61
7996 00:57:11.429313
7997 00:57:11.432435 Set Vref, RX VrefLevel [Byte0]: 62
7998 00:57:11.436239 [Byte1]: 62
7999 00:57:11.436314
8000 00:57:11.439424 Set Vref, RX VrefLevel [Byte0]: 63
8001 00:57:11.442721 [Byte1]: 63
8002 00:57:11.445552
8003 00:57:11.445633 Set Vref, RX VrefLevel [Byte0]: 64
8004 00:57:11.448748 [Byte1]: 64
8005 00:57:11.453391
8006 00:57:11.453467 Set Vref, RX VrefLevel [Byte0]: 65
8007 00:57:11.456397 [Byte1]: 65
8008 00:57:11.460758
8009 00:57:11.460833 Set Vref, RX VrefLevel [Byte0]: 66
8010 00:57:11.464378 [Byte1]: 66
8011 00:57:11.468691
8012 00:57:11.468770 Set Vref, RX VrefLevel [Byte0]: 67
8013 00:57:11.471970 [Byte1]: 67
8014 00:57:11.476156
8015 00:57:11.476230 Set Vref, RX VrefLevel [Byte0]: 68
8016 00:57:11.479086 [Byte1]: 68
8017 00:57:11.483637
8018 00:57:11.483753 Set Vref, RX VrefLevel [Byte0]: 69
8019 00:57:11.487086 [Byte1]: 69
8020 00:57:11.491655
8021 00:57:11.491752 Set Vref, RX VrefLevel [Byte0]: 70
8022 00:57:11.495056 [Byte1]: 70
8023 00:57:11.499084
8024 00:57:11.499159 Set Vref, RX VrefLevel [Byte0]: 71
8025 00:57:11.501982 [Byte1]: 71
8026 00:57:11.506281
8027 00:57:11.506361 Set Vref, RX VrefLevel [Byte0]: 72
8028 00:57:11.510316 [Byte1]: 72
8029 00:57:11.514203
8030 00:57:11.514284 Set Vref, RX VrefLevel [Byte0]: 73
8031 00:57:11.517171 [Byte1]: 73
8032 00:57:11.522172
8033 00:57:11.522253 Set Vref, RX VrefLevel [Byte0]: 74
8034 00:57:11.524994 [Byte1]: 74
8035 00:57:11.529284
8036 00:57:11.529390 Set Vref, RX VrefLevel [Byte0]: 75
8037 00:57:11.532576 [Byte1]: 75
8038 00:57:11.537031
8039 00:57:11.537111 Set Vref, RX VrefLevel [Byte0]: 76
8040 00:57:11.540198 [Byte1]: 76
8041 00:57:11.544846
8042 00:57:11.544914 Set Vref, RX VrefLevel [Byte0]: 77
8043 00:57:11.547879 [Byte1]: 77
8044 00:57:11.552354
8045 00:57:11.552433 Set Vref, RX VrefLevel [Byte0]: 78
8046 00:57:11.555535 [Byte1]: 78
8047 00:57:11.560002
8048 00:57:11.560081 Set Vref, RX VrefLevel [Byte0]: 79
8049 00:57:11.563043 [Byte1]: 79
8050 00:57:11.568041
8051 00:57:11.568121 Set Vref, RX VrefLevel [Byte0]: 80
8052 00:57:11.570946 [Byte1]: 80
8053 00:57:11.575265
8054 00:57:11.575359 Final RX Vref Byte 0 = 67 to rank0
8055 00:57:11.578178 Final RX Vref Byte 1 = 59 to rank0
8056 00:57:11.581815 Final RX Vref Byte 0 = 67 to rank1
8057 00:57:11.585072 Final RX Vref Byte 1 = 59 to rank1==
8058 00:57:11.588800 Dram Type= 6, Freq= 0, CH_0, rank 0
8059 00:57:11.595137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 00:57:11.595217 ==
8061 00:57:11.595285 DQS Delay:
8062 00:57:11.597941 DQS0 = 0, DQS1 = 0
8063 00:57:11.598021 DQM Delay:
8064 00:57:11.598085 DQM0 = 132, DQM1 = 123
8065 00:57:11.601537 DQ Delay:
8066 00:57:11.604700 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8067 00:57:11.607643 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
8068 00:57:11.612751 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8069 00:57:11.614683 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8070 00:57:11.614763
8071 00:57:11.614825
8072 00:57:11.614883
8073 00:57:11.617736 [DramC_TX_OE_Calibration] TA2
8074 00:57:11.621318 Original DQ_B0 (3 6) =30, OEN = 27
8075 00:57:11.624260 Original DQ_B1 (3 6) =30, OEN = 27
8076 00:57:11.627425 24, 0x0, End_B0=24 End_B1=24
8077 00:57:11.631061 25, 0x0, End_B0=25 End_B1=25
8078 00:57:11.631153 26, 0x0, End_B0=26 End_B1=26
8079 00:57:11.634405 27, 0x0, End_B0=27 End_B1=27
8080 00:57:11.637858 28, 0x0, End_B0=28 End_B1=28
8081 00:57:11.640975 29, 0x0, End_B0=29 End_B1=29
8082 00:57:11.641057 30, 0x0, End_B0=30 End_B1=30
8083 00:57:11.643924 31, 0x4141, End_B0=30 End_B1=30
8084 00:57:11.647155 Byte0 end_step=30 best_step=27
8085 00:57:11.651025 Byte1 end_step=30 best_step=27
8086 00:57:11.653876 Byte0 TX OE(2T, 0.5T) = (3, 3)
8087 00:57:11.657706 Byte1 TX OE(2T, 0.5T) = (3, 3)
8088 00:57:11.657785
8089 00:57:11.657847
8090 00:57:11.663936 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8091 00:57:11.667347 CH0 RK0: MR19=303, MR18=2112
8092 00:57:11.673546 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8093 00:57:11.673667
8094 00:57:11.677260 ----->DramcWriteLeveling(PI) begin...
8095 00:57:11.677358 ==
8096 00:57:11.680344 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 00:57:11.683494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 00:57:11.683608 ==
8099 00:57:11.687195 Write leveling (Byte 0): 36 => 36
8100 00:57:11.690675 Write leveling (Byte 1): 28 => 28
8101 00:57:11.693551 DramcWriteLeveling(PI) end<-----
8102 00:57:11.693686
8103 00:57:11.693809 ==
8104 00:57:11.697270 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 00:57:11.703530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 00:57:11.703635 ==
8107 00:57:11.703769 [Gating] SW mode calibration
8108 00:57:11.713163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8109 00:57:11.716561 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8110 00:57:11.722752 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 00:57:11.726546 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 00:57:11.729529 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 00:57:11.736290 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8114 00:57:11.739459 1 4 16 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
8115 00:57:11.743168 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8116 00:57:11.749707 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 00:57:11.752684 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 00:57:11.755739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 00:57:11.762739 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 00:57:11.765654 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8121 00:57:11.769143 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8122 00:57:11.775708 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8123 00:57:11.779444 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8124 00:57:11.782444 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8125 00:57:11.789016 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 00:57:11.792745 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 00:57:11.795664 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 00:57:11.799751 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 00:57:11.805781 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
8130 00:57:11.808899 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8131 00:57:11.812255 1 6 20 | B1->B0 | 3635 4646 | 1 0 | (0 0) (0 0)
8132 00:57:11.818602 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 00:57:11.822243 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 00:57:11.825365 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 00:57:11.831767 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 00:57:11.835536 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8137 00:57:11.838488 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8138 00:57:11.845403 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8139 00:57:11.848478 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8140 00:57:11.855252 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 00:57:11.858258 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 00:57:11.861701 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 00:57:11.868092 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 00:57:11.871445 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 00:57:11.875350 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 00:57:11.878336 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 00:57:11.884627 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 00:57:11.887782 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 00:57:11.891003 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 00:57:11.898234 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 00:57:11.901385 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 00:57:11.905063 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 00:57:11.911267 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8154 00:57:11.914699 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8155 00:57:11.917561 Total UI for P1: 0, mck2ui 16
8156 00:57:11.921283 best dqsien dly found for B0: ( 1, 9, 12)
8157 00:57:11.924163 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8158 00:57:11.930626 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8159 00:57:11.934194 Total UI for P1: 0, mck2ui 16
8160 00:57:11.937333 best dqsien dly found for B1: ( 1, 9, 18)
8161 00:57:11.940617 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8162 00:57:11.944061 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8163 00:57:11.944163
8164 00:57:11.947560 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8165 00:57:11.950713 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8166 00:57:11.954000 [Gating] SW calibration Done
8167 00:57:11.954099 ==
8168 00:57:11.957275 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 00:57:11.961198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 00:57:11.961339 ==
8171 00:57:11.964117 RX Vref Scan: 0
8172 00:57:11.964219
8173 00:57:11.967150 RX Vref 0 -> 0, step: 1
8174 00:57:11.967250
8175 00:57:11.967342 RX Delay 0 -> 252, step: 8
8176 00:57:11.973691 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8177 00:57:11.977280 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8178 00:57:11.980101 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8179 00:57:11.983645 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8180 00:57:11.986942 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8181 00:57:11.993407 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8182 00:57:11.996920 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8183 00:57:12.000270 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8184 00:57:12.003135 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8185 00:57:12.006882 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8186 00:57:12.013439 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8187 00:57:12.016438 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8188 00:57:12.019650 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8189 00:57:12.023138 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8190 00:57:12.029752 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8191 00:57:12.032891 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8192 00:57:12.032994 ==
8193 00:57:12.036168 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 00:57:12.039293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 00:57:12.039392 ==
8196 00:57:12.043191 DQS Delay:
8197 00:57:12.043270 DQS0 = 0, DQS1 = 0
8198 00:57:12.043359 DQM Delay:
8199 00:57:12.046409 DQM0 = 133, DQM1 = 128
8200 00:57:12.046510 DQ Delay:
8201 00:57:12.049348 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8202 00:57:12.053007 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8203 00:57:12.059393 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8204 00:57:12.062563 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8205 00:57:12.062662
8206 00:57:12.062755
8207 00:57:12.062840 ==
8208 00:57:12.066087 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 00:57:12.069479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 00:57:12.069581 ==
8211 00:57:12.069672
8212 00:57:12.069760
8213 00:57:12.072881 TX Vref Scan disable
8214 00:57:12.075782 == TX Byte 0 ==
8215 00:57:12.079474 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8216 00:57:12.082570 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8217 00:57:12.086117 == TX Byte 1 ==
8218 00:57:12.089092 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8219 00:57:12.092510 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8220 00:57:12.092614 ==
8221 00:57:12.096232 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 00:57:12.098871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 00:57:12.101855 ==
8224 00:57:12.114514
8225 00:57:12.117655 TX Vref early break, caculate TX vref
8226 00:57:12.120748 TX Vref=16, minBit 1, minWin=22, winSum=378
8227 00:57:12.124497 TX Vref=18, minBit 1, minWin=22, winSum=388
8228 00:57:12.127997 TX Vref=20, minBit 2, minWin=23, winSum=395
8229 00:57:12.130876 TX Vref=22, minBit 1, minWin=24, winSum=408
8230 00:57:12.133685 TX Vref=24, minBit 3, minWin=24, winSum=413
8231 00:57:12.140560 TX Vref=26, minBit 0, minWin=25, winSum=414
8232 00:57:12.144408 TX Vref=28, minBit 0, minWin=24, winSum=412
8233 00:57:12.147205 TX Vref=30, minBit 0, minWin=24, winSum=403
8234 00:57:12.150848 TX Vref=32, minBit 1, minWin=23, winSum=393
8235 00:57:12.153764 TX Vref=34, minBit 0, minWin=23, winSum=382
8236 00:57:12.160189 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8237 00:57:12.160270
8238 00:57:12.163760 Final TX Range 0 Vref 26
8239 00:57:12.163867
8240 00:57:12.163935 ==
8241 00:57:12.167035 Dram Type= 6, Freq= 0, CH_0, rank 1
8242 00:57:12.170464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 00:57:12.170545 ==
8244 00:57:12.170608
8245 00:57:12.170666
8246 00:57:12.173499 TX Vref Scan disable
8247 00:57:12.180149 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8248 00:57:12.180230 == TX Byte 0 ==
8249 00:57:12.183366 u2DelayCellOfst[0]=15 cells (4 PI)
8250 00:57:12.186543 u2DelayCellOfst[1]=18 cells (5 PI)
8251 00:57:12.190145 u2DelayCellOfst[2]=15 cells (4 PI)
8252 00:57:12.193666 u2DelayCellOfst[3]=18 cells (5 PI)
8253 00:57:12.196528 u2DelayCellOfst[4]=11 cells (3 PI)
8254 00:57:12.200242 u2DelayCellOfst[5]=0 cells (0 PI)
8255 00:57:12.202971 u2DelayCellOfst[6]=18 cells (5 PI)
8256 00:57:12.206564 u2DelayCellOfst[7]=18 cells (5 PI)
8257 00:57:12.210198 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8258 00:57:12.213221 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8259 00:57:12.216761 == TX Byte 1 ==
8260 00:57:12.220044 u2DelayCellOfst[8]=0 cells (0 PI)
8261 00:57:12.223194 u2DelayCellOfst[9]=3 cells (1 PI)
8262 00:57:12.226380 u2DelayCellOfst[10]=7 cells (2 PI)
8263 00:57:12.226457 u2DelayCellOfst[11]=3 cells (1 PI)
8264 00:57:12.229787 u2DelayCellOfst[12]=11 cells (3 PI)
8265 00:57:12.232776 u2DelayCellOfst[13]=11 cells (3 PI)
8266 00:57:12.236058 u2DelayCellOfst[14]=18 cells (5 PI)
8267 00:57:12.239435 u2DelayCellOfst[15]=11 cells (3 PI)
8268 00:57:12.246352 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8269 00:57:12.249494 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8270 00:57:12.249576 DramC Write-DBI on
8271 00:57:12.252717 ==
8272 00:57:12.256265 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 00:57:12.259187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 00:57:12.259269 ==
8275 00:57:12.259333
8276 00:57:12.259392
8277 00:57:12.262739 TX Vref Scan disable
8278 00:57:12.262820 == TX Byte 0 ==
8279 00:57:12.269329 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8280 00:57:12.269410 == TX Byte 1 ==
8281 00:57:12.272644 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8282 00:57:12.275842 DramC Write-DBI off
8283 00:57:12.275923
8284 00:57:12.275988 [DATLAT]
8285 00:57:12.279057 Freq=1600, CH0 RK1
8286 00:57:12.279137
8287 00:57:12.279201 DATLAT Default: 0xf
8288 00:57:12.282275 0, 0xFFFF, sum = 0
8289 00:57:12.282358 1, 0xFFFF, sum = 0
8290 00:57:12.285875 2, 0xFFFF, sum = 0
8291 00:57:12.285958 3, 0xFFFF, sum = 0
8292 00:57:12.288645 4, 0xFFFF, sum = 0
8293 00:57:12.292424 5, 0xFFFF, sum = 0
8294 00:57:12.292507 6, 0xFFFF, sum = 0
8295 00:57:12.295259 7, 0xFFFF, sum = 0
8296 00:57:12.295378 8, 0xFFFF, sum = 0
8297 00:57:12.298731 9, 0xFFFF, sum = 0
8298 00:57:12.298813 10, 0xFFFF, sum = 0
8299 00:57:12.301963 11, 0xFFFF, sum = 0
8300 00:57:12.302046 12, 0xFFFF, sum = 0
8301 00:57:12.305005 13, 0xFFFF, sum = 0
8302 00:57:12.305087 14, 0x0, sum = 1
8303 00:57:12.308501 15, 0x0, sum = 2
8304 00:57:12.308598 16, 0x0, sum = 3
8305 00:57:12.312136 17, 0x0, sum = 4
8306 00:57:12.312219 best_step = 15
8307 00:57:12.312283
8308 00:57:12.312342 ==
8309 00:57:12.315310 Dram Type= 6, Freq= 0, CH_0, rank 1
8310 00:57:12.321811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 00:57:12.321892 ==
8312 00:57:12.321957 RX Vref Scan: 0
8313 00:57:12.322017
8314 00:57:12.325177 RX Vref 0 -> 0, step: 1
8315 00:57:12.325283
8316 00:57:12.328394 RX Delay 11 -> 252, step: 4
8317 00:57:12.331719 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8318 00:57:12.335023 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8319 00:57:12.337842 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8320 00:57:12.344728 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8321 00:57:12.348007 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8322 00:57:12.351560 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8323 00:57:12.354762 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8324 00:57:12.357890 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8325 00:57:12.364501 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8326 00:57:12.368307 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8327 00:57:12.370948 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8328 00:57:12.374672 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8329 00:57:12.381016 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8330 00:57:12.384137 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8331 00:57:12.387709 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8332 00:57:12.390917 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8333 00:57:12.390999 ==
8334 00:57:12.394446 Dram Type= 6, Freq= 0, CH_0, rank 1
8335 00:57:12.401031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 00:57:12.401113 ==
8337 00:57:12.401177 DQS Delay:
8338 00:57:12.401237 DQS0 = 0, DQS1 = 0
8339 00:57:12.404399 DQM Delay:
8340 00:57:12.404490 DQM0 = 130, DQM1 = 125
8341 00:57:12.407660 DQ Delay:
8342 00:57:12.410719 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8343 00:57:12.413720 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8344 00:57:12.417120 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8345 00:57:12.420419 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8346 00:57:12.420639
8347 00:57:12.420741
8348 00:57:12.420804
8349 00:57:12.423863 [DramC_TX_OE_Calibration] TA2
8350 00:57:12.426869 Original DQ_B0 (3 6) =30, OEN = 27
8351 00:57:12.429974 Original DQ_B1 (3 6) =30, OEN = 27
8352 00:57:12.433519 24, 0x0, End_B0=24 End_B1=24
8353 00:57:12.436979 25, 0x0, End_B0=25 End_B1=25
8354 00:57:12.437062 26, 0x0, End_B0=26 End_B1=26
8355 00:57:12.440089 27, 0x0, End_B0=27 End_B1=27
8356 00:57:12.443752 28, 0x0, End_B0=28 End_B1=28
8357 00:57:12.446968 29, 0x0, End_B0=29 End_B1=29
8358 00:57:12.447050 30, 0x0, End_B0=30 End_B1=30
8359 00:57:12.449835 31, 0x4141, End_B0=30 End_B1=30
8360 00:57:12.453163 Byte0 end_step=30 best_step=27
8361 00:57:12.456197 Byte1 end_step=30 best_step=27
8362 00:57:12.459544 Byte0 TX OE(2T, 0.5T) = (3, 3)
8363 00:57:12.462960 Byte1 TX OE(2T, 0.5T) = (3, 3)
8364 00:57:12.463039
8365 00:57:12.463101
8366 00:57:12.470083 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8367 00:57:12.473350 CH0 RK1: MR19=303, MR18=2104
8368 00:57:12.479637 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8369 00:57:12.483025 [RxdqsGatingPostProcess] freq 1600
8370 00:57:12.489475 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8371 00:57:12.489555 best DQS0 dly(2T, 0.5T) = (1, 1)
8372 00:57:12.492643 best DQS1 dly(2T, 0.5T) = (1, 1)
8373 00:57:12.496113 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8374 00:57:12.499160 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8375 00:57:12.502648 best DQS0 dly(2T, 0.5T) = (1, 1)
8376 00:57:12.505937 best DQS1 dly(2T, 0.5T) = (1, 1)
8377 00:57:12.509451 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8378 00:57:12.512379 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8379 00:57:12.516018 Pre-setting of DQS Precalculation
8380 00:57:12.519029 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8381 00:57:12.522778 ==
8382 00:57:12.525788 Dram Type= 6, Freq= 0, CH_1, rank 0
8383 00:57:12.528809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8384 00:57:12.528890 ==
8385 00:57:12.532334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8386 00:57:12.538954 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8387 00:57:12.541838 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8388 00:57:12.548574 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8389 00:57:12.556753 [CA 0] Center 42 (13~72) winsize 60
8390 00:57:12.560051 [CA 1] Center 42 (13~72) winsize 60
8391 00:57:12.563811 [CA 2] Center 38 (9~67) winsize 59
8392 00:57:12.566484 [CA 3] Center 37 (8~66) winsize 59
8393 00:57:12.569744 [CA 4] Center 37 (8~67) winsize 60
8394 00:57:12.573340 [CA 5] Center 37 (8~67) winsize 60
8395 00:57:12.573451
8396 00:57:12.576758 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8397 00:57:12.576839
8398 00:57:12.580098 [CATrainingPosCal] consider 1 rank data
8399 00:57:12.583321 u2DelayCellTimex100 = 258/100 ps
8400 00:57:12.589968 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8401 00:57:12.593040 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8402 00:57:12.596354 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8403 00:57:12.600187 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8404 00:57:12.603150 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8405 00:57:12.606177 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8406 00:57:12.606274
8407 00:57:12.609605 CA PerBit enable=1, Macro0, CA PI delay=37
8408 00:57:12.609699
8409 00:57:12.613187 [CBTSetCACLKResult] CA Dly = 37
8410 00:57:12.616333 CS Dly: 10 (0~41)
8411 00:57:12.619480 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8412 00:57:12.622974 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8413 00:57:12.623079 ==
8414 00:57:12.626126 Dram Type= 6, Freq= 0, CH_1, rank 1
8415 00:57:12.632578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 00:57:12.632655 ==
8417 00:57:12.636285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8418 00:57:12.642488 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8419 00:57:12.646043 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8420 00:57:12.652271 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8421 00:57:12.659924 [CA 0] Center 42 (13~71) winsize 59
8422 00:57:12.663576 [CA 1] Center 42 (13~72) winsize 60
8423 00:57:12.666509 [CA 2] Center 37 (8~67) winsize 60
8424 00:57:12.670129 [CA 3] Center 37 (8~67) winsize 60
8425 00:57:12.673372 [CA 4] Center 37 (8~67) winsize 60
8426 00:57:12.676393 [CA 5] Center 37 (8~67) winsize 60
8427 00:57:12.676475
8428 00:57:12.680149 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8429 00:57:12.680245
8430 00:57:12.686514 [CATrainingPosCal] consider 2 rank data
8431 00:57:12.686617 u2DelayCellTimex100 = 258/100 ps
8432 00:57:12.692968 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8433 00:57:12.696262 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8434 00:57:12.699586 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8435 00:57:12.702600 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8436 00:57:12.706318 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8437 00:57:12.709130 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8438 00:57:12.709210
8439 00:57:12.713327 CA PerBit enable=1, Macro0, CA PI delay=37
8440 00:57:12.713424
8441 00:57:12.716079 [CBTSetCACLKResult] CA Dly = 37
8442 00:57:12.719411 CS Dly: 11 (0~43)
8443 00:57:12.722364 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8444 00:57:12.725903 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8445 00:57:12.726002
8446 00:57:12.729080 ----->DramcWriteLeveling(PI) begin...
8447 00:57:12.732302 ==
8448 00:57:12.732374 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 00:57:12.738939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 00:57:12.739045 ==
8451 00:57:12.742292 Write leveling (Byte 0): 25 => 25
8452 00:57:12.745397 Write leveling (Byte 1): 27 => 27
8453 00:57:12.748500 DramcWriteLeveling(PI) end<-----
8454 00:57:12.748601
8455 00:57:12.748689 ==
8456 00:57:12.752118 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 00:57:12.755334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 00:57:12.755433 ==
8459 00:57:12.759024 [Gating] SW mode calibration
8460 00:57:12.765459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8461 00:57:12.771771 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8462 00:57:12.774901 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 00:57:12.778222 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 00:57:12.785414 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 00:57:12.788432 1 4 12 | B1->B0 | 3232 3333 | 0 1 | (0 0) (1 1)
8466 00:57:12.791379 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8467 00:57:12.798456 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8468 00:57:12.801727 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8469 00:57:12.804801 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 00:57:12.811350 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 00:57:12.815032 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 00:57:12.818241 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8473 00:57:12.824393 1 5 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
8474 00:57:12.827909 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 00:57:12.831645 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 00:57:12.838020 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8477 00:57:12.841166 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8478 00:57:12.844637 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 00:57:12.851415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 00:57:12.854348 1 6 8 | B1->B0 | 2423 3636 | 1 0 | (0 0) (1 1)
8481 00:57:12.857764 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8482 00:57:12.864401 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8483 00:57:12.867651 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8484 00:57:12.870857 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8485 00:57:12.877748 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 00:57:12.880998 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 00:57:12.884542 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 00:57:12.891347 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8489 00:57:12.894242 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8490 00:57:12.896910 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 00:57:12.904116 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 00:57:12.906895 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 00:57:12.910419 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 00:57:12.917083 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 00:57:12.920948 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 00:57:12.924427 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 00:57:12.930088 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 00:57:12.933813 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 00:57:12.937331 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 00:57:12.943390 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 00:57:12.946961 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 00:57:12.949839 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 00:57:12.956510 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 00:57:12.959961 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 00:57:12.963167 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8506 00:57:12.966239 Total UI for P1: 0, mck2ui 16
8507 00:57:12.970063 best dqsien dly found for B0: ( 1, 9, 10)
8508 00:57:12.972901 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8509 00:57:12.979852 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 00:57:12.983120 Total UI for P1: 0, mck2ui 16
8511 00:57:12.986733 best dqsien dly found for B1: ( 1, 9, 14)
8512 00:57:12.989423 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8513 00:57:12.992689 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8514 00:57:12.992773
8515 00:57:12.996254 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8516 00:57:12.999855 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8517 00:57:13.003371 [Gating] SW calibration Done
8518 00:57:13.003454 ==
8519 00:57:13.006084 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 00:57:13.009438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 00:57:13.012616 ==
8522 00:57:13.012700 RX Vref Scan: 0
8523 00:57:13.012785
8524 00:57:13.016286 RX Vref 0 -> 0, step: 1
8525 00:57:13.016370
8526 00:57:13.016456 RX Delay 0 -> 252, step: 8
8527 00:57:13.022405 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8528 00:57:13.026188 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8529 00:57:13.029306 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8530 00:57:13.032850 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8531 00:57:13.035907 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8532 00:57:13.042579 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8533 00:57:13.045611 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8534 00:57:13.048953 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8535 00:57:13.052309 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8536 00:57:13.059192 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8537 00:57:13.062332 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8538 00:57:13.065881 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8539 00:57:13.068751 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8540 00:57:13.072587 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8541 00:57:13.078561 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8542 00:57:13.082105 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8543 00:57:13.082211 ==
8544 00:57:13.085136 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 00:57:13.088987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 00:57:13.089117 ==
8547 00:57:13.091796 DQS Delay:
8548 00:57:13.091882 DQS0 = 0, DQS1 = 0
8549 00:57:13.091969 DQM Delay:
8550 00:57:13.095246 DQM0 = 138, DQM1 = 130
8551 00:57:13.095354 DQ Delay:
8552 00:57:13.098224 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8553 00:57:13.101701 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8554 00:57:13.108155 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8555 00:57:13.111895 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8556 00:57:13.111980
8557 00:57:13.112064
8558 00:57:13.112144 ==
8559 00:57:13.115439 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 00:57:13.118619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 00:57:13.118704 ==
8562 00:57:13.118789
8563 00:57:13.118869
8564 00:57:13.121290 TX Vref Scan disable
8565 00:57:13.125046 == TX Byte 0 ==
8566 00:57:13.128797 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8567 00:57:13.131494 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8568 00:57:13.135203 == TX Byte 1 ==
8569 00:57:13.138195 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8570 00:57:13.141708 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8571 00:57:13.141795 ==
8572 00:57:13.144901 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 00:57:13.147831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 00:57:13.151468 ==
8575 00:57:13.162640
8576 00:57:13.165633 TX Vref early break, caculate TX vref
8577 00:57:13.169119 TX Vref=16, minBit 0, minWin=22, winSum=375
8578 00:57:13.172149 TX Vref=18, minBit 0, minWin=23, winSum=385
8579 00:57:13.175214 TX Vref=20, minBit 5, minWin=23, winSum=398
8580 00:57:13.179203 TX Vref=22, minBit 0, minWin=24, winSum=407
8581 00:57:13.182661 TX Vref=24, minBit 0, minWin=25, winSum=415
8582 00:57:13.188893 TX Vref=26, minBit 0, minWin=25, winSum=423
8583 00:57:13.192053 TX Vref=28, minBit 13, minWin=25, winSum=421
8584 00:57:13.195644 TX Vref=30, minBit 1, minWin=25, winSum=417
8585 00:57:13.198155 TX Vref=32, minBit 0, minWin=24, winSum=409
8586 00:57:13.201984 TX Vref=34, minBit 5, minWin=23, winSum=397
8587 00:57:13.208519 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8588 00:57:13.208604
8589 00:57:13.212446 Final TX Range 0 Vref 26
8590 00:57:13.212530
8591 00:57:13.212615 ==
8592 00:57:13.214824 Dram Type= 6, Freq= 0, CH_1, rank 0
8593 00:57:13.218557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8594 00:57:13.218642 ==
8595 00:57:13.218727
8596 00:57:13.218807
8597 00:57:13.221304 TX Vref Scan disable
8598 00:57:13.228232 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8599 00:57:13.228317 == TX Byte 0 ==
8600 00:57:13.231385 u2DelayCellOfst[0]=18 cells (5 PI)
8601 00:57:13.234533 u2DelayCellOfst[1]=15 cells (4 PI)
8602 00:57:13.238110 u2DelayCellOfst[2]=0 cells (0 PI)
8603 00:57:13.240906 u2DelayCellOfst[3]=3 cells (1 PI)
8604 00:57:13.244539 u2DelayCellOfst[4]=7 cells (2 PI)
8605 00:57:13.247556 u2DelayCellOfst[5]=22 cells (6 PI)
8606 00:57:13.251097 u2DelayCellOfst[6]=18 cells (5 PI)
8607 00:57:13.254236 u2DelayCellOfst[7]=7 cells (2 PI)
8608 00:57:13.257709 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8609 00:57:13.261342 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8610 00:57:13.264670 == TX Byte 1 ==
8611 00:57:13.267808 u2DelayCellOfst[8]=0 cells (0 PI)
8612 00:57:13.271160 u2DelayCellOfst[9]=3 cells (1 PI)
8613 00:57:13.271244 u2DelayCellOfst[10]=11 cells (3 PI)
8614 00:57:13.274595 u2DelayCellOfst[11]=3 cells (1 PI)
8615 00:57:13.277413 u2DelayCellOfst[12]=15 cells (4 PI)
8616 00:57:13.281180 u2DelayCellOfst[13]=15 cells (4 PI)
8617 00:57:13.284243 u2DelayCellOfst[14]=18 cells (5 PI)
8618 00:57:13.287629 u2DelayCellOfst[15]=18 cells (5 PI)
8619 00:57:13.294362 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8620 00:57:13.297289 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8621 00:57:13.297373 DramC Write-DBI on
8622 00:57:13.297458 ==
8623 00:57:13.300706 Dram Type= 6, Freq= 0, CH_1, rank 0
8624 00:57:13.307476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8625 00:57:13.307558 ==
8626 00:57:13.307622
8627 00:57:13.307723
8628 00:57:13.310536 TX Vref Scan disable
8629 00:57:13.310617 == TX Byte 0 ==
8630 00:57:13.317365 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8631 00:57:13.317447 == TX Byte 1 ==
8632 00:57:13.320569 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8633 00:57:13.323623 DramC Write-DBI off
8634 00:57:13.323759
8635 00:57:13.323825 [DATLAT]
8636 00:57:13.327303 Freq=1600, CH1 RK0
8637 00:57:13.327384
8638 00:57:13.327448 DATLAT Default: 0xf
8639 00:57:13.330027 0, 0xFFFF, sum = 0
8640 00:57:13.330110 1, 0xFFFF, sum = 0
8641 00:57:13.333553 2, 0xFFFF, sum = 0
8642 00:57:13.333635 3, 0xFFFF, sum = 0
8643 00:57:13.336779 4, 0xFFFF, sum = 0
8644 00:57:13.336862 5, 0xFFFF, sum = 0
8645 00:57:13.340305 6, 0xFFFF, sum = 0
8646 00:57:13.340388 7, 0xFFFF, sum = 0
8647 00:57:13.344034 8, 0xFFFF, sum = 0
8648 00:57:13.346758 9, 0xFFFF, sum = 0
8649 00:57:13.346840 10, 0xFFFF, sum = 0
8650 00:57:13.349935 11, 0xFFFF, sum = 0
8651 00:57:13.350018 12, 0xFFFF, sum = 0
8652 00:57:13.353178 13, 0xFFFF, sum = 0
8653 00:57:13.353261 14, 0x0, sum = 1
8654 00:57:13.356738 15, 0x0, sum = 2
8655 00:57:13.356820 16, 0x0, sum = 3
8656 00:57:13.359651 17, 0x0, sum = 4
8657 00:57:13.359744 best_step = 15
8658 00:57:13.359809
8659 00:57:13.359869 ==
8660 00:57:13.363209 Dram Type= 6, Freq= 0, CH_1, rank 0
8661 00:57:13.366234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8662 00:57:13.369893 ==
8663 00:57:13.369974 RX Vref Scan: 1
8664 00:57:13.370039
8665 00:57:13.372888 Set Vref Range= 24 -> 127
8666 00:57:13.372969
8667 00:57:13.376694 RX Vref 24 -> 127, step: 1
8668 00:57:13.376775
8669 00:57:13.376839 RX Delay 11 -> 252, step: 4
8670 00:57:13.376899
8671 00:57:13.379604 Set Vref, RX VrefLevel [Byte0]: 24
8672 00:57:13.382779 [Byte1]: 24
8673 00:57:13.386733
8674 00:57:13.386813 Set Vref, RX VrefLevel [Byte0]: 25
8675 00:57:13.389866 [Byte1]: 25
8676 00:57:13.394198
8677 00:57:13.394281 Set Vref, RX VrefLevel [Byte0]: 26
8678 00:57:13.397581 [Byte1]: 26
8679 00:57:13.402164
8680 00:57:13.402245 Set Vref, RX VrefLevel [Byte0]: 27
8681 00:57:13.405257 [Byte1]: 27
8682 00:57:13.409459
8683 00:57:13.409539 Set Vref, RX VrefLevel [Byte0]: 28
8684 00:57:13.412524 [Byte1]: 28
8685 00:57:13.417291
8686 00:57:13.417371 Set Vref, RX VrefLevel [Byte0]: 29
8687 00:57:13.420262 [Byte1]: 29
8688 00:57:13.424857
8689 00:57:13.424941 Set Vref, RX VrefLevel [Byte0]: 30
8690 00:57:13.427912 [Byte1]: 30
8691 00:57:13.432093
8692 00:57:13.432177 Set Vref, RX VrefLevel [Byte0]: 31
8693 00:57:13.435820 [Byte1]: 31
8694 00:57:13.439623
8695 00:57:13.443183 Set Vref, RX VrefLevel [Byte0]: 32
8696 00:57:13.446145 [Byte1]: 32
8697 00:57:13.446229
8698 00:57:13.449954 Set Vref, RX VrefLevel [Byte0]: 33
8699 00:57:13.452792 [Byte1]: 33
8700 00:57:13.452876
8701 00:57:13.456619 Set Vref, RX VrefLevel [Byte0]: 34
8702 00:57:13.459990 [Byte1]: 34
8703 00:57:13.462878
8704 00:57:13.462961 Set Vref, RX VrefLevel [Byte0]: 35
8705 00:57:13.465862 [Byte1]: 35
8706 00:57:13.470444
8707 00:57:13.470528 Set Vref, RX VrefLevel [Byte0]: 36
8708 00:57:13.473489 [Byte1]: 36
8709 00:57:13.477856
8710 00:57:13.477939 Set Vref, RX VrefLevel [Byte0]: 37
8711 00:57:13.481242 [Byte1]: 37
8712 00:57:13.485888
8713 00:57:13.485971 Set Vref, RX VrefLevel [Byte0]: 38
8714 00:57:13.488935 [Byte1]: 38
8715 00:57:13.493161
8716 00:57:13.493245 Set Vref, RX VrefLevel [Byte0]: 39
8717 00:57:13.496523 [Byte1]: 39
8718 00:57:13.500900
8719 00:57:13.500982 Set Vref, RX VrefLevel [Byte0]: 40
8720 00:57:13.504184 [Byte1]: 40
8721 00:57:13.508515
8722 00:57:13.508598 Set Vref, RX VrefLevel [Byte0]: 41
8723 00:57:13.511822 [Byte1]: 41
8724 00:57:13.516159
8725 00:57:13.516242 Set Vref, RX VrefLevel [Byte0]: 42
8726 00:57:13.519198 [Byte1]: 42
8727 00:57:13.523858
8728 00:57:13.523966 Set Vref, RX VrefLevel [Byte0]: 43
8729 00:57:13.526673 [Byte1]: 43
8730 00:57:13.531124
8731 00:57:13.531208 Set Vref, RX VrefLevel [Byte0]: 44
8732 00:57:13.534590 [Byte1]: 44
8733 00:57:13.539014
8734 00:57:13.539097 Set Vref, RX VrefLevel [Byte0]: 45
8735 00:57:13.542318 [Byte1]: 45
8736 00:57:13.546698
8737 00:57:13.546781 Set Vref, RX VrefLevel [Byte0]: 46
8738 00:57:13.549951 [Byte1]: 46
8739 00:57:13.554101
8740 00:57:13.554208 Set Vref, RX VrefLevel [Byte0]: 47
8741 00:57:13.557329 [Byte1]: 47
8742 00:57:13.561663
8743 00:57:13.561751 Set Vref, RX VrefLevel [Byte0]: 48
8744 00:57:13.565039 [Byte1]: 48
8745 00:57:13.569357
8746 00:57:13.569440 Set Vref, RX VrefLevel [Byte0]: 49
8747 00:57:13.572777 [Byte1]: 49
8748 00:57:13.577099
8749 00:57:13.577183 Set Vref, RX VrefLevel [Byte0]: 50
8750 00:57:13.580547 [Byte1]: 50
8751 00:57:13.584556
8752 00:57:13.584640 Set Vref, RX VrefLevel [Byte0]: 51
8753 00:57:13.588125 [Byte1]: 51
8754 00:57:13.591949
8755 00:57:13.592033 Set Vref, RX VrefLevel [Byte0]: 52
8756 00:57:13.595801 [Byte1]: 52
8757 00:57:13.600351
8758 00:57:13.600435 Set Vref, RX VrefLevel [Byte0]: 53
8759 00:57:13.603304 [Byte1]: 53
8760 00:57:13.607267
8761 00:57:13.607351 Set Vref, RX VrefLevel [Byte0]: 54
8762 00:57:13.610564 [Byte1]: 54
8763 00:57:13.614884
8764 00:57:13.614967 Set Vref, RX VrefLevel [Byte0]: 55
8765 00:57:13.617955 [Byte1]: 55
8766 00:57:13.622557
8767 00:57:13.622641 Set Vref, RX VrefLevel [Byte0]: 56
8768 00:57:13.625608 [Byte1]: 56
8769 00:57:13.630250
8770 00:57:13.630334 Set Vref, RX VrefLevel [Byte0]: 57
8771 00:57:13.633538 [Byte1]: 57
8772 00:57:13.637958
8773 00:57:13.638041 Set Vref, RX VrefLevel [Byte0]: 58
8774 00:57:13.641087 [Byte1]: 58
8775 00:57:13.645405
8776 00:57:13.645488 Set Vref, RX VrefLevel [Byte0]: 59
8777 00:57:13.648811 [Byte1]: 59
8778 00:57:13.653010
8779 00:57:13.653092 Set Vref, RX VrefLevel [Byte0]: 60
8780 00:57:13.656675 [Byte1]: 60
8781 00:57:13.660617
8782 00:57:13.660700 Set Vref, RX VrefLevel [Byte0]: 61
8783 00:57:13.664079 [Byte1]: 61
8784 00:57:13.668278
8785 00:57:13.668359 Set Vref, RX VrefLevel [Byte0]: 62
8786 00:57:13.671980 [Byte1]: 62
8787 00:57:13.675892
8788 00:57:13.675973 Set Vref, RX VrefLevel [Byte0]: 63
8789 00:57:13.679372 [Byte1]: 63
8790 00:57:13.683407
8791 00:57:13.683488 Set Vref, RX VrefLevel [Byte0]: 64
8792 00:57:13.686898 [Byte1]: 64
8793 00:57:13.690867
8794 00:57:13.690948 Set Vref, RX VrefLevel [Byte0]: 65
8795 00:57:13.694777 [Byte1]: 65
8796 00:57:13.698684
8797 00:57:13.698765 Set Vref, RX VrefLevel [Byte0]: 66
8798 00:57:13.701970 [Byte1]: 66
8799 00:57:13.706157
8800 00:57:13.706238 Set Vref, RX VrefLevel [Byte0]: 67
8801 00:57:13.709695 [Byte1]: 67
8802 00:57:13.714127
8803 00:57:13.714208 Set Vref, RX VrefLevel [Byte0]: 68
8804 00:57:13.717251 [Byte1]: 68
8805 00:57:13.722572
8806 00:57:13.722656 Set Vref, RX VrefLevel [Byte0]: 69
8807 00:57:13.725373 [Byte1]: 69
8808 00:57:13.728856
8809 00:57:13.728937 Set Vref, RX VrefLevel [Byte0]: 70
8810 00:57:13.732725 [Byte1]: 70
8811 00:57:13.737176
8812 00:57:13.737256 Set Vref, RX VrefLevel [Byte0]: 71
8813 00:57:13.740159 [Byte1]: 71
8814 00:57:13.744821
8815 00:57:13.744902 Final RX Vref Byte 0 = 52 to rank0
8816 00:57:13.748163 Final RX Vref Byte 1 = 57 to rank0
8817 00:57:13.750935 Final RX Vref Byte 0 = 52 to rank1
8818 00:57:13.754018 Final RX Vref Byte 1 = 57 to rank1==
8819 00:57:13.757492 Dram Type= 6, Freq= 0, CH_1, rank 0
8820 00:57:13.764484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 00:57:13.764569 ==
8822 00:57:13.764655 DQS Delay:
8823 00:57:13.767589 DQS0 = 0, DQS1 = 0
8824 00:57:13.767706 DQM Delay:
8825 00:57:13.767793 DQM0 = 134, DQM1 = 129
8826 00:57:13.770709 DQ Delay:
8827 00:57:13.774160 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8828 00:57:13.777931 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8829 00:57:13.780470 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =118
8830 00:57:13.783887 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8831 00:57:13.783971
8832 00:57:13.784056
8833 00:57:13.784138
8834 00:57:13.786892 [DramC_TX_OE_Calibration] TA2
8835 00:57:13.790434 Original DQ_B0 (3 6) =30, OEN = 27
8836 00:57:13.793936 Original DQ_B1 (3 6) =30, OEN = 27
8837 00:57:13.797244 24, 0x0, End_B0=24 End_B1=24
8838 00:57:13.800453 25, 0x0, End_B0=25 End_B1=25
8839 00:57:13.800532 26, 0x0, End_B0=26 End_B1=26
8840 00:57:13.803962 27, 0x0, End_B0=27 End_B1=27
8841 00:57:13.806956 28, 0x0, End_B0=28 End_B1=28
8842 00:57:13.810197 29, 0x0, End_B0=29 End_B1=29
8843 00:57:13.810283 30, 0x0, End_B0=30 End_B1=30
8844 00:57:13.813490 31, 0x4141, End_B0=30 End_B1=30
8845 00:57:13.816587 Byte0 end_step=30 best_step=27
8846 00:57:13.819723 Byte1 end_step=30 best_step=27
8847 00:57:13.823162 Byte0 TX OE(2T, 0.5T) = (3, 3)
8848 00:57:13.826512 Byte1 TX OE(2T, 0.5T) = (3, 3)
8849 00:57:13.826597
8850 00:57:13.826682
8851 00:57:13.833222 [DQSOSCAuto] RK0, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8852 00:57:13.837035 CH1 RK0: MR19=303, MR18=180D
8853 00:57:13.843023 CH1_RK0: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8854 00:57:13.843107
8855 00:57:13.846156 ----->DramcWriteLeveling(PI) begin...
8856 00:57:13.846241 ==
8857 00:57:13.849868 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 00:57:13.853260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 00:57:13.853345 ==
8860 00:57:13.856429 Write leveling (Byte 0): 25 => 25
8861 00:57:13.859452 Write leveling (Byte 1): 27 => 27
8862 00:57:13.862700 DramcWriteLeveling(PI) end<-----
8863 00:57:13.862787
8864 00:57:13.862873 ==
8865 00:57:13.866367 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 00:57:13.872732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 00:57:13.872816 ==
8868 00:57:13.872903 [Gating] SW mode calibration
8869 00:57:13.882456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8870 00:57:13.886108 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8871 00:57:13.893016 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 00:57:13.896265 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 00:57:13.899114 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8874 00:57:13.902596 1 4 12 | B1->B0 | 3434 2625 | 1 1 | (1 1) (1 0)
8875 00:57:13.909493 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8876 00:57:13.912854 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8877 00:57:13.915949 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8878 00:57:13.922331 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8879 00:57:13.925876 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8880 00:57:13.928909 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8881 00:57:13.935415 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8882 00:57:13.939091 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8883 00:57:13.942132 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8884 00:57:13.949149 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8885 00:57:13.951946 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 00:57:13.955521 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 00:57:13.962095 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8888 00:57:13.965333 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 00:57:13.968147 1 6 8 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
8890 00:57:13.975210 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8891 00:57:13.978390 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 00:57:13.984558 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8893 00:57:13.988341 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8894 00:57:13.991244 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8895 00:57:13.997696 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8896 00:57:14.001307 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 00:57:14.004809 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 00:57:14.008261 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8899 00:57:14.015006 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8900 00:57:14.017748 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 00:57:14.021454 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 00:57:14.027869 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 00:57:14.031176 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 00:57:14.037399 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 00:57:14.040960 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 00:57:14.044361 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 00:57:14.050645 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 00:57:14.054501 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 00:57:14.057035 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 00:57:14.063752 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 00:57:14.067019 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 00:57:14.070666 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 00:57:14.077242 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8914 00:57:14.080553 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8915 00:57:14.083611 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8916 00:57:14.087042 Total UI for P1: 0, mck2ui 16
8917 00:57:14.090232 best dqsien dly found for B0: ( 1, 9, 10)
8918 00:57:14.093607 Total UI for P1: 0, mck2ui 16
8919 00:57:14.097202 best dqsien dly found for B1: ( 1, 9, 10)
8920 00:57:14.100652 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8921 00:57:14.103331 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8922 00:57:14.103414
8923 00:57:14.106934 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8924 00:57:14.113378 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8925 00:57:14.113463 [Gating] SW calibration Done
8926 00:57:14.117037 ==
8927 00:57:14.119699 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 00:57:14.123435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 00:57:14.123520 ==
8930 00:57:14.123621 RX Vref Scan: 0
8931 00:57:14.123767
8932 00:57:14.126264 RX Vref 0 -> 0, step: 1
8933 00:57:14.126348
8934 00:57:14.130066 RX Delay 0 -> 252, step: 8
8935 00:57:14.132913 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8936 00:57:14.136426 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8937 00:57:14.140151 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8938 00:57:14.146561 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8939 00:57:14.150453 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8940 00:57:14.152843 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8941 00:57:14.156238 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8942 00:57:14.160008 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8943 00:57:14.165973 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8944 00:57:14.169606 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8945 00:57:14.172618 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8946 00:57:14.175824 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8947 00:57:14.183020 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8948 00:57:14.185795 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8949 00:57:14.188835 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8950 00:57:14.192881 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8951 00:57:14.193028 ==
8952 00:57:14.196253 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 00:57:14.202506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 00:57:14.202589 ==
8955 00:57:14.202655 DQS Delay:
8956 00:57:14.202714 DQS0 = 0, DQS1 = 0
8957 00:57:14.205871 DQM Delay:
8958 00:57:14.205952 DQM0 = 136, DQM1 = 129
8959 00:57:14.209079 DQ Delay:
8960 00:57:14.212427 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8961 00:57:14.215421 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8962 00:57:14.219057 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8963 00:57:14.221934 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8964 00:57:14.222016
8965 00:57:14.222080
8966 00:57:14.222138 ==
8967 00:57:14.225617 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 00:57:14.228538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 00:57:14.233142 ==
8970 00:57:14.233223
8971 00:57:14.233287
8972 00:57:14.233359 TX Vref Scan disable
8973 00:57:14.235336 == TX Byte 0 ==
8974 00:57:14.238784 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8975 00:57:14.242794 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8976 00:57:14.245101 == TX Byte 1 ==
8977 00:57:14.248871 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8978 00:57:14.251642 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8979 00:57:14.255041 ==
8980 00:57:14.258264 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 00:57:14.261606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 00:57:14.261688 ==
8983 00:57:14.274514
8984 00:57:14.277865 TX Vref early break, caculate TX vref
8985 00:57:14.280656 TX Vref=16, minBit 1, minWin=23, winSum=390
8986 00:57:14.284139 TX Vref=18, minBit 0, minWin=24, winSum=397
8987 00:57:14.287168 TX Vref=20, minBit 0, minWin=24, winSum=405
8988 00:57:14.290735 TX Vref=22, minBit 0, minWin=25, winSum=414
8989 00:57:14.293915 TX Vref=24, minBit 9, minWin=25, winSum=421
8990 00:57:14.300800 TX Vref=26, minBit 0, minWin=25, winSum=425
8991 00:57:14.303717 TX Vref=28, minBit 0, minWin=26, winSum=426
8992 00:57:14.306878 TX Vref=30, minBit 0, minWin=25, winSum=420
8993 00:57:14.310283 TX Vref=32, minBit 9, minWin=24, winSum=413
8994 00:57:14.313240 TX Vref=34, minBit 0, minWin=24, winSum=400
8995 00:57:14.320141 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8996 00:57:14.320221
8997 00:57:14.323266 Final TX Range 0 Vref 28
8998 00:57:14.323341
8999 00:57:14.323402 ==
9000 00:57:14.326736 Dram Type= 6, Freq= 0, CH_1, rank 1
9001 00:57:14.329771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9002 00:57:14.329846 ==
9003 00:57:14.329908
9004 00:57:14.329966
9005 00:57:14.333116 TX Vref Scan disable
9006 00:57:14.339576 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
9007 00:57:14.339658 == TX Byte 0 ==
9008 00:57:14.343167 u2DelayCellOfst[0]=18 cells (5 PI)
9009 00:57:14.347050 u2DelayCellOfst[1]=15 cells (4 PI)
9010 00:57:14.349911 u2DelayCellOfst[2]=0 cells (0 PI)
9011 00:57:14.352812 u2DelayCellOfst[3]=7 cells (2 PI)
9012 00:57:14.356373 u2DelayCellOfst[4]=11 cells (3 PI)
9013 00:57:14.359521 u2DelayCellOfst[5]=22 cells (6 PI)
9014 00:57:14.363073 u2DelayCellOfst[6]=22 cells (6 PI)
9015 00:57:14.366010 u2DelayCellOfst[7]=7 cells (2 PI)
9016 00:57:14.369119 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9017 00:57:14.372422 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9018 00:57:14.376027 == TX Byte 1 ==
9019 00:57:14.379382 u2DelayCellOfst[8]=0 cells (0 PI)
9020 00:57:14.382355 u2DelayCellOfst[9]=0 cells (0 PI)
9021 00:57:14.385994 u2DelayCellOfst[10]=11 cells (3 PI)
9022 00:57:14.389084 u2DelayCellOfst[11]=3 cells (1 PI)
9023 00:57:14.392081 u2DelayCellOfst[12]=11 cells (3 PI)
9024 00:57:14.392189 u2DelayCellOfst[13]=15 cells (4 PI)
9025 00:57:14.398740 u2DelayCellOfst[14]=18 cells (5 PI)
9026 00:57:14.398848 u2DelayCellOfst[15]=15 cells (4 PI)
9027 00:57:14.405101 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9028 00:57:14.408659 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9029 00:57:14.411961 DramC Write-DBI on
9030 00:57:14.412045 ==
9031 00:57:14.414961 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 00:57:14.418651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 00:57:14.418736 ==
9034 00:57:14.418822
9035 00:57:14.418902
9036 00:57:14.421441 TX Vref Scan disable
9037 00:57:14.421526 == TX Byte 0 ==
9038 00:57:14.428196 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9039 00:57:14.428280 == TX Byte 1 ==
9040 00:57:14.434866 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9041 00:57:14.434951 DramC Write-DBI off
9042 00:57:14.435036
9043 00:57:14.435117 [DATLAT]
9044 00:57:14.438253 Freq=1600, CH1 RK1
9045 00:57:14.438337
9046 00:57:14.441202 DATLAT Default: 0xf
9047 00:57:14.441286 0, 0xFFFF, sum = 0
9048 00:57:14.444918 1, 0xFFFF, sum = 0
9049 00:57:14.445003 2, 0xFFFF, sum = 0
9050 00:57:14.448314 3, 0xFFFF, sum = 0
9051 00:57:14.448399 4, 0xFFFF, sum = 0
9052 00:57:14.451237 5, 0xFFFF, sum = 0
9053 00:57:14.451322 6, 0xFFFF, sum = 0
9054 00:57:14.454816 7, 0xFFFF, sum = 0
9055 00:57:14.454901 8, 0xFFFF, sum = 0
9056 00:57:14.458132 9, 0xFFFF, sum = 0
9057 00:57:14.458217 10, 0xFFFF, sum = 0
9058 00:57:14.461437 11, 0xFFFF, sum = 0
9059 00:57:14.461521 12, 0xFFFF, sum = 0
9060 00:57:14.464714 13, 0xFFFF, sum = 0
9061 00:57:14.464799 14, 0x0, sum = 1
9062 00:57:14.468235 15, 0x0, sum = 2
9063 00:57:14.468321 16, 0x0, sum = 3
9064 00:57:14.471017 17, 0x0, sum = 4
9065 00:57:14.471102 best_step = 15
9066 00:57:14.471188
9067 00:57:14.471269 ==
9068 00:57:14.474430 Dram Type= 6, Freq= 0, CH_1, rank 1
9069 00:57:14.481462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9070 00:57:14.481546 ==
9071 00:57:14.481631 RX Vref Scan: 0
9072 00:57:14.481713
9073 00:57:14.484369 RX Vref 0 -> 0, step: 1
9074 00:57:14.484453
9075 00:57:14.487511 RX Delay 11 -> 252, step: 4
9076 00:57:14.490619 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9077 00:57:14.493902 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9078 00:57:14.500833 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9079 00:57:14.504055 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9080 00:57:14.507307 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9081 00:57:14.510292 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9082 00:57:14.513748 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9083 00:57:14.520456 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9084 00:57:14.523546 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9085 00:57:14.526893 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9086 00:57:14.530365 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9087 00:57:14.533476 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9088 00:57:14.540102 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9089 00:57:14.543474 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9090 00:57:14.547317 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9091 00:57:14.550193 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9092 00:57:14.550274 ==
9093 00:57:14.553224 Dram Type= 6, Freq= 0, CH_1, rank 1
9094 00:57:14.560294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9095 00:57:14.560375 ==
9096 00:57:14.560439 DQS Delay:
9097 00:57:14.563361 DQS0 = 0, DQS1 = 0
9098 00:57:14.563441 DQM Delay:
9099 00:57:14.566734 DQM0 = 133, DQM1 = 127
9100 00:57:14.566814 DQ Delay:
9101 00:57:14.569796 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9102 00:57:14.573297 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9103 00:57:14.576328 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =118
9104 00:57:14.579683 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
9105 00:57:14.579764
9106 00:57:14.579827
9107 00:57:14.579886
9108 00:57:14.583206 [DramC_TX_OE_Calibration] TA2
9109 00:57:14.586065 Original DQ_B0 (3 6) =30, OEN = 27
9110 00:57:14.589477 Original DQ_B1 (3 6) =30, OEN = 27
9111 00:57:14.592962 24, 0x0, End_B0=24 End_B1=24
9112 00:57:14.595803 25, 0x0, End_B0=25 End_B1=25
9113 00:57:14.595885 26, 0x0, End_B0=26 End_B1=26
9114 00:57:14.599415 27, 0x0, End_B0=27 End_B1=27
9115 00:57:14.603198 28, 0x0, End_B0=28 End_B1=28
9116 00:57:14.605957 29, 0x0, End_B0=29 End_B1=29
9117 00:57:14.609013 30, 0x0, End_B0=30 End_B1=30
9118 00:57:14.609094 31, 0x4545, End_B0=30 End_B1=30
9119 00:57:14.612674 Byte0 end_step=30 best_step=27
9120 00:57:14.616141 Byte1 end_step=30 best_step=27
9121 00:57:14.619235 Byte0 TX OE(2T, 0.5T) = (3, 3)
9122 00:57:14.622575 Byte1 TX OE(2T, 0.5T) = (3, 3)
9123 00:57:14.622655
9124 00:57:14.622719
9125 00:57:14.629133 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9126 00:57:14.632029 CH1 RK1: MR19=303, MR18=E0B
9127 00:57:14.638652 CH1_RK1: MR19=0x303, MR18=0xE0B, DQSOSC=402, MR23=63, INC=22, DEC=15
9128 00:57:14.642015 [RxdqsGatingPostProcess] freq 1600
9129 00:57:14.648471 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9130 00:57:14.651972 best DQS0 dly(2T, 0.5T) = (1, 1)
9131 00:57:14.652053 best DQS1 dly(2T, 0.5T) = (1, 1)
9132 00:57:14.655549 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9133 00:57:14.659005 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9134 00:57:14.662106 best DQS0 dly(2T, 0.5T) = (1, 1)
9135 00:57:14.664956 best DQS1 dly(2T, 0.5T) = (1, 1)
9136 00:57:14.668427 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9137 00:57:14.671308 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9138 00:57:14.675269 Pre-setting of DQS Precalculation
9139 00:57:14.681864 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9140 00:57:14.688105 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9141 00:57:14.694454 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9142 00:57:14.694534
9143 00:57:14.694598
9144 00:57:14.697662 [Calibration Summary] 3200 Mbps
9145 00:57:14.697741 CH 0, Rank 0
9146 00:57:14.701474 SW Impedance : PASS
9147 00:57:14.704776 DUTY Scan : NO K
9148 00:57:14.704856 ZQ Calibration : PASS
9149 00:57:14.707863 Jitter Meter : NO K
9150 00:57:14.711125 CBT Training : PASS
9151 00:57:14.711208 Write leveling : PASS
9152 00:57:14.714920 RX DQS gating : PASS
9153 00:57:14.717840 RX DQ/DQS(RDDQC) : PASS
9154 00:57:14.717925 TX DQ/DQS : PASS
9155 00:57:14.721262 RX DATLAT : PASS
9156 00:57:14.721346 RX DQ/DQS(Engine): PASS
9157 00:57:14.724375 TX OE : PASS
9158 00:57:14.724486 All Pass.
9159 00:57:14.724572
9160 00:57:14.727808 CH 0, Rank 1
9161 00:57:14.730773 SW Impedance : PASS
9162 00:57:14.730857 DUTY Scan : NO K
9163 00:57:14.734272 ZQ Calibration : PASS
9164 00:57:14.734356 Jitter Meter : NO K
9165 00:57:14.737468 CBT Training : PASS
9166 00:57:14.740664 Write leveling : PASS
9167 00:57:14.740748 RX DQS gating : PASS
9168 00:57:14.744308 RX DQ/DQS(RDDQC) : PASS
9169 00:57:14.748228 TX DQ/DQS : PASS
9170 00:57:14.748313 RX DATLAT : PASS
9171 00:57:14.750658 RX DQ/DQS(Engine): PASS
9172 00:57:14.753608 TX OE : PASS
9173 00:57:14.753718 All Pass.
9174 00:57:14.753804
9175 00:57:14.753885 CH 1, Rank 0
9176 00:57:14.757026 SW Impedance : PASS
9177 00:57:14.761040 DUTY Scan : NO K
9178 00:57:14.761125 ZQ Calibration : PASS
9179 00:57:14.763522 Jitter Meter : NO K
9180 00:57:14.767164 CBT Training : PASS
9181 00:57:14.767249 Write leveling : PASS
9182 00:57:14.770366 RX DQS gating : PASS
9183 00:57:14.773909 RX DQ/DQS(RDDQC) : PASS
9184 00:57:14.773989 TX DQ/DQS : PASS
9185 00:57:14.777385 RX DATLAT : PASS
9186 00:57:14.780837 RX DQ/DQS(Engine): PASS
9187 00:57:14.780926 TX OE : PASS
9188 00:57:14.780992 All Pass.
9189 00:57:14.783382
9190 00:57:14.783462 CH 1, Rank 1
9191 00:57:14.786833 SW Impedance : PASS
9192 00:57:14.786914 DUTY Scan : NO K
9193 00:57:14.790390 ZQ Calibration : PASS
9194 00:57:14.793396 Jitter Meter : NO K
9195 00:57:14.793477 CBT Training : PASS
9196 00:57:14.797231 Write leveling : PASS
9197 00:57:14.797312 RX DQS gating : PASS
9198 00:57:14.800069 RX DQ/DQS(RDDQC) : PASS
9199 00:57:14.803566 TX DQ/DQS : PASS
9200 00:57:14.803646 RX DATLAT : PASS
9201 00:57:14.807195 RX DQ/DQS(Engine): PASS
9202 00:57:14.809828 TX OE : PASS
9203 00:57:14.809909 All Pass.
9204 00:57:14.809973
9205 00:57:14.813414 DramC Write-DBI on
9206 00:57:14.813494 PER_BANK_REFRESH: Hybrid Mode
9207 00:57:14.816481 TX_TRACKING: ON
9208 00:57:14.826458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9209 00:57:14.832886 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9210 00:57:14.840070 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9211 00:57:14.842777 [FAST_K] Save calibration result to emmc
9212 00:57:14.846427 sync common calibartion params.
9213 00:57:14.849338 sync cbt_mode0:1, 1:1
9214 00:57:14.852676 dram_init: ddr_geometry: 2
9215 00:57:14.852760 dram_init: ddr_geometry: 2
9216 00:57:14.856259 dram_init: ddr_geometry: 2
9217 00:57:14.859051 0:dram_rank_size:100000000
9218 00:57:14.859136 1:dram_rank_size:100000000
9219 00:57:14.865733 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9220 00:57:14.869304 DFS_SHUFFLE_HW_MODE: ON
9221 00:57:14.872569 dramc_set_vcore_voltage set vcore to 725000
9222 00:57:14.875627 Read voltage for 1600, 0
9223 00:57:14.875729 Vio18 = 0
9224 00:57:14.875815 Vcore = 725000
9225 00:57:14.879536 Vdram = 0
9226 00:57:14.879619 Vddq = 0
9227 00:57:14.879718 Vmddr = 0
9228 00:57:14.882401 switch to 3200 Mbps bootup
9229 00:57:14.885991 [DramcRunTimeConfig]
9230 00:57:14.886076 PHYPLL
9231 00:57:14.886161 DPM_CONTROL_AFTERK: ON
9232 00:57:14.889108 PER_BANK_REFRESH: ON
9233 00:57:14.892285 REFRESH_OVERHEAD_REDUCTION: ON
9234 00:57:14.892369 CMD_PICG_NEW_MODE: OFF
9235 00:57:14.895617 XRTWTW_NEW_MODE: ON
9236 00:57:14.899011 XRTRTR_NEW_MODE: ON
9237 00:57:14.899095 TX_TRACKING: ON
9238 00:57:14.899181 RDSEL_TRACKING: OFF
9239 00:57:14.902744 DQS Precalculation for DVFS: ON
9240 00:57:14.905657 RX_TRACKING: OFF
9241 00:57:14.905741 HW_GATING DBG: ON
9242 00:57:14.908838 ZQCS_ENABLE_LP4: ON
9243 00:57:14.908921 RX_PICG_NEW_MODE: ON
9244 00:57:14.912880 TX_PICG_NEW_MODE: ON
9245 00:57:14.915814 ENABLE_RX_DCM_DPHY: ON
9246 00:57:14.918728 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9247 00:57:14.918813 DUMMY_READ_FOR_TRACKING: OFF
9248 00:57:14.921996 !!! SPM_CONTROL_AFTERK: OFF
9249 00:57:14.925796 !!! SPM could not control APHY
9250 00:57:14.928877 IMPEDANCE_TRACKING: ON
9251 00:57:14.928961 TEMP_SENSOR: ON
9252 00:57:14.932330 HW_SAVE_FOR_SR: OFF
9253 00:57:14.932413 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9254 00:57:14.938992 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9255 00:57:14.939076 Read ODT Tracking: ON
9256 00:57:14.941989 Refresh Rate DeBounce: ON
9257 00:57:14.942073 DFS_NO_QUEUE_FLUSH: ON
9258 00:57:14.945184 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9259 00:57:14.948585 ENABLE_DFS_RUNTIME_MRW: OFF
9260 00:57:14.952157 DDR_RESERVE_NEW_MODE: ON
9261 00:57:14.952241 MR_CBT_SWITCH_FREQ: ON
9262 00:57:14.954907 =========================
9263 00:57:14.974692 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9264 00:57:14.978620 dram_init: ddr_geometry: 2
9265 00:57:14.996769 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9266 00:57:14.999328 dram_init: dram init end (result: 0)
9267 00:57:15.006098 DRAM-K: Full calibration passed in 24633 msecs
9268 00:57:15.009786 MRC: failed to locate region type 0.
9269 00:57:15.009870 DRAM rank0 size:0x100000000,
9270 00:57:15.013023 DRAM rank1 size=0x100000000
9271 00:57:15.022338 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9272 00:57:15.029297 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9273 00:57:15.035978 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9274 00:57:15.045832 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9275 00:57:15.045913 DRAM rank0 size:0x100000000,
9276 00:57:15.048813 DRAM rank1 size=0x100000000
9277 00:57:15.048894 CBMEM:
9278 00:57:15.052227 IMD: root @ 0xfffff000 254 entries.
9279 00:57:15.055978 IMD: root @ 0xffffec00 62 entries.
9280 00:57:15.059072 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9281 00:57:15.065756 WARNING: RO_VPD is uninitialized or empty.
9282 00:57:15.068880 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9283 00:57:15.076109 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9284 00:57:15.089075 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9285 00:57:15.100193 BS: romstage times (exec / console): total (unknown) / 24122 ms
9286 00:57:15.100274
9287 00:57:15.100338
9288 00:57:15.110455 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9289 00:57:15.114082 ARM64: Exception handlers installed.
9290 00:57:15.116837 ARM64: Testing exception
9291 00:57:15.120178 ARM64: Done test exception
9292 00:57:15.120258 Enumerating buses...
9293 00:57:15.123784 Show all devs... Before device enumeration.
9294 00:57:15.127210 Root Device: enabled 1
9295 00:57:15.130025 CPU_CLUSTER: 0: enabled 1
9296 00:57:15.130106 CPU: 00: enabled 1
9297 00:57:15.133520 Compare with tree...
9298 00:57:15.133600 Root Device: enabled 1
9299 00:57:15.136562 CPU_CLUSTER: 0: enabled 1
9300 00:57:15.140321 CPU: 00: enabled 1
9301 00:57:15.140401 Root Device scanning...
9302 00:57:15.143279 scan_static_bus for Root Device
9303 00:57:15.146973 CPU_CLUSTER: 0 enabled
9304 00:57:15.150050 scan_static_bus for Root Device done
9305 00:57:15.153107 scan_bus: bus Root Device finished in 8 msecs
9306 00:57:15.153188 done
9307 00:57:15.159632 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9308 00:57:15.162700 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9309 00:57:15.169836 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9310 00:57:15.172961 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9311 00:57:15.176496 Allocating resources...
9312 00:57:15.179600 Reading resources...
9313 00:57:15.183078 Root Device read_resources bus 0 link: 0
9314 00:57:15.185972 DRAM rank0 size:0x100000000,
9315 00:57:15.186050 DRAM rank1 size=0x100000000
9316 00:57:15.192981 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9317 00:57:15.193065 CPU: 00 missing read_resources
9318 00:57:15.199211 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9319 00:57:15.202908 Root Device read_resources bus 0 link: 0 done
9320 00:57:15.206166 Done reading resources.
9321 00:57:15.209319 Show resources in subtree (Root Device)...After reading.
9322 00:57:15.212300 Root Device child on link 0 CPU_CLUSTER: 0
9323 00:57:15.215940 CPU_CLUSTER: 0 child on link 0 CPU: 00
9324 00:57:15.225458 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9325 00:57:15.225617 CPU: 00
9326 00:57:15.232569 Root Device assign_resources, bus 0 link: 0
9327 00:57:15.236032 CPU_CLUSTER: 0 missing set_resources
9328 00:57:15.238889 Root Device assign_resources, bus 0 link: 0 done
9329 00:57:15.239138 Done setting resources.
9330 00:57:15.246096 Show resources in subtree (Root Device)...After assigning values.
9331 00:57:15.248966 Root Device child on link 0 CPU_CLUSTER: 0
9332 00:57:15.252459 CPU_CLUSTER: 0 child on link 0 CPU: 00
9333 00:57:15.262217 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9334 00:57:15.262904 CPU: 00
9335 00:57:15.265285 Done allocating resources.
9336 00:57:15.272050 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9337 00:57:15.272778 Enabling resources...
9338 00:57:15.275720 done.
9339 00:57:15.278986 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9340 00:57:15.282180 Initializing devices...
9341 00:57:15.282753 Root Device init
9342 00:57:15.285383 init hardware done!
9343 00:57:15.286072 0x00000018: ctrlr->caps
9344 00:57:15.288693 52.000 MHz: ctrlr->f_max
9345 00:57:15.291996 0.400 MHz: ctrlr->f_min
9346 00:57:15.292305 0x40ff8080: ctrlr->voltages
9347 00:57:15.294863 sclk: 390625
9348 00:57:15.295089 Bus Width = 1
9349 00:57:15.298543 sclk: 390625
9350 00:57:15.298770 Bus Width = 1
9351 00:57:15.301993 Early init status = 3
9352 00:57:15.304621 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9353 00:57:15.309154 in-header: 03 fc 00 00 01 00 00 00
9354 00:57:15.312065 in-data: 00
9355 00:57:15.314972 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9356 00:57:15.319693 in-header: 03 fd 00 00 00 00 00 00
9357 00:57:15.322645 in-data:
9358 00:57:15.325946 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9359 00:57:15.329907 in-header: 03 fc 00 00 01 00 00 00
9360 00:57:15.333416 in-data: 00
9361 00:57:15.336672 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9362 00:57:15.342179 in-header: 03 fd 00 00 00 00 00 00
9363 00:57:15.345845 in-data:
9364 00:57:15.348577 [SSUSB] Setting up USB HOST controller...
9365 00:57:15.351810 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9366 00:57:15.355110 [SSUSB] phy power-on done.
9367 00:57:15.359394 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9368 00:57:15.365575 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9369 00:57:15.369229 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9370 00:57:15.375281 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9371 00:57:15.382199 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9372 00:57:15.388968 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9373 00:57:15.395610 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9374 00:57:15.401739 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9375 00:57:15.405026 SPM: binary array size = 0x9dc
9376 00:57:15.408432 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9377 00:57:15.415377 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9378 00:57:15.421962 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9379 00:57:15.428084 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9380 00:57:15.431743 configure_display: Starting display init
9381 00:57:15.465478 anx7625_power_on_init: Init interface.
9382 00:57:15.469108 anx7625_disable_pd_protocol: Disabled PD feature.
9383 00:57:15.472367 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9384 00:57:15.500316 anx7625_start_dp_work: Secure OCM version=00
9385 00:57:15.503784 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9386 00:57:15.520996 sp_tx_get_edid_block: EDID Block = 1
9387 00:57:15.621061 Extracted contents:
9388 00:57:15.624599 header: 00 ff ff ff ff ff ff 00
9389 00:57:15.627415 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9390 00:57:15.630914 version: 01 04
9391 00:57:15.633987 basic params: 95 1f 11 78 0a
9392 00:57:15.636925 chroma info: 76 90 94 55 54 90 27 21 50 54
9393 00:57:15.640438 established: 00 00 00
9394 00:57:15.647529 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9395 00:57:15.653511 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9396 00:57:15.657324 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 00:57:15.663271 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9398 00:57:15.669786 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9399 00:57:15.673154 extensions: 00
9400 00:57:15.673615 checksum: fb
9401 00:57:15.673980
9402 00:57:15.680493 Manufacturer: IVO Model 57d Serial Number 0
9403 00:57:15.681045 Made week 0 of 2020
9404 00:57:15.683734 EDID version: 1.4
9405 00:57:15.684195 Digital display
9406 00:57:15.686831 6 bits per primary color channel
9407 00:57:15.687389 DisplayPort interface
9408 00:57:15.689959 Maximum image size: 31 cm x 17 cm
9409 00:57:15.693326 Gamma: 220%
9410 00:57:15.693881 Check DPMS levels
9411 00:57:15.699780 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9412 00:57:15.703057 First detailed timing is preferred timing
9413 00:57:15.703523 Established timings supported:
9414 00:57:15.706558 Standard timings supported:
9415 00:57:15.710429 Detailed timings
9416 00:57:15.713250 Hex of detail: 383680a07038204018303c0035ae10000019
9417 00:57:15.720352 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9418 00:57:15.723281 0780 0798 07c8 0820 hborder 0
9419 00:57:15.726086 0438 043b 0447 0458 vborder 0
9420 00:57:15.729787 -hsync -vsync
9421 00:57:15.730339 Did detailed timing
9422 00:57:15.736215 Hex of detail: 000000000000000000000000000000000000
9423 00:57:15.739326 Manufacturer-specified data, tag 0
9424 00:57:15.742455 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9425 00:57:15.745904 ASCII string: InfoVision
9426 00:57:15.749790 Hex of detail: 000000fe00523134304e574635205248200a
9427 00:57:15.752686 ASCII string: R140NWF5 RH
9428 00:57:15.753149 Checksum
9429 00:57:15.756401 Checksum: 0xfb (valid)
9430 00:57:15.759445 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9431 00:57:15.762655 DSI data_rate: 832800000 bps
9432 00:57:15.769134 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9433 00:57:15.772754 anx7625_parse_edid: pixelclock(138800).
9434 00:57:15.776316 hactive(1920), hsync(48), hfp(24), hbp(88)
9435 00:57:15.779065 vactive(1080), vsync(12), vfp(3), vbp(17)
9436 00:57:15.782482 anx7625_dsi_config: config dsi.
9437 00:57:15.788379 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9438 00:57:15.802879 anx7625_dsi_config: success to config DSI
9439 00:57:15.806254 anx7625_dp_start: MIPI phy setup OK.
9440 00:57:15.809934 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9441 00:57:15.812908 mtk_ddp_mode_set invalid vrefresh 60
9442 00:57:15.815722 main_disp_path_setup
9443 00:57:15.816352 ovl_layer_smi_id_en
9444 00:57:15.819260 ovl_layer_smi_id_en
9445 00:57:15.819747 ccorr_config
9446 00:57:15.820114 aal_config
9447 00:57:15.822234 gamma_config
9448 00:57:15.822682 postmask_config
9449 00:57:15.825764 dither_config
9450 00:57:15.828900 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9451 00:57:15.835625 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9452 00:57:15.838757 Root Device init finished in 553 msecs
9453 00:57:15.841866 CPU_CLUSTER: 0 init
9454 00:57:15.848677 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9455 00:57:15.855517 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9456 00:57:15.856280 APU_MBOX 0x190000b0 = 0x10001
9457 00:57:15.858944 APU_MBOX 0x190001b0 = 0x10001
9458 00:57:15.862003 APU_MBOX 0x190005b0 = 0x10001
9459 00:57:15.865516 APU_MBOX 0x190006b0 = 0x10001
9460 00:57:15.872331 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9461 00:57:15.881605 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9462 00:57:15.894701 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9463 00:57:15.901181 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9464 00:57:15.912402 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9465 00:57:15.921405 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9466 00:57:15.925031 CPU_CLUSTER: 0 init finished in 81 msecs
9467 00:57:15.927966 Devices initialized
9468 00:57:15.931734 Show all devs... After init.
9469 00:57:15.932193 Root Device: enabled 1
9470 00:57:15.934737 CPU_CLUSTER: 0: enabled 1
9471 00:57:15.937979 CPU: 00: enabled 1
9472 00:57:15.941276 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9473 00:57:15.944988 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9474 00:57:15.947987 ELOG: NV offset 0x57f000 size 0x1000
9475 00:57:15.954749 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9476 00:57:15.961389 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9477 00:57:15.964709 ELOG: Event(17) added with size 13 at 2024-01-19 00:57:17 UTC
9478 00:57:15.971144 out: cmd=0x121: 03 db 21 01 00 00 00 00
9479 00:57:15.974554 in-header: 03 c2 00 00 2c 00 00 00
9480 00:57:15.984391 in-data: 9d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9481 00:57:15.991178 ELOG: Event(A1) added with size 10 at 2024-01-19 00:57:17 UTC
9482 00:57:15.997833 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9483 00:57:16.004506 ELOG: Event(A0) added with size 9 at 2024-01-19 00:57:17 UTC
9484 00:57:16.007378 elog_add_boot_reason: Logged dev mode boot
9485 00:57:16.014443 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9486 00:57:16.014999 Finalize devices...
9487 00:57:16.017774 Devices finalized
9488 00:57:16.020540 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9489 00:57:16.023956 Writing coreboot table at 0xffe64000
9490 00:57:16.027348 0. 000000000010a000-0000000000113fff: RAMSTAGE
9491 00:57:16.033705 1. 0000000040000000-00000000400fffff: RAM
9492 00:57:16.036950 2. 0000000040100000-000000004032afff: RAMSTAGE
9493 00:57:16.040441 3. 000000004032b000-00000000545fffff: RAM
9494 00:57:16.043582 4. 0000000054600000-000000005465ffff: BL31
9495 00:57:16.047188 5. 0000000054660000-00000000ffe63fff: RAM
9496 00:57:16.054117 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9497 00:57:16.056738 7. 0000000100000000-000000023fffffff: RAM
9498 00:57:16.060742 Passing 5 GPIOs to payload:
9499 00:57:16.064218 NAME | PORT | POLARITY | VALUE
9500 00:57:16.069996 EC in RW | 0x000000aa | low | undefined
9501 00:57:16.073200 EC interrupt | 0x00000005 | low | undefined
9502 00:57:16.077400 TPM interrupt | 0x000000ab | high | undefined
9503 00:57:16.083470 SD card detect | 0x00000011 | high | undefined
9504 00:57:16.086960 speaker enable | 0x00000093 | high | undefined
9505 00:57:16.090166 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9506 00:57:16.093299 in-header: 03 f9 00 00 02 00 00 00
9507 00:57:16.096997 in-data: 02 00
9508 00:57:16.099634 ADC[4]: Raw value=901922 ID=7
9509 00:57:16.100154 ADC[3]: Raw value=214021 ID=1
9510 00:57:16.103716 RAM Code: 0x71
9511 00:57:16.106241 ADC[6]: Raw value=75036 ID=0
9512 00:57:16.106706 ADC[5]: Raw value=213282 ID=1
9513 00:57:16.109665 SKU Code: 0x1
9514 00:57:16.116236 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 41a5
9515 00:57:16.116784 coreboot table: 964 bytes.
9516 00:57:16.120172 IMD ROOT 0. 0xfffff000 0x00001000
9517 00:57:16.122749 IMD SMALL 1. 0xffffe000 0x00001000
9518 00:57:16.126329 RO MCACHE 2. 0xffffc000 0x00001104
9519 00:57:16.129343 CONSOLE 3. 0xfff7c000 0x00080000
9520 00:57:16.133259 FMAP 4. 0xfff7b000 0x00000452
9521 00:57:16.136076 TIME STAMP 5. 0xfff7a000 0x00000910
9522 00:57:16.139881 VBOOT WORK 6. 0xfff66000 0x00014000
9523 00:57:16.142642 RAMOOPS 7. 0xffe66000 0x00100000
9524 00:57:16.146169 COREBOOT 8. 0xffe64000 0x00002000
9525 00:57:16.149252 IMD small region:
9526 00:57:16.153067 IMD ROOT 0. 0xffffec00 0x00000400
9527 00:57:16.156150 VPD 1. 0xffffeb80 0x0000006c
9528 00:57:16.160007 MMC STATUS 2. 0xffffeb60 0x00000004
9529 00:57:16.163056 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9530 00:57:16.165916 Probing TPM: done!
9531 00:57:16.169853 Connected to device vid:did:rid of 1ae0:0028:00
9532 00:57:16.180249 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9533 00:57:16.184007 Initialized TPM device CR50 revision 0
9534 00:57:16.187600 Checking cr50 for pending updates
9535 00:57:16.191909 Reading cr50 TPM mode
9536 00:57:16.199610 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9537 00:57:16.206962 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9538 00:57:16.246476 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9539 00:57:16.250185 Checking segment from ROM address 0x40100000
9540 00:57:16.253701 Checking segment from ROM address 0x4010001c
9541 00:57:16.260208 Loading segment from ROM address 0x40100000
9542 00:57:16.260773 code (compression=0)
9543 00:57:16.270233 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9544 00:57:16.276614 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9545 00:57:16.277180 it's not compressed!
9546 00:57:16.283018 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9547 00:57:16.289639 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9548 00:57:16.306686 Loading segment from ROM address 0x4010001c
9549 00:57:16.307226 Entry Point 0x80000000
9550 00:57:16.310277 Loaded segments
9551 00:57:16.313711 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9552 00:57:16.320221 Jumping to boot code at 0x80000000(0xffe64000)
9553 00:57:16.326754 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9554 00:57:16.333566 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9555 00:57:16.341410 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9556 00:57:16.345048 Checking segment from ROM address 0x40100000
9557 00:57:16.347941 Checking segment from ROM address 0x4010001c
9558 00:57:16.354421 Loading segment from ROM address 0x40100000
9559 00:57:16.354929 code (compression=1)
9560 00:57:16.361071 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9561 00:57:16.371627 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9562 00:57:16.372245 using LZMA
9563 00:57:16.379589 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9564 00:57:16.386501 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9565 00:57:16.389708 Loading segment from ROM address 0x4010001c
9566 00:57:16.390171 Entry Point 0x54601000
9567 00:57:16.393053 Loaded segments
9568 00:57:16.396567 NOTICE: MT8192 bl31_setup
9569 00:57:16.403733 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9570 00:57:16.406758 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9571 00:57:16.410191 WARNING: region 0:
9572 00:57:16.413139 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9573 00:57:16.413600 WARNING: region 1:
9574 00:57:16.420080 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9575 00:57:16.423386 WARNING: region 2:
9576 00:57:16.426858 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9577 00:57:16.429699 WARNING: region 3:
9578 00:57:16.433107 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9579 00:57:16.436417 WARNING: region 4:
9580 00:57:16.443097 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9581 00:57:16.443564 WARNING: region 5:
9582 00:57:16.446404 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 00:57:16.449981 WARNING: region 6:
9584 00:57:16.453203 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 00:57:16.456213 WARNING: region 7:
9586 00:57:16.459426 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9587 00:57:16.466487 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9588 00:57:16.469387 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9589 00:57:16.476426 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9590 00:57:16.479870 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9591 00:57:16.482761 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9592 00:57:16.489784 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9593 00:57:16.493138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9594 00:57:16.496461 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9595 00:57:16.502519 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9596 00:57:16.505816 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9597 00:57:16.509272 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9598 00:57:16.515571 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9599 00:57:16.519460 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9600 00:57:16.526244 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9601 00:57:16.529526 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9602 00:57:16.532177 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9603 00:57:16.539182 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9604 00:57:16.542888 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9605 00:57:16.549095 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9606 00:57:16.552436 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9607 00:57:16.555806 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9608 00:57:16.562862 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9609 00:57:16.565493 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9610 00:57:16.569038 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9611 00:57:16.576022 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9612 00:57:16.579149 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9613 00:57:16.585679 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9614 00:57:16.589217 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9615 00:57:16.596011 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9616 00:57:16.598994 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9617 00:57:16.602055 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9618 00:57:16.608682 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9619 00:57:16.611808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9620 00:57:16.615049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9621 00:57:16.621847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9622 00:57:16.625217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9623 00:57:16.628579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9624 00:57:16.631880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9625 00:57:16.638243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9626 00:57:16.641525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9627 00:57:16.644830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9628 00:57:16.648169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9629 00:57:16.655090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9630 00:57:16.658220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9631 00:57:16.661795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9632 00:57:16.664416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9633 00:57:16.671345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9634 00:57:16.675006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9635 00:57:16.678337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9636 00:57:16.684842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9637 00:57:16.688151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9638 00:57:16.694819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9639 00:57:16.697872 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9640 00:57:16.701519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9641 00:57:16.708032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9642 00:57:16.711413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9643 00:57:16.717839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9644 00:57:16.720890 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9645 00:57:16.728001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9646 00:57:16.730826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9647 00:57:16.737439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9648 00:57:16.740685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9649 00:57:16.747391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9650 00:57:16.750682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9651 00:57:16.754552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9652 00:57:16.760410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9653 00:57:16.764334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9654 00:57:16.770673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9655 00:57:16.774142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9656 00:57:16.780668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9657 00:57:16.784265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9658 00:57:16.788701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9659 00:57:16.794025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9660 00:57:16.797685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9661 00:57:16.804136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9662 00:57:16.807285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9663 00:57:16.813848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9664 00:57:16.817211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9665 00:57:16.823775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9666 00:57:16.828489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9667 00:57:16.830906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9668 00:57:16.837199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9669 00:57:16.840201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9670 00:57:16.846850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9671 00:57:16.850413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9672 00:57:16.856843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9673 00:57:16.859940 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9674 00:57:16.863294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9675 00:57:16.870622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9676 00:57:16.874156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9677 00:57:16.880199 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9678 00:57:16.883521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9679 00:57:16.890018 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9680 00:57:16.893632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9681 00:57:16.899750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9682 00:57:16.903296 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9683 00:57:16.907245 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9684 00:57:16.912811 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9685 00:57:16.916658 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9686 00:57:16.920064 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9687 00:57:16.923570 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9688 00:57:16.929564 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9689 00:57:16.933023 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9690 00:57:16.939826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9691 00:57:16.943259 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9692 00:57:16.946424 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9693 00:57:16.953037 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9694 00:57:16.956245 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9695 00:57:16.963104 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9696 00:57:16.966170 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9697 00:57:16.969591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9698 00:57:16.976540 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9699 00:57:16.979666 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9700 00:57:16.986699 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9701 00:57:16.990139 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9702 00:57:16.993034 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9703 00:57:16.996179 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9704 00:57:17.002727 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9705 00:57:17.006388 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9706 00:57:17.012853 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9707 00:57:17.016334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9708 00:57:17.019215 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9709 00:57:17.022452 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9710 00:57:17.029068 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9711 00:57:17.032661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9712 00:57:17.035664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9713 00:57:17.042841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9714 00:57:17.045717 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9715 00:57:17.052373 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9716 00:57:17.055716 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9717 00:57:17.058850 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9718 00:57:17.065737 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9719 00:57:17.069627 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9720 00:57:17.072902 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9721 00:57:17.078721 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9722 00:57:17.082272 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9723 00:57:17.089186 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9724 00:57:17.092270 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9725 00:57:17.095627 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9726 00:57:17.102180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9727 00:57:17.105347 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9728 00:57:17.111633 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9729 00:57:17.115002 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9730 00:57:17.118340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9731 00:57:17.125085 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9732 00:57:17.128308 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9733 00:57:17.134928 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9734 00:57:17.138695 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9735 00:57:17.141741 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9736 00:57:17.148654 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9737 00:57:17.151777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9738 00:57:17.158313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9739 00:57:17.161477 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9740 00:57:17.165015 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9741 00:57:17.171770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9742 00:57:17.175341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9743 00:57:17.181410 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9744 00:57:17.185171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9745 00:57:17.188635 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9746 00:57:17.195323 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9747 00:57:17.198082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9748 00:57:17.204378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9749 00:57:17.207888 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9750 00:57:17.211595 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9751 00:57:17.218181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9752 00:57:17.221634 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9753 00:57:17.227659 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9754 00:57:17.231013 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9755 00:57:17.234449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9756 00:57:17.240791 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9757 00:57:17.244557 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9758 00:57:17.251016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9759 00:57:17.254602 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9760 00:57:17.257296 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9761 00:57:17.263998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9762 00:57:17.268185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9763 00:57:17.271147 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9764 00:57:17.277346 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9765 00:57:17.280590 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9766 00:57:17.287286 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9767 00:57:17.290928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9768 00:57:17.293716 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9769 00:57:17.300606 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9770 00:57:17.303960 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9771 00:57:17.310309 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9772 00:57:17.314104 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9773 00:57:17.317386 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9774 00:57:17.323788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9775 00:57:17.326934 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9776 00:57:17.333491 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9777 00:57:17.336690 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9778 00:57:17.343432 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9779 00:57:17.347205 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9780 00:57:17.350306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9781 00:57:17.356618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9782 00:57:17.359871 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9783 00:57:17.366588 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9784 00:57:17.370051 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9785 00:57:17.376536 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9786 00:57:17.379923 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9787 00:57:17.382825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9788 00:57:17.389506 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9789 00:57:17.392964 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9790 00:57:17.399199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9791 00:57:17.403197 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9792 00:57:17.409469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9793 00:57:17.412287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9794 00:57:17.415781 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9795 00:57:17.422734 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9796 00:57:17.425608 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9797 00:57:17.432470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9798 00:57:17.435398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9799 00:57:17.442151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9800 00:57:17.445349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9801 00:57:17.449240 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9802 00:57:17.455523 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9803 00:57:17.458464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9804 00:57:17.465537 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9805 00:57:17.468619 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9806 00:57:17.474947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9807 00:57:17.478312 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9808 00:57:17.482412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9809 00:57:17.488102 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9810 00:57:17.492092 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9811 00:57:17.498265 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9812 00:57:17.501505 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9813 00:57:17.508017 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9814 00:57:17.511820 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9815 00:57:17.514548 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9816 00:57:17.521593 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9817 00:57:17.524431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9818 00:57:17.528216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9819 00:57:17.531135 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9820 00:57:17.538239 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9821 00:57:17.541196 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9822 00:57:17.544415 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9823 00:57:17.550763 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9824 00:57:17.554551 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9825 00:57:17.557555 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9826 00:57:17.564341 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9827 00:57:17.567337 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9828 00:57:17.574181 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9829 00:57:17.577871 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9830 00:57:17.580568 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9831 00:57:17.587294 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9832 00:57:17.590819 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9833 00:57:17.596706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9834 00:57:17.600376 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9835 00:57:17.603169 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9836 00:57:17.610114 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9837 00:57:17.613139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9838 00:57:17.616833 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9839 00:57:17.623372 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9840 00:57:17.626911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9841 00:57:17.629829 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9842 00:57:17.636398 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9843 00:57:17.639983 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9844 00:57:17.646676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9845 00:57:17.650186 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9846 00:57:17.652811 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9847 00:57:17.659836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9848 00:57:17.663138 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9849 00:57:17.669784 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9850 00:57:17.673517 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9851 00:57:17.676887 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9852 00:57:17.682994 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9853 00:57:17.686097 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9854 00:57:17.689794 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9855 00:57:17.696184 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9856 00:57:17.699372 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9857 00:57:17.702683 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9858 00:57:17.706294 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9859 00:57:17.709742 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9860 00:57:17.715808 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9861 00:57:17.719538 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9862 00:57:17.722545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9863 00:57:17.729122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9864 00:57:17.732378 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9865 00:57:17.735618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9866 00:57:17.738979 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9867 00:57:17.745022 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9868 00:57:17.748380 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9869 00:57:17.751910 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9870 00:57:17.758709 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9871 00:57:17.762179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9872 00:57:17.768802 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9873 00:57:17.771842 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9874 00:57:17.778565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9875 00:57:17.781863 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9876 00:57:17.784872 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9877 00:57:17.791790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9878 00:57:17.795153 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9879 00:57:17.801636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9880 00:57:17.804683 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9881 00:57:17.808123 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9882 00:57:17.814690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9883 00:57:17.817600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9884 00:57:17.824427 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9885 00:57:17.827477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9886 00:57:17.834066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9887 00:57:17.837614 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9888 00:57:17.840994 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9889 00:57:17.847440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9890 00:57:17.850848 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9891 00:57:17.857873 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9892 00:57:17.860807 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9893 00:57:17.864077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9894 00:57:17.870776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9895 00:57:17.873735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9896 00:57:17.880996 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9897 00:57:17.883954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9898 00:57:17.890809 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9899 00:57:17.894172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9900 00:57:17.897080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9901 00:57:17.903747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9902 00:57:17.906884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9903 00:57:17.914234 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9904 00:57:17.917003 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9905 00:57:17.920284 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9906 00:57:17.927174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9907 00:57:17.930394 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9908 00:57:17.936829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9909 00:57:17.939946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9910 00:57:17.943246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9911 00:57:17.950501 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9912 00:57:17.953177 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9913 00:57:17.960242 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9914 00:57:17.962968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9915 00:57:17.970283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9916 00:57:17.973516 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9917 00:57:17.977105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9918 00:57:17.983368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9919 00:57:17.986142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9920 00:57:17.994049 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9921 00:57:17.996644 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9922 00:57:18.002873 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9923 00:57:18.006613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9924 00:57:18.009516 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9925 00:57:18.016153 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9926 00:57:18.019854 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9927 00:57:18.025797 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9928 00:57:18.029347 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9929 00:57:18.032479 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9930 00:57:18.039052 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9931 00:57:18.042612 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9932 00:57:18.049656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9933 00:57:18.052266 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9934 00:57:18.055805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9935 00:57:18.062573 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9936 00:57:18.066062 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9937 00:57:18.072119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9938 00:57:18.075845 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9939 00:57:18.082149 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9940 00:57:18.085775 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9941 00:57:18.089432 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9942 00:57:18.095784 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9943 00:57:18.098962 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9944 00:57:18.105066 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9945 00:57:18.108621 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9946 00:57:18.115800 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9947 00:57:18.118257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9948 00:57:18.121802 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9949 00:57:18.128388 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9950 00:57:18.131447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9951 00:57:18.138742 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9952 00:57:18.141712 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9953 00:57:18.147770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9954 00:57:18.151473 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9955 00:57:18.158013 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9956 00:57:18.161148 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9957 00:57:18.165022 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9958 00:57:18.170886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9959 00:57:18.174365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9960 00:57:18.180775 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9961 00:57:18.184066 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9962 00:57:18.191095 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9963 00:57:18.193929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9964 00:57:18.200979 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9965 00:57:18.203595 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9966 00:57:18.210726 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9967 00:57:18.213690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9968 00:57:18.217104 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9969 00:57:18.223550 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9970 00:57:18.227063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9971 00:57:18.233640 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9972 00:57:18.237439 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9973 00:57:18.243364 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9974 00:57:18.246710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9975 00:57:18.253597 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9976 00:57:18.256764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9977 00:57:18.260402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9978 00:57:18.267012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9979 00:57:18.269822 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9980 00:57:18.276506 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9981 00:57:18.280142 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9982 00:57:18.286473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9983 00:57:18.289591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9984 00:57:18.296395 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9985 00:57:18.299367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9986 00:57:18.303350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9987 00:57:18.309472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9988 00:57:18.312616 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9989 00:57:18.319864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9990 00:57:18.323061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9991 00:57:18.329419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9992 00:57:18.332337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9993 00:57:18.335755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9994 00:57:18.342528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9995 00:57:18.345764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9996 00:57:18.352427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9997 00:57:18.355789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9998 00:57:18.362358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9999 00:57:18.365416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10000 00:57:18.372104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10001 00:57:18.375744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10002 00:57:18.382415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10003 00:57:18.385192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10004 00:57:18.392374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10005 00:57:18.395488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10006 00:57:18.402060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10007 00:57:18.404849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10008 00:57:18.411664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10009 00:57:18.415164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10010 00:57:18.421773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10011 00:57:18.424418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10012 00:57:18.431213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10013 00:57:18.435490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10014 00:57:18.441286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10015 00:57:18.444601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10016 00:57:18.451326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10017 00:57:18.457617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10018 00:57:18.460777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10019 00:57:18.467963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10020 00:57:18.471003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10021 00:57:18.474379 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10022 00:57:18.477933 INFO: [APUAPC] vio 0
10023 00:57:18.480860 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10024 00:57:18.487382 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10025 00:57:18.490726 INFO: [APUAPC] D0_APC_0: 0x400510
10026 00:57:18.494305 INFO: [APUAPC] D0_APC_1: 0x0
10027 00:57:18.497387 INFO: [APUAPC] D0_APC_2: 0x1540
10028 00:57:18.497802 INFO: [APUAPC] D0_APC_3: 0x0
10029 00:57:18.500886 INFO: [APUAPC] D1_APC_0: 0xffffffff
10030 00:57:18.507343 INFO: [APUAPC] D1_APC_1: 0xffffffff
10031 00:57:18.510460 INFO: [APUAPC] D1_APC_2: 0x3fffff
10032 00:57:18.510874 INFO: [APUAPC] D1_APC_3: 0x0
10033 00:57:18.513909 INFO: [APUAPC] D2_APC_0: 0xffffffff
10034 00:57:18.516905 INFO: [APUAPC] D2_APC_1: 0xffffffff
10035 00:57:18.520612 INFO: [APUAPC] D2_APC_2: 0x3fffff
10036 00:57:18.523960 INFO: [APUAPC] D2_APC_3: 0x0
10037 00:57:18.527475 INFO: [APUAPC] D3_APC_0: 0xffffffff
10038 00:57:18.530170 INFO: [APUAPC] D3_APC_1: 0xffffffff
10039 00:57:18.533464 INFO: [APUAPC] D3_APC_2: 0x3fffff
10040 00:57:18.536816 INFO: [APUAPC] D3_APC_3: 0x0
10041 00:57:18.540530 INFO: [APUAPC] D4_APC_0: 0xffffffff
10042 00:57:18.544008 INFO: [APUAPC] D4_APC_1: 0xffffffff
10043 00:57:18.547082 INFO: [APUAPC] D4_APC_2: 0x3fffff
10044 00:57:18.550596 INFO: [APUAPC] D4_APC_3: 0x0
10045 00:57:18.554101 INFO: [APUAPC] D5_APC_0: 0xffffffff
10046 00:57:18.556847 INFO: [APUAPC] D5_APC_1: 0xffffffff
10047 00:57:18.560385 INFO: [APUAPC] D5_APC_2: 0x3fffff
10048 00:57:18.563402 INFO: [APUAPC] D5_APC_3: 0x0
10049 00:57:18.566712 INFO: [APUAPC] D6_APC_0: 0xffffffff
10050 00:57:18.570015 INFO: [APUAPC] D6_APC_1: 0xffffffff
10051 00:57:18.573065 INFO: [APUAPC] D6_APC_2: 0x3fffff
10052 00:57:18.576622 INFO: [APUAPC] D6_APC_3: 0x0
10053 00:57:18.580039 INFO: [APUAPC] D7_APC_0: 0xffffffff
10054 00:57:18.583429 INFO: [APUAPC] D7_APC_1: 0xffffffff
10055 00:57:18.586904 INFO: [APUAPC] D7_APC_2: 0x3fffff
10056 00:57:18.590129 INFO: [APUAPC] D7_APC_3: 0x0
10057 00:57:18.593397 INFO: [APUAPC] D8_APC_0: 0xffffffff
10058 00:57:18.596452 INFO: [APUAPC] D8_APC_1: 0xffffffff
10059 00:57:18.599914 INFO: [APUAPC] D8_APC_2: 0x3fffff
10060 00:57:18.603073 INFO: [APUAPC] D8_APC_3: 0x0
10061 00:57:18.606497 INFO: [APUAPC] D9_APC_0: 0xffffffff
10062 00:57:18.609705 INFO: [APUAPC] D9_APC_1: 0xffffffff
10063 00:57:18.613037 INFO: [APUAPC] D9_APC_2: 0x3fffff
10064 00:57:18.616582 INFO: [APUAPC] D9_APC_3: 0x0
10065 00:57:18.619812 INFO: [APUAPC] D10_APC_0: 0xffffffff
10066 00:57:18.623067 INFO: [APUAPC] D10_APC_1: 0xffffffff
10067 00:57:18.626381 INFO: [APUAPC] D10_APC_2: 0x3fffff
10068 00:57:18.629308 INFO: [APUAPC] D10_APC_3: 0x0
10069 00:57:18.633350 INFO: [APUAPC] D11_APC_0: 0xffffffff
10070 00:57:18.636088 INFO: [APUAPC] D11_APC_1: 0xffffffff
10071 00:57:18.639511 INFO: [APUAPC] D11_APC_2: 0x3fffff
10072 00:57:18.642366 INFO: [APUAPC] D11_APC_3: 0x0
10073 00:57:18.646036 INFO: [APUAPC] D12_APC_0: 0xffffffff
10074 00:57:18.649021 INFO: [APUAPC] D12_APC_1: 0xffffffff
10075 00:57:18.652762 INFO: [APUAPC] D12_APC_2: 0x3fffff
10076 00:57:18.655859 INFO: [APUAPC] D12_APC_3: 0x0
10077 00:57:18.659004 INFO: [APUAPC] D13_APC_0: 0xffffffff
10078 00:57:18.662161 INFO: [APUAPC] D13_APC_1: 0xffffffff
10079 00:57:18.665598 INFO: [APUAPC] D13_APC_2: 0x3fffff
10080 00:57:18.669066 INFO: [APUAPC] D13_APC_3: 0x0
10081 00:57:18.672288 INFO: [APUAPC] D14_APC_0: 0xffffffff
10082 00:57:18.675265 INFO: [APUAPC] D14_APC_1: 0xffffffff
10083 00:57:18.679011 INFO: [APUAPC] D14_APC_2: 0x3fffff
10084 00:57:18.681793 INFO: [APUAPC] D14_APC_3: 0x0
10085 00:57:18.685463 INFO: [APUAPC] D15_APC_0: 0xffffffff
10086 00:57:18.688989 INFO: [APUAPC] D15_APC_1: 0xffffffff
10087 00:57:18.692540 INFO: [APUAPC] D15_APC_2: 0x3fffff
10088 00:57:18.695514 INFO: [APUAPC] D15_APC_3: 0x0
10089 00:57:18.698279 INFO: [APUAPC] APC_CON: 0x4
10090 00:57:18.701723 INFO: [NOCDAPC] D0_APC_0: 0x0
10091 00:57:18.705004 INFO: [NOCDAPC] D0_APC_1: 0x0
10092 00:57:18.708125 INFO: [NOCDAPC] D1_APC_0: 0x0
10093 00:57:18.711800 INFO: [NOCDAPC] D1_APC_1: 0xfff
10094 00:57:18.714885 INFO: [NOCDAPC] D2_APC_0: 0x0
10095 00:57:18.718474 INFO: [NOCDAPC] D2_APC_1: 0xfff
10096 00:57:18.718978 INFO: [NOCDAPC] D3_APC_0: 0x0
10097 00:57:18.721345 INFO: [NOCDAPC] D3_APC_1: 0xfff
10098 00:57:18.724702 INFO: [NOCDAPC] D4_APC_0: 0x0
10099 00:57:18.727799 INFO: [NOCDAPC] D4_APC_1: 0xfff
10100 00:57:18.731591 INFO: [NOCDAPC] D5_APC_0: 0x0
10101 00:57:18.734753 INFO: [NOCDAPC] D5_APC_1: 0xfff
10102 00:57:18.738132 INFO: [NOCDAPC] D6_APC_0: 0x0
10103 00:57:18.741747 INFO: [NOCDAPC] D6_APC_1: 0xfff
10104 00:57:18.744983 INFO: [NOCDAPC] D7_APC_0: 0x0
10105 00:57:18.747743 INFO: [NOCDAPC] D7_APC_1: 0xfff
10106 00:57:18.751190 INFO: [NOCDAPC] D8_APC_0: 0x0
10107 00:57:18.754646 INFO: [NOCDAPC] D8_APC_1: 0xfff
10108 00:57:18.755156 INFO: [NOCDAPC] D9_APC_0: 0x0
10109 00:57:18.757864 INFO: [NOCDAPC] D9_APC_1: 0xfff
10110 00:57:18.761149 INFO: [NOCDAPC] D10_APC_0: 0x0
10111 00:57:18.764624 INFO: [NOCDAPC] D10_APC_1: 0xfff
10112 00:57:18.767540 INFO: [NOCDAPC] D11_APC_0: 0x0
10113 00:57:18.771095 INFO: [NOCDAPC] D11_APC_1: 0xfff
10114 00:57:18.774728 INFO: [NOCDAPC] D12_APC_0: 0x0
10115 00:57:18.777980 INFO: [NOCDAPC] D12_APC_1: 0xfff
10116 00:57:18.781263 INFO: [NOCDAPC] D13_APC_0: 0x0
10117 00:57:18.784228 INFO: [NOCDAPC] D13_APC_1: 0xfff
10118 00:57:18.787441 INFO: [NOCDAPC] D14_APC_0: 0x0
10119 00:57:18.791100 INFO: [NOCDAPC] D14_APC_1: 0xfff
10120 00:57:18.794298 INFO: [NOCDAPC] D15_APC_0: 0x0
10121 00:57:18.797513 INFO: [NOCDAPC] D15_APC_1: 0xfff
10122 00:57:18.801004 INFO: [NOCDAPC] APC_CON: 0x4
10123 00:57:18.804474 INFO: [APUAPC] set_apusys_apc done
10124 00:57:18.807429 INFO: [DEVAPC] devapc_init done
10125 00:57:18.810437 INFO: GICv3 without legacy support detected.
10126 00:57:18.813617 INFO: ARM GICv3 driver initialized in EL3
10127 00:57:18.817148 INFO: Maximum SPI INTID supported: 639
10128 00:57:18.820609 INFO: BL31: Initializing runtime services
10129 00:57:18.827068 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10130 00:57:18.830964 INFO: SPM: enable CPC mode
10131 00:57:18.834240 INFO: mcdi ready for mcusys-off-idle and system suspend
10132 00:57:18.840464 INFO: BL31: Preparing for EL3 exit to normal world
10133 00:57:18.843450 INFO: Entry point address = 0x80000000
10134 00:57:18.846968 INFO: SPSR = 0x8
10135 00:57:18.851359
10136 00:57:18.851881
10137 00:57:18.852214
10138 00:57:18.855076 Starting depthcharge on Spherion...
10139 00:57:18.855614
10140 00:57:18.856010 Wipe memory regions:
10141 00:57:18.856323
10142 00:57:18.858969 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10143 00:57:18.859467 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10144 00:57:18.859926 Setting prompt string to ['asurada:']
10145 00:57:18.860331 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10146 00:57:18.860984 [0x00000040000000, 0x00000054600000)
10147 00:57:18.980416
10148 00:57:18.980930 [0x00000054660000, 0x00000080000000)
10149 00:57:19.240661
10150 00:57:19.241214 [0x000000821a7280, 0x000000ffe64000)
10151 00:57:19.985629
10152 00:57:19.986180 [0x00000100000000, 0x00000240000000)
10153 00:57:21.877096
10154 00:57:21.879637 Initializing XHCI USB controller at 0x11200000.
10155 00:57:22.861008
10156 00:57:22.861551 R8152: Initializing
10157 00:57:22.861916
10158 00:57:22.864621 Version 9 (ocp_data = 6010)
10159 00:57:22.865077
10160 00:57:22.867887 R8152: Done initializing
10161 00:57:22.868301
10162 00:57:22.868631 Adding net device
10163 00:57:23.265407
10164 00:57:23.268859 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10165 00:57:23.269322
10166 00:57:23.269686
10167 00:57:23.270030
10168 00:57:23.270865 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10170 00:57:23.372092 asurada: tftpboot 192.168.201.1 12571069/tftp-deploy-y3atqli7/kernel/image.itb 12571069/tftp-deploy-y3atqli7/kernel/cmdline
10171 00:57:23.372727 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10172 00:57:23.373162 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10173 00:57:23.377616 tftpboot 192.168.201.1 12571069/tftp-deploy-y3atqli7/kernel/image.itp-deploy-y3atqli7/kernel/cmdline
10174 00:57:23.378173
10175 00:57:23.378537 Waiting for link
10176 00:57:23.579715
10177 00:57:23.580299 done.
10178 00:57:23.580668
10179 00:57:23.581007 MAC: f4:f5:e8:50:de:0a
10180 00:57:23.581336
10181 00:57:23.582756 Sending DHCP discover... done.
10182 00:57:23.583215
10183 00:57:23.586535 Waiting for reply... done.
10184 00:57:23.587028
10185 00:57:23.589235 Sending DHCP request... done.
10186 00:57:23.589688
10187 00:57:23.590048 Waiting for reply... done.
10188 00:57:23.590383
10189 00:57:23.592561 My ip is 192.168.201.14
10190 00:57:23.593050
10191 00:57:23.595790 The DHCP server ip is 192.168.201.1
10192 00:57:23.596278
10193 00:57:23.599409 TFTP server IP predefined by user: 192.168.201.1
10194 00:57:23.599904
10195 00:57:23.606061 Bootfile predefined by user: 12571069/tftp-deploy-y3atqli7/kernel/image.itb
10196 00:57:23.606578
10197 00:57:23.609474 Sending tftp read request... done.
10198 00:57:23.609995
10199 00:57:23.617874 Waiting for the transfer...
10200 00:57:23.618293
10201 00:57:23.909164 00000000 ################################################################
10202 00:57:23.909336
10203 00:57:24.159763 00080000 ################################################################
10204 00:57:24.159901
10205 00:57:24.410061 00100000 ################################################################
10206 00:57:24.410215
10207 00:57:24.666018 00180000 ################################################################
10208 00:57:24.666176
10209 00:57:24.895879 00200000 ################################################################
10210 00:57:24.896104
10211 00:57:25.135656 00280000 ################################################################
10212 00:57:25.135830
10213 00:57:25.379307 00300000 ################################################################
10214 00:57:25.379440
10215 00:57:25.649433 00380000 ################################################################
10216 00:57:25.649567
10217 00:57:25.901759 00400000 ################################################################
10218 00:57:25.901890
10219 00:57:26.154664 00480000 ################################################################
10220 00:57:26.154799
10221 00:57:26.398468 00500000 ################################################################
10222 00:57:26.398601
10223 00:57:26.633327 00580000 ################################################################
10224 00:57:26.633463
10225 00:57:26.875623 00600000 ################################################################
10226 00:57:26.875792
10227 00:57:27.129783 00680000 ################################################################
10228 00:57:27.129928
10229 00:57:27.364160 00700000 ################################################################
10230 00:57:27.364305
10231 00:57:27.609545 00780000 ################################################################
10232 00:57:27.609684
10233 00:57:27.837972 00800000 ################################################################
10234 00:57:27.838111
10235 00:57:28.095269 00880000 ################################################################
10236 00:57:28.095427
10237 00:57:28.351895 00900000 ################################################################
10238 00:57:28.352048
10239 00:57:28.613854 00980000 ################################################################
10240 00:57:28.613995
10241 00:57:28.840572 00a00000 ################################################################
10242 00:57:28.840706
10243 00:57:29.073830 00a80000 ################################################################
10244 00:57:29.073962
10245 00:57:29.336284 00b00000 ################################################################
10246 00:57:29.336419
10247 00:57:29.592856 00b80000 ################################################################
10248 00:57:29.593010
10249 00:57:29.842882 00c00000 ################################################################
10250 00:57:29.843042
10251 00:57:30.077259 00c80000 ################################################################
10252 00:57:30.077389
10253 00:57:30.315736 00d00000 ################################################################
10254 00:57:30.315870
10255 00:57:30.581752 00d80000 ################################################################
10256 00:57:30.581918
10257 00:57:30.815143 00e00000 ################################################################
10258 00:57:30.815310
10259 00:57:31.066594 00e80000 ################################################################
10260 00:57:31.066748
10261 00:57:31.333837 00f00000 ################################################################
10262 00:57:31.333964
10263 00:57:31.572806 00f80000 ################################################################
10264 00:57:31.572936
10265 00:57:31.830169 01000000 ################################################################
10266 00:57:31.830326
10267 00:57:32.076538 01080000 ################################################################
10268 00:57:32.076713
10269 00:57:32.316122 01100000 ################################################################
10270 00:57:32.316255
10271 00:57:32.570819 01180000 ################################################################
10272 00:57:32.570957
10273 00:57:32.801892 01200000 ################################################################
10274 00:57:32.802024
10275 00:57:33.042630 01280000 ################################################################
10276 00:57:33.042761
10277 00:57:33.298535 01300000 ################################################################
10278 00:57:33.298667
10279 00:57:33.557874 01380000 ################################################################
10280 00:57:33.558021
10281 00:57:33.800318 01400000 ################################################################
10282 00:57:33.800468
10283 00:57:34.034939 01480000 ################################################################
10284 00:57:34.035096
10285 00:57:34.270422 01500000 ################################################################
10286 00:57:34.270556
10287 00:57:34.526744 01580000 ################################################################
10288 00:57:34.526873
10289 00:57:34.769091 01600000 ################################################################
10290 00:57:34.769238
10291 00:57:35.001254 01680000 ################################################################
10292 00:57:35.001385
10293 00:57:35.253143 01700000 ################################################################
10294 00:57:35.253269
10295 00:57:35.511324 01780000 ################################################################
10296 00:57:35.511456
10297 00:57:35.766059 01800000 ################################################################
10298 00:57:35.766212
10299 00:57:36.002659 01880000 ################################################################
10300 00:57:36.002793
10301 00:57:36.247470 01900000 ################################################################
10302 00:57:36.247637
10303 00:57:36.488152 01980000 ################################################################
10304 00:57:36.488275
10305 00:57:36.739652 01a00000 ################################################################
10306 00:57:36.739819
10307 00:57:37.003005 01a80000 ################################################################
10308 00:57:37.003138
10309 00:57:37.258956 01b00000 ################################################################
10310 00:57:37.259100
10311 00:57:37.524814 01b80000 ################################################################
10312 00:57:37.524948
10313 00:57:37.767000 01c00000 ################################################################
10314 00:57:37.767166
10315 00:57:38.017438 01c80000 ################################################################
10316 00:57:38.017591
10317 00:57:38.243726 01d00000 ######################################################## done.
10318 00:57:38.243891
10319 00:57:38.246368 The bootfile was 30865750 bytes long.
10320 00:57:38.246452
10321 00:57:38.249889 Sending tftp read request... done.
10322 00:57:38.249977
10323 00:57:38.250045 Waiting for the transfer...
10324 00:57:38.250109
10325 00:57:38.253006 00000000 # done.
10326 00:57:38.253100
10327 00:57:38.259525 Command line loaded dynamically from TFTP file: 12571069/tftp-deploy-y3atqli7/kernel/cmdline
10328 00:57:38.259627
10329 00:57:38.282769 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10330 00:57:38.282954
10331 00:57:38.283091 Loading FIT.
10332 00:57:38.283219
10333 00:57:38.286393 Image ramdisk-1 has 18767814 bytes.
10334 00:57:38.286564
10335 00:57:38.289361 Image fdt-1 has 47278 bytes.
10336 00:57:38.289559
10337 00:57:38.293398 Image kernel-1 has 12048624 bytes.
10338 00:57:38.293633
10339 00:57:38.303777 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10340 00:57:38.304163
10341 00:57:38.319460 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10342 00:57:38.319946
10343 00:57:38.326184 Choosing best match conf-1 for compat google,spherion-rev2.
10344 00:57:38.326598
10345 00:57:38.333203 Connected to device vid:did:rid of 1ae0:0028:00
10346 00:57:38.340675
10347 00:57:38.344092 tpm_get_response: command 0x17b, return code 0x0
10348 00:57:38.344508
10349 00:57:38.347268 ec_init: CrosEC protocol v3 supported (256, 248)
10350 00:57:38.351465
10351 00:57:38.354892 tpm_cleanup: add release locality here.
10352 00:57:38.355305
10353 00:57:38.355632 Shutting down all USB controllers.
10354 00:57:38.358082
10355 00:57:38.358473 Removing current net device
10356 00:57:38.358794
10357 00:57:38.364516 Exiting depthcharge with code 4 at timestamp: 48939156
10358 00:57:38.364930
10359 00:57:38.368115 LZMA decompressing kernel-1 to 0x821a6718
10360 00:57:38.368530
10361 00:57:38.370993 LZMA decompressing kernel-1 to 0x40000000
10362 00:57:39.870676
10363 00:57:39.871227 jumping to kernel
10364 00:57:39.872939 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10365 00:57:39.873461 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10366 00:57:39.873865 Setting prompt string to ['Linux version [0-9]']
10367 00:57:39.874232 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10368 00:57:39.874580 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10369 00:57:39.952437
10370 00:57:39.955548 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10371 00:57:39.959215 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10372 00:57:39.959665 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10373 00:57:39.960059 Setting prompt string to []
10374 00:57:39.960433 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10375 00:57:39.960786 Using line separator: #'\n'#
10376 00:57:39.961096 No login prompt set.
10377 00:57:39.961465 Parsing kernel messages
10378 00:57:39.961755 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10379 00:57:39.962258 [login-action] Waiting for messages, (timeout 00:04:04)
10380 00:57:39.979022 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10381 00:57:39.982022 [ 0.000000] random: crng init done
10382 00:57:39.988201 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10383 00:57:39.991921 [ 0.000000] efi: UEFI not found.
10384 00:57:39.998810 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10385 00:57:40.005006 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10386 00:57:40.015063 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10387 00:57:40.024654 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10388 00:57:40.031778 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10389 00:57:40.037897 [ 0.000000] printk: bootconsole [mtk8250] enabled
10390 00:57:40.044287 [ 0.000000] NUMA: No NUMA configuration found
10391 00:57:40.051441 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10392 00:57:40.057422 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10393 00:57:40.057840 [ 0.000000] Zone ranges:
10394 00:57:40.064061 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10395 00:57:40.067498 [ 0.000000] DMA32 empty
10396 00:57:40.074109 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10397 00:57:40.077230 [ 0.000000] Movable zone start for each node
10398 00:57:40.080687 [ 0.000000] Early memory node ranges
10399 00:57:40.087220 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10400 00:57:40.093263 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10401 00:57:40.099976 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10402 00:57:40.106615 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10403 00:57:40.113221 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10404 00:57:40.120568 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10405 00:57:40.177114 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10406 00:57:40.183183 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10407 00:57:40.190469 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10408 00:57:40.193191 [ 0.000000] psci: probing for conduit method from DT.
10409 00:57:40.199947 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10410 00:57:40.202928 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10411 00:57:40.210030 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10412 00:57:40.213578 [ 0.000000] psci: SMC Calling Convention v1.2
10413 00:57:40.220575 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10414 00:57:40.223271 [ 0.000000] Detected VIPT I-cache on CPU0
10415 00:57:40.229948 [ 0.000000] CPU features: detected: GIC system register CPU interface
10416 00:57:40.236322 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10417 00:57:40.243960 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10418 00:57:40.249637 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10419 00:57:40.258914 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10420 00:57:40.266131 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10421 00:57:40.268997 [ 0.000000] alternatives: applying boot alternatives
10422 00:57:40.275508 [ 0.000000] Fallback order for Node 0: 0
10423 00:57:40.282171 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10424 00:57:40.285368 [ 0.000000] Policy zone: Normal
10425 00:57:40.308705 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10426 00:57:40.318383 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10427 00:57:40.329922 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10428 00:57:40.339734 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10429 00:57:40.346675 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10430 00:57:40.349969 <6>[ 0.000000] software IO TLB: area num 8.
10431 00:57:40.406095 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10432 00:57:40.555783 <6>[ 0.000000] Memory: 7948928K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 403840K reserved, 32768K cma-reserved)
10433 00:57:40.562109 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10434 00:57:40.568323 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10435 00:57:40.571575 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10436 00:57:40.578256 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10437 00:57:40.585758 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10438 00:57:40.591132 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10439 00:57:40.598432 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10440 00:57:40.604519 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10441 00:57:40.612919 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10442 00:57:40.617977 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10443 00:57:40.620983 <6>[ 0.000000] GICv3: 608 SPIs implemented
10444 00:57:40.624348 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10445 00:57:40.630999 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10446 00:57:40.634495 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10447 00:57:40.641559 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10448 00:57:40.654946 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10449 00:57:40.667240 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10450 00:57:40.673841 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10451 00:57:40.681967 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10452 00:57:40.695638 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10453 00:57:40.701445 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10454 00:57:40.708769 <6>[ 0.009185] Console: colour dummy device 80x25
10455 00:57:40.719149 <6>[ 0.013942] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10456 00:57:40.724937 <6>[ 0.024448] pid_max: default: 32768 minimum: 301
10457 00:57:40.728292 <6>[ 0.029320] LSM: Security Framework initializing
10458 00:57:40.735776 <6>[ 0.034259] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 00:57:40.745231 <6>[ 0.042074] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 00:57:40.754727 <6>[ 0.051491] cblist_init_generic: Setting adjustable number of callback queues.
10461 00:57:40.758189 <6>[ 0.058935] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 00:57:40.768023 <6>[ 0.065273] cblist_init_generic: Setting adjustable number of callback queues.
10463 00:57:40.774614 <6>[ 0.072700] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 00:57:40.777399 <6>[ 0.079142] rcu: Hierarchical SRCU implementation.
10465 00:57:40.784307 <6>[ 0.084157] rcu: Max phase no-delay instances is 1000.
10466 00:57:40.790917 <6>[ 0.091180] EFI services will not be available.
10467 00:57:40.794099 <6>[ 0.096161] smp: Bringing up secondary CPUs ...
10468 00:57:40.803484 <6>[ 0.101209] Detected VIPT I-cache on CPU1
10469 00:57:40.809786 <6>[ 0.101281] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10470 00:57:40.816263 <6>[ 0.101312] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10471 00:57:40.819222 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10472 00:57:40.829580 <6>[ 0.101695] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10473 00:57:40.835866 <6>[ 0.101712] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10474 00:57:40.839247 <6>[ 0.101969] Detected VIPT I-cache on CPU3
10475 00:57:40.845891 <6>[ 0.102014] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10476 00:57:40.852137 <6>[ 0.102028] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10477 00:57:40.858448 <6>[ 0.102333] CPU features: detected: Spectre-v4
10478 00:57:40.862161 <6>[ 0.102339] CPU features: detected: Spectre-BHB
10479 00:57:40.865350 <6>[ 0.102344] Detected PIPT I-cache on CPU4
10480 00:57:40.872016 <6>[ 0.102400] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10481 00:57:40.878635 <6>[ 0.102416] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10482 00:57:40.885148 <6>[ 0.102701] Detected PIPT I-cache on CPU5
10483 00:57:40.891661 <6>[ 0.102764] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10484 00:57:40.898612 <6>[ 0.102781] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10485 00:57:40.902044 <6>[ 0.103061] Detected PIPT I-cache on CPU6
10486 00:57:40.911140 <6>[ 0.103126] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10487 00:57:40.918304 <6>[ 0.103144] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10488 00:57:40.921205 <6>[ 0.103438] Detected PIPT I-cache on CPU7
10489 00:57:40.928504 <6>[ 0.103503] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10490 00:57:40.934802 <6>[ 0.103520] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10491 00:57:40.937839 <6>[ 0.103568] smp: Brought up 1 node, 8 CPUs
10492 00:57:40.944537 <6>[ 0.244944] SMP: Total of 8 processors activated.
10493 00:57:40.951195 <6>[ 0.249865] CPU features: detected: 32-bit EL0 Support
10494 00:57:40.958127 <6>[ 0.255227] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10495 00:57:40.964298 <6>[ 0.264082] CPU features: detected: Common not Private translations
10496 00:57:40.971003 <6>[ 0.270557] CPU features: detected: CRC32 instructions
10497 00:57:40.977625 <6>[ 0.275909] CPU features: detected: RCpc load-acquire (LDAPR)
10498 00:57:40.981221 <6>[ 0.281906] CPU features: detected: LSE atomic instructions
10499 00:57:40.987459 <6>[ 0.287687] CPU features: detected: Privileged Access Never
10500 00:57:40.993967 <6>[ 0.293467] CPU features: detected: RAS Extension Support
10501 00:57:41.000682 <6>[ 0.299075] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10502 00:57:41.003975 <6>[ 0.306295] CPU: All CPU(s) started at EL2
10503 00:57:41.010537 <6>[ 0.310638] alternatives: applying system-wide alternatives
10504 00:57:41.020745 <6>[ 0.321396] devtmpfs: initialized
10505 00:57:41.036364 <6>[ 0.330375] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10506 00:57:41.043026 <6>[ 0.340337] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10507 00:57:41.049481 <6>[ 0.348571] pinctrl core: initialized pinctrl subsystem
10508 00:57:41.052592 <6>[ 0.355179] DMI not present or invalid.
10509 00:57:41.059602 <6>[ 0.359592] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10510 00:57:41.069319 <6>[ 0.366470] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10511 00:57:41.076131 <6>[ 0.374051] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10512 00:57:41.085540 <6>[ 0.382280] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10513 00:57:41.089190 <6>[ 0.390523] audit: initializing netlink subsys (disabled)
10514 00:57:41.098862 <5>[ 0.396215] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10515 00:57:41.105623 <6>[ 0.396912] thermal_sys: Registered thermal governor 'step_wise'
10516 00:57:41.112048 <6>[ 0.404184] thermal_sys: Registered thermal governor 'power_allocator'
10517 00:57:41.115172 <6>[ 0.410439] cpuidle: using governor menu
10518 00:57:41.121782 <6>[ 0.421397] NET: Registered PF_QIPCRTR protocol family
10519 00:57:41.128908 <6>[ 0.426879] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10520 00:57:41.135364 <6>[ 0.433982] ASID allocator initialised with 32768 entries
10521 00:57:41.138705 <6>[ 0.440542] Serial: AMBA PL011 UART driver
10522 00:57:41.148998 <4>[ 0.449327] Trying to register duplicate clock ID: 134
10523 00:57:41.204266 <6>[ 0.508723] KASLR enabled
10524 00:57:41.218754 <6>[ 0.516533] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10525 00:57:41.226137 <6>[ 0.523543] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10526 00:57:41.232332 <6>[ 0.530033] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10527 00:57:41.238745 <6>[ 0.537039] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10528 00:57:41.245532 <6>[ 0.543525] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10529 00:57:41.251604 <6>[ 0.550529] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10530 00:57:41.258426 <6>[ 0.557013] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10531 00:57:41.265271 <6>[ 0.564017] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10532 00:57:41.268467 <6>[ 0.571540] ACPI: Interpreter disabled.
10533 00:57:41.277364 <6>[ 0.577966] iommu: Default domain type: Translated
10534 00:57:41.284179 <6>[ 0.583076] iommu: DMA domain TLB invalidation policy: strict mode
10535 00:57:41.287012 <5>[ 0.589712] SCSI subsystem initialized
10536 00:57:41.293578 <6>[ 0.593878] usbcore: registered new interface driver usbfs
10537 00:57:41.300285 <6>[ 0.599610] usbcore: registered new interface driver hub
10538 00:57:41.303396 <6>[ 0.605162] usbcore: registered new device driver usb
10539 00:57:41.310793 <6>[ 0.611271] pps_core: LinuxPPS API ver. 1 registered
10540 00:57:41.320636 <6>[ 0.616466] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10541 00:57:41.323388 <6>[ 0.625815] PTP clock support registered
10542 00:57:41.327015 <6>[ 0.630058] EDAC MC: Ver: 3.0.0
10543 00:57:41.334250 <6>[ 0.635231] FPGA manager framework
10544 00:57:41.341526 <6>[ 0.638911] Advanced Linux Sound Architecture Driver Initialized.
10545 00:57:41.344680 <6>[ 0.645691] vgaarb: loaded
10546 00:57:41.350860 <6>[ 0.648845] clocksource: Switched to clocksource arch_sys_counter
10547 00:57:41.354606 <5>[ 0.655289] VFS: Disk quotas dquot_6.6.0
10548 00:57:41.361089 <6>[ 0.659476] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10549 00:57:41.363777 <6>[ 0.666668] pnp: PnP ACPI: disabled
10550 00:57:41.372647 <6>[ 0.673402] NET: Registered PF_INET protocol family
10551 00:57:41.382478 <6>[ 0.678997] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10552 00:57:41.393518 <6>[ 0.691332] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10553 00:57:41.404294 <6>[ 0.700146] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10554 00:57:41.410013 <6>[ 0.708123] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10555 00:57:41.420863 <6>[ 0.716826] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10556 00:57:41.426934 <6>[ 0.726586] TCP: Hash tables configured (established 65536 bind 65536)
10557 00:57:41.433030 <6>[ 0.733452] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10558 00:57:41.443454 <6>[ 0.740648] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 00:57:41.450719 <6>[ 0.748353] NET: Registered PF_UNIX/PF_LOCAL protocol family
10560 00:57:41.456771 <6>[ 0.754507] RPC: Registered named UNIX socket transport module.
10561 00:57:41.459499 <6>[ 0.760658] RPC: Registered udp transport module.
10562 00:57:41.465971 <6>[ 0.765591] RPC: Registered tcp transport module.
10563 00:57:41.473114 <6>[ 0.770521] RPC: Registered tcp NFSv4.1 backchannel transport module.
10564 00:57:41.476241 <6>[ 0.777188] PCI: CLS 0 bytes, default 64
10565 00:57:41.479158 <6>[ 0.781503] Unpacking initramfs...
10566 00:57:41.495816 <6>[ 0.793393] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10567 00:57:41.506465 <6>[ 0.802074] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10568 00:57:41.509329 <6>[ 0.810928] kvm [1]: IPA Size Limit: 40 bits
10569 00:57:41.515582 <6>[ 0.815461] kvm [1]: GICv3: no GICV resource entry
10570 00:57:41.518761 <6>[ 0.820482] kvm [1]: disabling GICv2 emulation
10571 00:57:41.525737 <6>[ 0.825168] kvm [1]: GIC system register CPU interface enabled
10572 00:57:41.533633 <6>[ 0.832900] kvm [1]: vgic interrupt IRQ18
10573 00:57:41.535422 <6>[ 0.837304] kvm [1]: VHE mode initialized successfully
10574 00:57:41.543330 <5>[ 0.843776] Initialise system trusted keyrings
10575 00:57:41.549571 <6>[ 0.848575] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10576 00:57:41.557868 <6>[ 0.858573] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10577 00:57:41.564764 <5>[ 0.865008] NFS: Registering the id_resolver key type
10578 00:57:41.567816 <5>[ 0.870303] Key type id_resolver registered
10579 00:57:41.574324 <5>[ 0.874716] Key type id_legacy registered
10580 00:57:41.580912 <6>[ 0.878996] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10581 00:57:41.587815 <6>[ 0.885918] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10582 00:57:41.594382 <6>[ 0.893663] 9p: Installing v9fs 9p2000 file system support
10583 00:57:41.631113 <5>[ 0.931863] Key type asymmetric registered
10584 00:57:41.634269 <5>[ 0.936197] Asymmetric key parser 'x509' registered
10585 00:57:41.644900 <6>[ 0.941341] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10586 00:57:41.649294 <6>[ 0.948958] io scheduler mq-deadline registered
10587 00:57:41.650889 <6>[ 0.953720] io scheduler kyber registered
10588 00:57:41.669595 <6>[ 0.970626] EINJ: ACPI disabled.
10589 00:57:41.702808 <4>[ 0.996785] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 00:57:41.712380 <4>[ 1.007437] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 00:57:41.728228 <6>[ 1.028486] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10592 00:57:41.735945 <6>[ 1.036555] printk: console [ttyS0] disabled
10593 00:57:41.764054 <6>[ 1.061201] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10594 00:57:41.770071 <6>[ 1.070693] printk: console [ttyS0] enabled
10595 00:57:41.773014 <6>[ 1.070693] printk: console [ttyS0] enabled
10596 00:57:41.780038 <6>[ 1.079587] printk: bootconsole [mtk8250] disabled
10597 00:57:41.783479 <6>[ 1.079587] printk: bootconsole [mtk8250] disabled
10598 00:57:41.790202 <6>[ 1.090855] SuperH (H)SCI(F) driver initialized
10599 00:57:41.793478 <6>[ 1.096155] msm_serial: driver initialized
10600 00:57:41.807446 <6>[ 1.105181] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10601 00:57:41.817845 <6>[ 1.113728] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10602 00:57:41.824285 <6>[ 1.122270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10603 00:57:41.833845 <6>[ 1.130900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10604 00:57:41.844180 <6>[ 1.139607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10605 00:57:41.850581 <6>[ 1.148329] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10606 00:57:41.860485 <6>[ 1.156871] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10607 00:57:41.867413 <6>[ 1.165675] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10608 00:57:41.877727 <6>[ 1.174219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10609 00:57:41.889587 <6>[ 1.189995] loop: module loaded
10610 00:57:41.895300 <6>[ 1.196082] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10611 00:57:41.918542 <4>[ 1.219358] mtk-pmic-keys: Failed to locate of_node [id: -1]
10612 00:57:41.925761 <6>[ 1.226253] megasas: 07.719.03.00-rc1
10613 00:57:41.934674 <6>[ 1.235751] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10614 00:57:41.947555 <6>[ 1.248228] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10615 00:57:41.963769 <6>[ 1.264509] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10616 00:57:42.024062 <6>[ 1.318162] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10617 00:57:42.268770 <6>[ 1.569354] Freeing initrd memory: 18324K
10618 00:57:42.280212 <6>[ 1.580887] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10619 00:57:42.290779 <6>[ 1.591805] tun: Universal TUN/TAP device driver, 1.6
10620 00:57:42.294113 <6>[ 1.597857] thunder_xcv, ver 1.0
10621 00:57:42.297593 <6>[ 1.601360] thunder_bgx, ver 1.0
10622 00:57:42.300433 <6>[ 1.604856] nicpf, ver 1.0
10623 00:57:42.311545 <6>[ 1.608863] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10624 00:57:42.314773 <6>[ 1.616339] hns3: Copyright (c) 2017 Huawei Corporation.
10625 00:57:42.321175 <6>[ 1.621925] hclge is initializing
10626 00:57:42.324467 <6>[ 1.625504] e1000: Intel(R) PRO/1000 Network Driver
10627 00:57:42.331083 <6>[ 1.630633] e1000: Copyright (c) 1999-2006 Intel Corporation.
10628 00:57:42.334254 <6>[ 1.636659] e1000e: Intel(R) PRO/1000 Network Driver
10629 00:57:42.341597 <6>[ 1.641874] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10630 00:57:42.348549 <6>[ 1.648062] igb: Intel(R) Gigabit Ethernet Network Driver
10631 00:57:42.354503 <6>[ 1.653712] igb: Copyright (c) 2007-2014 Intel Corporation.
10632 00:57:42.360714 <6>[ 1.659549] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10633 00:57:42.367071 <6>[ 1.666066] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10634 00:57:42.370759 <6>[ 1.672527] sky2: driver version 1.30
10635 00:57:42.377805 <6>[ 1.677518] VFIO - User Level meta-driver version: 0.3
10636 00:57:42.384913 <6>[ 1.685744] usbcore: registered new interface driver usb-storage
10637 00:57:42.391255 <6>[ 1.692188] usbcore: registered new device driver onboard-usb-hub
10638 00:57:42.400156 <6>[ 1.701319] mt6397-rtc mt6359-rtc: registered as rtc0
10639 00:57:42.410877 <6>[ 1.706787] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T00:57:43 UTC (1705625863)
10640 00:57:42.413646 <6>[ 1.716346] i2c_dev: i2c /dev entries driver
10641 00:57:42.430915 <6>[ 1.728007] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10642 00:57:42.450680 <6>[ 1.751992] cpu cpu0: EM: created perf domain
10643 00:57:42.453870 <6>[ 1.756935] cpu cpu4: EM: created perf domain
10644 00:57:42.461716 <6>[ 1.762519] sdhci: Secure Digital Host Controller Interface driver
10645 00:57:42.468322 <6>[ 1.768955] sdhci: Copyright(c) Pierre Ossman
10646 00:57:42.475132 <6>[ 1.773897] Synopsys Designware Multimedia Card Interface Driver
10647 00:57:42.481034 <6>[ 1.780527] sdhci-pltfm: SDHCI platform and OF driver helper
10648 00:57:42.485009 <6>[ 1.780642] mmc0: CQHCI version 5.10
10649 00:57:42.491186 <6>[ 1.790504] ledtrig-cpu: registered to indicate activity on CPUs
10650 00:57:42.498020 <6>[ 1.797460] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10651 00:57:42.504622 <6>[ 1.804508] usbcore: registered new interface driver usbhid
10652 00:57:42.507497 <6>[ 1.810330] usbhid: USB HID core driver
10653 00:57:42.514321 <6>[ 1.814525] spi_master spi0: will run message pump with realtime priority
10654 00:57:42.561487 <6>[ 1.855934] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10655 00:57:42.581048 <6>[ 1.872223] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10656 00:57:42.584678 <6>[ 1.885789] mmc0: Command Queue Engine enabled
10657 00:57:42.591248 <6>[ 1.890553] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10658 00:57:42.598233 <6>[ 1.897473] cros-ec-spi spi0.0: Chrome EC device registered
10659 00:57:42.601482 <6>[ 1.897845] mmcblk0: mmc0:0001 DA4128 116 GiB
10660 00:57:42.613188 <6>[ 1.914507] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10661 00:57:42.620614 <6>[ 1.921859] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10662 00:57:42.627236 <6>[ 1.927795] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10663 00:57:42.633927 <6>[ 1.933740] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10664 00:57:42.649362 <6>[ 1.947635] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 00:57:42.657283 <6>[ 1.958325] NET: Registered PF_PACKET protocol family
10666 00:57:42.660118 <6>[ 1.963727] 9pnet: Installing 9P2000 support
10667 00:57:42.667335 <5>[ 1.968289] Key type dns_resolver registered
10668 00:57:42.670504 <6>[ 1.973284] registered taskstats version 1
10669 00:57:42.677170 <5>[ 1.977676] Loading compiled-in X.509 certificates
10670 00:57:42.708097 <4>[ 2.002283] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 00:57:42.718020 <4>[ 2.013166] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10672 00:57:42.724009 <3>[ 2.023710] debugfs: File 'uA_load' in directory '/' already present!
10673 00:57:42.731115 <3>[ 2.030415] debugfs: File 'min_uV' in directory '/' already present!
10674 00:57:42.737748 <3>[ 2.037026] debugfs: File 'max_uV' in directory '/' already present!
10675 00:57:42.743879 <3>[ 2.043638] debugfs: File 'constraint_flags' in directory '/' already present!
10676 00:57:42.755847 <3>[ 2.053459] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10677 00:57:42.767853 <6>[ 2.069153] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10678 00:57:42.774922 <6>[ 2.076052] xhci-mtk 11200000.usb: xHCI Host Controller
10679 00:57:42.781591 <6>[ 2.081555] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10680 00:57:42.791528 <6>[ 2.089408] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10681 00:57:42.798359 <6>[ 2.098820] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10682 00:57:42.804426 <6>[ 2.104888] xhci-mtk 11200000.usb: xHCI Host Controller
10683 00:57:42.811390 <6>[ 2.110365] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10684 00:57:42.817930 <6>[ 2.118012] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10685 00:57:42.824282 <6>[ 2.125607] hub 1-0:1.0: USB hub found
10686 00:57:42.827835 <6>[ 2.129617] hub 1-0:1.0: 1 port detected
10687 00:57:42.838128 <6>[ 2.133891] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10688 00:57:42.841351 <6>[ 2.142383] hub 2-0:1.0: USB hub found
10689 00:57:42.844349 <6>[ 2.146388] hub 2-0:1.0: 1 port detected
10690 00:57:42.851608 <6>[ 2.153298] mtk-msdc 11f70000.mmc: Got CD GPIO
10691 00:57:42.864256 <6>[ 2.162323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10692 00:57:42.870814 <6>[ 2.170361] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10693 00:57:42.880965 <4>[ 2.178259] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10694 00:57:42.891201 <6>[ 2.187781] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10695 00:57:42.897363 <6>[ 2.195858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10696 00:57:42.903935 <6>[ 2.203973] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10697 00:57:42.914128 <6>[ 2.211898] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10698 00:57:42.920731 <6>[ 2.219715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10699 00:57:42.930778 <6>[ 2.227537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10700 00:57:42.940742 <6>[ 2.238034] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10701 00:57:42.947023 <6>[ 2.246422] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10702 00:57:42.957365 <6>[ 2.254761] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10703 00:57:42.963819 <6>[ 2.263100] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10704 00:57:42.973891 <6>[ 2.271439] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10705 00:57:42.981160 <6>[ 2.279781] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10706 00:57:42.990306 <6>[ 2.288120] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10707 00:57:43.000364 <6>[ 2.296458] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10708 00:57:43.007549 <6>[ 2.304797] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10709 00:57:43.016803 <6>[ 2.313139] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10710 00:57:43.023928 <6>[ 2.321478] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10711 00:57:43.033325 <6>[ 2.329830] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10712 00:57:43.040216 <6>[ 2.338174] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10713 00:57:43.049654 <6>[ 2.346513] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10714 00:57:43.056648 <6>[ 2.354851] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10715 00:57:43.062685 <6>[ 2.363633] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10716 00:57:43.069778 <6>[ 2.370791] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10717 00:57:43.076625 <6>[ 2.377544] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10718 00:57:43.086049 <6>[ 2.384311] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10719 00:57:43.092731 <6>[ 2.391246] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10720 00:57:43.099580 <6>[ 2.398107] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10721 00:57:43.110621 <6>[ 2.407236] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10722 00:57:43.119589 <6>[ 2.416355] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10723 00:57:43.128934 <6>[ 2.425652] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10724 00:57:43.138736 <6>[ 2.435121] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10725 00:57:43.149281 <6>[ 2.444587] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10726 00:57:43.155625 <6>[ 2.453706] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10727 00:57:43.165138 <6>[ 2.463171] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10728 00:57:43.175834 <6>[ 2.472290] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10729 00:57:43.185048 <6>[ 2.481584] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10730 00:57:43.194743 <6>[ 2.491743] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10731 00:57:43.205415 <6>[ 2.503392] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10732 00:57:43.211748 <6>[ 2.513059] Trying to probe devices needed for running init ...
10733 00:57:43.235022 <6>[ 2.533170] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10734 00:57:43.263353 <6>[ 2.564748] hub 2-1:1.0: USB hub found
10735 00:57:43.266906 <6>[ 2.569233] hub 2-1:1.0: 3 ports detected
10736 00:57:43.275345 <6>[ 2.576462] hub 2-1:1.0: USB hub found
10737 00:57:43.278907 <6>[ 2.580789] hub 2-1:1.0: 3 ports detected
10738 00:57:43.386718 <6>[ 2.685114] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10739 00:57:43.545841 <6>[ 2.847207] hub 1-1:1.0: USB hub found
10740 00:57:43.549495 <6>[ 2.851769] hub 1-1:1.0: 4 ports detected
10741 00:57:43.559242 <6>[ 2.860414] hub 1-1:1.0: USB hub found
10742 00:57:43.562873 <6>[ 2.864721] hub 1-1:1.0: 4 ports detected
10743 00:57:43.883577 <6>[ 3.181165] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10744 00:57:44.014101 <6>[ 3.315352] hub 1-1.1:1.0: USB hub found
10745 00:57:44.017391 <6>[ 3.319696] hub 1-1.1:1.0: 4 ports detected
10746 00:57:44.131455 <6>[ 3.429257] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10747 00:57:44.263656 <6>[ 3.564765] hub 1-1.4:1.0: USB hub found
10748 00:57:44.266623 <6>[ 3.569428] hub 1-1.4:1.0: 2 ports detected
10749 00:57:44.275667 <6>[ 3.577414] hub 1-1.4:1.0: USB hub found
10750 00:57:44.279487 <6>[ 3.582009] hub 1-1.4:1.0: 2 ports detected
10751 00:57:44.343499 <6>[ 3.641123] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10752 00:57:44.575478 <6>[ 3.873161] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10753 00:57:44.767144 <6>[ 4.065164] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10754 00:57:55.492632 <6>[ 14.798138] ALSA device list:
10755 00:57:55.499122 <6>[ 14.801425] No soundcards found.
10756 00:57:55.507187 <6>[ 14.809402] Freeing unused kernel memory: 8448K
10757 00:57:55.510087 <6>[ 14.814426] Run /init as init process
10758 00:57:55.521731 Loading, please wait...
10759 00:57:55.548347 Starting systemd-udevd version 252.19-1~deb12u1
10760 00:57:55.782609 <6>[ 15.081790] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10761 00:57:55.827967 <6>[ 15.130001] remoteproc remoteproc0: scp is available
10762 00:57:55.834569 <6>[ 15.135475] remoteproc remoteproc0: powering up scp
10763 00:57:55.840963 <6>[ 15.136365] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10764 00:57:55.851343 <6>[ 15.140642] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10765 00:57:55.858187 <6>[ 15.148204] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10766 00:57:55.864696 <6>[ 15.156870] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10767 00:57:55.870926 <6>[ 15.165363] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10768 00:57:55.880891 <4>[ 15.172484] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10769 00:57:55.887215 <3>[ 15.181695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 00:57:55.894127 <6>[ 15.189905] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10771 00:57:55.904244 <4>[ 15.190136] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10772 00:57:55.910748 <3>[ 15.195251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 00:57:55.920326 <3>[ 15.195265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 00:57:55.923236 <6>[ 15.226909] mc: Linux media interface: v0.10
10775 00:57:55.933721 <3>[ 15.232480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 00:57:55.943029 <4>[ 15.240126] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10777 00:57:55.946562 <4>[ 15.240126] Fallback method does not support PEC.
10778 00:57:55.954460 <3>[ 15.240936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 00:57:55.963933 <3>[ 15.262662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 00:57:55.971661 <6>[ 15.266171] videodev: Linux video capture interface: v2.00
10781 00:57:55.977946 <3>[ 15.270799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 00:57:55.984625 <3>[ 15.270813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 00:57:55.995657 <3>[ 15.272156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 00:57:56.001277 <3>[ 15.275443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10785 00:57:56.008202 <6>[ 15.279725] usbcore: registered new device driver r8152-cfgselector
10786 00:57:56.018106 <3>[ 15.285198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 00:57:56.024658 <6>[ 15.286223] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10788 00:57:56.031724 <6>[ 15.286227] pci_bus 0000:00: root bus resource [bus 00-ff]
10789 00:57:56.038547 <6>[ 15.286232] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10790 00:57:56.047855 <6>[ 15.286234] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10791 00:57:56.054020 <6>[ 15.286260] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10792 00:57:56.060840 <6>[ 15.286274] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10793 00:57:56.063974 <6>[ 15.286336] pci 0000:00:00.0: supports D1 D2
10794 00:57:56.070467 <6>[ 15.286338] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10795 00:57:56.080388 <6>[ 15.287281] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10796 00:57:56.087488 <6>[ 15.287383] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10797 00:57:56.093655 <6>[ 15.287408] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10798 00:57:56.100390 <6>[ 15.287427] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10799 00:57:56.110328 <6>[ 15.287442] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10800 00:57:56.113668 <6>[ 15.287550] pci 0000:01:00.0: supports D1 D2
10801 00:57:56.120140 <6>[ 15.287551] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10802 00:57:56.129681 <3>[ 15.296534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 00:57:56.140083 <6>[ 15.297102] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10804 00:57:56.146397 <3>[ 15.300959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 00:57:56.152887 <3>[ 15.300966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 00:57:56.163288 <3>[ 15.301017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 00:57:56.169547 <3>[ 15.301021] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 00:57:56.179344 <3>[ 15.301024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 00:57:56.186079 <3>[ 15.301030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 00:57:56.196146 <3>[ 15.301033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 00:57:56.202262 <3>[ 15.301055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 00:57:56.208841 <6>[ 15.304931] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10813 00:57:56.215782 <6>[ 15.305573] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10814 00:57:56.225772 <6>[ 15.305699] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10815 00:57:56.232315 <6>[ 15.305705] remoteproc remoteproc0: remote processor scp is now up
10816 00:57:56.238705 <6>[ 15.310993] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10817 00:57:56.248522 <6>[ 15.313409] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10818 00:57:56.258602 <6>[ 15.313739] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10819 00:57:56.268151 <6>[ 15.316754] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10820 00:57:56.274919 <6>[ 15.327828] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10821 00:57:56.285244 <6>[ 15.331733] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10822 00:57:56.287818 <6>[ 15.361461] Bluetooth: Core ver 2.22
10823 00:57:56.294910 <6>[ 15.368126] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10824 00:57:56.304397 <6>[ 15.368144] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10825 00:57:56.311783 <6>[ 15.368158] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10826 00:57:56.317888 <6>[ 15.372959] NET: Registered PF_BLUETOOTH protocol family
10827 00:57:56.324891 <6>[ 15.373213] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10828 00:57:56.338467 <6>[ 15.374428] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10829 00:57:56.341036 <6>[ 15.374525] usbcore: registered new interface driver uvcvideo
10830 00:57:56.351079 <6>[ 15.376997] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10831 00:57:56.357179 <6>[ 15.379548] pci 0000:00:00.0: PCI bridge to [bus 01]
10832 00:57:56.364102 <6>[ 15.387792] Bluetooth: HCI device and connection manager initialized
10833 00:57:56.370823 <6>[ 15.394047] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10834 00:57:56.377382 <6>[ 15.401528] Bluetooth: HCI socket layer initialized
10835 00:57:56.383811 <6>[ 15.409217] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10836 00:57:56.387260 <6>[ 15.409530] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10837 00:57:56.394132 <6>[ 15.416455] Bluetooth: L2CAP socket layer initialized
10838 00:57:56.400538 <6>[ 15.421483] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10839 00:57:56.404638 <6>[ 15.427842] Bluetooth: SCO socket layer initialized
10840 00:57:56.410334 <6>[ 15.436855] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10841 00:57:56.420370 <4>[ 15.480753] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10842 00:57:56.427241 <6>[ 15.495009] usbcore: registered new interface driver btusb
10843 00:57:56.437044 <4>[ 15.495582] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10844 00:57:56.443398 <3>[ 15.495590] Bluetooth: hci0: Failed to load firmware file (-2)
10845 00:57:56.449765 <3>[ 15.495594] Bluetooth: hci0: Failed to set up firmware (-2)
10846 00:57:56.460531 <4>[ 15.495597] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10847 00:57:56.467019 <4>[ 15.502486] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10848 00:57:56.476641 <5>[ 15.504225] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10849 00:57:56.479949 <6>[ 15.561178] r8152 1-1.1.1:1.0 eth0: v1.12.13
10850 00:57:56.486485 <5>[ 15.581905] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10851 00:57:56.493254 <6>[ 15.583331] usbcore: registered new interface driver r8152
10852 00:57:56.500236 <5>[ 15.591457] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10853 00:57:56.506164 <6>[ 15.611317] usbcore: registered new interface driver cdc_ether
10854 00:57:56.516301 <4>[ 15.619067] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10855 00:57:56.522908 <6>[ 15.631966] usbcore: registered new interface driver r8153_ecm
10856 00:57:56.526204 <6>[ 15.644293] cfg80211: failed to load regulatory.db
10857 00:57:56.533083 <6>[ 15.668127] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10858 00:57:56.539360 <6>[ 15.710391] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10859 00:57:56.545953 <6>[ 15.848135] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10860 00:57:56.570598 <6>[ 15.873082] mt7921e 0000:01:00.0: ASIC revision: 79610010
10861 00:57:56.673639 <6>[ 15.972744] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10862 00:57:56.676296 <6>[ 15.972744]
10863 00:57:56.679700 Begin: Loading essential drivers ... done.
10864 00:57:56.682946 Begin: Running /scripts/init-premount ... done.
10865 00:57:56.689563 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10866 00:57:56.699828 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10867 00:57:56.702804 Device /sys/class/net/enxf4f5e850de0a found
10868 00:57:56.702884 done.
10869 00:57:56.709413 Begin: Waiting up to 180 secs for any network device to become available ... done.
10870 00:57:56.757623 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10871 00:57:56.940184 <6>[ 16.239414] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10872 00:57:57.814259 <6>[ 17.117071] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10873 00:57:57.885516 <6>[ 17.187504] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10874 00:57:57.903885 IP-Config: no response after 2 secs - giving up
10875 00:57:57.934496 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10876 00:57:58.653961 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10877 00:57:58.660382 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10878 00:57:58.666946 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10879 00:57:58.674454 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10880 00:57:58.680060 host : mt8192-asurada-spherion-r0-cbg-9
10881 00:57:58.686281 domain : lava-rack
10882 00:57:58.689893 rootserver: 192.168.201.1 rootpath:
10883 00:57:58.690573 filename :
10884 00:57:58.769903 done.
10885 00:57:58.776967 Begin: Running /scripts/nfs-bottom ... done.
10886 00:57:58.799220 Begin: Running /scripts/init-bottom ... done.
10887 00:58:00.128361 <6>[ 19.431053] NET: Registered PF_INET6 protocol family
10888 00:58:00.135780 <6>[ 19.438899] Segment Routing with IPv6
10889 00:58:00.138873 <6>[ 19.442877] In-situ OAM (IOAM) with IPv6
10890 00:58:00.315022 <30>[ 19.591225] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10891 00:58:00.321257 <30>[ 19.624389] systemd[1]: Detected architecture arm64.
10892 00:58:00.337361
10893 00:58:00.340841 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10894 00:58:00.341443
10895 00:58:00.367560 <30>[ 19.670429] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10896 00:58:01.352834 <30>[ 20.653142] systemd[1]: Queued start job for default target graphical.target.
10897 00:58:01.402728 <30>[ 20.702579] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10898 00:58:01.408888 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10899 00:58:01.431099 <30>[ 20.730972] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10900 00:58:01.441222 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10901 00:58:01.458490 <30>[ 20.758889] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10902 00:58:01.468660 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10903 00:58:01.486788 <30>[ 20.786485] systemd[1]: Created slice user.slice - User and Session Slice.
10904 00:58:01.492993 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10905 00:58:01.517572 <30>[ 20.814040] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10906 00:58:01.527199 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10907 00:58:01.545107 <30>[ 20.841389] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10908 00:58:01.551059 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10909 00:58:01.580147 <30>[ 20.869829] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10910 00:58:01.589645 <30>[ 20.889852] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10911 00:58:01.596412 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10912 00:58:01.617239 <30>[ 20.917635] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10913 00:58:01.627461 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10914 00:58:01.642536 <30>[ 20.945716] systemd[1]: Reached target paths.target - Path Units.
10915 00:58:01.649137 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10916 00:58:01.669807 <30>[ 20.969619] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10917 00:58:01.676160 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10918 00:58:01.689438 <30>[ 20.993130] systemd[1]: Reached target slices.target - Slice Units.
10919 00:58:01.699739 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10920 00:58:01.714238 <30>[ 21.017641] systemd[1]: Reached target swap.target - Swaps.
10921 00:58:01.721052 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10922 00:58:01.741669 <30>[ 21.041638] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10923 00:58:01.751122 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10924 00:58:01.770176 <30>[ 21.070109] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10925 00:58:01.780303 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10926 00:58:01.799555 <30>[ 21.099911] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10927 00:58:01.809607 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10928 00:58:01.826899 <30>[ 21.127082] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10929 00:58:01.837029 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10930 00:58:01.854439 <30>[ 21.154485] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10931 00:58:01.860745 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10932 00:58:01.883175 <30>[ 21.182733] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10933 00:58:01.892517 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10934 00:58:01.911783 <30>[ 21.211753] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10935 00:58:01.921634 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10936 00:58:01.937566 <30>[ 21.237629] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10937 00:58:01.947633 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10938 00:58:01.989152 <30>[ 21.289205] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10939 00:58:01.995473 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10940 00:58:02.017959 <30>[ 21.317895] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10941 00:58:02.024324 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10942 00:58:02.081512 <30>[ 21.381558] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10943 00:58:02.088102 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10944 00:58:02.115657 <30>[ 21.409595] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10945 00:58:02.131505 <30>[ 21.431286] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10946 00:58:02.140965 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10947 00:58:02.162060 <30>[ 21.462558] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10948 00:58:02.168890 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10949 00:58:02.194623 <30>[ 21.494509] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10950 00:58:02.201095 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10951 00:58:02.225370 <30>[ 21.525471] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10952 00:58:02.239117 Starting [0;1;39mmodpr<6>[ 21.535303] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10953 00:58:02.241888 obe@drm.service[0m - Load Kernel Module drm...
10954 00:58:02.266297 <30>[ 21.566621] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10955 00:58:02.276328 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10956 00:58:02.318402 <30>[ 21.617974] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10957 00:58:02.324269 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10958 00:58:02.351275 <30>[ 21.651402] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10959 00:58:02.357853 Startin<6>[ 21.660806] fuse: init (API version 7.37)
10960 00:58:02.361478 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10961 00:58:02.390836 <30>[ 21.691143] systemd[1]: Starting systemd-journald.service - Journal Service...
10962 00:58:02.397442 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10963 00:58:02.429094 <30>[ 21.729346] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10964 00:58:02.436189 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10965 00:58:02.466245 <30>[ 21.763354] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10966 00:58:02.472650 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10967 00:58:02.522225 <30>[ 21.822044] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10968 00:58:02.535589 Starting [0;1;39msyste<3>[ 21.833834] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 00:58:02.538817 md-remount-f…nt Root and Kernel File Systems...
10970 00:58:02.560818 <30>[ 21.860168] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10971 00:58:02.573315 Starting [0;1;39msyste<3>[ 21.871431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 00:58:02.576517 md-udev-trig…[0m - Coldplug All udev Devices...
10973 00:58:02.600784 <30>[ 21.900469] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10974 00:58:02.607620 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10975 00:58:02.625189 <3>[ 21.925278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 00:58:02.634724 <30>[ 21.925497] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10977 00:58:02.641440 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10978 00:58:02.654368 <3>[ 21.954745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 00:58:02.664185 <30>[ 21.964312] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10980 00:58:02.671080 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10981 00:58:02.686586 <3>[ 21.987108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 00:58:02.697602 <30>[ 21.997768] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10983 00:58:02.707666 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10984 00:58:02.720775 <3>[ 22.020788] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 00:58:02.731824 <30>[ 22.031500] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10986 00:58:02.741420 <30>[ 22.040010] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10987 00:58:02.755121 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 22.053538] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 00:58:02.758200 Load Kernel Module configfs.
10989 00:58:02.773813 <30>[ 22.073847] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10990 00:58:02.780909 <30>[ 22.081646] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10991 00:58:02.790630 <3>[ 22.086690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 00:58:02.796949 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10993 00:58:02.818238 <30>[ 22.117981] systemd[1]: modprobe@drm.service: Deactivated successfully.
10994 00:58:02.824592 <3>[ 22.123909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 00:58:02.834599 <30>[ 22.125765] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10996 00:58:02.840774 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10997 00:58:02.858655 <30>[ 22.158786] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10998 00:58:02.864990 <3>[ 22.159270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 00:58:02.874822 <30>[ 22.167348] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11000 00:58:02.885656 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11001 00:58:02.901811 <30>[ 22.202156] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11002 00:58:02.908888 <30>[ 22.209914] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11003 00:58:02.918688 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11004 00:58:02.933972 <30>[ 22.233824] systemd[1]: Started systemd-journald.service - Journal Service.
11005 00:58:02.940205 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11006 00:58:02.962385 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11007 00:58:02.983660 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11008 00:58:03.012664 [[0;32m OK [<4>[ 22.304078] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11009 00:58:03.019181 <3>[ 22.320141] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11010 00:58:03.025804 0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11011 00:58:03.047367 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11012 00:58:03.067217 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11013 00:58:03.087962 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11014 00:58:03.146172 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11015 00:58:03.167389 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11016 00:58:03.194794 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11017 00:58:03.225997 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11018 00:58:03.242571 <46>[ 22.543023] systemd-journald[311]: Received client request to flush runtime journal.
11019 00:58:03.260816 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11020 00:58:03.287215 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11021 00:58:03.578347 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11022 00:58:03.597920 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11023 00:58:03.614096 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11024 00:58:04.030231 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11025 00:58:04.656706 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11026 00:58:04.679245 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11027 00:58:04.742132 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11028 00:58:04.807175 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11029 00:58:04.825119 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11030 00:58:04.844979 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11031 00:58:04.905580 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11032 00:58:04.929125 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11033 00:58:04.948693 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11034 00:58:04.971565 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11035 00:58:04.985442 See 'systemctl status systemd-binfmt.service' for details.
11036 00:58:05.156000 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11037 00:58:05.234382 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11038 00:58:05.255823 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11039 00:58:05.316350 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11040 00:58:05.494472 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11041 00:58:05.528355 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11042 00:58:05.689210 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11043 00:58:05.725647 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11044 00:58:05.745522 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11045 00:58:05.798274 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11046 00:58:05.817474 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11047 00:58:05.849635 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11048 00:58:05.873246 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11049 00:58:05.897063 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11050 00:58:05.905143 <46>[ 25.209074] systemd-journald[311]: Time jumped backwards, rotating.
11051 00:58:05.915615 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11052 00:58:05.933578 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11053 00:58:05.954220 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11054 00:58:05.978721 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11055 00:58:06.351339 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11056 00:58:06.369005 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11057 00:58:06.708897 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11058 00:58:07.039092 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11059 00:58:07.060886 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11060 00:58:07.076463 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11061 00:58:07.331091 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11062 00:58:07.348746 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11063 00:58:07.364720 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11064 00:58:07.438096 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11065 00:58:07.471012 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11066 00:58:07.573272 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11067 00:58:07.597401 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11068 00:58:07.622656 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11069 00:58:07.757439 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11070 00:58:07.796590 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11071 00:58:07.841385 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11072 00:58:07.865878 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11073 00:58:07.889776 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11074 00:58:07.925373 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11075 00:58:07.951474 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11076 00:58:07.972843 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11077 00:58:08.001194 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11078 00:58:08.022634 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11079 00:58:08.078121 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11080 00:58:08.103140 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11081 00:58:08.143285 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11082 00:58:08.230481 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11083 00:58:08.300191
11084 00:58:08.300342
11085 00:58:08.303491 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11086 00:58:08.303582
11087 00:58:08.306388 debian-bookworm-arm64 login: root (automatic login)
11088 00:58:08.306469
11089 00:58:08.306533
11090 00:58:08.575465 Linux debian-bookworm-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
11091 00:58:08.575614
11092 00:58:08.582179 The programs included with the Debian GNU/Linux system are free software;
11093 00:58:08.588875 the exact distribution terms for each program are described in the
11094 00:58:08.592592 individual files in /usr/share/doc/*/copyright.
11095 00:58:08.592679
11096 00:58:08.598690 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11097 00:58:08.603005 permitted by applicable law.
11098 00:58:09.528718 Matched prompt #10: / #
11100 00:58:09.528988 Setting prompt string to ['/ #']
11101 00:58:09.529083 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11103 00:58:09.529277 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11104 00:58:09.529395 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11105 00:58:09.529491 Setting prompt string to ['/ #']
11106 00:58:09.529576 Forcing a shell prompt, looking for ['/ #']
11108 00:58:09.579829 / #
11109 00:58:09.579995 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11110 00:58:09.580148 Waiting using forced prompt support (timeout 00:02:30)
11111 00:58:09.584492
11112 00:58:09.584772 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11113 00:58:09.584869 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11115 00:58:09.685234 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx'
11116 00:58:09.691633 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571069/extract-nfsrootfs-rjj_e7gx'
11118 00:58:09.792203 / # export NFS_SERVER_IP='192.168.201.1'
11119 00:58:09.797696 export NFS_SERVER_IP='192.168.201.1'
11120 00:58:09.797981 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11121 00:58:09.798077 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11122 00:58:09.798164 end: 2 depthcharge-action (duration 00:01:26) [common]
11123 00:58:09.798253 start: 3 lava-test-retry (timeout 00:07:48) [common]
11124 00:58:09.798339 start: 3.1 lava-test-shell (timeout 00:07:48) [common]
11125 00:58:09.798411 Using namespace: common
11127 00:58:09.898761 / # #
11128 00:58:09.898938 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11129 00:58:09.904319 #
11130 00:58:09.904592 Using /lava-12571069
11132 00:58:10.004941 / # export SHELL=/bin/bash
11133 00:58:10.010137 export SHELL=/bin/bash
11135 00:58:10.110652 / # . /lava-12571069/environment
11136 00:58:10.116229 . /lava-12571069/environment
11138 00:58:10.223641 / # /lava-12571069/bin/lava-test-runner /lava-12571069/0
11139 00:58:10.223796 Test shell timeout: 10s (minimum of the action and connection timeout)
11140 00:58:10.228904 /lava-12571069/bin/lava-test-runner /lava-12571069/0
11141 00:58:10.457744 + export TESTRUN_ID=0_timesync-off
11142 00:58:10.460986 + TESTRUN_ID=0_timesync-off
11143 00:58:10.465037 + cd /lava-12571069/0/tests/0_timesync-off
11144 00:58:10.467403 ++ cat uuid
11145 00:58:10.470949 + UUID=12571069_1.6.2.3.1
11146 00:58:10.471031 + set +x
11147 00:58:10.473608 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12571069_1.6.2.3.1>
11148 00:58:10.473867 Received signal: <STARTRUN> 0_timesync-off 12571069_1.6.2.3.1
11149 00:58:10.473946 Starting test lava.0_timesync-off (12571069_1.6.2.3.1)
11150 00:58:10.474030 Skipping test definition patterns.
11151 00:58:10.477480 + systemctl stop systemd-timesyncd
11152 00:58:10.560510 + set +x
11153 00:58:10.563993 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12571069_1.6.2.3.1>
11154 00:58:10.564250 Received signal: <ENDRUN> 0_timesync-off 12571069_1.6.2.3.1
11155 00:58:10.564335 Ending use of test pattern.
11156 00:58:10.564396 Ending test lava.0_timesync-off (12571069_1.6.2.3.1), duration 0.09
11158 00:58:10.633244 + export TESTRUN_ID=1_kselftest-alsa
11159 00:58:10.636393 + TESTRUN_ID=1_kselftest-alsa
11160 00:58:10.639582 + cd /lava-12571069/0/tests/1_kselftest-alsa
11161 00:58:10.642907 ++ cat uuid
11162 00:58:10.646599 + UUID=12571069_1.6.2.3.5
11163 00:58:10.646681 + set +x
11164 00:58:10.653043 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12571069_1.6.2.3.5>
11165 00:58:10.653302 Received signal: <STARTRUN> 1_kselftest-alsa 12571069_1.6.2.3.5
11166 00:58:10.653376 Starting test lava.1_kselftest-alsa (12571069_1.6.2.3.5)
11167 00:58:10.653457 Skipping test definition patterns.
11168 00:58:10.656055 + cd ./automated/linux/kselftest/
11169 00:58:10.682500 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11170 00:58:10.711150 INFO: install_deps skipped
11171 00:58:11.195726 --2024-01-19 00:58:11-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11172 00:58:11.201601 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11173 00:58:11.324106 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11174 00:58:11.453540 HTTP request sent, awaiting response... 200 OK
11175 00:58:11.457286 Length: 2966476 (2.8M) [application/octet-stream]
11176 00:58:11.460975 Saving to: 'kselftest.tar.xz'
11177 00:58:11.461057
11178 00:58:11.461120
11179 00:58:11.711913 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11180 00:58:11.973150 kselftest.tar.xz 1%[ ] 47.81K 186KB/s
11181 00:58:12.409927 kselftest.tar.xz 7%[> ] 217.50K 420KB/s
11182 00:58:12.675015 kselftest.tar.xz 28%[====> ] 817.06K 855KB/s
11183 00:58:12.757822 kselftest.tar.xz 82%[===============> ] 2.32M 1.90MB/s
11184 00:58:12.764061 kselftest.tar.xz 100%[===================>] 2.83M 2.17MB/s in 1.3s
11185 00:58:12.764195
11186 00:58:13.021491 2024-01-19 00:58:13 (2.17 MB/s) - 'kselftest.tar.xz' saved [2966476/2966476]
11187 00:58:13.021666
11188 00:58:18.425595 skiplist:
11189 00:58:18.427726 ========================================
11190 00:58:18.430926 ========================================
11191 00:58:18.472478 alsa:mixer-test
11192 00:58:18.490962 ============== Tests to run ===============
11193 00:58:18.491049 alsa:mixer-test
11194 00:58:18.494830 ===========End Tests to run ===============
11195 00:58:18.498020 shardfile-alsa pass
11196 00:58:18.596954 <12>[ 37.902384] kselftest: Running tests in alsa
11197 00:58:18.604956 TAP version 13
11198 00:58:18.619206 1..1
11199 00:58:18.632683 # selftests: alsa: mixer-test
11200 00:58:19.129150 # TAP version 13
11201 00:58:19.129298 # 1..0
11202 00:58:19.134781 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11203 00:58:19.137784 ok 1 selftests: alsa: mixer-test
11204 00:58:19.850120 alsa_mixer-test pass
11205 00:58:19.893741 + ../../utils/send-to-lava.sh ./output/result.txt
11206 00:58:19.952755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11207 00:58:19.953035 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11209 00:58:19.995167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11210 00:58:19.995265 + set +x
11211 00:58:19.995505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11213 00:58:20.001550 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12571069_1.6.2.3.5>
11214 00:58:20.001832 Received signal: <ENDRUN> 1_kselftest-alsa 12571069_1.6.2.3.5
11215 00:58:20.001943 Ending use of test pattern.
11216 00:58:20.002031 Ending test lava.1_kselftest-alsa (12571069_1.6.2.3.5), duration 9.35
11218 00:58:20.006149 <LAVA_TEST_RUNNER EXIT>
11219 00:58:20.006399 ok: lava_test_shell seems to have completed
11220 00:58:20.006495 alsa_mixer-test: pass
shardfile-alsa: pass
11221 00:58:20.006580 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11222 00:58:20.006662 end: 3 lava-test-retry (duration 00:00:10) [common]
11223 00:58:20.006747 start: 4 finalize (timeout 00:07:37) [common]
11224 00:58:20.006839 start: 4.1 power-off (timeout 00:00:30) [common]
11225 00:58:20.006986 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11226 00:58:20.084502 >> Command sent successfully.
11227 00:58:20.087388 Returned 0 in 0 seconds
11228 00:58:20.187796 end: 4.1 power-off (duration 00:00:00) [common]
11230 00:58:20.188170 start: 4.2 read-feedback (timeout 00:07:37) [common]
11231 00:58:20.188441 Listened to connection for namespace 'common' for up to 1s
11232 00:58:21.189378 Finalising connection for namespace 'common'
11233 00:58:21.189562 Disconnecting from shell: Finalise
11234 00:58:21.189667 / #
11235 00:58:21.290003 end: 4.2 read-feedback (duration 00:00:01) [common]
11236 00:58:21.290175 end: 4 finalize (duration 00:00:01) [common]
11237 00:58:21.290307 Cleaning after the job
11238 00:58:21.290418 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/ramdisk
11239 00:58:21.293426 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/kernel
11240 00:58:21.306517 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/dtb
11241 00:58:21.306711 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/nfsrootfs
11242 00:58:21.407427 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571069/tftp-deploy-y3atqli7/modules
11243 00:58:21.414935 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571069
11244 00:58:22.077502 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571069
11245 00:58:22.077689 Job finished correctly