Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 17
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 00:59:21.933840 lava-dispatcher, installed at version: 2023.10
2 00:59:21.934058 start: 0 validate
3 00:59:21.934192 Start time: 2024-01-19 00:59:21.934184+00:00 (UTC)
4 00:59:21.934309 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:59:21.934440 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 00:59:22.205019 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:59:22.205863 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:59:22.476383 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:59:22.477086 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:59:22.747817 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:59:22.748558 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:59:23.019538 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:59:23.020249 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:59:23.290282 validate duration: 1.36
16 00:59:23.290536 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:59:23.290636 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:59:23.290789 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:59:23.290995 Not decompressing ramdisk as can be used compressed.
20 00:59:23.291081 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 00:59:23.291151 saving as /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/ramdisk/initrd.cpio.gz
22 00:59:23.291220 total size: 4665395 (4 MB)
23 00:59:23.292291 progress 0 % (0 MB)
24 00:59:23.293895 progress 5 % (0 MB)
25 00:59:23.295190 progress 10 % (0 MB)
26 00:59:23.296432 progress 15 % (0 MB)
27 00:59:23.297712 progress 20 % (0 MB)
28 00:59:23.298929 progress 25 % (1 MB)
29 00:59:23.300144 progress 30 % (1 MB)
30 00:59:23.301389 progress 35 % (1 MB)
31 00:59:23.302637 progress 40 % (1 MB)
32 00:59:23.304003 progress 45 % (2 MB)
33 00:59:23.305208 progress 50 % (2 MB)
34 00:59:23.306463 progress 55 % (2 MB)
35 00:59:23.307668 progress 60 % (2 MB)
36 00:59:23.308907 progress 65 % (2 MB)
37 00:59:23.310228 progress 70 % (3 MB)
38 00:59:23.311526 progress 75 % (3 MB)
39 00:59:23.312739 progress 80 % (3 MB)
40 00:59:23.314167 progress 85 % (3 MB)
41 00:59:23.315403 progress 90 % (4 MB)
42 00:59:23.316638 progress 95 % (4 MB)
43 00:59:23.317923 progress 100 % (4 MB)
44 00:59:23.318076 4 MB downloaded in 0.03 s (165.67 MB/s)
45 00:59:23.318227 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:59:23.318471 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:59:23.318557 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:59:23.318641 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:59:23.318778 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:59:23.318852 saving as /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/kernel/Image
52 00:59:23.318914 total size: 51532288 (49 MB)
53 00:59:23.318975 No compression specified
54 00:59:23.320066 progress 0 % (0 MB)
55 00:59:23.333408 progress 5 % (2 MB)
56 00:59:23.346829 progress 10 % (4 MB)
57 00:59:23.360108 progress 15 % (7 MB)
58 00:59:23.373761 progress 20 % (9 MB)
59 00:59:23.387164 progress 25 % (12 MB)
60 00:59:23.400503 progress 30 % (14 MB)
61 00:59:23.413973 progress 35 % (17 MB)
62 00:59:23.427454 progress 40 % (19 MB)
63 00:59:23.440877 progress 45 % (22 MB)
64 00:59:23.454241 progress 50 % (24 MB)
65 00:59:23.467573 progress 55 % (27 MB)
66 00:59:23.481015 progress 60 % (29 MB)
67 00:59:23.494730 progress 65 % (31 MB)
68 00:59:23.508021 progress 70 % (34 MB)
69 00:59:23.521556 progress 75 % (36 MB)
70 00:59:23.535295 progress 80 % (39 MB)
71 00:59:23.548518 progress 85 % (41 MB)
72 00:59:23.562020 progress 90 % (44 MB)
73 00:59:23.575296 progress 95 % (46 MB)
74 00:59:23.588220 progress 100 % (49 MB)
75 00:59:23.588434 49 MB downloaded in 0.27 s (182.35 MB/s)
76 00:59:23.588586 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:59:23.588820 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:59:23.588912 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:59:23.588998 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:59:23.589141 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:59:23.589212 saving as /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/dtb/mt8192-asurada-spherion-r0.dtb
83 00:59:23.589274 total size: 47278 (0 MB)
84 00:59:23.589336 No compression specified
85 00:59:23.590491 progress 69 % (0 MB)
86 00:59:23.590770 progress 100 % (0 MB)
87 00:59:23.590928 0 MB downloaded in 0.00 s (27.30 MB/s)
88 00:59:23.591051 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:59:23.591280 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:59:23.591369 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:59:23.591453 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:59:23.591568 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 00:59:23.591637 saving as /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/nfsrootfs/full.rootfs.tar
95 00:59:23.591698 total size: 200813988 (191 MB)
96 00:59:23.591760 Using unxz to decompress xz
97 00:59:23.595875 progress 0 % (0 MB)
98 00:59:24.125076 progress 5 % (9 MB)
99 00:59:24.637571 progress 10 % (19 MB)
100 00:59:25.223049 progress 15 % (28 MB)
101 00:59:25.595360 progress 20 % (38 MB)
102 00:59:25.918291 progress 25 % (47 MB)
103 00:59:26.514085 progress 30 % (57 MB)
104 00:59:27.070596 progress 35 % (67 MB)
105 00:59:27.681312 progress 40 % (76 MB)
106 00:59:28.260114 progress 45 % (86 MB)
107 00:59:28.851158 progress 50 % (95 MB)
108 00:59:29.507471 progress 55 % (105 MB)
109 00:59:30.178824 progress 60 % (114 MB)
110 00:59:30.296109 progress 65 % (124 MB)
111 00:59:30.435048 progress 70 % (134 MB)
112 00:59:30.531430 progress 75 % (143 MB)
113 00:59:30.612342 progress 80 % (153 MB)
114 00:59:30.703520 progress 85 % (162 MB)
115 00:59:30.818034 progress 90 % (172 MB)
116 00:59:31.102454 progress 95 % (181 MB)
117 00:59:31.682361 progress 100 % (191 MB)
118 00:59:31.687587 191 MB downloaded in 8.10 s (23.66 MB/s)
119 00:59:31.687848 end: 1.4.1 http-download (duration 00:00:08) [common]
121 00:59:31.688112 end: 1.4 download-retry (duration 00:00:08) [common]
122 00:59:31.688201 start: 1.5 download-retry (timeout 00:09:52) [common]
123 00:59:31.688288 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 00:59:31.688449 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:59:31.688521 saving as /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/modules/modules.tar
126 00:59:31.688583 total size: 8625444 (8 MB)
127 00:59:31.688647 Using unxz to decompress xz
128 00:59:31.692966 progress 0 % (0 MB)
129 00:59:31.713861 progress 5 % (0 MB)
130 00:59:31.737401 progress 10 % (0 MB)
131 00:59:31.762417 progress 15 % (1 MB)
132 00:59:31.786123 progress 20 % (1 MB)
133 00:59:31.810102 progress 25 % (2 MB)
134 00:59:31.835923 progress 30 % (2 MB)
135 00:59:31.862476 progress 35 % (2 MB)
136 00:59:31.886565 progress 40 % (3 MB)
137 00:59:31.910856 progress 45 % (3 MB)
138 00:59:31.936646 progress 50 % (4 MB)
139 00:59:31.961440 progress 55 % (4 MB)
140 00:59:31.986940 progress 60 % (4 MB)
141 00:59:32.015066 progress 65 % (5 MB)
142 00:59:32.040901 progress 70 % (5 MB)
143 00:59:32.064733 progress 75 % (6 MB)
144 00:59:32.091971 progress 80 % (6 MB)
145 00:59:32.118352 progress 85 % (7 MB)
146 00:59:32.143628 progress 90 % (7 MB)
147 00:59:32.176981 progress 95 % (7 MB)
148 00:59:32.206087 progress 100 % (8 MB)
149 00:59:32.211138 8 MB downloaded in 0.52 s (15.74 MB/s)
150 00:59:32.211394 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:59:32.211662 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:59:32.211755 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 00:59:32.211848 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 00:59:35.818252 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8
156 00:59:35.818463 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:59:35.818568 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 00:59:35.818783 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl
159 00:59:35.818924 makedir: /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin
160 00:59:35.819032 makedir: /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/tests
161 00:59:35.819204 makedir: /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/results
162 00:59:35.819309 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-add-keys
163 00:59:35.819455 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-add-sources
164 00:59:35.819636 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-background-process-start
165 00:59:35.819785 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-background-process-stop
166 00:59:35.819916 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-common-functions
167 00:59:35.820045 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-echo-ipv4
168 00:59:35.820173 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-install-packages
169 00:59:35.820301 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-installed-packages
170 00:59:35.820433 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-os-build
171 00:59:35.820562 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-probe-channel
172 00:59:35.820693 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-probe-ip
173 00:59:35.820823 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-target-ip
174 00:59:35.820951 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-target-mac
175 00:59:35.821078 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-target-storage
176 00:59:35.821209 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-case
177 00:59:35.821337 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-event
178 00:59:35.821464 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-feedback
179 00:59:35.821634 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-raise
180 00:59:35.821762 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-reference
181 00:59:35.821890 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-runner
182 00:59:35.822016 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-set
183 00:59:35.822143 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-test-shell
184 00:59:35.822272 Updating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-add-keys (debian)
185 00:59:35.822429 Updating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-add-sources (debian)
186 00:59:35.822572 Updating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-install-packages (debian)
187 00:59:35.822714 Updating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-installed-packages (debian)
188 00:59:35.822854 Updating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/bin/lava-os-build (debian)
189 00:59:35.822978 Creating /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/environment
190 00:59:35.823077 LAVA metadata
191 00:59:35.823150 - LAVA_JOB_ID=12571114
192 00:59:35.823215 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:59:35.823321 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 00:59:35.823389 skipped lava-vland-overlay
195 00:59:35.823465 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:59:35.823547 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 00:59:35.823609 skipped lava-multinode-overlay
198 00:59:35.823695 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:59:35.823776 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 00:59:35.823852 Loading test definitions
201 00:59:35.823945 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 00:59:35.824018 Using /lava-12571114 at stage 0
203 00:59:35.824323 uuid=12571114_1.6.2.3.1 testdef=None
204 00:59:35.824412 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:59:35.824500 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 00:59:35.824962 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:59:35.825189 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 00:59:35.826049 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:59:35.826286 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 00:59:35.826838 runner path: /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/0/tests/0_timesync-off test_uuid 12571114_1.6.2.3.1
213 00:59:35.826997 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:59:35.827226 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 00:59:35.827300 Using /lava-12571114 at stage 0
217 00:59:35.827400 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:59:35.827481 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/0/tests/1_kselftest-arm64'
219 00:59:39.576528 Running '/usr/bin/git checkout kernelci.org
220 00:59:39.727137 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 00:59:39.727907 uuid=12571114_1.6.2.3.5 testdef=None
222 00:59:39.728071 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 00:59:39.728331 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 00:59:39.729089 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:59:39.729326 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 00:59:39.730351 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:59:39.730589 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 00:59:39.731524 runner path: /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/0/tests/1_kselftest-arm64 test_uuid 12571114_1.6.2.3.5
232 00:59:39.731620 BOARD='mt8192-asurada-spherion-r0'
233 00:59:39.731686 BRANCH='cip'
234 00:59:39.731746 SKIPFILE='/dev/null'
235 00:59:39.731805 SKIP_INSTALL='True'
236 00:59:39.731860 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:59:39.731919 TST_CASENAME=''
238 00:59:39.731975 TST_CMDFILES='arm64'
239 00:59:39.732117 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:59:39.732322 Creating lava-test-runner.conf files
242 00:59:39.732387 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571114/lava-overlay-j84shdgl/lava-12571114/0 for stage 0
243 00:59:39.732482 - 0_timesync-off
244 00:59:39.732554 - 1_kselftest-arm64
245 00:59:39.732650 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 00:59:39.732740 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 00:59:47.251067 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:59:47.251231 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 00:59:47.251325 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:59:47.251427 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:59:47.251523 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 00:59:47.371635 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:59:47.372049 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 00:59:47.372166 extracting modules file /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8
255 00:59:47.594367 extracting modules file /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571114/extract-overlay-ramdisk-d85br7um/ramdisk
256 00:59:47.822479 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:59:47.822654 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 00:59:47.822753 [common] Applying overlay to NFS
259 00:59:47.822826 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571114/compress-overlay-rj1_f8l3/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8
260 00:59:48.744701 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:59:48.744871 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 00:59:48.744968 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:59:48.745059 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 00:59:48.745137 Building ramdisk /var/lib/lava/dispatcher/tmp/12571114/extract-overlay-ramdisk-d85br7um/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571114/extract-overlay-ramdisk-d85br7um/ramdisk
265 00:59:49.077012 >> 119414 blocks
266 00:59:50.975258 rename /var/lib/lava/dispatcher/tmp/12571114/extract-overlay-ramdisk-d85br7um/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/ramdisk/ramdisk.cpio.gz
267 00:59:50.975714 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:59:50.975843 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 00:59:50.975958 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 00:59:50.976068 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/kernel/Image'
271 01:00:03.926356 Returned 0 in 12 seconds
272 01:00:04.027039 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/kernel/image.itb
273 01:00:04.400890 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:00:04.401288 output: Created: Fri Jan 19 01:00:04 2024
275 01:00:04.401365 output: Image 0 (kernel-1)
276 01:00:04.401433 output: Description:
277 01:00:04.401529 output: Created: Fri Jan 19 01:00:04 2024
278 01:00:04.401606 output: Type: Kernel Image
279 01:00:04.401664 output: Compression: lzma compressed
280 01:00:04.401720 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
281 01:00:04.401781 output: Architecture: AArch64
282 01:00:04.401838 output: OS: Linux
283 01:00:04.401895 output: Load Address: 0x00000000
284 01:00:04.401955 output: Entry Point: 0x00000000
285 01:00:04.402015 output: Hash algo: crc32
286 01:00:04.402071 output: Hash value: a52aa383
287 01:00:04.402129 output: Image 1 (fdt-1)
288 01:00:04.402183 output: Description: mt8192-asurada-spherion-r0
289 01:00:04.402237 output: Created: Fri Jan 19 01:00:04 2024
290 01:00:04.402291 output: Type: Flat Device Tree
291 01:00:04.402345 output: Compression: uncompressed
292 01:00:04.402399 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 01:00:04.402454 output: Architecture: AArch64
294 01:00:04.402507 output: Hash algo: crc32
295 01:00:04.402560 output: Hash value: cc4352de
296 01:00:04.402613 output: Image 2 (ramdisk-1)
297 01:00:04.402666 output: Description: unavailable
298 01:00:04.402720 output: Created: Fri Jan 19 01:00:04 2024
299 01:00:04.402774 output: Type: RAMDisk Image
300 01:00:04.402827 output: Compression: Unknown Compression
301 01:00:04.402880 output: Data Size: 17804151 Bytes = 17386.87 KiB = 16.98 MiB
302 01:00:04.402934 output: Architecture: AArch64
303 01:00:04.402987 output: OS: Linux
304 01:00:04.403039 output: Load Address: unavailable
305 01:00:04.403093 output: Entry Point: unavailable
306 01:00:04.403146 output: Hash algo: crc32
307 01:00:04.403198 output: Hash value: d3274d5f
308 01:00:04.403251 output: Default Configuration: 'conf-1'
309 01:00:04.403304 output: Configuration 0 (conf-1)
310 01:00:04.403357 output: Description: mt8192-asurada-spherion-r0
311 01:00:04.403409 output: Kernel: kernel-1
312 01:00:04.403462 output: Init Ramdisk: ramdisk-1
313 01:00:04.403515 output: FDT: fdt-1
314 01:00:04.403567 output: Loadables: kernel-1
315 01:00:04.403620 output:
316 01:00:04.403827 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 01:00:04.403931 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 01:00:04.404036 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 01:00:04.404134 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 01:00:04.404215 No LXC device requested
321 01:00:04.404296 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:00:04.404379 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 01:00:04.404455 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:00:04.404525 Checking files for TFTP limit of 4294967296 bytes.
325 01:00:04.405030 end: 1 tftp-deploy (duration 00:00:41) [common]
326 01:00:04.405180 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:00:04.405271 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:00:04.405398 substitutions:
329 01:00:04.405466 - {DTB}: 12571114/tftp-deploy-9rsx53qq/dtb/mt8192-asurada-spherion-r0.dtb
330 01:00:04.405545 - {INITRD}: 12571114/tftp-deploy-9rsx53qq/ramdisk/ramdisk.cpio.gz
331 01:00:04.405606 - {KERNEL}: 12571114/tftp-deploy-9rsx53qq/kernel/Image
332 01:00:04.405666 - {LAVA_MAC}: None
333 01:00:04.405725 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8
334 01:00:04.405782 - {NFS_SERVER_IP}: 192.168.201.1
335 01:00:04.405839 - {PRESEED_CONFIG}: None
336 01:00:04.405894 - {PRESEED_LOCAL}: None
337 01:00:04.405950 - {RAMDISK}: 12571114/tftp-deploy-9rsx53qq/ramdisk/ramdisk.cpio.gz
338 01:00:04.406005 - {ROOT_PART}: None
339 01:00:04.406058 - {ROOT}: None
340 01:00:04.406112 - {SERVER_IP}: 192.168.201.1
341 01:00:04.406166 - {TEE}: None
342 01:00:04.406220 Parsed boot commands:
343 01:00:04.406273 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:00:04.406461 Parsed boot commands: tftpboot 192.168.201.1 12571114/tftp-deploy-9rsx53qq/kernel/image.itb 12571114/tftp-deploy-9rsx53qq/kernel/cmdline
345 01:00:04.406551 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:00:04.406636 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:00:04.406729 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:00:04.406817 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:00:04.406895 Not connected, no need to disconnect.
350 01:00:04.406969 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:00:04.407053 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:00:04.407121 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 01:00:04.411373 Setting prompt string to ['lava-test: # ']
354 01:00:04.411766 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:00:04.411875 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:00:04.411980 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:00:04.412071 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:00:04.412303 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 01:00:09.560637 >> Command sent successfully.
360 01:00:09.571382 Returned 0 in 5 seconds
361 01:00:09.672562 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:00:09.674020 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:00:09.674553 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:00:09.675008 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:00:09.675365 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:00:09.675723 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:00:09.676956 [Enter `^Ec?' for help]
369 01:00:09.835920
370 01:00:09.836467
371 01:00:09.836842 F0: 102B 0000
372 01:00:09.837182
373 01:00:09.837529 F3: 1001 0000 [0200]
374 01:00:09.837848
375 01:00:09.839729 F3: 1001 0000
376 01:00:09.840272
377 01:00:09.840627 F7: 102D 0000
378 01:00:09.840951
379 01:00:09.841261 F1: 0000 0000
380 01:00:09.841609
381 01:00:09.843377 V0: 0000 0000 [0001]
382 01:00:09.843925
383 01:00:09.844279 00: 0007 8000
384 01:00:09.844628
385 01:00:09.846778 01: 0000 0000
386 01:00:09.847226
387 01:00:09.847573 BP: 0C00 0209 [0000]
388 01:00:09.847897
389 01:00:09.850552 G0: 1182 0000
390 01:00:09.851128
391 01:00:09.851484 EC: 0000 0021 [4000]
392 01:00:09.851808
393 01:00:09.854209 S7: 0000 0000 [0000]
394 01:00:09.854648
395 01:00:09.855054 CC: 0000 0000 [0001]
396 01:00:09.855563
397 01:00:09.857428 T0: 0000 0040 [010F]
398 01:00:09.857921
399 01:00:09.858270 Jump to BL
400 01:00:09.858596
401 01:00:09.882420
402 01:00:09.882949
403 01:00:09.883299
404 01:00:09.889126 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:00:09.892715 ARM64: Exception handlers installed.
406 01:00:09.896298 ARM64: Testing exception
407 01:00:09.900323 ARM64: Done test exception
408 01:00:09.907633 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:00:09.918316 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:00:09.925354 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:00:09.935377 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:00:09.941945 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:00:09.948546 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:00:09.959461 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:00:09.965956 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:00:09.985723 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:00:09.988546 WDT: Last reset was cold boot
418 01:00:09.992237 SPI1(PAD0) initialized at 2873684 Hz
419 01:00:09.995530 SPI5(PAD0) initialized at 992727 Hz
420 01:00:09.998618 VBOOT: Loading verstage.
421 01:00:10.005541 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:00:10.008752 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:00:10.011890 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:00:10.015141 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:00:10.022959 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:00:10.029553 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:00:10.040694 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 01:00:10.041235
429 01:00:10.041635
430 01:00:10.050556 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:00:10.053741 ARM64: Exception handlers installed.
432 01:00:10.057577 ARM64: Testing exception
433 01:00:10.058130 ARM64: Done test exception
434 01:00:10.063861 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:00:10.067161 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:00:10.081323 Probing TPM: . done!
437 01:00:10.081950 TPM ready after 0 ms
438 01:00:10.088070 Connected to device vid:did:rid of 1ae0:0028:00
439 01:00:10.095310 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 01:00:10.135050 Initialized TPM device CR50 revision 0
441 01:00:10.147254 tlcl_send_startup: Startup return code is 0
442 01:00:10.147802 TPM: setup succeeded
443 01:00:10.158550 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:00:10.167349 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:00:10.179061 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:00:10.187885 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:00:10.191444 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:00:10.195007 in-header: 03 07 00 00 08 00 00 00
449 01:00:10.198620 in-data: aa e4 47 04 13 02 00 00
450 01:00:10.202359 Chrome EC: UHEPI supported
451 01:00:10.209264 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:00:10.212671 in-header: 03 9d 00 00 08 00 00 00
453 01:00:10.216694 in-data: 10 20 20 08 00 00 00 00
454 01:00:10.217459 Phase 1
455 01:00:10.220302 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:00:10.227769 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:00:10.235255 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:00:10.235947 Recovery requested (1009000e)
459 01:00:10.244054 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:00:10.249061 tlcl_extend: response is 0
461 01:00:10.257358 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:00:10.262767 tlcl_extend: response is 0
463 01:00:10.269430 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:00:10.290375 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
465 01:00:10.297836 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 01:00:10.298370
467 01:00:10.298723
468 01:00:10.308658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:00:10.309208 ARM64: Exception handlers installed.
470 01:00:10.312180 ARM64: Testing exception
471 01:00:10.315612 ARM64: Done test exception
472 01:00:10.335845 pmic_efuse_setting: Set efuses in 11 msecs
473 01:00:10.339830 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:00:10.343775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:00:10.351187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:00:10.354858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:00:10.358382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:00:10.365668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:00:10.369222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:00:10.373035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:00:10.376972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:00:10.383710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:00:10.387153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:00:10.393709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:00:10.396941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:00:10.400143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:00:10.406932 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:00:10.414149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:00:10.420690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:00:10.424104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:00:10.430762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:00:10.437468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:00:10.441297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:00:10.448717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:00:10.452490 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:00:10.459644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:00:10.462756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:00:10.469748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:00:10.476417 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:00:10.479859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:00:10.483203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:00:10.489668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:00:10.493346 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:00:10.500952 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:00:10.504847 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:00:10.508112 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:00:10.515923 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:00:10.519364 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:00:10.523295 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:00:10.530038 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:00:10.533665 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:00:10.540366 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:00:10.543612 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:00:10.547064 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:00:10.553645 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:00:10.556947 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:00:10.560448 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:00:10.567062 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:00:10.570063 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:00:10.573559 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:00:10.576896 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:00:10.583508 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:00:10.587028 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:00:10.590167 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:00:10.596875 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:00:10.606655 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:00:10.610399 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:00:10.620458 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:00:10.626871 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:00:10.633653 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:00:10.637106 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:00:10.640214 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:00:10.647982 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1b
534 01:00:10.654778 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:00:10.658053 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 01:00:10.661202 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:00:10.672728 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 01:00:10.676275 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 01:00:10.682516 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 01:00:10.686212 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 01:00:10.689297 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 01:00:10.692364 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 01:00:10.695899 ADC[4]: Raw value=897410 ID=7
544 01:00:10.699310 ADC[3]: Raw value=213440 ID=1
545 01:00:10.702615 RAM Code: 0x71
546 01:00:10.705859 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 01:00:10.709347 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 01:00:10.719680 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 01:00:10.726167 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 01:00:10.729655 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 01:00:10.732784 in-header: 03 07 00 00 08 00 00 00
552 01:00:10.736529 in-data: aa e4 47 04 13 02 00 00
553 01:00:10.739848 Chrome EC: UHEPI supported
554 01:00:10.746864 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 01:00:10.750239 in-header: 03 d5 00 00 08 00 00 00
556 01:00:10.750676 in-data: 98 20 60 08 00 00 00 00
557 01:00:10.754229 MRC: failed to locate region type 0.
558 01:00:10.761227 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 01:00:10.764753 DRAM-K: Running full calibration
560 01:00:10.771819 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 01:00:10.772365 header.status = 0x0
562 01:00:10.775014 header.version = 0x6 (expected: 0x6)
563 01:00:10.778075 header.size = 0xd00 (expected: 0xd00)
564 01:00:10.782165 header.flags = 0x0
565 01:00:10.785757 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 01:00:10.804814 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
567 01:00:10.812011 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 01:00:10.815246 dram_init: ddr_geometry: 2
569 01:00:10.818227 [EMI] MDL number = 2
570 01:00:10.818750 [EMI] Get MDL freq = 0
571 01:00:10.821403 dram_init: ddr_type: 0
572 01:00:10.821897 is_discrete_lpddr4: 1
573 01:00:10.824749 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 01:00:10.825282
575 01:00:10.825690
576 01:00:10.828429 [Bian_co] ETT version 0.0.0.1
577 01:00:10.834718 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 01:00:10.835248
579 01:00:10.838228 dramc_set_vcore_voltage set vcore to 650000
580 01:00:10.838666 Read voltage for 800, 4
581 01:00:10.841725 Vio18 = 0
582 01:00:10.842255 Vcore = 650000
583 01:00:10.842603 Vdram = 0
584 01:00:10.845215 Vddq = 0
585 01:00:10.845786 Vmddr = 0
586 01:00:10.848238 dram_init: config_dvfs: 1
587 01:00:10.851895 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 01:00:10.858447 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 01:00:10.861756 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 01:00:10.864797 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 01:00:10.868656 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 01:00:10.871717 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 01:00:10.875061 MEM_TYPE=3, freq_sel=18
594 01:00:10.878367 sv_algorithm_assistance_LP4_1600
595 01:00:10.882052 ============ PULL DRAM RESETB DOWN ============
596 01:00:10.885238 ========== PULL DRAM RESETB DOWN end =========
597 01:00:10.891302 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 01:00:10.894796 ===================================
599 01:00:10.898379 LPDDR4 DRAM CONFIGURATION
600 01:00:10.901717 ===================================
601 01:00:10.902255 EX_ROW_EN[0] = 0x0
602 01:00:10.905028 EX_ROW_EN[1] = 0x0
603 01:00:10.905465 LP4Y_EN = 0x0
604 01:00:10.908705 WORK_FSP = 0x0
605 01:00:10.909285 WL = 0x2
606 01:00:10.912429 RL = 0x2
607 01:00:10.912998 BL = 0x2
608 01:00:10.915824 RPST = 0x0
609 01:00:10.916262 RD_PRE = 0x0
610 01:00:10.916607 WR_PRE = 0x1
611 01:00:10.919791 WR_PST = 0x0
612 01:00:10.920247 DBI_WR = 0x0
613 01:00:10.923441 DBI_RD = 0x0
614 01:00:10.924006 OTF = 0x1
615 01:00:10.926941 ===================================
616 01:00:10.931067 ===================================
617 01:00:10.931610 ANA top config
618 01:00:10.934399 ===================================
619 01:00:10.938032 DLL_ASYNC_EN = 0
620 01:00:10.941988 ALL_SLAVE_EN = 1
621 01:00:10.942541 NEW_RANK_MODE = 1
622 01:00:10.946081 DLL_IDLE_MODE = 1
623 01:00:10.949568 LP45_APHY_COMB_EN = 1
624 01:00:10.950011 TX_ODT_DIS = 1
625 01:00:10.953544 NEW_8X_MODE = 1
626 01:00:10.957609 ===================================
627 01:00:10.961122 ===================================
628 01:00:10.964322 data_rate = 1600
629 01:00:10.964760 CKR = 1
630 01:00:10.968282 DQ_P2S_RATIO = 8
631 01:00:10.971824 ===================================
632 01:00:10.975351 CA_P2S_RATIO = 8
633 01:00:10.979425 DQ_CA_OPEN = 0
634 01:00:10.979998 DQ_SEMI_OPEN = 0
635 01:00:10.983014 CA_SEMI_OPEN = 0
636 01:00:10.986478 CA_FULL_RATE = 0
637 01:00:10.990008 DQ_CKDIV4_EN = 1
638 01:00:10.990448 CA_CKDIV4_EN = 1
639 01:00:10.993764 CA_PREDIV_EN = 0
640 01:00:10.997124 PH8_DLY = 0
641 01:00:11.000472 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 01:00:11.003657 DQ_AAMCK_DIV = 4
643 01:00:11.004113 CA_AAMCK_DIV = 4
644 01:00:11.006946 CA_ADMCK_DIV = 4
645 01:00:11.010440 DQ_TRACK_CA_EN = 0
646 01:00:11.014160 CA_PICK = 800
647 01:00:11.017223 CA_MCKIO = 800
648 01:00:11.020685 MCKIO_SEMI = 0
649 01:00:11.024020 PLL_FREQ = 3068
650 01:00:11.024559 DQ_UI_PI_RATIO = 32
651 01:00:11.027328 CA_UI_PI_RATIO = 0
652 01:00:11.030372 ===================================
653 01:00:11.033433 ===================================
654 01:00:11.037198 memory_type:LPDDR4
655 01:00:11.040649 GP_NUM : 10
656 01:00:11.041188 SRAM_EN : 1
657 01:00:11.043861 MD32_EN : 0
658 01:00:11.047497 ===================================
659 01:00:11.050287 [ANA_INIT] >>>>>>>>>>>>>>
660 01:00:11.050824 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 01:00:11.054036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 01:00:11.057338 ===================================
663 01:00:11.060557 data_rate = 1600,PCW = 0X7600
664 01:00:11.063887 ===================================
665 01:00:11.066756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 01:00:11.073931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 01:00:11.080183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 01:00:11.083926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 01:00:11.087308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 01:00:11.090980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 01:00:11.091522 [ANA_INIT] flow start
672 01:00:11.094202 [ANA_INIT] PLL >>>>>>>>
673 01:00:11.098030 [ANA_INIT] PLL <<<<<<<<
674 01:00:11.098470 [ANA_INIT] MIDPI >>>>>>>>
675 01:00:11.101892 [ANA_INIT] MIDPI <<<<<<<<
676 01:00:11.105296 [ANA_INIT] DLL >>>>>>>>
677 01:00:11.105814 [ANA_INIT] flow end
678 01:00:11.109054 ============ LP4 DIFF to SE enter ============
679 01:00:11.113241 ============ LP4 DIFF to SE exit ============
680 01:00:11.116834 [ANA_INIT] <<<<<<<<<<<<<
681 01:00:11.120544 [Flow] Enable top DCM control >>>>>
682 01:00:11.124375 [Flow] Enable top DCM control <<<<<
683 01:00:11.127950 Enable DLL master slave shuffle
684 01:00:11.131719 ==============================================================
685 01:00:11.132302 Gating Mode config
686 01:00:11.138294 ==============================================================
687 01:00:11.141861 Config description:
688 01:00:11.151478 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 01:00:11.158421 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 01:00:11.161751 SELPH_MODE 0: By rank 1: By Phase
691 01:00:11.168375 ==============================================================
692 01:00:11.171204 GAT_TRACK_EN = 1
693 01:00:11.174925 RX_GATING_MODE = 2
694 01:00:11.175459 RX_GATING_TRACK_MODE = 2
695 01:00:11.177933 SELPH_MODE = 1
696 01:00:11.181464 PICG_EARLY_EN = 1
697 01:00:11.185120 VALID_LAT_VALUE = 1
698 01:00:11.191201 ==============================================================
699 01:00:11.194760 Enter into Gating configuration >>>>
700 01:00:11.197755 Exit from Gating configuration <<<<
701 01:00:11.201331 Enter into DVFS_PRE_config >>>>>
702 01:00:11.211423 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 01:00:11.214775 Exit from DVFS_PRE_config <<<<<
704 01:00:11.218000 Enter into PICG configuration >>>>
705 01:00:11.221395 Exit from PICG configuration <<<<
706 01:00:11.224974 [RX_INPUT] configuration >>>>>
707 01:00:11.228046 [RX_INPUT] configuration <<<<<
708 01:00:11.231781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 01:00:11.238174 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 01:00:11.245121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 01:00:11.248012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 01:00:11.254969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 01:00:11.261580 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 01:00:11.264585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 01:00:11.268277 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 01:00:11.275113 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 01:00:11.278198 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 01:00:11.281442 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 01:00:11.288457 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 01:00:11.291915 ===================================
721 01:00:11.292445 LPDDR4 DRAM CONFIGURATION
722 01:00:11.294869 ===================================
723 01:00:11.298334 EX_ROW_EN[0] = 0x0
724 01:00:11.298888 EX_ROW_EN[1] = 0x0
725 01:00:11.301447 LP4Y_EN = 0x0
726 01:00:11.302030 WORK_FSP = 0x0
727 01:00:11.304757 WL = 0x2
728 01:00:11.308131 RL = 0x2
729 01:00:11.308571 BL = 0x2
730 01:00:11.311836 RPST = 0x0
731 01:00:11.312384 RD_PRE = 0x0
732 01:00:11.314798 WR_PRE = 0x1
733 01:00:11.315242 WR_PST = 0x0
734 01:00:11.318306 DBI_WR = 0x0
735 01:00:11.318853 DBI_RD = 0x0
736 01:00:11.321736 OTF = 0x1
737 01:00:11.325193 ===================================
738 01:00:11.328248 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 01:00:11.331665 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 01:00:11.335013 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 01:00:11.338089 ===================================
742 01:00:11.341692 LPDDR4 DRAM CONFIGURATION
743 01:00:11.345009 ===================================
744 01:00:11.348539 EX_ROW_EN[0] = 0x10
745 01:00:11.349091 EX_ROW_EN[1] = 0x0
746 01:00:11.352106 LP4Y_EN = 0x0
747 01:00:11.352649 WORK_FSP = 0x0
748 01:00:11.355578 WL = 0x2
749 01:00:11.356016 RL = 0x2
750 01:00:11.359457 BL = 0x2
751 01:00:11.359998 RPST = 0x0
752 01:00:11.362460 RD_PRE = 0x0
753 01:00:11.362897 WR_PRE = 0x1
754 01:00:11.366126 WR_PST = 0x0
755 01:00:11.366569 DBI_WR = 0x0
756 01:00:11.369984 DBI_RD = 0x0
757 01:00:11.370424 OTF = 0x1
758 01:00:11.373672 ===================================
759 01:00:11.380997 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 01:00:11.384607 nWR fixed to 40
761 01:00:11.385051 [ModeRegInit_LP4] CH0 RK0
762 01:00:11.388277 [ModeRegInit_LP4] CH0 RK1
763 01:00:11.388777 [ModeRegInit_LP4] CH1 RK0
764 01:00:11.392285 [ModeRegInit_LP4] CH1 RK1
765 01:00:11.396306 match AC timing 13
766 01:00:11.400356 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 01:00:11.403820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 01:00:11.407384 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 01:00:11.410838 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 01:00:11.414562 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 01:00:11.418163 [EMI DOE] emi_dcm 0
772 01:00:11.421779 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 01:00:11.422217 ==
774 01:00:11.425507 Dram Type= 6, Freq= 0, CH_0, rank 0
775 01:00:11.429520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 01:00:11.430083 ==
777 01:00:11.436798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 01:00:11.440171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 01:00:11.451194 [CA 0] Center 38 (7~69) winsize 63
780 01:00:11.455161 [CA 1] Center 37 (7~68) winsize 62
781 01:00:11.458952 [CA 2] Center 35 (5~66) winsize 62
782 01:00:11.462410 [CA 3] Center 35 (5~66) winsize 62
783 01:00:11.465935 [CA 4] Center 34 (4~65) winsize 62
784 01:00:11.469620 [CA 5] Center 34 (4~65) winsize 62
785 01:00:11.470090
786 01:00:11.473358 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 01:00:11.473823
788 01:00:11.477324 [CATrainingPosCal] consider 1 rank data
789 01:00:11.477920 u2DelayCellTimex100 = 270/100 ps
790 01:00:11.481204 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 01:00:11.484507 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 01:00:11.488472 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 01:00:11.492245 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 01:00:11.496124 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 01:00:11.499259 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 01:00:11.499700
797 01:00:11.503402 CA PerBit enable=1, Macro0, CA PI delay=34
798 01:00:11.503946
799 01:00:11.507143 [CBTSetCACLKResult] CA Dly = 34
800 01:00:11.507579 CS Dly: 6 (0~37)
801 01:00:11.510556 ==
802 01:00:11.510986 Dram Type= 6, Freq= 0, CH_0, rank 1
803 01:00:11.518207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 01:00:11.518734 ==
805 01:00:11.521792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 01:00:11.528823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 01:00:11.537607 [CA 0] Center 38 (7~69) winsize 63
808 01:00:11.541379 [CA 1] Center 38 (7~69) winsize 63
809 01:00:11.545194 [CA 2] Center 35 (5~66) winsize 62
810 01:00:11.548809 [CA 3] Center 35 (5~66) winsize 62
811 01:00:11.552748 [CA 4] Center 34 (4~65) winsize 62
812 01:00:11.553339 [CA 5] Center 34 (4~65) winsize 62
813 01:00:11.556047
814 01:00:11.559979 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 01:00:11.560542
816 01:00:11.563485 [CATrainingPosCal] consider 2 rank data
817 01:00:11.564035 u2DelayCellTimex100 = 270/100 ps
818 01:00:11.567292 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 01:00:11.571094 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 01:00:11.574604 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 01:00:11.578236 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 01:00:11.581881 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 01:00:11.586047 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 01:00:11.586572
825 01:00:11.589189 CA PerBit enable=1, Macro0, CA PI delay=34
826 01:00:11.589697
827 01:00:11.592692 [CBTSetCACLKResult] CA Dly = 34
828 01:00:11.596826 CS Dly: 6 (0~37)
829 01:00:11.597365
830 01:00:11.600285 ----->DramcWriteLeveling(PI) begin...
831 01:00:11.600738 ==
832 01:00:11.601188 Dram Type= 6, Freq= 0, CH_0, rank 0
833 01:00:11.607379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 01:00:11.607827 ==
835 01:00:11.611414 Write leveling (Byte 0): 30 => 30
836 01:00:11.611860 Write leveling (Byte 1): 30 => 30
837 01:00:11.615366 DramcWriteLeveling(PI) end<-----
838 01:00:11.615808
839 01:00:11.616258 ==
840 01:00:11.618745 Dram Type= 6, Freq= 0, CH_0, rank 0
841 01:00:11.622654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 01:00:11.623197 ==
843 01:00:11.626021 [Gating] SW mode calibration
844 01:00:11.633926 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 01:00:11.637126 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 01:00:11.644603 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 01:00:11.648280 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 01:00:11.651554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 01:00:11.655296 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 01:00:11.662006 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 01:00:11.665451 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 01:00:11.668358 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 01:00:11.675755 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 01:00:11.678795 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 01:00:11.683201 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 01:00:11.686771 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:00:11.690086 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:00:11.696893 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:00:11.700107 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:00:11.704272 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:00:11.707880 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:00:11.714269 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:00:11.717543 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 01:00:11.720744 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
865 01:00:11.727564 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
866 01:00:11.730742 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:00:11.733956 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:00:11.740946 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:00:11.744218 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 01:00:11.747652 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 01:00:11.753846 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 01:00:11.757412 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 01:00:11.760598 0 9 12 | B1->B0 | 2626 3030 | 0 1 | (0 0) (1 1)
874 01:00:11.767237 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 01:00:11.770619 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 01:00:11.773943 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 01:00:11.777327 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 01:00:11.784014 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 01:00:11.787215 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 01:00:11.791237 0 10 8 | B1->B0 | 3333 3131 | 0 0 | (0 0) (1 0)
881 01:00:11.797772 0 10 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
882 01:00:11.801204 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 01:00:11.804368 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 01:00:11.810955 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 01:00:11.814383 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 01:00:11.817698 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 01:00:11.824585 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 01:00:11.827288 0 11 8 | B1->B0 | 2424 2d2d | 1 1 | (0 0) (0 0)
889 01:00:11.831168 0 11 12 | B1->B0 | 3737 4343 | 0 0 | (1 1) (0 0)
890 01:00:11.837591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 01:00:11.841005 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 01:00:11.844097 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 01:00:11.850833 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 01:00:11.854276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 01:00:11.857338 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 01:00:11.864434 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 01:00:11.867415 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 01:00:11.870636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 01:00:11.874089 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 01:00:11.881296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 01:00:11.883895 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 01:00:11.887473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 01:00:11.894129 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 01:00:11.897638 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 01:00:11.900832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:00:11.907275 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:00:11.910669 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:00:11.914446 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:00:11.920813 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:00:11.924142 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:00:11.927414 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:00:11.934445 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
913 01:00:11.937683 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
914 01:00:11.941123 Total UI for P1: 0, mck2ui 16
915 01:00:11.944059 best dqsien dly found for B0: ( 0, 14, 8)
916 01:00:11.947835 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 01:00:11.951311 Total UI for P1: 0, mck2ui 16
918 01:00:11.954304 best dqsien dly found for B1: ( 0, 14, 14)
919 01:00:11.957441 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 01:00:11.960838 best DQS1 dly(MCK, UI, PI) = (0, 14, 14)
921 01:00:11.961378
922 01:00:11.964158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 01:00:11.970371 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 14)
924 01:00:11.971071 [Gating] SW calibration Done
925 01:00:11.971470 ==
926 01:00:11.974027 Dram Type= 6, Freq= 0, CH_0, rank 0
927 01:00:11.980840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 01:00:11.981385 ==
929 01:00:11.981793 RX Vref Scan: 0
930 01:00:11.982121
931 01:00:11.984014 RX Vref 0 -> 0, step: 1
932 01:00:11.984446
933 01:00:11.987654 RX Delay -130 -> 252, step: 16
934 01:00:11.990687 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
935 01:00:11.994053 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
936 01:00:11.997312 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
937 01:00:12.004104 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
938 01:00:12.007111 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
939 01:00:12.010485 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
940 01:00:12.014192 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
941 01:00:12.017609 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
942 01:00:12.024287 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
943 01:00:12.029162 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
944 01:00:12.030437 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
945 01:00:12.033623 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
946 01:00:12.037016 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
947 01:00:12.043704 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
948 01:00:12.047042 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
949 01:00:12.050210 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
950 01:00:12.050639 ==
951 01:00:12.054085 Dram Type= 6, Freq= 0, CH_0, rank 0
952 01:00:12.057255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 01:00:12.057711 ==
954 01:00:12.060693 DQS Delay:
955 01:00:12.061228 DQS0 = 0, DQS1 = 0
956 01:00:12.064225 DQM Delay:
957 01:00:12.064762 DQM0 = 81, DQM1 = 70
958 01:00:12.065104 DQ Delay:
959 01:00:12.067405 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
960 01:00:12.070791 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
961 01:00:12.073991 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 01:00:12.077304 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 01:00:12.077874
964 01:00:12.078222
965 01:00:12.081434 ==
966 01:00:12.082020 Dram Type= 6, Freq= 0, CH_0, rank 0
967 01:00:12.087729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 01:00:12.088180 ==
969 01:00:12.088524
970 01:00:12.088846
971 01:00:12.089156 TX Vref Scan disable
972 01:00:12.091163 == TX Byte 0 ==
973 01:00:12.094423 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
974 01:00:12.098079 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
975 01:00:12.101239 == TX Byte 1 ==
976 01:00:12.104337 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 01:00:12.107872 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 01:00:12.111492 ==
979 01:00:12.114917 Dram Type= 6, Freq= 0, CH_0, rank 0
980 01:00:12.117984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 01:00:12.118421 ==
982 01:00:12.129999 TX Vref=22, minBit 0, minWin=26, winSum=432
983 01:00:12.133156 TX Vref=24, minBit 11, minWin=26, winSum=433
984 01:00:12.136990 TX Vref=26, minBit 10, minWin=27, winSum=444
985 01:00:12.139942 TX Vref=28, minBit 9, minWin=27, winSum=444
986 01:00:12.143494 TX Vref=30, minBit 7, minWin=27, winSum=440
987 01:00:12.150046 TX Vref=32, minBit 1, minWin=27, winSum=437
988 01:00:12.153635 [TxChooseVref] Worse bit 10, Min win 27, Win sum 444, Final Vref 26
989 01:00:12.154168
990 01:00:12.156922 Final TX Range 1 Vref 26
991 01:00:12.157466
992 01:00:12.157887 ==
993 01:00:12.160311 Dram Type= 6, Freq= 0, CH_0, rank 0
994 01:00:12.163420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 01:00:12.163967 ==
996 01:00:12.166600
997 01:00:12.167138
998 01:00:12.167486 TX Vref Scan disable
999 01:00:12.170193 == TX Byte 0 ==
1000 01:00:12.173377 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1001 01:00:12.180046 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1002 01:00:12.180594 == TX Byte 1 ==
1003 01:00:12.183723 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 01:00:12.187313 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 01:00:12.190401
1006 01:00:12.190926 [DATLAT]
1007 01:00:12.191351 Freq=800, CH0 RK0
1008 01:00:12.191734
1009 01:00:12.193378 DATLAT Default: 0xa
1010 01:00:12.194133 0, 0xFFFF, sum = 0
1011 01:00:12.196805 1, 0xFFFF, sum = 0
1012 01:00:12.197414 2, 0xFFFF, sum = 0
1013 01:00:12.199983 3, 0xFFFF, sum = 0
1014 01:00:12.200423 4, 0xFFFF, sum = 0
1015 01:00:12.203396 5, 0xFFFF, sum = 0
1016 01:00:12.203884 6, 0xFFFF, sum = 0
1017 01:00:12.206941 7, 0xFFFF, sum = 0
1018 01:00:12.209973 8, 0xFFFF, sum = 0
1019 01:00:12.210413 9, 0x0, sum = 1
1020 01:00:12.210778 10, 0x0, sum = 2
1021 01:00:12.213345 11, 0x0, sum = 3
1022 01:00:12.213877 12, 0x0, sum = 4
1023 01:00:12.216930 best_step = 10
1024 01:00:12.217363
1025 01:00:12.217778 ==
1026 01:00:12.219991 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 01:00:12.223484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 01:00:12.223917 ==
1029 01:00:12.226689 RX Vref Scan: 1
1030 01:00:12.227178
1031 01:00:12.227583 Set Vref Range= 32 -> 127
1032 01:00:12.227906
1033 01:00:12.229924 RX Vref 32 -> 127, step: 1
1034 01:00:12.230393
1035 01:00:12.233550 RX Delay -111 -> 252, step: 8
1036 01:00:12.233986
1037 01:00:12.236774 Set Vref, RX VrefLevel [Byte0]: 32
1038 01:00:12.240141 [Byte1]: 32
1039 01:00:12.240769
1040 01:00:12.243190 Set Vref, RX VrefLevel [Byte0]: 33
1041 01:00:12.246637 [Byte1]: 33
1042 01:00:12.250438
1043 01:00:12.251030 Set Vref, RX VrefLevel [Byte0]: 34
1044 01:00:12.253863 [Byte1]: 34
1045 01:00:12.258059
1046 01:00:12.258488 Set Vref, RX VrefLevel [Byte0]: 35
1047 01:00:12.262128 [Byte1]: 35
1048 01:00:12.265781
1049 01:00:12.266370 Set Vref, RX VrefLevel [Byte0]: 36
1050 01:00:12.269219 [Byte1]: 36
1051 01:00:12.273633
1052 01:00:12.274197 Set Vref, RX VrefLevel [Byte0]: 37
1053 01:00:12.276850 [Byte1]: 37
1054 01:00:12.281319
1055 01:00:12.281886 Set Vref, RX VrefLevel [Byte0]: 38
1056 01:00:12.284471 [Byte1]: 38
1057 01:00:12.288964
1058 01:00:12.289526 Set Vref, RX VrefLevel [Byte0]: 39
1059 01:00:12.292121 [Byte1]: 39
1060 01:00:12.297047
1061 01:00:12.297640 Set Vref, RX VrefLevel [Byte0]: 40
1062 01:00:12.299899 [Byte1]: 40
1063 01:00:12.304537
1064 01:00:12.305071 Set Vref, RX VrefLevel [Byte0]: 41
1065 01:00:12.307556 [Byte1]: 41
1066 01:00:12.311713
1067 01:00:12.312310 Set Vref, RX VrefLevel [Byte0]: 42
1068 01:00:12.314843 [Byte1]: 42
1069 01:00:12.319382
1070 01:00:12.319811 Set Vref, RX VrefLevel [Byte0]: 43
1071 01:00:12.322785 [Byte1]: 43
1072 01:00:12.326736
1073 01:00:12.327165 Set Vref, RX VrefLevel [Byte0]: 44
1074 01:00:12.330254 [Byte1]: 44
1075 01:00:12.334653
1076 01:00:12.335108 Set Vref, RX VrefLevel [Byte0]: 45
1077 01:00:12.338118 [Byte1]: 45
1078 01:00:12.342497
1079 01:00:12.342925 Set Vref, RX VrefLevel [Byte0]: 46
1080 01:00:12.345901 [Byte1]: 46
1081 01:00:12.349855
1082 01:00:12.350295 Set Vref, RX VrefLevel [Byte0]: 47
1083 01:00:12.353352 [Byte1]: 47
1084 01:00:12.358179
1085 01:00:12.358607 Set Vref, RX VrefLevel [Byte0]: 48
1086 01:00:12.361641 [Byte1]: 48
1087 01:00:12.366050
1088 01:00:12.366560 Set Vref, RX VrefLevel [Byte0]: 49
1089 01:00:12.369555 [Byte1]: 49
1090 01:00:12.372994
1091 01:00:12.373665 Set Vref, RX VrefLevel [Byte0]: 50
1092 01:00:12.376472 [Byte1]: 50
1093 01:00:12.380503
1094 01:00:12.380930 Set Vref, RX VrefLevel [Byte0]: 51
1095 01:00:12.384000 [Byte1]: 51
1096 01:00:12.388038
1097 01:00:12.388648 Set Vref, RX VrefLevel [Byte0]: 52
1098 01:00:12.391378 [Byte1]: 52
1099 01:00:12.395790
1100 01:00:12.396214 Set Vref, RX VrefLevel [Byte0]: 53
1101 01:00:12.399074 [Byte1]: 53
1102 01:00:12.403461
1103 01:00:12.403886 Set Vref, RX VrefLevel [Byte0]: 54
1104 01:00:12.406755 [Byte1]: 54
1105 01:00:12.411243
1106 01:00:12.411670 Set Vref, RX VrefLevel [Byte0]: 55
1107 01:00:12.414667 [Byte1]: 55
1108 01:00:12.418887
1109 01:00:12.419317 Set Vref, RX VrefLevel [Byte0]: 56
1110 01:00:12.422164 [Byte1]: 56
1111 01:00:12.426626
1112 01:00:12.427158 Set Vref, RX VrefLevel [Byte0]: 57
1113 01:00:12.429823 [Byte1]: 57
1114 01:00:12.434023
1115 01:00:12.434448 Set Vref, RX VrefLevel [Byte0]: 58
1116 01:00:12.437408 [Byte1]: 58
1117 01:00:12.441705
1118 01:00:12.442234 Set Vref, RX VrefLevel [Byte0]: 59
1119 01:00:12.445230 [Byte1]: 59
1120 01:00:12.449567
1121 01:00:12.450097 Set Vref, RX VrefLevel [Byte0]: 60
1122 01:00:12.452491 [Byte1]: 60
1123 01:00:12.457070
1124 01:00:12.457574 Set Vref, RX VrefLevel [Byte0]: 61
1125 01:00:12.460114 [Byte1]: 61
1126 01:00:12.464755
1127 01:00:12.465314 Set Vref, RX VrefLevel [Byte0]: 62
1128 01:00:12.467801 [Byte1]: 62
1129 01:00:12.472366
1130 01:00:12.472857 Set Vref, RX VrefLevel [Byte0]: 63
1131 01:00:12.475534 [Byte1]: 63
1132 01:00:12.479925
1133 01:00:12.480449 Set Vref, RX VrefLevel [Byte0]: 64
1134 01:00:12.483866 [Byte1]: 64
1135 01:00:12.487965
1136 01:00:12.488495 Set Vref, RX VrefLevel [Byte0]: 65
1137 01:00:12.490795 [Byte1]: 65
1138 01:00:12.495362
1139 01:00:12.495982 Set Vref, RX VrefLevel [Byte0]: 66
1140 01:00:12.498776 [Byte1]: 66
1141 01:00:12.503319
1142 01:00:12.503911 Set Vref, RX VrefLevel [Byte0]: 67
1143 01:00:12.506083 [Byte1]: 67
1144 01:00:12.510396
1145 01:00:12.510822 Set Vref, RX VrefLevel [Byte0]: 68
1146 01:00:12.514460 [Byte1]: 68
1147 01:00:12.518208
1148 01:00:12.518736 Set Vref, RX VrefLevel [Byte0]: 69
1149 01:00:12.521912 [Byte1]: 69
1150 01:00:12.526077
1151 01:00:12.526603 Set Vref, RX VrefLevel [Byte0]: 70
1152 01:00:12.529654 [Byte1]: 70
1153 01:00:12.533701
1154 01:00:12.534229 Set Vref, RX VrefLevel [Byte0]: 71
1155 01:00:12.537101 [Byte1]: 71
1156 01:00:12.541056
1157 01:00:12.541824 Set Vref, RX VrefLevel [Byte0]: 72
1158 01:00:12.544516 [Byte1]: 72
1159 01:00:12.548664
1160 01:00:12.549237 Set Vref, RX VrefLevel [Byte0]: 73
1161 01:00:12.551797 [Byte1]: 73
1162 01:00:12.556489
1163 01:00:12.556982 Set Vref, RX VrefLevel [Byte0]: 74
1164 01:00:12.559674 [Byte1]: 74
1165 01:00:12.563925
1166 01:00:12.564468 Set Vref, RX VrefLevel [Byte0]: 75
1167 01:00:12.567104 [Byte1]: 75
1168 01:00:12.571477
1169 01:00:12.572097 Set Vref, RX VrefLevel [Byte0]: 76
1170 01:00:12.574859 [Byte1]: 76
1171 01:00:12.579268
1172 01:00:12.579695 Set Vref, RX VrefLevel [Byte0]: 77
1173 01:00:12.582350 [Byte1]: 77
1174 01:00:12.587162
1175 01:00:12.587692 Set Vref, RX VrefLevel [Byte0]: 78
1176 01:00:12.590149 [Byte1]: 78
1177 01:00:12.594620
1178 01:00:12.595146 Final RX Vref Byte 0 = 56 to rank0
1179 01:00:12.598066 Final RX Vref Byte 1 = 58 to rank0
1180 01:00:12.601126 Final RX Vref Byte 0 = 56 to rank1
1181 01:00:12.604947 Final RX Vref Byte 1 = 58 to rank1==
1182 01:00:12.608167 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 01:00:12.614697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 01:00:12.615232 ==
1185 01:00:12.615574 DQS Delay:
1186 01:00:12.615887 DQS0 = 0, DQS1 = 0
1187 01:00:12.617880 DQM Delay:
1188 01:00:12.618305 DQM0 = 81, DQM1 = 68
1189 01:00:12.621705 DQ Delay:
1190 01:00:12.624948 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1191 01:00:12.628352 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1192 01:00:12.628884 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1193 01:00:12.634526 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1194 01:00:12.635025
1195 01:00:12.635437
1196 01:00:12.641054 [DQSOSCAuto] RK0, (LSB)MR18= 0x2322, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1197 01:00:12.644297 CH0 RK0: MR19=606, MR18=2322
1198 01:00:12.650876 CH0_RK0: MR19=0x606, MR18=0x2322, DQSOSC=401, MR23=63, INC=91, DEC=61
1199 01:00:12.651418
1200 01:00:12.654371 ----->DramcWriteLeveling(PI) begin...
1201 01:00:12.654876 ==
1202 01:00:12.657713 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 01:00:12.660795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 01:00:12.661228 ==
1205 01:00:12.664205 Write leveling (Byte 0): 31 => 31
1206 01:00:12.667137 Write leveling (Byte 1): 29 => 29
1207 01:00:12.670526 DramcWriteLeveling(PI) end<-----
1208 01:00:12.670609
1209 01:00:12.670675 ==
1210 01:00:12.673854 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 01:00:12.677118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 01:00:12.677229 ==
1213 01:00:12.680687 [Gating] SW mode calibration
1214 01:00:12.687228 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 01:00:12.693923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 01:00:12.697159 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 01:00:12.700438 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 01:00:12.707082 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1219 01:00:12.710535 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 01:00:12.713886 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 01:00:12.720510 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 01:00:12.723741 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 01:00:12.727249 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 01:00:12.733969 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 01:00:12.737297 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 01:00:12.740528 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 01:00:12.747365 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 01:00:12.750622 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:00:12.753996 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:00:12.801423 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:00:12.802119 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 01:00:12.803021 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:00:12.803573 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1234 01:00:12.804135 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1235 01:00:12.804655 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:00:12.805193 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 01:00:12.805759 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 01:00:12.806277 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:00:12.806796 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:00:12.807357 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 01:00:12.845735 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:00:12.846342 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1243 01:00:12.846723 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 01:00:12.847401 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 01:00:12.847748 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 01:00:12.848062 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 01:00:12.848390 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 01:00:12.848694 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 01:00:12.848989 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1250 01:00:12.849368 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (1 0) (1 0)
1251 01:00:12.853009 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 01:00:12.856715 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 01:00:12.859667 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 01:00:12.863230 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 01:00:12.870026 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 01:00:12.873382 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 01:00:12.876671 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1258 01:00:12.883673 0 11 8 | B1->B0 | 2f2f 4141 | 0 0 | (1 1) (0 0)
1259 01:00:12.887316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 01:00:12.890016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 01:00:12.896854 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 01:00:12.900320 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 01:00:12.903852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 01:00:12.910370 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 01:00:12.913808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 01:00:12.917821 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 01:00:12.921644 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 01:00:12.925380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 01:00:12.932342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 01:00:12.935633 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 01:00:12.938923 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 01:00:12.942358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 01:00:12.949245 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 01:00:12.952472 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 01:00:12.955684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 01:00:12.962596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 01:00:12.965802 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 01:00:12.969045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 01:00:12.975813 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 01:00:12.979000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 01:00:12.982439 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 01:00:12.989120 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 01:00:12.989756 Total UI for P1: 0, mck2ui 16
1284 01:00:12.995711 best dqsien dly found for B0: ( 0, 14, 6)
1285 01:00:12.999013 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 01:00:13.002655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 01:00:13.005720 Total UI for P1: 0, mck2ui 16
1288 01:00:13.008907 best dqsien dly found for B1: ( 0, 14, 10)
1289 01:00:13.012446 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1290 01:00:13.015799 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1291 01:00:13.016230
1292 01:00:13.019170 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 01:00:13.025951 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1294 01:00:13.026372 [Gating] SW calibration Done
1295 01:00:13.028999 ==
1296 01:00:13.029417 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 01:00:13.035608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 01:00:13.036030 ==
1299 01:00:13.036362 RX Vref Scan: 0
1300 01:00:13.036670
1301 01:00:13.038913 RX Vref 0 -> 0, step: 1
1302 01:00:13.039331
1303 01:00:13.042236 RX Delay -130 -> 252, step: 16
1304 01:00:13.045570 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1305 01:00:13.048781 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1306 01:00:13.052103 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1307 01:00:13.059137 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1308 01:00:13.062428 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1309 01:00:13.066172 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1310 01:00:13.068887 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1311 01:00:13.072578 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1312 01:00:13.079350 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1313 01:00:13.082638 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1314 01:00:13.085560 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1315 01:00:13.089426 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1316 01:00:13.092527 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1317 01:00:13.099542 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1318 01:00:13.102284 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1319 01:00:13.105887 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1320 01:00:13.106409 ==
1321 01:00:13.108953 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 01:00:13.112476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 01:00:13.112971 ==
1324 01:00:13.115688 DQS Delay:
1325 01:00:13.116216 DQS0 = 0, DQS1 = 0
1326 01:00:13.118940 DQM Delay:
1327 01:00:13.119360 DQM0 = 80, DQM1 = 71
1328 01:00:13.119696 DQ Delay:
1329 01:00:13.122534 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =69
1330 01:00:13.126081 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1331 01:00:13.128935 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1332 01:00:13.132274 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1333 01:00:13.132695
1334 01:00:13.133030
1335 01:00:13.135811 ==
1336 01:00:13.139057 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 01:00:13.142282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 01:00:13.142714 ==
1339 01:00:13.143050
1340 01:00:13.143363
1341 01:00:13.145517 TX Vref Scan disable
1342 01:00:13.145946 == TX Byte 0 ==
1343 01:00:13.148761 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1344 01:00:13.155721 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1345 01:00:13.156149 == TX Byte 1 ==
1346 01:00:13.158769 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1347 01:00:13.165371 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1348 01:00:13.165909 ==
1349 01:00:13.168592 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 01:00:13.171947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 01:00:13.172371 ==
1352 01:00:13.185155 TX Vref=22, minBit 0, minWin=27, winSum=435
1353 01:00:13.188540 TX Vref=24, minBit 3, minWin=27, winSum=441
1354 01:00:13.191864 TX Vref=26, minBit 11, minWin=26, winSum=442
1355 01:00:13.195087 TX Vref=28, minBit 7, minWin=27, winSum=448
1356 01:00:13.198701 TX Vref=30, minBit 8, minWin=27, winSum=448
1357 01:00:13.205383 TX Vref=32, minBit 1, minWin=27, winSum=445
1358 01:00:13.208556 [TxChooseVref] Worse bit 7, Min win 27, Win sum 448, Final Vref 28
1359 01:00:13.208986
1360 01:00:13.212078 Final TX Range 1 Vref 28
1361 01:00:13.212539
1362 01:00:13.212886 ==
1363 01:00:13.215172 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 01:00:13.218658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 01:00:13.219104 ==
1366 01:00:13.221723
1367 01:00:13.222203
1368 01:00:13.222577 TX Vref Scan disable
1369 01:00:13.225180 == TX Byte 0 ==
1370 01:00:13.228677 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1371 01:00:13.231793 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1372 01:00:13.235234 == TX Byte 1 ==
1373 01:00:13.238381 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1374 01:00:13.241924 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1375 01:00:13.245284
1376 01:00:13.245531 [DATLAT]
1377 01:00:13.245712 Freq=800, CH0 RK1
1378 01:00:13.245878
1379 01:00:13.248609 DATLAT Default: 0xa
1380 01:00:13.248830 0, 0xFFFF, sum = 0
1381 01:00:13.251746 1, 0xFFFF, sum = 0
1382 01:00:13.251972 2, 0xFFFF, sum = 0
1383 01:00:13.255268 3, 0xFFFF, sum = 0
1384 01:00:13.255494 4, 0xFFFF, sum = 0
1385 01:00:13.258647 5, 0xFFFF, sum = 0
1386 01:00:13.258874 6, 0xFFFF, sum = 0
1387 01:00:13.261889 7, 0xFFFF, sum = 0
1388 01:00:13.264945 8, 0xFFFF, sum = 0
1389 01:00:13.265030 9, 0x0, sum = 1
1390 01:00:13.265096 10, 0x0, sum = 2
1391 01:00:13.268493 11, 0x0, sum = 3
1392 01:00:13.268577 12, 0x0, sum = 4
1393 01:00:13.271653 best_step = 10
1394 01:00:13.271735
1395 01:00:13.271800 ==
1396 01:00:13.274962 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 01:00:13.278650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 01:00:13.278734 ==
1399 01:00:13.281632 RX Vref Scan: 0
1400 01:00:13.281715
1401 01:00:13.281780 RX Vref 0 -> 0, step: 1
1402 01:00:13.281840
1403 01:00:13.285045 RX Delay -111 -> 252, step: 8
1404 01:00:13.291934 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1405 01:00:13.295289 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1406 01:00:13.298815 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1407 01:00:13.302323 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1408 01:00:13.305586 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1409 01:00:13.311969 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1410 01:00:13.315261 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1411 01:00:13.318635 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1412 01:00:13.321684 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1413 01:00:13.325086 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1414 01:00:13.331795 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1415 01:00:13.335264 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1416 01:00:13.338651 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1417 01:00:13.341880 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1418 01:00:13.345262 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1419 01:00:13.351775 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1420 01:00:13.352214 ==
1421 01:00:13.355006 Dram Type= 6, Freq= 0, CH_0, rank 1
1422 01:00:13.358458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 01:00:13.358799 ==
1424 01:00:13.359074 DQS Delay:
1425 01:00:13.361693 DQS0 = 0, DQS1 = 0
1426 01:00:13.362093 DQM Delay:
1427 01:00:13.365090 DQM0 = 78, DQM1 = 70
1428 01:00:13.365538 DQ Delay:
1429 01:00:13.368299 DQ0 =80, DQ1 =80, DQ2 =76, DQ3 =72
1430 01:00:13.371904 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =88
1431 01:00:13.375134 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1432 01:00:13.378355 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1433 01:00:13.378797
1434 01:00:13.379200
1435 01:00:13.388529 [DQSOSCAuto] RK1, (LSB)MR18= 0x451f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1436 01:00:13.388998 CH0 RK1: MR19=606, MR18=451F
1437 01:00:13.394883 CH0_RK1: MR19=0x606, MR18=0x451F, DQSOSC=392, MR23=63, INC=96, DEC=64
1438 01:00:13.398337 [RxdqsGatingPostProcess] freq 800
1439 01:00:13.404877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1440 01:00:13.407976 Pre-setting of DQS Precalculation
1441 01:00:13.411465 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1442 01:00:13.411574 ==
1443 01:00:13.414528 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 01:00:13.418227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 01:00:13.421441 ==
1446 01:00:13.424777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 01:00:13.431462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 01:00:13.440067 [CA 0] Center 36 (6~67) winsize 62
1449 01:00:13.443288 [CA 1] Center 37 (7~67) winsize 61
1450 01:00:13.446774 [CA 2] Center 34 (5~64) winsize 60
1451 01:00:13.450018 [CA 3] Center 34 (4~64) winsize 61
1452 01:00:13.453560 [CA 4] Center 35 (5~65) winsize 61
1453 01:00:13.456826 [CA 5] Center 34 (4~64) winsize 61
1454 01:00:13.456934
1455 01:00:13.459866 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 01:00:13.459968
1457 01:00:13.463445 [CATrainingPosCal] consider 1 rank data
1458 01:00:13.466862 u2DelayCellTimex100 = 270/100 ps
1459 01:00:13.470168 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 01:00:13.473688 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1461 01:00:13.480002 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1462 01:00:13.483339 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1463 01:00:13.486797 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 01:00:13.490152 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 01:00:13.490234
1466 01:00:13.493391 CA PerBit enable=1, Macro0, CA PI delay=34
1467 01:00:13.493497
1468 01:00:13.497017 [CBTSetCACLKResult] CA Dly = 34
1469 01:00:13.497115 CS Dly: 5 (0~36)
1470 01:00:13.497194 ==
1471 01:00:13.500466 Dram Type= 6, Freq= 0, CH_1, rank 1
1472 01:00:13.506964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 01:00:13.507488 ==
1474 01:00:13.510541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1475 01:00:13.517172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1476 01:00:13.526700 [CA 0] Center 37 (7~67) winsize 61
1477 01:00:13.529850 [CA 1] Center 36 (6~67) winsize 62
1478 01:00:13.532906 [CA 2] Center 35 (5~65) winsize 61
1479 01:00:13.536076 [CA 3] Center 33 (3~64) winsize 62
1480 01:00:13.539648 [CA 4] Center 34 (4~65) winsize 62
1481 01:00:13.542859 [CA 5] Center 33 (3~64) winsize 62
1482 01:00:13.542947
1483 01:00:13.546442 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1484 01:00:13.546537
1485 01:00:13.549684 [CATrainingPosCal] consider 2 rank data
1486 01:00:13.553012 u2DelayCellTimex100 = 270/100 ps
1487 01:00:13.556520 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1488 01:00:13.559511 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1489 01:00:13.566201 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1490 01:00:13.569460 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1491 01:00:13.572791 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 01:00:13.576121 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1493 01:00:13.576203
1494 01:00:13.579834 CA PerBit enable=1, Macro0, CA PI delay=34
1495 01:00:13.579926
1496 01:00:13.583457 [CBTSetCACLKResult] CA Dly = 34
1497 01:00:13.583564 CS Dly: 6 (0~38)
1498 01:00:13.583667
1499 01:00:13.587140 ----->DramcWriteLeveling(PI) begin...
1500 01:00:13.587245 ==
1501 01:00:13.591225 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 01:00:13.594532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 01:00:13.594639 ==
1504 01:00:13.598132 Write leveling (Byte 0): 26 => 26
1505 01:00:13.601775 Write leveling (Byte 1): 30 => 30
1506 01:00:13.605582 DramcWriteLeveling(PI) end<-----
1507 01:00:13.605659
1508 01:00:13.605729 ==
1509 01:00:13.608854 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 01:00:13.612889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 01:00:13.612967 ==
1512 01:00:13.615839 [Gating] SW mode calibration
1513 01:00:13.622655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1514 01:00:13.629385 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1515 01:00:13.632554 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 01:00:13.635798 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1517 01:00:13.639010 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1518 01:00:13.645756 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 01:00:13.649076 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 01:00:13.652455 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 01:00:13.659032 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 01:00:13.662365 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 01:00:13.665916 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 01:00:13.672477 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 01:00:13.675893 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 01:00:13.679232 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:00:13.685891 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:00:13.689035 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:00:13.692618 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:00:13.699058 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:00:13.702507 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:00:13.705697 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:00:13.712276 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1534 01:00:13.715869 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 01:00:13.719101 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 01:00:13.725639 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:00:13.729057 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:00:13.732549 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:00:13.739293 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:00:13.742723 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:00:13.745579 0 9 8 | B1->B0 | 2c2c 2828 | 1 0 | (1 1) (1 1)
1542 01:00:13.752000 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1543 01:00:13.755363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 01:00:13.758887 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 01:00:13.762188 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 01:00:13.768936 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 01:00:13.772258 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 01:00:13.775427 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1549 01:00:13.782098 0 10 8 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
1550 01:00:13.785451 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 01:00:13.788868 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 01:00:13.795477 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 01:00:13.798674 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:00:13.802326 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:00:13.808596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 01:00:13.811968 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1557 01:00:13.815478 0 11 8 | B1->B0 | 3636 3434 | 0 1 | (0 0) (1 1)
1558 01:00:13.822135 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 01:00:13.825378 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 01:00:13.828714 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 01:00:13.835503 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 01:00:13.838841 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 01:00:13.842203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 01:00:13.848706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1565 01:00:13.852013 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 01:00:13.855470 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 01:00:13.862423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 01:00:13.865603 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 01:00:13.868748 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 01:00:13.872101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 01:00:13.878756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 01:00:13.882050 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 01:00:13.885256 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 01:00:13.891881 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 01:00:13.895280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 01:00:13.898601 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 01:00:13.905433 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 01:00:13.908630 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 01:00:13.912017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 01:00:13.918849 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 01:00:13.922229 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 01:00:13.925360 Total UI for P1: 0, mck2ui 16
1583 01:00:13.928792 best dqsien dly found for B0: ( 0, 14, 6)
1584 01:00:13.932063 Total UI for P1: 0, mck2ui 16
1585 01:00:13.935502 best dqsien dly found for B1: ( 0, 14, 6)
1586 01:00:13.938711 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1587 01:00:13.942232 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1588 01:00:13.942313
1589 01:00:13.945564 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 01:00:13.948830 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1591 01:00:13.952128 [Gating] SW calibration Done
1592 01:00:13.952229 ==
1593 01:00:13.955543 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 01:00:13.958952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 01:00:13.959034 ==
1596 01:00:13.962299 RX Vref Scan: 0
1597 01:00:13.962379
1598 01:00:13.965621 RX Vref 0 -> 0, step: 1
1599 01:00:13.965701
1600 01:00:13.965765 RX Delay -130 -> 252, step: 16
1601 01:00:13.972206 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1602 01:00:13.975468 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1603 01:00:13.979048 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1604 01:00:13.982400 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1605 01:00:13.985312 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1606 01:00:13.992013 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1607 01:00:13.995289 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1608 01:00:13.998632 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1609 01:00:14.002085 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1610 01:00:14.005296 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1611 01:00:14.012156 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1612 01:00:14.015450 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1613 01:00:14.018869 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1614 01:00:14.022203 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1615 01:00:14.025466 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1616 01:00:14.032292 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1617 01:00:14.032383 ==
1618 01:00:14.035495 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 01:00:14.038889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 01:00:14.038970 ==
1621 01:00:14.039039 DQS Delay:
1622 01:00:14.042361 DQS0 = 0, DQS1 = 0
1623 01:00:14.042442 DQM Delay:
1624 01:00:14.045297 DQM0 = 82, DQM1 = 75
1625 01:00:14.045394 DQ Delay:
1626 01:00:14.048867 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1627 01:00:14.052285 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1628 01:00:14.055597 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1629 01:00:14.058894 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 01:00:14.058974
1631 01:00:14.059037
1632 01:00:14.059096 ==
1633 01:00:14.062333 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 01:00:14.065795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 01:00:14.065964 ==
1636 01:00:14.066047
1637 01:00:14.069026
1638 01:00:14.069190 TX Vref Scan disable
1639 01:00:14.072505 == TX Byte 0 ==
1640 01:00:14.075709 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1641 01:00:14.078895 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1642 01:00:14.082102 == TX Byte 1 ==
1643 01:00:14.085268 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1644 01:00:14.088786 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1645 01:00:14.088925 ==
1646 01:00:14.092114 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 01:00:14.098600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 01:00:14.098767 ==
1649 01:00:14.110793 TX Vref=22, minBit 1, minWin=27, winSum=444
1650 01:00:14.114393 TX Vref=24, minBit 5, minWin=27, winSum=445
1651 01:00:14.117875 TX Vref=26, minBit 10, minWin=27, winSum=449
1652 01:00:14.120789 TX Vref=28, minBit 5, minWin=27, winSum=451
1653 01:00:14.124410 TX Vref=30, minBit 5, minWin=27, winSum=450
1654 01:00:14.130814 TX Vref=32, minBit 5, minWin=27, winSum=450
1655 01:00:14.134327 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 28
1656 01:00:14.134493
1657 01:00:14.137740 Final TX Range 1 Vref 28
1658 01:00:14.137910
1659 01:00:14.137998 ==
1660 01:00:14.140841 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 01:00:14.144319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 01:00:14.144502 ==
1663 01:00:14.147219
1664 01:00:14.147347
1665 01:00:14.147427 TX Vref Scan disable
1666 01:00:14.150934 == TX Byte 0 ==
1667 01:00:14.154561 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1668 01:00:14.158299 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1669 01:00:14.161566 == TX Byte 1 ==
1670 01:00:14.164814 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1671 01:00:14.168207 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1672 01:00:14.168378
1673 01:00:14.171638 [DATLAT]
1674 01:00:14.171812 Freq=800, CH1 RK0
1675 01:00:14.171950
1676 01:00:14.174756 DATLAT Default: 0xa
1677 01:00:14.174953 0, 0xFFFF, sum = 0
1678 01:00:14.178202 1, 0xFFFF, sum = 0
1679 01:00:14.178443 2, 0xFFFF, sum = 0
1680 01:00:14.181538 3, 0xFFFF, sum = 0
1681 01:00:14.181791 4, 0xFFFF, sum = 0
1682 01:00:14.185293 5, 0xFFFF, sum = 0
1683 01:00:14.185624 6, 0xFFFF, sum = 0
1684 01:00:14.188350 7, 0xFFFF, sum = 0
1685 01:00:14.188738 8, 0xFFFF, sum = 0
1686 01:00:14.191786 9, 0x0, sum = 1
1687 01:00:14.192251 10, 0x0, sum = 2
1688 01:00:14.195389 11, 0x0, sum = 3
1689 01:00:14.195898 12, 0x0, sum = 4
1690 01:00:14.198587 best_step = 10
1691 01:00:14.199022
1692 01:00:14.199354 ==
1693 01:00:14.201872 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 01:00:14.205460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 01:00:14.205929 ==
1696 01:00:14.206270 RX Vref Scan: 1
1697 01:00:14.206583
1698 01:00:14.208599 Set Vref Range= 32 -> 127
1699 01:00:14.209023
1700 01:00:14.211889 RX Vref 32 -> 127, step: 1
1701 01:00:14.212352
1702 01:00:14.215423 RX Delay -111 -> 252, step: 8
1703 01:00:14.215867
1704 01:00:14.218620 Set Vref, RX VrefLevel [Byte0]: 32
1705 01:00:14.221801 [Byte1]: 32
1706 01:00:14.222426
1707 01:00:14.225094 Set Vref, RX VrefLevel [Byte0]: 33
1708 01:00:14.228515 [Byte1]: 33
1709 01:00:14.228896
1710 01:00:14.231658 Set Vref, RX VrefLevel [Byte0]: 34
1711 01:00:14.234597 [Byte1]: 34
1712 01:00:14.238851
1713 01:00:14.238959 Set Vref, RX VrefLevel [Byte0]: 35
1714 01:00:14.242172 [Byte1]: 35
1715 01:00:14.246543
1716 01:00:14.246655 Set Vref, RX VrefLevel [Byte0]: 36
1717 01:00:14.249872 [Byte1]: 36
1718 01:00:14.253906
1719 01:00:14.254017 Set Vref, RX VrefLevel [Byte0]: 37
1720 01:00:14.257372 [Byte1]: 37
1721 01:00:14.261692
1722 01:00:14.261772 Set Vref, RX VrefLevel [Byte0]: 38
1723 01:00:14.265311 [Byte1]: 38
1724 01:00:14.269607
1725 01:00:14.269687 Set Vref, RX VrefLevel [Byte0]: 39
1726 01:00:14.272850 [Byte1]: 39
1727 01:00:14.277065
1728 01:00:14.277172 Set Vref, RX VrefLevel [Byte0]: 40
1729 01:00:14.280243 [Byte1]: 40
1730 01:00:14.284740
1731 01:00:14.284820 Set Vref, RX VrefLevel [Byte0]: 41
1732 01:00:14.287881 [Byte1]: 41
1733 01:00:14.292598
1734 01:00:14.292684 Set Vref, RX VrefLevel [Byte0]: 42
1735 01:00:14.295619 [Byte1]: 42
1736 01:00:14.300049
1737 01:00:14.300149 Set Vref, RX VrefLevel [Byte0]: 43
1738 01:00:14.303526 [Byte1]: 43
1739 01:00:14.307979
1740 01:00:14.308099 Set Vref, RX VrefLevel [Byte0]: 44
1741 01:00:14.311070 [Byte1]: 44
1742 01:00:14.315682
1743 01:00:14.315815 Set Vref, RX VrefLevel [Byte0]: 45
1744 01:00:14.318517 [Byte1]: 45
1745 01:00:14.323294
1746 01:00:14.323466 Set Vref, RX VrefLevel [Byte0]: 46
1747 01:00:14.326358 [Byte1]: 46
1748 01:00:14.330834
1749 01:00:14.331036 Set Vref, RX VrefLevel [Byte0]: 47
1750 01:00:14.334123 [Byte1]: 47
1751 01:00:14.338424
1752 01:00:14.338831 Set Vref, RX VrefLevel [Byte0]: 48
1753 01:00:14.341577 [Byte1]: 48
1754 01:00:14.345685
1755 01:00:14.345797 Set Vref, RX VrefLevel [Byte0]: 49
1756 01:00:14.349284 [Byte1]: 49
1757 01:00:14.353552
1758 01:00:14.353632 Set Vref, RX VrefLevel [Byte0]: 50
1759 01:00:14.356733 [Byte1]: 50
1760 01:00:14.361075
1761 01:00:14.361185 Set Vref, RX VrefLevel [Byte0]: 51
1762 01:00:14.364413 [Byte1]: 51
1763 01:00:14.368644
1764 01:00:14.368754 Set Vref, RX VrefLevel [Byte0]: 52
1765 01:00:14.372104 [Byte1]: 52
1766 01:00:14.376847
1767 01:00:14.377301 Set Vref, RX VrefLevel [Byte0]: 53
1768 01:00:14.380208 [Byte1]: 53
1769 01:00:14.384315
1770 01:00:14.384733 Set Vref, RX VrefLevel [Byte0]: 54
1771 01:00:14.387938 [Byte1]: 54
1772 01:00:14.391962
1773 01:00:14.392397 Set Vref, RX VrefLevel [Byte0]: 55
1774 01:00:14.395322 [Byte1]: 55
1775 01:00:14.399688
1776 01:00:14.400106 Set Vref, RX VrefLevel [Byte0]: 56
1777 01:00:14.402940 [Byte1]: 56
1778 01:00:14.407555
1779 01:00:14.407971 Set Vref, RX VrefLevel [Byte0]: 57
1780 01:00:14.410594 [Byte1]: 57
1781 01:00:14.415051
1782 01:00:14.415465 Set Vref, RX VrefLevel [Byte0]: 58
1783 01:00:14.418318 [Byte1]: 58
1784 01:00:14.423085
1785 01:00:14.423607 Set Vref, RX VrefLevel [Byte0]: 59
1786 01:00:14.425981 [Byte1]: 59
1787 01:00:14.430757
1788 01:00:14.431175 Set Vref, RX VrefLevel [Byte0]: 60
1789 01:00:14.433733 [Byte1]: 60
1790 01:00:14.437956
1791 01:00:14.438389 Set Vref, RX VrefLevel [Byte0]: 61
1792 01:00:14.441580 [Byte1]: 61
1793 01:00:14.445838
1794 01:00:14.446255 Set Vref, RX VrefLevel [Byte0]: 62
1795 01:00:14.449022 [Byte1]: 62
1796 01:00:14.453725
1797 01:00:14.454244 Set Vref, RX VrefLevel [Byte0]: 63
1798 01:00:14.457033 [Byte1]: 63
1799 01:00:14.461090
1800 01:00:14.461574 Set Vref, RX VrefLevel [Byte0]: 64
1801 01:00:14.464962 [Byte1]: 64
1802 01:00:14.468692
1803 01:00:14.469118 Set Vref, RX VrefLevel [Byte0]: 65
1804 01:00:14.472236 [Byte1]: 65
1805 01:00:14.476714
1806 01:00:14.477156 Set Vref, RX VrefLevel [Byte0]: 66
1807 01:00:14.479574 [Byte1]: 66
1808 01:00:14.484371
1809 01:00:14.484906 Set Vref, RX VrefLevel [Byte0]: 67
1810 01:00:14.487295 [Byte1]: 67
1811 01:00:14.491548
1812 01:00:14.491974 Set Vref, RX VrefLevel [Byte0]: 68
1813 01:00:14.494856 [Byte1]: 68
1814 01:00:14.499119
1815 01:00:14.499535 Set Vref, RX VrefLevel [Byte0]: 69
1816 01:00:14.502731 [Byte1]: 69
1817 01:00:14.506672
1818 01:00:14.507090 Set Vref, RX VrefLevel [Byte0]: 70
1819 01:00:14.510182 [Byte1]: 70
1820 01:00:14.514523
1821 01:00:14.514938 Set Vref, RX VrefLevel [Byte0]: 71
1822 01:00:14.517885 [Byte1]: 71
1823 01:00:14.522075
1824 01:00:14.522377 Set Vref, RX VrefLevel [Byte0]: 72
1825 01:00:14.525263 [Byte1]: 72
1826 01:00:14.529562
1827 01:00:14.529791 Set Vref, RX VrefLevel [Byte0]: 73
1828 01:00:14.532984 [Byte1]: 73
1829 01:00:14.537024
1830 01:00:14.537179 Set Vref, RX VrefLevel [Byte0]: 74
1831 01:00:14.540346 [Byte1]: 74
1832 01:00:14.544948
1833 01:00:14.545064 Final RX Vref Byte 0 = 60 to rank0
1834 01:00:14.548080 Final RX Vref Byte 1 = 55 to rank0
1835 01:00:14.551353 Final RX Vref Byte 0 = 60 to rank1
1836 01:00:14.554708 Final RX Vref Byte 1 = 55 to rank1==
1837 01:00:14.558303 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 01:00:14.564711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 01:00:14.564848 ==
1840 01:00:14.564931 DQS Delay:
1841 01:00:14.565009 DQS0 = 0, DQS1 = 0
1842 01:00:14.568132 DQM Delay:
1843 01:00:14.568235 DQM0 = 81, DQM1 = 72
1844 01:00:14.571368 DQ Delay:
1845 01:00:14.575024 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1846 01:00:14.575128 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1847 01:00:14.578159 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1848 01:00:14.581929 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
1849 01:00:14.584990
1850 01:00:14.585414
1851 01:00:14.591831 [DQSOSCAuto] RK0, (LSB)MR18= 0x1620, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1852 01:00:14.595202 CH1 RK0: MR19=606, MR18=1620
1853 01:00:14.601520 CH1_RK0: MR19=0x606, MR18=0x1620, DQSOSC=401, MR23=63, INC=91, DEC=61
1854 01:00:14.601930
1855 01:00:14.604918 ----->DramcWriteLeveling(PI) begin...
1856 01:00:14.605151 ==
1857 01:00:14.607938 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 01:00:14.611318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 01:00:14.611599 ==
1860 01:00:14.614821 Write leveling (Byte 0): 28 => 28
1861 01:00:14.618032 Write leveling (Byte 1): 30 => 30
1862 01:00:14.621265 DramcWriteLeveling(PI) end<-----
1863 01:00:14.621397
1864 01:00:14.621514 ==
1865 01:00:14.624478 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 01:00:14.627965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 01:00:14.628083 ==
1868 01:00:14.631234 [Gating] SW mode calibration
1869 01:00:14.638007 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 01:00:14.644809 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 01:00:14.648001 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 01:00:14.651469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1873 01:00:14.658047 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 01:00:14.661493 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 01:00:14.664502 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 01:00:14.671300 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 01:00:14.674521 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 01:00:14.677772 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 01:00:14.684822 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 01:00:14.688320 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:00:14.691464 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:00:14.697816 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:00:14.701246 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:00:14.704717 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:00:14.711684 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 01:00:14.714642 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 01:00:14.718025 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1888 01:00:14.724804 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1889 01:00:14.728286 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 01:00:14.731520 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 01:00:14.738229 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:00:14.741856 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 01:00:14.744864 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 01:00:14.748351 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 01:00:14.754840 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 01:00:14.757952 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1897 01:00:14.761559 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1898 01:00:14.767687 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 01:00:14.771338 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 01:00:14.774262 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 01:00:14.781147 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 01:00:14.784553 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 01:00:14.788558 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 01:00:14.795006 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (1 1)
1905 01:00:14.798204 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1906 01:00:14.801396 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 01:00:14.808211 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 01:00:14.811565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 01:00:14.814762 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 01:00:14.821628 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 01:00:14.824804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 01:00:14.827731 0 11 4 | B1->B0 | 2a2a 3535 | 1 0 | (0 0) (1 1)
1913 01:00:14.834832 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1914 01:00:14.838107 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 01:00:14.841197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 01:00:14.848148 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 01:00:14.851406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 01:00:14.854458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 01:00:14.857868 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1920 01:00:14.864480 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1921 01:00:14.868054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 01:00:14.871535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 01:00:14.878044 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 01:00:14.881224 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 01:00:14.884506 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 01:00:14.891395 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 01:00:14.894249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 01:00:14.898230 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 01:00:14.904835 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 01:00:14.907945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 01:00:14.911108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 01:00:14.917971 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 01:00:14.921558 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 01:00:14.924540 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 01:00:14.931393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1936 01:00:14.934413 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1937 01:00:14.937863 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 01:00:14.941514 Total UI for P1: 0, mck2ui 16
1939 01:00:14.944514 best dqsien dly found for B0: ( 0, 14, 2)
1940 01:00:14.947974 Total UI for P1: 0, mck2ui 16
1941 01:00:14.951370 best dqsien dly found for B1: ( 0, 14, 4)
1942 01:00:14.954224 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1943 01:00:14.957819 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1944 01:00:14.958245
1945 01:00:14.961046 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1946 01:00:14.967649 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 01:00:14.968074 [Gating] SW calibration Done
1948 01:00:14.968409 ==
1949 01:00:14.971358 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 01:00:14.977716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 01:00:14.978150 ==
1952 01:00:14.978489 RX Vref Scan: 0
1953 01:00:14.978804
1954 01:00:14.980972 RX Vref 0 -> 0, step: 1
1955 01:00:14.981400
1956 01:00:14.984395 RX Delay -130 -> 252, step: 16
1957 01:00:14.987442 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1958 01:00:14.991266 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1959 01:00:14.994359 iDelay=206, Bit 2, Center 61 (-66 ~ 189) 256
1960 01:00:15.001036 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1961 01:00:15.004206 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1962 01:00:15.007487 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1963 01:00:15.010934 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1964 01:00:15.014218 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1965 01:00:15.017440 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1966 01:00:15.024028 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1967 01:00:15.027710 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1968 01:00:15.030911 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1969 01:00:15.034318 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1970 01:00:15.037630 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1971 01:00:15.044185 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1972 01:00:15.047450 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1973 01:00:15.047867 ==
1974 01:00:15.051077 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 01:00:15.054140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 01:00:15.054560 ==
1977 01:00:15.057559 DQS Delay:
1978 01:00:15.058094 DQS0 = 0, DQS1 = 0
1979 01:00:15.058435 DQM Delay:
1980 01:00:15.060827 DQM0 = 76, DQM1 = 71
1981 01:00:15.061240 DQ Delay:
1982 01:00:15.064213 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1983 01:00:15.067613 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1984 01:00:15.070736 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1985 01:00:15.074138 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1986 01:00:15.074575
1987 01:00:15.074957
1988 01:00:15.075271 ==
1989 01:00:15.077522 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 01:00:15.084234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 01:00:15.084655 ==
1992 01:00:15.084986
1993 01:00:15.085295
1994 01:00:15.085641 TX Vref Scan disable
1995 01:00:15.087916 == TX Byte 0 ==
1996 01:00:15.091046 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 01:00:15.097803 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 01:00:15.098238 == TX Byte 1 ==
1999 01:00:15.101138 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2000 01:00:15.107830 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2001 01:00:15.108340 ==
2002 01:00:15.111344 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 01:00:15.114325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 01:00:15.114746 ==
2005 01:00:15.127205 TX Vref=22, minBit 1, minWin=27, winSum=446
2006 01:00:15.130459 TX Vref=24, minBit 0, minWin=28, winSum=454
2007 01:00:15.133419 TX Vref=26, minBit 1, minWin=27, winSum=452
2008 01:00:15.136771 TX Vref=28, minBit 1, minWin=27, winSum=456
2009 01:00:15.140112 TX Vref=30, minBit 5, minWin=27, winSum=460
2010 01:00:15.146833 TX Vref=32, minBit 1, minWin=27, winSum=455
2011 01:00:15.150291 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 24
2012 01:00:15.150808
2013 01:00:15.153901 Final TX Range 1 Vref 24
2014 01:00:15.154416
2015 01:00:15.154754 ==
2016 01:00:15.157190 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 01:00:15.160476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 01:00:15.163528 ==
2019 01:00:15.163947
2020 01:00:15.164278
2021 01:00:15.164651 TX Vref Scan disable
2022 01:00:15.167360 == TX Byte 0 ==
2023 01:00:15.170228 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 01:00:15.177113 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 01:00:15.177690 == TX Byte 1 ==
2026 01:00:15.180235 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2027 01:00:15.183665 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2028 01:00:15.187283
2029 01:00:15.187813 [DATLAT]
2030 01:00:15.188149 Freq=800, CH1 RK1
2031 01:00:15.188457
2032 01:00:15.190351 DATLAT Default: 0xa
2033 01:00:15.190768 0, 0xFFFF, sum = 0
2034 01:00:15.193834 1, 0xFFFF, sum = 0
2035 01:00:15.194255 2, 0xFFFF, sum = 0
2036 01:00:15.197147 3, 0xFFFF, sum = 0
2037 01:00:15.197613 4, 0xFFFF, sum = 0
2038 01:00:15.200758 5, 0xFFFF, sum = 0
2039 01:00:15.201273 6, 0xFFFF, sum = 0
2040 01:00:15.203739 7, 0xFFFF, sum = 0
2041 01:00:15.204159 8, 0xFFFF, sum = 0
2042 01:00:15.207376 9, 0x0, sum = 1
2043 01:00:15.207895 10, 0x0, sum = 2
2044 01:00:15.210946 11, 0x0, sum = 3
2045 01:00:15.211481 12, 0x0, sum = 4
2046 01:00:15.214059 best_step = 10
2047 01:00:15.214476
2048 01:00:15.214803 ==
2049 01:00:15.217651 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 01:00:15.220736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 01:00:15.221160 ==
2052 01:00:15.223943 RX Vref Scan: 0
2053 01:00:15.224356
2054 01:00:15.224688 RX Vref 0 -> 0, step: 1
2055 01:00:15.224993
2056 01:00:15.227231 RX Delay -111 -> 252, step: 8
2057 01:00:15.234134 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2058 01:00:15.237314 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2059 01:00:15.240385 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2060 01:00:15.243946 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2061 01:00:15.247371 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2062 01:00:15.254049 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2063 01:00:15.257216 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2064 01:00:15.260790 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2065 01:00:15.263976 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2066 01:00:15.267485 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2067 01:00:15.274173 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2068 01:00:15.277090 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2069 01:00:15.280485 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2070 01:00:15.283720 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2071 01:00:15.287252 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2072 01:00:15.293790 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2073 01:00:15.294320 ==
2074 01:00:15.297145 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 01:00:15.300291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 01:00:15.300719 ==
2077 01:00:15.301058 DQS Delay:
2078 01:00:15.304052 DQS0 = 0, DQS1 = 0
2079 01:00:15.304625 DQM Delay:
2080 01:00:15.307298 DQM0 = 78, DQM1 = 74
2081 01:00:15.307814 DQ Delay:
2082 01:00:15.310434 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2083 01:00:15.313786 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2084 01:00:15.317310 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2085 01:00:15.320431 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2086 01:00:15.320955
2087 01:00:15.321289
2088 01:00:15.330554 [DQSOSCAuto] RK1, (LSB)MR18= 0x243c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2089 01:00:15.331076 CH1 RK1: MR19=606, MR18=243C
2090 01:00:15.337319 CH1_RK1: MR19=0x606, MR18=0x243C, DQSOSC=394, MR23=63, INC=95, DEC=63
2091 01:00:15.340613 [RxdqsGatingPostProcess] freq 800
2092 01:00:15.347536 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 01:00:15.350425 Pre-setting of DQS Precalculation
2094 01:00:15.353844 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 01:00:15.360500 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 01:00:15.367316 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 01:00:15.367876
2098 01:00:15.370350
2099 01:00:15.370884 [Calibration Summary] 1600 Mbps
2100 01:00:15.373800 CH 0, Rank 0
2101 01:00:15.374216 SW Impedance : PASS
2102 01:00:15.376959 DUTY Scan : NO K
2103 01:00:15.380423 ZQ Calibration : PASS
2104 01:00:15.380940 Jitter Meter : NO K
2105 01:00:15.383607 CBT Training : PASS
2106 01:00:15.387461 Write leveling : PASS
2107 01:00:15.387982 RX DQS gating : PASS
2108 01:00:15.390408 RX DQ/DQS(RDDQC) : PASS
2109 01:00:15.393617 TX DQ/DQS : PASS
2110 01:00:15.394140 RX DATLAT : PASS
2111 01:00:15.397074 RX DQ/DQS(Engine): PASS
2112 01:00:15.397644 TX OE : NO K
2113 01:00:15.400331 All Pass.
2114 01:00:15.400751
2115 01:00:15.401081 CH 0, Rank 1
2116 01:00:15.403536 SW Impedance : PASS
2117 01:00:15.403956 DUTY Scan : NO K
2118 01:00:15.406818 ZQ Calibration : PASS
2119 01:00:15.410387 Jitter Meter : NO K
2120 01:00:15.410905 CBT Training : PASS
2121 01:00:15.413531 Write leveling : PASS
2122 01:00:15.416639 RX DQS gating : PASS
2123 01:00:15.417149 RX DQ/DQS(RDDQC) : PASS
2124 01:00:15.420565 TX DQ/DQS : PASS
2125 01:00:15.423736 RX DATLAT : PASS
2126 01:00:15.424261 RX DQ/DQS(Engine): PASS
2127 01:00:15.427018 TX OE : NO K
2128 01:00:15.427439 All Pass.
2129 01:00:15.427771
2130 01:00:15.430409 CH 1, Rank 0
2131 01:00:15.431007 SW Impedance : PASS
2132 01:00:15.433553 DUTY Scan : NO K
2133 01:00:15.437223 ZQ Calibration : PASS
2134 01:00:15.437685 Jitter Meter : NO K
2135 01:00:15.440379 CBT Training : PASS
2136 01:00:15.443613 Write leveling : PASS
2137 01:00:15.444031 RX DQS gating : PASS
2138 01:00:15.446900 RX DQ/DQS(RDDQC) : PASS
2139 01:00:15.447316 TX DQ/DQS : PASS
2140 01:00:15.450322 RX DATLAT : PASS
2141 01:00:15.453854 RX DQ/DQS(Engine): PASS
2142 01:00:15.454371 TX OE : NO K
2143 01:00:15.457047 All Pass.
2144 01:00:15.457623
2145 01:00:15.457971 CH 1, Rank 1
2146 01:00:15.460318 SW Impedance : PASS
2147 01:00:15.460837 DUTY Scan : NO K
2148 01:00:15.463315 ZQ Calibration : PASS
2149 01:00:15.467183 Jitter Meter : NO K
2150 01:00:15.467700 CBT Training : PASS
2151 01:00:15.470389 Write leveling : PASS
2152 01:00:15.473759 RX DQS gating : PASS
2153 01:00:15.474280 RX DQ/DQS(RDDQC) : PASS
2154 01:00:15.477052 TX DQ/DQS : PASS
2155 01:00:15.480074 RX DATLAT : PASS
2156 01:00:15.480492 RX DQ/DQS(Engine): PASS
2157 01:00:15.483470 TX OE : NO K
2158 01:00:15.483913 All Pass.
2159 01:00:15.484245
2160 01:00:15.487290 DramC Write-DBI off
2161 01:00:15.490353 PER_BANK_REFRESH: Hybrid Mode
2162 01:00:15.490775 TX_TRACKING: ON
2163 01:00:15.493559 [GetDramInforAfterCalByMRR] Vendor 6.
2164 01:00:15.497095 [GetDramInforAfterCalByMRR] Revision 606.
2165 01:00:15.500188 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 01:00:15.503521 MR0 0x3b3b
2167 01:00:15.503937 MR8 0x5151
2168 01:00:15.506890 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 01:00:15.507307
2170 01:00:15.507636 MR0 0x3b3b
2171 01:00:15.510163 MR8 0x5151
2172 01:00:15.513445 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 01:00:15.513895
2174 01:00:15.520302 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 01:00:15.527035 [FAST_K] Save calibration result to emmc
2176 01:00:15.529963 [FAST_K] Save calibration result to emmc
2177 01:00:15.530479 dram_init: config_dvfs: 1
2178 01:00:15.536984 dramc_set_vcore_voltage set vcore to 662500
2179 01:00:15.537540 Read voltage for 1200, 2
2180 01:00:15.540144 Vio18 = 0
2181 01:00:15.540661 Vcore = 662500
2182 01:00:15.540994 Vdram = 0
2183 01:00:15.541390 Vddq = 0
2184 01:00:15.543590 Vmddr = 0
2185 01:00:15.546625 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 01:00:15.553810 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 01:00:15.556537 MEM_TYPE=3, freq_sel=15
2188 01:00:15.557053 sv_algorithm_assistance_LP4_1600
2189 01:00:15.563438 ============ PULL DRAM RESETB DOWN ============
2190 01:00:15.566915 ========== PULL DRAM RESETB DOWN end =========
2191 01:00:15.570214 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 01:00:15.573304 ===================================
2193 01:00:15.576676 LPDDR4 DRAM CONFIGURATION
2194 01:00:15.580368 ===================================
2195 01:00:15.583323 EX_ROW_EN[0] = 0x0
2196 01:00:15.583835 EX_ROW_EN[1] = 0x0
2197 01:00:15.586451 LP4Y_EN = 0x0
2198 01:00:15.586866 WORK_FSP = 0x0
2199 01:00:15.589423 WL = 0x4
2200 01:00:15.589885 RL = 0x4
2201 01:00:15.593378 BL = 0x2
2202 01:00:15.593960 RPST = 0x0
2203 01:00:15.596067 RD_PRE = 0x0
2204 01:00:15.596483 WR_PRE = 0x1
2205 01:00:15.599397 WR_PST = 0x0
2206 01:00:15.599845 DBI_WR = 0x0
2207 01:00:15.603357 DBI_RD = 0x0
2208 01:00:15.603876 OTF = 0x1
2209 01:00:15.606057 ===================================
2210 01:00:15.609648 ===================================
2211 01:00:15.612786 ANA top config
2212 01:00:15.616385 ===================================
2213 01:00:15.619902 DLL_ASYNC_EN = 0
2214 01:00:15.620424 ALL_SLAVE_EN = 0
2215 01:00:15.622819 NEW_RANK_MODE = 1
2216 01:00:15.626353 DLL_IDLE_MODE = 1
2217 01:00:15.629730 LP45_APHY_COMB_EN = 1
2218 01:00:15.632997 TX_ODT_DIS = 1
2219 01:00:15.633556 NEW_8X_MODE = 1
2220 01:00:15.636032 ===================================
2221 01:00:15.639652 ===================================
2222 01:00:15.642719 data_rate = 2400
2223 01:00:15.646092 CKR = 1
2224 01:00:15.649948 DQ_P2S_RATIO = 8
2225 01:00:15.652628 ===================================
2226 01:00:15.656332 CA_P2S_RATIO = 8
2227 01:00:15.659384 DQ_CA_OPEN = 0
2228 01:00:15.659813 DQ_SEMI_OPEN = 0
2229 01:00:15.662680 CA_SEMI_OPEN = 0
2230 01:00:15.665928 CA_FULL_RATE = 0
2231 01:00:15.669525 DQ_CKDIV4_EN = 0
2232 01:00:15.673134 CA_CKDIV4_EN = 0
2233 01:00:15.673698 CA_PREDIV_EN = 0
2234 01:00:15.676069 PH8_DLY = 17
2235 01:00:15.679238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 01:00:15.682920 DQ_AAMCK_DIV = 4
2237 01:00:15.685941 CA_AAMCK_DIV = 4
2238 01:00:15.689622 CA_ADMCK_DIV = 4
2239 01:00:15.692920 DQ_TRACK_CA_EN = 0
2240 01:00:15.693449 CA_PICK = 1200
2241 01:00:15.696030 CA_MCKIO = 1200
2242 01:00:15.699200 MCKIO_SEMI = 0
2243 01:00:15.702855 PLL_FREQ = 2366
2244 01:00:15.706079 DQ_UI_PI_RATIO = 32
2245 01:00:15.709650 CA_UI_PI_RATIO = 0
2246 01:00:15.712692 ===================================
2247 01:00:15.716010 ===================================
2248 01:00:15.716438 memory_type:LPDDR4
2249 01:00:15.719089 GP_NUM : 10
2250 01:00:15.722705 SRAM_EN : 1
2251 01:00:15.723129 MD32_EN : 0
2252 01:00:15.726161 ===================================
2253 01:00:15.729131 [ANA_INIT] >>>>>>>>>>>>>>
2254 01:00:15.732661 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 01:00:15.736328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 01:00:15.739318 ===================================
2257 01:00:15.742703 data_rate = 2400,PCW = 0X5b00
2258 01:00:15.745817 ===================================
2259 01:00:15.749554 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 01:00:15.752639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 01:00:15.759574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 01:00:15.763270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 01:00:15.766264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 01:00:15.769755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 01:00:15.773173 [ANA_INIT] flow start
2266 01:00:15.776089 [ANA_INIT] PLL >>>>>>>>
2267 01:00:15.776518 [ANA_INIT] PLL <<<<<<<<
2268 01:00:15.779746 [ANA_INIT] MIDPI >>>>>>>>
2269 01:00:15.783296 [ANA_INIT] MIDPI <<<<<<<<
2270 01:00:15.783825 [ANA_INIT] DLL >>>>>>>>
2271 01:00:15.786262 [ANA_INIT] DLL <<<<<<<<
2272 01:00:15.789538 [ANA_INIT] flow end
2273 01:00:15.793098 ============ LP4 DIFF to SE enter ============
2274 01:00:15.796231 ============ LP4 DIFF to SE exit ============
2275 01:00:15.799735 [ANA_INIT] <<<<<<<<<<<<<
2276 01:00:15.803141 [Flow] Enable top DCM control >>>>>
2277 01:00:15.806221 [Flow] Enable top DCM control <<<<<
2278 01:00:15.809571 Enable DLL master slave shuffle
2279 01:00:15.813203 ==============================================================
2280 01:00:15.816325 Gating Mode config
2281 01:00:15.823306 ==============================================================
2282 01:00:15.823836 Config description:
2283 01:00:15.833337 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 01:00:15.839682 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 01:00:15.843247 SELPH_MODE 0: By rank 1: By Phase
2286 01:00:15.849247 ==============================================================
2287 01:00:15.852675 GAT_TRACK_EN = 1
2288 01:00:15.855935 RX_GATING_MODE = 2
2289 01:00:15.859256 RX_GATING_TRACK_MODE = 2
2290 01:00:15.862330 SELPH_MODE = 1
2291 01:00:15.866068 PICG_EARLY_EN = 1
2292 01:00:15.869240 VALID_LAT_VALUE = 1
2293 01:00:15.872427 ==============================================================
2294 01:00:15.875881 Enter into Gating configuration >>>>
2295 01:00:15.879084 Exit from Gating configuration <<<<
2296 01:00:15.882433 Enter into DVFS_PRE_config >>>>>
2297 01:00:15.892861 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 01:00:15.896104 Exit from DVFS_PRE_config <<<<<
2299 01:00:15.899343 Enter into PICG configuration >>>>
2300 01:00:15.902659 Exit from PICG configuration <<<<
2301 01:00:15.906042 [RX_INPUT] configuration >>>>>
2302 01:00:15.909237 [RX_INPUT] configuration <<<<<
2303 01:00:15.915875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 01:00:15.919115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 01:00:15.925703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 01:00:15.932768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 01:00:15.939128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 01:00:15.945778 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 01:00:15.948730 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 01:00:15.952312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 01:00:15.955485 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 01:00:15.961980 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 01:00:15.965375 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 01:00:15.969137 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 01:00:15.972187 ===================================
2316 01:00:15.975714 LPDDR4 DRAM CONFIGURATION
2317 01:00:15.978706 ===================================
2318 01:00:15.979270 EX_ROW_EN[0] = 0x0
2319 01:00:15.982108 EX_ROW_EN[1] = 0x0
2320 01:00:15.985592 LP4Y_EN = 0x0
2321 01:00:15.986256 WORK_FSP = 0x0
2322 01:00:15.988789 WL = 0x4
2323 01:00:15.989223 RL = 0x4
2324 01:00:15.991927 BL = 0x2
2325 01:00:15.992447 RPST = 0x0
2326 01:00:15.995482 RD_PRE = 0x0
2327 01:00:15.995904 WR_PRE = 0x1
2328 01:00:15.998740 WR_PST = 0x0
2329 01:00:15.999161 DBI_WR = 0x0
2330 01:00:16.001788 DBI_RD = 0x0
2331 01:00:16.002272 OTF = 0x1
2332 01:00:16.005301 ===================================
2333 01:00:16.008813 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 01:00:16.015435 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 01:00:16.018749 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 01:00:16.022102 ===================================
2337 01:00:16.025266 LPDDR4 DRAM CONFIGURATION
2338 01:00:16.028610 ===================================
2339 01:00:16.029055 EX_ROW_EN[0] = 0x10
2340 01:00:16.031947 EX_ROW_EN[1] = 0x0
2341 01:00:16.032398 LP4Y_EN = 0x0
2342 01:00:16.035525 WORK_FSP = 0x0
2343 01:00:16.035965 WL = 0x4
2344 01:00:16.038478 RL = 0x4
2345 01:00:16.041992 BL = 0x2
2346 01:00:16.042486 RPST = 0x0
2347 01:00:16.045131 RD_PRE = 0x0
2348 01:00:16.045731 WR_PRE = 0x1
2349 01:00:16.048382 WR_PST = 0x0
2350 01:00:16.048867 DBI_WR = 0x0
2351 01:00:16.052006 DBI_RD = 0x0
2352 01:00:16.052450 OTF = 0x1
2353 01:00:16.055242 ===================================
2354 01:00:16.061865 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 01:00:16.062345 ==
2356 01:00:16.065331 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 01:00:16.068453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 01:00:16.068907 ==
2359 01:00:16.072005 [Duty_Offset_Calibration]
2360 01:00:16.072421 B0:2 B1:0 CA:3
2361 01:00:16.075297
2362 01:00:16.078509 [DutyScan_Calibration_Flow] k_type=0
2363 01:00:16.086086
2364 01:00:16.086523 ==CLK 0==
2365 01:00:16.089398 Final CLK duty delay cell = 0
2366 01:00:16.092918 [0] MAX Duty = 5031%(X100), DQS PI = 20
2367 01:00:16.096058 [0] MIN Duty = 4875%(X100), DQS PI = 58
2368 01:00:16.096237 [0] AVG Duty = 4953%(X100)
2369 01:00:16.099526
2370 01:00:16.102933 CH0 CLK Duty spec in!! Max-Min= 156%
2371 01:00:16.106075 [DutyScan_Calibration_Flow] ====Done====
2372 01:00:16.106255
2373 01:00:16.109240 [DutyScan_Calibration_Flow] k_type=1
2374 01:00:16.124803
2375 01:00:16.124982 ==DQS 0 ==
2376 01:00:16.128088 Final DQS duty delay cell = 0
2377 01:00:16.131572 [0] MAX Duty = 5062%(X100), DQS PI = 28
2378 01:00:16.134763 [0] MIN Duty = 4907%(X100), DQS PI = 2
2379 01:00:16.135019 [0] AVG Duty = 4984%(X100)
2380 01:00:16.137840
2381 01:00:16.137921 ==DQS 1 ==
2382 01:00:16.141202 Final DQS duty delay cell = -4
2383 01:00:16.144430 [-4] MAX Duty = 4969%(X100), DQS PI = 6
2384 01:00:16.148090 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2385 01:00:16.151009 [-4] AVG Duty = 4922%(X100)
2386 01:00:16.151091
2387 01:00:16.154334 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2388 01:00:16.154415
2389 01:00:16.157754 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2390 01:00:16.161083 [DutyScan_Calibration_Flow] ====Done====
2391 01:00:16.161164
2392 01:00:16.164306 [DutyScan_Calibration_Flow] k_type=3
2393 01:00:16.181761
2394 01:00:16.181842 ==DQM 0 ==
2395 01:00:16.185165 Final DQM duty delay cell = 0
2396 01:00:16.188533 [0] MAX Duty = 5124%(X100), DQS PI = 28
2397 01:00:16.191947 [0] MIN Duty = 4876%(X100), DQS PI = 0
2398 01:00:16.192030 [0] AVG Duty = 5000%(X100)
2399 01:00:16.195192
2400 01:00:16.195264 ==DQM 1 ==
2401 01:00:16.198548 Final DQM duty delay cell = 4
2402 01:00:16.201884 [4] MAX Duty = 5124%(X100), DQS PI = 50
2403 01:00:16.205193 [4] MIN Duty = 5000%(X100), DQS PI = 32
2404 01:00:16.205293 [4] AVG Duty = 5062%(X100)
2405 01:00:16.208954
2406 01:00:16.211908 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2407 01:00:16.211987
2408 01:00:16.215516 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2409 01:00:16.218894 [DutyScan_Calibration_Flow] ====Done====
2410 01:00:16.218969
2411 01:00:16.222161 [DutyScan_Calibration_Flow] k_type=2
2412 01:00:16.236740
2413 01:00:16.236830 ==DQ 0 ==
2414 01:00:16.240486 Final DQ duty delay cell = -4
2415 01:00:16.243680 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2416 01:00:16.247004 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2417 01:00:16.250365 [-4] AVG Duty = 4969%(X100)
2418 01:00:16.250509
2419 01:00:16.250639 ==DQ 1 ==
2420 01:00:16.253706 Final DQ duty delay cell = -4
2421 01:00:16.257038 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2422 01:00:16.260266 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2423 01:00:16.263737 [-4] AVG Duty = 4938%(X100)
2424 01:00:16.263887
2425 01:00:16.267009 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2426 01:00:16.267158
2427 01:00:16.270231 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2428 01:00:16.273997 [DutyScan_Calibration_Flow] ====Done====
2429 01:00:16.274283 ==
2430 01:00:16.277173 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 01:00:16.280560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 01:00:16.280844 ==
2433 01:00:16.283871 [Duty_Offset_Calibration]
2434 01:00:16.284333 B0:1 B1:-2 CA:0
2435 01:00:16.284734
2436 01:00:16.287354 [DutyScan_Calibration_Flow] k_type=0
2437 01:00:16.297841
2438 01:00:16.298349 ==CLK 0==
2439 01:00:16.300999 Final CLK duty delay cell = 0
2440 01:00:16.304446 [0] MAX Duty = 5031%(X100), DQS PI = 16
2441 01:00:16.307551 [0] MIN Duty = 4844%(X100), DQS PI = 58
2442 01:00:16.307986 [0] AVG Duty = 4937%(X100)
2443 01:00:16.311208
2444 01:00:16.314559 CH1 CLK Duty spec in!! Max-Min= 187%
2445 01:00:16.317796 [DutyScan_Calibration_Flow] ====Done====
2446 01:00:16.318226
2447 01:00:16.320774 [DutyScan_Calibration_Flow] k_type=1
2448 01:00:16.336167
2449 01:00:16.336595 ==DQS 0 ==
2450 01:00:16.339472 Final DQS duty delay cell = -4
2451 01:00:16.343053 [-4] MAX Duty = 5000%(X100), DQS PI = 22
2452 01:00:16.345988 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2453 01:00:16.349379 [-4] AVG Duty = 4953%(X100)
2454 01:00:16.349869
2455 01:00:16.350206 ==DQS 1 ==
2456 01:00:16.353024 Final DQS duty delay cell = 0
2457 01:00:16.356368 [0] MAX Duty = 5093%(X100), DQS PI = 0
2458 01:00:16.359618 [0] MIN Duty = 4875%(X100), DQS PI = 26
2459 01:00:16.362723 [0] AVG Duty = 4984%(X100)
2460 01:00:16.363154
2461 01:00:16.366110 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2462 01:00:16.366525
2463 01:00:16.369623 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2464 01:00:16.372739 [DutyScan_Calibration_Flow] ====Done====
2465 01:00:16.373170
2466 01:00:16.376050 [DutyScan_Calibration_Flow] k_type=3
2467 01:00:16.392742
2468 01:00:16.393173 ==DQM 0 ==
2469 01:00:16.396363 Final DQM duty delay cell = 0
2470 01:00:16.399543 [0] MAX Duty = 5000%(X100), DQS PI = 22
2471 01:00:16.402879 [0] MIN Duty = 4876%(X100), DQS PI = 2
2472 01:00:16.403321 [0] AVG Duty = 4938%(X100)
2473 01:00:16.406134
2474 01:00:16.406556 ==DQM 1 ==
2475 01:00:16.409342 Final DQM duty delay cell = 0
2476 01:00:16.412776 [0] MAX Duty = 5031%(X100), DQS PI = 36
2477 01:00:16.416031 [0] MIN Duty = 4907%(X100), DQS PI = 4
2478 01:00:16.416463 [0] AVG Duty = 4969%(X100)
2479 01:00:16.419549
2480 01:00:16.422709 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2481 01:00:16.423144
2482 01:00:16.425907 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 01:00:16.429584 [DutyScan_Calibration_Flow] ====Done====
2484 01:00:16.430074
2485 01:00:16.432843 [DutyScan_Calibration_Flow] k_type=2
2486 01:00:16.449352
2487 01:00:16.450035 ==DQ 0 ==
2488 01:00:16.452351 Final DQ duty delay cell = 0
2489 01:00:16.455761 [0] MAX Duty = 5062%(X100), DQS PI = 18
2490 01:00:16.459228 [0] MIN Duty = 4938%(X100), DQS PI = 54
2491 01:00:16.459703 [0] AVG Duty = 5000%(X100)
2492 01:00:16.462495
2493 01:00:16.463057 ==DQ 1 ==
2494 01:00:16.465819 Final DQ duty delay cell = 0
2495 01:00:16.469035 [0] MAX Duty = 5093%(X100), DQS PI = 20
2496 01:00:16.472217 [0] MIN Duty = 4969%(X100), DQS PI = 26
2497 01:00:16.472656 [0] AVG Duty = 5031%(X100)
2498 01:00:16.475688
2499 01:00:16.479054 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2500 01:00:16.479502
2501 01:00:16.482267 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2502 01:00:16.485604 [DutyScan_Calibration_Flow] ====Done====
2503 01:00:16.488826 nWR fixed to 30
2504 01:00:16.489264 [ModeRegInit_LP4] CH0 RK0
2505 01:00:16.492392 [ModeRegInit_LP4] CH0 RK1
2506 01:00:16.495624 [ModeRegInit_LP4] CH1 RK0
2507 01:00:16.499056 [ModeRegInit_LP4] CH1 RK1
2508 01:00:16.499622 match AC timing 7
2509 01:00:16.502288 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 01:00:16.505947 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 01:00:16.512486 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 01:00:16.515638 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 01:00:16.522282 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 01:00:16.522741 ==
2515 01:00:16.525806 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 01:00:16.529221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 01:00:16.529787 ==
2518 01:00:16.535792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 01:00:16.539304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 01:00:16.549193 [CA 0] Center 40 (10~71) winsize 62
2521 01:00:16.552871 [CA 1] Center 39 (9~70) winsize 62
2522 01:00:16.555730 [CA 2] Center 36 (6~66) winsize 61
2523 01:00:16.559272 [CA 3] Center 35 (5~66) winsize 62
2524 01:00:16.562622 [CA 4] Center 34 (4~65) winsize 62
2525 01:00:16.566054 [CA 5] Center 33 (3~63) winsize 61
2526 01:00:16.566566
2527 01:00:16.569152 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2528 01:00:16.569753
2529 01:00:16.572772 [CATrainingPosCal] consider 1 rank data
2530 01:00:16.575884 u2DelayCellTimex100 = 270/100 ps
2531 01:00:16.578949 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2532 01:00:16.585920 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 01:00:16.589199 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2534 01:00:16.592533 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 01:00:16.595769 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 01:00:16.598935 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 01:00:16.599368
2538 01:00:16.602268 CA PerBit enable=1, Macro0, CA PI delay=33
2539 01:00:16.602695
2540 01:00:16.605543 [CBTSetCACLKResult] CA Dly = 33
2541 01:00:16.605975 CS Dly: 7 (0~38)
2542 01:00:16.609126 ==
2543 01:00:16.612474 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 01:00:16.615759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 01:00:16.616209 ==
2546 01:00:16.618962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 01:00:16.625571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2548 01:00:16.635234 [CA 0] Center 40 (10~70) winsize 61
2549 01:00:16.638568 [CA 1] Center 40 (10~70) winsize 61
2550 01:00:16.641914 [CA 2] Center 35 (5~66) winsize 62
2551 01:00:16.645106 [CA 3] Center 35 (5~66) winsize 62
2552 01:00:16.648719 [CA 4] Center 34 (4~65) winsize 62
2553 01:00:16.651701 [CA 5] Center 33 (3~64) winsize 62
2554 01:00:16.652304
2555 01:00:16.655174 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 01:00:16.655655
2557 01:00:16.658446 [CATrainingPosCal] consider 2 rank data
2558 01:00:16.661876 u2DelayCellTimex100 = 270/100 ps
2559 01:00:16.664871 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2560 01:00:16.671894 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2561 01:00:16.675044 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2562 01:00:16.678305 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 01:00:16.681770 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2564 01:00:16.684991 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2565 01:00:16.685424
2566 01:00:16.688218 CA PerBit enable=1, Macro0, CA PI delay=33
2567 01:00:16.688643
2568 01:00:16.691700 [CBTSetCACLKResult] CA Dly = 33
2569 01:00:16.694974 CS Dly: 8 (0~40)
2570 01:00:16.695399
2571 01:00:16.698304 ----->DramcWriteLeveling(PI) begin...
2572 01:00:16.698734 ==
2573 01:00:16.701778 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 01:00:16.704972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 01:00:16.705403 ==
2576 01:00:16.708216 Write leveling (Byte 0): 33 => 33
2577 01:00:16.711709 Write leveling (Byte 1): 31 => 31
2578 01:00:16.715012 DramcWriteLeveling(PI) end<-----
2579 01:00:16.715440
2580 01:00:16.715777 ==
2581 01:00:16.718599 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 01:00:16.721770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 01:00:16.722200 ==
2584 01:00:16.725084 [Gating] SW mode calibration
2585 01:00:16.732082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 01:00:16.738482 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 01:00:16.741804 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 01:00:16.745086 0 15 4 | B1->B0 | 2525 3434 | 1 0 | (0 0) (0 0)
2589 01:00:16.751801 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 01:00:16.755078 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 01:00:16.758340 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 01:00:16.765067 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 01:00:16.768286 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 01:00:16.771659 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2595 01:00:16.775101 1 0 0 | B1->B0 | 3232 2a2a | 0 1 | (0 0) (1 0)
2596 01:00:16.781871 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2597 01:00:16.785183 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 01:00:16.788323 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 01:00:16.794972 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 01:00:16.798390 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 01:00:16.801845 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 01:00:16.808532 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 01:00:16.811730 1 1 0 | B1->B0 | 2a2a 3636 | 0 1 | (0 0) (0 0)
2604 01:00:16.815297 1 1 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2605 01:00:16.822040 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 01:00:16.825019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 01:00:16.828609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 01:00:16.834948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 01:00:16.838462 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 01:00:16.841881 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 01:00:16.848472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 01:00:16.851708 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2613 01:00:16.855355 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 01:00:16.861804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 01:00:16.865158 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 01:00:16.868497 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 01:00:16.871916 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 01:00:16.878347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 01:00:16.881547 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 01:00:16.885109 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 01:00:16.891584 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 01:00:16.894943 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 01:00:16.898267 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 01:00:16.905149 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 01:00:16.908409 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 01:00:16.911667 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 01:00:16.918361 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2628 01:00:16.921739 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 01:00:16.924906 Total UI for P1: 0, mck2ui 16
2630 01:00:16.928218 best dqsien dly found for B0: ( 1, 3, 30)
2631 01:00:16.931613 Total UI for P1: 0, mck2ui 16
2632 01:00:16.934836 best dqsien dly found for B1: ( 1, 4, 0)
2633 01:00:16.938384 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2634 01:00:16.941649 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 01:00:16.942078
2636 01:00:16.945182 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2637 01:00:16.948429 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 01:00:16.951546 [Gating] SW calibration Done
2639 01:00:16.951975 ==
2640 01:00:16.955104 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 01:00:16.958395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 01:00:16.958826 ==
2643 01:00:16.961444 RX Vref Scan: 0
2644 01:00:16.961914
2645 01:00:16.964811 RX Vref 0 -> 0, step: 1
2646 01:00:16.965236
2647 01:00:16.965618 RX Delay -40 -> 252, step: 8
2648 01:00:16.971629 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2649 01:00:16.975021 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2650 01:00:16.978551 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2651 01:00:16.981893 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2652 01:00:16.985089 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2653 01:00:16.991723 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2654 01:00:16.995053 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2655 01:00:16.998580 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2656 01:00:17.001716 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2657 01:00:17.005058 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2658 01:00:17.008294 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2659 01:00:17.015051 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2660 01:00:17.018549 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2661 01:00:17.021637 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2662 01:00:17.024948 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2663 01:00:17.028419 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2664 01:00:17.031552 ==
2665 01:00:17.035195 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 01:00:17.038196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 01:00:17.038624 ==
2668 01:00:17.038963 DQS Delay:
2669 01:00:17.041791 DQS0 = 0, DQS1 = 0
2670 01:00:17.042217 DQM Delay:
2671 01:00:17.045135 DQM0 = 113, DQM1 = 102
2672 01:00:17.045591 DQ Delay:
2673 01:00:17.048329 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2674 01:00:17.051683 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2675 01:00:17.055078 DQ8 =95, DQ9 =83, DQ10 =103, DQ11 =95
2676 01:00:17.058359 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2677 01:00:17.058783
2678 01:00:17.059120
2679 01:00:17.059431 ==
2680 01:00:17.061962 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 01:00:17.068348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 01:00:17.068778 ==
2683 01:00:17.069119
2684 01:00:17.069431
2685 01:00:17.069785 TX Vref Scan disable
2686 01:00:17.071500 == TX Byte 0 ==
2687 01:00:17.074805 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2688 01:00:17.078621 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2689 01:00:17.081861 == TX Byte 1 ==
2690 01:00:17.084971 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2691 01:00:17.088468 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2692 01:00:17.091547 ==
2693 01:00:17.095086 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 01:00:17.098115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 01:00:17.098544 ==
2696 01:00:17.109666 TX Vref=22, minBit 1, minWin=25, winSum=414
2697 01:00:17.113137 TX Vref=24, minBit 1, minWin=25, winSum=420
2698 01:00:17.116371 TX Vref=26, minBit 7, minWin=25, winSum=428
2699 01:00:17.119655 TX Vref=28, minBit 4, minWin=26, winSum=430
2700 01:00:17.122936 TX Vref=30, minBit 10, minWin=26, winSum=433
2701 01:00:17.126373 TX Vref=32, minBit 2, minWin=26, winSum=427
2702 01:00:17.133018 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
2703 01:00:17.133452
2704 01:00:17.136394 Final TX Range 1 Vref 30
2705 01:00:17.136821
2706 01:00:17.137158 ==
2707 01:00:17.139770 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 01:00:17.143199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 01:00:17.143741 ==
2710 01:00:17.144155
2711 01:00:17.146339
2712 01:00:17.146764 TX Vref Scan disable
2713 01:00:17.149598 == TX Byte 0 ==
2714 01:00:17.153151 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2715 01:00:17.156279 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2716 01:00:17.159546 == TX Byte 1 ==
2717 01:00:17.162736 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2718 01:00:17.166243 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2719 01:00:17.169329
2720 01:00:17.169791 [DATLAT]
2721 01:00:17.170129 Freq=1200, CH0 RK0
2722 01:00:17.170449
2723 01:00:17.172684 DATLAT Default: 0xd
2724 01:00:17.173110 0, 0xFFFF, sum = 0
2725 01:00:17.176177 1, 0xFFFF, sum = 0
2726 01:00:17.176611 2, 0xFFFF, sum = 0
2727 01:00:17.179432 3, 0xFFFF, sum = 0
2728 01:00:17.179864 4, 0xFFFF, sum = 0
2729 01:00:17.182746 5, 0xFFFF, sum = 0
2730 01:00:17.186319 6, 0xFFFF, sum = 0
2731 01:00:17.186858 7, 0xFFFF, sum = 0
2732 01:00:17.189439 8, 0xFFFF, sum = 0
2733 01:00:17.189910 9, 0xFFFF, sum = 0
2734 01:00:17.192941 10, 0xFFFF, sum = 0
2735 01:00:17.193460 11, 0xFFFF, sum = 0
2736 01:00:17.196077 12, 0x0, sum = 1
2737 01:00:17.196507 13, 0x0, sum = 2
2738 01:00:17.199346 14, 0x0, sum = 3
2739 01:00:17.199778 15, 0x0, sum = 4
2740 01:00:17.200124 best_step = 13
2741 01:00:17.200438
2742 01:00:17.202600 ==
2743 01:00:17.205910 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 01:00:17.209351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 01:00:17.209826 ==
2746 01:00:17.210171 RX Vref Scan: 1
2747 01:00:17.210490
2748 01:00:17.212945 Set Vref Range= 32 -> 127
2749 01:00:17.213367
2750 01:00:17.216349 RX Vref 32 -> 127, step: 1
2751 01:00:17.216773
2752 01:00:17.219388 RX Delay -37 -> 252, step: 4
2753 01:00:17.219818
2754 01:00:17.222917 Set Vref, RX VrefLevel [Byte0]: 32
2755 01:00:17.226158 [Byte1]: 32
2756 01:00:17.226584
2757 01:00:17.229440 Set Vref, RX VrefLevel [Byte0]: 33
2758 01:00:17.232545 [Byte1]: 33
2759 01:00:17.235946
2760 01:00:17.236415 Set Vref, RX VrefLevel [Byte0]: 34
2761 01:00:17.239503 [Byte1]: 34
2762 01:00:17.244069
2763 01:00:17.244490 Set Vref, RX VrefLevel [Byte0]: 35
2764 01:00:17.247436 [Byte1]: 35
2765 01:00:17.251996
2766 01:00:17.252424 Set Vref, RX VrefLevel [Byte0]: 36
2767 01:00:17.255159 [Byte1]: 36
2768 01:00:17.260070
2769 01:00:17.260495 Set Vref, RX VrefLevel [Byte0]: 37
2770 01:00:17.263226 [Byte1]: 37
2771 01:00:17.268203
2772 01:00:17.268630 Set Vref, RX VrefLevel [Byte0]: 38
2773 01:00:17.271380 [Byte1]: 38
2774 01:00:17.276164
2775 01:00:17.276592 Set Vref, RX VrefLevel [Byte0]: 39
2776 01:00:17.279284 [Byte1]: 39
2777 01:00:17.284043
2778 01:00:17.284469 Set Vref, RX VrefLevel [Byte0]: 40
2779 01:00:17.287432 [Byte1]: 40
2780 01:00:17.292152
2781 01:00:17.292595 Set Vref, RX VrefLevel [Byte0]: 41
2782 01:00:17.295478 [Byte1]: 41
2783 01:00:17.299956
2784 01:00:17.300384 Set Vref, RX VrefLevel [Byte0]: 42
2785 01:00:17.303498 [Byte1]: 42
2786 01:00:17.307930
2787 01:00:17.308357 Set Vref, RX VrefLevel [Byte0]: 43
2788 01:00:17.311240 [Byte1]: 43
2789 01:00:17.316088
2790 01:00:17.316515 Set Vref, RX VrefLevel [Byte0]: 44
2791 01:00:17.319390 [Byte1]: 44
2792 01:00:17.324034
2793 01:00:17.324456 Set Vref, RX VrefLevel [Byte0]: 45
2794 01:00:17.327385 [Byte1]: 45
2795 01:00:17.332137
2796 01:00:17.332563 Set Vref, RX VrefLevel [Byte0]: 46
2797 01:00:17.335389 [Byte1]: 46
2798 01:00:17.340270
2799 01:00:17.340697 Set Vref, RX VrefLevel [Byte0]: 47
2800 01:00:17.343669 [Byte1]: 47
2801 01:00:17.348585
2802 01:00:17.349027 Set Vref, RX VrefLevel [Byte0]: 48
2803 01:00:17.351629 [Byte1]: 48
2804 01:00:17.356007
2805 01:00:17.356432 Set Vref, RX VrefLevel [Byte0]: 49
2806 01:00:17.359212 [Byte1]: 49
2807 01:00:17.364028
2808 01:00:17.364454 Set Vref, RX VrefLevel [Byte0]: 50
2809 01:00:17.367301 [Byte1]: 50
2810 01:00:17.372272
2811 01:00:17.372694 Set Vref, RX VrefLevel [Byte0]: 51
2812 01:00:17.375639 [Byte1]: 51
2813 01:00:17.380342
2814 01:00:17.380768 Set Vref, RX VrefLevel [Byte0]: 52
2815 01:00:17.383428 [Byte1]: 52
2816 01:00:17.388219
2817 01:00:17.388642 Set Vref, RX VrefLevel [Byte0]: 53
2818 01:00:17.391368 [Byte1]: 53
2819 01:00:17.396165
2820 01:00:17.396594 Set Vref, RX VrefLevel [Byte0]: 54
2821 01:00:17.399514 [Byte1]: 54
2822 01:00:17.403990
2823 01:00:17.404431 Set Vref, RX VrefLevel [Byte0]: 55
2824 01:00:17.407303 [Byte1]: 55
2825 01:00:17.412234
2826 01:00:17.412659 Set Vref, RX VrefLevel [Byte0]: 56
2827 01:00:17.415363 [Byte1]: 56
2828 01:00:17.420110
2829 01:00:17.420539 Set Vref, RX VrefLevel [Byte0]: 57
2830 01:00:17.423686 [Byte1]: 57
2831 01:00:17.428129
2832 01:00:17.428551 Set Vref, RX VrefLevel [Byte0]: 58
2833 01:00:17.431365 [Byte1]: 58
2834 01:00:17.436069
2835 01:00:17.436491 Set Vref, RX VrefLevel [Byte0]: 59
2836 01:00:17.439671 [Byte1]: 59
2837 01:00:17.444049
2838 01:00:17.444473 Set Vref, RX VrefLevel [Byte0]: 60
2839 01:00:17.447511 [Byte1]: 60
2840 01:00:17.452183
2841 01:00:17.452607 Set Vref, RX VrefLevel [Byte0]: 61
2842 01:00:17.455468 [Byte1]: 61
2843 01:00:17.460106
2844 01:00:17.460533 Set Vref, RX VrefLevel [Byte0]: 62
2845 01:00:17.463401 [Byte1]: 62
2846 01:00:17.467987
2847 01:00:17.468445 Set Vref, RX VrefLevel [Byte0]: 63
2848 01:00:17.471424 [Byte1]: 63
2849 01:00:17.476241
2850 01:00:17.476664 Set Vref, RX VrefLevel [Byte0]: 64
2851 01:00:17.479405 [Byte1]: 64
2852 01:00:17.484169
2853 01:00:17.484591 Set Vref, RX VrefLevel [Byte0]: 65
2854 01:00:17.487519 [Byte1]: 65
2855 01:00:17.492013
2856 01:00:17.492434 Set Vref, RX VrefLevel [Byte0]: 66
2857 01:00:17.495515 [Byte1]: 66
2858 01:00:17.500210
2859 01:00:17.500635 Set Vref, RX VrefLevel [Byte0]: 67
2860 01:00:17.503374 [Byte1]: 67
2861 01:00:17.508014
2862 01:00:17.508438 Set Vref, RX VrefLevel [Byte0]: 68
2863 01:00:17.511245 [Byte1]: 68
2864 01:00:17.515976
2865 01:00:17.516398 Set Vref, RX VrefLevel [Byte0]: 69
2866 01:00:17.519389 [Byte1]: 69
2867 01:00:17.523894
2868 01:00:17.524317 Set Vref, RX VrefLevel [Byte0]: 70
2869 01:00:17.527514 [Byte1]: 70
2870 01:00:17.532257
2871 01:00:17.532680 Set Vref, RX VrefLevel [Byte0]: 71
2872 01:00:17.538494 [Byte1]: 71
2873 01:00:17.538917
2874 01:00:17.541729 Set Vref, RX VrefLevel [Byte0]: 72
2875 01:00:17.544987 [Byte1]: 72
2876 01:00:17.545413
2877 01:00:17.548662 Set Vref, RX VrefLevel [Byte0]: 73
2878 01:00:17.551726 [Byte1]: 73
2879 01:00:17.556120
2880 01:00:17.556542 Set Vref, RX VrefLevel [Byte0]: 74
2881 01:00:17.559258 [Byte1]: 74
2882 01:00:17.564200
2883 01:00:17.564626 Final RX Vref Byte 0 = 59 to rank0
2884 01:00:17.567479 Final RX Vref Byte 1 = 56 to rank0
2885 01:00:17.570666 Final RX Vref Byte 0 = 59 to rank1
2886 01:00:17.574227 Final RX Vref Byte 1 = 56 to rank1==
2887 01:00:17.577600 Dram Type= 6, Freq= 0, CH_0, rank 0
2888 01:00:17.584000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 01:00:17.584480 ==
2890 01:00:17.584819 DQS Delay:
2891 01:00:17.585133 DQS0 = 0, DQS1 = 0
2892 01:00:17.587663 DQM Delay:
2893 01:00:17.588092 DQM0 = 112, DQM1 = 102
2894 01:00:17.590613 DQ Delay:
2895 01:00:17.593910 DQ0 =112, DQ1 =114, DQ2 =110, DQ3 =108
2896 01:00:17.597532 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2897 01:00:17.600853 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2898 01:00:17.604541 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2899 01:00:17.604970
2900 01:00:17.605303
2901 01:00:17.611117 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2902 01:00:17.614744 CH0 RK0: MR19=303, MR18=FBFA
2903 01:00:17.621305 CH0_RK0: MR19=0x303, MR18=0xFBFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2904 01:00:17.621785
2905 01:00:17.624583 ----->DramcWriteLeveling(PI) begin...
2906 01:00:17.625018 ==
2907 01:00:17.627665 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 01:00:17.631111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 01:00:17.631540 ==
2910 01:00:17.634354 Write leveling (Byte 0): 34 => 34
2911 01:00:17.637555 Write leveling (Byte 1): 30 => 30
2912 01:00:17.640883 DramcWriteLeveling(PI) end<-----
2913 01:00:17.641306
2914 01:00:17.641697 ==
2915 01:00:17.644503 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 01:00:17.647769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 01:00:17.651035 ==
2918 01:00:17.651474 [Gating] SW mode calibration
2919 01:00:17.660990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2920 01:00:17.664172 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2921 01:00:17.667410 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
2922 01:00:17.674250 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 01:00:17.677278 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 01:00:17.680731 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 01:00:17.687513 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 01:00:17.691004 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 01:00:17.694463 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2928 01:00:17.700864 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2929 01:00:17.704009 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 01:00:17.707575 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 01:00:17.714150 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 01:00:17.717467 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 01:00:17.720740 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 01:00:17.727435 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 01:00:17.730947 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2936 01:00:17.734149 1 0 28 | B1->B0 | 2323 4343 | 1 0 | (0 0) (0 0)
2937 01:00:17.740795 1 1 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2938 01:00:17.743986 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 01:00:17.747602 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 01:00:17.750741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 01:00:17.757776 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 01:00:17.760834 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 01:00:17.764138 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2944 01:00:17.770934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2945 01:00:17.774192 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2946 01:00:17.777427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 01:00:17.784477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 01:00:17.787541 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 01:00:17.790959 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 01:00:17.797701 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 01:00:17.800813 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 01:00:17.804065 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 01:00:17.810965 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 01:00:17.814328 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 01:00:17.817462 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 01:00:17.824063 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 01:00:17.827356 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 01:00:17.830950 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 01:00:17.837532 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 01:00:17.840663 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2961 01:00:17.844115 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 01:00:17.847464 Total UI for P1: 0, mck2ui 16
2963 01:00:17.850983 best dqsien dly found for B0: ( 1, 3, 28)
2964 01:00:17.854320 Total UI for P1: 0, mck2ui 16
2965 01:00:17.857285 best dqsien dly found for B1: ( 1, 3, 28)
2966 01:00:17.860865 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2967 01:00:17.864146 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2968 01:00:17.864569
2969 01:00:17.867355 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2970 01:00:17.874182 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2971 01:00:17.874604 [Gating] SW calibration Done
2972 01:00:17.874937 ==
2973 01:00:17.877375 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 01:00:17.884047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 01:00:17.884665 ==
2976 01:00:17.885055 RX Vref Scan: 0
2977 01:00:17.885381
2978 01:00:17.887394 RX Vref 0 -> 0, step: 1
2979 01:00:17.887814
2980 01:00:17.890677 RX Delay -40 -> 252, step: 8
2981 01:00:17.893985 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2982 01:00:17.897262 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2983 01:00:17.900610 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2984 01:00:17.904091 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2985 01:00:17.910836 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2986 01:00:17.914077 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2987 01:00:17.917376 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2988 01:00:17.920660 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2989 01:00:17.924018 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2990 01:00:17.927398 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2991 01:00:17.933929 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2992 01:00:17.937358 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2993 01:00:17.940650 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2994 01:00:17.943957 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2995 01:00:17.950914 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2996 01:00:17.953954 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2997 01:00:17.954378 ==
2998 01:00:17.957362 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 01:00:17.960846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 01:00:17.961275 ==
3001 01:00:17.961656 DQS Delay:
3002 01:00:17.964120 DQS0 = 0, DQS1 = 0
3003 01:00:17.964560 DQM Delay:
3004 01:00:17.967354 DQM0 = 112, DQM1 = 101
3005 01:00:17.967810 DQ Delay:
3006 01:00:17.970820 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3007 01:00:17.974238 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =119
3008 01:00:17.977507 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3009 01:00:17.980785 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3010 01:00:17.981212
3011 01:00:17.984044
3012 01:00:17.984467 ==
3013 01:00:17.987418 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 01:00:17.990849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 01:00:17.991280 ==
3016 01:00:17.991622
3017 01:00:17.991932
3018 01:00:17.994117 TX Vref Scan disable
3019 01:00:17.994545 == TX Byte 0 ==
3020 01:00:18.000746 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3021 01:00:18.003855 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3022 01:00:18.004284 == TX Byte 1 ==
3023 01:00:18.007391 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3024 01:00:18.014264 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3025 01:00:18.014691 ==
3026 01:00:18.017621 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 01:00:18.020762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 01:00:18.021189 ==
3029 01:00:18.033361 TX Vref=22, minBit 2, minWin=25, winSum=422
3030 01:00:18.036567 TX Vref=24, minBit 2, minWin=26, winSum=429
3031 01:00:18.040073 TX Vref=26, minBit 1, minWin=26, winSum=434
3032 01:00:18.043373 TX Vref=28, minBit 1, minWin=27, winSum=439
3033 01:00:18.046724 TX Vref=30, minBit 1, minWin=27, winSum=442
3034 01:00:18.050171 TX Vref=32, minBit 8, minWin=26, winSum=437
3035 01:00:18.056634 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
3036 01:00:18.057064
3037 01:00:18.060088 Final TX Range 1 Vref 30
3038 01:00:18.060514
3039 01:00:18.060846 ==
3040 01:00:18.063547 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 01:00:18.066694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 01:00:18.067119 ==
3043 01:00:18.067455
3044 01:00:18.067769
3045 01:00:18.069895 TX Vref Scan disable
3046 01:00:18.073157 == TX Byte 0 ==
3047 01:00:18.076847 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3048 01:00:18.079997 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3049 01:00:18.083330 == TX Byte 1 ==
3050 01:00:18.086678 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3051 01:00:18.090031 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3052 01:00:18.090473
3053 01:00:18.093281 [DATLAT]
3054 01:00:18.093742 Freq=1200, CH0 RK1
3055 01:00:18.094084
3056 01:00:18.096690 DATLAT Default: 0xd
3057 01:00:18.097215 0, 0xFFFF, sum = 0
3058 01:00:18.099845 1, 0xFFFF, sum = 0
3059 01:00:18.100384 2, 0xFFFF, sum = 0
3060 01:00:18.103488 3, 0xFFFF, sum = 0
3061 01:00:18.104090 4, 0xFFFF, sum = 0
3062 01:00:18.106496 5, 0xFFFF, sum = 0
3063 01:00:18.107007 6, 0xFFFF, sum = 0
3064 01:00:18.109860 7, 0xFFFF, sum = 0
3065 01:00:18.110356 8, 0xFFFF, sum = 0
3066 01:00:18.113376 9, 0xFFFF, sum = 0
3067 01:00:18.116745 10, 0xFFFF, sum = 0
3068 01:00:18.117278 11, 0xFFFF, sum = 0
3069 01:00:18.119709 12, 0x0, sum = 1
3070 01:00:18.120143 13, 0x0, sum = 2
3071 01:00:18.120532 14, 0x0, sum = 3
3072 01:00:18.123091 15, 0x0, sum = 4
3073 01:00:18.123519 best_step = 13
3074 01:00:18.123857
3075 01:00:18.126563 ==
3076 01:00:18.127093 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 01:00:18.133409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 01:00:18.133854 ==
3079 01:00:18.134189 RX Vref Scan: 0
3080 01:00:18.134657
3081 01:00:18.136722 RX Vref 0 -> 0, step: 1
3082 01:00:18.137139
3083 01:00:18.139981 RX Delay -37 -> 252, step: 4
3084 01:00:18.143247 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3085 01:00:18.146439 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3086 01:00:18.153160 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3087 01:00:18.156589 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3088 01:00:18.159983 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3089 01:00:18.163107 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3090 01:00:18.166630 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3091 01:00:18.173002 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3092 01:00:18.176439 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3093 01:00:18.179936 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3094 01:00:18.182985 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3095 01:00:18.186553 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3096 01:00:18.193270 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3097 01:00:18.196530 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3098 01:00:18.199735 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3099 01:00:18.203385 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3100 01:00:18.203864 ==
3101 01:00:18.206751 Dram Type= 6, Freq= 0, CH_0, rank 1
3102 01:00:18.213201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 01:00:18.213671 ==
3104 01:00:18.214014 DQS Delay:
3105 01:00:18.214324 DQS0 = 0, DQS1 = 0
3106 01:00:18.216689 DQM Delay:
3107 01:00:18.217107 DQM0 = 110, DQM1 = 102
3108 01:00:18.219810 DQ Delay:
3109 01:00:18.222895 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3110 01:00:18.226516 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3111 01:00:18.229955 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3112 01:00:18.232983 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3113 01:00:18.233455
3114 01:00:18.233890
3115 01:00:18.239912 [DQSOSCAuto] RK1, (LSB)MR18= 0x16fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3116 01:00:18.243113 CH0 RK1: MR19=403, MR18=16FD
3117 01:00:18.249667 CH0_RK1: MR19=0x403, MR18=0x16FD, DQSOSC=401, MR23=63, INC=40, DEC=27
3118 01:00:18.253100 [RxdqsGatingPostProcess] freq 1200
3119 01:00:18.259618 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3120 01:00:18.263166 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 01:00:18.263592 best DQS1 dly(2T, 0.5T) = (0, 12)
3122 01:00:18.266560 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 01:00:18.269820 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3124 01:00:18.273305 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 01:00:18.276640 best DQS1 dly(2T, 0.5T) = (0, 11)
3126 01:00:18.279921 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 01:00:18.283208 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3128 01:00:18.286464 Pre-setting of DQS Precalculation
3129 01:00:18.293092 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3130 01:00:18.293561 ==
3131 01:00:18.296387 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 01:00:18.299779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 01:00:18.300207 ==
3134 01:00:18.306198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 01:00:18.309577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3136 01:00:18.319299 [CA 0] Center 37 (7~67) winsize 61
3137 01:00:18.322736 [CA 1] Center 37 (7~68) winsize 62
3138 01:00:18.326020 [CA 2] Center 34 (4~64) winsize 61
3139 01:00:18.329297 [CA 3] Center 34 (4~64) winsize 61
3140 01:00:18.332472 [CA 4] Center 34 (4~64) winsize 61
3141 01:00:18.336061 [CA 5] Center 33 (3~63) winsize 61
3142 01:00:18.336482
3143 01:00:18.339379 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3144 01:00:18.339800
3145 01:00:18.342495 [CATrainingPosCal] consider 1 rank data
3146 01:00:18.345924 u2DelayCellTimex100 = 270/100 ps
3147 01:00:18.349416 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3148 01:00:18.352646 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 01:00:18.359183 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 01:00:18.362797 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 01:00:18.366070 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 01:00:18.369337 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3153 01:00:18.369789
3154 01:00:18.372733 CA PerBit enable=1, Macro0, CA PI delay=33
3155 01:00:18.373153
3156 01:00:18.376064 [CBTSetCACLKResult] CA Dly = 33
3157 01:00:18.376486 CS Dly: 6 (0~37)
3158 01:00:18.376821 ==
3159 01:00:18.379461 Dram Type= 6, Freq= 0, CH_1, rank 1
3160 01:00:18.385977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 01:00:18.386404 ==
3162 01:00:18.389350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3163 01:00:18.395922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3164 01:00:18.404621 [CA 0] Center 37 (7~67) winsize 61
3165 01:00:18.408252 [CA 1] Center 37 (7~68) winsize 62
3166 01:00:18.411638 [CA 2] Center 34 (4~65) winsize 62
3167 01:00:18.414840 [CA 3] Center 33 (3~64) winsize 62
3168 01:00:18.418078 [CA 4] Center 34 (4~64) winsize 61
3169 01:00:18.421294 [CA 5] Center 32 (2~63) winsize 62
3170 01:00:18.421771
3171 01:00:18.424953 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3172 01:00:18.425374
3173 01:00:18.427997 [CATrainingPosCal] consider 2 rank data
3174 01:00:18.431432 u2DelayCellTimex100 = 270/100 ps
3175 01:00:18.434757 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3176 01:00:18.438011 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3177 01:00:18.444975 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 01:00:18.447837 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3179 01:00:18.451416 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 01:00:18.454619 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3181 01:00:18.455044
3182 01:00:18.457881 CA PerBit enable=1, Macro0, CA PI delay=33
3183 01:00:18.458307
3184 01:00:18.461277 [CBTSetCACLKResult] CA Dly = 33
3185 01:00:18.461736 CS Dly: 7 (0~39)
3186 01:00:18.462080
3187 01:00:18.464710 ----->DramcWriteLeveling(PI) begin...
3188 01:00:18.468164 ==
3189 01:00:18.471352 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 01:00:18.474704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 01:00:18.475129 ==
3192 01:00:18.477973 Write leveling (Byte 0): 25 => 25
3193 01:00:18.481291 Write leveling (Byte 1): 28 => 28
3194 01:00:18.484723 DramcWriteLeveling(PI) end<-----
3195 01:00:18.485144
3196 01:00:18.485506 ==
3197 01:00:18.488196 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 01:00:18.491322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 01:00:18.491742 ==
3200 01:00:18.494644 [Gating] SW mode calibration
3201 01:00:18.501550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3202 01:00:18.504817 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3203 01:00:18.511287 0 15 0 | B1->B0 | 2f2f 2828 | 1 0 | (1 1) (0 0)
3204 01:00:18.514693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 01:00:18.518156 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 01:00:18.524732 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 01:00:18.528020 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 01:00:18.531222 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 01:00:18.538195 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 01:00:18.541401 0 15 28 | B1->B0 | 2e2e 3030 | 1 1 | (1 1) (0 0)
3211 01:00:18.544571 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3212 01:00:18.551591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 01:00:18.554895 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 01:00:18.558205 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 01:00:18.565013 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 01:00:18.568399 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 01:00:18.571841 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 01:00:18.578313 1 0 28 | B1->B0 | 3f3f 3b3b | 0 0 | (0 0) (0 0)
3219 01:00:18.581613 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3220 01:00:18.585137 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 01:00:18.588063 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 01:00:18.594734 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 01:00:18.597849 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 01:00:18.601359 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 01:00:18.608024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 01:00:18.611066 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3227 01:00:18.614305 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3228 01:00:18.621016 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 01:00:18.624418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 01:00:18.627605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 01:00:18.634116 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 01:00:18.637291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 01:00:18.640950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 01:00:18.647549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 01:00:18.650776 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 01:00:18.654077 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 01:00:18.660662 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 01:00:18.663976 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 01:00:18.667485 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 01:00:18.674181 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 01:00:18.677701 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 01:00:18.680769 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3243 01:00:18.687809 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 01:00:18.687891 Total UI for P1: 0, mck2ui 16
3245 01:00:18.690958 best dqsien dly found for B0: ( 1, 3, 28)
3246 01:00:18.694305 Total UI for P1: 0, mck2ui 16
3247 01:00:18.697668 best dqsien dly found for B1: ( 1, 3, 28)
3248 01:00:18.700806 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3249 01:00:18.707396 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3250 01:00:18.707479
3251 01:00:18.711098 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3252 01:00:18.714386 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3253 01:00:18.717396 [Gating] SW calibration Done
3254 01:00:18.717552 ==
3255 01:00:18.720891 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 01:00:18.724273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 01:00:18.724355 ==
3258 01:00:18.727558 RX Vref Scan: 0
3259 01:00:18.727640
3260 01:00:18.727705 RX Vref 0 -> 0, step: 1
3261 01:00:18.727765
3262 01:00:18.730780 RX Delay -40 -> 252, step: 8
3263 01:00:18.734174 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3264 01:00:18.737367 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3265 01:00:18.744180 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3266 01:00:18.747425 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3267 01:00:18.751085 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3268 01:00:18.754028 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3269 01:00:18.757677 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3270 01:00:18.764282 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3271 01:00:18.767482 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3272 01:00:18.770726 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3273 01:00:18.773975 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3274 01:00:18.777367 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3275 01:00:18.784182 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3276 01:00:18.787527 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3277 01:00:18.791088 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3278 01:00:18.794056 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3279 01:00:18.794137 ==
3280 01:00:18.797309 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 01:00:18.804001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 01:00:18.804087 ==
3283 01:00:18.804152 DQS Delay:
3284 01:00:18.804214 DQS0 = 0, DQS1 = 0
3285 01:00:18.807406 DQM Delay:
3286 01:00:18.807489 DQM0 = 115, DQM1 = 106
3287 01:00:18.810674 DQ Delay:
3288 01:00:18.814019 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =115
3289 01:00:18.817286 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3290 01:00:18.820706 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3291 01:00:18.823946 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3292 01:00:18.824028
3293 01:00:18.824093
3294 01:00:18.824153 ==
3295 01:00:18.827558 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 01:00:18.830747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 01:00:18.830830 ==
3298 01:00:18.830895
3299 01:00:18.833980
3300 01:00:18.834062 TX Vref Scan disable
3301 01:00:18.837511 == TX Byte 0 ==
3302 01:00:18.840799 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 01:00:18.843980 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 01:00:18.847268 == TX Byte 1 ==
3305 01:00:18.850708 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 01:00:18.853943 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 01:00:18.854029 ==
3308 01:00:18.857426 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 01:00:18.863854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 01:00:18.863937 ==
3311 01:00:18.874494 TX Vref=22, minBit 10, minWin=24, winSum=408
3312 01:00:18.877734 TX Vref=24, minBit 8, minWin=25, winSum=414
3313 01:00:18.881202 TX Vref=26, minBit 9, minWin=25, winSum=419
3314 01:00:18.884446 TX Vref=28, minBit 9, minWin=25, winSum=422
3315 01:00:18.887683 TX Vref=30, minBit 9, minWin=25, winSum=425
3316 01:00:18.894283 TX Vref=32, minBit 9, minWin=25, winSum=420
3317 01:00:18.897825 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 30
3318 01:00:18.897908
3319 01:00:18.900937 Final TX Range 1 Vref 30
3320 01:00:18.901023
3321 01:00:18.901088 ==
3322 01:00:18.904452 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 01:00:18.907824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 01:00:18.907908 ==
3325 01:00:18.911043
3326 01:00:18.911125
3327 01:00:18.911189 TX Vref Scan disable
3328 01:00:18.914340 == TX Byte 0 ==
3329 01:00:18.917583 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3330 01:00:18.924121 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3331 01:00:18.924203 == TX Byte 1 ==
3332 01:00:18.927321 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3333 01:00:18.934081 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3334 01:00:18.934165
3335 01:00:18.934230 [DATLAT]
3336 01:00:18.934291 Freq=1200, CH1 RK0
3337 01:00:18.934349
3338 01:00:18.937305 DATLAT Default: 0xd
3339 01:00:18.937387 0, 0xFFFF, sum = 0
3340 01:00:18.940733 1, 0xFFFF, sum = 0
3341 01:00:18.944108 2, 0xFFFF, sum = 0
3342 01:00:18.944192 3, 0xFFFF, sum = 0
3343 01:00:18.947414 4, 0xFFFF, sum = 0
3344 01:00:18.947498 5, 0xFFFF, sum = 0
3345 01:00:18.950730 6, 0xFFFF, sum = 0
3346 01:00:18.950814 7, 0xFFFF, sum = 0
3347 01:00:18.953946 8, 0xFFFF, sum = 0
3348 01:00:18.954029 9, 0xFFFF, sum = 0
3349 01:00:18.957263 10, 0xFFFF, sum = 0
3350 01:00:18.957346 11, 0xFFFF, sum = 0
3351 01:00:18.960538 12, 0x0, sum = 1
3352 01:00:18.960622 13, 0x0, sum = 2
3353 01:00:18.964000 14, 0x0, sum = 3
3354 01:00:18.964084 15, 0x0, sum = 4
3355 01:00:18.967177 best_step = 13
3356 01:00:18.967259
3357 01:00:18.967323 ==
3358 01:00:18.970362 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 01:00:18.973873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 01:00:18.973956 ==
3361 01:00:18.974021 RX Vref Scan: 1
3362 01:00:18.977385
3363 01:00:18.977473 Set Vref Range= 32 -> 127
3364 01:00:18.977615
3365 01:00:18.980401 RX Vref 32 -> 127, step: 1
3366 01:00:18.980486
3367 01:00:18.983580 RX Delay -21 -> 252, step: 4
3368 01:00:18.983663
3369 01:00:18.986934 Set Vref, RX VrefLevel [Byte0]: 32
3370 01:00:18.990130 [Byte1]: 32
3371 01:00:18.990212
3372 01:00:18.993450 Set Vref, RX VrefLevel [Byte0]: 33
3373 01:00:18.996611 [Byte1]: 33
3374 01:00:19.000855
3375 01:00:19.000936 Set Vref, RX VrefLevel [Byte0]: 34
3376 01:00:19.003960 [Byte1]: 34
3377 01:00:19.008892
3378 01:00:19.008973 Set Vref, RX VrefLevel [Byte0]: 35
3379 01:00:19.011944 [Byte1]: 35
3380 01:00:19.016481
3381 01:00:19.016565 Set Vref, RX VrefLevel [Byte0]: 36
3382 01:00:19.019793 [Byte1]: 36
3383 01:00:19.024456
3384 01:00:19.024538 Set Vref, RX VrefLevel [Byte0]: 37
3385 01:00:19.027900 [Byte1]: 37
3386 01:00:19.032304
3387 01:00:19.032384 Set Vref, RX VrefLevel [Byte0]: 38
3388 01:00:19.035751 [Byte1]: 38
3389 01:00:19.040481
3390 01:00:19.040561 Set Vref, RX VrefLevel [Byte0]: 39
3391 01:00:19.043747 [Byte1]: 39
3392 01:00:19.048196
3393 01:00:19.048277 Set Vref, RX VrefLevel [Byte0]: 40
3394 01:00:19.051496 [Byte1]: 40
3395 01:00:19.056149
3396 01:00:19.056230 Set Vref, RX VrefLevel [Byte0]: 41
3397 01:00:19.059459 [Byte1]: 41
3398 01:00:19.064257
3399 01:00:19.064337 Set Vref, RX VrefLevel [Byte0]: 42
3400 01:00:19.067251 [Byte1]: 42
3401 01:00:19.071837
3402 01:00:19.071917 Set Vref, RX VrefLevel [Byte0]: 43
3403 01:00:19.075285 [Byte1]: 43
3404 01:00:19.079872
3405 01:00:19.079952 Set Vref, RX VrefLevel [Byte0]: 44
3406 01:00:19.083087 [Byte1]: 44
3407 01:00:19.087772
3408 01:00:19.087852 Set Vref, RX VrefLevel [Byte0]: 45
3409 01:00:19.091177 [Byte1]: 45
3410 01:00:19.095678
3411 01:00:19.095758 Set Vref, RX VrefLevel [Byte0]: 46
3412 01:00:19.098928 [Byte1]: 46
3413 01:00:19.103912
3414 01:00:19.103993 Set Vref, RX VrefLevel [Byte0]: 47
3415 01:00:19.107238 [Byte1]: 47
3416 01:00:19.111604
3417 01:00:19.111684 Set Vref, RX VrefLevel [Byte0]: 48
3418 01:00:19.115040 [Byte1]: 48
3419 01:00:19.119536
3420 01:00:19.119616 Set Vref, RX VrefLevel [Byte0]: 49
3421 01:00:19.122849 [Byte1]: 49
3422 01:00:19.127414
3423 01:00:19.127494 Set Vref, RX VrefLevel [Byte0]: 50
3424 01:00:19.130603 [Byte1]: 50
3425 01:00:19.135468
3426 01:00:19.135549 Set Vref, RX VrefLevel [Byte0]: 51
3427 01:00:19.138604 [Byte1]: 51
3428 01:00:19.143425
3429 01:00:19.143504 Set Vref, RX VrefLevel [Byte0]: 52
3430 01:00:19.146425 [Byte1]: 52
3431 01:00:19.151119
3432 01:00:19.151199 Set Vref, RX VrefLevel [Byte0]: 53
3433 01:00:19.154421 [Byte1]: 53
3434 01:00:19.159142
3435 01:00:19.159223 Set Vref, RX VrefLevel [Byte0]: 54
3436 01:00:19.162373 [Byte1]: 54
3437 01:00:19.167156
3438 01:00:19.167236 Set Vref, RX VrefLevel [Byte0]: 55
3439 01:00:19.170363 [Byte1]: 55
3440 01:00:19.175098
3441 01:00:19.175178 Set Vref, RX VrefLevel [Byte0]: 56
3442 01:00:19.178299 [Byte1]: 56
3443 01:00:19.182943
3444 01:00:19.183023 Set Vref, RX VrefLevel [Byte0]: 57
3445 01:00:19.186293 [Byte1]: 57
3446 01:00:19.190784
3447 01:00:19.190864 Set Vref, RX VrefLevel [Byte0]: 58
3448 01:00:19.194152 [Byte1]: 58
3449 01:00:19.198904
3450 01:00:19.198985 Set Vref, RX VrefLevel [Byte0]: 59
3451 01:00:19.201902 [Byte1]: 59
3452 01:00:19.206586
3453 01:00:19.206666 Set Vref, RX VrefLevel [Byte0]: 60
3454 01:00:19.209815 [Byte1]: 60
3455 01:00:19.214386
3456 01:00:19.214466 Set Vref, RX VrefLevel [Byte0]: 61
3457 01:00:19.217770 [Byte1]: 61
3458 01:00:19.222442
3459 01:00:19.222523 Set Vref, RX VrefLevel [Byte0]: 62
3460 01:00:19.225706 [Byte1]: 62
3461 01:00:19.230410
3462 01:00:19.230491 Set Vref, RX VrefLevel [Byte0]: 63
3463 01:00:19.233723 [Byte1]: 63
3464 01:00:19.238358
3465 01:00:19.238438 Set Vref, RX VrefLevel [Byte0]: 64
3466 01:00:19.241580 [Byte1]: 64
3467 01:00:19.246269
3468 01:00:19.246349 Set Vref, RX VrefLevel [Byte0]: 65
3469 01:00:19.249391 [Byte1]: 65
3470 01:00:19.254089
3471 01:00:19.254169 Set Vref, RX VrefLevel [Byte0]: 66
3472 01:00:19.257331 [Byte1]: 66
3473 01:00:19.262267
3474 01:00:19.262347 Set Vref, RX VrefLevel [Byte0]: 67
3475 01:00:19.265503 [Byte1]: 67
3476 01:00:19.269891
3477 01:00:19.269971 Final RX Vref Byte 0 = 55 to rank0
3478 01:00:19.273432 Final RX Vref Byte 1 = 53 to rank0
3479 01:00:19.276783 Final RX Vref Byte 0 = 55 to rank1
3480 01:00:19.280037 Final RX Vref Byte 1 = 53 to rank1==
3481 01:00:19.283597 Dram Type= 6, Freq= 0, CH_1, rank 0
3482 01:00:19.286856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 01:00:19.290075 ==
3484 01:00:19.290157 DQS Delay:
3485 01:00:19.290222 DQS0 = 0, DQS1 = 0
3486 01:00:19.293568 DQM Delay:
3487 01:00:19.293649 DQM0 = 114, DQM1 = 107
3488 01:00:19.296778 DQ Delay:
3489 01:00:19.300328 DQ0 =116, DQ1 =112, DQ2 =104, DQ3 =112
3490 01:00:19.303476 DQ4 =112, DQ5 =120, DQ6 =124, DQ7 =112
3491 01:00:19.307043 DQ8 =92, DQ9 =96, DQ10 =106, DQ11 =102
3492 01:00:19.310317 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3493 01:00:19.310400
3494 01:00:19.310466
3495 01:00:19.316759 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3496 01:00:19.319840 CH1 RK0: MR19=303, MR18=EFF6
3497 01:00:19.326596 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3498 01:00:19.326679
3499 01:00:19.329867 ----->DramcWriteLeveling(PI) begin...
3500 01:00:19.329952 ==
3501 01:00:19.333173 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 01:00:19.336760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 01:00:19.339990 ==
3504 01:00:19.340073 Write leveling (Byte 0): 25 => 25
3505 01:00:19.343253 Write leveling (Byte 1): 26 => 26
3506 01:00:19.346656 DramcWriteLeveling(PI) end<-----
3507 01:00:19.346738
3508 01:00:19.346802 ==
3509 01:00:19.349893 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 01:00:19.356569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 01:00:19.356652 ==
3512 01:00:19.356717 [Gating] SW mode calibration
3513 01:00:19.366336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3514 01:00:19.369763 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3515 01:00:19.373392 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 01:00:19.379812 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 01:00:19.383139 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 01:00:19.386720 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 01:00:19.393326 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 01:00:19.396474 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 01:00:19.399812 0 15 24 | B1->B0 | 3333 2727 | 1 0 | (1 0) (1 0)
3522 01:00:19.406779 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3523 01:00:19.410077 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 01:00:19.413319 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 01:00:19.419869 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 01:00:19.423234 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 01:00:19.426652 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 01:00:19.433199 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3529 01:00:19.436426 1 0 24 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
3530 01:00:19.439837 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3531 01:00:19.446654 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 01:00:19.449976 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 01:00:19.453329 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 01:00:19.460023 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 01:00:19.463293 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 01:00:19.466391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3537 01:00:19.473038 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3538 01:00:19.476566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3539 01:00:19.479479 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 01:00:19.486150 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 01:00:19.489446 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 01:00:19.492830 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 01:00:19.499461 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 01:00:19.502639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 01:00:19.505944 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 01:00:19.509278 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 01:00:19.516164 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 01:00:19.519427 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 01:00:19.522588 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 01:00:19.529275 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 01:00:19.532618 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 01:00:19.535740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 01:00:19.542582 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3554 01:00:19.545783 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3555 01:00:19.549168 Total UI for P1: 0, mck2ui 16
3556 01:00:19.552297 best dqsien dly found for B0: ( 1, 3, 24)
3557 01:00:19.555572 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 01:00:19.558847 Total UI for P1: 0, mck2ui 16
3559 01:00:19.562053 best dqsien dly found for B1: ( 1, 3, 26)
3560 01:00:19.565684 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3561 01:00:19.569238 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3562 01:00:19.572188
3563 01:00:19.575653 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3564 01:00:19.578745 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3565 01:00:19.582274 [Gating] SW calibration Done
3566 01:00:19.582360 ==
3567 01:00:19.585765 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 01:00:19.588853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 01:00:19.588936 ==
3570 01:00:19.589002 RX Vref Scan: 0
3571 01:00:19.592232
3572 01:00:19.592314 RX Vref 0 -> 0, step: 1
3573 01:00:19.592379
3574 01:00:19.595590 RX Delay -40 -> 252, step: 8
3575 01:00:19.598970 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3576 01:00:19.601893 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3577 01:00:19.608850 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3578 01:00:19.612073 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3579 01:00:19.615410 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3580 01:00:19.618601 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3581 01:00:19.621860 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3582 01:00:19.628381 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3583 01:00:19.631790 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3584 01:00:19.635093 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3585 01:00:19.638498 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3586 01:00:19.641675 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3587 01:00:19.648384 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3588 01:00:19.651957 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3589 01:00:19.655081 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3590 01:00:19.658297 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3591 01:00:19.658380 ==
3592 01:00:19.661515 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 01:00:19.668417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 01:00:19.668501 ==
3595 01:00:19.668565 DQS Delay:
3596 01:00:19.671722 DQS0 = 0, DQS1 = 0
3597 01:00:19.671805 DQM Delay:
3598 01:00:19.671870 DQM0 = 110, DQM1 = 108
3599 01:00:19.674903 DQ Delay:
3600 01:00:19.678029 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3601 01:00:19.681448 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3602 01:00:19.684644 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3603 01:00:19.687982 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3604 01:00:19.688065
3605 01:00:19.688129
3606 01:00:19.688190 ==
3607 01:00:19.691592 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 01:00:19.694826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 01:00:19.697948 ==
3610 01:00:19.698029
3611 01:00:19.698093
3612 01:00:19.698153 TX Vref Scan disable
3613 01:00:19.701301 == TX Byte 0 ==
3614 01:00:19.704620 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3615 01:00:19.707844 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3616 01:00:19.711269 == TX Byte 1 ==
3617 01:00:19.714507 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3618 01:00:19.717707 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3619 01:00:19.721008 ==
3620 01:00:19.724648 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 01:00:19.727542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 01:00:19.727624 ==
3623 01:00:19.738783 TX Vref=22, minBit 9, minWin=25, winSum=420
3624 01:00:19.742107 TX Vref=24, minBit 1, minWin=26, winSum=426
3625 01:00:19.745598 TX Vref=26, minBit 3, minWin=26, winSum=429
3626 01:00:19.748961 TX Vref=28, minBit 9, minWin=26, winSum=430
3627 01:00:19.752036 TX Vref=30, minBit 9, minWin=26, winSum=430
3628 01:00:19.755260 TX Vref=32, minBit 1, minWin=25, winSum=429
3629 01:00:19.762080 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 28
3630 01:00:19.762163
3631 01:00:19.765193 Final TX Range 1 Vref 28
3632 01:00:19.765276
3633 01:00:19.765341 ==
3634 01:00:19.768727 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 01:00:19.771941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 01:00:19.772025 ==
3637 01:00:19.775272
3638 01:00:19.775354
3639 01:00:19.775418 TX Vref Scan disable
3640 01:00:19.778500 == TX Byte 0 ==
3641 01:00:19.781730 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3642 01:00:19.785076 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3643 01:00:19.788536 == TX Byte 1 ==
3644 01:00:19.791854 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3645 01:00:19.798314 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3646 01:00:19.798397
3647 01:00:19.798462 [DATLAT]
3648 01:00:19.798522 Freq=1200, CH1 RK1
3649 01:00:19.798580
3650 01:00:19.801655 DATLAT Default: 0xd
3651 01:00:19.801738 0, 0xFFFF, sum = 0
3652 01:00:19.804852 1, 0xFFFF, sum = 0
3653 01:00:19.808524 2, 0xFFFF, sum = 0
3654 01:00:19.808607 3, 0xFFFF, sum = 0
3655 01:00:19.811694 4, 0xFFFF, sum = 0
3656 01:00:19.811778 5, 0xFFFF, sum = 0
3657 01:00:19.815117 6, 0xFFFF, sum = 0
3658 01:00:19.815201 7, 0xFFFF, sum = 0
3659 01:00:19.818236 8, 0xFFFF, sum = 0
3660 01:00:19.818319 9, 0xFFFF, sum = 0
3661 01:00:19.821454 10, 0xFFFF, sum = 0
3662 01:00:19.821576 11, 0xFFFF, sum = 0
3663 01:00:19.824784 12, 0x0, sum = 1
3664 01:00:19.824867 13, 0x0, sum = 2
3665 01:00:19.828034 14, 0x0, sum = 3
3666 01:00:19.828118 15, 0x0, sum = 4
3667 01:00:19.831671 best_step = 13
3668 01:00:19.831753
3669 01:00:19.831817 ==
3670 01:00:19.834940 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 01:00:19.838158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 01:00:19.838242 ==
3673 01:00:19.838307 RX Vref Scan: 0
3674 01:00:19.841348
3675 01:00:19.841430 RX Vref 0 -> 0, step: 1
3676 01:00:19.841536
3677 01:00:19.844448 RX Delay -21 -> 252, step: 4
3678 01:00:19.851216 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3679 01:00:19.854476 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3680 01:00:19.857865 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3681 01:00:19.861259 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3682 01:00:19.864565 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3683 01:00:19.871048 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3684 01:00:19.874324 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3685 01:00:19.877661 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3686 01:00:19.880846 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3687 01:00:19.884017 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3688 01:00:19.890662 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3689 01:00:19.894101 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3690 01:00:19.897302 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3691 01:00:19.900882 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3692 01:00:19.904062 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3693 01:00:19.910602 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3694 01:00:19.910691 ==
3695 01:00:19.913884 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 01:00:19.917235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 01:00:19.917319 ==
3698 01:00:19.917384 DQS Delay:
3699 01:00:19.920526 DQS0 = 0, DQS1 = 0
3700 01:00:19.920609 DQM Delay:
3701 01:00:19.923738 DQM0 = 111, DQM1 = 110
3702 01:00:19.923819 DQ Delay:
3703 01:00:19.926887 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3704 01:00:19.930291 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =110
3705 01:00:19.933728 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =106
3706 01:00:19.940300 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3707 01:00:19.940389
3708 01:00:19.940476
3709 01:00:19.946962 [DQSOSCAuto] RK1, (LSB)MR18= 0xf706, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3710 01:00:19.950335 CH1 RK1: MR19=304, MR18=F706
3711 01:00:19.957017 CH1_RK1: MR19=0x304, MR18=0xF706, DQSOSC=407, MR23=63, INC=39, DEC=26
3712 01:00:19.960049 [RxdqsGatingPostProcess] freq 1200
3713 01:00:19.963617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3714 01:00:19.966924 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 01:00:19.970214 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 01:00:19.973396 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 01:00:19.976722 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 01:00:19.980285 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 01:00:19.983575 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 01:00:19.986482 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 01:00:19.989974 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 01:00:19.993055 Pre-setting of DQS Precalculation
3723 01:00:19.996672 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3724 01:00:20.006365 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3725 01:00:20.013042 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3726 01:00:20.013139
3727 01:00:20.013205
3728 01:00:20.016433 [Calibration Summary] 2400 Mbps
3729 01:00:20.016516 CH 0, Rank 0
3730 01:00:20.019799 SW Impedance : PASS
3731 01:00:20.019881 DUTY Scan : NO K
3732 01:00:20.022950 ZQ Calibration : PASS
3733 01:00:20.026342 Jitter Meter : NO K
3734 01:00:20.026424 CBT Training : PASS
3735 01:00:20.029493 Write leveling : PASS
3736 01:00:20.032752 RX DQS gating : PASS
3737 01:00:20.032834 RX DQ/DQS(RDDQC) : PASS
3738 01:00:20.036169 TX DQ/DQS : PASS
3739 01:00:20.039520 RX DATLAT : PASS
3740 01:00:20.039602 RX DQ/DQS(Engine): PASS
3741 01:00:20.042806 TX OE : NO K
3742 01:00:20.042888 All Pass.
3743 01:00:20.042953
3744 01:00:20.046173 CH 0, Rank 1
3745 01:00:20.046261 SW Impedance : PASS
3746 01:00:20.049378 DUTY Scan : NO K
3747 01:00:20.052643 ZQ Calibration : PASS
3748 01:00:20.052725 Jitter Meter : NO K
3749 01:00:20.055956 CBT Training : PASS
3750 01:00:20.056038 Write leveling : PASS
3751 01:00:20.059163 RX DQS gating : PASS
3752 01:00:20.062534 RX DQ/DQS(RDDQC) : PASS
3753 01:00:20.062615 TX DQ/DQS : PASS
3754 01:00:20.065938 RX DATLAT : PASS
3755 01:00:20.069246 RX DQ/DQS(Engine): PASS
3756 01:00:20.069328 TX OE : NO K
3757 01:00:20.072567 All Pass.
3758 01:00:20.072648
3759 01:00:20.072712 CH 1, Rank 0
3760 01:00:20.075757 SW Impedance : PASS
3761 01:00:20.075838 DUTY Scan : NO K
3762 01:00:20.079148 ZQ Calibration : PASS
3763 01:00:20.082334 Jitter Meter : NO K
3764 01:00:20.082416 CBT Training : PASS
3765 01:00:20.085696 Write leveling : PASS
3766 01:00:20.089257 RX DQS gating : PASS
3767 01:00:20.089337 RX DQ/DQS(RDDQC) : PASS
3768 01:00:20.092299 TX DQ/DQS : PASS
3769 01:00:20.095564 RX DATLAT : PASS
3770 01:00:20.095646 RX DQ/DQS(Engine): PASS
3771 01:00:20.099022 TX OE : NO K
3772 01:00:20.099104 All Pass.
3773 01:00:20.099169
3774 01:00:20.102545 CH 1, Rank 1
3775 01:00:20.102659 SW Impedance : PASS
3776 01:00:20.105578 DUTY Scan : NO K
3777 01:00:20.108678 ZQ Calibration : PASS
3778 01:00:20.108760 Jitter Meter : NO K
3779 01:00:20.112112 CBT Training : PASS
3780 01:00:20.115380 Write leveling : PASS
3781 01:00:20.115461 RX DQS gating : PASS
3782 01:00:20.118822 RX DQ/DQS(RDDQC) : PASS
3783 01:00:20.118904 TX DQ/DQS : PASS
3784 01:00:20.121937 RX DATLAT : PASS
3785 01:00:20.125484 RX DQ/DQS(Engine): PASS
3786 01:00:20.125566 TX OE : NO K
3787 01:00:20.128764 All Pass.
3788 01:00:20.128845
3789 01:00:20.128908 DramC Write-DBI off
3790 01:00:20.132041 PER_BANK_REFRESH: Hybrid Mode
3791 01:00:20.135167 TX_TRACKING: ON
3792 01:00:20.141798 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3793 01:00:20.145415 [FAST_K] Save calibration result to emmc
3794 01:00:20.151697 dramc_set_vcore_voltage set vcore to 650000
3795 01:00:20.151779 Read voltage for 600, 5
3796 01:00:20.151844 Vio18 = 0
3797 01:00:20.155129 Vcore = 650000
3798 01:00:20.155210 Vdram = 0
3799 01:00:20.155274 Vddq = 0
3800 01:00:20.158415 Vmddr = 0
3801 01:00:20.161952 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3802 01:00:20.168324 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3803 01:00:20.171813 MEM_TYPE=3, freq_sel=19
3804 01:00:20.171895 sv_algorithm_assistance_LP4_1600
3805 01:00:20.178145 ============ PULL DRAM RESETB DOWN ============
3806 01:00:20.181683 ========== PULL DRAM RESETB DOWN end =========
3807 01:00:20.184949 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3808 01:00:20.188208 ===================================
3809 01:00:20.191374 LPDDR4 DRAM CONFIGURATION
3810 01:00:20.194644 ===================================
3811 01:00:20.197946 EX_ROW_EN[0] = 0x0
3812 01:00:20.198029 EX_ROW_EN[1] = 0x0
3813 01:00:20.201356 LP4Y_EN = 0x0
3814 01:00:20.201438 WORK_FSP = 0x0
3815 01:00:20.204901 WL = 0x2
3816 01:00:20.204990 RL = 0x2
3817 01:00:20.207959 BL = 0x2
3818 01:00:20.208041 RPST = 0x0
3819 01:00:20.211221 RD_PRE = 0x0
3820 01:00:20.211333 WR_PRE = 0x1
3821 01:00:20.214533 WR_PST = 0x0
3822 01:00:20.214616 DBI_WR = 0x0
3823 01:00:20.217750 DBI_RD = 0x0
3824 01:00:20.221219 OTF = 0x1
3825 01:00:20.224549 ===================================
3826 01:00:20.227591 ===================================
3827 01:00:20.227674 ANA top config
3828 01:00:20.231149 ===================================
3829 01:00:20.234441 DLL_ASYNC_EN = 0
3830 01:00:20.234524 ALL_SLAVE_EN = 1
3831 01:00:20.237718 NEW_RANK_MODE = 1
3832 01:00:20.241025 DLL_IDLE_MODE = 1
3833 01:00:20.244285 LP45_APHY_COMB_EN = 1
3834 01:00:20.247456 TX_ODT_DIS = 1
3835 01:00:20.247539 NEW_8X_MODE = 1
3836 01:00:20.250834 ===================================
3837 01:00:20.254020 ===================================
3838 01:00:20.257412 data_rate = 1200
3839 01:00:20.260837 CKR = 1
3840 01:00:20.263988 DQ_P2S_RATIO = 8
3841 01:00:20.267194 ===================================
3842 01:00:20.270695 CA_P2S_RATIO = 8
3843 01:00:20.274105 DQ_CA_OPEN = 0
3844 01:00:20.274187 DQ_SEMI_OPEN = 0
3845 01:00:20.277312 CA_SEMI_OPEN = 0
3846 01:00:20.280544 CA_FULL_RATE = 0
3847 01:00:20.283918 DQ_CKDIV4_EN = 1
3848 01:00:20.287158 CA_CKDIV4_EN = 1
3849 01:00:20.290445 CA_PREDIV_EN = 0
3850 01:00:20.290528 PH8_DLY = 0
3851 01:00:20.294000 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3852 01:00:20.297223 DQ_AAMCK_DIV = 4
3853 01:00:20.300467 CA_AAMCK_DIV = 4
3854 01:00:20.303784 CA_ADMCK_DIV = 4
3855 01:00:20.307070 DQ_TRACK_CA_EN = 0
3856 01:00:20.310141 CA_PICK = 600
3857 01:00:20.310224 CA_MCKIO = 600
3858 01:00:20.313573 MCKIO_SEMI = 0
3859 01:00:20.316986 PLL_FREQ = 2288
3860 01:00:20.320166 DQ_UI_PI_RATIO = 32
3861 01:00:20.323686 CA_UI_PI_RATIO = 0
3862 01:00:20.327066 ===================================
3863 01:00:20.330249 ===================================
3864 01:00:20.333518 memory_type:LPDDR4
3865 01:00:20.333601 GP_NUM : 10
3866 01:00:20.336962 SRAM_EN : 1
3867 01:00:20.337044 MD32_EN : 0
3868 01:00:20.340264 ===================================
3869 01:00:20.343417 [ANA_INIT] >>>>>>>>>>>>>>
3870 01:00:20.346934 <<<<<< [CONFIGURE PHASE]: ANA_TX
3871 01:00:20.350236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3872 01:00:20.353639 ===================================
3873 01:00:20.357023 data_rate = 1200,PCW = 0X5800
3874 01:00:20.360309 ===================================
3875 01:00:20.363484 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3876 01:00:20.366834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 01:00:20.373306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 01:00:20.379952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3879 01:00:20.383339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3880 01:00:20.386674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3881 01:00:20.386758 [ANA_INIT] flow start
3882 01:00:20.389930 [ANA_INIT] PLL >>>>>>>>
3883 01:00:20.393276 [ANA_INIT] PLL <<<<<<<<
3884 01:00:20.393358 [ANA_INIT] MIDPI >>>>>>>>
3885 01:00:20.396614 [ANA_INIT] MIDPI <<<<<<<<
3886 01:00:20.399843 [ANA_INIT] DLL >>>>>>>>
3887 01:00:20.399925 [ANA_INIT] flow end
3888 01:00:20.406458 ============ LP4 DIFF to SE enter ============
3889 01:00:20.409985 ============ LP4 DIFF to SE exit ============
3890 01:00:20.410065 [ANA_INIT] <<<<<<<<<<<<<
3891 01:00:20.413267 [Flow] Enable top DCM control >>>>>
3892 01:00:20.416517 [Flow] Enable top DCM control <<<<<
3893 01:00:20.419657 Enable DLL master slave shuffle
3894 01:00:20.426239 ==============================================================
3895 01:00:20.429715 Gating Mode config
3896 01:00:20.433120 ==============================================================
3897 01:00:20.436436 Config description:
3898 01:00:20.446223 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3899 01:00:20.453073 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3900 01:00:20.456449 SELPH_MODE 0: By rank 1: By Phase
3901 01:00:20.462885 ==============================================================
3902 01:00:20.466235 GAT_TRACK_EN = 1
3903 01:00:20.469905 RX_GATING_MODE = 2
3904 01:00:20.473053 RX_GATING_TRACK_MODE = 2
3905 01:00:20.473136 SELPH_MODE = 1
3906 01:00:20.476306 PICG_EARLY_EN = 1
3907 01:00:20.479561 VALID_LAT_VALUE = 1
3908 01:00:20.486552 ==============================================================
3909 01:00:20.489639 Enter into Gating configuration >>>>
3910 01:00:20.492952 Exit from Gating configuration <<<<
3911 01:00:20.496490 Enter into DVFS_PRE_config >>>>>
3912 01:00:20.506339 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3913 01:00:20.509343 Exit from DVFS_PRE_config <<<<<
3914 01:00:20.512714 Enter into PICG configuration >>>>
3915 01:00:20.516062 Exit from PICG configuration <<<<
3916 01:00:20.519264 [RX_INPUT] configuration >>>>>
3917 01:00:20.522551 [RX_INPUT] configuration <<<<<
3918 01:00:20.525829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3919 01:00:20.532521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3920 01:00:20.539225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 01:00:20.545834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 01:00:20.552489 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 01:00:20.555630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 01:00:20.562369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3925 01:00:20.565654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3926 01:00:20.569050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3927 01:00:20.572086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3928 01:00:20.578915 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3929 01:00:20.582235 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 01:00:20.585488 ===================================
3931 01:00:20.588745 LPDDR4 DRAM CONFIGURATION
3932 01:00:20.592003 ===================================
3933 01:00:20.592079 EX_ROW_EN[0] = 0x0
3934 01:00:20.595232 EX_ROW_EN[1] = 0x0
3935 01:00:20.595303 LP4Y_EN = 0x0
3936 01:00:20.598495 WORK_FSP = 0x0
3937 01:00:20.598567 WL = 0x2
3938 01:00:20.602027 RL = 0x2
3939 01:00:20.602146 BL = 0x2
3940 01:00:20.605345 RPST = 0x0
3941 01:00:20.605443 RD_PRE = 0x0
3942 01:00:20.608681 WR_PRE = 0x1
3943 01:00:20.611898 WR_PST = 0x0
3944 01:00:20.611999 DBI_WR = 0x0
3945 01:00:20.615175 DBI_RD = 0x0
3946 01:00:20.615264 OTF = 0x1
3947 01:00:20.618605 ===================================
3948 01:00:20.621798 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3949 01:00:20.628341 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3950 01:00:20.631829 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3951 01:00:20.635041 ===================================
3952 01:00:20.638259 LPDDR4 DRAM CONFIGURATION
3953 01:00:20.641560 ===================================
3954 01:00:20.641631 EX_ROW_EN[0] = 0x10
3955 01:00:20.644894 EX_ROW_EN[1] = 0x0
3956 01:00:20.644962 LP4Y_EN = 0x0
3957 01:00:20.648243 WORK_FSP = 0x0
3958 01:00:20.648315 WL = 0x2
3959 01:00:20.651575 RL = 0x2
3960 01:00:20.651643 BL = 0x2
3961 01:00:20.654772 RPST = 0x0
3962 01:00:20.654845 RD_PRE = 0x0
3963 01:00:20.658138 WR_PRE = 0x1
3964 01:00:20.661366 WR_PST = 0x0
3965 01:00:20.661463 DBI_WR = 0x0
3966 01:00:20.664677 DBI_RD = 0x0
3967 01:00:20.664744 OTF = 0x1
3968 01:00:20.667944 ===================================
3969 01:00:20.674550 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3970 01:00:20.678278 nWR fixed to 30
3971 01:00:20.681639 [ModeRegInit_LP4] CH0 RK0
3972 01:00:20.681707 [ModeRegInit_LP4] CH0 RK1
3973 01:00:20.684762 [ModeRegInit_LP4] CH1 RK0
3974 01:00:20.688377 [ModeRegInit_LP4] CH1 RK1
3975 01:00:20.688478 match AC timing 17
3976 01:00:20.694948 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3977 01:00:20.698119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3978 01:00:20.701368 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3979 01:00:20.708053 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3980 01:00:20.711273 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3981 01:00:20.711376 ==
3982 01:00:20.714862 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 01:00:20.718022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 01:00:20.718094 ==
3985 01:00:20.724617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 01:00:20.731478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3987 01:00:20.734759 [CA 0] Center 37 (7~67) winsize 61
3988 01:00:20.738221 [CA 1] Center 36 (6~67) winsize 62
3989 01:00:20.741303 [CA 2] Center 35 (5~65) winsize 61
3990 01:00:20.744642 [CA 3] Center 35 (5~65) winsize 61
3991 01:00:20.748025 [CA 4] Center 34 (4~65) winsize 62
3992 01:00:20.751366 [CA 5] Center 34 (4~64) winsize 61
3993 01:00:20.751440
3994 01:00:20.754503 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3995 01:00:20.754576
3996 01:00:20.757877 [CATrainingPosCal] consider 1 rank data
3997 01:00:20.761233 u2DelayCellTimex100 = 270/100 ps
3998 01:00:20.764279 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3999 01:00:20.767650 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4000 01:00:20.770882 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4001 01:00:20.774321 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4002 01:00:20.777527 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4003 01:00:20.784213 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4004 01:00:20.784312
4005 01:00:20.787609 CA PerBit enable=1, Macro0, CA PI delay=34
4006 01:00:20.787680
4007 01:00:20.790877 [CBTSetCACLKResult] CA Dly = 34
4008 01:00:20.790950 CS Dly: 5 (0~36)
4009 01:00:20.791012 ==
4010 01:00:20.794267 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 01:00:20.797634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 01:00:20.800855 ==
4013 01:00:20.803965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4014 01:00:20.810868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4015 01:00:20.813987 [CA 0] Center 37 (7~67) winsize 61
4016 01:00:20.817242 [CA 1] Center 37 (7~67) winsize 61
4017 01:00:20.820546 [CA 2] Center 35 (5~65) winsize 61
4018 01:00:20.824213 [CA 3] Center 34 (4~65) winsize 62
4019 01:00:20.827198 [CA 4] Center 34 (3~65) winsize 63
4020 01:00:20.830850 [CA 5] Center 33 (3~64) winsize 62
4021 01:00:20.830921
4022 01:00:20.834300 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4023 01:00:20.834371
4024 01:00:20.837491 [CATrainingPosCal] consider 2 rank data
4025 01:00:20.840782 u2DelayCellTimex100 = 270/100 ps
4026 01:00:20.843970 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4027 01:00:20.847203 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4028 01:00:20.850679 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4029 01:00:20.858629 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4030 01:00:20.860471 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4031 01:00:20.864004 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4032 01:00:20.864072
4033 01:00:20.867244 CA PerBit enable=1, Macro0, CA PI delay=34
4034 01:00:20.867314
4035 01:00:20.870448 [CBTSetCACLKResult] CA Dly = 34
4036 01:00:20.870521 CS Dly: 5 (0~37)
4037 01:00:20.870583
4038 01:00:20.873916 ----->DramcWriteLeveling(PI) begin...
4039 01:00:20.876881 ==
4040 01:00:20.880496 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 01:00:20.883849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 01:00:20.883917 ==
4043 01:00:20.886855 Write leveling (Byte 0): 35 => 35
4044 01:00:20.890274 Write leveling (Byte 1): 32 => 32
4045 01:00:20.893577 DramcWriteLeveling(PI) end<-----
4046 01:00:20.893646
4047 01:00:20.893707 ==
4048 01:00:20.896895 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 01:00:20.900233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 01:00:20.900309 ==
4051 01:00:20.903520 [Gating] SW mode calibration
4052 01:00:20.910205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4053 01:00:20.913411 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4054 01:00:20.920338 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 01:00:20.923481 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 01:00:20.926775 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 01:00:20.933310 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4058 01:00:20.936569 0 9 16 | B1->B0 | 3131 2727 | 0 0 | (0 1) (1 1)
4059 01:00:20.939981 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4060 01:00:20.946501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 01:00:20.949872 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 01:00:20.953007 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 01:00:20.959830 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 01:00:20.963268 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 01:00:20.966584 0 10 12 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
4066 01:00:20.973044 0 10 16 | B1->B0 | 3535 4040 | 0 0 | (0 0) (0 0)
4067 01:00:20.976611 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 01:00:20.979942 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 01:00:20.986336 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 01:00:20.989622 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 01:00:20.992816 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 01:00:20.999582 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 01:00:21.002858 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4074 01:00:21.006204 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4075 01:00:21.012590 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 01:00:21.016205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 01:00:21.019365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 01:00:21.026034 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 01:00:21.029239 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 01:00:21.032201 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 01:00:21.039145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 01:00:21.042377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 01:00:21.045577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 01:00:21.052200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 01:00:21.055555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 01:00:21.058915 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 01:00:21.065295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 01:00:21.068777 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 01:00:21.072000 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 01:00:21.078691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4091 01:00:21.082216 Total UI for P1: 0, mck2ui 16
4092 01:00:21.085506 best dqsien dly found for B0: ( 0, 13, 14)
4093 01:00:21.088646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 01:00:21.091978 Total UI for P1: 0, mck2ui 16
4095 01:00:21.095242 best dqsien dly found for B1: ( 0, 13, 16)
4096 01:00:21.098720 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4097 01:00:21.101892 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4098 01:00:21.101962
4099 01:00:21.105348 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4100 01:00:21.108503 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4101 01:00:21.111640 [Gating] SW calibration Done
4102 01:00:21.111714 ==
4103 01:00:21.115082 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 01:00:21.121896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 01:00:21.121969 ==
4106 01:00:21.122034 RX Vref Scan: 0
4107 01:00:21.122093
4108 01:00:21.125195 RX Vref 0 -> 0, step: 1
4109 01:00:21.125265
4110 01:00:21.128402 RX Delay -230 -> 252, step: 16
4111 01:00:21.131456 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4112 01:00:21.135162 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4113 01:00:21.138070 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4114 01:00:21.144651 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4115 01:00:21.147938 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4116 01:00:21.151473 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4117 01:00:21.154667 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4118 01:00:21.161270 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4119 01:00:21.164604 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4120 01:00:21.167820 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4121 01:00:21.170992 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4122 01:00:21.177764 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4123 01:00:21.181189 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4124 01:00:21.184270 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4125 01:00:21.187850 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4126 01:00:21.194289 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4127 01:00:21.194362 ==
4128 01:00:21.197618 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 01:00:21.200819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 01:00:21.200888 ==
4131 01:00:21.200947 DQS Delay:
4132 01:00:21.204095 DQS0 = 0, DQS1 = 0
4133 01:00:21.204198 DQM Delay:
4134 01:00:21.207367 DQM0 = 39, DQM1 = 29
4135 01:00:21.207443 DQ Delay:
4136 01:00:21.210993 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =41
4137 01:00:21.214030 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4138 01:00:21.217396 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4139 01:00:21.220688 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4140 01:00:21.220756
4141 01:00:21.220816
4142 01:00:21.220871 ==
4143 01:00:21.224024 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 01:00:21.227316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 01:00:21.227388 ==
4146 01:00:21.227448
4147 01:00:21.230406
4148 01:00:21.230476 TX Vref Scan disable
4149 01:00:21.233932 == TX Byte 0 ==
4150 01:00:21.237297 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4151 01:00:21.240531 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4152 01:00:21.243845 == TX Byte 1 ==
4153 01:00:21.247164 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4154 01:00:21.250499 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4155 01:00:21.253680 ==
4156 01:00:21.253749 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 01:00:21.260214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 01:00:21.260287 ==
4159 01:00:21.260348
4160 01:00:21.260406
4161 01:00:21.263587 TX Vref Scan disable
4162 01:00:21.263655 == TX Byte 0 ==
4163 01:00:21.270047 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4164 01:00:21.273271 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4165 01:00:21.273340 == TX Byte 1 ==
4166 01:00:21.280141 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4167 01:00:21.283319 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4168 01:00:21.283389
4169 01:00:21.283449 [DATLAT]
4170 01:00:21.286713 Freq=600, CH0 RK0
4171 01:00:21.286789
4172 01:00:21.286894 DATLAT Default: 0x9
4173 01:00:21.289809 0, 0xFFFF, sum = 0
4174 01:00:21.289880 1, 0xFFFF, sum = 0
4175 01:00:21.293162 2, 0xFFFF, sum = 0
4176 01:00:21.296481 3, 0xFFFF, sum = 0
4177 01:00:21.296552 4, 0xFFFF, sum = 0
4178 01:00:21.299893 5, 0xFFFF, sum = 0
4179 01:00:21.299965 6, 0xFFFF, sum = 0
4180 01:00:21.303219 7, 0xFFFF, sum = 0
4181 01:00:21.303303 8, 0x0, sum = 1
4182 01:00:21.306489 9, 0x0, sum = 2
4183 01:00:21.306563 10, 0x0, sum = 3
4184 01:00:21.306627 11, 0x0, sum = 4
4185 01:00:21.309816 best_step = 9
4186 01:00:21.309886
4187 01:00:21.309949 ==
4188 01:00:21.313121 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 01:00:21.316424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 01:00:21.316490 ==
4191 01:00:21.319548 RX Vref Scan: 1
4192 01:00:21.319614
4193 01:00:21.319675 RX Vref 0 -> 0, step: 1
4194 01:00:21.323135
4195 01:00:21.323202 RX Delay -195 -> 252, step: 8
4196 01:00:21.323260
4197 01:00:21.326141 Set Vref, RX VrefLevel [Byte0]: 59
4198 01:00:21.329321 [Byte1]: 56
4199 01:00:21.334126
4200 01:00:21.334193 Final RX Vref Byte 0 = 59 to rank0
4201 01:00:21.337378 Final RX Vref Byte 1 = 56 to rank0
4202 01:00:21.340505 Final RX Vref Byte 0 = 59 to rank1
4203 01:00:21.343719 Final RX Vref Byte 1 = 56 to rank1==
4204 01:00:21.347255 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 01:00:21.353753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 01:00:21.353824 ==
4207 01:00:21.353885 DQS Delay:
4208 01:00:21.357234 DQS0 = 0, DQS1 = 0
4209 01:00:21.357330 DQM Delay:
4210 01:00:21.357421 DQM0 = 34, DQM1 = 29
4211 01:00:21.360445 DQ Delay:
4212 01:00:21.363499 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4213 01:00:21.367042 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4214 01:00:21.370043 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4215 01:00:21.373958 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4216 01:00:21.374031
4217 01:00:21.374094
4218 01:00:21.379990 [DQSOSCAuto] RK0, (LSB)MR18= 0x403e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4219 01:00:21.383526 CH0 RK0: MR19=808, MR18=403E
4220 01:00:21.390266 CH0_RK0: MR19=0x808, MR18=0x403E, DQSOSC=397, MR23=63, INC=166, DEC=110
4221 01:00:21.390359
4222 01:00:21.393209 ----->DramcWriteLeveling(PI) begin...
4223 01:00:21.393288 ==
4224 01:00:21.396611 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 01:00:21.400053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 01:00:21.400131 ==
4227 01:00:21.403342 Write leveling (Byte 0): 30 => 30
4228 01:00:21.406624 Write leveling (Byte 1): 30 => 30
4229 01:00:21.409921 DramcWriteLeveling(PI) end<-----
4230 01:00:21.410004
4231 01:00:21.410086 ==
4232 01:00:21.413264 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 01:00:21.416528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 01:00:21.416605 ==
4235 01:00:21.419855 [Gating] SW mode calibration
4236 01:00:21.426636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 01:00:21.433041 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4238 01:00:21.436478 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 01:00:21.443374 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 01:00:21.446611 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 01:00:21.449820 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
4242 01:00:21.456463 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4243 01:00:21.459650 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 01:00:21.463256 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 01:00:21.469752 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 01:00:21.472969 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 01:00:21.476561 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 01:00:21.479717 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 01:00:21.486297 0 10 12 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
4250 01:00:21.489696 0 10 16 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
4251 01:00:21.496258 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 01:00:21.499530 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 01:00:21.502921 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 01:00:21.506106 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 01:00:21.512703 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 01:00:21.516217 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 01:00:21.519416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4258 01:00:21.525948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 01:00:21.529305 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 01:00:21.532849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 01:00:21.539499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 01:00:21.542613 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 01:00:21.545861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 01:00:21.552683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 01:00:21.555979 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 01:00:21.559299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 01:00:21.566104 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 01:00:21.569231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 01:00:21.572352 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 01:00:21.579223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 01:00:21.582377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 01:00:21.585962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 01:00:21.592379 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4274 01:00:21.592458 Total UI for P1: 0, mck2ui 16
4275 01:00:21.598830 best dqsien dly found for B0: ( 0, 13, 10)
4276 01:00:21.602170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 01:00:21.605282 Total UI for P1: 0, mck2ui 16
4278 01:00:21.608873 best dqsien dly found for B1: ( 0, 13, 12)
4279 01:00:21.611939 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4280 01:00:21.615506 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4281 01:00:21.615587
4282 01:00:21.618764 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4283 01:00:21.621895 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4284 01:00:21.625447 [Gating] SW calibration Done
4285 01:00:21.625571 ==
4286 01:00:21.628794 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 01:00:21.635415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 01:00:21.635493 ==
4289 01:00:21.635581 RX Vref Scan: 0
4290 01:00:21.635661
4291 01:00:21.638665 RX Vref 0 -> 0, step: 1
4292 01:00:21.638746
4293 01:00:21.642134 RX Delay -230 -> 252, step: 16
4294 01:00:21.645309 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4295 01:00:21.648680 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4296 01:00:21.651864 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4297 01:00:21.658455 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4298 01:00:21.662040 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4299 01:00:21.665377 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4300 01:00:21.668597 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4301 01:00:21.675029 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4302 01:00:21.678616 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4303 01:00:21.681878 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4304 01:00:21.685137 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4305 01:00:21.688536 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4306 01:00:21.695291 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4307 01:00:21.698438 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4308 01:00:21.701904 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4309 01:00:21.705111 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4310 01:00:21.708404 ==
4311 01:00:21.711556 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 01:00:21.715222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 01:00:21.715749 ==
4314 01:00:21.716118 DQS Delay:
4315 01:00:21.718383 DQS0 = 0, DQS1 = 0
4316 01:00:21.718769 DQM Delay:
4317 01:00:21.721786 DQM0 = 35, DQM1 = 29
4318 01:00:21.722386 DQ Delay:
4319 01:00:21.725156 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4320 01:00:21.728417 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4321 01:00:21.731698 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4322 01:00:21.735006 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4323 01:00:21.735430
4324 01:00:21.735763
4325 01:00:21.736077 ==
4326 01:00:21.738516 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 01:00:21.741696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 01:00:21.742126 ==
4329 01:00:21.742463
4330 01:00:21.742780
4331 01:00:21.744968 TX Vref Scan disable
4332 01:00:21.748590 == TX Byte 0 ==
4333 01:00:21.751504 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4334 01:00:21.755203 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4335 01:00:21.758144 == TX Byte 1 ==
4336 01:00:21.761451 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4337 01:00:21.764910 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4338 01:00:21.765471 ==
4339 01:00:21.768449 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 01:00:21.775060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 01:00:21.775535 ==
4342 01:00:21.775906
4343 01:00:21.776252
4344 01:00:21.776586 TX Vref Scan disable
4345 01:00:21.779351 == TX Byte 0 ==
4346 01:00:21.782328 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4347 01:00:21.785677 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4348 01:00:21.789053 == TX Byte 1 ==
4349 01:00:21.792296 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4350 01:00:21.799081 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4351 01:00:21.799631
4352 01:00:21.800002 [DATLAT]
4353 01:00:21.800360 Freq=600, CH0 RK1
4354 01:00:21.800703
4355 01:00:21.802362 DATLAT Default: 0x9
4356 01:00:21.802880 0, 0xFFFF, sum = 0
4357 01:00:21.805637 1, 0xFFFF, sum = 0
4358 01:00:21.806154 2, 0xFFFF, sum = 0
4359 01:00:21.808923 3, 0xFFFF, sum = 0
4360 01:00:21.812061 4, 0xFFFF, sum = 0
4361 01:00:21.812534 5, 0xFFFF, sum = 0
4362 01:00:21.815468 6, 0xFFFF, sum = 0
4363 01:00:21.815943 7, 0xFFFF, sum = 0
4364 01:00:21.818930 8, 0x0, sum = 1
4365 01:00:21.819402 9, 0x0, sum = 2
4366 01:00:21.819775 10, 0x0, sum = 3
4367 01:00:21.822262 11, 0x0, sum = 4
4368 01:00:21.822789 best_step = 9
4369 01:00:21.823130
4370 01:00:21.823444 ==
4371 01:00:21.825409 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 01:00:21.832000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 01:00:21.832356 ==
4374 01:00:21.832600 RX Vref Scan: 0
4375 01:00:21.832843
4376 01:00:21.835288 RX Vref 0 -> 0, step: 1
4377 01:00:21.835606
4378 01:00:21.838588 RX Delay -195 -> 252, step: 8
4379 01:00:21.841983 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4380 01:00:21.848653 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4381 01:00:21.852029 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4382 01:00:21.855334 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4383 01:00:21.858574 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4384 01:00:21.861842 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4385 01:00:21.868774 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4386 01:00:21.871756 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4387 01:00:21.875426 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4388 01:00:21.878555 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4389 01:00:21.885310 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4390 01:00:21.888675 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4391 01:00:21.891991 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4392 01:00:21.895579 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4393 01:00:21.901732 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4394 01:00:21.905439 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4395 01:00:21.905940 ==
4396 01:00:21.908729 Dram Type= 6, Freq= 0, CH_0, rank 1
4397 01:00:21.912100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 01:00:21.912545 ==
4399 01:00:21.915167 DQS Delay:
4400 01:00:21.915651 DQS0 = 0, DQS1 = 0
4401 01:00:21.916023 DQM Delay:
4402 01:00:21.918785 DQM0 = 34, DQM1 = 27
4403 01:00:21.919238 DQ Delay:
4404 01:00:21.921878 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4405 01:00:21.925228 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4406 01:00:21.928487 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4407 01:00:21.931725 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4408 01:00:21.932140
4409 01:00:21.932498
4410 01:00:21.941522 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
4411 01:00:21.944799 CH0 RK1: MR19=808, MR18=6B38
4412 01:00:21.947880 CH0_RK1: MR19=0x808, MR18=0x6B38, DQSOSC=389, MR23=63, INC=173, DEC=115
4413 01:00:21.951504 [RxdqsGatingPostProcess] freq 600
4414 01:00:21.958099 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4415 01:00:21.961246 Pre-setting of DQS Precalculation
4416 01:00:21.964573 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4417 01:00:21.965020 ==
4418 01:00:21.967981 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 01:00:21.974512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 01:00:21.974973 ==
4421 01:00:21.977733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 01:00:21.984632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4423 01:00:21.987893 [CA 0] Center 36 (6~66) winsize 61
4424 01:00:21.991231 [CA 1] Center 35 (5~66) winsize 62
4425 01:00:21.994588 [CA 2] Center 34 (4~65) winsize 62
4426 01:00:21.997863 [CA 3] Center 34 (4~65) winsize 62
4427 01:00:22.001242 [CA 4] Center 34 (4~65) winsize 62
4428 01:00:22.004478 [CA 5] Center 33 (3~64) winsize 62
4429 01:00:22.004905
4430 01:00:22.007750 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4431 01:00:22.008178
4432 01:00:22.010996 [CATrainingPosCal] consider 1 rank data
4433 01:00:22.014330 u2DelayCellTimex100 = 270/100 ps
4434 01:00:22.017594 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4435 01:00:22.024417 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 01:00:22.027778 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 01:00:22.030880 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 01:00:22.034204 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 01:00:22.037541 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 01:00:22.037970
4441 01:00:22.041150 CA PerBit enable=1, Macro0, CA PI delay=33
4442 01:00:22.041621
4443 01:00:22.044406 [CBTSetCACLKResult] CA Dly = 33
4444 01:00:22.044831 CS Dly: 5 (0~36)
4445 01:00:22.047758 ==
4446 01:00:22.050936 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 01:00:22.054101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 01:00:22.054529 ==
4449 01:00:22.060650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4450 01:00:22.064133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4451 01:00:22.068084 [CA 0] Center 36 (6~66) winsize 61
4452 01:00:22.071237 [CA 1] Center 36 (5~67) winsize 63
4453 01:00:22.074861 [CA 2] Center 34 (4~65) winsize 62
4454 01:00:22.078060 [CA 3] Center 34 (3~65) winsize 63
4455 01:00:22.081370 [CA 4] Center 34 (4~65) winsize 62
4456 01:00:22.084585 [CA 5] Center 33 (3~64) winsize 62
4457 01:00:22.085014
4458 01:00:22.088036 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4459 01:00:22.088460
4460 01:00:22.091311 [CATrainingPosCal] consider 2 rank data
4461 01:00:22.094824 u2DelayCellTimex100 = 270/100 ps
4462 01:00:22.098011 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4463 01:00:22.101466 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 01:00:22.108041 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 01:00:22.111043 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 01:00:22.114615 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4467 01:00:22.117869 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4468 01:00:22.118310
4469 01:00:22.121265 CA PerBit enable=1, Macro0, CA PI delay=33
4470 01:00:22.121767
4471 01:00:22.124406 [CBTSetCACLKResult] CA Dly = 33
4472 01:00:22.124853 CS Dly: 5 (0~36)
4473 01:00:22.127773
4474 01:00:22.131155 ----->DramcWriteLeveling(PI) begin...
4475 01:00:22.131587 ==
4476 01:00:22.134600 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 01:00:22.137821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 01:00:22.138251 ==
4479 01:00:22.140975 Write leveling (Byte 0): 29 => 29
4480 01:00:22.144330 Write leveling (Byte 1): 30 => 30
4481 01:00:22.147776 DramcWriteLeveling(PI) end<-----
4482 01:00:22.148204
4483 01:00:22.148542 ==
4484 01:00:22.150747 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 01:00:22.154341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 01:00:22.154771 ==
4487 01:00:22.157416 [Gating] SW mode calibration
4488 01:00:22.164022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4489 01:00:22.170679 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4490 01:00:22.173972 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 01:00:22.177100 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 01:00:22.184090 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 01:00:22.187165 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 1) (0 1)
4494 01:00:22.190790 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
4495 01:00:22.197057 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 01:00:22.200349 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 01:00:22.203555 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 01:00:22.210318 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 01:00:22.213568 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 01:00:22.217080 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 01:00:22.223570 0 10 12 | B1->B0 | 3232 3131 | 0 0 | (1 1) (0 0)
4502 01:00:22.227005 0 10 16 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
4503 01:00:22.230104 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 01:00:22.236672 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 01:00:22.239933 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 01:00:22.243517 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 01:00:22.250207 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 01:00:22.253163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 01:00:22.256392 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4510 01:00:22.263113 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4511 01:00:22.266424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 01:00:22.269819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 01:00:22.276536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 01:00:22.279851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 01:00:22.282979 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 01:00:22.289536 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 01:00:22.292826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 01:00:22.296109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 01:00:22.302956 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 01:00:22.306012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 01:00:22.309358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 01:00:22.316168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 01:00:22.319207 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 01:00:22.322750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 01:00:22.326024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4526 01:00:22.329299 Total UI for P1: 0, mck2ui 16
4527 01:00:22.332835 best dqsien dly found for B1: ( 0, 13, 10)
4528 01:00:22.339503 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 01:00:22.342687 Total UI for P1: 0, mck2ui 16
4530 01:00:22.346292 best dqsien dly found for B0: ( 0, 13, 12)
4531 01:00:22.349643 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4532 01:00:22.352839 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4533 01:00:22.353274
4534 01:00:22.356037 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4535 01:00:22.359374 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4536 01:00:22.362599 [Gating] SW calibration Done
4537 01:00:22.363117 ==
4538 01:00:22.366337 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 01:00:22.369368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 01:00:22.369849 ==
4541 01:00:22.372533 RX Vref Scan: 0
4542 01:00:22.372967
4543 01:00:22.375864 RX Vref 0 -> 0, step: 1
4544 01:00:22.376298
4545 01:00:22.376739 RX Delay -230 -> 252, step: 16
4546 01:00:22.382677 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4547 01:00:22.385991 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4548 01:00:22.389278 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4549 01:00:22.392505 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4550 01:00:22.398977 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4551 01:00:22.402448 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4552 01:00:22.405679 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4553 01:00:22.409138 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4554 01:00:22.412401 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4555 01:00:22.418860 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4556 01:00:22.422276 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4557 01:00:22.425590 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4558 01:00:22.428968 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4559 01:00:22.435488 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4560 01:00:22.438809 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4561 01:00:22.441911 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4562 01:00:22.442378 ==
4563 01:00:22.445557 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 01:00:22.452082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 01:00:22.452508 ==
4566 01:00:22.452844 DQS Delay:
4567 01:00:22.453246 DQS0 = 0, DQS1 = 0
4568 01:00:22.455039 DQM Delay:
4569 01:00:22.455456 DQM0 = 38, DQM1 = 28
4570 01:00:22.458645 DQ Delay:
4571 01:00:22.461819 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4572 01:00:22.465154 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4573 01:00:22.468451 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4574 01:00:22.471672 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4575 01:00:22.472093
4576 01:00:22.472424
4577 01:00:22.472732 ==
4578 01:00:22.475738 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 01:00:22.478487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 01:00:22.478912 ==
4581 01:00:22.479245
4582 01:00:22.479554
4583 01:00:22.482013 TX Vref Scan disable
4584 01:00:22.482434 == TX Byte 0 ==
4585 01:00:22.488486 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4586 01:00:22.491660 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4587 01:00:22.492083 == TX Byte 1 ==
4588 01:00:22.498203 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4589 01:00:22.501609 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4590 01:00:22.502076 ==
4591 01:00:22.504848 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 01:00:22.508122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 01:00:22.508779 ==
4594 01:00:22.511498
4595 01:00:22.511918
4596 01:00:22.512253 TX Vref Scan disable
4597 01:00:22.515080 == TX Byte 0 ==
4598 01:00:22.518435 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4599 01:00:22.524908 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4600 01:00:22.525331 == TX Byte 1 ==
4601 01:00:22.528229 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4602 01:00:22.534556 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4603 01:00:22.534979
4604 01:00:22.535312 [DATLAT]
4605 01:00:22.535622 Freq=600, CH1 RK0
4606 01:00:22.535924
4607 01:00:22.538079 DATLAT Default: 0x9
4608 01:00:22.538502 0, 0xFFFF, sum = 0
4609 01:00:22.541285 1, 0xFFFF, sum = 0
4610 01:00:22.544730 2, 0xFFFF, sum = 0
4611 01:00:22.545156 3, 0xFFFF, sum = 0
4612 01:00:22.547942 4, 0xFFFF, sum = 0
4613 01:00:22.548371 5, 0xFFFF, sum = 0
4614 01:00:22.551344 6, 0xFFFF, sum = 0
4615 01:00:22.551769 7, 0xFFFF, sum = 0
4616 01:00:22.554667 8, 0x0, sum = 1
4617 01:00:22.555093 9, 0x0, sum = 2
4618 01:00:22.555436 10, 0x0, sum = 3
4619 01:00:22.557762 11, 0x0, sum = 4
4620 01:00:22.558188 best_step = 9
4621 01:00:22.558521
4622 01:00:22.561369 ==
4623 01:00:22.561872 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 01:00:22.568053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 01:00:22.568478 ==
4626 01:00:22.568811 RX Vref Scan: 1
4627 01:00:22.569123
4628 01:00:22.571222 RX Vref 0 -> 0, step: 1
4629 01:00:22.571641
4630 01:00:22.574461 RX Delay -195 -> 252, step: 8
4631 01:00:22.574880
4632 01:00:22.577674 Set Vref, RX VrefLevel [Byte0]: 55
4633 01:00:22.581061 [Byte1]: 53
4634 01:00:22.581507
4635 01:00:22.584428 Final RX Vref Byte 0 = 55 to rank0
4636 01:00:22.587514 Final RX Vref Byte 1 = 53 to rank0
4637 01:00:22.591171 Final RX Vref Byte 0 = 55 to rank1
4638 01:00:22.594439 Final RX Vref Byte 1 = 53 to rank1==
4639 01:00:22.597557 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 01:00:22.600911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 01:00:22.604070 ==
4642 01:00:22.604489 DQS Delay:
4643 01:00:22.604824 DQS0 = 0, DQS1 = 0
4644 01:00:22.607647 DQM Delay:
4645 01:00:22.608067 DQM0 = 38, DQM1 = 28
4646 01:00:22.610782 DQ Delay:
4647 01:00:22.611265 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =32
4648 01:00:22.613889 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4649 01:00:22.617415 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4650 01:00:22.620563 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4651 01:00:22.620966
4652 01:00:22.623832
4653 01:00:22.630847 [DQSOSCAuto] RK0, (LSB)MR18= 0x2734, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4654 01:00:22.634157 CH1 RK0: MR19=808, MR18=2734
4655 01:00:22.640376 CH1_RK0: MR19=0x808, MR18=0x2734, DQSOSC=400, MR23=63, INC=163, DEC=109
4656 01:00:22.640989
4657 01:00:22.643951 ----->DramcWriteLeveling(PI) begin...
4658 01:00:22.644467 ==
4659 01:00:22.647301 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 01:00:22.650484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 01:00:22.650986 ==
4662 01:00:22.653869 Write leveling (Byte 0): 30 => 30
4663 01:00:22.657306 Write leveling (Byte 1): 30 => 30
4664 01:00:22.660335 DramcWriteLeveling(PI) end<-----
4665 01:00:22.660816
4666 01:00:22.661232 ==
4667 01:00:22.663697 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 01:00:22.666909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 01:00:22.667421 ==
4670 01:00:22.670422 [Gating] SW mode calibration
4671 01:00:22.677308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4672 01:00:22.683751 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4673 01:00:22.686925 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 01:00:22.690129 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 01:00:22.697037 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4676 01:00:22.700092 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4677 01:00:22.703315 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
4678 01:00:22.709943 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 01:00:22.713303 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 01:00:22.716659 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 01:00:22.723204 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 01:00:22.726498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 01:00:22.730040 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4684 01:00:22.736693 0 10 12 | B1->B0 | 3131 4343 | 0 0 | (1 1) (0 0)
4685 01:00:22.739851 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 01:00:22.743060 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 01:00:22.750056 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 01:00:22.753292 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 01:00:22.756552 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 01:00:22.763226 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 01:00:22.766597 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 01:00:22.769760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4693 01:00:22.776113 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 01:00:22.779465 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 01:00:22.782894 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 01:00:22.789429 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 01:00:22.792636 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 01:00:22.795910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 01:00:22.802765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 01:00:22.805913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 01:00:22.809042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 01:00:22.815966 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 01:00:22.819159 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 01:00:22.822744 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 01:00:22.829246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 01:00:22.832455 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 01:00:22.835578 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 01:00:22.842384 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4709 01:00:22.845701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 01:00:22.848977 Total UI for P1: 0, mck2ui 16
4711 01:00:22.852450 best dqsien dly found for B0: ( 0, 13, 12)
4712 01:00:22.855718 Total UI for P1: 0, mck2ui 16
4713 01:00:22.858869 best dqsien dly found for B1: ( 0, 13, 14)
4714 01:00:22.862512 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4715 01:00:22.865846 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4716 01:00:22.866345
4717 01:00:22.868790 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4718 01:00:22.872167 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4719 01:00:22.875728 [Gating] SW calibration Done
4720 01:00:22.876201 ==
4721 01:00:22.878663 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 01:00:22.881992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 01:00:22.885570 ==
4724 01:00:22.886040 RX Vref Scan: 0
4725 01:00:22.886416
4726 01:00:22.888834 RX Vref 0 -> 0, step: 1
4727 01:00:22.889320
4728 01:00:22.892103 RX Delay -230 -> 252, step: 16
4729 01:00:22.895200 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4730 01:00:22.898582 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4731 01:00:22.901997 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4732 01:00:22.908428 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4733 01:00:22.912061 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4734 01:00:22.915077 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4735 01:00:22.918702 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4736 01:00:22.921838 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4737 01:00:22.928621 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4738 01:00:22.931621 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4739 01:00:22.935374 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4740 01:00:22.938463 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4741 01:00:22.945106 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4742 01:00:22.948331 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4743 01:00:22.951746 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4744 01:00:22.954903 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4745 01:00:22.955339 ==
4746 01:00:22.958294 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 01:00:22.964909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 01:00:22.965332 ==
4749 01:00:22.965712 DQS Delay:
4750 01:00:22.968283 DQS0 = 0, DQS1 = 0
4751 01:00:22.968704 DQM Delay:
4752 01:00:22.971698 DQM0 = 35, DQM1 = 29
4753 01:00:22.972116 DQ Delay:
4754 01:00:22.975238 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4755 01:00:22.978007 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4756 01:00:22.981601 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4757 01:00:22.984659 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4758 01:00:22.985081
4759 01:00:22.985412
4760 01:00:22.985820 ==
4761 01:00:22.988480 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 01:00:22.991499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 01:00:22.991924 ==
4764 01:00:22.992257
4765 01:00:22.992565
4766 01:00:22.994810 TX Vref Scan disable
4767 01:00:22.998339 == TX Byte 0 ==
4768 01:00:23.001557 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 01:00:23.004972 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 01:00:23.008205 == TX Byte 1 ==
4771 01:00:23.011448 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4772 01:00:23.014957 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4773 01:00:23.015415 ==
4774 01:00:23.018238 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 01:00:23.021505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 01:00:23.021953 ==
4777 01:00:23.022286
4778 01:00:23.024843
4779 01:00:23.025284 TX Vref Scan disable
4780 01:00:23.028293 == TX Byte 0 ==
4781 01:00:23.031648 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4782 01:00:23.038167 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4783 01:00:23.038616 == TX Byte 1 ==
4784 01:00:23.041429 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4785 01:00:23.048034 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4786 01:00:23.048494
4787 01:00:23.048859 [DATLAT]
4788 01:00:23.049195 Freq=600, CH1 RK1
4789 01:00:23.049582
4790 01:00:23.051407 DATLAT Default: 0x9
4791 01:00:23.054757 0, 0xFFFF, sum = 0
4792 01:00:23.055208 1, 0xFFFF, sum = 0
4793 01:00:23.057954 2, 0xFFFF, sum = 0
4794 01:00:23.058418 3, 0xFFFF, sum = 0
4795 01:00:23.061430 4, 0xFFFF, sum = 0
4796 01:00:23.062108 5, 0xFFFF, sum = 0
4797 01:00:23.064611 6, 0xFFFF, sum = 0
4798 01:00:23.065074 7, 0xFFFF, sum = 0
4799 01:00:23.068013 8, 0x0, sum = 1
4800 01:00:23.068476 9, 0x0, sum = 2
4801 01:00:23.068847 10, 0x0, sum = 3
4802 01:00:23.071221 11, 0x0, sum = 4
4803 01:00:23.071687 best_step = 9
4804 01:00:23.072053
4805 01:00:23.074633 ==
4806 01:00:23.075091 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 01:00:23.081365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 01:00:23.081857 ==
4809 01:00:23.082224 RX Vref Scan: 0
4810 01:00:23.082565
4811 01:00:23.084603 RX Vref 0 -> 0, step: 1
4812 01:00:23.085198
4813 01:00:23.088002 RX Delay -195 -> 252, step: 8
4814 01:00:23.091121 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4815 01:00:23.097941 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4816 01:00:23.101336 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4817 01:00:23.104715 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4818 01:00:23.107848 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4819 01:00:23.114453 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4820 01:00:23.117603 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4821 01:00:23.121047 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4822 01:00:23.124421 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4823 01:00:23.130825 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4824 01:00:23.134082 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4825 01:00:23.137438 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4826 01:00:23.140806 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4827 01:00:23.147168 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4828 01:00:23.150416 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4829 01:00:23.153858 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4830 01:00:23.154446 ==
4831 01:00:23.157215 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 01:00:23.160465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 01:00:23.163799 ==
4834 01:00:23.164356 DQS Delay:
4835 01:00:23.164721 DQS0 = 0, DQS1 = 0
4836 01:00:23.166968 DQM Delay:
4837 01:00:23.167386 DQM0 = 36, DQM1 = 29
4838 01:00:23.170351 DQ Delay:
4839 01:00:23.170769 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4840 01:00:23.173536 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4841 01:00:23.177045 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4842 01:00:23.180360 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4843 01:00:23.180784
4844 01:00:23.183757
4845 01:00:23.190237 [DQSOSCAuto] RK1, (LSB)MR18= 0x3354, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4846 01:00:23.193664 CH1 RK1: MR19=808, MR18=3354
4847 01:00:23.200127 CH1_RK1: MR19=0x808, MR18=0x3354, DQSOSC=393, MR23=63, INC=169, DEC=113
4848 01:00:23.203358 [RxdqsGatingPostProcess] freq 600
4849 01:00:23.206660 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4850 01:00:23.210281 Pre-setting of DQS Precalculation
4851 01:00:23.216812 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4852 01:00:23.223536 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4853 01:00:23.230116 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4854 01:00:23.230582
4855 01:00:23.230946
4856 01:00:23.233803 [Calibration Summary] 1200 Mbps
4857 01:00:23.234255 CH 0, Rank 0
4858 01:00:23.236870 SW Impedance : PASS
4859 01:00:23.237331 DUTY Scan : NO K
4860 01:00:23.240182 ZQ Calibration : PASS
4861 01:00:23.243542 Jitter Meter : NO K
4862 01:00:23.244048 CBT Training : PASS
4863 01:00:23.246699 Write leveling : PASS
4864 01:00:23.249962 RX DQS gating : PASS
4865 01:00:23.250453 RX DQ/DQS(RDDQC) : PASS
4866 01:00:23.253126 TX DQ/DQS : PASS
4867 01:00:23.256541 RX DATLAT : PASS
4868 01:00:23.257018 RX DQ/DQS(Engine): PASS
4869 01:00:23.259923 TX OE : NO K
4870 01:00:23.260416 All Pass.
4871 01:00:23.260847
4872 01:00:23.263260 CH 0, Rank 1
4873 01:00:23.263764 SW Impedance : PASS
4874 01:00:23.266530 DUTY Scan : NO K
4875 01:00:23.269702 ZQ Calibration : PASS
4876 01:00:23.270154 Jitter Meter : NO K
4877 01:00:23.273148 CBT Training : PASS
4878 01:00:23.276605 Write leveling : PASS
4879 01:00:23.277020 RX DQS gating : PASS
4880 01:00:23.279767 RX DQ/DQS(RDDQC) : PASS
4881 01:00:23.282896 TX DQ/DQS : PASS
4882 01:00:23.283288 RX DATLAT : PASS
4883 01:00:23.286347 RX DQ/DQS(Engine): PASS
4884 01:00:23.289693 TX OE : NO K
4885 01:00:23.290120 All Pass.
4886 01:00:23.290466
4887 01:00:23.290767 CH 1, Rank 0
4888 01:00:23.293132 SW Impedance : PASS
4889 01:00:23.293659 DUTY Scan : NO K
4890 01:00:23.296585 ZQ Calibration : PASS
4891 01:00:23.299585 Jitter Meter : NO K
4892 01:00:23.300031 CBT Training : PASS
4893 01:00:23.303089 Write leveling : PASS
4894 01:00:23.306289 RX DQS gating : PASS
4895 01:00:23.306747 RX DQ/DQS(RDDQC) : PASS
4896 01:00:23.309877 TX DQ/DQS : PASS
4897 01:00:23.313204 RX DATLAT : PASS
4898 01:00:23.313769 RX DQ/DQS(Engine): PASS
4899 01:00:23.316323 TX OE : NO K
4900 01:00:23.316775 All Pass.
4901 01:00:23.317136
4902 01:00:23.319814 CH 1, Rank 1
4903 01:00:23.320278 SW Impedance : PASS
4904 01:00:23.323077 DUTY Scan : NO K
4905 01:00:23.326465 ZQ Calibration : PASS
4906 01:00:23.326925 Jitter Meter : NO K
4907 01:00:23.329807 CBT Training : PASS
4908 01:00:23.332904 Write leveling : PASS
4909 01:00:23.333354 RX DQS gating : PASS
4910 01:00:23.336281 RX DQ/DQS(RDDQC) : PASS
4911 01:00:23.339557 TX DQ/DQS : PASS
4912 01:00:23.340014 RX DATLAT : PASS
4913 01:00:23.342713 RX DQ/DQS(Engine): PASS
4914 01:00:23.343159 TX OE : NO K
4915 01:00:23.346076 All Pass.
4916 01:00:23.346523
4917 01:00:23.346856 DramC Write-DBI off
4918 01:00:23.349439 PER_BANK_REFRESH: Hybrid Mode
4919 01:00:23.352965 TX_TRACKING: ON
4920 01:00:23.359470 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4921 01:00:23.362720 [FAST_K] Save calibration result to emmc
4922 01:00:23.369333 dramc_set_vcore_voltage set vcore to 662500
4923 01:00:23.369783 Read voltage for 933, 3
4924 01:00:23.370154 Vio18 = 0
4925 01:00:23.372758 Vcore = 662500
4926 01:00:23.373200 Vdram = 0
4927 01:00:23.373597 Vddq = 0
4928 01:00:23.376144 Vmddr = 0
4929 01:00:23.379319 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4930 01:00:23.385823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4931 01:00:23.386271 MEM_TYPE=3, freq_sel=17
4932 01:00:23.389141 sv_algorithm_assistance_LP4_1600
4933 01:00:23.396010 ============ PULL DRAM RESETB DOWN ============
4934 01:00:23.399149 ========== PULL DRAM RESETB DOWN end =========
4935 01:00:23.402374 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4936 01:00:23.405720 ===================================
4937 01:00:23.409280 LPDDR4 DRAM CONFIGURATION
4938 01:00:23.412476 ===================================
4939 01:00:23.415873 EX_ROW_EN[0] = 0x0
4940 01:00:23.416296 EX_ROW_EN[1] = 0x0
4941 01:00:23.419058 LP4Y_EN = 0x0
4942 01:00:23.419481 WORK_FSP = 0x0
4943 01:00:23.422255 WL = 0x3
4944 01:00:23.422677 RL = 0x3
4945 01:00:23.425835 BL = 0x2
4946 01:00:23.426256 RPST = 0x0
4947 01:00:23.429119 RD_PRE = 0x0
4948 01:00:23.429585 WR_PRE = 0x1
4949 01:00:23.432513 WR_PST = 0x0
4950 01:00:23.432932 DBI_WR = 0x0
4951 01:00:23.435589 DBI_RD = 0x0
4952 01:00:23.436009 OTF = 0x1
4953 01:00:23.439148 ===================================
4954 01:00:23.442295 ===================================
4955 01:00:23.445702 ANA top config
4956 01:00:23.449017 ===================================
4957 01:00:23.452259 DLL_ASYNC_EN = 0
4958 01:00:23.452681 ALL_SLAVE_EN = 1
4959 01:00:23.455550 NEW_RANK_MODE = 1
4960 01:00:23.458852 DLL_IDLE_MODE = 1
4961 01:00:23.462102 LP45_APHY_COMB_EN = 1
4962 01:00:23.462526 TX_ODT_DIS = 1
4963 01:00:23.465754 NEW_8X_MODE = 1
4964 01:00:23.468855 ===================================
4965 01:00:23.472197 ===================================
4966 01:00:23.475704 data_rate = 1866
4967 01:00:23.478897 CKR = 1
4968 01:00:23.481931 DQ_P2S_RATIO = 8
4969 01:00:23.485459 ===================================
4970 01:00:23.488829 CA_P2S_RATIO = 8
4971 01:00:23.489359 DQ_CA_OPEN = 0
4972 01:00:23.492005 DQ_SEMI_OPEN = 0
4973 01:00:23.495493 CA_SEMI_OPEN = 0
4974 01:00:23.498671 CA_FULL_RATE = 0
4975 01:00:23.501962 DQ_CKDIV4_EN = 1
4976 01:00:23.505148 CA_CKDIV4_EN = 1
4977 01:00:23.505634 CA_PREDIV_EN = 0
4978 01:00:23.508516 PH8_DLY = 0
4979 01:00:23.511705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4980 01:00:23.515254 DQ_AAMCK_DIV = 4
4981 01:00:23.518589 CA_AAMCK_DIV = 4
4982 01:00:23.521704 CA_ADMCK_DIV = 4
4983 01:00:23.522162 DQ_TRACK_CA_EN = 0
4984 01:00:23.525203 CA_PICK = 933
4985 01:00:23.528408 CA_MCKIO = 933
4986 01:00:23.531590 MCKIO_SEMI = 0
4987 01:00:23.534933 PLL_FREQ = 3732
4988 01:00:23.538383 DQ_UI_PI_RATIO = 32
4989 01:00:23.541637 CA_UI_PI_RATIO = 0
4990 01:00:23.544965 ===================================
4991 01:00:23.548288 ===================================
4992 01:00:23.548742 memory_type:LPDDR4
4993 01:00:23.551450 GP_NUM : 10
4994 01:00:23.554781 SRAM_EN : 1
4995 01:00:23.555237 MD32_EN : 0
4996 01:00:23.558000 ===================================
4997 01:00:23.561250 [ANA_INIT] >>>>>>>>>>>>>>
4998 01:00:23.564911 <<<<<< [CONFIGURE PHASE]: ANA_TX
4999 01:00:23.568136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5000 01:00:23.571360 ===================================
5001 01:00:23.574674 data_rate = 1866,PCW = 0X8f00
5002 01:00:23.577832 ===================================
5003 01:00:23.581182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5004 01:00:23.584714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 01:00:23.591227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 01:00:23.594283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5007 01:00:23.597719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5008 01:00:23.604443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5009 01:00:23.604866 [ANA_INIT] flow start
5010 01:00:23.607636 [ANA_INIT] PLL >>>>>>>>
5011 01:00:23.608056 [ANA_INIT] PLL <<<<<<<<
5012 01:00:23.611158 [ANA_INIT] MIDPI >>>>>>>>
5013 01:00:23.614253 [ANA_INIT] MIDPI <<<<<<<<
5014 01:00:23.617536 [ANA_INIT] DLL >>>>>>>>
5015 01:00:23.617956 [ANA_INIT] flow end
5016 01:00:23.621210 ============ LP4 DIFF to SE enter ============
5017 01:00:23.627595 ============ LP4 DIFF to SE exit ============
5018 01:00:23.628019 [ANA_INIT] <<<<<<<<<<<<<
5019 01:00:23.630915 [Flow] Enable top DCM control >>>>>
5020 01:00:23.634181 [Flow] Enable top DCM control <<<<<
5021 01:00:23.637415 Enable DLL master slave shuffle
5022 01:00:23.644092 ==============================================================
5023 01:00:23.644553 Gating Mode config
5024 01:00:23.650952 ==============================================================
5025 01:00:23.653988 Config description:
5026 01:00:23.664366 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5027 01:00:23.670941 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5028 01:00:23.674307 SELPH_MODE 0: By rank 1: By Phase
5029 01:00:23.680789 ==============================================================
5030 01:00:23.684491 GAT_TRACK_EN = 1
5031 01:00:23.684932 RX_GATING_MODE = 2
5032 01:00:23.687455 RX_GATING_TRACK_MODE = 2
5033 01:00:23.691077 SELPH_MODE = 1
5034 01:00:23.694039 PICG_EARLY_EN = 1
5035 01:00:23.697456 VALID_LAT_VALUE = 1
5036 01:00:23.704202 ==============================================================
5037 01:00:23.707560 Enter into Gating configuration >>>>
5038 01:00:23.710870 Exit from Gating configuration <<<<
5039 01:00:23.713985 Enter into DVFS_PRE_config >>>>>
5040 01:00:23.723993 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5041 01:00:23.727496 Exit from DVFS_PRE_config <<<<<
5042 01:00:23.730620 Enter into PICG configuration >>>>
5043 01:00:23.734040 Exit from PICG configuration <<<<
5044 01:00:23.737472 [RX_INPUT] configuration >>>>>
5045 01:00:23.740675 [RX_INPUT] configuration <<<<<
5046 01:00:23.744015 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5047 01:00:23.750640 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5048 01:00:23.757238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5049 01:00:23.764029 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5050 01:00:23.767282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 01:00:23.773870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 01:00:23.776964 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5053 01:00:23.783765 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5054 01:00:23.787137 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5055 01:00:23.790422 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5056 01:00:23.793715 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5057 01:00:23.800282 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 01:00:23.803452 ===================================
5059 01:00:23.806577 LPDDR4 DRAM CONFIGURATION
5060 01:00:23.809882 ===================================
5061 01:00:23.810307 EX_ROW_EN[0] = 0x0
5062 01:00:23.813183 EX_ROW_EN[1] = 0x0
5063 01:00:23.813729 LP4Y_EN = 0x0
5064 01:00:23.816740 WORK_FSP = 0x0
5065 01:00:23.817194 WL = 0x3
5066 01:00:23.819965 RL = 0x3
5067 01:00:23.820412 BL = 0x2
5068 01:00:23.823211 RPST = 0x0
5069 01:00:23.823655 RD_PRE = 0x0
5070 01:00:23.826535 WR_PRE = 0x1
5071 01:00:23.826978 WR_PST = 0x0
5072 01:00:23.829608 DBI_WR = 0x0
5073 01:00:23.830089 DBI_RD = 0x0
5074 01:00:23.833013 OTF = 0x1
5075 01:00:23.836201 ===================================
5076 01:00:23.839651 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5077 01:00:23.842829 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5078 01:00:23.849667 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 01:00:23.852875 ===================================
5080 01:00:23.856065 LPDDR4 DRAM CONFIGURATION
5081 01:00:23.859214 ===================================
5082 01:00:23.859636 EX_ROW_EN[0] = 0x10
5083 01:00:23.862876 EX_ROW_EN[1] = 0x0
5084 01:00:23.863327 LP4Y_EN = 0x0
5085 01:00:23.865991 WORK_FSP = 0x0
5086 01:00:23.866414 WL = 0x3
5087 01:00:23.869570 RL = 0x3
5088 01:00:23.870024 BL = 0x2
5089 01:00:23.872843 RPST = 0x0
5090 01:00:23.873258 RD_PRE = 0x0
5091 01:00:23.876174 WR_PRE = 0x1
5092 01:00:23.876565 WR_PST = 0x0
5093 01:00:23.879066 DBI_WR = 0x0
5094 01:00:23.879512 DBI_RD = 0x0
5095 01:00:23.882778 OTF = 0x1
5096 01:00:23.885916 ===================================
5097 01:00:23.892649 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5098 01:00:23.895777 nWR fixed to 30
5099 01:00:23.899195 [ModeRegInit_LP4] CH0 RK0
5100 01:00:23.899616 [ModeRegInit_LP4] CH0 RK1
5101 01:00:23.902307 [ModeRegInit_LP4] CH1 RK0
5102 01:00:23.905652 [ModeRegInit_LP4] CH1 RK1
5103 01:00:23.906072 match AC timing 9
5104 01:00:23.912566 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5105 01:00:23.915604 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5106 01:00:23.919011 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5107 01:00:23.925829 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5108 01:00:23.928985 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5109 01:00:23.929406 ==
5110 01:00:23.932222 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 01:00:23.935521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 01:00:23.935943 ==
5113 01:00:23.942685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 01:00:23.949072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5115 01:00:23.952229 [CA 0] Center 38 (8~69) winsize 62
5116 01:00:23.955788 [CA 1] Center 38 (7~69) winsize 63
5117 01:00:23.958954 [CA 2] Center 35 (5~66) winsize 62
5118 01:00:23.962464 [CA 3] Center 35 (4~66) winsize 63
5119 01:00:23.965748 [CA 4] Center 34 (4~65) winsize 62
5120 01:00:23.969057 [CA 5] Center 33 (3~64) winsize 62
5121 01:00:23.969545
5122 01:00:23.972255 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5123 01:00:23.972676
5124 01:00:23.975480 [CATrainingPosCal] consider 1 rank data
5125 01:00:23.978791 u2DelayCellTimex100 = 270/100 ps
5126 01:00:23.981968 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5127 01:00:23.985333 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5128 01:00:23.988802 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5129 01:00:23.992049 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5130 01:00:23.995221 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5131 01:00:24.001925 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5132 01:00:24.002347
5133 01:00:24.005125 CA PerBit enable=1, Macro0, CA PI delay=33
5134 01:00:24.005600
5135 01:00:24.008503 [CBTSetCACLKResult] CA Dly = 33
5136 01:00:24.008927 CS Dly: 6 (0~37)
5137 01:00:24.009262 ==
5138 01:00:24.011894 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 01:00:24.015209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 01:00:24.018438 ==
5141 01:00:24.021790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5142 01:00:24.028428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5143 01:00:24.031825 [CA 0] Center 38 (8~69) winsize 62
5144 01:00:24.035374 [CA 1] Center 38 (8~69) winsize 62
5145 01:00:24.038597 [CA 2] Center 35 (5~66) winsize 62
5146 01:00:24.041894 [CA 3] Center 35 (4~66) winsize 63
5147 01:00:24.045263 [CA 4] Center 34 (3~65) winsize 63
5148 01:00:24.048689 [CA 5] Center 33 (3~64) winsize 62
5149 01:00:24.049108
5150 01:00:24.051856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5151 01:00:24.052278
5152 01:00:24.055202 [CATrainingPosCal] consider 2 rank data
5153 01:00:24.058548 u2DelayCellTimex100 = 270/100 ps
5154 01:00:24.061612 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5155 01:00:24.065074 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5156 01:00:24.068229 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5157 01:00:24.074975 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5158 01:00:24.078161 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5159 01:00:24.081657 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5160 01:00:24.082208
5161 01:00:24.084907 CA PerBit enable=1, Macro0, CA PI delay=33
5162 01:00:24.085326
5163 01:00:24.088152 [CBTSetCACLKResult] CA Dly = 33
5164 01:00:24.088574 CS Dly: 7 (0~39)
5165 01:00:24.088907
5166 01:00:24.091805 ----->DramcWriteLeveling(PI) begin...
5167 01:00:24.092232 ==
5168 01:00:24.094737 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 01:00:24.101674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 01:00:24.102102 ==
5171 01:00:24.104995 Write leveling (Byte 0): 32 => 32
5172 01:00:24.108178 Write leveling (Byte 1): 27 => 27
5173 01:00:24.108597 DramcWriteLeveling(PI) end<-----
5174 01:00:24.108932
5175 01:00:24.111756 ==
5176 01:00:24.114892 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 01:00:24.118237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 01:00:24.118661 ==
5179 01:00:24.121576 [Gating] SW mode calibration
5180 01:00:24.128359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5181 01:00:24.131617 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5182 01:00:24.138022 0 14 0 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (1 1)
5183 01:00:24.141389 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 01:00:24.144635 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 01:00:24.151387 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 01:00:24.154586 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 01:00:24.157938 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 01:00:24.164601 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 01:00:24.167816 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5190 01:00:24.171192 0 15 0 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
5191 01:00:24.177798 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5192 01:00:24.180937 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 01:00:24.184288 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 01:00:24.191057 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 01:00:24.194296 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 01:00:24.197700 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 01:00:24.204299 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5198 01:00:24.207473 1 0 0 | B1->B0 | 2828 3b3b | 1 0 | (0 0) (0 0)
5199 01:00:24.211158 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5200 01:00:24.217646 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 01:00:24.220977 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 01:00:24.224296 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 01:00:24.230863 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 01:00:24.234030 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 01:00:24.237306 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5206 01:00:24.244115 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5207 01:00:24.247295 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 01:00:24.250444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5209 01:00:24.257138 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 01:00:24.260363 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 01:00:24.264095 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 01:00:24.270549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 01:00:24.273786 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 01:00:24.277046 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 01:00:24.280359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 01:00:24.287257 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 01:00:24.290473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 01:00:24.293634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 01:00:24.300204 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 01:00:24.303812 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 01:00:24.307014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5222 01:00:24.313584 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5223 01:00:24.316940 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 01:00:24.320176 Total UI for P1: 0, mck2ui 16
5225 01:00:24.323389 best dqsien dly found for B0: ( 1, 2, 30)
5226 01:00:24.327025 Total UI for P1: 0, mck2ui 16
5227 01:00:24.330366 best dqsien dly found for B1: ( 1, 3, 2)
5228 01:00:24.333630 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5229 01:00:24.336885 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5230 01:00:24.337311
5231 01:00:24.340118 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5232 01:00:24.343331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5233 01:00:24.346582 [Gating] SW calibration Done
5234 01:00:24.347007 ==
5235 01:00:24.349991 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 01:00:24.356634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 01:00:24.357063 ==
5238 01:00:24.357524 RX Vref Scan: 0
5239 01:00:24.357963
5240 01:00:24.359850 RX Vref 0 -> 0, step: 1
5241 01:00:24.360278
5242 01:00:24.363204 RX Delay -80 -> 252, step: 8
5243 01:00:24.366363 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5244 01:00:24.369619 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5245 01:00:24.373329 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5246 01:00:24.376438 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5247 01:00:24.383000 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5248 01:00:24.386231 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5249 01:00:24.389610 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5250 01:00:24.392866 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5251 01:00:24.396045 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5252 01:00:24.399565 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5253 01:00:24.406103 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5254 01:00:24.409736 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5255 01:00:24.412838 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5256 01:00:24.416052 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5257 01:00:24.422598 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5258 01:00:24.425954 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5259 01:00:24.426379 ==
5260 01:00:24.429409 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 01:00:24.432708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 01:00:24.433164 ==
5263 01:00:24.433679 DQS Delay:
5264 01:00:24.435821 DQS0 = 0, DQS1 = 0
5265 01:00:24.436246 DQM Delay:
5266 01:00:24.439157 DQM0 = 94, DQM1 = 83
5267 01:00:24.439581 DQ Delay:
5268 01:00:24.442659 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5269 01:00:24.445942 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5270 01:00:24.449326 DQ8 =79, DQ9 =67, DQ10 =83, DQ11 =79
5271 01:00:24.452646 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5272 01:00:24.453075
5273 01:00:24.453411
5274 01:00:24.453776 ==
5275 01:00:24.455976 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 01:00:24.459196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 01:00:24.462545 ==
5278 01:00:24.463016
5279 01:00:24.463366
5280 01:00:24.463683 TX Vref Scan disable
5281 01:00:24.465711 == TX Byte 0 ==
5282 01:00:24.469265 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5283 01:00:24.472320 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5284 01:00:24.475949 == TX Byte 1 ==
5285 01:00:24.479120 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5286 01:00:24.482397 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5287 01:00:24.485697 ==
5288 01:00:24.489263 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 01:00:24.492504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 01:00:24.492960 ==
5291 01:00:24.493321
5292 01:00:24.493684
5293 01:00:24.495860 TX Vref Scan disable
5294 01:00:24.496314 == TX Byte 0 ==
5295 01:00:24.502474 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5296 01:00:24.505839 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5297 01:00:24.506300 == TX Byte 1 ==
5298 01:00:24.512425 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5299 01:00:24.515608 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5300 01:00:24.516067
5301 01:00:24.516425 [DATLAT]
5302 01:00:24.518990 Freq=933, CH0 RK0
5303 01:00:24.519445
5304 01:00:24.519806 DATLAT Default: 0xd
5305 01:00:24.522435 0, 0xFFFF, sum = 0
5306 01:00:24.522900 1, 0xFFFF, sum = 0
5307 01:00:24.525461 2, 0xFFFF, sum = 0
5308 01:00:24.525963 3, 0xFFFF, sum = 0
5309 01:00:24.528671 4, 0xFFFF, sum = 0
5310 01:00:24.532320 5, 0xFFFF, sum = 0
5311 01:00:24.532777 6, 0xFFFF, sum = 0
5312 01:00:24.535315 7, 0xFFFF, sum = 0
5313 01:00:24.535802 8, 0xFFFF, sum = 0
5314 01:00:24.538604 9, 0xFFFF, sum = 0
5315 01:00:24.539063 10, 0x0, sum = 1
5316 01:00:24.541960 11, 0x0, sum = 2
5317 01:00:24.542415 12, 0x0, sum = 3
5318 01:00:24.542757 13, 0x0, sum = 4
5319 01:00:24.545311 best_step = 11
5320 01:00:24.545936
5321 01:00:24.546301 ==
5322 01:00:24.548626 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 01:00:24.551863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 01:00:24.552314 ==
5325 01:00:24.555306 RX Vref Scan: 1
5326 01:00:24.555811
5327 01:00:24.558574 RX Vref 0 -> 0, step: 1
5328 01:00:24.559026
5329 01:00:24.559361 RX Delay -77 -> 252, step: 4
5330 01:00:24.559727
5331 01:00:24.561719 Set Vref, RX VrefLevel [Byte0]: 59
5332 01:00:24.565342 [Byte1]: 56
5333 01:00:24.569835
5334 01:00:24.570261 Final RX Vref Byte 0 = 59 to rank0
5335 01:00:24.572997 Final RX Vref Byte 1 = 56 to rank0
5336 01:00:24.576305 Final RX Vref Byte 0 = 59 to rank1
5337 01:00:24.579756 Final RX Vref Byte 1 = 56 to rank1==
5338 01:00:24.583106 Dram Type= 6, Freq= 0, CH_0, rank 0
5339 01:00:24.589535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 01:00:24.589965 ==
5341 01:00:24.590303 DQS Delay:
5342 01:00:24.592975 DQS0 = 0, DQS1 = 0
5343 01:00:24.593433 DQM Delay:
5344 01:00:24.593848 DQM0 = 95, DQM1 = 84
5345 01:00:24.596183 DQ Delay:
5346 01:00:24.599481 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5347 01:00:24.602830 DQ4 =96, DQ5 =86, DQ6 =102, DQ7 =106
5348 01:00:24.605959 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
5349 01:00:24.609410 DQ12 =88, DQ13 =90, DQ14 =94, DQ15 =90
5350 01:00:24.609875
5351 01:00:24.610212
5352 01:00:24.616048 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5353 01:00:24.619325 CH0 RK0: MR19=505, MR18=1515
5354 01:00:24.626058 CH0_RK0: MR19=0x505, MR18=0x1515, DQSOSC=415, MR23=63, INC=62, DEC=41
5355 01:00:24.626498
5356 01:00:24.628854 ----->DramcWriteLeveling(PI) begin...
5357 01:00:24.629296 ==
5358 01:00:24.632395 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 01:00:24.635718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 01:00:24.636145 ==
5361 01:00:24.638994 Write leveling (Byte 0): 33 => 33
5362 01:00:24.642320 Write leveling (Byte 1): 29 => 29
5363 01:00:24.645607 DramcWriteLeveling(PI) end<-----
5364 01:00:24.646029
5365 01:00:24.646361 ==
5366 01:00:24.648916 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 01:00:24.652101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 01:00:24.655168 ==
5369 01:00:24.655395 [Gating] SW mode calibration
5370 01:00:24.665063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5371 01:00:24.668402 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5372 01:00:24.671345 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5373 01:00:24.678278 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 01:00:24.681338 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 01:00:24.684439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 01:00:24.691351 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 01:00:24.694691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 01:00:24.697720 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 01:00:24.704403 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
5380 01:00:24.707819 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
5381 01:00:24.711241 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 01:00:24.717621 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 01:00:24.721072 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 01:00:24.724296 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 01:00:24.730689 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 01:00:24.734268 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 01:00:24.737349 0 15 28 | B1->B0 | 2727 3333 | 0 1 | (0 0) (0 0)
5388 01:00:24.744267 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5389 01:00:24.747623 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 01:00:24.750764 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 01:00:24.757248 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 01:00:24.760532 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 01:00:24.763750 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 01:00:24.770418 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 01:00:24.773641 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5396 01:00:24.777188 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5397 01:00:24.783762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 01:00:24.787159 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 01:00:24.790257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 01:00:24.796925 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 01:00:24.799912 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 01:00:24.803267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 01:00:24.810384 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 01:00:24.813438 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 01:00:24.816719 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 01:00:24.823430 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 01:00:24.826501 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 01:00:24.829519 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 01:00:24.836487 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 01:00:24.839594 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 01:00:24.843019 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5412 01:00:24.849712 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 01:00:24.852829 Total UI for P1: 0, mck2ui 16
5414 01:00:24.856083 best dqsien dly found for B0: ( 1, 2, 28)
5415 01:00:24.859555 Total UI for P1: 0, mck2ui 16
5416 01:00:24.862744 best dqsien dly found for B1: ( 1, 2, 30)
5417 01:00:24.865943 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5418 01:00:24.869219 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5419 01:00:24.869301
5420 01:00:24.872525 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5421 01:00:24.875756 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5422 01:00:24.879067 [Gating] SW calibration Done
5423 01:00:24.879150 ==
5424 01:00:24.882509 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 01:00:24.885826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 01:00:24.885908 ==
5427 01:00:24.889137 RX Vref Scan: 0
5428 01:00:24.889218
5429 01:00:24.892375 RX Vref 0 -> 0, step: 1
5430 01:00:24.892457
5431 01:00:24.892521 RX Delay -80 -> 252, step: 8
5432 01:00:24.899061 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5433 01:00:24.902461 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5434 01:00:24.905656 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5435 01:00:24.909068 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5436 01:00:24.912271 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5437 01:00:24.919126 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5438 01:00:24.922447 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5439 01:00:24.925700 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5440 01:00:24.928868 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5441 01:00:24.932441 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5442 01:00:24.935815 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5443 01:00:24.942293 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5444 01:00:24.945589 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5445 01:00:24.948978 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5446 01:00:24.952213 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5447 01:00:24.955710 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5448 01:00:24.955792 ==
5449 01:00:24.958896 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 01:00:24.965584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 01:00:24.965668 ==
5452 01:00:24.965732 DQS Delay:
5453 01:00:24.969076 DQS0 = 0, DQS1 = 0
5454 01:00:24.969158 DQM Delay:
5455 01:00:24.969223 DQM0 = 92, DQM1 = 83
5456 01:00:24.972098 DQ Delay:
5457 01:00:24.975735 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5458 01:00:24.978903 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5459 01:00:24.982174 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5460 01:00:24.985535 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5461 01:00:24.985617
5462 01:00:24.985682
5463 01:00:24.985742 ==
5464 01:00:24.988993 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 01:00:24.992310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 01:00:24.992394 ==
5467 01:00:24.992458
5468 01:00:24.992517
5469 01:00:24.995542 TX Vref Scan disable
5470 01:00:24.998797 == TX Byte 0 ==
5471 01:00:25.002090 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5472 01:00:25.005272 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5473 01:00:25.008622 == TX Byte 1 ==
5474 01:00:25.012034 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5475 01:00:25.015145 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5476 01:00:25.015228 ==
5477 01:00:25.018449 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 01:00:25.021943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 01:00:25.025058 ==
5480 01:00:25.025141
5481 01:00:25.025205
5482 01:00:25.025265 TX Vref Scan disable
5483 01:00:25.029001 == TX Byte 0 ==
5484 01:00:25.032213 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5485 01:00:25.038759 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5486 01:00:25.038842 == TX Byte 1 ==
5487 01:00:25.042008 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5488 01:00:25.048729 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5489 01:00:25.048812
5490 01:00:25.048877 [DATLAT]
5491 01:00:25.048937 Freq=933, CH0 RK1
5492 01:00:25.048995
5493 01:00:25.051952 DATLAT Default: 0xb
5494 01:00:25.052036 0, 0xFFFF, sum = 0
5495 01:00:25.055453 1, 0xFFFF, sum = 0
5496 01:00:25.055537 2, 0xFFFF, sum = 0
5497 01:00:25.058611 3, 0xFFFF, sum = 0
5498 01:00:25.061917 4, 0xFFFF, sum = 0
5499 01:00:25.062000 5, 0xFFFF, sum = 0
5500 01:00:25.065511 6, 0xFFFF, sum = 0
5501 01:00:25.065595 7, 0xFFFF, sum = 0
5502 01:00:25.068806 8, 0xFFFF, sum = 0
5503 01:00:25.068889 9, 0xFFFF, sum = 0
5504 01:00:25.071974 10, 0x0, sum = 1
5505 01:00:25.072057 11, 0x0, sum = 2
5506 01:00:25.075003 12, 0x0, sum = 3
5507 01:00:25.075096 13, 0x0, sum = 4
5508 01:00:25.075164 best_step = 11
5509 01:00:25.078592
5510 01:00:25.078674 ==
5511 01:00:25.081858 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 01:00:25.084984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 01:00:25.085067 ==
5514 01:00:25.085133 RX Vref Scan: 0
5515 01:00:25.085194
5516 01:00:25.088451 RX Vref 0 -> 0, step: 1
5517 01:00:25.088533
5518 01:00:25.091796 RX Delay -77 -> 252, step: 4
5519 01:00:25.098391 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5520 01:00:25.101674 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5521 01:00:25.104938 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5522 01:00:25.108166 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5523 01:00:25.111486 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5524 01:00:25.114797 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5525 01:00:25.121665 iDelay=199, Bit 6, Center 102 (7 ~ 198) 192
5526 01:00:25.124967 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5527 01:00:25.127978 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5528 01:00:25.131287 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5529 01:00:25.134753 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5530 01:00:25.141530 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5531 01:00:25.144706 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5532 01:00:25.147995 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5533 01:00:25.151510 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5534 01:00:25.154850 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5535 01:00:25.154932 ==
5536 01:00:25.158008 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 01:00:25.164712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 01:00:25.164795 ==
5539 01:00:25.164860 DQS Delay:
5540 01:00:25.167854 DQS0 = 0, DQS1 = 0
5541 01:00:25.167936 DQM Delay:
5542 01:00:25.168001 DQM0 = 91, DQM1 = 85
5543 01:00:25.171478 DQ Delay:
5544 01:00:25.174644 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5545 01:00:25.177859 DQ4 =90, DQ5 =80, DQ6 =102, DQ7 =102
5546 01:00:25.181067 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5547 01:00:25.184721 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =92
5548 01:00:25.184803
5549 01:00:25.184867
5550 01:00:25.191295 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5551 01:00:25.194507 CH0 RK1: MR19=505, MR18=3213
5552 01:00:25.201247 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5553 01:00:25.204435 [RxdqsGatingPostProcess] freq 933
5554 01:00:25.207666 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5555 01:00:25.210864 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 01:00:25.214216 best DQS1 dly(2T, 0.5T) = (0, 11)
5557 01:00:25.217751 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 01:00:25.221011 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5559 01:00:25.224274 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 01:00:25.227585 best DQS1 dly(2T, 0.5T) = (0, 10)
5561 01:00:25.230819 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 01:00:25.234095 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5563 01:00:25.237319 Pre-setting of DQS Precalculation
5564 01:00:25.240855 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5565 01:00:25.244142 ==
5566 01:00:25.247222 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 01:00:25.250749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 01:00:25.250859 ==
5569 01:00:25.253938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 01:00:25.260652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5571 01:00:25.264248 [CA 0] Center 37 (7~67) winsize 61
5572 01:00:25.267760 [CA 1] Center 38 (8~68) winsize 61
5573 01:00:25.270868 [CA 2] Center 34 (5~64) winsize 60
5574 01:00:25.274185 [CA 3] Center 34 (5~64) winsize 60
5575 01:00:25.277485 [CA 4] Center 34 (5~64) winsize 60
5576 01:00:25.280735 [CA 5] Center 34 (4~64) winsize 61
5577 01:00:25.280818
5578 01:00:25.284317 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5579 01:00:25.284400
5580 01:00:25.287676 [CATrainingPosCal] consider 1 rank data
5581 01:00:25.290938 u2DelayCellTimex100 = 270/100 ps
5582 01:00:25.294289 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5583 01:00:25.300749 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5584 01:00:25.303979 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5585 01:00:25.307021 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5586 01:00:25.310629 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5587 01:00:25.313669 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5588 01:00:25.313797
5589 01:00:25.317096 CA PerBit enable=1, Macro0, CA PI delay=34
5590 01:00:25.317180
5591 01:00:25.320366 [CBTSetCACLKResult] CA Dly = 34
5592 01:00:25.323948 CS Dly: 6 (0~37)
5593 01:00:25.324031 ==
5594 01:00:25.327231 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 01:00:25.330496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 01:00:25.330580 ==
5597 01:00:25.337030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5598 01:00:25.340255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5599 01:00:25.344617 [CA 0] Center 37 (7~68) winsize 62
5600 01:00:25.347741 [CA 1] Center 37 (7~68) winsize 62
5601 01:00:25.351137 [CA 2] Center 35 (5~65) winsize 61
5602 01:00:25.354147 [CA 3] Center 34 (4~65) winsize 62
5603 01:00:25.357366 [CA 4] Center 35 (5~65) winsize 61
5604 01:00:25.360728 [CA 5] Center 34 (4~64) winsize 61
5605 01:00:25.360824
5606 01:00:25.364232 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5607 01:00:25.364314
5608 01:00:25.367498 [CATrainingPosCal] consider 2 rank data
5609 01:00:25.371008 u2DelayCellTimex100 = 270/100 ps
5610 01:00:25.374238 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5611 01:00:25.380982 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5612 01:00:25.384048 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5613 01:00:25.387477 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5614 01:00:25.390625 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5615 01:00:25.394275 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5616 01:00:25.394358
5617 01:00:25.397304 CA PerBit enable=1, Macro0, CA PI delay=34
5618 01:00:25.397404
5619 01:00:25.400833 [CBTSetCACLKResult] CA Dly = 34
5620 01:00:25.400915 CS Dly: 7 (0~39)
5621 01:00:25.404012
5622 01:00:25.407319 ----->DramcWriteLeveling(PI) begin...
5623 01:00:25.407402 ==
5624 01:00:25.410597 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 01:00:25.413747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 01:00:25.413837 ==
5627 01:00:25.417240 Write leveling (Byte 0): 28 => 28
5628 01:00:25.420608 Write leveling (Byte 1): 28 => 28
5629 01:00:25.423751 DramcWriteLeveling(PI) end<-----
5630 01:00:25.423833
5631 01:00:25.423896 ==
5632 01:00:25.427200 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 01:00:25.430497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 01:00:25.430580 ==
5635 01:00:25.433867 [Gating] SW mode calibration
5636 01:00:25.440557 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5637 01:00:25.447164 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5638 01:00:25.450471 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5639 01:00:25.453640 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 01:00:25.460287 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 01:00:25.463540 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 01:00:25.467089 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 01:00:25.473533 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 01:00:25.476752 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 01:00:25.480377 0 14 28 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 0)
5646 01:00:25.486740 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5647 01:00:25.489996 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 01:00:25.493485 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 01:00:25.499947 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 01:00:25.503375 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 01:00:25.506672 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 01:00:25.513220 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 01:00:25.516477 0 15 28 | B1->B0 | 2f2e 2f2f | 1 0 | (0 0) (0 0)
5654 01:00:25.520067 1 0 0 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5655 01:00:25.526583 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 01:00:25.530073 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 01:00:25.532990 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 01:00:25.539779 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 01:00:25.543022 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 01:00:25.546143 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 01:00:25.553172 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5662 01:00:25.556493 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5663 01:00:25.559423 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 01:00:25.565998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 01:00:25.569591 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 01:00:25.572748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 01:00:25.575916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 01:00:25.582630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 01:00:25.586028 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 01:00:25.589235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 01:00:25.596122 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 01:00:25.599389 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 01:00:25.602475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 01:00:25.609148 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 01:00:25.612429 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 01:00:25.615589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 01:00:25.622414 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5678 01:00:25.625673 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 01:00:25.628908 Total UI for P1: 0, mck2ui 16
5680 01:00:25.632445 best dqsien dly found for B0: ( 1, 2, 28)
5681 01:00:25.635691 Total UI for P1: 0, mck2ui 16
5682 01:00:25.638938 best dqsien dly found for B1: ( 1, 2, 28)
5683 01:00:25.642665 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5684 01:00:25.645800 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5685 01:00:25.645884
5686 01:00:25.648977 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5687 01:00:25.652507 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5688 01:00:25.655619 [Gating] SW calibration Done
5689 01:00:25.655703 ==
5690 01:00:25.658844 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 01:00:25.665466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 01:00:25.665586 ==
5693 01:00:25.665672 RX Vref Scan: 0
5694 01:00:25.665753
5695 01:00:25.668816 RX Vref 0 -> 0, step: 1
5696 01:00:25.668916
5697 01:00:25.672289 RX Delay -80 -> 252, step: 8
5698 01:00:25.675353 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5699 01:00:25.678663 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5700 01:00:25.682109 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5701 01:00:25.685379 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5702 01:00:25.691965 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5703 01:00:25.695334 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5704 01:00:25.698648 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5705 01:00:25.701938 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5706 01:00:25.705352 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5707 01:00:25.708716 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5708 01:00:25.715178 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5709 01:00:25.718608 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5710 01:00:25.721539 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5711 01:00:25.725327 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5712 01:00:25.728529 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5713 01:00:25.735097 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5714 01:00:25.735183 ==
5715 01:00:25.738219 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 01:00:25.741715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 01:00:25.741800 ==
5718 01:00:25.741884 DQS Delay:
5719 01:00:25.744974 DQS0 = 0, DQS1 = 0
5720 01:00:25.745075 DQM Delay:
5721 01:00:25.748210 DQM0 = 94, DQM1 = 86
5722 01:00:25.748295 DQ Delay:
5723 01:00:25.751528 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5724 01:00:25.755089 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5725 01:00:25.758337 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5726 01:00:25.761493 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5727 01:00:25.761579
5728 01:00:25.761680
5729 01:00:25.761779 ==
5730 01:00:25.765094 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 01:00:25.768181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 01:00:25.771496 ==
5733 01:00:25.771581
5734 01:00:25.771666
5735 01:00:25.771747 TX Vref Scan disable
5736 01:00:25.775007 == TX Byte 0 ==
5737 01:00:25.778269 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5738 01:00:25.781626 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5739 01:00:25.784995 == TX Byte 1 ==
5740 01:00:25.788299 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5741 01:00:25.791382 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5742 01:00:25.794805 ==
5743 01:00:25.794889 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 01:00:25.801353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 01:00:25.801463 ==
5746 01:00:25.801616
5747 01:00:25.801696
5748 01:00:25.804505 TX Vref Scan disable
5749 01:00:25.804607 == TX Byte 0 ==
5750 01:00:25.811440 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5751 01:00:25.814700 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5752 01:00:25.814785 == TX Byte 1 ==
5753 01:00:25.821102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5754 01:00:25.824335 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5755 01:00:25.824420
5756 01:00:25.824506 [DATLAT]
5757 01:00:25.827826 Freq=933, CH1 RK0
5758 01:00:25.827911
5759 01:00:25.827996 DATLAT Default: 0xd
5760 01:00:25.831046 0, 0xFFFF, sum = 0
5761 01:00:25.831133 1, 0xFFFF, sum = 0
5762 01:00:25.834271 2, 0xFFFF, sum = 0
5763 01:00:25.834357 3, 0xFFFF, sum = 0
5764 01:00:25.837665 4, 0xFFFF, sum = 0
5765 01:00:25.837750 5, 0xFFFF, sum = 0
5766 01:00:25.840870 6, 0xFFFF, sum = 0
5767 01:00:25.844355 7, 0xFFFF, sum = 0
5768 01:00:25.844441 8, 0xFFFF, sum = 0
5769 01:00:25.847638 9, 0xFFFF, sum = 0
5770 01:00:25.847724 10, 0x0, sum = 1
5771 01:00:25.851101 11, 0x0, sum = 2
5772 01:00:25.851187 12, 0x0, sum = 3
5773 01:00:25.851273 13, 0x0, sum = 4
5774 01:00:25.854073 best_step = 11
5775 01:00:25.854157
5776 01:00:25.854242 ==
5777 01:00:25.857763 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 01:00:25.860994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 01:00:25.861080 ==
5780 01:00:25.863907 RX Vref Scan: 1
5781 01:00:25.863991
5782 01:00:25.864077 RX Vref 0 -> 0, step: 1
5783 01:00:25.867580
5784 01:00:25.867722 RX Delay -69 -> 252, step: 4
5785 01:00:25.867809
5786 01:00:25.870982 Set Vref, RX VrefLevel [Byte0]: 55
5787 01:00:25.874109 [Byte1]: 53
5788 01:00:25.878501
5789 01:00:25.878585 Final RX Vref Byte 0 = 55 to rank0
5790 01:00:25.882085 Final RX Vref Byte 1 = 53 to rank0
5791 01:00:25.885084 Final RX Vref Byte 0 = 55 to rank1
5792 01:00:25.888481 Final RX Vref Byte 1 = 53 to rank1==
5793 01:00:25.891604 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 01:00:25.898273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 01:00:25.898358 ==
5796 01:00:25.898444 DQS Delay:
5797 01:00:25.901731 DQS0 = 0, DQS1 = 0
5798 01:00:25.901816 DQM Delay:
5799 01:00:25.901901 DQM0 = 95, DQM1 = 89
5800 01:00:25.904947 DQ Delay:
5801 01:00:25.908294 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5802 01:00:25.911632 DQ4 =94, DQ5 =104, DQ6 =108, DQ7 =94
5803 01:00:25.914880 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5804 01:00:25.918262 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5805 01:00:25.918345
5806 01:00:25.918410
5807 01:00:25.924769 [DQSOSCAuto] RK0, (LSB)MR18= 0x40d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5808 01:00:25.928108 CH1 RK0: MR19=505, MR18=40D
5809 01:00:25.934885 CH1_RK0: MR19=0x505, MR18=0x40D, DQSOSC=417, MR23=63, INC=62, DEC=41
5810 01:00:25.934972
5811 01:00:25.938159 ----->DramcWriteLeveling(PI) begin...
5812 01:00:25.938243 ==
5813 01:00:25.941483 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 01:00:25.944748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 01:00:25.944831 ==
5816 01:00:25.948104 Write leveling (Byte 0): 26 => 26
5817 01:00:25.951306 Write leveling (Byte 1): 28 => 28
5818 01:00:25.954482 DramcWriteLeveling(PI) end<-----
5819 01:00:25.954564
5820 01:00:25.954629 ==
5821 01:00:25.957682 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 01:00:25.961301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 01:00:25.961384 ==
5824 01:00:25.964571 [Gating] SW mode calibration
5825 01:00:25.971152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5826 01:00:25.977658 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5827 01:00:25.980855 0 14 0 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
5828 01:00:25.987541 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 01:00:25.990733 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 01:00:25.994295 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 01:00:26.000681 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 01:00:26.004109 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 01:00:26.007281 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5834 01:00:26.013994 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5835 01:00:26.017264 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5836 01:00:26.020447 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 01:00:26.027429 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 01:00:26.030498 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 01:00:26.033768 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 01:00:26.040420 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 01:00:26.043592 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5842 01:00:26.046998 0 15 28 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
5843 01:00:26.053562 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 01:00:26.056774 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 01:00:26.060331 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 01:00:26.066639 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 01:00:26.069936 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 01:00:26.073175 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 01:00:26.080023 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5850 01:00:26.083268 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5851 01:00:26.086614 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 01:00:26.093145 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 01:00:26.096354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 01:00:26.099974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 01:00:26.106379 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 01:00:26.109633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 01:00:26.112856 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 01:00:26.119450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 01:00:26.122978 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 01:00:26.126184 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 01:00:26.132806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 01:00:26.135965 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 01:00:26.139303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 01:00:26.145855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 01:00:26.149376 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5866 01:00:26.152612 Total UI for P1: 0, mck2ui 16
5867 01:00:26.155863 best dqsien dly found for B0: ( 1, 2, 22)
5868 01:00:26.159273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5869 01:00:26.165962 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 01:00:26.166045 Total UI for P1: 0, mck2ui 16
5871 01:00:26.169352 best dqsien dly found for B1: ( 1, 2, 26)
5872 01:00:26.175682 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5873 01:00:26.178985 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5874 01:00:26.179068
5875 01:00:26.182604 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5876 01:00:26.185616 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5877 01:00:26.189145 [Gating] SW calibration Done
5878 01:00:26.189228 ==
5879 01:00:26.192449 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 01:00:26.195681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 01:00:26.195768 ==
5882 01:00:26.198937 RX Vref Scan: 0
5883 01:00:26.199019
5884 01:00:26.199084 RX Vref 0 -> 0, step: 1
5885 01:00:26.199144
5886 01:00:26.202209 RX Delay -80 -> 252, step: 8
5887 01:00:26.205433 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5888 01:00:26.212221 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5889 01:00:26.215595 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5890 01:00:26.218785 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5891 01:00:26.221960 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5892 01:00:26.225328 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5893 01:00:26.228833 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5894 01:00:26.235142 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5895 01:00:26.238669 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5896 01:00:26.241900 iDelay=208, Bit 9, Center 79 (-24 ~ 183) 208
5897 01:00:26.245188 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5898 01:00:26.248456 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5899 01:00:26.255168 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5900 01:00:26.258427 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5901 01:00:26.261792 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5902 01:00:26.264896 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5903 01:00:26.264979 ==
5904 01:00:26.268403 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 01:00:26.271553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 01:00:26.274757 ==
5907 01:00:26.274840 DQS Delay:
5908 01:00:26.274905 DQS0 = 0, DQS1 = 0
5909 01:00:26.278076 DQM Delay:
5910 01:00:26.278158 DQM0 = 95, DQM1 = 89
5911 01:00:26.281343 DQ Delay:
5912 01:00:26.284758 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5913 01:00:26.288283 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5914 01:00:26.288366 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5915 01:00:26.294982 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =99
5916 01:00:26.295065
5917 01:00:26.295130
5918 01:00:26.295190 ==
5919 01:00:26.298193 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 01:00:26.301325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 01:00:26.301408 ==
5922 01:00:26.301499
5923 01:00:26.301577
5924 01:00:26.304601 TX Vref Scan disable
5925 01:00:26.304683 == TX Byte 0 ==
5926 01:00:26.311086 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5927 01:00:26.314271 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5928 01:00:26.314354 == TX Byte 1 ==
5929 01:00:26.320895 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5930 01:00:26.324507 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5931 01:00:26.324590 ==
5932 01:00:26.327754 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 01:00:26.331087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 01:00:26.331171 ==
5935 01:00:26.331236
5936 01:00:26.334396
5937 01:00:26.334478 TX Vref Scan disable
5938 01:00:26.337608 == TX Byte 0 ==
5939 01:00:26.340936 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5940 01:00:26.344216 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5941 01:00:26.347511 == TX Byte 1 ==
5942 01:00:26.350645 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5943 01:00:26.357277 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5944 01:00:26.357360
5945 01:00:26.357425 [DATLAT]
5946 01:00:26.357495 Freq=933, CH1 RK1
5947 01:00:26.357556
5948 01:00:26.360652 DATLAT Default: 0xb
5949 01:00:26.360734 0, 0xFFFF, sum = 0
5950 01:00:26.364106 1, 0xFFFF, sum = 0
5951 01:00:26.364190 2, 0xFFFF, sum = 0
5952 01:00:26.367268 3, 0xFFFF, sum = 0
5953 01:00:26.370453 4, 0xFFFF, sum = 0
5954 01:00:26.370537 5, 0xFFFF, sum = 0
5955 01:00:26.374072 6, 0xFFFF, sum = 0
5956 01:00:26.374157 7, 0xFFFF, sum = 0
5957 01:00:26.377256 8, 0xFFFF, sum = 0
5958 01:00:26.377340 9, 0xFFFF, sum = 0
5959 01:00:26.380361 10, 0x0, sum = 1
5960 01:00:26.380446 11, 0x0, sum = 2
5961 01:00:26.383724 12, 0x0, sum = 3
5962 01:00:26.383807 13, 0x0, sum = 4
5963 01:00:26.383874 best_step = 11
5964 01:00:26.383934
5965 01:00:26.387151 ==
5966 01:00:26.390499 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 01:00:26.393838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 01:00:26.393920 ==
5969 01:00:26.393985 RX Vref Scan: 0
5970 01:00:26.394046
5971 01:00:26.397234 RX Vref 0 -> 0, step: 1
5972 01:00:26.397316
5973 01:00:26.400407 RX Delay -69 -> 252, step: 4
5974 01:00:26.403685 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5975 01:00:26.410306 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5976 01:00:26.413631 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5977 01:00:26.417119 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5978 01:00:26.420323 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5979 01:00:26.423633 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5980 01:00:26.430342 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5981 01:00:26.433511 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5982 01:00:26.436989 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5983 01:00:26.440277 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5984 01:00:26.443625 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5985 01:00:26.446711 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5986 01:00:26.453227 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5987 01:00:26.456539 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5988 01:00:26.460089 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5989 01:00:26.463487 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5990 01:00:26.463570 ==
5991 01:00:26.466494 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 01:00:26.473297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 01:00:26.473380 ==
5994 01:00:26.473445 DQS Delay:
5995 01:00:26.476608 DQS0 = 0, DQS1 = 0
5996 01:00:26.476690 DQM Delay:
5997 01:00:26.476755 DQM0 = 92, DQM1 = 92
5998 01:00:26.479970 DQ Delay:
5999 01:00:26.483249 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6000 01:00:26.486495 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
6001 01:00:26.489775 DQ8 =80, DQ9 =82, DQ10 =90, DQ11 =86
6002 01:00:26.493195 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
6003 01:00:26.493278
6004 01:00:26.493343
6005 01:00:26.499731 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
6006 01:00:26.502963 CH1 RK1: MR19=505, MR18=C1F
6007 01:00:26.509509 CH1_RK1: MR19=0x505, MR18=0xC1F, DQSOSC=412, MR23=63, INC=63, DEC=42
6008 01:00:26.512946 [RxdqsGatingPostProcess] freq 933
6009 01:00:26.516137 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6010 01:00:26.519440 best DQS0 dly(2T, 0.5T) = (0, 10)
6011 01:00:26.522584 best DQS1 dly(2T, 0.5T) = (0, 10)
6012 01:00:26.525901 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6013 01:00:26.529186 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6014 01:00:26.532777 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 01:00:26.535839 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 01:00:26.539249 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 01:00:26.542566 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 01:00:26.546061 Pre-setting of DQS Precalculation
6019 01:00:26.549302 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6020 01:00:26.558967 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6021 01:00:26.565835 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6022 01:00:26.565918
6023 01:00:26.565983
6024 01:00:26.569005 [Calibration Summary] 1866 Mbps
6025 01:00:26.569088 CH 0, Rank 0
6026 01:00:26.572524 SW Impedance : PASS
6027 01:00:26.572607 DUTY Scan : NO K
6028 01:00:26.575675 ZQ Calibration : PASS
6029 01:00:26.578900 Jitter Meter : NO K
6030 01:00:26.578982 CBT Training : PASS
6031 01:00:26.582373 Write leveling : PASS
6032 01:00:26.585662 RX DQS gating : PASS
6033 01:00:26.585744 RX DQ/DQS(RDDQC) : PASS
6034 01:00:26.588771 TX DQ/DQS : PASS
6035 01:00:26.592169 RX DATLAT : PASS
6036 01:00:26.592251 RX DQ/DQS(Engine): PASS
6037 01:00:26.595349 TX OE : NO K
6038 01:00:26.595432 All Pass.
6039 01:00:26.595497
6040 01:00:26.598735 CH 0, Rank 1
6041 01:00:26.598817 SW Impedance : PASS
6042 01:00:26.601980 DUTY Scan : NO K
6043 01:00:26.605466 ZQ Calibration : PASS
6044 01:00:26.605568 Jitter Meter : NO K
6045 01:00:26.608841 CBT Training : PASS
6046 01:00:26.611858 Write leveling : PASS
6047 01:00:26.611941 RX DQS gating : PASS
6048 01:00:26.615390 RX DQ/DQS(RDDQC) : PASS
6049 01:00:26.618596 TX DQ/DQS : PASS
6050 01:00:26.618679 RX DATLAT : PASS
6051 01:00:26.621798 RX DQ/DQS(Engine): PASS
6052 01:00:26.625104 TX OE : NO K
6053 01:00:26.625187 All Pass.
6054 01:00:26.625253
6055 01:00:26.625313 CH 1, Rank 0
6056 01:00:26.628569 SW Impedance : PASS
6057 01:00:26.631726 DUTY Scan : NO K
6058 01:00:26.631809 ZQ Calibration : PASS
6059 01:00:26.634996 Jitter Meter : NO K
6060 01:00:26.638340 CBT Training : PASS
6061 01:00:26.638422 Write leveling : PASS
6062 01:00:26.641472 RX DQS gating : PASS
6063 01:00:26.641563 RX DQ/DQS(RDDQC) : PASS
6064 01:00:26.644941 TX DQ/DQS : PASS
6065 01:00:26.648193 RX DATLAT : PASS
6066 01:00:26.648276 RX DQ/DQS(Engine): PASS
6067 01:00:26.651787 TX OE : NO K
6068 01:00:26.651870 All Pass.
6069 01:00:26.651936
6070 01:00:26.654997 CH 1, Rank 1
6071 01:00:26.655079 SW Impedance : PASS
6072 01:00:26.658002 DUTY Scan : NO K
6073 01:00:26.661368 ZQ Calibration : PASS
6074 01:00:26.661451 Jitter Meter : NO K
6075 01:00:26.665089 CBT Training : PASS
6076 01:00:26.668309 Write leveling : PASS
6077 01:00:26.668391 RX DQS gating : PASS
6078 01:00:26.671642 RX DQ/DQS(RDDQC) : PASS
6079 01:00:26.674862 TX DQ/DQS : PASS
6080 01:00:26.674944 RX DATLAT : PASS
6081 01:00:26.677923 RX DQ/DQS(Engine): PASS
6082 01:00:26.681338 TX OE : NO K
6083 01:00:26.681420 All Pass.
6084 01:00:26.681508
6085 01:00:26.681583 DramC Write-DBI off
6086 01:00:26.684614 PER_BANK_REFRESH: Hybrid Mode
6087 01:00:26.687968 TX_TRACKING: ON
6088 01:00:26.694525 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6089 01:00:26.697867 [FAST_K] Save calibration result to emmc
6090 01:00:26.704449 dramc_set_vcore_voltage set vcore to 650000
6091 01:00:26.704532 Read voltage for 400, 6
6092 01:00:26.707882 Vio18 = 0
6093 01:00:26.707965 Vcore = 650000
6094 01:00:26.708030 Vdram = 0
6095 01:00:26.711099 Vddq = 0
6096 01:00:26.711189 Vmddr = 0
6097 01:00:26.714363 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6098 01:00:26.721221 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6099 01:00:26.724443 MEM_TYPE=3, freq_sel=20
6100 01:00:26.727886 sv_algorithm_assistance_LP4_800
6101 01:00:26.731239 ============ PULL DRAM RESETB DOWN ============
6102 01:00:26.734367 ========== PULL DRAM RESETB DOWN end =========
6103 01:00:26.737587 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6104 01:00:26.740939 ===================================
6105 01:00:26.744306 LPDDR4 DRAM CONFIGURATION
6106 01:00:26.747409 ===================================
6107 01:00:26.751087 EX_ROW_EN[0] = 0x0
6108 01:00:26.751170 EX_ROW_EN[1] = 0x0
6109 01:00:26.754254 LP4Y_EN = 0x0
6110 01:00:26.754337 WORK_FSP = 0x0
6111 01:00:26.757273 WL = 0x2
6112 01:00:26.757355 RL = 0x2
6113 01:00:26.760570 BL = 0x2
6114 01:00:26.760653 RPST = 0x0
6115 01:00:26.764145 RD_PRE = 0x0
6116 01:00:26.764228 WR_PRE = 0x1
6117 01:00:26.767675 WR_PST = 0x0
6118 01:00:26.770877 DBI_WR = 0x0
6119 01:00:26.770959 DBI_RD = 0x0
6120 01:00:26.774235 OTF = 0x1
6121 01:00:26.777430 ===================================
6122 01:00:26.780612 ===================================
6123 01:00:26.780695 ANA top config
6124 01:00:26.784058 ===================================
6125 01:00:26.787158 DLL_ASYNC_EN = 0
6126 01:00:26.790480 ALL_SLAVE_EN = 1
6127 01:00:26.790563 NEW_RANK_MODE = 1
6128 01:00:26.793954 DLL_IDLE_MODE = 1
6129 01:00:26.797273 LP45_APHY_COMB_EN = 1
6130 01:00:26.800610 TX_ODT_DIS = 1
6131 01:00:26.800693 NEW_8X_MODE = 1
6132 01:00:26.803647 ===================================
6133 01:00:26.807256 ===================================
6134 01:00:26.810607 data_rate = 800
6135 01:00:26.813828 CKR = 1
6136 01:00:26.816876 DQ_P2S_RATIO = 4
6137 01:00:26.820359 ===================================
6138 01:00:26.823836 CA_P2S_RATIO = 4
6139 01:00:26.826900 DQ_CA_OPEN = 0
6140 01:00:26.826974 DQ_SEMI_OPEN = 1
6141 01:00:26.830328 CA_SEMI_OPEN = 1
6142 01:00:26.833416 CA_FULL_RATE = 0
6143 01:00:26.837091 DQ_CKDIV4_EN = 0
6144 01:00:26.840282 CA_CKDIV4_EN = 1
6145 01:00:26.843545 CA_PREDIV_EN = 0
6146 01:00:26.843628 PH8_DLY = 0
6147 01:00:26.846841 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6148 01:00:26.850227 DQ_AAMCK_DIV = 0
6149 01:00:26.853465 CA_AAMCK_DIV = 0
6150 01:00:26.856721 CA_ADMCK_DIV = 4
6151 01:00:26.860232 DQ_TRACK_CA_EN = 0
6152 01:00:26.863185 CA_PICK = 800
6153 01:00:26.863268 CA_MCKIO = 400
6154 01:00:26.866824 MCKIO_SEMI = 400
6155 01:00:26.869942 PLL_FREQ = 3016
6156 01:00:26.873169 DQ_UI_PI_RATIO = 32
6157 01:00:26.876545 CA_UI_PI_RATIO = 32
6158 01:00:26.879881 ===================================
6159 01:00:26.883402 ===================================
6160 01:00:26.886748 memory_type:LPDDR4
6161 01:00:26.886831 GP_NUM : 10
6162 01:00:26.889693 SRAM_EN : 1
6163 01:00:26.889767 MD32_EN : 0
6164 01:00:26.893380 ===================================
6165 01:00:26.896620 [ANA_INIT] >>>>>>>>>>>>>>
6166 01:00:26.899975 <<<<<< [CONFIGURE PHASE]: ANA_TX
6167 01:00:26.903243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6168 01:00:26.906527 ===================================
6169 01:00:26.909758 data_rate = 800,PCW = 0X7400
6170 01:00:26.913193 ===================================
6171 01:00:26.916401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6172 01:00:26.922830 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 01:00:26.932912 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6174 01:00:26.936229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6175 01:00:26.939325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6176 01:00:26.946073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6177 01:00:26.946157 [ANA_INIT] flow start
6178 01:00:26.949631 [ANA_INIT] PLL >>>>>>>>
6179 01:00:26.949714 [ANA_INIT] PLL <<<<<<<<
6180 01:00:26.952601 [ANA_INIT] MIDPI >>>>>>>>
6181 01:00:26.956172 [ANA_INIT] MIDPI <<<<<<<<
6182 01:00:26.959268 [ANA_INIT] DLL >>>>>>>>
6183 01:00:26.959350 [ANA_INIT] flow end
6184 01:00:26.962556 ============ LP4 DIFF to SE enter ============
6185 01:00:26.969345 ============ LP4 DIFF to SE exit ============
6186 01:00:26.969448 [ANA_INIT] <<<<<<<<<<<<<
6187 01:00:26.972535 [Flow] Enable top DCM control >>>>>
6188 01:00:26.976023 [Flow] Enable top DCM control <<<<<
6189 01:00:26.979306 Enable DLL master slave shuffle
6190 01:00:26.985754 ==============================================================
6191 01:00:26.985837 Gating Mode config
6192 01:00:26.992607 ==============================================================
6193 01:00:26.995749 Config description:
6194 01:00:27.005812 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6195 01:00:27.012279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6196 01:00:27.015956 SELPH_MODE 0: By rank 1: By Phase
6197 01:00:27.022641 ==============================================================
6198 01:00:27.025905 GAT_TRACK_EN = 0
6199 01:00:27.028924 RX_GATING_MODE = 2
6200 01:00:27.029010 RX_GATING_TRACK_MODE = 2
6201 01:00:27.032163 SELPH_MODE = 1
6202 01:00:27.035766 PICG_EARLY_EN = 1
6203 01:00:27.039132 VALID_LAT_VALUE = 1
6204 01:00:27.045566 ==============================================================
6205 01:00:27.048916 Enter into Gating configuration >>>>
6206 01:00:27.052134 Exit from Gating configuration <<<<
6207 01:00:27.055543 Enter into DVFS_PRE_config >>>>>
6208 01:00:27.065293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6209 01:00:27.068923 Exit from DVFS_PRE_config <<<<<
6210 01:00:27.072133 Enter into PICG configuration >>>>
6211 01:00:27.075316 Exit from PICG configuration <<<<
6212 01:00:27.078559 [RX_INPUT] configuration >>>>>
6213 01:00:27.081882 [RX_INPUT] configuration <<<<<
6214 01:00:27.085181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6215 01:00:27.091789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6216 01:00:27.098621 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 01:00:27.105132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 01:00:27.111553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 01:00:27.114899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 01:00:27.121859 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6221 01:00:27.125069 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6222 01:00:27.128402 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6223 01:00:27.131627 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6224 01:00:27.134804 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6225 01:00:27.141354 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 01:00:27.144648 ===================================
6227 01:00:27.148296 LPDDR4 DRAM CONFIGURATION
6228 01:00:27.151362 ===================================
6229 01:00:27.151444 EX_ROW_EN[0] = 0x0
6230 01:00:27.154925 EX_ROW_EN[1] = 0x0
6231 01:00:27.155006 LP4Y_EN = 0x0
6232 01:00:27.158106 WORK_FSP = 0x0
6233 01:00:27.158188 WL = 0x2
6234 01:00:27.161363 RL = 0x2
6235 01:00:27.161470 BL = 0x2
6236 01:00:27.164764 RPST = 0x0
6237 01:00:27.164846 RD_PRE = 0x0
6238 01:00:27.168036 WR_PRE = 0x1
6239 01:00:27.168118 WR_PST = 0x0
6240 01:00:27.171150 DBI_WR = 0x0
6241 01:00:27.174375 DBI_RD = 0x0
6242 01:00:27.174457 OTF = 0x1
6243 01:00:27.177876 ===================================
6244 01:00:27.181197 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6245 01:00:27.184416 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6246 01:00:27.191236 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6247 01:00:27.194463 ===================================
6248 01:00:27.197752 LPDDR4 DRAM CONFIGURATION
6249 01:00:27.201096 ===================================
6250 01:00:27.201178 EX_ROW_EN[0] = 0x10
6251 01:00:27.204299 EX_ROW_EN[1] = 0x0
6252 01:00:27.204382 LP4Y_EN = 0x0
6253 01:00:27.207655 WORK_FSP = 0x0
6254 01:00:27.207737 WL = 0x2
6255 01:00:27.211168 RL = 0x2
6256 01:00:27.211250 BL = 0x2
6257 01:00:27.214246 RPST = 0x0
6258 01:00:27.214328 RD_PRE = 0x0
6259 01:00:27.217363 WR_PRE = 0x1
6260 01:00:27.217471 WR_PST = 0x0
6261 01:00:27.220783 DBI_WR = 0x0
6262 01:00:27.220865 DBI_RD = 0x0
6263 01:00:27.224322 OTF = 0x1
6264 01:00:27.227560 ===================================
6265 01:00:27.234084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6266 01:00:27.237532 nWR fixed to 30
6267 01:00:27.240702 [ModeRegInit_LP4] CH0 RK0
6268 01:00:27.240784 [ModeRegInit_LP4] CH0 RK1
6269 01:00:27.243977 [ModeRegInit_LP4] CH1 RK0
6270 01:00:27.247323 [ModeRegInit_LP4] CH1 RK1
6271 01:00:27.247404 match AC timing 19
6272 01:00:27.254236 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6273 01:00:27.257327 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6274 01:00:27.260550 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6275 01:00:27.267285 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6276 01:00:27.270558 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6277 01:00:27.270640 ==
6278 01:00:27.273777 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 01:00:27.277212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 01:00:27.277295 ==
6281 01:00:27.283827 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6282 01:00:27.290550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6283 01:00:27.293942 [CA 0] Center 36 (8~64) winsize 57
6284 01:00:27.297195 [CA 1] Center 36 (8~64) winsize 57
6285 01:00:27.300443 [CA 2] Center 36 (8~64) winsize 57
6286 01:00:27.304090 [CA 3] Center 36 (8~64) winsize 57
6287 01:00:27.304172 [CA 4] Center 36 (8~64) winsize 57
6288 01:00:27.307289 [CA 5] Center 36 (8~64) winsize 57
6289 01:00:27.307371
6290 01:00:27.313863 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6291 01:00:27.313945
6292 01:00:27.317127 [CATrainingPosCal] consider 1 rank data
6293 01:00:27.320222 u2DelayCellTimex100 = 270/100 ps
6294 01:00:27.323514 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 01:00:27.326991 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 01:00:27.330371 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 01:00:27.333758 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 01:00:27.336945 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 01:00:27.340123 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 01:00:27.340206
6301 01:00:27.343408 CA PerBit enable=1, Macro0, CA PI delay=36
6302 01:00:27.343490
6303 01:00:27.346762 [CBTSetCACLKResult] CA Dly = 36
6304 01:00:27.350340 CS Dly: 1 (0~32)
6305 01:00:27.350421 ==
6306 01:00:27.353603 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 01:00:27.356812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 01:00:27.356894 ==
6309 01:00:27.363499 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6310 01:00:27.370184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6311 01:00:27.373391 [CA 0] Center 36 (8~64) winsize 57
6312 01:00:27.373533 [CA 1] Center 36 (8~64) winsize 57
6313 01:00:27.376585 [CA 2] Center 36 (8~64) winsize 57
6314 01:00:27.379950 [CA 3] Center 36 (8~64) winsize 57
6315 01:00:27.383308 [CA 4] Center 36 (8~64) winsize 57
6316 01:00:27.386485 [CA 5] Center 36 (8~64) winsize 57
6317 01:00:27.386567
6318 01:00:27.389980 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6319 01:00:27.390062
6320 01:00:27.393248 [CATrainingPosCal] consider 2 rank data
6321 01:00:27.396444 u2DelayCellTimex100 = 270/100 ps
6322 01:00:27.399746 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 01:00:27.406206 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 01:00:27.409508 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 01:00:27.412895 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 01:00:27.416217 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 01:00:27.419350 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 01:00:27.419432
6329 01:00:27.422579 CA PerBit enable=1, Macro0, CA PI delay=36
6330 01:00:27.422661
6331 01:00:27.426061 [CBTSetCACLKResult] CA Dly = 36
6332 01:00:27.429104 CS Dly: 1 (0~32)
6333 01:00:27.429185
6334 01:00:27.432644 ----->DramcWriteLeveling(PI) begin...
6335 01:00:27.432753 ==
6336 01:00:27.436032 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 01:00:27.439163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 01:00:27.439246 ==
6339 01:00:27.442436 Write leveling (Byte 0): 40 => 8
6340 01:00:27.445751 Write leveling (Byte 1): 40 => 8
6341 01:00:27.448996 DramcWriteLeveling(PI) end<-----
6342 01:00:27.449078
6343 01:00:27.449142 ==
6344 01:00:27.452470 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 01:00:27.455991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 01:00:27.456077 ==
6347 01:00:27.459220 [Gating] SW mode calibration
6348 01:00:27.465645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6349 01:00:27.472136 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6350 01:00:27.475510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 01:00:27.478731 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6352 01:00:27.485757 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 01:00:27.488700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 01:00:27.492111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 01:00:27.498681 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 01:00:27.502233 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 01:00:27.505383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 01:00:27.511972 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 01:00:27.512054 Total UI for P1: 0, mck2ui 16
6360 01:00:27.518730 best dqsien dly found for B0: ( 0, 14, 24)
6361 01:00:27.518815 Total UI for P1: 0, mck2ui 16
6362 01:00:27.525511 best dqsien dly found for B1: ( 0, 14, 24)
6363 01:00:27.528631 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6364 01:00:27.532318 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6365 01:00:27.532399
6366 01:00:27.535336 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 01:00:27.538571 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6368 01:00:27.542120 [Gating] SW calibration Done
6369 01:00:27.542202 ==
6370 01:00:27.545221 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 01:00:27.548447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 01:00:27.548521 ==
6373 01:00:27.551958 RX Vref Scan: 0
6374 01:00:27.552039
6375 01:00:27.552102 RX Vref 0 -> 0, step: 1
6376 01:00:27.552161
6377 01:00:27.555033 RX Delay -410 -> 252, step: 16
6378 01:00:27.561585 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6379 01:00:27.565173 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6380 01:00:27.568245 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6381 01:00:27.571515 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6382 01:00:27.578194 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6383 01:00:27.581738 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6384 01:00:27.584964 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6385 01:00:27.588395 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6386 01:00:27.595207 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6387 01:00:27.598159 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6388 01:00:27.601673 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6389 01:00:27.604906 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6390 01:00:27.611265 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6391 01:00:27.614711 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6392 01:00:27.617925 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6393 01:00:27.624541 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6394 01:00:27.624623 ==
6395 01:00:27.627826 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 01:00:27.631017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 01:00:27.631098 ==
6398 01:00:27.631163 DQS Delay:
6399 01:00:27.634237 DQS0 = 59, DQS1 = 59
6400 01:00:27.634317 DQM Delay:
6401 01:00:27.637894 DQM0 = 18, DQM1 = 10
6402 01:00:27.637974 DQ Delay:
6403 01:00:27.641114 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6404 01:00:27.644293 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6405 01:00:27.647796 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6406 01:00:27.650856 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6407 01:00:27.650937
6408 01:00:27.651000
6409 01:00:27.651057 ==
6410 01:00:27.654418 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 01:00:27.657761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 01:00:27.657843 ==
6413 01:00:27.657907
6414 01:00:27.657966
6415 01:00:27.660907 TX Vref Scan disable
6416 01:00:27.664282 == TX Byte 0 ==
6417 01:00:27.667762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 01:00:27.671137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 01:00:27.671219 == TX Byte 1 ==
6420 01:00:27.677510 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 01:00:27.680772 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 01:00:27.680845 ==
6423 01:00:27.684204 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 01:00:27.687562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 01:00:27.687644 ==
6426 01:00:27.687707
6427 01:00:27.687766
6428 01:00:27.690768 TX Vref Scan disable
6429 01:00:27.693940 == TX Byte 0 ==
6430 01:00:27.697262 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 01:00:27.700918 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 01:00:27.704240 == TX Byte 1 ==
6433 01:00:27.707412 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 01:00:27.710645 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 01:00:27.710726
6436 01:00:27.710790 [DATLAT]
6437 01:00:27.714063 Freq=400, CH0 RK0
6438 01:00:27.714144
6439 01:00:27.714208 DATLAT Default: 0xf
6440 01:00:27.717248 0, 0xFFFF, sum = 0
6441 01:00:27.720474 1, 0xFFFF, sum = 0
6442 01:00:27.720558 2, 0xFFFF, sum = 0
6443 01:00:27.724043 3, 0xFFFF, sum = 0
6444 01:00:27.724126 4, 0xFFFF, sum = 0
6445 01:00:27.727062 5, 0xFFFF, sum = 0
6446 01:00:27.727144 6, 0xFFFF, sum = 0
6447 01:00:27.730456 7, 0xFFFF, sum = 0
6448 01:00:27.730538 8, 0xFFFF, sum = 0
6449 01:00:27.733943 9, 0xFFFF, sum = 0
6450 01:00:27.734024 10, 0xFFFF, sum = 0
6451 01:00:27.737112 11, 0xFFFF, sum = 0
6452 01:00:27.737193 12, 0xFFFF, sum = 0
6453 01:00:27.740407 13, 0x0, sum = 1
6454 01:00:27.740489 14, 0x0, sum = 2
6455 01:00:27.743588 15, 0x0, sum = 3
6456 01:00:27.743670 16, 0x0, sum = 4
6457 01:00:27.747228 best_step = 14
6458 01:00:27.747309
6459 01:00:27.747372 ==
6460 01:00:27.750322 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 01:00:27.753854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 01:00:27.753935 ==
6463 01:00:27.756817 RX Vref Scan: 1
6464 01:00:27.756898
6465 01:00:27.756961 RX Vref 0 -> 0, step: 1
6466 01:00:27.757021
6467 01:00:27.760293 RX Delay -359 -> 252, step: 8
6468 01:00:27.760374
6469 01:00:27.763482 Set Vref, RX VrefLevel [Byte0]: 59
6470 01:00:27.766911 [Byte1]: 56
6471 01:00:27.771239
6472 01:00:27.771320 Final RX Vref Byte 0 = 59 to rank0
6473 01:00:27.774568 Final RX Vref Byte 1 = 56 to rank0
6474 01:00:27.778002 Final RX Vref Byte 0 = 59 to rank1
6475 01:00:27.781458 Final RX Vref Byte 1 = 56 to rank1==
6476 01:00:27.784490 Dram Type= 6, Freq= 0, CH_0, rank 0
6477 01:00:27.791247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 01:00:27.791330 ==
6479 01:00:27.791395 DQS Delay:
6480 01:00:27.794458 DQS0 = 60, DQS1 = 68
6481 01:00:27.794539 DQM Delay:
6482 01:00:27.794604 DQM0 = 14, DQM1 = 14
6483 01:00:27.797652 DQ Delay:
6484 01:00:27.801019 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6485 01:00:27.804736 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6486 01:00:27.804818 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6487 01:00:27.807912 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6488 01:00:27.811118
6489 01:00:27.811200
6490 01:00:27.817680 [DQSOSCAuto] RK0, (LSB)MR18= 0x8583, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6491 01:00:27.821166 CH0 RK0: MR19=C0C, MR18=8583
6492 01:00:27.827657 CH0_RK0: MR19=0xC0C, MR18=0x8583, DQSOSC=393, MR23=63, INC=382, DEC=254
6493 01:00:27.827741 ==
6494 01:00:27.831104 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 01:00:27.834418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 01:00:27.834502 ==
6497 01:00:27.837673 [Gating] SW mode calibration
6498 01:00:27.844129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6499 01:00:27.850930 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6500 01:00:27.854261 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 01:00:27.857613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 01:00:27.864171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 01:00:27.867333 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 01:00:27.870552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 01:00:27.877399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 01:00:27.880444 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 01:00:27.884133 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 01:00:27.890620 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 01:00:27.890703 Total UI for P1: 0, mck2ui 16
6510 01:00:27.897112 best dqsien dly found for B0: ( 0, 14, 24)
6511 01:00:27.897195 Total UI for P1: 0, mck2ui 16
6512 01:00:27.900432 best dqsien dly found for B1: ( 0, 14, 24)
6513 01:00:27.907078 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6514 01:00:27.910313 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6515 01:00:27.910396
6516 01:00:27.913700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 01:00:27.917212 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6518 01:00:27.920255 [Gating] SW calibration Done
6519 01:00:27.920338 ==
6520 01:00:27.923898 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 01:00:27.927169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 01:00:27.927252 ==
6523 01:00:27.930521 RX Vref Scan: 0
6524 01:00:27.930603
6525 01:00:27.930668 RX Vref 0 -> 0, step: 1
6526 01:00:27.930729
6527 01:00:27.933720 RX Delay -410 -> 252, step: 16
6528 01:00:27.940249 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6529 01:00:27.943456 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6530 01:00:27.946777 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6531 01:00:27.950268 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6532 01:00:27.956633 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6533 01:00:27.960150 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6534 01:00:27.963704 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6535 01:00:27.966872 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6536 01:00:27.973505 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6537 01:00:27.976930 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6538 01:00:27.980153 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6539 01:00:27.983518 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6540 01:00:27.990211 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6541 01:00:27.993434 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6542 01:00:27.996804 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6543 01:00:28.000142 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6544 01:00:28.003389 ==
6545 01:00:28.006756 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 01:00:28.010230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 01:00:28.010624 ==
6548 01:00:28.010937 DQS Delay:
6549 01:00:28.013574 DQS0 = 59, DQS1 = 59
6550 01:00:28.014025 DQM Delay:
6551 01:00:28.016918 DQM0 = 16, DQM1 = 10
6552 01:00:28.017623 DQ Delay:
6553 01:00:28.020178 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6554 01:00:28.023552 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6555 01:00:28.026880 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6556 01:00:28.030058 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6557 01:00:28.030524
6558 01:00:28.030888
6559 01:00:28.031228 ==
6560 01:00:28.033356 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 01:00:28.036780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 01:00:28.037615 ==
6563 01:00:28.038124
6564 01:00:28.038476
6565 01:00:28.039726 TX Vref Scan disable
6566 01:00:28.040193 == TX Byte 0 ==
6567 01:00:28.046460 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6568 01:00:28.050023 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6569 01:00:28.050489 == TX Byte 1 ==
6570 01:00:28.056362 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6571 01:00:28.059753 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6572 01:00:28.060175 ==
6573 01:00:28.062869 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 01:00:28.066159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 01:00:28.066585 ==
6576 01:00:28.066957
6577 01:00:28.067268
6578 01:00:28.069687 TX Vref Scan disable
6579 01:00:28.072903 == TX Byte 0 ==
6580 01:00:28.076407 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6581 01:00:28.079921 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6582 01:00:28.080530 == TX Byte 1 ==
6583 01:00:28.085993 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6584 01:00:28.089379 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6585 01:00:28.089832
6586 01:00:28.090167 [DATLAT]
6587 01:00:28.093013 Freq=400, CH0 RK1
6588 01:00:28.093766
6589 01:00:28.094248 DATLAT Default: 0xe
6590 01:00:28.096068 0, 0xFFFF, sum = 0
6591 01:00:28.096498 1, 0xFFFF, sum = 0
6592 01:00:28.099190 2, 0xFFFF, sum = 0
6593 01:00:28.102486 3, 0xFFFF, sum = 0
6594 01:00:28.102911 4, 0xFFFF, sum = 0
6595 01:00:28.105963 5, 0xFFFF, sum = 0
6596 01:00:28.106396 6, 0xFFFF, sum = 0
6597 01:00:28.109133 7, 0xFFFF, sum = 0
6598 01:00:28.109573 8, 0xFFFF, sum = 0
6599 01:00:28.112585 9, 0xFFFF, sum = 0
6600 01:00:28.113042 10, 0xFFFF, sum = 0
6601 01:00:28.115898 11, 0xFFFF, sum = 0
6602 01:00:28.116357 12, 0xFFFF, sum = 0
6603 01:00:28.119208 13, 0x0, sum = 1
6604 01:00:28.119655 14, 0x0, sum = 2
6605 01:00:28.122643 15, 0x0, sum = 3
6606 01:00:28.123112 16, 0x0, sum = 4
6607 01:00:28.125690 best_step = 14
6608 01:00:28.126163
6609 01:00:28.126498 ==
6610 01:00:28.129005 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 01:00:28.132642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 01:00:28.133079 ==
6613 01:00:28.133524 RX Vref Scan: 0
6614 01:00:28.135710
6615 01:00:28.136176 RX Vref 0 -> 0, step: 1
6616 01:00:28.136616
6617 01:00:28.139240 RX Delay -359 -> 252, step: 8
6618 01:00:28.146613 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6619 01:00:28.149928 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6620 01:00:28.153261 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6621 01:00:28.156617 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6622 01:00:28.163106 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6623 01:00:28.166435 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6624 01:00:28.169837 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6625 01:00:28.173103 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6626 01:00:28.179810 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6627 01:00:28.183077 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6628 01:00:28.185950 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6629 01:00:28.192714 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6630 01:00:28.196225 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6631 01:00:28.199365 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6632 01:00:28.202593 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6633 01:00:28.209389 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6634 01:00:28.209879 ==
6635 01:00:28.212674 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 01:00:28.215853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 01:00:28.216293 ==
6638 01:00:28.216734 DQS Delay:
6639 01:00:28.219418 DQS0 = 60, DQS1 = 72
6640 01:00:28.219853 DQM Delay:
6641 01:00:28.222643 DQM0 = 11, DQM1 = 18
6642 01:00:28.223080 DQ Delay:
6643 01:00:28.225950 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6644 01:00:28.229102 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6645 01:00:28.232388 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6646 01:00:28.235915 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6647 01:00:28.236352
6648 01:00:28.236794
6649 01:00:28.242530 [DQSOSCAuto] RK1, (LSB)MR18= 0xc97d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 384 ps
6650 01:00:28.245720 CH0 RK1: MR19=C0C, MR18=C97D
6651 01:00:28.252432 CH0_RK1: MR19=0xC0C, MR18=0xC97D, DQSOSC=384, MR23=63, INC=400, DEC=267
6652 01:00:28.255793 [RxdqsGatingPostProcess] freq 400
6653 01:00:28.262302 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6654 01:00:28.265643 best DQS0 dly(2T, 0.5T) = (0, 10)
6655 01:00:28.266067 best DQS1 dly(2T, 0.5T) = (0, 10)
6656 01:00:28.269357 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6657 01:00:28.272506 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6658 01:00:28.275639 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 01:00:28.278946 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 01:00:28.282248 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 01:00:28.285806 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 01:00:28.289049 Pre-setting of DQS Precalculation
6663 01:00:28.295534 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6664 01:00:28.295959 ==
6665 01:00:28.298766 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 01:00:28.302058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 01:00:28.302553 ==
6668 01:00:28.309008 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6669 01:00:28.315345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6670 01:00:28.315785 [CA 0] Center 36 (8~64) winsize 57
6671 01:00:28.318773 [CA 1] Center 36 (8~64) winsize 57
6672 01:00:28.322279 [CA 2] Center 36 (8~64) winsize 57
6673 01:00:28.325464 [CA 3] Center 36 (8~64) winsize 57
6674 01:00:28.328657 [CA 4] Center 36 (8~64) winsize 57
6675 01:00:28.331845 [CA 5] Center 36 (8~64) winsize 57
6676 01:00:28.332282
6677 01:00:28.335469 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6678 01:00:28.335903
6679 01:00:28.338670 [CATrainingPosCal] consider 1 rank data
6680 01:00:28.342052 u2DelayCellTimex100 = 270/100 ps
6681 01:00:28.345394 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 01:00:28.348581 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 01:00:28.355078 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 01:00:28.358402 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 01:00:28.361799 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 01:00:28.365332 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 01:00:28.365796
6688 01:00:28.368514 CA PerBit enable=1, Macro0, CA PI delay=36
6689 01:00:28.368962
6690 01:00:28.371724 [CBTSetCACLKResult] CA Dly = 36
6691 01:00:28.372199 CS Dly: 1 (0~32)
6692 01:00:28.374952 ==
6693 01:00:28.378271 Dram Type= 6, Freq= 0, CH_1, rank 1
6694 01:00:28.381744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 01:00:28.382223 ==
6696 01:00:28.385123 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6697 01:00:28.391723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6698 01:00:28.394996 [CA 0] Center 36 (8~64) winsize 57
6699 01:00:28.398181 [CA 1] Center 36 (8~64) winsize 57
6700 01:00:28.401563 [CA 2] Center 36 (8~64) winsize 57
6701 01:00:28.404770 [CA 3] Center 36 (8~64) winsize 57
6702 01:00:28.408365 [CA 4] Center 36 (8~64) winsize 57
6703 01:00:28.411618 [CA 5] Center 36 (8~64) winsize 57
6704 01:00:28.412117
6705 01:00:28.414840 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6706 01:00:28.415318
6707 01:00:28.418083 [CATrainingPosCal] consider 2 rank data
6708 01:00:28.421359 u2DelayCellTimex100 = 270/100 ps
6709 01:00:28.424825 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 01:00:28.428144 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 01:00:28.431388 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 01:00:28.437761 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 01:00:28.440973 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 01:00:28.444304 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 01:00:28.444724
6716 01:00:28.447885 CA PerBit enable=1, Macro0, CA PI delay=36
6717 01:00:28.448320
6718 01:00:28.451133 [CBTSetCACLKResult] CA Dly = 36
6719 01:00:28.451554 CS Dly: 1 (0~32)
6720 01:00:28.451888
6721 01:00:28.454454 ----->DramcWriteLeveling(PI) begin...
6722 01:00:28.454884 ==
6723 01:00:28.457850 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 01:00:28.464418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 01:00:28.464844 ==
6726 01:00:28.467703 Write leveling (Byte 0): 40 => 8
6727 01:00:28.470917 Write leveling (Byte 1): 40 => 8
6728 01:00:28.471338 DramcWriteLeveling(PI) end<-----
6729 01:00:28.471670
6730 01:00:28.474425 ==
6731 01:00:28.474845 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 01:00:28.480726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 01:00:28.481357 ==
6734 01:00:28.484049 [Gating] SW mode calibration
6735 01:00:28.490841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6736 01:00:28.494249 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6737 01:00:28.500812 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 01:00:28.503967 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6739 01:00:28.507118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 01:00:28.513842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 01:00:28.517039 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 01:00:28.520666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 01:00:28.527169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 01:00:28.530416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 01:00:28.533652 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 01:00:28.537198 Total UI for P1: 0, mck2ui 16
6747 01:00:28.540365 best dqsien dly found for B0: ( 0, 14, 24)
6748 01:00:28.543680 Total UI for P1: 0, mck2ui 16
6749 01:00:28.546911 best dqsien dly found for B1: ( 0, 14, 24)
6750 01:00:28.550352 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6751 01:00:28.553631 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6752 01:00:28.554190
6753 01:00:28.560116 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 01:00:28.563382 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6755 01:00:28.566940 [Gating] SW calibration Done
6756 01:00:28.567400 ==
6757 01:00:28.570138 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 01:00:28.573389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 01:00:28.573855 ==
6760 01:00:28.574190 RX Vref Scan: 0
6761 01:00:28.574503
6762 01:00:28.576731 RX Vref 0 -> 0, step: 1
6763 01:00:28.577151
6764 01:00:28.579916 RX Delay -410 -> 252, step: 16
6765 01:00:28.583328 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6766 01:00:28.589906 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6767 01:00:28.593136 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6768 01:00:28.596823 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6769 01:00:28.599752 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6770 01:00:28.606810 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6771 01:00:28.609813 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6772 01:00:28.612970 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6773 01:00:28.616435 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6774 01:00:28.623011 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6775 01:00:28.626489 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6776 01:00:28.629602 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6777 01:00:28.632950 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6778 01:00:28.639573 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6779 01:00:28.642953 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6780 01:00:28.646271 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6781 01:00:28.646692 ==
6782 01:00:28.649669 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 01:00:28.656417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 01:00:28.656886 ==
6785 01:00:28.657256 DQS Delay:
6786 01:00:28.659632 DQS0 = 51, DQS1 = 67
6787 01:00:28.660087 DQM Delay:
6788 01:00:28.660420 DQM0 = 12, DQM1 = 19
6789 01:00:28.662934 DQ Delay:
6790 01:00:28.666141 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6791 01:00:28.666563 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6792 01:00:28.669362 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6793 01:00:28.672673 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6794 01:00:28.673095
6795 01:00:28.676421
6796 01:00:28.676858 ==
6797 01:00:28.679380 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 01:00:28.682923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 01:00:28.683348 ==
6800 01:00:28.683686
6801 01:00:28.684022
6802 01:00:28.686075 TX Vref Scan disable
6803 01:00:28.686495 == TX Byte 0 ==
6804 01:00:28.689390 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 01:00:28.695963 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 01:00:28.696386 == TX Byte 1 ==
6807 01:00:28.699171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 01:00:28.706212 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 01:00:28.706635 ==
6810 01:00:28.709554 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 01:00:28.712746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 01:00:28.713181 ==
6813 01:00:28.713549
6814 01:00:28.713868
6815 01:00:28.715926 TX Vref Scan disable
6816 01:00:28.716345 == TX Byte 0 ==
6817 01:00:28.719294 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 01:00:28.725791 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 01:00:28.726228 == TX Byte 1 ==
6820 01:00:28.729239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 01:00:28.735813 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 01:00:28.736389
6823 01:00:28.736838 [DATLAT]
6824 01:00:28.737274 Freq=400, CH1 RK0
6825 01:00:28.738996
6826 01:00:28.739443 DATLAT Default: 0xf
6827 01:00:28.742427 0, 0xFFFF, sum = 0
6828 01:00:28.742893 1, 0xFFFF, sum = 0
6829 01:00:28.745634 2, 0xFFFF, sum = 0
6830 01:00:28.746085 3, 0xFFFF, sum = 0
6831 01:00:28.748838 4, 0xFFFF, sum = 0
6832 01:00:28.749309 5, 0xFFFF, sum = 0
6833 01:00:28.752446 6, 0xFFFF, sum = 0
6834 01:00:28.752882 7, 0xFFFF, sum = 0
6835 01:00:28.755475 8, 0xFFFF, sum = 0
6836 01:00:28.755831 9, 0xFFFF, sum = 0
6837 01:00:28.758808 10, 0xFFFF, sum = 0
6838 01:00:28.759237 11, 0xFFFF, sum = 0
6839 01:00:28.762236 12, 0xFFFF, sum = 0
6840 01:00:28.762664 13, 0x0, sum = 1
6841 01:00:28.765433 14, 0x0, sum = 2
6842 01:00:28.765899 15, 0x0, sum = 3
6843 01:00:28.769003 16, 0x0, sum = 4
6844 01:00:28.769430 best_step = 14
6845 01:00:28.769799
6846 01:00:28.770161 ==
6847 01:00:28.771987 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 01:00:28.778605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 01:00:28.779028 ==
6850 01:00:28.779365 RX Vref Scan: 1
6851 01:00:28.779674
6852 01:00:28.781965 RX Vref 0 -> 0, step: 1
6853 01:00:28.782384
6854 01:00:28.785110 RX Delay -375 -> 252, step: 8
6855 01:00:28.785551
6856 01:00:28.788350 Set Vref, RX VrefLevel [Byte0]: 55
6857 01:00:28.791670 [Byte1]: 53
6858 01:00:28.795032
6859 01:00:28.795451 Final RX Vref Byte 0 = 55 to rank0
6860 01:00:28.798411 Final RX Vref Byte 1 = 53 to rank0
6861 01:00:28.801745 Final RX Vref Byte 0 = 55 to rank1
6862 01:00:28.805190 Final RX Vref Byte 1 = 53 to rank1==
6863 01:00:28.808374 Dram Type= 6, Freq= 0, CH_1, rank 0
6864 01:00:28.814901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 01:00:28.815326 ==
6866 01:00:28.815662 DQS Delay:
6867 01:00:28.818012 DQS0 = 52, DQS1 = 64
6868 01:00:28.818431 DQM Delay:
6869 01:00:28.818850 DQM0 = 9, DQM1 = 10
6870 01:00:28.821345 DQ Delay:
6871 01:00:28.824929 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6872 01:00:28.825350 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6873 01:00:28.828178 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6874 01:00:28.831496 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6875 01:00:28.831918
6876 01:00:28.834576
6877 01:00:28.841572 [DQSOSCAuto] RK0, (LSB)MR18= 0x5569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6878 01:00:28.844668 CH1 RK0: MR19=C0C, MR18=5569
6879 01:00:28.851467 CH1_RK0: MR19=0xC0C, MR18=0x5569, DQSOSC=396, MR23=63, INC=376, DEC=251
6880 01:00:28.851895 ==
6881 01:00:28.854693 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 01:00:28.857908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 01:00:28.858348 ==
6884 01:00:28.861110 [Gating] SW mode calibration
6885 01:00:28.867757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6886 01:00:28.874528 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6887 01:00:28.877949 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6888 01:00:28.881304 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6889 01:00:28.887678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 01:00:28.891123 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 01:00:28.894083 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 01:00:28.901101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 01:00:28.903923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 01:00:28.907564 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 01:00:28.913992 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 01:00:28.914421 Total UI for P1: 0, mck2ui 16
6897 01:00:28.920578 best dqsien dly found for B0: ( 0, 14, 24)
6898 01:00:28.921004 Total UI for P1: 0, mck2ui 16
6899 01:00:28.927231 best dqsien dly found for B1: ( 0, 14, 24)
6900 01:00:28.930680 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6901 01:00:28.933871 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6902 01:00:28.934342
6903 01:00:28.937104 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 01:00:28.940559 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6905 01:00:28.943885 [Gating] SW calibration Done
6906 01:00:28.944304 ==
6907 01:00:28.947135 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 01:00:28.950307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 01:00:28.950731 ==
6910 01:00:28.953559 RX Vref Scan: 0
6911 01:00:28.953979
6912 01:00:28.954309 RX Vref 0 -> 0, step: 1
6913 01:00:28.954619
6914 01:00:28.956741 RX Delay -410 -> 252, step: 16
6915 01:00:28.963668 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6916 01:00:28.966754 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6917 01:00:28.969883 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6918 01:00:28.973507 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6919 01:00:28.980117 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6920 01:00:28.983188 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6921 01:00:28.986719 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6922 01:00:28.990019 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6923 01:00:28.996569 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6924 01:00:29.000163 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6925 01:00:29.003368 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6926 01:00:29.006544 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6927 01:00:29.013081 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6928 01:00:29.016274 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6929 01:00:29.019717 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6930 01:00:29.026564 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6931 01:00:29.026991 ==
6932 01:00:29.029556 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 01:00:29.033051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 01:00:29.033512 ==
6935 01:00:29.033866 DQS Delay:
6936 01:00:29.036216 DQS0 = 59, DQS1 = 67
6937 01:00:29.036640 DQM Delay:
6938 01:00:29.039481 DQM0 = 19, DQM1 = 21
6939 01:00:29.039900 DQ Delay:
6940 01:00:29.042866 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6941 01:00:29.046492 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6942 01:00:29.049368 DQ8 =0, DQ9 =16, DQ10 =24, DQ11 =16
6943 01:00:29.052596 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6944 01:00:29.053030
6945 01:00:29.053360
6946 01:00:29.053729 ==
6947 01:00:29.055867 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 01:00:29.059165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 01:00:29.059588 ==
6950 01:00:29.059939
6951 01:00:29.062636
6952 01:00:29.063055 TX Vref Scan disable
6953 01:00:29.065883 == TX Byte 0 ==
6954 01:00:29.069218 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6955 01:00:29.072715 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6956 01:00:29.075868 == TX Byte 1 ==
6957 01:00:29.079341 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6958 01:00:29.082578 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6959 01:00:29.083000 ==
6960 01:00:29.085883 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 01:00:29.089110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 01:00:29.092345 ==
6963 01:00:29.092762
6964 01:00:29.093092
6965 01:00:29.093400 TX Vref Scan disable
6966 01:00:29.095861 == TX Byte 0 ==
6967 01:00:29.098923 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6968 01:00:29.102559 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6969 01:00:29.105822 == TX Byte 1 ==
6970 01:00:29.108985 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6971 01:00:29.112177 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6972 01:00:29.112606
6973 01:00:29.112941 [DATLAT]
6974 01:00:29.115388 Freq=400, CH1 RK1
6975 01:00:29.115809
6976 01:00:29.118787 DATLAT Default: 0xe
6977 01:00:29.119365 0, 0xFFFF, sum = 0
6978 01:00:29.122076 1, 0xFFFF, sum = 0
6979 01:00:29.122509 2, 0xFFFF, sum = 0
6980 01:00:29.125311 3, 0xFFFF, sum = 0
6981 01:00:29.125785 4, 0xFFFF, sum = 0
6982 01:00:29.128559 5, 0xFFFF, sum = 0
6983 01:00:29.128993 6, 0xFFFF, sum = 0
6984 01:00:29.131839 7, 0xFFFF, sum = 0
6985 01:00:29.132318 8, 0xFFFF, sum = 0
6986 01:00:29.135425 9, 0xFFFF, sum = 0
6987 01:00:29.135885 10, 0xFFFF, sum = 0
6988 01:00:29.138481 11, 0xFFFF, sum = 0
6989 01:00:29.138914 12, 0xFFFF, sum = 0
6990 01:00:29.141779 13, 0x0, sum = 1
6991 01:00:29.142208 14, 0x0, sum = 2
6992 01:00:29.145353 15, 0x0, sum = 3
6993 01:00:29.145848 16, 0x0, sum = 4
6994 01:00:29.148653 best_step = 14
6995 01:00:29.149073
6996 01:00:29.149421 ==
6997 01:00:29.151817 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 01:00:29.155073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 01:00:29.155502 ==
7000 01:00:29.158271 RX Vref Scan: 0
7001 01:00:29.158694
7002 01:00:29.159025 RX Vref 0 -> 0, step: 1
7003 01:00:29.159338
7004 01:00:29.161601 RX Delay -375 -> 252, step: 8
7005 01:00:29.169925 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7006 01:00:29.173032 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7007 01:00:29.176401 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7008 01:00:29.183250 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7009 01:00:29.186348 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7010 01:00:29.189523 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7011 01:00:29.192883 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7012 01:00:29.199633 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7013 01:00:29.202897 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7014 01:00:29.206072 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7015 01:00:29.209395 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7016 01:00:29.216012 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
7017 01:00:29.219169 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7018 01:00:29.222787 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7019 01:00:29.225908 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7020 01:00:29.232818 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7021 01:00:29.233262 ==
7022 01:00:29.235960 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 01:00:29.239292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 01:00:29.239736 ==
7025 01:00:29.240180 DQS Delay:
7026 01:00:29.242778 DQS0 = 60, DQS1 = 64
7027 01:00:29.243217 DQM Delay:
7028 01:00:29.246034 DQM0 = 12, DQM1 = 11
7029 01:00:29.246471 DQ Delay:
7030 01:00:29.249329 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7031 01:00:29.252488 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7032 01:00:29.255719 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7033 01:00:29.259118 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7034 01:00:29.259558
7035 01:00:29.260006
7036 01:00:29.265702 [DQSOSCAuto] RK1, (LSB)MR18= 0x7dad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7037 01:00:29.269009 CH1 RK1: MR19=C0C, MR18=7DAD
7038 01:00:29.275779 CH1_RK1: MR19=0xC0C, MR18=0x7DAD, DQSOSC=388, MR23=63, INC=392, DEC=261
7039 01:00:29.279075 [RxdqsGatingPostProcess] freq 400
7040 01:00:29.285603 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7041 01:00:29.288733 best DQS0 dly(2T, 0.5T) = (0, 10)
7042 01:00:29.292095 best DQS1 dly(2T, 0.5T) = (0, 10)
7043 01:00:29.295290 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7044 01:00:29.298765 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7045 01:00:29.299206 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 01:00:29.302228 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 01:00:29.305465 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 01:00:29.308647 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 01:00:29.312033 Pre-setting of DQS Precalculation
7050 01:00:29.318885 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7051 01:00:29.325253 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7052 01:00:29.331860 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7053 01:00:29.332289
7054 01:00:29.332624
7055 01:00:29.334987 [Calibration Summary] 800 Mbps
7056 01:00:29.335440 CH 0, Rank 0
7057 01:00:29.338551 SW Impedance : PASS
7058 01:00:29.341765 DUTY Scan : NO K
7059 01:00:29.342193 ZQ Calibration : PASS
7060 01:00:29.344941 Jitter Meter : NO K
7061 01:00:29.348426 CBT Training : PASS
7062 01:00:29.348859 Write leveling : PASS
7063 01:00:29.351638 RX DQS gating : PASS
7064 01:00:29.354806 RX DQ/DQS(RDDQC) : PASS
7065 01:00:29.355229 TX DQ/DQS : PASS
7066 01:00:29.358031 RX DATLAT : PASS
7067 01:00:29.361378 RX DQ/DQS(Engine): PASS
7068 01:00:29.361848 TX OE : NO K
7069 01:00:29.364857 All Pass.
7070 01:00:29.365280
7071 01:00:29.365661 CH 0, Rank 1
7072 01:00:29.368032 SW Impedance : PASS
7073 01:00:29.368460 DUTY Scan : NO K
7074 01:00:29.371379 ZQ Calibration : PASS
7075 01:00:29.374638 Jitter Meter : NO K
7076 01:00:29.375067 CBT Training : PASS
7077 01:00:29.378288 Write leveling : NO K
7078 01:00:29.378714 RX DQS gating : PASS
7079 01:00:29.381468 RX DQ/DQS(RDDQC) : PASS
7080 01:00:29.384653 TX DQ/DQS : PASS
7081 01:00:29.385081 RX DATLAT : PASS
7082 01:00:29.388210 RX DQ/DQS(Engine): PASS
7083 01:00:29.391298 TX OE : NO K
7084 01:00:29.391724 All Pass.
7085 01:00:29.392063
7086 01:00:29.392375 CH 1, Rank 0
7087 01:00:29.394687 SW Impedance : PASS
7088 01:00:29.398179 DUTY Scan : NO K
7089 01:00:29.398604 ZQ Calibration : PASS
7090 01:00:29.401307 Jitter Meter : NO K
7091 01:00:29.404801 CBT Training : PASS
7092 01:00:29.405226 Write leveling : PASS
7093 01:00:29.407735 RX DQS gating : PASS
7094 01:00:29.411341 RX DQ/DQS(RDDQC) : PASS
7095 01:00:29.411767 TX DQ/DQS : PASS
7096 01:00:29.414593 RX DATLAT : PASS
7097 01:00:29.417970 RX DQ/DQS(Engine): PASS
7098 01:00:29.418394 TX OE : NO K
7099 01:00:29.421217 All Pass.
7100 01:00:29.421882
7101 01:00:29.422244 CH 1, Rank 1
7102 01:00:29.424484 SW Impedance : PASS
7103 01:00:29.424912 DUTY Scan : NO K
7104 01:00:29.427632 ZQ Calibration : PASS
7105 01:00:29.431002 Jitter Meter : NO K
7106 01:00:29.431443 CBT Training : PASS
7107 01:00:29.434486 Write leveling : NO K
7108 01:00:29.437811 RX DQS gating : PASS
7109 01:00:29.438289 RX DQ/DQS(RDDQC) : PASS
7110 01:00:29.441108 TX DQ/DQS : PASS
7111 01:00:29.441699 RX DATLAT : PASS
7112 01:00:29.444186 RX DQ/DQS(Engine): PASS
7113 01:00:29.447888 TX OE : NO K
7114 01:00:29.448316 All Pass.
7115 01:00:29.448653
7116 01:00:29.451425 DramC Write-DBI off
7117 01:00:29.451850 PER_BANK_REFRESH: Hybrid Mode
7118 01:00:29.454217 TX_TRACKING: ON
7119 01:00:29.464371 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7120 01:00:29.467501 [FAST_K] Save calibration result to emmc
7121 01:00:29.470868 dramc_set_vcore_voltage set vcore to 725000
7122 01:00:29.471295 Read voltage for 1600, 0
7123 01:00:29.474232 Vio18 = 0
7124 01:00:29.474659 Vcore = 725000
7125 01:00:29.474991 Vdram = 0
7126 01:00:29.477574 Vddq = 0
7127 01:00:29.478002 Vmddr = 0
7128 01:00:29.483965 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7129 01:00:29.487387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7130 01:00:29.491081 MEM_TYPE=3, freq_sel=13
7131 01:00:29.494304 sv_algorithm_assistance_LP4_3733
7132 01:00:29.497525 ============ PULL DRAM RESETB DOWN ============
7133 01:00:29.500575 ========== PULL DRAM RESETB DOWN end =========
7134 01:00:29.507310 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7135 01:00:29.510598 ===================================
7136 01:00:29.511025 LPDDR4 DRAM CONFIGURATION
7137 01:00:29.513869 ===================================
7138 01:00:29.517030 EX_ROW_EN[0] = 0x0
7139 01:00:29.520268 EX_ROW_EN[1] = 0x0
7140 01:00:29.520694 LP4Y_EN = 0x0
7141 01:00:29.523795 WORK_FSP = 0x1
7142 01:00:29.524223 WL = 0x5
7143 01:00:29.526932 RL = 0x5
7144 01:00:29.527361 BL = 0x2
7145 01:00:29.530242 RPST = 0x0
7146 01:00:29.530687 RD_PRE = 0x0
7147 01:00:29.533551 WR_PRE = 0x1
7148 01:00:29.533979 WR_PST = 0x1
7149 01:00:29.536854 DBI_WR = 0x0
7150 01:00:29.537278 DBI_RD = 0x0
7151 01:00:29.540353 OTF = 0x1
7152 01:00:29.543602 ===================================
7153 01:00:29.546771 ===================================
7154 01:00:29.547197 ANA top config
7155 01:00:29.550052 ===================================
7156 01:00:29.553435 DLL_ASYNC_EN = 0
7157 01:00:29.556657 ALL_SLAVE_EN = 0
7158 01:00:29.559931 NEW_RANK_MODE = 1
7159 01:00:29.560359 DLL_IDLE_MODE = 1
7160 01:00:29.563437 LP45_APHY_COMB_EN = 1
7161 01:00:29.566752 TX_ODT_DIS = 0
7162 01:00:29.569972 NEW_8X_MODE = 1
7163 01:00:29.573163 ===================================
7164 01:00:29.576484 ===================================
7165 01:00:29.579748 data_rate = 3200
7166 01:00:29.580174 CKR = 1
7167 01:00:29.583208 DQ_P2S_RATIO = 8
7168 01:00:29.586381 ===================================
7169 01:00:29.589724 CA_P2S_RATIO = 8
7170 01:00:29.593277 DQ_CA_OPEN = 0
7171 01:00:29.596578 DQ_SEMI_OPEN = 0
7172 01:00:29.599790 CA_SEMI_OPEN = 0
7173 01:00:29.600217 CA_FULL_RATE = 0
7174 01:00:29.602959 DQ_CKDIV4_EN = 0
7175 01:00:29.606141 CA_CKDIV4_EN = 0
7176 01:00:29.609717 CA_PREDIV_EN = 0
7177 01:00:29.612815 PH8_DLY = 12
7178 01:00:29.616301 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7179 01:00:29.616732 DQ_AAMCK_DIV = 4
7180 01:00:29.619399 CA_AAMCK_DIV = 4
7181 01:00:29.622760 CA_ADMCK_DIV = 4
7182 01:00:29.626443 DQ_TRACK_CA_EN = 0
7183 01:00:29.629606 CA_PICK = 1600
7184 01:00:29.632771 CA_MCKIO = 1600
7185 01:00:29.636190 MCKIO_SEMI = 0
7186 01:00:29.639562 PLL_FREQ = 3068
7187 01:00:29.639992 DQ_UI_PI_RATIO = 32
7188 01:00:29.642705 CA_UI_PI_RATIO = 0
7189 01:00:29.645919 ===================================
7190 01:00:29.649380 ===================================
7191 01:00:29.652787 memory_type:LPDDR4
7192 01:00:29.655936 GP_NUM : 10
7193 01:00:29.656361 SRAM_EN : 1
7194 01:00:29.659119 MD32_EN : 0
7195 01:00:29.662401 ===================================
7196 01:00:29.665950 [ANA_INIT] >>>>>>>>>>>>>>
7197 01:00:29.666374 <<<<<< [CONFIGURE PHASE]: ANA_TX
7198 01:00:29.669048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7199 01:00:29.672380 ===================================
7200 01:00:29.675656 data_rate = 3200,PCW = 0X7600
7201 01:00:29.679269 ===================================
7202 01:00:29.682642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7203 01:00:29.689068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 01:00:29.695824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7205 01:00:29.699298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7206 01:00:29.702398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7207 01:00:29.705537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7208 01:00:29.708723 [ANA_INIT] flow start
7209 01:00:29.709150 [ANA_INIT] PLL >>>>>>>>
7210 01:00:29.712160 [ANA_INIT] PLL <<<<<<<<
7211 01:00:29.715489 [ANA_INIT] MIDPI >>>>>>>>
7212 01:00:29.718688 [ANA_INIT] MIDPI <<<<<<<<
7213 01:00:29.719111 [ANA_INIT] DLL >>>>>>>>
7214 01:00:29.721951 [ANA_INIT] DLL <<<<<<<<
7215 01:00:29.722370 [ANA_INIT] flow end
7216 01:00:29.728529 ============ LP4 DIFF to SE enter ============
7217 01:00:29.732026 ============ LP4 DIFF to SE exit ============
7218 01:00:29.735188 [ANA_INIT] <<<<<<<<<<<<<
7219 01:00:29.738402 [Flow] Enable top DCM control >>>>>
7220 01:00:29.741657 [Flow] Enable top DCM control <<<<<
7221 01:00:29.744986 Enable DLL master slave shuffle
7222 01:00:29.748584 ==============================================================
7223 01:00:29.751749 Gating Mode config
7224 01:00:29.755074 ==============================================================
7225 01:00:29.758249 Config description:
7226 01:00:29.768309 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7227 01:00:29.774665 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7228 01:00:29.778060 SELPH_MODE 0: By rank 1: By Phase
7229 01:00:29.784688 ==============================================================
7230 01:00:29.787952 GAT_TRACK_EN = 1
7231 01:00:29.791262 RX_GATING_MODE = 2
7232 01:00:29.794653 RX_GATING_TRACK_MODE = 2
7233 01:00:29.797905 SELPH_MODE = 1
7234 01:00:29.801454 PICG_EARLY_EN = 1
7235 01:00:29.804449 VALID_LAT_VALUE = 1
7236 01:00:29.807831 ==============================================================
7237 01:00:29.811308 Enter into Gating configuration >>>>
7238 01:00:29.814643 Exit from Gating configuration <<<<
7239 01:00:29.817909 Enter into DVFS_PRE_config >>>>>
7240 01:00:29.827814 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7241 01:00:29.831440 Exit from DVFS_PRE_config <<<<<
7242 01:00:29.834478 Enter into PICG configuration >>>>
7243 01:00:29.837945 Exit from PICG configuration <<<<
7244 01:00:29.841239 [RX_INPUT] configuration >>>>>
7245 01:00:29.844473 [RX_INPUT] configuration <<<<<
7246 01:00:29.851066 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7247 01:00:29.854468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7248 01:00:29.860906 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 01:00:29.867492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 01:00:29.873961 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 01:00:29.880851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 01:00:29.883989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7253 01:00:29.887390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7254 01:00:29.890782 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7255 01:00:29.897343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7256 01:00:29.900591 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7257 01:00:29.903896 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 01:00:29.907286 ===================================
7259 01:00:29.910727 LPDDR4 DRAM CONFIGURATION
7260 01:00:29.913913 ===================================
7261 01:00:29.914337 EX_ROW_EN[0] = 0x0
7262 01:00:29.917377 EX_ROW_EN[1] = 0x0
7263 01:00:29.920630 LP4Y_EN = 0x0
7264 01:00:29.921049 WORK_FSP = 0x1
7265 01:00:29.923876 WL = 0x5
7266 01:00:29.924298 RL = 0x5
7267 01:00:29.927309 BL = 0x2
7268 01:00:29.927731 RPST = 0x0
7269 01:00:29.930517 RD_PRE = 0x0
7270 01:00:29.930935 WR_PRE = 0x1
7271 01:00:29.933800 WR_PST = 0x1
7272 01:00:29.934359 DBI_WR = 0x0
7273 01:00:29.937044 DBI_RD = 0x0
7274 01:00:29.937465 OTF = 0x1
7275 01:00:29.940445 ===================================
7276 01:00:29.943743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7277 01:00:29.950379 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7278 01:00:29.953438 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7279 01:00:29.957007 ===================================
7280 01:00:29.960215 LPDDR4 DRAM CONFIGURATION
7281 01:00:29.963565 ===================================
7282 01:00:29.963986 EX_ROW_EN[0] = 0x10
7283 01:00:29.966752 EX_ROW_EN[1] = 0x0
7284 01:00:29.970129 LP4Y_EN = 0x0
7285 01:00:29.970547 WORK_FSP = 0x1
7286 01:00:29.973363 WL = 0x5
7287 01:00:29.973844 RL = 0x5
7288 01:00:29.976654 BL = 0x2
7289 01:00:29.977075 RPST = 0x0
7290 01:00:29.980232 RD_PRE = 0x0
7291 01:00:29.980653 WR_PRE = 0x1
7292 01:00:29.983518 WR_PST = 0x1
7293 01:00:29.983984 DBI_WR = 0x0
7294 01:00:29.986754 DBI_RD = 0x0
7295 01:00:29.987175 OTF = 0x1
7296 01:00:29.989982 ===================================
7297 01:00:29.996513 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7298 01:00:29.996935 ==
7299 01:00:30.000040 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 01:00:30.003129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 01:00:30.006602 ==
7302 01:00:30.007020 [Duty_Offset_Calibration]
7303 01:00:30.009767 B0:2 B1:0 CA:3
7304 01:00:30.010187
7305 01:00:30.013099 [DutyScan_Calibration_Flow] k_type=0
7306 01:00:30.021803
7307 01:00:30.022222 ==CLK 0==
7308 01:00:30.025081 Final CLK duty delay cell = 0
7309 01:00:30.028722 [0] MAX Duty = 5031%(X100), DQS PI = 12
7310 01:00:30.031983 [0] MIN Duty = 4907%(X100), DQS PI = 6
7311 01:00:30.032406 [0] AVG Duty = 4969%(X100)
7312 01:00:30.035420
7313 01:00:30.035841 CH0 CLK Duty spec in!! Max-Min= 124%
7314 01:00:30.041896 [DutyScan_Calibration_Flow] ====Done====
7315 01:00:30.042318
7316 01:00:30.045098 [DutyScan_Calibration_Flow] k_type=1
7317 01:00:30.061712
7318 01:00:30.062129 ==DQS 0 ==
7319 01:00:30.064858 Final DQS duty delay cell = 0
7320 01:00:30.068261 [0] MAX Duty = 5125%(X100), DQS PI = 30
7321 01:00:30.071430 [0] MIN Duty = 4875%(X100), DQS PI = 50
7322 01:00:30.074694 [0] AVG Duty = 5000%(X100)
7323 01:00:30.075116
7324 01:00:30.075448 ==DQS 1 ==
7325 01:00:30.078009 Final DQS duty delay cell = 0
7326 01:00:30.081346 [0] MAX Duty = 5156%(X100), DQS PI = 32
7327 01:00:30.084860 [0] MIN Duty = 5062%(X100), DQS PI = 0
7328 01:00:30.088115 [0] AVG Duty = 5109%(X100)
7329 01:00:30.088534
7330 01:00:30.091415 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7331 01:00:30.091835
7332 01:00:30.094874 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7333 01:00:30.097997 [DutyScan_Calibration_Flow] ====Done====
7334 01:00:30.098417
7335 01:00:30.101186 [DutyScan_Calibration_Flow] k_type=3
7336 01:00:30.119490
7337 01:00:30.119910 ==DQM 0 ==
7338 01:00:30.122628 Final DQM duty delay cell = 0
7339 01:00:30.125969 [0] MAX Duty = 5156%(X100), DQS PI = 30
7340 01:00:30.129399 [0] MIN Duty = 4875%(X100), DQS PI = 0
7341 01:00:30.132576 [0] AVG Duty = 5015%(X100)
7342 01:00:30.133003
7343 01:00:30.133339 ==DQM 1 ==
7344 01:00:30.136094 Final DQM duty delay cell = 4
7345 01:00:30.139392 [4] MAX Duty = 5187%(X100), DQS PI = 62
7346 01:00:30.142506 [4] MIN Duty = 5000%(X100), DQS PI = 12
7347 01:00:30.145747 [4] AVG Duty = 5093%(X100)
7348 01:00:30.146168
7349 01:00:30.148981 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7350 01:00:30.149405
7351 01:00:30.152432 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7352 01:00:30.155682 [DutyScan_Calibration_Flow] ====Done====
7353 01:00:30.156104
7354 01:00:30.158919 [DutyScan_Calibration_Flow] k_type=2
7355 01:00:30.175642
7356 01:00:30.176063 ==DQ 0 ==
7357 01:00:30.178865 Final DQ duty delay cell = -4
7358 01:00:30.182094 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7359 01:00:30.185297 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7360 01:00:30.188613 [-4] AVG Duty = 4938%(X100)
7361 01:00:30.189050
7362 01:00:30.189377 ==DQ 1 ==
7363 01:00:30.192294 Final DQ duty delay cell = 0
7364 01:00:30.195495 [0] MAX Duty = 5156%(X100), DQS PI = 58
7365 01:00:30.198690 [0] MIN Duty = 5000%(X100), DQS PI = 16
7366 01:00:30.201997 [0] AVG Duty = 5078%(X100)
7367 01:00:30.202463
7368 01:00:30.205334 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7369 01:00:30.205809
7370 01:00:30.208774 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7371 01:00:30.212004 [DutyScan_Calibration_Flow] ====Done====
7372 01:00:30.212445 ==
7373 01:00:30.215474 Dram Type= 6, Freq= 0, CH_1, rank 0
7374 01:00:30.218632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7375 01:00:30.219052 ==
7376 01:00:30.222028 [Duty_Offset_Calibration]
7377 01:00:30.222441 B0:1 B1:-2 CA:0
7378 01:00:30.222770
7379 01:00:30.225282 [DutyScan_Calibration_Flow] k_type=0
7380 01:00:30.236045
7381 01:00:30.236458 ==CLK 0==
7382 01:00:30.239255 Final CLK duty delay cell = 0
7383 01:00:30.242919 [0] MAX Duty = 5031%(X100), DQS PI = 0
7384 01:00:30.246170 [0] MIN Duty = 4876%(X100), DQS PI = 12
7385 01:00:30.246613 [0] AVG Duty = 4953%(X100)
7386 01:00:30.247066
7387 01:00:30.249427 CH1 CLK Duty spec in!! Max-Min= 155%
7388 01:00:30.255876 [DutyScan_Calibration_Flow] ====Done====
7389 01:00:30.256293
7390 01:00:30.259234 [DutyScan_Calibration_Flow] k_type=1
7391 01:00:30.274900
7392 01:00:30.275633 ==DQS 0 ==
7393 01:00:30.278221 Final DQS duty delay cell = -4
7394 01:00:30.281557 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7395 01:00:30.284674 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7396 01:00:30.287883 [-4] AVG Duty = 4891%(X100)
7397 01:00:30.288299
7398 01:00:30.288630 ==DQS 1 ==
7399 01:00:30.291266 Final DQS duty delay cell = 0
7400 01:00:30.294851 [0] MAX Duty = 5124%(X100), DQS PI = 28
7401 01:00:30.297947 [0] MIN Duty = 4813%(X100), DQS PI = 58
7402 01:00:30.301396 [0] AVG Duty = 4968%(X100)
7403 01:00:30.301843
7404 01:00:30.304707 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7405 01:00:30.305122
7406 01:00:30.307914 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7407 01:00:30.311181 [DutyScan_Calibration_Flow] ====Done====
7408 01:00:30.311596
7409 01:00:30.314464 [DutyScan_Calibration_Flow] k_type=3
7410 01:00:30.331882
7411 01:00:30.332297 ==DQM 0 ==
7412 01:00:30.335122 Final DQM duty delay cell = 0
7413 01:00:30.338485 [0] MAX Duty = 5000%(X100), DQS PI = 56
7414 01:00:30.341821 [0] MIN Duty = 4844%(X100), DQS PI = 22
7415 01:00:30.345316 [0] AVG Duty = 4922%(X100)
7416 01:00:30.345837
7417 01:00:30.346169 ==DQM 1 ==
7418 01:00:30.348275 Final DQM duty delay cell = 0
7419 01:00:30.351905 [0] MAX Duty = 5062%(X100), DQS PI = 4
7420 01:00:30.355145 [0] MIN Duty = 4844%(X100), DQS PI = 56
7421 01:00:30.358318 [0] AVG Duty = 4953%(X100)
7422 01:00:30.358735
7423 01:00:30.361664 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7424 01:00:30.362083
7425 01:00:30.364917 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7426 01:00:30.368024 [DutyScan_Calibration_Flow] ====Done====
7427 01:00:30.368442
7428 01:00:30.371100 [DutyScan_Calibration_Flow] k_type=2
7429 01:00:30.388456
7430 01:00:30.388950 ==DQ 0 ==
7431 01:00:30.391745 Final DQ duty delay cell = 0
7432 01:00:30.395422 [0] MAX Duty = 5062%(X100), DQS PI = 0
7433 01:00:30.398715 [0] MIN Duty = 4938%(X100), DQS PI = 26
7434 01:00:30.399134 [0] AVG Duty = 5000%(X100)
7435 01:00:30.401937
7436 01:00:30.402355 ==DQ 1 ==
7437 01:00:30.404951 Final DQ duty delay cell = 0
7438 01:00:30.408458 [0] MAX Duty = 5156%(X100), DQS PI = 26
7439 01:00:30.411695 [0] MIN Duty = 4938%(X100), DQS PI = 56
7440 01:00:30.412111 [0] AVG Duty = 5047%(X100)
7441 01:00:30.414972
7442 01:00:30.418265 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7443 01:00:30.418707
7444 01:00:30.421689 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7445 01:00:30.424848 [DutyScan_Calibration_Flow] ====Done====
7446 01:00:30.428231 nWR fixed to 30
7447 01:00:30.428655 [ModeRegInit_LP4] CH0 RK0
7448 01:00:30.431486 [ModeRegInit_LP4] CH0 RK1
7449 01:00:30.434565 [ModeRegInit_LP4] CH1 RK0
7450 01:00:30.437918 [ModeRegInit_LP4] CH1 RK1
7451 01:00:30.438334 match AC timing 5
7452 01:00:30.444566 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7453 01:00:30.448154 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7454 01:00:30.451389 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7455 01:00:30.458077 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7456 01:00:30.461540 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7457 01:00:30.461964 [MiockJmeterHQA]
7458 01:00:30.462296
7459 01:00:30.464769 [DramcMiockJmeter] u1RxGatingPI = 0
7460 01:00:30.468004 0 : 4368, 4140
7461 01:00:30.468429 4 : 4257, 4031
7462 01:00:30.471403 8 : 4258, 4029
7463 01:00:30.471827 12 : 4255, 4029
7464 01:00:30.472165 16 : 4260, 4032
7465 01:00:30.474679 20 : 4257, 4029
7466 01:00:30.475121 24 : 4368, 4140
7467 01:00:30.478078 28 : 4368, 4140
7468 01:00:30.478507 32 : 4258, 4029
7469 01:00:30.481197 36 : 4257, 4029
7470 01:00:30.481665 40 : 4368, 4142
7471 01:00:30.484386 44 : 4257, 4029
7472 01:00:30.484881 48 : 4367, 4142
7473 01:00:30.485353 52 : 4366, 4139
7474 01:00:30.488013 56 : 4363, 4137
7475 01:00:30.488443 60 : 4255, 4029
7476 01:00:30.491107 64 : 4254, 4029
7477 01:00:30.491536 68 : 4257, 4031
7478 01:00:30.494327 72 : 4252, 4029
7479 01:00:30.494756 76 : 4363, 4140
7480 01:00:30.497701 80 : 4253, 4029
7481 01:00:30.498161 84 : 4365, 4140
7482 01:00:30.498503 88 : 4253, 4029
7483 01:00:30.501023 92 : 4253, 4029
7484 01:00:30.501449 96 : 4253, 4029
7485 01:00:30.504310 100 : 4254, 4032
7486 01:00:30.504849 104 : 4255, 3600
7487 01:00:30.507673 108 : 4252, 2
7488 01:00:30.508101 112 : 4366, 0
7489 01:00:30.508439 116 : 4255, 0
7490 01:00:30.511077 120 : 4255, 0
7491 01:00:30.511507 124 : 4253, 0
7492 01:00:30.514233 128 : 4257, 0
7493 01:00:30.514661 132 : 4253, 0
7494 01:00:30.515001 136 : 4255, 0
7495 01:00:30.517539 140 : 4367, 0
7496 01:00:30.517972 144 : 4363, 0
7497 01:00:30.520695 148 : 4363, 0
7498 01:00:30.521121 152 : 4368, 0
7499 01:00:30.521625 156 : 4255, 0
7500 01:00:30.524199 160 : 4253, 0
7501 01:00:30.524626 164 : 4253, 0
7502 01:00:30.524995 168 : 4252, 0
7503 01:00:30.527495 172 : 4253, 0
7504 01:00:30.527924 176 : 4252, 0
7505 01:00:30.530834 180 : 4253, 0
7506 01:00:30.531268 184 : 4253, 0
7507 01:00:30.531607 188 : 4252, 0
7508 01:00:30.534091 192 : 4257, 0
7509 01:00:30.534539 196 : 4363, 0
7510 01:00:30.537580 200 : 4363, 0
7511 01:00:30.538120 204 : 4368, 0
7512 01:00:30.538469 208 : 4363, 0
7513 01:00:30.540728 212 : 4252, 0
7514 01:00:30.541187 216 : 4252, 0
7515 01:00:30.544278 220 : 4257, 0
7516 01:00:30.544724 224 : 4255, 0
7517 01:00:30.545174 228 : 4252, 0
7518 01:00:30.547441 232 : 4257, 1
7519 01:00:30.547887 236 : 4252, 1266
7520 01:00:30.550764 240 : 4252, 4029
7521 01:00:30.551212 244 : 4253, 4029
7522 01:00:30.554044 248 : 4255, 4029
7523 01:00:30.554491 252 : 4252, 4029
7524 01:00:30.557327 256 : 4250, 4027
7525 01:00:30.557823 260 : 4257, 4032
7526 01:00:30.558278 264 : 4254, 4029
7527 01:00:30.560599 268 : 4252, 4029
7528 01:00:30.561045 272 : 4363, 4140
7529 01:00:30.563846 276 : 4254, 4029
7530 01:00:30.564293 280 : 4255, 4029
7531 01:00:30.567440 284 : 4366, 4140
7532 01:00:30.567894 288 : 4252, 4029
7533 01:00:30.570530 292 : 4253, 4029
7534 01:00:30.570980 296 : 4368, 4142
7535 01:00:30.573806 300 : 4254, 4029
7536 01:00:30.574318 304 : 4252, 4029
7537 01:00:30.577123 308 : 4363, 4140
7538 01:00:30.577613 312 : 4254, 4029
7539 01:00:30.580843 316 : 4255, 4029
7540 01:00:30.581289 320 : 4366, 4140
7541 01:00:30.581789 324 : 4253, 4029
7542 01:00:30.583762 328 : 4254, 4029
7543 01:00:30.584211 332 : 4255, 4029
7544 01:00:30.587353 336 : 4255, 4029
7545 01:00:30.587803 340 : 4253, 4029
7546 01:00:30.590603 344 : 4255, 4029
7547 01:00:30.591051 348 : 4257, 4031
7548 01:00:30.593589 352 : 4255, 4001
7549 01:00:30.594038 356 : 4252, 2660
7550 01:00:30.597289 360 : 4253, 1
7551 01:00:30.597781
7552 01:00:30.598224 MIOCK jitter meter ch=0
7553 01:00:30.598645
7554 01:00:30.600437 1T = (360-108) = 252 dly cells
7555 01:00:30.606908 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7556 01:00:30.607492 ==
7557 01:00:30.610617 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 01:00:30.613691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 01:00:30.614135 ==
7560 01:00:30.620675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 01:00:30.623916 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 01:00:30.627151 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 01:00:30.633574 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 01:00:30.643604 [CA 0] Center 44 (14~75) winsize 62
7565 01:00:30.646944 [CA 1] Center 43 (13~74) winsize 62
7566 01:00:30.649871 [CA 2] Center 40 (11~69) winsize 59
7567 01:00:30.653211 [CA 3] Center 39 (10~68) winsize 59
7568 01:00:30.656765 [CA 4] Center 37 (8~67) winsize 60
7569 01:00:30.660127 [CA 5] Center 37 (7~67) winsize 61
7570 01:00:30.660554
7571 01:00:30.663376 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 01:00:30.663797
7573 01:00:30.670065 [CATrainingPosCal] consider 1 rank data
7574 01:00:30.670490 u2DelayCellTimex100 = 258/100 ps
7575 01:00:30.676507 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7576 01:00:30.679928 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7577 01:00:30.683176 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7578 01:00:30.686543 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7579 01:00:30.689789 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7580 01:00:30.693021 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7581 01:00:30.693462
7582 01:00:30.696512 CA PerBit enable=1, Macro0, CA PI delay=37
7583 01:00:30.696954
7584 01:00:30.699639 [CBTSetCACLKResult] CA Dly = 37
7585 01:00:30.703300 CS Dly: 11 (0~42)
7586 01:00:30.706164 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 01:00:30.709794 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 01:00:30.710241 ==
7589 01:00:30.713129 Dram Type= 6, Freq= 0, CH_0, rank 1
7590 01:00:30.719760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 01:00:30.720203 ==
7592 01:00:30.722949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7593 01:00:30.729339 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7594 01:00:30.732662 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7595 01:00:30.739427 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7596 01:00:30.747252 [CA 0] Center 44 (14~74) winsize 61
7597 01:00:30.750606 [CA 1] Center 43 (13~74) winsize 62
7598 01:00:30.753732 [CA 2] Center 39 (10~68) winsize 59
7599 01:00:30.757220 [CA 3] Center 39 (10~68) winsize 59
7600 01:00:30.760557 [CA 4] Center 36 (7~66) winsize 60
7601 01:00:30.763994 [CA 5] Center 36 (7~66) winsize 60
7602 01:00:30.764420
7603 01:00:30.766997 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7604 01:00:30.767426
7605 01:00:30.770429 [CATrainingPosCal] consider 2 rank data
7606 01:00:30.773944 u2DelayCellTimex100 = 258/100 ps
7607 01:00:30.780510 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7608 01:00:30.783768 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7609 01:00:30.787117 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7610 01:00:30.790343 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7611 01:00:30.793626 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7612 01:00:30.796950 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7613 01:00:30.797378
7614 01:00:30.800216 CA PerBit enable=1, Macro0, CA PI delay=36
7615 01:00:30.800639
7616 01:00:30.803717 [CBTSetCACLKResult] CA Dly = 36
7617 01:00:30.806883 CS Dly: 11 (0~43)
7618 01:00:30.810206 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7619 01:00:30.813791 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7620 01:00:30.814220
7621 01:00:30.816984 ----->DramcWriteLeveling(PI) begin...
7622 01:00:30.817416 ==
7623 01:00:30.820276 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 01:00:30.826632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 01:00:30.827063 ==
7626 01:00:30.829878 Write leveling (Byte 0): 35 => 35
7627 01:00:30.833214 Write leveling (Byte 1): 28 => 28
7628 01:00:30.836587 DramcWriteLeveling(PI) end<-----
7629 01:00:30.837028
7630 01:00:30.837369 ==
7631 01:00:30.840065 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 01:00:30.843263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 01:00:30.843697 ==
7634 01:00:30.846517 [Gating] SW mode calibration
7635 01:00:30.852981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7636 01:00:30.856215 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7637 01:00:30.862539 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 01:00:30.866151 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 01:00:30.872642 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 01:00:30.875962 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 01:00:30.879176 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7642 01:00:30.885565 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7643 01:00:30.888969 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7644 01:00:30.892454 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 01:00:30.898830 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 01:00:30.902348 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 01:00:30.905594 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 01:00:30.912249 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7649 01:00:30.915318 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7650 01:00:30.918648 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7651 01:00:30.925342 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7652 01:00:30.928588 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 01:00:30.931624 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 01:00:30.938494 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 01:00:30.941838 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 01:00:30.944921 1 6 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7657 01:00:30.948593 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7658 01:00:30.954964 1 6 20 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
7659 01:00:30.958235 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7660 01:00:30.964794 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 01:00:30.968137 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 01:00:30.971425 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 01:00:30.978034 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 01:00:30.981219 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 01:00:30.984610 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7666 01:00:30.991281 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7667 01:00:30.994546 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7668 01:00:30.997666 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 01:00:31.001148 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 01:00:31.007575 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 01:00:31.010998 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 01:00:31.014134 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 01:00:31.020753 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 01:00:31.024301 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 01:00:31.027385 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 01:00:31.034281 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 01:00:31.037214 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 01:00:31.043983 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 01:00:31.047149 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 01:00:31.050482 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 01:00:31.054047 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7682 01:00:31.060620 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7683 01:00:31.064018 Total UI for P1: 0, mck2ui 16
7684 01:00:31.067142 best dqsien dly found for B0: ( 1, 9, 16)
7685 01:00:31.070339 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7686 01:00:31.073735 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 01:00:31.077249 Total UI for P1: 0, mck2ui 16
7688 01:00:31.080534 best dqsien dly found for B1: ( 1, 9, 22)
7689 01:00:31.083721 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7690 01:00:31.090280 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7691 01:00:31.090362
7692 01:00:31.093505 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7693 01:00:31.096957 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7694 01:00:31.100321 [Gating] SW calibration Done
7695 01:00:31.100403 ==
7696 01:00:31.103494 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 01:00:31.106757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 01:00:31.106839 ==
7699 01:00:31.110050 RX Vref Scan: 0
7700 01:00:31.110132
7701 01:00:31.110195 RX Vref 0 -> 0, step: 1
7702 01:00:31.110255
7703 01:00:31.113321 RX Delay 0 -> 252, step: 8
7704 01:00:31.116653 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7705 01:00:31.123159 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7706 01:00:31.126564 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7707 01:00:31.129871 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7708 01:00:31.133214 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7709 01:00:31.136683 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7710 01:00:31.143029 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7711 01:00:31.146370 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7712 01:00:31.149661 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7713 01:00:31.153019 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7714 01:00:31.156349 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7715 01:00:31.162639 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7716 01:00:31.166048 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7717 01:00:31.169253 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7718 01:00:31.172685 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7719 01:00:31.175899 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7720 01:00:31.179245 ==
7721 01:00:31.182839 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 01:00:31.186050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 01:00:31.186132 ==
7724 01:00:31.186198 DQS Delay:
7725 01:00:31.189414 DQS0 = 0, DQS1 = 0
7726 01:00:31.189500 DQM Delay:
7727 01:00:31.192686 DQM0 = 128, DQM1 = 123
7728 01:00:31.192767 DQ Delay:
7729 01:00:31.195928 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7730 01:00:31.199370 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7731 01:00:31.202572 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7732 01:00:31.206010 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7733 01:00:31.206093
7734 01:00:31.206157
7735 01:00:31.206216 ==
7736 01:00:31.209222 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 01:00:31.216143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 01:00:31.216225 ==
7739 01:00:31.216290
7740 01:00:31.216351
7741 01:00:31.216408 TX Vref Scan disable
7742 01:00:31.219481 == TX Byte 0 ==
7743 01:00:31.222757 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7744 01:00:31.229711 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7745 01:00:31.229793 == TX Byte 1 ==
7746 01:00:31.232893 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7747 01:00:31.239560 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7748 01:00:31.239671 ==
7749 01:00:31.242922 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 01:00:31.245898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 01:00:31.245980 ==
7752 01:00:31.259226
7753 01:00:31.262421 TX Vref early break, caculate TX vref
7754 01:00:31.265795 TX Vref=16, minBit 8, minWin=21, winSum=358
7755 01:00:31.269034 TX Vref=18, minBit 8, minWin=22, winSum=366
7756 01:00:31.272481 TX Vref=20, minBit 8, minWin=22, winSum=379
7757 01:00:31.275649 TX Vref=22, minBit 8, minWin=23, winSum=384
7758 01:00:31.279047 TX Vref=24, minBit 8, minWin=23, winSum=398
7759 01:00:31.285677 TX Vref=26, minBit 8, minWin=24, winSum=408
7760 01:00:31.289083 TX Vref=28, minBit 8, minWin=24, winSum=406
7761 01:00:31.292414 TX Vref=30, minBit 8, minWin=24, winSum=402
7762 01:00:31.295838 TX Vref=32, minBit 8, minWin=23, winSum=392
7763 01:00:31.298993 TX Vref=34, minBit 8, minWin=23, winSum=383
7764 01:00:31.305554 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 26
7765 01:00:31.305636
7766 01:00:31.308845 Final TX Range 0 Vref 26
7767 01:00:31.308927
7768 01:00:31.308992 ==
7769 01:00:31.312283 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 01:00:31.315666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 01:00:31.315749 ==
7772 01:00:31.315815
7773 01:00:31.315875
7774 01:00:31.318797 TX Vref Scan disable
7775 01:00:31.325264 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7776 01:00:31.325368 == TX Byte 0 ==
7777 01:00:31.328626 u2DelayCellOfst[0]=18 cells (5 PI)
7778 01:00:31.331826 u2DelayCellOfst[1]=18 cells (5 PI)
7779 01:00:31.335145 u2DelayCellOfst[2]=11 cells (3 PI)
7780 01:00:31.338717 u2DelayCellOfst[3]=15 cells (4 PI)
7781 01:00:31.341808 u2DelayCellOfst[4]=7 cells (2 PI)
7782 01:00:31.345135 u2DelayCellOfst[5]=0 cells (0 PI)
7783 01:00:31.348827 u2DelayCellOfst[6]=22 cells (6 PI)
7784 01:00:31.352075 u2DelayCellOfst[7]=18 cells (5 PI)
7785 01:00:31.355241 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7786 01:00:31.358869 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7787 01:00:31.362074 == TX Byte 1 ==
7788 01:00:31.362156 u2DelayCellOfst[8]=0 cells (0 PI)
7789 01:00:31.365417 u2DelayCellOfst[9]=3 cells (1 PI)
7790 01:00:31.368715 u2DelayCellOfst[10]=7 cells (2 PI)
7791 01:00:31.371995 u2DelayCellOfst[11]=3 cells (1 PI)
7792 01:00:31.375245 u2DelayCellOfst[12]=11 cells (3 PI)
7793 01:00:31.378600 u2DelayCellOfst[13]=11 cells (3 PI)
7794 01:00:31.381830 u2DelayCellOfst[14]=15 cells (4 PI)
7795 01:00:31.385245 u2DelayCellOfst[15]=11 cells (3 PI)
7796 01:00:31.388319 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7797 01:00:31.394866 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7798 01:00:31.394949 DramC Write-DBI on
7799 01:00:31.395014 ==
7800 01:00:31.398296 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 01:00:31.405027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 01:00:31.405110 ==
7803 01:00:31.405175
7804 01:00:31.405241
7805 01:00:31.405317 TX Vref Scan disable
7806 01:00:31.408859 == TX Byte 0 ==
7807 01:00:31.412186 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7808 01:00:31.415270 == TX Byte 1 ==
7809 01:00:31.418711 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7810 01:00:31.422139 DramC Write-DBI off
7811 01:00:31.422222
7812 01:00:31.422289 [DATLAT]
7813 01:00:31.422350 Freq=1600, CH0 RK0
7814 01:00:31.422408
7815 01:00:31.425385 DATLAT Default: 0xf
7816 01:00:31.425499 0, 0xFFFF, sum = 0
7817 01:00:31.428706 1, 0xFFFF, sum = 0
7818 01:00:31.431968 2, 0xFFFF, sum = 0
7819 01:00:31.432051 3, 0xFFFF, sum = 0
7820 01:00:31.435353 4, 0xFFFF, sum = 0
7821 01:00:31.435436 5, 0xFFFF, sum = 0
7822 01:00:31.438538 6, 0xFFFF, sum = 0
7823 01:00:31.438621 7, 0xFFFF, sum = 0
7824 01:00:31.441735 8, 0xFFFF, sum = 0
7825 01:00:31.441818 9, 0xFFFF, sum = 0
7826 01:00:31.445289 10, 0xFFFF, sum = 0
7827 01:00:31.445399 11, 0xFFFF, sum = 0
7828 01:00:31.448544 12, 0xFFFF, sum = 0
7829 01:00:31.448627 13, 0xEFFF, sum = 0
7830 01:00:31.451664 14, 0x0, sum = 1
7831 01:00:31.451747 15, 0x0, sum = 2
7832 01:00:31.455226 16, 0x0, sum = 3
7833 01:00:31.455315 17, 0x0, sum = 4
7834 01:00:31.458574 best_step = 15
7835 01:00:31.458655
7836 01:00:31.458719 ==
7837 01:00:31.461735 Dram Type= 6, Freq= 0, CH_0, rank 0
7838 01:00:31.465100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7839 01:00:31.465182 ==
7840 01:00:31.468475 RX Vref Scan: 1
7841 01:00:31.468557
7842 01:00:31.468621 Set Vref Range= 24 -> 127
7843 01:00:31.468681
7844 01:00:31.471668 RX Vref 24 -> 127, step: 1
7845 01:00:31.471750
7846 01:00:31.474968 RX Delay 11 -> 252, step: 4
7847 01:00:31.475050
7848 01:00:31.478551 Set Vref, RX VrefLevel [Byte0]: 24
7849 01:00:31.481675 [Byte1]: 24
7850 01:00:31.481757
7851 01:00:31.485162 Set Vref, RX VrefLevel [Byte0]: 25
7852 01:00:31.488325 [Byte1]: 25
7853 01:00:31.488407
7854 01:00:31.491687 Set Vref, RX VrefLevel [Byte0]: 26
7855 01:00:31.495049 [Byte1]: 26
7856 01:00:31.499336
7857 01:00:31.499418 Set Vref, RX VrefLevel [Byte0]: 27
7858 01:00:31.502303 [Byte1]: 27
7859 01:00:31.506836
7860 01:00:31.506918 Set Vref, RX VrefLevel [Byte0]: 28
7861 01:00:31.510070 [Byte1]: 28
7862 01:00:31.514288
7863 01:00:31.514369 Set Vref, RX VrefLevel [Byte0]: 29
7864 01:00:31.517509 [Byte1]: 29
7865 01:00:31.522072
7866 01:00:31.522154 Set Vref, RX VrefLevel [Byte0]: 30
7867 01:00:31.525238 [Byte1]: 30
7868 01:00:31.529738
7869 01:00:31.529824 Set Vref, RX VrefLevel [Byte0]: 31
7870 01:00:31.532769 [Byte1]: 31
7871 01:00:31.537204
7872 01:00:31.537316 Set Vref, RX VrefLevel [Byte0]: 32
7873 01:00:31.540532 [Byte1]: 32
7874 01:00:31.544737
7875 01:00:31.544819 Set Vref, RX VrefLevel [Byte0]: 33
7876 01:00:31.548299 [Byte1]: 33
7877 01:00:31.552497
7878 01:00:31.552579 Set Vref, RX VrefLevel [Byte0]: 34
7879 01:00:31.555817 [Byte1]: 34
7880 01:00:31.560196
7881 01:00:31.560277 Set Vref, RX VrefLevel [Byte0]: 35
7882 01:00:31.563345 [Byte1]: 35
7883 01:00:31.567747
7884 01:00:31.567828 Set Vref, RX VrefLevel [Byte0]: 36
7885 01:00:31.571048 [Byte1]: 36
7886 01:00:31.575350
7887 01:00:31.575431 Set Vref, RX VrefLevel [Byte0]: 37
7888 01:00:31.578694 [Byte1]: 37
7889 01:00:31.582730
7890 01:00:31.582811 Set Vref, RX VrefLevel [Byte0]: 38
7891 01:00:31.586345 [Byte1]: 38
7892 01:00:31.590673
7893 01:00:31.590754 Set Vref, RX VrefLevel [Byte0]: 39
7894 01:00:31.593962 [Byte1]: 39
7895 01:00:31.598137
7896 01:00:31.598219 Set Vref, RX VrefLevel [Byte0]: 40
7897 01:00:31.601341 [Byte1]: 40
7898 01:00:31.605616
7899 01:00:31.605698 Set Vref, RX VrefLevel [Byte0]: 41
7900 01:00:31.608959 [Byte1]: 41
7901 01:00:31.613274
7902 01:00:31.613355 Set Vref, RX VrefLevel [Byte0]: 42
7903 01:00:31.616461 [Byte1]: 42
7904 01:00:31.620793
7905 01:00:31.620874 Set Vref, RX VrefLevel [Byte0]: 43
7906 01:00:31.624045 [Byte1]: 43
7907 01:00:31.628410
7908 01:00:31.628491 Set Vref, RX VrefLevel [Byte0]: 44
7909 01:00:31.632054 [Byte1]: 44
7910 01:00:31.636013
7911 01:00:31.636094 Set Vref, RX VrefLevel [Byte0]: 45
7912 01:00:31.639533 [Byte1]: 45
7913 01:00:31.643804
7914 01:00:31.643886 Set Vref, RX VrefLevel [Byte0]: 46
7915 01:00:31.647143 [Byte1]: 46
7916 01:00:31.651298
7917 01:00:31.651379 Set Vref, RX VrefLevel [Byte0]: 47
7918 01:00:31.654590 [Byte1]: 47
7919 01:00:31.659134
7920 01:00:31.659215 Set Vref, RX VrefLevel [Byte0]: 48
7921 01:00:31.662354 [Byte1]: 48
7922 01:00:31.666659
7923 01:00:31.666741 Set Vref, RX VrefLevel [Byte0]: 49
7924 01:00:31.670063 [Byte1]: 49
7925 01:00:31.674200
7926 01:00:31.674283 Set Vref, RX VrefLevel [Byte0]: 50
7927 01:00:31.677496 [Byte1]: 50
7928 01:00:31.681883
7929 01:00:31.681964 Set Vref, RX VrefLevel [Byte0]: 51
7930 01:00:31.685002 [Byte1]: 51
7931 01:00:31.689245
7932 01:00:31.689329 Set Vref, RX VrefLevel [Byte0]: 52
7933 01:00:31.692861 [Byte1]: 52
7934 01:00:31.697110
7935 01:00:31.697190 Set Vref, RX VrefLevel [Byte0]: 53
7936 01:00:31.700349 [Byte1]: 53
7937 01:00:31.704629
7938 01:00:31.704711 Set Vref, RX VrefLevel [Byte0]: 54
7939 01:00:31.707797 [Byte1]: 54
7940 01:00:31.712417
7941 01:00:31.712498 Set Vref, RX VrefLevel [Byte0]: 55
7942 01:00:31.715717 [Byte1]: 55
7943 01:00:31.720103
7944 01:00:31.720185 Set Vref, RX VrefLevel [Byte0]: 56
7945 01:00:31.723037 [Byte1]: 56
7946 01:00:31.727403
7947 01:00:31.727484 Set Vref, RX VrefLevel [Byte0]: 57
7948 01:00:31.730760 [Byte1]: 57
7949 01:00:31.735055
7950 01:00:31.735136 Set Vref, RX VrefLevel [Byte0]: 58
7951 01:00:31.738587 [Byte1]: 58
7952 01:00:31.742576
7953 01:00:31.742658 Set Vref, RX VrefLevel [Byte0]: 59
7954 01:00:31.746064 [Byte1]: 59
7955 01:00:31.750266
7956 01:00:31.750348 Set Vref, RX VrefLevel [Byte0]: 60
7957 01:00:31.753506 [Byte1]: 60
7958 01:00:31.758077
7959 01:00:31.758158 Set Vref, RX VrefLevel [Byte0]: 61
7960 01:00:31.761148 [Byte1]: 61
7961 01:00:31.765413
7962 01:00:31.765502 Set Vref, RX VrefLevel [Byte0]: 62
7963 01:00:31.768825 [Byte1]: 62
7964 01:00:31.773324
7965 01:00:31.773405 Set Vref, RX VrefLevel [Byte0]: 63
7966 01:00:31.776460 [Byte1]: 63
7967 01:00:31.780706
7968 01:00:31.780787 Set Vref, RX VrefLevel [Byte0]: 64
7969 01:00:31.783939 [Byte1]: 64
7970 01:00:31.788267
7971 01:00:31.788348 Set Vref, RX VrefLevel [Byte0]: 65
7972 01:00:31.791609 [Byte1]: 65
7973 01:00:31.795941
7974 01:00:31.796023 Set Vref, RX VrefLevel [Byte0]: 66
7975 01:00:31.799514 [Byte1]: 66
7976 01:00:31.803518
7977 01:00:31.803599 Set Vref, RX VrefLevel [Byte0]: 67
7978 01:00:31.806997 [Byte1]: 67
7979 01:00:31.811291
7980 01:00:31.811372 Set Vref, RX VrefLevel [Byte0]: 68
7981 01:00:31.814612 [Byte1]: 68
7982 01:00:31.818970
7983 01:00:31.819051 Set Vref, RX VrefLevel [Byte0]: 69
7984 01:00:31.822270 [Byte1]: 69
7985 01:00:31.826323
7986 01:00:31.826404 Set Vref, RX VrefLevel [Byte0]: 70
7987 01:00:31.830025 [Byte1]: 70
7988 01:00:31.833971
7989 01:00:31.834052 Set Vref, RX VrefLevel [Byte0]: 71
7990 01:00:31.837472 [Byte1]: 71
7991 01:00:31.841605
7992 01:00:31.841687 Set Vref, RX VrefLevel [Byte0]: 72
7993 01:00:31.844874 [Byte1]: 72
7994 01:00:31.849312
7995 01:00:31.849424 Set Vref, RX VrefLevel [Byte0]: 73
7996 01:00:31.852590 [Byte1]: 73
7997 01:00:31.856932
7998 01:00:31.857014 Set Vref, RX VrefLevel [Byte0]: 74
7999 01:00:31.860195 [Byte1]: 74
8000 01:00:31.864488
8001 01:00:31.864569 Set Vref, RX VrefLevel [Byte0]: 75
8002 01:00:31.867724 [Byte1]: 75
8003 01:00:31.872186
8004 01:00:31.872268 Set Vref, RX VrefLevel [Byte0]: 76
8005 01:00:31.875238 [Byte1]: 76
8006 01:00:31.879849
8007 01:00:31.879931 Final RX Vref Byte 0 = 63 to rank0
8008 01:00:31.882832 Final RX Vref Byte 1 = 59 to rank0
8009 01:00:31.886518 Final RX Vref Byte 0 = 63 to rank1
8010 01:00:31.889494 Final RX Vref Byte 1 = 59 to rank1==
8011 01:00:31.892815 Dram Type= 6, Freq= 0, CH_0, rank 0
8012 01:00:31.899550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 01:00:31.899634 ==
8014 01:00:31.899700 DQS Delay:
8015 01:00:31.902766 DQS0 = 0, DQS1 = 0
8016 01:00:31.902849 DQM Delay:
8017 01:00:31.902914 DQM0 = 126, DQM1 = 119
8018 01:00:31.906041 DQ Delay:
8019 01:00:31.909259 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8020 01:00:31.912892 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8021 01:00:31.916222 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8022 01:00:31.919238 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
8023 01:00:31.919321
8024 01:00:31.919387
8025 01:00:31.919447
8026 01:00:31.922576 [DramC_TX_OE_Calibration] TA2
8027 01:00:31.925858 Original DQ_B0 (3 6) =30, OEN = 27
8028 01:00:31.929339 Original DQ_B1 (3 6) =30, OEN = 27
8029 01:00:31.932680 24, 0x0, End_B0=24 End_B1=24
8030 01:00:31.932765 25, 0x0, End_B0=25 End_B1=25
8031 01:00:31.935861 26, 0x0, End_B0=26 End_B1=26
8032 01:00:31.939211 27, 0x0, End_B0=27 End_B1=27
8033 01:00:31.942590 28, 0x0, End_B0=28 End_B1=28
8034 01:00:31.946205 29, 0x0, End_B0=29 End_B1=29
8035 01:00:31.946288 30, 0x0, End_B0=30 End_B1=30
8036 01:00:31.949625 31, 0x4545, End_B0=30 End_B1=30
8037 01:00:31.952734 Byte0 end_step=30 best_step=27
8038 01:00:31.955838 Byte1 end_step=30 best_step=27
8039 01:00:31.959380 Byte0 TX OE(2T, 0.5T) = (3, 3)
8040 01:00:31.962629 Byte1 TX OE(2T, 0.5T) = (3, 3)
8041 01:00:31.962712
8042 01:00:31.962777
8043 01:00:31.969254 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8044 01:00:31.972694 CH0 RK0: MR19=303, MR18=1111
8045 01:00:31.979249 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=22, DEC=15
8046 01:00:31.979332
8047 01:00:31.982489 ----->DramcWriteLeveling(PI) begin...
8048 01:00:31.982573 ==
8049 01:00:31.986129 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 01:00:31.989368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 01:00:31.989451 ==
8052 01:00:31.992562 Write leveling (Byte 0): 33 => 33
8053 01:00:31.995912 Write leveling (Byte 1): 29 => 29
8054 01:00:31.999396 DramcWriteLeveling(PI) end<-----
8055 01:00:31.999478
8056 01:00:31.999544 ==
8057 01:00:32.002640 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 01:00:32.006010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 01:00:32.006094 ==
8060 01:00:32.009322 [Gating] SW mode calibration
8061 01:00:32.015675 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8062 01:00:32.022313 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8063 01:00:32.025448 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 01:00:32.032403 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 01:00:32.035638 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 01:00:32.038918 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8067 01:00:32.045399 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8068 01:00:32.048680 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8069 01:00:32.051885 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 01:00:32.058469 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 01:00:32.061844 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 01:00:32.065526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 01:00:32.068611 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8074 01:00:32.075017 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8075 01:00:32.078286 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8076 01:00:32.081647 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8077 01:00:32.088313 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 01:00:32.091900 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 01:00:32.095216 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 01:00:32.101723 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 01:00:32.104946 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8082 01:00:32.108488 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8083 01:00:32.115116 1 6 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8084 01:00:32.118211 1 6 20 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8085 01:00:32.121593 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 01:00:32.128157 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 01:00:32.131432 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 01:00:32.134618 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 01:00:32.141133 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 01:00:32.144532 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8091 01:00:32.147829 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8092 01:00:32.154497 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 01:00:32.158083 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 01:00:32.161275 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 01:00:32.167774 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 01:00:32.171092 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 01:00:32.174333 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 01:00:32.180994 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 01:00:32.184124 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 01:00:32.187512 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 01:00:32.194028 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 01:00:32.197532 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 01:00:32.200740 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 01:00:32.207296 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 01:00:32.210639 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 01:00:32.213837 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 01:00:32.220469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8108 01:00:32.220552 Total UI for P1: 0, mck2ui 16
8109 01:00:32.227264 best dqsien dly found for B0: ( 1, 9, 8)
8110 01:00:32.230570 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 01:00:32.233806 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 01:00:32.237405 Total UI for P1: 0, mck2ui 16
8113 01:00:32.240507 best dqsien dly found for B1: ( 1, 9, 18)
8114 01:00:32.243792 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8115 01:00:32.247258 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8116 01:00:32.247340
8117 01:00:32.253663 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8118 01:00:32.257017 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8119 01:00:32.260235 [Gating] SW calibration Done
8120 01:00:32.260317 ==
8121 01:00:32.263451 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 01:00:32.266774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 01:00:32.266857 ==
8124 01:00:32.266922 RX Vref Scan: 0
8125 01:00:32.266983
8126 01:00:32.270487 RX Vref 0 -> 0, step: 1
8127 01:00:32.270568
8128 01:00:32.273629 RX Delay 0 -> 252, step: 8
8129 01:00:32.276836 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8130 01:00:32.280224 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8131 01:00:32.283731 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8132 01:00:32.290110 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8133 01:00:32.293396 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8134 01:00:32.296800 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8135 01:00:32.300355 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8136 01:00:32.303289 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8137 01:00:32.309974 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8138 01:00:32.313249 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8139 01:00:32.316759 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8140 01:00:32.319990 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8141 01:00:32.326506 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8142 01:00:32.330172 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8143 01:00:32.333120 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8144 01:00:32.336468 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8145 01:00:32.336550 ==
8146 01:00:32.339949 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 01:00:32.343247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 01:00:32.346393 ==
8149 01:00:32.346476 DQS Delay:
8150 01:00:32.346540 DQS0 = 0, DQS1 = 0
8151 01:00:32.349710 DQM Delay:
8152 01:00:32.349791 DQM0 = 128, DQM1 = 121
8153 01:00:32.353329 DQ Delay:
8154 01:00:32.356506 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8155 01:00:32.359941 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8156 01:00:32.363118 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8157 01:00:32.366369 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8158 01:00:32.366451
8159 01:00:32.366515
8160 01:00:32.366575 ==
8161 01:00:32.369811 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 01:00:32.372946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 01:00:32.373028 ==
8164 01:00:32.376408
8165 01:00:32.376490
8166 01:00:32.376555 TX Vref Scan disable
8167 01:00:32.379634 == TX Byte 0 ==
8168 01:00:32.382894 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8169 01:00:32.386170 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8170 01:00:32.389515 == TX Byte 1 ==
8171 01:00:32.392922 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8172 01:00:32.396218 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8173 01:00:32.396301 ==
8174 01:00:32.399513 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 01:00:32.406321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 01:00:32.406403 ==
8177 01:00:32.419234
8178 01:00:32.422599 TX Vref early break, caculate TX vref
8179 01:00:32.426048 TX Vref=16, minBit 0, minWin=22, winSum=371
8180 01:00:32.429106 TX Vref=18, minBit 8, minWin=22, winSum=374
8181 01:00:32.432489 TX Vref=20, minBit 0, minWin=23, winSum=382
8182 01:00:32.435896 TX Vref=22, minBit 0, minWin=24, winSum=394
8183 01:00:32.439015 TX Vref=24, minBit 0, minWin=24, winSum=399
8184 01:00:32.445817 TX Vref=26, minBit 1, minWin=24, winSum=403
8185 01:00:32.448947 TX Vref=28, minBit 0, minWin=25, winSum=410
8186 01:00:32.452304 TX Vref=30, minBit 8, minWin=24, winSum=406
8187 01:00:32.455827 TX Vref=32, minBit 8, minWin=24, winSum=398
8188 01:00:32.459070 TX Vref=34, minBit 8, minWin=23, winSum=390
8189 01:00:32.462468 TX Vref=36, minBit 8, minWin=22, winSum=378
8190 01:00:32.469084 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8191 01:00:32.469167
8192 01:00:32.472659 Final TX Range 0 Vref 28
8193 01:00:32.472767
8194 01:00:32.472860 ==
8195 01:00:32.475858 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 01:00:32.479229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 01:00:32.479311 ==
8198 01:00:32.479375
8199 01:00:32.479435
8200 01:00:32.482632 TX Vref Scan disable
8201 01:00:32.489186 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8202 01:00:32.489268 == TX Byte 0 ==
8203 01:00:32.492447 u2DelayCellOfst[0]=11 cells (3 PI)
8204 01:00:32.495876 u2DelayCellOfst[1]=18 cells (5 PI)
8205 01:00:32.499187 u2DelayCellOfst[2]=11 cells (3 PI)
8206 01:00:32.502403 u2DelayCellOfst[3]=11 cells (3 PI)
8207 01:00:32.505663 u2DelayCellOfst[4]=7 cells (2 PI)
8208 01:00:32.509097 u2DelayCellOfst[5]=0 cells (0 PI)
8209 01:00:32.512166 u2DelayCellOfst[6]=18 cells (5 PI)
8210 01:00:32.515624 u2DelayCellOfst[7]=18 cells (5 PI)
8211 01:00:32.519007 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8212 01:00:32.522215 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8213 01:00:32.525412 == TX Byte 1 ==
8214 01:00:32.528782 u2DelayCellOfst[8]=0 cells (0 PI)
8215 01:00:32.532348 u2DelayCellOfst[9]=0 cells (0 PI)
8216 01:00:32.532430 u2DelayCellOfst[10]=7 cells (2 PI)
8217 01:00:32.535708 u2DelayCellOfst[11]=3 cells (1 PI)
8218 01:00:32.538916 u2DelayCellOfst[12]=11 cells (3 PI)
8219 01:00:32.542149 u2DelayCellOfst[13]=11 cells (3 PI)
8220 01:00:32.545451 u2DelayCellOfst[14]=11 cells (3 PI)
8221 01:00:32.548554 u2DelayCellOfst[15]=7 cells (2 PI)
8222 01:00:32.555407 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8223 01:00:32.558680 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8224 01:00:32.558763 DramC Write-DBI on
8225 01:00:32.558828 ==
8226 01:00:32.561946 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 01:00:32.568528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 01:00:32.568611 ==
8229 01:00:32.568675
8230 01:00:32.568735
8231 01:00:32.568792 TX Vref Scan disable
8232 01:00:32.572654 == TX Byte 0 ==
8233 01:00:32.576104 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8234 01:00:32.579451 == TX Byte 1 ==
8235 01:00:32.582666 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8236 01:00:32.586057 DramC Write-DBI off
8237 01:00:32.586139
8238 01:00:32.586202 [DATLAT]
8239 01:00:32.586262 Freq=1600, CH0 RK1
8240 01:00:32.586321
8241 01:00:32.589232 DATLAT Default: 0xf
8242 01:00:32.589314 0, 0xFFFF, sum = 0
8243 01:00:32.592448 1, 0xFFFF, sum = 0
8244 01:00:32.596141 2, 0xFFFF, sum = 0
8245 01:00:32.596223 3, 0xFFFF, sum = 0
8246 01:00:32.599262 4, 0xFFFF, sum = 0
8247 01:00:32.599346 5, 0xFFFF, sum = 0
8248 01:00:32.602455 6, 0xFFFF, sum = 0
8249 01:00:32.602537 7, 0xFFFF, sum = 0
8250 01:00:32.605774 8, 0xFFFF, sum = 0
8251 01:00:32.605857 9, 0xFFFF, sum = 0
8252 01:00:32.609017 10, 0xFFFF, sum = 0
8253 01:00:32.609100 11, 0xFFFF, sum = 0
8254 01:00:32.612238 12, 0xFFFF, sum = 0
8255 01:00:32.612321 13, 0xCFFF, sum = 0
8256 01:00:32.615875 14, 0x0, sum = 1
8257 01:00:32.615958 15, 0x0, sum = 2
8258 01:00:32.618924 16, 0x0, sum = 3
8259 01:00:32.619007 17, 0x0, sum = 4
8260 01:00:32.622224 best_step = 15
8261 01:00:32.622335
8262 01:00:32.622401 ==
8263 01:00:32.625781 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 01:00:32.629086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 01:00:32.629168 ==
8266 01:00:32.632234 RX Vref Scan: 0
8267 01:00:32.632316
8268 01:00:32.632380 RX Vref 0 -> 0, step: 1
8269 01:00:32.632440
8270 01:00:32.635844 RX Delay 3 -> 252, step: 4
8271 01:00:32.638997 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8272 01:00:32.645524 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8273 01:00:32.649084 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8274 01:00:32.652357 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8275 01:00:32.655785 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8276 01:00:32.659030 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8277 01:00:32.665470 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8278 01:00:32.668944 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8279 01:00:32.672163 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8280 01:00:32.675631 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8281 01:00:32.678912 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8282 01:00:32.685468 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8283 01:00:32.689030 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8284 01:00:32.692215 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8285 01:00:32.695462 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8286 01:00:32.698671 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8287 01:00:32.702215 ==
8288 01:00:32.705397 Dram Type= 6, Freq= 0, CH_0, rank 1
8289 01:00:32.708591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 01:00:32.708674 ==
8291 01:00:32.708739 DQS Delay:
8292 01:00:32.711946 DQS0 = 0, DQS1 = 0
8293 01:00:32.712028 DQM Delay:
8294 01:00:32.715236 DQM0 = 124, DQM1 = 118
8295 01:00:32.715319 DQ Delay:
8296 01:00:32.718683 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8297 01:00:32.722015 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8298 01:00:32.725177 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8299 01:00:32.728640 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8300 01:00:32.728723
8301 01:00:32.728787
8302 01:00:32.728847
8303 01:00:32.732132 [DramC_TX_OE_Calibration] TA2
8304 01:00:32.735269 Original DQ_B0 (3 6) =30, OEN = 27
8305 01:00:32.738360 Original DQ_B1 (3 6) =30, OEN = 27
8306 01:00:32.741990 24, 0x0, End_B0=24 End_B1=24
8307 01:00:32.745362 25, 0x0, End_B0=25 End_B1=25
8308 01:00:32.745446 26, 0x0, End_B0=26 End_B1=26
8309 01:00:32.748319 27, 0x0, End_B0=27 End_B1=27
8310 01:00:32.751610 28, 0x0, End_B0=28 End_B1=28
8311 01:00:32.755187 29, 0x0, End_B0=29 End_B1=29
8312 01:00:32.758251 30, 0x0, End_B0=30 End_B1=30
8313 01:00:32.758334 31, 0x4141, End_B0=30 End_B1=30
8314 01:00:32.761626 Byte0 end_step=30 best_step=27
8315 01:00:32.764969 Byte1 end_step=30 best_step=27
8316 01:00:32.768180 Byte0 TX OE(2T, 0.5T) = (3, 3)
8317 01:00:32.771479 Byte1 TX OE(2T, 0.5T) = (3, 3)
8318 01:00:32.771561
8319 01:00:32.771626
8320 01:00:32.778394 [DQSOSCAuto] RK1, (LSB)MR18= 0x2613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8321 01:00:32.781505 CH0 RK1: MR19=303, MR18=2613
8322 01:00:32.788075 CH0_RK1: MR19=0x303, MR18=0x2613, DQSOSC=390, MR23=63, INC=24, DEC=16
8323 01:00:32.791479 [RxdqsGatingPostProcess] freq 1600
8324 01:00:32.798211 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8325 01:00:32.801436 best DQS0 dly(2T, 0.5T) = (1, 1)
8326 01:00:32.801525 best DQS1 dly(2T, 0.5T) = (1, 1)
8327 01:00:32.804659 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8328 01:00:32.807860 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8329 01:00:32.811095 best DQS0 dly(2T, 0.5T) = (1, 1)
8330 01:00:32.814371 best DQS1 dly(2T, 0.5T) = (1, 1)
8331 01:00:32.817928 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8332 01:00:32.821226 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8333 01:00:32.824571 Pre-setting of DQS Precalculation
8334 01:00:32.827819 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8335 01:00:32.831097 ==
8336 01:00:32.834462 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 01:00:32.837854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 01:00:32.837938 ==
8339 01:00:32.841206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 01:00:32.847820 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 01:00:32.850861 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 01:00:32.857447 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 01:00:32.865722 [CA 0] Center 41 (12~71) winsize 60
8344 01:00:32.868946 [CA 1] Center 42 (13~72) winsize 60
8345 01:00:32.872403 [CA 2] Center 38 (9~67) winsize 59
8346 01:00:32.875414 [CA 3] Center 37 (8~66) winsize 59
8347 01:00:32.878960 [CA 4] Center 37 (8~67) winsize 60
8348 01:00:32.882090 [CA 5] Center 36 (7~66) winsize 60
8349 01:00:32.882172
8350 01:00:32.885828 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 01:00:32.885911
8352 01:00:32.888933 [CATrainingPosCal] consider 1 rank data
8353 01:00:32.892285 u2DelayCellTimex100 = 258/100 ps
8354 01:00:32.898691 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8355 01:00:32.902350 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8356 01:00:32.905258 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8357 01:00:32.908462 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8358 01:00:32.912024 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8359 01:00:32.915013 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 01:00:32.915101
8361 01:00:32.918765 CA PerBit enable=1, Macro0, CA PI delay=36
8362 01:00:32.918867
8363 01:00:32.921975 [CBTSetCACLKResult] CA Dly = 36
8364 01:00:32.925292 CS Dly: 9 (0~40)
8365 01:00:32.928754 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 01:00:32.931714 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 01:00:32.931825 ==
8368 01:00:32.934830 Dram Type= 6, Freq= 0, CH_1, rank 1
8369 01:00:32.941386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 01:00:32.941545 ==
8371 01:00:32.944995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8372 01:00:32.951431 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8373 01:00:32.954844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8374 01:00:32.961421 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8375 01:00:32.969365 [CA 0] Center 42 (13~72) winsize 60
8376 01:00:32.972447 [CA 1] Center 42 (12~73) winsize 62
8377 01:00:32.975759 [CA 2] Center 38 (9~68) winsize 60
8378 01:00:32.979275 [CA 3] Center 37 (8~67) winsize 60
8379 01:00:32.982633 [CA 4] Center 38 (9~68) winsize 60
8380 01:00:32.986013 [CA 5] Center 37 (7~67) winsize 61
8381 01:00:32.986478
8382 01:00:32.988971 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8383 01:00:32.989635
8384 01:00:32.992554 [CATrainingPosCal] consider 2 rank data
8385 01:00:32.995745 u2DelayCellTimex100 = 258/100 ps
8386 01:00:32.999229 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8387 01:00:33.005590 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8388 01:00:33.008848 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8389 01:00:33.012447 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8390 01:00:33.015481 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8391 01:00:33.019016 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8392 01:00:33.019480
8393 01:00:33.022283 CA PerBit enable=1, Macro0, CA PI delay=36
8394 01:00:33.022750
8395 01:00:33.025809 [CBTSetCACLKResult] CA Dly = 36
8396 01:00:33.029163 CS Dly: 10 (0~43)
8397 01:00:33.032054 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8398 01:00:33.035445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8399 01:00:33.035916
8400 01:00:33.038811 ----->DramcWriteLeveling(PI) begin...
8401 01:00:33.039265 ==
8402 01:00:33.042016 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 01:00:33.048643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 01:00:33.049068 ==
8405 01:00:33.052192 Write leveling (Byte 0): 26 => 26
8406 01:00:33.052612 Write leveling (Byte 1): 28 => 28
8407 01:00:33.055647 DramcWriteLeveling(PI) end<-----
8408 01:00:33.056063
8409 01:00:33.056389 ==
8410 01:00:33.058990 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 01:00:33.065581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 01:00:33.066053 ==
8413 01:00:33.068989 [Gating] SW mode calibration
8414 01:00:33.075411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8415 01:00:33.078996 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8416 01:00:33.085298 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 01:00:33.088748 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 01:00:33.092002 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 01:00:33.098610 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 01:00:33.101734 1 4 16 | B1->B0 | 3333 3131 | 0 0 | (0 0) (1 1)
8421 01:00:33.104994 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 01:00:33.111754 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 01:00:33.114999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 01:00:33.118376 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 01:00:33.124839 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 01:00:33.128133 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 01:00:33.131347 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8428 01:00:33.138352 1 5 16 | B1->B0 | 2525 2626 | 0 0 | (1 0) (1 0)
8429 01:00:33.141608 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 01:00:33.144901 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 01:00:33.151434 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 01:00:33.154730 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 01:00:33.158227 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 01:00:33.164600 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 01:00:33.167868 1 6 12 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
8436 01:00:33.171257 1 6 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
8437 01:00:33.174643 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 01:00:33.181426 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 01:00:33.184523 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 01:00:33.187799 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 01:00:33.194481 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 01:00:33.197953 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 01:00:33.201119 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 01:00:33.207855 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8445 01:00:33.211220 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 01:00:33.214255 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 01:00:33.221057 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 01:00:33.224299 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 01:00:33.227637 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 01:00:33.234216 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 01:00:33.237431 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 01:00:33.241081 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 01:00:33.247733 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 01:00:33.251060 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 01:00:33.254322 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 01:00:33.260729 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 01:00:33.264207 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 01:00:33.267525 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 01:00:33.273926 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8460 01:00:33.277122 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8461 01:00:33.280551 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 01:00:33.283913 Total UI for P1: 0, mck2ui 16
8463 01:00:33.287112 best dqsien dly found for B0: ( 1, 9, 14)
8464 01:00:33.290445 Total UI for P1: 0, mck2ui 16
8465 01:00:33.293869 best dqsien dly found for B1: ( 1, 9, 14)
8466 01:00:33.297151 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8467 01:00:33.300524 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8468 01:00:33.300993
8469 01:00:33.306915 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8470 01:00:33.310239 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8471 01:00:33.313383 [Gating] SW calibration Done
8472 01:00:33.313993 ==
8473 01:00:33.316969 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 01:00:33.320252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 01:00:33.320677 ==
8476 01:00:33.321010 RX Vref Scan: 0
8477 01:00:33.323500
8478 01:00:33.323924 RX Vref 0 -> 0, step: 1
8479 01:00:33.324259
8480 01:00:33.326889 RX Delay 0 -> 252, step: 8
8481 01:00:33.330094 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8482 01:00:33.333390 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8483 01:00:33.339989 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8484 01:00:33.343237 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8485 01:00:33.346820 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8486 01:00:33.350087 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8487 01:00:33.353272 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8488 01:00:33.359777 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8489 01:00:33.363111 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8490 01:00:33.366331 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8491 01:00:33.370018 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8492 01:00:33.373258 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8493 01:00:33.379819 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8494 01:00:33.383167 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8495 01:00:33.386615 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8496 01:00:33.389689 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8497 01:00:33.390110 ==
8498 01:00:33.393075 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 01:00:33.399663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 01:00:33.400091 ==
8501 01:00:33.400429 DQS Delay:
8502 01:00:33.402913 DQS0 = 0, DQS1 = 0
8503 01:00:33.403453 DQM Delay:
8504 01:00:33.403799 DQM0 = 132, DQM1 = 126
8505 01:00:33.406390 DQ Delay:
8506 01:00:33.409591 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8507 01:00:33.413147 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8508 01:00:33.416269 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8509 01:00:33.419401 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8510 01:00:33.419821
8511 01:00:33.420147
8512 01:00:33.420450 ==
8513 01:00:33.422732 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 01:00:33.426167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 01:00:33.429515 ==
8516 01:00:33.430164
8517 01:00:33.430557
8518 01:00:33.430902 TX Vref Scan disable
8519 01:00:33.432745 == TX Byte 0 ==
8520 01:00:33.436135 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8521 01:00:33.439484 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8522 01:00:33.442729 == TX Byte 1 ==
8523 01:00:33.446009 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8524 01:00:33.452459 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8525 01:00:33.452888 ==
8526 01:00:33.455604 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 01:00:33.459056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 01:00:33.459745 ==
8529 01:00:33.472381
8530 01:00:33.475734 TX Vref early break, caculate TX vref
8531 01:00:33.479041 TX Vref=16, minBit 10, minWin=21, winSum=363
8532 01:00:33.482258 TX Vref=18, minBit 8, minWin=22, winSum=370
8533 01:00:33.485844 TX Vref=20, minBit 0, minWin=23, winSum=381
8534 01:00:33.489053 TX Vref=22, minBit 1, minWin=23, winSum=395
8535 01:00:33.492268 TX Vref=24, minBit 11, minWin=23, winSum=395
8536 01:00:33.498861 TX Vref=26, minBit 12, minWin=24, winSum=411
8537 01:00:33.502539 TX Vref=28, minBit 11, minWin=24, winSum=412
8538 01:00:33.505596 TX Vref=30, minBit 0, minWin=24, winSum=409
8539 01:00:33.508945 TX Vref=32, minBit 0, minWin=24, winSum=401
8540 01:00:33.512195 TX Vref=34, minBit 6, minWin=23, winSum=391
8541 01:00:33.518914 TX Vref=36, minBit 6, minWin=22, winSum=380
8542 01:00:33.522051 [TxChooseVref] Worse bit 11, Min win 24, Win sum 412, Final Vref 28
8543 01:00:33.522482
8544 01:00:33.525549 Final TX Range 0 Vref 28
8545 01:00:33.526021
8546 01:00:33.526362 ==
8547 01:00:33.528913 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 01:00:33.532016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 01:00:33.535132 ==
8550 01:00:33.535559
8551 01:00:33.535896
8552 01:00:33.536206 TX Vref Scan disable
8553 01:00:33.542317 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8554 01:00:33.542747 == TX Byte 0 ==
8555 01:00:33.545568 u2DelayCellOfst[0]=18 cells (5 PI)
8556 01:00:33.548704 u2DelayCellOfst[1]=15 cells (4 PI)
8557 01:00:33.552275 u2DelayCellOfst[2]=0 cells (0 PI)
8558 01:00:33.555345 u2DelayCellOfst[3]=7 cells (2 PI)
8559 01:00:33.558830 u2DelayCellOfst[4]=11 cells (3 PI)
8560 01:00:33.562057 u2DelayCellOfst[5]=22 cells (6 PI)
8561 01:00:33.565276 u2DelayCellOfst[6]=22 cells (6 PI)
8562 01:00:33.568654 u2DelayCellOfst[7]=7 cells (2 PI)
8563 01:00:33.572137 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8564 01:00:33.575018 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8565 01:00:33.578314 == TX Byte 1 ==
8566 01:00:33.581611 u2DelayCellOfst[8]=0 cells (0 PI)
8567 01:00:33.584943 u2DelayCellOfst[9]=3 cells (1 PI)
8568 01:00:33.588013 u2DelayCellOfst[10]=11 cells (3 PI)
8569 01:00:33.591436 u2DelayCellOfst[11]=3 cells (1 PI)
8570 01:00:33.594675 u2DelayCellOfst[12]=15 cells (4 PI)
8571 01:00:33.598133 u2DelayCellOfst[13]=18 cells (5 PI)
8572 01:00:33.601671 u2DelayCellOfst[14]=18 cells (5 PI)
8573 01:00:33.602093 u2DelayCellOfst[15]=18 cells (5 PI)
8574 01:00:33.608360 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8575 01:00:33.611540 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8576 01:00:33.614809 DramC Write-DBI on
8577 01:00:33.615228 ==
8578 01:00:33.618013 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 01:00:33.621335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 01:00:33.621807 ==
8581 01:00:33.622144
8582 01:00:33.622453
8583 01:00:33.624398 TX Vref Scan disable
8584 01:00:33.624818 == TX Byte 0 ==
8585 01:00:33.631379 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8586 01:00:33.631807 == TX Byte 1 ==
8587 01:00:33.634089 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8588 01:00:33.637351 DramC Write-DBI off
8589 01:00:33.637432
8590 01:00:33.637534 [DATLAT]
8591 01:00:33.640790 Freq=1600, CH1 RK0
8592 01:00:33.640872
8593 01:00:33.640937 DATLAT Default: 0xf
8594 01:00:33.643970 0, 0xFFFF, sum = 0
8595 01:00:33.647097 1, 0xFFFF, sum = 0
8596 01:00:33.647181 2, 0xFFFF, sum = 0
8597 01:00:33.650760 3, 0xFFFF, sum = 0
8598 01:00:33.650843 4, 0xFFFF, sum = 0
8599 01:00:33.654201 5, 0xFFFF, sum = 0
8600 01:00:33.654284 6, 0xFFFF, sum = 0
8601 01:00:33.657431 7, 0xFFFF, sum = 0
8602 01:00:33.657533 8, 0xFFFF, sum = 0
8603 01:00:33.660472 9, 0xFFFF, sum = 0
8604 01:00:33.660555 10, 0xFFFF, sum = 0
8605 01:00:33.663860 11, 0xFFFF, sum = 0
8606 01:00:33.663943 12, 0xFFFF, sum = 0
8607 01:00:33.667339 13, 0x8FFF, sum = 0
8608 01:00:33.667423 14, 0x0, sum = 1
8609 01:00:33.670562 15, 0x0, sum = 2
8610 01:00:33.670645 16, 0x0, sum = 3
8611 01:00:33.674190 17, 0x0, sum = 4
8612 01:00:33.674273 best_step = 15
8613 01:00:33.674337
8614 01:00:33.674397 ==
8615 01:00:33.677392 Dram Type= 6, Freq= 0, CH_1, rank 0
8616 01:00:33.680908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8617 01:00:33.684127 ==
8618 01:00:33.684221 RX Vref Scan: 1
8619 01:00:33.684295
8620 01:00:33.687331 Set Vref Range= 24 -> 127
8621 01:00:33.687424
8622 01:00:33.690633 RX Vref 24 -> 127, step: 1
8623 01:00:33.690735
8624 01:00:33.690816 RX Delay 11 -> 252, step: 4
8625 01:00:33.690891
8626 01:00:33.694009 Set Vref, RX VrefLevel [Byte0]: 24
8627 01:00:33.697237 [Byte1]: 24
8628 01:00:33.701107
8629 01:00:33.701229 Set Vref, RX VrefLevel [Byte0]: 25
8630 01:00:33.704416 [Byte1]: 25
8631 01:00:33.708647
8632 01:00:33.708807 Set Vref, RX VrefLevel [Byte0]: 26
8633 01:00:33.712011 [Byte1]: 26
8634 01:00:33.716164
8635 01:00:33.716335 Set Vref, RX VrefLevel [Byte0]: 27
8636 01:00:33.719588 [Byte1]: 27
8637 01:00:33.723664
8638 01:00:33.723749 Set Vref, RX VrefLevel [Byte0]: 28
8639 01:00:33.727041 [Byte1]: 28
8640 01:00:33.731517
8641 01:00:33.731598 Set Vref, RX VrefLevel [Byte0]: 29
8642 01:00:33.734537 [Byte1]: 29
8643 01:00:33.738942
8644 01:00:33.739024 Set Vref, RX VrefLevel [Byte0]: 30
8645 01:00:33.742211 [Byte1]: 30
8646 01:00:33.746684
8647 01:00:33.746765 Set Vref, RX VrefLevel [Byte0]: 31
8648 01:00:33.749830 [Byte1]: 31
8649 01:00:33.754087
8650 01:00:33.754168 Set Vref, RX VrefLevel [Byte0]: 32
8651 01:00:33.757625 [Byte1]: 32
8652 01:00:33.761838
8653 01:00:33.761920 Set Vref, RX VrefLevel [Byte0]: 33
8654 01:00:33.765323 [Byte1]: 33
8655 01:00:33.769415
8656 01:00:33.769503 Set Vref, RX VrefLevel [Byte0]: 34
8657 01:00:33.772808 [Byte1]: 34
8658 01:00:33.777103
8659 01:00:33.777184 Set Vref, RX VrefLevel [Byte0]: 35
8660 01:00:33.780349 [Byte1]: 35
8661 01:00:33.784863
8662 01:00:33.784945 Set Vref, RX VrefLevel [Byte0]: 36
8663 01:00:33.788106 [Byte1]: 36
8664 01:00:33.792417
8665 01:00:33.792498 Set Vref, RX VrefLevel [Byte0]: 37
8666 01:00:33.795676 [Byte1]: 37
8667 01:00:33.800022
8668 01:00:33.800104 Set Vref, RX VrefLevel [Byte0]: 38
8669 01:00:33.803397 [Byte1]: 38
8670 01:00:33.807752
8671 01:00:33.807840 Set Vref, RX VrefLevel [Byte0]: 39
8672 01:00:33.811106 [Byte1]: 39
8673 01:00:33.815082
8674 01:00:33.815184 Set Vref, RX VrefLevel [Byte0]: 40
8675 01:00:33.818322 [Byte1]: 40
8676 01:00:33.822660
8677 01:00:33.822771 Set Vref, RX VrefLevel [Byte0]: 41
8678 01:00:33.826157 [Byte1]: 41
8679 01:00:33.830422
8680 01:00:33.830592 Set Vref, RX VrefLevel [Byte0]: 42
8681 01:00:33.834000 [Byte1]: 42
8682 01:00:33.837954
8683 01:00:33.838107 Set Vref, RX VrefLevel [Byte0]: 43
8684 01:00:33.841503 [Byte1]: 43
8685 01:00:33.845895
8686 01:00:33.846099 Set Vref, RX VrefLevel [Byte0]: 44
8687 01:00:33.848959 [Byte1]: 44
8688 01:00:33.853275
8689 01:00:33.853534 Set Vref, RX VrefLevel [Byte0]: 45
8690 01:00:33.856669 [Byte1]: 45
8691 01:00:33.860983
8692 01:00:33.861372 Set Vref, RX VrefLevel [Byte0]: 46
8693 01:00:33.864609 [Byte1]: 46
8694 01:00:33.868906
8695 01:00:33.869329 Set Vref, RX VrefLevel [Byte0]: 47
8696 01:00:33.872219 [Byte1]: 47
8697 01:00:33.876546
8698 01:00:33.877005 Set Vref, RX VrefLevel [Byte0]: 48
8699 01:00:33.879809 [Byte1]: 48
8700 01:00:33.883817
8701 01:00:33.884271 Set Vref, RX VrefLevel [Byte0]: 49
8702 01:00:33.887410 [Byte1]: 49
8703 01:00:33.891596
8704 01:00:33.892022 Set Vref, RX VrefLevel [Byte0]: 50
8705 01:00:33.894898 [Byte1]: 50
8706 01:00:33.899330
8707 01:00:33.899757 Set Vref, RX VrefLevel [Byte0]: 51
8708 01:00:33.902619 [Byte1]: 51
8709 01:00:33.907005
8710 01:00:33.907431 Set Vref, RX VrefLevel [Byte0]: 52
8711 01:00:33.910297 [Byte1]: 52
8712 01:00:33.914406
8713 01:00:33.914833 Set Vref, RX VrefLevel [Byte0]: 53
8714 01:00:33.917623 [Byte1]: 53
8715 01:00:33.921948
8716 01:00:33.922372 Set Vref, RX VrefLevel [Byte0]: 54
8717 01:00:33.925314 [Byte1]: 54
8718 01:00:33.929636
8719 01:00:33.930063 Set Vref, RX VrefLevel [Byte0]: 55
8720 01:00:33.932934 [Byte1]: 55
8721 01:00:33.937239
8722 01:00:33.937711 Set Vref, RX VrefLevel [Byte0]: 56
8723 01:00:33.940601 [Byte1]: 56
8724 01:00:33.945049
8725 01:00:33.945668 Set Vref, RX VrefLevel [Byte0]: 57
8726 01:00:33.948326 [Byte1]: 57
8727 01:00:33.952555
8728 01:00:33.952977 Set Vref, RX VrefLevel [Byte0]: 58
8729 01:00:33.955694 [Byte1]: 58
8730 01:00:33.960189
8731 01:00:33.960606 Set Vref, RX VrefLevel [Byte0]: 59
8732 01:00:33.963540 [Byte1]: 59
8733 01:00:33.967886
8734 01:00:33.968302 Set Vref, RX VrefLevel [Byte0]: 60
8735 01:00:33.971263 [Byte1]: 60
8736 01:00:33.975295
8737 01:00:33.975712 Set Vref, RX VrefLevel [Byte0]: 61
8738 01:00:33.978551 [Byte1]: 61
8739 01:00:33.982885
8740 01:00:33.983304 Set Vref, RX VrefLevel [Byte0]: 62
8741 01:00:33.986152 [Byte1]: 62
8742 01:00:33.990831
8743 01:00:33.991254 Set Vref, RX VrefLevel [Byte0]: 63
8744 01:00:33.993941 [Byte1]: 63
8745 01:00:33.998292
8746 01:00:33.998713 Set Vref, RX VrefLevel [Byte0]: 64
8747 01:00:34.001373 [Byte1]: 64
8748 01:00:34.005757
8749 01:00:34.006177 Set Vref, RX VrefLevel [Byte0]: 65
8750 01:00:34.009074 [Byte1]: 65
8751 01:00:34.013604
8752 01:00:34.014038 Set Vref, RX VrefLevel [Byte0]: 66
8753 01:00:34.016549 [Byte1]: 66
8754 01:00:34.020920
8755 01:00:34.021340 Set Vref, RX VrefLevel [Byte0]: 67
8756 01:00:34.024125 [Byte1]: 67
8757 01:00:34.028576
8758 01:00:34.029008 Set Vref, RX VrefLevel [Byte0]: 68
8759 01:00:34.031847 [Byte1]: 68
8760 01:00:34.036179
8761 01:00:34.036599 Set Vref, RX VrefLevel [Byte0]: 69
8762 01:00:34.039372 [Byte1]: 69
8763 01:00:34.043764
8764 01:00:34.044196 Set Vref, RX VrefLevel [Byte0]: 70
8765 01:00:34.047136 [Byte1]: 70
8766 01:00:34.051686
8767 01:00:34.052109 Set Vref, RX VrefLevel [Byte0]: 71
8768 01:00:34.054812 [Byte1]: 71
8769 01:00:34.059218
8770 01:00:34.059644 Final RX Vref Byte 0 = 57 to rank0
8771 01:00:34.062323 Final RX Vref Byte 1 = 54 to rank0
8772 01:00:34.065710 Final RX Vref Byte 0 = 57 to rank1
8773 01:00:34.068927 Final RX Vref Byte 1 = 54 to rank1==
8774 01:00:34.072196 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 01:00:34.078950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 01:00:34.079396 ==
8777 01:00:34.079737 DQS Delay:
8778 01:00:34.082296 DQS0 = 0, DQS1 = 0
8779 01:00:34.082722 DQM Delay:
8780 01:00:34.083059 DQM0 = 130, DQM1 = 123
8781 01:00:34.085544 DQ Delay:
8782 01:00:34.088681 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8783 01:00:34.092197 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8784 01:00:34.095433 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8785 01:00:34.098665 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8786 01:00:34.099093
8787 01:00:34.099425
8788 01:00:34.099732
8789 01:00:34.102012 [DramC_TX_OE_Calibration] TA2
8790 01:00:34.105263 Original DQ_B0 (3 6) =30, OEN = 27
8791 01:00:34.108492 Original DQ_B1 (3 6) =30, OEN = 27
8792 01:00:34.111822 24, 0x0, End_B0=24 End_B1=24
8793 01:00:34.112256 25, 0x0, End_B0=25 End_B1=25
8794 01:00:34.115116 26, 0x0, End_B0=26 End_B1=26
8795 01:00:34.118561 27, 0x0, End_B0=27 End_B1=27
8796 01:00:34.121905 28, 0x0, End_B0=28 End_B1=28
8797 01:00:34.125163 29, 0x0, End_B0=29 End_B1=29
8798 01:00:34.125787 30, 0x0, End_B0=30 End_B1=30
8799 01:00:34.128464 31, 0x4141, End_B0=30 End_B1=30
8800 01:00:34.131817 Byte0 end_step=30 best_step=27
8801 01:00:34.135067 Byte1 end_step=30 best_step=27
8802 01:00:34.138280 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 01:00:34.141618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 01:00:34.142046
8805 01:00:34.142381
8806 01:00:34.148682 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8807 01:00:34.151608 CH1 RK0: MR19=303, MR18=70C
8808 01:00:34.158211 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8809 01:00:34.158639
8810 01:00:34.161580 ----->DramcWriteLeveling(PI) begin...
8811 01:00:34.162007 ==
8812 01:00:34.164851 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 01:00:34.168566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 01:00:34.168990 ==
8815 01:00:34.171695 Write leveling (Byte 0): 26 => 26
8816 01:00:34.174871 Write leveling (Byte 1): 27 => 27
8817 01:00:34.178105 DramcWriteLeveling(PI) end<-----
8818 01:00:34.178526
8819 01:00:34.178857 ==
8820 01:00:34.181418 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 01:00:34.184828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 01:00:34.185267 ==
8823 01:00:34.188163 [Gating] SW mode calibration
8824 01:00:34.194749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 01:00:34.201614 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 01:00:34.204834 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 01:00:34.207999 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 01:00:34.214636 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8829 01:00:34.217944 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8830 01:00:34.221428 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 01:00:34.227914 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 01:00:34.231420 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 01:00:34.234766 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 01:00:34.241372 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 01:00:34.244580 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 01:00:34.247847 1 5 8 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (0 1)
8837 01:00:34.254518 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8838 01:00:34.257822 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 01:00:34.261145 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 01:00:34.267696 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 01:00:34.270871 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 01:00:34.274327 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 01:00:34.280887 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8844 01:00:34.284078 1 6 8 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (0 0)
8845 01:00:34.287406 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8846 01:00:34.294077 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 01:00:34.297142 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 01:00:34.300650 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 01:00:34.307042 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 01:00:34.310519 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 01:00:34.313940 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 01:00:34.320416 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8853 01:00:34.323755 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8854 01:00:34.327032 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 01:00:34.333798 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 01:00:34.336814 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 01:00:34.340274 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 01:00:34.346825 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 01:00:34.350120 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 01:00:34.353742 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 01:00:34.360325 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 01:00:34.363651 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 01:00:34.366985 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 01:00:34.373584 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 01:00:34.376762 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 01:00:34.380141 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 01:00:34.386687 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 01:00:34.389940 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 01:00:34.392986 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8870 01:00:34.396477 Total UI for P1: 0, mck2ui 16
8871 01:00:34.399783 best dqsien dly found for B0: ( 1, 9, 8)
8872 01:00:34.406243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 01:00:34.406666 Total UI for P1: 0, mck2ui 16
8874 01:00:34.413014 best dqsien dly found for B1: ( 1, 9, 10)
8875 01:00:34.416316 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8876 01:00:34.419705 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8877 01:00:34.420123
8878 01:00:34.422950 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8879 01:00:34.426099 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8880 01:00:34.429248 [Gating] SW calibration Done
8881 01:00:34.429715 ==
8882 01:00:34.432571 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 01:00:34.435614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 01:00:34.436040 ==
8885 01:00:34.439237 RX Vref Scan: 0
8886 01:00:34.439657
8887 01:00:34.439987 RX Vref 0 -> 0, step: 1
8888 01:00:34.442538
8889 01:00:34.443001 RX Delay 0 -> 252, step: 8
8890 01:00:34.449064 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8891 01:00:34.452244 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8892 01:00:34.455675 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8893 01:00:34.459134 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8894 01:00:34.462398 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8895 01:00:34.465835 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8896 01:00:34.472494 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8897 01:00:34.475890 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8898 01:00:34.479177 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8899 01:00:34.482430 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8900 01:00:34.488711 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8901 01:00:34.492104 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8902 01:00:34.495759 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8903 01:00:34.498884 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8904 01:00:34.502040 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8905 01:00:34.508812 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8906 01:00:34.509238 ==
8907 01:00:34.511984 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 01:00:34.515386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 01:00:34.515810 ==
8910 01:00:34.516144 DQS Delay:
8911 01:00:34.518722 DQS0 = 0, DQS1 = 0
8912 01:00:34.519143 DQM Delay:
8913 01:00:34.521867 DQM0 = 130, DQM1 = 127
8914 01:00:34.522288 DQ Delay:
8915 01:00:34.525258 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8916 01:00:34.528406 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8917 01:00:34.531949 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8918 01:00:34.535282 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8919 01:00:34.535704
8920 01:00:34.538474
8921 01:00:34.538891 ==
8922 01:00:34.541775 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 01:00:34.545274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 01:00:34.545895 ==
8925 01:00:34.546396
8926 01:00:34.546752
8927 01:00:34.548587 TX Vref Scan disable
8928 01:00:34.549007 == TX Byte 0 ==
8929 01:00:34.555063 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8930 01:00:34.558200 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8931 01:00:34.558622 == TX Byte 1 ==
8932 01:00:34.564942 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 01:00:34.568007 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8934 01:00:34.568429 ==
8935 01:00:34.571456 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 01:00:34.574556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 01:00:34.575028 ==
8938 01:00:34.589355
8939 01:00:34.592477 TX Vref early break, caculate TX vref
8940 01:00:34.595841 TX Vref=16, minBit 0, minWin=23, winSum=388
8941 01:00:34.599079 TX Vref=18, minBit 0, minWin=23, winSum=396
8942 01:00:34.602360 TX Vref=20, minBit 0, minWin=23, winSum=403
8943 01:00:34.605895 TX Vref=22, minBit 0, minWin=25, winSum=411
8944 01:00:34.608994 TX Vref=24, minBit 0, minWin=25, winSum=420
8945 01:00:34.615956 TX Vref=26, minBit 0, minWin=24, winSum=422
8946 01:00:34.618844 TX Vref=28, minBit 0, minWin=25, winSum=426
8947 01:00:34.622494 TX Vref=30, minBit 1, minWin=24, winSum=420
8948 01:00:34.625662 TX Vref=32, minBit 1, minWin=24, winSum=414
8949 01:00:34.628821 TX Vref=34, minBit 0, minWin=24, winSum=405
8950 01:00:34.632291 TX Vref=36, minBit 1, minWin=23, winSum=397
8951 01:00:34.638675 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8952 01:00:34.639098
8953 01:00:34.642377 Final TX Range 0 Vref 28
8954 01:00:34.642801
8955 01:00:34.643130 ==
8956 01:00:34.645717 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 01:00:34.648566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 01:00:34.649189 ==
8959 01:00:34.652290
8960 01:00:34.652706
8961 01:00:34.653035 TX Vref Scan disable
8962 01:00:34.658604 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8963 01:00:34.659025 == TX Byte 0 ==
8964 01:00:34.661860 u2DelayCellOfst[0]=18 cells (5 PI)
8965 01:00:34.665429 u2DelayCellOfst[1]=15 cells (4 PI)
8966 01:00:34.668621 u2DelayCellOfst[2]=0 cells (0 PI)
8967 01:00:34.671952 u2DelayCellOfst[3]=7 cells (2 PI)
8968 01:00:34.675192 u2DelayCellOfst[4]=11 cells (3 PI)
8969 01:00:34.678424 u2DelayCellOfst[5]=22 cells (6 PI)
8970 01:00:34.682001 u2DelayCellOfst[6]=22 cells (6 PI)
8971 01:00:34.685313 u2DelayCellOfst[7]=7 cells (2 PI)
8972 01:00:34.688494 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8973 01:00:34.691760 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8974 01:00:34.695132 == TX Byte 1 ==
8975 01:00:34.698416 u2DelayCellOfst[8]=0 cells (0 PI)
8976 01:00:34.701752 u2DelayCellOfst[9]=7 cells (2 PI)
8977 01:00:34.705176 u2DelayCellOfst[10]=11 cells (3 PI)
8978 01:00:34.708454 u2DelayCellOfst[11]=7 cells (2 PI)
8979 01:00:34.708875 u2DelayCellOfst[12]=15 cells (4 PI)
8980 01:00:34.711539 u2DelayCellOfst[13]=18 cells (5 PI)
8981 01:00:34.714917 u2DelayCellOfst[14]=22 cells (6 PI)
8982 01:00:34.718290 u2DelayCellOfst[15]=18 cells (5 PI)
8983 01:00:34.725010 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8984 01:00:34.728183 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8985 01:00:34.728607 DramC Write-DBI on
8986 01:00:34.731238 ==
8987 01:00:34.734901 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 01:00:34.738129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 01:00:34.738553 ==
8990 01:00:34.738888
8991 01:00:34.739195
8992 01:00:34.741199 TX Vref Scan disable
8993 01:00:34.741646 == TX Byte 0 ==
8994 01:00:34.747882 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8995 01:00:34.748305 == TX Byte 1 ==
8996 01:00:34.751391 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8997 01:00:34.754651 DramC Write-DBI off
8998 01:00:34.755071
8999 01:00:34.755400 [DATLAT]
9000 01:00:34.757881 Freq=1600, CH1 RK1
9001 01:00:34.758302
9002 01:00:34.758634 DATLAT Default: 0xf
9003 01:00:34.761464 0, 0xFFFF, sum = 0
9004 01:00:34.761933 1, 0xFFFF, sum = 0
9005 01:00:34.764514 2, 0xFFFF, sum = 0
9006 01:00:34.764940 3, 0xFFFF, sum = 0
9007 01:00:34.767676 4, 0xFFFF, sum = 0
9008 01:00:34.768103 5, 0xFFFF, sum = 0
9009 01:00:34.771239 6, 0xFFFF, sum = 0
9010 01:00:34.771665 7, 0xFFFF, sum = 0
9011 01:00:34.774549 8, 0xFFFF, sum = 0
9012 01:00:34.774977 9, 0xFFFF, sum = 0
9013 01:00:34.777919 10, 0xFFFF, sum = 0
9014 01:00:34.781182 11, 0xFFFF, sum = 0
9015 01:00:34.781635 12, 0xFFFF, sum = 0
9016 01:00:34.784465 13, 0x8FFF, sum = 0
9017 01:00:34.784893 14, 0x0, sum = 1
9018 01:00:34.787863 15, 0x0, sum = 2
9019 01:00:34.788289 16, 0x0, sum = 3
9020 01:00:34.791059 17, 0x0, sum = 4
9021 01:00:34.791486 best_step = 15
9022 01:00:34.791818
9023 01:00:34.792127 ==
9024 01:00:34.794232 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 01:00:34.797557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 01:00:34.797982 ==
9027 01:00:34.800742 RX Vref Scan: 0
9028 01:00:34.801160
9029 01:00:34.804123 RX Vref 0 -> 0, step: 1
9030 01:00:34.804546
9031 01:00:34.804885 RX Delay 3 -> 252, step: 4
9032 01:00:34.811233 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9033 01:00:34.814912 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9034 01:00:34.818455 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9035 01:00:34.821269 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9036 01:00:34.824559 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9037 01:00:34.831388 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9038 01:00:34.834548 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9039 01:00:34.837704 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9040 01:00:34.841247 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9041 01:00:34.844610 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9042 01:00:34.851175 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9043 01:00:34.854401 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9044 01:00:34.857834 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9045 01:00:34.860943 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9046 01:00:34.867548 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9047 01:00:34.870953 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9048 01:00:34.871376 ==
9049 01:00:34.874260 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 01:00:34.877828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 01:00:34.878254 ==
9052 01:00:34.880881 DQS Delay:
9053 01:00:34.881302 DQS0 = 0, DQS1 = 0
9054 01:00:34.881670 DQM Delay:
9055 01:00:34.884258 DQM0 = 127, DQM1 = 125
9056 01:00:34.884682 DQ Delay:
9057 01:00:34.887551 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9058 01:00:34.890949 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9059 01:00:34.894190 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9060 01:00:34.900932 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9061 01:00:34.901352
9062 01:00:34.901716
9063 01:00:34.902028
9064 01:00:34.904321 [DramC_TX_OE_Calibration] TA2
9065 01:00:34.904744 Original DQ_B0 (3 6) =30, OEN = 27
9066 01:00:34.907640 Original DQ_B1 (3 6) =30, OEN = 27
9067 01:00:34.910817 24, 0x0, End_B0=24 End_B1=24
9068 01:00:34.914148 25, 0x0, End_B0=25 End_B1=25
9069 01:00:34.917518 26, 0x0, End_B0=26 End_B1=26
9070 01:00:34.918004 27, 0x0, End_B0=27 End_B1=27
9071 01:00:34.920878 28, 0x0, End_B0=28 End_B1=28
9072 01:00:34.924312 29, 0x0, End_B0=29 End_B1=29
9073 01:00:34.927425 30, 0x0, End_B0=30 End_B1=30
9074 01:00:34.930638 31, 0x4141, End_B0=30 End_B1=30
9075 01:00:34.933913 Byte0 end_step=30 best_step=27
9076 01:00:34.934336 Byte1 end_step=30 best_step=27
9077 01:00:34.937260 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 01:00:34.940712 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 01:00:34.941132
9080 01:00:34.941459
9081 01:00:34.950747 [DQSOSCAuto] RK1, (LSB)MR18= 0x111c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9082 01:00:34.951174 CH1 RK1: MR19=303, MR18=111C
9083 01:00:34.957133 CH1_RK1: MR19=0x303, MR18=0x111C, DQSOSC=395, MR23=63, INC=23, DEC=15
9084 01:00:34.960328 [RxdqsGatingPostProcess] freq 1600
9085 01:00:34.967226 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 01:00:34.970300 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 01:00:34.973642 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 01:00:34.977200 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 01:00:34.980358 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 01:00:34.980782 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 01:00:34.983671 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 01:00:34.986962 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 01:00:34.990243 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 01:00:34.993349 Pre-setting of DQS Precalculation
9095 01:00:35.000176 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 01:00:35.006654 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 01:00:35.013260 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 01:00:35.013725
9099 01:00:35.014244
9100 01:00:35.016897 [Calibration Summary] 3200 Mbps
9101 01:00:35.017318 CH 0, Rank 0
9102 01:00:35.019923 SW Impedance : PASS
9103 01:00:35.023291 DUTY Scan : NO K
9104 01:00:35.023832 ZQ Calibration : PASS
9105 01:00:35.026437 Jitter Meter : NO K
9106 01:00:35.029744 CBT Training : PASS
9107 01:00:35.030166 Write leveling : PASS
9108 01:00:35.033149 RX DQS gating : PASS
9109 01:00:35.036391 RX DQ/DQS(RDDQC) : PASS
9110 01:00:35.036812 TX DQ/DQS : PASS
9111 01:00:35.039611 RX DATLAT : PASS
9112 01:00:35.042978 RX DQ/DQS(Engine): PASS
9113 01:00:35.043455 TX OE : PASS
9114 01:00:35.046524 All Pass.
9115 01:00:35.046971
9116 01:00:35.047317 CH 0, Rank 1
9117 01:00:35.049842 SW Impedance : PASS
9118 01:00:35.050265 DUTY Scan : NO K
9119 01:00:35.052876 ZQ Calibration : PASS
9120 01:00:35.056294 Jitter Meter : NO K
9121 01:00:35.056716 CBT Training : PASS
9122 01:00:35.059555 Write leveling : PASS
9123 01:00:35.062877 RX DQS gating : PASS
9124 01:00:35.063298 RX DQ/DQS(RDDQC) : PASS
9125 01:00:35.066199 TX DQ/DQS : PASS
9126 01:00:35.066622 RX DATLAT : PASS
9127 01:00:35.069648 RX DQ/DQS(Engine): PASS
9128 01:00:35.072909 TX OE : PASS
9129 01:00:35.073330 All Pass.
9130 01:00:35.073707
9131 01:00:35.074025 CH 1, Rank 0
9132 01:00:35.076144 SW Impedance : PASS
9133 01:00:35.079515 DUTY Scan : NO K
9134 01:00:35.079935 ZQ Calibration : PASS
9135 01:00:35.082820 Jitter Meter : NO K
9136 01:00:35.085644 CBT Training : PASS
9137 01:00:35.086065 Write leveling : PASS
9138 01:00:35.089251 RX DQS gating : PASS
9139 01:00:35.092505 RX DQ/DQS(RDDQC) : PASS
9140 01:00:35.092923 TX DQ/DQS : PASS
9141 01:00:35.095831 RX DATLAT : PASS
9142 01:00:35.099071 RX DQ/DQS(Engine): PASS
9143 01:00:35.099491 TX OE : PASS
9144 01:00:35.102286 All Pass.
9145 01:00:35.102703
9146 01:00:35.103036 CH 1, Rank 1
9147 01:00:35.105901 SW Impedance : PASS
9148 01:00:35.106345 DUTY Scan : NO K
9149 01:00:35.108907 ZQ Calibration : PASS
9150 01:00:35.112501 Jitter Meter : NO K
9151 01:00:35.112921 CBT Training : PASS
9152 01:00:35.115789 Write leveling : PASS
9153 01:00:35.118688 RX DQS gating : PASS
9154 01:00:35.119109 RX DQ/DQS(RDDQC) : PASS
9155 01:00:35.122210 TX DQ/DQS : PASS
9156 01:00:35.125389 RX DATLAT : PASS
9157 01:00:35.125842 RX DQ/DQS(Engine): PASS
9158 01:00:35.128820 TX OE : PASS
9159 01:00:35.129240 All Pass.
9160 01:00:35.129626
9161 01:00:35.132091 DramC Write-DBI on
9162 01:00:35.135309 PER_BANK_REFRESH: Hybrid Mode
9163 01:00:35.135731 TX_TRACKING: ON
9164 01:00:35.145537 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 01:00:35.151962 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 01:00:35.158765 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 01:00:35.161940 [FAST_K] Save calibration result to emmc
9168 01:00:35.165076 sync common calibartion params.
9169 01:00:35.168406 sync cbt_mode0:1, 1:1
9170 01:00:35.171654 dram_init: ddr_geometry: 2
9171 01:00:35.172075 dram_init: ddr_geometry: 2
9172 01:00:35.174946 dram_init: ddr_geometry: 2
9173 01:00:35.178423 0:dram_rank_size:100000000
9174 01:00:35.181604 1:dram_rank_size:100000000
9175 01:00:35.185028 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 01:00:35.188382 DFS_SHUFFLE_HW_MODE: ON
9177 01:00:35.191661 dramc_set_vcore_voltage set vcore to 725000
9178 01:00:35.194956 Read voltage for 1600, 0
9179 01:00:35.195377 Vio18 = 0
9180 01:00:35.195706 Vcore = 725000
9181 01:00:35.198204 Vdram = 0
9182 01:00:35.198623 Vddq = 0
9183 01:00:35.198955 Vmddr = 0
9184 01:00:35.201371 switch to 3200 Mbps bootup
9185 01:00:35.204892 [DramcRunTimeConfig]
9186 01:00:35.205313 PHYPLL
9187 01:00:35.205696 DPM_CONTROL_AFTERK: ON
9188 01:00:35.208164 PER_BANK_REFRESH: ON
9189 01:00:35.211647 REFRESH_OVERHEAD_REDUCTION: ON
9190 01:00:35.212071 CMD_PICG_NEW_MODE: OFF
9191 01:00:35.214827 XRTWTW_NEW_MODE: ON
9192 01:00:35.218101 XRTRTR_NEW_MODE: ON
9193 01:00:35.218520 TX_TRACKING: ON
9194 01:00:35.218962 RDSEL_TRACKING: OFF
9195 01:00:35.221382 DQS Precalculation for DVFS: ON
9196 01:00:35.224658 RX_TRACKING: OFF
9197 01:00:35.225074 HW_GATING DBG: ON
9198 01:00:35.227953 ZQCS_ENABLE_LP4: ON
9199 01:00:35.228385 RX_PICG_NEW_MODE: ON
9200 01:00:35.231513 TX_PICG_NEW_MODE: ON
9201 01:00:35.234465 ENABLE_RX_DCM_DPHY: ON
9202 01:00:35.237935 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 01:00:35.238359 DUMMY_READ_FOR_TRACKING: OFF
9204 01:00:35.241215 !!! SPM_CONTROL_AFTERK: OFF
9205 01:00:35.244516 !!! SPM could not control APHY
9206 01:00:35.247704 IMPEDANCE_TRACKING: ON
9207 01:00:35.248128 TEMP_SENSOR: ON
9208 01:00:35.250690 HW_SAVE_FOR_SR: OFF
9209 01:00:35.253934 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 01:00:35.257228 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 01:00:35.257710 Read ODT Tracking: ON
9212 01:00:35.260547 Refresh Rate DeBounce: ON
9213 01:00:35.264123 DFS_NO_QUEUE_FLUSH: ON
9214 01:00:35.267546 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 01:00:35.268014 ENABLE_DFS_RUNTIME_MRW: OFF
9216 01:00:35.270593 DDR_RESERVE_NEW_MODE: ON
9217 01:00:35.273843 MR_CBT_SWITCH_FREQ: ON
9218 01:00:35.274264 =========================
9219 01:00:35.294190 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 01:00:35.297357 dram_init: ddr_geometry: 2
9221 01:00:35.315585 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 01:00:35.318726 dram_init: dram init end (result: 0)
9223 01:00:35.325302 DRAM-K: Full calibration passed in 24549 msecs
9224 01:00:35.328631 MRC: failed to locate region type 0.
9225 01:00:35.329108 DRAM rank0 size:0x100000000,
9226 01:00:35.331871 DRAM rank1 size=0x100000000
9227 01:00:35.342091 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 01:00:35.348891 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 01:00:35.355387 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 01:00:35.361965 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 01:00:35.365164 DRAM rank0 size:0x100000000,
9232 01:00:35.368530 DRAM rank1 size=0x100000000
9233 01:00:35.368991 CBMEM:
9234 01:00:35.371779 IMD: root @ 0xfffff000 254 entries.
9235 01:00:35.375139 IMD: root @ 0xffffec00 62 entries.
9236 01:00:35.378220 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 01:00:35.381793 WARNING: RO_VPD is uninitialized or empty.
9238 01:00:35.388189 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 01:00:35.395677 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 01:00:35.408496 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9241 01:00:35.419347 BS: romstage times (exec / console): total (unknown) / 24015 ms
9242 01:00:35.419430
9243 01:00:35.419495
9244 01:00:35.429353 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 01:00:35.432637 ARM64: Exception handlers installed.
9246 01:00:35.435968 ARM64: Testing exception
9247 01:00:35.439294 ARM64: Done test exception
9248 01:00:35.439375 Enumerating buses...
9249 01:00:35.442601 Show all devs... Before device enumeration.
9250 01:00:35.445913 Root Device: enabled 1
9251 01:00:35.449063 CPU_CLUSTER: 0: enabled 1
9252 01:00:35.449146 CPU: 00: enabled 1
9253 01:00:35.452560 Compare with tree...
9254 01:00:35.452644 Root Device: enabled 1
9255 01:00:35.455873 CPU_CLUSTER: 0: enabled 1
9256 01:00:35.459095 CPU: 00: enabled 1
9257 01:00:35.459177 Root Device scanning...
9258 01:00:35.462382 scan_static_bus for Root Device
9259 01:00:35.465775 CPU_CLUSTER: 0 enabled
9260 01:00:35.469173 scan_static_bus for Root Device done
9261 01:00:35.472355 scan_bus: bus Root Device finished in 8 msecs
9262 01:00:35.472438 done
9263 01:00:35.479174 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 01:00:35.482194 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 01:00:35.488851 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 01:00:35.492322 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 01:00:35.495487 Allocating resources...
9268 01:00:35.498953 Reading resources...
9269 01:00:35.502227 Root Device read_resources bus 0 link: 0
9270 01:00:35.502310 DRAM rank0 size:0x100000000,
9271 01:00:35.505543 DRAM rank1 size=0x100000000
9272 01:00:35.508769 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 01:00:35.512031 CPU: 00 missing read_resources
9274 01:00:35.518551 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 01:00:35.521831 Root Device read_resources bus 0 link: 0 done
9276 01:00:35.521915 Done reading resources.
9277 01:00:35.528463 Show resources in subtree (Root Device)...After reading.
9278 01:00:35.531956 Root Device child on link 0 CPU_CLUSTER: 0
9279 01:00:35.535281 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 01:00:35.545159 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 01:00:35.545245 CPU: 00
9282 01:00:35.548460 Root Device assign_resources, bus 0 link: 0
9283 01:00:35.551845 CPU_CLUSTER: 0 missing set_resources
9284 01:00:35.558616 Root Device assign_resources, bus 0 link: 0 done
9285 01:00:35.558699 Done setting resources.
9286 01:00:35.565406 Show resources in subtree (Root Device)...After assigning values.
9287 01:00:35.568590 Root Device child on link 0 CPU_CLUSTER: 0
9288 01:00:35.571988 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 01:00:35.581792 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 01:00:35.581876 CPU: 00
9291 01:00:35.585436 Done allocating resources.
9292 01:00:35.588605 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 01:00:35.592019 Enabling resources...
9294 01:00:35.592102 done.
9295 01:00:35.598352 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 01:00:35.598435 Initializing devices...
9297 01:00:35.601802 Root Device init
9298 01:00:35.601884 init hardware done!
9299 01:00:35.605039 0x00000018: ctrlr->caps
9300 01:00:35.608286 52.000 MHz: ctrlr->f_max
9301 01:00:35.608370 0.400 MHz: ctrlr->f_min
9302 01:00:35.611692 0x40ff8080: ctrlr->voltages
9303 01:00:35.611776 sclk: 390625
9304 01:00:35.614821 Bus Width = 1
9305 01:00:35.614903 sclk: 390625
9306 01:00:35.618160 Bus Width = 1
9307 01:00:35.618243 Early init status = 3
9308 01:00:35.624713 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 01:00:35.628344 in-header: 03 fc 00 00 01 00 00 00
9310 01:00:35.628454 in-data: 00
9311 01:00:35.634566 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 01:00:35.638147 in-header: 03 fd 00 00 00 00 00 00
9313 01:00:35.641425 in-data:
9314 01:00:35.644499 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 01:00:35.648075 in-header: 03 fc 00 00 01 00 00 00
9316 01:00:35.651318 in-data: 00
9317 01:00:35.654550 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 01:00:35.659129 in-header: 03 fd 00 00 00 00 00 00
9319 01:00:35.662687 in-data:
9320 01:00:35.665722 [SSUSB] Setting up USB HOST controller...
9321 01:00:35.669290 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 01:00:35.672580 [SSUSB] phy power-on done.
9323 01:00:35.675855 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 01:00:35.682612 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 01:00:35.685934 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 01:00:35.692460 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 01:00:35.699245 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 01:00:35.705647 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 01:00:35.712293 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 01:00:35.718816 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 01:00:35.722277 SPM: binary array size = 0x9dc
9332 01:00:35.725655 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 01:00:35.732210 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 01:00:35.738834 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 01:00:35.745505 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 01:00:35.748391 configure_display: Starting display init
9337 01:00:35.782988 anx7625_power_on_init: Init interface.
9338 01:00:35.786317 anx7625_disable_pd_protocol: Disabled PD feature.
9339 01:00:35.789569 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 01:00:35.817376 anx7625_start_dp_work: Secure OCM version=00
9341 01:00:35.820622 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 01:00:35.835387 sp_tx_get_edid_block: EDID Block = 1
9343 01:00:35.938070 Extracted contents:
9344 01:00:35.941314 header: 00 ff ff ff ff ff ff 00
9345 01:00:35.944510 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 01:00:35.947900 version: 01 04
9347 01:00:35.950995 basic params: 95 1f 11 78 0a
9348 01:00:35.954237 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 01:00:35.957568 established: 00 00 00
9350 01:00:35.964481 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 01:00:35.970865 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 01:00:35.974176 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 01:00:35.980968 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 01:00:35.987319 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 01:00:35.990660 extensions: 00
9356 01:00:35.991154 checksum: fb
9357 01:00:35.991580
9358 01:00:35.997139 Manufacturer: IVO Model 57d Serial Number 0
9359 01:00:35.997716 Made week 0 of 2020
9360 01:00:36.000673 EDID version: 1.4
9361 01:00:36.001257 Digital display
9362 01:00:36.003865 6 bits per primary color channel
9363 01:00:36.004349 DisplayPort interface
9364 01:00:36.007133 Maximum image size: 31 cm x 17 cm
9365 01:00:36.010544 Gamma: 220%
9366 01:00:36.011014 Check DPMS levels
9367 01:00:36.017049 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 01:00:36.020291 First detailed timing is preferred timing
9369 01:00:36.020770 Established timings supported:
9370 01:00:36.023688 Standard timings supported:
9371 01:00:36.027011 Detailed timings
9372 01:00:36.030267 Hex of detail: 383680a07038204018303c0035ae10000019
9373 01:00:36.036840 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 01:00:36.040258 0780 0798 07c8 0820 hborder 0
9375 01:00:36.043578 0438 043b 0447 0458 vborder 0
9376 01:00:36.046915 -hsync -vsync
9377 01:00:36.047519 Did detailed timing
9378 01:00:36.053449 Hex of detail: 000000000000000000000000000000000000
9379 01:00:36.056731 Manufacturer-specified data, tag 0
9380 01:00:36.060225 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 01:00:36.063521 ASCII string: InfoVision
9382 01:00:36.066785 Hex of detail: 000000fe00523134304e574635205248200a
9383 01:00:36.070023 ASCII string: R140NWF5 RH
9384 01:00:36.070527 Checksum
9385 01:00:36.073350 Checksum: 0xfb (valid)
9386 01:00:36.076655 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 01:00:36.079876 DSI data_rate: 832800000 bps
9388 01:00:36.086610 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 01:00:36.089912 anx7625_parse_edid: pixelclock(138800).
9390 01:00:36.093119 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 01:00:36.096344 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 01:00:36.099683 anx7625_dsi_config: config dsi.
9393 01:00:36.106521 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 01:00:36.119840 anx7625_dsi_config: success to config DSI
9395 01:00:36.123233 anx7625_dp_start: MIPI phy setup OK.
9396 01:00:36.126561 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 01:00:36.129903 mtk_ddp_mode_set invalid vrefresh 60
9398 01:00:36.133350 main_disp_path_setup
9399 01:00:36.133891 ovl_layer_smi_id_en
9400 01:00:36.136485 ovl_layer_smi_id_en
9401 01:00:36.136968 ccorr_config
9402 01:00:36.137526 aal_config
9403 01:00:36.139828 gamma_config
9404 01:00:36.140304 postmask_config
9405 01:00:36.143125 dither_config
9406 01:00:36.146681 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 01:00:36.153122 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 01:00:36.156460 Root Device init finished in 551 msecs
9409 01:00:36.159736 CPU_CLUSTER: 0 init
9410 01:00:36.166115 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 01:00:36.172775 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 01:00:36.173266 APU_MBOX 0x190000b0 = 0x10001
9413 01:00:36.176212 APU_MBOX 0x190001b0 = 0x10001
9414 01:00:36.179498 APU_MBOX 0x190005b0 = 0x10001
9415 01:00:36.182789 APU_MBOX 0x190006b0 = 0x10001
9416 01:00:36.189398 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 01:00:36.198842 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9418 01:00:36.211422 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 01:00:36.217997 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 01:00:36.229520 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9421 01:00:36.238853 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 01:00:36.242013 CPU_CLUSTER: 0 init finished in 81 msecs
9423 01:00:36.245775 Devices initialized
9424 01:00:36.248790 Show all devs... After init.
9425 01:00:36.249216 Root Device: enabled 1
9426 01:00:36.251976 CPU_CLUSTER: 0: enabled 1
9427 01:00:36.255266 CPU: 00: enabled 1
9428 01:00:36.258618 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9429 01:00:36.261837 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 01:00:36.265123 ELOG: NV offset 0x57f000 size 0x1000
9431 01:00:36.271851 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9432 01:00:36.278495 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 01:00:36.281741 ELOG: Event(17) added with size 13 at 2024-01-19 01:00:36 UTC
9434 01:00:36.288392 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 01:00:36.291626 in-header: 03 74 00 00 2c 00 00 00
9436 01:00:36.301763 in-data: eb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 01:00:36.308280 ELOG: Event(A1) added with size 10 at 2024-01-19 01:00:36 UTC
9438 01:00:36.315034 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 01:00:36.321455 ELOG: Event(A0) added with size 9 at 2024-01-19 01:00:36 UTC
9440 01:00:36.324734 elog_add_boot_reason: Logged dev mode boot
9441 01:00:36.331526 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 01:00:36.331953 Finalize devices...
9443 01:00:36.334806 Devices finalized
9444 01:00:36.338009 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 01:00:36.341471 Writing coreboot table at 0xffe64000
9446 01:00:36.344651 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 01:00:36.348014 1. 0000000040000000-00000000400fffff: RAM
9448 01:00:36.354603 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 01:00:36.358018 3. 000000004032b000-00000000545fffff: RAM
9450 01:00:36.361299 4. 0000000054600000-000000005465ffff: BL31
9451 01:00:36.364541 5. 0000000054660000-00000000ffe63fff: RAM
9452 01:00:36.371334 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 01:00:36.374608 7. 0000000100000000-000000023fffffff: RAM
9454 01:00:36.377985 Passing 5 GPIOs to payload:
9455 01:00:36.381043 NAME | PORT | POLARITY | VALUE
9456 01:00:36.384624 EC in RW | 0x000000aa | low | undefined
9457 01:00:36.391128 EC interrupt | 0x00000005 | low | undefined
9458 01:00:36.394332 TPM interrupt | 0x000000ab | high | undefined
9459 01:00:36.400880 SD card detect | 0x00000011 | high | undefined
9460 01:00:36.404345 speaker enable | 0x00000093 | high | undefined
9461 01:00:36.407654 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 01:00:36.411032 in-header: 03 f9 00 00 02 00 00 00
9463 01:00:36.414159 in-data: 02 00
9464 01:00:36.417415 ADC[4]: Raw value=894081 ID=7
9465 01:00:36.417894 ADC[3]: Raw value=212700 ID=1
9466 01:00:36.420694 RAM Code: 0x71
9467 01:00:36.424246 ADC[6]: Raw value=75092 ID=0
9468 01:00:36.424674 ADC[5]: Raw value=211960 ID=1
9469 01:00:36.427209 SKU Code: 0x1
9470 01:00:36.430597 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1418
9471 01:00:36.433928 coreboot table: 964 bytes.
9472 01:00:36.437218 IMD ROOT 0. 0xfffff000 0x00001000
9473 01:00:36.440708 IMD SMALL 1. 0xffffe000 0x00001000
9474 01:00:36.443805 RO MCACHE 2. 0xffffc000 0x00001104
9475 01:00:36.447153 CONSOLE 3. 0xfff7c000 0x00080000
9476 01:00:36.450499 FMAP 4. 0xfff7b000 0x00000452
9477 01:00:36.453616 TIME STAMP 5. 0xfff7a000 0x00000910
9478 01:00:36.457073 VBOOT WORK 6. 0xfff66000 0x00014000
9479 01:00:36.460155 RAMOOPS 7. 0xffe66000 0x00100000
9480 01:00:36.463663 COREBOOT 8. 0xffe64000 0x00002000
9481 01:00:36.467117 IMD small region:
9482 01:00:36.470377 IMD ROOT 0. 0xffffec00 0x00000400
9483 01:00:36.473732 VPD 1. 0xffffeb80 0x0000006c
9484 01:00:36.476874 MMC STATUS 2. 0xffffeb60 0x00000004
9485 01:00:36.480269 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 01:00:36.483482 Probing TPM: done!
9487 01:00:36.487018 Connected to device vid:did:rid of 1ae0:0028:00
9488 01:00:36.497612 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 01:00:36.501149 Initialized TPM device CR50 revision 0
9490 01:00:36.504812 Checking cr50 for pending updates
9491 01:00:36.508760 Reading cr50 TPM mode
9492 01:00:36.517138 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 01:00:36.523600 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 01:00:36.563989 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9495 01:00:36.567114 Checking segment from ROM address 0x40100000
9496 01:00:36.570610 Checking segment from ROM address 0x4010001c
9497 01:00:36.577047 Loading segment from ROM address 0x40100000
9498 01:00:36.577680 code (compression=0)
9499 01:00:36.587210 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 01:00:36.593875 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 01:00:36.594362 it's not compressed!
9502 01:00:36.600546 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 01:00:36.603972 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 01:00:36.624407 Loading segment from ROM address 0x4010001c
9505 01:00:36.624888 Entry Point 0x80000000
9506 01:00:36.627690 Loaded segments
9507 01:00:36.630791 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 01:00:36.637360 Jumping to boot code at 0x80000000(0xffe64000)
9509 01:00:36.644305 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 01:00:36.650809 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 01:00:36.658793 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9512 01:00:36.662141 Checking segment from ROM address 0x40100000
9513 01:00:36.665318 Checking segment from ROM address 0x4010001c
9514 01:00:36.672113 Loading segment from ROM address 0x40100000
9515 01:00:36.672542 code (compression=1)
9516 01:00:36.678654 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 01:00:36.688585 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 01:00:36.689025 using LZMA
9519 01:00:36.697051 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 01:00:36.703626 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 01:00:36.706844 Loading segment from ROM address 0x4010001c
9522 01:00:36.707313 Entry Point 0x54601000
9523 01:00:36.710050 Loaded segments
9524 01:00:36.713228 NOTICE: MT8192 bl31_setup
9525 01:00:36.720550 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 01:00:36.723877 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 01:00:36.727460 WARNING: region 0:
9528 01:00:36.730742 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 01:00:36.731168 WARNING: region 1:
9530 01:00:36.737219 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 01:00:36.740539 WARNING: region 2:
9532 01:00:36.744035 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 01:00:36.747152 WARNING: region 3:
9534 01:00:36.750653 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 01:00:36.753839 WARNING: region 4:
9536 01:00:36.760312 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 01:00:36.760784 WARNING: region 5:
9538 01:00:36.763868 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 01:00:36.767259 WARNING: region 6:
9540 01:00:36.770756 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 01:00:36.774013 WARNING: region 7:
9542 01:00:36.777341 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 01:00:36.784188 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 01:00:36.787410 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 01:00:36.790526 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 01:00:36.797204 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 01:00:36.800619 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 01:00:36.803964 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 01:00:36.810742 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 01:00:36.813962 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 01:00:36.820910 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 01:00:36.823988 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 01:00:36.827241 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 01:00:36.833843 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 01:00:36.837443 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 01:00:36.840837 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 01:00:36.847430 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 01:00:36.850777 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 01:00:36.853923 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 01:00:36.860572 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 01:00:36.863949 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 01:00:36.870466 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 01:00:36.873931 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 01:00:36.877022 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 01:00:36.884081 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 01:00:36.887305 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 01:00:36.893807 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 01:00:36.897361 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 01:00:36.900576 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 01:00:36.907423 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 01:00:36.910730 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 01:00:36.913889 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 01:00:36.920600 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 01:00:36.923959 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 01:00:36.930498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 01:00:36.933827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 01:00:36.937315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 01:00:36.941003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 01:00:36.944039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 01:00:36.950449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 01:00:36.954018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 01:00:36.957373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 01:00:36.960670 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 01:00:36.966965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 01:00:36.970636 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 01:00:36.973750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 01:00:36.980407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 01:00:36.983547 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 01:00:36.987161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 01:00:36.990331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 01:00:36.997111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 01:00:37.000426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 01:00:37.006984 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 01:00:37.010128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 01:00:37.016985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 01:00:37.020344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 01:00:37.023515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 01:00:37.030405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 01:00:37.033675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 01:00:37.040616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 01:00:37.043873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 01:00:37.050257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 01:00:37.053626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 01:00:37.056865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 01:00:37.063892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 01:00:37.067087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 01:00:37.073649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 01:00:37.076880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 01:00:37.083853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 01:00:37.087182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 01:00:37.090376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 01:00:37.097044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 01:00:37.100201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 01:00:37.106904 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 01:00:37.110100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 01:00:37.116908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 01:00:37.120363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 01:00:37.123649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 01:00:37.130313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 01:00:37.133643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 01:00:37.140307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 01:00:37.143509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 01:00:37.150277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 01:00:37.153537 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 01:00:37.156884 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 01:00:37.163330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 01:00:37.166886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 01:00:37.173307 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 01:00:37.176644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 01:00:37.183395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 01:00:37.186573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 01:00:37.190290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 01:00:37.196937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 01:00:37.200011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 01:00:37.206900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 01:00:37.210038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 01:00:37.216725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 01:00:37.219941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 01:00:37.223411 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 01:00:37.229993 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 01:00:37.233319 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 01:00:37.236735 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 01:00:37.240158 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 01:00:37.246650 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 01:00:37.250081 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 01:00:37.256719 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 01:00:37.260099 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 01:00:37.263302 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 01:00:37.270120 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 01:00:37.273343 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 01:00:37.280076 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 01:00:37.283404 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 01:00:37.286523 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 01:00:37.293407 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 01:00:37.296697 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 01:00:37.303170 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 01:00:37.306553 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 01:00:37.309991 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 01:00:37.313190 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 01:00:37.319933 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 01:00:37.323523 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 01:00:37.326482 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 01:00:37.333072 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 01:00:37.336419 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 01:00:37.339530 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 01:00:37.346403 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 01:00:37.349579 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 01:00:37.353226 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 01:00:37.359771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 01:00:37.363300 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 01:00:37.366369 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 01:00:37.373189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 01:00:37.376418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 01:00:37.383225 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 01:00:37.386244 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 01:00:37.389642 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 01:00:37.396130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 01:00:37.399444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 01:00:37.406035 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 01:00:37.409587 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 01:00:37.412805 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 01:00:37.419608 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 01:00:37.422791 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 01:00:37.429334 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 01:00:37.432932 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 01:00:37.436223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 01:00:37.442839 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 01:00:37.446208 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 01:00:37.449364 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 01:00:37.456215 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 01:00:37.459544 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 01:00:37.466121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 01:00:37.469412 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 01:00:37.472975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 01:00:37.479511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 01:00:37.482651 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 01:00:37.489371 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 01:00:37.492961 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 01:00:37.496349 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 01:00:37.502851 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 01:00:37.506058 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 01:00:37.512777 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 01:00:37.515885 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 01:00:37.519349 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 01:00:37.525892 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 01:00:37.529120 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 01:00:37.535914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 01:00:37.539089 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 01:00:37.542403 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 01:00:37.549229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 01:00:37.552650 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 01:00:37.555681 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 01:00:37.562199 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 01:00:37.565404 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 01:00:37.572004 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 01:00:37.575731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 01:00:37.578682 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 01:00:37.585456 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 01:00:37.588779 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 01:00:37.595431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 01:00:37.598660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 01:00:37.602036 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 01:00:37.608448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 01:00:37.611650 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 01:00:37.618323 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 01:00:37.621757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 01:00:37.625051 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 01:00:37.631809 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 01:00:37.635029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 01:00:37.641591 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 01:00:37.644767 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 01:00:37.648333 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 01:00:37.654838 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 01:00:37.658121 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 01:00:37.664962 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 01:00:37.668139 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 01:00:37.674618 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 01:00:37.677978 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 01:00:37.681596 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 01:00:37.688084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 01:00:37.691334 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 01:00:37.697863 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 01:00:37.701031 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 01:00:37.707935 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 01:00:37.711063 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 01:00:37.714334 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 01:00:37.720955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 01:00:37.724390 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 01:00:37.731208 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 01:00:37.734312 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 01:00:37.737538 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 01:00:37.744759 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 01:00:37.747677 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 01:00:37.754205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 01:00:37.757685 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 01:00:37.764116 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 01:00:37.767409 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 01:00:37.770719 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 01:00:37.777314 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 01:00:37.780595 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 01:00:37.787285 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 01:00:37.790590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 01:00:37.797124 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 01:00:37.800554 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 01:00:37.803963 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 01:00:37.810403 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 01:00:37.813750 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 01:00:37.820206 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 01:00:37.823564 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 01:00:37.826858 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 01:00:37.833622 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 01:00:37.836952 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 01:00:37.840348 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 01:00:37.846693 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 01:00:37.850245 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 01:00:37.853467 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 01:00:37.856826 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 01:00:37.863335 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 01:00:37.866584 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 01:00:37.873133 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 01:00:37.876617 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 01:00:37.879840 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 01:00:37.886445 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 01:00:37.889756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 01:00:37.892842 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 01:00:37.899631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 01:00:37.902891 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 01:00:37.909730 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 01:00:37.912804 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 01:00:37.915936 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 01:00:37.922793 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 01:00:37.925759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 01:00:37.929465 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 01:00:37.935783 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 01:00:37.939424 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 01:00:37.942477 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 01:00:37.949286 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 01:00:37.952631 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 01:00:37.959347 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 01:00:37.962304 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 01:00:37.965832 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 01:00:37.972563 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 01:00:37.975512 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 01:00:37.978887 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 01:00:37.985747 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 01:00:37.989008 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 01:00:37.995654 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 01:00:37.998881 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 01:00:38.002325 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 01:00:38.008764 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 01:00:38.012126 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 01:00:38.015264 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 01:00:38.018834 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 01:00:38.025542 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 01:00:38.028738 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 01:00:38.032011 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 01:00:38.035399 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 01:00:38.041956 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 01:00:38.045180 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 01:00:38.048372 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 01:00:38.051815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 01:00:38.058547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 01:00:38.061562 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 01:00:38.064835 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 01:00:38.071843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 01:00:38.074744 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 01:00:38.081626 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 01:00:38.084707 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 01:00:38.088277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 01:00:38.094696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 01:00:38.098135 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 01:00:38.104814 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 01:00:38.108131 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 01:00:38.111368 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 01:00:38.117971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 01:00:38.121436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 01:00:38.127808 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 01:00:38.131107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 01:00:38.137934 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 01:00:38.141138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 01:00:38.144275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 01:00:38.151039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 01:00:38.154630 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 01:00:38.161121 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 01:00:38.164639 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 01:00:38.167615 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 01:00:38.174338 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 01:00:38.177572 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 01:00:38.184706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 01:00:38.187638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 01:00:38.190960 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 01:00:38.197548 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 01:00:38.200910 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 01:00:38.207494 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 01:00:38.210943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 01:00:38.214216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 01:00:38.220789 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 01:00:38.224007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 01:00:38.230738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 01:00:38.233856 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 01:00:38.240528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 01:00:38.243588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 01:00:38.247210 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 01:00:38.253695 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 01:00:38.257115 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 01:00:38.263555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 01:00:38.266832 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 01:00:38.270217 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 01:00:38.276764 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 01:00:38.279965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 01:00:38.286869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 01:00:38.289916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 01:00:38.296432 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 01:00:38.299846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 01:00:38.303410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 01:00:38.309836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 01:00:38.313060 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 01:00:38.319681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 01:00:38.323159 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 01:00:38.326352 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 01:00:38.332997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 01:00:38.336154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 01:00:38.343074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 01:00:38.346037 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 01:00:38.352646 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 01:00:38.356007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 01:00:38.359199 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 01:00:38.365962 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 01:00:38.369269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 01:00:38.375756 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 01:00:38.379180 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 01:00:38.382426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 01:00:38.389020 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 01:00:38.392512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 01:00:38.399114 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 01:00:38.402029 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 01:00:38.408720 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 01:00:38.411987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 01:00:38.415413 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 01:00:38.422060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 01:00:38.425035 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 01:00:38.431887 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 01:00:38.435243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 01:00:38.441747 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 01:00:38.445238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 01:00:38.451524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 01:00:38.454757 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 01:00:38.458116 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 01:00:38.464952 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 01:00:38.468258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 01:00:38.474898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 01:00:38.478005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 01:00:38.484480 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 01:00:38.487984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 01:00:38.494514 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 01:00:38.498019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 01:00:38.501173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 01:00:38.507822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 01:00:38.510959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 01:00:38.517610 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 01:00:38.521102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 01:00:38.527749 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 01:00:38.531029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 01:00:38.537385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 01:00:38.540906 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 01:00:38.543913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 01:00:38.550730 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 01:00:38.554350 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 01:00:38.560996 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 01:00:38.564040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 01:00:38.570849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 01:00:38.574050 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 01:00:38.577538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 01:00:38.584084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 01:00:38.587301 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 01:00:38.594174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 01:00:38.597322 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 01:00:38.604047 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 01:00:38.607259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 01:00:38.610580 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 01:00:38.617190 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 01:00:38.620333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 01:00:38.627102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 01:00:38.630239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 01:00:38.636954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 01:00:38.640173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 01:00:38.643306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 01:00:38.649803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 01:00:38.653534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 01:00:38.659853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 01:00:38.663203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 01:00:38.669937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 01:00:38.673157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 01:00:38.679613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 01:00:38.683051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 01:00:38.689580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 01:00:38.692764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 01:00:38.699509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 01:00:38.703091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 01:00:38.709260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 01:00:38.712567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 01:00:38.719202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 01:00:38.722676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 01:00:38.729326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 01:00:38.732696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 01:00:38.739106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 01:00:38.742430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 01:00:38.749229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 01:00:38.752602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 01:00:38.759010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 01:00:38.762150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 01:00:38.769052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 01:00:38.772267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 01:00:38.778877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 01:00:38.782141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 01:00:38.788642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 01:00:38.791886 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 01:00:38.795207 INFO: [APUAPC] vio 0
9979 01:00:38.798667 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 01:00:38.805297 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 01:00:38.808605 INFO: [APUAPC] D0_APC_0: 0x400510
9982 01:00:38.811692 INFO: [APUAPC] D0_APC_1: 0x0
9983 01:00:38.815156 INFO: [APUAPC] D0_APC_2: 0x1540
9984 01:00:38.815606 INFO: [APUAPC] D0_APC_3: 0x0
9985 01:00:38.818434 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 01:00:38.821582 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 01:00:38.824899 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 01:00:38.828251 INFO: [APUAPC] D1_APC_3: 0x0
9989 01:00:38.831512 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 01:00:38.834777 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 01:00:38.838310 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 01:00:38.841460 INFO: [APUAPC] D2_APC_3: 0x0
9993 01:00:38.844580 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 01:00:38.847805 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 01:00:38.851374 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 01:00:38.854392 INFO: [APUAPC] D3_APC_3: 0x0
9997 01:00:38.857914 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 01:00:38.861208 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 01:00:38.864296 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 01:00:38.867968 INFO: [APUAPC] D4_APC_3: 0x0
10001 01:00:38.871244 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 01:00:38.874594 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 01:00:38.877891 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 01:00:38.881155 INFO: [APUAPC] D5_APC_3: 0x0
10005 01:00:38.884342 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 01:00:38.887433 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 01:00:38.891044 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 01:00:38.893970 INFO: [APUAPC] D6_APC_3: 0x0
10009 01:00:38.897279 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 01:00:38.900957 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 01:00:38.904282 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 01:00:38.907515 INFO: [APUAPC] D7_APC_3: 0x0
10013 01:00:38.910833 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 01:00:38.913747 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 01:00:38.917249 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 01:00:38.920481 INFO: [APUAPC] D8_APC_3: 0x0
10017 01:00:38.923731 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 01:00:38.927175 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 01:00:38.930572 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 01:00:38.933856 INFO: [APUAPC] D9_APC_3: 0x0
10021 01:00:38.936958 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 01:00:38.940368 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 01:00:38.943630 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 01:00:38.946928 INFO: [APUAPC] D10_APC_3: 0x0
10025 01:00:38.950171 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 01:00:38.954012 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 01:00:38.956781 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 01:00:38.960071 INFO: [APUAPC] D11_APC_3: 0x0
10029 01:00:38.963490 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 01:00:38.966572 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 01:00:38.970215 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 01:00:38.973545 INFO: [APUAPC] D12_APC_3: 0x0
10033 01:00:38.976941 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 01:00:38.980267 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 01:00:38.983570 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 01:00:38.986916 INFO: [APUAPC] D13_APC_3: 0x0
10037 01:00:38.990122 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 01:00:38.993519 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 01:00:38.996823 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 01:00:38.999819 INFO: [APUAPC] D14_APC_3: 0x0
10041 01:00:39.003201 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 01:00:39.006325 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 01:00:39.009764 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 01:00:39.012948 INFO: [APUAPC] D15_APC_3: 0x0
10045 01:00:39.016078 INFO: [APUAPC] APC_CON: 0x4
10046 01:00:39.019634 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 01:00:39.022790 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 01:00:39.026226 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 01:00:39.029652 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 01:00:39.032844 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 01:00:39.033269 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 01:00:39.036188 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 01:00:39.039295 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 01:00:39.042557 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 01:00:39.046135 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 01:00:39.049398 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 01:00:39.052580 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 01:00:39.056224 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 01:00:39.059246 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 01:00:39.062738 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 01:00:39.066117 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 01:00:39.066544 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 01:00:39.069197 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 01:00:39.072489 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 01:00:39.075945 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 01:00:39.078810 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 01:00:39.082081 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 01:00:39.085578 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 01:00:39.088882 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 01:00:39.092442 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 01:00:39.095607 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 01:00:39.098795 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 01:00:39.102067 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 01:00:39.105421 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 01:00:39.108687 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 01:00:39.112134 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 01:00:39.115359 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 01:00:39.115799 INFO: [NOCDAPC] APC_CON: 0x4
10079 01:00:39.118820 INFO: [APUAPC] set_apusys_apc done
10080 01:00:39.121728 INFO: [DEVAPC] devapc_init done
10081 01:00:39.128341 INFO: GICv3 without legacy support detected.
10082 01:00:39.131668 INFO: ARM GICv3 driver initialized in EL3
10083 01:00:39.134859 INFO: Maximum SPI INTID supported: 639
10084 01:00:39.138404 INFO: BL31: Initializing runtime services
10085 01:00:39.144730 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 01:00:39.148369 INFO: SPM: enable CPC mode
10087 01:00:39.151577 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 01:00:39.158349 INFO: BL31: Preparing for EL3 exit to normal world
10089 01:00:39.161614 INFO: Entry point address = 0x80000000
10090 01:00:39.162057 INFO: SPSR = 0x8
10091 01:00:39.168799
10092 01:00:39.169237
10093 01:00:39.169751
10094 01:00:39.171905 Starting depthcharge on Spherion...
10095 01:00:39.172345
10096 01:00:39.172794 Wipe memory regions:
10097 01:00:39.173214
10098 01:00:39.175922 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 01:00:39.176493 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 01:00:39.176944 Setting prompt string to ['asurada:']
10101 01:00:39.177455 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 01:00:39.178272 [0x00000040000000, 0x00000054600000)
10103 01:00:39.297974
10104 01:00:39.298557 [0x00000054660000, 0x00000080000000)
10105 01:00:39.558041
10106 01:00:39.558590 [0x000000821a7280, 0x000000ffe64000)
10107 01:00:40.303124
10108 01:00:40.303699 [0x00000100000000, 0x00000240000000)
10109 01:00:42.193131
10110 01:00:42.195957 Initializing XHCI USB controller at 0x11200000.
10111 01:00:43.234663
10112 01:00:43.237834 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 01:00:43.238277
10114 01:00:43.238724
10115 01:00:43.239140
10116 01:00:43.239992 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 01:00:43.341387 asurada: tftpboot 192.168.201.1 12571114/tftp-deploy-9rsx53qq/kernel/image.itb 12571114/tftp-deploy-9rsx53qq/kernel/cmdline
10119 01:00:43.342199 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 01:00:43.342701 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 01:00:43.347009 tftpboot 192.168.201.1 12571114/tftp-deploy-9rsx53qq/kernel/image.itp-deploy-9rsx53qq/kernel/cmdline
10122 01:00:43.347443
10123 01:00:43.347870 Waiting for link
10124 01:00:43.507848
10125 01:00:43.508422 R8152: Initializing
10126 01:00:43.508801
10127 01:00:43.511066 Version 6 (ocp_data = 5c30)
10128 01:00:43.511640
10129 01:00:43.514090 R8152: Done initializing
10130 01:00:43.514518
10131 01:00:43.514853 Adding net device
10132 01:00:45.539263
10133 01:00:45.539399 done.
10134 01:00:45.539467
10135 01:00:45.539529 MAC: 00:24:32:30:78:ff
10136 01:00:45.539589
10137 01:00:45.542467 Sending DHCP discover... done.
10138 01:00:45.542550
10139 01:00:45.545712 Waiting for reply... done.
10140 01:00:45.545823
10141 01:00:45.549297 Sending DHCP request... done.
10142 01:00:45.549412
10143 01:00:45.549549 Waiting for reply... done.
10144 01:00:45.549636
10145 01:00:45.552856 My ip is 192.168.201.21
10146 01:00:45.552932
10147 01:00:45.555829 The DHCP server ip is 192.168.201.1
10148 01:00:45.555903
10149 01:00:45.559068 TFTP server IP predefined by user: 192.168.201.1
10150 01:00:45.559146
10151 01:00:45.566132 Bootfile predefined by user: 12571114/tftp-deploy-9rsx53qq/kernel/image.itb
10152 01:00:45.566208
10153 01:00:45.569373 Sending tftp read request... done.
10154 01:00:45.569471
10155 01:00:45.572713 Waiting for the transfer...
10156 01:00:45.572786
10157 01:00:46.154205 00000000 ################################################################
10158 01:00:46.154721
10159 01:00:46.769327 00080000 ################################################################
10160 01:00:46.769506
10161 01:00:47.347999 00100000 ################################################################
10162 01:00:47.348137
10163 01:00:48.063834 00180000 ################################################################
10164 01:00:48.064347
10165 01:00:48.798811 00200000 ################################################################
10166 01:00:48.799356
10167 01:00:49.553850 00280000 ################################################################
10168 01:00:49.554389
10169 01:00:50.291492 00300000 ################################################################
10170 01:00:50.292010
10171 01:00:51.019409 00380000 ################################################################
10172 01:00:51.019936
10173 01:00:51.743942 00400000 ################################################################
10174 01:00:51.744457
10175 01:00:52.498269 00480000 ################################################################
10176 01:00:52.498845
10177 01:00:53.245033 00500000 ################################################################
10178 01:00:53.245611
10179 01:00:53.988283 00580000 ################################################################
10180 01:00:53.988817
10181 01:00:54.740130 00600000 ################################################################
10182 01:00:54.740846
10183 01:00:55.493668 00680000 ################################################################
10184 01:00:55.494192
10185 01:00:56.255526 00700000 ################################################################
10186 01:00:56.256092
10187 01:00:57.021108 00780000 ################################################################
10188 01:00:57.021687
10189 01:00:57.782920 00800000 ################################################################
10190 01:00:57.783498
10191 01:00:58.546183 00880000 ################################################################
10192 01:00:58.546718
10193 01:00:59.306415 00900000 ################################################################
10194 01:00:59.306951
10195 01:01:00.059527 00980000 ################################################################
10196 01:01:00.060054
10197 01:01:00.733715 00a00000 ################################################################
10198 01:01:00.733847
10199 01:01:01.375130 00a80000 ################################################################
10200 01:01:01.375294
10201 01:01:01.977864 00b00000 ################################################################
10202 01:01:01.978049
10203 01:01:02.709810 00b80000 ################################################################
10204 01:01:02.710320
10205 01:01:03.457259 00c00000 ################################################################
10206 01:01:03.457935
10207 01:01:04.218318 00c80000 ################################################################
10208 01:01:04.218900
10209 01:01:04.928034 00d00000 ################################################################
10210 01:01:04.928561
10211 01:01:05.616262 00d80000 ################################################################
10212 01:01:05.616789
10213 01:01:06.322325 00e00000 ################################################################
10214 01:01:06.322461
10215 01:01:06.951420 00e80000 ################################################################
10216 01:01:06.951565
10217 01:01:07.610540 00f00000 ################################################################
10218 01:01:07.611190
10219 01:01:08.274787 00f80000 ################################################################
10220 01:01:08.275285
10221 01:01:08.923964 01000000 ################################################################
10222 01:01:08.924570
10223 01:01:09.561547 01080000 ################################################################
10224 01:01:09.561886
10225 01:01:10.232240 01100000 ################################################################
10226 01:01:10.232390
10227 01:01:10.804633 01180000 ################################################################
10228 01:01:10.804782
10229 01:01:11.344301 01200000 ################################################################
10230 01:01:11.344450
10231 01:01:11.930325 01280000 ################################################################
10232 01:01:11.930469
10233 01:01:12.510705 01300000 ################################################################
10234 01:01:12.511322
10235 01:01:13.071727 01380000 ################################################################
10236 01:01:13.071866
10237 01:01:13.624761 01400000 ################################################################
10238 01:01:13.624899
10239 01:01:14.196124 01480000 ################################################################
10240 01:01:14.196263
10241 01:01:14.761447 01500000 ################################################################
10242 01:01:14.761621
10243 01:01:15.459374 01580000 ################################################################
10244 01:01:15.460002
10245 01:01:16.169187 01600000 ################################################################
10246 01:01:16.169841
10247 01:01:16.866752 01680000 ################################################################
10248 01:01:16.867270
10249 01:01:17.450673 01700000 ################################################################
10250 01:01:17.450815
10251 01:01:18.041071 01780000 ################################################################
10252 01:01:18.041281
10253 01:01:18.720168 01800000 ################################################################
10254 01:01:18.720678
10255 01:01:19.345186 01880000 ################################################################
10256 01:01:19.345331
10257 01:01:19.935197 01900000 ################################################################
10258 01:01:19.935346
10259 01:01:20.496380 01980000 ################################################################
10260 01:01:20.496536
10261 01:01:21.090743 01a00000 ################################################################
10262 01:01:21.090895
10263 01:01:21.645494 01a80000 ################################################################
10264 01:01:21.645653
10265 01:01:22.224871 01b00000 ################################################################
10266 01:01:22.225395
10267 01:01:22.814758 01b80000 ################################################################
10268 01:01:22.815293
10269 01:01:23.449102 01c00000 ################################################################
10270 01:01:23.449300
10271 01:01:23.468418 01c80000 ### done.
10272 01:01:23.468624
10273 01:01:23.471621 The bootfile was 29902086 bytes long.
10274 01:01:23.471824
10275 01:01:23.475215 Sending tftp read request... done.
10276 01:01:23.475456
10277 01:01:23.478502 Waiting for the transfer...
10278 01:01:23.478801
10279 01:01:23.479037 00000000 # done.
10280 01:01:23.479266
10281 01:01:23.488471 Command line loaded dynamically from TFTP file: 12571114/tftp-deploy-9rsx53qq/kernel/cmdline
10282 01:01:23.488903
10283 01:01:23.508561 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10284 01:01:23.509046
10285 01:01:23.511729 Loading FIT.
10286 01:01:23.512155
10287 01:01:23.514885 Image ramdisk-1 has 17804151 bytes.
10288 01:01:23.515343
10289 01:01:23.515696 Image fdt-1 has 47278 bytes.
10290 01:01:23.516020
10291 01:01:23.518061 Image kernel-1 has 12048624 bytes.
10292 01:01:23.518488
10293 01:01:23.528187 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10294 01:01:23.528637
10295 01:01:23.544520 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 01:01:23.544976
10297 01:01:23.551303 Choosing best match conf-1 for compat google,spherion-rev2.
10298 01:01:23.555329
10299 01:01:23.559884 Connected to device vid:did:rid of 1ae0:0028:00
10300 01:01:23.566849
10301 01:01:23.569911 tpm_get_response: command 0x17b, return code 0x0
10302 01:01:23.570340
10303 01:01:23.573595 ec_init: CrosEC protocol v3 supported (256, 248)
10304 01:01:23.578708
10305 01:01:23.582157 tpm_cleanup: add release locality here.
10306 01:01:23.582684
10307 01:01:23.583022 Shutting down all USB controllers.
10308 01:01:23.585310
10309 01:01:23.585764 Removing current net device
10310 01:01:23.586105
10311 01:01:23.592312 Exiting depthcharge with code 4 at timestamp: 73705936
10312 01:01:23.592848
10313 01:01:23.595308 LZMA decompressing kernel-1 to 0x821a6718
10314 01:01:23.595736
10315 01:01:23.598544 LZMA decompressing kernel-1 to 0x40000000
10316 01:01:25.096922
10317 01:01:25.097433 jumping to kernel
10318 01:01:25.099099 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10319 01:01:25.099598 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10320 01:01:25.099986 Setting prompt string to ['Linux version [0-9]']
10321 01:01:25.100349 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 01:01:25.100711 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 01:01:25.178899
10324 01:01:25.182144 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 01:01:25.185911 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10326 01:01:25.186370 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 01:01:25.186738 Setting prompt string to []
10328 01:01:25.187126 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 01:01:25.187499 Using line separator: #'\n'#
10330 01:01:25.187880 No login prompt set.
10331 01:01:25.188205 Parsing kernel messages
10332 01:01:25.188494 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 01:01:25.189002 [login-action] Waiting for messages, (timeout 00:03:39)
10334 01:01:25.205150 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10335 01:01:25.208457 [ 0.000000] random: crng init done
10336 01:01:25.215003 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 01:01:25.218192 [ 0.000000] efi: UEFI not found.
10338 01:01:25.225098 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 01:01:25.231678 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 01:01:25.241420 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 01:01:25.251560 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 01:01:25.257830 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 01:01:25.264363 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 01:01:25.271136 [ 0.000000] NUMA: No NUMA configuration found
10345 01:01:25.277788 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 01:01:25.280947 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10347 01:01:25.284410 [ 0.000000] Zone ranges:
10348 01:01:25.290936 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 01:01:25.294483 [ 0.000000] DMA32 empty
10350 01:01:25.301017 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 01:01:25.304283 [ 0.000000] Movable zone start for each node
10352 01:01:25.307569 [ 0.000000] Early memory node ranges
10353 01:01:25.314007 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 01:01:25.320642 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 01:01:25.327468 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 01:01:25.333912 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 01:01:25.340481 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 01:01:25.347058 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 01:01:25.403337 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 01:01:25.410170 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 01:01:25.416456 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 01:01:25.420050 [ 0.000000] psci: probing for conduit method from DT.
10363 01:01:25.426695 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 01:01:25.429980 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 01:01:25.436466 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 01:01:25.439770 [ 0.000000] psci: SMC Calling Convention v1.2
10367 01:01:25.446282 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10368 01:01:25.449695 [ 0.000000] Detected VIPT I-cache on CPU0
10369 01:01:25.456325 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 01:01:25.462784 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 01:01:25.469357 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 01:01:25.475950 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 01:01:25.482917 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 01:01:25.492715 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 01:01:25.496049 [ 0.000000] alternatives: applying boot alternatives
10376 01:01:25.502735 [ 0.000000] Fallback order for Node 0: 0
10377 01:01:25.509369 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 01:01:25.512614 [ 0.000000] Policy zone: Normal
10379 01:01:25.535971 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10380 01:01:25.545727 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 01:01:25.555564 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 01:01:25.565604 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 01:01:25.572178 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 01:01:25.575448 <6>[ 0.000000] software IO TLB: area num 8.
10385 01:01:25.631530 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 01:01:25.780914 <6>[ 0.000000] Memory: 7949872K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402896K reserved, 32768K cma-reserved)
10387 01:01:25.787666 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 01:01:25.794171 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 01:01:25.797518 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 01:01:25.803972 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 01:01:25.810731 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 01:01:25.814507 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 01:01:25.823881 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 01:01:25.830835 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 01:01:25.837178 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 01:01:25.843895 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 01:01:25.847102 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 01:01:25.850360 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 01:01:25.857199 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 01:01:25.860392 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 01:01:25.867079 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 01:01:25.880150 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 01:01:25.889813 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 01:01:25.899631 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 01:01:25.906797 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 01:01:25.920114 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 01:01:25.926525 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 01:01:25.933610 <6>[ 0.009186] Console: colour dummy device 80x25
10409 01:01:25.943374 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 01:01:25.949991 <6>[ 0.024354] pid_max: default: 32768 minimum: 301
10411 01:01:25.953438 <6>[ 0.029219] LSM: Security Framework initializing
10412 01:01:25.959799 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 01:01:25.969610 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 01:01:25.979900 <6>[ 0.051479] cblist_init_generic: Setting adjustable number of callback queues.
10415 01:01:25.983052 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 01:01:25.992959 <6>[ 0.065297] cblist_init_generic: Setting adjustable number of callback queues.
10417 01:01:25.999444 <6>[ 0.072770] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 01:01:26.002784 <6>[ 0.079213] rcu: Hierarchical SRCU implementation.
10419 01:01:26.009420 <6>[ 0.084228] rcu: Max phase no-delay instances is 1000.
10420 01:01:26.015949 <6>[ 0.091251] EFI services will not be available.
10421 01:01:26.019238 <6>[ 0.096195] smp: Bringing up secondary CPUs ...
10422 01:01:26.027994 <6>[ 0.101242] Detected VIPT I-cache on CPU1
10423 01:01:26.034775 <6>[ 0.101312] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 01:01:26.041895 <6>[ 0.101345] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 01:01:26.045230 <6>[ 0.101680] Detected VIPT I-cache on CPU2
10426 01:01:26.051445 <6>[ 0.101727] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 01:01:26.058189 <6>[ 0.101743] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 01:01:26.064824 <6>[ 0.101999] Detected VIPT I-cache on CPU3
10429 01:01:26.071909 <6>[ 0.102043] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 01:01:26.078082 <6>[ 0.102057] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 01:01:26.081538 <6>[ 0.102359] CPU features: detected: Spectre-v4
10432 01:01:26.087919 <6>[ 0.102366] CPU features: detected: Spectre-BHB
10433 01:01:26.091202 <6>[ 0.102371] Detected PIPT I-cache on CPU4
10434 01:01:26.097750 <6>[ 0.102427] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 01:01:26.104644 <6>[ 0.102444] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 01:01:26.111158 <6>[ 0.102738] Detected PIPT I-cache on CPU5
10437 01:01:26.117758 <6>[ 0.102804] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 01:01:26.124400 <6>[ 0.102821] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 01:01:26.127641 <6>[ 0.103102] Detected PIPT I-cache on CPU6
10440 01:01:26.134494 <6>[ 0.103167] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 01:01:26.141099 <6>[ 0.103184] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 01:01:26.147515 <6>[ 0.103482] Detected PIPT I-cache on CPU7
10443 01:01:26.154160 <6>[ 0.103546] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 01:01:26.161108 <6>[ 0.103562] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 01:01:26.164242 <6>[ 0.103610] smp: Brought up 1 node, 8 CPUs
10446 01:01:26.170845 <6>[ 0.245066] SMP: Total of 8 processors activated.
10447 01:01:26.174131 <6>[ 0.249987] CPU features: detected: 32-bit EL0 Support
10448 01:01:26.184400 <6>[ 0.255384] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 01:01:26.190702 <6>[ 0.264184] CPU features: detected: Common not Private translations
10450 01:01:26.197205 <6>[ 0.270660] CPU features: detected: CRC32 instructions
10451 01:01:26.200641 <6>[ 0.276011] CPU features: detected: RCpc load-acquire (LDAPR)
10452 01:01:26.207242 <6>[ 0.281971] CPU features: detected: LSE atomic instructions
10453 01:01:26.214099 <6>[ 0.287789] CPU features: detected: Privileged Access Never
10454 01:01:26.220462 <6>[ 0.293604] CPU features: detected: RAS Extension Support
10455 01:01:26.227209 <6>[ 0.299248] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 01:01:26.230525 <6>[ 0.306467] CPU: All CPU(s) started at EL2
10457 01:01:26.236955 <6>[ 0.310810] alternatives: applying system-wide alternatives
10458 01:01:26.246279 <6>[ 0.321531] devtmpfs: initialized
10459 01:01:26.261585 <6>[ 0.330384] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10460 01:01:26.268245 <6>[ 0.340344] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10461 01:01:26.271482 <6>[ 0.347944] pinctrl core: initialized pinctrl subsystem
10462 01:01:26.279043 <6>[ 0.354571] DMI not present or invalid.
10463 01:01:26.285920 <6>[ 0.358978] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10464 01:01:26.292487 <6>[ 0.365843] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10465 01:01:26.302416 <6>[ 0.373433] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10466 01:01:26.309001 <6>[ 0.381656] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10467 01:01:26.315481 <6>[ 0.389900] audit: initializing netlink subsys (disabled)
10468 01:01:26.321975 <5>[ 0.395591] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10469 01:01:26.328763 <6>[ 0.396277] thermal_sys: Registered thermal governor 'step_wise'
10470 01:01:26.335696 <6>[ 0.403562] thermal_sys: Registered thermal governor 'power_allocator'
10471 01:01:26.342087 <6>[ 0.409815] cpuidle: using governor menu
10472 01:01:26.345535 <6>[ 0.420775] NET: Registered PF_QIPCRTR protocol family
10473 01:01:26.351887 <6>[ 0.426257] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10474 01:01:26.358649 <6>[ 0.433359] ASID allocator initialised with 32768 entries
10475 01:01:26.365415 <6>[ 0.439909] Serial: AMBA PL011 UART driver
10476 01:01:26.373640 <4>[ 0.448637] Trying to register duplicate clock ID: 134
10477 01:01:26.427236 <6>[ 0.505714] KASLR enabled
10478 01:01:26.441577 <6>[ 0.513426] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10479 01:01:26.448092 <6>[ 0.520440] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10480 01:01:26.454540 <6>[ 0.526930] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10481 01:01:26.461061 <6>[ 0.533936] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10482 01:01:26.467722 <6>[ 0.540424] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10483 01:01:26.474250 <6>[ 0.547426] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10484 01:01:26.480769 <6>[ 0.553913] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10485 01:01:26.487404 <6>[ 0.560916] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10486 01:01:26.490781 <6>[ 0.568425] ACPI: Interpreter disabled.
10487 01:01:26.499590 <6>[ 0.574844] iommu: Default domain type: Translated
10488 01:01:26.506279 <6>[ 0.579958] iommu: DMA domain TLB invalidation policy: strict mode
10489 01:01:26.509549 <5>[ 0.586617] SCSI subsystem initialized
10490 01:01:26.516114 <6>[ 0.590780] usbcore: registered new interface driver usbfs
10491 01:01:26.522866 <6>[ 0.596513] usbcore: registered new interface driver hub
10492 01:01:26.525931 <6>[ 0.602064] usbcore: registered new device driver usb
10493 01:01:26.532849 <6>[ 0.608158] pps_core: LinuxPPS API ver. 1 registered
10494 01:01:26.542845 <6>[ 0.613352] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10495 01:01:26.546111 <6>[ 0.622698] PTP clock support registered
10496 01:01:26.549267 <6>[ 0.626942] EDAC MC: Ver: 3.0.0
10497 01:01:26.556824 <6>[ 0.632102] FPGA manager framework
10498 01:01:26.563436 <6>[ 0.635782] Advanced Linux Sound Architecture Driver Initialized.
10499 01:01:26.566779 <6>[ 0.642557] vgaarb: loaded
10500 01:01:26.573288 <6>[ 0.645713] clocksource: Switched to clocksource arch_sys_counter
10501 01:01:26.576408 <5>[ 0.652159] VFS: Disk quotas dquot_6.6.0
10502 01:01:26.583096 <6>[ 0.656345] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10503 01:01:26.586417 <6>[ 0.663533] pnp: PnP ACPI: disabled
10504 01:01:26.594949 <6>[ 0.670219] NET: Registered PF_INET protocol family
10505 01:01:26.604644 <6>[ 0.675815] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10506 01:01:26.616089 <6>[ 0.688129] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10507 01:01:26.626087 <6>[ 0.696947] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10508 01:01:26.632792 <6>[ 0.704920] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10509 01:01:26.642417 <6>[ 0.713617] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10510 01:01:26.649096 <6>[ 0.723378] TCP: Hash tables configured (established 65536 bind 65536)
10511 01:01:26.655583 <6>[ 0.730244] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 01:01:26.665561 <6>[ 0.737444] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 01:01:26.672328 <6>[ 0.745149] NET: Registered PF_UNIX/PF_LOCAL protocol family
10514 01:01:26.675550 <6>[ 0.751302] RPC: Registered named UNIX socket transport module.
10515 01:01:26.682284 <6>[ 0.757453] RPC: Registered udp transport module.
10516 01:01:26.685339 <6>[ 0.762387] RPC: Registered tcp transport module.
10517 01:01:26.695372 <6>[ 0.767320] RPC: Registered tcp NFSv4.1 backchannel transport module.
10518 01:01:26.698756 <6>[ 0.773987] PCI: CLS 0 bytes, default 64
10519 01:01:26.702040 <6>[ 0.778302] Unpacking initramfs...
10520 01:01:26.718204 <6>[ 0.790269] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10521 01:01:26.728324 <6>[ 0.798934] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10522 01:01:26.731371 <6>[ 0.807791] kvm [1]: IPA Size Limit: 40 bits
10523 01:01:26.738078 <6>[ 0.812321] kvm [1]: GICv3: no GICV resource entry
10524 01:01:26.741447 <6>[ 0.817341] kvm [1]: disabling GICv2 emulation
10525 01:01:26.747857 <6>[ 0.822029] kvm [1]: GIC system register CPU interface enabled
10526 01:01:26.751500 <6>[ 0.828203] kvm [1]: vgic interrupt IRQ18
10527 01:01:26.757922 <6>[ 0.832562] kvm [1]: VHE mode initialized successfully
10528 01:01:26.764431 <5>[ 0.839084] Initialise system trusted keyrings
10529 01:01:26.771025 <6>[ 0.843881] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10530 01:01:26.778659 <6>[ 0.853845] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10531 01:01:26.785181 <5>[ 0.860233] NFS: Registering the id_resolver key type
10532 01:01:26.788420 <5>[ 0.865535] Key type id_resolver registered
10533 01:01:26.795123 <5>[ 0.869950] Key type id_legacy registered
10534 01:01:26.801447 <6>[ 0.874230] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10535 01:01:26.808080 <6>[ 0.881152] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10536 01:01:26.814660 <6>[ 0.888874] 9p: Installing v9fs 9p2000 file system support
10537 01:01:26.850979 <5>[ 0.926233] Key type asymmetric registered
10538 01:01:26.854043 <5>[ 0.930562] Asymmetric key parser 'x509' registered
10539 01:01:26.864398 <6>[ 0.935706] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10540 01:01:26.867609 <6>[ 0.943319] io scheduler mq-deadline registered
10541 01:01:26.870912 <6>[ 0.948100] io scheduler kyber registered
10542 01:01:26.890228 <6>[ 0.965065] EINJ: ACPI disabled.
10543 01:01:26.921880 <4>[ 0.990466] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 01:01:26.931648 <4>[ 1.001105] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 01:01:26.946498 <6>[ 1.021813] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10546 01:01:26.954388 <6>[ 1.029826] printk: console [ttyS0] disabled
10547 01:01:26.982759 <6>[ 1.054470] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10548 01:01:26.989034 <6>[ 1.063952] printk: console [ttyS0] enabled
10549 01:01:26.992373 <6>[ 1.063952] printk: console [ttyS0] enabled
10550 01:01:26.999036 <6>[ 1.072850] printk: bootconsole [mtk8250] disabled
10551 01:01:27.002187 <6>[ 1.072850] printk: bootconsole [mtk8250] disabled
10552 01:01:27.009365 <6>[ 1.084210] SuperH (H)SCI(F) driver initialized
10553 01:01:27.012209 <6>[ 1.089490] msm_serial: driver initialized
10554 01:01:27.026572 <6>[ 1.098511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10555 01:01:27.036255 <6>[ 1.107060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10556 01:01:27.043262 <6>[ 1.115602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10557 01:01:27.052982 <6>[ 1.124232] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10558 01:01:27.062780 <6>[ 1.132939] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10559 01:01:27.069514 <6>[ 1.141663] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10560 01:01:27.079249 <6>[ 1.150208] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10561 01:01:27.085769 <6>[ 1.159020] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10562 01:01:27.095690 <6>[ 1.167567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10563 01:01:27.107665 <6>[ 1.183319] loop: module loaded
10564 01:01:27.113960 <6>[ 1.189260] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10565 01:01:27.136898 <4>[ 1.212637] mtk-pmic-keys: Failed to locate of_node [id: -1]
10566 01:01:27.143378 <6>[ 1.219383] megasas: 07.719.03.00-rc1
10567 01:01:27.153329 <6>[ 1.228959] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10568 01:01:27.165206 <6>[ 1.241097] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 01:01:27.181961 <6>[ 1.257562] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 01:01:27.238217 <6>[ 1.307397] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10571 01:01:27.445944 <6>[ 1.521951] Freeing initrd memory: 17380K
10572 01:01:27.456452 <6>[ 1.532244] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10573 01:01:27.467612 <6>[ 1.543367] tun: Universal TUN/TAP device driver, 1.6
10574 01:01:27.470786 <6>[ 1.549436] thunder_xcv, ver 1.0
10575 01:01:27.474199 <6>[ 1.552944] thunder_bgx, ver 1.0
10576 01:01:27.477495 <6>[ 1.556440] nicpf, ver 1.0
10577 01:01:27.488279 <6>[ 1.560459] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10578 01:01:27.491589 <6>[ 1.567935] hns3: Copyright (c) 2017 Huawei Corporation.
10579 01:01:27.494870 <6>[ 1.573523] hclge is initializing
10580 01:01:27.501260 <6>[ 1.577105] e1000: Intel(R) PRO/1000 Network Driver
10581 01:01:27.508168 <6>[ 1.582234] e1000: Copyright (c) 1999-2006 Intel Corporation.
10582 01:01:27.511201 <6>[ 1.588245] e1000e: Intel(R) PRO/1000 Network Driver
10583 01:01:27.518013 <6>[ 1.593461] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10584 01:01:27.524494 <6>[ 1.599645] igb: Intel(R) Gigabit Ethernet Network Driver
10585 01:01:27.531136 <6>[ 1.605296] igb: Copyright (c) 2007-2014 Intel Corporation.
10586 01:01:27.537675 <6>[ 1.611132] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10587 01:01:27.544286 <6>[ 1.617650] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10588 01:01:27.547789 <6>[ 1.624112] sky2: driver version 1.30
10589 01:01:27.554483 <6>[ 1.629107] VFIO - User Level meta-driver version: 0.3
10590 01:01:27.561500 <6>[ 1.637339] usbcore: registered new interface driver usb-storage
10591 01:01:27.567991 <6>[ 1.643791] usbcore: registered new device driver onboard-usb-hub
10592 01:01:27.577170 <6>[ 1.652980] mt6397-rtc mt6359-rtc: registered as rtc0
10593 01:01:27.587281 <6>[ 1.658450] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:01:28 UTC (1705626088)
10594 01:01:27.590303 <6>[ 1.668017] i2c_dev: i2c /dev entries driver
10595 01:01:27.606919 <6>[ 1.679726] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10596 01:01:27.626745 <6>[ 1.702687] cpu cpu0: EM: created perf domain
10597 01:01:27.630281 <6>[ 1.707609] cpu cpu4: EM: created perf domain
10598 01:01:27.637216 <6>[ 1.713223] sdhci: Secure Digital Host Controller Interface driver
10599 01:01:27.643833 <6>[ 1.719657] sdhci: Copyright(c) Pierre Ossman
10600 01:01:27.650735 <6>[ 1.724606] Synopsys Designware Multimedia Card Interface Driver
10601 01:01:27.657345 <6>[ 1.731259] sdhci-pltfm: SDHCI platform and OF driver helper
10602 01:01:27.660718 <6>[ 1.731383] mmc0: CQHCI version 5.10
10603 01:01:27.667139 <6>[ 1.741220] ledtrig-cpu: registered to indicate activity on CPUs
10604 01:01:27.673636 <6>[ 1.748161] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10605 01:01:27.680304 <6>[ 1.755204] usbcore: registered new interface driver usbhid
10606 01:01:27.683582 <6>[ 1.761026] usbhid: USB HID core driver
10607 01:01:27.690170 <6>[ 1.765226] spi_master spi0: will run message pump with realtime priority
10608 01:01:27.732660 <6>[ 1.801788] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10609 01:01:27.750945 <6>[ 1.816847] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10610 01:01:27.754117 <6>[ 1.830469] mmc0: Command Queue Engine enabled
10611 01:01:27.760766 <6>[ 1.835240] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10612 01:01:27.767650 <6>[ 1.842160] cros-ec-spi spi0.0: Chrome EC device registered
10613 01:01:27.770907 <6>[ 1.842454] mmcblk0: mmc0:0001 DA4128 116 GiB
10614 01:01:27.781655 <6>[ 1.857537] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 01:01:27.789054 <6>[ 1.864968] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10616 01:01:27.795605 <6>[ 1.871063] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10617 01:01:27.806025 <6>[ 1.875876] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10618 01:01:27.812448 <6>[ 1.877003] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10619 01:01:27.815878 <6>[ 1.886850] NET: Registered PF_PACKET protocol family
10620 01:01:27.822185 <6>[ 1.897503] 9pnet: Installing 9P2000 support
10621 01:01:27.825650 <5>[ 1.902071] Key type dns_resolver registered
10622 01:01:27.828931 <6>[ 1.907030] registered taskstats version 1
10623 01:01:27.835856 <5>[ 1.911422] Loading compiled-in X.509 certificates
10624 01:01:27.866065 <4>[ 1.935119] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 01:01:27.876075 <4>[ 1.945997] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 01:01:27.882256 <3>[ 1.956583] debugfs: File 'uA_load' in directory '/' already present!
10627 01:01:27.889136 <3>[ 1.963297] debugfs: File 'min_uV' in directory '/' already present!
10628 01:01:27.895876 <3>[ 1.969910] debugfs: File 'max_uV' in directory '/' already present!
10629 01:01:27.902406 <3>[ 1.976519] debugfs: File 'constraint_flags' in directory '/' already present!
10630 01:01:27.914247 <3>[ 1.986807] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10631 01:01:27.925119 <6>[ 2.000690] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10632 01:01:27.932408 <6>[ 2.007611] xhci-mtk 11200000.usb: xHCI Host Controller
10633 01:01:27.938970 <6>[ 2.013134] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10634 01:01:27.948868 <6>[ 2.021026] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10635 01:01:27.955911 <6>[ 2.030462] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10636 01:01:27.961997 <6>[ 2.036539] xhci-mtk 11200000.usb: xHCI Host Controller
10637 01:01:27.968857 <6>[ 2.042018] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10638 01:01:27.975763 <6>[ 2.049666] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10639 01:01:27.982231 <6>[ 2.057443] hub 1-0:1.0: USB hub found
10640 01:01:27.985758 <6>[ 2.061469] hub 1-0:1.0: 1 port detected
10641 01:01:27.992485 <6>[ 2.065764] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10642 01:01:27.999564 <6>[ 2.074536] hub 2-0:1.0: USB hub found
10643 01:01:28.002310 <6>[ 2.078560] hub 2-0:1.0: 1 port detected
10644 01:01:28.011300 <6>[ 2.086511] mtk-msdc 11f70000.mmc: Got CD GPIO
10645 01:01:28.023525 <6>[ 2.095434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10646 01:01:28.030039 <6>[ 2.103469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10647 01:01:28.039999 <4>[ 2.111469] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10648 01:01:28.050249 <6>[ 2.120999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10649 01:01:28.056820 <6>[ 2.129102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10650 01:01:28.063477 <6>[ 2.137113] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10651 01:01:28.073597 <6>[ 2.145045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10652 01:01:28.079911 <6>[ 2.152864] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10653 01:01:28.089775 <6>[ 2.160696] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10654 01:01:28.099710 <6>[ 2.171106] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10655 01:01:28.106192 <6>[ 2.179492] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10656 01:01:28.116213 <6>[ 2.187835] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10657 01:01:28.122898 <6>[ 2.196186] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10658 01:01:28.132793 <6>[ 2.204526] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10659 01:01:28.139452 <6>[ 2.212877] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10660 01:01:28.149620 <6>[ 2.221217] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10661 01:01:28.156465 <6>[ 2.229570] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10662 01:01:28.165866 <6>[ 2.237911] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10663 01:01:28.172430 <6>[ 2.246259] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10664 01:01:28.182724 <6>[ 2.254603] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10665 01:01:28.192454 <6>[ 2.262944] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10666 01:01:28.199202 <6>[ 2.271283] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10667 01:01:28.209390 <6>[ 2.279621] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10668 01:01:28.215595 <6>[ 2.287960] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10669 01:01:28.222127 <6>[ 2.296717] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10670 01:01:28.228977 <6>[ 2.303874] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10671 01:01:28.235602 <6>[ 2.310635] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10672 01:01:28.242287 <6>[ 2.317391] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10673 01:01:28.252262 <6>[ 2.324347] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10674 01:01:28.258799 <6>[ 2.331182] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10675 01:01:28.269156 <6>[ 2.340314] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10676 01:01:28.278937 <6>[ 2.349434] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10677 01:01:28.288982 <6>[ 2.358750] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10678 01:01:28.298432 <6>[ 2.368313] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10679 01:01:28.305455 <6>[ 2.377780] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10680 01:01:28.315267 <6>[ 2.386899] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10681 01:01:28.324826 <6>[ 2.396365] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10682 01:01:28.335124 <6>[ 2.405483] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10683 01:01:28.345173 <6>[ 2.414777] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10684 01:01:28.354771 <6>[ 2.424936] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10685 01:01:28.364529 <6>[ 2.436426] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10686 01:01:28.371264 <6>[ 2.446398] Trying to probe devices needed for running init ...
10687 01:01:28.421826 <6>[ 2.494009] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10688 01:01:28.576915 <6>[ 2.651804] hub 1-1:1.0: USB hub found
10689 01:01:28.579924 <6>[ 2.656325] hub 1-1:1.0: 4 ports detected
10690 01:01:28.590208 <6>[ 2.665516] hub 1-1:1.0: USB hub found
10691 01:01:28.593734 <6>[ 2.669992] hub 1-1:1.0: 4 ports detected
10692 01:01:28.702084 <6>[ 2.774334] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10693 01:01:28.728366 <6>[ 2.803662] hub 2-1:1.0: USB hub found
10694 01:01:28.731560 <6>[ 2.808152] hub 2-1:1.0: 3 ports detected
10695 01:01:28.740968 <6>[ 2.816154] hub 2-1:1.0: USB hub found
10696 01:01:28.744283 <6>[ 2.820625] hub 2-1:1.0: 3 ports detected
10697 01:01:28.917652 <6>[ 2.990009] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10698 01:01:29.050165 <6>[ 3.125612] hub 1-1.4:1.0: USB hub found
10699 01:01:29.053636 <6>[ 3.130258] hub 1-1.4:1.0: 2 ports detected
10700 01:01:29.062371 <6>[ 3.137787] hub 1-1.4:1.0: USB hub found
10701 01:01:29.065770 <6>[ 3.142375] hub 1-1.4:1.0: 2 ports detected
10702 01:01:29.134188 <6>[ 3.206212] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10703 01:01:29.361870 <6>[ 3.434028] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 01:01:29.553762 <6>[ 3.626013] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 01:01:40.654905 <6>[ 14.734944] ALSA device list:
10706 01:01:40.661693 <6>[ 14.738232] No soundcards found.
10707 01:01:40.669270 <6>[ 14.746069] Freeing unused kernel memory: 8448K
10708 01:01:40.672479 <6>[ 14.751066] Run /init as init process
10709 01:01:40.684023 Loading, please wait...
10710 01:01:40.705864 Starting version 247.3-7+deb11u2
10711 01:01:40.899840 <3>[ 14.972699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 01:01:40.905984 <3>[ 14.980996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 01:01:40.916023 <3>[ 14.989111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 01:01:40.926065 <3>[ 14.998465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 01:01:40.932750 <6>[ 15.001277] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10716 01:01:40.938812 <3>[ 15.007883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 01:01:40.948686 <6>[ 15.014235] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10718 01:01:40.958845 <3>[ 15.022276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 01:01:40.965732 <6>[ 15.030974] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10720 01:01:40.972198 <6>[ 15.037208] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10721 01:01:40.978585 <6>[ 15.037247] mc: Linux media interface: v0.10
10722 01:01:40.985267 <3>[ 15.039045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 01:01:40.992172 <6>[ 15.056881] remoteproc remoteproc0: scp is available
10724 01:01:40.998748 <6>[ 15.058558] videodev: Linux video capture interface: v2.00
10725 01:01:41.005149 <3>[ 15.059635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 01:01:41.011500 <6>[ 15.067088] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10727 01:01:41.018450 <6>[ 15.068198] remoteproc remoteproc0: powering up scp
10728 01:01:41.025833 <3>[ 15.073399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 01:01:41.035159 <6>[ 15.078944] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10730 01:01:41.042419 <3>[ 15.089948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 01:01:41.051776 <4>[ 15.091644] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10732 01:01:41.054999 <4>[ 15.091644] Fallback method does not support PEC.
10733 01:01:41.061658 <6>[ 15.094640] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10734 01:01:41.068305 <4>[ 15.096690] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10735 01:01:41.078507 <3>[ 15.099768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 01:01:41.084773 <4>[ 15.100838] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10737 01:01:41.094920 <3>[ 15.108663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 01:01:41.098351 <6>[ 15.109908] Bluetooth: Core ver 2.22
10739 01:01:41.104663 <6>[ 15.110445] NET: Registered PF_BLUETOOTH protocol family
10740 01:01:41.111432 <6>[ 15.110448] Bluetooth: HCI device and connection manager initialized
10741 01:01:41.114774 <6>[ 15.110470] Bluetooth: HCI socket layer initialized
10742 01:01:41.121850 <6>[ 15.110476] Bluetooth: L2CAP socket layer initialized
10743 01:01:41.125395 <6>[ 15.110491] Bluetooth: SCO socket layer initialized
10744 01:01:41.132108 <3>[ 15.116347] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 01:01:41.141841 <3>[ 15.116563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 01:01:41.148930 <6>[ 15.129455] usbcore: registered new device driver r8152-cfgselector
10747 01:01:41.155222 <3>[ 15.138161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 01:01:41.165322 <3>[ 15.138165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 01:01:41.172068 <3>[ 15.138169] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 01:01:41.181587 <3>[ 15.138172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 01:01:41.188210 <3>[ 15.138201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 01:01:41.194801 <6>[ 15.171037] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10753 01:01:41.205064 <3>[ 15.207872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 01:01:41.211596 <6>[ 15.215195] pci_bus 0000:00: root bus resource [bus 00-ff]
10755 01:01:41.221545 <6>[ 15.226154] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10756 01:01:41.227900 <6>[ 15.229925] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10757 01:01:41.234280 <6>[ 15.237959] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10758 01:01:41.240993 <6>[ 15.237968] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10759 01:01:41.251087 <6>[ 15.238960] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10760 01:01:41.261092 <6>[ 15.241175] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10761 01:01:41.271015 <6>[ 15.246117] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10762 01:01:41.277648 <6>[ 15.254081] remoteproc remoteproc0: remote processor scp is now up
10763 01:01:41.284096 <6>[ 15.258115] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10764 01:01:41.290856 <6>[ 15.262249] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10765 01:01:41.300769 <6>[ 15.279163] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10766 01:01:41.307052 <6>[ 15.279905] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10767 01:01:41.317004 <4>[ 15.285173] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10768 01:01:41.323778 <4>[ 15.285179] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10769 01:01:41.330321 <6>[ 15.286020] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10770 01:01:41.336698 <6>[ 15.287195] usbcore: registered new interface driver btusb
10771 01:01:41.346793 <4>[ 15.287774] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10772 01:01:41.353061 <3>[ 15.287793] Bluetooth: hci0: Failed to load firmware file (-2)
10773 01:01:41.359770 <3>[ 15.287803] Bluetooth: hci0: Failed to set up firmware (-2)
10774 01:01:41.369857 <4>[ 15.287811] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10775 01:01:41.379588 <6>[ 15.293081] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10776 01:01:41.390073 <6>[ 15.293094] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10777 01:01:41.396668 <6>[ 15.293183] usbcore: registered new interface driver uvcvideo
10778 01:01:41.402959 <6>[ 15.301800] pci 0000:00:00.0: supports D1 D2
10779 01:01:41.409461 <6>[ 15.318042] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10780 01:01:41.415930 <6>[ 15.324437] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10781 01:01:41.426154 <6>[ 15.498068] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10782 01:01:41.432859 <6>[ 15.506482] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10783 01:01:41.439076 <6>[ 15.512766] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10784 01:01:41.442453 <6>[ 15.517877] r8152 2-1.3:1.0 eth0: v1.12.13
10785 01:01:41.449057 <6>[ 15.520251] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10786 01:01:41.455559 <6>[ 15.524689] usbcore: registered new interface driver r8152
10787 01:01:41.462287 <6>[ 15.532063] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10788 01:01:41.468849 <6>[ 15.545392] pci 0000:01:00.0: supports D1 D2
10789 01:01:41.475543 <6>[ 15.549911] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10790 01:01:41.482032 <6>[ 15.557223] usbcore: registered new interface driver cdc_ether
10791 01:01:41.489036 <6>[ 15.564291] usbcore: registered new interface driver r8153_ecm
10792 01:01:41.495811 <6>[ 15.565901] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10793 01:01:41.502421 <6>[ 15.577269] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10794 01:01:41.512240 <6>[ 15.585348] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10795 01:01:41.518615 <6>[ 15.592223] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10796 01:01:41.525346 <6>[ 15.593346] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10797 01:01:41.535224 <6>[ 15.607425] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10798 01:01:41.542337 <6>[ 15.615425] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10799 01:01:41.545292 <6>[ 15.623425] pci 0000:00:00.0: PCI bridge to [bus 01]
10800 01:01:41.555235 <6>[ 15.628642] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10801 01:01:41.562004 <6>[ 15.636779] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10802 01:01:41.568399 <6>[ 15.643664] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10803 01:01:41.575152 <6>[ 15.650568] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10804 01:01:41.602443 <5>[ 15.676106] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10805 01:01:41.620115 <5>[ 15.693684] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10806 01:01:41.627018 <5>[ 15.701571] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10807 01:01:41.636654 <4>[ 15.710033] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10808 01:01:41.642977 <6>[ 15.718920] cfg80211: failed to load regulatory.db
10809 01:01:41.686761 <6>[ 15.760052] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10810 01:01:41.693129 <6>[ 15.767566] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10811 01:01:41.717639 <6>[ 15.794336] mt7921e 0000:01:00.0: ASIC revision: 79610010
10812 01:01:41.820350 <6>[ 15.893967] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10813 01:01:41.823601 <6>[ 15.893967]
10814 01:01:41.838472 Begin: Loading essential drivers ... done.
10815 01:01:41.841343 Begin: Running /scripts/init-premount ... done.
10816 01:01:41.848426 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10817 01:01:41.858114 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10818 01:01:41.861786 Device /sys/class/net/enx0024323078ff found
10819 01:01:41.862308 done.
10820 01:01:41.928501 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10821 01:01:42.088067 <6>[ 16.161360] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10822 01:01:42.937579 <6>[ 17.014228] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10823 01:01:42.959457 <6>[ 17.036314] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10824 01:01:43.081666 IP-Config: no response after 2 secs - giving up
10825 01:01:43.113004 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10826 01:01:43.843852 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10827 01:01:43.847382 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10828 01:01:43.853984 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10829 01:01:43.860716 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10830 01:01:43.867095 host : mt8192-asurada-spherion-r0-cbg-8
10831 01:01:43.873705 domain : lava-rack
10832 01:01:43.880371 rootserver: 192.168.201.1 rootpath:
10833 01:01:43.880884 filename :
10834 01:01:43.992811 done.
10835 01:01:44.000714 Begin: Running /scripts/nfs-bottom ... done.
10836 01:01:44.018637 Begin: Running /scripts/init-bottom ... done.
10837 01:01:45.256613 <6>[ 19.334045] NET: Registered PF_INET6 protocol family
10838 01:01:45.264136 <6>[ 19.341922] Segment Routing with IPv6
10839 01:01:45.267707 <6>[ 19.345881] In-situ OAM (IOAM) with IPv6
10840 01:01:45.413423 <30>[ 19.471109] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10841 01:01:45.420060 <30>[ 19.495500] systemd[1]: Detected architecture arm64.
10842 01:01:45.440912
10843 01:01:45.444552 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10844 01:01:45.445074
10845 01:01:45.463563 <30>[ 19.540879] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10846 01:01:46.485797 <30>[ 20.560295] systemd[1]: Queued start job for default target Graphical Interface.
10847 01:01:46.522962 <30>[ 20.600309] systemd[1]: Created slice system-getty.slice.
10848 01:01:46.529550 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10849 01:01:46.546114 <30>[ 20.623349] systemd[1]: Created slice system-modprobe.slice.
10850 01:01:46.552641 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10851 01:01:46.570930 <30>[ 20.648121] systemd[1]: Created slice system-serial\x2dgetty.slice.
10852 01:01:46.581081 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10853 01:01:46.593611 <30>[ 20.671068] systemd[1]: Created slice User and Session Slice.
10854 01:01:46.600466 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10855 01:01:46.621090 <30>[ 20.694845] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10856 01:01:46.630918 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10857 01:01:46.648658 <30>[ 20.722776] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10858 01:01:46.655015 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10859 01:01:46.679128 <30>[ 20.750157] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10860 01:01:46.685949 <30>[ 20.762299] systemd[1]: Reached target Local Encrypted Volumes.
10861 01:01:46.692386 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10862 01:01:46.709641 <30>[ 20.786584] systemd[1]: Reached target Paths.
10863 01:01:46.712483 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10864 01:01:46.728444 <30>[ 20.805996] systemd[1]: Reached target Remote File Systems.
10865 01:01:46.735556 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10866 01:01:46.752980 <30>[ 20.830360] systemd[1]: Reached target Slices.
10867 01:01:46.759288 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10868 01:01:46.772574 <30>[ 20.850002] systemd[1]: Reached target Swap.
10869 01:01:46.776285 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10870 01:01:46.796251 <30>[ 20.870526] systemd[1]: Listening on initctl Compatibility Named Pipe.
10871 01:01:46.802943 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10872 01:01:46.809526 <30>[ 20.886882] systemd[1]: Listening on Journal Audit Socket.
10873 01:01:46.816289 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10874 01:01:46.834330 <30>[ 20.911672] systemd[1]: Listening on Journal Socket (/dev/log).
10875 01:01:46.841096 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10876 01:01:46.857193 <30>[ 20.934555] systemd[1]: Listening on Journal Socket.
10877 01:01:46.863669 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10878 01:01:46.881356 <30>[ 20.955747] systemd[1]: Listening on Network Service Netlink Socket.
10879 01:01:46.888073 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10880 01:01:46.904730 <30>[ 20.981913] systemd[1]: Listening on udev Control Socket.
10881 01:01:46.911369 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10882 01:01:46.925086 <30>[ 21.002437] systemd[1]: Listening on udev Kernel Socket.
10883 01:01:46.931551 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10884 01:01:46.981094 <30>[ 21.058473] systemd[1]: Mounting Huge Pages File System...
10885 01:01:46.987256 Mounting [0;1;39mHuge Pages File System[0m...
10886 01:01:47.003131 <30>[ 21.080397] systemd[1]: Mounting POSIX Message Queue File System...
10887 01:01:47.009507 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10888 01:01:47.027790 <30>[ 21.105330] systemd[1]: Mounting Kernel Debug File System...
10889 01:01:47.034332 Mounting [0;1;39mKernel Debug File System[0m...
10890 01:01:47.052065 <30>[ 21.126445] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10891 01:01:47.108359 <30>[ 21.182535] systemd[1]: Starting Create list of static device nodes for the current kernel...
10892 01:01:47.114957 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10893 01:01:47.141434 <30>[ 21.219104] systemd[1]: Starting Load Kernel Module configfs...
10894 01:01:47.148418 Starting [0;1;39mLoad Kernel Module configfs[0m...
10895 01:01:47.173694 <30>[ 21.251264] systemd[1]: Starting Load Kernel Module drm...
10896 01:01:47.180052 Starting [0;1;39mLoad Kernel Module drm[0m...
10897 01:01:47.201979 <30>[ 21.279550] systemd[1]: Starting Load Kernel Module fuse...
10898 01:01:47.208428 Starting [0;1;39mLoad Kernel Module fuse[0m...
10899 01:01:47.233250 <30>[ 21.307417] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10900 01:01:47.250861 <30>[ 21.328358] systemd[1]: Starting Journal Service...
10901 01:01:47.257355 Starting [0;1;39mJournal Service[0m...
10902 01:01:47.264536 <6>[ 21.342273] fuse: init (API version 7.37)
10903 01:01:47.284862 <30>[ 21.362391] systemd[1]: Starting Load Kernel Modules...
10904 01:01:47.291568 Starting [0;1;39mLoad Kernel Modules[0m...
10905 01:01:47.315925 <30>[ 21.390324] systemd[1]: Starting Remount Root and Kernel File Systems...
10906 01:01:47.322482 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10907 01:01:47.344018 <30>[ 21.421599] systemd[1]: Starting Coldplug All udev Devices...
10908 01:01:47.350717 Starting [0;1;39mColdplug All udev Devices[0m...
10909 01:01:47.375989 <30>[ 21.453445] systemd[1]: Mounted Huge Pages File System.
10910 01:01:47.382502 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10911 01:01:47.397372 <30>[ 21.475112] systemd[1]: Mounted POSIX Message Queue File System.
10912 01:01:47.403817 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10913 01:01:47.420516 <30>[ 21.498320] systemd[1]: Mounted Kernel Debug File System.
10914 01:01:47.427386 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10915 01:01:47.450077 <30>[ 21.524432] systemd[1]: Finished Create list of static device nodes for the current kernel.
10916 01:01:47.459806 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10917 01:01:47.475432 <3>[ 21.549766] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 01:01:47.482058 <30>[ 21.559731] systemd[1]: modprobe@configfs.service: Succeeded.
10919 01:01:47.489330 <30>[ 21.566821] systemd[1]: Finished Load Kernel Module configfs.
10920 01:01:47.496322 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10921 01:01:47.506426 <3>[ 21.579295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 01:01:47.513324 <30>[ 21.590769] systemd[1]: modprobe@drm.service: Succeeded.
10923 01:01:47.519860 <30>[ 21.597338] systemd[1]: Finished Load Kernel Module drm.
10924 01:01:47.526298 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10925 01:01:47.545439 <30>[ 21.622887] systemd[1]: modprobe@fuse.service: Succeeded.
10926 01:01:47.551886 <30>[ 21.629326] systemd[1]: Finished Load Kernel Module fuse.
10927 01:01:47.565402 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0<3>[ 21.640433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 01:01:47.568627 m.
10929 01:01:47.575786 <30>[ 21.651783] systemd[1]: Finished Load Kernel Modules.
10930 01:01:47.578997 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10931 01:01:47.596781 <30>[ 21.670950] systemd[1]: Finished Remount Root and Kernel File Systems.
10932 01:01:47.603368 <3>[ 21.671032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 01:01:47.613132 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10934 01:01:47.633674 <3>[ 21.707675] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 01:01:47.653200 <30>[ 21.730646] systemd[1]: Mounting FUSE Control File System...
10936 01:01:47.666675 Mounting [0;1;39mFUSE Control File Sys<3>[ 21.740335] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 01:01:47.667166 tem[0m...
10938 01:01:47.689839 <30>[ 21.766948] systemd[1]: Mounting Kernel Configuration File System...
10939 01:01:47.699647 <3>[ 21.771709] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 01:01:47.705882 Mounting [0;1;39mKernel Configuration File System[0m...
10941 01:01:47.729725 <30>[ 21.804178] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10942 01:01:47.739745 <3>[ 21.804811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 01:01:47.749617 <30>[ 21.813341] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10944 01:01:47.773520 <30>[ 21.850824] systemd[1]: Starting Load/Save Random Seed...
10945 01:01:47.780016 Starting [0;1;39mLoad/Save Random Seed[0m...
10946 01:01:47.790318 <3>[ 21.862763] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 01:01:47.800127 <3>[ 21.873129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10948 01:01:47.806519 <30>[ 21.874374] systemd[1]: Starting Apply Kernel Variables...
10949 01:01:47.809945 Starting [0;1;39mApply Kernel Variables[0m...
10950 01:01:47.860938 <30>[ 21.938673] systemd[1]: Starting Create System Users...
10951 01:01:47.867428 Starting [0;1;39mCreate System Users[0m...
10952 01:01:47.890824 <4>[ 21.958105] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10953 01:01:47.897616 <3>[ 21.973878] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10954 01:01:47.904127 <30>[ 21.976028] systemd[1]: Mounted FUSE Control File System.
10955 01:01:47.910644 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10956 01:01:47.932832 <29>[ 22.006670] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10957 01:01:47.942904 <28>[ 22.016831] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10958 01:01:47.949555 <27>[ 22.025671] systemd[1]: Failed to start Coldplug All udev Devices.
10959 01:01:47.955940 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10960 01:01:47.972244 See 'systemctl status systemd-udev-trigger.service' for details.
10961 01:01:47.992733 <30>[ 22.070460] systemd[1]: Started Journal Service.
10962 01:01:47.999462 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10963 01:01:48.016170 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10964 01:01:48.034024 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10965 01:01:48.049512 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10966 01:01:48.070149 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10967 01:01:48.129008 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10968 01:01:48.146527 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10969 01:01:48.193262 <46>[ 22.267702] systemd-journald[292]: Received client request to flush runtime journal.
10970 01:01:49.305762 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10971 01:01:49.320846 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10972 01:01:49.335972 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10973 01:01:49.380142 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10974 01:01:49.617894 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10975 01:01:49.673447 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10976 01:01:49.786573 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10977 01:01:49.857436 Starting [0;1;39mNetwork Service[0m...
10978 01:01:50.140312 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10979 01:01:50.167624 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10980 01:01:50.220218 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10981 01:01:50.520860 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10982 01:01:50.539548 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10983 01:01:50.577174 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10984 01:01:50.598298 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10985 01:01:50.617892 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10986 01:01:50.637234 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10987 01:01:50.656629 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10988 01:01:50.736808 Starting [0;1;39mNetwork Name Resolution[0m...
10989 01:01:50.775304 Starting [0;1;39mNetwork Time Synchronization[0m...
10990 01:01:50.796070 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10991 01:01:50.850883 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10992 01:01:50.998883 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10993 01:01:51.016658 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10994 01:01:51.035460 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10995 01:01:51.048053 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10996 01:01:51.063934 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10997 01:01:51.097605 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10998 01:01:51.169672 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10999 01:01:51.216962 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11000 01:01:51.263775 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11001 01:01:51.275935 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11002 01:01:51.304829 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11003 01:01:51.316303 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11004 01:01:51.331990 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11005 01:01:51.376591 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11006 01:01:52.067718 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11007 01:01:52.504321 Starting [0;1;39mUser Login Management[0m...
11008 01:01:52.541731 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11009 01:01:52.560091 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11010 01:01:52.578793 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11011 01:01:52.624115 Starting [0;1;39mPermit User Sessions[0m...
11012 01:01:52.693548 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11013 01:01:52.709598 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11014 01:01:52.768549 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11015 01:01:52.790581 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11016 01:01:52.812110 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11017 01:01:52.830439 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11018 01:01:52.850288 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11019 01:01:52.868585 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11020 01:01:52.924959 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11021 01:01:52.978198 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11022 01:01:53.093390
11023 01:01:53.093949
11024 01:01:53.096703 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11025 01:01:53.097128
11026 01:01:53.100106 debian-bullseye-arm64 login: root (automatic login)
11027 01:01:53.100694
11028 01:01:53.101049
11029 01:01:53.503239 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
11030 01:01:53.503742
11031 01:01:53.510016 The programs included with the Debian GNU/Linux system are free software;
11032 01:01:53.516609 the exact distribution terms for each program are described in the
11033 01:01:53.519870 individual files in /usr/share/doc/*/copyright.
11034 01:01:53.520294
11035 01:01:53.526511 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11036 01:01:53.529855 permitted by applicable law.
11037 01:01:54.624647 Matched prompt #10: / #
11039 01:01:54.625854 Setting prompt string to ['/ #']
11040 01:01:54.626310 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11042 01:01:54.627298 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11043 01:01:54.627743 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
11044 01:01:54.628098 Setting prompt string to ['/ #']
11045 01:01:54.628410 Forcing a shell prompt, looking for ['/ #']
11047 01:01:54.678984 / #
11048 01:01:54.679316 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11049 01:01:54.679512 Waiting using forced prompt support (timeout 00:02:30)
11050 01:01:54.684647
11051 01:01:54.685266 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11052 01:01:54.685582 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11054 01:01:54.786614 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8'
11055 01:01:54.793097 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571114/extract-nfsrootfs-v09cbub8'
11057 01:01:54.894971 / # export NFS_SERVER_IP='192.168.201.1'
11058 01:01:54.901291 export NFS_SERVER_IP='192.168.201.1'
11059 01:01:54.902397 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11060 01:01:54.903064 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11061 01:01:54.903605 end: 2 depthcharge-action (duration 00:01:50) [common]
11062 01:01:54.904125 start: 3 lava-test-retry (timeout 00:07:28) [common]
11063 01:01:54.904627 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11064 01:01:54.905078 Using namespace: common
11066 01:01:55.006475 / # #
11067 01:01:55.007317 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11068 01:01:55.013213 #
11069 01:01:55.014237 Using /lava-12571114
11071 01:01:55.115539 / # export SHELL=/bin/bash
11072 01:01:55.122159 export SHELL=/bin/bash
11074 01:01:55.224016 / # . /lava-12571114/environment
11075 01:01:55.230787 . /lava-12571114/environment
11077 01:01:55.339933 / # /lava-12571114/bin/lava-test-runner /lava-12571114/0
11078 01:01:55.340582 Test shell timeout: 10s (minimum of the action and connection timeout)
11079 01:01:55.346455 /lava-12571114/bin/lava-test-runner /lava-12571114/0
11080 01:01:55.730629 + export TESTRUN_ID=0_timesync-off
11081 01:01:55.733953 + TESTRUN_ID=0_timesync-off
11082 01:01:55.737029 + cd /lava-12571114/0/tests/0_timesync-off
11083 01:01:55.740419 ++ cat uuid
11084 01:01:55.752822 + UUID=12571114_1.6.2.3.1
11085 01:01:55.753248 + set +x
11086 01:01:55.759381 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12571114_1.6.2.3.1>
11087 01:01:55.760071 Received signal: <STARTRUN> 0_timesync-off 12571114_1.6.2.3.1
11088 01:01:55.760461 Starting test lava.0_timesync-off (12571114_1.6.2.3.1)
11089 01:01:55.760891 Skipping test definition patterns.
11090 01:01:55.762639 + systemctl stop systemd-timesyncd
11091 01:01:55.831530 + set +x
11092 01:01:55.834994 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12571114_1.6.2.3.1>
11093 01:01:55.835672 Received signal: <ENDRUN> 0_timesync-off 12571114_1.6.2.3.1
11094 01:01:55.836083 Ending use of test pattern.
11095 01:01:55.836402 Ending test lava.0_timesync-off (12571114_1.6.2.3.1), duration 0.08
11097 01:01:55.940373 + export TESTRUN_ID=1_kselftest-arm64
11098 01:01:55.940887 + TESTRUN_ID=1_kselftest-arm64
11099 01:01:55.946805 + cd /lava-12571114/0/tests/1_kselftest-arm64
11100 01:01:55.947235 ++ cat uuid
11101 01:01:55.957599 + UUID=12571114_1.6.2.3.5
11102 01:01:55.958028 + set +x
11103 01:01:55.964337 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12571114_1.6.2.3.5>
11104 01:01:55.965028 Received signal: <STARTRUN> 1_kselftest-arm64 12571114_1.6.2.3.5
11105 01:01:55.965386 Starting test lava.1_kselftest-arm64 (12571114_1.6.2.3.5)
11106 01:01:55.965832 Skipping test definition patterns.
11107 01:01:55.967606 + cd ./automated/linux/kselftest/
11108 01:01:55.993634 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11109 01:01:56.055958 INFO: install_deps skipped
11110 01:01:56.187302 --2024-01-19 01:01:56-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11111 01:01:56.194072 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11112 01:01:56.322034 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11113 01:01:56.451349 HTTP request sent, awaiting response... 200 OK
11114 01:01:56.454981 Length: 2966476 (2.8M) [application/octet-stream]
11115 01:01:56.457885 Saving to: 'kselftest.tar.xz'
11116 01:01:56.457980
11117 01:01:56.458060
11118 01:01:56.711460 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11119 01:01:56.971440 kselftest.tar.xz 1%[ ] 47.81K 185KB/s
11120 01:01:57.230493 kselftest.tar.xz 7%[> ] 217.50K 420KB/s
11121 01:01:57.552163 kselftest.tar.xz 30%[=====> ] 896.25K 1.13MB/s
11122 01:01:57.566950 kselftest.tar.xz 47%[========> ] 1.35M 1.23MB/s
11123 01:01:57.573218 kselftest.tar.xz 100%[===================>] 2.83M 2.54MB/s in 1.1s
11124 01:01:57.573707
11125 01:01:57.831182 2024-01-19 01:01:57 (2.54 MB/s) - 'kselftest.tar.xz' saved [2966476/2966476]
11126 01:01:57.831332
11127 01:02:04.885686 skiplist:
11128 01:02:04.888917 ========================================
11129 01:02:04.892170 ========================================
11130 01:02:04.944777 arm64:tags_test
11131 01:02:04.947982 arm64:run_tags_test.sh
11132 01:02:04.948071 arm64:fake_sigreturn_bad_magic
11133 01:02:04.951737 arm64:fake_sigreturn_bad_size
11134 01:02:04.954801 arm64:fake_sigreturn_bad_size_for_magic0
11135 01:02:04.958220 arm64:fake_sigreturn_duplicated_fpsimd
11136 01:02:04.961264 arm64:fake_sigreturn_misaligned_sp
11137 01:02:04.964505 arm64:fake_sigreturn_missing_fpsimd
11138 01:02:04.967953 arm64:fake_sigreturn_sme_change_vl
11139 01:02:04.971439 arm64:fake_sigreturn_sve_change_vl
11140 01:02:04.974619 arm64:mangle_pstate_invalid_compat_toggle
11141 01:02:04.977936 arm64:mangle_pstate_invalid_daif_bits
11142 01:02:04.981160 arm64:mangle_pstate_invalid_mode_el1h
11143 01:02:04.984433 arm64:mangle_pstate_invalid_mode_el1t
11144 01:02:04.987981 arm64:mangle_pstate_invalid_mode_el2h
11145 01:02:04.991356 arm64:mangle_pstate_invalid_mode_el2t
11146 01:02:04.994454 arm64:mangle_pstate_invalid_mode_el3h
11147 01:02:04.997778 arm64:mangle_pstate_invalid_mode_el3t
11148 01:02:05.001229 arm64:sme_trap_no_sm
11149 01:02:05.004586 arm64:sme_trap_non_streaming
11150 01:02:05.004828 arm64:sme_trap_za
11151 01:02:05.007923 arm64:sme_vl
11152 01:02:05.008226 arm64:ssve_regs
11153 01:02:05.011147 arm64:sve_regs
11154 01:02:05.011448 arm64:sve_vl
11155 01:02:05.011690 arm64:za_no_regs
11156 01:02:05.014589 arm64:za_regs
11157 01:02:05.014979 arm64:pac
11158 01:02:05.017902 arm64:fp-stress
11159 01:02:05.018330 arm64:sve-ptrace
11160 01:02:05.021065 arm64:sve-probe-vls
11161 01:02:05.021536 arm64:vec-syscfg
11162 01:02:05.021918 arm64:za-fork
11163 01:02:05.024536 arm64:za-ptrace
11164 01:02:05.027725 arm64:check_buffer_fill
11165 01:02:05.028149 arm64:check_child_memory
11166 01:02:05.031324 arm64:check_gcr_el1_cswitch
11167 01:02:05.034327 arm64:check_ksm_options
11168 01:02:05.034752 arm64:check_mmap_options
11169 01:02:05.037605 arm64:check_prctl
11170 01:02:05.040940 arm64:check_tags_inclusion
11171 01:02:05.041365 arm64:check_user_mem
11172 01:02:05.044074 arm64:btitest
11173 01:02:05.044502 arm64:nobtitest
11174 01:02:05.044838 arm64:hwcap
11175 01:02:05.047527 arm64:ptrace
11176 01:02:05.047950 arm64:syscall-abi
11177 01:02:05.050790 arm64:tpidr2
11178 01:02:05.054038 ============== Tests to run ===============
11179 01:02:05.054469 arm64:tags_test
11180 01:02:05.057456 arm64:run_tags_test.sh
11181 01:02:05.060623 arm64:fake_sigreturn_bad_magic
11182 01:02:05.063934 arm64:fake_sigreturn_bad_size
11183 01:02:05.067449 arm64:fake_sigreturn_bad_size_for_magic0
11184 01:02:05.070673 arm64:fake_sigreturn_duplicated_fpsimd
11185 01:02:05.073958 arm64:fake_sigreturn_misaligned_sp
11186 01:02:05.077243 arm64:fake_sigreturn_missing_fpsimd
11187 01:02:05.080624 arm64:fake_sigreturn_sme_change_vl
11188 01:02:05.081048 arm64:fake_sigreturn_sve_change_vl
11189 01:02:05.087149 arm64:mangle_pstate_invalid_compat_toggle
11190 01:02:05.090940 arm64:mangle_pstate_invalid_daif_bits
11191 01:02:05.093617 arm64:mangle_pstate_invalid_mode_el1h
11192 01:02:05.097026 arm64:mangle_pstate_invalid_mode_el1t
11193 01:02:05.100208 arm64:mangle_pstate_invalid_mode_el2h
11194 01:02:05.103731 arm64:mangle_pstate_invalid_mode_el2t
11195 01:02:05.106888 arm64:mangle_pstate_invalid_mode_el3h
11196 01:02:05.110357 arm64:mangle_pstate_invalid_mode_el3t
11197 01:02:05.110785 arm64:sme_trap_no_sm
11198 01:02:05.113550 arm64:sme_trap_non_streaming
11199 01:02:05.116883 arm64:sme_trap_za
11200 01:02:05.117308 arm64:sme_vl
11201 01:02:05.117725 arm64:ssve_regs
11202 01:02:05.120162 arm64:sve_regs
11203 01:02:05.120588 arm64:sve_vl
11204 01:02:05.123405 arm64:za_no_regs
11205 01:02:05.123831 arm64:za_regs
11206 01:02:05.124169 arm64:pac
11207 01:02:05.126681 arm64:fp-stress
11208 01:02:05.127108 arm64:sve-ptrace
11209 01:02:05.129907 arm64:sve-probe-vls
11210 01:02:05.130335 arm64:vec-syscfg
11211 01:02:05.133197 arm64:za-fork
11212 01:02:05.133837 arm64:za-ptrace
11213 01:02:05.136624 arm64:check_buffer_fill
11214 01:02:05.139868 arm64:check_child_memory
11215 01:02:05.140293 arm64:check_gcr_el1_cswitch
11216 01:02:05.143162 arm64:check_ksm_options
11217 01:02:05.146508 arm64:check_mmap_options
11218 01:02:05.146932 arm64:check_prctl
11219 01:02:05.149827 arm64:check_tags_inclusion
11220 01:02:05.150252 arm64:check_user_mem
11221 01:02:05.153074 arm64:btitest
11222 01:02:05.153547 arm64:nobtitest
11223 01:02:05.156400 arm64:hwcap
11224 01:02:05.156861 arm64:ptrace
11225 01:02:05.159979 arm64:syscall-abi
11226 01:02:05.160403 arm64:tpidr2
11227 01:02:05.163045 ===========End Tests to run ===============
11228 01:02:05.166251 shardfile-arm64 pass
11229 01:02:05.544429 <12>[ 39.624285] kselftest: Running tests in arm64
11230 01:02:05.557419 TAP version 13
11231 01:02:05.573780 1..48
11232 01:02:05.595375 # selftests: arm64: tags_test
11233 01:02:06.065422 ok 1 selftests: arm64: tags_test
11234 01:02:06.084500 # selftests: arm64: run_tags_test.sh
11235 01:02:06.158748 # --------------------
11236 01:02:06.161844 # running tags test
11237 01:02:06.162316 # --------------------
11238 01:02:06.165201 # [PASS]
11239 01:02:06.168401 ok 2 selftests: arm64: run_tags_test.sh
11240 01:02:06.184321 # selftests: arm64: fake_sigreturn_bad_magic
11241 01:02:06.253860 # Registered handlers for all signals.
11242 01:02:06.254008 # Detected MINSTKSIGSZ:4720
11243 01:02:06.256996 # Testcase initialized.
11244 01:02:06.260506 # uc context validated.
11245 01:02:06.263733 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11246 01:02:06.266920 # Handled SIG_COPYCTX
11247 01:02:06.267003 # Available space:3568
11248 01:02:06.273468 # Using badly built context - ERR: BAD MAGIC !
11249 01:02:06.280169 # SIG_OK -- SP:0xFFFFE5887F10 si_addr@:0xffffe5887f10 si_code:2 token@:0xffffe5886cb0 offset:-4704
11250 01:02:06.283662 # ==>> completed. PASS(1)
11251 01:02:06.290232 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11252 01:02:06.296838 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE5886CB0
11253 01:02:06.303360 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11254 01:02:06.306865 # selftests: arm64: fake_sigreturn_bad_size
11255 01:02:06.344876 # Registered handlers for all signals.
11256 01:02:06.345020 # Detected MINSTKSIGSZ:4720
11257 01:02:06.348248 # Testcase initialized.
11258 01:02:06.351666 # uc context validated.
11259 01:02:06.354937 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11260 01:02:06.358057 # Handled SIG_COPYCTX
11261 01:02:06.358142 # Available space:3568
11262 01:02:06.361421 # uc context validated.
11263 01:02:06.368170 # Using badly built context - ERR: Bad size for esr_context
11264 01:02:06.374443 # SIG_OK -- SP:0xFFFFC58A2A80 si_addr@:0xffffc58a2a80 si_code:2 token@:0xffffc58a1820 offset:-4704
11265 01:02:06.377795 # ==>> completed. PASS(1)
11266 01:02:06.384333 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11267 01:02:06.391143 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC58A1820
11268 01:02:06.394239 ok 4 selftests: arm64: fake_sigreturn_bad_size
11269 01:02:06.400825 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11270 01:02:06.425649 # Registered handlers for all signals.
11271 01:02:06.425760 # Detected MINSTKSIGSZ:4720
11272 01:02:06.428862 # Testcase initialized.
11273 01:02:06.431986 # uc context validated.
11274 01:02:06.435364 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11275 01:02:06.438597 # Handled SIG_COPYCTX
11276 01:02:06.438680 # Available space:3568
11277 01:02:06.445327 # Using badly built context - ERR: Bad size for terminator
11278 01:02:06.455128 # SIG_OK -- SP:0xFFFFFB447850 si_addr@:0xfffffb447850 si_code:2 token@:0xfffffb4465f0 offset:-4704
11279 01:02:06.455236 # ==>> completed. PASS(1)
11280 01:02:06.465270 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11281 01:02:06.471706 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFB4465F0
11282 01:02:06.475203 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11283 01:02:06.481470 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11284 01:02:06.514865 # Registered handlers for all signals.
11285 01:02:06.515026 # Detected MINSTKSIGSZ:4720
11286 01:02:06.518009 # Testcase initialized.
11287 01:02:06.520906 # uc context validated.
11288 01:02:06.524570 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11289 01:02:06.527627 # Handled SIG_COPYCTX
11290 01:02:06.527744 # Available space:3568
11291 01:02:06.534473 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11292 01:02:06.544407 # SIG_OK -- SP:0xFFFFC2B68C90 si_addr@:0xffffc2b68c90 si_code:2 token@:0xffffc2b67a30 offset:-4704
11293 01:02:06.544588 # ==>> completed. PASS(1)
11294 01:02:06.554099 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11295 01:02:06.560938 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC2B67A30
11296 01:02:06.564210 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11297 01:02:06.567374 # selftests: arm64: fake_sigreturn_misaligned_sp
11298 01:02:06.599182 # Registered handlers for all signals.
11299 01:02:06.599344 # Detected MINSTKSIGSZ:4720
11300 01:02:06.602671 # Testcase initialized.
11301 01:02:06.605930 # uc context validated.
11302 01:02:06.609407 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11303 01:02:06.612751 # Handled SIG_COPYCTX
11304 01:02:06.619662 # SIG_OK -- SP:0xFFFFC2F00AE3 si_addr@:0xffffc2f00ae3 si_code:2 token@:0xffffc2f00ae3 offset:0
11305 01:02:06.622905 # ==>> completed. PASS(1)
11306 01:02:06.629246 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11307 01:02:06.635955 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC2F00AE3
11308 01:02:06.642415 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11309 01:02:06.645903 # selftests: arm64: fake_sigreturn_missing_fpsimd
11310 01:02:06.695525 # Registered handlers for all signals.
11311 01:02:06.696076 # Detected MINSTKSIGSZ:4720
11312 01:02:06.698960 # Testcase initialized.
11313 01:02:06.702133 # uc context validated.
11314 01:02:06.705458 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11315 01:02:06.708758 # Handled SIG_COPYCTX
11316 01:02:06.711903 # Mangling template header. Spare space:4096
11317 01:02:06.715145 # Using badly built context - ERR: Missing FPSIMD
11318 01:02:06.725137 # SIG_OK -- SP:0xFFFFE4AEDFA0 si_addr@:0xffffe4aedfa0 si_code:2 token@:0xffffe4aecd40 offset:-4704
11319 01:02:06.728354 # ==>> completed. PASS(1)
11320 01:02:06.735115 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11321 01:02:06.741516 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE4AECD40
11322 01:02:06.744950 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11323 01:02:06.751361 # selftests: arm64: fake_sigreturn_sme_change_vl
11324 01:02:06.793626 # Registered handlers for all signals.
11325 01:02:06.794241 # Detected MINSTKSIGSZ:4720
11326 01:02:06.796596 # ==>> completed. SKIP.
11327 01:02:06.803500 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11328 01:02:06.806549 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11329 01:02:06.817780 # selftests: arm64: fake_sigreturn_sve_change_vl
11330 01:02:06.890298 # Registered handlers for all signals.
11331 01:02:06.890566 # Detected MINSTKSIGSZ:4720
11332 01:02:06.893382 # ==>> completed. SKIP.
11333 01:02:06.900428 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11334 01:02:06.903691 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11335 01:02:06.913969 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11336 01:02:06.962828 # Registered handlers for all signals.
11337 01:02:06.963334 # Detected MINSTKSIGSZ:4720
11338 01:02:06.966061 # Testcase initialized.
11339 01:02:06.969320 # uc context validated.
11340 01:02:06.969812 # Handled SIG_TRIG
11341 01:02:06.979233 # SIG_OK -- SP:0xFFFFF2D4B860 si_addr@:0xfffff2d4b860 si_code:2 token@:(nil) offset:-281474755770464
11342 01:02:06.982311 # ==>> completed. PASS(1)
11343 01:02:06.988888 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11344 01:02:06.995480 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11345 01:02:06.998765 # selftests: arm64: mangle_pstate_invalid_daif_bits
11346 01:02:07.058620 # Registered handlers for all signals.
11347 01:02:07.059127 # Detected MINSTKSIGSZ:4720
11348 01:02:07.062176 # Testcase initialized.
11349 01:02:07.065102 # uc context validated.
11350 01:02:07.065570 # Handled SIG_TRIG
11351 01:02:07.075225 # SIG_OK -- SP:0xFFFFC565BBE0 si_addr@:0xffffc565bbe0 si_code:2 token@:(nil) offset:-281473993522144
11352 01:02:07.078226 # ==>> completed. PASS(1)
11353 01:02:07.085085 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11354 01:02:07.088428 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11355 01:02:07.095007 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11356 01:02:07.168743 # Registered handlers for all signals.
11357 01:02:07.169312 # Detected MINSTKSIGSZ:4720
11358 01:02:07.171678 # Testcase initialized.
11359 01:02:07.175010 # uc context validated.
11360 01:02:07.175532 # Handled SIG_TRIG
11361 01:02:07.184744 # SIG_OK -- SP:0xFFFFC10E87E0 si_addr@:0xffffc10e87e0 si_code:2 token@:(nil) offset:-281473920698336
11362 01:02:07.188000 # ==>> completed. PASS(1)
11363 01:02:07.194715 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11364 01:02:07.198015 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11365 01:02:07.204445 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11366 01:02:07.270041 # Registered handlers for all signals.
11367 01:02:07.270623 # Detected MINSTKSIGSZ:4720
11368 01:02:07.273277 # Testcase initialized.
11369 01:02:07.276457 # uc context validated.
11370 01:02:07.276930 # Handled SIG_TRIG
11371 01:02:07.286575 # SIG_OK -- SP:0xFFFFEE0CCBF0 si_addr@:0xffffee0ccbf0 si_code:2 token@:(nil) offset:-281474675559408
11372 01:02:07.289759 # ==>> completed. PASS(1)
11373 01:02:07.296170 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11374 01:02:07.299321 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11375 01:02:07.306040 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11376 01:02:07.359881 # Registered handlers for all signals.
11377 01:02:07.360140 # Detected MINSTKSIGSZ:4720
11378 01:02:07.363548 # Testcase initialized.
11379 01:02:07.366615 # uc context validated.
11380 01:02:07.366870 # Handled SIG_TRIG
11381 01:02:07.376782 # SIG_OK -- SP:0xFFFFCCC7A720 si_addr@:0xffffccc7a720 si_code:2 token@:(nil) offset:-281474117379872
11382 01:02:07.380076 # ==>> completed. PASS(1)
11383 01:02:07.386427 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11384 01:02:07.389708 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11385 01:02:07.396178 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11386 01:02:07.440961 # Registered handlers for all signals.
11387 01:02:07.441698 # Detected MINSTKSIGSZ:4720
11388 01:02:07.444247 # Testcase initialized.
11389 01:02:07.447568 # uc context validated.
11390 01:02:07.448244 # Handled SIG_TRIG
11391 01:02:07.457329 # SIG_OK -- SP:0xFFFFF62F2C40 si_addr@:0xfffff62f2c40 si_code:2 token@:(nil) offset:-281474812030016
11392 01:02:07.460767 # ==>> completed. PASS(1)
11393 01:02:07.467388 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11394 01:02:07.470590 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11395 01:02:07.476958 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11396 01:02:07.525854 # Registered handlers for all signals.
11397 01:02:07.526496 # Detected MINSTKSIGSZ:4720
11398 01:02:07.529293 # Testcase initialized.
11399 01:02:07.532105 # uc context validated.
11400 01:02:07.532570 # Handled SIG_TRIG
11401 01:02:07.542235 # SIG_OK -- SP:0xFFFFEAB5BA10 si_addr@:0xffffeab5ba10 si_code:2 token@:(nil) offset:-281474619521552
11402 01:02:07.545386 # ==>> completed. PASS(1)
11403 01:02:07.551778 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11404 01:02:07.555370 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11405 01:02:07.561874 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11406 01:02:07.626770 # Registered handlers for all signals.
11407 01:02:07.627321 # Detected MINSTKSIGSZ:4720
11408 01:02:07.630444 # Testcase initialized.
11409 01:02:07.633605 # uc context validated.
11410 01:02:07.634029 # Handled SIG_TRIG
11411 01:02:07.643436 # SIG_OK -- SP:0xFFFFDDAF7490 si_addr@:0xffffddaf7490 si_code:2 token@:(nil) offset:-281474401006736
11412 01:02:07.646663 # ==>> completed. PASS(1)
11413 01:02:07.653426 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11414 01:02:07.656556 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11415 01:02:07.659957 # selftests: arm64: sme_trap_no_sm
11416 01:02:07.723045 # Registered handlers for all signals.
11417 01:02:07.723621 # Detected MINSTKSIGSZ:4720
11418 01:02:07.725687 # ==>> completed. SKIP.
11419 01:02:07.735504 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11420 01:02:07.739072 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11421 01:02:07.742189 # selftests: arm64: sme_trap_non_streaming
11422 01:02:07.820692 # Registered handlers for all signals.
11423 01:02:07.821200 # Detected MINSTKSIGSZ:4720
11424 01:02:07.823968 # ==>> completed. SKIP.
11425 01:02:07.833973 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11426 01:02:07.840244 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11427 01:02:07.848221 # selftests: arm64: sme_trap_za
11428 01:02:07.911285 # Registered handlers for all signals.
11429 01:02:07.911823 # Detected MINSTKSIGSZ:4720
11430 01:02:07.914313 # Testcase initialized.
11431 01:02:07.924214 # SIG_OK -- SP:0xFFFFD2E0CFD0 si_addr@:0xaaaabaf12510 si_code:1 token@:(nil) offset:-187650257528080
11432 01:02:07.924678 # ==>> completed. PASS(1)
11433 01:02:07.934321 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11434 01:02:07.937420 ok 21 selftests: arm64: sme_trap_za
11435 01:02:07.937886 # selftests: arm64: sme_vl
11436 01:02:08.003929 # Registered handlers for all signals.
11437 01:02:08.004437 # Detected MINSTKSIGSZ:4720
11438 01:02:08.006806 # ==>> completed. SKIP.
11439 01:02:08.010061 # # SME VL :: Check that we get the right SME VL reported
11440 01:02:08.016710 ok 22 selftests: arm64: sme_vl # SKIP
11441 01:02:08.021554 # selftests: arm64: ssve_regs
11442 01:02:08.097701 # Registered handlers for all signals.
11443 01:02:08.098307 # Detected MINSTKSIGSZ:4720
11444 01:02:08.101063 # ==>> completed. SKIP.
11445 01:02:08.107600 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11446 01:02:08.113965 ok 23 selftests: arm64: ssve_regs # SKIP
11447 01:02:08.119303 # selftests: arm64: sve_regs
11448 01:02:08.197513 # Registered handlers for all signals.
11449 01:02:08.198025 # Detected MINSTKSIGSZ:4720
11450 01:02:08.200873 # ==>> completed. SKIP.
11451 01:02:08.207327 # # SVE registers :: Check that we get the right SVE registers reported
11452 01:02:08.210438 ok 24 selftests: arm64: sve_regs # SKIP
11453 01:02:08.217599 # selftests: arm64: sve_vl
11454 01:02:08.297127 # Registered handlers for all signals.
11455 01:02:08.297706 # Detected MINSTKSIGSZ:4720
11456 01:02:08.300264 # ==>> completed. SKIP.
11457 01:02:08.306878 # # SVE VL :: Check that we get the right SVE VL reported
11458 01:02:08.310158 ok 25 selftests: arm64: sve_vl # SKIP
11459 01:02:08.317930 # selftests: arm64: za_no_regs
11460 01:02:08.393148 # Registered handlers for all signals.
11461 01:02:08.393739 # Detected MINSTKSIGSZ:4720
11462 01:02:08.396519 # ==>> completed. SKIP.
11463 01:02:08.403056 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11464 01:02:08.406214 ok 26 selftests: arm64: za_no_regs # SKIP
11465 01:02:08.414380 # selftests: arm64: za_regs
11466 01:02:08.491716 # Registered handlers for all signals.
11467 01:02:08.492228 # Detected MINSTKSIGSZ:4720
11468 01:02:08.495082 # ==>> completed. SKIP.
11469 01:02:08.501559 # # ZA register :: Check that we get the right ZA registers reported
11470 01:02:08.504568 ok 27 selftests: arm64: za_regs # SKIP
11471 01:02:08.512437 # selftests: arm64: pac
11472 01:02:08.575602 # TAP version 13
11473 01:02:08.576127 # 1..7
11474 01:02:08.578818 # # Starting 7 tests from 1 test cases.
11475 01:02:08.581981 # # RUN global.corrupt_pac ...
11476 01:02:08.585096 # # SKIP PAUTH not enabled
11477 01:02:08.588446 # # OK global.corrupt_pac
11478 01:02:08.591593 # ok 1 # SKIP PAUTH not enabled
11479 01:02:08.598305 # # RUN global.pac_instructions_not_nop ...
11480 01:02:08.601756 # # SKIP PAUTH not enabled
11481 01:02:08.604938 # # OK global.pac_instructions_not_nop
11482 01:02:08.608312 # ok 2 # SKIP PAUTH not enabled
11483 01:02:08.614630 # # RUN global.pac_instructions_not_nop_generic ...
11484 01:02:08.617724 # # SKIP Generic PAUTH not enabled
11485 01:02:08.620813 # # OK global.pac_instructions_not_nop_generic
11486 01:02:08.627509 # ok 3 # SKIP Generic PAUTH not enabled
11487 01:02:08.630962 # # RUN global.single_thread_different_keys ...
11488 01:02:08.634650 # # SKIP PAUTH not enabled
11489 01:02:08.641030 # # OK global.single_thread_different_keys
11490 01:02:08.641114 # ok 4 # SKIP PAUTH not enabled
11491 01:02:08.647232 # # RUN global.exec_changed_keys ...
11492 01:02:08.650953 # # SKIP PAUTH not enabled
11493 01:02:08.653908 # # OK global.exec_changed_keys
11494 01:02:08.657646 # ok 5 # SKIP PAUTH not enabled
11495 01:02:08.660886 # # RUN global.context_switch_keep_keys ...
11496 01:02:08.664718 # # SKIP PAUTH not enabled
11497 01:02:08.671356 # # OK global.context_switch_keep_keys
11498 01:02:08.671889 # ok 6 # SKIP PAUTH not enabled
11499 01:02:08.677411 # # RUN global.context_switch_keep_keys_generic ...
11500 01:02:08.681244 # # SKIP Generic PAUTH not enabled
11501 01:02:08.687239 # # OK global.context_switch_keep_keys_generic
11502 01:02:08.690879 # ok 7 # SKIP Generic PAUTH not enabled
11503 01:02:08.694348 # # PASSED: 7 / 7 tests passed.
11504 01:02:08.697424 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11505 01:02:08.700925 ok 28 selftests: arm64: pac
11506 01:02:08.703990 # selftests: arm64: fp-stress
11507 01:02:12.074018 <6>[ 46.157793] vpu: disabling
11508 01:02:12.077136 <6>[ 46.160841] vproc2: disabling
11509 01:02:12.080847 <6>[ 46.164481] vproc1: disabling
11510 01:02:12.084478 <6>[ 46.168103] vaud18: disabling
11511 01:02:12.091193 <6>[ 46.171604] vsram_others: disabling
11512 01:02:12.094324 <6>[ 46.175577] va09: disabling
11513 01:02:12.097824 <6>[ 46.178778] vsram_md: disabling
11514 01:02:12.100922 <6>[ 46.182365] Vgpu: disabling
11515 01:02:18.667632 # TAP version 13
11516 01:02:18.668147 # 1..16
11517 01:02:18.670566 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11518 01:02:18.674018 # # Will run for 10s
11519 01:02:18.677333 # # Started FPSIMD-0-0
11520 01:02:18.677786 # # Started FPSIMD-0-1
11521 01:02:18.680384 # # Started FPSIMD-1-0
11522 01:02:18.680813 # # Started FPSIMD-1-1
11523 01:02:18.683904 # # Started FPSIMD-2-0
11524 01:02:18.687078 # # Started FPSIMD-2-1
11525 01:02:18.687484 # # Started FPSIMD-3-0
11526 01:02:18.690434 # # Started FPSIMD-3-1
11527 01:02:18.693619 # # Started FPSIMD-4-0
11528 01:02:18.694080 # # Started FPSIMD-4-1
11529 01:02:18.696996 # # Started FPSIMD-5-0
11530 01:02:18.700349 # # Started FPSIMD-5-1
11531 01:02:18.700902 # # Started FPSIMD-6-0
11532 01:02:18.703397 # # Started FPSIMD-6-1
11533 01:02:18.703852 # # Started FPSIMD-7-0
11534 01:02:18.706858 # # Started FPSIMD-7-1
11535 01:02:18.710208 # # FPSIMD-0-1: Vector length: 128 bits
11536 01:02:18.713523 # # FPSIMD-0-1: PID: 1155
11537 01:02:18.716647 # # FPSIMD-0-0: Vector length: 128 bits
11538 01:02:18.719800 # # FPSIMD-0-0: PID: 1154
11539 01:02:18.723463 # # FPSIMD-2-1: Vector length: 128 bits
11540 01:02:18.723982 # # FPSIMD-2-1: PID: 1159
11541 01:02:18.726830 # # FPSIMD-2-0: Vector length: 128 bits
11542 01:02:18.729978 # # FPSIMD-2-0: PID: 1158
11543 01:02:18.733244 # # FPSIMD-1-1: Vector length: 128 bits
11544 01:02:18.736707 # # FPSIMD-1-1: PID: 1157
11545 01:02:18.740039 # # FPSIMD-1-0: Vector length: 128 bits
11546 01:02:18.743288 # # FPSIMD-1-0: PID: 1156
11547 01:02:18.746468 # # FPSIMD-3-1: Vector length: 128 bits
11548 01:02:18.749758 # # FPSIMD-3-1: PID: 1161
11549 01:02:18.753321 # # FPSIMD-6-0: Vector length: 128 bits
11550 01:02:18.753927 # # FPSIMD-6-0: PID: 1166
11551 01:02:18.756511 # # FPSIMD-6-1: Vector length: 128 bits
11552 01:02:18.759464 # # FPSIMD-6-1: PID: 1167
11553 01:02:18.763081 # # FPSIMD-4-1: Vector length: 128 bits
11554 01:02:18.766366 # # FPSIMD-4-1: PID: 1163
11555 01:02:18.769724 # # FPSIMD-4-0: Vector length: 128 bits
11556 01:02:18.772995 # # FPSIMD-4-0: PID: 1162
11557 01:02:18.776113 # # FPSIMD-7-1: Vector length: 128 bits
11558 01:02:18.779432 # # FPSIMD-7-1: PID: 1169
11559 01:02:18.782956 # # FPSIMD-3-0: Vector length: 128 bits
11560 01:02:18.783383 # # FPSIMD-3-0: PID: 1160
11561 01:02:18.785831 # # FPSIMD-5-1: Vector length: 128 bits
11562 01:02:18.789440 # # FPSIMD-5-1: PID: 1165
11563 01:02:18.792848 # # FPSIMD-5-0: Vector length: 128 bits
11564 01:02:18.795849 # # FPSIMD-5-0: PID: 1164
11565 01:02:18.799410 # # FPSIMD-7-0: Vector length: 128 bits
11566 01:02:18.802617 # # FPSIMD-7-0: PID: 1168
11567 01:02:18.803000 # # Finishing up...
11568 01:02:18.805939 # ok 1 FPSIMD-0-0
11569 01:02:18.806389 # ok 2 FPSIMD-0-1
11570 01:02:18.809064 # ok 3 FPSIMD-1-0
11571 01:02:18.809597 # ok 4 FPSIMD-1-1
11572 01:02:18.812538 # ok 5 FPSIMD-2-0
11573 01:02:18.813008 # ok 6 FPSIMD-2-1
11574 01:02:18.815605 # ok 7 FPSIMD-3-0
11575 01:02:18.816124 # ok 8 FPSIMD-3-1
11576 01:02:18.819107 # ok 9 FPSIMD-4-0
11577 01:02:18.819874 # ok 10 FPSIMD-4-1
11578 01:02:18.822405 # ok 11 FPSIMD-5-0
11579 01:02:18.823181 # ok 12 FPSIMD-5-1
11580 01:02:18.825728 # ok 13 FPSIMD-6-0
11581 01:02:18.826327 # ok 14 FPSIMD-6-1
11582 01:02:18.828950 # ok 15 FPSIMD-7-0
11583 01:02:18.829541 # ok 16 FPSIMD-7-1
11584 01:02:18.838824 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1204687, signals=10
11585 01:02:18.845444 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=2152710, signals=10
11586 01:02:18.851935 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1080329, signals=10
11587 01:02:18.858754 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=988886, signals=10
11588 01:02:18.865244 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1971165, signals=10
11589 01:02:18.871737 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1483672, signals=10
11590 01:02:18.881775 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1426430, signals=10
11591 01:02:18.888142 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=956482, signals=9
11592 01:02:18.895095 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1060440, signals=10
11593 01:02:18.901769 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1336070, signals=9
11594 01:02:18.908160 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=955001, signals=10
11595 01:02:18.914542 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=906290, signals=10
11596 01:02:18.924290 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1149832, signals=10
11597 01:02:18.930811 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1941037, signals=10
11598 01:02:18.937276 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=904793, signals=10
11599 01:02:18.943958 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=968122, signals=9
11600 01:02:18.950490 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11601 01:02:18.954044 ok 29 selftests: arm64: fp-stress
11602 01:02:18.954128 # selftests: arm64: sve-ptrace
11603 01:02:18.957387 # TAP version 13
11604 01:02:18.957483 # 1..4104
11605 01:02:18.960661 # ok 2 # SKIP SVE not available
11606 01:02:18.964037 # # Planned tests != run tests (4104 != 1)
11607 01:02:18.970450 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11608 01:02:18.974000 ok 30 selftests: arm64: sve-ptrace # SKIP
11609 01:02:18.977148 # selftests: arm64: sve-probe-vls
11610 01:02:18.977271 # TAP version 13
11611 01:02:18.977368 # 1..2
11612 01:02:18.980323 # ok 2 # SKIP SVE not available
11613 01:02:18.984152 # # Planned tests != run tests (2 != 1)
11614 01:02:18.990429 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11615 01:02:18.993438 ok 31 selftests: arm64: sve-probe-vls # SKIP
11616 01:02:18.996995 # selftests: arm64: vec-syscfg
11617 01:02:18.997270 # TAP version 13
11618 01:02:19.000146 # 1..20
11619 01:02:19.003474 # ok 1 # SKIP SVE not supported
11620 01:02:19.003750 # ok 2 # SKIP SVE not supported
11621 01:02:19.006854 # ok 3 # SKIP SVE not supported
11622 01:02:19.010230 # ok 4 # SKIP SVE not supported
11623 01:02:19.013445 # ok 5 # SKIP SVE not supported
11624 01:02:19.017216 # ok 6 # SKIP SVE not supported
11625 01:02:19.020321 # ok 7 # SKIP SVE not supported
11626 01:02:19.023529 # ok 8 # SKIP SVE not supported
11627 01:02:19.023978 # ok 9 # SKIP SVE not supported
11628 01:02:19.026756 # ok 10 # SKIP SVE not supported
11629 01:02:19.030123 # ok 11 # SKIP SME not supported
11630 01:02:19.033352 # ok 12 # SKIP SME not supported
11631 01:02:19.036510 # ok 13 # SKIP SME not supported
11632 01:02:19.039944 # ok 14 # SKIP SME not supported
11633 01:02:19.043354 # ok 15 # SKIP SME not supported
11634 01:02:19.046621 # ok 16 # SKIP SME not supported
11635 01:02:19.050057 # ok 17 # SKIP SME not supported
11636 01:02:19.053128 # ok 18 # SKIP SME not supported
11637 01:02:19.053628 # ok 19 # SKIP SME not supported
11638 01:02:19.056412 # ok 20 # SKIP SME not supported
11639 01:02:19.063207 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11640 01:02:19.066602 ok 32 selftests: arm64: vec-syscfg
11641 01:02:19.069899 # selftests: arm64: za-fork
11642 01:02:19.070322 # TAP version 13
11643 01:02:19.070654 # 1..1
11644 01:02:19.073280 # # PID: 1244
11645 01:02:19.073825 # # SME support not present
11646 01:02:19.076395 # ok 0 skipped
11647 01:02:19.079959 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11648 01:02:19.083076 ok 33 selftests: arm64: za-fork
11649 01:02:19.086236 # selftests: arm64: za-ptrace
11650 01:02:19.140461 # TAP version 13
11651 01:02:19.140970 # 1..1
11652 01:02:19.143678 # ok 2 # SKIP SME not available
11653 01:02:19.150317 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11654 01:02:19.153653 ok 34 selftests: arm64: za-ptrace # SKIP
11655 01:02:19.164290 # selftests: arm64: check_buffer_fill
11656 01:02:19.223920 # # SKIP: MTE features unavailable
11657 01:02:19.231574 ok 35 selftests: arm64: check_buffer_fill # SKIP
11658 01:02:19.249937 # selftests: arm64: check_child_memory
11659 01:02:19.311377 # # SKIP: MTE features unavailable
11660 01:02:19.318752 ok 36 selftests: arm64: check_child_memory # SKIP
11661 01:02:19.339440 # selftests: arm64: check_gcr_el1_cswitch
11662 01:02:19.410353 # # SKIP: MTE features unavailable
11663 01:02:19.417667 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11664 01:02:19.435153 # selftests: arm64: check_ksm_options
11665 01:02:19.496523 # # SKIP: MTE features unavailable
11666 01:02:19.503739 ok 38 selftests: arm64: check_ksm_options # SKIP
11667 01:02:19.520073 # selftests: arm64: check_mmap_options
11668 01:02:19.590832 # # SKIP: MTE features unavailable
11669 01:02:19.597766 ok 39 selftests: arm64: check_mmap_options # SKIP
11670 01:02:19.612353 # selftests: arm64: check_prctl
11671 01:02:19.687502 # TAP version 13
11672 01:02:19.687962 # 1..5
11673 01:02:19.690690 # ok 1 check_basic_read
11674 01:02:19.691130 # ok 2 NONE
11675 01:02:19.693874 # ok 3 # SKIP SYNC
11676 01:02:19.694355 # ok 4 # SKIP ASYNC
11677 01:02:19.697227 # ok 5 # SKIP SYNC+ASYNC
11678 01:02:19.700501 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11679 01:02:19.703748 ok 40 selftests: arm64: check_prctl
11680 01:02:19.714557 # selftests: arm64: check_tags_inclusion
11681 01:02:19.782735 # # SKIP: MTE features unavailable
11682 01:02:19.789871 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11683 01:02:19.804512 # selftests: arm64: check_user_mem
11684 01:02:19.873867 # # SKIP: MTE features unavailable
11685 01:02:19.882152 ok 42 selftests: arm64: check_user_mem # SKIP
11686 01:02:19.896665 # selftests: arm64: btitest
11687 01:02:19.954834 # TAP version 13
11688 01:02:19.954935 # 1..18
11689 01:02:19.958584 # # HWCAP_PACA not present
11690 01:02:19.961820 # # HWCAP2_BTI not present
11691 01:02:19.962242 # # Test binary built for BTI
11692 01:02:19.968456 # ok 1 nohint_func/call_using_br_x0 # SKIP
11693 01:02:19.971644 # ok 1 nohint_func/call_using_br_x16 # SKIP
11694 01:02:19.975167 # ok 1 nohint_func/call_using_blr # SKIP
11695 01:02:19.978450 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11696 01:02:19.981627 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11697 01:02:19.988244 # ok 1 bti_none_func/call_using_blr # SKIP
11698 01:02:19.991400 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11699 01:02:19.994715 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11700 01:02:19.997966 # ok 1 bti_c_func/call_using_blr # SKIP
11701 01:02:20.001320 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11702 01:02:20.004737 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11703 01:02:20.007900 # ok 1 bti_j_func/call_using_blr # SKIP
11704 01:02:20.011432 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11705 01:02:20.017805 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11706 01:02:20.021085 # ok 1 bti_jc_func/call_using_blr # SKIP
11707 01:02:20.024631 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11708 01:02:20.027801 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11709 01:02:20.031125 # ok 1 paciasp_func/call_using_blr # SKIP
11710 01:02:20.037719 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11711 01:02:20.040910 # # WARNING - EXPECTED TEST COUNT WRONG
11712 01:02:20.044200 ok 43 selftests: arm64: btitest
11713 01:02:20.047501 # selftests: arm64: nobtitest
11714 01:02:20.047918 # TAP version 13
11715 01:02:20.048250 # 1..18
11716 01:02:20.050738 # # HWCAP_PACA not present
11717 01:02:20.054249 # # HWCAP2_BTI not present
11718 01:02:20.057450 # # Test binary not built for BTI
11719 01:02:20.060827 # ok 1 nohint_func/call_using_br_x0 # SKIP
11720 01:02:20.064000 # ok 1 nohint_func/call_using_br_x16 # SKIP
11721 01:02:20.067419 # ok 1 nohint_func/call_using_blr # SKIP
11722 01:02:20.070931 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11723 01:02:20.077547 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11724 01:02:20.080665 # ok 1 bti_none_func/call_using_blr # SKIP
11725 01:02:20.083915 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11726 01:02:20.087122 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11727 01:02:20.090542 # ok 1 bti_c_func/call_using_blr # SKIP
11728 01:02:20.093884 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11729 01:02:20.097158 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11730 01:02:20.100387 # ok 1 bti_j_func/call_using_blr # SKIP
11731 01:02:20.106850 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11732 01:02:20.110475 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11733 01:02:20.113596 # ok 1 bti_jc_func/call_using_blr # SKIP
11734 01:02:20.117009 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11735 01:02:20.120117 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11736 01:02:20.123600 # ok 1 paciasp_func/call_using_blr # SKIP
11737 01:02:20.130134 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11738 01:02:20.133583 # # WARNING - EXPECTED TEST COUNT WRONG
11739 01:02:20.136599 ok 44 selftests: arm64: nobtitest
11740 01:02:20.140062 # selftests: arm64: hwcap
11741 01:02:20.140484 # TAP version 13
11742 01:02:20.140824 # 1..28
11743 01:02:20.143224 # ok 1 cpuinfo_match_RNG
11744 01:02:20.146697 # # SIGILL reported for RNG
11745 01:02:20.147138 # ok 2 # SKIP sigill_RNG
11746 01:02:20.149936 # ok 3 cpuinfo_match_SME
11747 01:02:20.153053 # ok 4 sigill_SME
11748 01:02:20.153512 # ok 5 cpuinfo_match_SVE
11749 01:02:20.156513 # ok 6 sigill_SVE
11750 01:02:20.159858 # ok 7 cpuinfo_match_SVE 2
11751 01:02:20.160283 # # SIGILL reported for SVE 2
11752 01:02:20.163052 # ok 8 # SKIP sigill_SVE 2
11753 01:02:20.166291 # ok 9 cpuinfo_match_SVE AES
11754 01:02:20.169703 # # SIGILL reported for SVE AES
11755 01:02:20.172769 # ok 10 # SKIP sigill_SVE AES
11756 01:02:20.173302 # ok 11 cpuinfo_match_SVE2 PMULL
11757 01:02:20.176272 # # SIGILL reported for SVE2 PMULL
11758 01:02:20.179506 # ok 12 # SKIP sigill_SVE2 PMULL
11759 01:02:20.182951 # ok 13 cpuinfo_match_SVE2 BITPERM
11760 01:02:20.186222 # # SIGILL reported for SVE2 BITPERM
11761 01:02:20.189593 # ok 14 # SKIP sigill_SVE2 BITPERM
11762 01:02:20.192922 # ok 15 cpuinfo_match_SVE2 SHA3
11763 01:02:20.195966 # # SIGILL reported for SVE2 SHA3
11764 01:02:20.199268 # ok 16 # SKIP sigill_SVE2 SHA3
11765 01:02:20.202769 # ok 17 cpuinfo_match_SVE2 SM4
11766 01:02:20.205815 # # SIGILL reported for SVE2 SM4
11767 01:02:20.206053 # ok 18 # SKIP sigill_SVE2 SM4
11768 01:02:20.209126 # ok 19 cpuinfo_match_SVE2 I8MM
11769 01:02:20.212576 # # SIGILL reported for SVE2 I8MM
11770 01:02:20.215780 # ok 20 # SKIP sigill_SVE2 I8MM
11771 01:02:20.218997 # ok 21 cpuinfo_match_SVE2 F32MM
11772 01:02:20.222278 # # SIGILL reported for SVE2 F32MM
11773 01:02:20.225419 # ok 22 # SKIP sigill_SVE2 F32MM
11774 01:02:20.228983 # ok 23 cpuinfo_match_SVE2 F64MM
11775 01:02:20.232100 # # SIGILL reported for SVE2 F64MM
11776 01:02:20.235688 # ok 24 # SKIP sigill_SVE2 F64MM
11777 01:02:20.235971 # ok 25 cpuinfo_match_SVE2 BF16
11778 01:02:20.239044 # # SIGILL reported for SVE2 BF16
11779 01:02:20.242391 # ok 26 # SKIP sigill_SVE2 BF16
11780 01:02:20.245527 # ok 27 cpuinfo_match_SVE2 EBF16
11781 01:02:20.248735 # ok 28 # SKIP sigill_SVE2 EBF16
11782 01:02:20.255345 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11783 01:02:20.255427 ok 45 selftests: arm64: hwcap
11784 01:02:20.258440 # selftests: arm64: ptrace
11785 01:02:20.261831 # TAP version 13
11786 01:02:20.261912 # 1..7
11787 01:02:20.265354 # # Parent is 1486, child is 1487
11788 01:02:20.265434 # ok 1 read_tpidr_one
11789 01:02:20.268421 # ok 2 write_tpidr_one
11790 01:02:20.271990 # ok 3 verify_tpidr_one
11791 01:02:20.272071 # ok 4 count_tpidrs
11792 01:02:20.275109 # ok 5 tpidr2_write
11793 01:02:20.275191 # ok 6 tpidr2_read
11794 01:02:20.278532 # ok 7 write_tpidr_only
11795 01:02:20.281540 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11796 01:02:20.284871 ok 46 selftests: arm64: ptrace
11797 01:02:20.288284 # selftests: arm64: syscall-abi
11798 01:02:20.296034 # TAP version 13
11799 01:02:20.296116 # 1..2
11800 01:02:20.299081 # ok 1 getpid() FPSIMD
11801 01:02:20.302404 # ok 2 sched_yield() FPSIMD
11802 01:02:20.305590 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11803 01:02:20.308783 ok 47 selftests: arm64: syscall-abi
11804 01:02:20.313939 # selftests: arm64: tpidr2
11805 01:02:20.376873 # TAP version 13
11806 01:02:20.376987 # 1..5
11807 01:02:20.380174 # # PID: 1523
11808 01:02:20.380295 # # SME support not present
11809 01:02:20.383592 # ok 0 skipped, TPIDR2 not supported
11810 01:02:20.386815 # ok 1 skipped, TPIDR2 not supported
11811 01:02:20.390508 # ok 2 skipped, TPIDR2 not supported
11812 01:02:20.393449 # ok 3 skipped, TPIDR2 not supported
11813 01:02:20.396564 # ok 4 skipped, TPIDR2 not supported
11814 01:02:20.403264 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11815 01:02:20.406614 ok 48 selftests: arm64: tpidr2
11816 01:02:21.065305 arm64_tags_test pass
11817 01:02:21.068518 arm64_run_tags_test_sh pass
11818 01:02:21.071770 arm64_fake_sigreturn_bad_magic pass
11819 01:02:21.075239 arm64_fake_sigreturn_bad_size pass
11820 01:02:21.078465 arm64_fake_sigreturn_bad_size_for_magic0 pass
11821 01:02:21.081912 arm64_fake_sigreturn_duplicated_fpsimd pass
11822 01:02:21.085001 arm64_fake_sigreturn_misaligned_sp pass
11823 01:02:21.088292 arm64_fake_sigreturn_missing_fpsimd pass
11824 01:02:21.091541 arm64_fake_sigreturn_sme_change_vl skip
11825 01:02:21.098087 arm64_fake_sigreturn_sve_change_vl skip
11826 01:02:21.101639 arm64_mangle_pstate_invalid_compat_toggle pass
11827 01:02:21.104858 arm64_mangle_pstate_invalid_daif_bits pass
11828 01:02:21.108248 arm64_mangle_pstate_invalid_mode_el1h pass
11829 01:02:21.111757 arm64_mangle_pstate_invalid_mode_el1t pass
11830 01:02:21.114893 arm64_mangle_pstate_invalid_mode_el2h pass
11831 01:02:21.121519 arm64_mangle_pstate_invalid_mode_el2t pass
11832 01:02:21.124749 arm64_mangle_pstate_invalid_mode_el3h pass
11833 01:02:21.128190 arm64_mangle_pstate_invalid_mode_el3t pass
11834 01:02:21.131148 arm64_sme_trap_no_sm skip
11835 01:02:21.131570 arm64_sme_trap_non_streaming skip
11836 01:02:21.134738 arm64_sme_trap_za pass
11837 01:02:21.137870 arm64_sme_vl skip
11838 01:02:21.138349 arm64_ssve_regs skip
11839 01:02:21.141115 arm64_sve_regs skip
11840 01:02:21.141580 arm64_sve_vl skip
11841 01:02:21.144555 arm64_za_no_regs skip
11842 01:02:21.144976 arm64_za_regs skip
11843 01:02:21.147995 arm64_pac_pauth_not_enabled skip
11844 01:02:21.151123 arm64_pac_pauth_not_enabled skip
11845 01:02:21.154166 arm64_pac_generic_pauth_not_enabled skip
11846 01:02:21.157780 arm64_pac_pauth_not_enabled skip
11847 01:02:21.161137 arm64_pac_pauth_not_enabled skip
11848 01:02:21.164370 arm64_pac_pauth_not_enabled skip
11849 01:02:21.167917 arm64_pac_generic_pauth_not_enabled skip
11850 01:02:21.168449 arm64_pac pass
11851 01:02:21.171078 arm64_fp-stress_FPSIMD-0-0 pass
11852 01:02:21.174339 arm64_fp-stress_FPSIMD-0-1 pass
11853 01:02:21.177684 arm64_fp-stress_FPSIMD-1-0 pass
11854 01:02:21.180948 arm64_fp-stress_FPSIMD-1-1 pass
11855 01:02:21.184461 arm64_fp-stress_FPSIMD-2-0 pass
11856 01:02:21.187486 arm64_fp-stress_FPSIMD-2-1 pass
11857 01:02:21.190677 arm64_fp-stress_FPSIMD-3-0 pass
11858 01:02:21.191142 arm64_fp-stress_FPSIMD-3-1 pass
11859 01:02:21.193889 arm64_fp-stress_FPSIMD-4-0 pass
11860 01:02:21.197372 arm64_fp-stress_FPSIMD-4-1 pass
11861 01:02:21.200560 arm64_fp-stress_FPSIMD-5-0 pass
11862 01:02:21.203807 arm64_fp-stress_FPSIMD-5-1 pass
11863 01:02:21.207326 arm64_fp-stress_FPSIMD-6-0 pass
11864 01:02:21.210277 arm64_fp-stress_FPSIMD-6-1 pass
11865 01:02:21.213693 arm64_fp-stress_FPSIMD-7-0 pass
11866 01:02:21.214119 arm64_fp-stress_FPSIMD-7-1 pass
11867 01:02:21.217272 arm64_fp-stress pass
11868 01:02:21.220694 arm64_sve-ptrace_sve_not_available skip
11869 01:02:21.223440 arm64_sve-ptrace skip
11870 01:02:21.226856 arm64_sve-probe-vls_sve_not_available skip
11871 01:02:21.227295 arm64_sve-probe-vls skip
11872 01:02:21.233546 arm64_vec-syscfg_sve_not_supported skip
11873 01:02:21.237088 arm64_vec-syscfg_sve_not_supported skip
11874 01:02:21.240215 arm64_vec-syscfg_sve_not_supported skip
11875 01:02:21.243373 arm64_vec-syscfg_sve_not_supported skip
11876 01:02:21.246852 arm64_vec-syscfg_sve_not_supported skip
11877 01:02:21.250064 arm64_vec-syscfg_sve_not_supported skip
11878 01:02:21.253517 arm64_vec-syscfg_sve_not_supported skip
11879 01:02:21.256607 arm64_vec-syscfg_sve_not_supported skip
11880 01:02:21.260408 arm64_vec-syscfg_sve_not_supported skip
11881 01:02:21.263067 arm64_vec-syscfg_sve_not_supported skip
11882 01:02:21.266652 arm64_vec-syscfg_sme_not_supported skip
11883 01:02:21.269942 arm64_vec-syscfg_sme_not_supported skip
11884 01:02:21.273089 arm64_vec-syscfg_sme_not_supported skip
11885 01:02:21.279806 arm64_vec-syscfg_sme_not_supported skip
11886 01:02:21.283113 arm64_vec-syscfg_sme_not_supported skip
11887 01:02:21.286481 arm64_vec-syscfg_sme_not_supported skip
11888 01:02:21.289815 arm64_vec-syscfg_sme_not_supported skip
11889 01:02:21.292833 arm64_vec-syscfg_sme_not_supported skip
11890 01:02:21.296029 arm64_vec-syscfg_sme_not_supported skip
11891 01:02:21.299479 arm64_vec-syscfg_sme_not_supported skip
11892 01:02:21.302747 arm64_vec-syscfg pass
11893 01:02:21.302837 arm64_za-fork_skipped pass
11894 01:02:21.306187 arm64_za-fork pass
11895 01:02:21.309050 arm64_za-ptrace_sme_not_available skip
11896 01:02:21.312616 arm64_za-ptrace skip
11897 01:02:21.312718 arm64_check_buffer_fill skip
11898 01:02:21.315932 arm64_check_child_memory skip
11899 01:02:21.319177 arm64_check_gcr_el1_cswitch skip
11900 01:02:21.322615 arm64_check_ksm_options skip
11901 01:02:21.325460 arm64_check_mmap_options skip
11902 01:02:21.328903 arm64_check_prctl_check_basic_read pass
11903 01:02:21.329039 arm64_check_prctl_NONE pass
11904 01:02:21.332431 arm64_check_prctl_sync skip
11905 01:02:21.335581 arm64_check_prctl_async skip
11906 01:02:21.338860 arm64_check_prctl_sync_async skip
11907 01:02:21.342210 arm64_check_prctl pass
11908 01:02:21.342413 arm64_check_tags_inclusion skip
11909 01:02:21.345230 arm64_check_user_mem skip
11910 01:02:21.348625 arm64_btitest_nohint_func_call_using_br_x0 skip
11911 01:02:21.355636 arm64_btitest_nohint_func_call_using_br_x16 skip
11912 01:02:21.358891 arm64_btitest_nohint_func_call_using_blr skip
11913 01:02:21.362046 arm64_btitest_bti_none_func_call_using_br_x0 skip
11914 01:02:21.368427 arm64_btitest_bti_none_func_call_using_br_x16 skip
11915 01:02:21.371920 arm64_btitest_bti_none_func_call_using_blr skip
11916 01:02:21.375269 arm64_btitest_bti_c_func_call_using_br_x0 skip
11917 01:02:21.382071 arm64_btitest_bti_c_func_call_using_br_x16 skip
11918 01:02:21.385576 arm64_btitest_bti_c_func_call_using_blr skip
11919 01:02:21.388913 arm64_btitest_bti_j_func_call_using_br_x0 skip
11920 01:02:21.392078 arm64_btitest_bti_j_func_call_using_br_x16 skip
11921 01:02:21.395427 arm64_btitest_bti_j_func_call_using_blr skip
11922 01:02:21.401704 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11923 01:02:21.405174 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11924 01:02:21.408364 arm64_btitest_bti_jc_func_call_using_blr skip
11925 01:02:21.415087 arm64_btitest_paciasp_func_call_using_br_x0 skip
11926 01:02:21.418424 arm64_btitest_paciasp_func_call_using_br_x16 skip
11927 01:02:21.421608 arm64_btitest_paciasp_func_call_using_blr skip
11928 01:02:21.424823 arm64_btitest pass
11929 01:02:21.428259 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11930 01:02:21.431561 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11931 01:02:21.438063 arm64_nobtitest_nohint_func_call_using_blr skip
11932 01:02:21.441574 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11933 01:02:21.448239 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11934 01:02:21.451223 arm64_nobtitest_bti_none_func_call_using_blr skip
11935 01:02:21.454695 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11936 01:02:21.461212 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11937 01:02:21.464609 arm64_nobtitest_bti_c_func_call_using_blr skip
11938 01:02:21.467893 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11939 01:02:21.474553 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11940 01:02:21.477620 arm64_nobtitest_bti_j_func_call_using_blr skip
11941 01:02:21.481362 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11942 01:02:21.484368 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11943 01:02:21.490925 arm64_nobtitest_bti_jc_func_call_using_blr skip
11944 01:02:21.494136 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11945 01:02:21.500908 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11946 01:02:21.504223 arm64_nobtitest_paciasp_func_call_using_blr skip
11947 01:02:21.504647 arm64_nobtitest pass
11948 01:02:21.507413 arm64_hwcap_cpuinfo_match_RNG pass
11949 01:02:21.510958 arm64_hwcap_sigill_rng skip
11950 01:02:21.514201 arm64_hwcap_cpuinfo_match_SME pass
11951 01:02:21.517321 arm64_hwcap_sigill_SME pass
11952 01:02:21.520435 arm64_hwcap_cpuinfo_match_SVE pass
11953 01:02:21.523937 arm64_hwcap_sigill_SVE pass
11954 01:02:21.527352 arm64_hwcap_cpuinfo_match_SVE_2 pass
11955 01:02:21.527774 arm64_hwcap_sigill_sve_2 skip
11956 01:02:21.530492 arm64_hwcap_cpuinfo_match_SVE_AES pass
11957 01:02:21.533640 arm64_hwcap_sigill_sve_aes skip
11958 01:02:21.537362 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11959 01:02:21.540581 arm64_hwcap_sigill_sve2_pmull skip
11960 01:02:21.547422 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11961 01:02:21.550279 arm64_hwcap_sigill_sve2_bitperm skip
11962 01:02:21.553769 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11963 01:02:21.556989 arm64_hwcap_sigill_sve2_sha3 skip
11964 01:02:21.560149 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11965 01:02:21.563680 arm64_hwcap_sigill_sve2_sm4 skip
11966 01:02:21.566771 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11967 01:02:21.570146 arm64_hwcap_sigill_sve2_i8mm skip
11968 01:02:21.573295 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11969 01:02:21.576688 arm64_hwcap_sigill_sve2_f32mm skip
11970 01:02:21.580209 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11971 01:02:21.583400 arm64_hwcap_sigill_sve2_f64mm skip
11972 01:02:21.586834 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11973 01:02:21.590057 arm64_hwcap_sigill_sve2_bf16 skip
11974 01:02:21.593281 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11975 01:02:21.596466 arm64_hwcap_sigill_sve2_ebf16 skip
11976 01:02:21.596891 arm64_hwcap pass
11977 01:02:21.599722 arm64_ptrace_read_tpidr_one pass
11978 01:02:21.602993 arm64_ptrace_write_tpidr_one pass
11979 01:02:21.606305 arm64_ptrace_verify_tpidr_one pass
11980 01:02:21.609290 arm64_ptrace_count_tpidrs pass
11981 01:02:21.612713 arm64_ptrace_tpidr2_write pass
11982 01:02:21.616032 arm64_ptrace_tpidr2_read pass
11983 01:02:21.619250 arm64_ptrace_write_tpidr_only pass
11984 01:02:21.619434 arm64_ptrace pass
11985 01:02:21.622715 arm64_syscall-abi_getpid_FPSIMD pass
11986 01:02:21.625933 arm64_syscall-abi_sched_yield_FPSIMD pass
11987 01:02:21.629194 arm64_syscall-abi pass
11988 01:02:21.632562 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11989 01:02:21.635899 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11990 01:02:21.642411 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11991 01:02:21.645967 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11992 01:02:21.649050 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11993 01:02:21.652424 arm64_tpidr2 pass
11994 01:02:21.655569 + ../../utils/send-to-lava.sh ./output/result.txt
11995 01:02:21.662369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11996 01:02:21.663167 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11998 01:02:21.665714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11999 01:02:21.666452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12001 01:02:21.672227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12002 01:02:21.672914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12004 01:02:21.716221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12005 01:02:21.716484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12007 01:02:21.776343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12008 01:02:21.776611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12010 01:02:21.839303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12011 01:02:21.839617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12013 01:02:21.902704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12014 01:02:21.902969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12016 01:02:21.965951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12017 01:02:21.966229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12019 01:02:22.027813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12020 01:02:22.028084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12022 01:02:22.086292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12023 01:02:22.086589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12025 01:02:22.144028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12026 01:02:22.144335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12028 01:02:22.200385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12029 01:02:22.200681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12031 01:02:22.266086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12032 01:02:22.266362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12034 01:02:22.332133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12035 01:02:22.332409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12037 01:02:22.397320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12038 01:02:22.397587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12040 01:02:22.457429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12041 01:02:22.457750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12043 01:02:22.516386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12044 01:02:22.516652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12046 01:02:22.579213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12047 01:02:22.579481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12049 01:02:22.638873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12050 01:02:22.639140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12052 01:02:22.696853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12053 01:02:22.697122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12055 01:02:22.768056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12056 01:02:22.768327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12058 01:02:22.828017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12059 01:02:22.828298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12061 01:02:22.893097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12062 01:02:22.893362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12064 01:02:22.956076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12065 01:02:22.956346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12067 01:02:23.024243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12068 01:02:23.024521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12070 01:02:23.089316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12071 01:02:23.089577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12073 01:02:23.147269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12074 01:02:23.147539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12076 01:02:23.215357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12077 01:02:23.215625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12079 01:02:23.267900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12081 01:02:23.270884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12082 01:02:23.328160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12084 01:02:23.331149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12085 01:02:23.395076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12086 01:02:23.395375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12088 01:02:23.454592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12089 01:02:23.454868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12091 01:02:23.517664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12093 01:02:23.520690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12094 01:02:23.584604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12096 01:02:23.587688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12097 01:02:23.654718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12098 01:02:23.655424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12100 01:02:23.718708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12101 01:02:23.719463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12103 01:02:23.786733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12104 01:02:23.787427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12106 01:02:23.858653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12107 01:02:23.859368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12109 01:02:23.921926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12110 01:02:23.922195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12112 01:02:23.987092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12113 01:02:23.987356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12115 01:02:24.048491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12116 01:02:24.048774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12118 01:02:24.107724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12119 01:02:24.107986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12121 01:02:24.168241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12122 01:02:24.168509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12124 01:02:24.230687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12125 01:02:24.230963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12127 01:02:24.296955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12128 01:02:24.297224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12130 01:02:24.365792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12131 01:02:24.366494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12133 01:02:24.440540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12134 01:02:24.441432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12136 01:02:24.503276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12137 01:02:24.503977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12139 01:02:24.564235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12140 01:02:24.564946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12142 01:02:24.635542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12144 01:02:24.638385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12145 01:02:24.706364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12146 01:02:24.707116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12148 01:02:24.780878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12149 01:02:24.781607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12151 01:02:24.858511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12152 01:02:24.859276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12154 01:02:24.922239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12155 01:02:24.922509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12157 01:02:24.979923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12158 01:02:24.980186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12160 01:02:25.039848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12161 01:02:25.040126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12163 01:02:25.100186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12164 01:02:25.100449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12166 01:02:25.163363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12167 01:02:25.163631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12169 01:02:25.224282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12170 01:02:25.224549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12172 01:02:25.286082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12173 01:02:25.286344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12175 01:02:25.349147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12176 01:02:25.349459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12178 01:02:25.409002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12179 01:02:25.409266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12181 01:02:25.472328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12182 01:02:25.472600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12184 01:02:25.539443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12185 01:02:25.540203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12187 01:02:25.606806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12188 01:02:25.607562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12190 01:02:25.680530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12191 01:02:25.681252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12193 01:02:25.744576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12194 01:02:25.745283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12196 01:02:25.816896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12197 01:02:25.817653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12199 01:02:25.889168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12200 01:02:25.889928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12202 01:02:25.960495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12203 01:02:25.961255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12205 01:02:26.029855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12206 01:02:26.030565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12208 01:02:26.099559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12209 01:02:26.100305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12211 01:02:26.166144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12212 01:02:26.166861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12214 01:02:26.239983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12215 01:02:26.240850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12217 01:02:26.311053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12218 01:02:26.311746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12220 01:02:26.375833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12221 01:02:26.376594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12223 01:02:26.442063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12224 01:02:26.442820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12226 01:02:26.504227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12227 01:02:26.504976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12229 01:02:26.573756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12230 01:02:26.574543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12232 01:02:26.641736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12233 01:02:26.642566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12235 01:02:26.711136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12236 01:02:26.712042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12238 01:02:26.780639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12239 01:02:26.781428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12241 01:02:26.854670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12242 01:02:26.855432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12244 01:02:26.915851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12245 01:02:26.916605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12247 01:02:26.985804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12249 01:02:26.988462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12250 01:02:27.049946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12251 01:02:27.050227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12253 01:02:27.110682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12254 01:02:27.110943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12256 01:02:27.176252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12257 01:02:27.176524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12259 01:02:27.240717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12260 01:02:27.241526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12262 01:02:27.307934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12263 01:02:27.308822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12265 01:02:27.378330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12266 01:02:27.379054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12268 01:02:27.444137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12270 01:02:27.446850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12271 01:02:27.516739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12272 01:02:27.517564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12274 01:02:27.584530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12275 01:02:27.585390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12277 01:02:27.655523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12278 01:02:27.656493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12280 01:02:27.731227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12281 01:02:27.732141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12283 01:02:27.801298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12284 01:02:27.802327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12286 01:02:27.874416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12287 01:02:27.875337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12289 01:02:27.946804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12290 01:02:27.947656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12292 01:02:28.023126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12293 01:02:28.023398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12295 01:02:28.083929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12296 01:02:28.084197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12298 01:02:28.150290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12299 01:02:28.150596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12301 01:02:28.219345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12302 01:02:28.219642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12304 01:02:28.289106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12305 01:02:28.289402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12307 01:02:28.346372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12308 01:02:28.346651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12310 01:02:28.408865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12311 01:02:28.409127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12313 01:02:28.471765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12314 01:02:28.472453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12316 01:02:28.545519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12317 01:02:28.546328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12319 01:02:28.618153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12320 01:02:28.618958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12322 01:02:28.690471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12323 01:02:28.691367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12325 01:02:28.755382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12326 01:02:28.755681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12328 01:02:28.823307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12329 01:02:28.823633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12331 01:02:28.878886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12332 01:02:28.879201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12334 01:02:28.936136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12335 01:02:28.936449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12337 01:02:28.996920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12338 01:02:28.997184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12340 01:02:29.063469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12341 01:02:29.063741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12343 01:02:29.127514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12344 01:02:29.127796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12346 01:02:29.183941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12347 01:02:29.184841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12349 01:02:29.255694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12350 01:02:29.256601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12352 01:02:29.329200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12353 01:02:29.329531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12355 01:02:29.391409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12356 01:02:29.391673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12358 01:02:29.454290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12359 01:02:29.454560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12361 01:02:29.520776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12362 01:02:29.521037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12364 01:02:29.583366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12365 01:02:29.583638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12367 01:02:29.649686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12368 01:02:29.649963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12370 01:02:29.705608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12371 01:02:29.705866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12373 01:02:29.765985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12374 01:02:29.766253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12376 01:02:29.827368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12377 01:02:29.827630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12379 01:02:29.888682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12380 01:02:29.888949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12382 01:02:29.949898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12383 01:02:29.950215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12385 01:02:30.014791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12386 01:02:30.015067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12388 01:02:30.070654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12389 01:02:30.070924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12391 01:02:30.136645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12392 01:02:30.136910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12394 01:02:30.203326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12395 01:02:30.203596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12397 01:02:30.259341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12398 01:02:30.259611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12400 01:02:30.326889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12401 01:02:30.327153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12403 01:02:30.379808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12404 01:02:30.380073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12406 01:02:30.438775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12407 01:02:30.439040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12409 01:02:30.504574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12410 01:02:30.504840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12412 01:02:30.569768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12413 01:02:30.570036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12415 01:02:30.628166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12416 01:02:30.628464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12418 01:02:30.696985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12419 01:02:30.697252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12421 01:02:30.749149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12422 01:02:30.749422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12424 01:02:30.818447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12425 01:02:30.818710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12427 01:02:30.881437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12428 01:02:30.881727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12430 01:02:30.944765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12431 01:02:30.945088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12433 01:02:31.001574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12434 01:02:31.001875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12436 01:02:31.064945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12437 01:02:31.065249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12439 01:02:31.127284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12440 01:02:31.127584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12442 01:02:31.183198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12443 01:02:31.183498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12445 01:02:31.247023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12447 01:02:31.250053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12448 01:02:31.305921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12449 01:02:31.306182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12451 01:02:31.367837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12453 01:02:31.370790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12454 01:02:31.433232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12455 01:02:31.433529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12457 01:02:31.497865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12458 01:02:31.498134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12460 01:02:31.558489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12461 01:02:31.558782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12463 01:02:31.622277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12464 01:02:31.622542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12466 01:02:31.692292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12467 01:02:31.692597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12469 01:02:31.755045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12471 01:02:31.758021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12472 01:02:31.823942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12473 01:02:31.824234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12475 01:02:31.883120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12476 01:02:31.883387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12478 01:02:31.940643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12479 01:02:31.940907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12481 01:02:32.007509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12483 01:02:32.010414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12484 01:02:32.074847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12486 01:02:32.077956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12487 01:02:32.144734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12488 01:02:32.145062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12490 01:02:32.202788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12491 01:02:32.203063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12493 01:02:32.265437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12494 01:02:32.265795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12496 01:02:32.330052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12497 01:02:32.330324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12499 01:02:32.391505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12501 01:02:32.394730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12502 01:02:32.455146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12503 01:02:32.455439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12505 01:02:32.512982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12506 01:02:32.513269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12508 01:02:32.575740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12509 01:02:32.576006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12511 01:02:32.640986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12512 01:02:32.641250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12514 01:02:32.710283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12515 01:02:32.710556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12517 01:02:32.774131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12518 01:02:32.774395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12520 01:02:32.832735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12521 01:02:32.833051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12523 01:02:32.903434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12524 01:02:32.903702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12526 01:02:32.963845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12527 01:02:32.964128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12529 01:02:33.027749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12530 01:02:33.027845 + set +x
12531 01:02:33.028085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12533 01:02:33.034207 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12571114_1.6.2.3.5>
12534 01:02:33.034470 Received signal: <ENDRUN> 1_kselftest-arm64 12571114_1.6.2.3.5
12535 01:02:33.034545 Ending use of test pattern.
12536 01:02:33.034607 Ending test lava.1_kselftest-arm64 (12571114_1.6.2.3.5), duration 37.07
12538 01:02:33.037699 <LAVA_TEST_RUNNER EXIT>
12539 01:02:33.037952 ok: lava_test_shell seems to have completed
12540 01:02:33.038978 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12541 01:02:33.039127 end: 3.1 lava-test-shell (duration 00:00:38) [common]
12542 01:02:33.039225 end: 3 lava-test-retry (duration 00:00:38) [common]
12543 01:02:33.039313 start: 4 finalize (timeout 00:06:50) [common]
12544 01:02:33.039401 start: 4.1 power-off (timeout 00:00:30) [common]
12545 01:02:33.039553 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12546 01:02:33.115448 >> Command sent successfully.
12547 01:02:33.118281 Returned 0 in 0 seconds
12548 01:02:33.219114 end: 4.1 power-off (duration 00:00:00) [common]
12550 01:02:33.220827 start: 4.2 read-feedback (timeout 00:06:50) [common]
12551 01:02:33.222254 Listened to connection for namespace 'common' for up to 1s
12552 01:02:34.222775 Finalising connection for namespace 'common'
12553 01:02:34.223376 Disconnecting from shell: Finalise
12554 01:02:34.223806 / #
12555 01:02:34.324759 end: 4.2 read-feedback (duration 00:00:01) [common]
12556 01:02:34.325467 end: 4 finalize (duration 00:00:01) [common]
12557 01:02:34.326127 Cleaning after the job
12558 01:02:34.326604 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/ramdisk
12559 01:02:34.338390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/kernel
12560 01:02:34.366033 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/dtb
12561 01:02:34.366280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/nfsrootfs
12562 01:02:34.459430 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571114/tftp-deploy-9rsx53qq/modules
12563 01:02:34.467033 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571114
12564 01:02:35.136738 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571114
12565 01:02:35.136919 Job finished correctly