Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 17
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
1 00:59:02.645881 lava-dispatcher, installed at version: 2023.10
2 00:59:02.646088 start: 0 validate
3 00:59:02.646214 Start time: 2024-01-19 00:59:02.646207+00:00 (UTC)
4 00:59:02.646327 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:59:02.646467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 00:59:02.909645 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:59:02.909818 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:59:03.166218 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:59:03.166391 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:59:03.431772 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:59:03.431944 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:59:03.697220 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:59:03.697392 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:59:03.964216 validate duration: 1.32
16 00:59:03.964477 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:59:03.964577 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:59:03.964667 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:59:03.964789 Not decompressing ramdisk as can be used compressed.
20 00:59:03.964876 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 00:59:03.964943 saving as /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/ramdisk/initrd.cpio.gz
22 00:59:03.965012 total size: 4665395 (4 MB)
23 00:59:03.966028 progress 0 % (0 MB)
24 00:59:03.967356 progress 5 % (0 MB)
25 00:59:03.968552 progress 10 % (0 MB)
26 00:59:03.969745 progress 15 % (0 MB)
27 00:59:03.970943 progress 20 % (0 MB)
28 00:59:03.972127 progress 25 % (1 MB)
29 00:59:03.973312 progress 30 % (1 MB)
30 00:59:03.974600 progress 35 % (1 MB)
31 00:59:03.975827 progress 40 % (1 MB)
32 00:59:03.977233 progress 45 % (2 MB)
33 00:59:03.978454 progress 50 % (2 MB)
34 00:59:03.979634 progress 55 % (2 MB)
35 00:59:03.980922 progress 60 % (2 MB)
36 00:59:03.982203 progress 65 % (2 MB)
37 00:59:03.983389 progress 70 % (3 MB)
38 00:59:03.984578 progress 75 % (3 MB)
39 00:59:03.985760 progress 80 % (3 MB)
40 00:59:03.987137 progress 85 % (3 MB)
41 00:59:03.988318 progress 90 % (4 MB)
42 00:59:03.989500 progress 95 % (4 MB)
43 00:59:03.990737 progress 100 % (4 MB)
44 00:59:03.990886 4 MB downloaded in 0.03 s (171.96 MB/s)
45 00:59:03.991030 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:59:03.991265 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:59:03.991355 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:59:03.991445 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:59:03.991572 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:59:03.991650 saving as /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/kernel/Image
52 00:59:03.991714 total size: 51532288 (49 MB)
53 00:59:03.991777 No compression specified
54 00:59:03.992797 progress 0 % (0 MB)
55 00:59:04.005622 progress 5 % (2 MB)
56 00:59:04.018491 progress 10 % (4 MB)
57 00:59:04.031481 progress 15 % (7 MB)
58 00:59:04.044695 progress 20 % (9 MB)
59 00:59:04.057903 progress 25 % (12 MB)
60 00:59:04.070688 progress 30 % (14 MB)
61 00:59:04.083724 progress 35 % (17 MB)
62 00:59:04.096701 progress 40 % (19 MB)
63 00:59:04.109378 progress 45 % (22 MB)
64 00:59:04.122182 progress 50 % (24 MB)
65 00:59:04.135142 progress 55 % (27 MB)
66 00:59:04.148120 progress 60 % (29 MB)
67 00:59:04.161128 progress 65 % (31 MB)
68 00:59:04.173899 progress 70 % (34 MB)
69 00:59:04.186933 progress 75 % (36 MB)
70 00:59:04.199921 progress 80 % (39 MB)
71 00:59:04.212711 progress 85 % (41 MB)
72 00:59:04.226721 progress 90 % (44 MB)
73 00:59:04.240621 progress 95 % (46 MB)
74 00:59:04.253305 progress 100 % (49 MB)
75 00:59:04.253524 49 MB downloaded in 0.26 s (187.72 MB/s)
76 00:59:04.253677 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:59:04.253913 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:59:04.254013 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:59:04.254102 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:59:04.254239 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:59:04.254310 saving as /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/dtb/mt8192-asurada-spherion-r0.dtb
83 00:59:04.254373 total size: 47278 (0 MB)
84 00:59:04.254437 No compression specified
85 00:59:04.255562 progress 69 % (0 MB)
86 00:59:04.255838 progress 100 % (0 MB)
87 00:59:04.255995 0 MB downloaded in 0.00 s (27.85 MB/s)
88 00:59:04.256121 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:59:04.256352 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:59:04.256447 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:59:04.256533 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:59:04.256644 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 00:59:04.256714 saving as /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/nfsrootfs/full.rootfs.tar
95 00:59:04.256776 total size: 200813988 (191 MB)
96 00:59:04.256840 Using unxz to decompress xz
97 00:59:04.260364 progress 0 % (0 MB)
98 00:59:04.781263 progress 5 % (9 MB)
99 00:59:05.288340 progress 10 % (19 MB)
100 00:59:05.861111 progress 15 % (28 MB)
101 00:59:06.228311 progress 20 % (38 MB)
102 00:59:06.549257 progress 25 % (47 MB)
103 00:59:07.128741 progress 30 % (57 MB)
104 00:59:07.673211 progress 35 % (67 MB)
105 00:59:08.255216 progress 40 % (76 MB)
106 00:59:08.803473 progress 45 % (86 MB)
107 00:59:09.375712 progress 50 % (95 MB)
108 00:59:09.993676 progress 55 % (105 MB)
109 00:59:10.652570 progress 60 % (114 MB)
110 00:59:10.768908 progress 65 % (124 MB)
111 00:59:10.907268 progress 70 % (134 MB)
112 00:59:11.002885 progress 75 % (143 MB)
113 00:59:11.073433 progress 80 % (153 MB)
114 00:59:11.141674 progress 85 % (162 MB)
115 00:59:11.241731 progress 90 % (172 MB)
116 00:59:11.521447 progress 95 % (181 MB)
117 00:59:12.100414 progress 100 % (191 MB)
118 00:59:12.105718 191 MB downloaded in 7.85 s (24.40 MB/s)
119 00:59:12.105999 end: 1.4.1 http-download (duration 00:00:08) [common]
121 00:59:12.106263 end: 1.4 download-retry (duration 00:00:08) [common]
122 00:59:12.106356 start: 1.5 download-retry (timeout 00:09:52) [common]
123 00:59:12.106444 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 00:59:12.106602 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:59:12.106676 saving as /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/modules/modules.tar
126 00:59:12.106739 total size: 8625444 (8 MB)
127 00:59:12.106805 Using unxz to decompress xz
128 00:59:12.110613 progress 0 % (0 MB)
129 00:59:12.131648 progress 5 % (0 MB)
130 00:59:12.155040 progress 10 % (0 MB)
131 00:59:12.178394 progress 15 % (1 MB)
132 00:59:12.202096 progress 20 % (1 MB)
133 00:59:12.226605 progress 25 % (2 MB)
134 00:59:12.252300 progress 30 % (2 MB)
135 00:59:12.278368 progress 35 % (2 MB)
136 00:59:12.301864 progress 40 % (3 MB)
137 00:59:12.326345 progress 45 % (3 MB)
138 00:59:12.351588 progress 50 % (4 MB)
139 00:59:12.375794 progress 55 % (4 MB)
140 00:59:12.400746 progress 60 % (4 MB)
141 00:59:12.429031 progress 65 % (5 MB)
142 00:59:12.454326 progress 70 % (5 MB)
143 00:59:12.477813 progress 75 % (6 MB)
144 00:59:12.504588 progress 80 % (6 MB)
145 00:59:12.530547 progress 85 % (7 MB)
146 00:59:12.555449 progress 90 % (7 MB)
147 00:59:12.586492 progress 95 % (7 MB)
148 00:59:12.614290 progress 100 % (8 MB)
149 00:59:12.619377 8 MB downloaded in 0.51 s (16.05 MB/s)
150 00:59:12.619658 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:59:12.619927 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:59:12.620024 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 00:59:12.620124 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 00:59:15.810850 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9
156 00:59:15.811067 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 00:59:15.811174 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 00:59:15.811346 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u
159 00:59:15.811472 makedir: /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin
160 00:59:15.811570 makedir: /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/tests
161 00:59:15.811665 makedir: /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/results
162 00:59:15.811768 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-add-keys
163 00:59:15.811909 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-add-sources
164 00:59:15.812033 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-background-process-start
165 00:59:15.812153 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-background-process-stop
166 00:59:15.812276 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-common-functions
167 00:59:15.812394 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-echo-ipv4
168 00:59:15.812513 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-install-packages
169 00:59:15.812630 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-installed-packages
170 00:59:15.812747 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-os-build
171 00:59:15.812864 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-probe-channel
172 00:59:15.812980 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-probe-ip
173 00:59:15.813104 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-target-ip
174 00:59:15.813222 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-target-mac
175 00:59:15.813339 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-target-storage
176 00:59:15.813459 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-case
177 00:59:15.813579 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-event
178 00:59:15.813698 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-feedback
179 00:59:15.813817 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-raise
180 00:59:15.813942 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-reference
181 00:59:15.814099 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-runner
182 00:59:15.814217 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-set
183 00:59:15.814337 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-test-shell
184 00:59:15.814457 Updating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-add-keys (debian)
185 00:59:15.814610 Updating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-add-sources (debian)
186 00:59:15.814752 Updating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-install-packages (debian)
187 00:59:15.814885 Updating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-installed-packages (debian)
188 00:59:15.815016 Updating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/bin/lava-os-build (debian)
189 00:59:15.815136 Creating /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/environment
190 00:59:15.815235 LAVA metadata
191 00:59:15.815304 - LAVA_JOB_ID=12571077
192 00:59:15.815367 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:59:15.815470 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 00:59:15.815535 skipped lava-vland-overlay
195 00:59:15.815608 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:59:15.815688 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 00:59:15.815748 skipped lava-multinode-overlay
198 00:59:15.815819 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:59:15.815895 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 00:59:15.815968 Loading test definitions
201 00:59:15.816054 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 00:59:15.816124 Using /lava-12571077 at stage 0
203 00:59:15.816395 uuid=12571077_1.6.2.3.1 testdef=None
204 00:59:15.816495 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:59:15.816619 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 00:59:15.817069 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:59:15.817289 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 00:59:15.817848 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:59:15.818299 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 00:59:15.818828 runner path: /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/0/tests/0_timesync-off test_uuid 12571077_1.6.2.3.1
213 00:59:15.818980 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:59:15.819204 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 00:59:15.819278 Using /lava-12571077 at stage 0
217 00:59:15.819373 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:59:15.819452 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/0/tests/1_kselftest-dt'
219 00:59:18.170342 Running '/usr/bin/git checkout kernelci.org
220 00:59:18.286182 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 00:59:18.286868 uuid=12571077_1.6.2.3.5 testdef=None
222 00:59:18.287031 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 00:59:18.287320 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 00:59:18.288045 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:59:18.288272 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 00:59:18.289293 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:59:18.289525 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 00:59:18.290464 runner path: /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/0/tests/1_kselftest-dt test_uuid 12571077_1.6.2.3.5
232 00:59:18.290556 BOARD='mt8192-asurada-spherion-r0'
233 00:59:18.290621 BRANCH='cip'
234 00:59:18.290680 SKIPFILE='/dev/null'
235 00:59:18.290739 SKIP_INSTALL='True'
236 00:59:18.290797 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:59:18.290855 TST_CASENAME=''
238 00:59:18.290914 TST_CMDFILES='dt'
239 00:59:18.291098 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:59:18.291301 Creating lava-test-runner.conf files
242 00:59:18.291367 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571077/lava-overlay-_dd0uz9u/lava-12571077/0 for stage 0
243 00:59:18.291459 - 0_timesync-off
244 00:59:18.291527 - 1_kselftest-dt
245 00:59:18.291620 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 00:59:18.291706 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 00:59:25.631865 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 00:59:25.632033 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 00:59:25.632124 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:59:25.632227 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 00:59:25.632316 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 00:59:25.743078 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:59:25.743441 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 00:59:25.743550 extracting modules file /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9
255 00:59:25.949493 extracting modules file /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571077/extract-overlay-ramdisk-468w7nx3/ramdisk
256 00:59:26.152629 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:59:26.152804 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 00:59:26.152898 [common] Applying overlay to NFS
259 00:59:26.152970 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571077/compress-overlay-fh837tpw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9
260 00:59:27.037046 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:59:27.037218 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 00:59:27.037343 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:59:27.037438 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 00:59:27.037566 Building ramdisk /var/lib/lava/dispatcher/tmp/12571077/extract-overlay-ramdisk-468w7nx3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571077/extract-overlay-ramdisk-468w7nx3/ramdisk
265 00:59:27.425926 >> 119414 blocks
266 00:59:29.429178 rename /var/lib/lava/dispatcher/tmp/12571077/extract-overlay-ramdisk-468w7nx3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/ramdisk/ramdisk.cpio.gz
267 00:59:29.429598 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:59:29.429723 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 00:59:29.429825 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 00:59:29.429936 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/kernel/Image'
271 00:59:41.876045 Returned 0 in 12 seconds
272 00:59:41.976650 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/kernel/image.itb
273 00:59:43.396946 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:59:43.397329 output: Created: Fri Jan 19 00:59:43 2024
275 00:59:43.397438 output: Image 0 (kernel-1)
276 00:59:43.397548 output: Description:
277 00:59:43.397654 output: Created: Fri Jan 19 00:59:43 2024
278 00:59:43.397764 output: Type: Kernel Image
279 00:59:43.397868 output: Compression: lzma compressed
280 00:59:43.398016 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
281 00:59:43.398121 output: Architecture: AArch64
282 00:59:43.398224 output: OS: Linux
283 00:59:43.398325 output: Load Address: 0x00000000
284 00:59:43.398403 output: Entry Point: 0x00000000
285 00:59:43.398488 output: Hash algo: crc32
286 00:59:43.398588 output: Hash value: a52aa383
287 00:59:43.398666 output: Image 1 (fdt-1)
288 00:59:43.398765 output: Description: mt8192-asurada-spherion-r0
289 00:59:43.398861 output: Created: Fri Jan 19 00:59:43 2024
290 00:59:43.398959 output: Type: Flat Device Tree
291 00:59:43.399082 output: Compression: uncompressed
292 00:59:43.399187 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 00:59:43.399290 output: Architecture: AArch64
294 00:59:43.399391 output: Hash algo: crc32
295 00:59:43.399495 output: Hash value: cc4352de
296 00:59:43.399596 output: Image 2 (ramdisk-1)
297 00:59:43.399699 output: Description: unavailable
298 00:59:43.399801 output: Created: Fri Jan 19 00:59:43 2024
299 00:59:43.399903 output: Type: RAMDisk Image
300 00:59:43.400005 output: Compression: Unknown Compression
301 00:59:43.400106 output: Data Size: 17805959 Bytes = 17388.63 KiB = 16.98 MiB
302 00:59:43.400211 output: Architecture: AArch64
303 00:59:43.400312 output: OS: Linux
304 00:59:43.400415 output: Load Address: unavailable
305 00:59:43.400516 output: Entry Point: unavailable
306 00:59:43.400617 output: Hash algo: crc32
307 00:59:43.400721 output: Hash value: 32c6661f
308 00:59:43.400822 output: Default Configuration: 'conf-1'
309 00:59:43.400925 output: Configuration 0 (conf-1)
310 00:59:43.401026 output: Description: mt8192-asurada-spherion-r0
311 00:59:43.401127 output: Kernel: kernel-1
312 00:59:43.401227 output: Init Ramdisk: ramdisk-1
313 00:59:43.401328 output: FDT: fdt-1
314 00:59:43.401432 output: Loadables: kernel-1
315 00:59:43.401533 output:
316 00:59:43.401795 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 00:59:43.401956 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 00:59:43.402095 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 00:59:43.402213 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 00:59:43.402306 No LXC device requested
321 00:59:43.402431 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:59:43.402542 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 00:59:43.402663 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:59:43.402770 Checking files for TFTP limit of 4294967296 bytes.
325 00:59:43.403320 end: 1 tftp-deploy (duration 00:00:39) [common]
326 00:59:43.403442 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:59:43.403554 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:59:43.403701 substitutions:
329 00:59:43.403779 - {DTB}: 12571077/tftp-deploy-9bqywlm8/dtb/mt8192-asurada-spherion-r0.dtb
330 00:59:43.403863 - {INITRD}: 12571077/tftp-deploy-9bqywlm8/ramdisk/ramdisk.cpio.gz
331 00:59:43.403969 - {KERNEL}: 12571077/tftp-deploy-9bqywlm8/kernel/Image
332 00:59:43.404070 - {LAVA_MAC}: None
333 00:59:43.404172 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9
334 00:59:43.404271 - {NFS_SERVER_IP}: 192.168.201.1
335 00:59:43.404369 - {PRESEED_CONFIG}: None
336 00:59:43.404467 - {PRESEED_LOCAL}: None
337 00:59:43.404564 - {RAMDISK}: 12571077/tftp-deploy-9bqywlm8/ramdisk/ramdisk.cpio.gz
338 00:59:43.404665 - {ROOT_PART}: None
339 00:59:43.404761 - {ROOT}: None
340 00:59:43.404857 - {SERVER_IP}: 192.168.201.1
341 00:59:43.404953 - {TEE}: None
342 00:59:43.405049 Parsed boot commands:
343 00:59:43.405149 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:59:43.405391 Parsed boot commands: tftpboot 192.168.201.1 12571077/tftp-deploy-9bqywlm8/kernel/image.itb 12571077/tftp-deploy-9bqywlm8/kernel/cmdline
345 00:59:43.405518 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:59:43.405651 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:59:43.405785 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:59:43.405920 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:59:43.406048 Not connected, no need to disconnect.
350 00:59:43.406150 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:59:43.406275 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:59:43.406383 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 00:59:43.409925 Setting prompt string to ['lava-test: # ']
354 00:59:43.410318 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:59:43.410457 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:59:43.410626 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:59:43.410766 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:59:43.411096 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 00:59:48.545966 >> Command sent successfully.
360 00:59:48.548350 Returned 0 in 5 seconds
361 00:59:48.649136 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 00:59:48.651015 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 00:59:48.651671 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 00:59:48.652315 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:59:48.652799 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:59:48.653423 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:59:48.655225 [Enter `^Ec?' for help]
369 00:59:48.824313
370 00:59:48.824840
371 00:59:48.825211 F0: 102B 0000
372 00:59:48.825550
373 00:59:48.825865 F3: 1001 0000 [0200]
374 00:59:48.827509
375 00:59:48.827933 F3: 1001 0000
376 00:59:48.828276
377 00:59:48.828598 F7: 102D 0000
378 00:59:48.828907
379 00:59:48.831104 F1: 0000 0000
380 00:59:48.831537
381 00:59:48.831879 V0: 0000 0000 [0001]
382 00:59:48.832201
383 00:59:48.834181 00: 0007 8000
384 00:59:48.834618
385 00:59:48.834973 01: 0000 0000
386 00:59:48.835304
387 00:59:48.837691 BP: 0C00 0209 [0000]
388 00:59:48.838144
389 00:59:48.838491 G0: 1182 0000
390 00:59:48.838809
391 00:59:48.841310 EC: 0000 0021 [4000]
392 00:59:48.841742
393 00:59:48.842112 S7: 0000 0000 [0000]
394 00:59:48.842436
395 00:59:48.844784 CC: 0000 0000 [0001]
396 00:59:48.845211
397 00:59:48.845553 T0: 0000 0040 [010F]
398 00:59:48.845884
399 00:59:48.846228 Jump to BL
400 00:59:48.846533
401 00:59:48.871081
402 00:59:48.871511
403 00:59:48.871851
404 00:59:48.877863 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 00:59:48.881566 ARM64: Exception handlers installed.
406 00:59:48.885102 ARM64: Testing exception
407 00:59:48.888678 ARM64: Done test exception
408 00:59:48.896024 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 00:59:48.905159 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 00:59:48.912377 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 00:59:48.922095 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 00:59:48.929018 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 00:59:48.938832 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 00:59:48.949341 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 00:59:48.955932 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 00:59:48.974026 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 00:59:48.977254 WDT: Last reset was cold boot
418 00:59:48.980612 SPI1(PAD0) initialized at 2873684 Hz
419 00:59:48.984250 SPI5(PAD0) initialized at 992727 Hz
420 00:59:48.987294 VBOOT: Loading verstage.
421 00:59:48.993930 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 00:59:48.997509 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 00:59:49.000917 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 00:59:49.004095 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 00:59:49.011364 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 00:59:49.018182 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 00:59:49.028933 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 00:59:49.029371
429 00:59:49.029719
430 00:59:49.039057 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 00:59:49.042394 ARM64: Exception handlers installed.
432 00:59:49.045845 ARM64: Testing exception
433 00:59:49.046377 ARM64: Done test exception
434 00:59:49.052166 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 00:59:49.055688 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 00:59:49.069758 Probing TPM: . done!
437 00:59:49.070215 TPM ready after 0 ms
438 00:59:49.077002 Connected to device vid:did:rid of 1ae0:0028:00
439 00:59:49.084030 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 00:59:49.141359 Initialized TPM device CR50 revision 0
441 00:59:49.152655 tlcl_send_startup: Startup return code is 0
442 00:59:49.153173 TPM: setup succeeded
443 00:59:49.164092 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 00:59:49.172853 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:59:49.182840 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 00:59:49.192609 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 00:59:49.195566 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 00:59:49.201382 in-header: 03 07 00 00 08 00 00 00
449 00:59:49.205159 in-data: aa e4 47 04 13 02 00 00
450 00:59:49.209078 Chrome EC: UHEPI supported
451 00:59:49.216439 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 00:59:49.220044 in-header: 03 ad 00 00 08 00 00 00
453 00:59:49.224048 in-data: 00 20 20 08 00 00 00 00
454 00:59:49.224311 Phase 1
455 00:59:49.228104 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 00:59:49.234996 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 00:59:49.238544 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 00:59:49.242595 Recovery requested (1009000e)
459 00:59:49.252087 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 00:59:49.257176 tlcl_extend: response is 0
461 00:59:49.266967 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 00:59:49.272522 tlcl_extend: response is 0
463 00:59:49.279590 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 00:59:49.299653 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 00:59:49.306910 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 00:59:49.307408
467 00:59:49.307795
468 00:59:49.317265 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 00:59:49.320201 ARM64: Exception handlers installed.
470 00:59:49.320685 ARM64: Testing exception
471 00:59:49.323802 ARM64: Done test exception
472 00:59:49.345316 pmic_efuse_setting: Set efuses in 11 msecs
473 00:59:49.348155 pmwrap_interface_init: Select PMIF_VLD_RDY
474 00:59:49.354847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 00:59:49.358726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 00:59:49.362023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 00:59:49.368499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 00:59:49.371956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 00:59:49.379688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 00:59:49.383794 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 00:59:49.387121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 00:59:49.391028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 00:59:49.398274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 00:59:49.402041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 00:59:49.405913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 00:59:49.409610 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 00:59:49.416411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 00:59:49.423228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 00:59:49.430349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 00:59:49.433641 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 00:59:49.440850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 00:59:49.444917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 00:59:49.451631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 00:59:49.455079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 00:59:49.462530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 00:59:49.468724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 00:59:49.472282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 00:59:49.478825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 00:59:49.485456 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 00:59:49.488771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 00:59:49.495526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 00:59:49.498706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 00:59:49.501924 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 00:59:49.508863 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 00:59:49.512676 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 00:59:49.519411 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 00:59:49.522687 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 00:59:49.529578 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 00:59:49.532078 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 00:59:49.539550 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 00:59:49.542207 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 00:59:49.549394 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 00:59:49.552714 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 00:59:49.556470 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 00:59:49.559846 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 00:59:49.566878 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 00:59:49.570176 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 00:59:49.573635 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 00:59:49.579804 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 00:59:49.583382 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 00:59:49.586924 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 00:59:49.589831 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 00:59:49.596629 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 00:59:49.599879 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 00:59:49.607339 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 00:59:49.616666 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 00:59:49.619756 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 00:59:49.630285 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 00:59:49.636659 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 00:59:49.640213 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 00:59:49.646607 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:59:49.650523 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 00:59:49.657454 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x3a
534 00:59:49.663912 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 00:59:49.667391 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 00:59:49.670781 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 00:59:49.681791 [RTC]rtc_get_frequency_meter,154: input=15, output=772
538 00:59:49.691821 [RTC]rtc_get_frequency_meter,154: input=23, output=958
539 00:59:49.700994 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 00:59:49.710036 [RTC]rtc_get_frequency_meter,154: input=17, output=816
541 00:59:49.719618 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 00:59:49.723141 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 00:59:49.729967 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 00:59:49.732860 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
545 00:59:49.736396 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 00:59:49.740311 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
547 00:59:49.744079 ADC[4]: Raw value=903245 ID=7
548 00:59:49.748145 ADC[3]: Raw value=213179 ID=1
549 00:59:49.748418 RAM Code: 0x71
550 00:59:49.751730 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 00:59:49.759504 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 00:59:49.767472 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 00:59:49.771519 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 00:59:49.774897 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 00:59:49.778553 in-header: 03 07 00 00 08 00 00 00
556 00:59:49.782555 in-data: aa e4 47 04 13 02 00 00
557 00:59:49.786187 Chrome EC: UHEPI supported
558 00:59:49.793234 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 00:59:49.796944 in-header: 03 ed 00 00 08 00 00 00
560 00:59:49.800864 in-data: 80 20 60 08 00 00 00 00
561 00:59:49.803768 MRC: failed to locate region type 0.
562 00:59:49.810747 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 00:59:49.811237 DRAM-K: Running full calibration
564 00:59:49.817448 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 00:59:49.820535 header.status = 0x0
566 00:59:49.823917 header.version = 0x6 (expected: 0x6)
567 00:59:49.827590 header.size = 0xd00 (expected: 0xd00)
568 00:59:49.828083 header.flags = 0x0
569 00:59:49.834284 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 00:59:49.853128 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
571 00:59:49.859875 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 00:59:49.863466 dram_init: ddr_geometry: 2
573 00:59:49.863950 [EMI] MDL number = 2
574 00:59:49.867132 [EMI] Get MDL freq = 0
575 00:59:49.867719 dram_init: ddr_type: 0
576 00:59:49.870697 is_discrete_lpddr4: 1
577 00:59:49.874854 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 00:59:49.875533
579 00:59:49.875920
580 00:59:49.878194 [Bian_co] ETT version 0.0.0.1
581 00:59:49.881780 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 00:59:49.882292
583 00:59:49.885252 dramc_set_vcore_voltage set vcore to 650000
584 00:59:49.888508 Read voltage for 800, 4
585 00:59:49.888993 Vio18 = 0
586 00:59:49.889381 Vcore = 650000
587 00:59:49.892155 Vdram = 0
588 00:59:49.892637 Vddq = 0
589 00:59:49.893029 Vmddr = 0
590 00:59:49.895764 dram_init: config_dvfs: 1
591 00:59:49.898934 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 00:59:49.905628 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 00:59:49.909102 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 00:59:49.912127 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 00:59:49.915520 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 00:59:49.921796 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 00:59:49.922426 MEM_TYPE=3, freq_sel=18
598 00:59:49.925632 sv_algorithm_assistance_LP4_1600
599 00:59:49.928738 ============ PULL DRAM RESETB DOWN ============
600 00:59:49.935372 ========== PULL DRAM RESETB DOWN end =========
601 00:59:49.938519 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 00:59:49.942571 ===================================
603 00:59:49.945458 LPDDR4 DRAM CONFIGURATION
604 00:59:49.948697 ===================================
605 00:59:49.949212 EX_ROW_EN[0] = 0x0
606 00:59:49.952330 EX_ROW_EN[1] = 0x0
607 00:59:49.952818 LP4Y_EN = 0x0
608 00:59:49.955467 WORK_FSP = 0x0
609 00:59:49.955953 WL = 0x2
610 00:59:49.959474 RL = 0x2
611 00:59:49.960150 BL = 0x2
612 00:59:49.962005 RPST = 0x0
613 00:59:49.962489 RD_PRE = 0x0
614 00:59:49.965653 WR_PRE = 0x1
615 00:59:49.968768 WR_PST = 0x0
616 00:59:49.969358 DBI_WR = 0x0
617 00:59:49.971951 DBI_RD = 0x0
618 00:59:49.972435 OTF = 0x1
619 00:59:49.975516 ===================================
620 00:59:49.978716 ===================================
621 00:59:49.979205 ANA top config
622 00:59:49.982284 ===================================
623 00:59:49.985280 DLL_ASYNC_EN = 0
624 00:59:49.989154 ALL_SLAVE_EN = 1
625 00:59:49.992913 NEW_RANK_MODE = 1
626 00:59:49.995318 DLL_IDLE_MODE = 1
627 00:59:49.995798 LP45_APHY_COMB_EN = 1
628 00:59:49.999004 TX_ODT_DIS = 1
629 00:59:50.002108 NEW_8X_MODE = 1
630 00:59:50.005835 ===================================
631 00:59:50.008970 ===================================
632 00:59:50.012647 data_rate = 1600
633 00:59:50.015476 CKR = 1
634 00:59:50.015961 DQ_P2S_RATIO = 8
635 00:59:50.019364 ===================================
636 00:59:50.022161 CA_P2S_RATIO = 8
637 00:59:50.025533 DQ_CA_OPEN = 0
638 00:59:50.028833 DQ_SEMI_OPEN = 0
639 00:59:50.032227 CA_SEMI_OPEN = 0
640 00:59:50.032808 CA_FULL_RATE = 0
641 00:59:50.035433 DQ_CKDIV4_EN = 1
642 00:59:50.038694 CA_CKDIV4_EN = 1
643 00:59:50.042121 CA_PREDIV_EN = 0
644 00:59:50.045927 PH8_DLY = 0
645 00:59:50.049144 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 00:59:50.049727 DQ_AAMCK_DIV = 4
647 00:59:50.051952 CA_AAMCK_DIV = 4
648 00:59:50.055703 CA_ADMCK_DIV = 4
649 00:59:50.058936 DQ_TRACK_CA_EN = 0
650 00:59:50.061893 CA_PICK = 800
651 00:59:50.065663 CA_MCKIO = 800
652 00:59:50.069180 MCKIO_SEMI = 0
653 00:59:50.069678 PLL_FREQ = 3068
654 00:59:50.072573 DQ_UI_PI_RATIO = 32
655 00:59:50.075927 CA_UI_PI_RATIO = 0
656 00:59:50.078914 ===================================
657 00:59:50.082000 ===================================
658 00:59:50.085518 memory_type:LPDDR4
659 00:59:50.086038 GP_NUM : 10
660 00:59:50.089217 SRAM_EN : 1
661 00:59:50.092342 MD32_EN : 0
662 00:59:50.096382 ===================================
663 00:59:50.097014 [ANA_INIT] >>>>>>>>>>>>>>
664 00:59:50.099961 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 00:59:50.103442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 00:59:50.107743 ===================================
667 00:59:50.108366 data_rate = 1600,PCW = 0X7600
668 00:59:50.110886 ===================================
669 00:59:50.115073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 00:59:50.122749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 00:59:50.126477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 00:59:50.130303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 00:59:50.133292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 00:59:50.136840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 00:59:50.140210 [ANA_INIT] flow start
676 00:59:50.143156 [ANA_INIT] PLL >>>>>>>>
677 00:59:50.143653 [ANA_INIT] PLL <<<<<<<<
678 00:59:50.146767 [ANA_INIT] MIDPI >>>>>>>>
679 00:59:50.149888 [ANA_INIT] MIDPI <<<<<<<<
680 00:59:50.153422 [ANA_INIT] DLL >>>>>>>>
681 00:59:50.154063 [ANA_INIT] flow end
682 00:59:50.156695 ============ LP4 DIFF to SE enter ============
683 00:59:50.163470 ============ LP4 DIFF to SE exit ============
684 00:59:50.164095 [ANA_INIT] <<<<<<<<<<<<<
685 00:59:50.166486 [Flow] Enable top DCM control >>>>>
686 00:59:50.169847 [Flow] Enable top DCM control <<<<<
687 00:59:50.173171 Enable DLL master slave shuffle
688 00:59:50.179943 ==============================================================
689 00:59:50.180546 Gating Mode config
690 00:59:50.186696 ==============================================================
691 00:59:50.190086 Config description:
692 00:59:50.197140 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 00:59:50.204161 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 00:59:50.208146 SELPH_MODE 0: By rank 1: By Phase
695 00:59:50.215432 ==============================================================
696 00:59:50.219091 GAT_TRACK_EN = 1
697 00:59:50.222781 RX_GATING_MODE = 2
698 00:59:50.226097 RX_GATING_TRACK_MODE = 2
699 00:59:50.226682 SELPH_MODE = 1
700 00:59:50.229739 PICG_EARLY_EN = 1
701 00:59:50.233237 VALID_LAT_VALUE = 1
702 00:59:50.240675 ==============================================================
703 00:59:50.241266 Enter into Gating configuration >>>>
704 00:59:50.244629 Exit from Gating configuration <<<<
705 00:59:50.247498 Enter into DVFS_PRE_config >>>>>
706 00:59:50.258540 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 00:59:50.262554 Exit from DVFS_PRE_config <<<<<
708 00:59:50.266253 Enter into PICG configuration >>>>
709 00:59:50.270011 Exit from PICG configuration <<<<
710 00:59:50.273298 [RX_INPUT] configuration >>>>>
711 00:59:50.273778 [RX_INPUT] configuration <<<<<
712 00:59:50.281107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 00:59:50.284460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 00:59:50.292170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 00:59:50.295843 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 00:59:50.303913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 00:59:50.311562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 00:59:50.314799 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 00:59:50.318518 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 00:59:50.322727 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 00:59:50.326367 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 00:59:50.329982 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 00:59:50.333411 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 00:59:50.336768 ===================================
725 00:59:50.340999 LPDDR4 DRAM CONFIGURATION
726 00:59:50.344317 ===================================
727 00:59:50.344849 EX_ROW_EN[0] = 0x0
728 00:59:50.348187 EX_ROW_EN[1] = 0x0
729 00:59:50.348674 LP4Y_EN = 0x0
730 00:59:50.351952 WORK_FSP = 0x0
731 00:59:50.352461 WL = 0x2
732 00:59:50.355572 RL = 0x2
733 00:59:50.356083 BL = 0x2
734 00:59:50.359779 RPST = 0x0
735 00:59:50.360376 RD_PRE = 0x0
736 00:59:50.363248 WR_PRE = 0x1
737 00:59:50.363737 WR_PST = 0x0
738 00:59:50.364127 DBI_WR = 0x0
739 00:59:50.366668 DBI_RD = 0x0
740 00:59:50.367208 OTF = 0x1
741 00:59:50.370528 ===================================
742 00:59:50.374247 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 00:59:50.378560 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 00:59:50.385188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 00:59:50.389216 ===================================
746 00:59:50.389861 LPDDR4 DRAM CONFIGURATION
747 00:59:50.393036 ===================================
748 00:59:50.396238 EX_ROW_EN[0] = 0x10
749 00:59:50.396903 EX_ROW_EN[1] = 0x0
750 00:59:50.400289 LP4Y_EN = 0x0
751 00:59:50.400795 WORK_FSP = 0x0
752 00:59:50.403968 WL = 0x2
753 00:59:50.404452 RL = 0x2
754 00:59:50.407890 BL = 0x2
755 00:59:50.408374 RPST = 0x0
756 00:59:50.408762 RD_PRE = 0x0
757 00:59:50.411742 WR_PRE = 0x1
758 00:59:50.412228 WR_PST = 0x0
759 00:59:50.415358 DBI_WR = 0x0
760 00:59:50.415846 DBI_RD = 0x0
761 00:59:50.419574 OTF = 0x1
762 00:59:50.423371 ===================================
763 00:59:50.426895 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 00:59:50.431796 nWR fixed to 40
765 00:59:50.432384 [ModeRegInit_LP4] CH0 RK0
766 00:59:50.435719 [ModeRegInit_LP4] CH0 RK1
767 00:59:50.439200 [ModeRegInit_LP4] CH1 RK0
768 00:59:50.439943 [ModeRegInit_LP4] CH1 RK1
769 00:59:50.442597 match AC timing 13
770 00:59:50.446817 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 00:59:50.450331 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 00:59:50.454249 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 00:59:50.461777 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 00:59:50.466293 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 00:59:50.466898 [EMI DOE] emi_dcm 0
776 00:59:50.470241 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 00:59:50.470837 ==
778 00:59:50.473517 Dram Type= 6, Freq= 0, CH_0, rank 0
779 00:59:50.477191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:59:50.477791 ==
781 00:59:50.484706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 00:59:50.488170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 00:59:50.499378 [CA 0] Center 38 (7~69) winsize 63
784 00:59:50.503001 [CA 1] Center 38 (7~69) winsize 63
785 00:59:50.506486 [CA 2] Center 35 (5~66) winsize 62
786 00:59:50.509789 [CA 3] Center 35 (4~66) winsize 63
787 00:59:50.513270 [CA 4] Center 34 (4~65) winsize 62
788 00:59:50.516720 [CA 5] Center 34 (3~65) winsize 63
789 00:59:50.517304
790 00:59:50.519803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 00:59:50.520290
792 00:59:50.523273 [CATrainingPosCal] consider 1 rank data
793 00:59:50.526304 u2DelayCellTimex100 = 270/100 ps
794 00:59:50.530072 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
795 00:59:50.533194 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
796 00:59:50.536375 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
797 00:59:50.539884 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
798 00:59:50.542784 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
799 00:59:50.546105 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
800 00:59:50.546490
801 00:59:50.552816 CA PerBit enable=1, Macro0, CA PI delay=34
802 00:59:50.553075
803 00:59:50.555928 [CBTSetCACLKResult] CA Dly = 34
804 00:59:50.556130 CS Dly: 5 (0~36)
805 00:59:50.556292 ==
806 00:59:50.559958 Dram Type= 6, Freq= 0, CH_0, rank 1
807 00:59:50.563019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 00:59:50.563188 ==
809 00:59:50.569745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 00:59:50.575797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 00:59:50.584334 [CA 0] Center 38 (7~69) winsize 63
812 00:59:50.588259 [CA 1] Center 38 (7~69) winsize 63
813 00:59:50.591492 [CA 2] Center 36 (6~67) winsize 62
814 00:59:50.594413 [CA 3] Center 36 (5~67) winsize 63
815 00:59:50.598227 [CA 4] Center 35 (4~66) winsize 63
816 00:59:50.601025 [CA 5] Center 34 (4~65) winsize 62
817 00:59:50.601112
818 00:59:50.604593 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 00:59:50.604680
820 00:59:50.607610 [CATrainingPosCal] consider 2 rank data
821 00:59:50.611186 u2DelayCellTimex100 = 270/100 ps
822 00:59:50.614627 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 00:59:50.617899 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 00:59:50.624343 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 00:59:50.627691 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 00:59:50.631264 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 00:59:50.634813 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
828 00:59:50.635611
829 00:59:50.637905 CA PerBit enable=1, Macro0, CA PI delay=34
830 00:59:50.638431
831 00:59:50.641364 [CBTSetCACLKResult] CA Dly = 34
832 00:59:50.641869 CS Dly: 6 (0~38)
833 00:59:50.642315
834 00:59:50.644773 ----->DramcWriteLeveling(PI) begin...
835 00:59:50.648185 ==
836 00:59:50.651300 Dram Type= 6, Freq= 0, CH_0, rank 0
837 00:59:50.654756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 00:59:50.655248 ==
839 00:59:50.658166 Write leveling (Byte 0): 31 => 31
840 00:59:50.661291 Write leveling (Byte 1): 31 => 31
841 00:59:50.664566 DramcWriteLeveling(PI) end<-----
842 00:59:50.665053
843 00:59:50.665436 ==
844 00:59:50.667747 Dram Type= 6, Freq= 0, CH_0, rank 0
845 00:59:50.671538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 00:59:50.672035 ==
847 00:59:50.674405 [Gating] SW mode calibration
848 00:59:50.681367 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 00:59:50.685226 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 00:59:50.689040 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 00:59:50.696307 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 00:59:50.699293 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 00:59:50.702669 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 00:59:50.706279 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 00:59:50.713479 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:59:50.716844 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:59:50.720024 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:59:50.726992 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:59:50.730278 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:59:50.733835 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:59:50.740367 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:59:50.743544 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:59:50.747222 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:59:50.753688 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 00:59:50.757181 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 00:59:50.760094 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 00:59:50.767135 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 00:59:50.770263 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 00:59:50.773719 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 00:59:50.777297 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 00:59:50.783662 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 00:59:50.787013 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 00:59:50.790279 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 00:59:50.797250 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 00:59:50.800427 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
876 00:59:50.803374 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
877 00:59:50.810351 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
878 00:59:50.813869 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 00:59:50.817015 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 00:59:50.823675 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 00:59:50.826766 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 00:59:50.830121 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
883 00:59:50.837379 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
884 00:59:50.840533 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
885 00:59:50.843833 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 00:59:50.850510 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 00:59:50.853868 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 00:59:50.857670 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 00:59:50.860897 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 00:59:50.867235 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 00:59:50.871071 0 11 4 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
892 00:59:50.873857 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
893 00:59:50.881052 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:59:50.884323 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 00:59:50.887710 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 00:59:50.894159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 00:59:50.897623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 00:59:50.901051 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 00:59:50.907471 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 00:59:50.910736 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 00:59:50.914378 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 00:59:50.921149 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 00:59:50.924208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 00:59:50.927517 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 00:59:50.931122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 00:59:50.937150 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 00:59:50.941203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 00:59:50.943751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 00:59:50.950510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 00:59:50.954004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 00:59:50.957092 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 00:59:50.963939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 00:59:50.967578 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 00:59:50.970627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 00:59:50.977376 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 00:59:50.980592 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 00:59:50.983979 Total UI for P1: 0, mck2ui 16
918 00:59:50.987188 best dqsien dly found for B0: ( 0, 14, 2)
919 00:59:50.991223 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 00:59:50.994207 Total UI for P1: 0, mck2ui 16
921 00:59:50.997339 best dqsien dly found for B1: ( 0, 14, 8)
922 00:59:51.000828 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
923 00:59:51.004550 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 00:59:51.004641
925 00:59:51.007528 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
926 00:59:51.014208 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 00:59:51.014313 [Gating] SW calibration Done
928 00:59:51.014398 ==
929 00:59:51.017135 Dram Type= 6, Freq= 0, CH_0, rank 0
930 00:59:51.023929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 00:59:51.024055 ==
932 00:59:51.024155 RX Vref Scan: 0
933 00:59:51.024247
934 00:59:51.027317 RX Vref 0 -> 0, step: 1
935 00:59:51.027441
936 00:59:51.030659 RX Delay -130 -> 252, step: 16
937 00:59:51.034228 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 00:59:51.037076 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 00:59:51.040481 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 00:59:51.047305 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 00:59:51.050626 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 00:59:51.054237 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 00:59:51.057590 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 00:59:51.061531 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 00:59:51.064745 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 00:59:51.070997 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 00:59:51.074662 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 00:59:51.078032 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 00:59:51.081174 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 00:59:51.087562 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 00:59:51.091027 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 00:59:51.094784 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 00:59:51.095368 ==
954 00:59:51.097993 Dram Type= 6, Freq= 0, CH_0, rank 0
955 00:59:51.101145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 00:59:51.101624 ==
957 00:59:51.104567 DQS Delay:
958 00:59:51.105037 DQS0 = 0, DQS1 = 0
959 00:59:51.105416 DQM Delay:
960 00:59:51.107666 DQM0 = 91, DQM1 = 79
961 00:59:51.108138 DQ Delay:
962 00:59:51.111536 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
963 00:59:51.114429 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 00:59:51.118380 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 00:59:51.121315 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
966 00:59:51.121833
967 00:59:51.122257
968 00:59:51.122611 ==
969 00:59:51.124202 Dram Type= 6, Freq= 0, CH_0, rank 0
970 00:59:51.132008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 00:59:51.132597 ==
972 00:59:51.132981
973 00:59:51.133335
974 00:59:51.133671 TX Vref Scan disable
975 00:59:51.134862 == TX Byte 0 ==
976 00:59:51.138337 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 00:59:51.141634 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 00:59:51.144862 == TX Byte 1 ==
979 00:59:51.148195 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 00:59:51.151539 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 00:59:51.155093 ==
982 00:59:51.158580 Dram Type= 6, Freq= 0, CH_0, rank 0
983 00:59:51.161650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 00:59:51.162284 ==
985 00:59:51.174114 TX Vref=22, minBit 11, minWin=26, winSum=442
986 00:59:51.177518 TX Vref=24, minBit 8, minWin=27, winSum=444
987 00:59:51.180763 TX Vref=26, minBit 8, minWin=27, winSum=449
988 00:59:51.184494 TX Vref=28, minBit 8, minWin=27, winSum=450
989 00:59:51.187601 TX Vref=30, minBit 9, minWin=27, winSum=456
990 00:59:51.190460 TX Vref=32, minBit 5, minWin=28, winSum=455
991 00:59:51.197178 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 32
992 00:59:51.197765
993 00:59:51.200841 Final TX Range 1 Vref 32
994 00:59:51.201426
995 00:59:51.201810 ==
996 00:59:51.204175 Dram Type= 6, Freq= 0, CH_0, rank 0
997 00:59:51.207365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 00:59:51.207844 ==
999 00:59:51.208226
1000 00:59:51.208580
1001 00:59:51.210402 TX Vref Scan disable
1002 00:59:51.214235 == TX Byte 0 ==
1003 00:59:51.217754 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1004 00:59:51.220839 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1005 00:59:51.223695 == TX Byte 1 ==
1006 00:59:51.227296 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 00:59:51.230988 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 00:59:51.231563
1009 00:59:51.233912 [DATLAT]
1010 00:59:51.234417 Freq=800, CH0 RK0
1011 00:59:51.234803
1012 00:59:51.237219 DATLAT Default: 0xa
1013 00:59:51.237791 0, 0xFFFF, sum = 0
1014 00:59:51.240495 1, 0xFFFF, sum = 0
1015 00:59:51.240975 2, 0xFFFF, sum = 0
1016 00:59:51.244006 3, 0xFFFF, sum = 0
1017 00:59:51.244490 4, 0xFFFF, sum = 0
1018 00:59:51.246956 5, 0xFFFF, sum = 0
1019 00:59:51.247436 6, 0xFFFF, sum = 0
1020 00:59:51.250384 7, 0xFFFF, sum = 0
1021 00:59:51.250862 8, 0xFFFF, sum = 0
1022 00:59:51.253790 9, 0x0, sum = 1
1023 00:59:51.254311 10, 0x0, sum = 2
1024 00:59:51.257299 11, 0x0, sum = 3
1025 00:59:51.257903 12, 0x0, sum = 4
1026 00:59:51.260930 best_step = 10
1027 00:59:51.261493
1028 00:59:51.261867 ==
1029 00:59:51.264155 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 00:59:51.267292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 00:59:51.267860 ==
1032 00:59:51.270775 RX Vref Scan: 1
1033 00:59:51.271343
1034 00:59:51.271721 Set Vref Range= 32 -> 127
1035 00:59:51.272076
1036 00:59:51.273873 RX Vref 32 -> 127, step: 1
1037 00:59:51.274485
1038 00:59:51.277505 RX Delay -95 -> 252, step: 8
1039 00:59:51.278217
1040 00:59:51.280762 Set Vref, RX VrefLevel [Byte0]: 32
1041 00:59:51.284118 [Byte1]: 32
1042 00:59:51.284588
1043 00:59:51.287547 Set Vref, RX VrefLevel [Byte0]: 33
1044 00:59:51.290502 [Byte1]: 33
1045 00:59:51.294394
1046 00:59:51.294969 Set Vref, RX VrefLevel [Byte0]: 34
1047 00:59:51.297645 [Byte1]: 34
1048 00:59:51.302019
1049 00:59:51.302597 Set Vref, RX VrefLevel [Byte0]: 35
1050 00:59:51.305224 [Byte1]: 35
1051 00:59:51.309247
1052 00:59:51.309818 Set Vref, RX VrefLevel [Byte0]: 36
1053 00:59:51.312601 [Byte1]: 36
1054 00:59:51.317232
1055 00:59:51.317820 Set Vref, RX VrefLevel [Byte0]: 37
1056 00:59:51.320367 [Byte1]: 37
1057 00:59:51.325615
1058 00:59:51.326236 Set Vref, RX VrefLevel [Byte0]: 38
1059 00:59:51.328510 [Byte1]: 38
1060 00:59:51.332154
1061 00:59:51.332628 Set Vref, RX VrefLevel [Byte0]: 39
1062 00:59:51.335508 [Byte1]: 39
1063 00:59:51.339755
1064 00:59:51.340248 Set Vref, RX VrefLevel [Byte0]: 40
1065 00:59:51.343202 [Byte1]: 40
1066 00:59:51.347366
1067 00:59:51.347841 Set Vref, RX VrefLevel [Byte0]: 41
1068 00:59:51.350752 [Byte1]: 41
1069 00:59:51.354930
1070 00:59:51.355686 Set Vref, RX VrefLevel [Byte0]: 42
1071 00:59:51.358204 [Byte1]: 42
1072 00:59:51.362986
1073 00:59:51.363503 Set Vref, RX VrefLevel [Byte0]: 43
1074 00:59:51.366154 [Byte1]: 43
1075 00:59:51.369916
1076 00:59:51.370072 Set Vref, RX VrefLevel [Byte0]: 44
1077 00:59:51.373242 [Byte1]: 44
1078 00:59:51.377511
1079 00:59:51.377623 Set Vref, RX VrefLevel [Byte0]: 45
1080 00:59:51.380468 [Byte1]: 45
1081 00:59:51.385158
1082 00:59:51.385295 Set Vref, RX VrefLevel [Byte0]: 46
1083 00:59:51.388126 [Byte1]: 46
1084 00:59:51.392498
1085 00:59:51.392620 Set Vref, RX VrefLevel [Byte0]: 47
1086 00:59:51.395490 [Byte1]: 47
1087 00:59:51.399848
1088 00:59:51.400032 Set Vref, RX VrefLevel [Byte0]: 48
1089 00:59:51.403282 [Byte1]: 48
1090 00:59:51.407388
1091 00:59:51.407500 Set Vref, RX VrefLevel [Byte0]: 49
1092 00:59:51.410646 [Byte1]: 49
1093 00:59:51.415505
1094 00:59:51.415588 Set Vref, RX VrefLevel [Byte0]: 50
1095 00:59:51.418436 [Byte1]: 50
1096 00:59:51.422588
1097 00:59:51.422672 Set Vref, RX VrefLevel [Byte0]: 51
1098 00:59:51.425822 [Byte1]: 51
1099 00:59:51.430102
1100 00:59:51.430215 Set Vref, RX VrefLevel [Byte0]: 52
1101 00:59:51.434183 [Byte1]: 52
1102 00:59:51.437785
1103 00:59:51.437868 Set Vref, RX VrefLevel [Byte0]: 53
1104 00:59:51.441341 [Byte1]: 53
1105 00:59:51.445382
1106 00:59:51.445493 Set Vref, RX VrefLevel [Byte0]: 54
1107 00:59:51.448908 [Byte1]: 54
1108 00:59:51.452838
1109 00:59:51.452949 Set Vref, RX VrefLevel [Byte0]: 55
1110 00:59:51.456408 [Byte1]: 55
1111 00:59:51.460441
1112 00:59:51.460526 Set Vref, RX VrefLevel [Byte0]: 56
1113 00:59:51.464131 [Byte1]: 56
1114 00:59:51.468144
1115 00:59:51.468223 Set Vref, RX VrefLevel [Byte0]: 57
1116 00:59:51.471784 [Byte1]: 57
1117 00:59:51.475779
1118 00:59:51.475858 Set Vref, RX VrefLevel [Byte0]: 58
1119 00:59:51.479160 [Byte1]: 58
1120 00:59:51.483570
1121 00:59:51.483647 Set Vref, RX VrefLevel [Byte0]: 59
1122 00:59:51.486840 [Byte1]: 59
1123 00:59:51.491020
1124 00:59:51.491099 Set Vref, RX VrefLevel [Byte0]: 60
1125 00:59:51.494721 [Byte1]: 60
1126 00:59:51.499298
1127 00:59:51.499720 Set Vref, RX VrefLevel [Byte0]: 61
1128 00:59:51.502420 [Byte1]: 61
1129 00:59:51.506810
1130 00:59:51.507468 Set Vref, RX VrefLevel [Byte0]: 62
1131 00:59:51.510251 [Byte1]: 62
1132 00:59:51.514545
1133 00:59:51.515164 Set Vref, RX VrefLevel [Byte0]: 63
1134 00:59:51.517596 [Byte1]: 63
1135 00:59:51.522212
1136 00:59:51.522874 Set Vref, RX VrefLevel [Byte0]: 64
1137 00:59:51.525043 [Byte1]: 64
1138 00:59:51.529269
1139 00:59:51.529890 Set Vref, RX VrefLevel [Byte0]: 65
1140 00:59:51.532485 [Byte1]: 65
1141 00:59:51.536996
1142 00:59:51.537443 Set Vref, RX VrefLevel [Byte0]: 66
1143 00:59:51.540130 [Byte1]: 66
1144 00:59:51.544249
1145 00:59:51.544342 Set Vref, RX VrefLevel [Byte0]: 67
1146 00:59:51.547560 [Byte1]: 67
1147 00:59:51.551761
1148 00:59:51.551843 Set Vref, RX VrefLevel [Byte0]: 68
1149 00:59:51.555507 [Byte1]: 68
1150 00:59:51.559680
1151 00:59:51.559757 Set Vref, RX VrefLevel [Byte0]: 69
1152 00:59:51.562793 [Byte1]: 69
1153 00:59:51.566931
1154 00:59:51.567018 Set Vref, RX VrefLevel [Byte0]: 70
1155 00:59:51.570460 [Byte1]: 70
1156 00:59:51.574625
1157 00:59:51.574697 Set Vref, RX VrefLevel [Byte0]: 71
1158 00:59:51.577922 [Byte1]: 71
1159 00:59:51.582548
1160 00:59:51.582631 Set Vref, RX VrefLevel [Byte0]: 72
1161 00:59:51.585560 [Byte1]: 72
1162 00:59:51.589964
1163 00:59:51.590093 Set Vref, RX VrefLevel [Byte0]: 73
1164 00:59:51.593097 [Byte1]: 73
1165 00:59:51.597521
1166 00:59:51.597646 Set Vref, RX VrefLevel [Byte0]: 74
1167 00:59:51.600956 [Byte1]: 74
1168 00:59:51.605173
1169 00:59:51.605309 Set Vref, RX VrefLevel [Byte0]: 75
1170 00:59:51.608240 [Byte1]: 75
1171 00:59:51.613459
1172 00:59:51.613594 Set Vref, RX VrefLevel [Byte0]: 76
1173 00:59:51.616186 [Byte1]: 76
1174 00:59:51.620321
1175 00:59:51.620514 Final RX Vref Byte 0 = 62 to rank0
1176 00:59:51.623827 Final RX Vref Byte 1 = 62 to rank0
1177 00:59:51.627001 Final RX Vref Byte 0 = 62 to rank1
1178 00:59:51.630272 Final RX Vref Byte 1 = 62 to rank1==
1179 00:59:51.634114 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 00:59:51.640301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 00:59:51.640752 ==
1182 00:59:51.641124 DQS Delay:
1183 00:59:51.641493 DQS0 = 0, DQS1 = 0
1184 00:59:51.643623 DQM Delay:
1185 00:59:51.643941 DQM0 = 93, DQM1 = 83
1186 00:59:51.647156 DQ Delay:
1187 00:59:51.650537 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 00:59:51.653873 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1189 00:59:51.654211 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1190 00:59:51.660705 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1191 00:59:51.661098
1192 00:59:51.661408
1193 00:59:51.667912 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1194 00:59:51.670898 CH0 RK0: MR19=606, MR18=3D38
1195 00:59:51.677620 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1196 00:59:51.678202
1197 00:59:51.681320 ----->DramcWriteLeveling(PI) begin...
1198 00:59:51.681804 ==
1199 00:59:51.684398 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 00:59:51.687526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 00:59:51.688005 ==
1202 00:59:51.691221 Write leveling (Byte 0): 31 => 31
1203 00:59:51.694816 Write leveling (Byte 1): 30 => 30
1204 00:59:51.697823 DramcWriteLeveling(PI) end<-----
1205 00:59:51.698433
1206 00:59:51.698817 ==
1207 00:59:51.701193 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 00:59:51.705177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 00:59:51.705747 ==
1210 00:59:51.707652 [Gating] SW mode calibration
1211 00:59:51.714726 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 00:59:51.721404 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 00:59:51.724703 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 00:59:51.728020 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1215 00:59:51.734895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1216 00:59:51.737745 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:59:51.741237 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:59:51.747196 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:59:51.791128 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:59:51.791409 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:59:51.791486 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:59:51.791918 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:59:51.792170 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:59:51.792426 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:59:51.792493 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:59:51.792732 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:59:51.793203 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:59:51.793608 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 00:59:51.836018 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 00:59:51.836611 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1231 00:59:51.836997 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:59:51.837718 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:59:51.838132 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:59:51.838481 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:59:51.838813 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:59:51.839135 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:59:51.839514 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 00:59:51.839849 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1239 00:59:51.859019 0 9 8 | B1->B0 | 2c2c 3433 | 0 1 | (0 0) (1 1)
1240 00:59:51.859728 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 00:59:51.860731 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 00:59:51.861370 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 00:59:51.861976 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 00:59:51.862822 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 00:59:51.866478 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 00:59:51.870011 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
1247 00:59:51.872937 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1248 00:59:51.876265 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:59:51.883025 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:59:51.886173 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:59:51.889711 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:59:51.896144 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:59:51.899397 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 00:59:51.902729 0 11 4 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
1255 00:59:51.909706 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
1256 00:59:51.913144 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:59:51.916318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:59:51.923091 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 00:59:51.926719 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 00:59:51.930489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 00:59:51.933886 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 00:59:51.941499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 00:59:51.944765 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 00:59:51.948474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 00:59:51.951047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 00:59:51.958866 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 00:59:51.962414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:59:51.965532 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:59:51.968775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:59:51.975554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:59:51.979112 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:59:51.982060 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:59:51.988902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:59:51.992476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:59:51.995360 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:59:52.001888 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:59:52.005450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 00:59:52.008749 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1279 00:59:52.015578 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 00:59:52.015811 Total UI for P1: 0, mck2ui 16
1281 00:59:52.022162 best dqsien dly found for B0: ( 0, 14, 4)
1282 00:59:52.022245 Total UI for P1: 0, mck2ui 16
1283 00:59:52.024960 best dqsien dly found for B1: ( 0, 14, 4)
1284 00:59:52.032218 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1285 00:59:52.034920 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1286 00:59:52.035004
1287 00:59:52.038845 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1288 00:59:52.041799 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1289 00:59:52.045204 [Gating] SW calibration Done
1290 00:59:52.045288 ==
1291 00:59:52.048647 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 00:59:52.051550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 00:59:52.051634 ==
1294 00:59:52.051701 RX Vref Scan: 0
1295 00:59:52.055351
1296 00:59:52.055434 RX Vref 0 -> 0, step: 1
1297 00:59:52.055502
1298 00:59:52.058335 RX Delay -130 -> 252, step: 16
1299 00:59:52.061877 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1300 00:59:52.065762 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1301 00:59:52.071745 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1302 00:59:52.075245 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1303 00:59:52.078719 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1304 00:59:52.082128 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1305 00:59:52.085216 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1306 00:59:52.092123 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1307 00:59:52.095585 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1308 00:59:52.098832 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1309 00:59:52.101902 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1310 00:59:52.105461 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1311 00:59:52.111961 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1312 00:59:52.115086 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1313 00:59:52.118592 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1314 00:59:52.122257 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1315 00:59:52.122343 ==
1316 00:59:52.125125 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 00:59:52.131902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 00:59:52.132001 ==
1319 00:59:52.132079 DQS Delay:
1320 00:59:52.132151 DQS0 = 0, DQS1 = 0
1321 00:59:52.135274 DQM Delay:
1322 00:59:52.135380 DQM0 = 87, DQM1 = 79
1323 00:59:52.138746 DQ Delay:
1324 00:59:52.141758 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1325 00:59:52.141873 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1326 00:59:52.145407 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1327 00:59:52.151891 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1328 00:59:52.152007
1329 00:59:52.152098
1330 00:59:52.152184 ==
1331 00:59:52.155391 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:59:52.158752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:59:52.158867 ==
1334 00:59:52.158958
1335 00:59:52.159042
1336 00:59:52.161797 TX Vref Scan disable
1337 00:59:52.161911 == TX Byte 0 ==
1338 00:59:52.168510 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1339 00:59:52.172098 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1340 00:59:52.172213 == TX Byte 1 ==
1341 00:59:52.178848 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1342 00:59:52.181806 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1343 00:59:52.181952 ==
1344 00:59:52.185599 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 00:59:52.188806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 00:59:52.188923 ==
1347 00:59:52.202336 TX Vref=22, minBit 3, minWin=27, winSum=444
1348 00:59:52.205914 TX Vref=24, minBit 8, minWin=27, winSum=448
1349 00:59:52.209478 TX Vref=26, minBit 8, minWin=27, winSum=452
1350 00:59:52.212301 TX Vref=28, minBit 10, minWin=27, winSum=455
1351 00:59:52.215740 TX Vref=30, minBit 12, minWin=27, winSum=455
1352 00:59:52.222153 TX Vref=32, minBit 8, minWin=27, winSum=452
1353 00:59:52.225625 [TxChooseVref] Worse bit 10, Min win 27, Win sum 455, Final Vref 28
1354 00:59:52.225730
1355 00:59:52.228923 Final TX Range 1 Vref 28
1356 00:59:52.229026
1357 00:59:52.229140 ==
1358 00:59:52.232427 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 00:59:52.235701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 00:59:52.235803 ==
1361 00:59:52.239278
1362 00:59:52.239379
1363 00:59:52.239463 TX Vref Scan disable
1364 00:59:52.242694 == TX Byte 0 ==
1365 00:59:52.245834 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1366 00:59:52.249168 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1367 00:59:52.252648 == TX Byte 1 ==
1368 00:59:52.256410 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1369 00:59:52.259612 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1370 00:59:52.262858
1371 00:59:52.263067 [DATLAT]
1372 00:59:52.263210 Freq=800, CH0 RK1
1373 00:59:52.263321
1374 00:59:52.265873 DATLAT Default: 0xa
1375 00:59:52.266059 0, 0xFFFF, sum = 0
1376 00:59:52.269499 1, 0xFFFF, sum = 0
1377 00:59:52.269656 2, 0xFFFF, sum = 0
1378 00:59:52.272618 3, 0xFFFF, sum = 0
1379 00:59:52.272815 4, 0xFFFF, sum = 0
1380 00:59:52.275944 5, 0xFFFF, sum = 0
1381 00:59:52.276107 6, 0xFFFF, sum = 0
1382 00:59:52.279367 7, 0xFFFF, sum = 0
1383 00:59:52.282830 8, 0xFFFF, sum = 0
1384 00:59:52.282914 9, 0x0, sum = 1
1385 00:59:52.282982 10, 0x0, sum = 2
1386 00:59:52.285915 11, 0x0, sum = 3
1387 00:59:52.286049 12, 0x0, sum = 4
1388 00:59:52.289398 best_step = 10
1389 00:59:52.289777
1390 00:59:52.290236 ==
1391 00:59:52.292919 Dram Type= 6, Freq= 0, CH_0, rank 1
1392 00:59:52.296068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 00:59:52.296683 ==
1394 00:59:52.299700 RX Vref Scan: 0
1395 00:59:52.300195
1396 00:59:52.300776 RX Vref 0 -> 0, step: 1
1397 00:59:52.301238
1398 00:59:52.302748 RX Delay -79 -> 252, step: 8
1399 00:59:52.309674 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1400 00:59:52.312829 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1401 00:59:52.316070 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1402 00:59:52.319510 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1403 00:59:52.322945 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1404 00:59:52.328851 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1405 00:59:52.332389 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1406 00:59:52.335641 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1407 00:59:52.339179 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1408 00:59:52.342706 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1409 00:59:52.349055 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1410 00:59:52.352553 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1411 00:59:52.356068 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1412 00:59:52.359288 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1413 00:59:52.362720 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1414 00:59:52.369363 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1415 00:59:52.369447 ==
1416 00:59:52.372418 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 00:59:52.376514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 00:59:52.376601 ==
1419 00:59:52.376666 DQS Delay:
1420 00:59:52.379420 DQS0 = 0, DQS1 = 0
1421 00:59:52.379503 DQM Delay:
1422 00:59:52.382960 DQM0 = 91, DQM1 = 81
1423 00:59:52.383043 DQ Delay:
1424 00:59:52.385834 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1425 00:59:52.389232 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1426 00:59:52.392690 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1427 00:59:52.395867 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1428 00:59:52.395963
1429 00:59:52.396030
1430 00:59:52.403359 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1431 00:59:52.406081 CH0 RK1: MR19=606, MR18=3E18
1432 00:59:52.412600 CH0_RK1: MR19=0x606, MR18=0x3E18, DQSOSC=394, MR23=63, INC=95, DEC=63
1433 00:59:52.416151 [RxdqsGatingPostProcess] freq 800
1434 00:59:52.422915 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1435 00:59:52.422999 Pre-setting of DQS Precalculation
1436 00:59:52.429660 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1437 00:59:52.429744 ==
1438 00:59:52.432550 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 00:59:52.436030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 00:59:52.436114 ==
1441 00:59:52.442895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1442 00:59:52.449176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1443 00:59:52.457719 [CA 0] Center 36 (6~67) winsize 62
1444 00:59:52.461256 [CA 1] Center 36 (6~67) winsize 62
1445 00:59:52.464241 [CA 2] Center 35 (5~65) winsize 61
1446 00:59:52.467569 [CA 3] Center 34 (4~65) winsize 62
1447 00:59:52.471386 [CA 4] Center 34 (4~65) winsize 62
1448 00:59:52.474256 [CA 5] Center 34 (3~65) winsize 63
1449 00:59:52.474342
1450 00:59:52.477733 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1451 00:59:52.477816
1452 00:59:52.480970 [CATrainingPosCal] consider 1 rank data
1453 00:59:52.484441 u2DelayCellTimex100 = 270/100 ps
1454 00:59:52.487686 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 00:59:52.491090 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 00:59:52.497526 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1457 00:59:52.501042 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 00:59:52.504784 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 00:59:52.507551 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1460 00:59:52.507648
1461 00:59:52.511043 CA PerBit enable=1, Macro0, CA PI delay=34
1462 00:59:52.511122
1463 00:59:52.514477 [CBTSetCACLKResult] CA Dly = 34
1464 00:59:52.514556 CS Dly: 5 (0~36)
1465 00:59:52.514653 ==
1466 00:59:52.517703 Dram Type= 6, Freq= 0, CH_1, rank 1
1467 00:59:52.524597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 00:59:52.524710 ==
1469 00:59:52.527779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1470 00:59:52.534246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1471 00:59:52.543473 [CA 0] Center 37 (6~68) winsize 63
1472 00:59:52.547109 [CA 1] Center 37 (6~68) winsize 63
1473 00:59:52.550377 [CA 2] Center 35 (4~66) winsize 63
1474 00:59:52.553600 [CA 3] Center 34 (4~65) winsize 62
1475 00:59:52.556948 [CA 4] Center 34 (4~65) winsize 62
1476 00:59:52.560913 [CA 5] Center 34 (4~64) winsize 61
1477 00:59:52.560997
1478 00:59:52.563722 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1479 00:59:52.563807
1480 00:59:52.567359 [CATrainingPosCal] consider 2 rank data
1481 00:59:52.570701 u2DelayCellTimex100 = 270/100 ps
1482 00:59:52.573961 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1483 00:59:52.576881 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 00:59:52.584068 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1485 00:59:52.587265 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 00:59:52.590690 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 00:59:52.594358 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1488 00:59:52.594447
1489 00:59:52.597665 CA PerBit enable=1, Macro0, CA PI delay=34
1490 00:59:52.597752
1491 00:59:52.601350 [CBTSetCACLKResult] CA Dly = 34
1492 00:59:52.601437 CS Dly: 6 (0~38)
1493 00:59:52.601526
1494 00:59:52.605007 ----->DramcWriteLeveling(PI) begin...
1495 00:59:52.605095 ==
1496 00:59:52.609098 Dram Type= 6, Freq= 0, CH_1, rank 0
1497 00:59:52.612813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1498 00:59:52.612930 ==
1499 00:59:52.616506 Write leveling (Byte 0): 26 => 26
1500 00:59:52.620344 Write leveling (Byte 1): 31 => 31
1501 00:59:52.623648 DramcWriteLeveling(PI) end<-----
1502 00:59:52.623736
1503 00:59:52.623823 ==
1504 00:59:52.627395 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 00:59:52.630780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 00:59:52.630865 ==
1507 00:59:52.634428 [Gating] SW mode calibration
1508 00:59:52.640683 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1509 00:59:52.644497 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1510 00:59:52.650900 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1511 00:59:52.654364 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1512 00:59:52.657752 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:59:52.664574 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:59:52.667486 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:59:52.670932 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:59:52.677670 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:59:52.680983 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:59:52.684521 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:59:52.687539 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:59:52.694068 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:59:52.697598 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:59:52.700953 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:59:52.707545 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:59:52.711161 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:59:52.714269 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 00:59:52.721031 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1527 00:59:52.724113 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1528 00:59:52.727781 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1529 00:59:52.734048 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:59:52.737528 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:59:52.740955 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:59:52.747750 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:59:52.751398 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:59:52.754491 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:59:52.758035 0 9 4 | B1->B0 | 2323 2929 | 1 1 | (1 1) (1 1)
1536 00:59:52.764538 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 00:59:52.768162 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 00:59:52.771122 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 00:59:52.777635 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 00:59:52.781288 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 00:59:52.784844 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 00:59:52.791249 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1543 00:59:52.794526 0 10 4 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
1544 00:59:52.797556 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 00:59:52.804327 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:59:52.807619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:59:52.811282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:59:52.818159 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:59:52.821354 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:59:52.824312 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1551 00:59:52.831109 0 11 4 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
1552 00:59:52.834534 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 00:59:52.838167 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 00:59:52.844917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:59:52.847854 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:59:52.851173 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 00:59:52.854491 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:59:52.861128 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:59:52.864621 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1560 00:59:52.868268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 00:59:52.874551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 00:59:52.877917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 00:59:52.881288 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 00:59:52.888028 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 00:59:52.891447 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:59:52.894715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:59:52.901545 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:59:52.904740 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:59:52.908333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:59:52.914691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:59:52.917816 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:59:52.921286 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:59:52.928055 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:59:52.931324 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1575 00:59:52.934783 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1576 00:59:52.940971 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 00:59:52.941086 Total UI for P1: 0, mck2ui 16
1578 00:59:52.944473 best dqsien dly found for B0: ( 0, 14, 2)
1579 00:59:52.947925 Total UI for P1: 0, mck2ui 16
1580 00:59:52.951122 best dqsien dly found for B1: ( 0, 14, 4)
1581 00:59:52.954521 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1582 00:59:52.961023 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1583 00:59:52.961190
1584 00:59:52.964950 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1585 00:59:52.967863 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 00:59:52.971269 [Gating] SW calibration Done
1587 00:59:52.971448 ==
1588 00:59:52.974769 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 00:59:52.978026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 00:59:52.978211 ==
1591 00:59:52.978335 RX Vref Scan: 0
1592 00:59:52.978442
1593 00:59:52.981354 RX Vref 0 -> 0, step: 1
1594 00:59:52.981553
1595 00:59:52.984918 RX Delay -130 -> 252, step: 16
1596 00:59:52.988149 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1597 00:59:52.991751 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1598 00:59:52.998192 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1599 00:59:53.001399 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1600 00:59:53.004744 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1601 00:59:53.008154 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1602 00:59:53.011759 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1603 00:59:53.018292 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1604 00:59:53.021828 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1605 00:59:53.025213 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1606 00:59:53.028577 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1607 00:59:53.031926 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1608 00:59:53.038603 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1609 00:59:53.041859 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1610 00:59:53.045495 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1611 00:59:53.048817 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1612 00:59:53.049329 ==
1613 00:59:53.051835 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 00:59:53.055051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 00:59:53.058837 ==
1616 00:59:53.059433 DQS Delay:
1617 00:59:53.059927 DQS0 = 0, DQS1 = 0
1618 00:59:53.062283 DQM Delay:
1619 00:59:53.062893 DQM0 = 89, DQM1 = 83
1620 00:59:53.065586 DQ Delay:
1621 00:59:53.066215 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1622 00:59:53.068733 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =93
1623 00:59:53.072072 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1624 00:59:53.075572 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1625 00:59:53.076161
1626 00:59:53.076654
1627 00:59:53.078517 ==
1628 00:59:53.082272 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 00:59:53.085529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 00:59:53.086144 ==
1631 00:59:53.086636
1632 00:59:53.087088
1633 00:59:53.088394 TX Vref Scan disable
1634 00:59:53.088881 == TX Byte 0 ==
1635 00:59:53.092252 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1636 00:59:53.098998 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1637 00:59:53.099602 == TX Byte 1 ==
1638 00:59:53.101931 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1639 00:59:53.108728 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1640 00:59:53.109315 ==
1641 00:59:53.112341 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 00:59:53.115850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 00:59:53.116433 ==
1644 00:59:53.129500 TX Vref=22, minBit 8, minWin=27, winSum=450
1645 00:59:53.132429 TX Vref=24, minBit 8, minWin=27, winSum=452
1646 00:59:53.135718 TX Vref=26, minBit 8, minWin=27, winSum=453
1647 00:59:53.139384 TX Vref=28, minBit 0, minWin=28, winSum=457
1648 00:59:53.142477 TX Vref=30, minBit 15, minWin=27, winSum=457
1649 00:59:53.145811 TX Vref=32, minBit 15, minWin=27, winSum=460
1650 00:59:53.153153 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1651 00:59:53.153985
1652 00:59:53.155778 Final TX Range 1 Vref 28
1653 00:59:53.156475
1654 00:59:53.157077 ==
1655 00:59:53.159345 Dram Type= 6, Freq= 0, CH_1, rank 0
1656 00:59:53.162639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1657 00:59:53.163114 ==
1658 00:59:53.163491
1659 00:59:53.163837
1660 00:59:53.166167 TX Vref Scan disable
1661 00:59:53.169152 == TX Byte 0 ==
1662 00:59:53.172734 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1663 00:59:53.176349 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1664 00:59:53.180141 == TX Byte 1 ==
1665 00:59:53.182965 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1666 00:59:53.186490 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1667 00:59:53.186967
1668 00:59:53.190198 [DATLAT]
1669 00:59:53.190673 Freq=800, CH1 RK0
1670 00:59:53.191053
1671 00:59:53.193293 DATLAT Default: 0xa
1672 00:59:53.193812 0, 0xFFFF, sum = 0
1673 00:59:53.196503 1, 0xFFFF, sum = 0
1674 00:59:53.196985 2, 0xFFFF, sum = 0
1675 00:59:53.200200 3, 0xFFFF, sum = 0
1676 00:59:53.200884 4, 0xFFFF, sum = 0
1677 00:59:53.203207 5, 0xFFFF, sum = 0
1678 00:59:53.203889 6, 0xFFFF, sum = 0
1679 00:59:53.206704 7, 0xFFFF, sum = 0
1680 00:59:53.207386 8, 0xFFFF, sum = 0
1681 00:59:53.210020 9, 0x0, sum = 1
1682 00:59:53.210649 10, 0x0, sum = 2
1683 00:59:53.213572 11, 0x0, sum = 3
1684 00:59:53.214282 12, 0x0, sum = 4
1685 00:59:53.214629 best_step = 10
1686 00:59:53.216546
1687 00:59:53.216964 ==
1688 00:59:53.219939 Dram Type= 6, Freq= 0, CH_1, rank 0
1689 00:59:53.223107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1690 00:59:53.223450 ==
1691 00:59:53.223654 RX Vref Scan: 1
1692 00:59:53.223977
1693 00:59:53.226511 Set Vref Range= 32 -> 127
1694 00:59:53.226704
1695 00:59:53.229933 RX Vref 32 -> 127, step: 1
1696 00:59:53.230111
1697 00:59:53.233637 RX Delay -95 -> 252, step: 8
1698 00:59:53.233797
1699 00:59:53.236856 Set Vref, RX VrefLevel [Byte0]: 32
1700 00:59:53.239683 [Byte1]: 32
1701 00:59:53.239840
1702 00:59:53.243552 Set Vref, RX VrefLevel [Byte0]: 33
1703 00:59:53.246572 [Byte1]: 33
1704 00:59:53.246797
1705 00:59:53.249885 Set Vref, RX VrefLevel [Byte0]: 34
1706 00:59:53.253527 [Byte1]: 34
1707 00:59:53.256760
1708 00:59:53.256907 Set Vref, RX VrefLevel [Byte0]: 35
1709 00:59:53.259849 [Byte1]: 35
1710 00:59:53.264430
1711 00:59:53.264582 Set Vref, RX VrefLevel [Byte0]: 36
1712 00:59:53.267626 [Byte1]: 36
1713 00:59:53.272213
1714 00:59:53.272837 Set Vref, RX VrefLevel [Byte0]: 37
1715 00:59:53.275368 [Byte1]: 37
1716 00:59:53.279547
1717 00:59:53.279984 Set Vref, RX VrefLevel [Byte0]: 38
1718 00:59:53.282968 [Byte1]: 38
1719 00:59:53.287429
1720 00:59:53.287854 Set Vref, RX VrefLevel [Byte0]: 39
1721 00:59:53.290667 [Byte1]: 39
1722 00:59:53.294856
1723 00:59:53.295297 Set Vref, RX VrefLevel [Byte0]: 40
1724 00:59:53.298172 [Byte1]: 40
1725 00:59:53.302380
1726 00:59:53.302649 Set Vref, RX VrefLevel [Byte0]: 41
1727 00:59:53.305660 [Byte1]: 41
1728 00:59:53.309758
1729 00:59:53.309983 Set Vref, RX VrefLevel [Byte0]: 42
1730 00:59:53.316036 [Byte1]: 42
1731 00:59:53.316266
1732 00:59:53.319583 Set Vref, RX VrefLevel [Byte0]: 43
1733 00:59:53.323067 [Byte1]: 43
1734 00:59:53.323227
1735 00:59:53.326411 Set Vref, RX VrefLevel [Byte0]: 44
1736 00:59:53.330348 [Byte1]: 44
1737 00:59:53.330947
1738 00:59:53.333420 Set Vref, RX VrefLevel [Byte0]: 45
1739 00:59:53.336398 [Byte1]: 45
1740 00:59:53.340680
1741 00:59:53.341100 Set Vref, RX VrefLevel [Byte0]: 46
1742 00:59:53.344026 [Byte1]: 46
1743 00:59:53.348345
1744 00:59:53.348767 Set Vref, RX VrefLevel [Byte0]: 47
1745 00:59:53.351657 [Byte1]: 47
1746 00:59:53.355610
1747 00:59:53.356055 Set Vref, RX VrefLevel [Byte0]: 48
1748 00:59:53.359509 [Byte1]: 48
1749 00:59:53.363525
1750 00:59:53.363993 Set Vref, RX VrefLevel [Byte0]: 49
1751 00:59:53.366696 [Byte1]: 49
1752 00:59:53.371102
1753 00:59:53.371664 Set Vref, RX VrefLevel [Byte0]: 50
1754 00:59:53.374488 [Byte1]: 50
1755 00:59:53.378562
1756 00:59:53.379030 Set Vref, RX VrefLevel [Byte0]: 51
1757 00:59:53.381835 [Byte1]: 51
1758 00:59:53.386023
1759 00:59:53.386491 Set Vref, RX VrefLevel [Byte0]: 52
1760 00:59:53.389514 [Byte1]: 52
1761 00:59:53.393708
1762 00:59:53.394280 Set Vref, RX VrefLevel [Byte0]: 53
1763 00:59:53.396895 [Byte1]: 53
1764 00:59:53.401637
1765 00:59:53.402262 Set Vref, RX VrefLevel [Byte0]: 54
1766 00:59:53.404864 [Byte1]: 54
1767 00:59:53.408668
1768 00:59:53.409156 Set Vref, RX VrefLevel [Byte0]: 55
1769 00:59:53.412388 [Byte1]: 55
1770 00:59:53.416869
1771 00:59:53.417557 Set Vref, RX VrefLevel [Byte0]: 56
1772 00:59:53.420319 [Byte1]: 56
1773 00:59:53.424206
1774 00:59:53.424889 Set Vref, RX VrefLevel [Byte0]: 57
1775 00:59:53.427329 [Byte1]: 57
1776 00:59:53.431689
1777 00:59:53.432188 Set Vref, RX VrefLevel [Byte0]: 58
1778 00:59:53.434866 [Byte1]: 58
1779 00:59:53.439366
1780 00:59:53.439839 Set Vref, RX VrefLevel [Byte0]: 59
1781 00:59:53.442839 [Byte1]: 59
1782 00:59:53.446867
1783 00:59:53.447358 Set Vref, RX VrefLevel [Byte0]: 60
1784 00:59:53.450042 [Byte1]: 60
1785 00:59:53.454361
1786 00:59:53.454836 Set Vref, RX VrefLevel [Byte0]: 61
1787 00:59:53.457755 [Byte1]: 61
1788 00:59:53.461750
1789 00:59:53.462118 Set Vref, RX VrefLevel [Byte0]: 62
1790 00:59:53.465317 [Byte1]: 62
1791 00:59:53.469434
1792 00:59:53.469765 Set Vref, RX VrefLevel [Byte0]: 63
1793 00:59:53.472504 [Byte1]: 63
1794 00:59:53.477155
1795 00:59:53.477487 Set Vref, RX VrefLevel [Byte0]: 64
1796 00:59:53.480415 [Byte1]: 64
1797 00:59:53.484618
1798 00:59:53.484948 Set Vref, RX VrefLevel [Byte0]: 65
1799 00:59:53.488398 [Byte1]: 65
1800 00:59:53.492134
1801 00:59:53.492484 Set Vref, RX VrefLevel [Byte0]: 66
1802 00:59:53.495316 [Byte1]: 66
1803 00:59:53.499687
1804 00:59:53.500006 Set Vref, RX VrefLevel [Byte0]: 67
1805 00:59:53.503418 [Byte1]: 67
1806 00:59:53.507529
1807 00:59:53.507856 Set Vref, RX VrefLevel [Byte0]: 68
1808 00:59:53.510874 [Byte1]: 68
1809 00:59:53.515090
1810 00:59:53.515420 Set Vref, RX VrefLevel [Byte0]: 69
1811 00:59:53.518388 [Byte1]: 69
1812 00:59:53.522630
1813 00:59:53.522953 Set Vref, RX VrefLevel [Byte0]: 70
1814 00:59:53.525789 [Byte1]: 70
1815 00:59:53.530225
1816 00:59:53.530308 Set Vref, RX VrefLevel [Byte0]: 71
1817 00:59:53.533040 [Byte1]: 71
1818 00:59:53.537505
1819 00:59:53.537587 Set Vref, RX VrefLevel [Byte0]: 72
1820 00:59:53.540799 [Byte1]: 72
1821 00:59:53.545054
1822 00:59:53.545137 Set Vref, RX VrefLevel [Byte0]: 73
1823 00:59:53.548621 [Byte1]: 73
1824 00:59:53.553554
1825 00:59:53.553637 Set Vref, RX VrefLevel [Byte0]: 74
1826 00:59:53.556398 [Byte1]: 74
1827 00:59:53.560518
1828 00:59:53.560611 Set Vref, RX VrefLevel [Byte0]: 75
1829 00:59:53.563809 [Byte1]: 75
1830 00:59:53.568093
1831 00:59:53.568197 Set Vref, RX VrefLevel [Byte0]: 76
1832 00:59:53.571642 [Byte1]: 76
1833 00:59:53.575770
1834 00:59:53.575852 Set Vref, RX VrefLevel [Byte0]: 77
1835 00:59:53.578885 [Byte1]: 77
1836 00:59:53.583155
1837 00:59:53.583238 Set Vref, RX VrefLevel [Byte0]: 78
1838 00:59:53.586594 [Byte1]: 78
1839 00:59:53.590963
1840 00:59:53.591055 Final RX Vref Byte 0 = 50 to rank0
1841 00:59:53.594145 Final RX Vref Byte 1 = 61 to rank0
1842 00:59:53.597667 Final RX Vref Byte 0 = 50 to rank1
1843 00:59:53.601309 Final RX Vref Byte 1 = 61 to rank1==
1844 00:59:53.604227 Dram Type= 6, Freq= 0, CH_1, rank 0
1845 00:59:53.610794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 00:59:53.610972 ==
1847 00:59:53.611119 DQS Delay:
1848 00:59:53.611257 DQS0 = 0, DQS1 = 0
1849 00:59:53.614247 DQM Delay:
1850 00:59:53.614384 DQM0 = 92, DQM1 = 81
1851 00:59:53.617539 DQ Delay:
1852 00:59:53.621210 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1853 00:59:53.624784 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1854 00:59:53.625052 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1855 00:59:53.631177 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1856 00:59:53.631471
1857 00:59:53.631645
1858 00:59:53.638254 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1859 00:59:53.641309 CH1 RK0: MR19=606, MR18=2B48
1860 00:59:53.648110 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1861 00:59:53.648605
1862 00:59:53.651378 ----->DramcWriteLeveling(PI) begin...
1863 00:59:53.651877 ==
1864 00:59:53.654805 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 00:59:53.658429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 00:59:53.659003 ==
1867 00:59:53.661490 Write leveling (Byte 0): 29 => 29
1868 00:59:53.664947 Write leveling (Byte 1): 29 => 29
1869 00:59:53.668265 DramcWriteLeveling(PI) end<-----
1870 00:59:53.668827
1871 00:59:53.669199 ==
1872 00:59:53.671509 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 00:59:53.674840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 00:59:53.675422 ==
1875 00:59:53.678046 [Gating] SW mode calibration
1876 00:59:53.684906 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1877 00:59:53.691727 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1878 00:59:53.694630 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1879 00:59:53.698155 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1880 00:59:53.704559 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:59:53.708223 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:59:53.711317 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 00:59:53.718225 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:59:53.721295 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:59:53.724388 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:59:53.731349 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:59:53.734563 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:59:53.737871 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:59:53.744581 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:59:53.748071 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:59:53.751494 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 00:59:53.758240 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 00:59:53.761572 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 00:59:53.765047 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1895 00:59:53.768336 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1896 00:59:53.774851 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1897 00:59:53.778350 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 00:59:53.781199 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 00:59:53.788296 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 00:59:53.791365 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:59:53.794792 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:59:53.801744 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:59:53.804888 0 9 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1904 00:59:53.808607 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 00:59:53.814893 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 00:59:53.818694 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 00:59:53.821727 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 00:59:53.825203 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 00:59:53.831817 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 00:59:53.835330 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1911 00:59:53.838369 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
1912 00:59:53.845168 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1913 00:59:53.848147 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 00:59:53.851960 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 00:59:53.858728 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 00:59:53.861714 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 00:59:53.865601 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 00:59:53.871553 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 00:59:53.875213 0 11 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
1920 00:59:53.878618 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 00:59:53.885189 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 00:59:53.888501 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 00:59:53.891831 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 00:59:53.898480 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 00:59:53.902087 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 00:59:53.905014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 00:59:53.908272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 00:59:53.915241 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 00:59:53.918515 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:59:53.921865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:59:53.928415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 00:59:53.932448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 00:59:53.935518 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 00:59:53.942115 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 00:59:53.945359 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 00:59:53.948771 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 00:59:53.955039 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 00:59:53.958990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 00:59:53.962357 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 00:59:53.968734 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 00:59:53.972051 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 00:59:53.975594 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 00:59:53.982320 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1944 00:59:53.985382 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 00:59:53.988707 Total UI for P1: 0, mck2ui 16
1946 00:59:53.992264 best dqsien dly found for B0: ( 0, 14, 6)
1947 00:59:53.995604 Total UI for P1: 0, mck2ui 16
1948 00:59:53.998645 best dqsien dly found for B1: ( 0, 14, 4)
1949 00:59:54.001887 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1950 00:59:54.005215 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1951 00:59:54.005693
1952 00:59:54.008795 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1953 00:59:54.012165 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1954 00:59:54.015319 [Gating] SW calibration Done
1955 00:59:54.015789 ==
1956 00:59:54.018643 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 00:59:54.022169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 00:59:54.022742 ==
1959 00:59:54.025527 RX Vref Scan: 0
1960 00:59:54.026019
1961 00:59:54.026401 RX Vref 0 -> 0, step: 1
1962 00:59:54.026751
1963 00:59:54.029316 RX Delay -130 -> 252, step: 16
1964 00:59:54.032150 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1965 00:59:54.038962 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1966 00:59:54.042473 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1967 00:59:54.045776 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1968 00:59:54.049458 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1969 00:59:54.052019 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1970 00:59:54.058872 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1971 00:59:54.062372 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1972 00:59:54.065602 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1973 00:59:54.068894 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1974 00:59:54.072345 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1975 00:59:54.078382 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1976 00:59:54.081525 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1977 00:59:54.085165 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1978 00:59:54.088041 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1979 00:59:54.095393 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1980 00:59:54.095868 ==
1981 00:59:54.098591 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 00:59:54.102042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 00:59:54.102512 ==
1984 00:59:54.102885 DQS Delay:
1985 00:59:54.105318 DQS0 = 0, DQS1 = 0
1986 00:59:54.105827 DQM Delay:
1987 00:59:54.109017 DQM0 = 89, DQM1 = 85
1988 00:59:54.109668 DQ Delay:
1989 00:59:54.112247 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1990 00:59:54.115658 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1991 00:59:54.118993 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1992 00:59:54.122306 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1993 00:59:54.122785
1994 00:59:54.123164
1995 00:59:54.123514 ==
1996 00:59:54.125666 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 00:59:54.128959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 00:59:54.129443 ==
1999 00:59:54.129828
2000 00:59:54.130242
2001 00:59:54.132646 TX Vref Scan disable
2002 00:59:54.133123 == TX Byte 0 ==
2003 00:59:54.139048 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2004 00:59:54.142499 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2005 00:59:54.145598 == TX Byte 1 ==
2006 00:59:54.148696 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2007 00:59:54.151992 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2008 00:59:54.152466 ==
2009 00:59:54.155399 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 00:59:54.159142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 00:59:54.159779 ==
2012 00:59:54.173059 TX Vref=22, minBit 13, minWin=27, winSum=450
2013 00:59:54.176084 TX Vref=24, minBit 13, minWin=27, winSum=454
2014 00:59:54.179357 TX Vref=26, minBit 13, minWin=27, winSum=458
2015 00:59:54.182699 TX Vref=28, minBit 8, minWin=28, winSum=459
2016 00:59:54.186029 TX Vref=30, minBit 8, minWin=28, winSum=459
2017 00:59:54.192551 TX Vref=32, minBit 8, minWin=28, winSum=458
2018 00:59:54.196115 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
2019 00:59:54.196203
2020 00:59:54.199256 Final TX Range 1 Vref 28
2021 00:59:54.199377
2022 00:59:54.199459 ==
2023 00:59:54.202703 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 00:59:54.205783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 00:59:54.208981 ==
2026 00:59:54.209092
2027 00:59:54.209158
2028 00:59:54.209220 TX Vref Scan disable
2029 00:59:54.212848 == TX Byte 0 ==
2030 00:59:54.216155 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2031 00:59:54.219560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2032 00:59:54.223123 == TX Byte 1 ==
2033 00:59:54.226118 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2034 00:59:54.229653 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2035 00:59:54.229738
2036 00:59:54.232954 [DATLAT]
2037 00:59:54.233037 Freq=800, CH1 RK1
2038 00:59:54.233103
2039 00:59:54.236107 DATLAT Default: 0xa
2040 00:59:54.236194 0, 0xFFFF, sum = 0
2041 00:59:54.239758 1, 0xFFFF, sum = 0
2042 00:59:54.239870 2, 0xFFFF, sum = 0
2043 00:59:54.242715 3, 0xFFFF, sum = 0
2044 00:59:54.242800 4, 0xFFFF, sum = 0
2045 00:59:54.246312 5, 0xFFFF, sum = 0
2046 00:59:54.246483 6, 0xFFFF, sum = 0
2047 00:59:54.249528 7, 0xFFFF, sum = 0
2048 00:59:54.249672 8, 0xFFFF, sum = 0
2049 00:59:54.252785 9, 0x0, sum = 1
2050 00:59:54.252884 10, 0x0, sum = 2
2051 00:59:54.256173 11, 0x0, sum = 3
2052 00:59:54.256285 12, 0x0, sum = 4
2053 00:59:54.259606 best_step = 10
2054 00:59:54.259719
2055 00:59:54.259809 ==
2056 00:59:54.262816 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 00:59:54.266262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 00:59:54.266419 ==
2059 00:59:54.269684 RX Vref Scan: 0
2060 00:59:54.269847
2061 00:59:54.269997 RX Vref 0 -> 0, step: 1
2062 00:59:54.270103
2063 00:59:54.272813 RX Delay -95 -> 252, step: 8
2064 00:59:54.279699 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2065 00:59:54.282767 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2066 00:59:54.286249 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2067 00:59:54.289740 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2068 00:59:54.293320 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2069 00:59:54.299482 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2070 00:59:54.302781 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2071 00:59:54.306302 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2072 00:59:54.309937 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2073 00:59:54.313101 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2074 00:59:54.316340 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2075 00:59:54.322951 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2076 00:59:54.326384 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2077 00:59:54.329548 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2078 00:59:54.333137 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2079 00:59:54.339654 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2080 00:59:54.339830 ==
2081 00:59:54.342645 Dram Type= 6, Freq= 0, CH_1, rank 1
2082 00:59:54.346164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2083 00:59:54.346350 ==
2084 00:59:54.346475 DQS Delay:
2085 00:59:54.349690 DQS0 = 0, DQS1 = 0
2086 00:59:54.349844 DQM Delay:
2087 00:59:54.352866 DQM0 = 90, DQM1 = 82
2088 00:59:54.353040 DQ Delay:
2089 00:59:54.356263 DQ0 =92, DQ1 =88, DQ2 =80, DQ3 =88
2090 00:59:54.359372 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2091 00:59:54.363769 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2092 00:59:54.366817 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2093 00:59:54.366974
2094 00:59:54.367098
2095 00:59:54.372959 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2096 00:59:54.376427 CH1 RK1: MR19=606, MR18=350A
2097 00:59:54.383166 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2098 00:59:54.386375 [RxdqsGatingPostProcess] freq 800
2099 00:59:54.392821 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2100 00:59:54.393001 Pre-setting of DQS Precalculation
2101 00:59:54.399586 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2102 00:59:54.406157 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2103 00:59:54.413594 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2104 00:59:54.413996
2105 00:59:54.414274
2106 00:59:54.416870 [Calibration Summary] 1600 Mbps
2107 00:59:54.419803 CH 0, Rank 0
2108 00:59:54.420206 SW Impedance : PASS
2109 00:59:54.423744 DUTY Scan : NO K
2110 00:59:54.427044 ZQ Calibration : PASS
2111 00:59:54.427621 Jitter Meter : NO K
2112 00:59:54.429984 CBT Training : PASS
2113 00:59:54.430484 Write leveling : PASS
2114 00:59:54.433298 RX DQS gating : PASS
2115 00:59:54.437067 RX DQ/DQS(RDDQC) : PASS
2116 00:59:54.437638 TX DQ/DQS : PASS
2117 00:59:54.440339 RX DATLAT : PASS
2118 00:59:54.443912 RX DQ/DQS(Engine): PASS
2119 00:59:54.444498 TX OE : NO K
2120 00:59:54.446590 All Pass.
2121 00:59:54.447064
2122 00:59:54.447442 CH 0, Rank 1
2123 00:59:54.449866 SW Impedance : PASS
2124 00:59:54.450532 DUTY Scan : NO K
2125 00:59:54.453365 ZQ Calibration : PASS
2126 00:59:54.456728 Jitter Meter : NO K
2127 00:59:54.457229 CBT Training : PASS
2128 00:59:54.459626 Write leveling : PASS
2129 00:59:54.463386 RX DQS gating : PASS
2130 00:59:54.463854 RX DQ/DQS(RDDQC) : PASS
2131 00:59:54.466528 TX DQ/DQS : PASS
2132 00:59:54.469563 RX DATLAT : PASS
2133 00:59:54.470187 RX DQ/DQS(Engine): PASS
2134 00:59:54.473080 TX OE : NO K
2135 00:59:54.473551 All Pass.
2136 00:59:54.473920
2137 00:59:54.476690 CH 1, Rank 0
2138 00:59:54.477158 SW Impedance : PASS
2139 00:59:54.480465 DUTY Scan : NO K
2140 00:59:54.480938 ZQ Calibration : PASS
2141 00:59:54.483396 Jitter Meter : NO K
2142 00:59:54.486480 CBT Training : PASS
2143 00:59:54.486948 Write leveling : PASS
2144 00:59:54.489859 RX DQS gating : PASS
2145 00:59:54.493041 RX DQ/DQS(RDDQC) : PASS
2146 00:59:54.493369 TX DQ/DQS : PASS
2147 00:59:54.496044 RX DATLAT : PASS
2148 00:59:54.499518 RX DQ/DQS(Engine): PASS
2149 00:59:54.499802 TX OE : NO K
2150 00:59:54.502960 All Pass.
2151 00:59:54.503157
2152 00:59:54.503313 CH 1, Rank 1
2153 00:59:54.505918 SW Impedance : PASS
2154 00:59:54.506142 DUTY Scan : NO K
2155 00:59:54.509741 ZQ Calibration : PASS
2156 00:59:54.512936 Jitter Meter : NO K
2157 00:59:54.513132 CBT Training : PASS
2158 00:59:54.516541 Write leveling : PASS
2159 00:59:54.519878 RX DQS gating : PASS
2160 00:59:54.520076 RX DQ/DQS(RDDQC) : PASS
2161 00:59:54.522996 TX DQ/DQS : PASS
2162 00:59:54.523194 RX DATLAT : PASS
2163 00:59:54.526186 RX DQ/DQS(Engine): PASS
2164 00:59:54.529608 TX OE : NO K
2165 00:59:54.529784 All Pass.
2166 00:59:54.529933
2167 00:59:54.532752 DramC Write-DBI off
2168 00:59:54.532973 PER_BANK_REFRESH: Hybrid Mode
2169 00:59:54.536071 TX_TRACKING: ON
2170 00:59:54.539641 [GetDramInforAfterCalByMRR] Vendor 6.
2171 00:59:54.542835 [GetDramInforAfterCalByMRR] Revision 606.
2172 00:59:54.546280 [GetDramInforAfterCalByMRR] Revision 2 0.
2173 00:59:54.546473 MR0 0x3b3b
2174 00:59:54.549363 MR8 0x5151
2175 00:59:54.552765 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 00:59:54.552959
2177 00:59:54.553112 MR0 0x3b3b
2178 00:59:54.556062 MR8 0x5151
2179 00:59:54.559571 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 00:59:54.559772
2181 00:59:54.565891 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2182 00:59:54.569258 [FAST_K] Save calibration result to emmc
2183 00:59:54.575913 [FAST_K] Save calibration result to emmc
2184 00:59:54.575997 dram_init: config_dvfs: 1
2185 00:59:54.579268 dramc_set_vcore_voltage set vcore to 662500
2186 00:59:54.582302 Read voltage for 1200, 2
2187 00:59:54.582373 Vio18 = 0
2188 00:59:54.586112 Vcore = 662500
2189 00:59:54.586185 Vdram = 0
2190 00:59:54.586247 Vddq = 0
2191 00:59:54.588892 Vmddr = 0
2192 00:59:54.592408 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2193 00:59:54.599124 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2194 00:59:54.599211 MEM_TYPE=3, freq_sel=15
2195 00:59:54.602524 sv_algorithm_assistance_LP4_1600
2196 00:59:54.609741 ============ PULL DRAM RESETB DOWN ============
2197 00:59:54.613085 ========== PULL DRAM RESETB DOWN end =========
2198 00:59:54.615823 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 00:59:54.619675 ===================================
2200 00:59:54.622739 LPDDR4 DRAM CONFIGURATION
2201 00:59:54.625849 ===================================
2202 00:59:54.625932 EX_ROW_EN[0] = 0x0
2203 00:59:54.629059 EX_ROW_EN[1] = 0x0
2204 00:59:54.632545 LP4Y_EN = 0x0
2205 00:59:54.632628 WORK_FSP = 0x0
2206 00:59:54.636298 WL = 0x4
2207 00:59:54.636381 RL = 0x4
2208 00:59:54.639121 BL = 0x2
2209 00:59:54.639203 RPST = 0x0
2210 00:59:54.642414 RD_PRE = 0x0
2211 00:59:54.642496 WR_PRE = 0x1
2212 00:59:54.646202 WR_PST = 0x0
2213 00:59:54.646284 DBI_WR = 0x0
2214 00:59:54.649020 DBI_RD = 0x0
2215 00:59:54.649102 OTF = 0x1
2216 00:59:54.652248 ===================================
2217 00:59:54.655783 ===================================
2218 00:59:54.659143 ANA top config
2219 00:59:54.662507 ===================================
2220 00:59:54.662591 DLL_ASYNC_EN = 0
2221 00:59:54.665957 ALL_SLAVE_EN = 0
2222 00:59:54.669675 NEW_RANK_MODE = 1
2223 00:59:54.673273 DLL_IDLE_MODE = 1
2224 00:59:54.673440 LP45_APHY_COMB_EN = 1
2225 00:59:54.676531 TX_ODT_DIS = 1
2226 00:59:54.679661 NEW_8X_MODE = 1
2227 00:59:54.683125 ===================================
2228 00:59:54.686300 ===================================
2229 00:59:54.689900 data_rate = 2400
2230 00:59:54.693586 CKR = 1
2231 00:59:54.693795 DQ_P2S_RATIO = 8
2232 00:59:54.696315 ===================================
2233 00:59:54.699823 CA_P2S_RATIO = 8
2234 00:59:54.702709 DQ_CA_OPEN = 0
2235 00:59:54.706006 DQ_SEMI_OPEN = 0
2236 00:59:54.709591 CA_SEMI_OPEN = 0
2237 00:59:54.712725 CA_FULL_RATE = 0
2238 00:59:54.712928 DQ_CKDIV4_EN = 0
2239 00:59:54.716296 CA_CKDIV4_EN = 0
2240 00:59:54.719783 CA_PREDIV_EN = 0
2241 00:59:54.723536 PH8_DLY = 17
2242 00:59:54.726781 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2243 00:59:54.730151 DQ_AAMCK_DIV = 4
2244 00:59:54.730718 CA_AAMCK_DIV = 4
2245 00:59:54.733622 CA_ADMCK_DIV = 4
2246 00:59:54.737472 DQ_TRACK_CA_EN = 0
2247 00:59:54.740203 CA_PICK = 1200
2248 00:59:54.743364 CA_MCKIO = 1200
2249 00:59:54.747182 MCKIO_SEMI = 0
2250 00:59:54.750149 PLL_FREQ = 2366
2251 00:59:54.750617 DQ_UI_PI_RATIO = 32
2252 00:59:54.753373 CA_UI_PI_RATIO = 0
2253 00:59:54.756631 ===================================
2254 00:59:54.759780 ===================================
2255 00:59:54.763438 memory_type:LPDDR4
2256 00:59:54.766748 GP_NUM : 10
2257 00:59:54.767224 SRAM_EN : 1
2258 00:59:54.770012 MD32_EN : 0
2259 00:59:54.773394 ===================================
2260 00:59:54.776762 [ANA_INIT] >>>>>>>>>>>>>>
2261 00:59:54.777243 <<<<<< [CONFIGURE PHASE]: ANA_TX
2262 00:59:54.780135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2263 00:59:54.783645 ===================================
2264 00:59:54.786327 data_rate = 2400,PCW = 0X5b00
2265 00:59:54.790163 ===================================
2266 00:59:54.793421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2267 00:59:54.800176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 00:59:54.803629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 00:59:54.810053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2270 00:59:54.813635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2271 00:59:54.817011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2272 00:59:54.820371 [ANA_INIT] flow start
2273 00:59:54.820952 [ANA_INIT] PLL >>>>>>>>
2274 00:59:54.823596 [ANA_INIT] PLL <<<<<<<<
2275 00:59:54.827264 [ANA_INIT] MIDPI >>>>>>>>
2276 00:59:54.827838 [ANA_INIT] MIDPI <<<<<<<<
2277 00:59:54.830225 [ANA_INIT] DLL >>>>>>>>
2278 00:59:54.833911 [ANA_INIT] DLL <<<<<<<<
2279 00:59:54.834538 [ANA_INIT] flow end
2280 00:59:54.840694 ============ LP4 DIFF to SE enter ============
2281 00:59:54.843699 ============ LP4 DIFF to SE exit ============
2282 00:59:54.844278 [ANA_INIT] <<<<<<<<<<<<<
2283 00:59:54.847533 [Flow] Enable top DCM control >>>>>
2284 00:59:54.850262 [Flow] Enable top DCM control <<<<<
2285 00:59:54.853575 Enable DLL master slave shuffle
2286 00:59:54.860144 ==============================================================
2287 00:59:54.860621 Gating Mode config
2288 00:59:54.866751 ==============================================================
2289 00:59:54.870323 Config description:
2290 00:59:54.880913 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2291 00:59:54.887320 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2292 00:59:54.890606 SELPH_MODE 0: By rank 1: By Phase
2293 00:59:54.897494 ==============================================================
2294 00:59:54.898134 GAT_TRACK_EN = 1
2295 00:59:54.900639 RX_GATING_MODE = 2
2296 00:59:54.904320 RX_GATING_TRACK_MODE = 2
2297 00:59:54.907036 SELPH_MODE = 1
2298 00:59:54.910742 PICG_EARLY_EN = 1
2299 00:59:54.914345 VALID_LAT_VALUE = 1
2300 00:59:54.920866 ==============================================================
2301 00:59:54.924058 Enter into Gating configuration >>>>
2302 00:59:54.927328 Exit from Gating configuration <<<<
2303 00:59:54.930674 Enter into DVFS_PRE_config >>>>>
2304 00:59:54.941217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2305 00:59:54.944407 Exit from DVFS_PRE_config <<<<<
2306 00:59:54.947337 Enter into PICG configuration >>>>
2307 00:59:54.950561 Exit from PICG configuration <<<<
2308 00:59:54.951038 [RX_INPUT] configuration >>>>>
2309 00:59:54.953968 [RX_INPUT] configuration <<<<<
2310 00:59:54.960823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2311 00:59:54.964122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2312 00:59:54.970894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 00:59:54.977896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 00:59:54.984282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 00:59:54.990657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 00:59:54.994203 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2317 00:59:54.997526 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2318 00:59:55.000817 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2319 00:59:55.007624 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2320 00:59:55.010801 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2321 00:59:55.014932 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 00:59:55.017466 ===================================
2323 00:59:55.020889 LPDDR4 DRAM CONFIGURATION
2324 00:59:55.024844 ===================================
2325 00:59:55.028213 EX_ROW_EN[0] = 0x0
2326 00:59:55.028796 EX_ROW_EN[1] = 0x0
2327 00:59:55.031286 LP4Y_EN = 0x0
2328 00:59:55.031762 WORK_FSP = 0x0
2329 00:59:55.034610 WL = 0x4
2330 00:59:55.035258 RL = 0x4
2331 00:59:55.037998 BL = 0x2
2332 00:59:55.038476 RPST = 0x0
2333 00:59:55.041703 RD_PRE = 0x0
2334 00:59:55.042327 WR_PRE = 0x1
2335 00:59:55.045243 WR_PST = 0x0
2336 00:59:55.045825 DBI_WR = 0x0
2337 00:59:55.048228 DBI_RD = 0x0
2338 00:59:55.048813 OTF = 0x1
2339 00:59:55.051429 ===================================
2340 00:59:55.054493 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2341 00:59:55.061214 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2342 00:59:55.064582 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 00:59:55.068258 ===================================
2344 00:59:55.071547 LPDDR4 DRAM CONFIGURATION
2345 00:59:55.075035 ===================================
2346 00:59:55.075615 EX_ROW_EN[0] = 0x10
2347 00:59:55.078278 EX_ROW_EN[1] = 0x0
2348 00:59:55.078854 LP4Y_EN = 0x0
2349 00:59:55.081630 WORK_FSP = 0x0
2350 00:59:55.082249 WL = 0x4
2351 00:59:55.085010 RL = 0x4
2352 00:59:55.087888 BL = 0x2
2353 00:59:55.088365 RPST = 0x0
2354 00:59:55.091297 RD_PRE = 0x0
2355 00:59:55.092034 WR_PRE = 0x1
2356 00:59:55.094269 WR_PST = 0x0
2357 00:59:55.094772 DBI_WR = 0x0
2358 00:59:55.097830 DBI_RD = 0x0
2359 00:59:55.098352 OTF = 0x1
2360 00:59:55.101017 ===================================
2361 00:59:55.107919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2362 00:59:55.108383 ==
2363 00:59:55.111044 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 00:59:55.114483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 00:59:55.114953 ==
2366 00:59:55.117619 [Duty_Offset_Calibration]
2367 00:59:55.121284 B0:2 B1:0 CA:1
2368 00:59:55.121747
2369 00:59:55.124222 [DutyScan_Calibration_Flow] k_type=0
2370 00:59:55.131844
2371 00:59:55.132264 ==CLK 0==
2372 00:59:55.135157 Final CLK duty delay cell = -4
2373 00:59:55.138165 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2374 00:59:55.142034 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2375 00:59:55.145273 [-4] AVG Duty = 4953%(X100)
2376 00:59:55.145693
2377 00:59:55.148310 CH0 CLK Duty spec in!! Max-Min= 156%
2378 00:59:55.151441 [DutyScan_Calibration_Flow] ====Done====
2379 00:59:55.151770
2380 00:59:55.155127 [DutyScan_Calibration_Flow] k_type=1
2381 00:59:55.170484
2382 00:59:55.171044 ==DQS 0 ==
2383 00:59:55.173678 Final DQS duty delay cell = 0
2384 00:59:55.177382 [0] MAX Duty = 5187%(X100), DQS PI = 30
2385 00:59:55.180638 [0] MIN Duty = 4938%(X100), DQS PI = 0
2386 00:59:55.181211 [0] AVG Duty = 5062%(X100)
2387 00:59:55.183920
2388 00:59:55.184482 ==DQS 1 ==
2389 00:59:55.187166 Final DQS duty delay cell = -4
2390 00:59:55.190526 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2391 00:59:55.193876 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2392 00:59:55.197041 [-4] AVG Duty = 5015%(X100)
2393 00:59:55.197603
2394 00:59:55.200456 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2395 00:59:55.201190
2396 00:59:55.203711 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2397 00:59:55.206955 [DutyScan_Calibration_Flow] ====Done====
2398 00:59:55.207420
2399 00:59:55.210434 [DutyScan_Calibration_Flow] k_type=3
2400 00:59:55.227904
2401 00:59:55.228457 ==DQM 0 ==
2402 00:59:55.230456 Final DQM duty delay cell = 0
2403 00:59:55.234024 [0] MAX Duty = 5062%(X100), DQS PI = 24
2404 00:59:55.237372 [0] MIN Duty = 4844%(X100), DQS PI = 0
2405 00:59:55.237926 [0] AVG Duty = 4953%(X100)
2406 00:59:55.240984
2407 00:59:55.241532 ==DQM 1 ==
2408 00:59:55.243943 Final DQM duty delay cell = 0
2409 00:59:55.247183 [0] MAX Duty = 5187%(X100), DQS PI = 48
2410 00:59:55.250874 [0] MIN Duty = 5000%(X100), DQS PI = 12
2411 00:59:55.251399 [0] AVG Duty = 5093%(X100)
2412 00:59:55.253732
2413 00:59:55.257188 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2414 00:59:55.257750
2415 00:59:55.260861 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2416 00:59:55.264666 [DutyScan_Calibration_Flow] ====Done====
2417 00:59:55.265226
2418 00:59:55.267213 [DutyScan_Calibration_Flow] k_type=2
2419 00:59:55.283816
2420 00:59:55.284385 ==DQ 0 ==
2421 00:59:55.287680 Final DQ duty delay cell = -4
2422 00:59:55.290403 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2423 00:59:55.294013 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2424 00:59:55.297302 [-4] AVG Duty = 4968%(X100)
2425 00:59:55.297872
2426 00:59:55.298287 ==DQ 1 ==
2427 00:59:55.300337 Final DQ duty delay cell = 4
2428 00:59:55.303801 [4] MAX Duty = 5093%(X100), DQS PI = 4
2429 00:59:55.307026 [4] MIN Duty = 5031%(X100), DQS PI = 2
2430 00:59:55.307520 [4] AVG Duty = 5062%(X100)
2431 00:59:55.310582
2432 00:59:55.314175 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2433 00:59:55.314747
2434 00:59:55.317642 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2435 00:59:55.320687 [DutyScan_Calibration_Flow] ====Done====
2436 00:59:55.321261 ==
2437 00:59:55.324324 Dram Type= 6, Freq= 0, CH_1, rank 0
2438 00:59:55.327656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 00:59:55.328236 ==
2440 00:59:55.330524 [Duty_Offset_Calibration]
2441 00:59:55.330997 B0:0 B1:-1 CA:2
2442 00:59:55.331373
2443 00:59:55.334037 [DutyScan_Calibration_Flow] k_type=0
2444 00:59:55.344283
2445 00:59:55.344875 ==CLK 0==
2446 00:59:55.347275 Final CLK duty delay cell = 0
2447 00:59:55.350549 [0] MAX Duty = 5156%(X100), DQS PI = 16
2448 00:59:55.353983 [0] MIN Duty = 4938%(X100), DQS PI = 44
2449 00:59:55.354485 [0] AVG Duty = 5047%(X100)
2450 00:59:55.357666
2451 00:59:55.360817 CH1 CLK Duty spec in!! Max-Min= 218%
2452 00:59:55.364640 [DutyScan_Calibration_Flow] ====Done====
2453 00:59:55.365224
2454 00:59:55.367478 [DutyScan_Calibration_Flow] k_type=1
2455 00:59:55.383594
2456 00:59:55.384171 ==DQS 0 ==
2457 00:59:55.386919 Final DQS duty delay cell = 0
2458 00:59:55.390153 [0] MAX Duty = 5093%(X100), DQS PI = 24
2459 00:59:55.393254 [0] MIN Duty = 4969%(X100), DQS PI = 0
2460 00:59:55.396855 [0] AVG Duty = 5031%(X100)
2461 00:59:55.397430
2462 00:59:55.397802 ==DQS 1 ==
2463 00:59:55.400369 Final DQS duty delay cell = 0
2464 00:59:55.403162 [0] MAX Duty = 5156%(X100), DQS PI = 0
2465 00:59:55.406879 [0] MIN Duty = 4844%(X100), DQS PI = 36
2466 00:59:55.407354 [0] AVG Duty = 5000%(X100)
2467 00:59:55.410201
2468 00:59:55.413692 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2469 00:59:55.414337
2470 00:59:55.416742 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2471 00:59:55.420144 [DutyScan_Calibration_Flow] ====Done====
2472 00:59:55.420728
2473 00:59:55.423161 [DutyScan_Calibration_Flow] k_type=3
2474 00:59:55.440927
2475 00:59:55.441502 ==DQM 0 ==
2476 00:59:55.443932 Final DQM duty delay cell = 4
2477 00:59:55.447447 [4] MAX Duty = 5093%(X100), DQS PI = 22
2478 00:59:55.450996 [4] MIN Duty = 4969%(X100), DQS PI = 28
2479 00:59:55.453975 [4] AVG Duty = 5031%(X100)
2480 00:59:55.454651
2481 00:59:55.455037 ==DQM 1 ==
2482 00:59:55.457281 Final DQM duty delay cell = 0
2483 00:59:55.460736 [0] MAX Duty = 5249%(X100), DQS PI = 0
2484 00:59:55.463963 [0] MIN Duty = 4907%(X100), DQS PI = 36
2485 00:59:55.464436 [0] AVG Duty = 5078%(X100)
2486 00:59:55.467211
2487 00:59:55.470675 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2488 00:59:55.471251
2489 00:59:55.474069 CH1 DQM 1 Duty spec in!! Max-Min= 342%
2490 00:59:55.477182 [DutyScan_Calibration_Flow] ====Done====
2491 00:59:55.477651
2492 00:59:55.480878 [DutyScan_Calibration_Flow] k_type=2
2493 00:59:55.496966
2494 00:59:55.497557 ==DQ 0 ==
2495 00:59:55.500353 Final DQ duty delay cell = 0
2496 00:59:55.503705 [0] MAX Duty = 5031%(X100), DQS PI = 18
2497 00:59:55.507717 [0] MIN Duty = 4938%(X100), DQS PI = 0
2498 00:59:55.508301 [0] AVG Duty = 4984%(X100)
2499 00:59:55.508679
2500 00:59:55.510450 ==DQ 1 ==
2501 00:59:55.513642 Final DQ duty delay cell = 0
2502 00:59:55.516906 [0] MAX Duty = 5031%(X100), DQS PI = 2
2503 00:59:55.520673 [0] MIN Duty = 4813%(X100), DQS PI = 36
2504 00:59:55.521261 [0] AVG Duty = 4922%(X100)
2505 00:59:55.521636
2506 00:59:55.523616 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2507 00:59:55.524086
2508 00:59:55.527029 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2509 00:59:55.533529 [DutyScan_Calibration_Flow] ====Done====
2510 00:59:55.537287 nWR fixed to 30
2511 00:59:55.537867 [ModeRegInit_LP4] CH0 RK0
2512 00:59:55.540460 [ModeRegInit_LP4] CH0 RK1
2513 00:59:55.544104 [ModeRegInit_LP4] CH1 RK0
2514 00:59:55.544680 [ModeRegInit_LP4] CH1 RK1
2515 00:59:55.547448 match AC timing 7
2516 00:59:55.550486 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2517 00:59:55.553648 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2518 00:59:55.560490 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2519 00:59:55.564001 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2520 00:59:55.570592 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2521 00:59:55.571176 ==
2522 00:59:55.574089 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 00:59:55.577285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 00:59:55.577872 ==
2525 00:59:55.583924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 00:59:55.587182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 00:59:55.596808 [CA 0] Center 38 (7~69) winsize 63
2528 00:59:55.599978 [CA 1] Center 38 (8~69) winsize 62
2529 00:59:55.603212 [CA 2] Center 35 (5~66) winsize 62
2530 00:59:55.606568 [CA 3] Center 35 (4~66) winsize 63
2531 00:59:55.610086 [CA 4] Center 34 (4~65) winsize 62
2532 00:59:55.613693 [CA 5] Center 33 (3~63) winsize 61
2533 00:59:55.614360
2534 00:59:55.616599 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2535 00:59:55.617073
2536 00:59:55.620291 [CATrainingPosCal] consider 1 rank data
2537 00:59:55.623638 u2DelayCellTimex100 = 270/100 ps
2538 00:59:55.626827 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2539 00:59:55.630325 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2540 00:59:55.637160 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 00:59:55.640188 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2542 00:59:55.643680 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 00:59:55.647003 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2544 00:59:55.647601
2545 00:59:55.650327 CA PerBit enable=1, Macro0, CA PI delay=33
2546 00:59:55.650904
2547 00:59:55.653804 [CBTSetCACLKResult] CA Dly = 33
2548 00:59:55.654423 CS Dly: 6 (0~37)
2549 00:59:55.654868 ==
2550 00:59:55.656759 Dram Type= 6, Freq= 0, CH_0, rank 1
2551 00:59:55.663477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 00:59:55.664053 ==
2553 00:59:55.666977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 00:59:55.673905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2555 00:59:55.682504 [CA 0] Center 39 (8~70) winsize 63
2556 00:59:55.685865 [CA 1] Center 38 (8~69) winsize 62
2557 00:59:55.689669 [CA 2] Center 35 (5~66) winsize 62
2558 00:59:55.692580 [CA 3] Center 35 (5~66) winsize 62
2559 00:59:55.695932 [CA 4] Center 34 (4~65) winsize 62
2560 00:59:55.699606 [CA 5] Center 34 (4~64) winsize 61
2561 00:59:55.700180
2562 00:59:55.702565 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2563 00:59:55.703164
2564 00:59:55.705733 [CATrainingPosCal] consider 2 rank data
2565 00:59:55.709020 u2DelayCellTimex100 = 270/100 ps
2566 00:59:55.712382 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2567 00:59:55.716263 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2568 00:59:55.722652 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 00:59:55.726311 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2570 00:59:55.729335 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2571 00:59:55.732967 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2572 00:59:55.733553
2573 00:59:55.735989 CA PerBit enable=1, Macro0, CA PI delay=33
2574 00:59:55.736463
2575 00:59:55.739590 [CBTSetCACLKResult] CA Dly = 33
2576 00:59:55.740161 CS Dly: 7 (0~39)
2577 00:59:55.740537
2578 00:59:55.742539 ----->DramcWriteLeveling(PI) begin...
2579 00:59:55.743016 ==
2580 00:59:55.746791 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 00:59:55.752719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 00:59:55.753297 ==
2583 00:59:55.755625 Write leveling (Byte 0): 32 => 32
2584 00:59:55.759644 Write leveling (Byte 1): 30 => 30
2585 00:59:55.760223 DramcWriteLeveling(PI) end<-----
2586 00:59:55.762746
2587 00:59:55.763212 ==
2588 00:59:55.766064 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 00:59:55.769249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 00:59:55.769802 ==
2591 00:59:55.772678 [Gating] SW mode calibration
2592 00:59:55.779240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2593 00:59:55.783506 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2594 00:59:55.789192 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2595 00:59:55.792354 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2596 00:59:55.795882 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 00:59:55.802496 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 00:59:55.806194 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 00:59:55.809290 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 00:59:55.816471 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2601 00:59:55.819920 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2602 00:59:55.822622 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2603 00:59:55.829486 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 00:59:55.832793 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 00:59:55.836176 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 00:59:55.842453 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 00:59:55.846429 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 00:59:55.849602 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2609 00:59:55.852560 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2610 00:59:55.859613 1 1 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
2611 00:59:55.862819 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 00:59:55.866428 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 00:59:55.872888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 00:59:55.876681 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 00:59:55.879952 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 00:59:55.886551 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2617 00:59:55.890113 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2618 00:59:55.893006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2619 00:59:55.899904 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2620 00:59:55.902955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 00:59:55.906048 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 00:59:55.912776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 00:59:55.916242 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 00:59:55.919730 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 00:59:55.926388 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 00:59:55.929917 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 00:59:55.932701 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 00:59:55.936092 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 00:59:55.942686 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 00:59:55.946151 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 00:59:55.949614 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 00:59:55.956162 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2633 00:59:55.959594 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2634 00:59:55.962844 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2635 00:59:55.966390 Total UI for P1: 0, mck2ui 16
2636 00:59:55.970109 best dqsien dly found for B0: ( 1, 3, 26)
2637 00:59:55.976402 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 00:59:55.976981 Total UI for P1: 0, mck2ui 16
2639 00:59:55.983107 best dqsien dly found for B1: ( 1, 4, 0)
2640 00:59:55.986528 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2641 00:59:55.990155 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2642 00:59:55.990726
2643 00:59:55.993186 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2644 00:59:55.996661 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2645 00:59:56.000113 [Gating] SW calibration Done
2646 00:59:56.000689 ==
2647 00:59:56.003109 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 00:59:56.006649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 00:59:56.007240 ==
2650 00:59:56.007624 RX Vref Scan: 0
2651 00:59:56.010126
2652 00:59:56.010601 RX Vref 0 -> 0, step: 1
2653 00:59:56.010980
2654 00:59:56.013336 RX Delay -40 -> 252, step: 8
2655 00:59:56.016922 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2656 00:59:56.020436 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2657 00:59:56.026794 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2658 00:59:56.030025 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2659 00:59:56.033552 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2660 00:59:56.037121 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2661 00:59:56.040060 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2662 00:59:56.046657 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2663 00:59:56.049973 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2664 00:59:56.053464 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2665 00:59:56.056493 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2666 00:59:56.059976 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2667 00:59:56.066830 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2668 00:59:56.070220 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2669 00:59:56.073047 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2670 00:59:56.077020 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2671 00:59:56.077596 ==
2672 00:59:56.080081 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 00:59:56.083158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 00:59:56.086807 ==
2675 00:59:56.087380 DQS Delay:
2676 00:59:56.087757 DQS0 = 0, DQS1 = 0
2677 00:59:56.090457 DQM Delay:
2678 00:59:56.091031 DQM0 = 122, DQM1 = 110
2679 00:59:56.093164 DQ Delay:
2680 00:59:56.097031 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2681 00:59:56.100215 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2682 00:59:56.103584 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2683 00:59:56.106380 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2684 00:59:56.106857
2685 00:59:56.107234
2686 00:59:56.107584 ==
2687 00:59:56.109979 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 00:59:56.113491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 00:59:56.114015 ==
2690 00:59:56.114408
2691 00:59:56.114760
2692 00:59:56.116407 TX Vref Scan disable
2693 00:59:56.119807 == TX Byte 0 ==
2694 00:59:56.123469 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2695 00:59:56.126734 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2696 00:59:56.129863 == TX Byte 1 ==
2697 00:59:56.133574 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2698 00:59:56.136923 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2699 00:59:56.137497 ==
2700 00:59:56.140196 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 00:59:56.143597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 00:59:56.146811 ==
2703 00:59:56.157024 TX Vref=22, minBit 1, minWin=24, winSum=409
2704 00:59:56.160210 TX Vref=24, minBit 0, minWin=25, winSum=418
2705 00:59:56.163106 TX Vref=26, minBit 0, minWin=25, winSum=420
2706 00:59:56.166488 TX Vref=28, minBit 7, minWin=25, winSum=427
2707 00:59:56.170265 TX Vref=30, minBit 4, minWin=25, winSum=427
2708 00:59:56.173709 TX Vref=32, minBit 1, minWin=25, winSum=424
2709 00:59:56.179996 [TxChooseVref] Worse bit 7, Min win 25, Win sum 427, Final Vref 28
2710 00:59:56.180473
2711 00:59:56.183502 Final TX Range 1 Vref 28
2712 00:59:56.183977
2713 00:59:56.184352 ==
2714 00:59:56.186461 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 00:59:56.190041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 00:59:56.190514 ==
2717 00:59:56.190890
2718 00:59:56.193206
2719 00:59:56.193673 TX Vref Scan disable
2720 00:59:56.196661 == TX Byte 0 ==
2721 00:59:56.200069 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2722 00:59:56.203408 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2723 00:59:56.206561 == TX Byte 1 ==
2724 00:59:56.210338 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2725 00:59:56.213422 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2726 00:59:56.213879
2727 00:59:56.216745 [DATLAT]
2728 00:59:56.217271 Freq=1200, CH0 RK0
2729 00:59:56.217611
2730 00:59:56.220211 DATLAT Default: 0xd
2731 00:59:56.220631 0, 0xFFFF, sum = 0
2732 00:59:56.223314 1, 0xFFFF, sum = 0
2733 00:59:56.223753 2, 0xFFFF, sum = 0
2734 00:59:56.226517 3, 0xFFFF, sum = 0
2735 00:59:56.226945 4, 0xFFFF, sum = 0
2736 00:59:56.230179 5, 0xFFFF, sum = 0
2737 00:59:56.230639 6, 0xFFFF, sum = 0
2738 00:59:56.233617 7, 0xFFFF, sum = 0
2739 00:59:56.234198 8, 0xFFFF, sum = 0
2740 00:59:56.236620 9, 0xFFFF, sum = 0
2741 00:59:56.240007 10, 0xFFFF, sum = 0
2742 00:59:56.240647 11, 0xFFFF, sum = 0
2743 00:59:56.243404 12, 0x0, sum = 1
2744 00:59:56.243836 13, 0x0, sum = 2
2745 00:59:56.244177 14, 0x0, sum = 3
2746 00:59:56.246684 15, 0x0, sum = 4
2747 00:59:56.247111 best_step = 13
2748 00:59:56.247446
2749 00:59:56.250045 ==
2750 00:59:56.250466 Dram Type= 6, Freq= 0, CH_0, rank 0
2751 00:59:56.256800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2752 00:59:56.257231 ==
2753 00:59:56.257648 RX Vref Scan: 1
2754 00:59:56.258010
2755 00:59:56.260173 Set Vref Range= 32 -> 127
2756 00:59:56.260613
2757 00:59:56.263848 RX Vref 32 -> 127, step: 1
2758 00:59:56.264437
2759 00:59:56.266859 RX Delay -13 -> 252, step: 4
2760 00:59:56.267279
2761 00:59:56.269905 Set Vref, RX VrefLevel [Byte0]: 32
2762 00:59:56.273771 [Byte1]: 32
2763 00:59:56.274288
2764 00:59:56.276814 Set Vref, RX VrefLevel [Byte0]: 33
2765 00:59:56.280288 [Byte1]: 33
2766 00:59:56.280820
2767 00:59:56.283563 Set Vref, RX VrefLevel [Byte0]: 34
2768 00:59:56.286868 [Byte1]: 34
2769 00:59:56.290696
2770 00:59:56.291363 Set Vref, RX VrefLevel [Byte0]: 35
2771 00:59:56.293818 [Byte1]: 35
2772 00:59:56.298512
2773 00:59:56.298932 Set Vref, RX VrefLevel [Byte0]: 36
2774 00:59:56.301692 [Byte1]: 36
2775 00:59:56.306462
2776 00:59:56.307030 Set Vref, RX VrefLevel [Byte0]: 37
2777 00:59:56.309627 [Byte1]: 37
2778 00:59:56.314120
2779 00:59:56.314545 Set Vref, RX VrefLevel [Byte0]: 38
2780 00:59:56.317927 [Byte1]: 38
2781 00:59:56.322529
2782 00:59:56.323056 Set Vref, RX VrefLevel [Byte0]: 39
2783 00:59:56.325475 [Byte1]: 39
2784 00:59:56.330100
2785 00:59:56.330630 Set Vref, RX VrefLevel [Byte0]: 40
2786 00:59:56.333260 [Byte1]: 40
2787 00:59:56.338009
2788 00:59:56.338585 Set Vref, RX VrefLevel [Byte0]: 41
2789 00:59:56.341602 [Byte1]: 41
2790 00:59:56.346124
2791 00:59:56.346716 Set Vref, RX VrefLevel [Byte0]: 42
2792 00:59:56.349095 [Byte1]: 42
2793 00:59:56.353673
2794 00:59:56.354177 Set Vref, RX VrefLevel [Byte0]: 43
2795 00:59:56.357441 [Byte1]: 43
2796 00:59:56.361598
2797 00:59:56.362108 Set Vref, RX VrefLevel [Byte0]: 44
2798 00:59:56.365275 [Byte1]: 44
2799 00:59:56.369543
2800 00:59:56.370058 Set Vref, RX VrefLevel [Byte0]: 45
2801 00:59:56.372962 [Byte1]: 45
2802 00:59:56.377396
2803 00:59:56.378008 Set Vref, RX VrefLevel [Byte0]: 46
2804 00:59:56.380743 [Byte1]: 46
2805 00:59:56.385681
2806 00:59:56.386300 Set Vref, RX VrefLevel [Byte0]: 47
2807 00:59:56.388553 [Byte1]: 47
2808 00:59:56.393301
2809 00:59:56.393807 Set Vref, RX VrefLevel [Byte0]: 48
2810 00:59:56.396650 [Byte1]: 48
2811 00:59:56.401169
2812 00:59:56.401639 Set Vref, RX VrefLevel [Byte0]: 49
2813 00:59:56.404494 [Byte1]: 49
2814 00:59:56.409184
2815 00:59:56.409520 Set Vref, RX VrefLevel [Byte0]: 50
2816 00:59:56.412198 [Byte1]: 50
2817 00:59:56.416721
2818 00:59:56.416920 Set Vref, RX VrefLevel [Byte0]: 51
2819 00:59:56.420190 [Byte1]: 51
2820 00:59:56.424784
2821 00:59:56.425011 Set Vref, RX VrefLevel [Byte0]: 52
2822 00:59:56.428211 [Byte1]: 52
2823 00:59:56.432826
2824 00:59:56.432988 Set Vref, RX VrefLevel [Byte0]: 53
2825 00:59:56.435947 [Byte1]: 53
2826 00:59:56.440494
2827 00:59:56.440744 Set Vref, RX VrefLevel [Byte0]: 54
2828 00:59:56.443496 [Byte1]: 54
2829 00:59:56.448471
2830 00:59:56.448957 Set Vref, RX VrefLevel [Byte0]: 55
2831 00:59:56.452111 [Byte1]: 55
2832 00:59:56.456517
2833 00:59:56.456995 Set Vref, RX VrefLevel [Byte0]: 56
2834 00:59:56.459671 [Byte1]: 56
2835 00:59:56.464286
2836 00:59:56.464892 Set Vref, RX VrefLevel [Byte0]: 57
2837 00:59:56.467845 [Byte1]: 57
2838 00:59:56.472132
2839 00:59:56.472777 Set Vref, RX VrefLevel [Byte0]: 58
2840 00:59:56.475633 [Byte1]: 58
2841 00:59:56.479974
2842 00:59:56.480701 Set Vref, RX VrefLevel [Byte0]: 59
2843 00:59:56.483389 [Byte1]: 59
2844 00:59:56.487909
2845 00:59:56.488477 Set Vref, RX VrefLevel [Byte0]: 60
2846 00:59:56.491141 [Byte1]: 60
2847 00:59:56.495942
2848 00:59:56.496214 Set Vref, RX VrefLevel [Byte0]: 61
2849 00:59:56.498911 [Byte1]: 61
2850 00:59:56.503191
2851 00:59:56.503384 Set Vref, RX VrefLevel [Byte0]: 62
2852 00:59:56.506657 [Byte1]: 62
2853 00:59:56.511174
2854 00:59:56.511313 Set Vref, RX VrefLevel [Byte0]: 63
2855 00:59:56.514609 [Byte1]: 63
2856 00:59:56.519097
2857 00:59:56.519233 Set Vref, RX VrefLevel [Byte0]: 64
2858 00:59:56.522823 [Byte1]: 64
2859 00:59:56.527740
2860 00:59:56.527978 Set Vref, RX VrefLevel [Byte0]: 65
2861 00:59:56.530389 [Byte1]: 65
2862 00:59:56.535006
2863 00:59:56.535230 Set Vref, RX VrefLevel [Byte0]: 66
2864 00:59:56.538297 [Byte1]: 66
2865 00:59:56.542967
2866 00:59:56.543229 Set Vref, RX VrefLevel [Byte0]: 67
2867 00:59:56.546322 [Byte1]: 67
2868 00:59:56.550780
2869 00:59:56.551119 Set Vref, RX VrefLevel [Byte0]: 68
2870 00:59:56.554142 [Byte1]: 68
2871 00:59:56.558622
2872 00:59:56.558920 Set Vref, RX VrefLevel [Byte0]: 69
2873 00:59:56.562049 [Byte1]: 69
2874 00:59:56.566636
2875 00:59:56.567101 Set Vref, RX VrefLevel [Byte0]: 70
2876 00:59:56.570645 [Byte1]: 70
2877 00:59:56.574840
2878 00:59:56.575309 Set Vref, RX VrefLevel [Byte0]: 71
2879 00:59:56.578721 [Byte1]: 71
2880 00:59:56.583098
2881 00:59:56.583679 Final RX Vref Byte 0 = 60 to rank0
2882 00:59:56.586312 Final RX Vref Byte 1 = 50 to rank0
2883 00:59:56.589516 Final RX Vref Byte 0 = 60 to rank1
2884 00:59:56.592898 Final RX Vref Byte 1 = 50 to rank1==
2885 00:59:56.596326 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 00:59:56.599638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 00:59:56.602864 ==
2888 00:59:56.603442 DQS Delay:
2889 00:59:56.603817 DQS0 = 0, DQS1 = 0
2890 00:59:56.605922 DQM Delay:
2891 00:59:56.606423 DQM0 = 123, DQM1 = 109
2892 00:59:56.609430 DQ Delay:
2893 00:59:56.612541 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2894 00:59:56.615831 DQ4 =126, DQ5 =116, DQ6 =132, DQ7 =128
2895 00:59:56.619112 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2896 00:59:56.622463 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2897 00:59:56.622936
2898 00:59:56.623312
2899 00:59:56.629611 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2900 00:59:56.632899 CH0 RK0: MR19=404, MR18=804
2901 00:59:56.639685 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2902 00:59:56.640268
2903 00:59:56.642826 ----->DramcWriteLeveling(PI) begin...
2904 00:59:56.643412 ==
2905 00:59:56.646054 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 00:59:56.649576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 00:59:56.650198 ==
2908 00:59:56.653024 Write leveling (Byte 0): 35 => 35
2909 00:59:56.656246 Write leveling (Byte 1): 31 => 31
2910 00:59:56.659815 DramcWriteLeveling(PI) end<-----
2911 00:59:56.660435
2912 00:59:56.660820 ==
2913 00:59:56.663053 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 00:59:56.666366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 00:59:56.669509 ==
2916 00:59:56.670125 [Gating] SW mode calibration
2917 00:59:56.679924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 00:59:56.683135 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 00:59:56.686772 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2920 00:59:56.693195 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 00:59:56.696071 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 00:59:56.699512 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 00:59:56.706610 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 00:59:56.709578 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 00:59:56.712885 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 00:59:56.719742 0 15 28 | B1->B0 | 2d2d 2c2c | 0 0 | (1 0) (0 1)
2927 00:59:56.722627 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2928 00:59:56.726402 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 00:59:56.729905 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 00:59:56.736271 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 00:59:56.739495 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 00:59:56.742815 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 00:59:56.749637 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 00:59:56.752961 1 0 28 | B1->B0 | 3737 3e3e | 1 1 | (0 0) (0 0)
2935 00:59:56.756225 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 00:59:56.762960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 00:59:56.766187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 00:59:56.769619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 00:59:56.776027 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 00:59:56.779276 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 00:59:56.782693 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 00:59:56.789990 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 00:59:56.792822 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2944 00:59:56.795910 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 00:59:56.802770 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 00:59:56.806150 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 00:59:56.810023 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 00:59:56.816379 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 00:59:56.819784 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 00:59:56.822818 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 00:59:56.829799 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 00:59:56.833310 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 00:59:56.836515 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:59:56.839770 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:59:56.846476 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:59:56.849806 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:59:56.853106 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:59:56.859579 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2959 00:59:56.862936 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 00:59:56.866374 Total UI for P1: 0, mck2ui 16
2961 00:59:56.869667 best dqsien dly found for B0: ( 1, 3, 28)
2962 00:59:56.872947 Total UI for P1: 0, mck2ui 16
2963 00:59:56.876048 best dqsien dly found for B1: ( 1, 3, 30)
2964 00:59:56.880172 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2965 00:59:56.882791 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2966 00:59:56.883264
2967 00:59:56.886373 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2968 00:59:56.889719 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2969 00:59:56.893398 [Gating] SW calibration Done
2970 00:59:56.894068 ==
2971 00:59:56.896406 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 00:59:56.899733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 00:59:56.903434 ==
2974 00:59:56.904021 RX Vref Scan: 0
2975 00:59:56.904406
2976 00:59:56.906657 RX Vref 0 -> 0, step: 1
2977 00:59:56.907129
2978 00:59:56.907506 RX Delay -40 -> 252, step: 8
2979 00:59:56.913119 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2980 00:59:56.916459 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2981 00:59:56.920275 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2982 00:59:56.923244 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2983 00:59:56.926411 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2984 00:59:56.933484 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2985 00:59:56.936603 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2986 00:59:56.940432 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2987 00:59:56.943026 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2988 00:59:56.947375 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2989 00:59:56.953381 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2990 00:59:56.956230 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2991 00:59:56.959811 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2992 00:59:56.963042 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2993 00:59:56.966464 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2994 00:59:56.973289 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2995 00:59:56.973870 ==
2996 00:59:56.976183 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 00:59:56.979936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 00:59:56.980520 ==
2999 00:59:56.980903 DQS Delay:
3000 00:59:56.983679 DQS0 = 0, DQS1 = 0
3001 00:59:56.984258 DQM Delay:
3002 00:59:56.986603 DQM0 = 120, DQM1 = 108
3003 00:59:56.987200 DQ Delay:
3004 00:59:56.989933 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3005 00:59:56.993183 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3006 00:59:56.996162 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3007 00:59:56.999706 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3008 00:59:57.000183
3009 00:59:57.000559
3010 00:59:57.002899 ==
3011 00:59:57.006616 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 00:59:57.009660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 00:59:57.010176 ==
3014 00:59:57.010559
3015 00:59:57.010909
3016 00:59:57.013241 TX Vref Scan disable
3017 00:59:57.013711 == TX Byte 0 ==
3018 00:59:57.016223 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3019 00:59:57.023069 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3020 00:59:57.023631 == TX Byte 1 ==
3021 00:59:57.026573 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3022 00:59:57.033375 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3023 00:59:57.033989 ==
3024 00:59:57.036676 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 00:59:57.039693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 00:59:57.040271 ==
3027 00:59:57.052165 TX Vref=22, minBit 3, minWin=24, winSum=410
3028 00:59:57.055354 TX Vref=24, minBit 4, minWin=24, winSum=415
3029 00:59:57.058714 TX Vref=26, minBit 3, minWin=25, winSum=422
3030 00:59:57.062329 TX Vref=28, minBit 3, minWin=24, winSum=421
3031 00:59:57.065197 TX Vref=30, minBit 0, minWin=25, winSum=422
3032 00:59:57.068647 TX Vref=32, minBit 2, minWin=25, winSum=426
3033 00:59:57.075388 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 32
3034 00:59:57.075966
3035 00:59:57.079065 Final TX Range 1 Vref 32
3036 00:59:57.079642
3037 00:59:57.080020 ==
3038 00:59:57.081975 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 00:59:57.085310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 00:59:57.085886 ==
3041 00:59:57.086308
3042 00:59:57.088669
3043 00:59:57.089237 TX Vref Scan disable
3044 00:59:57.092294 == TX Byte 0 ==
3045 00:59:57.095356 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3046 00:59:57.098922 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3047 00:59:57.101680 == TX Byte 1 ==
3048 00:59:57.105714 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3049 00:59:57.108952 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3050 00:59:57.109430
3051 00:59:57.111872 [DATLAT]
3052 00:59:57.112347 Freq=1200, CH0 RK1
3053 00:59:57.112725
3054 00:59:57.115239 DATLAT Default: 0xd
3055 00:59:57.115882 0, 0xFFFF, sum = 0
3056 00:59:57.118679 1, 0xFFFF, sum = 0
3057 00:59:57.119157 2, 0xFFFF, sum = 0
3058 00:59:57.122212 3, 0xFFFF, sum = 0
3059 00:59:57.122780 4, 0xFFFF, sum = 0
3060 00:59:57.125409 5, 0xFFFF, sum = 0
3061 00:59:57.126014 6, 0xFFFF, sum = 0
3062 00:59:57.128713 7, 0xFFFF, sum = 0
3063 00:59:57.129136 8, 0xFFFF, sum = 0
3064 00:59:57.132091 9, 0xFFFF, sum = 0
3065 00:59:57.132570 10, 0xFFFF, sum = 0
3066 00:59:57.135576 11, 0xFFFF, sum = 0
3067 00:59:57.136145 12, 0x0, sum = 1
3068 00:59:57.138729 13, 0x0, sum = 2
3069 00:59:57.139214 14, 0x0, sum = 3
3070 00:59:57.142200 15, 0x0, sum = 4
3071 00:59:57.142773 best_step = 13
3072 00:59:57.143154
3073 00:59:57.143506 ==
3074 00:59:57.145590 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 00:59:57.151987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 00:59:57.152557 ==
3077 00:59:57.152938 RX Vref Scan: 0
3078 00:59:57.153294
3079 00:59:57.155441 RX Vref 0 -> 0, step: 1
3080 00:59:57.156002
3081 00:59:57.158559 RX Delay -21 -> 252, step: 4
3082 00:59:57.162147 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3083 00:59:57.165646 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3084 00:59:57.172221 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3085 00:59:57.175682 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3086 00:59:57.179165 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3087 00:59:57.182259 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3088 00:59:57.185645 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3089 00:59:57.188939 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3090 00:59:57.195464 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3091 00:59:57.199428 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3092 00:59:57.202588 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3093 00:59:57.205818 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3094 00:59:57.209188 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3095 00:59:57.215627 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3096 00:59:57.218816 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3097 00:59:57.222232 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3098 00:59:57.222712 ==
3099 00:59:57.225607 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 00:59:57.229162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 00:59:57.229736 ==
3102 00:59:57.232573 DQS Delay:
3103 00:59:57.233142 DQS0 = 0, DQS1 = 0
3104 00:59:57.235919 DQM Delay:
3105 00:59:57.236487 DQM0 = 119, DQM1 = 108
3106 00:59:57.239399 DQ Delay:
3107 00:59:57.242493 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3108 00:59:57.246250 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3109 00:59:57.249017 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3110 00:59:57.252751 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3111 00:59:57.253326
3112 00:59:57.253703
3113 00:59:57.259165 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3114 00:59:57.262584 CH0 RK1: MR19=403, MR18=11F8
3115 00:59:57.269408 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3116 00:59:57.272493 [RxdqsGatingPostProcess] freq 1200
3117 00:59:57.275627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3118 00:59:57.279764 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 00:59:57.283043 best DQS1 dly(2T, 0.5T) = (0, 12)
3120 00:59:57.286025 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 00:59:57.289486 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3122 00:59:57.292902 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 00:59:57.296047 best DQS1 dly(2T, 0.5T) = (0, 11)
3124 00:59:57.299372 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 00:59:57.302785 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3126 00:59:57.305749 Pre-setting of DQS Precalculation
3127 00:59:57.309273 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3128 00:59:57.309843 ==
3129 00:59:57.312598 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 00:59:57.319744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 00:59:57.320221 ==
3132 00:59:57.323304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 00:59:57.329645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3134 00:59:57.338373 [CA 0] Center 37 (7~68) winsize 62
3135 00:59:57.341659 [CA 1] Center 37 (7~68) winsize 62
3136 00:59:57.344675 [CA 2] Center 35 (5~65) winsize 61
3137 00:59:57.348495 [CA 3] Center 34 (4~65) winsize 62
3138 00:59:57.351768 [CA 4] Center 33 (3~64) winsize 62
3139 00:59:57.354573 [CA 5] Center 33 (3~64) winsize 62
3140 00:59:57.355045
3141 00:59:57.357993 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3142 00:59:57.358467
3143 00:59:57.361325 [CATrainingPosCal] consider 1 rank data
3144 00:59:57.364819 u2DelayCellTimex100 = 270/100 ps
3145 00:59:57.368519 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 00:59:57.371777 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 00:59:57.375241 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3148 00:59:57.381575 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3149 00:59:57.384805 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3150 00:59:57.388929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 00:59:57.389497
3152 00:59:57.391337 CA PerBit enable=1, Macro0, CA PI delay=33
3153 00:59:57.391807
3154 00:59:57.395079 [CBTSetCACLKResult] CA Dly = 33
3155 00:59:57.395665 CS Dly: 5 (0~36)
3156 00:59:57.396049 ==
3157 00:59:57.397903 Dram Type= 6, Freq= 0, CH_1, rank 1
3158 00:59:57.405046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 00:59:57.405619 ==
3160 00:59:57.408348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3161 00:59:57.414722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3162 00:59:57.423638 [CA 0] Center 38 (8~68) winsize 61
3163 00:59:57.426620 [CA 1] Center 38 (7~69) winsize 63
3164 00:59:57.430424 [CA 2] Center 35 (5~66) winsize 62
3165 00:59:57.433398 [CA 3] Center 35 (5~65) winsize 61
3166 00:59:57.436847 [CA 4] Center 35 (5~65) winsize 61
3167 00:59:57.440684 [CA 5] Center 34 (4~64) winsize 61
3168 00:59:57.441253
3169 00:59:57.443950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3170 00:59:57.444520
3171 00:59:57.446793 [CATrainingPosCal] consider 2 rank data
3172 00:59:57.450133 u2DelayCellTimex100 = 270/100 ps
3173 00:59:57.453735 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3174 00:59:57.456793 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3175 00:59:57.463672 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3176 00:59:57.467240 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3177 00:59:57.470467 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3178 00:59:57.473809 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3179 00:59:57.474424
3180 00:59:57.477246 CA PerBit enable=1, Macro0, CA PI delay=34
3181 00:59:57.477817
3182 00:59:57.480350 [CBTSetCACLKResult] CA Dly = 34
3183 00:59:57.480919 CS Dly: 6 (0~39)
3184 00:59:57.481300
3185 00:59:57.483756 ----->DramcWriteLeveling(PI) begin...
3186 00:59:57.487243 ==
3187 00:59:57.487816 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 00:59:57.493667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 00:59:57.494276 ==
3190 00:59:57.497116 Write leveling (Byte 0): 25 => 25
3191 00:59:57.500408 Write leveling (Byte 1): 30 => 30
3192 00:59:57.503894 DramcWriteLeveling(PI) end<-----
3193 00:59:57.504465
3194 00:59:57.504840 ==
3195 00:59:57.506762 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 00:59:57.510387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 00:59:57.510961 ==
3198 00:59:57.513630 [Gating] SW mode calibration
3199 00:59:57.520220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3200 00:59:57.523542 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3201 00:59:57.529999 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 00:59:57.533801 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 00:59:57.536902 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 00:59:57.543788 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 00:59:57.547340 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 00:59:57.550327 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 00:59:57.556959 0 15 24 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (1 0)
3208 00:59:57.560347 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 00:59:57.563953 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 00:59:57.570869 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 00:59:57.573388 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 00:59:57.576950 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 00:59:57.583726 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 00:59:57.587202 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3215 00:59:57.590572 1 0 24 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
3216 00:59:57.597276 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 00:59:57.600268 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 00:59:57.603838 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 00:59:57.607332 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 00:59:57.613814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 00:59:57.617100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 00:59:57.620464 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3223 00:59:57.626874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3224 00:59:57.630398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3225 00:59:57.633503 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 00:59:57.640408 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 00:59:57.643502 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 00:59:57.646779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 00:59:57.653996 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 00:59:57.657208 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 00:59:57.660293 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 00:59:57.667398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 00:59:57.670324 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 00:59:57.673529 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 00:59:57.680817 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:59:57.684068 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:59:57.687465 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:59:57.690713 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:59:57.697546 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 00:59:57.700737 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3241 00:59:57.704236 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 00:59:57.707533 Total UI for P1: 0, mck2ui 16
3243 00:59:57.710719 best dqsien dly found for B0: ( 1, 3, 26)
3244 00:59:57.714182 Total UI for P1: 0, mck2ui 16
3245 00:59:57.717835 best dqsien dly found for B1: ( 1, 3, 26)
3246 00:59:57.720562 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3247 00:59:57.724204 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3248 00:59:57.724770
3249 00:59:57.730554 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3250 00:59:57.734012 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3251 00:59:57.737269 [Gating] SW calibration Done
3252 00:59:57.737836 ==
3253 00:59:57.740659 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 00:59:57.743961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 00:59:57.744534 ==
3256 00:59:57.744913 RX Vref Scan: 0
3257 00:59:57.745261
3258 00:59:57.747044 RX Vref 0 -> 0, step: 1
3259 00:59:57.747510
3260 00:59:57.750609 RX Delay -40 -> 252, step: 8
3261 00:59:57.754083 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3262 00:59:57.757336 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3263 00:59:57.760491 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3264 00:59:57.767503 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3265 00:59:57.770548 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3266 00:59:57.773795 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3267 00:59:57.777389 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3268 00:59:57.780403 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3269 00:59:57.787543 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3270 00:59:57.790548 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3271 00:59:57.794110 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3272 00:59:57.797497 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3273 00:59:57.800626 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3274 00:59:57.807170 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3275 00:59:57.810684 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3276 00:59:57.813628 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3277 00:59:57.814155 ==
3278 00:59:57.817087 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 00:59:57.820794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 00:59:57.821379 ==
3281 00:59:57.824134 DQS Delay:
3282 00:59:57.824719 DQS0 = 0, DQS1 = 0
3283 00:59:57.827378 DQM Delay:
3284 00:59:57.827962 DQM0 = 120, DQM1 = 113
3285 00:59:57.830620 DQ Delay:
3286 00:59:57.833674 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3287 00:59:57.837320 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3288 00:59:57.841128 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3289 00:59:57.843999 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3290 00:59:57.844585
3291 00:59:57.844966
3292 00:59:57.845314 ==
3293 00:59:57.847198 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 00:59:57.850586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 00:59:57.851066 ==
3296 00:59:57.851446
3297 00:59:57.851796
3298 00:59:57.854102 TX Vref Scan disable
3299 00:59:57.857161 == TX Byte 0 ==
3300 00:59:57.860443 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 00:59:57.863948 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 00:59:57.867241 == TX Byte 1 ==
3303 00:59:57.870806 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3304 00:59:57.874180 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3305 00:59:57.874773 ==
3306 00:59:57.877437 Dram Type= 6, Freq= 0, CH_1, rank 0
3307 00:59:57.880699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3308 00:59:57.881285 ==
3309 00:59:57.894051 TX Vref=22, minBit 1, minWin=25, winSum=407
3310 00:59:57.897523 TX Vref=24, minBit 1, minWin=24, winSum=412
3311 00:59:57.900383 TX Vref=26, minBit 11, minWin=25, winSum=420
3312 00:59:57.903784 TX Vref=28, minBit 2, minWin=25, winSum=418
3313 00:59:57.907232 TX Vref=30, minBit 11, minWin=25, winSum=425
3314 00:59:57.913693 TX Vref=32, minBit 1, minWin=26, winSum=425
3315 00:59:57.916968 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 32
3316 00:59:57.917454
3317 00:59:57.920529 Final TX Range 1 Vref 32
3318 00:59:57.921005
3319 00:59:57.921378 ==
3320 00:59:57.923567 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 00:59:57.927336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 00:59:57.927940 ==
3323 00:59:57.930126
3324 00:59:57.930601
3325 00:59:57.930976 TX Vref Scan disable
3326 00:59:57.934310 == TX Byte 0 ==
3327 00:59:57.937083 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3328 00:59:57.940569 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3329 00:59:57.944252 == TX Byte 1 ==
3330 00:59:57.947341 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3331 00:59:57.950674 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3332 00:59:57.953716
3333 00:59:57.954299 [DATLAT]
3334 00:59:57.954868 Freq=1200, CH1 RK0
3335 00:59:57.955256
3336 00:59:57.957177 DATLAT Default: 0xd
3337 00:59:57.957648 0, 0xFFFF, sum = 0
3338 00:59:57.960505 1, 0xFFFF, sum = 0
3339 00:59:57.960992 2, 0xFFFF, sum = 0
3340 00:59:57.963716 3, 0xFFFF, sum = 0
3341 00:59:57.964206 4, 0xFFFF, sum = 0
3342 00:59:57.967100 5, 0xFFFF, sum = 0
3343 00:59:57.967579 6, 0xFFFF, sum = 0
3344 00:59:57.970801 7, 0xFFFF, sum = 0
3345 00:59:57.974432 8, 0xFFFF, sum = 0
3346 00:59:57.975014 9, 0xFFFF, sum = 0
3347 00:59:57.977108 10, 0xFFFF, sum = 0
3348 00:59:57.977587 11, 0xFFFF, sum = 0
3349 00:59:57.980457 12, 0x0, sum = 1
3350 00:59:57.980933 13, 0x0, sum = 2
3351 00:59:57.983691 14, 0x0, sum = 3
3352 00:59:57.984172 15, 0x0, sum = 4
3353 00:59:57.984552 best_step = 13
3354 00:59:57.984900
3355 00:59:57.986878 ==
3356 00:59:57.990323 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 00:59:57.994717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 00:59:57.995296 ==
3359 00:59:57.995674 RX Vref Scan: 1
3360 00:59:57.996018
3361 00:59:57.997296 Set Vref Range= 32 -> 127
3362 00:59:57.997753
3363 00:59:58.000436 RX Vref 32 -> 127, step: 1
3364 00:59:58.000894
3365 00:59:58.003633 RX Delay -13 -> 252, step: 4
3366 00:59:58.004091
3367 00:59:58.007367 Set Vref, RX VrefLevel [Byte0]: 32
3368 00:59:58.010445 [Byte1]: 32
3369 00:59:58.010905
3370 00:59:58.013917 Set Vref, RX VrefLevel [Byte0]: 33
3371 00:59:58.017003 [Byte1]: 33
3372 00:59:58.017594
3373 00:59:58.020568 Set Vref, RX VrefLevel [Byte0]: 34
3374 00:59:58.024064 [Byte1]: 34
3375 00:59:58.028221
3376 00:59:58.028643 Set Vref, RX VrefLevel [Byte0]: 35
3377 00:59:58.031453 [Byte1]: 35
3378 00:59:58.036357
3379 00:59:58.036792 Set Vref, RX VrefLevel [Byte0]: 36
3380 00:59:58.038978 [Byte1]: 36
3381 00:59:58.043816
3382 00:59:58.044234 Set Vref, RX VrefLevel [Byte0]: 37
3383 00:59:58.047066 [Byte1]: 37
3384 00:59:58.051638
3385 00:59:58.052061 Set Vref, RX VrefLevel [Byte0]: 38
3386 00:59:58.054834 [Byte1]: 38
3387 00:59:58.059620
3388 00:59:58.060037 Set Vref, RX VrefLevel [Byte0]: 39
3389 00:59:58.063180 [Byte1]: 39
3390 00:59:58.067431
3391 00:59:58.067997 Set Vref, RX VrefLevel [Byte0]: 40
3392 00:59:58.070755 [Byte1]: 40
3393 00:59:58.075502
3394 00:59:58.076059 Set Vref, RX VrefLevel [Byte0]: 41
3395 00:59:58.078680 [Byte1]: 41
3396 00:59:58.083185
3397 00:59:58.083739 Set Vref, RX VrefLevel [Byte0]: 42
3398 00:59:58.086835 [Byte1]: 42
3399 00:59:58.090973
3400 00:59:58.091531 Set Vref, RX VrefLevel [Byte0]: 43
3401 00:59:58.094592 [Byte1]: 43
3402 00:59:58.099085
3403 00:59:58.099540 Set Vref, RX VrefLevel [Byte0]: 44
3404 00:59:58.102310 [Byte1]: 44
3405 00:59:58.106888
3406 00:59:58.107446 Set Vref, RX VrefLevel [Byte0]: 45
3407 00:59:58.110111 [Byte1]: 45
3408 00:59:58.114773
3409 00:59:58.115506 Set Vref, RX VrefLevel [Byte0]: 46
3410 00:59:58.118225 [Byte1]: 46
3411 00:59:58.122908
3412 00:59:58.123470 Set Vref, RX VrefLevel [Byte0]: 47
3413 00:59:58.126244 [Byte1]: 47
3414 00:59:58.130783
3415 00:59:58.131336 Set Vref, RX VrefLevel [Byte0]: 48
3416 00:59:58.133830 [Byte1]: 48
3417 00:59:58.138651
3418 00:59:58.139213 Set Vref, RX VrefLevel [Byte0]: 49
3419 00:59:58.142075 [Byte1]: 49
3420 00:59:58.146424
3421 00:59:58.146980 Set Vref, RX VrefLevel [Byte0]: 50
3422 00:59:58.149875 [Byte1]: 50
3423 00:59:58.154401
3424 00:59:58.154956 Set Vref, RX VrefLevel [Byte0]: 51
3425 00:59:58.157640 [Byte1]: 51
3426 00:59:58.162229
3427 00:59:58.162783 Set Vref, RX VrefLevel [Byte0]: 52
3428 00:59:58.165419 [Byte1]: 52
3429 00:59:58.170156
3430 00:59:58.170710 Set Vref, RX VrefLevel [Byte0]: 53
3431 00:59:58.173537 [Byte1]: 53
3432 00:59:58.178304
3433 00:59:58.178858 Set Vref, RX VrefLevel [Byte0]: 54
3434 00:59:58.181196 [Byte1]: 54
3435 00:59:58.185816
3436 00:59:58.186316 Set Vref, RX VrefLevel [Byte0]: 55
3437 00:59:58.189073 [Byte1]: 55
3438 00:59:58.193632
3439 00:59:58.194245 Set Vref, RX VrefLevel [Byte0]: 56
3440 00:59:58.197281 [Byte1]: 56
3441 00:59:58.201564
3442 00:59:58.202169 Set Vref, RX VrefLevel [Byte0]: 57
3443 00:59:58.205262 [Byte1]: 57
3444 00:59:58.209623
3445 00:59:58.210249 Set Vref, RX VrefLevel [Byte0]: 58
3446 00:59:58.213042 [Byte1]: 58
3447 00:59:58.217171
3448 00:59:58.217810 Set Vref, RX VrefLevel [Byte0]: 59
3449 00:59:58.220661 [Byte1]: 59
3450 00:59:58.225381
3451 00:59:58.225982 Set Vref, RX VrefLevel [Byte0]: 60
3452 00:59:58.228823 [Byte1]: 60
3453 00:59:58.233256
3454 00:59:58.233828 Set Vref, RX VrefLevel [Byte0]: 61
3455 00:59:58.236424 [Byte1]: 61
3456 00:59:58.240981
3457 00:59:58.241545 Set Vref, RX VrefLevel [Byte0]: 62
3458 00:59:58.244660 [Byte1]: 62
3459 00:59:58.249106
3460 00:59:58.249680 Set Vref, RX VrefLevel [Byte0]: 63
3461 00:59:58.252420 [Byte1]: 63
3462 00:59:58.256860
3463 00:59:58.257329 Set Vref, RX VrefLevel [Byte0]: 64
3464 00:59:58.260272 [Byte1]: 64
3465 00:59:58.264843
3466 00:59:58.265409 Set Vref, RX VrefLevel [Byte0]: 65
3467 00:59:58.268068 [Byte1]: 65
3468 00:59:58.272777
3469 00:59:58.273344 Set Vref, RX VrefLevel [Byte0]: 66
3470 00:59:58.275549 [Byte1]: 66
3471 00:59:58.280805
3472 00:59:58.281389 Set Vref, RX VrefLevel [Byte0]: 67
3473 00:59:58.283564 [Byte1]: 67
3474 00:59:58.288303
3475 00:59:58.288882 Set Vref, RX VrefLevel [Byte0]: 68
3476 00:59:58.291427 [Byte1]: 68
3477 00:59:58.296328
3478 00:59:58.296903 Final RX Vref Byte 0 = 51 to rank0
3479 00:59:58.299838 Final RX Vref Byte 1 = 52 to rank0
3480 00:59:58.303183 Final RX Vref Byte 0 = 51 to rank1
3481 00:59:58.306258 Final RX Vref Byte 1 = 52 to rank1==
3482 00:59:58.309440 Dram Type= 6, Freq= 0, CH_1, rank 0
3483 00:59:58.312879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 00:59:58.316173 ==
3485 00:59:58.316694 DQS Delay:
3486 00:59:58.317070 DQS0 = 0, DQS1 = 0
3487 00:59:58.319658 DQM Delay:
3488 00:59:58.320127 DQM0 = 119, DQM1 = 112
3489 00:59:58.323025 DQ Delay:
3490 00:59:58.326499 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3491 00:59:58.330081 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3492 00:59:58.333302 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3493 00:59:58.337082 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =116
3494 00:59:58.337658
3495 00:59:58.338081
3496 00:59:58.343587 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3497 00:59:58.346629 CH1 RK0: MR19=404, MR18=215
3498 00:59:58.353561 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3499 00:59:58.354162
3500 00:59:58.356397 ----->DramcWriteLeveling(PI) begin...
3501 00:59:58.356892 ==
3502 00:59:58.359957 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 00:59:58.363725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 00:59:58.364299 ==
3505 00:59:58.366641 Write leveling (Byte 0): 25 => 25
3506 00:59:58.370077 Write leveling (Byte 1): 29 => 29
3507 00:59:58.373345 DramcWriteLeveling(PI) end<-----
3508 00:59:58.373916
3509 00:59:58.374355 ==
3510 00:59:58.376746 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 00:59:58.380014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 00:59:58.383330 ==
3513 00:59:58.383899 [Gating] SW mode calibration
3514 00:59:58.390116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3515 00:59:58.396682 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3516 00:59:58.399957 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 00:59:58.406871 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 00:59:58.409882 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 00:59:58.413324 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 00:59:58.419755 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 00:59:58.423313 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3522 00:59:58.426498 0 15 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 0)
3523 00:59:58.433262 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3524 00:59:58.436830 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 00:59:58.439928 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 00:59:58.442991 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 00:59:58.450203 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 00:59:58.453275 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 00:59:58.456317 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3530 00:59:58.463062 1 0 24 | B1->B0 | 3e3e 3232 | 0 1 | (0 0) (0 0)
3531 00:59:58.466880 1 0 28 | B1->B0 | 4646 3e3e | 0 1 | (0 0) (0 0)
3532 00:59:58.469869 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 00:59:58.476707 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 00:59:58.480137 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 00:59:58.483458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 00:59:58.490032 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 00:59:58.493424 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 00:59:58.496335 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3539 00:59:58.503082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3540 00:59:58.506272 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 00:59:58.509892 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 00:59:58.516153 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 00:59:58.519346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 00:59:58.523168 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 00:59:58.530014 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 00:59:58.533203 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 00:59:58.536367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 00:59:58.542877 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 00:59:58.546046 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 00:59:58.549502 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 00:59:58.556211 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 00:59:58.559456 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 00:59:58.562854 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 00:59:58.569346 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3555 00:59:58.573108 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3556 00:59:58.576282 Total UI for P1: 0, mck2ui 16
3557 00:59:58.580034 best dqsien dly found for B0: ( 1, 3, 24)
3558 00:59:58.583314 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 00:59:58.586192 Total UI for P1: 0, mck2ui 16
3560 00:59:58.589652 best dqsien dly found for B1: ( 1, 3, 26)
3561 00:59:58.593008 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3562 00:59:58.595968 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3563 00:59:58.596446
3564 00:59:58.599294 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3565 00:59:58.602964 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3566 00:59:58.605874 [Gating] SW calibration Done
3567 00:59:58.606401 ==
3568 00:59:58.609583 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 00:59:58.615852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 00:59:58.616420 ==
3571 00:59:58.616801 RX Vref Scan: 0
3572 00:59:58.617187
3573 00:59:58.619084 RX Vref 0 -> 0, step: 1
3574 00:59:58.619769
3575 00:59:58.622348 RX Delay -40 -> 252, step: 8
3576 00:59:58.625766 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3577 00:59:58.629374 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3578 00:59:58.632888 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3579 00:59:58.635973 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3580 00:59:58.642611 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3581 00:59:58.645991 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3582 00:59:58.649298 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3583 00:59:58.652841 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3584 00:59:58.655952 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3585 00:59:58.662822 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3586 00:59:58.666000 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3587 00:59:58.669737 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3588 00:59:58.672610 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3589 00:59:58.675982 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3590 00:59:58.682516 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3591 00:59:58.686160 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3592 00:59:58.686742 ==
3593 00:59:58.689222 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 00:59:58.692730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 00:59:58.693317 ==
3596 00:59:58.695944 DQS Delay:
3597 00:59:58.696529 DQS0 = 0, DQS1 = 0
3598 00:59:58.696907 DQM Delay:
3599 00:59:58.699149 DQM0 = 120, DQM1 = 112
3600 00:59:58.699731 DQ Delay:
3601 00:59:58.702710 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3602 00:59:58.705770 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3603 00:59:58.712324 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3604 00:59:58.715784 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3605 00:59:58.716265
3606 00:59:58.716640
3607 00:59:58.716988 ==
3608 00:59:58.718950 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 00:59:58.722126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 00:59:58.722599 ==
3611 00:59:58.722974
3612 00:59:58.723320
3613 00:59:58.725756 TX Vref Scan disable
3614 00:59:58.729091 == TX Byte 0 ==
3615 00:59:58.732680 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 00:59:58.736009 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 00:59:58.738946 == TX Byte 1 ==
3618 00:59:58.742313 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3619 00:59:58.745552 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3620 00:59:58.746156 ==
3621 00:59:58.748728 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 00:59:58.752723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 00:59:58.753296 ==
3624 00:59:58.765642 TX Vref=22, minBit 1, minWin=25, winSum=417
3625 00:59:58.768840 TX Vref=24, minBit 1, minWin=25, winSum=422
3626 00:59:58.772349 TX Vref=26, minBit 3, minWin=25, winSum=426
3627 00:59:58.776053 TX Vref=28, minBit 3, minWin=26, winSum=429
3628 00:59:58.778870 TX Vref=30, minBit 1, minWin=26, winSum=431
3629 00:59:58.785683 TX Vref=32, minBit 9, minWin=25, winSum=427
3630 00:59:58.788840 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3631 00:59:58.789414
3632 00:59:58.792266 Final TX Range 1 Vref 30
3633 00:59:58.792838
3634 00:59:58.793214 ==
3635 00:59:58.795413 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 00:59:58.798689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 00:59:58.799264 ==
3638 00:59:58.801980
3639 00:59:58.802552
3640 00:59:58.803009 TX Vref Scan disable
3641 00:59:58.805582 == TX Byte 0 ==
3642 00:59:58.808616 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3643 00:59:58.815060 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3644 00:59:58.815666 == TX Byte 1 ==
3645 00:59:58.818304 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3646 00:59:58.824987 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3647 00:59:58.825559
3648 00:59:58.825934 [DATLAT]
3649 00:59:58.826344 Freq=1200, CH1 RK1
3650 00:59:58.826683
3651 00:59:58.827997 DATLAT Default: 0xd
3652 00:59:58.828467 0, 0xFFFF, sum = 0
3653 00:59:58.831733 1, 0xFFFF, sum = 0
3654 00:59:58.832311 2, 0xFFFF, sum = 0
3655 00:59:58.835403 3, 0xFFFF, sum = 0
3656 00:59:58.838190 4, 0xFFFF, sum = 0
3657 00:59:58.838685 5, 0xFFFF, sum = 0
3658 00:59:58.841600 6, 0xFFFF, sum = 0
3659 00:59:58.842114 7, 0xFFFF, sum = 0
3660 00:59:58.845050 8, 0xFFFF, sum = 0
3661 00:59:58.845529 9, 0xFFFF, sum = 0
3662 00:59:58.848333 10, 0xFFFF, sum = 0
3663 00:59:58.848909 11, 0xFFFF, sum = 0
3664 00:59:58.851429 12, 0x0, sum = 1
3665 00:59:58.851910 13, 0x0, sum = 2
3666 00:59:58.855125 14, 0x0, sum = 3
3667 00:59:58.855702 15, 0x0, sum = 4
3668 00:59:58.858647 best_step = 13
3669 00:59:58.859119
3670 00:59:58.859491 ==
3671 00:59:58.861642 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 00:59:58.865442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 00:59:58.866052 ==
3674 00:59:58.866433 RX Vref Scan: 0
3675 00:59:58.866780
3676 00:59:58.868132 RX Vref 0 -> 0, step: 1
3677 00:59:58.868603
3678 00:59:58.871763 RX Delay -13 -> 252, step: 4
3679 00:59:58.874831 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3680 00:59:58.881708 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3681 00:59:58.884992 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3682 00:59:58.888336 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3683 00:59:58.891572 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3684 00:59:58.894813 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3685 00:59:58.901573 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3686 00:59:58.905577 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3687 00:59:58.908276 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3688 00:59:58.911969 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3689 00:59:58.914899 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3690 00:59:58.921212 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3691 00:59:58.924579 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3692 00:59:58.928287 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3693 00:59:58.931472 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3694 00:59:58.934949 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3695 00:59:58.938468 ==
3696 00:59:58.939042 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 00:59:58.944465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 00:59:58.944941 ==
3699 00:59:58.945315 DQS Delay:
3700 00:59:58.948202 DQS0 = 0, DQS1 = 0
3701 00:59:58.948674 DQM Delay:
3702 00:59:58.951346 DQM0 = 119, DQM1 = 113
3703 00:59:58.951817 DQ Delay:
3704 00:59:58.954759 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3705 00:59:58.957898 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3706 00:59:58.962343 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3707 00:59:58.964607 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3708 00:59:58.965079
3709 00:59:58.965450
3710 00:59:58.974777 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3711 00:59:58.975355 CH1 RK1: MR19=403, MR18=8EC
3712 00:59:58.981418 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3713 00:59:58.984656 [RxdqsGatingPostProcess] freq 1200
3714 00:59:58.991300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3715 00:59:58.994631 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 00:59:58.997918 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 00:59:59.001497 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 00:59:59.004731 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 00:59:59.007812 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 00:59:59.011156 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 00:59:59.011728 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 00:59:59.014051 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 00:59:59.017438 Pre-setting of DQS Precalculation
3724 00:59:59.023998 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3725 00:59:59.030897 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3726 00:59:59.037999 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3727 00:59:59.038570
3728 00:59:59.038947
3729 00:59:59.040689 [Calibration Summary] 2400 Mbps
3730 00:59:59.044537 CH 0, Rank 0
3731 00:59:59.045006 SW Impedance : PASS
3732 00:59:59.048186 DUTY Scan : NO K
3733 00:59:59.050826 ZQ Calibration : PASS
3734 00:59:59.051301 Jitter Meter : NO K
3735 00:59:59.054011 CBT Training : PASS
3736 00:59:59.054487 Write leveling : PASS
3737 00:59:59.057255 RX DQS gating : PASS
3738 00:59:59.061132 RX DQ/DQS(RDDQC) : PASS
3739 00:59:59.061601 TX DQ/DQS : PASS
3740 00:59:59.064123 RX DATLAT : PASS
3741 00:59:59.067447 RX DQ/DQS(Engine): PASS
3742 00:59:59.068016 TX OE : NO K
3743 00:59:59.070621 All Pass.
3744 00:59:59.071089
3745 00:59:59.071462 CH 0, Rank 1
3746 00:59:59.073909 SW Impedance : PASS
3747 00:59:59.074406 DUTY Scan : NO K
3748 00:59:59.077377 ZQ Calibration : PASS
3749 00:59:59.081058 Jitter Meter : NO K
3750 00:59:59.081630 CBT Training : PASS
3751 00:59:59.084198 Write leveling : PASS
3752 00:59:59.087242 RX DQS gating : PASS
3753 00:59:59.087813 RX DQ/DQS(RDDQC) : PASS
3754 00:59:59.090588 TX DQ/DQS : PASS
3755 00:59:59.094246 RX DATLAT : PASS
3756 00:59:59.094817 RX DQ/DQS(Engine): PASS
3757 00:59:59.097362 TX OE : NO K
3758 00:59:59.097967 All Pass.
3759 00:59:59.098352
3760 00:59:59.100697 CH 1, Rank 0
3761 00:59:59.101267 SW Impedance : PASS
3762 00:59:59.103975 DUTY Scan : NO K
3763 00:59:59.107401 ZQ Calibration : PASS
3764 00:59:59.107974 Jitter Meter : NO K
3765 00:59:59.110814 CBT Training : PASS
3766 00:59:59.111385 Write leveling : PASS
3767 00:59:59.114393 RX DQS gating : PASS
3768 00:59:59.116960 RX DQ/DQS(RDDQC) : PASS
3769 00:59:59.117433 TX DQ/DQS : PASS
3770 00:59:59.120650 RX DATLAT : PASS
3771 00:59:59.123826 RX DQ/DQS(Engine): PASS
3772 00:59:59.124296 TX OE : NO K
3773 00:59:59.127321 All Pass.
3774 00:59:59.127937
3775 00:59:59.128322 CH 1, Rank 1
3776 00:59:59.130475 SW Impedance : PASS
3777 00:59:59.131065 DUTY Scan : NO K
3778 00:59:59.133551 ZQ Calibration : PASS
3779 00:59:59.137224 Jitter Meter : NO K
3780 00:59:59.137793 CBT Training : PASS
3781 00:59:59.140197 Write leveling : PASS
3782 00:59:59.143721 RX DQS gating : PASS
3783 00:59:59.144305 RX DQ/DQS(RDDQC) : PASS
3784 00:59:59.146772 TX DQ/DQS : PASS
3785 00:59:59.150379 RX DATLAT : PASS
3786 00:59:59.150951 RX DQ/DQS(Engine): PASS
3787 00:59:59.153419 TX OE : NO K
3788 00:59:59.154025 All Pass.
3789 00:59:59.154414
3790 00:59:59.156908 DramC Write-DBI off
3791 00:59:59.160601 PER_BANK_REFRESH: Hybrid Mode
3792 00:59:59.161180 TX_TRACKING: ON
3793 00:59:59.170029 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3794 00:59:59.173598 [FAST_K] Save calibration result to emmc
3795 00:59:59.177250 dramc_set_vcore_voltage set vcore to 650000
3796 00:59:59.180224 Read voltage for 600, 5
3797 00:59:59.180794 Vio18 = 0
3798 00:59:59.181175 Vcore = 650000
3799 00:59:59.183449 Vdram = 0
3800 00:59:59.184021 Vddq = 0
3801 00:59:59.184399 Vmddr = 0
3802 00:59:59.190505 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3803 00:59:59.193314 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3804 00:59:59.197109 MEM_TYPE=3, freq_sel=19
3805 00:59:59.200099 sv_algorithm_assistance_LP4_1600
3806 00:59:59.203311 ============ PULL DRAM RESETB DOWN ============
3807 00:59:59.206622 ========== PULL DRAM RESETB DOWN end =========
3808 00:59:59.213267 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3809 00:59:59.216605 ===================================
3810 00:59:59.217081 LPDDR4 DRAM CONFIGURATION
3811 00:59:59.219580 ===================================
3812 00:59:59.223074 EX_ROW_EN[0] = 0x0
3813 00:59:59.226286 EX_ROW_EN[1] = 0x0
3814 00:59:59.226758 LP4Y_EN = 0x0
3815 00:59:59.229849 WORK_FSP = 0x0
3816 00:59:59.230453 WL = 0x2
3817 00:59:59.233897 RL = 0x2
3818 00:59:59.234505 BL = 0x2
3819 00:59:59.236399 RPST = 0x0
3820 00:59:59.236973 RD_PRE = 0x0
3821 00:59:59.239668 WR_PRE = 0x1
3822 00:59:59.240140 WR_PST = 0x0
3823 00:59:59.242836 DBI_WR = 0x0
3824 00:59:59.243307 DBI_RD = 0x0
3825 00:59:59.246299 OTF = 0x1
3826 00:59:59.249776 ===================================
3827 00:59:59.252906 ===================================
3828 00:59:59.253381 ANA top config
3829 00:59:59.256587 ===================================
3830 00:59:59.259564 DLL_ASYNC_EN = 0
3831 00:59:59.263222 ALL_SLAVE_EN = 1
3832 00:59:59.266411 NEW_RANK_MODE = 1
3833 00:59:59.266954 DLL_IDLE_MODE = 1
3834 00:59:59.269501 LP45_APHY_COMB_EN = 1
3835 00:59:59.273175 TX_ODT_DIS = 1
3836 00:59:59.276097 NEW_8X_MODE = 1
3837 00:59:59.280000 ===================================
3838 00:59:59.282944 ===================================
3839 00:59:59.286513 data_rate = 1200
3840 00:59:59.286986 CKR = 1
3841 00:59:59.289812 DQ_P2S_RATIO = 8
3842 00:59:59.293283 ===================================
3843 00:59:59.296482 CA_P2S_RATIO = 8
3844 00:59:59.299796 DQ_CA_OPEN = 0
3845 00:59:59.303326 DQ_SEMI_OPEN = 0
3846 00:59:59.303898 CA_SEMI_OPEN = 0
3847 00:59:59.306701 CA_FULL_RATE = 0
3848 00:59:59.309649 DQ_CKDIV4_EN = 1
3849 00:59:59.313442 CA_CKDIV4_EN = 1
3850 00:59:59.316404 CA_PREDIV_EN = 0
3851 00:59:59.319502 PH8_DLY = 0
3852 00:59:59.319972 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3853 00:59:59.322858 DQ_AAMCK_DIV = 4
3854 00:59:59.326140 CA_AAMCK_DIV = 4
3855 00:59:59.329815 CA_ADMCK_DIV = 4
3856 00:59:59.333036 DQ_TRACK_CA_EN = 0
3857 00:59:59.336314 CA_PICK = 600
3858 00:59:59.339774 CA_MCKIO = 600
3859 00:59:59.340251 MCKIO_SEMI = 0
3860 00:59:59.342594 PLL_FREQ = 2288
3861 00:59:59.345829 DQ_UI_PI_RATIO = 32
3862 00:59:59.349578 CA_UI_PI_RATIO = 0
3863 00:59:59.352877 ===================================
3864 00:59:59.356230 ===================================
3865 00:59:59.359565 memory_type:LPDDR4
3866 00:59:59.360140 GP_NUM : 10
3867 00:59:59.362610 SRAM_EN : 1
3868 00:59:59.366065 MD32_EN : 0
3869 00:59:59.369113 ===================================
3870 00:59:59.369586 [ANA_INIT] >>>>>>>>>>>>>>
3871 00:59:59.373187 <<<<<< [CONFIGURE PHASE]: ANA_TX
3872 00:59:59.376263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3873 00:59:59.379433 ===================================
3874 00:59:59.382783 data_rate = 1200,PCW = 0X5800
3875 00:59:59.386130 ===================================
3876 00:59:59.389179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3877 00:59:59.395874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 00:59:59.399601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 00:59:59.405884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3880 00:59:59.409555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3881 00:59:59.412579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3882 00:59:59.413153 [ANA_INIT] flow start
3883 00:59:59.416046 [ANA_INIT] PLL >>>>>>>>
3884 00:59:59.418952 [ANA_INIT] PLL <<<<<<<<
3885 00:59:59.419422 [ANA_INIT] MIDPI >>>>>>>>
3886 00:59:59.422427 [ANA_INIT] MIDPI <<<<<<<<
3887 00:59:59.425920 [ANA_INIT] DLL >>>>>>>>
3888 00:59:59.426431 [ANA_INIT] flow end
3889 00:59:59.432477 ============ LP4 DIFF to SE enter ============
3890 00:59:59.435966 ============ LP4 DIFF to SE exit ============
3891 00:59:59.439249 [ANA_INIT] <<<<<<<<<<<<<
3892 00:59:59.442154 [Flow] Enable top DCM control >>>>>
3893 00:59:59.445781 [Flow] Enable top DCM control <<<<<
3894 00:59:59.446382 Enable DLL master slave shuffle
3895 00:59:59.452226 ==============================================================
3896 00:59:59.455468 Gating Mode config
3897 00:59:59.458921 ==============================================================
3898 00:59:59.462189 Config description:
3899 00:59:59.472267 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3900 00:59:59.478922 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3901 00:59:59.482191 SELPH_MODE 0: By rank 1: By Phase
3902 00:59:59.489040 ==============================================================
3903 00:59:59.492333 GAT_TRACK_EN = 1
3904 00:59:59.495585 RX_GATING_MODE = 2
3905 00:59:59.498704 RX_GATING_TRACK_MODE = 2
3906 00:59:59.502269 SELPH_MODE = 1
3907 00:59:59.502746 PICG_EARLY_EN = 1
3908 00:59:59.505733 VALID_LAT_VALUE = 1
3909 00:59:59.512463 ==============================================================
3910 00:59:59.515324 Enter into Gating configuration >>>>
3911 00:59:59.518483 Exit from Gating configuration <<<<
3912 00:59:59.522115 Enter into DVFS_PRE_config >>>>>
3913 00:59:59.532155 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3914 00:59:59.535298 Exit from DVFS_PRE_config <<<<<
3915 00:59:59.538842 Enter into PICG configuration >>>>
3916 00:59:59.542166 Exit from PICG configuration <<<<
3917 00:59:59.545314 [RX_INPUT] configuration >>>>>
3918 00:59:59.548798 [RX_INPUT] configuration <<<<<
3919 00:59:59.552136 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3920 00:59:59.558723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3921 00:59:59.565513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 00:59:59.572258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 00:59:59.578277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 00:59:59.581788 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 00:59:59.588471 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3926 00:59:59.591756 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3927 00:59:59.595155 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3928 00:59:59.598629 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3929 00:59:59.605576 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3930 00:59:59.608620 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 00:59:59.611725 ===================================
3932 00:59:59.615080 LPDDR4 DRAM CONFIGURATION
3933 00:59:59.618623 ===================================
3934 00:59:59.619158 EX_ROW_EN[0] = 0x0
3935 00:59:59.621558 EX_ROW_EN[1] = 0x0
3936 00:59:59.622077 LP4Y_EN = 0x0
3937 00:59:59.625869 WORK_FSP = 0x0
3938 00:59:59.626397 WL = 0x2
3939 00:59:59.628483 RL = 0x2
3940 00:59:59.628952 BL = 0x2
3941 00:59:59.631867 RPST = 0x0
3942 00:59:59.632341 RD_PRE = 0x0
3943 00:59:59.635280 WR_PRE = 0x1
3944 00:59:59.635914 WR_PST = 0x0
3945 00:59:59.638194 DBI_WR = 0x0
3946 00:59:59.638667 DBI_RD = 0x0
3947 00:59:59.641865 OTF = 0x1
3948 00:59:59.645654 ===================================
3949 00:59:59.648492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3950 00:59:59.651798 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3951 00:59:59.658253 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 00:59:59.662167 ===================================
3953 00:59:59.664746 LPDDR4 DRAM CONFIGURATION
3954 00:59:59.667975 ===================================
3955 00:59:59.668445 EX_ROW_EN[0] = 0x10
3956 00:59:59.671751 EX_ROW_EN[1] = 0x0
3957 00:59:59.672323 LP4Y_EN = 0x0
3958 00:59:59.675154 WORK_FSP = 0x0
3959 00:59:59.675659 WL = 0x2
3960 00:59:59.678048 RL = 0x2
3961 00:59:59.678520 BL = 0x2
3962 00:59:59.681578 RPST = 0x0
3963 00:59:59.682193 RD_PRE = 0x0
3964 00:59:59.684845 WR_PRE = 0x1
3965 00:59:59.685425 WR_PST = 0x0
3966 00:59:59.687848 DBI_WR = 0x0
3967 00:59:59.688320 DBI_RD = 0x0
3968 00:59:59.691344 OTF = 0x1
3969 00:59:59.694931 ===================================
3970 00:59:59.701273 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3971 00:59:59.704565 nWR fixed to 30
3972 00:59:59.708099 [ModeRegInit_LP4] CH0 RK0
3973 00:59:59.708572 [ModeRegInit_LP4] CH0 RK1
3974 00:59:59.711208 [ModeRegInit_LP4] CH1 RK0
3975 00:59:59.714555 [ModeRegInit_LP4] CH1 RK1
3976 00:59:59.715025 match AC timing 17
3977 00:59:59.721729 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3978 00:59:59.724944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3979 00:59:59.728146 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3980 00:59:59.734636 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3981 00:59:59.738410 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3982 00:59:59.738988 ==
3983 00:59:59.741466 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 00:59:59.744522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 00:59:59.744997 ==
3986 00:59:59.751135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 00:59:59.757713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3988 00:59:59.760998 [CA 0] Center 36 (5~67) winsize 63
3989 00:59:59.764515 [CA 1] Center 36 (6~67) winsize 62
3990 00:59:59.767920 [CA 2] Center 34 (4~65) winsize 62
3991 00:59:59.770818 [CA 3] Center 34 (4~65) winsize 62
3992 00:59:59.774256 [CA 4] Center 33 (3~64) winsize 62
3993 00:59:59.778006 [CA 5] Center 33 (2~64) winsize 63
3994 00:59:59.778596
3995 00:59:59.781080 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3996 00:59:59.781646
3997 00:59:59.784672 [CATrainingPosCal] consider 1 rank data
3998 00:59:59.787988 u2DelayCellTimex100 = 270/100 ps
3999 00:59:59.791547 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4000 00:59:59.794062 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4001 00:59:59.798820 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 00:59:59.801087 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 00:59:59.804302 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 00:59:59.810952 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4005 00:59:59.811538
4006 00:59:59.814351 CA PerBit enable=1, Macro0, CA PI delay=33
4007 00:59:59.814932
4008 00:59:59.817320 [CBTSetCACLKResult] CA Dly = 33
4009 00:59:59.817790 CS Dly: 5 (0~36)
4010 00:59:59.818223 ==
4011 00:59:59.820737 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 00:59:59.824476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 00:59:59.827227 ==
4014 00:59:59.830895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 00:59:59.837397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4016 00:59:59.840708 [CA 0] Center 36 (6~67) winsize 62
4017 00:59:59.844706 [CA 1] Center 36 (6~67) winsize 62
4018 00:59:59.847767 [CA 2] Center 34 (4~65) winsize 62
4019 00:59:59.850880 [CA 3] Center 34 (4~65) winsize 62
4020 00:59:59.854272 [CA 4] Center 34 (3~65) winsize 63
4021 00:59:59.857712 [CA 5] Center 33 (3~64) winsize 62
4022 00:59:59.858448
4023 00:59:59.861056 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4024 00:59:59.861658
4025 00:59:59.864288 [CATrainingPosCal] consider 2 rank data
4026 00:59:59.867824 u2DelayCellTimex100 = 270/100 ps
4027 00:59:59.870576 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4028 00:59:59.874103 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4029 00:59:59.877479 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 00:59:59.880686 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4031 00:59:59.887175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 00:59:59.890559 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 00:59:59.891037
4034 00:59:59.894311 CA PerBit enable=1, Macro0, CA PI delay=33
4035 00:59:59.894880
4036 00:59:59.897402 [CBTSetCACLKResult] CA Dly = 33
4037 00:59:59.897874 CS Dly: 5 (0~37)
4038 00:59:59.898302
4039 00:59:59.900440 ----->DramcWriteLeveling(PI) begin...
4040 00:59:59.900975 ==
4041 00:59:59.903796 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 00:59:59.910553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 00:59:59.911128 ==
4044 00:59:59.914211 Write leveling (Byte 0): 33 => 33
4045 00:59:59.914777 Write leveling (Byte 1): 32 => 32
4046 00:59:59.917284 DramcWriteLeveling(PI) end<-----
4047 00:59:59.917755
4048 00:59:59.920505 ==
4049 00:59:59.920976 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 00:59:59.927227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 00:59:59.927704 ==
4052 00:59:59.930520 [Gating] SW mode calibration
4053 00:59:59.937254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4054 00:59:59.940417 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4055 00:59:59.947256 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 00:59:59.950447 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 00:59:59.953909 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 00:59:59.960638 0 9 12 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
4059 00:59:59.963584 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
4060 00:59:59.967571 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 00:59:59.973632 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 00:59:59.976977 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 00:59:59.980391 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 00:59:59.987116 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 00:59:59.990190 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 00:59:59.993333 0 10 12 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
4067 00:59:59.999988 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4068 01:00:00.003457 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 01:00:00.006598 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 01:00:00.013757 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 01:00:00.016517 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 01:00:00.020069 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 01:00:00.023336 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 01:00:00.030012 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4075 01:00:00.033169 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4076 01:00:00.037257 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 01:00:00.043273 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 01:00:00.046860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 01:00:00.050379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 01:00:00.057369 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 01:00:00.059975 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 01:00:00.063356 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 01:00:00.070039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 01:00:00.073528 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 01:00:00.076631 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 01:00:00.083701 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 01:00:00.086675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 01:00:00.089840 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 01:00:00.096779 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 01:00:00.099880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 01:00:00.103020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4092 01:00:00.109598 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 01:00:00.110183 Total UI for P1: 0, mck2ui 16
4094 01:00:00.113368 best dqsien dly found for B0: ( 0, 13, 16)
4095 01:00:00.116728 Total UI for P1: 0, mck2ui 16
4096 01:00:00.119853 best dqsien dly found for B1: ( 0, 13, 16)
4097 01:00:00.126702 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4098 01:00:00.130015 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4099 01:00:00.130486
4100 01:00:00.132987 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4101 01:00:00.136503 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4102 01:00:00.139741 [Gating] SW calibration Done
4103 01:00:00.140316 ==
4104 01:00:00.143671 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 01:00:00.146247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 01:00:00.146722 ==
4107 01:00:00.149936 RX Vref Scan: 0
4108 01:00:00.150543
4109 01:00:00.150917 RX Vref 0 -> 0, step: 1
4110 01:00:00.151267
4111 01:00:00.152827 RX Delay -230 -> 252, step: 16
4112 01:00:00.156505 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4113 01:00:00.163184 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4114 01:00:00.166481 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4115 01:00:00.169835 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4116 01:00:00.173205 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4117 01:00:00.179520 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4118 01:00:00.183063 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4119 01:00:00.186522 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4120 01:00:00.189630 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4121 01:00:00.193026 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4122 01:00:00.199611 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4123 01:00:00.202964 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4124 01:00:00.206351 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4125 01:00:00.209435 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4126 01:00:00.216099 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4127 01:00:00.219350 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4128 01:00:00.219833 ==
4129 01:00:00.222567 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 01:00:00.226068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 01:00:00.226640 ==
4132 01:00:00.229509 DQS Delay:
4133 01:00:00.230070 DQS0 = 0, DQS1 = 0
4134 01:00:00.230454 DQM Delay:
4135 01:00:00.233172 DQM0 = 53, DQM1 = 40
4136 01:00:00.233743 DQ Delay:
4137 01:00:00.236004 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4138 01:00:00.239615 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4139 01:00:00.242643 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4140 01:00:00.247036 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4141 01:00:00.247607
4142 01:00:00.247983
4143 01:00:00.248323 ==
4144 01:00:00.249276 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 01:00:00.256578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 01:00:00.257180 ==
4147 01:00:00.257566
4148 01:00:00.257910
4149 01:00:00.258284 TX Vref Scan disable
4150 01:00:00.259932 == TX Byte 0 ==
4151 01:00:00.262870 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4152 01:00:00.269809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4153 01:00:00.270424 == TX Byte 1 ==
4154 01:00:00.272974 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4155 01:00:00.280186 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4156 01:00:00.280758 ==
4157 01:00:00.282812 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 01:00:00.286120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 01:00:00.286694 ==
4160 01:00:00.287074
4161 01:00:00.287422
4162 01:00:00.289723 TX Vref Scan disable
4163 01:00:00.293705 == TX Byte 0 ==
4164 01:00:00.295970 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4165 01:00:00.299310 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4166 01:00:00.302966 == TX Byte 1 ==
4167 01:00:00.306172 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4168 01:00:00.309488 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4169 01:00:00.310110
4170 01:00:00.310601 [DATLAT]
4171 01:00:00.312698 Freq=600, CH0 RK0
4172 01:00:00.313286
4173 01:00:00.313784 DATLAT Default: 0x9
4174 01:00:00.315980 0, 0xFFFF, sum = 0
4175 01:00:00.319372 1, 0xFFFF, sum = 0
4176 01:00:00.319865 2, 0xFFFF, sum = 0
4177 01:00:00.322298 3, 0xFFFF, sum = 0
4178 01:00:00.322793 4, 0xFFFF, sum = 0
4179 01:00:00.326071 5, 0xFFFF, sum = 0
4180 01:00:00.326669 6, 0xFFFF, sum = 0
4181 01:00:00.329198 7, 0xFFFF, sum = 0
4182 01:00:00.329688 8, 0x0, sum = 1
4183 01:00:00.330257 9, 0x0, sum = 2
4184 01:00:00.332496 10, 0x0, sum = 3
4185 01:00:00.333092 11, 0x0, sum = 4
4186 01:00:00.335654 best_step = 9
4187 01:00:00.336140
4188 01:00:00.336627 ==
4189 01:00:00.338928 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 01:00:00.342289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 01:00:00.342778 ==
4192 01:00:00.345588 RX Vref Scan: 1
4193 01:00:00.346101
4194 01:00:00.346591 RX Vref 0 -> 0, step: 1
4195 01:00:00.347053
4196 01:00:00.348955 RX Delay -179 -> 252, step: 8
4197 01:00:00.349440
4198 01:00:00.352556 Set Vref, RX VrefLevel [Byte0]: 60
4199 01:00:00.355878 [Byte1]: 50
4200 01:00:00.359689
4201 01:00:00.360148 Final RX Vref Byte 0 = 60 to rank0
4202 01:00:00.363200 Final RX Vref Byte 1 = 50 to rank0
4203 01:00:00.366949 Final RX Vref Byte 0 = 60 to rank1
4204 01:00:00.369985 Final RX Vref Byte 1 = 50 to rank1==
4205 01:00:00.373273 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 01:00:00.379980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 01:00:00.380511 ==
4208 01:00:00.380856 DQS Delay:
4209 01:00:00.381173 DQS0 = 0, DQS1 = 0
4210 01:00:00.383588 DQM Delay:
4211 01:00:00.384193 DQM0 = 49, DQM1 = 37
4212 01:00:00.386818 DQ Delay:
4213 01:00:00.390239 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4214 01:00:00.393395 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4215 01:00:00.396815 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4216 01:00:00.399803 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4217 01:00:00.400330
4218 01:00:00.400674
4219 01:00:00.406793 [DQSOSCAuto] RK0, (LSB)MR18= 0x554f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4220 01:00:00.409890 CH0 RK0: MR19=808, MR18=554F
4221 01:00:00.416597 CH0_RK0: MR19=0x808, MR18=0x554F, DQSOSC=393, MR23=63, INC=169, DEC=113
4222 01:00:00.417157
4223 01:00:00.419635 ----->DramcWriteLeveling(PI) begin...
4224 01:00:00.420116 ==
4225 01:00:00.423002 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 01:00:00.426846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 01:00:00.427442 ==
4228 01:00:00.429616 Write leveling (Byte 0): 35 => 35
4229 01:00:00.432753 Write leveling (Byte 1): 30 => 30
4230 01:00:00.436116 DramcWriteLeveling(PI) end<-----
4231 01:00:00.436590
4232 01:00:00.436963 ==
4233 01:00:00.440045 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 01:00:00.443023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 01:00:00.443503 ==
4236 01:00:00.446159 [Gating] SW mode calibration
4237 01:00:00.452999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4238 01:00:00.459678 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4239 01:00:00.462944 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 01:00:00.466468 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 01:00:00.473167 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 01:00:00.476669 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 1)
4243 01:00:00.479549 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4244 01:00:00.486215 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 01:00:00.489774 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 01:00:00.493002 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 01:00:00.499383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 01:00:00.502877 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 01:00:00.505909 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 01:00:00.512362 0 10 12 | B1->B0 | 2f2f 3333 | 1 0 | (0 0) (0 0)
4251 01:00:00.515851 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4252 01:00:00.519177 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 01:00:00.525996 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 01:00:00.528831 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 01:00:00.532813 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 01:00:00.539053 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 01:00:00.542005 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 01:00:00.545797 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4259 01:00:00.552203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 01:00:00.555951 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 01:00:00.558715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 01:00:00.565660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 01:00:00.568808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 01:00:00.572329 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 01:00:00.578828 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 01:00:00.582233 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 01:00:00.585657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 01:00:00.592522 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 01:00:00.596280 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 01:00:00.598587 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 01:00:00.605181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 01:00:00.608863 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 01:00:00.611647 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 01:00:00.618312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 01:00:00.621928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 01:00:00.624834 Total UI for P1: 0, mck2ui 16
4277 01:00:00.628376 best dqsien dly found for B0: ( 0, 13, 14)
4278 01:00:00.632026 Total UI for P1: 0, mck2ui 16
4279 01:00:00.634785 best dqsien dly found for B1: ( 0, 13, 14)
4280 01:00:00.638205 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4281 01:00:00.641713 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4282 01:00:00.642229
4283 01:00:00.644969 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4284 01:00:00.648824 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4285 01:00:00.651738 [Gating] SW calibration Done
4286 01:00:00.652234 ==
4287 01:00:00.655260 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 01:00:00.658330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 01:00:00.661730 ==
4290 01:00:00.662198 RX Vref Scan: 0
4291 01:00:00.662667
4292 01:00:00.665234 RX Vref 0 -> 0, step: 1
4293 01:00:00.665771
4294 01:00:00.668156 RX Delay -230 -> 252, step: 16
4295 01:00:00.671554 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4296 01:00:00.675092 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4297 01:00:00.678285 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4298 01:00:00.685077 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4299 01:00:00.688367 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4300 01:00:00.691990 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4301 01:00:00.695712 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4302 01:00:00.698633 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4303 01:00:00.704824 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4304 01:00:00.708480 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4305 01:00:00.711677 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4306 01:00:00.715619 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4307 01:00:00.721462 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4308 01:00:00.724934 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4309 01:00:00.728179 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4310 01:00:00.731183 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4311 01:00:00.731659 ==
4312 01:00:00.734639 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 01:00:00.741824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 01:00:00.742468 ==
4315 01:00:00.742848 DQS Delay:
4316 01:00:00.745059 DQS0 = 0, DQS1 = 0
4317 01:00:00.745640 DQM Delay:
4318 01:00:00.746074 DQM0 = 48, DQM1 = 42
4319 01:00:00.748042 DQ Delay:
4320 01:00:00.751327 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4321 01:00:00.754645 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4322 01:00:00.758111 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4323 01:00:00.761572 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4324 01:00:00.762094
4325 01:00:00.762477
4326 01:00:00.762824 ==
4327 01:00:00.765119 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 01:00:00.767834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 01:00:00.768466 ==
4330 01:00:00.768847
4331 01:00:00.769196
4332 01:00:00.771219 TX Vref Scan disable
4333 01:00:00.771686 == TX Byte 0 ==
4334 01:00:00.778399 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4335 01:00:00.781253 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4336 01:00:00.784868 == TX Byte 1 ==
4337 01:00:00.787811 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4338 01:00:00.791028 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4339 01:00:00.791613 ==
4340 01:00:00.794659 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 01:00:00.798252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 01:00:00.801405 ==
4343 01:00:00.802013
4344 01:00:00.802395
4345 01:00:00.802744 TX Vref Scan disable
4346 01:00:00.805183 == TX Byte 0 ==
4347 01:00:00.808534 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4348 01:00:00.811712 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4349 01:00:00.814853 == TX Byte 1 ==
4350 01:00:00.818690 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4351 01:00:00.821419 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4352 01:00:00.824804
4353 01:00:00.825378 [DATLAT]
4354 01:00:00.825755 Freq=600, CH0 RK1
4355 01:00:00.826152
4356 01:00:00.828323 DATLAT Default: 0x9
4357 01:00:00.828900 0, 0xFFFF, sum = 0
4358 01:00:00.831348 1, 0xFFFF, sum = 0
4359 01:00:00.831833 2, 0xFFFF, sum = 0
4360 01:00:00.834843 3, 0xFFFF, sum = 0
4361 01:00:00.835310 4, 0xFFFF, sum = 0
4362 01:00:00.838053 5, 0xFFFF, sum = 0
4363 01:00:00.841350 6, 0xFFFF, sum = 0
4364 01:00:00.841817 7, 0xFFFF, sum = 0
4365 01:00:00.842245 8, 0x0, sum = 1
4366 01:00:00.844698 9, 0x0, sum = 2
4367 01:00:00.845162 10, 0x0, sum = 3
4368 01:00:00.848016 11, 0x0, sum = 4
4369 01:00:00.848481 best_step = 9
4370 01:00:00.848845
4371 01:00:00.849182 ==
4372 01:00:00.851023 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 01:00:00.857796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 01:00:00.858255 ==
4375 01:00:00.858588 RX Vref Scan: 0
4376 01:00:00.858894
4377 01:00:00.861363 RX Vref 0 -> 0, step: 1
4378 01:00:00.861782
4379 01:00:00.864896 RX Delay -179 -> 252, step: 8
4380 01:00:00.867890 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4381 01:00:00.874451 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4382 01:00:00.878064 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4383 01:00:00.881146 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4384 01:00:00.884953 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4385 01:00:00.888190 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4386 01:00:00.894866 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4387 01:00:00.897990 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4388 01:00:00.901526 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4389 01:00:00.905014 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4390 01:00:00.907914 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4391 01:00:00.914574 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4392 01:00:00.918184 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4393 01:00:00.921801 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4394 01:00:00.924322 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4395 01:00:00.931027 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4396 01:00:00.931623 ==
4397 01:00:00.934277 Dram Type= 6, Freq= 0, CH_0, rank 1
4398 01:00:00.937844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 01:00:00.938457 ==
4400 01:00:00.938831 DQS Delay:
4401 01:00:00.941240 DQS0 = 0, DQS1 = 0
4402 01:00:00.941797 DQM Delay:
4403 01:00:00.944959 DQM0 = 48, DQM1 = 41
4404 01:00:00.945518 DQ Delay:
4405 01:00:00.947519 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4406 01:00:00.951183 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4407 01:00:00.954213 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4408 01:00:00.957650 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =52
4409 01:00:00.958247
4410 01:00:00.958618
4411 01:00:00.964132 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4412 01:00:00.967227 CH0 RK1: MR19=808, MR18=5F2C
4413 01:00:00.974386 CH0_RK1: MR19=0x808, MR18=0x5F2C, DQSOSC=391, MR23=63, INC=171, DEC=114
4414 01:00:00.977721 [RxdqsGatingPostProcess] freq 600
4415 01:00:00.984435 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4416 01:00:00.987319 Pre-setting of DQS Precalculation
4417 01:00:00.991235 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4418 01:00:00.991818 ==
4419 01:00:00.994115 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 01:00:00.997780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 01:00:00.998404 ==
4422 01:00:01.004527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4423 01:00:01.010848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4424 01:00:01.014340 [CA 0] Center 35 (5~66) winsize 62
4425 01:00:01.017397 [CA 1] Center 35 (5~66) winsize 62
4426 01:00:01.020355 [CA 2] Center 34 (4~65) winsize 62
4427 01:00:01.023864 [CA 3] Center 33 (3~64) winsize 62
4428 01:00:01.027303 [CA 4] Center 34 (3~65) winsize 63
4429 01:00:01.030861 [CA 5] Center 33 (3~64) winsize 62
4430 01:00:01.031341
4431 01:00:01.033759 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4432 01:00:01.034309
4433 01:00:01.037181 [CATrainingPosCal] consider 1 rank data
4434 01:00:01.040396 u2DelayCellTimex100 = 270/100 ps
4435 01:00:01.043595 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 01:00:01.046877 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4437 01:00:01.050446 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 01:00:01.053874 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 01:00:01.056923 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4440 01:00:01.063469 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 01:00:01.063945
4442 01:00:01.066920 CA PerBit enable=1, Macro0, CA PI delay=33
4443 01:00:01.067393
4444 01:00:01.069870 [CBTSetCACLKResult] CA Dly = 33
4445 01:00:01.070423 CS Dly: 5 (0~36)
4446 01:00:01.070807 ==
4447 01:00:01.073750 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 01:00:01.076648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 01:00:01.080229 ==
4450 01:00:01.083332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 01:00:01.090123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4452 01:00:01.093825 [CA 0] Center 35 (5~66) winsize 62
4453 01:00:01.096676 [CA 1] Center 35 (5~66) winsize 62
4454 01:00:01.100345 [CA 2] Center 34 (4~65) winsize 62
4455 01:00:01.103229 [CA 3] Center 34 (4~65) winsize 62
4456 01:00:01.106479 [CA 4] Center 34 (4~65) winsize 62
4457 01:00:01.110356 [CA 5] Center 33 (3~64) winsize 62
4458 01:00:01.110904
4459 01:00:01.113282 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4460 01:00:01.113856
4461 01:00:01.116398 [CATrainingPosCal] consider 2 rank data
4462 01:00:01.119616 u2DelayCellTimex100 = 270/100 ps
4463 01:00:01.123044 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 01:00:01.126634 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 01:00:01.133163 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 01:00:01.136303 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4467 01:00:01.139859 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 01:00:01.142626 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 01:00:01.143099
4470 01:00:01.146176 CA PerBit enable=1, Macro0, CA PI delay=33
4471 01:00:01.146741
4472 01:00:01.149873 [CBTSetCACLKResult] CA Dly = 33
4473 01:00:01.150505 CS Dly: 5 (0~37)
4474 01:00:01.150890
4475 01:00:01.153324 ----->DramcWriteLeveling(PI) begin...
4476 01:00:01.156457 ==
4477 01:00:01.159298 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 01:00:01.162680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 01:00:01.163158 ==
4480 01:00:01.165888 Write leveling (Byte 0): 28 => 28
4481 01:00:01.169063 Write leveling (Byte 1): 32 => 32
4482 01:00:01.172319 DramcWriteLeveling(PI) end<-----
4483 01:00:01.172784
4484 01:00:01.173151 ==
4485 01:00:01.175883 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 01:00:01.179202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 01:00:01.179778 ==
4488 01:00:01.182729 [Gating] SW mode calibration
4489 01:00:01.189420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4490 01:00:01.196071 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4491 01:00:01.198845 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 01:00:01.202489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 01:00:01.209078 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4494 01:00:01.212016 0 9 12 | B1->B0 | 2c2c 2c2c | 1 0 | (1 1) (0 1)
4495 01:00:01.215698 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 01:00:01.222040 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 01:00:01.225555 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 01:00:01.228920 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 01:00:01.235815 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 01:00:01.238649 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 01:00:01.242504 0 10 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4502 01:00:01.246180 0 10 12 | B1->B0 | 3a3a 3c3c | 0 0 | (0 0) (0 0)
4503 01:00:01.252676 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 01:00:01.256008 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 01:00:01.258777 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 01:00:01.265658 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 01:00:01.268914 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 01:00:01.272521 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 01:00:01.278722 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 01:00:01.282165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4511 01:00:01.285040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 01:00:01.293002 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 01:00:01.295800 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 01:00:01.298809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 01:00:01.305322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 01:00:01.308512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 01:00:01.311853 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 01:00:01.318582 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 01:00:01.322268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 01:00:01.325238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 01:00:01.332062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 01:00:01.335358 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 01:00:01.338218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 01:00:01.345130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 01:00:01.348576 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4526 01:00:01.351793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4527 01:00:01.354725 Total UI for P1: 0, mck2ui 16
4528 01:00:01.358567 best dqsien dly found for B0: ( 0, 13, 8)
4529 01:00:01.365282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 01:00:01.365867 Total UI for P1: 0, mck2ui 16
4531 01:00:01.368803 best dqsien dly found for B1: ( 0, 13, 12)
4532 01:00:01.374984 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4533 01:00:01.378414 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4534 01:00:01.378928
4535 01:00:01.382327 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4536 01:00:01.384826 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4537 01:00:01.388583 [Gating] SW calibration Done
4538 01:00:01.389168 ==
4539 01:00:01.391590 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 01:00:01.395203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 01:00:01.395686 ==
4542 01:00:01.398046 RX Vref Scan: 0
4543 01:00:01.398556
4544 01:00:01.398936 RX Vref 0 -> 0, step: 1
4545 01:00:01.399290
4546 01:00:01.401631 RX Delay -230 -> 252, step: 16
4547 01:00:01.405033 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4548 01:00:01.411802 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4549 01:00:01.414604 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4550 01:00:01.418512 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4551 01:00:01.422075 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4552 01:00:01.424728 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4553 01:00:01.431762 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4554 01:00:01.435108 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4555 01:00:01.438333 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4556 01:00:01.441730 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4557 01:00:01.447935 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4558 01:00:01.451489 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4559 01:00:01.454806 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4560 01:00:01.457932 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4561 01:00:01.464988 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4562 01:00:01.468543 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4563 01:00:01.469090 ==
4564 01:00:01.471347 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 01:00:01.474373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 01:00:01.474809 ==
4567 01:00:01.477756 DQS Delay:
4568 01:00:01.478344 DQS0 = 0, DQS1 = 0
4569 01:00:01.478691 DQM Delay:
4570 01:00:01.481614 DQM0 = 52, DQM1 = 45
4571 01:00:01.482187 DQ Delay:
4572 01:00:01.484564 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4573 01:00:01.487813 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4574 01:00:01.491284 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4575 01:00:01.494466 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4576 01:00:01.494901
4577 01:00:01.495274
4578 01:00:01.495598 ==
4579 01:00:01.497572 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 01:00:01.504349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 01:00:01.504891 ==
4582 01:00:01.505264
4583 01:00:01.505598
4584 01:00:01.505908 TX Vref Scan disable
4585 01:00:01.507740 == TX Byte 0 ==
4586 01:00:01.511067 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4587 01:00:01.518063 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4588 01:00:01.518610 == TX Byte 1 ==
4589 01:00:01.521184 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4590 01:00:01.527797 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4591 01:00:01.528338 ==
4592 01:00:01.530921 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 01:00:01.534363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 01:00:01.534804 ==
4595 01:00:01.535149
4596 01:00:01.535685
4597 01:00:01.537471 TX Vref Scan disable
4598 01:00:01.541208 == TX Byte 0 ==
4599 01:00:01.544176 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4600 01:00:01.547390 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4601 01:00:01.550759 == TX Byte 1 ==
4602 01:00:01.553907 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4603 01:00:01.557213 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4604 01:00:01.557636
4605 01:00:01.558004 [DATLAT]
4606 01:00:01.560566 Freq=600, CH1 RK0
4607 01:00:01.560989
4608 01:00:01.564109 DATLAT Default: 0x9
4609 01:00:01.564644 0, 0xFFFF, sum = 0
4610 01:00:01.567123 1, 0xFFFF, sum = 0
4611 01:00:01.567551 2, 0xFFFF, sum = 0
4612 01:00:01.570424 3, 0xFFFF, sum = 0
4613 01:00:01.570854 4, 0xFFFF, sum = 0
4614 01:00:01.574182 5, 0xFFFF, sum = 0
4615 01:00:01.574761 6, 0xFFFF, sum = 0
4616 01:00:01.577372 7, 0xFFFF, sum = 0
4617 01:00:01.577800 8, 0x0, sum = 1
4618 01:00:01.580599 9, 0x0, sum = 2
4619 01:00:01.581134 10, 0x0, sum = 3
4620 01:00:01.583877 11, 0x0, sum = 4
4621 01:00:01.584310 best_step = 9
4622 01:00:01.584647
4623 01:00:01.584962 ==
4624 01:00:01.587055 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 01:00:01.590392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 01:00:01.590819 ==
4627 01:00:01.593862 RX Vref Scan: 1
4628 01:00:01.594433
4629 01:00:01.597298 RX Vref 0 -> 0, step: 1
4630 01:00:01.597722
4631 01:00:01.598191 RX Delay -163 -> 252, step: 8
4632 01:00:01.598672
4633 01:00:01.600592 Set Vref, RX VrefLevel [Byte0]: 51
4634 01:00:01.603630 [Byte1]: 52
4635 01:00:01.608086
4636 01:00:01.608504 Final RX Vref Byte 0 = 51 to rank0
4637 01:00:01.611604 Final RX Vref Byte 1 = 52 to rank0
4638 01:00:01.615020 Final RX Vref Byte 0 = 51 to rank1
4639 01:00:01.618165 Final RX Vref Byte 1 = 52 to rank1==
4640 01:00:01.621509 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 01:00:01.624964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 01:00:01.628677 ==
4643 01:00:01.629145 DQS Delay:
4644 01:00:01.629514 DQS0 = 0, DQS1 = 0
4645 01:00:01.631556 DQM Delay:
4646 01:00:01.632048 DQM0 = 49, DQM1 = 40
4647 01:00:01.634772 DQ Delay:
4648 01:00:01.638023 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4649 01:00:01.638486 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4650 01:00:01.641267 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4651 01:00:01.648417 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4652 01:00:01.648853
4653 01:00:01.649197
4654 01:00:01.654966 [DQSOSCAuto] RK0, (LSB)MR18= 0x4970, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 396 ps
4655 01:00:01.657799 CH1 RK0: MR19=808, MR18=4970
4656 01:00:01.664226 CH1_RK0: MR19=0x808, MR18=0x4970, DQSOSC=388, MR23=63, INC=174, DEC=116
4657 01:00:01.664665
4658 01:00:01.668000 ----->DramcWriteLeveling(PI) begin...
4659 01:00:01.668438 ==
4660 01:00:01.671315 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 01:00:01.674427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 01:00:01.674860 ==
4663 01:00:01.678141 Write leveling (Byte 0): 30 => 30
4664 01:00:01.681424 Write leveling (Byte 1): 30 => 30
4665 01:00:01.684275 DramcWriteLeveling(PI) end<-----
4666 01:00:01.684708
4667 01:00:01.685050 ==
4668 01:00:01.687761 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 01:00:01.691112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 01:00:01.691548 ==
4671 01:00:01.694323 [Gating] SW mode calibration
4672 01:00:01.700727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 01:00:01.707953 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 01:00:01.710797 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 01:00:01.717355 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 01:00:01.720594 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4677 01:00:01.724090 0 9 12 | B1->B0 | 2f2f 3434 | 0 0 | (1 1) (1 1)
4678 01:00:01.730690 0 9 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
4679 01:00:01.733805 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 01:00:01.737403 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 01:00:01.744095 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 01:00:01.747698 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 01:00:01.750657 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 01:00:01.754052 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4685 01:00:01.760562 0 10 12 | B1->B0 | 3939 2f2f | 0 1 | (0 0) (0 0)
4686 01:00:01.764281 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 01:00:01.767527 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 01:00:01.774332 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 01:00:01.777225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 01:00:01.781080 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 01:00:01.787251 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 01:00:01.790761 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4693 01:00:01.793897 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 01:00:01.800996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 01:00:01.804314 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 01:00:01.807353 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 01:00:01.813735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 01:00:01.817018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 01:00:01.820127 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 01:00:01.827358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 01:00:01.830532 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 01:00:01.833585 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 01:00:01.840479 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 01:00:01.844049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 01:00:01.847197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 01:00:01.854147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 01:00:01.857189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 01:00:01.860393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4709 01:00:01.866995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4710 01:00:01.870333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 01:00:01.873465 Total UI for P1: 0, mck2ui 16
4712 01:00:01.876808 best dqsien dly found for B0: ( 0, 13, 10)
4713 01:00:01.880461 Total UI for P1: 0, mck2ui 16
4714 01:00:01.883687 best dqsien dly found for B1: ( 0, 13, 12)
4715 01:00:01.886779 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4716 01:00:01.890106 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4717 01:00:01.890692
4718 01:00:01.893608 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4719 01:00:01.896808 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4720 01:00:01.900014 [Gating] SW calibration Done
4721 01:00:01.900599 ==
4722 01:00:01.903654 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 01:00:01.906782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 01:00:01.910295 ==
4725 01:00:01.910891 RX Vref Scan: 0
4726 01:00:01.911279
4727 01:00:01.913401 RX Vref 0 -> 0, step: 1
4728 01:00:01.914020
4729 01:00:01.916836 RX Delay -230 -> 252, step: 16
4730 01:00:01.919701 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4731 01:00:01.923197 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4732 01:00:01.926282 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4733 01:00:01.929715 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4734 01:00:01.936376 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4735 01:00:01.939694 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4736 01:00:01.943269 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4737 01:00:01.946945 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4738 01:00:01.953369 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4739 01:00:01.956588 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4740 01:00:01.959838 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4741 01:00:01.963386 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4742 01:00:01.966327 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4743 01:00:01.973450 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4744 01:00:01.976591 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4745 01:00:01.979963 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4746 01:00:01.980541 ==
4747 01:00:01.983127 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 01:00:01.989632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 01:00:01.990249 ==
4750 01:00:01.990633 DQS Delay:
4751 01:00:01.990983 DQS0 = 0, DQS1 = 0
4752 01:00:01.993024 DQM Delay:
4753 01:00:01.993594 DQM0 = 52, DQM1 = 48
4754 01:00:01.996567 DQ Delay:
4755 01:00:02.000115 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4756 01:00:02.000692 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4757 01:00:02.003213 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4758 01:00:02.010187 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4759 01:00:02.010752
4760 01:00:02.011133
4761 01:00:02.011482 ==
4762 01:00:02.012899 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 01:00:02.016277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 01:00:02.016854 ==
4765 01:00:02.017233
4766 01:00:02.017580
4767 01:00:02.019879 TX Vref Scan disable
4768 01:00:02.020354 == TX Byte 0 ==
4769 01:00:02.026060 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4770 01:00:02.029858 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4771 01:00:02.030474 == TX Byte 1 ==
4772 01:00:02.036254 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4773 01:00:02.039730 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4774 01:00:02.040239 ==
4775 01:00:02.042750 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 01:00:02.046011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 01:00:02.046488 ==
4778 01:00:02.046868
4779 01:00:02.047219
4780 01:00:02.049098 TX Vref Scan disable
4781 01:00:02.052517 == TX Byte 0 ==
4782 01:00:02.055925 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4783 01:00:02.062681 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4784 01:00:02.063268 == TX Byte 1 ==
4785 01:00:02.066460 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4786 01:00:02.072923 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4787 01:00:02.073499
4788 01:00:02.073880 [DATLAT]
4789 01:00:02.074276 Freq=600, CH1 RK1
4790 01:00:02.074618
4791 01:00:02.075754 DATLAT Default: 0x9
4792 01:00:02.076227 0, 0xFFFF, sum = 0
4793 01:00:02.078904 1, 0xFFFF, sum = 0
4794 01:00:02.079387 2, 0xFFFF, sum = 0
4795 01:00:02.082867 3, 0xFFFF, sum = 0
4796 01:00:02.086058 4, 0xFFFF, sum = 0
4797 01:00:02.086642 5, 0xFFFF, sum = 0
4798 01:00:02.089322 6, 0xFFFF, sum = 0
4799 01:00:02.089906 7, 0xFFFF, sum = 0
4800 01:00:02.090329 8, 0x0, sum = 1
4801 01:00:02.092901 9, 0x0, sum = 2
4802 01:00:02.093479 10, 0x0, sum = 3
4803 01:00:02.095818 11, 0x0, sum = 4
4804 01:00:02.096402 best_step = 9
4805 01:00:02.096781
4806 01:00:02.097129 ==
4807 01:00:02.099376 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 01:00:02.106111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 01:00:02.106682 ==
4810 01:00:02.107067 RX Vref Scan: 0
4811 01:00:02.107420
4812 01:00:02.109393 RX Vref 0 -> 0, step: 1
4813 01:00:02.110008
4814 01:00:02.112703 RX Delay -163 -> 252, step: 8
4815 01:00:02.115886 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4816 01:00:02.122554 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4817 01:00:02.126081 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4818 01:00:02.128967 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4819 01:00:02.132331 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4820 01:00:02.135915 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4821 01:00:02.142359 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4822 01:00:02.145491 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4823 01:00:02.148998 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4824 01:00:02.152072 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4825 01:00:02.155681 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4826 01:00:02.162146 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4827 01:00:02.165519 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4828 01:00:02.168909 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4829 01:00:02.172414 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4830 01:00:02.178772 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4831 01:00:02.179354 ==
4832 01:00:02.182381 Dram Type= 6, Freq= 0, CH_1, rank 1
4833 01:00:02.185460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4834 01:00:02.186073 ==
4835 01:00:02.186458 DQS Delay:
4836 01:00:02.189210 DQS0 = 0, DQS1 = 0
4837 01:00:02.189785 DQM Delay:
4838 01:00:02.192399 DQM0 = 50, DQM1 = 44
4839 01:00:02.192970 DQ Delay:
4840 01:00:02.195710 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4841 01:00:02.198775 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4842 01:00:02.202205 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4843 01:00:02.205440 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =56
4844 01:00:02.206056
4845 01:00:02.206448
4846 01:00:02.212146 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4847 01:00:02.215598 CH1 RK1: MR19=808, MR18=5C22
4848 01:00:02.221897 CH1_RK1: MR19=0x808, MR18=0x5C22, DQSOSC=392, MR23=63, INC=170, DEC=113
4849 01:00:02.225842 [RxdqsGatingPostProcess] freq 600
4850 01:00:02.232193 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4851 01:00:02.232764 Pre-setting of DQS Precalculation
4852 01:00:02.238803 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4853 01:00:02.245500 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4854 01:00:02.251930 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4855 01:00:02.252503
4856 01:00:02.252876
4857 01:00:02.255643 [Calibration Summary] 1200 Mbps
4858 01:00:02.258202 CH 0, Rank 0
4859 01:00:02.258677 SW Impedance : PASS
4860 01:00:02.261858 DUTY Scan : NO K
4861 01:00:02.264855 ZQ Calibration : PASS
4862 01:00:02.265332 Jitter Meter : NO K
4863 01:00:02.268645 CBT Training : PASS
4864 01:00:02.269225 Write leveling : PASS
4865 01:00:02.271766 RX DQS gating : PASS
4866 01:00:02.275183 RX DQ/DQS(RDDQC) : PASS
4867 01:00:02.275765 TX DQ/DQS : PASS
4868 01:00:02.278600 RX DATLAT : PASS
4869 01:00:02.281582 RX DQ/DQS(Engine): PASS
4870 01:00:02.282085 TX OE : NO K
4871 01:00:02.285284 All Pass.
4872 01:00:02.285855
4873 01:00:02.286272 CH 0, Rank 1
4874 01:00:02.288419 SW Impedance : PASS
4875 01:00:02.288990 DUTY Scan : NO K
4876 01:00:02.292413 ZQ Calibration : PASS
4877 01:00:02.295137 Jitter Meter : NO K
4878 01:00:02.295711 CBT Training : PASS
4879 01:00:02.298577 Write leveling : PASS
4880 01:00:02.301528 RX DQS gating : PASS
4881 01:00:02.302138 RX DQ/DQS(RDDQC) : PASS
4882 01:00:02.305046 TX DQ/DQS : PASS
4883 01:00:02.308367 RX DATLAT : PASS
4884 01:00:02.308941 RX DQ/DQS(Engine): PASS
4885 01:00:02.311728 TX OE : NO K
4886 01:00:02.312303 All Pass.
4887 01:00:02.312681
4888 01:00:02.314820 CH 1, Rank 0
4889 01:00:02.315295 SW Impedance : PASS
4890 01:00:02.318785 DUTY Scan : NO K
4891 01:00:02.321590 ZQ Calibration : PASS
4892 01:00:02.322188 Jitter Meter : NO K
4893 01:00:02.324939 CBT Training : PASS
4894 01:00:02.327734 Write leveling : PASS
4895 01:00:02.328232 RX DQS gating : PASS
4896 01:00:02.331216 RX DQ/DQS(RDDQC) : PASS
4897 01:00:02.331788 TX DQ/DQS : PASS
4898 01:00:02.335167 RX DATLAT : PASS
4899 01:00:02.337631 RX DQ/DQS(Engine): PASS
4900 01:00:02.338278 TX OE : NO K
4901 01:00:02.341261 All Pass.
4902 01:00:02.341740
4903 01:00:02.342160 CH 1, Rank 1
4904 01:00:02.344590 SW Impedance : PASS
4905 01:00:02.345164 DUTY Scan : NO K
4906 01:00:02.347792 ZQ Calibration : PASS
4907 01:00:02.351627 Jitter Meter : NO K
4908 01:00:02.352225 CBT Training : PASS
4909 01:00:02.354495 Write leveling : PASS
4910 01:00:02.358491 RX DQS gating : PASS
4911 01:00:02.359072 RX DQ/DQS(RDDQC) : PASS
4912 01:00:02.361380 TX DQ/DQS : PASS
4913 01:00:02.364091 RX DATLAT : PASS
4914 01:00:02.364568 RX DQ/DQS(Engine): PASS
4915 01:00:02.367793 TX OE : NO K
4916 01:00:02.368272 All Pass.
4917 01:00:02.368652
4918 01:00:02.370698 DramC Write-DBI off
4919 01:00:02.374272 PER_BANK_REFRESH: Hybrid Mode
4920 01:00:02.374747 TX_TRACKING: ON
4921 01:00:02.384239 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4922 01:00:02.387619 [FAST_K] Save calibration result to emmc
4923 01:00:02.390618 dramc_set_vcore_voltage set vcore to 662500
4924 01:00:02.394412 Read voltage for 933, 3
4925 01:00:02.394839 Vio18 = 0
4926 01:00:02.395182 Vcore = 662500
4927 01:00:02.397410 Vdram = 0
4928 01:00:02.397840 Vddq = 0
4929 01:00:02.398245 Vmddr = 0
4930 01:00:02.404277 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4931 01:00:02.407665 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4932 01:00:02.411386 MEM_TYPE=3, freq_sel=17
4933 01:00:02.414138 sv_algorithm_assistance_LP4_1600
4934 01:00:02.417586 ============ PULL DRAM RESETB DOWN ============
4935 01:00:02.421092 ========== PULL DRAM RESETB DOWN end =========
4936 01:00:02.427547 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4937 01:00:02.430844 ===================================
4938 01:00:02.431375 LPDDR4 DRAM CONFIGURATION
4939 01:00:02.433892 ===================================
4940 01:00:02.437808 EX_ROW_EN[0] = 0x0
4941 01:00:02.440862 EX_ROW_EN[1] = 0x0
4942 01:00:02.441391 LP4Y_EN = 0x0
4943 01:00:02.444372 WORK_FSP = 0x0
4944 01:00:02.444919 WL = 0x3
4945 01:00:02.447704 RL = 0x3
4946 01:00:02.448235 BL = 0x2
4947 01:00:02.450495 RPST = 0x0
4948 01:00:02.450927 RD_PRE = 0x0
4949 01:00:02.453929 WR_PRE = 0x1
4950 01:00:02.454486 WR_PST = 0x0
4951 01:00:02.457511 DBI_WR = 0x0
4952 01:00:02.458072 DBI_RD = 0x0
4953 01:00:02.460565 OTF = 0x1
4954 01:00:02.464217 ===================================
4955 01:00:02.467165 ===================================
4956 01:00:02.467597 ANA top config
4957 01:00:02.470593 ===================================
4958 01:00:02.473910 DLL_ASYNC_EN = 0
4959 01:00:02.477526 ALL_SLAVE_EN = 1
4960 01:00:02.480383 NEW_RANK_MODE = 1
4961 01:00:02.480818 DLL_IDLE_MODE = 1
4962 01:00:02.483875 LP45_APHY_COMB_EN = 1
4963 01:00:02.487123 TX_ODT_DIS = 1
4964 01:00:02.490592 NEW_8X_MODE = 1
4965 01:00:02.494596 ===================================
4966 01:00:02.497357 ===================================
4967 01:00:02.500655 data_rate = 1866
4968 01:00:02.501185 CKR = 1
4969 01:00:02.503958 DQ_P2S_RATIO = 8
4970 01:00:02.507261 ===================================
4971 01:00:02.510557 CA_P2S_RATIO = 8
4972 01:00:02.514016 DQ_CA_OPEN = 0
4973 01:00:02.517197 DQ_SEMI_OPEN = 0
4974 01:00:02.517724 CA_SEMI_OPEN = 0
4975 01:00:02.520705 CA_FULL_RATE = 0
4976 01:00:02.523788 DQ_CKDIV4_EN = 1
4977 01:00:02.527204 CA_CKDIV4_EN = 1
4978 01:00:02.530845 CA_PREDIV_EN = 0
4979 01:00:02.534066 PH8_DLY = 0
4980 01:00:02.534589 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4981 01:00:02.537195 DQ_AAMCK_DIV = 4
4982 01:00:02.540436 CA_AAMCK_DIV = 4
4983 01:00:02.543746 CA_ADMCK_DIV = 4
4984 01:00:02.547541 DQ_TRACK_CA_EN = 0
4985 01:00:02.550494 CA_PICK = 933
4986 01:00:02.553479 CA_MCKIO = 933
4987 01:00:02.553914 MCKIO_SEMI = 0
4988 01:00:02.557257 PLL_FREQ = 3732
4989 01:00:02.560376 DQ_UI_PI_RATIO = 32
4990 01:00:02.563645 CA_UI_PI_RATIO = 0
4991 01:00:02.567075 ===================================
4992 01:00:02.570509 ===================================
4993 01:00:02.573483 memory_type:LPDDR4
4994 01:00:02.573915 GP_NUM : 10
4995 01:00:02.577080 SRAM_EN : 1
4996 01:00:02.580275 MD32_EN : 0
4997 01:00:02.580710 ===================================
4998 01:00:02.583949 [ANA_INIT] >>>>>>>>>>>>>>
4999 01:00:02.586831 <<<<<< [CONFIGURE PHASE]: ANA_TX
5000 01:00:02.590190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5001 01:00:02.594001 ===================================
5002 01:00:02.596957 data_rate = 1866,PCW = 0X8f00
5003 01:00:02.600436 ===================================
5004 01:00:02.603800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5005 01:00:02.610737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 01:00:02.613748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 01:00:02.620671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5008 01:00:02.623370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5009 01:00:02.626775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5010 01:00:02.627255 [ANA_INIT] flow start
5011 01:00:02.630334 [ANA_INIT] PLL >>>>>>>>
5012 01:00:02.633829 [ANA_INIT] PLL <<<<<<<<
5013 01:00:02.634432 [ANA_INIT] MIDPI >>>>>>>>
5014 01:00:02.637162 [ANA_INIT] MIDPI <<<<<<<<
5015 01:00:02.639964 [ANA_INIT] DLL >>>>>>>>
5016 01:00:02.640574 [ANA_INIT] flow end
5017 01:00:02.646689 ============ LP4 DIFF to SE enter ============
5018 01:00:02.650251 ============ LP4 DIFF to SE exit ============
5019 01:00:02.653652 [ANA_INIT] <<<<<<<<<<<<<
5020 01:00:02.657127 [Flow] Enable top DCM control >>>>>
5021 01:00:02.660055 [Flow] Enable top DCM control <<<<<
5022 01:00:02.660626 Enable DLL master slave shuffle
5023 01:00:02.666539 ==============================================================
5024 01:00:02.670277 Gating Mode config
5025 01:00:02.673420 ==============================================================
5026 01:00:02.676632 Config description:
5027 01:00:02.686691 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5028 01:00:02.693196 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5029 01:00:02.696456 SELPH_MODE 0: By rank 1: By Phase
5030 01:00:02.703063 ==============================================================
5031 01:00:02.706531 GAT_TRACK_EN = 1
5032 01:00:02.709841 RX_GATING_MODE = 2
5033 01:00:02.713058 RX_GATING_TRACK_MODE = 2
5034 01:00:02.716435 SELPH_MODE = 1
5035 01:00:02.717005 PICG_EARLY_EN = 1
5036 01:00:02.719939 VALID_LAT_VALUE = 1
5037 01:00:02.726422 ==============================================================
5038 01:00:02.730002 Enter into Gating configuration >>>>
5039 01:00:02.733316 Exit from Gating configuration <<<<
5040 01:00:02.736228 Enter into DVFS_PRE_config >>>>>
5041 01:00:02.746622 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5042 01:00:02.749222 Exit from DVFS_PRE_config <<<<<
5043 01:00:02.752949 Enter into PICG configuration >>>>
5044 01:00:02.756359 Exit from PICG configuration <<<<
5045 01:00:02.759710 [RX_INPUT] configuration >>>>>
5046 01:00:02.762754 [RX_INPUT] configuration <<<<<
5047 01:00:02.765992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5048 01:00:02.772767 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5049 01:00:02.779561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 01:00:02.785998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 01:00:02.792981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 01:00:02.796127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 01:00:02.802755 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5054 01:00:02.805970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5055 01:00:02.809724 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5056 01:00:02.812736 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5057 01:00:02.819341 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5058 01:00:02.822842 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 01:00:02.825852 ===================================
5060 01:00:02.829314 LPDDR4 DRAM CONFIGURATION
5061 01:00:02.832600 ===================================
5062 01:00:02.833170 EX_ROW_EN[0] = 0x0
5063 01:00:02.836246 EX_ROW_EN[1] = 0x0
5064 01:00:02.836819 LP4Y_EN = 0x0
5065 01:00:02.839426 WORK_FSP = 0x0
5066 01:00:02.839893 WL = 0x3
5067 01:00:02.842419 RL = 0x3
5068 01:00:02.842886 BL = 0x2
5069 01:00:02.845716 RPST = 0x0
5070 01:00:02.846215 RD_PRE = 0x0
5071 01:00:02.849250 WR_PRE = 0x1
5072 01:00:02.852612 WR_PST = 0x0
5073 01:00:02.853187 DBI_WR = 0x0
5074 01:00:02.856119 DBI_RD = 0x0
5075 01:00:02.856694 OTF = 0x1
5076 01:00:02.859255 ===================================
5077 01:00:02.862636 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5078 01:00:02.865767 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5079 01:00:02.872448 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5080 01:00:02.876061 ===================================
5081 01:00:02.879140 LPDDR4 DRAM CONFIGURATION
5082 01:00:02.882781 ===================================
5083 01:00:02.883251 EX_ROW_EN[0] = 0x10
5084 01:00:02.885961 EX_ROW_EN[1] = 0x0
5085 01:00:02.886575 LP4Y_EN = 0x0
5086 01:00:02.889338 WORK_FSP = 0x0
5087 01:00:02.889910 WL = 0x3
5088 01:00:02.892308 RL = 0x3
5089 01:00:02.892777 BL = 0x2
5090 01:00:02.896183 RPST = 0x0
5091 01:00:02.896767 RD_PRE = 0x0
5092 01:00:02.899146 WR_PRE = 0x1
5093 01:00:02.899616 WR_PST = 0x0
5094 01:00:02.902330 DBI_WR = 0x0
5095 01:00:02.902801 DBI_RD = 0x0
5096 01:00:02.906377 OTF = 0x1
5097 01:00:02.909035 ===================================
5098 01:00:02.915635 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5099 01:00:02.919223 nWR fixed to 30
5100 01:00:02.922187 [ModeRegInit_LP4] CH0 RK0
5101 01:00:02.922663 [ModeRegInit_LP4] CH0 RK1
5102 01:00:02.925913 [ModeRegInit_LP4] CH1 RK0
5103 01:00:02.929126 [ModeRegInit_LP4] CH1 RK1
5104 01:00:02.929705 match AC timing 9
5105 01:00:02.935693 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5106 01:00:02.938948 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5107 01:00:02.942364 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5108 01:00:02.949082 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5109 01:00:02.952073 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5110 01:00:02.952659 ==
5111 01:00:02.955344 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 01:00:02.958487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 01:00:02.958966 ==
5114 01:00:02.965661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 01:00:02.972315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5116 01:00:02.975498 [CA 0] Center 38 (7~69) winsize 63
5117 01:00:02.978606 [CA 1] Center 38 (8~69) winsize 62
5118 01:00:02.981996 [CA 2] Center 35 (5~66) winsize 62
5119 01:00:02.985514 [CA 3] Center 34 (4~65) winsize 62
5120 01:00:02.988520 [CA 4] Center 34 (4~65) winsize 62
5121 01:00:02.991793 [CA 5] Center 33 (3~64) winsize 62
5122 01:00:02.992263
5123 01:00:02.995334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5124 01:00:02.995914
5125 01:00:02.998437 [CATrainingPosCal] consider 1 rank data
5126 01:00:03.002126 u2DelayCellTimex100 = 270/100 ps
5127 01:00:03.005695 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5128 01:00:03.008509 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 01:00:03.011832 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5130 01:00:03.015378 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5131 01:00:03.018589 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5132 01:00:03.022079 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 01:00:03.024907
5134 01:00:03.028772 CA PerBit enable=1, Macro0, CA PI delay=33
5135 01:00:03.029342
5136 01:00:03.031951 [CBTSetCACLKResult] CA Dly = 33
5137 01:00:03.032519 CS Dly: 7 (0~38)
5138 01:00:03.032898 ==
5139 01:00:03.035467 Dram Type= 6, Freq= 0, CH_0, rank 1
5140 01:00:03.038810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 01:00:03.039381 ==
5142 01:00:03.045343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5143 01:00:03.052238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5144 01:00:03.055648 [CA 0] Center 38 (8~69) winsize 62
5145 01:00:03.058611 [CA 1] Center 38 (8~69) winsize 62
5146 01:00:03.061974 [CA 2] Center 36 (6~66) winsize 61
5147 01:00:03.065793 [CA 3] Center 35 (5~66) winsize 62
5148 01:00:03.068497 [CA 4] Center 34 (4~65) winsize 62
5149 01:00:03.072047 [CA 5] Center 34 (4~64) winsize 61
5150 01:00:03.072637
5151 01:00:03.075190 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5152 01:00:03.075763
5153 01:00:03.078326 [CATrainingPosCal] consider 2 rank data
5154 01:00:03.081775 u2DelayCellTimex100 = 270/100 ps
5155 01:00:03.085184 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5156 01:00:03.088496 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5157 01:00:03.091930 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5158 01:00:03.095803 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5159 01:00:03.098624 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5160 01:00:03.102076 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5161 01:00:03.104979
5162 01:00:03.108212 CA PerBit enable=1, Macro0, CA PI delay=34
5163 01:00:03.108681
5164 01:00:03.111934 [CBTSetCACLKResult] CA Dly = 34
5165 01:00:03.112408 CS Dly: 7 (0~39)
5166 01:00:03.112781
5167 01:00:03.114823 ----->DramcWriteLeveling(PI) begin...
5168 01:00:03.115299 ==
5169 01:00:03.118704 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 01:00:03.121586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 01:00:03.124682 ==
5172 01:00:03.125153 Write leveling (Byte 0): 31 => 31
5173 01:00:03.128918 Write leveling (Byte 1): 28 => 28
5174 01:00:03.131623 DramcWriteLeveling(PI) end<-----
5175 01:00:03.132174
5176 01:00:03.132548 ==
5177 01:00:03.134931 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 01:00:03.141203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 01:00:03.141684 ==
5180 01:00:03.144658 [Gating] SW mode calibration
5181 01:00:03.151863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5182 01:00:03.154640 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5183 01:00:03.161694 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5184 01:00:03.164890 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 01:00:03.168366 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 01:00:03.174793 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 01:00:03.178521 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 01:00:03.182010 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 01:00:03.187904 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5190 01:00:03.191275 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5191 01:00:03.194514 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
5192 01:00:03.197873 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 01:00:03.204921 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 01:00:03.207807 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 01:00:03.210971 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 01:00:03.217976 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 01:00:03.221581 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5198 01:00:03.224559 0 15 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
5199 01:00:03.230917 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5200 01:00:03.234700 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 01:00:03.237777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 01:00:03.244146 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 01:00:03.247849 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 01:00:03.250725 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 01:00:03.257977 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5206 01:00:03.260931 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5207 01:00:03.264130 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5208 01:00:03.271110 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 01:00:03.274303 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 01:00:03.277783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 01:00:03.284358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 01:00:03.287560 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 01:00:03.290784 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 01:00:03.297499 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 01:00:03.300812 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 01:00:03.303926 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 01:00:03.310942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 01:00:03.314247 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 01:00:03.317153 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 01:00:03.323854 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 01:00:03.327582 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5222 01:00:03.330445 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5223 01:00:03.337244 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5224 01:00:03.337833 Total UI for P1: 0, mck2ui 16
5225 01:00:03.340874 best dqsien dly found for B0: ( 1, 2, 26)
5226 01:00:03.347009 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 01:00:03.350159 Total UI for P1: 0, mck2ui 16
5228 01:00:03.353859 best dqsien dly found for B1: ( 1, 3, 0)
5229 01:00:03.357104 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5230 01:00:03.360346 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5231 01:00:03.360921
5232 01:00:03.364217 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5233 01:00:03.366790 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5234 01:00:03.370452 [Gating] SW calibration Done
5235 01:00:03.370929 ==
5236 01:00:03.373504 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 01:00:03.377184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 01:00:03.377770 ==
5239 01:00:03.380400 RX Vref Scan: 0
5240 01:00:03.380980
5241 01:00:03.384044 RX Vref 0 -> 0, step: 1
5242 01:00:03.384630
5243 01:00:03.385011 RX Delay -80 -> 252, step: 8
5244 01:00:03.390593 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5245 01:00:03.393638 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5246 01:00:03.397060 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5247 01:00:03.400560 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5248 01:00:03.403615 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5249 01:00:03.407227 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5250 01:00:03.413696 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5251 01:00:03.416793 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5252 01:00:03.420580 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5253 01:00:03.423804 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5254 01:00:03.426608 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5255 01:00:03.430547 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5256 01:00:03.436839 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5257 01:00:03.440316 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5258 01:00:03.443468 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5259 01:00:03.446626 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5260 01:00:03.447105 ==
5261 01:00:03.450285 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 01:00:03.453545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 01:00:03.456793 ==
5264 01:00:03.457361 DQS Delay:
5265 01:00:03.457740 DQS0 = 0, DQS1 = 0
5266 01:00:03.460667 DQM Delay:
5267 01:00:03.461238 DQM0 = 105, DQM1 = 90
5268 01:00:03.463294 DQ Delay:
5269 01:00:03.466478 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5270 01:00:03.469812 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5271 01:00:03.473568 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5272 01:00:03.476697 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5273 01:00:03.477269
5274 01:00:03.477647
5275 01:00:03.478051 ==
5276 01:00:03.480409 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 01:00:03.483568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 01:00:03.484146 ==
5279 01:00:03.484528
5280 01:00:03.484878
5281 01:00:03.487106 TX Vref Scan disable
5282 01:00:03.487678 == TX Byte 0 ==
5283 01:00:03.493610 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5284 01:00:03.497154 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5285 01:00:03.497726 == TX Byte 1 ==
5286 01:00:03.503555 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5287 01:00:03.507177 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5288 01:00:03.507754 ==
5289 01:00:03.510223 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 01:00:03.513137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 01:00:03.513717 ==
5292 01:00:03.514145
5293 01:00:03.514502
5294 01:00:03.516633 TX Vref Scan disable
5295 01:00:03.520129 == TX Byte 0 ==
5296 01:00:03.523132 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5297 01:00:03.526642 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5298 01:00:03.529784 == TX Byte 1 ==
5299 01:00:03.533371 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5300 01:00:03.536819 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5301 01:00:03.537396
5302 01:00:03.540470 [DATLAT]
5303 01:00:03.541053 Freq=933, CH0 RK0
5304 01:00:03.541435
5305 01:00:03.543173 DATLAT Default: 0xd
5306 01:00:03.543644 0, 0xFFFF, sum = 0
5307 01:00:03.546487 1, 0xFFFF, sum = 0
5308 01:00:03.547118 2, 0xFFFF, sum = 0
5309 01:00:03.549664 3, 0xFFFF, sum = 0
5310 01:00:03.550226 4, 0xFFFF, sum = 0
5311 01:00:03.553013 5, 0xFFFF, sum = 0
5312 01:00:03.553602 6, 0xFFFF, sum = 0
5313 01:00:03.556638 7, 0xFFFF, sum = 0
5314 01:00:03.557241 8, 0xFFFF, sum = 0
5315 01:00:03.559878 9, 0xFFFF, sum = 0
5316 01:00:03.560358 10, 0x0, sum = 1
5317 01:00:03.563171 11, 0x0, sum = 2
5318 01:00:03.563655 12, 0x0, sum = 3
5319 01:00:03.566538 13, 0x0, sum = 4
5320 01:00:03.567016 best_step = 11
5321 01:00:03.567396
5322 01:00:03.567742 ==
5323 01:00:03.570003 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 01:00:03.576362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 01:00:03.576921 ==
5326 01:00:03.577302 RX Vref Scan: 1
5327 01:00:03.577649
5328 01:00:03.579451 RX Vref 0 -> 0, step: 1
5329 01:00:03.579926
5330 01:00:03.582911 RX Delay -53 -> 252, step: 4
5331 01:00:03.583387
5332 01:00:03.586215 Set Vref, RX VrefLevel [Byte0]: 60
5333 01:00:03.589874 [Byte1]: 50
5334 01:00:03.590489
5335 01:00:03.592945 Final RX Vref Byte 0 = 60 to rank0
5336 01:00:03.596275 Final RX Vref Byte 1 = 50 to rank0
5337 01:00:03.599767 Final RX Vref Byte 0 = 60 to rank1
5338 01:00:03.602778 Final RX Vref Byte 1 = 50 to rank1==
5339 01:00:03.606411 Dram Type= 6, Freq= 0, CH_0, rank 0
5340 01:00:03.609316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 01:00:03.609905 ==
5342 01:00:03.612732 DQS Delay:
5343 01:00:03.613338 DQS0 = 0, DQS1 = 0
5344 01:00:03.615981 DQM Delay:
5345 01:00:03.616566 DQM0 = 107, DQM1 = 92
5346 01:00:03.616944 DQ Delay:
5347 01:00:03.619361 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5348 01:00:03.625930 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =116
5349 01:00:03.626539 DQ8 =86, DQ9 =76, DQ10 =94, DQ11 =90
5350 01:00:03.633111 DQ12 =98, DQ13 =92, DQ14 =100, DQ15 =100
5351 01:00:03.633692
5352 01:00:03.634129
5353 01:00:03.639211 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5354 01:00:03.642556 CH0 RK0: MR19=505, MR18=2723
5355 01:00:03.649159 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5356 01:00:03.649632
5357 01:00:03.652393 ----->DramcWriteLeveling(PI) begin...
5358 01:00:03.652969 ==
5359 01:00:03.655588 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 01:00:03.659021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 01:00:03.659483 ==
5362 01:00:03.662132 Write leveling (Byte 0): 35 => 35
5363 01:00:03.665798 Write leveling (Byte 1): 29 => 29
5364 01:00:03.668907 DramcWriteLeveling(PI) end<-----
5365 01:00:03.669362
5366 01:00:03.669722 ==
5367 01:00:03.672239 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 01:00:03.675561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 01:00:03.676026 ==
5370 01:00:03.678952 [Gating] SW mode calibration
5371 01:00:03.686218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5372 01:00:03.692680 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5373 01:00:03.695759 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 01:00:03.698949 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 01:00:03.705781 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 01:00:03.709099 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 01:00:03.712560 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 01:00:03.719257 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 01:00:03.722449 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
5380 01:00:03.725786 0 14 28 | B1->B0 | 2626 2525 | 0 1 | (0 0) (1 0)
5381 01:00:03.732930 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 01:00:03.735738 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 01:00:03.739153 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 01:00:03.745597 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 01:00:03.748919 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 01:00:03.752261 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 01:00:03.758834 0 15 24 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5388 01:00:03.762494 0 15 28 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
5389 01:00:03.765685 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 01:00:03.772476 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 01:00:03.775691 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 01:00:03.779455 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 01:00:03.785963 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 01:00:03.789320 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 01:00:03.792807 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 01:00:03.799479 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5397 01:00:03.802283 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 01:00:03.805802 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 01:00:03.809099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 01:00:03.816130 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 01:00:03.819038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 01:00:03.822527 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 01:00:03.829653 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 01:00:03.832452 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 01:00:03.835428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 01:00:03.842293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 01:00:03.845619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 01:00:03.849154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 01:00:03.855779 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 01:00:03.859428 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 01:00:03.862113 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 01:00:03.868901 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5413 01:00:03.869544 Total UI for P1: 0, mck2ui 16
5414 01:00:03.875632 best dqsien dly found for B0: ( 1, 2, 26)
5415 01:00:03.879109 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 01:00:03.882751 Total UI for P1: 0, mck2ui 16
5417 01:00:03.885726 best dqsien dly found for B1: ( 1, 2, 28)
5418 01:00:03.889014 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5419 01:00:03.892417 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5420 01:00:03.893000
5421 01:00:03.895733 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5422 01:00:03.898846 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5423 01:00:03.902833 [Gating] SW calibration Done
5424 01:00:03.903424 ==
5425 01:00:03.905459 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 01:00:03.909089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 01:00:03.909675 ==
5428 01:00:03.912325 RX Vref Scan: 0
5429 01:00:03.912905
5430 01:00:03.915781 RX Vref 0 -> 0, step: 1
5431 01:00:03.916365
5432 01:00:03.916849 RX Delay -80 -> 252, step: 8
5433 01:00:03.922393 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5434 01:00:03.925832 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5435 01:00:03.928955 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5436 01:00:03.932290 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5437 01:00:03.935333 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5438 01:00:03.942320 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5439 01:00:03.945470 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5440 01:00:03.948787 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5441 01:00:03.952257 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5442 01:00:03.955946 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5443 01:00:03.958739 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5444 01:00:03.965487 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5445 01:00:03.968713 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5446 01:00:03.972343 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5447 01:00:03.975700 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5448 01:00:03.978863 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5449 01:00:03.979340 ==
5450 01:00:03.981959 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 01:00:03.989039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 01:00:03.989620 ==
5453 01:00:03.990037 DQS Delay:
5454 01:00:03.992366 DQS0 = 0, DQS1 = 0
5455 01:00:03.992937 DQM Delay:
5456 01:00:03.995477 DQM0 = 105, DQM1 = 92
5457 01:00:03.996048 DQ Delay:
5458 01:00:03.998716 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =103
5459 01:00:04.001792 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5460 01:00:04.005430 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5461 01:00:04.008766 DQ12 =95, DQ13 =91, DQ14 =103, DQ15 =103
5462 01:00:04.009344
5463 01:00:04.009724
5464 01:00:04.010132 ==
5465 01:00:04.012162 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 01:00:04.015019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 01:00:04.015596 ==
5468 01:00:04.015978
5469 01:00:04.018396
5470 01:00:04.018866 TX Vref Scan disable
5471 01:00:04.021984 == TX Byte 0 ==
5472 01:00:04.025144 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5473 01:00:04.028575 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5474 01:00:04.031702 == TX Byte 1 ==
5475 01:00:04.035015 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5476 01:00:04.038288 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5477 01:00:04.038868 ==
5478 01:00:04.041733 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 01:00:04.048184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 01:00:04.048760 ==
5481 01:00:04.049141
5482 01:00:04.049488
5483 01:00:04.049821 TX Vref Scan disable
5484 01:00:04.052829 == TX Byte 0 ==
5485 01:00:04.055787 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5486 01:00:04.062454 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5487 01:00:04.063145 == TX Byte 1 ==
5488 01:00:04.065885 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5489 01:00:04.072707 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5490 01:00:04.073339
5491 01:00:04.073722 [DATLAT]
5492 01:00:04.074183 Freq=933, CH0 RK1
5493 01:00:04.074542
5494 01:00:04.076019 DATLAT Default: 0xb
5495 01:00:04.076497 0, 0xFFFF, sum = 0
5496 01:00:04.079007 1, 0xFFFF, sum = 0
5497 01:00:04.079485 2, 0xFFFF, sum = 0
5498 01:00:04.082620 3, 0xFFFF, sum = 0
5499 01:00:04.085804 4, 0xFFFF, sum = 0
5500 01:00:04.086420 5, 0xFFFF, sum = 0
5501 01:00:04.089179 6, 0xFFFF, sum = 0
5502 01:00:04.089755 7, 0xFFFF, sum = 0
5503 01:00:04.092492 8, 0xFFFF, sum = 0
5504 01:00:04.092972 9, 0xFFFF, sum = 0
5505 01:00:04.095636 10, 0x0, sum = 1
5506 01:00:04.096113 11, 0x0, sum = 2
5507 01:00:04.099298 12, 0x0, sum = 3
5508 01:00:04.099873 13, 0x0, sum = 4
5509 01:00:04.100255 best_step = 11
5510 01:00:04.100602
5511 01:00:04.102595 ==
5512 01:00:04.103163 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 01:00:04.109377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 01:00:04.109985 ==
5515 01:00:04.110374 RX Vref Scan: 0
5516 01:00:04.110726
5517 01:00:04.112592 RX Vref 0 -> 0, step: 1
5518 01:00:04.113063
5519 01:00:04.115533 RX Delay -53 -> 252, step: 4
5520 01:00:04.119387 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5521 01:00:04.126074 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5522 01:00:04.129106 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5523 01:00:04.132704 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5524 01:00:04.135820 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5525 01:00:04.139254 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5526 01:00:04.145557 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5527 01:00:04.149053 iDelay=203, Bit 7, Center 114 (31 ~ 198) 168
5528 01:00:04.152314 iDelay=203, Bit 8, Center 86 (3 ~ 170) 168
5529 01:00:04.155535 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5530 01:00:04.159169 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5531 01:00:04.162466 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5532 01:00:04.169072 iDelay=203, Bit 12, Center 98 (11 ~ 186) 176
5533 01:00:04.172443 iDelay=203, Bit 13, Center 96 (15 ~ 178) 164
5534 01:00:04.175408 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5535 01:00:04.179582 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5536 01:00:04.180161 ==
5537 01:00:04.182519 Dram Type= 6, Freq= 0, CH_0, rank 1
5538 01:00:04.188819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 01:00:04.189392 ==
5540 01:00:04.189773 DQS Delay:
5541 01:00:04.190162 DQS0 = 0, DQS1 = 0
5542 01:00:04.192011 DQM Delay:
5543 01:00:04.192481 DQM0 = 104, DQM1 = 93
5544 01:00:04.195283 DQ Delay:
5545 01:00:04.198872 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5546 01:00:04.202061 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =114
5547 01:00:04.205496 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5548 01:00:04.208717 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5549 01:00:04.209291
5550 01:00:04.209666
5551 01:00:04.215266 [DQSOSCAuto] RK1, (LSB)MR18= 0x2506, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 410 ps
5552 01:00:04.218895 CH0 RK1: MR19=505, MR18=2506
5553 01:00:04.225156 CH0_RK1: MR19=0x505, MR18=0x2506, DQSOSC=410, MR23=63, INC=64, DEC=42
5554 01:00:04.228702 [RxdqsGatingPostProcess] freq 933
5555 01:00:04.235189 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5556 01:00:04.235764 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 01:00:04.239119 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 01:00:04.241970 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 01:00:04.245491 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 01:00:04.248489 best DQS0 dly(2T, 0.5T) = (0, 10)
5561 01:00:04.251489 best DQS1 dly(2T, 0.5T) = (0, 10)
5562 01:00:04.255229 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5563 01:00:04.258451 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5564 01:00:04.261827 Pre-setting of DQS Precalculation
5565 01:00:04.268292 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5566 01:00:04.268819 ==
5567 01:00:04.271564 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 01:00:04.274578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 01:00:04.275047 ==
5570 01:00:04.281513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 01:00:04.284834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5572 01:00:04.289419 [CA 0] Center 37 (7~67) winsize 61
5573 01:00:04.292482 [CA 1] Center 37 (6~68) winsize 63
5574 01:00:04.295276 [CA 2] Center 35 (5~65) winsize 61
5575 01:00:04.298731 [CA 3] Center 34 (4~65) winsize 62
5576 01:00:04.302342 [CA 4] Center 34 (4~65) winsize 62
5577 01:00:04.305898 [CA 5] Center 34 (4~65) winsize 62
5578 01:00:04.306500
5579 01:00:04.309055 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5580 01:00:04.309617
5581 01:00:04.312685 [CATrainingPosCal] consider 1 rank data
5582 01:00:04.315658 u2DelayCellTimex100 = 270/100 ps
5583 01:00:04.318787 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5584 01:00:04.322202 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5585 01:00:04.328993 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5586 01:00:04.332150 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5587 01:00:04.335650 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5588 01:00:04.338714 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5589 01:00:04.339285
5590 01:00:04.342213 CA PerBit enable=1, Macro0, CA PI delay=34
5591 01:00:04.342779
5592 01:00:04.345583 [CBTSetCACLKResult] CA Dly = 34
5593 01:00:04.346177 CS Dly: 5 (0~36)
5594 01:00:04.348545 ==
5595 01:00:04.349404 Dram Type= 6, Freq= 0, CH_1, rank 1
5596 01:00:04.355075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 01:00:04.355643 ==
5598 01:00:04.358791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5599 01:00:04.365152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5600 01:00:04.368640 [CA 0] Center 37 (7~68) winsize 62
5601 01:00:04.372127 [CA 1] Center 37 (7~68) winsize 62
5602 01:00:04.375138 [CA 2] Center 35 (5~66) winsize 62
5603 01:00:04.378421 [CA 3] Center 34 (4~65) winsize 62
5604 01:00:04.382060 [CA 4] Center 35 (5~65) winsize 61
5605 01:00:04.385045 [CA 5] Center 34 (4~64) winsize 61
5606 01:00:04.385659
5607 01:00:04.388508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5608 01:00:04.389071
5609 01:00:04.391696 [CATrainingPosCal] consider 2 rank data
5610 01:00:04.395209 u2DelayCellTimex100 = 270/100 ps
5611 01:00:04.398325 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5612 01:00:04.404963 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5613 01:00:04.408755 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5614 01:00:04.411707 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5615 01:00:04.415504 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5616 01:00:04.418667 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5617 01:00:04.419238
5618 01:00:04.421785 CA PerBit enable=1, Macro0, CA PI delay=34
5619 01:00:04.422384
5620 01:00:04.425030 [CBTSetCACLKResult] CA Dly = 34
5621 01:00:04.425600 CS Dly: 6 (0~38)
5622 01:00:04.428032
5623 01:00:04.431806 ----->DramcWriteLeveling(PI) begin...
5624 01:00:04.432396 ==
5625 01:00:04.434864 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 01:00:04.438229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 01:00:04.438817 ==
5628 01:00:04.441406 Write leveling (Byte 0): 26 => 26
5629 01:00:04.444851 Write leveling (Byte 1): 29 => 29
5630 01:00:04.448136 DramcWriteLeveling(PI) end<-----
5631 01:00:04.448720
5632 01:00:04.449292 ==
5633 01:00:04.451343 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 01:00:04.455154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 01:00:04.455732 ==
5636 01:00:04.458289 [Gating] SW mode calibration
5637 01:00:04.464828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5638 01:00:04.471588 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5639 01:00:04.474671 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 01:00:04.477673 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 01:00:04.484390 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 01:00:04.487817 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 01:00:04.491014 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 01:00:04.497722 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 01:00:04.501118 0 14 24 | B1->B0 | 3030 3030 | 0 0 | (0 0) (1 0)
5646 01:00:04.504481 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 01:00:04.511370 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 01:00:04.514425 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 01:00:04.517394 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 01:00:04.524175 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 01:00:04.527217 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 01:00:04.531023 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 01:00:04.538026 0 15 24 | B1->B0 | 2a2a 2e2e | 0 0 | (0 0) (0 0)
5654 01:00:04.540934 0 15 28 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (0 0)
5655 01:00:04.544205 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 01:00:04.550924 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 01:00:04.554053 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 01:00:04.558035 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 01:00:04.564342 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 01:00:04.567571 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 01:00:04.570539 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5662 01:00:04.577333 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5663 01:00:04.581038 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 01:00:04.583916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 01:00:04.587279 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 01:00:04.593893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 01:00:04.597531 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 01:00:04.600668 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 01:00:04.607331 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 01:00:04.610949 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 01:00:04.614670 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 01:00:04.620466 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 01:00:04.624056 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 01:00:04.627052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 01:00:04.634126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 01:00:04.637140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5677 01:00:04.640408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5678 01:00:04.647365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 01:00:04.647949 Total UI for P1: 0, mck2ui 16
5680 01:00:04.654177 best dqsien dly found for B0: ( 1, 2, 22)
5681 01:00:04.654754 Total UI for P1: 0, mck2ui 16
5682 01:00:04.660566 best dqsien dly found for B1: ( 1, 2, 26)
5683 01:00:04.664010 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5684 01:00:04.667533 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5685 01:00:04.668107
5686 01:00:04.670251 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5687 01:00:04.673834 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5688 01:00:04.677138 [Gating] SW calibration Done
5689 01:00:04.677690 ==
5690 01:00:04.680965 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 01:00:04.683730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 01:00:04.684315 ==
5693 01:00:04.686939 RX Vref Scan: 0
5694 01:00:04.687517
5695 01:00:04.687893 RX Vref 0 -> 0, step: 1
5696 01:00:04.688236
5697 01:00:04.690881 RX Delay -80 -> 252, step: 8
5698 01:00:04.693969 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5699 01:00:04.700148 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5700 01:00:04.703957 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5701 01:00:04.707136 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5702 01:00:04.710690 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5703 01:00:04.713356 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5704 01:00:04.720275 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5705 01:00:04.723743 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5706 01:00:04.726917 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5707 01:00:04.730043 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5708 01:00:04.733521 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5709 01:00:04.736712 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5710 01:00:04.743515 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5711 01:00:04.746891 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5712 01:00:04.750729 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5713 01:00:04.753248 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5714 01:00:04.753720 ==
5715 01:00:04.757184 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 01:00:04.763425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 01:00:04.764001 ==
5718 01:00:04.764379 DQS Delay:
5719 01:00:04.766765 DQS0 = 0, DQS1 = 0
5720 01:00:04.767238 DQM Delay:
5721 01:00:04.767614 DQM0 = 104, DQM1 = 99
5722 01:00:04.769630 DQ Delay:
5723 01:00:04.773418 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5724 01:00:04.776557 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5725 01:00:04.780275 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =95
5726 01:00:04.783368 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =103
5727 01:00:04.783941
5728 01:00:04.784318
5729 01:00:04.784667 ==
5730 01:00:04.786399 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 01:00:04.789970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 01:00:04.790559 ==
5733 01:00:04.790939
5734 01:00:04.793594
5735 01:00:04.794102 TX Vref Scan disable
5736 01:00:04.797054 == TX Byte 0 ==
5737 01:00:04.799807 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5738 01:00:04.803533 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5739 01:00:04.806599 == TX Byte 1 ==
5740 01:00:04.809594 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5741 01:00:04.813492 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5742 01:00:04.814125 ==
5743 01:00:04.816571 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 01:00:04.823041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 01:00:04.823797 ==
5746 01:00:04.824199
5747 01:00:04.824550
5748 01:00:04.824888 TX Vref Scan disable
5749 01:00:04.827317 == TX Byte 0 ==
5750 01:00:04.830516 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5751 01:00:04.834191 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5752 01:00:04.837647 == TX Byte 1 ==
5753 01:00:04.840523 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5754 01:00:04.844164 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5755 01:00:04.847170
5756 01:00:04.847746 [DATLAT]
5757 01:00:04.848121 Freq=933, CH1 RK0
5758 01:00:04.848472
5759 01:00:04.850500 DATLAT Default: 0xd
5760 01:00:04.850969 0, 0xFFFF, sum = 0
5761 01:00:04.853620 1, 0xFFFF, sum = 0
5762 01:00:04.854116 2, 0xFFFF, sum = 0
5763 01:00:04.856845 3, 0xFFFF, sum = 0
5764 01:00:04.860579 4, 0xFFFF, sum = 0
5765 01:00:04.861165 5, 0xFFFF, sum = 0
5766 01:00:04.863836 6, 0xFFFF, sum = 0
5767 01:00:04.864421 7, 0xFFFF, sum = 0
5768 01:00:04.867123 8, 0xFFFF, sum = 0
5769 01:00:04.867712 9, 0xFFFF, sum = 0
5770 01:00:04.870142 10, 0x0, sum = 1
5771 01:00:04.870621 11, 0x0, sum = 2
5772 01:00:04.871004 12, 0x0, sum = 3
5773 01:00:04.873498 13, 0x0, sum = 4
5774 01:00:04.874002 best_step = 11
5775 01:00:04.874380
5776 01:00:04.877115 ==
5777 01:00:04.880398 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 01:00:04.883615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 01:00:04.884196 ==
5780 01:00:04.884582 RX Vref Scan: 1
5781 01:00:04.884934
5782 01:00:04.887057 RX Vref 0 -> 0, step: 1
5783 01:00:04.887631
5784 01:00:04.890278 RX Delay -53 -> 252, step: 4
5785 01:00:04.890846
5786 01:00:04.893714 Set Vref, RX VrefLevel [Byte0]: 51
5787 01:00:04.897087 [Byte1]: 52
5788 01:00:04.897660
5789 01:00:04.900262 Final RX Vref Byte 0 = 51 to rank0
5790 01:00:04.903847 Final RX Vref Byte 1 = 52 to rank0
5791 01:00:04.906903 Final RX Vref Byte 0 = 51 to rank1
5792 01:00:04.910130 Final RX Vref Byte 1 = 52 to rank1==
5793 01:00:04.913292 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 01:00:04.916923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 01:00:04.917495 ==
5796 01:00:04.920610 DQS Delay:
5797 01:00:04.921185 DQS0 = 0, DQS1 = 0
5798 01:00:04.923193 DQM Delay:
5799 01:00:04.923661 DQM0 = 107, DQM1 = 100
5800 01:00:04.926579 DQ Delay:
5801 01:00:04.929898 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5802 01:00:04.933134 DQ4 =108, DQ5 =114, DQ6 =116, DQ7 =104
5803 01:00:04.937082 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =92
5804 01:00:04.939745 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =106
5805 01:00:04.940257
5806 01:00:04.940631
5807 01:00:04.946348 [DQSOSCAuto] RK0, (LSB)MR18= 0x1831, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5808 01:00:04.950015 CH1 RK0: MR19=505, MR18=1831
5809 01:00:04.956802 CH1_RK0: MR19=0x505, MR18=0x1831, DQSOSC=406, MR23=63, INC=65, DEC=43
5810 01:00:04.957377
5811 01:00:04.959960 ----->DramcWriteLeveling(PI) begin...
5812 01:00:04.960540 ==
5813 01:00:04.963744 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 01:00:04.966551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 01:00:04.967022 ==
5816 01:00:04.970280 Write leveling (Byte 0): 24 => 24
5817 01:00:04.973669 Write leveling (Byte 1): 30 => 30
5818 01:00:04.976520 DramcWriteLeveling(PI) end<-----
5819 01:00:04.977092
5820 01:00:04.977465 ==
5821 01:00:04.980247 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 01:00:04.983412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 01:00:04.986554 ==
5824 01:00:04.987126 [Gating] SW mode calibration
5825 01:00:04.996987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5826 01:00:04.999879 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5827 01:00:05.003240 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5828 01:00:05.009848 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 01:00:05.012958 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 01:00:05.016447 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 01:00:05.023271 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 01:00:05.026214 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 01:00:05.029394 0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (1 0) (0 1)
5834 01:00:05.036555 0 14 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 1)
5835 01:00:05.039913 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 01:00:05.043019 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 01:00:05.049234 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 01:00:05.052719 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 01:00:05.056224 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 01:00:05.062713 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 01:00:05.065902 0 15 24 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
5842 01:00:05.069747 0 15 28 | B1->B0 | 3e3e 3333 | 0 0 | (0 0) (0 0)
5843 01:00:05.076298 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 01:00:05.079217 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 01:00:05.082543 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 01:00:05.089551 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 01:00:05.092876 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 01:00:05.096246 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5849 01:00:05.102813 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5850 01:00:05.106225 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5851 01:00:05.109448 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 01:00:05.115849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 01:00:05.119159 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 01:00:05.122463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 01:00:05.128975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 01:00:05.132240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 01:00:05.135482 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 01:00:05.142522 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 01:00:05.145704 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 01:00:05.149030 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 01:00:05.152252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 01:00:05.159237 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 01:00:05.162142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 01:00:05.165484 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 01:00:05.172128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 01:00:05.175604 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 01:00:05.179026 Total UI for P1: 0, mck2ui 16
5868 01:00:05.182183 best dqsien dly found for B0: ( 1, 2, 26)
5869 01:00:05.185772 Total UI for P1: 0, mck2ui 16
5870 01:00:05.188649 best dqsien dly found for B1: ( 1, 2, 26)
5871 01:00:05.192179 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5872 01:00:05.195667 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5873 01:00:05.196240
5874 01:00:05.198950 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5875 01:00:05.202096 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5876 01:00:05.205492 [Gating] SW calibration Done
5877 01:00:05.206093 ==
5878 01:00:05.208860 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 01:00:05.215457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 01:00:05.216034 ==
5881 01:00:05.216414 RX Vref Scan: 0
5882 01:00:05.216762
5883 01:00:05.218708 RX Vref 0 -> 0, step: 1
5884 01:00:05.219178
5885 01:00:05.222072 RX Delay -80 -> 252, step: 8
5886 01:00:05.225588 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5887 01:00:05.228780 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5888 01:00:05.232091 iDelay=200, Bit 2, Center 95 (16 ~ 175) 160
5889 01:00:05.235376 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5890 01:00:05.241900 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5891 01:00:05.245461 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5892 01:00:05.248276 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5893 01:00:05.252281 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5894 01:00:05.254941 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5895 01:00:05.258467 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5896 01:00:05.265030 iDelay=200, Bit 10, Center 103 (16 ~ 191) 176
5897 01:00:05.268831 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5898 01:00:05.272238 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5899 01:00:05.275210 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5900 01:00:05.281833 iDelay=200, Bit 14, Center 107 (16 ~ 199) 184
5901 01:00:05.285279 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5902 01:00:05.285850 ==
5903 01:00:05.288949 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 01:00:05.291661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 01:00:05.292235 ==
5906 01:00:05.292615 DQS Delay:
5907 01:00:05.295436 DQS0 = 0, DQS1 = 0
5908 01:00:05.296005 DQM Delay:
5909 01:00:05.298316 DQM0 = 105, DQM1 = 100
5910 01:00:05.298887 DQ Delay:
5911 01:00:05.301683 DQ0 =111, DQ1 =99, DQ2 =95, DQ3 =103
5912 01:00:05.305244 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =103
5913 01:00:05.308579 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =95
5914 01:00:05.312231 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5915 01:00:05.312802
5916 01:00:05.313177
5917 01:00:05.315079 ==
5918 01:00:05.318448 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 01:00:05.322099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 01:00:05.322678 ==
5921 01:00:05.323055
5922 01:00:05.323401
5923 01:00:05.325251 TX Vref Scan disable
5924 01:00:05.325823 == TX Byte 0 ==
5925 01:00:05.328427 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5926 01:00:05.335218 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5927 01:00:05.335789 == TX Byte 1 ==
5928 01:00:05.338427 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5929 01:00:05.345260 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5930 01:00:05.345836 ==
5931 01:00:05.348141 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 01:00:05.352224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 01:00:05.352699 ==
5934 01:00:05.353072
5935 01:00:05.353415
5936 01:00:05.354846 TX Vref Scan disable
5937 01:00:05.357998 == TX Byte 0 ==
5938 01:00:05.361547 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5939 01:00:05.365074 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5940 01:00:05.368073 == TX Byte 1 ==
5941 01:00:05.371327 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5942 01:00:05.374496 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5943 01:00:05.374967
5944 01:00:05.378502 [DATLAT]
5945 01:00:05.379157 Freq=933, CH1 RK1
5946 01:00:05.379563
5947 01:00:05.381457 DATLAT Default: 0xb
5948 01:00:05.382076 0, 0xFFFF, sum = 0
5949 01:00:05.385084 1, 0xFFFF, sum = 0
5950 01:00:05.385659 2, 0xFFFF, sum = 0
5951 01:00:05.388144 3, 0xFFFF, sum = 0
5952 01:00:05.388720 4, 0xFFFF, sum = 0
5953 01:00:05.391568 5, 0xFFFF, sum = 0
5954 01:00:05.392149 6, 0xFFFF, sum = 0
5955 01:00:05.394871 7, 0xFFFF, sum = 0
5956 01:00:05.395450 8, 0xFFFF, sum = 0
5957 01:00:05.398028 9, 0xFFFF, sum = 0
5958 01:00:05.398605 10, 0x0, sum = 1
5959 01:00:05.401458 11, 0x0, sum = 2
5960 01:00:05.402082 12, 0x0, sum = 3
5961 01:00:05.404763 13, 0x0, sum = 4
5962 01:00:05.405340 best_step = 11
5963 01:00:05.405719
5964 01:00:05.406116 ==
5965 01:00:05.408140 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 01:00:05.411505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 01:00:05.414660 ==
5968 01:00:05.415231 RX Vref Scan: 0
5969 01:00:05.415609
5970 01:00:05.418494 RX Vref 0 -> 0, step: 1
5971 01:00:05.419065
5972 01:00:05.421275 RX Delay -45 -> 252, step: 4
5973 01:00:05.424793 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5974 01:00:05.427869 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5975 01:00:05.434551 iDelay=199, Bit 2, Center 98 (23 ~ 174) 152
5976 01:00:05.437762 iDelay=199, Bit 3, Center 104 (27 ~ 182) 156
5977 01:00:05.440975 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5978 01:00:05.444204 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5979 01:00:05.448051 iDelay=199, Bit 6, Center 116 (39 ~ 194) 156
5980 01:00:05.451616 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5981 01:00:05.457638 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5982 01:00:05.460964 iDelay=199, Bit 9, Center 90 (11 ~ 170) 160
5983 01:00:05.464376 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5984 01:00:05.467770 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5985 01:00:05.470689 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5986 01:00:05.477823 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5987 01:00:05.481470 iDelay=199, Bit 14, Center 110 (27 ~ 194) 168
5988 01:00:05.484237 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5989 01:00:05.484815 ==
5990 01:00:05.487668 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 01:00:05.491554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 01:00:05.494529 ==
5993 01:00:05.495107 DQS Delay:
5994 01:00:05.495481 DQS0 = 0, DQS1 = 0
5995 01:00:05.498291 DQM Delay:
5996 01:00:05.498868 DQM0 = 108, DQM1 = 101
5997 01:00:05.501324 DQ Delay:
5998 01:00:05.501896 DQ0 =112, DQ1 =102, DQ2 =98, DQ3 =104
5999 01:00:05.508461 DQ4 =108, DQ5 =118, DQ6 =116, DQ7 =106
6000 01:00:05.511496 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =96
6001 01:00:05.514736 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =110
6002 01:00:05.515318
6003 01:00:05.515697
6004 01:00:05.520745 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
6005 01:00:05.524818 CH1 RK1: MR19=504, MR18=21FE
6006 01:00:05.531011 CH1_RK1: MR19=0x504, MR18=0x21FE, DQSOSC=411, MR23=63, INC=64, DEC=42
6007 01:00:05.534099 [RxdqsGatingPostProcess] freq 933
6008 01:00:05.537995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6009 01:00:05.541192 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 01:00:05.544403 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 01:00:05.547423 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 01:00:05.550686 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 01:00:05.554120 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 01:00:05.557767 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 01:00:05.560645 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 01:00:05.564093 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 01:00:05.567433 Pre-setting of DQS Precalculation
6018 01:00:05.570718 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6019 01:00:05.580956 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6020 01:00:05.587440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6021 01:00:05.587916
6022 01:00:05.588288
6023 01:00:05.590599 [Calibration Summary] 1866 Mbps
6024 01:00:05.591114 CH 0, Rank 0
6025 01:00:05.594347 SW Impedance : PASS
6026 01:00:05.594903 DUTY Scan : NO K
6027 01:00:05.597550 ZQ Calibration : PASS
6028 01:00:05.600897 Jitter Meter : NO K
6029 01:00:05.601432 CBT Training : PASS
6030 01:00:05.604058 Write leveling : PASS
6031 01:00:05.607300 RX DQS gating : PASS
6032 01:00:05.607840 RX DQ/DQS(RDDQC) : PASS
6033 01:00:05.610647 TX DQ/DQS : PASS
6034 01:00:05.614040 RX DATLAT : PASS
6035 01:00:05.614576 RX DQ/DQS(Engine): PASS
6036 01:00:05.617617 TX OE : NO K
6037 01:00:05.618185 All Pass.
6038 01:00:05.618539
6039 01:00:05.620846 CH 0, Rank 1
6040 01:00:05.621385 SW Impedance : PASS
6041 01:00:05.623899 DUTY Scan : NO K
6042 01:00:05.627243 ZQ Calibration : PASS
6043 01:00:05.627782 Jitter Meter : NO K
6044 01:00:05.630895 CBT Training : PASS
6045 01:00:05.633472 Write leveling : PASS
6046 01:00:05.633897 RX DQS gating : PASS
6047 01:00:05.637356 RX DQ/DQS(RDDQC) : PASS
6048 01:00:05.640374 TX DQ/DQS : PASS
6049 01:00:05.640911 RX DATLAT : PASS
6050 01:00:05.643761 RX DQ/DQS(Engine): PASS
6051 01:00:05.644298 TX OE : NO K
6052 01:00:05.646826 All Pass.
6053 01:00:05.647360
6054 01:00:05.647702 CH 1, Rank 0
6055 01:00:05.650095 SW Impedance : PASS
6056 01:00:05.650635 DUTY Scan : NO K
6057 01:00:05.653609 ZQ Calibration : PASS
6058 01:00:05.656782 Jitter Meter : NO K
6059 01:00:05.657216 CBT Training : PASS
6060 01:00:05.660081 Write leveling : PASS
6061 01:00:05.663834 RX DQS gating : PASS
6062 01:00:05.664371 RX DQ/DQS(RDDQC) : PASS
6063 01:00:05.666810 TX DQ/DQS : PASS
6064 01:00:05.670094 RX DATLAT : PASS
6065 01:00:05.670536 RX DQ/DQS(Engine): PASS
6066 01:00:05.673907 TX OE : NO K
6067 01:00:05.674486 All Pass.
6068 01:00:05.674838
6069 01:00:05.676857 CH 1, Rank 1
6070 01:00:05.677409 SW Impedance : PASS
6071 01:00:05.680206 DUTY Scan : NO K
6072 01:00:05.683383 ZQ Calibration : PASS
6073 01:00:05.683921 Jitter Meter : NO K
6074 01:00:05.686567 CBT Training : PASS
6075 01:00:05.690057 Write leveling : PASS
6076 01:00:05.690631 RX DQS gating : PASS
6077 01:00:05.693466 RX DQ/DQS(RDDQC) : PASS
6078 01:00:05.694053 TX DQ/DQS : PASS
6079 01:00:05.696673 RX DATLAT : PASS
6080 01:00:05.700363 RX DQ/DQS(Engine): PASS
6081 01:00:05.700908 TX OE : NO K
6082 01:00:05.703072 All Pass.
6083 01:00:05.703544
6084 01:00:05.703917 DramC Write-DBI off
6085 01:00:05.707304 PER_BANK_REFRESH: Hybrid Mode
6086 01:00:05.710547 TX_TRACKING: ON
6087 01:00:05.717033 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6088 01:00:05.720262 [FAST_K] Save calibration result to emmc
6089 01:00:05.723442 dramc_set_vcore_voltage set vcore to 650000
6090 01:00:05.726753 Read voltage for 400, 6
6091 01:00:05.727336 Vio18 = 0
6092 01:00:05.730171 Vcore = 650000
6093 01:00:05.730751 Vdram = 0
6094 01:00:05.731157 Vddq = 0
6095 01:00:05.733299 Vmddr = 0
6096 01:00:05.736793 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6097 01:00:05.743588 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6098 01:00:05.744173 MEM_TYPE=3, freq_sel=20
6099 01:00:05.746552 sv_algorithm_assistance_LP4_800
6100 01:00:05.752889 ============ PULL DRAM RESETB DOWN ============
6101 01:00:05.756619 ========== PULL DRAM RESETB DOWN end =========
6102 01:00:05.759847 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6103 01:00:05.763025 ===================================
6104 01:00:05.766489 LPDDR4 DRAM CONFIGURATION
6105 01:00:05.769847 ===================================
6106 01:00:05.773097 EX_ROW_EN[0] = 0x0
6107 01:00:05.773571 EX_ROW_EN[1] = 0x0
6108 01:00:05.776272 LP4Y_EN = 0x0
6109 01:00:05.776748 WORK_FSP = 0x0
6110 01:00:05.779443 WL = 0x2
6111 01:00:05.779960 RL = 0x2
6112 01:00:05.783001 BL = 0x2
6113 01:00:05.783586 RPST = 0x0
6114 01:00:05.786577 RD_PRE = 0x0
6115 01:00:05.787048 WR_PRE = 0x1
6116 01:00:05.789401 WR_PST = 0x0
6117 01:00:05.789892 DBI_WR = 0x0
6118 01:00:05.792901 DBI_RD = 0x0
6119 01:00:05.793481 OTF = 0x1
6120 01:00:05.796070 ===================================
6121 01:00:05.799749 ===================================
6122 01:00:05.803108 ANA top config
6123 01:00:05.806232 ===================================
6124 01:00:05.810011 DLL_ASYNC_EN = 0
6125 01:00:05.810595 ALL_SLAVE_EN = 1
6126 01:00:05.812887 NEW_RANK_MODE = 1
6127 01:00:05.816742 DLL_IDLE_MODE = 1
6128 01:00:05.820064 LP45_APHY_COMB_EN = 1
6129 01:00:05.820645 TX_ODT_DIS = 1
6130 01:00:05.822835 NEW_8X_MODE = 1
6131 01:00:05.826540 ===================================
6132 01:00:05.829624 ===================================
6133 01:00:05.833390 data_rate = 800
6134 01:00:05.836279 CKR = 1
6135 01:00:05.840061 DQ_P2S_RATIO = 4
6136 01:00:05.842742 ===================================
6137 01:00:05.843219 CA_P2S_RATIO = 4
6138 01:00:05.846186 DQ_CA_OPEN = 0
6139 01:00:05.849669 DQ_SEMI_OPEN = 1
6140 01:00:05.853031 CA_SEMI_OPEN = 1
6141 01:00:05.856587 CA_FULL_RATE = 0
6142 01:00:05.859717 DQ_CKDIV4_EN = 0
6143 01:00:05.860300 CA_CKDIV4_EN = 1
6144 01:00:05.863461 CA_PREDIV_EN = 0
6145 01:00:05.866034 PH8_DLY = 0
6146 01:00:05.869167 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6147 01:00:05.872846 DQ_AAMCK_DIV = 0
6148 01:00:05.876039 CA_AAMCK_DIV = 0
6149 01:00:05.876626 CA_ADMCK_DIV = 4
6150 01:00:05.879696 DQ_TRACK_CA_EN = 0
6151 01:00:05.883245 CA_PICK = 800
6152 01:00:05.886116 CA_MCKIO = 400
6153 01:00:05.889325 MCKIO_SEMI = 400
6154 01:00:05.893027 PLL_FREQ = 3016
6155 01:00:05.895896 DQ_UI_PI_RATIO = 32
6156 01:00:05.899530 CA_UI_PI_RATIO = 32
6157 01:00:05.902624 ===================================
6158 01:00:05.906112 ===================================
6159 01:00:05.906687 memory_type:LPDDR4
6160 01:00:05.909275 GP_NUM : 10
6161 01:00:05.912927 SRAM_EN : 1
6162 01:00:05.913511 MD32_EN : 0
6163 01:00:05.916030 ===================================
6164 01:00:05.919178 [ANA_INIT] >>>>>>>>>>>>>>
6165 01:00:05.922533 <<<<<< [CONFIGURE PHASE]: ANA_TX
6166 01:00:05.925822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6167 01:00:05.929378 ===================================
6168 01:00:05.932560 data_rate = 800,PCW = 0X7400
6169 01:00:05.935640 ===================================
6170 01:00:05.939245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6171 01:00:05.942550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 01:00:05.955349 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 01:00:05.959055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6174 01:00:05.962394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6175 01:00:05.965817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6176 01:00:05.968833 [ANA_INIT] flow start
6177 01:00:05.969435 [ANA_INIT] PLL >>>>>>>>
6178 01:00:05.971972 [ANA_INIT] PLL <<<<<<<<
6179 01:00:05.975554 [ANA_INIT] MIDPI >>>>>>>>
6180 01:00:05.979052 [ANA_INIT] MIDPI <<<<<<<<
6181 01:00:05.979649 [ANA_INIT] DLL >>>>>>>>
6182 01:00:05.982044 [ANA_INIT] flow end
6183 01:00:05.985353 ============ LP4 DIFF to SE enter ============
6184 01:00:05.989058 ============ LP4 DIFF to SE exit ============
6185 01:00:05.992300 [ANA_INIT] <<<<<<<<<<<<<
6186 01:00:05.995494 [Flow] Enable top DCM control >>>>>
6187 01:00:05.999026 [Flow] Enable top DCM control <<<<<
6188 01:00:06.002051 Enable DLL master slave shuffle
6189 01:00:06.008848 ==============================================================
6190 01:00:06.009433 Gating Mode config
6191 01:00:06.015811 ==============================================================
6192 01:00:06.016411 Config description:
6193 01:00:06.025298 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6194 01:00:06.031809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6195 01:00:06.038768 SELPH_MODE 0: By rank 1: By Phase
6196 01:00:06.041856 ==============================================================
6197 01:00:06.045496 GAT_TRACK_EN = 0
6198 01:00:06.048198 RX_GATING_MODE = 2
6199 01:00:06.051934 RX_GATING_TRACK_MODE = 2
6200 01:00:06.055320 SELPH_MODE = 1
6201 01:00:06.058248 PICG_EARLY_EN = 1
6202 01:00:06.062082 VALID_LAT_VALUE = 1
6203 01:00:06.065167 ==============================================================
6204 01:00:06.071837 Enter into Gating configuration >>>>
6205 01:00:06.072430 Exit from Gating configuration <<<<
6206 01:00:06.075333 Enter into DVFS_PRE_config >>>>>
6207 01:00:06.088537 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6208 01:00:06.091434 Exit from DVFS_PRE_config <<<<<
6209 01:00:06.094799 Enter into PICG configuration >>>>
6210 01:00:06.097908 Exit from PICG configuration <<<<
6211 01:00:06.098441 [RX_INPUT] configuration >>>>>
6212 01:00:06.101529 [RX_INPUT] configuration <<<<<
6213 01:00:06.108115 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6214 01:00:06.111689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6215 01:00:06.118067 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 01:00:06.124772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 01:00:06.130979 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 01:00:06.138029 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 01:00:06.141446 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6220 01:00:06.144531 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6221 01:00:06.151225 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6222 01:00:06.154518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6223 01:00:06.157551 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6224 01:00:06.164488 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 01:00:06.167582 ===================================
6226 01:00:06.168166 LPDDR4 DRAM CONFIGURATION
6227 01:00:06.170981 ===================================
6228 01:00:06.174447 EX_ROW_EN[0] = 0x0
6229 01:00:06.175035 EX_ROW_EN[1] = 0x0
6230 01:00:06.177973 LP4Y_EN = 0x0
6231 01:00:06.178562 WORK_FSP = 0x0
6232 01:00:06.180729 WL = 0x2
6233 01:00:06.181228 RL = 0x2
6234 01:00:06.184634 BL = 0x2
6235 01:00:06.185215 RPST = 0x0
6236 01:00:06.187194 RD_PRE = 0x0
6237 01:00:06.190793 WR_PRE = 0x1
6238 01:00:06.191265 WR_PST = 0x0
6239 01:00:06.194108 DBI_WR = 0x0
6240 01:00:06.194582 DBI_RD = 0x0
6241 01:00:06.197134 OTF = 0x1
6242 01:00:06.200483 ===================================
6243 01:00:06.204106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6244 01:00:06.207641 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6245 01:00:06.210668 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6246 01:00:06.214516 ===================================
6247 01:00:06.217344 LPDDR4 DRAM CONFIGURATION
6248 01:00:06.220418 ===================================
6249 01:00:06.223594 EX_ROW_EN[0] = 0x10
6250 01:00:06.224214 EX_ROW_EN[1] = 0x0
6251 01:00:06.227057 LP4Y_EN = 0x0
6252 01:00:06.227643 WORK_FSP = 0x0
6253 01:00:06.230149 WL = 0x2
6254 01:00:06.230665 RL = 0x2
6255 01:00:06.233901 BL = 0x2
6256 01:00:06.234400 RPST = 0x0
6257 01:00:06.237265 RD_PRE = 0x0
6258 01:00:06.240434 WR_PRE = 0x1
6259 01:00:06.241006 WR_PST = 0x0
6260 01:00:06.243648 DBI_WR = 0x0
6261 01:00:06.244227 DBI_RD = 0x0
6262 01:00:06.247010 OTF = 0x1
6263 01:00:06.250332 ===================================
6264 01:00:06.253644 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6265 01:00:06.259022 nWR fixed to 30
6266 01:00:06.262055 [ModeRegInit_LP4] CH0 RK0
6267 01:00:06.262539 [ModeRegInit_LP4] CH0 RK1
6268 01:00:06.266267 [ModeRegInit_LP4] CH1 RK0
6269 01:00:06.268966 [ModeRegInit_LP4] CH1 RK1
6270 01:00:06.269549 match AC timing 19
6271 01:00:06.275758 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6272 01:00:06.279309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6273 01:00:06.282554 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6274 01:00:06.288927 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6275 01:00:06.292383 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6276 01:00:06.292980 ==
6277 01:00:06.295469 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 01:00:06.298505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 01:00:06.298986 ==
6280 01:00:06.305532 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 01:00:06.312079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6282 01:00:06.315847 [CA 0] Center 36 (8~64) winsize 57
6283 01:00:06.318829 [CA 1] Center 36 (8~64) winsize 57
6284 01:00:06.321867 [CA 2] Center 36 (8~64) winsize 57
6285 01:00:06.325363 [CA 3] Center 36 (8~64) winsize 57
6286 01:00:06.325983 [CA 4] Center 36 (8~64) winsize 57
6287 01:00:06.328864 [CA 5] Center 36 (8~64) winsize 57
6288 01:00:06.329548
6289 01:00:06.335164 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6290 01:00:06.335741
6291 01:00:06.338836 [CATrainingPosCal] consider 1 rank data
6292 01:00:06.342064 u2DelayCellTimex100 = 270/100 ps
6293 01:00:06.345618 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 01:00:06.348583 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 01:00:06.352447 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 01:00:06.355675 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 01:00:06.358828 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 01:00:06.361815 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 01:00:06.362346
6300 01:00:06.365634 CA PerBit enable=1, Macro0, CA PI delay=36
6301 01:00:06.366261
6302 01:00:06.368556 [CBTSetCACLKResult] CA Dly = 36
6303 01:00:06.371680 CS Dly: 1 (0~32)
6304 01:00:06.372155 ==
6305 01:00:06.375276 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 01:00:06.378607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 01:00:06.379191 ==
6308 01:00:06.385247 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6309 01:00:06.388543 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6310 01:00:06.391883 [CA 0] Center 36 (8~64) winsize 57
6311 01:00:06.394875 [CA 1] Center 36 (8~64) winsize 57
6312 01:00:06.398374 [CA 2] Center 36 (8~64) winsize 57
6313 01:00:06.401398 [CA 3] Center 36 (8~64) winsize 57
6314 01:00:06.404977 [CA 4] Center 36 (8~64) winsize 57
6315 01:00:06.408452 [CA 5] Center 36 (8~64) winsize 57
6316 01:00:06.409030
6317 01:00:06.411494 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6318 01:00:06.411969
6319 01:00:06.415000 [CATrainingPosCal] consider 2 rank data
6320 01:00:06.418114 u2DelayCellTimex100 = 270/100 ps
6321 01:00:06.421668 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 01:00:06.424835 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 01:00:06.431310 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 01:00:06.434875 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 01:00:06.438119 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 01:00:06.441527 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 01:00:06.442148
6328 01:00:06.444600 CA PerBit enable=1, Macro0, CA PI delay=36
6329 01:00:06.445183
6330 01:00:06.448602 [CBTSetCACLKResult] CA Dly = 36
6331 01:00:06.449189 CS Dly: 1 (0~32)
6332 01:00:06.449681
6333 01:00:06.451249 ----->DramcWriteLeveling(PI) begin...
6334 01:00:06.454303 ==
6335 01:00:06.458138 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 01:00:06.461268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 01:00:06.461762 ==
6338 01:00:06.464774 Write leveling (Byte 0): 40 => 8
6339 01:00:06.467926 Write leveling (Byte 1): 32 => 0
6340 01:00:06.471512 DramcWriteLeveling(PI) end<-----
6341 01:00:06.472007
6342 01:00:06.472408 ==
6343 01:00:06.474781 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 01:00:06.478324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 01:00:06.478901 ==
6346 01:00:06.481089 [Gating] SW mode calibration
6347 01:00:06.487708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6348 01:00:06.494555 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6349 01:00:06.497775 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 01:00:06.501321 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 01:00:06.507560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 01:00:06.511011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 01:00:06.514088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 01:00:06.521025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 01:00:06.524514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 01:00:06.527863 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 01:00:06.534107 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 01:00:06.534717 Total UI for P1: 0, mck2ui 16
6359 01:00:06.536976 best dqsien dly found for B0: ( 0, 14, 24)
6360 01:00:06.540522 Total UI for P1: 0, mck2ui 16
6361 01:00:06.543483 best dqsien dly found for B1: ( 0, 14, 24)
6362 01:00:06.550416 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6363 01:00:06.553621 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6364 01:00:06.553788
6365 01:00:06.556751 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 01:00:06.560214 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 01:00:06.563457 [Gating] SW calibration Done
6368 01:00:06.563635 ==
6369 01:00:06.566771 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 01:00:06.569977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 01:00:06.570130 ==
6372 01:00:06.573188 RX Vref Scan: 0
6373 01:00:06.573324
6374 01:00:06.573417 RX Vref 0 -> 0, step: 1
6375 01:00:06.573504
6376 01:00:06.576591 RX Delay -410 -> 252, step: 16
6377 01:00:06.579924 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6378 01:00:06.586916 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6379 01:00:06.590347 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6380 01:00:06.593856 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6381 01:00:06.597019 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6382 01:00:06.603495 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6383 01:00:06.606856 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6384 01:00:06.610118 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6385 01:00:06.613735 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6386 01:00:06.620376 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6387 01:00:06.623960 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6388 01:00:06.627104 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6389 01:00:06.633310 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6390 01:00:06.636526 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6391 01:00:06.640232 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6392 01:00:06.643166 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6393 01:00:06.643632 ==
6394 01:00:06.646723 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 01:00:06.653236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 01:00:06.653784 ==
6397 01:00:06.654250 DQS Delay:
6398 01:00:06.656875 DQS0 = 27, DQS1 = 43
6399 01:00:06.657434 DQM Delay:
6400 01:00:06.660084 DQM0 = 12, DQM1 = 13
6401 01:00:06.660685 DQ Delay:
6402 01:00:06.663354 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6403 01:00:06.666556 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6404 01:00:06.670281 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6405 01:00:06.673143 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6406 01:00:06.673703
6407 01:00:06.674116
6408 01:00:06.674462 ==
6409 01:00:06.676524 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 01:00:06.679873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 01:00:06.680439 ==
6412 01:00:06.680808
6413 01:00:06.681145
6414 01:00:06.682882 TX Vref Scan disable
6415 01:00:06.683345 == TX Byte 0 ==
6416 01:00:06.689642 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 01:00:06.693108 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 01:00:06.693663 == TX Byte 1 ==
6419 01:00:06.696610 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6420 01:00:06.702809 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6421 01:00:06.703368 ==
6422 01:00:06.706299 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 01:00:06.710039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 01:00:06.710611 ==
6425 01:00:06.710983
6426 01:00:06.711321
6427 01:00:06.713132 TX Vref Scan disable
6428 01:00:06.713680 == TX Byte 0 ==
6429 01:00:06.719595 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 01:00:06.722769 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 01:00:06.723237 == TX Byte 1 ==
6432 01:00:06.729656 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6433 01:00:06.732738 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6434 01:00:06.733205
6435 01:00:06.733568 [DATLAT]
6436 01:00:06.735988 Freq=400, CH0 RK0
6437 01:00:06.736455
6438 01:00:06.736816 DATLAT Default: 0xf
6439 01:00:06.739130 0, 0xFFFF, sum = 0
6440 01:00:06.739602 1, 0xFFFF, sum = 0
6441 01:00:06.742884 2, 0xFFFF, sum = 0
6442 01:00:06.743456 3, 0xFFFF, sum = 0
6443 01:00:06.746712 4, 0xFFFF, sum = 0
6444 01:00:06.747277 5, 0xFFFF, sum = 0
6445 01:00:06.749398 6, 0xFFFF, sum = 0
6446 01:00:06.749914 7, 0xFFFF, sum = 0
6447 01:00:06.753193 8, 0xFFFF, sum = 0
6448 01:00:06.753757 9, 0xFFFF, sum = 0
6449 01:00:06.756181 10, 0xFFFF, sum = 0
6450 01:00:06.759139 11, 0xFFFF, sum = 0
6451 01:00:06.759610 12, 0xFFFF, sum = 0
6452 01:00:06.762844 13, 0x0, sum = 1
6453 01:00:06.763313 14, 0x0, sum = 2
6454 01:00:06.765804 15, 0x0, sum = 3
6455 01:00:06.766351 16, 0x0, sum = 4
6456 01:00:06.766729 best_step = 14
6457 01:00:06.767067
6458 01:00:06.769524 ==
6459 01:00:06.772644 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 01:00:06.775944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 01:00:06.776413 ==
6462 01:00:06.776780 RX Vref Scan: 1
6463 01:00:06.777119
6464 01:00:06.778991 RX Vref 0 -> 0, step: 1
6465 01:00:06.779452
6466 01:00:06.782426 RX Delay -327 -> 252, step: 8
6467 01:00:06.783052
6468 01:00:06.785618 Set Vref, RX VrefLevel [Byte0]: 60
6469 01:00:06.789067 [Byte1]: 50
6470 01:00:06.793505
6471 01:00:06.794133 Final RX Vref Byte 0 = 60 to rank0
6472 01:00:06.796035 Final RX Vref Byte 1 = 50 to rank0
6473 01:00:06.799097 Final RX Vref Byte 0 = 60 to rank1
6474 01:00:06.802567 Final RX Vref Byte 1 = 50 to rank1==
6475 01:00:06.806129 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 01:00:06.812836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 01:00:06.813368 ==
6478 01:00:06.813712 DQS Delay:
6479 01:00:06.816206 DQS0 = 28, DQS1 = 48
6480 01:00:06.816635 DQM Delay:
6481 01:00:06.816977 DQM0 = 12, DQM1 = 15
6482 01:00:06.819222 DQ Delay:
6483 01:00:06.822613 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6484 01:00:06.823046 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6485 01:00:06.826109 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6486 01:00:06.829155 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6487 01:00:06.832525
6488 01:00:06.832953
6489 01:00:06.839345 [DQSOSCAuto] RK0, (LSB)MR18= 0xa79e, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6490 01:00:06.843019 CH0 RK0: MR19=C0C, MR18=A79E
6491 01:00:06.849631 CH0_RK0: MR19=0xC0C, MR18=0xA79E, DQSOSC=389, MR23=63, INC=390, DEC=260
6492 01:00:06.850212 ==
6493 01:00:06.852609 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 01:00:06.855864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 01:00:06.856300 ==
6496 01:00:06.858963 [Gating] SW mode calibration
6497 01:00:06.865775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 01:00:06.872613 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6499 01:00:06.875567 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 01:00:06.879140 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 01:00:06.885593 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 01:00:06.889042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 01:00:06.892676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 01:00:06.898805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 01:00:06.902751 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 01:00:06.905850 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 01:00:06.909114 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 01:00:06.912274 Total UI for P1: 0, mck2ui 16
6509 01:00:06.915704 best dqsien dly found for B0: ( 0, 14, 24)
6510 01:00:06.919110 Total UI for P1: 0, mck2ui 16
6511 01:00:06.922585 best dqsien dly found for B1: ( 0, 14, 24)
6512 01:00:06.925594 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6513 01:00:06.932083 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6514 01:00:06.932658
6515 01:00:06.935147 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 01:00:06.938792 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 01:00:06.942565 [Gating] SW calibration Done
6518 01:00:06.943143 ==
6519 01:00:06.945083 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 01:00:06.948896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 01:00:06.949473 ==
6522 01:00:06.952029 RX Vref Scan: 0
6523 01:00:06.952497
6524 01:00:06.952866 RX Vref 0 -> 0, step: 1
6525 01:00:06.953210
6526 01:00:06.955153 RX Delay -410 -> 252, step: 16
6527 01:00:06.958543 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6528 01:00:06.965152 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6529 01:00:06.968610 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6530 01:00:06.971961 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6531 01:00:06.975248 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6532 01:00:06.981803 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6533 01:00:06.985533 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6534 01:00:06.988343 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6535 01:00:06.992237 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6536 01:00:06.998822 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6537 01:00:07.001889 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6538 01:00:07.005420 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6539 01:00:07.008970 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6540 01:00:07.015567 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6541 01:00:07.018714 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6542 01:00:07.022194 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6543 01:00:07.022769 ==
6544 01:00:07.025282 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 01:00:07.031686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 01:00:07.032194 ==
6547 01:00:07.032586 DQS Delay:
6548 01:00:07.032938 DQS0 = 27, DQS1 = 35
6549 01:00:07.035134 DQM Delay:
6550 01:00:07.035606 DQM0 = 11, DQM1 = 8
6551 01:00:07.038847 DQ Delay:
6552 01:00:07.039421 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6553 01:00:07.041657 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6554 01:00:07.045144 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6555 01:00:07.048792 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6556 01:00:07.049380
6557 01:00:07.049761
6558 01:00:07.050152 ==
6559 01:00:07.051564 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 01:00:07.058667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 01:00:07.059259 ==
6562 01:00:07.059638
6563 01:00:07.059985
6564 01:00:07.060317 TX Vref Scan disable
6565 01:00:07.061629 == TX Byte 0 ==
6566 01:00:07.064859 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6567 01:00:07.068605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6568 01:00:07.072000 == TX Byte 1 ==
6569 01:00:07.075068 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6570 01:00:07.078702 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6571 01:00:07.079176 ==
6572 01:00:07.081631 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 01:00:07.088134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 01:00:07.088694 ==
6575 01:00:07.089071
6576 01:00:07.089418
6577 01:00:07.089746 TX Vref Scan disable
6578 01:00:07.091687 == TX Byte 0 ==
6579 01:00:07.095516 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6580 01:00:07.098486 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6581 01:00:07.102079 == TX Byte 1 ==
6582 01:00:07.105489 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6583 01:00:07.108799 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6584 01:00:07.109369
6585 01:00:07.111986 [DATLAT]
6586 01:00:07.112552 Freq=400, CH0 RK1
6587 01:00:07.112931
6588 01:00:07.114841 DATLAT Default: 0xe
6589 01:00:07.115412 0, 0xFFFF, sum = 0
6590 01:00:07.118251 1, 0xFFFF, sum = 0
6591 01:00:07.118828 2, 0xFFFF, sum = 0
6592 01:00:07.121590 3, 0xFFFF, sum = 0
6593 01:00:07.122199 4, 0xFFFF, sum = 0
6594 01:00:07.124975 5, 0xFFFF, sum = 0
6595 01:00:07.125550 6, 0xFFFF, sum = 0
6596 01:00:07.128516 7, 0xFFFF, sum = 0
6597 01:00:07.131112 8, 0xFFFF, sum = 0
6598 01:00:07.131591 9, 0xFFFF, sum = 0
6599 01:00:07.134567 10, 0xFFFF, sum = 0
6600 01:00:07.135046 11, 0xFFFF, sum = 0
6601 01:00:07.138099 12, 0xFFFF, sum = 0
6602 01:00:07.138679 13, 0x0, sum = 1
6603 01:00:07.141414 14, 0x0, sum = 2
6604 01:00:07.142012 15, 0x0, sum = 3
6605 01:00:07.144784 16, 0x0, sum = 4
6606 01:00:07.145368 best_step = 14
6607 01:00:07.145747
6608 01:00:07.146127 ==
6609 01:00:07.147890 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 01:00:07.151135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 01:00:07.151612 ==
6612 01:00:07.154594 RX Vref Scan: 0
6613 01:00:07.155160
6614 01:00:07.157999 RX Vref 0 -> 0, step: 1
6615 01:00:07.158572
6616 01:00:07.158946 RX Delay -311 -> 252, step: 8
6617 01:00:07.166389 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6618 01:00:07.169798 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6619 01:00:07.173386 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6620 01:00:07.179513 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6621 01:00:07.183130 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6622 01:00:07.186380 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6623 01:00:07.189695 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6624 01:00:07.192820 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6625 01:00:07.199571 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6626 01:00:07.203562 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6627 01:00:07.206609 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6628 01:00:07.210269 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6629 01:00:07.216863 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6630 01:00:07.220019 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6631 01:00:07.223233 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6632 01:00:07.230065 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6633 01:00:07.230646 ==
6634 01:00:07.232796 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 01:00:07.236077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 01:00:07.236554 ==
6637 01:00:07.236935 DQS Delay:
6638 01:00:07.239880 DQS0 = 28, DQS1 = 44
6639 01:00:07.240464 DQM Delay:
6640 01:00:07.243237 DQM0 = 9, DQM1 = 15
6641 01:00:07.243822 DQ Delay:
6642 01:00:07.246739 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6643 01:00:07.249665 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6644 01:00:07.253031 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6645 01:00:07.256063 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6646 01:00:07.256694
6647 01:00:07.257196
6648 01:00:07.262887 [DQSOSCAuto] RK1, (LSB)MR18= 0xb469, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6649 01:00:07.266001 CH0 RK1: MR19=C0C, MR18=B469
6650 01:00:07.273023 CH0_RK1: MR19=0xC0C, MR18=0xB469, DQSOSC=387, MR23=63, INC=394, DEC=262
6651 01:00:07.276592 [RxdqsGatingPostProcess] freq 400
6652 01:00:07.279702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6653 01:00:07.282756 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 01:00:07.286167 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 01:00:07.289397 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 01:00:07.293055 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 01:00:07.296993 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 01:00:07.299831 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 01:00:07.303051 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 01:00:07.306457 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 01:00:07.310081 Pre-setting of DQS Precalculation
6662 01:00:07.312954 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6663 01:00:07.316608 ==
6664 01:00:07.317190 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 01:00:07.322838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 01:00:07.323504 ==
6667 01:00:07.326288 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 01:00:07.332914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6669 01:00:07.336231 [CA 0] Center 36 (8~64) winsize 57
6670 01:00:07.339759 [CA 1] Center 36 (8~64) winsize 57
6671 01:00:07.343129 [CA 2] Center 36 (8~64) winsize 57
6672 01:00:07.346447 [CA 3] Center 36 (8~64) winsize 57
6673 01:00:07.349681 [CA 4] Center 36 (8~64) winsize 57
6674 01:00:07.352947 [CA 5] Center 36 (8~64) winsize 57
6675 01:00:07.353533
6676 01:00:07.356499 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6677 01:00:07.357085
6678 01:00:07.359349 [CATrainingPosCal] consider 1 rank data
6679 01:00:07.362688 u2DelayCellTimex100 = 270/100 ps
6680 01:00:07.366044 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 01:00:07.369433 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 01:00:07.372714 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 01:00:07.375832 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 01:00:07.379323 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 01:00:07.385725 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 01:00:07.386225
6687 01:00:07.389418 CA PerBit enable=1, Macro0, CA PI delay=36
6688 01:00:07.390031
6689 01:00:07.392584 [CBTSetCACLKResult] CA Dly = 36
6690 01:00:07.393060 CS Dly: 1 (0~32)
6691 01:00:07.393439 ==
6692 01:00:07.396077 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 01:00:07.399290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 01:00:07.402633 ==
6695 01:00:07.406143 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6696 01:00:07.412863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6697 01:00:07.415831 [CA 0] Center 36 (8~64) winsize 57
6698 01:00:07.419556 [CA 1] Center 36 (8~64) winsize 57
6699 01:00:07.422799 [CA 2] Center 36 (8~64) winsize 57
6700 01:00:07.425725 [CA 3] Center 36 (8~64) winsize 57
6701 01:00:07.428947 [CA 4] Center 36 (8~64) winsize 57
6702 01:00:07.432020 [CA 5] Center 36 (8~64) winsize 57
6703 01:00:07.432512
6704 01:00:07.435511 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6705 01:00:07.436022
6706 01:00:07.439337 [CATrainingPosCal] consider 2 rank data
6707 01:00:07.442402 u2DelayCellTimex100 = 270/100 ps
6708 01:00:07.445736 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 01:00:07.449006 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 01:00:07.452338 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 01:00:07.455801 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 01:00:07.458851 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 01:00:07.462438 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 01:00:07.463024
6715 01:00:07.468772 CA PerBit enable=1, Macro0, CA PI delay=36
6716 01:00:07.469358
6717 01:00:07.469776 [CBTSetCACLKResult] CA Dly = 36
6718 01:00:07.472196 CS Dly: 1 (0~32)
6719 01:00:07.472687
6720 01:00:07.475640 ----->DramcWriteLeveling(PI) begin...
6721 01:00:07.476263 ==
6722 01:00:07.478668 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 01:00:07.482040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 01:00:07.482568 ==
6725 01:00:07.485364 Write leveling (Byte 0): 40 => 8
6726 01:00:07.488490 Write leveling (Byte 1): 32 => 0
6727 01:00:07.491949 DramcWriteLeveling(PI) end<-----
6728 01:00:07.492426
6729 01:00:07.492799 ==
6730 01:00:07.495347 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 01:00:07.498577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 01:00:07.499206 ==
6733 01:00:07.502045 [Gating] SW mode calibration
6734 01:00:07.508897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6735 01:00:07.515293 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6736 01:00:07.518613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 01:00:07.525359 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 01:00:07.528661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 01:00:07.531867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 01:00:07.538637 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 01:00:07.542104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 01:00:07.544932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 01:00:07.551927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 01:00:07.555603 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 01:00:07.558548 Total UI for P1: 0, mck2ui 16
6746 01:00:07.561777 best dqsien dly found for B0: ( 0, 14, 24)
6747 01:00:07.565186 Total UI for P1: 0, mck2ui 16
6748 01:00:07.568609 best dqsien dly found for B1: ( 0, 14, 24)
6749 01:00:07.571768 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6750 01:00:07.574841 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6751 01:00:07.575318
6752 01:00:07.578254 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 01:00:07.581826 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 01:00:07.584794 [Gating] SW calibration Done
6755 01:00:07.585359 ==
6756 01:00:07.588262 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 01:00:07.591876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 01:00:07.592465 ==
6759 01:00:07.595161 RX Vref Scan: 0
6760 01:00:07.595742
6761 01:00:07.598171 RX Vref 0 -> 0, step: 1
6762 01:00:07.598747
6763 01:00:07.599128 RX Delay -410 -> 252, step: 16
6764 01:00:07.606018 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6765 01:00:07.608663 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6766 01:00:07.612029 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6767 01:00:07.615255 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6768 01:00:07.622003 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6769 01:00:07.625079 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6770 01:00:07.628467 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6771 01:00:07.631811 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6772 01:00:07.638707 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6773 01:00:07.641852 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6774 01:00:07.645245 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6775 01:00:07.648905 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6776 01:00:07.655586 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6777 01:00:07.658539 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6778 01:00:07.662185 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6779 01:00:07.668523 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6780 01:00:07.669108 ==
6781 01:00:07.671918 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 01:00:07.675299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 01:00:07.675779 ==
6784 01:00:07.676156 DQS Delay:
6785 01:00:07.678261 DQS0 = 27, DQS1 = 43
6786 01:00:07.678737 DQM Delay:
6787 01:00:07.681825 DQM0 = 4, DQM1 = 17
6788 01:00:07.682451 DQ Delay:
6789 01:00:07.684938 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6790 01:00:07.688580 DQ4 =0, DQ5 =8, DQ6 =16, DQ7 =0
6791 01:00:07.691552 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6792 01:00:07.695252 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6793 01:00:07.695874
6794 01:00:07.696276
6795 01:00:07.696627 ==
6796 01:00:07.698013 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 01:00:07.702055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 01:00:07.702633 ==
6799 01:00:07.703015
6800 01:00:07.703362
6801 01:00:07.704974 TX Vref Scan disable
6802 01:00:07.705446 == TX Byte 0 ==
6803 01:00:07.711245 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 01:00:07.714759 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 01:00:07.715234 == TX Byte 1 ==
6806 01:00:07.721774 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6807 01:00:07.724935 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6808 01:00:07.725426 ==
6809 01:00:07.728409 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 01:00:07.731428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 01:00:07.732017 ==
6812 01:00:07.732399
6813 01:00:07.732750
6814 01:00:07.734480 TX Vref Scan disable
6815 01:00:07.734953 == TX Byte 0 ==
6816 01:00:07.742115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 01:00:07.745252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 01:00:07.745838 == TX Byte 1 ==
6819 01:00:07.751490 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6820 01:00:07.755158 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6821 01:00:07.755744
6822 01:00:07.756123 [DATLAT]
6823 01:00:07.758115 Freq=400, CH1 RK0
6824 01:00:07.758698
6825 01:00:07.759082 DATLAT Default: 0xf
6826 01:00:07.761820 0, 0xFFFF, sum = 0
6827 01:00:07.762444 1, 0xFFFF, sum = 0
6828 01:00:07.765061 2, 0xFFFF, sum = 0
6829 01:00:07.765648 3, 0xFFFF, sum = 0
6830 01:00:07.768181 4, 0xFFFF, sum = 0
6831 01:00:07.768662 5, 0xFFFF, sum = 0
6832 01:00:07.771700 6, 0xFFFF, sum = 0
6833 01:00:07.774711 7, 0xFFFF, sum = 0
6834 01:00:07.775208 8, 0xFFFF, sum = 0
6835 01:00:07.777853 9, 0xFFFF, sum = 0
6836 01:00:07.778368 10, 0xFFFF, sum = 0
6837 01:00:07.781361 11, 0xFFFF, sum = 0
6838 01:00:07.781976 12, 0xFFFF, sum = 0
6839 01:00:07.784825 13, 0x0, sum = 1
6840 01:00:07.785407 14, 0x0, sum = 2
6841 01:00:07.788020 15, 0x0, sum = 3
6842 01:00:07.788602 16, 0x0, sum = 4
6843 01:00:07.788987 best_step = 14
6844 01:00:07.791402
6845 01:00:07.792110 ==
6846 01:00:07.794645 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 01:00:07.798117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 01:00:07.798681 ==
6849 01:00:07.799060 RX Vref Scan: 1
6850 01:00:07.799411
6851 01:00:07.801085 RX Vref 0 -> 0, step: 1
6852 01:00:07.801553
6853 01:00:07.804584 RX Delay -327 -> 252, step: 8
6854 01:00:07.805057
6855 01:00:07.807664 Set Vref, RX VrefLevel [Byte0]: 51
6856 01:00:07.811436 [Byte1]: 52
6857 01:00:07.815175
6858 01:00:07.815793 Final RX Vref Byte 0 = 51 to rank0
6859 01:00:07.818373 Final RX Vref Byte 1 = 52 to rank0
6860 01:00:07.821233 Final RX Vref Byte 0 = 51 to rank1
6861 01:00:07.825204 Final RX Vref Byte 1 = 52 to rank1==
6862 01:00:07.827762 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 01:00:07.834936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 01:00:07.835437 ==
6865 01:00:07.835814 DQS Delay:
6866 01:00:07.838155 DQS0 = 32, DQS1 = 40
6867 01:00:07.838626 DQM Delay:
6868 01:00:07.839002 DQM0 = 11, DQM1 = 13
6869 01:00:07.841594 DQ Delay:
6870 01:00:07.844924 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6871 01:00:07.845494 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6872 01:00:07.848350 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6873 01:00:07.852029 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6874 01:00:07.852602
6875 01:00:07.852976
6876 01:00:07.861496 [DQSOSCAuto] RK0, (LSB)MR18= 0x97d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6877 01:00:07.865174 CH1 RK0: MR19=C0C, MR18=97D1
6878 01:00:07.871622 CH1_RK0: MR19=0xC0C, MR18=0x97D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6879 01:00:07.872200 ==
6880 01:00:07.874439 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 01:00:07.878435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 01:00:07.879015 ==
6883 01:00:07.881754 [Gating] SW mode calibration
6884 01:00:07.888004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6885 01:00:07.891528 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6886 01:00:07.898117 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 01:00:07.901858 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 01:00:07.904970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 01:00:07.911351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 01:00:07.914729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 01:00:07.918058 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 01:00:07.924681 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 01:00:07.927751 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 01:00:07.931538 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 01:00:07.934411 Total UI for P1: 0, mck2ui 16
6896 01:00:07.937851 best dqsien dly found for B0: ( 0, 14, 24)
6897 01:00:07.940988 Total UI for P1: 0, mck2ui 16
6898 01:00:07.944538 best dqsien dly found for B1: ( 0, 14, 24)
6899 01:00:07.947975 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6900 01:00:07.951349 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6901 01:00:07.951924
6902 01:00:07.957997 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 01:00:07.961302 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 01:00:07.964480 [Gating] SW calibration Done
6905 01:00:07.965047 ==
6906 01:00:07.967587 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 01:00:07.971496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 01:00:07.971974 ==
6909 01:00:07.972350 RX Vref Scan: 0
6910 01:00:07.972701
6911 01:00:07.974512 RX Vref 0 -> 0, step: 1
6912 01:00:07.974989
6913 01:00:07.977771 RX Delay -410 -> 252, step: 16
6914 01:00:07.981335 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6915 01:00:07.987762 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6916 01:00:07.990832 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6917 01:00:07.994515 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6918 01:00:07.998145 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6919 01:00:08.004056 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6920 01:00:08.007732 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6921 01:00:08.010785 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6922 01:00:08.014076 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6923 01:00:08.021005 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6924 01:00:08.024570 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6925 01:00:08.027688 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6926 01:00:08.030844 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6927 01:00:08.037402 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6928 01:00:08.040901 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6929 01:00:08.044550 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6930 01:00:08.045026 ==
6931 01:00:08.048075 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 01:00:08.051324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 01:00:08.054331 ==
6934 01:00:08.054807 DQS Delay:
6935 01:00:08.055205 DQS0 = 27, DQS1 = 43
6936 01:00:08.057610 DQM Delay:
6937 01:00:08.058141 DQM0 = 11, DQM1 = 21
6938 01:00:08.060901 DQ Delay:
6939 01:00:08.061470 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6940 01:00:08.063913 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6941 01:00:08.067647 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =24
6942 01:00:08.071265 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6943 01:00:08.071844
6944 01:00:08.072225
6945 01:00:08.072598 ==
6946 01:00:08.073830 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 01:00:08.080881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 01:00:08.081458 ==
6949 01:00:08.081836
6950 01:00:08.082283
6951 01:00:08.083957 TX Vref Scan disable
6952 01:00:08.084432 == TX Byte 0 ==
6953 01:00:08.087552 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6954 01:00:08.090566 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6955 01:00:08.093748 == TX Byte 1 ==
6956 01:00:08.096968 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6957 01:00:08.100582 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6958 01:00:08.104301 ==
6959 01:00:08.104776 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 01:00:08.110335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 01:00:08.110819 ==
6962 01:00:08.111203
6963 01:00:08.111564
6964 01:00:08.113736 TX Vref Scan disable
6965 01:00:08.114268 == TX Byte 0 ==
6966 01:00:08.117609 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6967 01:00:08.124646 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6968 01:00:08.125224 == TX Byte 1 ==
6969 01:00:08.127067 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6970 01:00:08.130371 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6971 01:00:08.134064
6972 01:00:08.134530 [DATLAT]
6973 01:00:08.134905 Freq=400, CH1 RK1
6974 01:00:08.135255
6975 01:00:08.137147 DATLAT Default: 0xe
6976 01:00:08.137618 0, 0xFFFF, sum = 0
6977 01:00:08.140180 1, 0xFFFF, sum = 0
6978 01:00:08.140660 2, 0xFFFF, sum = 0
6979 01:00:08.144295 3, 0xFFFF, sum = 0
6980 01:00:08.144881 4, 0xFFFF, sum = 0
6981 01:00:08.146940 5, 0xFFFF, sum = 0
6982 01:00:08.147418 6, 0xFFFF, sum = 0
6983 01:00:08.150298 7, 0xFFFF, sum = 0
6984 01:00:08.154072 8, 0xFFFF, sum = 0
6985 01:00:08.154671 9, 0xFFFF, sum = 0
6986 01:00:08.157269 10, 0xFFFF, sum = 0
6987 01:00:08.157849 11, 0xFFFF, sum = 0
6988 01:00:08.160938 12, 0xFFFF, sum = 0
6989 01:00:08.161523 13, 0x0, sum = 1
6990 01:00:08.163952 14, 0x0, sum = 2
6991 01:00:08.164533 15, 0x0, sum = 3
6992 01:00:08.166772 16, 0x0, sum = 4
6993 01:00:08.167299 best_step = 14
6994 01:00:08.167691
6995 01:00:08.168043 ==
6996 01:00:08.170325 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 01:00:08.173331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 01:00:08.173808 ==
6999 01:00:08.177081 RX Vref Scan: 0
7000 01:00:08.177664
7001 01:00:08.180215 RX Vref 0 -> 0, step: 1
7002 01:00:08.180795
7003 01:00:08.181177 RX Delay -327 -> 252, step: 8
7004 01:00:08.189337 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7005 01:00:08.192689 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7006 01:00:08.195827 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7007 01:00:08.199413 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7008 01:00:08.205873 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7009 01:00:08.209338 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7010 01:00:08.212751 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7011 01:00:08.215754 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7012 01:00:08.222221 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7013 01:00:08.225613 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7014 01:00:08.228881 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7015 01:00:08.232035 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7016 01:00:08.238589 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7017 01:00:08.242214 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7018 01:00:08.245806 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7019 01:00:08.252008 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7020 01:00:08.252589 ==
7021 01:00:08.255508 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 01:00:08.258789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 01:00:08.259369 ==
7024 01:00:08.259752 DQS Delay:
7025 01:00:08.261864 DQS0 = 32, DQS1 = 36
7026 01:00:08.262472 DQM Delay:
7027 01:00:08.265305 DQM0 = 12, DQM1 = 11
7028 01:00:08.265874 DQ Delay:
7029 01:00:08.268768 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7030 01:00:08.271541 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7031 01:00:08.275484 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7032 01:00:08.278183 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7033 01:00:08.278656
7034 01:00:08.279037
7035 01:00:08.285543 [DQSOSCAuto] RK1, (LSB)MR18= 0xad55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7036 01:00:08.289252 CH1 RK1: MR19=C0C, MR18=AD55
7037 01:00:08.295076 CH1_RK1: MR19=0xC0C, MR18=0xAD55, DQSOSC=388, MR23=63, INC=392, DEC=261
7038 01:00:08.298794 [RxdqsGatingPostProcess] freq 400
7039 01:00:08.305043 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7040 01:00:08.308459 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 01:00:08.309032 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 01:00:08.311805 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 01:00:08.315023 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 01:00:08.318285 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 01:00:08.322081 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 01:00:08.324860 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 01:00:08.328645 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 01:00:08.331688 Pre-setting of DQS Precalculation
7049 01:00:08.338216 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7050 01:00:08.344873 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7051 01:00:08.352465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7052 01:00:08.353199
7053 01:00:08.353700
7054 01:00:08.354976 [Calibration Summary] 800 Mbps
7055 01:00:08.355461 CH 0, Rank 0
7056 01:00:08.358127 SW Impedance : PASS
7057 01:00:08.361381 DUTY Scan : NO K
7058 01:00:08.361850 ZQ Calibration : PASS
7059 01:00:08.364830 Jitter Meter : NO K
7060 01:00:08.365300 CBT Training : PASS
7061 01:00:08.368403 Write leveling : PASS
7062 01:00:08.371423 RX DQS gating : PASS
7063 01:00:08.372109 RX DQ/DQS(RDDQC) : PASS
7064 01:00:08.374880 TX DQ/DQS : PASS
7065 01:00:08.378629 RX DATLAT : PASS
7066 01:00:08.379098 RX DQ/DQS(Engine): PASS
7067 01:00:08.381430 TX OE : NO K
7068 01:00:08.381903 All Pass.
7069 01:00:08.382335
7070 01:00:08.385157 CH 0, Rank 1
7071 01:00:08.385728 SW Impedance : PASS
7072 01:00:08.388387 DUTY Scan : NO K
7073 01:00:08.391496 ZQ Calibration : PASS
7074 01:00:08.391968 Jitter Meter : NO K
7075 01:00:08.394502 CBT Training : PASS
7076 01:00:08.398164 Write leveling : NO K
7077 01:00:08.398740 RX DQS gating : PASS
7078 01:00:08.401565 RX DQ/DQS(RDDQC) : PASS
7079 01:00:08.405187 TX DQ/DQS : PASS
7080 01:00:08.405757 RX DATLAT : PASS
7081 01:00:08.407997 RX DQ/DQS(Engine): PASS
7082 01:00:08.411944 TX OE : NO K
7083 01:00:08.412521 All Pass.
7084 01:00:08.412896
7085 01:00:08.413242 CH 1, Rank 0
7086 01:00:08.414440 SW Impedance : PASS
7087 01:00:08.418475 DUTY Scan : NO K
7088 01:00:08.419050 ZQ Calibration : PASS
7089 01:00:08.420984 Jitter Meter : NO K
7090 01:00:08.421455 CBT Training : PASS
7091 01:00:08.424947 Write leveling : PASS
7092 01:00:08.428092 RX DQS gating : PASS
7093 01:00:08.428664 RX DQ/DQS(RDDQC) : PASS
7094 01:00:08.431139 TX DQ/DQS : PASS
7095 01:00:08.434442 RX DATLAT : PASS
7096 01:00:08.435211 RX DQ/DQS(Engine): PASS
7097 01:00:08.437631 TX OE : NO K
7098 01:00:08.438199 All Pass.
7099 01:00:08.438583
7100 01:00:08.440648 CH 1, Rank 1
7101 01:00:08.441118 SW Impedance : PASS
7102 01:00:08.443971 DUTY Scan : NO K
7103 01:00:08.447593 ZQ Calibration : PASS
7104 01:00:08.448247 Jitter Meter : NO K
7105 01:00:08.450704 CBT Training : PASS
7106 01:00:08.454232 Write leveling : NO K
7107 01:00:08.454884 RX DQS gating : PASS
7108 01:00:08.457471 RX DQ/DQS(RDDQC) : PASS
7109 01:00:08.460752 TX DQ/DQS : PASS
7110 01:00:08.461243 RX DATLAT : PASS
7111 01:00:08.464272 RX DQ/DQS(Engine): PASS
7112 01:00:08.464759 TX OE : NO K
7113 01:00:08.467453 All Pass.
7114 01:00:08.468029
7115 01:00:08.468500 DramC Write-DBI off
7116 01:00:08.470665 PER_BANK_REFRESH: Hybrid Mode
7117 01:00:08.474258 TX_TRACKING: ON
7118 01:00:08.480804 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7119 01:00:08.484939 [FAST_K] Save calibration result to emmc
7120 01:00:08.490921 dramc_set_vcore_voltage set vcore to 725000
7121 01:00:08.491512 Read voltage for 1600, 0
7122 01:00:08.494413 Vio18 = 0
7123 01:00:08.494951 Vcore = 725000
7124 01:00:08.495294 Vdram = 0
7125 01:00:08.495609 Vddq = 0
7126 01:00:08.497771 Vmddr = 0
7127 01:00:08.500534 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7128 01:00:08.507214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7129 01:00:08.510497 MEM_TYPE=3, freq_sel=13
7130 01:00:08.510932 sv_algorithm_assistance_LP4_3733
7131 01:00:08.516667 ============ PULL DRAM RESETB DOWN ============
7132 01:00:08.519969 ========== PULL DRAM RESETB DOWN end =========
7133 01:00:08.523404 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7134 01:00:08.526849 ===================================
7135 01:00:08.529874 LPDDR4 DRAM CONFIGURATION
7136 01:00:08.533224 ===================================
7137 01:00:08.536643 EX_ROW_EN[0] = 0x0
7138 01:00:08.536738 EX_ROW_EN[1] = 0x0
7139 01:00:08.540044 LP4Y_EN = 0x0
7140 01:00:08.540194 WORK_FSP = 0x1
7141 01:00:08.543410 WL = 0x5
7142 01:00:08.543484 RL = 0x5
7143 01:00:08.546792 BL = 0x2
7144 01:00:08.546876 RPST = 0x0
7145 01:00:08.550242 RD_PRE = 0x0
7146 01:00:08.550332 WR_PRE = 0x1
7147 01:00:08.553555 WR_PST = 0x1
7148 01:00:08.556758 DBI_WR = 0x0
7149 01:00:08.556856 DBI_RD = 0x0
7150 01:00:08.559879 OTF = 0x1
7151 01:00:08.563480 ===================================
7152 01:00:08.566250 ===================================
7153 01:00:08.566385 ANA top config
7154 01:00:08.569968 ===================================
7155 01:00:08.573241 DLL_ASYNC_EN = 0
7156 01:00:08.576834 ALL_SLAVE_EN = 0
7157 01:00:08.576992 NEW_RANK_MODE = 1
7158 01:00:08.579637 DLL_IDLE_MODE = 1
7159 01:00:08.582946 LP45_APHY_COMB_EN = 1
7160 01:00:08.586309 TX_ODT_DIS = 0
7161 01:00:08.586498 NEW_8X_MODE = 1
7162 01:00:08.589395 ===================================
7163 01:00:08.592939 ===================================
7164 01:00:08.596697 data_rate = 3200
7165 01:00:08.599500 CKR = 1
7166 01:00:08.602869 DQ_P2S_RATIO = 8
7167 01:00:08.606060 ===================================
7168 01:00:08.609415 CA_P2S_RATIO = 8
7169 01:00:08.612694 DQ_CA_OPEN = 0
7170 01:00:08.612887 DQ_SEMI_OPEN = 0
7171 01:00:08.615880 CA_SEMI_OPEN = 0
7172 01:00:08.619408 CA_FULL_RATE = 0
7173 01:00:08.622984 DQ_CKDIV4_EN = 0
7174 01:00:08.625896 CA_CKDIV4_EN = 0
7175 01:00:08.629269 CA_PREDIV_EN = 0
7176 01:00:08.629498 PH8_DLY = 12
7177 01:00:08.632627 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7178 01:00:08.635943 DQ_AAMCK_DIV = 4
7179 01:00:08.639322 CA_AAMCK_DIV = 4
7180 01:00:08.642522 CA_ADMCK_DIV = 4
7181 01:00:08.645761 DQ_TRACK_CA_EN = 0
7182 01:00:08.649151 CA_PICK = 1600
7183 01:00:08.649373 CA_MCKIO = 1600
7184 01:00:08.652553 MCKIO_SEMI = 0
7185 01:00:08.655777 PLL_FREQ = 3068
7186 01:00:08.659357 DQ_UI_PI_RATIO = 32
7187 01:00:08.662431 CA_UI_PI_RATIO = 0
7188 01:00:08.665791 ===================================
7189 01:00:08.669058 ===================================
7190 01:00:08.672475 memory_type:LPDDR4
7191 01:00:08.672731 GP_NUM : 10
7192 01:00:08.676126 SRAM_EN : 1
7193 01:00:08.676311 MD32_EN : 0
7194 01:00:08.679141 ===================================
7195 01:00:08.682356 [ANA_INIT] >>>>>>>>>>>>>>
7196 01:00:08.685441 <<<<<< [CONFIGURE PHASE]: ANA_TX
7197 01:00:08.689186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7198 01:00:08.692365 ===================================
7199 01:00:08.695721 data_rate = 3200,PCW = 0X7600
7200 01:00:08.698751 ===================================
7201 01:00:08.702461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7202 01:00:08.708994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 01:00:08.712067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 01:00:08.719199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7205 01:00:08.721850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7206 01:00:08.725374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7207 01:00:08.725449 [ANA_INIT] flow start
7208 01:00:08.728760 [ANA_INIT] PLL >>>>>>>>
7209 01:00:08.732583 [ANA_INIT] PLL <<<<<<<<
7210 01:00:08.732657 [ANA_INIT] MIDPI >>>>>>>>
7211 01:00:08.735573 [ANA_INIT] MIDPI <<<<<<<<
7212 01:00:08.738631 [ANA_INIT] DLL >>>>>>>>
7213 01:00:08.738725 [ANA_INIT] DLL <<<<<<<<
7214 01:00:08.742258 [ANA_INIT] flow end
7215 01:00:08.745536 ============ LP4 DIFF to SE enter ============
7216 01:00:08.748669 ============ LP4 DIFF to SE exit ============
7217 01:00:08.752101 [ANA_INIT] <<<<<<<<<<<<<
7218 01:00:08.755375 [Flow] Enable top DCM control >>>>>
7219 01:00:08.758469 [Flow] Enable top DCM control <<<<<
7220 01:00:08.762050 Enable DLL master slave shuffle
7221 01:00:08.768655 ==============================================================
7222 01:00:08.768747 Gating Mode config
7223 01:00:08.775257 ==============================================================
7224 01:00:08.778521 Config description:
7225 01:00:08.785129 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7226 01:00:08.791814 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7227 01:00:08.798319 SELPH_MODE 0: By rank 1: By Phase
7228 01:00:08.805446 ==============================================================
7229 01:00:08.805531 GAT_TRACK_EN = 1
7230 01:00:08.808649 RX_GATING_MODE = 2
7231 01:00:08.812326 RX_GATING_TRACK_MODE = 2
7232 01:00:08.815409 SELPH_MODE = 1
7233 01:00:08.818753 PICG_EARLY_EN = 1
7234 01:00:08.822203 VALID_LAT_VALUE = 1
7235 01:00:08.828580 ==============================================================
7236 01:00:08.831941 Enter into Gating configuration >>>>
7237 01:00:08.834903 Exit from Gating configuration <<<<
7238 01:00:08.838250 Enter into DVFS_PRE_config >>>>>
7239 01:00:08.848370 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7240 01:00:08.851351 Exit from DVFS_PRE_config <<<<<
7241 01:00:08.854927 Enter into PICG configuration >>>>
7242 01:00:08.857951 Exit from PICG configuration <<<<
7243 01:00:08.861329 [RX_INPUT] configuration >>>>>
7244 01:00:08.861420 [RX_INPUT] configuration <<<<<
7245 01:00:08.868444 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7246 01:00:08.874513 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7247 01:00:08.881327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 01:00:08.884392 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 01:00:08.890931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 01:00:08.897646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 01:00:08.901348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7252 01:00:08.904527 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7253 01:00:08.911884 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7254 01:00:08.915222 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7255 01:00:08.918168 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7256 01:00:08.924843 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 01:00:08.928323 ===================================
7258 01:00:08.928512 LPDDR4 DRAM CONFIGURATION
7259 01:00:08.931766 ===================================
7260 01:00:08.935046 EX_ROW_EN[0] = 0x0
7261 01:00:08.938178 EX_ROW_EN[1] = 0x0
7262 01:00:08.938347 LP4Y_EN = 0x0
7263 01:00:08.941277 WORK_FSP = 0x1
7264 01:00:08.941482 WL = 0x5
7265 01:00:08.944995 RL = 0x5
7266 01:00:08.945217 BL = 0x2
7267 01:00:08.947804 RPST = 0x0
7268 01:00:08.947996 RD_PRE = 0x0
7269 01:00:08.951475 WR_PRE = 0x1
7270 01:00:08.951715 WR_PST = 0x1
7271 01:00:08.954984 DBI_WR = 0x0
7272 01:00:08.955169 DBI_RD = 0x0
7273 01:00:08.957972 OTF = 0x1
7274 01:00:08.961391 ===================================
7275 01:00:08.964426 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7276 01:00:08.967671 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7277 01:00:08.974182 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7278 01:00:08.974275 ===================================
7279 01:00:08.977698 LPDDR4 DRAM CONFIGURATION
7280 01:00:08.980961 ===================================
7281 01:00:08.984111 EX_ROW_EN[0] = 0x10
7282 01:00:08.984222 EX_ROW_EN[1] = 0x0
7283 01:00:08.987588 LP4Y_EN = 0x0
7284 01:00:08.987693 WORK_FSP = 0x1
7285 01:00:08.990702 WL = 0x5
7286 01:00:08.990825 RL = 0x5
7287 01:00:08.994277 BL = 0x2
7288 01:00:08.994426 RPST = 0x0
7289 01:00:08.997866 RD_PRE = 0x0
7290 01:00:09.001141 WR_PRE = 0x1
7291 01:00:09.001256 WR_PST = 0x1
7292 01:00:09.004051 DBI_WR = 0x0
7293 01:00:09.004189 DBI_RD = 0x0
7294 01:00:09.007368 OTF = 0x1
7295 01:00:09.011101 ===================================
7296 01:00:09.013932 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7297 01:00:09.017740 ==
7298 01:00:09.020788 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 01:00:09.024995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 01:00:09.025297 ==
7301 01:00:09.027574 [Duty_Offset_Calibration]
7302 01:00:09.027820 B0:2 B1:0 CA:1
7303 01:00:09.028077
7304 01:00:09.030461 [DutyScan_Calibration_Flow] k_type=0
7305 01:00:09.040056
7306 01:00:09.040391 ==CLK 0==
7307 01:00:09.044060 Final CLK duty delay cell = -4
7308 01:00:09.046470 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7309 01:00:09.050005 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7310 01:00:09.053603 [-4] AVG Duty = 4906%(X100)
7311 01:00:09.054173
7312 01:00:09.057503 CH0 CLK Duty spec in!! Max-Min= 187%
7313 01:00:09.060014 [DutyScan_Calibration_Flow] ====Done====
7314 01:00:09.060445
7315 01:00:09.063469 [DutyScan_Calibration_Flow] k_type=1
7316 01:00:09.079863
7317 01:00:09.080544 ==DQS 0 ==
7318 01:00:09.082824 Final DQS duty delay cell = 0
7319 01:00:09.086579 [0] MAX Duty = 5249%(X100), DQS PI = 32
7320 01:00:09.089643 [0] MIN Duty = 4969%(X100), DQS PI = 0
7321 01:00:09.090149 [0] AVG Duty = 5109%(X100)
7322 01:00:09.093287
7323 01:00:09.093756 ==DQS 1 ==
7324 01:00:09.096319 Final DQS duty delay cell = -4
7325 01:00:09.099641 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7326 01:00:09.103450 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7327 01:00:09.106497 [-4] AVG Duty = 5000%(X100)
7328 01:00:09.106978
7329 01:00:09.109994 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7330 01:00:09.110594
7331 01:00:09.113173 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7332 01:00:09.116673 [DutyScan_Calibration_Flow] ====Done====
7333 01:00:09.117248
7334 01:00:09.119469 [DutyScan_Calibration_Flow] k_type=3
7335 01:00:09.137418
7336 01:00:09.138022 ==DQM 0 ==
7337 01:00:09.140821 Final DQM duty delay cell = 0
7338 01:00:09.144518 [0] MAX Duty = 5093%(X100), DQS PI = 26
7339 01:00:09.147166 [0] MIN Duty = 4844%(X100), DQS PI = 2
7340 01:00:09.147743 [0] AVG Duty = 4968%(X100)
7341 01:00:09.150869
7342 01:00:09.151439 ==DQM 1 ==
7343 01:00:09.154105 Final DQM duty delay cell = 0
7344 01:00:09.157341 [0] MAX Duty = 5249%(X100), DQS PI = 28
7345 01:00:09.160814 [0] MIN Duty = 5000%(X100), DQS PI = 20
7346 01:00:09.161395 [0] AVG Duty = 5124%(X100)
7347 01:00:09.164045
7348 01:00:09.167273 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7349 01:00:09.167847
7350 01:00:09.170822 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7351 01:00:09.173623 [DutyScan_Calibration_Flow] ====Done====
7352 01:00:09.174159
7353 01:00:09.177246 [DutyScan_Calibration_Flow] k_type=2
7354 01:00:09.194368
7355 01:00:09.194936 ==DQ 0 ==
7356 01:00:09.197916 Final DQ duty delay cell = 0
7357 01:00:09.200897 [0] MAX Duty = 5156%(X100), DQS PI = 36
7358 01:00:09.204306 [0] MIN Duty = 5000%(X100), DQS PI = 16
7359 01:00:09.204882 [0] AVG Duty = 5078%(X100)
7360 01:00:09.207366
7361 01:00:09.207854 ==DQ 1 ==
7362 01:00:09.210811 Final DQ duty delay cell = 0
7363 01:00:09.214344 [0] MAX Duty = 4969%(X100), DQS PI = 50
7364 01:00:09.217411 [0] MIN Duty = 4875%(X100), DQS PI = 0
7365 01:00:09.217872 [0] AVG Duty = 4922%(X100)
7366 01:00:09.218293
7367 01:00:09.221142 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7368 01:00:09.224197
7369 01:00:09.227414 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7370 01:00:09.230826 [DutyScan_Calibration_Flow] ====Done====
7371 01:00:09.231252 ==
7372 01:00:09.234463 Dram Type= 6, Freq= 0, CH_1, rank 0
7373 01:00:09.237486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7374 01:00:09.237909 ==
7375 01:00:09.240803 [Duty_Offset_Calibration]
7376 01:00:09.241318 B0:0 B1:-1 CA:2
7377 01:00:09.241651
7378 01:00:09.244415 [DutyScan_Calibration_Flow] k_type=0
7379 01:00:09.254639
7380 01:00:09.255155 ==CLK 0==
7381 01:00:09.258114 Final CLK duty delay cell = 0
7382 01:00:09.261288 [0] MAX Duty = 5156%(X100), DQS PI = 10
7383 01:00:09.264415 [0] MIN Duty = 4906%(X100), DQS PI = 46
7384 01:00:09.264886 [0] AVG Duty = 5031%(X100)
7385 01:00:09.267325
7386 01:00:09.270884 CH1 CLK Duty spec in!! Max-Min= 250%
7387 01:00:09.274286 [DutyScan_Calibration_Flow] ====Done====
7388 01:00:09.274846
7389 01:00:09.277534 [DutyScan_Calibration_Flow] k_type=1
7390 01:00:09.294100
7391 01:00:09.294523 ==DQS 0 ==
7392 01:00:09.297522 Final DQS duty delay cell = 0
7393 01:00:09.301103 [0] MAX Duty = 5124%(X100), DQS PI = 26
7394 01:00:09.304369 [0] MIN Duty = 4969%(X100), DQS PI = 0
7395 01:00:09.304905 [0] AVG Duty = 5046%(X100)
7396 01:00:09.307379
7397 01:00:09.307797 ==DQS 1 ==
7398 01:00:09.310755 Final DQS duty delay cell = 0
7399 01:00:09.314039 [0] MAX Duty = 5156%(X100), DQS PI = 0
7400 01:00:09.317314 [0] MIN Duty = 4844%(X100), DQS PI = 34
7401 01:00:09.320556 [0] AVG Duty = 5000%(X100)
7402 01:00:09.321226
7403 01:00:09.323625 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7404 01:00:09.324046
7405 01:00:09.327099 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7406 01:00:09.330543 [DutyScan_Calibration_Flow] ====Done====
7407 01:00:09.331092
7408 01:00:09.333977 [DutyScan_Calibration_Flow] k_type=3
7409 01:00:09.352137
7410 01:00:09.352709 ==DQM 0 ==
7411 01:00:09.355306 Final DQM duty delay cell = 4
7412 01:00:09.358437 [4] MAX Duty = 5125%(X100), DQS PI = 8
7413 01:00:09.362052 [4] MIN Duty = 5000%(X100), DQS PI = 34
7414 01:00:09.365466 [4] AVG Duty = 5062%(X100)
7415 01:00:09.366075
7416 01:00:09.366447 ==DQM 1 ==
7417 01:00:09.368428 Final DQM duty delay cell = 0
7418 01:00:09.372526 [0] MAX Duty = 5281%(X100), DQS PI = 58
7419 01:00:09.375072 [0] MIN Duty = 4876%(X100), DQS PI = 34
7420 01:00:09.378613 [0] AVG Duty = 5078%(X100)
7421 01:00:09.379196
7422 01:00:09.381712 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7423 01:00:09.382216
7424 01:00:09.385192 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7425 01:00:09.389019 [DutyScan_Calibration_Flow] ====Done====
7426 01:00:09.389607
7427 01:00:09.391645 [DutyScan_Calibration_Flow] k_type=2
7428 01:00:09.408797
7429 01:00:09.409378 ==DQ 0 ==
7430 01:00:09.411756 Final DQ duty delay cell = 0
7431 01:00:09.415369 [0] MAX Duty = 5062%(X100), DQS PI = 20
7432 01:00:09.418529 [0] MIN Duty = 4969%(X100), DQS PI = 0
7433 01:00:09.419101 [0] AVG Duty = 5015%(X100)
7434 01:00:09.419478
7435 01:00:09.422033 ==DQ 1 ==
7436 01:00:09.425036 Final DQ duty delay cell = 0
7437 01:00:09.428658 [0] MAX Duty = 5062%(X100), DQS PI = 2
7438 01:00:09.431687 [0] MIN Duty = 4813%(X100), DQS PI = 34
7439 01:00:09.432167 [0] AVG Duty = 4937%(X100)
7440 01:00:09.432548
7441 01:00:09.435305 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7442 01:00:09.435782
7443 01:00:09.438628 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7444 01:00:09.445446 [DutyScan_Calibration_Flow] ====Done====
7445 01:00:09.448517 nWR fixed to 30
7446 01:00:09.449092 [ModeRegInit_LP4] CH0 RK0
7447 01:00:09.452177 [ModeRegInit_LP4] CH0 RK1
7448 01:00:09.455754 [ModeRegInit_LP4] CH1 RK0
7449 01:00:09.456327 [ModeRegInit_LP4] CH1 RK1
7450 01:00:09.459000 match AC timing 5
7451 01:00:09.461655 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7452 01:00:09.465166 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7453 01:00:09.471975 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7454 01:00:09.475253 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7455 01:00:09.481860 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7456 01:00:09.482496 [MiockJmeterHQA]
7457 01:00:09.482875
7458 01:00:09.485387 [DramcMiockJmeter] u1RxGatingPI = 0
7459 01:00:09.488394 0 : 4255, 4029
7460 01:00:09.488975 4 : 4252, 4027
7461 01:00:09.489394 8 : 4255, 4029
7462 01:00:09.491702 12 : 4255, 4029
7463 01:00:09.492179 16 : 4257, 4029
7464 01:00:09.495257 20 : 4363, 4137
7465 01:00:09.495851 24 : 4362, 4137
7466 01:00:09.498502 28 : 4363, 4138
7467 01:00:09.498980 32 : 4257, 4029
7468 01:00:09.499361 36 : 4257, 4029
7469 01:00:09.501540 40 : 4252, 4027
7470 01:00:09.502063 44 : 4257, 4032
7471 01:00:09.504804 48 : 4363, 4137
7472 01:00:09.505280 52 : 4257, 4029
7473 01:00:09.508037 56 : 4363, 4137
7474 01:00:09.508537 60 : 4252, 4027
7475 01:00:09.511516 64 : 4250, 4027
7476 01:00:09.512108 68 : 4250, 4026
7477 01:00:09.512491 72 : 4363, 4137
7478 01:00:09.514662 76 : 4250, 4027
7479 01:00:09.515142 80 : 4250, 4027
7480 01:00:09.518092 84 : 4250, 4027
7481 01:00:09.518606 88 : 4250, 3841
7482 01:00:09.521363 92 : 4250, 0
7483 01:00:09.521849 96 : 4361, 0
7484 01:00:09.522334 100 : 4252, 0
7485 01:00:09.524781 104 : 4252, 0
7486 01:00:09.525360 108 : 4361, 0
7487 01:00:09.528414 112 : 4250, 0
7488 01:00:09.528991 116 : 4250, 0
7489 01:00:09.529380 120 : 4250, 0
7490 01:00:09.531355 124 : 4249, 0
7491 01:00:09.531839 128 : 4363, 0
7492 01:00:09.532221 132 : 4250, 0
7493 01:00:09.535190 136 : 4360, 0
7494 01:00:09.535673 140 : 4250, 0
7495 01:00:09.538005 144 : 4250, 0
7496 01:00:09.538491 148 : 4250, 0
7497 01:00:09.538869 152 : 4250, 0
7498 01:00:09.541818 156 : 4253, 0
7499 01:00:09.542352 160 : 4361, 0
7500 01:00:09.544794 164 : 4250, 0
7501 01:00:09.545278 168 : 4361, 0
7502 01:00:09.545663 172 : 4250, 0
7503 01:00:09.548160 176 : 4360, 0
7504 01:00:09.548598 180 : 4250, 0
7505 01:00:09.551761 184 : 4250, 0
7506 01:00:09.552297 188 : 4250, 0
7507 01:00:09.552650 192 : 4250, 0
7508 01:00:09.554680 196 : 4252, 0
7509 01:00:09.555118 200 : 4250, 5
7510 01:00:09.557803 204 : 4250, 2331
7511 01:00:09.558270 208 : 4250, 4027
7512 01:00:09.558623 212 : 4361, 4137
7513 01:00:09.561452 216 : 4253, 4029
7514 01:00:09.561891 220 : 4250, 4027
7515 01:00:09.564762 224 : 4250, 4027
7516 01:00:09.565199 228 : 4361, 4137
7517 01:00:09.568400 232 : 4250, 4027
7518 01:00:09.568942 236 : 4361, 4137
7519 01:00:09.571388 240 : 4363, 4140
7520 01:00:09.571926 244 : 4250, 4027
7521 01:00:09.574583 248 : 4250, 4027
7522 01:00:09.575021 252 : 4255, 4031
7523 01:00:09.577891 256 : 4250, 4027
7524 01:00:09.578389 260 : 4250, 4027
7525 01:00:09.581397 264 : 4252, 4027
7526 01:00:09.581838 268 : 4255, 4031
7527 01:00:09.584914 272 : 4250, 4027
7528 01:00:09.585449 276 : 4361, 4137
7529 01:00:09.585800 280 : 4361, 4138
7530 01:00:09.587944 284 : 4250, 4026
7531 01:00:09.588383 288 : 4360, 4138
7532 01:00:09.591168 292 : 4361, 4137
7533 01:00:09.591705 296 : 4250, 4027
7534 01:00:09.594473 300 : 4255, 4029
7535 01:00:09.594913 304 : 4363, 4140
7536 01:00:09.598038 308 : 4250, 4027
7537 01:00:09.598576 312 : 4250, 3888
7538 01:00:09.601109 316 : 4250, 2191
7539 01:00:09.601646 320 : 4253, 4
7540 01:00:09.602029
7541 01:00:09.604620 MIOCK jitter meter ch=0
7542 01:00:09.605156
7543 01:00:09.608054 1T = (320-92) = 228 dly cells
7544 01:00:09.611189 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7545 01:00:09.611725 ==
7546 01:00:09.614510 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 01:00:09.621124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 01:00:09.621660 ==
7549 01:00:09.624173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7550 01:00:09.630972 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7551 01:00:09.634452 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7552 01:00:09.640917 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7553 01:00:09.648839 [CA 0] Center 42 (12~72) winsize 61
7554 01:00:09.651804 [CA 1] Center 42 (13~72) winsize 60
7555 01:00:09.655244 [CA 2] Center 37 (7~67) winsize 61
7556 01:00:09.658767 [CA 3] Center 37 (7~67) winsize 61
7557 01:00:09.661749 [CA 4] Center 36 (6~66) winsize 61
7558 01:00:09.665382 [CA 5] Center 35 (5~65) winsize 61
7559 01:00:09.665992
7560 01:00:09.668999 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7561 01:00:09.669571
7562 01:00:09.671912 [CATrainingPosCal] consider 1 rank data
7563 01:00:09.675371 u2DelayCellTimex100 = 285/100 ps
7564 01:00:09.678498 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7565 01:00:09.685527 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7566 01:00:09.688476 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7567 01:00:09.692149 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7568 01:00:09.695282 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7569 01:00:09.698665 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7570 01:00:09.699242
7571 01:00:09.702082 CA PerBit enable=1, Macro0, CA PI delay=35
7572 01:00:09.702556
7573 01:00:09.705255 [CBTSetCACLKResult] CA Dly = 35
7574 01:00:09.708523 CS Dly: 9 (0~40)
7575 01:00:09.711917 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7576 01:00:09.715467 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7577 01:00:09.716044 ==
7578 01:00:09.718065 Dram Type= 6, Freq= 0, CH_0, rank 1
7579 01:00:09.722114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 01:00:09.722690 ==
7581 01:00:09.728705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7582 01:00:09.731717 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7583 01:00:09.738057 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7584 01:00:09.741465 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7585 01:00:09.751811 [CA 0] Center 43 (13~73) winsize 61
7586 01:00:09.755132 [CA 1] Center 43 (13~73) winsize 61
7587 01:00:09.758315 [CA 2] Center 38 (9~67) winsize 59
7588 01:00:09.762198 [CA 3] Center 38 (8~68) winsize 61
7589 01:00:09.765106 [CA 4] Center 37 (7~67) winsize 61
7590 01:00:09.768522 [CA 5] Center 36 (6~66) winsize 61
7591 01:00:09.769092
7592 01:00:09.772292 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7593 01:00:09.772866
7594 01:00:09.774920 [CATrainingPosCal] consider 2 rank data
7595 01:00:09.778193 u2DelayCellTimex100 = 285/100 ps
7596 01:00:09.781413 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7597 01:00:09.788575 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7598 01:00:09.792101 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7599 01:00:09.795254 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7600 01:00:09.798798 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7601 01:00:09.801907 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7602 01:00:09.802527
7603 01:00:09.805357 CA PerBit enable=1, Macro0, CA PI delay=35
7604 01:00:09.806001
7605 01:00:09.809036 [CBTSetCACLKResult] CA Dly = 35
7606 01:00:09.811762 CS Dly: 10 (0~43)
7607 01:00:09.815106 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7608 01:00:09.818571 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7609 01:00:09.819158
7610 01:00:09.821933 ----->DramcWriteLeveling(PI) begin...
7611 01:00:09.822551 ==
7612 01:00:09.824927 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 01:00:09.828272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 01:00:09.831521 ==
7615 01:00:09.834817 Write leveling (Byte 0): 38 => 38
7616 01:00:09.835403 Write leveling (Byte 1): 31 => 31
7617 01:00:09.838509 DramcWriteLeveling(PI) end<-----
7618 01:00:09.838987
7619 01:00:09.839387 ==
7620 01:00:09.841612 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 01:00:09.848241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 01:00:09.848725 ==
7623 01:00:09.851601 [Gating] SW mode calibration
7624 01:00:09.858056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7625 01:00:09.861193 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7626 01:00:09.868010 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 01:00:09.871432 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 01:00:09.874462 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
7629 01:00:09.881175 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7630 01:00:09.884754 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7631 01:00:09.888226 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7632 01:00:09.894899 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 01:00:09.898238 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 01:00:09.901627 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 01:00:09.908125 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 01:00:09.911336 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)
7637 01:00:09.914538 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7638 01:00:09.918101 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7639 01:00:09.924415 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7640 01:00:09.927862 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 01:00:09.931107 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 01:00:09.937458 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 01:00:09.941204 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7644 01:00:09.944431 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7645 01:00:09.950996 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7646 01:00:09.954187 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7647 01:00:09.957715 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 01:00:09.964093 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 01:00:09.967301 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 01:00:09.970917 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 01:00:09.977353 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 01:00:09.980704 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7653 01:00:09.984037 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7654 01:00:09.990871 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7655 01:00:09.994230 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7656 01:00:09.998034 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 01:00:10.004313 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 01:00:10.006948 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 01:00:10.010624 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 01:00:10.017359 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 01:00:10.020416 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 01:00:10.023947 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 01:00:10.030628 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 01:00:10.034253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 01:00:10.037246 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 01:00:10.043670 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 01:00:10.047415 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 01:00:10.050673 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7669 01:00:10.057011 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7670 01:00:10.060389 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7671 01:00:10.063511 Total UI for P1: 0, mck2ui 16
7672 01:00:10.066796 best dqsien dly found for B0: ( 1, 9, 10)
7673 01:00:10.070021 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 01:00:10.074108 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 01:00:10.076851 Total UI for P1: 0, mck2ui 16
7676 01:00:10.080103 best dqsien dly found for B1: ( 1, 9, 20)
7677 01:00:10.086669 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7678 01:00:10.089812 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7679 01:00:10.090489
7680 01:00:10.093781 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7681 01:00:10.097180 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7682 01:00:10.100088 [Gating] SW calibration Done
7683 01:00:10.100649 ==
7684 01:00:10.103667 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 01:00:10.106563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 01:00:10.107041 ==
7687 01:00:10.110215 RX Vref Scan: 0
7688 01:00:10.110782
7689 01:00:10.111157 RX Vref 0 -> 0, step: 1
7690 01:00:10.111508
7691 01:00:10.113304 RX Delay 0 -> 252, step: 8
7692 01:00:10.117088 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7693 01:00:10.123653 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7694 01:00:10.126731 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7695 01:00:10.129900 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7696 01:00:10.133334 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7697 01:00:10.136735 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7698 01:00:10.139864 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7699 01:00:10.146453 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7700 01:00:10.149802 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7701 01:00:10.153305 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7702 01:00:10.156131 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7703 01:00:10.159752 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7704 01:00:10.166358 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7705 01:00:10.169635 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7706 01:00:10.172959 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7707 01:00:10.176773 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7708 01:00:10.177363 ==
7709 01:00:10.179391 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 01:00:10.186309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 01:00:10.186785 ==
7712 01:00:10.187159 DQS Delay:
7713 01:00:10.189544 DQS0 = 0, DQS1 = 0
7714 01:00:10.190046 DQM Delay:
7715 01:00:10.190427 DQM0 = 138, DQM1 = 127
7716 01:00:10.192930 DQ Delay:
7717 01:00:10.196124 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7718 01:00:10.199591 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7719 01:00:10.202716 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7720 01:00:10.206149 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7721 01:00:10.206622
7722 01:00:10.206990
7723 01:00:10.207329 ==
7724 01:00:10.210058 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 01:00:10.213281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 01:00:10.216398 ==
7727 01:00:10.216971
7728 01:00:10.217347
7729 01:00:10.217691 TX Vref Scan disable
7730 01:00:10.219962 == TX Byte 0 ==
7731 01:00:10.222929 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7732 01:00:10.226548 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7733 01:00:10.229713 == TX Byte 1 ==
7734 01:00:10.233165 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7735 01:00:10.236387 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7736 01:00:10.239644 ==
7737 01:00:10.240110 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 01:00:10.246207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 01:00:10.246777 ==
7740 01:00:10.260172
7741 01:00:10.263439 TX Vref early break, caculate TX vref
7742 01:00:10.266593 TX Vref=16, minBit 4, minWin=22, winSum=375
7743 01:00:10.269622 TX Vref=18, minBit 7, minWin=23, winSum=384
7744 01:00:10.273633 TX Vref=20, minBit 7, minWin=23, winSum=393
7745 01:00:10.276506 TX Vref=22, minBit 0, minWin=25, winSum=408
7746 01:00:10.279628 TX Vref=24, minBit 0, minWin=25, winSum=418
7747 01:00:10.286254 TX Vref=26, minBit 2, minWin=25, winSum=425
7748 01:00:10.289524 TX Vref=28, minBit 4, minWin=25, winSum=428
7749 01:00:10.293125 TX Vref=30, minBit 0, minWin=26, winSum=423
7750 01:00:10.296337 TX Vref=32, minBit 0, minWin=25, winSum=417
7751 01:00:10.299581 TX Vref=34, minBit 11, minWin=24, winSum=407
7752 01:00:10.302988 TX Vref=36, minBit 1, minWin=24, winSum=392
7753 01:00:10.309588 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
7754 01:00:10.310240
7755 01:00:10.312875 Final TX Range 0 Vref 30
7756 01:00:10.313430
7757 01:00:10.313922 ==
7758 01:00:10.315897 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 01:00:10.319513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 01:00:10.320028 ==
7761 01:00:10.322829
7762 01:00:10.323422
7763 01:00:10.323914 TX Vref Scan disable
7764 01:00:10.329527 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7765 01:00:10.330159 == TX Byte 0 ==
7766 01:00:10.332612 u2DelayCellOfst[0]=10 cells (3 PI)
7767 01:00:10.335869 u2DelayCellOfst[1]=17 cells (5 PI)
7768 01:00:10.338979 u2DelayCellOfst[2]=10 cells (3 PI)
7769 01:00:10.342439 u2DelayCellOfst[3]=10 cells (3 PI)
7770 01:00:10.345820 u2DelayCellOfst[4]=6 cells (2 PI)
7771 01:00:10.349323 u2DelayCellOfst[5]=0 cells (0 PI)
7772 01:00:10.352588 u2DelayCellOfst[6]=17 cells (5 PI)
7773 01:00:10.355904 u2DelayCellOfst[7]=13 cells (4 PI)
7774 01:00:10.358893 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7775 01:00:10.362496 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7776 01:00:10.365843 == TX Byte 1 ==
7777 01:00:10.369098 u2DelayCellOfst[8]=0 cells (0 PI)
7778 01:00:10.372522 u2DelayCellOfst[9]=3 cells (1 PI)
7779 01:00:10.375536 u2DelayCellOfst[10]=6 cells (2 PI)
7780 01:00:10.378623 u2DelayCellOfst[11]=3 cells (1 PI)
7781 01:00:10.382633 u2DelayCellOfst[12]=13 cells (4 PI)
7782 01:00:10.383120 u2DelayCellOfst[13]=10 cells (3 PI)
7783 01:00:10.385664 u2DelayCellOfst[14]=17 cells (5 PI)
7784 01:00:10.389029 u2DelayCellOfst[15]=13 cells (4 PI)
7785 01:00:10.395517 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7786 01:00:10.398943 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7787 01:00:10.399434 DramC Write-DBI on
7788 01:00:10.402115 ==
7789 01:00:10.405683 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 01:00:10.408891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 01:00:10.409490 ==
7792 01:00:10.410022
7793 01:00:10.410470
7794 01:00:10.411889 TX Vref Scan disable
7795 01:00:10.412372 == TX Byte 0 ==
7796 01:00:10.418861 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7797 01:00:10.419458 == TX Byte 1 ==
7798 01:00:10.421880 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7799 01:00:10.425137 DramC Write-DBI off
7800 01:00:10.425726
7801 01:00:10.426261 [DATLAT]
7802 01:00:10.428466 Freq=1600, CH0 RK0
7803 01:00:10.429062
7804 01:00:10.429548 DATLAT Default: 0xf
7805 01:00:10.431898 0, 0xFFFF, sum = 0
7806 01:00:10.432500 1, 0xFFFF, sum = 0
7807 01:00:10.435105 2, 0xFFFF, sum = 0
7808 01:00:10.435637 3, 0xFFFF, sum = 0
7809 01:00:10.438329 4, 0xFFFF, sum = 0
7810 01:00:10.438857 5, 0xFFFF, sum = 0
7811 01:00:10.441659 6, 0xFFFF, sum = 0
7812 01:00:10.445057 7, 0xFFFF, sum = 0
7813 01:00:10.445636 8, 0xFFFF, sum = 0
7814 01:00:10.448515 9, 0xFFFF, sum = 0
7815 01:00:10.449095 10, 0xFFFF, sum = 0
7816 01:00:10.451771 11, 0xFFFF, sum = 0
7817 01:00:10.452353 12, 0xFFFF, sum = 0
7818 01:00:10.455125 13, 0xFFFF, sum = 0
7819 01:00:10.455597 14, 0x0, sum = 1
7820 01:00:10.458379 15, 0x0, sum = 2
7821 01:00:10.458966 16, 0x0, sum = 3
7822 01:00:10.461877 17, 0x0, sum = 4
7823 01:00:10.462482 best_step = 15
7824 01:00:10.462859
7825 01:00:10.463200 ==
7826 01:00:10.464977 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 01:00:10.468836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 01:00:10.469417 ==
7829 01:00:10.471888 RX Vref Scan: 1
7830 01:00:10.472460
7831 01:00:10.475228 Set Vref Range= 24 -> 127
7832 01:00:10.475694
7833 01:00:10.476065 RX Vref 24 -> 127, step: 1
7834 01:00:10.476410
7835 01:00:10.478149 RX Delay 19 -> 252, step: 4
7836 01:00:10.478613
7837 01:00:10.481685 Set Vref, RX VrefLevel [Byte0]: 24
7838 01:00:10.484989 [Byte1]: 24
7839 01:00:10.488385
7840 01:00:10.488971 Set Vref, RX VrefLevel [Byte0]: 25
7841 01:00:10.491760 [Byte1]: 25
7842 01:00:10.495948
7843 01:00:10.496415 Set Vref, RX VrefLevel [Byte0]: 26
7844 01:00:10.499539 [Byte1]: 26
7845 01:00:10.503501
7846 01:00:10.504043 Set Vref, RX VrefLevel [Byte0]: 27
7847 01:00:10.506634 [Byte1]: 27
7848 01:00:10.511969
7849 01:00:10.512555 Set Vref, RX VrefLevel [Byte0]: 28
7850 01:00:10.514481 [Byte1]: 28
7851 01:00:10.518826
7852 01:00:10.519417 Set Vref, RX VrefLevel [Byte0]: 29
7853 01:00:10.521784 [Byte1]: 29
7854 01:00:10.526688
7855 01:00:10.527283 Set Vref, RX VrefLevel [Byte0]: 30
7856 01:00:10.529637 [Byte1]: 30
7857 01:00:10.534126
7858 01:00:10.534703 Set Vref, RX VrefLevel [Byte0]: 31
7859 01:00:10.537534 [Byte1]: 31
7860 01:00:10.541217
7861 01:00:10.541870 Set Vref, RX VrefLevel [Byte0]: 32
7862 01:00:10.544798 [Byte1]: 32
7863 01:00:10.548632
7864 01:00:10.549100 Set Vref, RX VrefLevel [Byte0]: 33
7865 01:00:10.552326 [Byte1]: 33
7866 01:00:10.556979
7867 01:00:10.557546 Set Vref, RX VrefLevel [Byte0]: 34
7868 01:00:10.559882 [Byte1]: 34
7869 01:00:10.564242
7870 01:00:10.564810 Set Vref, RX VrefLevel [Byte0]: 35
7871 01:00:10.567690 [Byte1]: 35
7872 01:00:10.571664
7873 01:00:10.572231 Set Vref, RX VrefLevel [Byte0]: 36
7874 01:00:10.574828 [Byte1]: 36
7875 01:00:10.579315
7876 01:00:10.579920 Set Vref, RX VrefLevel [Byte0]: 37
7877 01:00:10.582356 [Byte1]: 37
7878 01:00:10.586923
7879 01:00:10.587500 Set Vref, RX VrefLevel [Byte0]: 38
7880 01:00:10.590197 [Byte1]: 38
7881 01:00:10.594535
7882 01:00:10.595114 Set Vref, RX VrefLevel [Byte0]: 39
7883 01:00:10.597520 [Byte1]: 39
7884 01:00:10.601820
7885 01:00:10.602435 Set Vref, RX VrefLevel [Byte0]: 40
7886 01:00:10.605299 [Byte1]: 40
7887 01:00:10.609327
7888 01:00:10.612923 Set Vref, RX VrefLevel [Byte0]: 41
7889 01:00:10.616258 [Byte1]: 41
7890 01:00:10.616836
7891 01:00:10.619870 Set Vref, RX VrefLevel [Byte0]: 42
7892 01:00:10.622483 [Byte1]: 42
7893 01:00:10.622956
7894 01:00:10.626339 Set Vref, RX VrefLevel [Byte0]: 43
7895 01:00:10.629324 [Byte1]: 43
7896 01:00:10.629912
7897 01:00:10.632635 Set Vref, RX VrefLevel [Byte0]: 44
7898 01:00:10.635883 [Byte1]: 44
7899 01:00:10.639660
7900 01:00:10.640128 Set Vref, RX VrefLevel [Byte0]: 45
7901 01:00:10.643199 [Byte1]: 45
7902 01:00:10.647398
7903 01:00:10.647978 Set Vref, RX VrefLevel [Byte0]: 46
7904 01:00:10.650813 [Byte1]: 46
7905 01:00:10.654823
7906 01:00:10.655420 Set Vref, RX VrefLevel [Byte0]: 47
7907 01:00:10.658370 [Byte1]: 47
7908 01:00:10.662565
7909 01:00:10.663145 Set Vref, RX VrefLevel [Byte0]: 48
7910 01:00:10.665790 [Byte1]: 48
7911 01:00:10.670606
7912 01:00:10.671182 Set Vref, RX VrefLevel [Byte0]: 49
7913 01:00:10.673503 [Byte1]: 49
7914 01:00:10.677741
7915 01:00:10.678368 Set Vref, RX VrefLevel [Byte0]: 50
7916 01:00:10.680784 [Byte1]: 50
7917 01:00:10.685516
7918 01:00:10.686131 Set Vref, RX VrefLevel [Byte0]: 51
7919 01:00:10.688575 [Byte1]: 51
7920 01:00:10.692901
7921 01:00:10.693376 Set Vref, RX VrefLevel [Byte0]: 52
7922 01:00:10.696000 [Byte1]: 52
7923 01:00:10.700856
7924 01:00:10.701434 Set Vref, RX VrefLevel [Byte0]: 53
7925 01:00:10.703595 [Byte1]: 53
7926 01:00:10.707823
7927 01:00:10.708294 Set Vref, RX VrefLevel [Byte0]: 54
7928 01:00:10.711178 [Byte1]: 54
7929 01:00:10.715806
7930 01:00:10.716380 Set Vref, RX VrefLevel [Byte0]: 55
7931 01:00:10.719008 [Byte1]: 55
7932 01:00:10.723243
7933 01:00:10.723822 Set Vref, RX VrefLevel [Byte0]: 56
7934 01:00:10.726304 [Byte1]: 56
7935 01:00:10.730470
7936 01:00:10.730946 Set Vref, RX VrefLevel [Byte0]: 57
7937 01:00:10.734825 [Byte1]: 57
7938 01:00:10.738174
7939 01:00:10.738783 Set Vref, RX VrefLevel [Byte0]: 58
7940 01:00:10.744881 [Byte1]: 58
7941 01:00:10.745476
7942 01:00:10.748209 Set Vref, RX VrefLevel [Byte0]: 59
7943 01:00:10.751561 [Byte1]: 59
7944 01:00:10.752139
7945 01:00:10.755236 Set Vref, RX VrefLevel [Byte0]: 60
7946 01:00:10.758046 [Byte1]: 60
7947 01:00:10.758622
7948 01:00:10.761675 Set Vref, RX VrefLevel [Byte0]: 61
7949 01:00:10.764959 [Byte1]: 61
7950 01:00:10.768695
7951 01:00:10.769269 Set Vref, RX VrefLevel [Byte0]: 62
7952 01:00:10.771940 [Byte1]: 62
7953 01:00:10.776398
7954 01:00:10.776974 Set Vref, RX VrefLevel [Byte0]: 63
7955 01:00:10.779364 [Byte1]: 63
7956 01:00:10.783545
7957 01:00:10.784115 Set Vref, RX VrefLevel [Byte0]: 64
7958 01:00:10.786970 [Byte1]: 64
7959 01:00:10.791413
7960 01:00:10.791991 Set Vref, RX VrefLevel [Byte0]: 65
7961 01:00:10.794384 [Byte1]: 65
7962 01:00:10.798566
7963 01:00:10.799197 Set Vref, RX VrefLevel [Byte0]: 66
7964 01:00:10.801871 [Byte1]: 66
7965 01:00:10.806840
7966 01:00:10.807416 Set Vref, RX VrefLevel [Byte0]: 67
7967 01:00:10.809885 [Byte1]: 67
7968 01:00:10.814414
7969 01:00:10.814885 Set Vref, RX VrefLevel [Byte0]: 68
7970 01:00:10.817330 [Byte1]: 68
7971 01:00:10.821835
7972 01:00:10.822573 Set Vref, RX VrefLevel [Byte0]: 69
7973 01:00:10.824555 [Byte1]: 69
7974 01:00:10.828985
7975 01:00:10.829521 Set Vref, RX VrefLevel [Byte0]: 70
7976 01:00:10.832207 [Byte1]: 70
7977 01:00:10.836477
7978 01:00:10.837098 Set Vref, RX VrefLevel [Byte0]: 71
7979 01:00:10.839952 [Byte1]: 71
7980 01:00:10.844031
7981 01:00:10.844543 Set Vref, RX VrefLevel [Byte0]: 72
7982 01:00:10.847136 [Byte1]: 72
7983 01:00:10.851503
7984 01:00:10.852025 Set Vref, RX VrefLevel [Byte0]: 73
7985 01:00:10.854940 [Byte1]: 73
7986 01:00:10.859605
7987 01:00:10.860075 Set Vref, RX VrefLevel [Byte0]: 74
7988 01:00:10.862789 [Byte1]: 74
7989 01:00:10.866526
7990 01:00:10.866874 Set Vref, RX VrefLevel [Byte0]: 75
7991 01:00:10.869900 [Byte1]: 75
7992 01:00:10.874206
7993 01:00:10.874448 Set Vref, RX VrefLevel [Byte0]: 76
7994 01:00:10.877711 [Byte1]: 76
7995 01:00:10.881696
7996 01:00:10.881889 Set Vref, RX VrefLevel [Byte0]: 77
7997 01:00:10.885188 [Byte1]: 77
7998 01:00:10.889394
7999 01:00:10.889531 Set Vref, RX VrefLevel [Byte0]: 78
8000 01:00:10.892611 [Byte1]: 78
8001 01:00:10.897298
8002 01:00:10.897574 Set Vref, RX VrefLevel [Byte0]: 79
8003 01:00:10.900021 [Byte1]: 79
8004 01:00:10.904231
8005 01:00:10.904425 Set Vref, RX VrefLevel [Byte0]: 80
8006 01:00:10.907453 [Byte1]: 80
8007 01:00:10.911893
8008 01:00:10.911976 Final RX Vref Byte 0 = 59 to rank0
8009 01:00:10.915238 Final RX Vref Byte 1 = 60 to rank0
8010 01:00:10.918582 Final RX Vref Byte 0 = 59 to rank1
8011 01:00:10.921759 Final RX Vref Byte 1 = 60 to rank1==
8012 01:00:10.925233 Dram Type= 6, Freq= 0, CH_0, rank 0
8013 01:00:10.931923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 01:00:10.932008 ==
8015 01:00:10.932075 DQS Delay:
8016 01:00:10.932136 DQS0 = 0, DQS1 = 0
8017 01:00:10.935228 DQM Delay:
8018 01:00:10.935312 DQM0 = 135, DQM1 = 124
8019 01:00:10.938358 DQ Delay:
8020 01:00:10.942035 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8021 01:00:10.945572 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
8022 01:00:10.948735 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8023 01:00:10.951925 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =132
8024 01:00:10.952089
8025 01:00:10.952164
8026 01:00:10.952271
8027 01:00:10.955062 [DramC_TX_OE_Calibration] TA2
8028 01:00:10.958457 Original DQ_B0 (3 6) =30, OEN = 27
8029 01:00:10.961702 Original DQ_B1 (3 6) =30, OEN = 27
8030 01:00:10.965242 24, 0x0, End_B0=24 End_B1=24
8031 01:00:10.965329 25, 0x0, End_B0=25 End_B1=25
8032 01:00:10.968909 26, 0x0, End_B0=26 End_B1=26
8033 01:00:10.971991 27, 0x0, End_B0=27 End_B1=27
8034 01:00:10.975580 28, 0x0, End_B0=28 End_B1=28
8035 01:00:10.978846 29, 0x0, End_B0=29 End_B1=29
8036 01:00:10.979027 30, 0x0, End_B0=30 End_B1=30
8037 01:00:10.982033 31, 0x4141, End_B0=30 End_B1=30
8038 01:00:10.985434 Byte0 end_step=30 best_step=27
8039 01:00:10.988945 Byte1 end_step=30 best_step=27
8040 01:00:10.991907 Byte0 TX OE(2T, 0.5T) = (3, 3)
8041 01:00:10.995267 Byte1 TX OE(2T, 0.5T) = (3, 3)
8042 01:00:10.995474
8043 01:00:10.995584
8044 01:00:11.001701 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8045 01:00:11.005144 CH0 RK0: MR19=303, MR18=201E
8046 01:00:11.011733 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8047 01:00:11.011989
8048 01:00:11.015152 ----->DramcWriteLeveling(PI) begin...
8049 01:00:11.015409 ==
8050 01:00:11.018410 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 01:00:11.021889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 01:00:11.022257 ==
8053 01:00:11.025035 Write leveling (Byte 0): 35 => 35
8054 01:00:11.028501 Write leveling (Byte 1): 30 => 30
8055 01:00:11.032100 DramcWriteLeveling(PI) end<-----
8056 01:00:11.032503
8057 01:00:11.032817 ==
8058 01:00:11.035298 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 01:00:11.038530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 01:00:11.039013 ==
8061 01:00:11.041409 [Gating] SW mode calibration
8062 01:00:11.048501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 01:00:11.055342 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8064 01:00:11.058296 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 01:00:11.064777 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 01:00:11.069074 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 01:00:11.071861 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8068 01:00:11.075065 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 01:00:11.081590 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 01:00:11.084786 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 01:00:11.088357 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 01:00:11.095241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 01:00:11.098324 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 01:00:11.101699 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8075 01:00:11.108088 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
8076 01:00:11.111350 1 5 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8077 01:00:11.115342 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 01:00:11.121696 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 01:00:11.124866 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 01:00:11.128051 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 01:00:11.134318 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 01:00:11.137601 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8083 01:00:11.141223 1 6 12 | B1->B0 | 2727 3f3f | 1 0 | (0 0) (0 0)
8084 01:00:11.147677 1 6 16 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8085 01:00:11.150852 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 01:00:11.154205 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 01:00:11.160900 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 01:00:11.164045 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 01:00:11.167214 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 01:00:11.173916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 01:00:11.177394 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8092 01:00:11.180519 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8093 01:00:11.187766 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 01:00:11.190872 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 01:00:11.193870 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 01:00:11.200784 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 01:00:11.203827 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 01:00:11.207166 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 01:00:11.213967 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 01:00:11.217254 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 01:00:11.220414 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 01:00:11.227366 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 01:00:11.230399 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 01:00:11.233467 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 01:00:11.240341 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 01:00:11.243740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 01:00:11.246879 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8108 01:00:11.253829 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 01:00:11.254496 Total UI for P1: 0, mck2ui 16
8110 01:00:11.257128 best dqsien dly found for B0: ( 1, 9, 10)
8111 01:00:11.260330 Total UI for P1: 0, mck2ui 16
8112 01:00:11.263557 best dqsien dly found for B1: ( 1, 9, 12)
8113 01:00:11.267026 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8114 01:00:11.273469 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8115 01:00:11.274200
8116 01:00:11.276713 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8117 01:00:11.280088 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8118 01:00:11.283381 [Gating] SW calibration Done
8119 01:00:11.283826 ==
8120 01:00:11.287040 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 01:00:11.290217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 01:00:11.290651 ==
8123 01:00:11.293628 RX Vref Scan: 0
8124 01:00:11.294225
8125 01:00:11.294581 RX Vref 0 -> 0, step: 1
8126 01:00:11.294906
8127 01:00:11.296739 RX Delay 0 -> 252, step: 8
8128 01:00:11.300027 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 01:00:11.303284 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8130 01:00:11.310374 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8131 01:00:11.314068 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8132 01:00:11.316462 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8133 01:00:11.319826 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8134 01:00:11.323206 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8135 01:00:11.330074 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8136 01:00:11.333186 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8137 01:00:11.336542 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8138 01:00:11.339815 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8139 01:00:11.343095 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8140 01:00:11.349910 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8141 01:00:11.353172 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8142 01:00:11.356486 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8143 01:00:11.359767 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8144 01:00:11.360201 ==
8145 01:00:11.363465 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 01:00:11.369597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 01:00:11.370060 ==
8148 01:00:11.370411 DQS Delay:
8149 01:00:11.373159 DQS0 = 0, DQS1 = 0
8150 01:00:11.373590 DQM Delay:
8151 01:00:11.376379 DQM0 = 135, DQM1 = 125
8152 01:00:11.376808 DQ Delay:
8153 01:00:11.379975 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8154 01:00:11.383176 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8155 01:00:11.386687 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8156 01:00:11.389727 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8157 01:00:11.390192
8158 01:00:11.390533
8159 01:00:11.390849 ==
8160 01:00:11.393387 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 01:00:11.399632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 01:00:11.400068 ==
8163 01:00:11.400408
8164 01:00:11.400725
8165 01:00:11.401030 TX Vref Scan disable
8166 01:00:11.403215 == TX Byte 0 ==
8167 01:00:11.406456 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8168 01:00:11.412810 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8169 01:00:11.413243 == TX Byte 1 ==
8170 01:00:11.416409 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8171 01:00:11.422982 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8172 01:00:11.423416 ==
8173 01:00:11.426312 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 01:00:11.429634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 01:00:11.430114 ==
8176 01:00:11.442545
8177 01:00:11.445749 TX Vref early break, caculate TX vref
8178 01:00:11.449402 TX Vref=16, minBit 0, minWin=24, winSum=389
8179 01:00:11.452200 TX Vref=18, minBit 1, minWin=23, winSum=396
8180 01:00:11.455976 TX Vref=20, minBit 0, minWin=24, winSum=405
8181 01:00:11.458879 TX Vref=22, minBit 0, minWin=25, winSum=417
8182 01:00:11.462204 TX Vref=24, minBit 0, minWin=26, winSum=422
8183 01:00:11.468845 TX Vref=26, minBit 1, minWin=26, winSum=428
8184 01:00:11.472179 TX Vref=28, minBit 0, minWin=26, winSum=432
8185 01:00:11.475534 TX Vref=30, minBit 2, minWin=25, winSum=424
8186 01:00:11.478875 TX Vref=32, minBit 2, minWin=25, winSum=420
8187 01:00:11.482246 TX Vref=34, minBit 1, minWin=24, winSum=406
8188 01:00:11.488717 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8189 01:00:11.489158
8190 01:00:11.492208 Final TX Range 0 Vref 28
8191 01:00:11.492650
8192 01:00:11.493096 ==
8193 01:00:11.495371 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 01:00:11.498734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 01:00:11.499185 ==
8196 01:00:11.499620
8197 01:00:11.500027
8198 01:00:11.502032 TX Vref Scan disable
8199 01:00:11.508657 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8200 01:00:11.509099 == TX Byte 0 ==
8201 01:00:11.511918 u2DelayCellOfst[0]=13 cells (4 PI)
8202 01:00:11.515587 u2DelayCellOfst[1]=17 cells (5 PI)
8203 01:00:11.518476 u2DelayCellOfst[2]=13 cells (4 PI)
8204 01:00:11.521893 u2DelayCellOfst[3]=10 cells (3 PI)
8205 01:00:11.525266 u2DelayCellOfst[4]=10 cells (3 PI)
8206 01:00:11.528698 u2DelayCellOfst[5]=0 cells (0 PI)
8207 01:00:11.531874 u2DelayCellOfst[6]=17 cells (5 PI)
8208 01:00:11.535124 u2DelayCellOfst[7]=17 cells (5 PI)
8209 01:00:11.538375 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8210 01:00:11.541582 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8211 01:00:11.544968 == TX Byte 1 ==
8212 01:00:11.548403 u2DelayCellOfst[8]=0 cells (0 PI)
8213 01:00:11.548820 u2DelayCellOfst[9]=3 cells (1 PI)
8214 01:00:11.551952 u2DelayCellOfst[10]=10 cells (3 PI)
8215 01:00:11.555112 u2DelayCellOfst[11]=3 cells (1 PI)
8216 01:00:11.558257 u2DelayCellOfst[12]=13 cells (4 PI)
8217 01:00:11.561703 u2DelayCellOfst[13]=13 cells (4 PI)
8218 01:00:11.564786 u2DelayCellOfst[14]=17 cells (5 PI)
8219 01:00:11.568335 u2DelayCellOfst[15]=10 cells (3 PI)
8220 01:00:11.571548 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8221 01:00:11.578075 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8222 01:00:11.578738 DramC Write-DBI on
8223 01:00:11.579216 ==
8224 01:00:11.581462 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 01:00:11.588173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 01:00:11.588641 ==
8227 01:00:11.589016
8228 01:00:11.589332
8229 01:00:11.589630 TX Vref Scan disable
8230 01:00:11.591988 == TX Byte 0 ==
8231 01:00:11.595745 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8232 01:00:11.598725 == TX Byte 1 ==
8233 01:00:11.602017 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8234 01:00:11.605526 DramC Write-DBI off
8235 01:00:11.606082
8236 01:00:11.606462 [DATLAT]
8237 01:00:11.606834 Freq=1600, CH0 RK1
8238 01:00:11.607174
8239 01:00:11.608593 DATLAT Default: 0xf
8240 01:00:11.609038 0, 0xFFFF, sum = 0
8241 01:00:11.611918 1, 0xFFFF, sum = 0
8242 01:00:11.615127 2, 0xFFFF, sum = 0
8243 01:00:11.615629 3, 0xFFFF, sum = 0
8244 01:00:11.618504 4, 0xFFFF, sum = 0
8245 01:00:11.618950 5, 0xFFFF, sum = 0
8246 01:00:11.621933 6, 0xFFFF, sum = 0
8247 01:00:11.622405 7, 0xFFFF, sum = 0
8248 01:00:11.625055 8, 0xFFFF, sum = 0
8249 01:00:11.625486 9, 0xFFFF, sum = 0
8250 01:00:11.628374 10, 0xFFFF, sum = 0
8251 01:00:11.628804 11, 0xFFFF, sum = 0
8252 01:00:11.632103 12, 0xFFFF, sum = 0
8253 01:00:11.632532 13, 0xFFFF, sum = 0
8254 01:00:11.635392 14, 0x0, sum = 1
8255 01:00:11.635820 15, 0x0, sum = 2
8256 01:00:11.638257 16, 0x0, sum = 3
8257 01:00:11.638686 17, 0x0, sum = 4
8258 01:00:11.641914 best_step = 15
8259 01:00:11.642360
8260 01:00:11.642698 ==
8261 01:00:11.645424 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 01:00:11.648463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 01:00:11.648889 ==
8264 01:00:11.651922 RX Vref Scan: 0
8265 01:00:11.652343
8266 01:00:11.652677 RX Vref 0 -> 0, step: 1
8267 01:00:11.652990
8268 01:00:11.655663 RX Delay 11 -> 252, step: 4
8269 01:00:11.658430 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8270 01:00:11.664893 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8271 01:00:11.668646 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8272 01:00:11.671724 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8273 01:00:11.675227 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8274 01:00:11.678377 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8275 01:00:11.685355 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8276 01:00:11.688195 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8277 01:00:11.691712 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8278 01:00:11.694861 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8279 01:00:11.697964 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8280 01:00:11.704922 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8281 01:00:11.708122 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8282 01:00:11.711132 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8283 01:00:11.714691 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8284 01:00:11.717764 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8285 01:00:11.721149 ==
8286 01:00:11.724706 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 01:00:11.727982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 01:00:11.728406 ==
8289 01:00:11.728743 DQS Delay:
8290 01:00:11.731237 DQS0 = 0, DQS1 = 0
8291 01:00:11.731658 DQM Delay:
8292 01:00:11.734221 DQM0 = 133, DQM1 = 123
8293 01:00:11.734641 DQ Delay:
8294 01:00:11.737711 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8295 01:00:11.741169 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8296 01:00:11.744768 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8297 01:00:11.747745 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8298 01:00:11.748167
8299 01:00:11.748501
8300 01:00:11.748807
8301 01:00:11.751261 [DramC_TX_OE_Calibration] TA2
8302 01:00:11.754401 Original DQ_B0 (3 6) =30, OEN = 27
8303 01:00:11.757527 Original DQ_B1 (3 6) =30, OEN = 27
8304 01:00:11.760809 24, 0x0, End_B0=24 End_B1=24
8305 01:00:11.764056 25, 0x0, End_B0=25 End_B1=25
8306 01:00:11.768009 26, 0x0, End_B0=26 End_B1=26
8307 01:00:11.768433 27, 0x0, End_B0=27 End_B1=27
8308 01:00:11.770759 28, 0x0, End_B0=28 End_B1=28
8309 01:00:11.774348 29, 0x0, End_B0=29 End_B1=29
8310 01:00:11.777296 30, 0x0, End_B0=30 End_B1=30
8311 01:00:11.780577 31, 0x4141, End_B0=30 End_B1=30
8312 01:00:11.781007 Byte0 end_step=30 best_step=27
8313 01:00:11.784073 Byte1 end_step=30 best_step=27
8314 01:00:11.787206 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 01:00:11.790704 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 01:00:11.791099
8317 01:00:11.791568
8318 01:00:11.797124 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8319 01:00:11.800691 CH0 RK1: MR19=303, MR18=1E0B
8320 01:00:11.807207 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8321 01:00:11.810374 [RxdqsGatingPostProcess] freq 1600
8322 01:00:11.816778 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 01:00:11.820458 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 01:00:11.823634 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 01:00:11.824060 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 01:00:11.826879 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 01:00:11.830280 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 01:00:11.833207 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 01:00:11.837130 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 01:00:11.840122 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 01:00:11.843448 Pre-setting of DQS Precalculation
8332 01:00:11.850241 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 01:00:11.850690 ==
8334 01:00:11.853512 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 01:00:11.856848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 01:00:11.857287 ==
8337 01:00:11.863233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 01:00:11.866735 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 01:00:11.869711 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 01:00:11.876485 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 01:00:11.884923 [CA 0] Center 42 (13~72) winsize 60
8342 01:00:11.888511 [CA 1] Center 42 (12~72) winsize 61
8343 01:00:11.891723 [CA 2] Center 38 (9~68) winsize 60
8344 01:00:11.894749 [CA 3] Center 37 (8~67) winsize 60
8345 01:00:11.898543 [CA 4] Center 38 (8~68) winsize 61
8346 01:00:11.901451 [CA 5] Center 37 (7~67) winsize 61
8347 01:00:11.901893
8348 01:00:11.904833 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8349 01:00:11.905253
8350 01:00:11.908013 [CATrainingPosCal] consider 1 rank data
8351 01:00:11.911408 u2DelayCellTimex100 = 285/100 ps
8352 01:00:11.914860 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8353 01:00:11.921239 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8354 01:00:11.925076 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 01:00:11.928188 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 01:00:11.931444 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8357 01:00:11.934481 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8358 01:00:11.934902
8359 01:00:11.938031 CA PerBit enable=1, Macro0, CA PI delay=37
8360 01:00:11.938479
8361 01:00:11.941108 [CBTSetCACLKResult] CA Dly = 37
8362 01:00:11.944545 CS Dly: 8 (0~39)
8363 01:00:11.947896 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 01:00:11.951416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 01:00:11.951831 ==
8366 01:00:11.954391 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 01:00:11.957884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 01:00:11.958218 ==
8369 01:00:11.964224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 01:00:11.967885 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 01:00:11.974312 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 01:00:11.977384 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 01:00:11.987685 [CA 0] Center 41 (12~71) winsize 60
8374 01:00:11.990959 [CA 1] Center 41 (12~71) winsize 60
8375 01:00:11.994286 [CA 2] Center 38 (9~67) winsize 59
8376 01:00:11.998104 [CA 3] Center 37 (8~67) winsize 60
8377 01:00:12.001522 [CA 4] Center 37 (8~67) winsize 60
8378 01:00:12.004517 [CA 5] Center 37 (7~67) winsize 61
8379 01:00:12.004932
8380 01:00:12.007833 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 01:00:12.008250
8382 01:00:12.011362 [CATrainingPosCal] consider 2 rank data
8383 01:00:12.014499 u2DelayCellTimex100 = 285/100 ps
8384 01:00:12.018290 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8385 01:00:12.024636 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8386 01:00:12.028036 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8387 01:00:12.031354 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8388 01:00:12.034852 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8389 01:00:12.037821 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8390 01:00:12.038284
8391 01:00:12.041091 CA PerBit enable=1, Macro0, CA PI delay=37
8392 01:00:12.041507
8393 01:00:12.044414 [CBTSetCACLKResult] CA Dly = 37
8394 01:00:12.047830 CS Dly: 9 (0~42)
8395 01:00:12.051176 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 01:00:12.054495 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 01:00:12.054909
8398 01:00:12.057648 ----->DramcWriteLeveling(PI) begin...
8399 01:00:12.058105 ==
8400 01:00:12.061518 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 01:00:12.064808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 01:00:12.067984 ==
8403 01:00:12.068397 Write leveling (Byte 0): 24 => 24
8404 01:00:12.071350 Write leveling (Byte 1): 27 => 27
8405 01:00:12.074385 DramcWriteLeveling(PI) end<-----
8406 01:00:12.074799
8407 01:00:12.075121 ==
8408 01:00:12.077895 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 01:00:12.084389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 01:00:12.084804 ==
8411 01:00:12.085197 [Gating] SW mode calibration
8412 01:00:12.094479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 01:00:12.097773 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 01:00:12.104582 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 01:00:12.108186 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 01:00:12.111177 1 4 8 | B1->B0 | 2828 2d2d | 1 0 | (1 1) (0 0)
8417 01:00:12.114362 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 01:00:12.120867 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 01:00:12.124104 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 01:00:12.127668 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 01:00:12.134155 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 01:00:12.137518 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 01:00:12.141041 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8424 01:00:12.147415 1 5 8 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (1 0)
8425 01:00:12.150756 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8426 01:00:12.153874 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 01:00:12.160419 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 01:00:12.163955 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 01:00:12.167097 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 01:00:12.173693 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 01:00:12.177151 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8432 01:00:12.180473 1 6 8 | B1->B0 | 3838 3f3e | 0 1 | (0 0) (0 0)
8433 01:00:12.187267 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 01:00:12.190592 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 01:00:12.193896 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 01:00:12.200203 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 01:00:12.203578 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 01:00:12.206746 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 01:00:12.213507 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8440 01:00:12.216994 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 01:00:12.220155 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 01:00:12.226861 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8443 01:00:12.230511 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 01:00:12.233530 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 01:00:12.239966 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 01:00:12.243503 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 01:00:12.246967 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 01:00:12.253333 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 01:00:12.256901 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 01:00:12.260247 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 01:00:12.267058 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 01:00:12.270010 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 01:00:12.273844 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 01:00:12.276959 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 01:00:12.283088 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8456 01:00:12.286920 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 01:00:12.290187 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8458 01:00:12.293678 Total UI for P1: 0, mck2ui 16
8459 01:00:12.296765 best dqsien dly found for B0: ( 1, 9, 6)
8460 01:00:12.303129 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8461 01:00:12.306428 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 01:00:12.309882 Total UI for P1: 0, mck2ui 16
8463 01:00:12.313278 best dqsien dly found for B1: ( 1, 9, 12)
8464 01:00:12.316451 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8465 01:00:12.320029 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8466 01:00:12.320556
8467 01:00:12.323172 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8468 01:00:12.326521 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8469 01:00:12.330046 [Gating] SW calibration Done
8470 01:00:12.330478 ==
8471 01:00:12.333022 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 01:00:12.339723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 01:00:12.340237 ==
8474 01:00:12.340740 RX Vref Scan: 0
8475 01:00:12.341078
8476 01:00:12.343208 RX Vref 0 -> 0, step: 1
8477 01:00:12.343640
8478 01:00:12.346322 RX Delay 0 -> 252, step: 8
8479 01:00:12.349717 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8480 01:00:12.353184 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8481 01:00:12.356414 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8482 01:00:12.360262 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8483 01:00:12.366502 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8484 01:00:12.369540 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8485 01:00:12.373276 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8486 01:00:12.376571 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8487 01:00:12.380264 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8488 01:00:12.382973 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8489 01:00:12.389910 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8490 01:00:12.393001 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8491 01:00:12.396266 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8492 01:00:12.400043 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8493 01:00:12.406044 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8494 01:00:12.409432 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8495 01:00:12.409901 ==
8496 01:00:12.412962 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 01:00:12.416265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 01:00:12.416896 ==
8499 01:00:12.419408 DQS Delay:
8500 01:00:12.420072 DQS0 = 0, DQS1 = 0
8501 01:00:12.420673 DQM Delay:
8502 01:00:12.423420 DQM0 = 136, DQM1 = 131
8503 01:00:12.424100 DQ Delay:
8504 01:00:12.426265 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8505 01:00:12.429116 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8506 01:00:12.432887 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8507 01:00:12.439857 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8508 01:00:12.440293
8509 01:00:12.440725
8510 01:00:12.441183 ==
8511 01:00:12.442985 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 01:00:12.446685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 01:00:12.447169 ==
8514 01:00:12.447646
8515 01:00:12.448093
8516 01:00:12.449429 TX Vref Scan disable
8517 01:00:12.449907 == TX Byte 0 ==
8518 01:00:12.456236 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8519 01:00:12.459215 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8520 01:00:12.459690 == TX Byte 1 ==
8521 01:00:12.466542 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8522 01:00:12.469803 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8523 01:00:12.470278 ==
8524 01:00:12.472465 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 01:00:12.476077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 01:00:12.476519 ==
8527 01:00:12.489467
8528 01:00:12.492644 TX Vref early break, caculate TX vref
8529 01:00:12.496323 TX Vref=16, minBit 10, minWin=22, winSum=374
8530 01:00:12.499650 TX Vref=18, minBit 10, minWin=22, winSum=378
8531 01:00:12.502895 TX Vref=20, minBit 10, minWin=23, winSum=393
8532 01:00:12.506063 TX Vref=22, minBit 15, minWin=23, winSum=400
8533 01:00:12.512583 TX Vref=24, minBit 0, minWin=25, winSum=412
8534 01:00:12.515968 TX Vref=26, minBit 10, minWin=25, winSum=422
8535 01:00:12.519597 TX Vref=28, minBit 10, minWin=25, winSum=424
8536 01:00:12.522728 TX Vref=30, minBit 8, minWin=25, winSum=419
8537 01:00:12.526042 TX Vref=32, minBit 12, minWin=24, winSum=410
8538 01:00:12.529444 TX Vref=34, minBit 12, minWin=23, winSum=401
8539 01:00:12.535701 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 28
8540 01:00:12.536221
8541 01:00:12.539357 Final TX Range 0 Vref 28
8542 01:00:12.539895
8543 01:00:12.540414 ==
8544 01:00:12.542694 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 01:00:12.545874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 01:00:12.546407 ==
8547 01:00:12.549914
8548 01:00:12.550527
8549 01:00:12.550905 TX Vref Scan disable
8550 01:00:12.556005 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8551 01:00:12.556491 == TX Byte 0 ==
8552 01:00:12.559359 u2DelayCellOfst[0]=17 cells (5 PI)
8553 01:00:12.562425 u2DelayCellOfst[1]=10 cells (3 PI)
8554 01:00:12.565826 u2DelayCellOfst[2]=0 cells (0 PI)
8555 01:00:12.569309 u2DelayCellOfst[3]=6 cells (2 PI)
8556 01:00:12.572445 u2DelayCellOfst[4]=6 cells (2 PI)
8557 01:00:12.576310 u2DelayCellOfst[5]=17 cells (5 PI)
8558 01:00:12.579395 u2DelayCellOfst[6]=17 cells (5 PI)
8559 01:00:12.582771 u2DelayCellOfst[7]=6 cells (2 PI)
8560 01:00:12.585995 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8561 01:00:12.589711 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8562 01:00:12.592417 == TX Byte 1 ==
8563 01:00:12.596126 u2DelayCellOfst[8]=0 cells (0 PI)
8564 01:00:12.596672 u2DelayCellOfst[9]=3 cells (1 PI)
8565 01:00:12.599323 u2DelayCellOfst[10]=10 cells (3 PI)
8566 01:00:12.602580 u2DelayCellOfst[11]=3 cells (1 PI)
8567 01:00:12.605687 u2DelayCellOfst[12]=17 cells (5 PI)
8568 01:00:12.609020 u2DelayCellOfst[13]=17 cells (5 PI)
8569 01:00:12.612253 u2DelayCellOfst[14]=20 cells (6 PI)
8570 01:00:12.615611 u2DelayCellOfst[15]=17 cells (5 PI)
8571 01:00:12.619140 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8572 01:00:12.625447 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8573 01:00:12.625558 DramC Write-DBI on
8574 01:00:12.625658 ==
8575 01:00:12.628542 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 01:00:12.634928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 01:00:12.635039 ==
8578 01:00:12.635137
8579 01:00:12.635235
8580 01:00:12.635331 TX Vref Scan disable
8581 01:00:12.638999 == TX Byte 0 ==
8582 01:00:12.642465 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8583 01:00:12.646140 == TX Byte 1 ==
8584 01:00:12.649286 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8585 01:00:12.652257 DramC Write-DBI off
8586 01:00:12.652342
8587 01:00:12.652409 [DATLAT]
8588 01:00:12.652471 Freq=1600, CH1 RK0
8589 01:00:12.652530
8590 01:00:12.655682 DATLAT Default: 0xf
8591 01:00:12.655765 0, 0xFFFF, sum = 0
8592 01:00:12.658761 1, 0xFFFF, sum = 0
8593 01:00:12.662184 2, 0xFFFF, sum = 0
8594 01:00:12.662293 3, 0xFFFF, sum = 0
8595 01:00:12.665477 4, 0xFFFF, sum = 0
8596 01:00:12.665580 5, 0xFFFF, sum = 0
8597 01:00:12.668831 6, 0xFFFF, sum = 0
8598 01:00:12.668906 7, 0xFFFF, sum = 0
8599 01:00:12.672213 8, 0xFFFF, sum = 0
8600 01:00:12.672298 9, 0xFFFF, sum = 0
8601 01:00:12.675482 10, 0xFFFF, sum = 0
8602 01:00:12.675567 11, 0xFFFF, sum = 0
8603 01:00:12.678942 12, 0xFFFF, sum = 0
8604 01:00:12.679028 13, 0xFFFF, sum = 0
8605 01:00:12.682088 14, 0x0, sum = 1
8606 01:00:12.682193 15, 0x0, sum = 2
8607 01:00:12.685672 16, 0x0, sum = 3
8608 01:00:12.685783 17, 0x0, sum = 4
8609 01:00:12.689054 best_step = 15
8610 01:00:12.689164
8611 01:00:12.689260 ==
8612 01:00:12.692509 Dram Type= 6, Freq= 0, CH_1, rank 0
8613 01:00:12.695714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8614 01:00:12.695804 ==
8615 01:00:12.699079 RX Vref Scan: 1
8616 01:00:12.699162
8617 01:00:12.699229 Set Vref Range= 24 -> 127
8618 01:00:12.699292
8619 01:00:12.702164 RX Vref 24 -> 127, step: 1
8620 01:00:12.702273
8621 01:00:12.705372 RX Delay 19 -> 252, step: 4
8622 01:00:12.705461
8623 01:00:12.708668 Set Vref, RX VrefLevel [Byte0]: 24
8624 01:00:12.712327 [Byte1]: 24
8625 01:00:12.712422
8626 01:00:12.715460 Set Vref, RX VrefLevel [Byte0]: 25
8627 01:00:12.718985 [Byte1]: 25
8628 01:00:12.719098
8629 01:00:12.722174 Set Vref, RX VrefLevel [Byte0]: 26
8630 01:00:12.725358 [Byte1]: 26
8631 01:00:12.729651
8632 01:00:12.729874 Set Vref, RX VrefLevel [Byte0]: 27
8633 01:00:12.732924 [Byte1]: 27
8634 01:00:12.737029
8635 01:00:12.737321 Set Vref, RX VrefLevel [Byte0]: 28
8636 01:00:12.740891 [Byte1]: 28
8637 01:00:12.744595
8638 01:00:12.744834 Set Vref, RX VrefLevel [Byte0]: 29
8639 01:00:12.748311 [Byte1]: 29
8640 01:00:12.752230
8641 01:00:12.752501 Set Vref, RX VrefLevel [Byte0]: 30
8642 01:00:12.755818 [Byte1]: 30
8643 01:00:12.759874
8644 01:00:12.760307 Set Vref, RX VrefLevel [Byte0]: 31
8645 01:00:12.763848 [Byte1]: 31
8646 01:00:12.767475
8647 01:00:12.767957 Set Vref, RX VrefLevel [Byte0]: 32
8648 01:00:12.771340 [Byte1]: 32
8649 01:00:12.775144
8650 01:00:12.775637 Set Vref, RX VrefLevel [Byte0]: 33
8651 01:00:12.778822 [Byte1]: 33
8652 01:00:12.782877
8653 01:00:12.783467 Set Vref, RX VrefLevel [Byte0]: 34
8654 01:00:12.785911 [Byte1]: 34
8655 01:00:12.790517
8656 01:00:12.790991 Set Vref, RX VrefLevel [Byte0]: 35
8657 01:00:12.793798 [Byte1]: 35
8658 01:00:12.797867
8659 01:00:12.798460 Set Vref, RX VrefLevel [Byte0]: 36
8660 01:00:12.801142 [Byte1]: 36
8661 01:00:12.805354
8662 01:00:12.805818 Set Vref, RX VrefLevel [Byte0]: 37
8663 01:00:12.808670 [Byte1]: 37
8664 01:00:12.812976
8665 01:00:12.813397 Set Vref, RX VrefLevel [Byte0]: 38
8666 01:00:12.816792 [Byte1]: 38
8667 01:00:12.820730
8668 01:00:12.821301 Set Vref, RX VrefLevel [Byte0]: 39
8669 01:00:12.824144 [Byte1]: 39
8670 01:00:12.828387
8671 01:00:12.828959 Set Vref, RX VrefLevel [Byte0]: 40
8672 01:00:12.831550 [Byte1]: 40
8673 01:00:12.835697
8674 01:00:12.836199 Set Vref, RX VrefLevel [Byte0]: 41
8675 01:00:12.838934 [Byte1]: 41
8676 01:00:12.843434
8677 01:00:12.844036 Set Vref, RX VrefLevel [Byte0]: 42
8678 01:00:12.847158 [Byte1]: 42
8679 01:00:12.850931
8680 01:00:12.851397 Set Vref, RX VrefLevel [Byte0]: 43
8681 01:00:12.854654 [Byte1]: 43
8682 01:00:12.858496
8683 01:00:12.858968 Set Vref, RX VrefLevel [Byte0]: 44
8684 01:00:12.861644 [Byte1]: 44
8685 01:00:12.866146
8686 01:00:12.866617 Set Vref, RX VrefLevel [Byte0]: 45
8687 01:00:12.869441 [Byte1]: 45
8688 01:00:12.873465
8689 01:00:12.873993 Set Vref, RX VrefLevel [Byte0]: 46
8690 01:00:12.876975 [Byte1]: 46
8691 01:00:12.881343
8692 01:00:12.881990 Set Vref, RX VrefLevel [Byte0]: 47
8693 01:00:12.884516 [Byte1]: 47
8694 01:00:12.888759
8695 01:00:12.889231 Set Vref, RX VrefLevel [Byte0]: 48
8696 01:00:12.892102 [Byte1]: 48
8697 01:00:12.896479
8698 01:00:12.897082 Set Vref, RX VrefLevel [Byte0]: 49
8699 01:00:12.899812 [Byte1]: 49
8700 01:00:12.903859
8701 01:00:12.904447 Set Vref, RX VrefLevel [Byte0]: 50
8702 01:00:12.907328 [Byte1]: 50
8703 01:00:12.911485
8704 01:00:12.911957 Set Vref, RX VrefLevel [Byte0]: 51
8705 01:00:12.914597 [Byte1]: 51
8706 01:00:12.919389
8707 01:00:12.919970 Set Vref, RX VrefLevel [Byte0]: 52
8708 01:00:12.922442 [Byte1]: 52
8709 01:00:12.926582
8710 01:00:12.927167 Set Vref, RX VrefLevel [Byte0]: 53
8711 01:00:12.930121 [Byte1]: 53
8712 01:00:12.934582
8713 01:00:12.935162 Set Vref, RX VrefLevel [Byte0]: 54
8714 01:00:12.938003 [Byte1]: 54
8715 01:00:12.942024
8716 01:00:12.942635 Set Vref, RX VrefLevel [Byte0]: 55
8717 01:00:12.945678 [Byte1]: 55
8718 01:00:12.949064
8719 01:00:12.949538 Set Vref, RX VrefLevel [Byte0]: 56
8720 01:00:12.952857 [Byte1]: 56
8721 01:00:12.956985
8722 01:00:12.957481 Set Vref, RX VrefLevel [Byte0]: 57
8723 01:00:12.960195 [Byte1]: 57
8724 01:00:12.964423
8725 01:00:12.964900 Set Vref, RX VrefLevel [Byte0]: 58
8726 01:00:12.967863 [Byte1]: 58
8727 01:00:12.971900
8728 01:00:12.972372 Set Vref, RX VrefLevel [Byte0]: 59
8729 01:00:12.975132 [Byte1]: 59
8730 01:00:12.979846
8731 01:00:12.980340 Set Vref, RX VrefLevel [Byte0]: 60
8732 01:00:12.982912 [Byte1]: 60
8733 01:00:12.987424
8734 01:00:12.987893 Set Vref, RX VrefLevel [Byte0]: 61
8735 01:00:12.990428 [Byte1]: 61
8736 01:00:12.994974
8737 01:00:12.995442 Set Vref, RX VrefLevel [Byte0]: 62
8738 01:00:12.997861 [Byte1]: 62
8739 01:00:13.002381
8740 01:00:13.002854 Set Vref, RX VrefLevel [Byte0]: 63
8741 01:00:13.005519 [Byte1]: 63
8742 01:00:13.010025
8743 01:00:13.010495 Set Vref, RX VrefLevel [Byte0]: 64
8744 01:00:13.013525 [Byte1]: 64
8745 01:00:13.017828
8746 01:00:13.018334 Set Vref, RX VrefLevel [Byte0]: 65
8747 01:00:13.021133 [Byte1]: 65
8748 01:00:13.025108
8749 01:00:13.025582 Set Vref, RX VrefLevel [Byte0]: 66
8750 01:00:13.028451 [Byte1]: 66
8751 01:00:13.033103
8752 01:00:13.033673 Set Vref, RX VrefLevel [Byte0]: 67
8753 01:00:13.036232 [Byte1]: 67
8754 01:00:13.040414
8755 01:00:13.040890 Set Vref, RX VrefLevel [Byte0]: 68
8756 01:00:13.043573 [Byte1]: 68
8757 01:00:13.048224
8758 01:00:13.048803 Set Vref, RX VrefLevel [Byte0]: 69
8759 01:00:13.051278 [Byte1]: 69
8760 01:00:13.055379
8761 01:00:13.055947 Set Vref, RX VrefLevel [Byte0]: 70
8762 01:00:13.058710 [Byte1]: 70
8763 01:00:13.063047
8764 01:00:13.063666 Set Vref, RX VrefLevel [Byte0]: 71
8765 01:00:13.066187 [Byte1]: 71
8766 01:00:13.070874
8767 01:00:13.071464 Set Vref, RX VrefLevel [Byte0]: 72
8768 01:00:13.073739 [Byte1]: 72
8769 01:00:13.078171
8770 01:00:13.078737 Set Vref, RX VrefLevel [Byte0]: 73
8771 01:00:13.081332 [Byte1]: 73
8772 01:00:13.085981
8773 01:00:13.086449 Set Vref, RX VrefLevel [Byte0]: 74
8774 01:00:13.089161 [Byte1]: 74
8775 01:00:13.093095
8776 01:00:13.093702 Set Vref, RX VrefLevel [Byte0]: 75
8777 01:00:13.096704 [Byte1]: 75
8778 01:00:13.100920
8779 01:00:13.101488 Final RX Vref Byte 0 = 58 to rank0
8780 01:00:13.104391 Final RX Vref Byte 1 = 60 to rank0
8781 01:00:13.107443 Final RX Vref Byte 0 = 58 to rank1
8782 01:00:13.110601 Final RX Vref Byte 1 = 60 to rank1==
8783 01:00:13.114061 Dram Type= 6, Freq= 0, CH_1, rank 0
8784 01:00:13.120937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 01:00:13.121688 ==
8786 01:00:13.122138 DQS Delay:
8787 01:00:13.122493 DQS0 = 0, DQS1 = 0
8788 01:00:13.124531 DQM Delay:
8789 01:00:13.125053 DQM0 = 133, DQM1 = 129
8790 01:00:13.127646 DQ Delay:
8791 01:00:13.130662 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8792 01:00:13.134463 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8793 01:00:13.137535 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8794 01:00:13.140751 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =136
8795 01:00:13.141324
8796 01:00:13.141697
8797 01:00:13.142094
8798 01:00:13.144075 [DramC_TX_OE_Calibration] TA2
8799 01:00:13.147320 Original DQ_B0 (3 6) =30, OEN = 27
8800 01:00:13.150735 Original DQ_B1 (3 6) =30, OEN = 27
8801 01:00:13.153910 24, 0x0, End_B0=24 End_B1=24
8802 01:00:13.154528 25, 0x0, End_B0=25 End_B1=25
8803 01:00:13.157564 26, 0x0, End_B0=26 End_B1=26
8804 01:00:13.160584 27, 0x0, End_B0=27 End_B1=27
8805 01:00:13.163882 28, 0x0, End_B0=28 End_B1=28
8806 01:00:13.167373 29, 0x0, End_B0=29 End_B1=29
8807 01:00:13.168010 30, 0x0, End_B0=30 End_B1=30
8808 01:00:13.170455 31, 0x5151, End_B0=30 End_B1=30
8809 01:00:13.173799 Byte0 end_step=30 best_step=27
8810 01:00:13.176993 Byte1 end_step=30 best_step=27
8811 01:00:13.180763 Byte0 TX OE(2T, 0.5T) = (3, 3)
8812 01:00:13.183592 Byte1 TX OE(2T, 0.5T) = (3, 3)
8813 01:00:13.184062
8814 01:00:13.184429
8815 01:00:13.190301 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8816 01:00:13.193542 CH1 RK0: MR19=303, MR18=1927
8817 01:00:13.199758 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8818 01:00:13.200393
8819 01:00:13.203167 ----->DramcWriteLeveling(PI) begin...
8820 01:00:13.203663 ==
8821 01:00:13.207133 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 01:00:13.210051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 01:00:13.210548 ==
8824 01:00:13.213320 Write leveling (Byte 0): 27 => 27
8825 01:00:13.216418 Write leveling (Byte 1): 27 => 27
8826 01:00:13.219928 DramcWriteLeveling(PI) end<-----
8827 01:00:13.220416
8828 01:00:13.220894 ==
8829 01:00:13.223994 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 01:00:13.226535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 01:00:13.227029 ==
8832 01:00:13.229682 [Gating] SW mode calibration
8833 01:00:13.236653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8834 01:00:13.243477 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8835 01:00:13.246224 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 01:00:13.253522 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 01:00:13.256510 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8838 01:00:13.259656 1 4 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8839 01:00:13.266591 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 01:00:13.269422 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 01:00:13.272922 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 01:00:13.279642 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 01:00:13.283021 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 01:00:13.286215 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 01:00:13.293062 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 1) (1 0)
8846 01:00:13.295937 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 1)
8847 01:00:13.299360 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8848 01:00:13.305969 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 01:00:13.309295 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 01:00:13.313055 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 01:00:13.316176 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 01:00:13.322609 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 01:00:13.326227 1 6 8 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8854 01:00:13.328965 1 6 12 | B1->B0 | 4646 3737 | 0 0 | (0 0) (0 0)
8855 01:00:13.335905 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 01:00:13.339476 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 01:00:13.342302 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 01:00:13.349315 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 01:00:13.352607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 01:00:13.355833 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 01:00:13.362524 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8862 01:00:13.365869 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8863 01:00:13.368929 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 01:00:13.376018 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 01:00:13.379174 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 01:00:13.382444 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 01:00:13.388952 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 01:00:13.392647 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 01:00:13.395874 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 01:00:13.402458 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 01:00:13.405614 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 01:00:13.408713 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 01:00:13.415393 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 01:00:13.418612 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 01:00:13.422005 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 01:00:13.428819 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 01:00:13.431997 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8878 01:00:13.435084 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 01:00:13.438988 Total UI for P1: 0, mck2ui 16
8880 01:00:13.441696 best dqsien dly found for B0: ( 1, 9, 8)
8881 01:00:13.445428 Total UI for P1: 0, mck2ui 16
8882 01:00:13.448436 best dqsien dly found for B1: ( 1, 9, 8)
8883 01:00:13.452095 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8884 01:00:13.455244 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8885 01:00:13.455811
8886 01:00:13.458332 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8887 01:00:13.465193 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8888 01:00:13.465771 [Gating] SW calibration Done
8889 01:00:13.466208 ==
8890 01:00:13.468766 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 01:00:13.475376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 01:00:13.475940 ==
8893 01:00:13.476317 RX Vref Scan: 0
8894 01:00:13.476665
8895 01:00:13.478161 RX Vref 0 -> 0, step: 1
8896 01:00:13.478642
8897 01:00:13.481847 RX Delay 0 -> 252, step: 8
8898 01:00:13.484969 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8899 01:00:13.488559 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8900 01:00:13.492005 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8901 01:00:13.495050 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8902 01:00:13.501673 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8903 01:00:13.504927 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8904 01:00:13.508416 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8905 01:00:13.511428 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8906 01:00:13.514949 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8907 01:00:13.521745 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8908 01:00:13.525015 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8909 01:00:13.528415 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8910 01:00:13.531839 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8911 01:00:13.538135 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8912 01:00:13.541482 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8913 01:00:13.545257 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8914 01:00:13.545730 ==
8915 01:00:13.548047 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 01:00:13.551969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 01:00:13.552588 ==
8918 01:00:13.554711 DQS Delay:
8919 01:00:13.555183 DQS0 = 0, DQS1 = 0
8920 01:00:13.558409 DQM Delay:
8921 01:00:13.558993 DQM0 = 136, DQM1 = 131
8922 01:00:13.559376 DQ Delay:
8923 01:00:13.562086 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8924 01:00:13.565137 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8925 01:00:13.571323 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =127
8926 01:00:13.574787 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8927 01:00:13.575261
8928 01:00:13.575652
8929 01:00:13.576014 ==
8930 01:00:13.578091 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 01:00:13.582028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 01:00:13.582605 ==
8933 01:00:13.582981
8934 01:00:13.583328
8935 01:00:13.584680 TX Vref Scan disable
8936 01:00:13.587910 == TX Byte 0 ==
8937 01:00:13.591131 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8938 01:00:13.594651 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8939 01:00:13.597998 == TX Byte 1 ==
8940 01:00:13.601203 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8941 01:00:13.604983 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8942 01:00:13.605565 ==
8943 01:00:13.608255 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 01:00:13.611552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 01:00:13.614627 ==
8946 01:00:13.626387
8947 01:00:13.630163 TX Vref early break, caculate TX vref
8948 01:00:13.633400 TX Vref=16, minBit 9, minWin=22, winSum=384
8949 01:00:13.636549 TX Vref=18, minBit 9, minWin=23, winSum=393
8950 01:00:13.639650 TX Vref=20, minBit 8, minWin=23, winSum=400
8951 01:00:13.642737 TX Vref=22, minBit 9, minWin=24, winSum=408
8952 01:00:13.646319 TX Vref=24, minBit 9, minWin=25, winSum=418
8953 01:00:13.652818 TX Vref=26, minBit 15, minWin=25, winSum=424
8954 01:00:13.656048 TX Vref=28, minBit 15, minWin=25, winSum=423
8955 01:00:13.659437 TX Vref=30, minBit 0, minWin=25, winSum=418
8956 01:00:13.662772 TX Vref=32, minBit 10, minWin=24, winSum=412
8957 01:00:13.666262 TX Vref=34, minBit 0, minWin=24, winSum=404
8958 01:00:13.669604 TX Vref=36, minBit 0, minWin=24, winSum=396
8959 01:00:13.675925 [TxChooseVref] Worse bit 15, Min win 25, Win sum 424, Final Vref 26
8960 01:00:13.676010
8961 01:00:13.679352 Final TX Range 0 Vref 26
8962 01:00:13.679523
8963 01:00:13.679609 ==
8964 01:00:13.682850 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 01:00:13.686059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 01:00:13.686206 ==
8967 01:00:13.689073
8968 01:00:13.689205
8969 01:00:13.689288 TX Vref Scan disable
8970 01:00:13.695811 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8971 01:00:13.696286 == TX Byte 0 ==
8972 01:00:13.699665 u2DelayCellOfst[0]=17 cells (5 PI)
8973 01:00:13.702774 u2DelayCellOfst[1]=10 cells (3 PI)
8974 01:00:13.706180 u2DelayCellOfst[2]=0 cells (0 PI)
8975 01:00:13.709315 u2DelayCellOfst[3]=6 cells (2 PI)
8976 01:00:13.712786 u2DelayCellOfst[4]=10 cells (3 PI)
8977 01:00:13.716448 u2DelayCellOfst[5]=20 cells (6 PI)
8978 01:00:13.719607 u2DelayCellOfst[6]=20 cells (6 PI)
8979 01:00:13.723112 u2DelayCellOfst[7]=6 cells (2 PI)
8980 01:00:13.725894 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8981 01:00:13.729260 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8982 01:00:13.732592 == TX Byte 1 ==
8983 01:00:13.736063 u2DelayCellOfst[8]=0 cells (0 PI)
8984 01:00:13.739460 u2DelayCellOfst[9]=3 cells (1 PI)
8985 01:00:13.742772 u2DelayCellOfst[10]=10 cells (3 PI)
8986 01:00:13.745772 u2DelayCellOfst[11]=3 cells (1 PI)
8987 01:00:13.746294 u2DelayCellOfst[12]=13 cells (4 PI)
8988 01:00:13.748920 u2DelayCellOfst[13]=17 cells (5 PI)
8989 01:00:13.752264 u2DelayCellOfst[14]=20 cells (6 PI)
8990 01:00:13.755840 u2DelayCellOfst[15]=17 cells (5 PI)
8991 01:00:13.762801 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8992 01:00:13.765934 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8993 01:00:13.766676 DramC Write-DBI on
8994 01:00:13.769071 ==
8995 01:00:13.769569 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 01:00:13.775967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 01:00:13.776436 ==
8998 01:00:13.776809
8999 01:00:13.777151
9000 01:00:13.779178 TX Vref Scan disable
9001 01:00:13.779769 == TX Byte 0 ==
9002 01:00:13.785328 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9003 01:00:13.786010 == TX Byte 1 ==
9004 01:00:13.788752 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9005 01:00:13.792373 DramC Write-DBI off
9006 01:00:13.792843
9007 01:00:13.793215 [DATLAT]
9008 01:00:13.796076 Freq=1600, CH1 RK1
9009 01:00:13.796646
9010 01:00:13.797126 DATLAT Default: 0xf
9011 01:00:13.798868 0, 0xFFFF, sum = 0
9012 01:00:13.799455 1, 0xFFFF, sum = 0
9013 01:00:13.802466 2, 0xFFFF, sum = 0
9014 01:00:13.803004 3, 0xFFFF, sum = 0
9015 01:00:13.805528 4, 0xFFFF, sum = 0
9016 01:00:13.806034 5, 0xFFFF, sum = 0
9017 01:00:13.808854 6, 0xFFFF, sum = 0
9018 01:00:13.809326 7, 0xFFFF, sum = 0
9019 01:00:13.812563 8, 0xFFFF, sum = 0
9020 01:00:13.813271 9, 0xFFFF, sum = 0
9021 01:00:13.815341 10, 0xFFFF, sum = 0
9022 01:00:13.818764 11, 0xFFFF, sum = 0
9023 01:00:13.819361 12, 0xFFFF, sum = 0
9024 01:00:13.822115 13, 0xFFFF, sum = 0
9025 01:00:13.822732 14, 0x0, sum = 1
9026 01:00:13.825118 15, 0x0, sum = 2
9027 01:00:13.825594 16, 0x0, sum = 3
9028 01:00:13.828645 17, 0x0, sum = 4
9029 01:00:13.829118 best_step = 15
9030 01:00:13.829490
9031 01:00:13.829833 ==
9032 01:00:13.832415 Dram Type= 6, Freq= 0, CH_1, rank 1
9033 01:00:13.835278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9034 01:00:13.835872 ==
9035 01:00:13.838627 RX Vref Scan: 0
9036 01:00:13.839094
9037 01:00:13.842107 RX Vref 0 -> 0, step: 1
9038 01:00:13.842576
9039 01:00:13.842945 RX Delay 19 -> 252, step: 4
9040 01:00:13.848661 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9041 01:00:13.852058 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9042 01:00:13.855624 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9043 01:00:13.859143 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9044 01:00:13.862204 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9045 01:00:13.868982 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9046 01:00:13.872588 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9047 01:00:13.875428 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9048 01:00:13.878822 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9049 01:00:13.882642 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9050 01:00:13.888728 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9051 01:00:13.892166 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9052 01:00:13.895622 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9053 01:00:13.898695 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9054 01:00:13.902001 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9055 01:00:13.908909 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9056 01:00:13.909531 ==
9057 01:00:13.912202 Dram Type= 6, Freq= 0, CH_1, rank 1
9058 01:00:13.916066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9059 01:00:13.916685 ==
9060 01:00:13.917165 DQS Delay:
9061 01:00:13.918760 DQS0 = 0, DQS1 = 0
9062 01:00:13.919231 DQM Delay:
9063 01:00:13.922186 DQM0 = 133, DQM1 = 130
9064 01:00:13.922657 DQ Delay:
9065 01:00:13.925533 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9066 01:00:13.928896 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9067 01:00:13.932335 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9068 01:00:13.935429 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9069 01:00:13.935898
9070 01:00:13.936270
9071 01:00:13.936617
9072 01:00:13.938653 [DramC_TX_OE_Calibration] TA2
9073 01:00:13.942053 Original DQ_B0 (3 6) =30, OEN = 27
9074 01:00:13.945323 Original DQ_B1 (3 6) =30, OEN = 27
9075 01:00:13.948686 24, 0x0, End_B0=24 End_B1=24
9076 01:00:13.952321 25, 0x0, End_B0=25 End_B1=25
9077 01:00:13.952801 26, 0x0, End_B0=26 End_B1=26
9078 01:00:13.955662 27, 0x0, End_B0=27 End_B1=27
9079 01:00:13.958585 28, 0x0, End_B0=28 End_B1=28
9080 01:00:13.962048 29, 0x0, End_B0=29 End_B1=29
9081 01:00:13.965292 30, 0x0, End_B0=30 End_B1=30
9082 01:00:13.965892 31, 0x4141, End_B0=30 End_B1=30
9083 01:00:13.968827 Byte0 end_step=30 best_step=27
9084 01:00:13.971757 Byte1 end_step=30 best_step=27
9085 01:00:13.975391 Byte0 TX OE(2T, 0.5T) = (3, 3)
9086 01:00:13.978560 Byte1 TX OE(2T, 0.5T) = (3, 3)
9087 01:00:13.979030
9088 01:00:13.979402
9089 01:00:13.985070 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9090 01:00:13.988375 CH1 RK1: MR19=303, MR18=1E09
9091 01:00:13.995049 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9092 01:00:13.998377 [RxdqsGatingPostProcess] freq 1600
9093 01:00:14.004991 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9094 01:00:14.008025 best DQS0 dly(2T, 0.5T) = (1, 1)
9095 01:00:14.008660 best DQS1 dly(2T, 0.5T) = (1, 1)
9096 01:00:14.011397 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9097 01:00:14.015491 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9098 01:00:14.018467 best DQS0 dly(2T, 0.5T) = (1, 1)
9099 01:00:14.021280 best DQS1 dly(2T, 0.5T) = (1, 1)
9100 01:00:14.024685 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9101 01:00:14.027951 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9102 01:00:14.031375 Pre-setting of DQS Precalculation
9103 01:00:14.034771 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9104 01:00:14.044654 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9105 01:00:14.051576 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9106 01:00:14.052002
9107 01:00:14.052339
9108 01:00:14.055048 [Calibration Summary] 3200 Mbps
9109 01:00:14.055477 CH 0, Rank 0
9110 01:00:14.058135 SW Impedance : PASS
9111 01:00:14.058562 DUTY Scan : NO K
9112 01:00:14.062222 ZQ Calibration : PASS
9113 01:00:14.065014 Jitter Meter : NO K
9114 01:00:14.065570 CBT Training : PASS
9115 01:00:14.068243 Write leveling : PASS
9116 01:00:14.071241 RX DQS gating : PASS
9117 01:00:14.071671 RX DQ/DQS(RDDQC) : PASS
9118 01:00:14.074608 TX DQ/DQS : PASS
9119 01:00:14.077912 RX DATLAT : PASS
9120 01:00:14.078412 RX DQ/DQS(Engine): PASS
9121 01:00:14.081424 TX OE : PASS
9122 01:00:14.081853 All Pass.
9123 01:00:14.082247
9124 01:00:14.084498 CH 0, Rank 1
9125 01:00:14.084922 SW Impedance : PASS
9126 01:00:14.088085 DUTY Scan : NO K
9127 01:00:14.091604 ZQ Calibration : PASS
9128 01:00:14.092139 Jitter Meter : NO K
9129 01:00:14.094491 CBT Training : PASS
9130 01:00:14.094951 Write leveling : PASS
9131 01:00:14.098006 RX DQS gating : PASS
9132 01:00:14.101161 RX DQ/DQS(RDDQC) : PASS
9133 01:00:14.101589 TX DQ/DQS : PASS
9134 01:00:14.104752 RX DATLAT : PASS
9135 01:00:14.107862 RX DQ/DQS(Engine): PASS
9136 01:00:14.108444 TX OE : PASS
9137 01:00:14.110998 All Pass.
9138 01:00:14.111427
9139 01:00:14.111764 CH 1, Rank 0
9140 01:00:14.114329 SW Impedance : PASS
9141 01:00:14.114762 DUTY Scan : NO K
9142 01:00:14.117881 ZQ Calibration : PASS
9143 01:00:14.121434 Jitter Meter : NO K
9144 01:00:14.121859 CBT Training : PASS
9145 01:00:14.124760 Write leveling : PASS
9146 01:00:14.127979 RX DQS gating : PASS
9147 01:00:14.128544 RX DQ/DQS(RDDQC) : PASS
9148 01:00:14.130678 TX DQ/DQS : PASS
9149 01:00:14.134575 RX DATLAT : PASS
9150 01:00:14.135004 RX DQ/DQS(Engine): PASS
9151 01:00:14.138106 TX OE : PASS
9152 01:00:14.138532 All Pass.
9153 01:00:14.138870
9154 01:00:14.140805 CH 1, Rank 1
9155 01:00:14.141404 SW Impedance : PASS
9156 01:00:14.144056 DUTY Scan : NO K
9157 01:00:14.147591 ZQ Calibration : PASS
9158 01:00:14.148018 Jitter Meter : NO K
9159 01:00:14.151096 CBT Training : PASS
9160 01:00:14.154070 Write leveling : PASS
9161 01:00:14.154501 RX DQS gating : PASS
9162 01:00:14.157563 RX DQ/DQS(RDDQC) : PASS
9163 01:00:14.158196 TX DQ/DQS : PASS
9164 01:00:14.160438 RX DATLAT : PASS
9165 01:00:14.164008 RX DQ/DQS(Engine): PASS
9166 01:00:14.164436 TX OE : PASS
9167 01:00:14.167703 All Pass.
9168 01:00:14.168241
9169 01:00:14.168589 DramC Write-DBI on
9170 01:00:14.170530 PER_BANK_REFRESH: Hybrid Mode
9171 01:00:14.173791 TX_TRACKING: ON
9172 01:00:14.180720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9173 01:00:14.190447 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9174 01:00:14.197369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9175 01:00:14.200545 [FAST_K] Save calibration result to emmc
9176 01:00:14.204029 sync common calibartion params.
9177 01:00:14.204458 sync cbt_mode0:1, 1:1
9178 01:00:14.207546 dram_init: ddr_geometry: 2
9179 01:00:14.210439 dram_init: ddr_geometry: 2
9180 01:00:14.214304 dram_init: ddr_geometry: 2
9181 01:00:14.214840 0:dram_rank_size:100000000
9182 01:00:14.217424 1:dram_rank_size:100000000
9183 01:00:14.223471 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9184 01:00:14.223900 DFS_SHUFFLE_HW_MODE: ON
9185 01:00:14.230445 dramc_set_vcore_voltage set vcore to 725000
9186 01:00:14.230900 Read voltage for 1600, 0
9187 01:00:14.233364 Vio18 = 0
9188 01:00:14.233791 Vcore = 725000
9189 01:00:14.234164 Vdram = 0
9190 01:00:14.234482 Vddq = 0
9191 01:00:14.237123 Vmddr = 0
9192 01:00:14.237544 switch to 3200 Mbps bootup
9193 01:00:14.240550 [DramcRunTimeConfig]
9194 01:00:14.241086 PHYPLL
9195 01:00:14.243594 DPM_CONTROL_AFTERK: ON
9196 01:00:14.244018 PER_BANK_REFRESH: ON
9197 01:00:14.246923 REFRESH_OVERHEAD_REDUCTION: ON
9198 01:00:14.250264 CMD_PICG_NEW_MODE: OFF
9199 01:00:14.250974 XRTWTW_NEW_MODE: ON
9200 01:00:14.253260 XRTRTR_NEW_MODE: ON
9201 01:00:14.253686 TX_TRACKING: ON
9202 01:00:14.256614 RDSEL_TRACKING: OFF
9203 01:00:14.260009 DQS Precalculation for DVFS: ON
9204 01:00:14.260437 RX_TRACKING: OFF
9205 01:00:14.263491 HW_GATING DBG: ON
9206 01:00:14.263918 ZQCS_ENABLE_LP4: ON
9207 01:00:14.266500 RX_PICG_NEW_MODE: ON
9208 01:00:14.269722 TX_PICG_NEW_MODE: ON
9209 01:00:14.270312 ENABLE_RX_DCM_DPHY: ON
9210 01:00:14.273427 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9211 01:00:14.276729 DUMMY_READ_FOR_TRACKING: OFF
9212 01:00:14.280046 !!! SPM_CONTROL_AFTERK: OFF
9213 01:00:14.280509 !!! SPM could not control APHY
9214 01:00:14.283268 IMPEDANCE_TRACKING: ON
9215 01:00:14.283719 TEMP_SENSOR: ON
9216 01:00:14.286685 HW_SAVE_FOR_SR: OFF
9217 01:00:14.290066 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9218 01:00:14.293350 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9219 01:00:14.297090 Read ODT Tracking: ON
9220 01:00:14.297516 Refresh Rate DeBounce: ON
9221 01:00:14.300048 DFS_NO_QUEUE_FLUSH: ON
9222 01:00:14.303173 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9223 01:00:14.306779 ENABLE_DFS_RUNTIME_MRW: OFF
9224 01:00:14.307298 DDR_RESERVE_NEW_MODE: ON
9225 01:00:14.309862 MR_CBT_SWITCH_FREQ: ON
9226 01:00:14.313398 =========================
9227 01:00:14.330525 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9228 01:00:14.333691 dram_init: ddr_geometry: 2
9229 01:00:14.352410 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9230 01:00:14.355653 dram_init: dram init end (result: 0)
9231 01:00:14.362223 DRAM-K: Full calibration passed in 24538 msecs
9232 01:00:14.365387 MRC: failed to locate region type 0.
9233 01:00:14.365472 DRAM rank0 size:0x100000000,
9234 01:00:14.368849 DRAM rank1 size=0x100000000
9235 01:00:14.379668 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9236 01:00:14.385992 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9237 01:00:14.392537 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9238 01:00:14.399296 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9239 01:00:14.402826 DRAM rank0 size:0x100000000,
9240 01:00:14.405997 DRAM rank1 size=0x100000000
9241 01:00:14.406419 CBMEM:
9242 01:00:14.409272 IMD: root @ 0xfffff000 254 entries.
9243 01:00:14.412648 IMD: root @ 0xffffec00 62 entries.
9244 01:00:14.416132 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9245 01:00:14.419179 WARNING: RO_VPD is uninitialized or empty.
9246 01:00:14.425696 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9247 01:00:14.432405 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9248 01:00:14.445436 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9249 01:00:14.456796 BS: romstage times (exec / console): total (unknown) / 24029 ms
9250 01:00:14.457410
9251 01:00:14.457788
9252 01:00:14.466866 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9253 01:00:14.469809 ARM64: Exception handlers installed.
9254 01:00:14.473435 ARM64: Testing exception
9255 01:00:14.476971 ARM64: Done test exception
9256 01:00:14.477538 Enumerating buses...
9257 01:00:14.480126 Show all devs... Before device enumeration.
9258 01:00:14.483579 Root Device: enabled 1
9259 01:00:14.486847 CPU_CLUSTER: 0: enabled 1
9260 01:00:14.487317 CPU: 00: enabled 1
9261 01:00:14.489971 Compare with tree...
9262 01:00:14.490461 Root Device: enabled 1
9263 01:00:14.493308 CPU_CLUSTER: 0: enabled 1
9264 01:00:14.496481 CPU: 00: enabled 1
9265 01:00:14.496950 Root Device scanning...
9266 01:00:14.499831 scan_static_bus for Root Device
9267 01:00:14.503001 CPU_CLUSTER: 0 enabled
9268 01:00:14.506330 scan_static_bus for Root Device done
9269 01:00:14.509866 scan_bus: bus Root Device finished in 8 msecs
9270 01:00:14.510404 done
9271 01:00:14.517021 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9272 01:00:14.519821 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9273 01:00:14.526566 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9274 01:00:14.529755 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9275 01:00:14.532953 Allocating resources...
9276 01:00:14.536308 Reading resources...
9277 01:00:14.540047 Root Device read_resources bus 0 link: 0
9278 01:00:14.540522 DRAM rank0 size:0x100000000,
9279 01:00:14.543057 DRAM rank1 size=0x100000000
9280 01:00:14.546453 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9281 01:00:14.549612 CPU: 00 missing read_resources
9282 01:00:14.553557 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9283 01:00:14.559890 Root Device read_resources bus 0 link: 0 done
9284 01:00:14.560477 Done reading resources.
9285 01:00:14.566840 Show resources in subtree (Root Device)...After reading.
9286 01:00:14.569843 Root Device child on link 0 CPU_CLUSTER: 0
9287 01:00:14.573172 CPU_CLUSTER: 0 child on link 0 CPU: 00
9288 01:00:14.582803 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9289 01:00:14.583426 CPU: 00
9290 01:00:14.586126 Root Device assign_resources, bus 0 link: 0
9291 01:00:14.589523 CPU_CLUSTER: 0 missing set_resources
9292 01:00:14.595974 Root Device assign_resources, bus 0 link: 0 done
9293 01:00:14.596450 Done setting resources.
9294 01:00:14.602500 Show resources in subtree (Root Device)...After assigning values.
9295 01:00:14.605903 Root Device child on link 0 CPU_CLUSTER: 0
9296 01:00:14.609471 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 01:00:14.619560 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 01:00:14.620182 CPU: 00
9299 01:00:14.622523 Done allocating resources.
9300 01:00:14.626279 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9301 01:00:14.629792 Enabling resources...
9302 01:00:14.630415 done.
9303 01:00:14.635656 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9304 01:00:14.636294 Initializing devices...
9305 01:00:14.639129 Root Device init
9306 01:00:14.639674 init hardware done!
9307 01:00:14.642386 0x00000018: ctrlr->caps
9308 01:00:14.646080 52.000 MHz: ctrlr->f_max
9309 01:00:14.646774 0.400 MHz: ctrlr->f_min
9310 01:00:14.649159 0x40ff8080: ctrlr->voltages
9311 01:00:14.649636 sclk: 390625
9312 01:00:14.652370 Bus Width = 1
9313 01:00:14.653002 sclk: 390625
9314 01:00:14.655495 Bus Width = 1
9315 01:00:14.656010 Early init status = 3
9316 01:00:14.662156 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9317 01:00:14.665480 in-header: 03 fc 00 00 01 00 00 00
9318 01:00:14.665973 in-data: 00
9319 01:00:14.672132 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9320 01:00:14.675638 in-header: 03 fd 00 00 00 00 00 00
9321 01:00:14.678795 in-data:
9322 01:00:14.682238 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9323 01:00:14.685304 in-header: 03 fc 00 00 01 00 00 00
9324 01:00:14.688586 in-data: 00
9325 01:00:14.692100 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9326 01:00:14.696850 in-header: 03 fd 00 00 00 00 00 00
9327 01:00:14.700161 in-data:
9328 01:00:14.703494 [SSUSB] Setting up USB HOST controller...
9329 01:00:14.706808 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9330 01:00:14.710461 [SSUSB] phy power-on done.
9331 01:00:14.713428 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9332 01:00:14.720202 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9333 01:00:14.723081 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9334 01:00:14.729876 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9335 01:00:14.736673 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9336 01:00:14.743254 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9337 01:00:14.750196 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9338 01:00:14.756416 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9339 01:00:14.759800 SPM: binary array size = 0x9dc
9340 01:00:14.763081 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9341 01:00:14.769850 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9342 01:00:14.776183 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9343 01:00:14.780052 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9344 01:00:14.786382 configure_display: Starting display init
9345 01:00:14.820504 anx7625_power_on_init: Init interface.
9346 01:00:14.823337 anx7625_disable_pd_protocol: Disabled PD feature.
9347 01:00:14.826311 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9348 01:00:14.854502 anx7625_start_dp_work: Secure OCM version=00
9349 01:00:14.857786 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9350 01:00:14.871996 sp_tx_get_edid_block: EDID Block = 1
9351 01:00:14.975111 Extracted contents:
9352 01:00:14.978292 header: 00 ff ff ff ff ff ff 00
9353 01:00:14.981886 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9354 01:00:14.985255 version: 01 04
9355 01:00:14.988405 basic params: 95 1f 11 78 0a
9356 01:00:14.991231 chroma info: 76 90 94 55 54 90 27 21 50 54
9357 01:00:14.994863 established: 00 00 00
9358 01:00:15.001220 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9359 01:00:15.004832 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9360 01:00:15.011319 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9361 01:00:15.018057 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9362 01:00:15.024400 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9363 01:00:15.027632 extensions: 00
9364 01:00:15.028094 checksum: fb
9365 01:00:15.028455
9366 01:00:15.031080 Manufacturer: IVO Model 57d Serial Number 0
9367 01:00:15.034533 Made week 0 of 2020
9368 01:00:15.034989 EDID version: 1.4
9369 01:00:15.037819 Digital display
9370 01:00:15.041047 6 bits per primary color channel
9371 01:00:15.041714 DisplayPort interface
9372 01:00:15.044677 Maximum image size: 31 cm x 17 cm
9373 01:00:15.047738 Gamma: 220%
9374 01:00:15.048269 Check DPMS levels
9375 01:00:15.051208 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9376 01:00:15.057736 First detailed timing is preferred timing
9377 01:00:15.058223 Established timings supported:
9378 01:00:15.060869 Standard timings supported:
9379 01:00:15.064007 Detailed timings
9380 01:00:15.067838 Hex of detail: 383680a07038204018303c0035ae10000019
9381 01:00:15.074189 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9382 01:00:15.077554 0780 0798 07c8 0820 hborder 0
9383 01:00:15.080649 0438 043b 0447 0458 vborder 0
9384 01:00:15.083916 -hsync -vsync
9385 01:00:15.084373 Did detailed timing
9386 01:00:15.090809 Hex of detail: 000000000000000000000000000000000000
9387 01:00:15.094163 Manufacturer-specified data, tag 0
9388 01:00:15.097590 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9389 01:00:15.100863 ASCII string: InfoVision
9390 01:00:15.104081 Hex of detail: 000000fe00523134304e574635205248200a
9391 01:00:15.107792 ASCII string: R140NWF5 RH
9392 01:00:15.108352 Checksum
9393 01:00:15.110944 Checksum: 0xfb (valid)
9394 01:00:15.114171 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9395 01:00:15.117314 DSI data_rate: 832800000 bps
9396 01:00:15.123894 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9397 01:00:15.127628 anx7625_parse_edid: pixelclock(138800).
9398 01:00:15.130135 hactive(1920), hsync(48), hfp(24), hbp(88)
9399 01:00:15.133879 vactive(1080), vsync(12), vfp(3), vbp(17)
9400 01:00:15.136917 anx7625_dsi_config: config dsi.
9401 01:00:15.143314 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9402 01:00:15.156984 anx7625_dsi_config: success to config DSI
9403 01:00:15.159969 anx7625_dp_start: MIPI phy setup OK.
9404 01:00:15.162945 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9405 01:00:15.166776 mtk_ddp_mode_set invalid vrefresh 60
9406 01:00:15.169464 main_disp_path_setup
9407 01:00:15.169545 ovl_layer_smi_id_en
9408 01:00:15.172950 ovl_layer_smi_id_en
9409 01:00:15.173033 ccorr_config
9410 01:00:15.173098 aal_config
9411 01:00:15.176320 gamma_config
9412 01:00:15.176402 postmask_config
9413 01:00:15.179646 dither_config
9414 01:00:15.183315 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9415 01:00:15.189386 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9416 01:00:15.192805 Root Device init finished in 551 msecs
9417 01:00:15.195828 CPU_CLUSTER: 0 init
9418 01:00:15.202960 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9419 01:00:15.209315 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9420 01:00:15.209411 APU_MBOX 0x190000b0 = 0x10001
9421 01:00:15.212768 APU_MBOX 0x190001b0 = 0x10001
9422 01:00:15.216000 APU_MBOX 0x190005b0 = 0x10001
9423 01:00:15.219303 APU_MBOX 0x190006b0 = 0x10001
9424 01:00:15.225791 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9425 01:00:15.236096 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9426 01:00:15.248333 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9427 01:00:15.255117 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9428 01:00:15.266535 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9429 01:00:15.275875 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9430 01:00:15.278893 CPU_CLUSTER: 0 init finished in 81 msecs
9431 01:00:15.281872 Devices initialized
9432 01:00:15.285393 Show all devs... After init.
9433 01:00:15.285512 Root Device: enabled 1
9434 01:00:15.288668 CPU_CLUSTER: 0: enabled 1
9435 01:00:15.291931 CPU: 00: enabled 1
9436 01:00:15.295271 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9437 01:00:15.298440 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9438 01:00:15.302099 ELOG: NV offset 0x57f000 size 0x1000
9439 01:00:15.308398 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9440 01:00:15.315298 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9441 01:00:15.318455 ELOG: Event(17) added with size 13 at 2024-01-19 00:59:35 UTC
9442 01:00:15.321873 out: cmd=0x121: 03 db 21 01 00 00 00 00
9443 01:00:15.326004 in-header: 03 0c 00 00 2c 00 00 00
9444 01:00:15.339685 in-data: 53 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9445 01:00:15.346145 ELOG: Event(A1) added with size 10 at 2024-01-19 00:59:35 UTC
9446 01:00:15.352702 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9447 01:00:15.359249 ELOG: Event(A0) added with size 9 at 2024-01-19 00:59:35 UTC
9448 01:00:15.362431 elog_add_boot_reason: Logged dev mode boot
9449 01:00:15.366289 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9450 01:00:15.369345 Finalize devices...
9451 01:00:15.369430 Devices finalized
9452 01:00:15.375947 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9453 01:00:15.379317 Writing coreboot table at 0xffe64000
9454 01:00:15.382353 0. 000000000010a000-0000000000113fff: RAMSTAGE
9455 01:00:15.385873 1. 0000000040000000-00000000400fffff: RAM
9456 01:00:15.389008 2. 0000000040100000-000000004032afff: RAMSTAGE
9457 01:00:15.395752 3. 000000004032b000-00000000545fffff: RAM
9458 01:00:15.399124 4. 0000000054600000-000000005465ffff: BL31
9459 01:00:15.402164 5. 0000000054660000-00000000ffe63fff: RAM
9460 01:00:15.408899 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9461 01:00:15.412426 7. 0000000100000000-000000023fffffff: RAM
9462 01:00:15.412502 Passing 5 GPIOs to payload:
9463 01:00:15.419048 NAME | PORT | POLARITY | VALUE
9464 01:00:15.422425 EC in RW | 0x000000aa | low | undefined
9465 01:00:15.428733 EC interrupt | 0x00000005 | low | undefined
9466 01:00:15.432184 TPM interrupt | 0x000000ab | high | undefined
9467 01:00:15.435645 SD card detect | 0x00000011 | high | undefined
9468 01:00:15.442026 speaker enable | 0x00000093 | high | undefined
9469 01:00:15.445582 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9470 01:00:15.448968 in-header: 03 f9 00 00 02 00 00 00
9471 01:00:15.449053 in-data: 02 00
9472 01:00:15.452369 ADC[4]: Raw value=901770 ID=7
9473 01:00:15.455532 ADC[3]: Raw value=213179 ID=1
9474 01:00:15.455611 RAM Code: 0x71
9475 01:00:15.458922 ADC[6]: Raw value=74502 ID=0
9476 01:00:15.462171 ADC[5]: Raw value=212072 ID=1
9477 01:00:15.462243 SKU Code: 0x1
9478 01:00:15.468835 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bcf0
9479 01:00:15.472056 coreboot table: 964 bytes.
9480 01:00:15.475368 IMD ROOT 0. 0xfffff000 0x00001000
9481 01:00:15.478843 IMD SMALL 1. 0xffffe000 0x00001000
9482 01:00:15.481925 RO MCACHE 2. 0xffffc000 0x00001104
9483 01:00:15.485329 CONSOLE 3. 0xfff7c000 0x00080000
9484 01:00:15.488715 FMAP 4. 0xfff7b000 0x00000452
9485 01:00:15.492306 TIME STAMP 5. 0xfff7a000 0x00000910
9486 01:00:15.495568 VBOOT WORK 6. 0xfff66000 0x00014000
9487 01:00:15.498578 RAMOOPS 7. 0xffe66000 0x00100000
9488 01:00:15.501969 COREBOOT 8. 0xffe64000 0x00002000
9489 01:00:15.502053 IMD small region:
9490 01:00:15.505093 IMD ROOT 0. 0xffffec00 0x00000400
9491 01:00:15.508364 VPD 1. 0xffffeb80 0x0000006c
9492 01:00:15.511813 MMC STATUS 2. 0xffffeb60 0x00000004
9493 01:00:15.518674 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9494 01:00:15.522468 Probing TPM: done!
9495 01:00:15.525551 Connected to device vid:did:rid of 1ae0:0028:00
9496 01:00:15.535557 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9497 01:00:15.538903 Initialized TPM device CR50 revision 0
9498 01:00:15.542217 Checking cr50 for pending updates
9499 01:00:15.545617 Reading cr50 TPM mode
9500 01:00:15.554214 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9501 01:00:15.561000 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9502 01:00:15.600995 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9503 01:00:15.603980 Checking segment from ROM address 0x40100000
9504 01:00:15.607474 Checking segment from ROM address 0x4010001c
9505 01:00:15.614135 Loading segment from ROM address 0x40100000
9506 01:00:15.614219 code (compression=0)
9507 01:00:15.624276 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9508 01:00:15.630777 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9509 01:00:15.630863 it's not compressed!
9510 01:00:15.637599 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9511 01:00:15.640822 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9512 01:00:15.661389 Loading segment from ROM address 0x4010001c
9513 01:00:15.661474 Entry Point 0x80000000
9514 01:00:15.664572 Loaded segments
9515 01:00:15.668105 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9516 01:00:15.674439 Jumping to boot code at 0x80000000(0xffe64000)
9517 01:00:15.681226 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9518 01:00:15.687793 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9519 01:00:15.696009 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9520 01:00:15.699297 Checking segment from ROM address 0x40100000
9521 01:00:15.702628 Checking segment from ROM address 0x4010001c
9522 01:00:15.709041 Loading segment from ROM address 0x40100000
9523 01:00:15.709128 code (compression=1)
9524 01:00:15.716064 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9525 01:00:15.725550 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9526 01:00:15.725638 using LZMA
9527 01:00:15.733997 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9528 01:00:15.740486 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9529 01:00:15.744060 Loading segment from ROM address 0x4010001c
9530 01:00:15.744144 Entry Point 0x54601000
9531 01:00:15.747234 Loaded segments
9532 01:00:15.750640 NOTICE: MT8192 bl31_setup
9533 01:00:15.757459 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9534 01:00:15.761027 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9535 01:00:15.764192 WARNING: region 0:
9536 01:00:15.767693 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9537 01:00:15.767778 WARNING: region 1:
9538 01:00:15.774131 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9539 01:00:15.777430 WARNING: region 2:
9540 01:00:15.781085 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9541 01:00:15.783984 WARNING: region 3:
9542 01:00:15.787462 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 01:00:15.790740 WARNING: region 4:
9544 01:00:15.797586 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 01:00:15.797693 WARNING: region 5:
9546 01:00:15.801127 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 01:00:15.804169 WARNING: region 6:
9548 01:00:15.807559 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 01:00:15.810682 WARNING: region 7:
9550 01:00:15.814209 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 01:00:15.820909 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9552 01:00:15.824135 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9553 01:00:15.827518 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9554 01:00:15.834061 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9555 01:00:15.837855 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9556 01:00:15.840779 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9557 01:00:15.847546 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9558 01:00:15.851020 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9559 01:00:15.854366 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9560 01:00:15.861136 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9561 01:00:15.864463 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9562 01:00:15.871146 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9563 01:00:15.874311 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9564 01:00:15.877691 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9565 01:00:15.884850 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9566 01:00:15.887650 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9567 01:00:15.891119 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9568 01:00:15.897877 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9569 01:00:15.901182 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9570 01:00:15.904462 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9571 01:00:15.911178 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9572 01:00:15.914635 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9573 01:00:15.921145 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9574 01:00:15.924706 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9575 01:00:15.927771 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9576 01:00:15.934621 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9577 01:00:15.937968 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9578 01:00:15.945091 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9579 01:00:15.948365 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9580 01:00:15.951697 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9581 01:00:15.957886 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9582 01:00:15.961515 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9583 01:00:15.964373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9584 01:00:15.971243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9585 01:00:15.974783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9586 01:00:15.978365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9587 01:00:15.981622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9588 01:00:15.988070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9589 01:00:15.991396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9590 01:00:15.994796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9591 01:00:15.998326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9592 01:00:16.004833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9593 01:00:16.007898 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9594 01:00:16.011278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9595 01:00:16.014688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9596 01:00:16.021657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9597 01:00:16.025153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9598 01:00:16.028298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9599 01:00:16.035172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9600 01:00:16.038676 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9601 01:00:16.042009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9602 01:00:16.048665 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9603 01:00:16.051940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9604 01:00:16.058353 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9605 01:00:16.061987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9606 01:00:16.068562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9607 01:00:16.071754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9608 01:00:16.075191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9609 01:00:16.081895 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9610 01:00:16.085278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9611 01:00:16.091876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9612 01:00:16.095360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9613 01:00:16.101983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9614 01:00:16.105239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9615 01:00:16.108414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9616 01:00:16.115448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9617 01:00:16.118650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9618 01:00:16.125695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9619 01:00:16.128871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9620 01:00:16.134804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9621 01:00:16.138258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9622 01:00:16.141463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9623 01:00:16.148292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9624 01:00:16.151575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9625 01:00:16.158128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9626 01:00:16.161792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9627 01:00:16.168441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9628 01:00:16.171480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9629 01:00:16.175195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9630 01:00:16.181457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9631 01:00:16.184781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9632 01:00:16.191801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9633 01:00:16.194952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9634 01:00:16.201709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9635 01:00:16.205062 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9636 01:00:16.208562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9637 01:00:16.215680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9638 01:00:16.218521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9639 01:00:16.225497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9640 01:00:16.228725 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9641 01:00:16.231653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9642 01:00:16.238465 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9643 01:00:16.241606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9644 01:00:16.248513 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9645 01:00:16.251863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9646 01:00:16.258349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9647 01:00:16.261876 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9648 01:00:16.265124 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9649 01:00:16.268553 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9650 01:00:16.275058 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9651 01:00:16.278569 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9652 01:00:16.281996 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9653 01:00:16.288563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9654 01:00:16.291880 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9655 01:00:16.298673 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9656 01:00:16.301796 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9657 01:00:16.305186 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9658 01:00:16.312235 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9659 01:00:16.315362 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9660 01:00:16.322220 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9661 01:00:16.325598 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9662 01:00:16.328858 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9663 01:00:16.335578 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9664 01:00:16.339379 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9665 01:00:16.342202 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9666 01:00:16.349187 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9667 01:00:16.352500 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9668 01:00:16.355782 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9669 01:00:16.362638 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9670 01:00:16.365886 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9671 01:00:16.369797 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9672 01:00:16.372686 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9673 01:00:16.375890 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9674 01:00:16.382678 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9675 01:00:16.386571 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9676 01:00:16.392924 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9677 01:00:16.396106 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9678 01:00:16.399570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9679 01:00:16.406000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9680 01:00:16.409578 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9681 01:00:16.412600 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9682 01:00:16.420044 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9683 01:00:16.422635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9684 01:00:16.429672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9685 01:00:16.432995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9686 01:00:16.436388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9687 01:00:16.443081 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9688 01:00:16.446209 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9689 01:00:16.452809 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9690 01:00:16.456289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9691 01:00:16.459543 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9692 01:00:16.465956 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9693 01:00:16.469222 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9694 01:00:16.472942 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9695 01:00:16.479348 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9696 01:00:16.482879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9697 01:00:16.489542 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9698 01:00:16.492692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9699 01:00:16.495948 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9700 01:00:16.502600 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9701 01:00:16.506078 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9702 01:00:16.509403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9703 01:00:16.516248 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9704 01:00:16.519217 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9705 01:00:16.525793 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9706 01:00:16.529159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9707 01:00:16.532777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9708 01:00:16.539404 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9709 01:00:16.543161 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9710 01:00:16.549291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9711 01:00:16.552766 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9712 01:00:16.556145 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9713 01:00:16.562503 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9714 01:00:16.566165 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9715 01:00:16.572487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9716 01:00:16.576074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9717 01:00:16.579408 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9718 01:00:16.586243 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9719 01:00:16.589100 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9720 01:00:16.595845 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9721 01:00:16.599317 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9722 01:00:16.602806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9723 01:00:16.609200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9724 01:00:16.612512 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9725 01:00:16.615878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9726 01:00:16.622464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9727 01:00:16.625624 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9728 01:00:16.632543 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9729 01:00:16.635715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9730 01:00:16.639165 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9731 01:00:16.645489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9732 01:00:16.649219 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9733 01:00:16.655783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9734 01:00:16.659044 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9735 01:00:16.662494 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9736 01:00:16.669099 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9737 01:00:16.672245 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9738 01:00:16.675828 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9739 01:00:16.682617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9740 01:00:16.686203 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9741 01:00:16.692873 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9742 01:00:16.695905 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9743 01:00:16.702878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9744 01:00:16.706043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9745 01:00:16.709219 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9746 01:00:16.716168 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9747 01:00:16.719654 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9748 01:00:16.726380 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9749 01:00:16.729626 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9750 01:00:16.732906 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9751 01:00:16.739215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9752 01:00:16.743137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9753 01:00:16.749227 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9754 01:00:16.752601 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9755 01:00:16.759672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9756 01:00:16.762656 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9757 01:00:16.765818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9758 01:00:16.772497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9759 01:00:16.776151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9760 01:00:16.782570 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9761 01:00:16.786295 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9762 01:00:16.789294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9763 01:00:16.795844 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9764 01:00:16.799361 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9765 01:00:16.805902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9766 01:00:16.809000 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9767 01:00:16.812450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9768 01:00:16.819855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9769 01:00:16.822312 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9770 01:00:16.829100 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9771 01:00:16.832369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9772 01:00:16.838444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9773 01:00:16.842045 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9774 01:00:16.845149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9775 01:00:16.851752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9776 01:00:16.855495 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9777 01:00:16.861959 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9778 01:00:16.865726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9779 01:00:16.869006 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9780 01:00:16.875194 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9781 01:00:16.878971 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9782 01:00:16.882392 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9783 01:00:16.885216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9784 01:00:16.892436 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9785 01:00:16.895736 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9786 01:00:16.898958 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9787 01:00:16.905426 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9788 01:00:16.908693 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9789 01:00:16.912742 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9790 01:00:16.918756 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9791 01:00:16.922410 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9792 01:00:16.928892 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9793 01:00:16.932603 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9794 01:00:16.935342 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9795 01:00:16.942153 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9796 01:00:16.944978 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9797 01:00:16.948390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9798 01:00:16.955088 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9799 01:00:16.958515 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9800 01:00:16.961825 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9801 01:00:16.968460 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9802 01:00:16.972111 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9803 01:00:16.978652 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9804 01:00:16.981956 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9805 01:00:16.985652 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9806 01:00:16.991886 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9807 01:00:16.994994 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9808 01:00:16.998311 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9809 01:00:17.004902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9810 01:00:17.008621 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9811 01:00:17.011728 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9812 01:00:17.018529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9813 01:00:17.021680 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9814 01:00:17.025016 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9815 01:00:17.031766 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9816 01:00:17.035122 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9817 01:00:17.041777 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9818 01:00:17.045317 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9819 01:00:17.048504 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9820 01:00:17.051695 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9821 01:00:17.058328 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9822 01:00:17.061906 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9823 01:00:17.064837 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9824 01:00:17.068100 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9825 01:00:17.075468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9826 01:00:17.078347 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9827 01:00:17.081469 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9828 01:00:17.084806 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9829 01:00:17.091602 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9830 01:00:17.094932 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9831 01:00:17.098063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9832 01:00:17.105187 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9833 01:00:17.108056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9834 01:00:17.111499 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9835 01:00:17.118308 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9836 01:00:17.121146 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9837 01:00:17.128123 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9838 01:00:17.131433 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9839 01:00:17.134362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9840 01:00:17.140908 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9841 01:00:17.144661 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9842 01:00:17.151375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9843 01:00:17.154658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9844 01:00:17.157824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9845 01:00:17.164563 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9846 01:00:17.167893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9847 01:00:17.174513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9848 01:00:17.177604 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9849 01:00:17.180824 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9850 01:00:17.187787 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9851 01:00:17.190899 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9852 01:00:17.197441 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9853 01:00:17.201182 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9854 01:00:17.207363 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9855 01:00:17.210558 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9856 01:00:17.213825 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9857 01:00:17.220771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9858 01:00:17.223743 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9859 01:00:17.230376 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9860 01:00:17.233666 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9861 01:00:17.237325 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9862 01:00:17.243931 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9863 01:00:17.246892 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9864 01:00:17.253764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9865 01:00:17.256929 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9866 01:00:17.260447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9867 01:00:17.266859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9868 01:00:17.270718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9869 01:00:17.276750 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9870 01:00:17.279916 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9871 01:00:17.286569 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9872 01:00:17.289771 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9873 01:00:17.293114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9874 01:00:17.300227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9875 01:00:17.303537 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9876 01:00:17.309841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9877 01:00:17.313275 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9878 01:00:17.320417 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9879 01:00:17.323255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9880 01:00:17.326816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9881 01:00:17.333093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9882 01:00:17.336518 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9883 01:00:17.343525 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9884 01:00:17.346307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9885 01:00:17.349920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9886 01:00:17.356224 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9887 01:00:17.359753 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9888 01:00:17.366928 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9889 01:00:17.369885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9890 01:00:17.373166 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9891 01:00:17.379702 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9892 01:00:17.383131 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9893 01:00:17.390000 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9894 01:00:17.393353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9895 01:00:17.396353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9896 01:00:17.402997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9897 01:00:17.406378 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9898 01:00:17.413154 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9899 01:00:17.416292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9900 01:00:17.419620 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9901 01:00:17.426327 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9902 01:00:17.429501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9903 01:00:17.436410 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9904 01:00:17.439227 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9905 01:00:17.445931 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9906 01:00:17.449442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9907 01:00:17.452838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9908 01:00:17.459484 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9909 01:00:17.462596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9910 01:00:17.469192 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9911 01:00:17.472625 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9912 01:00:17.479097 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9913 01:00:17.482357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9914 01:00:17.485645 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9915 01:00:17.492334 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9916 01:00:17.495848 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9917 01:00:17.502745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9918 01:00:17.505806 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9919 01:00:17.512513 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9920 01:00:17.515816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9921 01:00:17.519416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9922 01:00:17.525677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9923 01:00:17.529046 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9924 01:00:17.535511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9925 01:00:17.538831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9926 01:00:17.545767 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9927 01:00:17.548609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9928 01:00:17.556186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9929 01:00:17.558692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9930 01:00:17.562111 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9931 01:00:17.568667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9932 01:00:17.571817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9933 01:00:17.579052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9934 01:00:17.581751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9935 01:00:17.588878 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9936 01:00:17.592095 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9937 01:00:17.595382 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9938 01:00:17.601930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9939 01:00:17.605037 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9940 01:00:17.612041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9941 01:00:17.615062 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9942 01:00:17.621688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9943 01:00:17.624992 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9944 01:00:17.631575 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9945 01:00:17.634730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9946 01:00:17.638269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9947 01:00:17.644521 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9948 01:00:17.647829 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9949 01:00:17.654656 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9950 01:00:17.657788 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9951 01:00:17.664539 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9952 01:00:17.667900 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9953 01:00:17.670870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9954 01:00:17.677690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9955 01:00:17.681209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9956 01:00:17.687586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9957 01:00:17.691054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9958 01:00:17.697601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9959 01:00:17.700939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9960 01:00:17.707327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9961 01:00:17.711218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9962 01:00:17.717276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9963 01:00:17.720782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9964 01:00:17.727212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9965 01:00:17.730748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9966 01:00:17.737220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9967 01:00:17.740707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9968 01:00:17.747385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9969 01:00:17.750568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9970 01:00:17.757251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9971 01:00:17.760646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9972 01:00:17.763901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9973 01:00:17.770631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9974 01:00:17.773820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9975 01:00:17.780308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9976 01:00:17.783738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9977 01:00:17.790239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9978 01:00:17.793629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9979 01:00:17.800173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9980 01:00:17.807003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9981 01:00:17.810414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9982 01:00:17.816645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9983 01:00:17.820170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9984 01:00:17.827022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9985 01:00:17.830190 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9986 01:00:17.830301 INFO: [APUAPC] vio 0
9987 01:00:17.837384 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9988 01:00:17.840775 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9989 01:00:17.844085 INFO: [APUAPC] D0_APC_0: 0x400510
9990 01:00:17.847363 INFO: [APUAPC] D0_APC_1: 0x0
9991 01:00:17.850611 INFO: [APUAPC] D0_APC_2: 0x1540
9992 01:00:17.854219 INFO: [APUAPC] D0_APC_3: 0x0
9993 01:00:17.857377 INFO: [APUAPC] D1_APC_0: 0xffffffff
9994 01:00:17.861121 INFO: [APUAPC] D1_APC_1: 0xffffffff
9995 01:00:17.863880 INFO: [APUAPC] D1_APC_2: 0x3fffff
9996 01:00:17.867375 INFO: [APUAPC] D1_APC_3: 0x0
9997 01:00:17.870297 INFO: [APUAPC] D2_APC_0: 0xffffffff
9998 01:00:17.873656 INFO: [APUAPC] D2_APC_1: 0xffffffff
9999 01:00:17.877204 INFO: [APUAPC] D2_APC_2: 0x3fffff
10000 01:00:17.880342 INFO: [APUAPC] D2_APC_3: 0x0
10001 01:00:17.883584 INFO: [APUAPC] D3_APC_0: 0xffffffff
10002 01:00:17.886748 INFO: [APUAPC] D3_APC_1: 0xffffffff
10003 01:00:17.890246 INFO: [APUAPC] D3_APC_2: 0x3fffff
10004 01:00:17.893843 INFO: [APUAPC] D3_APC_3: 0x0
10005 01:00:17.897121 INFO: [APUAPC] D4_APC_0: 0xffffffff
10006 01:00:17.900615 INFO: [APUAPC] D4_APC_1: 0xffffffff
10007 01:00:17.904006 INFO: [APUAPC] D4_APC_2: 0x3fffff
10008 01:00:17.906928 INFO: [APUAPC] D4_APC_3: 0x0
10009 01:00:17.909981 INFO: [APUAPC] D5_APC_0: 0xffffffff
10010 01:00:17.913330 INFO: [APUAPC] D5_APC_1: 0xffffffff
10011 01:00:17.916647 INFO: [APUAPC] D5_APC_2: 0x3fffff
10012 01:00:17.916734 INFO: [APUAPC] D5_APC_3: 0x0
10013 01:00:17.923405 INFO: [APUAPC] D6_APC_0: 0xffffffff
10014 01:00:17.926520 INFO: [APUAPC] D6_APC_1: 0xffffffff
10015 01:00:17.930048 INFO: [APUAPC] D6_APC_2: 0x3fffff
10016 01:00:17.930121 INFO: [APUAPC] D6_APC_3: 0x0
10017 01:00:17.933187 INFO: [APUAPC] D7_APC_0: 0xffffffff
10018 01:00:17.939767 INFO: [APUAPC] D7_APC_1: 0xffffffff
10019 01:00:17.943077 INFO: [APUAPC] D7_APC_2: 0x3fffff
10020 01:00:17.943149 INFO: [APUAPC] D7_APC_3: 0x0
10021 01:00:17.946447 INFO: [APUAPC] D8_APC_0: 0xffffffff
10022 01:00:17.949880 INFO: [APUAPC] D8_APC_1: 0xffffffff
10023 01:00:17.953541 INFO: [APUAPC] D8_APC_2: 0x3fffff
10024 01:00:17.956300 INFO: [APUAPC] D8_APC_3: 0x0
10025 01:00:17.959624 INFO: [APUAPC] D9_APC_0: 0xffffffff
10026 01:00:17.963218 INFO: [APUAPC] D9_APC_1: 0xffffffff
10027 01:00:17.966625 INFO: [APUAPC] D9_APC_2: 0x3fffff
10028 01:00:17.969753 INFO: [APUAPC] D9_APC_3: 0x0
10029 01:00:17.973127 INFO: [APUAPC] D10_APC_0: 0xffffffff
10030 01:00:17.976488 INFO: [APUAPC] D10_APC_1: 0xffffffff
10031 01:00:17.979655 INFO: [APUAPC] D10_APC_2: 0x3fffff
10032 01:00:17.982903 INFO: [APUAPC] D10_APC_3: 0x0
10033 01:00:17.986196 INFO: [APUAPC] D11_APC_0: 0xffffffff
10034 01:00:17.989544 INFO: [APUAPC] D11_APC_1: 0xffffffff
10035 01:00:17.992806 INFO: [APUAPC] D11_APC_2: 0x3fffff
10036 01:00:17.996096 INFO: [APUAPC] D11_APC_3: 0x0
10037 01:00:17.999694 INFO: [APUAPC] D12_APC_0: 0xffffffff
10038 01:00:18.002918 INFO: [APUAPC] D12_APC_1: 0xffffffff
10039 01:00:18.006036 INFO: [APUAPC] D12_APC_2: 0x3fffff
10040 01:00:18.009704 INFO: [APUAPC] D12_APC_3: 0x0
10041 01:00:18.012650 INFO: [APUAPC] D13_APC_0: 0xffffffff
10042 01:00:18.016146 INFO: [APUAPC] D13_APC_1: 0xffffffff
10043 01:00:18.019210 INFO: [APUAPC] D13_APC_2: 0x3fffff
10044 01:00:18.022513 INFO: [APUAPC] D13_APC_3: 0x0
10045 01:00:18.026087 INFO: [APUAPC] D14_APC_0: 0xffffffff
10046 01:00:18.029357 INFO: [APUAPC] D14_APC_1: 0xffffffff
10047 01:00:18.032721 INFO: [APUAPC] D14_APC_2: 0x3fffff
10048 01:00:18.036096 INFO: [APUAPC] D14_APC_3: 0x0
10049 01:00:18.039496 INFO: [APUAPC] D15_APC_0: 0xffffffff
10050 01:00:18.042662 INFO: [APUAPC] D15_APC_1: 0xffffffff
10051 01:00:18.045871 INFO: [APUAPC] D15_APC_2: 0x3fffff
10052 01:00:18.049578 INFO: [APUAPC] D15_APC_3: 0x0
10053 01:00:18.052856 INFO: [APUAPC] APC_CON: 0x4
10054 01:00:18.056284 INFO: [NOCDAPC] D0_APC_0: 0x0
10055 01:00:18.059414 INFO: [NOCDAPC] D0_APC_1: 0x0
10056 01:00:18.062584 INFO: [NOCDAPC] D1_APC_0: 0x0
10057 01:00:18.065777 INFO: [NOCDAPC] D1_APC_1: 0xfff
10058 01:00:18.069150 INFO: [NOCDAPC] D2_APC_0: 0x0
10059 01:00:18.072514 INFO: [NOCDAPC] D2_APC_1: 0xfff
10060 01:00:18.072597 INFO: [NOCDAPC] D3_APC_0: 0x0
10061 01:00:18.075990 INFO: [NOCDAPC] D3_APC_1: 0xfff
10062 01:00:18.079560 INFO: [NOCDAPC] D4_APC_0: 0x0
10063 01:00:18.082900 INFO: [NOCDAPC] D4_APC_1: 0xfff
10064 01:00:18.086173 INFO: [NOCDAPC] D5_APC_0: 0x0
10065 01:00:18.089330 INFO: [NOCDAPC] D5_APC_1: 0xfff
10066 01:00:18.092692 INFO: [NOCDAPC] D6_APC_0: 0x0
10067 01:00:18.095792 INFO: [NOCDAPC] D6_APC_1: 0xfff
10068 01:00:18.099242 INFO: [NOCDAPC] D7_APC_0: 0x0
10069 01:00:18.102742 INFO: [NOCDAPC] D7_APC_1: 0xfff
10070 01:00:18.105973 INFO: [NOCDAPC] D8_APC_0: 0x0
10071 01:00:18.106208 INFO: [NOCDAPC] D8_APC_1: 0xfff
10072 01:00:18.109052 INFO: [NOCDAPC] D9_APC_0: 0x0
10073 01:00:18.112636 INFO: [NOCDAPC] D9_APC_1: 0xfff
10074 01:00:18.116030 INFO: [NOCDAPC] D10_APC_0: 0x0
10075 01:00:18.118810 INFO: [NOCDAPC] D10_APC_1: 0xfff
10076 01:00:18.122262 INFO: [NOCDAPC] D11_APC_0: 0x0
10077 01:00:18.125485 INFO: [NOCDAPC] D11_APC_1: 0xfff
10078 01:00:18.128705 INFO: [NOCDAPC] D12_APC_0: 0x0
10079 01:00:18.132122 INFO: [NOCDAPC] D12_APC_1: 0xfff
10080 01:00:18.135508 INFO: [NOCDAPC] D13_APC_0: 0x0
10081 01:00:18.138832 INFO: [NOCDAPC] D13_APC_1: 0xfff
10082 01:00:18.142151 INFO: [NOCDAPC] D14_APC_0: 0x0
10083 01:00:18.145471 INFO: [NOCDAPC] D14_APC_1: 0xfff
10084 01:00:18.148769 INFO: [NOCDAPC] D15_APC_0: 0x0
10085 01:00:18.151950 INFO: [NOCDAPC] D15_APC_1: 0xfff
10086 01:00:18.152050 INFO: [NOCDAPC] APC_CON: 0x4
10087 01:00:18.155387 INFO: [APUAPC] set_apusys_apc done
10088 01:00:18.158564 INFO: [DEVAPC] devapc_init done
10089 01:00:18.165593 INFO: GICv3 without legacy support detected.
10090 01:00:18.168824 INFO: ARM GICv3 driver initialized in EL3
10091 01:00:18.171957 INFO: Maximum SPI INTID supported: 639
10092 01:00:18.175364 INFO: BL31: Initializing runtime services
10093 01:00:18.181981 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10094 01:00:18.185099 INFO: SPM: enable CPC mode
10095 01:00:18.188391 INFO: mcdi ready for mcusys-off-idle and system suspend
10096 01:00:18.195252 INFO: BL31: Preparing for EL3 exit to normal world
10097 01:00:18.198593 INFO: Entry point address = 0x80000000
10098 01:00:18.198684 INFO: SPSR = 0x8
10099 01:00:18.205597
10100 01:00:18.205679
10101 01:00:18.205745
10102 01:00:18.206388 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10103 01:00:18.206490 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10104 01:00:18.206573 Setting prompt string to ['asurada:']
10105 01:00:18.206654 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10106 01:00:18.209087 Starting depthcharge on Spherion...
10107 01:00:18.209170
10108 01:00:18.209236 Wipe memory regions:
10109 01:00:18.209296
10110 01:00:18.212231 [0x00000040000000, 0x00000054600000)
10111 01:00:18.334496
10112 01:00:18.334645 [0x00000054660000, 0x00000080000000)
10113 01:00:18.595169
10114 01:00:18.595329 [0x000000821a7280, 0x000000ffe64000)
10115 01:00:19.340400
10116 01:00:19.340910 [0x00000100000000, 0x00000240000000)
10117 01:00:21.230801
10118 01:00:21.234090 Initializing XHCI USB controller at 0x11200000.
10119 01:00:22.271996
10120 01:00:22.275143 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10121 01:00:22.275717
10122 01:00:22.276094
10123 01:00:22.276441
10124 01:00:22.277319 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10126 01:00:22.378915 asurada: tftpboot 192.168.201.1 12571077/tftp-deploy-9bqywlm8/kernel/image.itb 12571077/tftp-deploy-9bqywlm8/kernel/cmdline
10127 01:00:22.379601 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 01:00:22.380099 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10129 01:00:22.384409 tftpboot 192.168.201.1 12571077/tftp-deploy-9bqywlm8/kernel/image.itp-deploy-9bqywlm8/kernel/cmdline
10130 01:00:22.384886
10131 01:00:22.385255 Waiting for link
10132 01:00:22.545330
10133 01:00:22.545916 R8152: Initializing
10134 01:00:22.546358
10135 01:00:22.548879 Version 9 (ocp_data = 6010)
10136 01:00:22.549530
10137 01:00:22.551759 R8152: Done initializing
10138 01:00:22.552333
10139 01:00:22.552709 Adding net device
10140 01:00:24.493514
10141 01:00:24.494119 done.
10142 01:00:24.494523
10143 01:00:24.494871 MAC: 00:e0:4c:72:2d:d6
10144 01:00:24.495206
10145 01:00:24.496656 Sending DHCP discover... done.
10146 01:00:24.497124
10147 01:00:24.500066 Waiting for reply... done.
10148 01:00:24.500644
10149 01:00:24.503059 Sending DHCP request... done.
10150 01:00:24.503527
10151 01:00:24.506911 Waiting for reply... done.
10152 01:00:24.507379
10153 01:00:24.507747 My ip is 192.168.201.21
10154 01:00:24.508095
10155 01:00:24.510259 The DHCP server ip is 192.168.201.1
10156 01:00:24.510732
10157 01:00:24.516921 TFTP server IP predefined by user: 192.168.201.1
10158 01:00:24.517397
10159 01:00:24.523640 Bootfile predefined by user: 12571077/tftp-deploy-9bqywlm8/kernel/image.itb
10160 01:00:24.524204
10161 01:00:24.524576 Sending tftp read request... done.
10162 01:00:24.526745
10163 01:00:24.531887 Waiting for the transfer...
10164 01:00:24.532355
10165 01:00:24.841466 00000000 ################################################################
10166 01:00:24.841603
10167 01:00:25.104365 00080000 ################################################################
10168 01:00:25.104495
10169 01:00:25.348597 00100000 ################################################################
10170 01:00:25.348752
10171 01:00:25.596330 00180000 ################################################################
10172 01:00:25.596481
10173 01:00:25.841519 00200000 ################################################################
10174 01:00:25.841670
10175 01:00:26.087029 00280000 ################################################################
10176 01:00:26.087180
10177 01:00:26.332166 00300000 ################################################################
10178 01:00:26.332312
10179 01:00:26.578947 00380000 ################################################################
10180 01:00:26.579100
10181 01:00:26.825146 00400000 ################################################################
10182 01:00:26.825289
10183 01:00:27.069355 00480000 ################################################################
10184 01:00:27.069507
10185 01:00:27.314531 00500000 ################################################################
10186 01:00:27.314679
10187 01:00:27.558853 00580000 ################################################################
10188 01:00:27.559007
10189 01:00:27.802904 00600000 ################################################################
10190 01:00:27.803052
10191 01:00:28.048608 00680000 ################################################################
10192 01:00:28.048759
10193 01:00:28.294307 00700000 ################################################################
10194 01:00:28.294452
10195 01:00:28.538564 00780000 ################################################################
10196 01:00:28.538718
10197 01:00:28.784621 00800000 ################################################################
10198 01:00:28.784769
10199 01:00:29.030126 00880000 ################################################################
10200 01:00:29.030275
10201 01:00:29.275342 00900000 ################################################################
10202 01:00:29.275499
10203 01:00:29.521043 00980000 ################################################################
10204 01:00:29.521225
10205 01:00:29.766724 00a00000 ################################################################
10206 01:00:29.766904
10207 01:00:30.010360 00a80000 ################################################################
10208 01:00:30.010535
10209 01:00:30.254758 00b00000 ################################################################
10210 01:00:30.254907
10211 01:00:30.500975 00b80000 ################################################################
10212 01:00:30.501121
10213 01:00:30.744636 00c00000 ################################################################
10214 01:00:30.744821
10215 01:00:30.989087 00c80000 ################################################################
10216 01:00:30.989245
10217 01:00:31.234649 00d00000 ################################################################
10218 01:00:31.234799
10219 01:00:31.479368 00d80000 ################################################################
10220 01:00:31.479511
10221 01:00:31.724514 00e00000 ################################################################
10222 01:00:31.724664
10223 01:00:31.970184 00e80000 ################################################################
10224 01:00:31.970327
10225 01:00:32.214521 00f00000 ################################################################
10226 01:00:32.214679
10227 01:00:32.463091 00f80000 ################################################################
10228 01:00:32.463226
10229 01:00:32.719512 01000000 ################################################################
10230 01:00:32.719656
10231 01:00:32.969205 01080000 ################################################################
10232 01:00:32.969337
10233 01:00:33.218571 01100000 ################################################################
10234 01:00:33.218707
10235 01:00:33.467970 01180000 ################################################################
10236 01:00:33.468116
10237 01:00:33.718365 01200000 ################################################################
10238 01:00:33.718511
10239 01:00:33.967422 01280000 ################################################################
10240 01:00:33.967578
10241 01:00:34.216644 01300000 ################################################################
10242 01:00:34.216770
10243 01:00:34.465531 01380000 ################################################################
10244 01:00:34.465679
10245 01:00:34.714190 01400000 ################################################################
10246 01:00:34.714354
10247 01:00:34.962912 01480000 ################################################################
10248 01:00:34.963034
10249 01:00:35.212308 01500000 ################################################################
10250 01:00:35.212457
10251 01:00:35.462395 01580000 ################################################################
10252 01:00:35.462553
10253 01:00:35.711029 01600000 ################################################################
10254 01:00:35.711157
10255 01:00:35.959940 01680000 ################################################################
10256 01:00:35.960093
10257 01:00:36.209657 01700000 ################################################################
10258 01:00:36.209809
10259 01:00:36.458348 01780000 ################################################################
10260 01:00:36.458473
10261 01:00:36.707658 01800000 ################################################################
10262 01:00:36.707784
10263 01:00:36.956891 01880000 ################################################################
10264 01:00:36.957046
10265 01:00:37.205898 01900000 ################################################################
10266 01:00:37.206058
10267 01:00:37.455059 01980000 ################################################################
10268 01:00:37.455205
10269 01:00:37.704262 01a00000 ################################################################
10270 01:00:37.704400
10271 01:00:37.953527 01a80000 ################################################################
10272 01:00:37.953673
10273 01:00:38.202932 01b00000 ################################################################
10274 01:00:38.203067
10275 01:00:38.451086 01b80000 ################################################################
10276 01:00:38.451208
10277 01:00:38.727618 01c00000 ################################################################
10278 01:00:38.727748
10279 01:00:38.737305 01c80000 ### done.
10280 01:00:38.737390
10281 01:00:38.741158 The bootfile was 29903894 bytes long.
10282 01:00:38.741248
10283 01:00:38.744037 Sending tftp read request... done.
10284 01:00:38.744126
10285 01:00:38.747815 Waiting for the transfer...
10286 01:00:38.747991
10287 01:00:38.748074 00000000 # done.
10288 01:00:38.748159
10289 01:00:38.757451 Command line loaded dynamically from TFTP file: 12571077/tftp-deploy-9bqywlm8/kernel/cmdline
10290 01:00:38.757652
10291 01:00:38.777379 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10292 01:00:38.777665
10293 01:00:38.780671 Loading FIT.
10294 01:00:38.780885
10295 01:00:38.784184 Image ramdisk-1 has 17805959 bytes.
10296 01:00:38.784424
10297 01:00:38.787491 Image fdt-1 has 47278 bytes.
10298 01:00:38.787813
10299 01:00:38.788022 Image kernel-1 has 12048624 bytes.
10300 01:00:38.788205
10301 01:00:38.797665 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10302 01:00:38.798185
10303 01:00:38.814686 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10304 01:00:38.817289
10305 01:00:38.821523 Choosing best match conf-1 for compat google,spherion-rev2.
10306 01:00:38.825380
10307 01:00:38.830359 Connected to device vid:did:rid of 1ae0:0028:00
10308 01:00:38.837918
10309 01:00:38.841399 tpm_get_response: command 0x17b, return code 0x0
10310 01:00:38.841884
10311 01:00:38.844765 ec_init: CrosEC protocol v3 supported (256, 248)
10312 01:00:38.848876
10313 01:00:38.851932 tpm_cleanup: add release locality here.
10314 01:00:38.852411
10315 01:00:38.852789 Shutting down all USB controllers.
10316 01:00:38.853143
10317 01:00:38.855513 Removing current net device
10318 01:00:38.855989
10319 01:00:38.861850 Exiting depthcharge with code 4 at timestamp: 49987034
10320 01:00:38.862357
10321 01:00:38.865233 LZMA decompressing kernel-1 to 0x821a6718
10322 01:00:38.865712
10323 01:00:38.868691 LZMA decompressing kernel-1 to 0x40000000
10324 01:00:40.367235
10325 01:00:40.367810 jumping to kernel
10326 01:00:40.369527 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10327 01:00:40.370147 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10328 01:00:40.370606 Setting prompt string to ['Linux version [0-9]']
10329 01:00:40.371006 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10330 01:00:40.371410 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10331 01:00:40.449408
10332 01:00:40.452270 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10333 01:00:40.455841 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10334 01:00:40.456426 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10335 01:00:40.456924 Setting prompt string to []
10336 01:00:40.457356 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10337 01:00:40.457761 Using line separator: #'\n'#
10338 01:00:40.458143 No login prompt set.
10339 01:00:40.458588 Parsing kernel messages
10340 01:00:40.458921 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10341 01:00:40.459495 [login-action] Waiting for messages, (timeout 00:04:03)
10342 01:00:40.475033 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10343 01:00:40.478209 [ 0.000000] random: crng init done
10344 01:00:40.484826 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10345 01:00:40.488227 [ 0.000000] efi: UEFI not found.
10346 01:00:40.495053 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10347 01:00:40.501454 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10348 01:00:40.511553 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10349 01:00:40.521695 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10350 01:00:40.527983 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10351 01:00:40.534552 [ 0.000000] printk: bootconsole [mtk8250] enabled
10352 01:00:40.541468 [ 0.000000] NUMA: No NUMA configuration found
10353 01:00:40.547731 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10354 01:00:40.551024 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10355 01:00:40.554437 [ 0.000000] Zone ranges:
10356 01:00:40.560672 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10357 01:00:40.563868 [ 0.000000] DMA32 empty
10358 01:00:40.570509 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10359 01:00:40.573836 [ 0.000000] Movable zone start for each node
10360 01:00:40.576967 [ 0.000000] Early memory node ranges
10361 01:00:40.583725 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10362 01:00:40.590761 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10363 01:00:40.596979 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10364 01:00:40.603999 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10365 01:00:40.610548 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10366 01:00:40.617507 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10367 01:00:40.673329 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10368 01:00:40.679982 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10369 01:00:40.686386 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10370 01:00:40.690059 [ 0.000000] psci: probing for conduit method from DT.
10371 01:00:40.696586 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10372 01:00:40.700007 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10373 01:00:40.706263 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10374 01:00:40.709697 [ 0.000000] psci: SMC Calling Convention v1.2
10375 01:00:40.716294 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10376 01:00:40.719655 [ 0.000000] Detected VIPT I-cache on CPU0
10377 01:00:40.726113 [ 0.000000] CPU features: detected: GIC system register CPU interface
10378 01:00:40.732979 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10379 01:00:40.739674 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10380 01:00:40.746270 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10381 01:00:40.752747 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10382 01:00:40.762610 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10383 01:00:40.766218 [ 0.000000] alternatives: applying boot alternatives
10384 01:00:40.772183 [ 0.000000] Fallback order for Node 0: 0
10385 01:00:40.779239 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10386 01:00:40.782228 [ 0.000000] Policy zone: Normal
10387 01:00:40.805596 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10388 01:00:40.815914 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10389 01:00:40.826313 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10390 01:00:40.836468 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10391 01:00:40.842851 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10392 01:00:40.846058 <6>[ 0.000000] software IO TLB: area num 8.
10393 01:00:40.902743 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10394 01:00:41.051915 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10395 01:00:41.058905 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10396 01:00:41.065518 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10397 01:00:41.068588 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10398 01:00:41.074712 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10399 01:00:41.081462 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10400 01:00:41.085114 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10401 01:00:41.094629 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10402 01:00:41.101548 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10403 01:00:41.108362 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10404 01:00:41.114485 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10405 01:00:41.118199 <6>[ 0.000000] GICv3: 608 SPIs implemented
10406 01:00:41.121141 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10407 01:00:41.127859 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10408 01:00:41.131589 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10409 01:00:41.138329 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10410 01:00:41.151302 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10411 01:00:41.161302 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10412 01:00:41.170828 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10413 01:00:41.178457 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10414 01:00:41.191636 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10415 01:00:41.197995 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10416 01:00:41.204879 <6>[ 0.009236] Console: colour dummy device 80x25
10417 01:00:41.214665 <6>[ 0.013963] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10418 01:00:41.218120 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10419 01:00:41.224605 <6>[ 0.029276] LSM: Security Framework initializing
10420 01:00:41.232327 <6>[ 0.034215] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 01:00:41.241300 <6>[ 0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 01:00:41.248348 <6>[ 0.051451] cblist_init_generic: Setting adjustable number of callback queues.
10423 01:00:41.254900 <6>[ 0.058894] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 01:00:41.264890 <6>[ 0.065272] cblist_init_generic: Setting adjustable number of callback queues.
10425 01:00:41.268141 <6>[ 0.072745] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 01:00:41.274823 <6>[ 0.079145] rcu: Hierarchical SRCU implementation.
10427 01:00:41.281240 <6>[ 0.084161] rcu: Max phase no-delay instances is 1000.
10428 01:00:41.288259 <6>[ 0.091187] EFI services will not be available.
10429 01:00:41.291013 <6>[ 0.096142] smp: Bringing up secondary CPUs ...
10430 01:00:41.299123 <6>[ 0.101195] Detected VIPT I-cache on CPU1
10431 01:00:41.305825 <6>[ 0.101263] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10432 01:00:41.312297 <6>[ 0.101290] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10433 01:00:41.315217 <6>[ 0.101604] Detected VIPT I-cache on CPU2
10434 01:00:41.325729 <6>[ 0.101648] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10435 01:00:41.328981 <6>[ 0.101665] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10436 01:00:41.335607 <6>[ 0.101917] Detected VIPT I-cache on CPU3
10437 01:00:41.342144 <6>[ 0.101964] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10438 01:00:41.348971 <6>[ 0.101979] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10439 01:00:41.352111 <6>[ 0.102284] CPU features: detected: Spectre-v4
10440 01:00:41.358746 <6>[ 0.102292] CPU features: detected: Spectre-BHB
10441 01:00:41.362362 <6>[ 0.102296] Detected PIPT I-cache on CPU4
10442 01:00:41.368878 <6>[ 0.102354] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10443 01:00:41.375423 <6>[ 0.102371] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10444 01:00:41.381849 <6>[ 0.102661] Detected PIPT I-cache on CPU5
10445 01:00:41.388612 <6>[ 0.102725] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10446 01:00:41.395087 <6>[ 0.102742] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10447 01:00:41.398461 <6>[ 0.103027] Detected PIPT I-cache on CPU6
10448 01:00:41.405326 <6>[ 0.103093] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10449 01:00:41.411578 <6>[ 0.103110] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10450 01:00:41.418085 <6>[ 0.103406] Detected PIPT I-cache on CPU7
10451 01:00:41.425428 <6>[ 0.103471] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10452 01:00:41.431440 <6>[ 0.103488] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10453 01:00:41.434603 <6>[ 0.103534] smp: Brought up 1 node, 8 CPUs
10454 01:00:41.441421 <6>[ 0.244991] SMP: Total of 8 processors activated.
10455 01:00:41.444888 <6>[ 0.249942] CPU features: detected: 32-bit EL0 Support
10456 01:00:41.454617 <6>[ 0.255338] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10457 01:00:41.461166 <6>[ 0.264138] CPU features: detected: Common not Private translations
10458 01:00:41.467902 <6>[ 0.270614] CPU features: detected: CRC32 instructions
10459 01:00:41.471082 <6>[ 0.275965] CPU features: detected: RCpc load-acquire (LDAPR)
10460 01:00:41.477623 <6>[ 0.281925] CPU features: detected: LSE atomic instructions
10461 01:00:41.484357 <6>[ 0.287743] CPU features: detected: Privileged Access Never
10462 01:00:41.490758 <6>[ 0.293522] CPU features: detected: RAS Extension Support
10463 01:00:41.497579 <6>[ 0.299130] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10464 01:00:41.501019 <6>[ 0.306349] CPU: All CPU(s) started at EL2
10465 01:00:41.507536 <6>[ 0.310666] alternatives: applying system-wide alternatives
10466 01:00:41.516705 <6>[ 0.321358] devtmpfs: initialized
10467 01:00:41.528904 <6>[ 0.330314] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10468 01:00:41.539366 <6>[ 0.340274] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10469 01:00:41.545581 <6>[ 0.348504] pinctrl core: initialized pinctrl subsystem
10470 01:00:41.548942 <6>[ 0.355295] DMI not present or invalid.
10471 01:00:41.555836 <6>[ 0.359711] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10472 01:00:41.565894 <6>[ 0.366593] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10473 01:00:41.572608 <6>[ 0.374175] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10474 01:00:41.582298 <6>[ 0.382403] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10475 01:00:41.585434 <6>[ 0.390646] audit: initializing netlink subsys (disabled)
10476 01:00:41.595982 <5>[ 0.396338] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10477 01:00:41.602165 <6>[ 0.397082] thermal_sys: Registered thermal governor 'step_wise'
10478 01:00:41.609346 <6>[ 0.404305] thermal_sys: Registered thermal governor 'power_allocator'
10479 01:00:41.612067 <6>[ 0.410561] cpuidle: using governor menu
10480 01:00:41.618790 <6>[ 0.421520] NET: Registered PF_QIPCRTR protocol family
10481 01:00:41.625093 <6>[ 0.427008] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10482 01:00:41.631664 <6>[ 0.434109] ASID allocator initialised with 32768 entries
10483 01:00:41.634853 <6>[ 0.440726] Serial: AMBA PL011 UART driver
10484 01:00:41.645289 <4>[ 0.449856] Trying to register duplicate clock ID: 134
10485 01:00:41.702021 <6>[ 0.509540] KASLR enabled
10486 01:00:41.716441 <6>[ 0.517328] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10487 01:00:41.722421 <6>[ 0.524341] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10488 01:00:41.729353 <6>[ 0.530830] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10489 01:00:41.736069 <6>[ 0.537837] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10490 01:00:41.742567 <6>[ 0.544324] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10491 01:00:41.749544 <6>[ 0.551328] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10492 01:00:41.755927 <6>[ 0.557814] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10493 01:00:41.762404 <6>[ 0.564819] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10494 01:00:41.765785 <6>[ 0.572342] ACPI: Interpreter disabled.
10495 01:00:41.774033 <6>[ 0.578847] iommu: Default domain type: Translated
10496 01:00:41.781287 <6>[ 0.583959] iommu: DMA domain TLB invalidation policy: strict mode
10497 01:00:41.784517 <5>[ 0.590620] SCSI subsystem initialized
10498 01:00:41.791408 <6>[ 0.594786] usbcore: registered new interface driver usbfs
10499 01:00:41.797543 <6>[ 0.600518] usbcore: registered new interface driver hub
10500 01:00:41.800901 <6>[ 0.606069] usbcore: registered new device driver usb
10501 01:00:41.807339 <6>[ 0.612212] pps_core: LinuxPPS API ver. 1 registered
10502 01:00:41.817579 <6>[ 0.617406] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10503 01:00:41.821214 <6>[ 0.626755] PTP clock support registered
10504 01:00:41.824586 <6>[ 0.630997] EDAC MC: Ver: 3.0.0
10505 01:00:41.831782 <6>[ 0.636207] FPGA manager framework
10506 01:00:41.838387 <6>[ 0.639888] Advanced Linux Sound Architecture Driver Initialized.
10507 01:00:41.841555 <6>[ 0.646662] vgaarb: loaded
10508 01:00:41.847883 <6>[ 0.649820] clocksource: Switched to clocksource arch_sys_counter
10509 01:00:41.851860 <5>[ 0.656264] VFS: Disk quotas dquot_6.6.0
10510 01:00:41.857966 <6>[ 0.660449] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10511 01:00:41.861247 <6>[ 0.667638] pnp: PnP ACPI: disabled
10512 01:00:41.869666 <6>[ 0.674348] NET: Registered PF_INET protocol family
10513 01:00:41.879551 <6>[ 0.679946] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10514 01:00:41.890920 <6>[ 0.692256] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10515 01:00:41.901196 <6>[ 0.701069] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10516 01:00:41.907542 <6>[ 0.709043] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10517 01:00:41.917534 <6>[ 0.717744] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10518 01:00:41.923943 <6>[ 0.727500] TCP: Hash tables configured (established 65536 bind 65536)
10519 01:00:41.931078 <6>[ 0.734365] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 01:00:41.940715 <6>[ 0.741565] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 01:00:41.947183 <6>[ 0.749269] NET: Registered PF_UNIX/PF_LOCAL protocol family
10522 01:00:41.950816 <6>[ 0.755371] RPC: Registered named UNIX socket transport module.
10523 01:00:41.957235 <6>[ 0.761523] RPC: Registered udp transport module.
10524 01:00:41.960444 <6>[ 0.766455] RPC: Registered tcp transport module.
10525 01:00:41.967245 <6>[ 0.771388] RPC: Registered tcp NFSv4.1 backchannel transport module.
10526 01:00:41.973936 <6>[ 0.778054] PCI: CLS 0 bytes, default 64
10527 01:00:41.976576 <6>[ 0.782371] Unpacking initramfs...
10528 01:00:41.993330 <6>[ 0.794369] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10529 01:00:42.003639 <6>[ 0.803025] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10530 01:00:42.006632 <6>[ 0.811898] kvm [1]: IPA Size Limit: 40 bits
10531 01:00:42.012836 <6>[ 0.816426] kvm [1]: GICv3: no GICV resource entry
10532 01:00:42.016593 <6>[ 0.821447] kvm [1]: disabling GICv2 emulation
10533 01:00:42.023812 <6>[ 0.826136] kvm [1]: GIC system register CPU interface enabled
10534 01:00:42.026789 <6>[ 0.832306] kvm [1]: vgic interrupt IRQ18
10535 01:00:42.033057 <6>[ 0.836665] kvm [1]: VHE mode initialized successfully
10536 01:00:42.039414 <5>[ 0.843173] Initialise system trusted keyrings
10537 01:00:42.045762 <6>[ 0.847965] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10538 01:00:42.053156 <6>[ 0.857934] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10539 01:00:42.060260 <5>[ 0.864320] NFS: Registering the id_resolver key type
10540 01:00:42.062960 <5>[ 0.869619] Key type id_resolver registered
10541 01:00:42.069877 <5>[ 0.874037] Key type id_legacy registered
10542 01:00:42.076297 <6>[ 0.878312] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10543 01:00:42.083105 <6>[ 0.885233] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10544 01:00:42.089973 <6>[ 0.892936] 9p: Installing v9fs 9p2000 file system support
10545 01:00:42.125969 <5>[ 0.930519] Key type asymmetric registered
10546 01:00:42.129077 <5>[ 0.934850] Asymmetric key parser 'x509' registered
10547 01:00:42.139287 <6>[ 0.939991] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10548 01:00:42.142764 <6>[ 0.947608] io scheduler mq-deadline registered
10549 01:00:42.145879 <6>[ 0.952385] io scheduler kyber registered
10550 01:00:42.165508 <6>[ 0.969930] EINJ: ACPI disabled.
10551 01:00:42.198313 <4>[ 0.996390] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 01:00:42.208596 <4>[ 1.007030] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 01:00:42.223789 <6>[ 1.028219] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10554 01:00:42.232121 <6>[ 1.036371] printk: console [ttyS0] disabled
10555 01:00:42.260060 <6>[ 1.061022] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10556 01:00:42.266281 <6>[ 1.070496] printk: console [ttyS0] enabled
10557 01:00:42.269581 <6>[ 1.070496] printk: console [ttyS0] enabled
10558 01:00:42.276030 <6>[ 1.079391] printk: bootconsole [mtk8250] disabled
10559 01:00:42.279444 <6>[ 1.079391] printk: bootconsole [mtk8250] disabled
10560 01:00:42.286454 <6>[ 1.090718] SuperH (H)SCI(F) driver initialized
10561 01:00:42.289550 <6>[ 1.096025] msm_serial: driver initialized
10562 01:00:42.303671 <6>[ 1.105140] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10563 01:00:42.313861 <6>[ 1.113690] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10564 01:00:42.320930 <6>[ 1.122233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10565 01:00:42.330417 <6>[ 1.130861] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10566 01:00:42.340310 <6>[ 1.139568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10567 01:00:42.346815 <6>[ 1.148293] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10568 01:00:42.356812 <6>[ 1.156837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10569 01:00:42.363446 <6>[ 1.165641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10570 01:00:42.373337 <6>[ 1.174186] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10571 01:00:42.385725 <6>[ 1.190193] loop: module loaded
10572 01:00:42.391860 <6>[ 1.196198] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10573 01:00:42.415043 <4>[ 1.219686] mtk-pmic-keys: Failed to locate of_node [id: -1]
10574 01:00:42.422237 <6>[ 1.226612] megasas: 07.719.03.00-rc1
10575 01:00:42.431659 <6>[ 1.236270] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10576 01:00:42.440849 <6>[ 1.245185] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10577 01:00:42.457178 <6>[ 1.261644] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10578 01:00:42.513746 <6>[ 1.311680] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10579 01:00:42.714925 <6>[ 1.519757] Freeing initrd memory: 17384K
10580 01:00:42.725004 <6>[ 1.529918] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10581 01:00:42.737004 <6>[ 1.541078] tun: Universal TUN/TAP device driver, 1.6
10582 01:00:42.739649 <6>[ 1.547176] thunder_xcv, ver 1.0
10583 01:00:42.743491 <6>[ 1.550683] thunder_bgx, ver 1.0
10584 01:00:42.746576 <6>[ 1.554177] nicpf, ver 1.0
10585 01:00:42.757033 <6>[ 1.558225] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10586 01:00:42.760178 <6>[ 1.565700] hns3: Copyright (c) 2017 Huawei Corporation.
10587 01:00:42.766776 <6>[ 1.571291] hclge is initializing
10588 01:00:42.770175 <6>[ 1.574872] e1000: Intel(R) PRO/1000 Network Driver
10589 01:00:42.777183 <6>[ 1.580001] e1000: Copyright (c) 1999-2006 Intel Corporation.
10590 01:00:42.780023 <6>[ 1.586014] e1000e: Intel(R) PRO/1000 Network Driver
10591 01:00:42.787044 <6>[ 1.591230] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10592 01:00:42.793223 <6>[ 1.597416] igb: Intel(R) Gigabit Ethernet Network Driver
10593 01:00:42.800126 <6>[ 1.603065] igb: Copyright (c) 2007-2014 Intel Corporation.
10594 01:00:42.806780 <6>[ 1.608901] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10595 01:00:42.812961 <6>[ 1.615419] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10596 01:00:42.816202 <6>[ 1.621900] sky2: driver version 1.30
10597 01:00:42.822955 <6>[ 1.626935] VFIO - User Level meta-driver version: 0.3
10598 01:00:42.830559 <6>[ 1.635253] usbcore: registered new interface driver usb-storage
10599 01:00:42.837460 <6>[ 1.641711] usbcore: registered new device driver onboard-usb-hub
10600 01:00:42.846505 <6>[ 1.650965] mt6397-rtc mt6359-rtc: registered as rtc0
10601 01:00:42.856045 <6>[ 1.656432] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:00:03 UTC (1705626003)
10602 01:00:42.859584 <6>[ 1.666028] i2c_dev: i2c /dev entries driver
10603 01:00:42.876661 <6>[ 1.677995] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10604 01:00:42.896394 <6>[ 1.700985] cpu cpu0: EM: created perf domain
10605 01:00:42.899856 <6>[ 1.705938] cpu cpu4: EM: created perf domain
10606 01:00:42.907074 <6>[ 1.711577] sdhci: Secure Digital Host Controller Interface driver
10607 01:00:42.913585 <6>[ 1.718013] sdhci: Copyright(c) Pierre Ossman
10608 01:00:42.920228 <6>[ 1.722972] Synopsys Designware Multimedia Card Interface Driver
10609 01:00:42.926848 <6>[ 1.729629] sdhci-pltfm: SDHCI platform and OF driver helper
10610 01:00:42.929913 <6>[ 1.729731] mmc0: CQHCI version 5.10
10611 01:00:42.936530 <6>[ 1.739690] ledtrig-cpu: registered to indicate activity on CPUs
10612 01:00:42.943615 <6>[ 1.746793] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10613 01:00:42.950110 <6>[ 1.753848] usbcore: registered new interface driver usbhid
10614 01:00:42.953457 <6>[ 1.759669] usbhid: USB HID core driver
10615 01:00:42.960495 <6>[ 1.763873] spi_master spi0: will run message pump with realtime priority
10616 01:00:43.003340 <6>[ 1.800922] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10617 01:00:43.021919 <6>[ 1.816876] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10618 01:00:43.025646 <6>[ 1.830476] mmc0: Command Queue Engine enabled
10619 01:00:43.032478 <6>[ 1.835253] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10620 01:00:43.038862 <6>[ 1.842174] cros-ec-spi spi0.0: Chrome EC device registered
10621 01:00:43.042583 <6>[ 1.842495] mmcblk0: mmc0:0001 DA4128 116 GiB
10622 01:00:43.052032 <6>[ 1.856808] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10623 01:00:43.059595 <6>[ 1.864163] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10624 01:00:43.066227 <6>[ 1.870165] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10625 01:00:43.073046 <6>[ 1.876024] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10626 01:00:43.090491 <6>[ 1.891839] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10627 01:00:43.098102 <6>[ 1.902770] NET: Registered PF_PACKET protocol family
10628 01:00:43.101772 <6>[ 1.908162] 9pnet: Installing 9P2000 support
10629 01:00:43.108263 <5>[ 1.912728] Key type dns_resolver registered
10630 01:00:43.111752 <6>[ 1.917713] registered taskstats version 1
10631 01:00:43.118141 <5>[ 1.922100] Loading compiled-in X.509 certificates
10632 01:00:43.148418 <4>[ 1.946652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 01:00:43.158753 <4>[ 1.957420] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 01:00:43.165381 <3>[ 1.967957] debugfs: File 'uA_load' in directory '/' already present!
10635 01:00:43.172149 <3>[ 1.974658] debugfs: File 'min_uV' in directory '/' already present!
10636 01:00:43.179054 <3>[ 1.981265] debugfs: File 'max_uV' in directory '/' already present!
10637 01:00:43.185561 <3>[ 1.987872] debugfs: File 'constraint_flags' in directory '/' already present!
10638 01:00:43.196188 <3>[ 1.997423] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10639 01:00:43.206264 <6>[ 2.010733] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10640 01:00:43.213033 <6>[ 2.017480] xhci-mtk 11200000.usb: xHCI Host Controller
10641 01:00:43.219422 <6>[ 2.022988] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10642 01:00:43.229429 <6>[ 2.030843] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10643 01:00:43.236022 <6>[ 2.040266] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10644 01:00:43.242996 <6>[ 2.046325] xhci-mtk 11200000.usb: xHCI Host Controller
10645 01:00:43.249651 <6>[ 2.051801] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10646 01:00:43.256514 <6>[ 2.059445] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10647 01:00:43.263328 <6>[ 2.067097] hub 1-0:1.0: USB hub found
10648 01:00:43.265868 <6>[ 2.071106] hub 1-0:1.0: 1 port detected
10649 01:00:43.272377 <6>[ 2.075367] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10650 01:00:43.279515 <6>[ 2.083988] hub 2-0:1.0: USB hub found
10651 01:00:43.282860 <6>[ 2.088005] hub 2-0:1.0: 1 port detected
10652 01:00:43.291380 <6>[ 2.095983] mtk-msdc 11f70000.mmc: Got CD GPIO
10653 01:00:43.302442 <6>[ 2.104016] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10654 01:00:43.309555 <6>[ 2.112033] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10655 01:00:43.319205 <4>[ 2.119954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10656 01:00:43.329100 <6>[ 2.129471] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10657 01:00:43.335418 <6>[ 2.137547] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10658 01:00:43.342300 <6>[ 2.145556] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10659 01:00:43.352218 <6>[ 2.153475] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10660 01:00:43.358837 <6>[ 2.161291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10661 01:00:43.368771 <6>[ 2.169107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10662 01:00:43.378888 <6>[ 2.179444] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10663 01:00:43.385428 <6>[ 2.187799] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10664 01:00:43.395935 <6>[ 2.196147] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10665 01:00:43.402048 <6>[ 2.204485] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10666 01:00:43.412563 <6>[ 2.212825] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10667 01:00:43.419128 <6>[ 2.221165] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10668 01:00:43.429304 <6>[ 2.229503] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10669 01:00:43.435143 <6>[ 2.237842] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10670 01:00:43.445406 <6>[ 2.246181] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10671 01:00:43.452296 <6>[ 2.254522] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10672 01:00:43.461906 <6>[ 2.262862] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10673 01:00:43.468648 <6>[ 2.271214] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10674 01:00:43.478656 <6>[ 2.279553] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10675 01:00:43.485252 <6>[ 2.287891] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10676 01:00:43.495020 <6>[ 2.296231] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10677 01:00:43.501871 <6>[ 2.304975] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10678 01:00:43.509082 <6>[ 2.312119] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10679 01:00:43.515292 <6>[ 2.318893] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10680 01:00:43.521557 <6>[ 2.325658] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10681 01:00:43.528511 <6>[ 2.332602] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10682 01:00:43.538199 <6>[ 2.339461] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10683 01:00:43.548043 <6>[ 2.348590] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10684 01:00:43.558039 <6>[ 2.357710] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10685 01:00:43.568192 <6>[ 2.367004] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10686 01:00:43.577849 <6>[ 2.376470] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10687 01:00:43.584189 <6>[ 2.385936] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10688 01:00:43.594068 <6>[ 2.395055] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10689 01:00:43.604539 <6>[ 2.404520] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10690 01:00:43.614488 <6>[ 2.413638] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10691 01:00:43.624507 <6>[ 2.422931] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10692 01:00:43.634321 <6>[ 2.433092] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10693 01:00:43.644177 <6>[ 2.444605] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10694 01:00:43.650974 <6>[ 2.454395] Trying to probe devices needed for running init ...
10695 01:00:43.692620 <6>[ 2.494091] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10696 01:00:43.847514 <6>[ 2.652148] hub 1-1:1.0: USB hub found
10697 01:00:43.850687 <6>[ 2.656645] hub 1-1:1.0: 4 ports detected
10698 01:00:43.860843 <6>[ 2.665397] hub 1-1:1.0: USB hub found
10699 01:00:43.863861 <6>[ 2.669768] hub 1-1:1.0: 4 ports detected
10700 01:00:43.972987 <6>[ 2.774443] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10701 01:00:43.999026 <6>[ 2.803890] hub 2-1:1.0: USB hub found
10702 01:00:44.002663 <6>[ 2.808386] hub 2-1:1.0: 3 ports detected
10703 01:00:44.011533 <6>[ 2.816527] hub 2-1:1.0: USB hub found
10704 01:00:44.014755 <6>[ 2.820976] hub 2-1:1.0: 3 ports detected
10705 01:00:44.188728 <6>[ 2.990137] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10706 01:00:44.321594 <6>[ 3.126030] hub 1-1.4:1.0: USB hub found
10707 01:00:44.324936 <6>[ 3.130697] hub 1-1.4:1.0: 2 ports detected
10708 01:00:44.334353 <6>[ 3.139058] hub 1-1.4:1.0: USB hub found
10709 01:00:44.337827 <6>[ 3.143657] hub 1-1.4:1.0: 2 ports detected
10710 01:00:44.400745 <6>[ 3.202214] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10711 01:00:44.636484 <6>[ 3.438135] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10712 01:00:44.828741 <6>[ 3.630116] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10713 01:00:55.925650 <6>[ 14.735101] ALSA device list:
10714 01:00:55.931755 <6>[ 14.738394] No soundcards found.
10715 01:00:55.940176 <6>[ 14.746316] Freeing unused kernel memory: 8448K
10716 01:00:55.943632 <6>[ 14.751341] Run /init as init process
10717 01:00:55.955012 Loading, please wait...
10718 01:00:55.975219 Starting version 247.3-7+deb11u2
10719 01:00:56.158528 <6>[ 14.961179] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10720 01:00:56.198839 <6>[ 15.004883] remoteproc remoteproc0: scp is available
10721 01:00:56.205583 <6>[ 15.010256] remoteproc remoteproc0: powering up scp
10722 01:00:56.211639 <6>[ 15.010909] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10723 01:00:56.218478 <6>[ 15.015395] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10724 01:00:56.225271 <6>[ 15.015411] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10725 01:00:56.234929 <6>[ 15.037081] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10726 01:00:56.242195 <6>[ 15.045785] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10727 01:00:56.258056 <3>[ 15.060757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 01:00:56.264472 <3>[ 15.069227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 01:00:56.274547 <3>[ 15.077331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 01:00:56.284482 <3>[ 15.087075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 01:00:56.291068 <3>[ 15.095278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 01:00:56.300999 <3>[ 15.103449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 01:00:56.307487 <3>[ 15.111531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 01:00:56.317651 <3>[ 15.119743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 01:00:56.320973 <6>[ 15.123481] mc: Linux media interface: v0.10
10736 01:00:56.327428 <4>[ 15.126745] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10737 01:00:56.337469 <4>[ 15.135891] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10738 01:00:56.344104 <6>[ 15.140619] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10739 01:00:56.350533 <6>[ 15.140629] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10740 01:00:56.360317 <3>[ 15.147386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 01:00:56.364128 <6>[ 15.148632] Bluetooth: Core ver 2.22
10742 01:00:56.370538 <6>[ 15.148686] NET: Registered PF_BLUETOOTH protocol family
10743 01:00:56.377557 <6>[ 15.148689] Bluetooth: HCI device and connection manager initialized
10744 01:00:56.380449 <6>[ 15.148707] Bluetooth: HCI socket layer initialized
10745 01:00:56.387377 <6>[ 15.148713] Bluetooth: L2CAP socket layer initialized
10746 01:00:56.390876 <6>[ 15.148723] Bluetooth: SCO socket layer initialized
10747 01:00:56.397778 <6>[ 15.148781] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10748 01:00:56.403925 <6>[ 15.155633] remoteproc remoteproc0: remote processor scp is now up
10749 01:00:56.411333 <6>[ 15.160160] usbcore: registered new device driver r8152-cfgselector
10750 01:00:56.420994 <3>[ 15.162875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 01:00:56.427698 <4>[ 15.174077] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10752 01:00:56.434796 <4>[ 15.174077] Fallback method does not support PEC.
10753 01:00:56.441076 <3>[ 15.175035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 01:00:56.448032 <6>[ 15.179302] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10755 01:00:56.454359 <6>[ 15.179306] pci_bus 0000:00: root bus resource [bus 00-ff]
10756 01:00:56.460767 <6>[ 15.179311] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10757 01:00:56.470854 <6>[ 15.179314] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10758 01:00:56.477377 <6>[ 15.179338] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10759 01:00:56.484439 <6>[ 15.179351] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10760 01:00:56.490789 <6>[ 15.179419] pci 0000:00:00.0: supports D1 D2
10761 01:00:56.497327 <6>[ 15.179421] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10762 01:00:56.503859 <6>[ 15.180398] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10763 01:00:56.513987 <3>[ 15.186856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 01:00:56.520632 <3>[ 15.187148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 01:00:56.527340 <6>[ 15.192434] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10766 01:00:56.537698 <3>[ 15.195922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10767 01:00:56.543662 <3>[ 15.197516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 01:00:56.549833 <6>[ 15.202584] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10769 01:00:56.560084 <6>[ 15.203749] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10770 01:00:56.566414 <6>[ 15.205089] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10771 01:00:56.576526 <3>[ 15.210205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 01:00:56.583955 <6>[ 15.216684] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10773 01:00:56.593561 <3>[ 15.223153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 01:00:56.600195 <3>[ 15.223357] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10775 01:00:56.606322 <6>[ 15.231236] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10776 01:00:56.616215 <3>[ 15.244854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 01:00:56.620018 <6>[ 15.253036] pci 0000:01:00.0: supports D1 D2
10778 01:00:56.629397 <6>[ 15.254228] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10779 01:00:56.639203 <6>[ 15.254573] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10780 01:00:56.649332 <6>[ 15.255058] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10781 01:00:56.655559 <6>[ 15.259316] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10782 01:00:56.665365 <3>[ 15.259809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 01:00:56.672025 <6>[ 15.265528] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10784 01:00:56.679067 <6>[ 15.273384] videodev: Linux video capture interface: v2.00
10785 01:00:56.685993 <4>[ 15.277374] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10786 01:00:56.695789 <4>[ 15.277383] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10787 01:00:56.702404 <6>[ 15.285957] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10788 01:00:56.708918 <6>[ 15.316843] usbcore: registered new interface driver btusb
10789 01:00:56.719105 <4>[ 15.317222] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10790 01:00:56.725635 <3>[ 15.317232] Bluetooth: hci0: Failed to load firmware file (-2)
10791 01:00:56.729092 <3>[ 15.317236] Bluetooth: hci0: Failed to set up firmware (-2)
10792 01:00:56.738745 <4>[ 15.317240] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10793 01:00:56.748618 <6>[ 15.324057] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10794 01:00:56.751912 <6>[ 15.330040] r8152 2-1.3:1.0 eth0: v1.12.13
10795 01:00:56.758530 <6>[ 15.330093] usbcore: registered new interface driver r8152
10796 01:00:56.765125 <6>[ 15.355687] usbcore: registered new interface driver cdc_ether
10797 01:00:56.771442 <6>[ 15.356189] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10798 01:00:56.785057 <6>[ 15.357320] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10799 01:00:56.788587 <6>[ 15.357446] usbcore: registered new interface driver uvcvideo
10800 01:00:56.798242 <6>[ 15.362675] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10801 01:00:56.804865 <6>[ 15.362686] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10802 01:00:56.814813 <6>[ 15.362699] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10803 01:00:56.821686 <6>[ 15.379844] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10804 01:00:56.827843 <6>[ 15.387297] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10805 01:00:56.834626 <6>[ 15.387410] usbcore: registered new interface driver r8153_ecm
10806 01:00:56.841191 <6>[ 15.405859] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10807 01:00:56.844500 <6>[ 15.411614] pci 0000:00:00.0: PCI bridge to [bus 01]
10808 01:00:56.854560 <6>[ 15.657082] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10809 01:00:56.860949 <6>[ 15.665244] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10810 01:00:56.867616 <6>[ 15.672109] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10811 01:00:56.873779 <6>[ 15.678557] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10812 01:00:56.889472 <5>[ 15.691989] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10813 01:00:56.908124 <5>[ 15.710956] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10814 01:00:56.915137 <5>[ 15.718351] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10815 01:00:56.924920 <4>[ 15.726801] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10816 01:00:56.927748 <6>[ 15.735681] cfg80211: failed to load regulatory.db
10817 01:00:56.977301 <6>[ 15.780536] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10818 01:00:56.984274 <6>[ 15.788088] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10819 01:00:57.008819 <6>[ 15.814735] mt7921e 0000:01:00.0: ASIC revision: 79610010
10820 01:00:57.110282 <6>[ 15.913474] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10821 01:00:57.113274 <6>[ 15.913474]
10822 01:00:57.125933 Begin: Loading essential drivers ... done.
10823 01:00:57.128938 Begin: Running /scripts/init-premount ... done.
10824 01:00:57.135454 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10825 01:00:57.145377 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10826 01:00:57.148716 Device /sys/class/net/enx00e04c722dd6 found
10827 01:00:57.149294 done.
10828 01:00:57.206735 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10829 01:00:57.377869 <6>[ 16.180729] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10830 01:00:58.219502 <6>[ 17.025854] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10831 01:00:58.257657 <6>[ 17.064118] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10832 01:00:58.350044 IP-Config: no response after 2 secs - giving up
10833 01:00:58.395328 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10834 01:00:58.407500 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10835 01:00:59.121076 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10836 01:00:59.127604 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10837 01:00:59.134498 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10838 01:00:59.141238 host : mt8192-asurada-spherion-r0-cbg-1
10839 01:00:59.147654 domain : lava-rack
10840 01:00:59.154236 rootserver: 192.168.201.1 rootpath:
10841 01:00:59.154812 filename :
10842 01:00:59.231667 done.
10843 01:00:59.238913 Begin: Running /scripts/nfs-bottom ... done.
10844 01:00:59.256771 Begin: Running /scripts/init-bottom ... done.
10845 01:01:00.460691 <6>[ 19.267550] NET: Registered PF_INET6 protocol family
10846 01:01:00.468483 <6>[ 19.275106] Segment Routing with IPv6
10847 01:01:00.471765 <6>[ 19.279118] In-situ OAM (IOAM) with IPv6
10848 01:01:00.615011 <30>[ 19.402120] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10849 01:01:00.618358 <30>[ 19.426577] systemd[1]: Detected architecture arm64.
10850 01:01:00.641495
10851 01:01:00.645066 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10852 01:01:00.645652
10853 01:01:00.662303 <30>[ 19.468940] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10854 01:01:01.500572 <30>[ 20.304174] systemd[1]: Queued start job for default target Graphical Interface.
10855 01:01:01.533521 <30>[ 20.340499] systemd[1]: Created slice system-getty.slice.
10856 01:01:01.540292 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10857 01:01:01.556607 <30>[ 20.363488] systemd[1]: Created slice system-modprobe.slice.
10858 01:01:01.563171 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10859 01:01:01.581512 <30>[ 20.388220] systemd[1]: Created slice system-serial\x2dgetty.slice.
10860 01:01:01.591845 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10861 01:01:01.604279 <30>[ 20.411178] systemd[1]: Created slice User and Session Slice.
10862 01:01:01.610711 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10863 01:01:01.631472 <30>[ 20.434951] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10864 01:01:01.641549 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10865 01:01:01.659606 <30>[ 20.462889] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10866 01:01:01.666387 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10867 01:01:01.689898 <30>[ 20.490255] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10868 01:01:01.696406 <30>[ 20.502410] systemd[1]: Reached target Local Encrypted Volumes.
10869 01:01:01.703435 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10870 01:01:01.719834 <30>[ 20.526654] systemd[1]: Reached target Paths.
10871 01:01:01.726332 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10872 01:01:01.739413 <30>[ 20.546113] systemd[1]: Reached target Remote File Systems.
10873 01:01:01.746246 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10874 01:01:01.763918 <30>[ 20.570487] systemd[1]: Reached target Slices.
10875 01:01:01.770281 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10876 01:01:01.783082 <30>[ 20.590136] systemd[1]: Reached target Swap.
10877 01:01:01.786758 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10878 01:01:01.806634 <30>[ 20.610594] systemd[1]: Listening on initctl Compatibility Named Pipe.
10879 01:01:01.813554 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10880 01:01:01.820274 <30>[ 20.626777] systemd[1]: Listening on Journal Audit Socket.
10881 01:01:01.827125 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10882 01:01:01.844954 <30>[ 20.651564] systemd[1]: Listening on Journal Socket (/dev/log).
10883 01:01:01.851629 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10884 01:01:01.867694 <30>[ 20.674679] systemd[1]: Listening on Journal Socket.
10885 01:01:01.874792 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10886 01:01:01.891866 <30>[ 20.695647] systemd[1]: Listening on Network Service Netlink Socket.
10887 01:01:01.898550 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10888 01:01:01.914127 <30>[ 20.721069] systemd[1]: Listening on udev Control Socket.
10889 01:01:01.920504 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10890 01:01:01.935797 <30>[ 20.742550] systemd[1]: Listening on udev Kernel Socket.
10891 01:01:01.942499 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10892 01:01:01.983464 <30>[ 20.790165] systemd[1]: Mounting Huge Pages File System...
10893 01:01:01.989686 Mounting [0;1;39mHuge Pages File System[0m...
10894 01:01:02.007438 <30>[ 20.814361] systemd[1]: Mounting POSIX Message Queue File System...
10895 01:01:02.014314 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10896 01:01:02.063677 <30>[ 20.870263] systemd[1]: Mounting Kernel Debug File System...
10897 01:01:02.070049 Mounting [0;1;39mKernel Debug File System[0m...
10898 01:01:02.086593 <30>[ 20.890658] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10899 01:01:02.099964 <30>[ 20.903548] systemd[1]: Starting Create list of static device nodes for the current kernel...
10900 01:01:02.106836 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10901 01:01:02.159772 <30>[ 20.966825] systemd[1]: Starting Load Kernel Module configfs...
10902 01:01:02.166428 Starting [0;1;39mLoad Kernel Module configfs[0m...
10903 01:01:02.181586 <30>[ 20.988735] systemd[1]: Starting Load Kernel Module drm...
10904 01:01:02.188279 Starting [0;1;39mLoad Kernel Module drm[0m...
10905 01:01:02.206633 <30>[ 21.013421] systemd[1]: Starting Load Kernel Module fuse...
10906 01:01:02.212894 Starting [0;1;39mLoad Kernel Module fuse[0m...
10907 01:01:02.251413 <30>[ 21.054979] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10908 01:01:02.258516 <6>[ 21.065727] fuse: init (API version 7.37)
10909 01:01:02.291586 <30>[ 21.098631] systemd[1]: Starting Journal Service...
10910 01:01:02.294992 Starting [0;1;39mJournal Service[0m...
10911 01:01:02.319810 <30>[ 21.126525] systemd[1]: Starting Load Kernel Modules...
10912 01:01:02.326088 Starting [0;1;39mLoad Kernel Modules[0m...
10913 01:01:02.375243 <30>[ 21.178929] systemd[1]: Starting Remount Root and Kernel File Systems...
10914 01:01:02.381550 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10915 01:01:02.398572 <30>[ 21.205441] systemd[1]: Starting Coldplug All udev Devices...
10916 01:01:02.404732 Starting [0;1;39mColdplug All udev Devices[0m...
10917 01:01:02.424254 <30>[ 21.231418] systemd[1]: Mounted Huge Pages File System.
10918 01:01:02.430949 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10919 01:01:02.447937 <30>[ 21.255108] systemd[1]: Mounted POSIX Message Queue File System.
10920 01:01:02.461668 [[0;32m OK [<3>[ 21.262947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 01:01:02.464617 0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10922 01:01:02.479843 <30>[ 21.286794] systemd[1]: Mounted Kernel Debug File System.
10923 01:01:02.487176 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10924 01:01:02.497517 <3>[ 21.301316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 01:01:02.508397 <30>[ 21.312048] systemd[1]: Finished Create list of static device nodes for the current kernel.
10926 01:01:02.518157 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10927 01:01:02.531960 <30>[ 21.339181] systemd[1]: modprobe@configfs.service: Succeeded.
10928 01:01:02.539630 <30>[ 21.346695] systemd[1]: Finished Load Kernel Module configfs.
10929 01:01:02.546620 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10930 01:01:02.557177 <3>[ 21.360890] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 01:01:02.563851 <30>[ 21.370953] systemd[1]: modprobe@drm.service: Succeeded.
10932 01:01:02.570586 <30>[ 21.377690] systemd[1]: Finished Load Kernel Module drm.
10933 01:01:02.577208 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10934 01:01:02.593188 <30>[ 21.399510] systemd[1]: modprobe@fuse.service: Succeeded.
10935 01:01:02.603436 <3>[ 21.402258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 01:01:02.606181 <30>[ 21.406460] systemd[1]: Finished Load Kernel Module fuse.
10937 01:01:02.613976 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10938 01:01:02.632836 <3>[ 21.436666] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 01:01:02.640927 <30>[ 21.447724] systemd[1]: Finished Load Kernel Modules.
10940 01:01:02.647633 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10941 01:01:02.661534 <30>[ 21.468087] systemd[1]: Finished Remount Root and Kernel File Systems.
10942 01:01:02.671419 <3>[ 21.470717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 01:01:02.677912 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10944 01:01:02.704596 <3>[ 21.508214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 01:01:02.729868 <30>[ 21.536659] systemd[1]: Mounting FUSE Control File System...
10946 01:01:02.739924 <3>[ 21.539318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 01:01:02.746402 Mounting [0;1;39mFUSE Control File System[0m...
10948 01:01:02.762025 <30>[ 21.568787] systemd[1]: Mounting Kernel Configuration File System...
10949 01:01:02.771671 <3>[ 21.572831] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 01:01:02.778472 Mounting [0;1;39mKernel Configuration File System[0m...
10951 01:01:02.804967 <30>[ 21.608555] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10952 01:01:02.814755 <3>[ 21.608613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 01:01:02.824928 <30>[ 21.617589] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10954 01:01:02.833099 <30>[ 21.640304] systemd[1]: Starting Load/Save Random Seed...
10955 01:01:02.840382 Starting [0;1;39mLoad/Save Random Seed[0m...
10956 01:01:02.884298 <30>[ 21.690835] systemd[1]: Starting Apply Kernel Variables...
10957 01:01:02.900494 <4>[ 21.692986] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10958 01:01:02.907352 <3>[ 21.712556] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10959 01:01:02.913900 Starting [0;1;39mApply Kernel Variables[0m...
10960 01:01:02.932320 <30>[ 21.738749] systemd[1]: Starting Create System Users...
10961 01:01:02.938409 Starting [0;1;39mCreate System Users[0m...
10962 01:01:02.953335 <30>[ 21.760293] systemd[1]: Started Journal Service.
10963 01:01:02.959807 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10964 01:01:02.980055 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10965 01:01:02.991165 See 'systemctl status systemd-udev-trigger.service' for details.
10966 01:01:03.008133 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10967 01:01:03.023202 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10968 01:01:03.039820 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10969 01:01:03.057054 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10970 01:01:03.072713 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10971 01:01:03.112442 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10972 01:01:03.133995 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10973 01:01:03.175086 <46>[ 21.979579] systemd-journald[306]: Received client request to flush runtime journal.
10974 01:01:03.202775 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10975 01:01:03.219406 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10976 01:01:03.239639 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10977 01:01:03.315231 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10978 01:01:04.569711 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10979 01:01:04.599618 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10980 01:01:04.666462 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10981 01:01:04.719672 Starting [0;1;39mNetwork Service[0m...
10982 01:01:05.020566 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10983 01:01:05.048308 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10984 01:01:05.110730 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10985 01:01:05.408601 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10986 01:01:05.426008 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10987 01:01:05.456501 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10988 01:01:05.475753 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10989 01:01:05.492063 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10990 01:01:05.512466 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10991 01:01:05.527913 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10992 01:01:05.631485 Starting [0;1;39mNetwork Name Resolution[0m...
10993 01:01:05.657537 Starting [0;1;39mNetwork Time Synchronization[0m...
10994 01:01:05.673878 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10995 01:01:05.714597 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10996 01:01:05.826247 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10997 01:01:05.843428 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10998 01:01:05.862013 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10999 01:01:05.875072 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11000 01:01:05.890993 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11001 01:01:05.961031 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11002 01:01:06.270055 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11003 01:01:06.739779 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11004 01:01:06.776383 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11005 01:01:06.790245 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11006 01:01:07.126772 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11007 01:01:07.138281 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11008 01:01:07.154293 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11009 01:01:07.219421 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11010 01:01:07.269257 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11011 01:01:07.344559 Starting [0;1;39mUser Login Management[0m...
11012 01:01:07.363164 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11013 01:01:07.375112 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11014 01:01:07.391361 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11015 01:01:07.415260 Starting [0;1;39mPermit User Sessions[0m...
11016 01:01:07.577868 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11017 01:01:07.619878 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11018 01:01:07.659615 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11019 01:01:07.674988 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11020 01:01:07.698819 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11021 01:01:07.718638 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11022 01:01:07.734861 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11023 01:01:07.750914 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11024 01:01:07.795965 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11025 01:01:07.843907 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11026 01:01:07.904519
11027 01:01:07.904682
11028 01:01:07.907469 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11029 01:01:07.907554
11030 01:01:07.911557 debian-bullseye-arm64 login: root (automatic login)
11031 01:01:07.912030
11032 01:01:07.912406
11033 01:01:08.280720 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
11034 01:01:08.281185
11035 01:01:08.287507 The programs included with the Debian GNU/Linux system are free software;
11036 01:01:08.294364 the exact distribution terms for each program are described in the
11037 01:01:08.297435 individual files in /usr/share/doc/*/copyright.
11038 01:01:08.297909
11039 01:01:08.304444 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 01:01:08.307237 permitted by applicable law.
11041 01:01:09.164955 Matched prompt #10: / #
11043 01:01:09.166276 Setting prompt string to ['/ #']
11044 01:01:09.166756 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11046 01:01:09.167840 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11047 01:01:09.168324 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11048 01:01:09.168724 Setting prompt string to ['/ #']
11049 01:01:09.169075 Forcing a shell prompt, looking for ['/ #']
11051 01:01:09.219604 / #
11052 01:01:09.219806 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11053 01:01:09.219897 Waiting using forced prompt support (timeout 00:02:30)
11054 01:01:09.225006
11055 01:01:09.225833 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11056 01:01:09.226470 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11058 01:01:09.327947 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9'
11059 01:01:09.334334 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571077/extract-nfsrootfs-w7yex2w9'
11061 01:01:09.436312 / # export NFS_SERVER_IP='192.168.201.1'
11062 01:01:09.442535 export NFS_SERVER_IP='192.168.201.1'
11063 01:01:09.443368 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 01:01:09.443943 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11065 01:01:09.444526 end: 2 depthcharge-action (duration 00:01:26) [common]
11066 01:01:09.445035 start: 3 lava-test-retry (timeout 00:07:55) [common]
11067 01:01:09.445505 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11068 01:01:09.445923 Using namespace: common
11070 01:01:09.547356 / # #
11071 01:01:09.548018 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 01:01:09.553917 #
11073 01:01:09.554907 Using /lava-12571077
11075 01:01:09.656358 / # export SHELL=/bin/bash
11076 01:01:09.663060 export SHELL=/bin/bash
11078 01:01:09.764835 / # . /lava-12571077/environment
11079 01:01:09.771382 . /lava-12571077/environment
11081 01:01:09.878672 / # /lava-12571077/bin/lava-test-runner /lava-12571077/0
11082 01:01:09.879331 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 01:01:09.885033 /lava-12571077/bin/lava-test-runner /lava-12571077/0
11084 01:01:10.176709 + export TESTRUN_ID=0_timesync-off
11085 01:01:10.179910 + TESTRUN_ID=0_timesync-off
11086 01:01:10.183044 + cd /lava-12571077/0/tests/0_timesync-off
11087 01:01:10.186279 ++ cat uuid
11088 01:01:10.190791 + UUID=12571077_1.6.2.3.1
11089 01:01:10.190903 + set +x
11090 01:01:10.197341 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12571077_1.6.2.3.1>
11091 01:01:10.197664 Received signal: <STARTRUN> 0_timesync-off 12571077_1.6.2.3.1
11092 01:01:10.197770 Starting test lava.0_timesync-off (12571077_1.6.2.3.1)
11093 01:01:10.197909 Skipping test definition patterns.
11094 01:01:10.200613 + systemctl stop systemd-timesyncd
11095 01:01:10.255112 + set +x
11096 01:01:10.258294 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12571077_1.6.2.3.1>
11097 01:01:10.258800 Received signal: <ENDRUN> 0_timesync-off 12571077_1.6.2.3.1
11098 01:01:10.259070 Ending use of test pattern.
11099 01:01:10.259286 Ending test lava.0_timesync-off (12571077_1.6.2.3.1), duration 0.06
11101 01:01:10.331919 + export TESTRUN_ID=1_kselftest-dt
11102 01:01:10.335124 + TESTRUN_ID=1_kselftest-dt
11103 01:01:10.338471 + cd /lava-12571077/0/tests/1_kselftest-dt
11104 01:01:10.341870 ++ cat uuid
11105 01:01:10.341991 + UUID=12571077_1.6.2.3.5
11106 01:01:10.344773 + set +x
11107 01:01:10.347976 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12571077_1.6.2.3.5>
11108 01:01:10.348231 Received signal: <STARTRUN> 1_kselftest-dt 12571077_1.6.2.3.5
11109 01:01:10.348303 Starting test lava.1_kselftest-dt (12571077_1.6.2.3.5)
11110 01:01:10.348383 Skipping test definition patterns.
11111 01:01:10.351815 + cd ./automated/linux/kselftest/
11112 01:01:10.377890 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11113 01:01:10.409304 INFO: install_deps skipped
11114 01:01:10.521235 --2024-01-19 01:00:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11115 01:01:10.532117 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11116 01:01:10.661931 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11117 01:01:10.790942 HTTP request sent, awaiting response... 200 OK
11118 01:01:10.794328 Length: 2966476 (2.8M) [application/octet-stream]
11119 01:01:10.798130 Saving to: 'kselftest.tar.xz'
11120 01:01:10.798716
11121 01:01:10.799103
11122 01:01:11.049789 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11123 01:01:11.308629 kselftest.tar.xz 1%[ ] 46.39K 180KB/s
11124 01:01:11.746404 kselftest.tar.xz 7%[> ] 216.08K 419KB/s
11125 01:01:12.016494 kselftest.tar.xz 28%[====> ] 822.71K 862KB/s
11126 01:01:12.022957 kselftest.tar.xz 83%[===============> ] 2.37M 1.93MB/s
11127 01:01:12.029127 kselftest.tar.xz 100%[===================>] 2.83M 2.30MB/s in 1.2s
11128 01:01:12.029211
11129 01:01:12.285243 2024-01-19 01:00:31 (2.30 MB/s) - 'kselftest.tar.xz' saved [2966476/2966476]
11130 01:01:12.285432
11131 01:01:18.115054 skiplist:
11132 01:01:18.118351 ========================================
11133 01:01:18.121597 ========================================
11134 01:01:18.193119 ============== Tests to run ===============
11135 01:01:18.196240 ===========End Tests to run ===============
11136 01:01:18.202011 shardfile-dt fail
11137 01:01:18.229982 ./kselftest.sh: 131: cannot open /lava-12571077/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11138 01:01:18.233349 + ../../utils/send-to-lava.sh ./output/result.txt
11139 01:01:18.308834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11140 01:01:18.309411 + set +x
11141 01:01:18.310095 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11143 01:01:18.315770 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12571077_1.6.2.3.5>
11144 01:01:18.316625 Received signal: <ENDRUN> 1_kselftest-dt 12571077_1.6.2.3.5
11145 01:01:18.317047 Ending use of test pattern.
11146 01:01:18.317404 Ending test lava.1_kselftest-dt (12571077_1.6.2.3.5), duration 7.97
11148 01:01:18.318690 ok: lava_test_shell seems to have completed
11149 01:01:18.319208 shardfile-dt: fail
11150 01:01:18.319653 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11151 01:01:18.320123 end: 3 lava-test-retry (duration 00:00:09) [common]
11152 01:01:18.320625 start: 4 finalize (timeout 00:07:46) [common]
11153 01:01:18.321149 start: 4.1 power-off (timeout 00:00:30) [common]
11154 01:01:18.322025 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11155 01:01:18.441883 >> Command sent successfully.
11156 01:01:18.446226 Returned 0 in 0 seconds
11157 01:01:18.547088 end: 4.1 power-off (duration 00:00:00) [common]
11159 01:01:18.548905 start: 4.2 read-feedback (timeout 00:07:45) [common]
11161 01:01:18.551146 Listened to connection for namespace 'common' for up to 1s
11162 01:01:19.550275 Finalising connection for namespace 'common'
11163 01:01:19.551043 Disconnecting from shell: Finalise
11164 01:01:19.551467 / #
11165 01:01:19.652488 end: 4.2 read-feedback (duration 00:00:01) [common]
11166 01:01:19.653354 end: 4 finalize (duration 00:00:01) [common]
11167 01:01:19.654279 Cleaning after the job
11168 01:01:19.654825 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/ramdisk
11169 01:01:19.666021 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/kernel
11170 01:01:19.697620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/dtb
11171 01:01:19.697961 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/nfsrootfs
11172 01:01:19.769704 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571077/tftp-deploy-9bqywlm8/modules
11173 01:01:19.775206 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571077
11174 01:01:20.287768 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571077
11175 01:01:20.287956 Job finished correctly