Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 17
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 00:55:22.444054 lava-dispatcher, installed at version: 2023.10
2 00:55:22.444284 start: 0 validate
3 00:55:22.444415 Start time: 2024-01-19 00:55:22.444407+00:00 (UTC)
4 00:55:22.444537 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:55:22.444666 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 00:55:22.704455 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:55:22.704621 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:22.972196 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:22.972984 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:51.833502 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:51.834243 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:55:52.355275 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:55:52.356010 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:55:52.628152 validate duration: 30.18
16 00:55:52.628679 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:55:52.628926 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:55:52.629128 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:55:52.629399 Not decompressing ramdisk as can be used compressed.
20 00:55:52.629601 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 00:55:52.629716 saving as /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/ramdisk/initrd.cpio.gz
22 00:55:52.629782 total size: 4665395 (4 MB)
23 00:55:56.221161 progress 0 % (0 MB)
24 00:55:56.225925 progress 5 % (0 MB)
25 00:55:56.227156 progress 10 % (0 MB)
26 00:55:56.228371 progress 15 % (0 MB)
27 00:55:56.229621 progress 20 % (0 MB)
28 00:55:56.230826 progress 25 % (1 MB)
29 00:55:56.232026 progress 30 % (1 MB)
30 00:55:56.233265 progress 35 % (1 MB)
31 00:55:56.234462 progress 40 % (1 MB)
32 00:55:56.235817 progress 45 % (2 MB)
33 00:55:56.237046 progress 50 % (2 MB)
34 00:55:56.238247 progress 55 % (2 MB)
35 00:55:56.239448 progress 60 % (2 MB)
36 00:55:56.240635 progress 65 % (2 MB)
37 00:55:56.241868 progress 70 % (3 MB)
38 00:55:56.243061 progress 75 % (3 MB)
39 00:55:56.244253 progress 80 % (3 MB)
40 00:55:56.245616 progress 85 % (3 MB)
41 00:55:56.246809 progress 90 % (4 MB)
42 00:55:56.248002 progress 95 % (4 MB)
43 00:55:56.249251 progress 100 % (4 MB)
44 00:55:56.249397 4 MB downloaded in 3.62 s (1.23 MB/s)
45 00:55:56.249540 end: 1.1.1 http-download (duration 00:00:04) [common]
47 00:55:56.249773 end: 1.1 download-retry (duration 00:00:04) [common]
48 00:55:56.249855 start: 1.2 download-retry (timeout 00:09:56) [common]
49 00:55:56.249951 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 00:55:56.250085 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:55:56.250152 saving as /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/kernel/Image
52 00:55:56.250212 total size: 51532288 (49 MB)
53 00:55:56.250270 No compression specified
54 00:55:56.251268 progress 0 % (0 MB)
55 00:55:56.264515 progress 5 % (2 MB)
56 00:55:56.278424 progress 10 % (4 MB)
57 00:55:56.291714 progress 15 % (7 MB)
58 00:55:56.305151 progress 20 % (9 MB)
59 00:55:56.318434 progress 25 % (12 MB)
60 00:55:56.331670 progress 30 % (14 MB)
61 00:55:56.344811 progress 35 % (17 MB)
62 00:55:56.357905 progress 40 % (19 MB)
63 00:55:56.371301 progress 45 % (22 MB)
64 00:55:56.385015 progress 50 % (24 MB)
65 00:55:56.398277 progress 55 % (27 MB)
66 00:55:56.411809 progress 60 % (29 MB)
67 00:55:56.425191 progress 65 % (31 MB)
68 00:55:56.438437 progress 70 % (34 MB)
69 00:55:56.451696 progress 75 % (36 MB)
70 00:55:56.465049 progress 80 % (39 MB)
71 00:55:56.478632 progress 85 % (41 MB)
72 00:55:56.492184 progress 90 % (44 MB)
73 00:55:56.505532 progress 95 % (46 MB)
74 00:55:56.518429 progress 100 % (49 MB)
75 00:55:56.518668 49 MB downloaded in 0.27 s (183.07 MB/s)
76 00:55:56.518822 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:55:56.519049 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:55:56.519136 start: 1.3 download-retry (timeout 00:09:56) [common]
80 00:55:56.519219 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 00:55:56.519359 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:55:56.519427 saving as /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/dtb/mt8192-asurada-spherion-r0.dtb
83 00:55:56.519486 total size: 47278 (0 MB)
84 00:55:56.519545 No compression specified
85 00:55:56.520720 progress 69 % (0 MB)
86 00:55:56.521020 progress 100 % (0 MB)
87 00:55:56.521177 0 MB downloaded in 0.00 s (26.70 MB/s)
88 00:55:56.521299 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:55:56.521522 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:55:56.521606 start: 1.4 download-retry (timeout 00:09:56) [common]
92 00:55:56.521687 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 00:55:56.521797 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 00:55:56.521862 saving as /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/nfsrootfs/full.rootfs.tar
95 00:55:56.521921 total size: 200813988 (191 MB)
96 00:55:56.521980 Using unxz to decompress xz
97 00:55:56.526283 progress 0 % (0 MB)
98 00:55:57.060503 progress 5 % (9 MB)
99 00:55:57.578165 progress 10 % (19 MB)
100 00:55:58.171382 progress 15 % (28 MB)
101 00:55:58.549911 progress 20 % (38 MB)
102 00:55:58.884771 progress 25 % (47 MB)
103 00:55:59.483460 progress 30 % (57 MB)
104 00:56:00.032711 progress 35 % (67 MB)
105 00:56:00.642742 progress 40 % (76 MB)
106 00:56:01.229248 progress 45 % (86 MB)
107 00:56:01.834938 progress 50 % (95 MB)
108 00:56:02.478106 progress 55 % (105 MB)
109 00:56:03.167890 progress 60 % (114 MB)
110 00:56:03.299538 progress 65 % (124 MB)
111 00:56:03.445766 progress 70 % (134 MB)
112 00:56:03.545249 progress 75 % (143 MB)
113 00:56:03.616766 progress 80 % (153 MB)
114 00:56:03.686607 progress 85 % (162 MB)
115 00:56:03.788025 progress 90 % (172 MB)
116 00:56:04.072678 progress 95 % (181 MB)
117 00:56:04.661238 progress 100 % (191 MB)
118 00:56:04.666524 191 MB downloaded in 8.14 s (23.51 MB/s)
119 00:56:04.666888 end: 1.4.1 http-download (duration 00:00:08) [common]
121 00:56:04.667287 end: 1.4 download-retry (duration 00:00:08) [common]
122 00:56:04.667414 start: 1.5 download-retry (timeout 00:09:48) [common]
123 00:56:04.667537 start: 1.5.1 http-download (timeout 00:09:48) [common]
124 00:56:04.667755 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:56:04.667860 saving as /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/modules/modules.tar
126 00:56:04.667983 total size: 8625444 (8 MB)
127 00:56:04.668079 Using unxz to decompress xz
128 00:56:04.938850 progress 0 % (0 MB)
129 00:56:04.967105 progress 5 % (0 MB)
130 00:56:04.995279 progress 10 % (0 MB)
131 00:56:05.019139 progress 15 % (1 MB)
132 00:56:05.043541 progress 20 % (1 MB)
133 00:56:05.067655 progress 25 % (2 MB)
134 00:56:05.094118 progress 30 % (2 MB)
135 00:56:05.120738 progress 35 % (2 MB)
136 00:56:05.144414 progress 40 % (3 MB)
137 00:56:05.169163 progress 45 % (3 MB)
138 00:56:05.195176 progress 50 % (4 MB)
139 00:56:05.219998 progress 55 % (4 MB)
140 00:56:05.245694 progress 60 % (4 MB)
141 00:56:05.274786 progress 65 % (5 MB)
142 00:56:05.301920 progress 70 % (5 MB)
143 00:56:05.327051 progress 75 % (6 MB)
144 00:56:05.355300 progress 80 % (6 MB)
145 00:56:05.382694 progress 85 % (7 MB)
146 00:56:05.408461 progress 90 % (7 MB)
147 00:56:05.440040 progress 95 % (7 MB)
148 00:56:05.468368 progress 100 % (8 MB)
149 00:56:05.473317 8 MB downloaded in 0.81 s (10.21 MB/s)
150 00:56:05.473659 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:56:05.474055 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:56:05.474188 start: 1.6 prepare-tftp-overlay (timeout 00:09:47) [common]
154 00:56:05.474322 start: 1.6.1 extract-nfsrootfs (timeout 00:09:47) [common]
155 00:56:09.041331 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr
156 00:56:09.041545 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 00:56:09.041645 start: 1.6.2 lava-overlay (timeout 00:09:44) [common]
158 00:56:09.041821 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc
159 00:56:09.041950 makedir: /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin
160 00:56:09.042050 makedir: /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/tests
161 00:56:09.042147 makedir: /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/results
162 00:56:09.042251 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-add-keys
163 00:56:09.042403 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-add-sources
164 00:56:09.042533 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-background-process-start
165 00:56:09.042661 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-background-process-stop
166 00:56:09.042786 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-common-functions
167 00:56:09.042909 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-echo-ipv4
168 00:56:09.043033 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-install-packages
169 00:56:09.043156 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-installed-packages
170 00:56:09.043278 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-os-build
171 00:56:09.043403 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-probe-channel
172 00:56:09.043527 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-probe-ip
173 00:56:09.043651 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-target-ip
174 00:56:09.043774 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-target-mac
175 00:56:09.043897 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-target-storage
176 00:56:09.044022 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-case
177 00:56:09.044147 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-event
178 00:56:09.044273 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-feedback
179 00:56:09.044396 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-raise
180 00:56:09.044517 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-reference
181 00:56:09.044640 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-runner
182 00:56:09.044769 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-set
183 00:56:09.044891 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-test-shell
184 00:56:09.045017 Updating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-add-keys (debian)
185 00:56:09.045169 Updating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-add-sources (debian)
186 00:56:09.045307 Updating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-install-packages (debian)
187 00:56:09.045443 Updating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-installed-packages (debian)
188 00:56:09.045579 Updating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/bin/lava-os-build (debian)
189 00:56:09.045697 Creating /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/environment
190 00:56:09.045790 LAVA metadata
191 00:56:09.045860 - LAVA_JOB_ID=12571063
192 00:56:09.045921 - LAVA_DISPATCHER_IP=192.168.201.1
193 00:56:09.046024 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 00:56:09.046089 skipped lava-vland-overlay
195 00:56:09.046162 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 00:56:09.046250 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 00:56:09.046310 skipped lava-multinode-overlay
198 00:56:09.046380 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 00:56:09.046456 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 00:56:09.046527 Loading test definitions
201 00:56:09.046614 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 00:56:09.046684 Using /lava-12571063 at stage 0
203 00:56:09.046965 uuid=12571063_1.6.2.3.1 testdef=None
204 00:56:09.047051 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 00:56:09.047134 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 00:56:09.047583 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 00:56:09.047798 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 00:56:09.048346 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 00:56:09.048571 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 00:56:09.049250 runner path: /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/0/tests/0_timesync-off test_uuid 12571063_1.6.2.3.1
213 00:56:09.049402 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 00:56:09.049622 start: 1.6.2.3.5 git-repo-action (timeout 00:09:44) [common]
216 00:56:09.049692 Using /lava-12571063 at stage 0
217 00:56:09.049786 Fetching tests from https://github.com/kernelci/test-definitions.git
218 00:56:09.049863 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/0/tests/1_kselftest-tpm2'
219 00:56:12.324448 Running '/usr/bin/git checkout kernelci.org
220 00:56:12.473864 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 00:56:12.474632 uuid=12571063_1.6.2.3.5 testdef=None
222 00:56:12.474798 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 00:56:12.475088 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 00:56:12.475849 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 00:56:12.476085 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 00:56:12.477119 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 00:56:12.477352 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 00:56:12.478277 runner path: /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/0/tests/1_kselftest-tpm2 test_uuid 12571063_1.6.2.3.5
232 00:56:12.478370 BOARD='mt8192-asurada-spherion-r0'
233 00:56:12.478434 BRANCH='cip'
234 00:56:12.478492 SKIPFILE='/dev/null'
235 00:56:12.478548 SKIP_INSTALL='True'
236 00:56:12.478601 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 00:56:12.478657 TST_CASENAME=''
238 00:56:12.478710 TST_CMDFILES='tpm2'
239 00:56:12.478851 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 00:56:12.479049 Creating lava-test-runner.conf files
242 00:56:12.479111 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571063/lava-overlay-uhsdjddc/lava-12571063/0 for stage 0
243 00:56:12.479203 - 0_timesync-off
244 00:56:12.479271 - 1_kselftest-tpm2
245 00:56:12.479364 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 00:56:12.479454 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 00:56:20.181833 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 00:56:20.182003 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 00:56:20.182095 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 00:56:20.182201 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 00:56:20.182308 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 00:56:20.303969 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 00:56:20.304360 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 00:56:20.304477 extracting modules file /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr
255 00:56:20.529343 extracting modules file /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571063/extract-overlay-ramdisk-3m7cioen/ramdisk
256 00:56:20.754106 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 00:56:20.754273 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 00:56:20.754363 [common] Applying overlay to NFS
259 00:56:20.754430 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571063/compress-overlay-07icmahz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr
260 00:56:21.669508 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 00:56:21.669663 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 00:56:21.669756 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 00:56:21.669847 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 00:56:21.669927 Building ramdisk /var/lib/lava/dispatcher/tmp/12571063/extract-overlay-ramdisk-3m7cioen/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571063/extract-overlay-ramdisk-3m7cioen/ramdisk
265 00:56:22.011544 >> 119414 blocks
266 00:56:23.940056 rename /var/lib/lava/dispatcher/tmp/12571063/extract-overlay-ramdisk-3m7cioen/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/ramdisk/ramdisk.cpio.gz
267 00:56:23.940494 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 00:56:23.940614 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 00:56:23.940718 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 00:56:23.940875 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/kernel/Image'
271 00:56:36.635409 Returned 0 in 12 seconds
272 00:56:36.736054 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/kernel/image.itb
273 00:56:37.103849 output: FIT description: Kernel Image image with one or more FDT blobs
274 00:56:37.104256 output: Created: Fri Jan 19 00:56:37 2024
275 00:56:37.104362 output: Image 0 (kernel-1)
276 00:56:37.104460 output: Description:
277 00:56:37.104555 output: Created: Fri Jan 19 00:56:37 2024
278 00:56:37.104649 output: Type: Kernel Image
279 00:56:37.104749 output: Compression: lzma compressed
280 00:56:37.104815 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
281 00:56:37.104875 output: Architecture: AArch64
282 00:56:37.104937 output: OS: Linux
283 00:56:37.104998 output: Load Address: 0x00000000
284 00:56:37.105064 output: Entry Point: 0x00000000
285 00:56:37.105123 output: Hash algo: crc32
286 00:56:37.105182 output: Hash value: a52aa383
287 00:56:37.105240 output: Image 1 (fdt-1)
288 00:56:37.105303 output: Description: mt8192-asurada-spherion-r0
289 00:56:37.105359 output: Created: Fri Jan 19 00:56:37 2024
290 00:56:37.105413 output: Type: Flat Device Tree
291 00:56:37.105468 output: Compression: uncompressed
292 00:56:37.105527 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 00:56:37.105587 output: Architecture: AArch64
294 00:56:37.105641 output: Hash algo: crc32
295 00:56:37.105695 output: Hash value: cc4352de
296 00:56:37.105751 output: Image 2 (ramdisk-1)
297 00:56:37.105809 output: Description: unavailable
298 00:56:37.105864 output: Created: Fri Jan 19 00:56:37 2024
299 00:56:37.105918 output: Type: RAMDisk Image
300 00:56:37.105972 output: Compression: Unknown Compression
301 00:56:37.106030 output: Data Size: 17800094 Bytes = 17382.90 KiB = 16.98 MiB
302 00:56:37.106085 output: Architecture: AArch64
303 00:56:37.106144 output: OS: Linux
304 00:56:37.106199 output: Load Address: unavailable
305 00:56:37.106259 output: Entry Point: unavailable
306 00:56:37.106343 output: Hash algo: crc32
307 00:56:37.106422 output: Hash value: f836fbb1
308 00:56:37.106482 output: Default Configuration: 'conf-1'
309 00:56:37.106566 output: Configuration 0 (conf-1)
310 00:56:37.106649 output: Description: mt8192-asurada-spherion-r0
311 00:56:37.106718 output: Kernel: kernel-1
312 00:56:37.106773 output: Init Ramdisk: ramdisk-1
313 00:56:37.106826 output: FDT: fdt-1
314 00:56:37.106878 output: Loadables: kernel-1
315 00:56:37.106948 output:
316 00:56:37.107211 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 00:56:37.107343 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 00:56:37.107496 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 00:56:37.107628 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 00:56:37.107748 No LXC device requested
321 00:56:37.107861 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 00:56:37.107991 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 00:56:37.108101 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 00:56:37.108211 Checking files for TFTP limit of 4294967296 bytes.
325 00:56:37.108933 end: 1 tftp-deploy (duration 00:00:44) [common]
326 00:56:37.109069 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 00:56:37.109208 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 00:56:37.109392 substitutions:
329 00:56:37.109493 - {DTB}: 12571063/tftp-deploy-81zhmeaq/dtb/mt8192-asurada-spherion-r0.dtb
330 00:56:37.109587 - {INITRD}: 12571063/tftp-deploy-81zhmeaq/ramdisk/ramdisk.cpio.gz
331 00:56:37.109690 - {KERNEL}: 12571063/tftp-deploy-81zhmeaq/kernel/Image
332 00:56:37.109779 - {LAVA_MAC}: None
333 00:56:37.109879 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr
334 00:56:37.109968 - {NFS_SERVER_IP}: 192.168.201.1
335 00:56:37.110055 - {PRESEED_CONFIG}: None
336 00:56:37.110152 - {PRESEED_LOCAL}: None
337 00:56:37.110238 - {RAMDISK}: 12571063/tftp-deploy-81zhmeaq/ramdisk/ramdisk.cpio.gz
338 00:56:37.110332 - {ROOT_PART}: None
339 00:56:37.110397 - {ROOT}: None
340 00:56:37.110453 - {SERVER_IP}: 192.168.201.1
341 00:56:37.110508 - {TEE}: None
342 00:56:37.110580 Parsed boot commands:
343 00:56:37.110642 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 00:56:37.110918 Parsed boot commands: tftpboot 192.168.201.1 12571063/tftp-deploy-81zhmeaq/kernel/image.itb 12571063/tftp-deploy-81zhmeaq/kernel/cmdline
345 00:56:37.111014 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 00:56:37.111129 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 00:56:37.111224 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 00:56:37.111327 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 00:56:37.111403 Not connected, no need to disconnect.
350 00:56:37.111480 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 00:56:37.111583 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 00:56:37.111655 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 00:56:37.116027 Setting prompt string to ['lava-test: # ']
354 00:56:37.116449 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 00:56:37.116607 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 00:56:37.116759 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 00:56:37.116895 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 00:56:37.117233 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 00:56:42.255563 >> Command sent successfully.
360 00:56:42.257963 Returned 0 in 5 seconds
361 00:56:42.358345 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 00:56:42.358800 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 00:56:42.358950 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 00:56:42.359084 Setting prompt string to 'Starting depthcharge on Spherion...'
366 00:56:42.359196 Changing prompt to 'Starting depthcharge on Spherion...'
367 00:56:42.359308 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 00:56:42.359712 [Enter `^Ec?' for help]
369 00:56:42.543141
370 00:56:42.543312
371 00:56:42.543423 F0: 102B 0000
372 00:56:42.543520
373 00:56:42.543609 F3: 1001 0000 [0200]
374 00:56:42.543709
375 00:56:42.545939 F3: 1001 0000
376 00:56:42.546037
377 00:56:42.546121 F7: 102D 0000
378 00:56:42.546182
379 00:56:42.546239 F1: 0000 0000
380 00:56:42.550062
381 00:56:42.550144 V0: 0000 0000 [0001]
382 00:56:42.550218
383 00:56:42.550307 00: 0007 8000
384 00:56:42.550401
385 00:56:42.553611 01: 0000 0000
386 00:56:42.553702
387 00:56:42.553767 BP: 0C00 0209 [0000]
388 00:56:42.553832
389 00:56:42.557209 G0: 1182 0000
390 00:56:42.557310
391 00:56:42.557411 EC: 0000 0021 [4000]
392 00:56:42.557489
393 00:56:42.561413 S7: 0000 0000 [0000]
394 00:56:42.561487
395 00:56:42.561587 CC: 0000 0000 [0001]
396 00:56:42.561678
397 00:56:42.563920 T0: 0000 0040 [010F]
398 00:56:42.564034
399 00:56:42.564131 Jump to BL
400 00:56:42.564203
401 00:56:42.589116
402 00:56:42.589236
403 00:56:42.589334
404 00:56:42.595937 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 00:56:42.599688 ARM64: Exception handlers installed.
406 00:56:42.603005 ARM64: Testing exception
407 00:56:42.606056 ARM64: Done test exception
408 00:56:42.612937 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 00:56:42.623339 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 00:56:42.629576 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 00:56:42.640308 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 00:56:42.647054 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 00:56:42.656770 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 00:56:42.668057 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 00:56:42.673885 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 00:56:42.692048 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 00:56:42.695684 WDT: Last reset was cold boot
418 00:56:42.698568 SPI1(PAD0) initialized at 2873684 Hz
419 00:56:42.701919 SPI5(PAD0) initialized at 992727 Hz
420 00:56:42.705509 VBOOT: Loading verstage.
421 00:56:42.712659 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 00:56:42.715723 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 00:56:42.719486 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 00:56:42.722128 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 00:56:42.729954 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 00:56:42.736269 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 00:56:42.746970 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 00:56:42.747048
429 00:56:42.747112
430 00:56:42.757057 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 00:56:42.760384 ARM64: Exception handlers installed.
432 00:56:42.764887 ARM64: Testing exception
433 00:56:42.764962 ARM64: Done test exception
434 00:56:42.770359 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 00:56:42.774293 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 00:56:42.787986 Probing TPM: . done!
437 00:56:42.788095 TPM ready after 0 ms
438 00:56:42.795226 Connected to device vid:did:rid of 1ae0:0028:00
439 00:56:42.801670 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 00:56:42.805239 Initialized TPM device CR50 revision 0
441 00:56:42.857329 tlcl_send_startup: Startup return code is 0
442 00:56:42.857436 TPM: setup succeeded
443 00:56:42.867855 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 00:56:42.876852 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 00:56:42.884383 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 00:56:42.896435 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 00:56:42.899528 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 00:56:42.902955 in-header: 03 07 00 00 08 00 00 00
449 00:56:42.906253 in-data: aa e4 47 04 13 02 00 00
450 00:56:42.909645 Chrome EC: UHEPI supported
451 00:56:42.916624 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 00:56:42.919657 in-header: 03 9d 00 00 08 00 00 00
453 00:56:42.922997 in-data: 10 20 20 08 00 00 00 00
454 00:56:42.923079 Phase 1
455 00:56:42.930519 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 00:56:42.933067 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 00:56:42.939355 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 00:56:42.943082 Recovery requested (1009000e)
459 00:56:42.947166 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 00:56:42.956153 tlcl_extend: response is 0
461 00:56:42.964954 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 00:56:42.969083 tlcl_extend: response is 0
463 00:56:42.976004 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 00:56:42.996880 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 00:56:43.004077 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 00:56:43.004179
467 00:56:43.004273
468 00:56:43.013742 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 00:56:43.016593 ARM64: Exception handlers installed.
470 00:56:43.020262 ARM64: Testing exception
471 00:56:43.020360 ARM64: Done test exception
472 00:56:43.042243 pmic_efuse_setting: Set efuses in 11 msecs
473 00:56:43.045451 pmwrap_interface_init: Select PMIF_VLD_RDY
474 00:56:43.053143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 00:56:43.055843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 00:56:43.059609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 00:56:43.067628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 00:56:43.071152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 00:56:43.074217 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 00:56:43.081160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 00:56:43.084313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 00:56:43.090649 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 00:56:43.094129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 00:56:43.101261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 00:56:43.104279 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 00:56:43.108008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 00:56:43.114915 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 00:56:43.120906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 00:56:43.127929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 00:56:43.131414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 00:56:43.138593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 00:56:43.141172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 00:56:43.148008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 00:56:43.154776 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 00:56:43.158120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 00:56:43.165210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 00:56:43.171772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 00:56:43.174905 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 00:56:43.181123 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 00:56:43.187769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 00:56:43.191581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 00:56:43.198098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 00:56:43.201542 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 00:56:43.204696 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 00:56:43.211588 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 00:56:43.214855 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 00:56:43.221070 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 00:56:43.224500 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 00:56:43.231158 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 00:56:43.237930 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 00:56:43.241233 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 00:56:43.245592 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 00:56:43.251604 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 00:56:43.254559 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 00:56:43.258202 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 00:56:43.264839 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 00:56:43.267823 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 00:56:43.271236 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 00:56:43.278131 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 00:56:43.280918 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 00:56:43.284924 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 00:56:43.287785 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 00:56:43.295316 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 00:56:43.298234 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 00:56:43.304884 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 00:56:43.314289 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 00:56:43.317406 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 00:56:43.327468 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 00:56:43.334401 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 00:56:43.341109 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 00:56:43.344046 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 00:56:43.348546 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 00:56:43.354766 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x10
534 00:56:43.362098 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 00:56:43.364776 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 00:56:43.371423 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 00:56:43.379127 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 00:56:43.389113 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 00:56:43.398971 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 00:56:43.408034 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 00:56:43.417588 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 00:56:43.427208 [RTC]rtc_get_frequency_meter,154: input=16, output=788
543 00:56:43.436341 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 00:56:43.439865 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 00:56:43.447499 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 00:56:43.450243 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 00:56:43.453528 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 00:56:43.460989 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 00:56:43.463208 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 00:56:43.466652 ADC[4]: Raw value=670432 ID=5
551 00:56:43.466733 ADC[3]: Raw value=212917 ID=1
552 00:56:43.470892 RAM Code: 0x51
553 00:56:43.473161 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 00:56:43.480072 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 00:56:43.486771 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 00:56:43.493344 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 00:56:43.496590 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 00:56:43.500097 in-header: 03 07 00 00 08 00 00 00
559 00:56:43.503462 in-data: aa e4 47 04 13 02 00 00
560 00:56:43.506921 Chrome EC: UHEPI supported
561 00:56:43.513495 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 00:56:43.517207 in-header: 03 d5 00 00 08 00 00 00
563 00:56:43.519984 in-data: 98 20 60 08 00 00 00 00
564 00:56:43.523646 MRC: failed to locate region type 0.
565 00:56:43.530218 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 00:56:43.530299 DRAM-K: Running full calibration
567 00:56:43.536571 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 00:56:43.540226 header.status = 0x0
569 00:56:43.543205 header.version = 0x6 (expected: 0x6)
570 00:56:43.546620 header.size = 0xd00 (expected: 0xd00)
571 00:56:43.546702 header.flags = 0x0
572 00:56:43.553640 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 00:56:43.571377 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 00:56:43.578265 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 00:56:43.581252 dram_init: ddr_geometry: 0
576 00:56:43.584618 [EMI] MDL number = 0
577 00:56:43.584691 [EMI] Get MDL freq = 0
578 00:56:43.588328 dram_init: ddr_type: 0
579 00:56:43.588408 is_discrete_lpddr4: 1
580 00:56:43.592012 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 00:56:43.592082
582 00:56:43.592142
583 00:56:43.595541 [Bian_co] ETT version 0.0.0.1
584 00:56:43.598353 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 00:56:43.598427
586 00:56:43.605416 dramc_set_vcore_voltage set vcore to 650000
587 00:56:43.605492 Read voltage for 800, 4
588 00:56:43.608784 Vio18 = 0
589 00:56:43.608855 Vcore = 650000
590 00:56:43.608916 Vdram = 0
591 00:56:43.611791 Vddq = 0
592 00:56:43.611868 Vmddr = 0
593 00:56:43.614827 dram_init: config_dvfs: 1
594 00:56:43.618445 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 00:56:43.625041 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 00:56:43.628480 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 00:56:43.631436 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 00:56:43.634918 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 00:56:43.638254 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 00:56:43.641907 MEM_TYPE=3, freq_sel=18
601 00:56:43.645126 sv_algorithm_assistance_LP4_1600
602 00:56:43.647984 ============ PULL DRAM RESETB DOWN ============
603 00:56:43.651725 ========== PULL DRAM RESETB DOWN end =========
604 00:56:43.658428 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 00:56:43.661426 ===================================
606 00:56:43.661509 LPDDR4 DRAM CONFIGURATION
607 00:56:43.665673 ===================================
608 00:56:43.668250 EX_ROW_EN[0] = 0x0
609 00:56:43.672327 EX_ROW_EN[1] = 0x0
610 00:56:43.672409 LP4Y_EN = 0x0
611 00:56:43.675312 WORK_FSP = 0x0
612 00:56:43.675395 WL = 0x2
613 00:56:43.678247 RL = 0x2
614 00:56:43.678358 BL = 0x2
615 00:56:43.681427 RPST = 0x0
616 00:56:43.681506 RD_PRE = 0x0
617 00:56:43.685047 WR_PRE = 0x1
618 00:56:43.685121 WR_PST = 0x0
619 00:56:43.688585 DBI_WR = 0x0
620 00:56:43.688681 DBI_RD = 0x0
621 00:56:43.691377 OTF = 0x1
622 00:56:43.694961 ===================================
623 00:56:43.698863 ===================================
624 00:56:43.698960 ANA top config
625 00:56:43.701630 ===================================
626 00:56:43.704645 DLL_ASYNC_EN = 0
627 00:56:43.707910 ALL_SLAVE_EN = 1
628 00:56:43.711606 NEW_RANK_MODE = 1
629 00:56:43.711691 DLL_IDLE_MODE = 1
630 00:56:43.714787 LP45_APHY_COMB_EN = 1
631 00:56:43.718120 TX_ODT_DIS = 1
632 00:56:43.721624 NEW_8X_MODE = 1
633 00:56:43.725245 ===================================
634 00:56:43.728207 ===================================
635 00:56:43.728353 data_rate = 1600
636 00:56:43.731707 CKR = 1
637 00:56:43.735082 DQ_P2S_RATIO = 8
638 00:56:43.738385 ===================================
639 00:56:43.741889 CA_P2S_RATIO = 8
640 00:56:43.744981 DQ_CA_OPEN = 0
641 00:56:43.748252 DQ_SEMI_OPEN = 0
642 00:56:43.748359 CA_SEMI_OPEN = 0
643 00:56:43.751308 CA_FULL_RATE = 0
644 00:56:43.754979 DQ_CKDIV4_EN = 1
645 00:56:43.758088 CA_CKDIV4_EN = 1
646 00:56:43.762112 CA_PREDIV_EN = 0
647 00:56:43.765015 PH8_DLY = 0
648 00:56:43.765094 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 00:56:43.767995 DQ_AAMCK_DIV = 4
650 00:56:43.771385 CA_AAMCK_DIV = 4
651 00:56:43.775010 CA_ADMCK_DIV = 4
652 00:56:43.778307 DQ_TRACK_CA_EN = 0
653 00:56:43.781353 CA_PICK = 800
654 00:56:43.781442 CA_MCKIO = 800
655 00:56:43.785305 MCKIO_SEMI = 0
656 00:56:43.788325 PLL_FREQ = 3068
657 00:56:43.791252 DQ_UI_PI_RATIO = 32
658 00:56:43.794698 CA_UI_PI_RATIO = 0
659 00:56:43.798701 ===================================
660 00:56:43.801662 ===================================
661 00:56:43.805159 memory_type:LPDDR4
662 00:56:43.805251 GP_NUM : 10
663 00:56:43.808693 SRAM_EN : 1
664 00:56:43.808828 MD32_EN : 0
665 00:56:43.811916 ===================================
666 00:56:43.815161 [ANA_INIT] >>>>>>>>>>>>>>
667 00:56:43.818299 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 00:56:43.821412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 00:56:43.824880 ===================================
670 00:56:43.828300 data_rate = 1600,PCW = 0X7600
671 00:56:43.831285 ===================================
672 00:56:43.834819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 00:56:43.841507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 00:56:43.844960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 00:56:43.851184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 00:56:43.854539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 00:56:43.857817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 00:56:43.857909 [ANA_INIT] flow start
679 00:56:43.861658 [ANA_INIT] PLL >>>>>>>>
680 00:56:43.864383 [ANA_INIT] PLL <<<<<<<<
681 00:56:43.864475 [ANA_INIT] MIDPI >>>>>>>>
682 00:56:43.868177 [ANA_INIT] MIDPI <<<<<<<<
683 00:56:43.871246 [ANA_INIT] DLL >>>>>>>>
684 00:56:43.871332 [ANA_INIT] flow end
685 00:56:43.878424 ============ LP4 DIFF to SE enter ============
686 00:56:43.882095 ============ LP4 DIFF to SE exit ============
687 00:56:43.882173 [ANA_INIT] <<<<<<<<<<<<<
688 00:56:43.884543 [Flow] Enable top DCM control >>>>>
689 00:56:43.888458 [Flow] Enable top DCM control <<<<<
690 00:56:43.891250 Enable DLL master slave shuffle
691 00:56:43.898083 ==============================================================
692 00:56:43.901674 Gating Mode config
693 00:56:43.904412 ==============================================================
694 00:56:43.908009 Config description:
695 00:56:43.917425 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 00:56:43.924768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 00:56:43.927598 SELPH_MODE 0: By rank 1: By Phase
698 00:56:43.934596 ==============================================================
699 00:56:43.937859 GAT_TRACK_EN = 1
700 00:56:43.941541 RX_GATING_MODE = 2
701 00:56:43.944342 RX_GATING_TRACK_MODE = 2
702 00:56:43.944417 SELPH_MODE = 1
703 00:56:43.947482 PICG_EARLY_EN = 1
704 00:56:43.951598 VALID_LAT_VALUE = 1
705 00:56:43.958297 ==============================================================
706 00:56:43.961028 Enter into Gating configuration >>>>
707 00:56:43.964916 Exit from Gating configuration <<<<
708 00:56:43.967442 Enter into DVFS_PRE_config >>>>>
709 00:56:43.977700 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 00:56:43.980991 Exit from DVFS_PRE_config <<<<<
711 00:56:43.984661 Enter into PICG configuration >>>>
712 00:56:43.987833 Exit from PICG configuration <<<<
713 00:56:43.991220 [RX_INPUT] configuration >>>>>
714 00:56:43.994086 [RX_INPUT] configuration <<<<<
715 00:56:43.997414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 00:56:44.004542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 00:56:44.011381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 00:56:44.017759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 00:56:44.021002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 00:56:44.027554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 00:56:44.030697 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 00:56:44.037438 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 00:56:44.040785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 00:56:44.044052 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 00:56:44.047729 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 00:56:44.054211 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 00:56:44.057562 ===================================
728 00:56:44.057662 LPDDR4 DRAM CONFIGURATION
729 00:56:44.060863 ===================================
730 00:56:44.064466 EX_ROW_EN[0] = 0x0
731 00:56:44.067313 EX_ROW_EN[1] = 0x0
732 00:56:44.067398 LP4Y_EN = 0x0
733 00:56:44.071093 WORK_FSP = 0x0
734 00:56:44.071191 WL = 0x2
735 00:56:44.074190 RL = 0x2
736 00:56:44.074272 BL = 0x2
737 00:56:44.077481 RPST = 0x0
738 00:56:44.077565 RD_PRE = 0x0
739 00:56:44.081073 WR_PRE = 0x1
740 00:56:44.081158 WR_PST = 0x0
741 00:56:44.083770 DBI_WR = 0x0
742 00:56:44.083855 DBI_RD = 0x0
743 00:56:44.087596 OTF = 0x1
744 00:56:44.090697 ===================================
745 00:56:44.094084 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 00:56:44.097624 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 00:56:44.104188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 00:56:44.107116 ===================================
749 00:56:44.107206 LPDDR4 DRAM CONFIGURATION
750 00:56:44.110698 ===================================
751 00:56:44.114022 EX_ROW_EN[0] = 0x10
752 00:56:44.117285 EX_ROW_EN[1] = 0x0
753 00:56:44.117365 LP4Y_EN = 0x0
754 00:56:44.120291 WORK_FSP = 0x0
755 00:56:44.120370 WL = 0x2
756 00:56:44.123541 RL = 0x2
757 00:56:44.123615 BL = 0x2
758 00:56:44.128161 RPST = 0x0
759 00:56:44.128279 RD_PRE = 0x0
760 00:56:44.130805 WR_PRE = 0x1
761 00:56:44.130878 WR_PST = 0x0
762 00:56:44.133773 DBI_WR = 0x0
763 00:56:44.133876 DBI_RD = 0x0
764 00:56:44.137328 OTF = 0x1
765 00:56:44.140699 ===================================
766 00:56:44.147557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 00:56:44.149984 nWR fixed to 40
768 00:56:44.150061 [ModeRegInit_LP4] CH0 RK0
769 00:56:44.153498 [ModeRegInit_LP4] CH0 RK1
770 00:56:44.157289 [ModeRegInit_LP4] CH1 RK0
771 00:56:44.160022 [ModeRegInit_LP4] CH1 RK1
772 00:56:44.160101 match AC timing 12
773 00:56:44.163779 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 00:56:44.170361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 00:56:44.173774 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 00:56:44.176989 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 00:56:44.183719 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 00:56:44.183799 [EMI DOE] emi_dcm 0
779 00:56:44.190611 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 00:56:44.190710 ==
781 00:56:44.193941 Dram Type= 6, Freq= 0, CH_0, rank 0
782 00:56:44.196930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 00:56:44.197031 ==
784 00:56:44.203493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 00:56:44.207126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 00:56:44.217130 [CA 0] Center 37 (7~68) winsize 62
787 00:56:44.220504 [CA 1] Center 37 (7~68) winsize 62
788 00:56:44.223620 [CA 2] Center 35 (5~66) winsize 62
789 00:56:44.227619 [CA 3] Center 35 (4~66) winsize 63
790 00:56:44.230189 [CA 4] Center 34 (4~65) winsize 62
791 00:56:44.233576 [CA 5] Center 34 (4~64) winsize 61
792 00:56:44.233658
793 00:56:44.237607 [CmdBusTrainingLP45] Vref(ca) range 1: 30
794 00:56:44.237721
795 00:56:44.240592 [CATrainingPosCal] consider 1 rank data
796 00:56:44.243761 u2DelayCellTimex100 = 270/100 ps
797 00:56:44.247215 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 00:56:44.250552 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 00:56:44.257480 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 00:56:44.260389 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
801 00:56:44.263478 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 00:56:44.267366 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 00:56:44.267471
804 00:56:44.270487 CA PerBit enable=1, Macro0, CA PI delay=34
805 00:56:44.270584
806 00:56:44.274087 [CBTSetCACLKResult] CA Dly = 34
807 00:56:44.274185 CS Dly: 5 (0~36)
808 00:56:44.274280 ==
809 00:56:44.277091 Dram Type= 6, Freq= 0, CH_0, rank 1
810 00:56:44.283802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 00:56:44.283900 ==
812 00:56:44.287780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 00:56:44.293484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 00:56:44.303086 [CA 0] Center 37 (7~68) winsize 62
815 00:56:44.306369 [CA 1] Center 37 (6~68) winsize 63
816 00:56:44.309266 [CA 2] Center 35 (4~66) winsize 63
817 00:56:44.312981 [CA 3] Center 35 (4~66) winsize 63
818 00:56:44.316308 [CA 4] Center 33 (3~64) winsize 62
819 00:56:44.319999 [CA 5] Center 34 (3~65) winsize 63
820 00:56:44.320107
821 00:56:44.324272 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 00:56:44.324354
823 00:56:44.326839 [CATrainingPosCal] consider 2 rank data
824 00:56:44.330265 u2DelayCellTimex100 = 270/100 ps
825 00:56:44.333338 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 00:56:44.336929 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 00:56:44.343188 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 00:56:44.346553 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
829 00:56:44.349240 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 00:56:44.352583 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 00:56:44.352722
832 00:56:44.356684 CA PerBit enable=1, Macro0, CA PI delay=34
833 00:56:44.356794
834 00:56:44.359866 [CBTSetCACLKResult] CA Dly = 34
835 00:56:44.359944 CS Dly: 6 (0~38)
836 00:56:44.360007
837 00:56:44.362596 ----->DramcWriteLeveling(PI) begin...
838 00:56:44.366185 ==
839 00:56:44.369474 Dram Type= 6, Freq= 0, CH_0, rank 0
840 00:56:44.372900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 00:56:44.372971 ==
842 00:56:44.376616 Write leveling (Byte 0): 29 => 29
843 00:56:44.379865 Write leveling (Byte 1): 30 => 30
844 00:56:44.382818 DramcWriteLeveling(PI) end<-----
845 00:56:44.382892
846 00:56:44.382953 ==
847 00:56:44.386210 Dram Type= 6, Freq= 0, CH_0, rank 0
848 00:56:44.389434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 00:56:44.389516 ==
850 00:56:44.392553 [Gating] SW mode calibration
851 00:56:44.399935 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 00:56:44.402930 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 00:56:44.409398 0 6 0 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 1)
854 00:56:44.412548 0 6 4 | B1->B0 | 2929 2525 | 1 0 | (1 0) (0 0)
855 00:56:44.416181 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 00:56:44.423256 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 00:56:44.426132 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 00:56:44.429253 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 00:56:44.436913 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:56:44.439522 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:56:44.442563 0 7 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
862 00:56:44.449440 0 7 4 | B1->B0 | 3c3c 4444 | 1 0 | (0 0) (0 0)
863 00:56:44.452632 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 00:56:44.456052 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 00:56:44.463045 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 00:56:44.465829 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 00:56:44.469058 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:56:44.476090 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:56:44.479190 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 00:56:44.482448 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 00:56:44.489441 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 00:56:44.492240 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 00:56:44.495954 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 00:56:44.502209 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:56:44.505913 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:56:44.509414 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:56:44.512709 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:56:44.519311 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:56:44.522541 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:56:44.525932 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:56:44.532566 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:56:44.536038 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:56:44.539035 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:56:44.545893 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
885 00:56:44.549129 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:56:44.552452 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 00:56:44.556051 Total UI for P1: 0, mck2ui 16
888 00:56:44.559026 best dqsien dly found for B0: ( 0, 10, 2)
889 00:56:44.562772 Total UI for P1: 0, mck2ui 16
890 00:56:44.565728 best dqsien dly found for B1: ( 0, 10, 2)
891 00:56:44.569725 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 00:56:44.572611 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
893 00:56:44.572726
894 00:56:44.579276 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 00:56:44.582722 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
896 00:56:44.582808 [Gating] SW calibration Done
897 00:56:44.585981 ==
898 00:56:44.586073 Dram Type= 6, Freq= 0, CH_0, rank 0
899 00:56:44.593112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 00:56:44.593220 ==
901 00:56:44.593315 RX Vref Scan: 0
902 00:56:44.593410
903 00:56:44.596842 RX Vref 0 -> 0, step: 1
904 00:56:44.596944
905 00:56:44.600310 RX Delay -130 -> 252, step: 16
906 00:56:44.603233 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 00:56:44.606173 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 00:56:44.610224 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 00:56:44.613304 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 00:56:44.619513 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 00:56:44.622919 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 00:56:44.626352 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 00:56:44.630174 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 00:56:44.633069 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 00:56:44.639871 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 00:56:44.643057 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 00:56:44.646893 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 00:56:44.650043 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 00:56:44.652976 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
920 00:56:44.659936 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 00:56:44.663063 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 00:56:44.663145 ==
923 00:56:44.666385 Dram Type= 6, Freq= 0, CH_0, rank 0
924 00:56:44.669549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 00:56:44.669656 ==
926 00:56:44.673271 DQS Delay:
927 00:56:44.673354 DQS0 = 0, DQS1 = 0
928 00:56:44.673463 DQM Delay:
929 00:56:44.676911 DQM0 = 82, DQM1 = 73
930 00:56:44.676994 DQ Delay:
931 00:56:44.679855 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 00:56:44.683228 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 00:56:44.686415 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 00:56:44.689930 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
935 00:56:44.690013
936 00:56:44.690077
937 00:56:44.690137 ==
938 00:56:44.692982 Dram Type= 6, Freq= 0, CH_0, rank 0
939 00:56:44.699441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 00:56:44.699524 ==
941 00:56:44.699589
942 00:56:44.699649
943 00:56:44.699708 TX Vref Scan disable
944 00:56:44.703356 == TX Byte 0 ==
945 00:56:44.706605 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
946 00:56:44.710031 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
947 00:56:44.713447 == TX Byte 1 ==
948 00:56:44.716922 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 00:56:44.720321 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 00:56:44.723073 ==
951 00:56:44.726334 Dram Type= 6, Freq= 0, CH_0, rank 0
952 00:56:44.730014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 00:56:44.730098 ==
954 00:56:44.742213 TX Vref=22, minBit 0, minWin=27, winSum=445
955 00:56:44.745587 TX Vref=24, minBit 2, minWin=27, winSum=448
956 00:56:44.748523 TX Vref=26, minBit 5, minWin=27, winSum=453
957 00:56:44.752287 TX Vref=28, minBit 2, minWin=28, winSum=457
958 00:56:44.755290 TX Vref=30, minBit 0, minWin=28, winSum=454
959 00:56:44.759138 TX Vref=32, minBit 0, minWin=28, winSum=454
960 00:56:44.765428 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
961 00:56:44.765511
962 00:56:44.768750 Final TX Range 1 Vref 28
963 00:56:44.768833
964 00:56:44.768898 ==
965 00:56:44.772590 Dram Type= 6, Freq= 0, CH_0, rank 0
966 00:56:44.775568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 00:56:44.775651 ==
968 00:56:44.775717
969 00:56:44.779409
970 00:56:44.779491 TX Vref Scan disable
971 00:56:44.782040 == TX Byte 0 ==
972 00:56:44.785630 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
973 00:56:44.789366 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
974 00:56:44.792120 == TX Byte 1 ==
975 00:56:44.796426 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 00:56:44.799050 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 00:56:44.799133
978 00:56:44.802537 [DATLAT]
979 00:56:44.802641 Freq=800, CH0 RK0
980 00:56:44.802722
981 00:56:44.805588 DATLAT Default: 0xa
982 00:56:44.805732 0, 0xFFFF, sum = 0
983 00:56:44.808899 1, 0xFFFF, sum = 0
984 00:56:44.808982 2, 0xFFFF, sum = 0
985 00:56:44.812201 3, 0xFFFF, sum = 0
986 00:56:44.812287 4, 0xFFFF, sum = 0
987 00:56:44.815225 5, 0xFFFF, sum = 0
988 00:56:44.815309 6, 0xFFFF, sum = 0
989 00:56:44.818615 7, 0xFFFF, sum = 0
990 00:56:44.818699 8, 0x0, sum = 1
991 00:56:44.822562 9, 0x0, sum = 2
992 00:56:44.822683 10, 0x0, sum = 3
993 00:56:44.825521 11, 0x0, sum = 4
994 00:56:44.825604 best_step = 9
995 00:56:44.825669
996 00:56:44.825731 ==
997 00:56:44.828643 Dram Type= 6, Freq= 0, CH_0, rank 0
998 00:56:44.831895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 00:56:44.835360 ==
1000 00:56:44.835464 RX Vref Scan: 1
1001 00:56:44.835563
1002 00:56:44.838801 Set Vref Range= 32 -> 127
1003 00:56:44.838891
1004 00:56:44.842074 RX Vref 32 -> 127, step: 1
1005 00:56:44.842149
1006 00:56:44.842211 RX Delay -111 -> 252, step: 8
1007 00:56:44.842276
1008 00:56:44.846096 Set Vref, RX VrefLevel [Byte0]: 32
1009 00:56:44.849146 [Byte1]: 32
1010 00:56:44.853218
1011 00:56:44.853315 Set Vref, RX VrefLevel [Byte0]: 33
1012 00:56:44.856689 [Byte1]: 33
1013 00:56:44.860657
1014 00:56:44.860785 Set Vref, RX VrefLevel [Byte0]: 34
1015 00:56:44.863927 [Byte1]: 34
1016 00:56:44.868837
1017 00:56:44.868919 Set Vref, RX VrefLevel [Byte0]: 35
1018 00:56:44.871321 [Byte1]: 35
1019 00:56:44.876562
1020 00:56:44.876688 Set Vref, RX VrefLevel [Byte0]: 36
1021 00:56:44.879103 [Byte1]: 36
1022 00:56:44.883996
1023 00:56:44.884079 Set Vref, RX VrefLevel [Byte0]: 37
1024 00:56:44.886930 [Byte1]: 37
1025 00:56:44.891681
1026 00:56:44.891806 Set Vref, RX VrefLevel [Byte0]: 38
1027 00:56:44.894776 [Byte1]: 38
1028 00:56:44.898777
1029 00:56:44.898858 Set Vref, RX VrefLevel [Byte0]: 39
1030 00:56:44.902377 [Byte1]: 39
1031 00:56:44.907204
1032 00:56:44.907285 Set Vref, RX VrefLevel [Byte0]: 40
1033 00:56:44.909792 [Byte1]: 40
1034 00:56:44.914187
1035 00:56:44.914269 Set Vref, RX VrefLevel [Byte0]: 41
1036 00:56:44.918215 [Byte1]: 41
1037 00:56:44.921447
1038 00:56:44.921527 Set Vref, RX VrefLevel [Byte0]: 42
1039 00:56:44.925138 [Byte1]: 42
1040 00:56:44.929740
1041 00:56:44.929821 Set Vref, RX VrefLevel [Byte0]: 43
1042 00:56:44.932468 [Byte1]: 43
1043 00:56:44.937271
1044 00:56:44.937369 Set Vref, RX VrefLevel [Byte0]: 44
1045 00:56:44.940466 [Byte1]: 44
1046 00:56:44.945124
1047 00:56:44.945205 Set Vref, RX VrefLevel [Byte0]: 45
1048 00:56:44.947758 [Byte1]: 45
1049 00:56:44.952439
1050 00:56:44.952520 Set Vref, RX VrefLevel [Byte0]: 46
1051 00:56:44.955806 [Byte1]: 46
1052 00:56:44.959986
1053 00:56:44.960083 Set Vref, RX VrefLevel [Byte0]: 47
1054 00:56:44.963768 [Byte1]: 47
1055 00:56:44.967713
1056 00:56:44.967794 Set Vref, RX VrefLevel [Byte0]: 48
1057 00:56:44.970794 [Byte1]: 48
1058 00:56:44.975622
1059 00:56:44.975703 Set Vref, RX VrefLevel [Byte0]: 49
1060 00:56:44.979581 [Byte1]: 49
1061 00:56:44.983348
1062 00:56:44.983444 Set Vref, RX VrefLevel [Byte0]: 50
1063 00:56:44.986433 [Byte1]: 50
1064 00:56:44.990839
1065 00:56:44.990921 Set Vref, RX VrefLevel [Byte0]: 51
1066 00:56:44.993943 [Byte1]: 51
1067 00:56:44.998272
1068 00:56:44.998352 Set Vref, RX VrefLevel [Byte0]: 52
1069 00:56:45.001481 [Byte1]: 52
1070 00:56:45.006941
1071 00:56:45.007022 Set Vref, RX VrefLevel [Byte0]: 53
1072 00:56:45.011035 [Byte1]: 53
1073 00:56:45.013560
1074 00:56:45.013655 Set Vref, RX VrefLevel [Byte0]: 54
1075 00:56:45.018009 [Byte1]: 54
1076 00:56:45.020989
1077 00:56:45.021071 Set Vref, RX VrefLevel [Byte0]: 55
1078 00:56:45.024344 [Byte1]: 55
1079 00:56:45.028887
1080 00:56:45.028983 Set Vref, RX VrefLevel [Byte0]: 56
1081 00:56:45.032269 [Byte1]: 56
1082 00:56:45.036372
1083 00:56:45.036470 Set Vref, RX VrefLevel [Byte0]: 57
1084 00:56:45.039898 [Byte1]: 57
1085 00:56:45.044061
1086 00:56:45.044158 Set Vref, RX VrefLevel [Byte0]: 58
1087 00:56:45.047467 [Byte1]: 58
1088 00:56:45.051664
1089 00:56:45.051793 Set Vref, RX VrefLevel [Byte0]: 59
1090 00:56:45.055099 [Byte1]: 59
1091 00:56:45.059633
1092 00:56:45.059716 Set Vref, RX VrefLevel [Byte0]: 60
1093 00:56:45.062548 [Byte1]: 60
1094 00:56:45.066887
1095 00:56:45.066984 Set Vref, RX VrefLevel [Byte0]: 61
1096 00:56:45.070338 [Byte1]: 61
1097 00:56:45.075062
1098 00:56:45.075143 Set Vref, RX VrefLevel [Byte0]: 62
1099 00:56:45.078238 [Byte1]: 62
1100 00:56:45.081999
1101 00:56:45.082079 Set Vref, RX VrefLevel [Byte0]: 63
1102 00:56:45.086420 [Byte1]: 63
1103 00:56:45.089939
1104 00:56:45.090037 Set Vref, RX VrefLevel [Byte0]: 64
1105 00:56:45.093305 [Byte1]: 64
1106 00:56:45.097741
1107 00:56:45.097852 Set Vref, RX VrefLevel [Byte0]: 65
1108 00:56:45.100882 [Byte1]: 65
1109 00:56:45.105378
1110 00:56:45.105460 Set Vref, RX VrefLevel [Byte0]: 66
1111 00:56:45.108715 [Byte1]: 66
1112 00:56:45.112973
1113 00:56:45.113056 Set Vref, RX VrefLevel [Byte0]: 67
1114 00:56:45.116489 [Byte1]: 67
1115 00:56:45.120614
1116 00:56:45.120697 Set Vref, RX VrefLevel [Byte0]: 68
1117 00:56:45.123623 [Byte1]: 68
1118 00:56:45.127957
1119 00:56:45.128078 Set Vref, RX VrefLevel [Byte0]: 69
1120 00:56:45.131941 [Byte1]: 69
1121 00:56:45.135971
1122 00:56:45.136063 Set Vref, RX VrefLevel [Byte0]: 70
1123 00:56:45.139118 [Byte1]: 70
1124 00:56:45.143262
1125 00:56:45.143359 Set Vref, RX VrefLevel [Byte0]: 71
1126 00:56:45.146822 [Byte1]: 71
1127 00:56:45.151163
1128 00:56:45.151237 Set Vref, RX VrefLevel [Byte0]: 72
1129 00:56:45.154644 [Byte1]: 72
1130 00:56:45.159042
1131 00:56:45.159125 Set Vref, RX VrefLevel [Byte0]: 73
1132 00:56:45.162240 [Byte1]: 73
1133 00:56:45.166249
1134 00:56:45.166330 Final RX Vref Byte 0 = 52 to rank0
1135 00:56:45.170457 Final RX Vref Byte 1 = 54 to rank0
1136 00:56:45.173096 Final RX Vref Byte 0 = 52 to rank1
1137 00:56:45.176243 Final RX Vref Byte 1 = 54 to rank1==
1138 00:56:45.180358 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 00:56:45.183361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 00:56:45.186483 ==
1141 00:56:45.186563 DQS Delay:
1142 00:56:45.186627 DQS0 = 0, DQS1 = 0
1143 00:56:45.190653 DQM Delay:
1144 00:56:45.190732 DQM0 = 84, DQM1 = 73
1145 00:56:45.194182 DQ Delay:
1146 00:56:45.194265 DQ0 =80, DQ1 =84, DQ2 =84, DQ3 =80
1147 00:56:45.197422 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1148 00:56:45.199798 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1149 00:56:45.203290 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1150 00:56:45.203372
1151 00:56:45.206588
1152 00:56:45.213674 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1153 00:56:45.216597 CH0 RK0: MR19=606, MR18=3A3A
1154 00:56:45.222819 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1155 00:56:45.222901
1156 00:56:45.226737 ----->DramcWriteLeveling(PI) begin...
1157 00:56:45.226819 ==
1158 00:56:45.229702 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 00:56:45.232834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 00:56:45.232917 ==
1161 00:56:45.236385 Write leveling (Byte 0): 30 => 30
1162 00:56:45.239682 Write leveling (Byte 1): 26 => 26
1163 00:56:45.243072 DramcWriteLeveling(PI) end<-----
1164 00:56:45.243153
1165 00:56:45.243217 ==
1166 00:56:45.246963 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 00:56:45.249951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 00:56:45.250033 ==
1169 00:56:45.253079 [Gating] SW mode calibration
1170 00:56:45.259731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 00:56:45.266205 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 00:56:45.269524 0 6 0 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
1173 00:56:45.272749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1174 00:56:45.279507 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:56:45.283119 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:56:45.286712 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:56:45.292790 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:56:45.296410 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 00:56:45.299647 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 00:56:45.306009 0 7 0 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
1181 00:56:45.309948 0 7 4 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
1182 00:56:45.313734 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 00:56:45.320491 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 00:56:45.323347 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 00:56:45.326693 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 00:56:45.329583 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 00:56:45.335992 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 00:56:45.339446 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1189 00:56:45.343606 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 00:56:45.349557 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 00:56:45.352873 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 00:56:45.356319 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 00:56:45.362670 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 00:56:45.366097 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 00:56:45.369428 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 00:56:45.376351 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 00:56:45.379461 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 00:56:45.382750 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 00:56:45.389904 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 00:56:45.393175 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:56:45.396338 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:56:45.403544 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:56:45.406178 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:56:45.409441 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1205 00:56:45.416479 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 00:56:45.416561 Total UI for P1: 0, mck2ui 16
1207 00:56:45.422514 best dqsien dly found for B0: ( 0, 10, 0)
1208 00:56:45.422595 Total UI for P1: 0, mck2ui 16
1209 00:56:45.426510 best dqsien dly found for B1: ( 0, 10, 0)
1210 00:56:45.432936 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1211 00:56:45.435883 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1212 00:56:45.435963
1213 00:56:45.439335 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1214 00:56:45.442671 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1215 00:56:45.447257 [Gating] SW calibration Done
1216 00:56:45.447339 ==
1217 00:56:45.449208 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 00:56:45.452774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1219 00:56:45.452856 ==
1220 00:56:45.455798 RX Vref Scan: 0
1221 00:56:45.455880
1222 00:56:45.455944 RX Vref 0 -> 0, step: 1
1223 00:56:45.456005
1224 00:56:45.459222 RX Delay -130 -> 252, step: 16
1225 00:56:45.463404 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1226 00:56:45.510443 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1227 00:56:45.510580 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1228 00:56:45.510929 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1229 00:56:45.511287 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1230 00:56:45.511415 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1231 00:56:45.511623 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1232 00:56:45.512163 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1233 00:56:45.512695 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1234 00:56:45.512889 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1235 00:56:45.513226 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1236 00:56:45.513601 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1237 00:56:45.513729 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1238 00:56:45.534182 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1239 00:56:45.535034 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1240 00:56:45.535694 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1241 00:56:45.536180 ==
1242 00:56:45.536508 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 00:56:45.536940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1244 00:56:45.537282 ==
1245 00:56:45.537558 DQS Delay:
1246 00:56:45.539131 DQS0 = 0, DQS1 = 0
1247 00:56:45.539514 DQM Delay:
1248 00:56:45.539818 DQM0 = 81, DQM1 = 73
1249 00:56:45.540116 DQ Delay:
1250 00:56:45.542118 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1251 00:56:45.546254 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1252 00:56:45.549148 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1253 00:56:45.551941 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1254 00:56:45.552356
1255 00:56:45.552686
1256 00:56:45.553051 ==
1257 00:56:45.555529 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 00:56:45.558798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1259 00:56:45.559210 ==
1260 00:56:45.562506
1261 00:56:45.562914
1262 00:56:45.563238 TX Vref Scan disable
1263 00:56:45.565424 == TX Byte 0 ==
1264 00:56:45.568948 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1265 00:56:45.571807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1266 00:56:45.575786 == TX Byte 1 ==
1267 00:56:45.579046 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1268 00:56:45.582269 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1269 00:56:45.582680 ==
1270 00:56:45.585321 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 00:56:45.591991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 00:56:45.592403 ==
1273 00:56:45.604860 TX Vref=22, minBit 8, minWin=27, winSum=445
1274 00:56:45.607698 TX Vref=24, minBit 14, minWin=27, winSum=450
1275 00:56:45.610657 TX Vref=26, minBit 9, minWin=27, winSum=451
1276 00:56:45.614376 TX Vref=28, minBit 2, minWin=28, winSum=455
1277 00:56:45.617311 TX Vref=30, minBit 2, minWin=28, winSum=456
1278 00:56:45.624128 TX Vref=32, minBit 0, minWin=28, winSum=455
1279 00:56:45.627318 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1280 00:56:45.627742
1281 00:56:45.630840 Final TX Range 1 Vref 30
1282 00:56:45.631263
1283 00:56:45.631585 ==
1284 00:56:45.633959 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:56:45.637506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1286 00:56:45.637915 ==
1287 00:56:45.638239
1288 00:56:45.640572
1289 00:56:45.641012 TX Vref Scan disable
1290 00:56:45.644330 == TX Byte 0 ==
1291 00:56:45.647869 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1292 00:56:45.654149 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1293 00:56:45.654567 == TX Byte 1 ==
1294 00:56:45.657940 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1295 00:56:45.664250 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1296 00:56:45.664659
1297 00:56:45.665029 [DATLAT]
1298 00:56:45.665333 Freq=800, CH0 RK1
1299 00:56:45.665630
1300 00:56:45.668141 DATLAT Default: 0x9
1301 00:56:45.668550 0, 0xFFFF, sum = 0
1302 00:56:45.670823 1, 0xFFFF, sum = 0
1303 00:56:45.671289 2, 0xFFFF, sum = 0
1304 00:56:45.674371 3, 0xFFFF, sum = 0
1305 00:56:45.677629 4, 0xFFFF, sum = 0
1306 00:56:45.678045 5, 0xFFFF, sum = 0
1307 00:56:45.681551 6, 0xFFFF, sum = 0
1308 00:56:45.682000 7, 0xFFFF, sum = 0
1309 00:56:45.682366 8, 0x0, sum = 1
1310 00:56:45.683991 9, 0x0, sum = 2
1311 00:56:45.684424 10, 0x0, sum = 3
1312 00:56:45.687431 11, 0x0, sum = 4
1313 00:56:45.687881 best_step = 9
1314 00:56:45.688249
1315 00:56:45.688585 ==
1316 00:56:45.690393 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 00:56:45.697418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1318 00:56:45.697845 ==
1319 00:56:45.698195 RX Vref Scan: 0
1320 00:56:45.698524
1321 00:56:45.700616 RX Vref 0 -> 0, step: 1
1322 00:56:45.701077
1323 00:56:45.704439 RX Delay -111 -> 252, step: 8
1324 00:56:45.707567 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1325 00:56:45.710742 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1326 00:56:45.717120 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1327 00:56:45.721336 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1328 00:56:45.723991 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1329 00:56:45.727683 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1330 00:56:45.730825 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1331 00:56:45.737354 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1332 00:56:45.740757 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1333 00:56:45.743621 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1334 00:56:45.747251 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1335 00:56:45.750475 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1336 00:56:45.757033 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1337 00:56:45.760005 iDelay=217, Bit 13, Center 76 (-39 ~ 192) 232
1338 00:56:45.763571 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1339 00:56:45.767016 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1340 00:56:45.767119 ==
1341 00:56:45.769918 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 00:56:45.776728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1343 00:56:45.776832 ==
1344 00:56:45.776913 DQS Delay:
1345 00:56:45.776987 DQS0 = 0, DQS1 = 0
1346 00:56:45.780283 DQM Delay:
1347 00:56:45.780384 DQM0 = 86, DQM1 = 73
1348 00:56:45.783711 DQ Delay:
1349 00:56:45.786908 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1350 00:56:45.787010 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1351 00:56:45.790379 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1352 00:56:45.793939 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1353 00:56:45.797234
1354 00:56:45.797336
1355 00:56:45.803798 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1356 00:56:45.806902 CH0 RK1: MR19=606, MR18=4141
1357 00:56:45.813454 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1358 00:56:45.817124 [RxdqsGatingPostProcess] freq 800
1359 00:56:45.820662 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1360 00:56:45.823370 Pre-setting of DQS Precalculation
1361 00:56:45.830453 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1362 00:56:45.830558 ==
1363 00:56:45.834058 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 00:56:45.837482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 00:56:45.837584 ==
1366 00:56:45.841318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1367 00:56:45.847431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1368 00:56:45.856672 [CA 0] Center 37 (6~68) winsize 63
1369 00:56:45.860243 [CA 1] Center 37 (6~68) winsize 63
1370 00:56:45.863713 [CA 2] Center 34 (4~65) winsize 62
1371 00:56:45.867120 [CA 3] Center 34 (4~65) winsize 62
1372 00:56:45.870345 [CA 4] Center 33 (3~64) winsize 62
1373 00:56:45.873579 [CA 5] Center 33 (3~64) winsize 62
1374 00:56:45.873788
1375 00:56:45.876858 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1376 00:56:45.877167
1377 00:56:45.880148 [CATrainingPosCal] consider 1 rank data
1378 00:56:45.884341 u2DelayCellTimex100 = 270/100 ps
1379 00:56:45.887749 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1380 00:56:45.890706 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 00:56:45.897508 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1382 00:56:45.901096 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 00:56:45.903597 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1384 00:56:45.907123 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1385 00:56:45.907640
1386 00:56:45.909952 CA PerBit enable=1, Macro0, CA PI delay=33
1387 00:56:45.910475
1388 00:56:45.913461 [CBTSetCACLKResult] CA Dly = 33
1389 00:56:45.913945 CS Dly: 5 (0~36)
1390 00:56:45.916894 ==
1391 00:56:45.917369 Dram Type= 6, Freq= 0, CH_1, rank 1
1392 00:56:45.923234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1393 00:56:45.923709 ==
1394 00:56:45.926883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 00:56:45.933189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 00:56:45.942968 [CA 0] Center 36 (6~67) winsize 62
1397 00:56:45.945984 [CA 1] Center 37 (6~68) winsize 63
1398 00:56:45.949332 [CA 2] Center 34 (4~65) winsize 62
1399 00:56:45.953047 [CA 3] Center 34 (4~65) winsize 62
1400 00:56:45.956235 [CA 4] Center 33 (3~64) winsize 62
1401 00:56:45.959226 [CA 5] Center 33 (3~64) winsize 62
1402 00:56:45.959642
1403 00:56:45.963287 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1404 00:56:45.963703
1405 00:56:45.966133 [CATrainingPosCal] consider 2 rank data
1406 00:56:45.969296 u2DelayCellTimex100 = 270/100 ps
1407 00:56:45.973028 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1408 00:56:45.975951 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1409 00:56:45.982590 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 00:56:45.986048 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 00:56:45.989215 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1412 00:56:45.992329 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 00:56:45.992778
1414 00:56:45.996673 CA PerBit enable=1, Macro0, CA PI delay=33
1415 00:56:45.997121
1416 00:56:46.000037 [CBTSetCACLKResult] CA Dly = 33
1417 00:56:46.000451 CS Dly: 5 (0~36)
1418 00:56:46.000808
1419 00:56:46.002474 ----->DramcWriteLeveling(PI) begin...
1420 00:56:46.006382 ==
1421 00:56:46.009777 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 00:56:46.012289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1423 00:56:46.012726 ==
1424 00:56:46.015845 Write leveling (Byte 0): 24 => 24
1425 00:56:46.019484 Write leveling (Byte 1): 25 => 25
1426 00:56:46.022643 DramcWriteLeveling(PI) end<-----
1427 00:56:46.023058
1428 00:56:46.023385 ==
1429 00:56:46.026187 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 00:56:46.028990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1431 00:56:46.029408 ==
1432 00:56:46.032635 [Gating] SW mode calibration
1433 00:56:46.038913 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1434 00:56:46.045447 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1435 00:56:46.048824 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (1 0)
1436 00:56:46.052755 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 00:56:46.058857 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 00:56:46.062220 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 00:56:46.065694 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 00:56:46.071875 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 00:56:46.075559 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 00:56:46.079385 0 6 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1443 00:56:46.082235 0 7 0 | B1->B0 | 2f2f 3d3d | 1 0 | (0 0) (1 1)
1444 00:56:46.088639 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 00:56:46.092545 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 00:56:46.095302 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 00:56:46.102244 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 00:56:46.105484 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 00:56:46.108983 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 00:56:46.115659 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1451 00:56:46.118823 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1452 00:56:46.121973 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 00:56:46.128989 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 00:56:46.131756 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 00:56:46.135183 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 00:56:46.142573 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 00:56:46.146090 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 00:56:46.148438 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 00:56:46.156190 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 00:56:46.158555 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 00:56:46.162076 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 00:56:46.169153 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 00:56:46.172095 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 00:56:46.175619 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 00:56:46.182102 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 00:56:46.185290 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1467 00:56:46.189242 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1468 00:56:46.191859 Total UI for P1: 0, mck2ui 16
1469 00:56:46.195496 best dqsien dly found for B0: ( 0, 9, 28)
1470 00:56:46.198569 Total UI for P1: 0, mck2ui 16
1471 00:56:46.202143 best dqsien dly found for B1: ( 0, 9, 30)
1472 00:56:46.205537 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1473 00:56:46.208412 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1474 00:56:46.209038
1475 00:56:46.211992 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1476 00:56:46.219044 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1477 00:56:46.219522 [Gating] SW calibration Done
1478 00:56:46.219941 ==
1479 00:56:46.222337 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 00:56:46.229054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1481 00:56:46.229674 ==
1482 00:56:46.230228 RX Vref Scan: 0
1483 00:56:46.230787
1484 00:56:46.231771 RX Vref 0 -> 0, step: 1
1485 00:56:46.232166
1486 00:56:46.235378 RX Delay -130 -> 252, step: 16
1487 00:56:46.238698 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1488 00:56:46.242040 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1489 00:56:46.245566 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1490 00:56:46.252055 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1491 00:56:46.255251 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1492 00:56:46.258681 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1493 00:56:46.261804 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1494 00:56:46.265135 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1495 00:56:46.272596 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1496 00:56:46.275452 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1497 00:56:46.278386 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1498 00:56:46.281869 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1499 00:56:46.285169 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1500 00:56:46.291958 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1501 00:56:46.295116 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1502 00:56:46.298888 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1503 00:56:46.299296 ==
1504 00:56:46.301508 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 00:56:46.305673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1506 00:56:46.306082 ==
1507 00:56:46.314111 DQS Delay:
1508 00:56:46.314563 DQS0 = 0, DQS1 = 0
1509 00:56:46.315016 DQM Delay:
1510 00:56:46.315443 DQM0 = 80, DQM1 = 72
1511 00:56:46.315875 DQ Delay:
1512 00:56:46.316616 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1513 00:56:46.318764 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1514 00:56:46.322247 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1515 00:56:46.325275 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1516 00:56:46.325742
1517 00:56:46.326190
1518 00:56:46.326625 ==
1519 00:56:46.328421 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 00:56:46.335167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1521 00:56:46.335789 ==
1522 00:56:46.336247
1523 00:56:46.336674
1524 00:56:46.338131 TX Vref Scan disable
1525 00:56:46.338656 == TX Byte 0 ==
1526 00:56:46.341757 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1527 00:56:46.348513 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1528 00:56:46.349034 == TX Byte 1 ==
1529 00:56:46.351963 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1530 00:56:46.358276 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1531 00:56:46.358931 ==
1532 00:56:46.361339 Dram Type= 6, Freq= 0, CH_1, rank 0
1533 00:56:46.365075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1534 00:56:46.365529 ==
1535 00:56:46.377749 TX Vref=22, minBit 3, minWin=27, winSum=449
1536 00:56:46.381287 TX Vref=24, minBit 3, minWin=27, winSum=451
1537 00:56:46.385028 TX Vref=26, minBit 3, minWin=27, winSum=450
1538 00:56:46.388322 TX Vref=28, minBit 0, minWin=28, winSum=457
1539 00:56:46.391184 TX Vref=30, minBit 0, minWin=28, winSum=460
1540 00:56:46.394489 TX Vref=32, minBit 0, minWin=28, winSum=453
1541 00:56:46.401112 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1542 00:56:46.401549
1543 00:56:46.404387 Final TX Range 1 Vref 30
1544 00:56:46.404871
1545 00:56:46.405227 ==
1546 00:56:46.407607 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 00:56:46.411234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1548 00:56:46.411690 ==
1549 00:56:46.412038
1550 00:56:46.414959
1551 00:56:46.415395 TX Vref Scan disable
1552 00:56:46.417935 == TX Byte 0 ==
1553 00:56:46.421098 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1554 00:56:46.424695 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1555 00:56:46.428070 == TX Byte 1 ==
1556 00:56:46.431115 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1557 00:56:46.435905 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1558 00:56:46.437523
1559 00:56:46.438002 [DATLAT]
1560 00:56:46.438357 Freq=800, CH1 RK0
1561 00:56:46.438769
1562 00:56:46.441035 DATLAT Default: 0xa
1563 00:56:46.441617 0, 0xFFFF, sum = 0
1564 00:56:46.444895 1, 0xFFFF, sum = 0
1565 00:56:46.445336 2, 0xFFFF, sum = 0
1566 00:56:46.448095 3, 0xFFFF, sum = 0
1567 00:56:46.448552 4, 0xFFFF, sum = 0
1568 00:56:46.451480 5, 0xFFFF, sum = 0
1569 00:56:46.454572 6, 0xFFFF, sum = 0
1570 00:56:46.455082 7, 0xFFFF, sum = 0
1571 00:56:46.455453 8, 0x0, sum = 1
1572 00:56:46.458355 9, 0x0, sum = 2
1573 00:56:46.458825 10, 0x0, sum = 3
1574 00:56:46.461242 11, 0x0, sum = 4
1575 00:56:46.461718 best_step = 9
1576 00:56:46.462185
1577 00:56:46.462615 ==
1578 00:56:46.465221 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 00:56:46.471322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1580 00:56:46.471777 ==
1581 00:56:46.472230 RX Vref Scan: 1
1582 00:56:46.472760
1583 00:56:46.474679 Set Vref Range= 32 -> 127
1584 00:56:46.475135
1585 00:56:46.477428 RX Vref 32 -> 127, step: 1
1586 00:56:46.477863
1587 00:56:46.481541 RX Delay -111 -> 252, step: 8
1588 00:56:46.481976
1589 00:56:46.482325 Set Vref, RX VrefLevel [Byte0]: 32
1590 00:56:46.484438 [Byte1]: 32
1591 00:56:46.488798
1592 00:56:46.489235 Set Vref, RX VrefLevel [Byte0]: 33
1593 00:56:46.492440 [Byte1]: 33
1594 00:56:46.496585
1595 00:56:46.497102 Set Vref, RX VrefLevel [Byte0]: 34
1596 00:56:46.499993 [Byte1]: 34
1597 00:56:46.503813
1598 00:56:46.504212 Set Vref, RX VrefLevel [Byte0]: 35
1599 00:56:46.507442 [Byte1]: 35
1600 00:56:46.511356
1601 00:56:46.511805 Set Vref, RX VrefLevel [Byte0]: 36
1602 00:56:46.514721 [Byte1]: 36
1603 00:56:46.519358
1604 00:56:46.519770 Set Vref, RX VrefLevel [Byte0]: 37
1605 00:56:46.522547 [Byte1]: 37
1606 00:56:46.527151
1607 00:56:46.527653 Set Vref, RX VrefLevel [Byte0]: 38
1608 00:56:46.530619 [Byte1]: 38
1609 00:56:46.535099
1610 00:56:46.535641 Set Vref, RX VrefLevel [Byte0]: 39
1611 00:56:46.537740 [Byte1]: 39
1612 00:56:46.541950
1613 00:56:46.542362 Set Vref, RX VrefLevel [Byte0]: 40
1614 00:56:46.546332 [Byte1]: 40
1615 00:56:46.550199
1616 00:56:46.550611 Set Vref, RX VrefLevel [Byte0]: 41
1617 00:56:46.553271 [Byte1]: 41
1618 00:56:46.558275
1619 00:56:46.558836 Set Vref, RX VrefLevel [Byte0]: 42
1620 00:56:46.561188 [Byte1]: 42
1621 00:56:46.565459
1622 00:56:46.565870 Set Vref, RX VrefLevel [Byte0]: 43
1623 00:56:46.568740 [Byte1]: 43
1624 00:56:46.572905
1625 00:56:46.573322 Set Vref, RX VrefLevel [Byte0]: 44
1626 00:56:46.576675 [Byte1]: 44
1627 00:56:46.580462
1628 00:56:46.580912 Set Vref, RX VrefLevel [Byte0]: 45
1629 00:56:46.583832 [Byte1]: 45
1630 00:56:46.587825
1631 00:56:46.588272 Set Vref, RX VrefLevel [Byte0]: 46
1632 00:56:46.591639 [Byte1]: 46
1633 00:56:46.595798
1634 00:56:46.596263 Set Vref, RX VrefLevel [Byte0]: 47
1635 00:56:46.599415 [Byte1]: 47
1636 00:56:46.603655
1637 00:56:46.604107 Set Vref, RX VrefLevel [Byte0]: 48
1638 00:56:46.606665 [Byte1]: 48
1639 00:56:46.610878
1640 00:56:46.611331 Set Vref, RX VrefLevel [Byte0]: 49
1641 00:56:46.614807 [Byte1]: 49
1642 00:56:46.618718
1643 00:56:46.619164 Set Vref, RX VrefLevel [Byte0]: 50
1644 00:56:46.622542 [Byte1]: 50
1645 00:56:46.626546
1646 00:56:46.627012 Set Vref, RX VrefLevel [Byte0]: 51
1647 00:56:46.629812 [Byte1]: 51
1648 00:56:46.634181
1649 00:56:46.634627 Set Vref, RX VrefLevel [Byte0]: 52
1650 00:56:46.637590 [Byte1]: 52
1651 00:56:46.641453
1652 00:56:46.642015 Set Vref, RX VrefLevel [Byte0]: 53
1653 00:56:46.645141 [Byte1]: 53
1654 00:56:46.649473
1655 00:56:46.649921 Set Vref, RX VrefLevel [Byte0]: 54
1656 00:56:46.652576 [Byte1]: 54
1657 00:56:46.656519
1658 00:56:46.660415 Set Vref, RX VrefLevel [Byte0]: 55
1659 00:56:46.663461 [Byte1]: 55
1660 00:56:46.663930
1661 00:56:46.666485 Set Vref, RX VrefLevel [Byte0]: 56
1662 00:56:46.670066 [Byte1]: 56
1663 00:56:46.670579
1664 00:56:46.674263 Set Vref, RX VrefLevel [Byte0]: 57
1665 00:56:46.676971 [Byte1]: 57
1666 00:56:46.677403
1667 00:56:46.680178 Set Vref, RX VrefLevel [Byte0]: 58
1668 00:56:46.683666 [Byte1]: 58
1669 00:56:46.687890
1670 00:56:46.688474 Set Vref, RX VrefLevel [Byte0]: 59
1671 00:56:46.691283 [Byte1]: 59
1672 00:56:46.695478
1673 00:56:46.695889 Set Vref, RX VrefLevel [Byte0]: 60
1674 00:56:46.698739 [Byte1]: 60
1675 00:56:46.703060
1676 00:56:46.703471 Set Vref, RX VrefLevel [Byte0]: 61
1677 00:56:46.705857 [Byte1]: 61
1678 00:56:46.710431
1679 00:56:46.710841 Set Vref, RX VrefLevel [Byte0]: 62
1680 00:56:46.713850 [Byte1]: 62
1681 00:56:46.718597
1682 00:56:46.719006 Set Vref, RX VrefLevel [Byte0]: 63
1683 00:56:46.721479 [Byte1]: 63
1684 00:56:46.726504
1685 00:56:46.726915 Set Vref, RX VrefLevel [Byte0]: 64
1686 00:56:46.729387 [Byte1]: 64
1687 00:56:46.733163
1688 00:56:46.733632 Set Vref, RX VrefLevel [Byte0]: 65
1689 00:56:46.736950 [Byte1]: 65
1690 00:56:46.741531
1691 00:56:46.742002 Set Vref, RX VrefLevel [Byte0]: 66
1692 00:56:46.744974 [Byte1]: 66
1693 00:56:46.748625
1694 00:56:46.749240 Set Vref, RX VrefLevel [Byte0]: 67
1695 00:56:46.752847 [Byte1]: 67
1696 00:56:46.756366
1697 00:56:46.756840 Set Vref, RX VrefLevel [Byte0]: 68
1698 00:56:46.759693 [Byte1]: 68
1699 00:56:46.763970
1700 00:56:46.764377 Set Vref, RX VrefLevel [Byte0]: 69
1701 00:56:46.767778 [Byte1]: 69
1702 00:56:46.771522
1703 00:56:46.772081 Set Vref, RX VrefLevel [Byte0]: 70
1704 00:56:46.775059 [Byte1]: 70
1705 00:56:46.779155
1706 00:56:46.779563 Set Vref, RX VrefLevel [Byte0]: 71
1707 00:56:46.782857 [Byte1]: 71
1708 00:56:46.786634
1709 00:56:46.787041 Set Vref, RX VrefLevel [Byte0]: 72
1710 00:56:46.790174 [Byte1]: 72
1711 00:56:46.794468
1712 00:56:46.794894 Set Vref, RX VrefLevel [Byte0]: 73
1713 00:56:46.798200 [Byte1]: 73
1714 00:56:46.802271
1715 00:56:46.802667 Set Vref, RX VrefLevel [Byte0]: 74
1716 00:56:46.805666 [Byte1]: 74
1717 00:56:46.810651
1718 00:56:46.811035 Set Vref, RX VrefLevel [Byte0]: 75
1719 00:56:46.812808 [Byte1]: 75
1720 00:56:46.817605
1721 00:56:46.818008 Final RX Vref Byte 0 = 58 to rank0
1722 00:56:46.820950 Final RX Vref Byte 1 = 56 to rank0
1723 00:56:46.824245 Final RX Vref Byte 0 = 58 to rank1
1724 00:56:46.827562 Final RX Vref Byte 1 = 56 to rank1==
1725 00:56:46.831054 Dram Type= 6, Freq= 0, CH_1, rank 0
1726 00:56:46.834022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1727 00:56:46.837878 ==
1728 00:56:46.838257 DQS Delay:
1729 00:56:46.838588 DQS0 = 0, DQS1 = 0
1730 00:56:46.840754 DQM Delay:
1731 00:56:46.841286 DQM0 = 81, DQM1 = 75
1732 00:56:46.844754 DQ Delay:
1733 00:56:46.847609 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1734 00:56:46.848051 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1735 00:56:46.850795 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1736 00:56:46.854764 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1737 00:56:46.855220
1738 00:56:46.858320
1739 00:56:46.864430 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1740 00:56:46.868312 CH1 RK0: MR19=606, MR18=5454
1741 00:56:46.874599 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1742 00:56:46.875126
1743 00:56:46.878452 ----->DramcWriteLeveling(PI) begin...
1744 00:56:46.878923 ==
1745 00:56:46.882005 Dram Type= 6, Freq= 0, CH_1, rank 1
1746 00:56:46.884630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1747 00:56:46.885106 ==
1748 00:56:46.888251 Write leveling (Byte 0): 24 => 24
1749 00:56:46.891275 Write leveling (Byte 1): 24 => 24
1750 00:56:46.894452 DramcWriteLeveling(PI) end<-----
1751 00:56:46.894863
1752 00:56:46.895185 ==
1753 00:56:46.897640 Dram Type= 6, Freq= 0, CH_1, rank 1
1754 00:56:46.900972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1755 00:56:46.901421 ==
1756 00:56:46.904092 [Gating] SW mode calibration
1757 00:56:46.910907 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1758 00:56:46.917426 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1759 00:56:46.921260 0 6 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1760 00:56:46.924564 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 00:56:46.931242 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1762 00:56:46.934242 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 00:56:46.937965 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 00:56:46.944362 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 00:56:46.947145 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 00:56:46.950859 0 6 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1767 00:56:46.957587 0 7 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1768 00:56:46.960837 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 00:56:46.964281 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1770 00:56:46.970399 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 00:56:46.973916 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 00:56:46.977050 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 00:56:46.983976 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 00:56:46.987008 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1775 00:56:46.990632 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 00:56:46.997561 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 00:56:47.001362 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 00:56:47.004126 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 00:56:47.010505 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 00:56:47.013897 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 00:56:47.017471 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 00:56:47.023746 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 00:56:47.027055 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 00:56:47.029995 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 00:56:47.033681 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 00:56:47.039975 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 00:56:47.043835 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 00:56:47.046387 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 00:56:47.052952 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 00:56:47.056180 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1791 00:56:47.059886 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1792 00:56:47.062943 Total UI for P1: 0, mck2ui 16
1793 00:56:47.066484 best dqsien dly found for B0: ( 0, 9, 28)
1794 00:56:47.070149 Total UI for P1: 0, mck2ui 16
1795 00:56:47.073339 best dqsien dly found for B1: ( 0, 9, 30)
1796 00:56:47.077192 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1797 00:56:47.080105 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1798 00:56:47.083152
1799 00:56:47.086348 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1800 00:56:47.089726 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1801 00:56:47.093290 [Gating] SW calibration Done
1802 00:56:47.093700 ==
1803 00:56:47.096788 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 00:56:47.100019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1805 00:56:47.100432 ==
1806 00:56:47.100802 RX Vref Scan: 0
1807 00:56:47.101117
1808 00:56:47.104177 RX Vref 0 -> 0, step: 1
1809 00:56:47.104760
1810 00:56:47.106742 RX Delay -130 -> 252, step: 16
1811 00:56:47.109986 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1812 00:56:47.113287 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1813 00:56:47.120324 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1814 00:56:47.123632 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1815 00:56:47.126583 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1816 00:56:47.129682 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1817 00:56:47.133785 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1818 00:56:47.140070 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1819 00:56:47.143153 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1820 00:56:47.147143 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1821 00:56:47.150144 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1822 00:56:47.152973 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1823 00:56:47.159820 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1824 00:56:47.162955 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1825 00:56:47.166414 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1826 00:56:47.169632 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1827 00:56:47.169712 ==
1828 00:56:47.173368 Dram Type= 6, Freq= 0, CH_1, rank 1
1829 00:56:47.179706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1830 00:56:47.179787 ==
1831 00:56:47.179850 DQS Delay:
1832 00:56:47.179907 DQS0 = 0, DQS1 = 0
1833 00:56:47.183349 DQM Delay:
1834 00:56:47.183429 DQM0 = 86, DQM1 = 76
1835 00:56:47.186306 DQ Delay:
1836 00:56:47.189414 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1837 00:56:47.192800 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1838 00:56:47.196156 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1839 00:56:47.199856 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1840 00:56:47.199936
1841 00:56:47.200000
1842 00:56:47.200067 ==
1843 00:56:47.202688 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 00:56:47.206362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1845 00:56:47.206442 ==
1846 00:56:47.206505
1847 00:56:47.206563
1848 00:56:47.209656 TX Vref Scan disable
1849 00:56:47.209735 == TX Byte 0 ==
1850 00:56:47.216309 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1851 00:56:47.219562 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1852 00:56:47.219651 == TX Byte 1 ==
1853 00:56:47.226672 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1854 00:56:47.229188 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1855 00:56:47.229268 ==
1856 00:56:47.232552 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 00:56:47.236153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1858 00:56:47.236233 ==
1859 00:56:47.249884 TX Vref=22, minBit 3, minWin=27, winSum=448
1860 00:56:47.253312 TX Vref=24, minBit 3, minWin=27, winSum=452
1861 00:56:47.256572 TX Vref=26, minBit 0, minWin=28, winSum=457
1862 00:56:47.259842 TX Vref=28, minBit 0, minWin=28, winSum=458
1863 00:56:47.263084 TX Vref=30, minBit 0, minWin=28, winSum=458
1864 00:56:47.270157 TX Vref=32, minBit 0, minWin=28, winSum=457
1865 00:56:47.272912 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1866 00:56:47.272993
1867 00:56:47.276331 Final TX Range 1 Vref 28
1868 00:56:47.276411
1869 00:56:47.276473 ==
1870 00:56:47.280211 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 00:56:47.283425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1872 00:56:47.283505 ==
1873 00:56:47.283568
1874 00:56:47.286695
1875 00:56:47.286773 TX Vref Scan disable
1876 00:56:47.290207 == TX Byte 0 ==
1877 00:56:47.293585 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1878 00:56:47.296684 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1879 00:56:47.299972 == TX Byte 1 ==
1880 00:56:47.303275 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1881 00:56:47.306551 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1882 00:56:47.310003
1883 00:56:47.310082 [DATLAT]
1884 00:56:47.310148 Freq=800, CH1 RK1
1885 00:56:47.310207
1886 00:56:47.313266 DATLAT Default: 0x9
1887 00:56:47.313345 0, 0xFFFF, sum = 0
1888 00:56:47.316679 1, 0xFFFF, sum = 0
1889 00:56:47.316803 2, 0xFFFF, sum = 0
1890 00:56:47.320461 3, 0xFFFF, sum = 0
1891 00:56:47.320569 4, 0xFFFF, sum = 0
1892 00:56:47.322904 5, 0xFFFF, sum = 0
1893 00:56:47.326513 6, 0xFFFF, sum = 0
1894 00:56:47.326594 7, 0xFFFF, sum = 0
1895 00:56:47.326658 8, 0x0, sum = 1
1896 00:56:47.329659 9, 0x0, sum = 2
1897 00:56:47.329740 10, 0x0, sum = 3
1898 00:56:47.333196 11, 0x0, sum = 4
1899 00:56:47.333277 best_step = 9
1900 00:56:47.333340
1901 00:56:47.333399 ==
1902 00:56:47.336905 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 00:56:47.343331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1904 00:56:47.343411 ==
1905 00:56:47.343474 RX Vref Scan: 0
1906 00:56:47.343533
1907 00:56:47.347084 RX Vref 0 -> 0, step: 1
1908 00:56:47.347164
1909 00:56:47.349451 RX Delay -111 -> 252, step: 8
1910 00:56:47.352980 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1911 00:56:47.356524 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1912 00:56:47.363414 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1913 00:56:47.366458 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1914 00:56:47.370043 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1915 00:56:47.372760 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1916 00:56:47.376838 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1917 00:56:47.379738 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1918 00:56:47.386292 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1919 00:56:47.389913 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1920 00:56:47.393485 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1921 00:56:47.396599 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1922 00:56:47.403173 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1923 00:56:47.406134 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1924 00:56:47.409345 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1925 00:56:47.413495 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1926 00:56:47.413578 ==
1927 00:56:47.416080 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 00:56:47.423121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1929 00:56:47.423201 ==
1930 00:56:47.423264 DQS Delay:
1931 00:56:47.423322 DQS0 = 0, DQS1 = 0
1932 00:56:47.426633 DQM Delay:
1933 00:56:47.426712 DQM0 = 84, DQM1 = 75
1934 00:56:47.429582 DQ Delay:
1935 00:56:47.433186 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1936 00:56:47.436245 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1937 00:56:47.436325 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1938 00:56:47.443085 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1939 00:56:47.443165
1940 00:56:47.443228
1941 00:56:47.449591 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1942 00:56:47.453222 CH1 RK1: MR19=606, MR18=4141
1943 00:56:47.459568 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1944 00:56:47.462956 [RxdqsGatingPostProcess] freq 800
1945 00:56:47.466404 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1946 00:56:47.469175 Pre-setting of DQS Precalculation
1947 00:56:47.476012 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1948 00:56:47.482299 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1949 00:56:47.489767 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1950 00:56:47.489847
1951 00:56:47.489910
1952 00:56:47.492384 [Calibration Summary] 1600 Mbps
1953 00:56:47.492498 CH 0, Rank 0
1954 00:56:47.495830 SW Impedance : PASS
1955 00:56:47.499477 DUTY Scan : NO K
1956 00:56:47.499556 ZQ Calibration : PASS
1957 00:56:47.502589 Jitter Meter : NO K
1958 00:56:47.502669 CBT Training : PASS
1959 00:56:47.505665 Write leveling : PASS
1960 00:56:47.508828 RX DQS gating : PASS
1961 00:56:47.508907 RX DQ/DQS(RDDQC) : PASS
1962 00:56:47.512430 TX DQ/DQS : PASS
1963 00:56:47.517346 RX DATLAT : PASS
1964 00:56:47.517426 RX DQ/DQS(Engine): PASS
1965 00:56:47.519032 TX OE : NO K
1966 00:56:47.519111 All Pass.
1967 00:56:47.519175
1968 00:56:47.522269 CH 0, Rank 1
1969 00:56:47.522375 SW Impedance : PASS
1970 00:56:47.525717 DUTY Scan : NO K
1971 00:56:47.529057 ZQ Calibration : PASS
1972 00:56:47.529137 Jitter Meter : NO K
1973 00:56:47.532463 CBT Training : PASS
1974 00:56:47.535840 Write leveling : PASS
1975 00:56:47.535920 RX DQS gating : PASS
1976 00:56:47.539515 RX DQ/DQS(RDDQC) : PASS
1977 00:56:47.542800 TX DQ/DQS : PASS
1978 00:56:47.542879 RX DATLAT : PASS
1979 00:56:47.545439 RX DQ/DQS(Engine): PASS
1980 00:56:47.548698 TX OE : NO K
1981 00:56:47.548821 All Pass.
1982 00:56:47.548906
1983 00:56:47.548986 CH 1, Rank 0
1984 00:56:47.552364 SW Impedance : PASS
1985 00:56:47.555922 DUTY Scan : NO K
1986 00:56:47.556006 ZQ Calibration : PASS
1987 00:56:47.558748 Jitter Meter : NO K
1988 00:56:47.558832 CBT Training : PASS
1989 00:56:47.562197 Write leveling : PASS
1990 00:56:47.565269 RX DQS gating : PASS
1991 00:56:47.565353 RX DQ/DQS(RDDQC) : PASS
1992 00:56:47.569043 TX DQ/DQS : PASS
1993 00:56:47.572614 RX DATLAT : PASS
1994 00:56:47.572698 RX DQ/DQS(Engine): PASS
1995 00:56:47.575727 TX OE : NO K
1996 00:56:47.575812 All Pass.
1997 00:56:47.575897
1998 00:56:47.579025 CH 1, Rank 1
1999 00:56:47.579109 SW Impedance : PASS
2000 00:56:47.582379 DUTY Scan : NO K
2001 00:56:47.585724 ZQ Calibration : PASS
2002 00:56:47.585809 Jitter Meter : NO K
2003 00:56:47.588548 CBT Training : PASS
2004 00:56:47.592358 Write leveling : PASS
2005 00:56:47.592441 RX DQS gating : PASS
2006 00:56:47.595220 RX DQ/DQS(RDDQC) : PASS
2007 00:56:47.598997 TX DQ/DQS : PASS
2008 00:56:47.599106 RX DATLAT : PASS
2009 00:56:47.602679 RX DQ/DQS(Engine): PASS
2010 00:56:47.602791 TX OE : NO K
2011 00:56:47.605523 All Pass.
2012 00:56:47.605603
2013 00:56:47.605667 DramC Write-DBI off
2014 00:56:47.608952 PER_BANK_REFRESH: Hybrid Mode
2015 00:56:47.612584 TX_TRACKING: ON
2016 00:56:47.615800 [GetDramInforAfterCalByMRR] Vendor 6.
2017 00:56:47.618916 [GetDramInforAfterCalByMRR] Revision 606.
2018 00:56:47.622508 [GetDramInforAfterCalByMRR] Revision 2 0.
2019 00:56:47.622589 MR0 0x3939
2020 00:56:47.622654 MR8 0x1111
2021 00:56:47.629119 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2022 00:56:47.629200
2023 00:56:47.629263 MR0 0x3939
2024 00:56:47.629323 MR8 0x1111
2025 00:56:47.631794 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2026 00:56:47.631875
2027 00:56:47.642212 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2028 00:56:47.645790 [FAST_K] Save calibration result to emmc
2029 00:56:47.650057 [FAST_K] Save calibration result to emmc
2030 00:56:47.652000 dram_init: config_dvfs: 1
2031 00:56:47.655502 dramc_set_vcore_voltage set vcore to 662500
2032 00:56:47.658515 Read voltage for 1200, 2
2033 00:56:47.658596 Vio18 = 0
2034 00:56:47.658660 Vcore = 662500
2035 00:56:47.662162 Vdram = 0
2036 00:56:47.662243 Vddq = 0
2037 00:56:47.662308 Vmddr = 0
2038 00:56:47.668757 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2039 00:56:47.672229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2040 00:56:47.675891 MEM_TYPE=3, freq_sel=15
2041 00:56:47.678439 sv_algorithm_assistance_LP4_1600
2042 00:56:47.681989 ============ PULL DRAM RESETB DOWN ============
2043 00:56:47.689320 ========== PULL DRAM RESETB DOWN end =========
2044 00:56:47.692045 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2045 00:56:47.694840 ===================================
2046 00:56:47.698723 LPDDR4 DRAM CONFIGURATION
2047 00:56:47.701752 ===================================
2048 00:56:47.701834 EX_ROW_EN[0] = 0x0
2049 00:56:47.705548 EX_ROW_EN[1] = 0x0
2050 00:56:47.705628 LP4Y_EN = 0x0
2051 00:56:47.708474 WORK_FSP = 0x0
2052 00:56:47.708554 WL = 0x4
2053 00:56:47.711485 RL = 0x4
2054 00:56:47.711589 BL = 0x2
2055 00:56:47.715100 RPST = 0x0
2056 00:56:47.715196 RD_PRE = 0x0
2057 00:56:47.718566 WR_PRE = 0x1
2058 00:56:47.718634 WR_PST = 0x0
2059 00:56:47.722027 DBI_WR = 0x0
2060 00:56:47.725285 DBI_RD = 0x0
2061 00:56:47.725355 OTF = 0x1
2062 00:56:47.727963 ===================================
2063 00:56:47.731604 ===================================
2064 00:56:47.731701 ANA top config
2065 00:56:47.734831 ===================================
2066 00:56:47.738327 DLL_ASYNC_EN = 0
2067 00:56:47.742041 ALL_SLAVE_EN = 0
2068 00:56:47.745259 NEW_RANK_MODE = 1
2069 00:56:47.748550 DLL_IDLE_MODE = 1
2070 00:56:47.748645 LP45_APHY_COMB_EN = 1
2071 00:56:47.752456 TX_ODT_DIS = 1
2072 00:56:47.754763 NEW_8X_MODE = 1
2073 00:56:47.759028 ===================================
2074 00:56:47.761982 ===================================
2075 00:56:47.764673 data_rate = 2400
2076 00:56:47.768656 CKR = 1
2077 00:56:47.768774 DQ_P2S_RATIO = 8
2078 00:56:47.771800 ===================================
2079 00:56:47.774860 CA_P2S_RATIO = 8
2080 00:56:47.778142 DQ_CA_OPEN = 0
2081 00:56:47.781347 DQ_SEMI_OPEN = 0
2082 00:56:47.784652 CA_SEMI_OPEN = 0
2083 00:56:47.787933 CA_FULL_RATE = 0
2084 00:56:47.788004 DQ_CKDIV4_EN = 0
2085 00:56:47.792333 CA_CKDIV4_EN = 0
2086 00:56:47.794686 CA_PREDIV_EN = 0
2087 00:56:47.798612 PH8_DLY = 17
2088 00:56:47.801472 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2089 00:56:47.801543 DQ_AAMCK_DIV = 4
2090 00:56:47.804700 CA_AAMCK_DIV = 4
2091 00:56:47.808350 CA_ADMCK_DIV = 4
2092 00:56:47.811412 DQ_TRACK_CA_EN = 0
2093 00:56:47.815385 CA_PICK = 1200
2094 00:56:47.819475 CA_MCKIO = 1200
2095 00:56:47.821722 MCKIO_SEMI = 0
2096 00:56:47.824549 PLL_FREQ = 2366
2097 00:56:47.824620 DQ_UI_PI_RATIO = 32
2098 00:56:47.828639 CA_UI_PI_RATIO = 0
2099 00:56:47.831408 ===================================
2100 00:56:47.835505 ===================================
2101 00:56:47.837926 memory_type:LPDDR4
2102 00:56:47.842112 GP_NUM : 10
2103 00:56:47.842186 SRAM_EN : 1
2104 00:56:47.845289 MD32_EN : 0
2105 00:56:47.848157 ===================================
2106 00:56:47.848227 [ANA_INIT] >>>>>>>>>>>>>>
2107 00:56:47.851455 <<<<<< [CONFIGURE PHASE]: ANA_TX
2108 00:56:47.854812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2109 00:56:47.857988 ===================================
2110 00:56:47.861546 data_rate = 2400,PCW = 0X5b00
2111 00:56:47.864659 ===================================
2112 00:56:47.868016 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2113 00:56:47.874925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2114 00:56:47.878330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2115 00:56:47.885060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2116 00:56:47.888186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2117 00:56:47.891143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2118 00:56:47.894751 [ANA_INIT] flow start
2119 00:56:47.894832 [ANA_INIT] PLL >>>>>>>>
2120 00:56:47.898233 [ANA_INIT] PLL <<<<<<<<
2121 00:56:47.901352 [ANA_INIT] MIDPI >>>>>>>>
2122 00:56:47.901433 [ANA_INIT] MIDPI <<<<<<<<
2123 00:56:47.905118 [ANA_INIT] DLL >>>>>>>>
2124 00:56:47.908042 [ANA_INIT] DLL <<<<<<<<
2125 00:56:47.908122 [ANA_INIT] flow end
2126 00:56:47.911367 ============ LP4 DIFF to SE enter ============
2127 00:56:47.918017 ============ LP4 DIFF to SE exit ============
2128 00:56:47.918098 [ANA_INIT] <<<<<<<<<<<<<
2129 00:56:47.921608 [Flow] Enable top DCM control >>>>>
2130 00:56:47.924552 [Flow] Enable top DCM control <<<<<
2131 00:56:47.928199 Enable DLL master slave shuffle
2132 00:56:47.934760 ==============================================================
2133 00:56:47.938073 Gating Mode config
2134 00:56:47.941299 ==============================================================
2135 00:56:47.944855 Config description:
2136 00:56:47.954348 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2137 00:56:47.961315 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2138 00:56:47.964594 SELPH_MODE 0: By rank 1: By Phase
2139 00:56:47.972258 ==============================================================
2140 00:56:47.974109 GAT_TRACK_EN = 1
2141 00:56:47.978691 RX_GATING_MODE = 2
2142 00:56:47.980949 RX_GATING_TRACK_MODE = 2
2143 00:56:47.981058 SELPH_MODE = 1
2144 00:56:47.984383 PICG_EARLY_EN = 1
2145 00:56:47.987758 VALID_LAT_VALUE = 1
2146 00:56:47.994479 ==============================================================
2147 00:56:47.997909 Enter into Gating configuration >>>>
2148 00:56:48.001000 Exit from Gating configuration <<<<
2149 00:56:48.004087 Enter into DVFS_PRE_config >>>>>
2150 00:56:48.014259 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2151 00:56:48.017308 Exit from DVFS_PRE_config <<<<<
2152 00:56:48.021648 Enter into PICG configuration >>>>
2153 00:56:48.024195 Exit from PICG configuration <<<<
2154 00:56:48.028442 [RX_INPUT] configuration >>>>>
2155 00:56:48.030851 [RX_INPUT] configuration <<<<<
2156 00:56:48.034552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2157 00:56:48.040997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2158 00:56:48.047332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2159 00:56:48.054155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2160 00:56:48.057336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2161 00:56:48.064097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2162 00:56:48.067874 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2163 00:56:48.074280 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2164 00:56:48.077485 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2165 00:56:48.081194 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2166 00:56:48.084322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2167 00:56:48.091167 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2168 00:56:48.094868 ===================================
2169 00:56:48.094950 LPDDR4 DRAM CONFIGURATION
2170 00:56:48.097847 ===================================
2171 00:56:48.100917 EX_ROW_EN[0] = 0x0
2172 00:56:48.104250 EX_ROW_EN[1] = 0x0
2173 00:56:48.104329 LP4Y_EN = 0x0
2174 00:56:48.108023 WORK_FSP = 0x0
2175 00:56:48.108103 WL = 0x4
2176 00:56:48.111036 RL = 0x4
2177 00:56:48.111116 BL = 0x2
2178 00:56:48.115785 RPST = 0x0
2179 00:56:48.115864 RD_PRE = 0x0
2180 00:56:48.117493 WR_PRE = 0x1
2181 00:56:48.117574 WR_PST = 0x0
2182 00:56:48.121051 DBI_WR = 0x0
2183 00:56:48.121131 DBI_RD = 0x0
2184 00:56:48.124329 OTF = 0x1
2185 00:56:48.127234 ===================================
2186 00:56:48.130685 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2187 00:56:48.134106 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2188 00:56:48.140610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 00:56:48.144257 ===================================
2190 00:56:48.144339 LPDDR4 DRAM CONFIGURATION
2191 00:56:48.148538 ===================================
2192 00:56:48.151566 EX_ROW_EN[0] = 0x10
2193 00:56:48.151646 EX_ROW_EN[1] = 0x0
2194 00:56:48.153815 LP4Y_EN = 0x0
2195 00:56:48.157254 WORK_FSP = 0x0
2196 00:56:48.157335 WL = 0x4
2197 00:56:48.161202 RL = 0x4
2198 00:56:48.161284 BL = 0x2
2199 00:56:48.163777 RPST = 0x0
2200 00:56:48.163858 RD_PRE = 0x0
2201 00:56:48.167731 WR_PRE = 0x1
2202 00:56:48.167811 WR_PST = 0x0
2203 00:56:48.170665 DBI_WR = 0x0
2204 00:56:48.170746 DBI_RD = 0x0
2205 00:56:48.174440 OTF = 0x1
2206 00:56:48.177322 ===================================
2207 00:56:48.184096 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2208 00:56:48.184178 ==
2209 00:56:48.187798 Dram Type= 6, Freq= 0, CH_0, rank 0
2210 00:56:48.191187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2211 00:56:48.191268 ==
2212 00:56:48.194461 [Duty_Offset_Calibration]
2213 00:56:48.194542 B0:0 B1:2 CA:1
2214 00:56:48.194608
2215 00:56:48.197392 [DutyScan_Calibration_Flow] k_type=0
2216 00:56:48.207272
2217 00:56:48.207353 ==CLK 0==
2218 00:56:48.210772 Final CLK duty delay cell = 0
2219 00:56:48.213482 [0] MAX Duty = 5093%(X100), DQS PI = 12
2220 00:56:48.217643 [0] MIN Duty = 4938%(X100), DQS PI = 52
2221 00:56:48.217728 [0] AVG Duty = 5015%(X100)
2222 00:56:48.220922
2223 00:56:48.223812 CH0 CLK Duty spec in!! Max-Min= 155%
2224 00:56:48.227305 [DutyScan_Calibration_Flow] ====Done====
2225 00:56:48.227386
2226 00:56:48.230176 [DutyScan_Calibration_Flow] k_type=1
2227 00:56:48.246613
2228 00:56:48.246697 ==DQS 0 ==
2229 00:56:48.250012 Final DQS duty delay cell = 0
2230 00:56:48.253006 [0] MAX Duty = 5125%(X100), DQS PI = 28
2231 00:56:48.256391 [0] MIN Duty = 5031%(X100), DQS PI = 4
2232 00:56:48.256472 [0] AVG Duty = 5078%(X100)
2233 00:56:48.260192
2234 00:56:48.260273 ==DQS 1 ==
2235 00:56:48.262822 Final DQS duty delay cell = 0
2236 00:56:48.266380 [0] MAX Duty = 5062%(X100), DQS PI = 58
2237 00:56:48.269621 [0] MIN Duty = 4906%(X100), DQS PI = 16
2238 00:56:48.269700 [0] AVG Duty = 4984%(X100)
2239 00:56:48.273113
2240 00:56:48.276701 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2241 00:56:48.276814
2242 00:56:48.279673 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2243 00:56:48.283043 [DutyScan_Calibration_Flow] ====Done====
2244 00:56:48.283119
2245 00:56:48.286570 [DutyScan_Calibration_Flow] k_type=3
2246 00:56:48.303775
2247 00:56:48.303856 ==DQM 0 ==
2248 00:56:48.306880 Final DQM duty delay cell = 0
2249 00:56:48.310454 [0] MAX Duty = 5156%(X100), DQS PI = 20
2250 00:56:48.313528 [0] MIN Duty = 4969%(X100), DQS PI = 54
2251 00:56:48.316872 [0] AVG Duty = 5062%(X100)
2252 00:56:48.316952
2253 00:56:48.317037 ==DQM 1 ==
2254 00:56:48.320440 Final DQM duty delay cell = 4
2255 00:56:48.323869 [4] MAX Duty = 5187%(X100), DQS PI = 52
2256 00:56:48.327449 [4] MIN Duty = 5000%(X100), DQS PI = 18
2257 00:56:48.330677 [4] AVG Duty = 5093%(X100)
2258 00:56:48.330766
2259 00:56:48.333613 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2260 00:56:48.333716
2261 00:56:48.336581 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2262 00:56:48.340730 [DutyScan_Calibration_Flow] ====Done====
2263 00:56:48.340840
2264 00:56:48.343105 [DutyScan_Calibration_Flow] k_type=2
2265 00:56:48.358656
2266 00:56:48.358739 ==DQ 0 ==
2267 00:56:48.361709 Final DQ duty delay cell = -4
2268 00:56:48.365107 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2269 00:56:48.369152 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2270 00:56:48.371907 [-4] AVG Duty = 4937%(X100)
2271 00:56:48.371989
2272 00:56:48.372072 ==DQ 1 ==
2273 00:56:48.375550 Final DQ duty delay cell = -4
2274 00:56:48.378743 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2275 00:56:48.381893 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2276 00:56:48.385576 [-4] AVG Duty = 4969%(X100)
2277 00:56:48.385659
2278 00:56:48.388372 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2279 00:56:48.388455
2280 00:56:48.391632 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2281 00:56:48.395171 [DutyScan_Calibration_Flow] ====Done====
2282 00:56:48.395251 ==
2283 00:56:48.398249 Dram Type= 6, Freq= 0, CH_1, rank 0
2284 00:56:48.401534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2285 00:56:48.401615 ==
2286 00:56:48.405208 [Duty_Offset_Calibration]
2287 00:56:48.405287 B0:0 B1:4 CA:-5
2288 00:56:48.405351
2289 00:56:48.408583 [DutyScan_Calibration_Flow] k_type=0
2290 00:56:48.419134
2291 00:56:48.419216 ==CLK 0==
2292 00:56:48.422516 Final CLK duty delay cell = 0
2293 00:56:48.426162 [0] MAX Duty = 5094%(X100), DQS PI = 24
2294 00:56:48.429709 [0] MIN Duty = 4907%(X100), DQS PI = 44
2295 00:56:48.429810 [0] AVG Duty = 5000%(X100)
2296 00:56:48.432386
2297 00:56:48.435679 CH1 CLK Duty spec in!! Max-Min= 187%
2298 00:56:48.439451 [DutyScan_Calibration_Flow] ====Done====
2299 00:56:48.439534
2300 00:56:48.442224 [DutyScan_Calibration_Flow] k_type=1
2301 00:56:48.457580
2302 00:56:48.457662 ==DQS 0 ==
2303 00:56:48.461357 Final DQS duty delay cell = 0
2304 00:56:48.464574 [0] MAX Duty = 5125%(X100), DQS PI = 16
2305 00:56:48.467240 [0] MIN Duty = 4875%(X100), DQS PI = 40
2306 00:56:48.471426 [0] AVG Duty = 5000%(X100)
2307 00:56:48.471509
2308 00:56:48.471593 ==DQS 1 ==
2309 00:56:48.474051 Final DQS duty delay cell = -4
2310 00:56:48.477791 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2311 00:56:48.480843 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2312 00:56:48.484181 [-4] AVG Duty = 4953%(X100)
2313 00:56:48.484263
2314 00:56:48.487606 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2315 00:56:48.487689
2316 00:56:48.491356 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2317 00:56:48.494205 [DutyScan_Calibration_Flow] ====Done====
2318 00:56:48.494288
2319 00:56:48.497819 [DutyScan_Calibration_Flow] k_type=3
2320 00:56:48.512842
2321 00:56:48.512984 ==DQM 0 ==
2322 00:56:48.516348 Final DQM duty delay cell = -4
2323 00:56:48.519269 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2324 00:56:48.522642 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2325 00:56:48.526025 [-4] AVG Duty = 4984%(X100)
2326 00:56:48.526133
2327 00:56:48.526238 ==DQM 1 ==
2328 00:56:48.529612 Final DQM duty delay cell = -4
2329 00:56:48.533242 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2330 00:56:48.536213 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2331 00:56:48.539528 [-4] AVG Duty = 4984%(X100)
2332 00:56:48.539612
2333 00:56:48.542671 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2334 00:56:48.542755
2335 00:56:48.545918 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2336 00:56:48.549187 [DutyScan_Calibration_Flow] ====Done====
2337 00:56:48.549283
2338 00:56:48.552884 [DutyScan_Calibration_Flow] k_type=2
2339 00:56:48.570323
2340 00:56:48.570403 ==DQ 0 ==
2341 00:56:48.573350 Final DQ duty delay cell = 0
2342 00:56:48.576557 [0] MAX Duty = 5062%(X100), DQS PI = 0
2343 00:56:48.579554 [0] MIN Duty = 4938%(X100), DQS PI = 44
2344 00:56:48.579664 [0] AVG Duty = 5000%(X100)
2345 00:56:48.579728
2346 00:56:48.583042 ==DQ 1 ==
2347 00:56:48.586509 Final DQ duty delay cell = 0
2348 00:56:48.590287 [0] MAX Duty = 5000%(X100), DQS PI = 8
2349 00:56:48.593358 [0] MIN Duty = 4875%(X100), DQS PI = 16
2350 00:56:48.593441 [0] AVG Duty = 4937%(X100)
2351 00:56:48.593507
2352 00:56:48.596445 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2353 00:56:48.596519
2354 00:56:48.599566 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2355 00:56:48.606729 [DutyScan_Calibration_Flow] ====Done====
2356 00:56:48.610023 nWR fixed to 30
2357 00:56:48.610096 [ModeRegInit_LP4] CH0 RK0
2358 00:56:48.613164 [ModeRegInit_LP4] CH0 RK1
2359 00:56:48.616391 [ModeRegInit_LP4] CH1 RK0
2360 00:56:48.616468 [ModeRegInit_LP4] CH1 RK1
2361 00:56:48.620460 match AC timing 6
2362 00:56:48.623864 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2363 00:56:48.626366 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2364 00:56:48.632830 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2365 00:56:48.637427 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2366 00:56:48.642892 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2367 00:56:48.642970 ==
2368 00:56:48.646706 Dram Type= 6, Freq= 0, CH_0, rank 0
2369 00:56:48.649808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2370 00:56:48.649878 ==
2371 00:56:48.656553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2372 00:56:48.660105 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2373 00:56:48.669726 [CA 0] Center 39 (9~70) winsize 62
2374 00:56:48.673522 [CA 1] Center 39 (9~70) winsize 62
2375 00:56:48.676605 [CA 2] Center 36 (5~67) winsize 63
2376 00:56:48.679826 [CA 3] Center 35 (5~66) winsize 62
2377 00:56:48.683007 [CA 4] Center 34 (4~65) winsize 62
2378 00:56:48.687047 [CA 5] Center 33 (3~64) winsize 62
2379 00:56:48.687244
2380 00:56:48.689384 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2381 00:56:48.689577
2382 00:56:48.693034 [CATrainingPosCal] consider 1 rank data
2383 00:56:48.697172 u2DelayCellTimex100 = 270/100 ps
2384 00:56:48.699438 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2385 00:56:48.703094 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2386 00:56:48.709402 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2387 00:56:48.713117 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2388 00:56:48.716428 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2389 00:56:48.719580 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2390 00:56:48.719957
2391 00:56:48.722821 CA PerBit enable=1, Macro0, CA PI delay=33
2392 00:56:48.723289
2393 00:56:48.726536 [CBTSetCACLKResult] CA Dly = 33
2394 00:56:48.726995 CS Dly: 7 (0~38)
2395 00:56:48.730147 ==
2396 00:56:48.733436 Dram Type= 6, Freq= 0, CH_0, rank 1
2397 00:56:48.737269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2398 00:56:48.737796 ==
2399 00:56:48.739839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2400 00:56:48.747043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2401 00:56:48.755446 [CA 0] Center 39 (8~70) winsize 63
2402 00:56:48.759260 [CA 1] Center 38 (8~69) winsize 62
2403 00:56:48.762453 [CA 2] Center 36 (5~67) winsize 63
2404 00:56:48.765573 [CA 3] Center 35 (4~66) winsize 63
2405 00:56:48.768882 [CA 4] Center 33 (3~64) winsize 62
2406 00:56:48.772167 [CA 5] Center 34 (3~65) winsize 63
2407 00:56:48.772686
2408 00:56:48.775178 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2409 00:56:48.775636
2410 00:56:48.778909 [CATrainingPosCal] consider 2 rank data
2411 00:56:48.782024 u2DelayCellTimex100 = 270/100 ps
2412 00:56:48.785832 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2413 00:56:48.789274 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2414 00:56:48.795605 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2415 00:56:48.799225 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2416 00:56:48.802728 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2417 00:56:48.805138 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2418 00:56:48.805596
2419 00:56:48.809280 CA PerBit enable=1, Macro0, CA PI delay=33
2420 00:56:48.809839
2421 00:56:48.811822 [CBTSetCACLKResult] CA Dly = 33
2422 00:56:48.812277 CS Dly: 7 (0~39)
2423 00:56:48.812634
2424 00:56:48.815277 ----->DramcWriteLeveling(PI) begin...
2425 00:56:48.819127 ==
2426 00:56:48.821982 Dram Type= 6, Freq= 0, CH_0, rank 0
2427 00:56:48.825751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2428 00:56:48.826212 ==
2429 00:56:48.828423 Write leveling (Byte 0): 28 => 28
2430 00:56:48.832007 Write leveling (Byte 1): 26 => 26
2431 00:56:48.835561 DramcWriteLeveling(PI) end<-----
2432 00:56:48.836019
2433 00:56:48.836567 ==
2434 00:56:48.838782 Dram Type= 6, Freq= 0, CH_0, rank 0
2435 00:56:48.842353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2436 00:56:48.842809 ==
2437 00:56:48.845862 [Gating] SW mode calibration
2438 00:56:48.852320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2439 00:56:48.855796 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2440 00:56:48.861858 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2441 00:56:48.866152 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2442 00:56:48.868647 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2443 00:56:48.875332 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2444 00:56:48.879388 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2445 00:56:48.881711 0 11 20 | B1->B0 | 2e2e 2727 | 0 1 | (0 1) (1 0)
2446 00:56:48.888618 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2447 00:56:48.892066 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 00:56:48.894979 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2449 00:56:48.902904 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 00:56:48.905529 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 00:56:48.908393 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 00:56:48.915844 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2453 00:56:48.919250 0 12 20 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
2454 00:56:48.922909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 00:56:48.929095 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 00:56:48.931893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 00:56:48.935752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 00:56:48.942182 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 00:56:48.945108 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 00:56:48.949281 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2461 00:56:48.955402 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2462 00:56:48.958997 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2463 00:56:48.961820 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 00:56:48.968855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 00:56:48.972385 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 00:56:48.975546 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 00:56:48.978635 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 00:56:48.985018 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 00:56:48.989187 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 00:56:48.992351 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 00:56:48.998815 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 00:56:49.002252 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 00:56:49.005697 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 00:56:49.012032 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 00:56:49.015558 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 00:56:49.019113 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 00:56:49.025814 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2478 00:56:49.028746 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2479 00:56:49.032144 Total UI for P1: 0, mck2ui 16
2480 00:56:49.035543 best dqsien dly found for B0: ( 0, 15, 20)
2481 00:56:49.038432 Total UI for P1: 0, mck2ui 16
2482 00:56:49.041982 best dqsien dly found for B1: ( 0, 15, 20)
2483 00:56:49.045348 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2484 00:56:49.048978 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2485 00:56:49.049534
2486 00:56:49.052005 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2487 00:56:49.055811 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2488 00:56:49.058615 [Gating] SW calibration Done
2489 00:56:49.059163 ==
2490 00:56:49.061603 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 00:56:49.065026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2492 00:56:49.068569 ==
2493 00:56:49.069072 RX Vref Scan: 0
2494 00:56:49.069439
2495 00:56:49.071688 RX Vref 0 -> 0, step: 1
2496 00:56:49.072140
2497 00:56:49.072493 RX Delay -40 -> 252, step: 8
2498 00:56:49.078866 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2499 00:56:49.081935 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2500 00:56:49.085195 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2501 00:56:49.088418 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2502 00:56:49.091944 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2503 00:56:49.098408 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2504 00:56:49.102801 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2505 00:56:49.106184 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2506 00:56:49.109525 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2507 00:56:49.111862 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2508 00:56:49.118635 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2509 00:56:49.122341 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2510 00:56:49.126021 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2511 00:56:49.128338 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2512 00:56:49.132091 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2513 00:56:49.138200 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2514 00:56:49.138715 ==
2515 00:56:49.142911 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 00:56:49.145247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2517 00:56:49.145711 ==
2518 00:56:49.146118 DQS Delay:
2519 00:56:49.148842 DQS0 = 0, DQS1 = 0
2520 00:56:49.149332 DQM Delay:
2521 00:56:49.151991 DQM0 = 115, DQM1 = 106
2522 00:56:49.152497 DQ Delay:
2523 00:56:49.155300 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2524 00:56:49.158868 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2525 00:56:49.161910 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2526 00:56:49.165046 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2527 00:56:49.165595
2528 00:56:49.166201
2529 00:56:49.169215 ==
2530 00:56:49.171793 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 00:56:49.175118 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2532 00:56:49.175584 ==
2533 00:56:49.175948
2534 00:56:49.176290
2535 00:56:49.178443 TX Vref Scan disable
2536 00:56:49.178900 == TX Byte 0 ==
2537 00:56:49.181336 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2538 00:56:49.188278 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2539 00:56:49.188870 == TX Byte 1 ==
2540 00:56:49.191504 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2541 00:56:49.198604 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2542 00:56:49.199055 ==
2543 00:56:49.201678 Dram Type= 6, Freq= 0, CH_0, rank 0
2544 00:56:49.204898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2545 00:56:49.205357 ==
2546 00:56:49.216891 TX Vref=22, minBit 9, minWin=25, winSum=416
2547 00:56:49.219926 TX Vref=24, minBit 10, minWin=25, winSum=422
2548 00:56:49.223482 TX Vref=26, minBit 8, minWin=25, winSum=431
2549 00:56:49.227134 TX Vref=28, minBit 8, minWin=26, winSum=435
2550 00:56:49.230199 TX Vref=30, minBit 10, minWin=26, winSum=434
2551 00:56:49.236670 TX Vref=32, minBit 10, minWin=26, winSum=434
2552 00:56:49.240196 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
2553 00:56:49.240956
2554 00:56:49.243887 Final TX Range 1 Vref 28
2555 00:56:49.244346
2556 00:56:49.244699 ==
2557 00:56:49.246946 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 00:56:49.250653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2559 00:56:49.253311 ==
2560 00:56:49.253863
2561 00:56:49.254229
2562 00:56:49.254564 TX Vref Scan disable
2563 00:56:49.256800 == TX Byte 0 ==
2564 00:56:49.260162 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2565 00:56:49.266630 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2566 00:56:49.267332 == TX Byte 1 ==
2567 00:56:49.270305 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2568 00:56:49.277203 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2569 00:56:49.277842
2570 00:56:49.278410 [DATLAT]
2571 00:56:49.278915 Freq=1200, CH0 RK0
2572 00:56:49.279273
2573 00:56:49.279977 DATLAT Default: 0xd
2574 00:56:49.280362 0, 0xFFFF, sum = 0
2575 00:56:49.283624 1, 0xFFFF, sum = 0
2576 00:56:49.284302 2, 0xFFFF, sum = 0
2577 00:56:49.287107 3, 0xFFFF, sum = 0
2578 00:56:49.289961 4, 0xFFFF, sum = 0
2579 00:56:49.290607 5, 0xFFFF, sum = 0
2580 00:56:49.293554 6, 0xFFFF, sum = 0
2581 00:56:49.294132 7, 0xFFFF, sum = 0
2582 00:56:49.296675 8, 0xFFFF, sum = 0
2583 00:56:49.297264 9, 0xFFFF, sum = 0
2584 00:56:49.299884 10, 0xFFFF, sum = 0
2585 00:56:49.300497 11, 0x0, sum = 1
2586 00:56:49.304228 12, 0x0, sum = 2
2587 00:56:49.304836 13, 0x0, sum = 3
2588 00:56:49.306390 14, 0x0, sum = 4
2589 00:56:49.306888 best_step = 12
2590 00:56:49.307367
2591 00:56:49.307716 ==
2592 00:56:49.310180 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 00:56:49.313046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2594 00:56:49.313545 ==
2595 00:56:49.316373 RX Vref Scan: 1
2596 00:56:49.316900
2597 00:56:49.320156 Set Vref Range= 32 -> 127
2598 00:56:49.320607
2599 00:56:49.321027 RX Vref 32 -> 127, step: 1
2600 00:56:49.321395
2601 00:56:49.323422 RX Delay -21 -> 252, step: 4
2602 00:56:49.323869
2603 00:56:49.327864 Set Vref, RX VrefLevel [Byte0]: 32
2604 00:56:49.329926 [Byte1]: 32
2605 00:56:49.333468
2606 00:56:49.333919 Set Vref, RX VrefLevel [Byte0]: 33
2607 00:56:49.337128 [Byte1]: 33
2608 00:56:49.341221
2609 00:56:49.341676 Set Vref, RX VrefLevel [Byte0]: 34
2610 00:56:49.344819 [Byte1]: 34
2611 00:56:49.349014
2612 00:56:49.349466 Set Vref, RX VrefLevel [Byte0]: 35
2613 00:56:49.353095 [Byte1]: 35
2614 00:56:49.357633
2615 00:56:49.358395 Set Vref, RX VrefLevel [Byte0]: 36
2616 00:56:49.360924 [Byte1]: 36
2617 00:56:49.365754
2618 00:56:49.368513 Set Vref, RX VrefLevel [Byte0]: 37
2619 00:56:49.369014 [Byte1]: 37
2620 00:56:49.373636
2621 00:56:49.374090 Set Vref, RX VrefLevel [Byte0]: 38
2622 00:56:49.376145 [Byte1]: 38
2623 00:56:49.380934
2624 00:56:49.381516 Set Vref, RX VrefLevel [Byte0]: 39
2625 00:56:49.384544 [Byte1]: 39
2626 00:56:49.389298
2627 00:56:49.389753 Set Vref, RX VrefLevel [Byte0]: 40
2628 00:56:49.393297 [Byte1]: 40
2629 00:56:49.397252
2630 00:56:49.397704 Set Vref, RX VrefLevel [Byte0]: 41
2631 00:56:49.400291 [Byte1]: 41
2632 00:56:49.405579
2633 00:56:49.406126 Set Vref, RX VrefLevel [Byte0]: 42
2634 00:56:49.407951 [Byte1]: 42
2635 00:56:49.412616
2636 00:56:49.413212 Set Vref, RX VrefLevel [Byte0]: 43
2637 00:56:49.416218 [Byte1]: 43
2638 00:56:49.420522
2639 00:56:49.421029 Set Vref, RX VrefLevel [Byte0]: 44
2640 00:56:49.423843 [Byte1]: 44
2641 00:56:49.429026
2642 00:56:49.429590 Set Vref, RX VrefLevel [Byte0]: 45
2643 00:56:49.432178 [Byte1]: 45
2644 00:56:49.436194
2645 00:56:49.436652 Set Vref, RX VrefLevel [Byte0]: 46
2646 00:56:49.440182 [Byte1]: 46
2647 00:56:49.444423
2648 00:56:49.444964 Set Vref, RX VrefLevel [Byte0]: 47
2649 00:56:49.448520 [Byte1]: 47
2650 00:56:49.452827
2651 00:56:49.453281 Set Vref, RX VrefLevel [Byte0]: 48
2652 00:56:49.455666 [Byte1]: 48
2653 00:56:49.460180
2654 00:56:49.460791 Set Vref, RX VrefLevel [Byte0]: 49
2655 00:56:49.463359 [Byte1]: 49
2656 00:56:49.468315
2657 00:56:49.468929 Set Vref, RX VrefLevel [Byte0]: 50
2658 00:56:49.471758 [Byte1]: 50
2659 00:56:49.475981
2660 00:56:49.476529 Set Vref, RX VrefLevel [Byte0]: 51
2661 00:56:49.479633 [Byte1]: 51
2662 00:56:49.484191
2663 00:56:49.484741 Set Vref, RX VrefLevel [Byte0]: 52
2664 00:56:49.487821 [Byte1]: 52
2665 00:56:49.492313
2666 00:56:49.492896 Set Vref, RX VrefLevel [Byte0]: 53
2667 00:56:49.496059 [Byte1]: 53
2668 00:56:49.500046
2669 00:56:49.500566 Set Vref, RX VrefLevel [Byte0]: 54
2670 00:56:49.503801 [Byte1]: 54
2671 00:56:49.507825
2672 00:56:49.508374 Set Vref, RX VrefLevel [Byte0]: 55
2673 00:56:49.511584 [Byte1]: 55
2674 00:56:49.516064
2675 00:56:49.516622 Set Vref, RX VrefLevel [Byte0]: 56
2676 00:56:49.519217 [Byte1]: 56
2677 00:56:49.524453
2678 00:56:49.525042 Set Vref, RX VrefLevel [Byte0]: 57
2679 00:56:49.527311 [Byte1]: 57
2680 00:56:49.532214
2681 00:56:49.532822 Set Vref, RX VrefLevel [Byte0]: 58
2682 00:56:49.534768 [Byte1]: 58
2683 00:56:49.539416
2684 00:56:49.539871 Set Vref, RX VrefLevel [Byte0]: 59
2685 00:56:49.543132 [Byte1]: 59
2686 00:56:49.547580
2687 00:56:49.548036 Set Vref, RX VrefLevel [Byte0]: 60
2688 00:56:49.551107 [Byte1]: 60
2689 00:56:49.555593
2690 00:56:49.556046 Set Vref, RX VrefLevel [Byte0]: 61
2691 00:56:49.559043 [Byte1]: 61
2692 00:56:49.563082
2693 00:56:49.567120 Set Vref, RX VrefLevel [Byte0]: 62
2694 00:56:49.567580 [Byte1]: 62
2695 00:56:49.571516
2696 00:56:49.572097 Set Vref, RX VrefLevel [Byte0]: 63
2697 00:56:49.574338 [Byte1]: 63
2698 00:56:49.579310
2699 00:56:49.579817 Set Vref, RX VrefLevel [Byte0]: 64
2700 00:56:49.582495 [Byte1]: 64
2701 00:56:49.586721
2702 00:56:49.587252 Set Vref, RX VrefLevel [Byte0]: 65
2703 00:56:49.590032 [Byte1]: 65
2704 00:56:49.595208
2705 00:56:49.595709 Set Vref, RX VrefLevel [Byte0]: 66
2706 00:56:49.598423 [Byte1]: 66
2707 00:56:49.603050
2708 00:56:49.603579 Final RX Vref Byte 0 = 46 to rank0
2709 00:56:49.606300 Final RX Vref Byte 1 = 49 to rank0
2710 00:56:49.609650 Final RX Vref Byte 0 = 46 to rank1
2711 00:56:49.612869 Final RX Vref Byte 1 = 49 to rank1==
2712 00:56:49.616646 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 00:56:49.622806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2714 00:56:49.623363 ==
2715 00:56:49.623734 DQS Delay:
2716 00:56:49.624242 DQS0 = 0, DQS1 = 0
2717 00:56:49.626244 DQM Delay:
2718 00:56:49.626698 DQM0 = 114, DQM1 = 105
2719 00:56:49.630122 DQ Delay:
2720 00:56:49.633103 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2721 00:56:49.636151 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2722 00:56:49.640279 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2723 00:56:49.642842 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2724 00:56:49.643302
2725 00:56:49.643737
2726 00:56:49.649298 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2727 00:56:49.653185 CH0 RK0: MR19=404, MR18=B0B
2728 00:56:49.659698 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2729 00:56:49.660156
2730 00:56:49.662878 ----->DramcWriteLeveling(PI) begin...
2731 00:56:49.663341 ==
2732 00:56:49.666122 Dram Type= 6, Freq= 0, CH_0, rank 1
2733 00:56:49.668977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2734 00:56:49.669653 ==
2735 00:56:49.672556 Write leveling (Byte 0): 26 => 26
2736 00:56:49.675779 Write leveling (Byte 1): 24 => 24
2737 00:56:49.679294 DramcWriteLeveling(PI) end<-----
2738 00:56:49.679748
2739 00:56:49.680103 ==
2740 00:56:49.682826 Dram Type= 6, Freq= 0, CH_0, rank 1
2741 00:56:49.689172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2742 00:56:49.689732 ==
2743 00:56:49.690132 [Gating] SW mode calibration
2744 00:56:49.699700 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2745 00:56:49.703095 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2746 00:56:49.705918 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2747 00:56:49.713100 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2748 00:56:49.715521 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2749 00:56:49.719002 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2750 00:56:49.725585 0 11 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
2751 00:56:49.729434 0 11 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2752 00:56:49.732399 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 00:56:49.739226 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 00:56:49.742598 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 00:56:49.745546 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 00:56:49.753060 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 00:56:49.755767 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 00:56:49.758887 0 12 16 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
2759 00:56:49.765659 0 12 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
2760 00:56:49.769667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 00:56:49.772487 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 00:56:49.779248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 00:56:49.783023 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 00:56:49.786175 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 00:56:49.792573 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 00:56:49.795883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2767 00:56:49.799218 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 00:56:49.802483 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 00:56:49.809450 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 00:56:49.812077 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 00:56:49.816124 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 00:56:49.822583 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 00:56:49.825737 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 00:56:49.829067 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 00:56:49.835953 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 00:56:49.839891 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 00:56:49.842546 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 00:56:49.848979 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 00:56:49.852559 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 00:56:49.856229 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 00:56:49.862241 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 00:56:49.866523 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2783 00:56:49.868978 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2784 00:56:49.875645 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2785 00:56:49.876213 Total UI for P1: 0, mck2ui 16
2786 00:56:49.882603 best dqsien dly found for B0: ( 0, 15, 18)
2787 00:56:49.883147 Total UI for P1: 0, mck2ui 16
2788 00:56:49.885550 best dqsien dly found for B1: ( 0, 15, 18)
2789 00:56:49.892819 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2790 00:56:49.895473 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2791 00:56:49.895983
2792 00:56:49.899445 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2793 00:56:49.902388 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2794 00:56:49.905523 [Gating] SW calibration Done
2795 00:56:49.905982 ==
2796 00:56:49.909168 Dram Type= 6, Freq= 0, CH_0, rank 1
2797 00:56:49.912620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2798 00:56:49.913199 ==
2799 00:56:49.916060 RX Vref Scan: 0
2800 00:56:49.916620
2801 00:56:49.917054 RX Vref 0 -> 0, step: 1
2802 00:56:49.917402
2803 00:56:49.919367 RX Delay -40 -> 252, step: 8
2804 00:56:49.922711 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2805 00:56:49.929292 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2806 00:56:49.932069 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2807 00:56:49.936115 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2808 00:56:49.939505 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2809 00:56:49.942388 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2810 00:56:49.949606 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2811 00:56:49.952103 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2812 00:56:49.956286 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2813 00:56:49.959343 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2814 00:56:49.962443 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2815 00:56:49.965743 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2816 00:56:49.971991 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2817 00:56:49.975549 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2818 00:56:49.979297 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2819 00:56:49.983086 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2820 00:56:49.983651 ==
2821 00:56:49.986031 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 00:56:49.992589 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2823 00:56:49.993204 ==
2824 00:56:49.993576 DQS Delay:
2825 00:56:49.995645 DQS0 = 0, DQS1 = 0
2826 00:56:49.996177 DQM Delay:
2827 00:56:49.996548 DQM0 = 113, DQM1 = 107
2828 00:56:49.998879 DQ Delay:
2829 00:56:50.002584 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2830 00:56:50.005832 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2831 00:56:50.009502 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2832 00:56:50.012749 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2833 00:56:50.013309
2834 00:56:50.013674
2835 00:56:50.014012 ==
2836 00:56:50.015533 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 00:56:50.018700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2838 00:56:50.019250 ==
2839 00:56:50.022085
2840 00:56:50.022544
2841 00:56:50.022904 TX Vref Scan disable
2842 00:56:50.026655 == TX Byte 0 ==
2843 00:56:50.028669 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2844 00:56:50.032229 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2845 00:56:50.035382 == TX Byte 1 ==
2846 00:56:50.038521 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2847 00:56:50.042316 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2848 00:56:50.042780 ==
2849 00:56:50.045295 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 00:56:50.053022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2851 00:56:50.053596 ==
2852 00:56:50.062697 TX Vref=22, minBit 9, minWin=25, winSum=417
2853 00:56:50.065952 TX Vref=24, minBit 8, minWin=25, winSum=421
2854 00:56:50.069500 TX Vref=26, minBit 8, minWin=25, winSum=422
2855 00:56:50.072775 TX Vref=28, minBit 1, minWin=26, winSum=432
2856 00:56:50.076091 TX Vref=30, minBit 8, minWin=26, winSum=433
2857 00:56:50.079532 TX Vref=32, minBit 4, minWin=26, winSum=427
2858 00:56:50.086927 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
2859 00:56:50.087485
2860 00:56:50.089728 Final TX Range 1 Vref 30
2861 00:56:50.090207
2862 00:56:50.090670 ==
2863 00:56:50.093476 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 00:56:50.096401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2865 00:56:50.096922 ==
2866 00:56:50.097297
2867 00:56:50.099770
2868 00:56:50.100330 TX Vref Scan disable
2869 00:56:50.102622 == TX Byte 0 ==
2870 00:56:50.106049 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2871 00:56:50.109596 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2872 00:56:50.112875 == TX Byte 1 ==
2873 00:56:50.116594 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2874 00:56:50.120095 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2875 00:56:50.120766
2876 00:56:50.122991 [DATLAT]
2877 00:56:50.123549 Freq=1200, CH0 RK1
2878 00:56:50.123919
2879 00:56:50.126538 DATLAT Default: 0xc
2880 00:56:50.126999 0, 0xFFFF, sum = 0
2881 00:56:50.130022 1, 0xFFFF, sum = 0
2882 00:56:50.130669 2, 0xFFFF, sum = 0
2883 00:56:50.132944 3, 0xFFFF, sum = 0
2884 00:56:50.133503 4, 0xFFFF, sum = 0
2885 00:56:50.136559 5, 0xFFFF, sum = 0
2886 00:56:50.137228 6, 0xFFFF, sum = 0
2887 00:56:50.139079 7, 0xFFFF, sum = 0
2888 00:56:50.139546 8, 0xFFFF, sum = 0
2889 00:56:50.142490 9, 0xFFFF, sum = 0
2890 00:56:50.145848 10, 0xFFFF, sum = 0
2891 00:56:50.146316 11, 0x0, sum = 1
2892 00:56:50.146782 12, 0x0, sum = 2
2893 00:56:50.149222 13, 0x0, sum = 3
2894 00:56:50.149805 14, 0x0, sum = 4
2895 00:56:50.152853 best_step = 12
2896 00:56:50.153450
2897 00:56:50.154039 ==
2898 00:56:50.156430 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 00:56:50.159149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2900 00:56:50.159608 ==
2901 00:56:50.162837 RX Vref Scan: 0
2902 00:56:50.163298
2903 00:56:50.163661 RX Vref 0 -> 0, step: 1
2904 00:56:50.164008
2905 00:56:50.166520 RX Delay -21 -> 252, step: 4
2906 00:56:50.172799 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2907 00:56:50.176144 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2908 00:56:50.179633 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2909 00:56:50.183176 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2910 00:56:50.186513 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2911 00:56:50.192828 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2912 00:56:50.196610 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2913 00:56:50.200181 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2914 00:56:50.203401 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2915 00:56:50.206959 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2916 00:56:50.213181 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2917 00:56:50.216525 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2918 00:56:50.220049 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2919 00:56:50.223715 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2920 00:56:50.226205 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2921 00:56:50.232908 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2922 00:56:50.233445 ==
2923 00:56:50.236682 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 00:56:50.239457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2925 00:56:50.239956 ==
2926 00:56:50.240332 DQS Delay:
2927 00:56:50.243309 DQS0 = 0, DQS1 = 0
2928 00:56:50.243767 DQM Delay:
2929 00:56:50.246117 DQM0 = 114, DQM1 = 105
2930 00:56:50.246568 DQ Delay:
2931 00:56:50.249363 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2932 00:56:50.252608 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2933 00:56:50.256026 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2934 00:56:50.259343 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2935 00:56:50.259851
2936 00:56:50.260212
2937 00:56:50.269326 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2938 00:56:50.272884 CH0 RK1: MR19=404, MR18=D0D
2939 00:56:50.276055 CH0_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2940 00:56:50.279161 [RxdqsGatingPostProcess] freq 1200
2941 00:56:50.285964 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2942 00:56:50.289402 Pre-setting of DQS Precalculation
2943 00:56:50.292823 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2944 00:56:50.293287 ==
2945 00:56:50.296011 Dram Type= 6, Freq= 0, CH_1, rank 0
2946 00:56:50.303098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2947 00:56:50.303649 ==
2948 00:56:50.305960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2949 00:56:50.312624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2950 00:56:50.321018 [CA 0] Center 37 (7~68) winsize 62
2951 00:56:50.325488 [CA 1] Center 37 (7~68) winsize 62
2952 00:56:50.328767 [CA 2] Center 34 (4~65) winsize 62
2953 00:56:50.331967 [CA 3] Center 33 (3~64) winsize 62
2954 00:56:50.334801 [CA 4] Center 32 (2~63) winsize 62
2955 00:56:50.337823 [CA 5] Center 32 (2~63) winsize 62
2956 00:56:50.338285
2957 00:56:50.341448 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2958 00:56:50.341907
2959 00:56:50.344550 [CATrainingPosCal] consider 1 rank data
2960 00:56:50.348448 u2DelayCellTimex100 = 270/100 ps
2961 00:56:50.351421 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2962 00:56:50.355431 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2963 00:56:50.361306 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2964 00:56:50.364650 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2965 00:56:50.368027 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2966 00:56:50.371330 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2967 00:56:50.371890
2968 00:56:50.374630 CA PerBit enable=1, Macro0, CA PI delay=32
2969 00:56:50.375108
2970 00:56:50.378132 [CBTSetCACLKResult] CA Dly = 32
2971 00:56:50.378592 CS Dly: 6 (0~37)
2972 00:56:50.381167 ==
2973 00:56:50.381627 Dram Type= 6, Freq= 0, CH_1, rank 1
2974 00:56:50.387793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2975 00:56:50.388469 ==
2976 00:56:50.391128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2977 00:56:50.397769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2978 00:56:50.406607 [CA 0] Center 37 (7~68) winsize 62
2979 00:56:50.410208 [CA 1] Center 37 (7~68) winsize 62
2980 00:56:50.413324 [CA 2] Center 33 (3~64) winsize 62
2981 00:56:50.416466 [CA 3] Center 33 (3~64) winsize 62
2982 00:56:50.419737 [CA 4] Center 32 (2~63) winsize 62
2983 00:56:50.423188 [CA 5] Center 32 (1~63) winsize 63
2984 00:56:50.423777
2985 00:56:50.426501 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2986 00:56:50.427108
2987 00:56:50.430437 [CATrainingPosCal] consider 2 rank data
2988 00:56:50.433874 u2DelayCellTimex100 = 270/100 ps
2989 00:56:50.436416 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2990 00:56:50.439874 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2991 00:56:50.447057 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2992 00:56:50.449992 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2993 00:56:50.453359 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2994 00:56:50.456564 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2995 00:56:50.457165
2996 00:56:50.459861 CA PerBit enable=1, Macro0, CA PI delay=32
2997 00:56:50.460313
2998 00:56:50.463014 [CBTSetCACLKResult] CA Dly = 32
2999 00:56:50.463562 CS Dly: 6 (0~38)
3000 00:56:50.463921
3001 00:56:50.466439 ----->DramcWriteLeveling(PI) begin...
3002 00:56:50.469853 ==
3003 00:56:50.473094 Dram Type= 6, Freq= 0, CH_1, rank 0
3004 00:56:50.476236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3005 00:56:50.476693 ==
3006 00:56:50.479465 Write leveling (Byte 0): 21 => 21
3007 00:56:50.483178 Write leveling (Byte 1): 21 => 21
3008 00:56:50.486821 DramcWriteLeveling(PI) end<-----
3009 00:56:50.487393
3010 00:56:50.487754 ==
3011 00:56:50.490169 Dram Type= 6, Freq= 0, CH_1, rank 0
3012 00:56:50.493129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3013 00:56:50.493607 ==
3014 00:56:50.496435 [Gating] SW mode calibration
3015 00:56:50.503421 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3016 00:56:50.506672 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3017 00:56:50.513059 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 00:56:50.516351 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 00:56:50.519844 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3020 00:56:50.527126 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3021 00:56:50.529887 0 11 16 | B1->B0 | 3030 2b2b | 1 0 | (1 0) (0 1)
3022 00:56:50.533301 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3023 00:56:50.540104 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 00:56:50.543143 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 00:56:50.546146 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 00:56:50.552775 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 00:56:50.556218 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 00:56:50.560070 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3029 00:56:50.566189 0 12 16 | B1->B0 | 3838 4545 | 0 0 | (1 1) (0 0)
3030 00:56:50.569700 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 00:56:50.573444 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 00:56:50.580067 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 00:56:50.583506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 00:56:50.586780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 00:56:50.593064 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 00:56:50.596690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 00:56:50.599336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3038 00:56:50.606346 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3039 00:56:50.609403 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 00:56:50.613227 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 00:56:50.616222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 00:56:50.623126 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 00:56:50.626833 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 00:56:50.630094 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 00:56:50.636637 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 00:56:50.639666 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 00:56:50.643332 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 00:56:50.650217 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 00:56:50.652833 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 00:56:50.656301 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 00:56:50.662910 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 00:56:50.666033 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3053 00:56:50.670384 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3054 00:56:50.676329 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3055 00:56:50.676835 Total UI for P1: 0, mck2ui 16
3056 00:56:50.683500 best dqsien dly found for B0: ( 0, 15, 14)
3057 00:56:50.687079 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3058 00:56:50.689667 Total UI for P1: 0, mck2ui 16
3059 00:56:50.693266 best dqsien dly found for B1: ( 0, 15, 18)
3060 00:56:50.696387 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3061 00:56:50.699442 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3062 00:56:50.699901
3063 00:56:50.702919 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3064 00:56:50.706511 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3065 00:56:50.709263 [Gating] SW calibration Done
3066 00:56:50.709736 ==
3067 00:56:50.713476 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 00:56:50.716658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3069 00:56:50.717228 ==
3070 00:56:50.720178 RX Vref Scan: 0
3071 00:56:50.720682
3072 00:56:50.722666 RX Vref 0 -> 0, step: 1
3073 00:56:50.723127
3074 00:56:50.723487 RX Delay -40 -> 252, step: 8
3075 00:56:50.729687 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3076 00:56:50.733383 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3077 00:56:50.736180 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3078 00:56:50.739630 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3079 00:56:50.742948 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3080 00:56:50.749294 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3081 00:56:50.752691 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3082 00:56:50.756466 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3083 00:56:50.759909 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3084 00:56:50.762742 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3085 00:56:50.770340 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3086 00:56:50.773275 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3087 00:56:50.776442 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3088 00:56:50.779698 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3089 00:56:50.782959 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3090 00:56:50.789471 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3091 00:56:50.789991 ==
3092 00:56:50.793053 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 00:56:50.795874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3094 00:56:50.796422 ==
3095 00:56:50.796843 DQS Delay:
3096 00:56:50.800175 DQS0 = 0, DQS1 = 0
3097 00:56:50.800630 DQM Delay:
3098 00:56:50.802448 DQM0 = 116, DQM1 = 109
3099 00:56:50.802899 DQ Delay:
3100 00:56:50.806074 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3101 00:56:50.809882 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3102 00:56:50.812872 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3103 00:56:50.816135 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3104 00:56:50.816625
3105 00:56:50.817044
3106 00:56:50.819518 ==
3107 00:56:50.822926 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 00:56:50.826346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3109 00:56:50.826903 ==
3110 00:56:50.827267
3111 00:56:50.827601
3112 00:56:50.829451 TX Vref Scan disable
3113 00:56:50.829911 == TX Byte 0 ==
3114 00:56:50.832696 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3115 00:56:50.839262 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3116 00:56:50.839811 == TX Byte 1 ==
3117 00:56:50.843014 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3118 00:56:50.849626 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3119 00:56:50.850110 ==
3120 00:56:50.852778 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 00:56:50.856301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3122 00:56:50.856888 ==
3123 00:56:50.867322 TX Vref=22, minBit 1, minWin=25, winSum=416
3124 00:56:50.870690 TX Vref=24, minBit 8, minWin=25, winSum=422
3125 00:56:50.874492 TX Vref=26, minBit 9, minWin=25, winSum=425
3126 00:56:50.877695 TX Vref=28, minBit 9, minWin=25, winSum=430
3127 00:56:50.881253 TX Vref=30, minBit 1, minWin=26, winSum=430
3128 00:56:50.885750 TX Vref=32, minBit 0, minWin=26, winSum=430
3129 00:56:50.891158 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3130 00:56:50.891723
3131 00:56:50.894012 Final TX Range 1 Vref 30
3132 00:56:50.894474
3133 00:56:50.894836 ==
3134 00:56:50.897629 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 00:56:50.901308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3136 00:56:50.901770 ==
3137 00:56:50.902136
3138 00:56:50.904295
3139 00:56:50.904802 TX Vref Scan disable
3140 00:56:50.907376 == TX Byte 0 ==
3141 00:56:50.911073 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3142 00:56:50.914627 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3143 00:56:50.917957 == TX Byte 1 ==
3144 00:56:50.920887 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3145 00:56:50.924159 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3146 00:56:50.924618
3147 00:56:50.927796 [DATLAT]
3148 00:56:50.928375 Freq=1200, CH1 RK0
3149 00:56:50.928810
3150 00:56:50.932037 DATLAT Default: 0xd
3151 00:56:50.932616 0, 0xFFFF, sum = 0
3152 00:56:50.934044 1, 0xFFFF, sum = 0
3153 00:56:50.934506 2, 0xFFFF, sum = 0
3154 00:56:50.937943 3, 0xFFFF, sum = 0
3155 00:56:50.938411 4, 0xFFFF, sum = 0
3156 00:56:50.940925 5, 0xFFFF, sum = 0
3157 00:56:50.941395 6, 0xFFFF, sum = 0
3158 00:56:50.944120 7, 0xFFFF, sum = 0
3159 00:56:50.944588 8, 0xFFFF, sum = 0
3160 00:56:50.947524 9, 0xFFFF, sum = 0
3161 00:56:50.951334 10, 0xFFFF, sum = 0
3162 00:56:50.951799 11, 0x0, sum = 1
3163 00:56:50.952172 12, 0x0, sum = 2
3164 00:56:50.954725 13, 0x0, sum = 3
3165 00:56:50.955292 14, 0x0, sum = 4
3166 00:56:50.957380 best_step = 12
3167 00:56:50.957839
3168 00:56:50.958199 ==
3169 00:56:50.960861 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 00:56:50.964075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3171 00:56:50.964541 ==
3172 00:56:50.967829 RX Vref Scan: 1
3173 00:56:50.968284
3174 00:56:50.968648 Set Vref Range= 32 -> 127
3175 00:56:50.969027
3176 00:56:50.970550 RX Vref 32 -> 127, step: 1
3177 00:56:50.971010
3178 00:56:50.974767 RX Delay -21 -> 252, step: 4
3179 00:56:50.975464
3180 00:56:50.977583 Set Vref, RX VrefLevel [Byte0]: 32
3181 00:56:50.981246 [Byte1]: 32
3182 00:56:50.981708
3183 00:56:50.983958 Set Vref, RX VrefLevel [Byte0]: 33
3184 00:56:50.987866 [Byte1]: 33
3185 00:56:50.993081
3186 00:56:50.993623 Set Vref, RX VrefLevel [Byte0]: 34
3187 00:56:50.996048 [Byte1]: 34
3188 00:56:51.000372
3189 00:56:51.000866 Set Vref, RX VrefLevel [Byte0]: 35
3190 00:56:51.003386 [Byte1]: 35
3191 00:56:51.008246
3192 00:56:51.008841 Set Vref, RX VrefLevel [Byte0]: 36
3193 00:56:51.011904 [Byte1]: 36
3194 00:56:51.015572
3195 00:56:51.019254 Set Vref, RX VrefLevel [Byte0]: 37
3196 00:56:51.019784 [Byte1]: 37
3197 00:56:51.023776
3198 00:56:51.024319 Set Vref, RX VrefLevel [Byte0]: 38
3199 00:56:51.026988 [Byte1]: 38
3200 00:56:51.031709
3201 00:56:51.032270 Set Vref, RX VrefLevel [Byte0]: 39
3202 00:56:51.035016 [Byte1]: 39
3203 00:56:51.039415
3204 00:56:51.039888 Set Vref, RX VrefLevel [Byte0]: 40
3205 00:56:51.042647 [Byte1]: 40
3206 00:56:51.047203
3207 00:56:51.047669 Set Vref, RX VrefLevel [Byte0]: 41
3208 00:56:51.051179 [Byte1]: 41
3209 00:56:51.055633
3210 00:56:51.056176 Set Vref, RX VrefLevel [Byte0]: 42
3211 00:56:51.058540 [Byte1]: 42
3212 00:56:51.063101
3213 00:56:51.063625 Set Vref, RX VrefLevel [Byte0]: 43
3214 00:56:51.066426 [Byte1]: 43
3215 00:56:51.071781
3216 00:56:51.072500 Set Vref, RX VrefLevel [Byte0]: 44
3217 00:56:51.074766 [Byte1]: 44
3218 00:56:51.079069
3219 00:56:51.079541 Set Vref, RX VrefLevel [Byte0]: 45
3220 00:56:51.082273 [Byte1]: 45
3221 00:56:51.086917
3222 00:56:51.087662 Set Vref, RX VrefLevel [Byte0]: 46
3223 00:56:51.090053 [Byte1]: 46
3224 00:56:51.094545
3225 00:56:51.095011 Set Vref, RX VrefLevel [Byte0]: 47
3226 00:56:51.098003 [Byte1]: 47
3227 00:56:51.102368
3228 00:56:51.102827 Set Vref, RX VrefLevel [Byte0]: 48
3229 00:56:51.106086 [Byte1]: 48
3230 00:56:51.110988
3231 00:56:51.111330 Set Vref, RX VrefLevel [Byte0]: 49
3232 00:56:51.113811 [Byte1]: 49
3233 00:56:51.118414
3234 00:56:51.118819 Set Vref, RX VrefLevel [Byte0]: 50
3235 00:56:51.121449 [Byte1]: 50
3236 00:56:51.126230
3237 00:56:51.126417 Set Vref, RX VrefLevel [Byte0]: 51
3238 00:56:51.130068 [Byte1]: 51
3239 00:56:51.134317
3240 00:56:51.134472 Set Vref, RX VrefLevel [Byte0]: 52
3241 00:56:51.137500 [Byte1]: 52
3242 00:56:51.142126
3243 00:56:51.142259 Set Vref, RX VrefLevel [Byte0]: 53
3244 00:56:51.145547 [Byte1]: 53
3245 00:56:51.149615
3246 00:56:51.149749 Set Vref, RX VrefLevel [Byte0]: 54
3247 00:56:51.152715 [Byte1]: 54
3248 00:56:51.157418
3249 00:56:51.157607 Set Vref, RX VrefLevel [Byte0]: 55
3250 00:56:51.160908 [Byte1]: 55
3251 00:56:51.165333
3252 00:56:51.165534 Set Vref, RX VrefLevel [Byte0]: 56
3253 00:56:51.168965 [Byte1]: 56
3254 00:56:51.173856
3255 00:56:51.174029 Set Vref, RX VrefLevel [Byte0]: 57
3256 00:56:51.176842 [Byte1]: 57
3257 00:56:51.181820
3258 00:56:51.181954 Set Vref, RX VrefLevel [Byte0]: 58
3259 00:56:51.184675 [Byte1]: 58
3260 00:56:51.189425
3261 00:56:51.189576 Set Vref, RX VrefLevel [Byte0]: 59
3262 00:56:51.193424 [Byte1]: 59
3263 00:56:51.197633
3264 00:56:51.198256 Set Vref, RX VrefLevel [Byte0]: 60
3265 00:56:51.200967 [Byte1]: 60
3266 00:56:51.205530
3267 00:56:51.205998 Set Vref, RX VrefLevel [Byte0]: 61
3268 00:56:51.208646 [Byte1]: 61
3269 00:56:51.213740
3270 00:56:51.217205 Set Vref, RX VrefLevel [Byte0]: 62
3271 00:56:51.219820 [Byte1]: 62
3272 00:56:51.220281
3273 00:56:51.223271 Set Vref, RX VrefLevel [Byte0]: 63
3274 00:56:51.226281 [Byte1]: 63
3275 00:56:51.226599
3276 00:56:51.230226 Set Vref, RX VrefLevel [Byte0]: 64
3277 00:56:51.232759 [Byte1]: 64
3278 00:56:51.237407
3279 00:56:51.237596 Set Vref, RX VrefLevel [Byte0]: 65
3280 00:56:51.240053 [Byte1]: 65
3281 00:56:51.245073
3282 00:56:51.245228 Set Vref, RX VrefLevel [Byte0]: 66
3283 00:56:51.248111 [Byte1]: 66
3284 00:56:51.252437
3285 00:56:51.252553 Final RX Vref Byte 0 = 52 to rank0
3286 00:56:51.256828 Final RX Vref Byte 1 = 49 to rank0
3287 00:56:51.259487 Final RX Vref Byte 0 = 52 to rank1
3288 00:56:51.262913 Final RX Vref Byte 1 = 49 to rank1==
3289 00:56:51.266675 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 00:56:51.272913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3291 00:56:51.273110 ==
3292 00:56:51.273240 DQS Delay:
3293 00:56:51.273353 DQS0 = 0, DQS1 = 0
3294 00:56:51.276266 DQM Delay:
3295 00:56:51.276402 DQM0 = 115, DQM1 = 105
3296 00:56:51.279406 DQ Delay:
3297 00:56:51.283098 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3298 00:56:51.286514 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3299 00:56:51.289222 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3300 00:56:51.292922 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3301 00:56:51.293148
3302 00:56:51.293273
3303 00:56:51.299487 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3304 00:56:51.303446 CH1 RK0: MR19=404, MR18=1A1A
3305 00:56:51.309421 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3306 00:56:51.309645
3307 00:56:51.313001 ----->DramcWriteLeveling(PI) begin...
3308 00:56:51.313348 ==
3309 00:56:51.316730 Dram Type= 6, Freq= 0, CH_1, rank 1
3310 00:56:51.320032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3311 00:56:51.323324 ==
3312 00:56:51.323876 Write leveling (Byte 0): 21 => 21
3313 00:56:51.326565 Write leveling (Byte 1): 21 => 21
3314 00:56:51.329571 DramcWriteLeveling(PI) end<-----
3315 00:56:51.330030
3316 00:56:51.330387 ==
3317 00:56:51.333536 Dram Type= 6, Freq= 0, CH_1, rank 1
3318 00:56:51.339917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3319 00:56:51.340381 ==
3320 00:56:51.340766 [Gating] SW mode calibration
3321 00:56:51.349654 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3322 00:56:51.353106 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3323 00:56:51.356302 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3324 00:56:51.363008 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3325 00:56:51.366529 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3326 00:56:51.369500 0 11 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
3327 00:56:51.376540 0 11 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
3328 00:56:51.380046 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 00:56:51.383098 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3330 00:56:51.389558 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3331 00:56:51.393185 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3332 00:56:51.396273 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3333 00:56:51.402754 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3334 00:56:51.405903 0 12 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3335 00:56:51.409529 0 12 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3336 00:56:51.416182 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 00:56:51.419802 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 00:56:51.423099 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 00:56:51.429722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3340 00:56:51.432745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3341 00:56:51.436550 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3342 00:56:51.443368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3343 00:56:51.446195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3344 00:56:51.449501 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3345 00:56:51.455968 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 00:56:51.459787 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 00:56:51.462752 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 00:56:51.466205 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 00:56:51.472805 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 00:56:51.476692 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 00:56:51.479278 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 00:56:51.486030 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 00:56:51.489261 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 00:56:51.492677 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 00:56:51.499949 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 00:56:51.502496 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 00:56:51.506144 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 00:56:51.512792 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3359 00:56:51.516225 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3360 00:56:51.519464 Total UI for P1: 0, mck2ui 16
3361 00:56:51.522761 best dqsien dly found for B0: ( 0, 15, 12)
3362 00:56:51.525783 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3363 00:56:51.529012 Total UI for P1: 0, mck2ui 16
3364 00:56:51.532702 best dqsien dly found for B1: ( 0, 15, 14)
3365 00:56:51.536393 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3366 00:56:51.538925 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3367 00:56:51.539163
3368 00:56:51.545417 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3369 00:56:51.550603 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3370 00:56:51.550792 [Gating] SW calibration Done
3371 00:56:51.552767 ==
3372 00:56:51.556089 Dram Type= 6, Freq= 0, CH_1, rank 1
3373 00:56:51.559581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3374 00:56:51.559810 ==
3375 00:56:51.559959 RX Vref Scan: 0
3376 00:56:51.560098
3377 00:56:51.563239 RX Vref 0 -> 0, step: 1
3378 00:56:51.563496
3379 00:56:51.565947 RX Delay -40 -> 252, step: 8
3380 00:56:51.569221 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3381 00:56:51.572972 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3382 00:56:51.575881 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3383 00:56:51.582800 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3384 00:56:51.585722 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3385 00:56:51.589329 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3386 00:56:51.592537 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3387 00:56:51.596176 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3388 00:56:51.602595 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3389 00:56:51.606385 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3390 00:56:51.609433 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3391 00:56:51.612530 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3392 00:56:51.616066 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3393 00:56:51.622421 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3394 00:56:51.625838 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3395 00:56:51.629762 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3396 00:56:51.630307 ==
3397 00:56:51.633076 Dram Type= 6, Freq= 0, CH_1, rank 1
3398 00:56:51.636124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3399 00:56:51.636665 ==
3400 00:56:51.639341 DQS Delay:
3401 00:56:51.639874 DQS0 = 0, DQS1 = 0
3402 00:56:51.642585 DQM Delay:
3403 00:56:51.643039 DQM0 = 115, DQM1 = 106
3404 00:56:51.645615 DQ Delay:
3405 00:56:51.649478 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3406 00:56:51.652895 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3407 00:56:51.655534 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3408 00:56:51.659542 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3409 00:56:51.660110
3410 00:56:51.660468
3411 00:56:51.660852 ==
3412 00:56:51.662825 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 00:56:51.666678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3414 00:56:51.667137 ==
3415 00:56:51.667495
3416 00:56:51.667823
3417 00:56:51.669622 TX Vref Scan disable
3418 00:56:51.672734 == TX Byte 0 ==
3419 00:56:51.676388 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3420 00:56:51.679168 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3421 00:56:51.682572 == TX Byte 1 ==
3422 00:56:51.685769 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3423 00:56:51.689003 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3424 00:56:51.689506 ==
3425 00:56:51.692784 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 00:56:51.695624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3427 00:56:51.696078 ==
3428 00:56:51.708889 TX Vref=22, minBit 8, minWin=25, winSum=422
3429 00:56:51.712370 TX Vref=24, minBit 0, minWin=26, winSum=425
3430 00:56:51.715552 TX Vref=26, minBit 9, minWin=25, winSum=429
3431 00:56:51.718717 TX Vref=28, minBit 8, minWin=26, winSum=433
3432 00:56:51.722022 TX Vref=30, minBit 9, minWin=26, winSum=436
3433 00:56:51.725660 TX Vref=32, minBit 0, minWin=26, winSum=431
3434 00:56:51.732121 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3435 00:56:51.732828
3436 00:56:51.735417 Final TX Range 1 Vref 30
3437 00:56:51.736099
3438 00:56:51.736480 ==
3439 00:56:51.738802 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 00:56:51.741931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3441 00:56:51.742516 ==
3442 00:56:51.742883
3443 00:56:51.745710
3444 00:56:51.746164 TX Vref Scan disable
3445 00:56:51.748631 == TX Byte 0 ==
3446 00:56:51.752282 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3447 00:56:51.755439 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3448 00:56:51.759227 == TX Byte 1 ==
3449 00:56:51.762196 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3450 00:56:51.765625 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3451 00:56:51.766195
3452 00:56:51.768528 [DATLAT]
3453 00:56:51.769118 Freq=1200, CH1 RK1
3454 00:56:51.769490
3455 00:56:51.772103 DATLAT Default: 0xc
3456 00:56:51.772652 0, 0xFFFF, sum = 0
3457 00:56:51.776114 1, 0xFFFF, sum = 0
3458 00:56:51.776672 2, 0xFFFF, sum = 0
3459 00:56:51.778853 3, 0xFFFF, sum = 0
3460 00:56:51.779455 4, 0xFFFF, sum = 0
3461 00:56:51.781896 5, 0xFFFF, sum = 0
3462 00:56:51.782375 6, 0xFFFF, sum = 0
3463 00:56:51.785362 7, 0xFFFF, sum = 0
3464 00:56:51.785826 8, 0xFFFF, sum = 0
3465 00:56:51.789198 9, 0xFFFF, sum = 0
3466 00:56:51.791728 10, 0xFFFF, sum = 0
3467 00:56:51.792187 11, 0x0, sum = 1
3468 00:56:51.792555 12, 0x0, sum = 2
3469 00:56:51.794905 13, 0x0, sum = 3
3470 00:56:51.795365 14, 0x0, sum = 4
3471 00:56:51.798491 best_step = 12
3472 00:56:51.799044
3473 00:56:51.799402 ==
3474 00:56:51.801847 Dram Type= 6, Freq= 0, CH_1, rank 1
3475 00:56:51.805098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3476 00:56:51.805557 ==
3477 00:56:51.808469 RX Vref Scan: 0
3478 00:56:51.808979
3479 00:56:51.809345 RX Vref 0 -> 0, step: 1
3480 00:56:51.812196
3481 00:56:51.812648 RX Delay -21 -> 252, step: 4
3482 00:56:51.819187 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3483 00:56:51.822269 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3484 00:56:51.825424 iDelay=199, Bit 2, Center 106 (35 ~ 178) 144
3485 00:56:51.829382 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3486 00:56:51.833387 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3487 00:56:51.838518 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3488 00:56:51.841917 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3489 00:56:51.845657 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3490 00:56:51.848863 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3491 00:56:51.851763 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3492 00:56:51.859015 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3493 00:56:51.862491 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3494 00:56:51.865108 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3495 00:56:51.868852 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3496 00:56:51.871792 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3497 00:56:51.878689 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3498 00:56:51.879237 ==
3499 00:56:51.881990 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 00:56:51.885283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3501 00:56:51.885740 ==
3502 00:56:51.886101 DQS Delay:
3503 00:56:51.888420 DQS0 = 0, DQS1 = 0
3504 00:56:51.888923 DQM Delay:
3505 00:56:51.891905 DQM0 = 114, DQM1 = 104
3506 00:56:51.892448 DQ Delay:
3507 00:56:51.895272 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3508 00:56:51.898481 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3509 00:56:51.901584 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3510 00:56:51.905209 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =110
3511 00:56:51.905664
3512 00:56:51.906019
3513 00:56:51.915172 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3514 00:56:51.919092 CH1 RK1: MR19=404, MR18=E0E
3515 00:56:51.922149 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3516 00:56:51.925348 [RxdqsGatingPostProcess] freq 1200
3517 00:56:51.931943 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3518 00:56:51.935686 Pre-setting of DQS Precalculation
3519 00:56:51.938112 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3520 00:56:51.948630 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3521 00:56:51.955685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3522 00:56:51.956237
3523 00:56:51.956595
3524 00:56:51.958747 [Calibration Summary] 2400 Mbps
3525 00:56:51.959298 CH 0, Rank 0
3526 00:56:51.962154 SW Impedance : PASS
3527 00:56:51.962703 DUTY Scan : NO K
3528 00:56:51.965674 ZQ Calibration : PASS
3529 00:56:51.968997 Jitter Meter : NO K
3530 00:56:51.969546 CBT Training : PASS
3531 00:56:51.972241 Write leveling : PASS
3532 00:56:51.975168 RX DQS gating : PASS
3533 00:56:51.975625 RX DQ/DQS(RDDQC) : PASS
3534 00:56:51.979482 TX DQ/DQS : PASS
3535 00:56:51.981946 RX DATLAT : PASS
3536 00:56:51.982580 RX DQ/DQS(Engine): PASS
3537 00:56:51.985267 TX OE : NO K
3538 00:56:51.985724 All Pass.
3539 00:56:51.986082
3540 00:56:51.988770 CH 0, Rank 1
3541 00:56:51.989226 SW Impedance : PASS
3542 00:56:51.991959 DUTY Scan : NO K
3543 00:56:51.992513 ZQ Calibration : PASS
3544 00:56:51.995528 Jitter Meter : NO K
3545 00:56:51.998800 CBT Training : PASS
3546 00:56:51.999254 Write leveling : PASS
3547 00:56:52.001431 RX DQS gating : PASS
3548 00:56:52.005458 RX DQ/DQS(RDDQC) : PASS
3549 00:56:52.006006 TX DQ/DQS : PASS
3550 00:56:52.008162 RX DATLAT : PASS
3551 00:56:52.011786 RX DQ/DQS(Engine): PASS
3552 00:56:52.012242 TX OE : NO K
3553 00:56:52.015617 All Pass.
3554 00:56:52.016175
3555 00:56:52.016537 CH 1, Rank 0
3556 00:56:52.018497 SW Impedance : PASS
3557 00:56:52.019069 DUTY Scan : NO K
3558 00:56:52.021609 ZQ Calibration : PASS
3559 00:56:52.024756 Jitter Meter : NO K
3560 00:56:52.025351 CBT Training : PASS
3561 00:56:52.028333 Write leveling : PASS
3562 00:56:52.032101 RX DQS gating : PASS
3563 00:56:52.032652 RX DQ/DQS(RDDQC) : PASS
3564 00:56:52.035206 TX DQ/DQS : PASS
3565 00:56:52.038562 RX DATLAT : PASS
3566 00:56:52.039019 RX DQ/DQS(Engine): PASS
3567 00:56:52.041999 TX OE : NO K
3568 00:56:52.042455 All Pass.
3569 00:56:52.042814
3570 00:56:52.045423 CH 1, Rank 1
3571 00:56:52.045877 SW Impedance : PASS
3572 00:56:52.047899 DUTY Scan : NO K
3573 00:56:52.048419 ZQ Calibration : PASS
3574 00:56:52.052133 Jitter Meter : NO K
3575 00:56:52.055512 CBT Training : PASS
3576 00:56:52.056061 Write leveling : PASS
3577 00:56:52.058639 RX DQS gating : PASS
3578 00:56:52.062111 RX DQ/DQS(RDDQC) : PASS
3579 00:56:52.062666 TX DQ/DQS : PASS
3580 00:56:52.064804 RX DATLAT : PASS
3581 00:56:52.068854 RX DQ/DQS(Engine): PASS
3582 00:56:52.069409 TX OE : NO K
3583 00:56:52.071867 All Pass.
3584 00:56:52.072420
3585 00:56:52.072826 DramC Write-DBI off
3586 00:56:52.075532 PER_BANK_REFRESH: Hybrid Mode
3587 00:56:52.076085 TX_TRACKING: ON
3588 00:56:52.085065 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3589 00:56:52.088929 [FAST_K] Save calibration result to emmc
3590 00:56:52.091432 dramc_set_vcore_voltage set vcore to 650000
3591 00:56:52.095575 Read voltage for 600, 5
3592 00:56:52.096154 Vio18 = 0
3593 00:56:52.098674 Vcore = 650000
3594 00:56:52.099255 Vdram = 0
3595 00:56:52.099753 Vddq = 0
3596 00:56:52.100213 Vmddr = 0
3597 00:56:52.105148 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3598 00:56:52.111644 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3599 00:56:52.112250 MEM_TYPE=3, freq_sel=19
3600 00:56:52.115690 sv_algorithm_assistance_LP4_1600
3601 00:56:52.118292 ============ PULL DRAM RESETB DOWN ============
3602 00:56:52.124825 ========== PULL DRAM RESETB DOWN end =========
3603 00:56:52.128460 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3604 00:56:52.131411 ===================================
3605 00:56:52.135562 LPDDR4 DRAM CONFIGURATION
3606 00:56:52.137888 ===================================
3607 00:56:52.138369 EX_ROW_EN[0] = 0x0
3608 00:56:52.141574 EX_ROW_EN[1] = 0x0
3609 00:56:52.142050 LP4Y_EN = 0x0
3610 00:56:52.144898 WORK_FSP = 0x0
3611 00:56:52.145372 WL = 0x2
3612 00:56:52.147894 RL = 0x2
3613 00:56:52.151398 BL = 0x2
3614 00:56:52.151896 RPST = 0x0
3615 00:56:52.154675 RD_PRE = 0x0
3616 00:56:52.155256 WR_PRE = 0x1
3617 00:56:52.158531 WR_PST = 0x0
3618 00:56:52.159106 DBI_WR = 0x0
3619 00:56:52.161426 DBI_RD = 0x0
3620 00:56:52.161901 OTF = 0x1
3621 00:56:52.165216 ===================================
3622 00:56:52.167932 ===================================
3623 00:56:52.172026 ANA top config
3624 00:56:52.175160 ===================================
3625 00:56:52.175744 DLL_ASYNC_EN = 0
3626 00:56:52.178034 ALL_SLAVE_EN = 1
3627 00:56:52.181662 NEW_RANK_MODE = 1
3628 00:56:52.184801 DLL_IDLE_MODE = 1
3629 00:56:52.185283 LP45_APHY_COMB_EN = 1
3630 00:56:52.188188 TX_ODT_DIS = 1
3631 00:56:52.190978 NEW_8X_MODE = 1
3632 00:56:52.195028 ===================================
3633 00:56:52.198091 ===================================
3634 00:56:52.201206 data_rate = 1200
3635 00:56:52.204612 CKR = 1
3636 00:56:52.207726 DQ_P2S_RATIO = 8
3637 00:56:52.211132 ===================================
3638 00:56:52.211691 CA_P2S_RATIO = 8
3639 00:56:52.214283 DQ_CA_OPEN = 0
3640 00:56:52.217832 DQ_SEMI_OPEN = 0
3641 00:56:52.220772 CA_SEMI_OPEN = 0
3642 00:56:52.224296 CA_FULL_RATE = 0
3643 00:56:52.227538 DQ_CKDIV4_EN = 1
3644 00:56:52.228116 CA_CKDIV4_EN = 1
3645 00:56:52.230712 CA_PREDIV_EN = 0
3646 00:56:52.234327 PH8_DLY = 0
3647 00:56:52.237525 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3648 00:56:52.240335 DQ_AAMCK_DIV = 4
3649 00:56:52.243634 CA_AAMCK_DIV = 4
3650 00:56:52.244111 CA_ADMCK_DIV = 4
3651 00:56:52.247652 DQ_TRACK_CA_EN = 0
3652 00:56:52.250572 CA_PICK = 600
3653 00:56:52.253973 CA_MCKIO = 600
3654 00:56:52.256926 MCKIO_SEMI = 0
3655 00:56:52.260181 PLL_FREQ = 2288
3656 00:56:52.263762 DQ_UI_PI_RATIO = 32
3657 00:56:52.264239 CA_UI_PI_RATIO = 0
3658 00:56:52.267090 ===================================
3659 00:56:52.270848 ===================================
3660 00:56:52.273432 memory_type:LPDDR4
3661 00:56:52.276576 GP_NUM : 10
3662 00:56:52.277090 SRAM_EN : 1
3663 00:56:52.280250 MD32_EN : 0
3664 00:56:52.283737 ===================================
3665 00:56:52.286915 [ANA_INIT] >>>>>>>>>>>>>>
3666 00:56:52.290131 <<<<<< [CONFIGURE PHASE]: ANA_TX
3667 00:56:52.293958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3668 00:56:52.297039 ===================================
3669 00:56:52.297502 data_rate = 1200,PCW = 0X5800
3670 00:56:52.299895 ===================================
3671 00:56:52.306723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3672 00:56:52.309958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3673 00:56:52.316680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3674 00:56:52.319805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3675 00:56:52.323384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3676 00:56:52.327006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3677 00:56:52.330502 [ANA_INIT] flow start
3678 00:56:52.333370 [ANA_INIT] PLL >>>>>>>>
3679 00:56:52.333833 [ANA_INIT] PLL <<<<<<<<
3680 00:56:52.336248 [ANA_INIT] MIDPI >>>>>>>>
3681 00:56:52.340456 [ANA_INIT] MIDPI <<<<<<<<
3682 00:56:52.341076 [ANA_INIT] DLL >>>>>>>>
3683 00:56:52.343595 [ANA_INIT] flow end
3684 00:56:52.346276 ============ LP4 DIFF to SE enter ============
3685 00:56:52.352986 ============ LP4 DIFF to SE exit ============
3686 00:56:52.353564 [ANA_INIT] <<<<<<<<<<<<<
3687 00:56:52.357260 [Flow] Enable top DCM control >>>>>
3688 00:56:52.359945 [Flow] Enable top DCM control <<<<<
3689 00:56:52.363683 Enable DLL master slave shuffle
3690 00:56:52.369401 ==============================================================
3691 00:56:52.369975 Gating Mode config
3692 00:56:52.376490 ==============================================================
3693 00:56:52.379019 Config description:
3694 00:56:52.385807 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3695 00:56:52.396163 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3696 00:56:52.399644 SELPH_MODE 0: By rank 1: By Phase
3697 00:56:52.406360 ==============================================================
3698 00:56:52.409023 GAT_TRACK_EN = 1
3699 00:56:52.409480 RX_GATING_MODE = 2
3700 00:56:52.412509 RX_GATING_TRACK_MODE = 2
3701 00:56:52.415741 SELPH_MODE = 1
3702 00:56:52.419061 PICG_EARLY_EN = 1
3703 00:56:52.422411 VALID_LAT_VALUE = 1
3704 00:56:52.429352 ==============================================================
3705 00:56:52.432659 Enter into Gating configuration >>>>
3706 00:56:52.435791 Exit from Gating configuration <<<<
3707 00:56:52.438776 Enter into DVFS_PRE_config >>>>>
3708 00:56:52.448612 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3709 00:56:52.452265 Exit from DVFS_PRE_config <<<<<
3710 00:56:52.455608 Enter into PICG configuration >>>>
3711 00:56:52.458781 Exit from PICG configuration <<<<
3712 00:56:52.461766 [RX_INPUT] configuration >>>>>
3713 00:56:52.465309 [RX_INPUT] configuration <<<<<
3714 00:56:52.468425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3715 00:56:52.474872 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3716 00:56:52.481737 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3717 00:56:52.488239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3718 00:56:52.491299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3719 00:56:52.498303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3720 00:56:52.505051 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3721 00:56:52.508665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3722 00:56:52.511193 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3723 00:56:52.514875 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3724 00:56:52.518156 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3725 00:56:52.524490 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 00:56:52.528325 ===================================
3727 00:56:52.531196 LPDDR4 DRAM CONFIGURATION
3728 00:56:52.535051 ===================================
3729 00:56:52.535560 EX_ROW_EN[0] = 0x0
3730 00:56:52.538163 EX_ROW_EN[1] = 0x0
3731 00:56:52.538676 LP4Y_EN = 0x0
3732 00:56:52.541086 WORK_FSP = 0x0
3733 00:56:52.541499 WL = 0x2
3734 00:56:52.543976 RL = 0x2
3735 00:56:52.544599 BL = 0x2
3736 00:56:52.547591 RPST = 0x0
3737 00:56:52.548001 RD_PRE = 0x0
3738 00:56:52.550844 WR_PRE = 0x1
3739 00:56:52.553735 WR_PST = 0x0
3740 00:56:52.554146 DBI_WR = 0x0
3741 00:56:52.557350 DBI_RD = 0x0
3742 00:56:52.558111 OTF = 0x1
3743 00:56:52.561046 ===================================
3744 00:56:52.564314 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3745 00:56:52.567855 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3746 00:56:52.574360 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 00:56:52.577409 ===================================
3748 00:56:52.580659 LPDDR4 DRAM CONFIGURATION
3749 00:56:52.583709 ===================================
3750 00:56:52.584127 EX_ROW_EN[0] = 0x10
3751 00:56:52.587618 EX_ROW_EN[1] = 0x0
3752 00:56:52.588035 LP4Y_EN = 0x0
3753 00:56:52.590442 WORK_FSP = 0x0
3754 00:56:52.590861 WL = 0x2
3755 00:56:52.593464 RL = 0x2
3756 00:56:52.593879 BL = 0x2
3757 00:56:52.597053 RPST = 0x0
3758 00:56:52.597471 RD_PRE = 0x0
3759 00:56:52.600585 WR_PRE = 0x1
3760 00:56:52.601047 WR_PST = 0x0
3761 00:56:52.603507 DBI_WR = 0x0
3762 00:56:52.607732 DBI_RD = 0x0
3763 00:56:52.608257 OTF = 0x1
3764 00:56:52.610572 ===================================
3765 00:56:52.616572 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3766 00:56:52.620505 nWR fixed to 30
3767 00:56:52.623992 [ModeRegInit_LP4] CH0 RK0
3768 00:56:52.624527 [ModeRegInit_LP4] CH0 RK1
3769 00:56:52.627407 [ModeRegInit_LP4] CH1 RK0
3770 00:56:52.630878 [ModeRegInit_LP4] CH1 RK1
3771 00:56:52.631308 match AC timing 16
3772 00:56:52.636856 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3773 00:56:52.640769 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3774 00:56:52.643447 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3775 00:56:52.649992 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3776 00:56:52.653905 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3777 00:56:52.654338 ==
3778 00:56:52.657008 Dram Type= 6, Freq= 0, CH_0, rank 0
3779 00:56:52.660947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3780 00:56:52.661487 ==
3781 00:56:52.667131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3782 00:56:52.674180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3783 00:56:52.677290 [CA 0] Center 36 (6~66) winsize 61
3784 00:56:52.680147 [CA 1] Center 35 (5~66) winsize 62
3785 00:56:52.683753 [CA 2] Center 34 (4~65) winsize 62
3786 00:56:52.686936 [CA 3] Center 34 (4~65) winsize 62
3787 00:56:52.689827 [CA 4] Center 33 (3~64) winsize 62
3788 00:56:52.693392 [CA 5] Center 33 (3~64) winsize 62
3789 00:56:52.693807
3790 00:56:52.696690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3791 00:56:52.697235
3792 00:56:52.699944 [CATrainingPosCal] consider 1 rank data
3793 00:56:52.703328 u2DelayCellTimex100 = 270/100 ps
3794 00:56:52.707512 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3795 00:56:52.709872 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3796 00:56:52.713498 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3797 00:56:52.716989 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3798 00:56:52.720361 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3799 00:56:52.727095 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3800 00:56:52.727658
3801 00:56:52.730560 CA PerBit enable=1, Macro0, CA PI delay=33
3802 00:56:52.731105
3803 00:56:52.732995 [CBTSetCACLKResult] CA Dly = 33
3804 00:56:52.733408 CS Dly: 5 (0~36)
3805 00:56:52.733753 ==
3806 00:56:52.736624 Dram Type= 6, Freq= 0, CH_0, rank 1
3807 00:56:52.740204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3808 00:56:52.744383 ==
3809 00:56:52.746905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3810 00:56:52.753070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3811 00:56:52.756857 [CA 0] Center 35 (5~66) winsize 62
3812 00:56:52.759903 [CA 1] Center 35 (5~66) winsize 62
3813 00:56:52.763561 [CA 2] Center 34 (4~65) winsize 62
3814 00:56:52.766311 [CA 3] Center 34 (4~65) winsize 62
3815 00:56:52.769831 [CA 4] Center 33 (3~64) winsize 62
3816 00:56:52.773151 [CA 5] Center 33 (3~64) winsize 62
3817 00:56:52.773704
3818 00:56:52.776237 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3819 00:56:52.776850
3820 00:56:52.779998 [CATrainingPosCal] consider 2 rank data
3821 00:56:52.783262 u2DelayCellTimex100 = 270/100 ps
3822 00:56:52.786220 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3823 00:56:52.789893 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3824 00:56:52.792892 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3825 00:56:52.800121 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3826 00:56:52.802671 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3827 00:56:52.806443 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3828 00:56:52.806998
3829 00:56:52.809475 CA PerBit enable=1, Macro0, CA PI delay=33
3830 00:56:52.809983
3831 00:56:52.812685 [CBTSetCACLKResult] CA Dly = 33
3832 00:56:52.813174 CS Dly: 5 (0~36)
3833 00:56:52.813529
3834 00:56:52.815601 ----->DramcWriteLeveling(PI) begin...
3835 00:56:52.816066 ==
3836 00:56:52.819524 Dram Type= 6, Freq= 0, CH_0, rank 0
3837 00:56:52.826257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3838 00:56:52.826806 ==
3839 00:56:52.829205 Write leveling (Byte 0): 32 => 32
3840 00:56:52.832396 Write leveling (Byte 1): 31 => 31
3841 00:56:52.835960 DramcWriteLeveling(PI) end<-----
3842 00:56:52.836516
3843 00:56:52.836938 ==
3844 00:56:52.839192 Dram Type= 6, Freq= 0, CH_0, rank 0
3845 00:56:52.842350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3846 00:56:52.843030 ==
3847 00:56:52.845662 [Gating] SW mode calibration
3848 00:56:52.852525 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3849 00:56:52.855833 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3850 00:56:52.862147 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3851 00:56:52.865561 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3852 00:56:52.869434 0 5 8 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (1 0)
3853 00:56:52.875640 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3854 00:56:52.878635 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 00:56:52.881815 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 00:56:52.888888 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 00:56:52.892265 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3858 00:56:52.895423 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3859 00:56:52.901981 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3860 00:56:52.905273 0 6 8 | B1->B0 | 2a2a 2e2e | 0 0 | (0 0) (0 0)
3861 00:56:52.909282 0 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3862 00:56:52.915565 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 00:56:52.919221 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 00:56:52.922035 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 00:56:52.928901 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 00:56:52.931802 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3867 00:56:52.935237 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3868 00:56:52.941941 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3869 00:56:52.945279 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3870 00:56:52.948496 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 00:56:52.955027 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 00:56:52.958945 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 00:56:52.961369 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 00:56:52.968813 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 00:56:52.971545 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 00:56:52.974625 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 00:56:52.981219 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 00:56:52.984690 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 00:56:52.988542 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 00:56:52.994546 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 00:56:52.997797 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 00:56:53.001241 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 00:56:53.008215 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3884 00:56:53.011891 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 00:56:53.014446 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3886 00:56:53.017573 Total UI for P1: 0, mck2ui 16
3887 00:56:53.021049 best dqsien dly found for B0: ( 0, 9, 10)
3888 00:56:53.028479 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3889 00:56:53.029049 Total UI for P1: 0, mck2ui 16
3890 00:56:53.031315 best dqsien dly found for B1: ( 0, 9, 12)
3891 00:56:53.037472 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3892 00:56:53.041214 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3893 00:56:53.041689
3894 00:56:53.044337 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3895 00:56:53.047690 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3896 00:56:53.050776 [Gating] SW calibration Done
3897 00:56:53.051449 ==
3898 00:56:53.054000 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 00:56:53.057474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3900 00:56:53.058034 ==
3901 00:56:53.060918 RX Vref Scan: 0
3902 00:56:53.061483
3903 00:56:53.061974 RX Vref 0 -> 0, step: 1
3904 00:56:53.062439
3905 00:56:53.064474 RX Delay -230 -> 252, step: 16
3906 00:56:53.070845 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3907 00:56:53.074567 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3908 00:56:53.077425 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3909 00:56:53.081023 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3910 00:56:53.084202 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3911 00:56:53.090838 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3912 00:56:53.093732 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3913 00:56:53.097866 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3914 00:56:53.100535 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3915 00:56:53.107566 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3916 00:56:53.110820 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3917 00:56:53.113960 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3918 00:56:53.117950 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3919 00:56:53.124424 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3920 00:56:53.127436 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3921 00:56:53.130755 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3922 00:56:53.131271 ==
3923 00:56:53.134285 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 00:56:53.137765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3925 00:56:53.138287 ==
3926 00:56:53.140104 DQS Delay:
3927 00:56:53.140519 DQS0 = 0, DQS1 = 0
3928 00:56:53.143633 DQM Delay:
3929 00:56:53.144048 DQM0 = 38, DQM1 = 33
3930 00:56:53.144375 DQ Delay:
3931 00:56:53.147032 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3932 00:56:53.150413 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3933 00:56:53.153394 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3934 00:56:53.156642 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3935 00:56:53.157081
3936 00:56:53.157408
3937 00:56:53.161073 ==
3938 00:56:53.164063 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 00:56:53.166844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3940 00:56:53.167266 ==
3941 00:56:53.167596
3942 00:56:53.167899
3943 00:56:53.170155 TX Vref Scan disable
3944 00:56:53.170576 == TX Byte 0 ==
3945 00:56:53.177705 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3946 00:56:53.180235 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3947 00:56:53.180821 == TX Byte 1 ==
3948 00:56:53.186758 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3949 00:56:53.189709 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3950 00:56:53.190144 ==
3951 00:56:53.193137 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 00:56:53.197186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3953 00:56:53.197644 ==
3954 00:56:53.198085
3955 00:56:53.198499
3956 00:56:53.199628 TX Vref Scan disable
3957 00:56:53.203003 == TX Byte 0 ==
3958 00:56:53.206580 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3959 00:56:53.209370 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3960 00:56:53.212766 == TX Byte 1 ==
3961 00:56:53.216234 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3962 00:56:53.219274 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3963 00:56:53.219848
3964 00:56:53.223051 [DATLAT]
3965 00:56:53.223465 Freq=600, CH0 RK0
3966 00:56:53.223809
3967 00:56:53.225830 DATLAT Default: 0x9
3968 00:56:53.226176 0, 0xFFFF, sum = 0
3969 00:56:53.229355 1, 0xFFFF, sum = 0
3970 00:56:53.229777 2, 0xFFFF, sum = 0
3971 00:56:53.233271 3, 0xFFFF, sum = 0
3972 00:56:53.233706 4, 0xFFFF, sum = 0
3973 00:56:53.235806 5, 0xFFFF, sum = 0
3974 00:56:53.236230 6, 0xFFFF, sum = 0
3975 00:56:53.239351 7, 0x0, sum = 1
3976 00:56:53.239772 8, 0x0, sum = 2
3977 00:56:53.242832 9, 0x0, sum = 3
3978 00:56:53.243298 10, 0x0, sum = 4
3979 00:56:53.245846 best_step = 8
3980 00:56:53.246259
3981 00:56:53.246587 ==
3982 00:56:53.249011 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 00:56:53.252537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3984 00:56:53.252992 ==
3985 00:56:53.256465 RX Vref Scan: 1
3986 00:56:53.256926
3987 00:56:53.257260 RX Vref 0 -> 0, step: 1
3988 00:56:53.257569
3989 00:56:53.259464 RX Delay -195 -> 252, step: 8
3990 00:56:53.259919
3991 00:56:53.262999 Set Vref, RX VrefLevel [Byte0]: 46
3992 00:56:53.265542 [Byte1]: 49
3993 00:56:53.270112
3994 00:56:53.270617 Final RX Vref Byte 0 = 46 to rank0
3995 00:56:53.273868 Final RX Vref Byte 1 = 49 to rank0
3996 00:56:53.276490 Final RX Vref Byte 0 = 46 to rank1
3997 00:56:53.279401 Final RX Vref Byte 1 = 49 to rank1==
3998 00:56:53.282806 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 00:56:53.289479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4000 00:56:53.289965 ==
4001 00:56:53.290302 DQS Delay:
4002 00:56:53.292547 DQS0 = 0, DQS1 = 0
4003 00:56:53.293045 DQM Delay:
4004 00:56:53.293380 DQM0 = 41, DQM1 = 30
4005 00:56:53.295798 DQ Delay:
4006 00:56:53.299704 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4007 00:56:53.302920 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4008 00:56:53.306486 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4009 00:56:53.309301 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4010 00:56:53.309713
4011 00:56:53.310036
4012 00:56:53.316535 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4013 00:56:53.319296 CH0 RK0: MR19=808, MR18=5656
4014 00:56:53.325879 CH0_RK0: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
4015 00:56:53.326428
4016 00:56:53.329481 ----->DramcWriteLeveling(PI) begin...
4017 00:56:53.329946 ==
4018 00:56:53.333163 Dram Type= 6, Freq= 0, CH_0, rank 1
4019 00:56:53.336382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4020 00:56:53.336834 ==
4021 00:56:53.340252 Write leveling (Byte 0): 30 => 30
4022 00:56:53.342509 Write leveling (Byte 1): 30 => 30
4023 00:56:53.345575 DramcWriteLeveling(PI) end<-----
4024 00:56:53.345993
4025 00:56:53.346322 ==
4026 00:56:53.349003 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 00:56:53.352453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4028 00:56:53.352904 ==
4029 00:56:53.355550 [Gating] SW mode calibration
4030 00:56:53.362469 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4031 00:56:53.368626 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4032 00:56:53.372265 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 00:56:53.379014 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 00:56:53.382427 0 5 8 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
4035 00:56:53.385593 0 5 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
4036 00:56:53.392759 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 00:56:53.395674 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 00:56:53.398587 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 00:56:53.404873 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 00:56:53.408353 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 00:56:53.411696 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 00:56:53.418289 0 6 8 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (1 1)
4043 00:56:53.421803 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4044 00:56:53.424661 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 00:56:53.431250 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 00:56:53.434726 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 00:56:53.438061 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 00:56:53.445034 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 00:56:53.447961 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 00:56:53.451763 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4051 00:56:53.458164 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4052 00:56:53.462067 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 00:56:53.465068 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 00:56:53.471240 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 00:56:53.474686 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 00:56:53.478063 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 00:56:53.484640 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 00:56:53.488079 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 00:56:53.490728 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 00:56:53.497729 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 00:56:53.501154 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 00:56:53.504972 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 00:56:53.510882 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 00:56:53.514307 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 00:56:53.517465 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 00:56:53.524312 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4067 00:56:53.527831 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 00:56:53.531011 Total UI for P1: 0, mck2ui 16
4069 00:56:53.533936 best dqsien dly found for B0: ( 0, 9, 8)
4070 00:56:53.537284 Total UI for P1: 0, mck2ui 16
4071 00:56:53.541247 best dqsien dly found for B1: ( 0, 9, 8)
4072 00:56:53.544337 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4073 00:56:53.548106 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4074 00:56:53.548677
4075 00:56:53.550654 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4076 00:56:53.553768 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4077 00:56:53.557203 [Gating] SW calibration Done
4078 00:56:53.557661 ==
4079 00:56:53.560928 Dram Type= 6, Freq= 0, CH_0, rank 1
4080 00:56:53.564234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4081 00:56:53.564846 ==
4082 00:56:53.567799 RX Vref Scan: 0
4083 00:56:53.568358
4084 00:56:53.568766 RX Vref 0 -> 0, step: 1
4085 00:56:53.570898
4086 00:56:53.571355 RX Delay -230 -> 252, step: 16
4087 00:56:53.577820 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4088 00:56:53.580702 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4089 00:56:53.584040 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4090 00:56:53.587560 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4091 00:56:53.590707 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4092 00:56:53.597111 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4093 00:56:53.601113 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4094 00:56:53.604267 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4095 00:56:53.607993 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4096 00:56:53.614101 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4097 00:56:53.617380 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4098 00:56:53.620492 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4099 00:56:53.624087 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4100 00:56:53.630302 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4101 00:56:53.634015 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4102 00:56:53.637021 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4103 00:56:53.637483 ==
4104 00:56:53.640573 Dram Type= 6, Freq= 0, CH_0, rank 1
4105 00:56:53.643664 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4106 00:56:53.644259 ==
4107 00:56:53.647430 DQS Delay:
4108 00:56:53.647851 DQS0 = 0, DQS1 = 0
4109 00:56:53.650064 DQM Delay:
4110 00:56:53.650478 DQM0 = 41, DQM1 = 33
4111 00:56:53.653648 DQ Delay:
4112 00:56:53.654065 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4113 00:56:53.656660 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4114 00:56:53.660084 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4115 00:56:53.663525 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4116 00:56:53.666846
4117 00:56:53.667266
4118 00:56:53.667595 ==
4119 00:56:53.669853 Dram Type= 6, Freq= 0, CH_0, rank 1
4120 00:56:53.673226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4121 00:56:53.673647 ==
4122 00:56:53.674105
4123 00:56:53.674441
4124 00:56:53.677465 TX Vref Scan disable
4125 00:56:53.677962 == TX Byte 0 ==
4126 00:56:53.683945 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4127 00:56:53.687150 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4128 00:56:53.687575 == TX Byte 1 ==
4129 00:56:53.693073 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4130 00:56:53.696244 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4131 00:56:53.696774 ==
4132 00:56:53.699473 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 00:56:53.703120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4134 00:56:53.703642 ==
4135 00:56:53.703980
4136 00:56:53.704284
4137 00:56:53.705970 TX Vref Scan disable
4138 00:56:53.710257 == TX Byte 0 ==
4139 00:56:53.713174 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4140 00:56:53.719602 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4141 00:56:53.720104 == TX Byte 1 ==
4142 00:56:53.722613 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4143 00:56:53.729600 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4144 00:56:53.730078
4145 00:56:53.730414 [DATLAT]
4146 00:56:53.730725 Freq=600, CH0 RK1
4147 00:56:53.731061
4148 00:56:53.733224 DATLAT Default: 0x8
4149 00:56:53.733642 0, 0xFFFF, sum = 0
4150 00:56:53.735908 1, 0xFFFF, sum = 0
4151 00:56:53.739149 2, 0xFFFF, sum = 0
4152 00:56:53.739662 3, 0xFFFF, sum = 0
4153 00:56:53.742457 4, 0xFFFF, sum = 0
4154 00:56:53.742884 5, 0xFFFF, sum = 0
4155 00:56:53.745815 6, 0xFFFF, sum = 0
4156 00:56:53.746238 7, 0x0, sum = 1
4157 00:56:53.746577 8, 0x0, sum = 2
4158 00:56:53.749105 9, 0x0, sum = 3
4159 00:56:53.749529 10, 0x0, sum = 4
4160 00:56:53.752637 best_step = 8
4161 00:56:53.753124
4162 00:56:53.753461 ==
4163 00:56:53.755734 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 00:56:53.759381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4165 00:56:53.759803 ==
4166 00:56:53.762426 RX Vref Scan: 0
4167 00:56:53.762899
4168 00:56:53.763240 RX Vref 0 -> 0, step: 1
4169 00:56:53.763554
4170 00:56:53.765950 RX Delay -195 -> 252, step: 8
4171 00:56:53.773280 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4172 00:56:53.776373 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4173 00:56:53.780079 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4174 00:56:53.782840 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4175 00:56:53.789784 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4176 00:56:53.792992 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4177 00:56:53.796305 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4178 00:56:53.799598 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4179 00:56:53.802764 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4180 00:56:53.809347 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4181 00:56:53.813200 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4182 00:56:53.815903 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4183 00:56:53.822858 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4184 00:56:53.825697 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4185 00:56:53.829402 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4186 00:56:53.832275 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4187 00:56:53.832694 ==
4188 00:56:53.836632 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 00:56:53.843014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4190 00:56:53.843587 ==
4191 00:56:53.843999 DQS Delay:
4192 00:56:53.845754 DQS0 = 0, DQS1 = 0
4193 00:56:53.846170 DQM Delay:
4194 00:56:53.846622 DQM0 = 41, DQM1 = 32
4195 00:56:53.848988 DQ Delay:
4196 00:56:53.852550 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4197 00:56:53.856091 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4198 00:56:53.859031 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4199 00:56:53.862675 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4200 00:56:53.863332
4201 00:56:53.863678
4202 00:56:53.869124 [DQSOSCAuto] RK1, (LSB)MR18= 0x6868, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4203 00:56:53.872250 CH0 RK1: MR19=808, MR18=6868
4204 00:56:53.879081 CH0_RK1: MR19=0x808, MR18=0x6868, DQSOSC=390, MR23=63, INC=172, DEC=114
4205 00:56:53.882456 [RxdqsGatingPostProcess] freq 600
4206 00:56:53.885840 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4207 00:56:53.889294 Pre-setting of DQS Precalculation
4208 00:56:53.895844 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4209 00:56:53.896373 ==
4210 00:56:53.898364 Dram Type= 6, Freq= 0, CH_1, rank 0
4211 00:56:53.902433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4212 00:56:53.902963 ==
4213 00:56:53.909064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4214 00:56:53.915308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4215 00:56:53.919350 [CA 0] Center 35 (5~66) winsize 62
4216 00:56:53.922092 [CA 1] Center 35 (5~66) winsize 62
4217 00:56:53.924895 [CA 2] Center 33 (3~64) winsize 62
4218 00:56:53.928260 [CA 3] Center 33 (3~64) winsize 62
4219 00:56:53.932367 [CA 4] Center 33 (2~64) winsize 63
4220 00:56:53.935072 [CA 5] Center 33 (2~64) winsize 63
4221 00:56:53.935498
4222 00:56:53.938718 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4223 00:56:53.939232
4224 00:56:53.941957 [CATrainingPosCal] consider 1 rank data
4225 00:56:53.944946 u2DelayCellTimex100 = 270/100 ps
4226 00:56:53.948356 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4227 00:56:53.951990 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4228 00:56:53.955062 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4229 00:56:53.958096 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4230 00:56:53.961967 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4231 00:56:53.965358 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4232 00:56:53.965908
4233 00:56:53.971835 CA PerBit enable=1, Macro0, CA PI delay=33
4234 00:56:53.972393
4235 00:56:53.972795 [CBTSetCACLKResult] CA Dly = 33
4236 00:56:53.975229 CS Dly: 4 (0~35)
4237 00:56:53.975794 ==
4238 00:56:53.978343 Dram Type= 6, Freq= 0, CH_1, rank 1
4239 00:56:53.981628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4240 00:56:53.982185 ==
4241 00:56:53.988672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4242 00:56:53.994945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4243 00:56:53.998001 [CA 0] Center 35 (5~66) winsize 62
4244 00:56:54.001484 [CA 1] Center 34 (4~65) winsize 62
4245 00:56:54.004643 [CA 2] Center 33 (3~64) winsize 62
4246 00:56:54.008780 [CA 3] Center 33 (3~64) winsize 62
4247 00:56:54.011217 [CA 4] Center 32 (2~63) winsize 62
4248 00:56:54.014676 [CA 5] Center 32 (2~63) winsize 62
4249 00:56:54.015231
4250 00:56:54.017985 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4251 00:56:54.018447
4252 00:56:54.020968 [CATrainingPosCal] consider 2 rank data
4253 00:56:54.024540 u2DelayCellTimex100 = 270/100 ps
4254 00:56:54.027799 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4255 00:56:54.031458 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4256 00:56:54.035023 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4257 00:56:54.037891 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4258 00:56:54.040939 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4259 00:56:54.044613 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4260 00:56:54.048360
4261 00:56:54.051121 CA PerBit enable=1, Macro0, CA PI delay=32
4262 00:56:54.051667
4263 00:56:54.055144 [CBTSetCACLKResult] CA Dly = 32
4264 00:56:54.055605 CS Dly: 4 (0~36)
4265 00:56:54.055966
4266 00:56:54.057541 ----->DramcWriteLeveling(PI) begin...
4267 00:56:54.057974 ==
4268 00:56:54.061632 Dram Type= 6, Freq= 0, CH_1, rank 0
4269 00:56:54.064996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4270 00:56:54.067359 ==
4271 00:56:54.067838 Write leveling (Byte 0): 28 => 28
4272 00:56:54.070950 Write leveling (Byte 1): 28 => 28
4273 00:56:54.074275 DramcWriteLeveling(PI) end<-----
4274 00:56:54.074789
4275 00:56:54.075121 ==
4276 00:56:54.077715 Dram Type= 6, Freq= 0, CH_1, rank 0
4277 00:56:54.084359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4278 00:56:54.084901 ==
4279 00:56:54.087821 [Gating] SW mode calibration
4280 00:56:54.093729 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4281 00:56:54.097932 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4282 00:56:54.103783 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4283 00:56:54.107176 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
4284 00:56:54.110453 0 5 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
4285 00:56:54.117355 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4286 00:56:54.121345 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 00:56:54.123937 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 00:56:54.131118 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 00:56:54.133348 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 00:56:54.137187 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 00:56:54.144211 0 6 4 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
4292 00:56:54.146674 0 6 8 | B1->B0 | 3c3c 3e3e | 0 1 | (0 0) (0 0)
4293 00:56:54.150126 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 00:56:54.156873 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 00:56:54.160494 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 00:56:54.163509 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 00:56:54.167127 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 00:56:54.173442 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 00:56:54.177144 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 00:56:54.180616 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 00:56:54.186665 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 00:56:54.190596 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 00:56:54.193762 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 00:56:54.200746 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 00:56:54.203675 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 00:56:54.206878 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 00:56:54.212944 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 00:56:54.216884 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 00:56:54.220594 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 00:56:54.226753 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 00:56:54.229497 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 00:56:54.233366 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 00:56:54.239501 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 00:56:54.242661 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 00:56:54.246355 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4316 00:56:54.250055 Total UI for P1: 0, mck2ui 16
4317 00:56:54.252768 best dqsien dly found for B0: ( 0, 9, 2)
4318 00:56:54.259438 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 00:56:54.259997 Total UI for P1: 0, mck2ui 16
4320 00:56:54.266101 best dqsien dly found for B1: ( 0, 9, 4)
4321 00:56:54.269264 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4322 00:56:54.272367 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4323 00:56:54.272867
4324 00:56:54.275779 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4325 00:56:54.279571 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4326 00:56:54.282572 [Gating] SW calibration Done
4327 00:56:54.283137 ==
4328 00:56:54.285720 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 00:56:54.289079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4330 00:56:54.289633 ==
4331 00:56:54.292512 RX Vref Scan: 0
4332 00:56:54.293351
4333 00:56:54.293746 RX Vref 0 -> 0, step: 1
4334 00:56:54.294089
4335 00:56:54.295644 RX Delay -230 -> 252, step: 16
4336 00:56:54.303249 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4337 00:56:54.305582 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4338 00:56:54.309018 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4339 00:56:54.312167 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4340 00:56:54.315606 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4341 00:56:54.322058 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4342 00:56:54.326015 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4343 00:56:54.329041 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4344 00:56:54.331980 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4345 00:56:54.339996 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4346 00:56:54.342158 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4347 00:56:54.345506 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4348 00:56:54.348971 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4349 00:56:54.355148 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4350 00:56:54.358482 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4351 00:56:54.362232 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4352 00:56:54.362787 ==
4353 00:56:54.365348 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 00:56:54.368884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4355 00:56:54.371799 ==
4356 00:56:54.372348 DQS Delay:
4357 00:56:54.372749 DQS0 = 0, DQS1 = 0
4358 00:56:54.375058 DQM Delay:
4359 00:56:54.375509 DQM0 = 43, DQM1 = 33
4360 00:56:54.378783 DQ Delay:
4361 00:56:54.379232 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4362 00:56:54.382086 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4363 00:56:54.384779 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4364 00:56:54.388426 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4365 00:56:54.388920
4366 00:56:54.391362
4367 00:56:54.391833 ==
4368 00:56:54.395863 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 00:56:54.398094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 00:56:54.398548 ==
4371 00:56:54.398906
4372 00:56:54.399234
4373 00:56:54.401602 TX Vref Scan disable
4374 00:56:54.402055 == TX Byte 0 ==
4375 00:56:54.408732 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4376 00:56:54.412222 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4377 00:56:54.412762 == TX Byte 1 ==
4378 00:56:54.417898 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4379 00:56:54.421891 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4380 00:56:54.422354 ==
4381 00:56:54.424864 Dram Type= 6, Freq= 0, CH_1, rank 0
4382 00:56:54.428599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4383 00:56:54.429161 ==
4384 00:56:54.429491
4385 00:56:54.429794
4386 00:56:54.431509 TX Vref Scan disable
4387 00:56:54.434280 == TX Byte 0 ==
4388 00:56:54.437820 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4389 00:56:54.442113 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4390 00:56:54.444848 == TX Byte 1 ==
4391 00:56:54.447420 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4392 00:56:54.454102 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4393 00:56:54.454667
4394 00:56:54.455011 [DATLAT]
4395 00:56:54.455309 Freq=600, CH1 RK0
4396 00:56:54.455600
4397 00:56:54.457660 DATLAT Default: 0x9
4398 00:56:54.458161 0, 0xFFFF, sum = 0
4399 00:56:54.460749 1, 0xFFFF, sum = 0
4400 00:56:54.461262 2, 0xFFFF, sum = 0
4401 00:56:54.465040 3, 0xFFFF, sum = 0
4402 00:56:54.467336 4, 0xFFFF, sum = 0
4403 00:56:54.467854 5, 0xFFFF, sum = 0
4404 00:56:54.470667 6, 0xFFFF, sum = 0
4405 00:56:54.471172 7, 0x0, sum = 1
4406 00:56:54.471506 8, 0x0, sum = 2
4407 00:56:54.474324 9, 0x0, sum = 3
4408 00:56:54.474829 10, 0x0, sum = 4
4409 00:56:54.477765 best_step = 8
4410 00:56:54.478261
4411 00:56:54.478585 ==
4412 00:56:54.480802 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 00:56:54.484486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4414 00:56:54.485228 ==
4415 00:56:54.487185 RX Vref Scan: 1
4416 00:56:54.487684
4417 00:56:54.488012 RX Vref 0 -> 0, step: 1
4418 00:56:54.488318
4419 00:56:54.490756 RX Delay -195 -> 252, step: 8
4420 00:56:54.491253
4421 00:56:54.493862 Set Vref, RX VrefLevel [Byte0]: 52
4422 00:56:54.497121 [Byte1]: 49
4423 00:56:54.501028
4424 00:56:54.501438 Final RX Vref Byte 0 = 52 to rank0
4425 00:56:54.504866 Final RX Vref Byte 1 = 49 to rank0
4426 00:56:54.508148 Final RX Vref Byte 0 = 52 to rank1
4427 00:56:54.511231 Final RX Vref Byte 1 = 49 to rank1==
4428 00:56:54.514725 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 00:56:54.521246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4430 00:56:54.521797 ==
4431 00:56:54.522219 DQS Delay:
4432 00:56:54.525147 DQS0 = 0, DQS1 = 0
4433 00:56:54.525702 DQM Delay:
4434 00:56:54.526061 DQM0 = 37, DQM1 = 31
4435 00:56:54.527846 DQ Delay:
4436 00:56:54.531079 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4437 00:56:54.534234 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4438 00:56:54.537600 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4439 00:56:54.541400 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4440 00:56:54.541944
4441 00:56:54.542298
4442 00:56:54.547875 [DQSOSCAuto] RK0, (LSB)MR18= 0x7c7c, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4443 00:56:54.551137 CH1 RK0: MR19=808, MR18=7C7C
4444 00:56:54.557655 CH1_RK0: MR19=0x808, MR18=0x7C7C, DQSOSC=386, MR23=63, INC=176, DEC=117
4445 00:56:54.558116
4446 00:56:54.561133 ----->DramcWriteLeveling(PI) begin...
4447 00:56:54.561688 ==
4448 00:56:54.564087 Dram Type= 6, Freq= 0, CH_1, rank 1
4449 00:56:54.567615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4450 00:56:54.568169 ==
4451 00:56:54.570736 Write leveling (Byte 0): 29 => 29
4452 00:56:54.574329 Write leveling (Byte 1): 29 => 29
4453 00:56:54.577470 DramcWriteLeveling(PI) end<-----
4454 00:56:54.578012
4455 00:56:54.578374 ==
4456 00:56:54.580831 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 00:56:54.584416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4458 00:56:54.587323 ==
4459 00:56:54.587867 [Gating] SW mode calibration
4460 00:56:54.594552 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 00:56:54.600493 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4462 00:56:54.604452 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 00:56:54.610625 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
4464 00:56:54.613874 0 5 8 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
4465 00:56:54.616999 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 00:56:54.624107 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 00:56:54.627302 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 00:56:54.630411 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 00:56:54.637018 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 00:56:54.640406 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 00:56:54.643916 0 6 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
4472 00:56:54.650389 0 6 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4473 00:56:54.653132 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 00:56:54.656918 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 00:56:54.663500 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 00:56:54.667084 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 00:56:54.671010 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 00:56:54.676615 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 00:56:54.679852 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 00:56:54.683965 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4481 00:56:54.689996 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 00:56:54.693635 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 00:56:54.696446 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 00:56:54.702876 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 00:56:54.706619 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 00:56:54.709895 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 00:56:54.716037 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 00:56:54.719983 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 00:56:54.723854 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 00:56:54.726348 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 00:56:54.733398 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 00:56:54.736791 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 00:56:54.739538 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 00:56:54.746680 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 00:56:54.749988 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4496 00:56:54.752872 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 00:56:54.756386 Total UI for P1: 0, mck2ui 16
4498 00:56:54.759826 best dqsien dly found for B0: ( 0, 9, 4)
4499 00:56:54.763468 Total UI for P1: 0, mck2ui 16
4500 00:56:54.766492 best dqsien dly found for B1: ( 0, 9, 4)
4501 00:56:54.769881 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4502 00:56:54.773034 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4503 00:56:54.773580
4504 00:56:54.780203 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4505 00:56:54.783219 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4506 00:56:54.783775 [Gating] SW calibration Done
4507 00:56:54.786325 ==
4508 00:56:54.789666 Dram Type= 6, Freq= 0, CH_1, rank 1
4509 00:56:54.792870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4510 00:56:54.793425 ==
4511 00:56:54.793792 RX Vref Scan: 0
4512 00:56:54.794129
4513 00:56:54.795757 RX Vref 0 -> 0, step: 1
4514 00:56:54.796410
4515 00:56:54.799559 RX Delay -230 -> 252, step: 16
4516 00:56:54.804333 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4517 00:56:54.806459 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4518 00:56:54.812561 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4519 00:56:54.816471 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4520 00:56:54.819555 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4521 00:56:54.822601 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4522 00:56:54.829269 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4523 00:56:54.832236 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4524 00:56:54.835781 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4525 00:56:54.839347 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4526 00:56:54.846200 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4527 00:56:54.849545 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4528 00:56:54.852783 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4529 00:56:54.855772 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4530 00:56:54.862342 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4531 00:56:54.865316 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4532 00:56:54.865867 ==
4533 00:56:54.869274 Dram Type= 6, Freq= 0, CH_1, rank 1
4534 00:56:54.871943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4535 00:56:54.872498 ==
4536 00:56:54.875787 DQS Delay:
4537 00:56:54.876339 DQS0 = 0, DQS1 = 0
4538 00:56:54.876703 DQM Delay:
4539 00:56:54.879202 DQM0 = 39, DQM1 = 35
4540 00:56:54.879757 DQ Delay:
4541 00:56:54.883092 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4542 00:56:54.885427 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4543 00:56:54.888589 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4544 00:56:54.891805 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4545 00:56:54.892353
4546 00:56:54.892752
4547 00:56:54.893106 ==
4548 00:56:54.895559 Dram Type= 6, Freq= 0, CH_1, rank 1
4549 00:56:54.902511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4550 00:56:54.903062 ==
4551 00:56:54.903422
4552 00:56:54.903751
4553 00:56:54.904067 TX Vref Scan disable
4554 00:56:54.905103 == TX Byte 0 ==
4555 00:56:54.909484 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4556 00:56:54.911910 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4557 00:56:54.916282 == TX Byte 1 ==
4558 00:56:54.918743 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 00:56:54.925424 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 00:56:54.925994 ==
4561 00:56:54.928310 Dram Type= 6, Freq= 0, CH_1, rank 1
4562 00:56:54.931949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4563 00:56:54.932515 ==
4564 00:56:54.933105
4565 00:56:54.933559
4566 00:56:54.934826 TX Vref Scan disable
4567 00:56:54.938219 == TX Byte 0 ==
4568 00:56:54.942156 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 00:56:54.944856 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 00:56:54.948094 == TX Byte 1 ==
4571 00:56:54.952007 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4572 00:56:54.955205 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4573 00:56:54.955792
4574 00:56:54.956295 [DATLAT]
4575 00:56:54.958142 Freq=600, CH1 RK1
4576 00:56:54.958612
4577 00:56:54.961545 DATLAT Default: 0x8
4578 00:56:54.962116 0, 0xFFFF, sum = 0
4579 00:56:54.965650 1, 0xFFFF, sum = 0
4580 00:56:54.966224 2, 0xFFFF, sum = 0
4581 00:56:54.967810 3, 0xFFFF, sum = 0
4582 00:56:54.968283 4, 0xFFFF, sum = 0
4583 00:56:54.972256 5, 0xFFFF, sum = 0
4584 00:56:54.972881 6, 0xFFFF, sum = 0
4585 00:56:54.974351 7, 0x0, sum = 1
4586 00:56:54.974822 8, 0x0, sum = 2
4587 00:56:54.975303 9, 0x0, sum = 3
4588 00:56:54.978182 10, 0x0, sum = 4
4589 00:56:54.978759 best_step = 8
4590 00:56:54.979245
4591 00:56:54.981225 ==
4592 00:56:54.981692 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 00:56:54.988344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4594 00:56:54.988965 ==
4595 00:56:54.989511 RX Vref Scan: 0
4596 00:56:54.989962
4597 00:56:54.990989 RX Vref 0 -> 0, step: 1
4598 00:56:54.991543
4599 00:56:54.994866 RX Delay -195 -> 252, step: 8
4600 00:56:54.997675 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4601 00:56:55.004800 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4602 00:56:55.008172 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4603 00:56:55.011328 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4604 00:56:55.014598 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4605 00:56:55.021386 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4606 00:56:55.024573 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4607 00:56:55.027695 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4608 00:56:55.031269 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4609 00:56:55.037700 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4610 00:56:55.040902 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4611 00:56:55.044354 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4612 00:56:55.046988 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4613 00:56:55.053958 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4614 00:56:55.057112 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4615 00:56:55.060312 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4616 00:56:55.060894 ==
4617 00:56:55.064184 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 00:56:55.067714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4619 00:56:55.070472 ==
4620 00:56:55.070927 DQS Delay:
4621 00:56:55.071289 DQS0 = 0, DQS1 = 0
4622 00:56:55.073965 DQM Delay:
4623 00:56:55.074517 DQM0 = 37, DQM1 = 29
4624 00:56:55.076834 DQ Delay:
4625 00:56:55.077385 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4626 00:56:55.080756 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4627 00:56:55.084057 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4628 00:56:55.087103 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4629 00:56:55.090551
4630 00:56:55.091120
4631 00:56:55.097040 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4632 00:56:55.100578 CH1 RK1: MR19=808, MR18=6262
4633 00:56:55.106528 CH1_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4634 00:56:55.109708 [RxdqsGatingPostProcess] freq 600
4635 00:56:55.113193 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4636 00:56:55.116885 Pre-setting of DQS Precalculation
4637 00:56:55.123581 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4638 00:56:55.129887 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4639 00:56:55.137062 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4640 00:56:55.137621
4641 00:56:55.137985
4642 00:56:55.140784 [Calibration Summary] 1200 Mbps
4643 00:56:55.141333 CH 0, Rank 0
4644 00:56:55.143459 SW Impedance : PASS
4645 00:56:55.146585 DUTY Scan : NO K
4646 00:56:55.147041 ZQ Calibration : PASS
4647 00:56:55.150190 Jitter Meter : NO K
4648 00:56:55.152963 CBT Training : PASS
4649 00:56:55.153514 Write leveling : PASS
4650 00:56:55.156333 RX DQS gating : PASS
4651 00:56:55.159369 RX DQ/DQS(RDDQC) : PASS
4652 00:56:55.159823 TX DQ/DQS : PASS
4653 00:56:55.163184 RX DATLAT : PASS
4654 00:56:55.163728 RX DQ/DQS(Engine): PASS
4655 00:56:55.166796 TX OE : NO K
4656 00:56:55.167345 All Pass.
4657 00:56:55.167709
4658 00:56:55.169346 CH 0, Rank 1
4659 00:56:55.169805 SW Impedance : PASS
4660 00:56:55.173361 DUTY Scan : NO K
4661 00:56:55.175807 ZQ Calibration : PASS
4662 00:56:55.176351 Jitter Meter : NO K
4663 00:56:55.180000 CBT Training : PASS
4664 00:56:55.183030 Write leveling : PASS
4665 00:56:55.183579 RX DQS gating : PASS
4666 00:56:55.186077 RX DQ/DQS(RDDQC) : PASS
4667 00:56:55.189118 TX DQ/DQS : PASS
4668 00:56:55.189576 RX DATLAT : PASS
4669 00:56:55.192366 RX DQ/DQS(Engine): PASS
4670 00:56:55.196049 TX OE : NO K
4671 00:56:55.196598 All Pass.
4672 00:56:55.197030
4673 00:56:55.197374 CH 1, Rank 0
4674 00:56:55.199483 SW Impedance : PASS
4675 00:56:55.202615 DUTY Scan : NO K
4676 00:56:55.203169 ZQ Calibration : PASS
4677 00:56:55.206102 Jitter Meter : NO K
4678 00:56:55.209580 CBT Training : PASS
4679 00:56:55.210034 Write leveling : PASS
4680 00:56:55.212223 RX DQS gating : PASS
4681 00:56:55.215785 RX DQ/DQS(RDDQC) : PASS
4682 00:56:55.216341 TX DQ/DQS : PASS
4683 00:56:55.218986 RX DATLAT : PASS
4684 00:56:55.222899 RX DQ/DQS(Engine): PASS
4685 00:56:55.223452 TX OE : NO K
4686 00:56:55.223817 All Pass.
4687 00:56:55.224153
4688 00:56:55.225524 CH 1, Rank 1
4689 00:56:55.228773 SW Impedance : PASS
4690 00:56:55.229230 DUTY Scan : NO K
4691 00:56:55.232101 ZQ Calibration : PASS
4692 00:56:55.232649 Jitter Meter : NO K
4693 00:56:55.235824 CBT Training : PASS
4694 00:56:55.238980 Write leveling : PASS
4695 00:56:55.239605 RX DQS gating : PASS
4696 00:56:55.242141 RX DQ/DQS(RDDQC) : PASS
4697 00:56:55.245519 TX DQ/DQS : PASS
4698 00:56:55.245977 RX DATLAT : PASS
4699 00:56:55.249305 RX DQ/DQS(Engine): PASS
4700 00:56:55.252422 TX OE : NO K
4701 00:56:55.253056 All Pass.
4702 00:56:55.253426
4703 00:56:55.255588 DramC Write-DBI off
4704 00:56:55.256042 PER_BANK_REFRESH: Hybrid Mode
4705 00:56:55.258871 TX_TRACKING: ON
4706 00:56:55.265981 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4707 00:56:55.272459 [FAST_K] Save calibration result to emmc
4708 00:56:55.275317 dramc_set_vcore_voltage set vcore to 662500
4709 00:56:55.275863 Read voltage for 933, 3
4710 00:56:55.278740 Vio18 = 0
4711 00:56:55.279312 Vcore = 662500
4712 00:56:55.279680 Vdram = 0
4713 00:56:55.282140 Vddq = 0
4714 00:56:55.282690 Vmddr = 0
4715 00:56:55.285325 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4716 00:56:55.291995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4717 00:56:55.294937 MEM_TYPE=3, freq_sel=17
4718 00:56:55.298152 sv_algorithm_assistance_LP4_1600
4719 00:56:55.302167 ============ PULL DRAM RESETB DOWN ============
4720 00:56:55.305186 ========== PULL DRAM RESETB DOWN end =========
4721 00:56:55.311580 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4722 00:56:55.315771 ===================================
4723 00:56:55.316326 LPDDR4 DRAM CONFIGURATION
4724 00:56:55.318428 ===================================
4725 00:56:55.321381 EX_ROW_EN[0] = 0x0
4726 00:56:55.321935 EX_ROW_EN[1] = 0x0
4727 00:56:55.325186 LP4Y_EN = 0x0
4728 00:56:55.328690 WORK_FSP = 0x0
4729 00:56:55.329309 WL = 0x3
4730 00:56:55.331715 RL = 0x3
4731 00:56:55.332275 BL = 0x2
4732 00:56:55.334748 RPST = 0x0
4733 00:56:55.335297 RD_PRE = 0x0
4734 00:56:55.338511 WR_PRE = 0x1
4735 00:56:55.338969 WR_PST = 0x0
4736 00:56:55.341409 DBI_WR = 0x0
4737 00:56:55.341960 DBI_RD = 0x0
4738 00:56:55.344647 OTF = 0x1
4739 00:56:55.347548 ===================================
4740 00:56:55.351673 ===================================
4741 00:56:55.352224 ANA top config
4742 00:56:55.354361 ===================================
4743 00:56:55.357843 DLL_ASYNC_EN = 0
4744 00:56:55.361133 ALL_SLAVE_EN = 1
4745 00:56:55.364389 NEW_RANK_MODE = 1
4746 00:56:55.364871 DLL_IDLE_MODE = 1
4747 00:56:55.367797 LP45_APHY_COMB_EN = 1
4748 00:56:55.371363 TX_ODT_DIS = 1
4749 00:56:55.374380 NEW_8X_MODE = 1
4750 00:56:55.377826 ===================================
4751 00:56:55.381393 ===================================
4752 00:56:55.384200 data_rate = 1866
4753 00:56:55.384792 CKR = 1
4754 00:56:55.387544 DQ_P2S_RATIO = 8
4755 00:56:55.391238 ===================================
4756 00:56:55.394407 CA_P2S_RATIO = 8
4757 00:56:55.398130 DQ_CA_OPEN = 0
4758 00:56:55.400377 DQ_SEMI_OPEN = 0
4759 00:56:55.404022 CA_SEMI_OPEN = 0
4760 00:56:55.404576 CA_FULL_RATE = 0
4761 00:56:55.407258 DQ_CKDIV4_EN = 1
4762 00:56:55.410972 CA_CKDIV4_EN = 1
4763 00:56:55.414068 CA_PREDIV_EN = 0
4764 00:56:55.417305 PH8_DLY = 0
4765 00:56:55.420865 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4766 00:56:55.421412 DQ_AAMCK_DIV = 4
4767 00:56:55.424302 CA_AAMCK_DIV = 4
4768 00:56:55.427502 CA_ADMCK_DIV = 4
4769 00:56:55.430407 DQ_TRACK_CA_EN = 0
4770 00:56:55.434047 CA_PICK = 933
4771 00:56:55.437026 CA_MCKIO = 933
4772 00:56:55.437589 MCKIO_SEMI = 0
4773 00:56:55.440464 PLL_FREQ = 3732
4774 00:56:55.444864 DQ_UI_PI_RATIO = 32
4775 00:56:55.447157 CA_UI_PI_RATIO = 0
4776 00:56:55.450936 ===================================
4777 00:56:55.453913 ===================================
4778 00:56:55.457592 memory_type:LPDDR4
4779 00:56:55.458150 GP_NUM : 10
4780 00:56:55.460085 SRAM_EN : 1
4781 00:56:55.463633 MD32_EN : 0
4782 00:56:55.467070 ===================================
4783 00:56:55.467632 [ANA_INIT] >>>>>>>>>>>>>>
4784 00:56:55.470448 <<<<<< [CONFIGURE PHASE]: ANA_TX
4785 00:56:55.473811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4786 00:56:55.476770 ===================================
4787 00:56:55.480489 data_rate = 1866,PCW = 0X8f00
4788 00:56:55.483702 ===================================
4789 00:56:55.487123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4790 00:56:55.493378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4791 00:56:55.497240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4792 00:56:55.503720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4793 00:56:55.507104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4794 00:56:55.510341 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4795 00:56:55.510799 [ANA_INIT] flow start
4796 00:56:55.512993 [ANA_INIT] PLL >>>>>>>>
4797 00:56:55.516370 [ANA_INIT] PLL <<<<<<<<
4798 00:56:55.520068 [ANA_INIT] MIDPI >>>>>>>>
4799 00:56:55.520620 [ANA_INIT] MIDPI <<<<<<<<
4800 00:56:55.523484 [ANA_INIT] DLL >>>>>>>>
4801 00:56:55.526830 [ANA_INIT] flow end
4802 00:56:55.530076 ============ LP4 DIFF to SE enter ============
4803 00:56:55.533188 ============ LP4 DIFF to SE exit ============
4804 00:56:55.536662 [ANA_INIT] <<<<<<<<<<<<<
4805 00:56:55.539499 [Flow] Enable top DCM control >>>>>
4806 00:56:55.543421 [Flow] Enable top DCM control <<<<<
4807 00:56:55.546676 Enable DLL master slave shuffle
4808 00:56:55.549381 ==============================================================
4809 00:56:55.553563 Gating Mode config
4810 00:56:55.559406 ==============================================================
4811 00:56:55.559866 Config description:
4812 00:56:55.569566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4813 00:56:55.576240 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4814 00:56:55.579950 SELPH_MODE 0: By rank 1: By Phase
4815 00:56:55.586074 ==============================================================
4816 00:56:55.589284 GAT_TRACK_EN = 1
4817 00:56:55.592611 RX_GATING_MODE = 2
4818 00:56:55.596176 RX_GATING_TRACK_MODE = 2
4819 00:56:55.599684 SELPH_MODE = 1
4820 00:56:55.602507 PICG_EARLY_EN = 1
4821 00:56:55.605882 VALID_LAT_VALUE = 1
4822 00:56:55.609350 ==============================================================
4823 00:56:55.612312 Enter into Gating configuration >>>>
4824 00:56:55.616052 Exit from Gating configuration <<<<
4825 00:56:55.619815 Enter into DVFS_PRE_config >>>>>
4826 00:56:55.632431 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4827 00:56:55.633035 Exit from DVFS_PRE_config <<<<<
4828 00:56:55.636016 Enter into PICG configuration >>>>
4829 00:56:55.639036 Exit from PICG configuration <<<<
4830 00:56:55.642925 [RX_INPUT] configuration >>>>>
4831 00:56:55.646152 [RX_INPUT] configuration <<<<<
4832 00:56:55.652388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4833 00:56:55.656482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4834 00:56:55.662624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4835 00:56:55.669361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4836 00:56:55.675647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4837 00:56:55.682642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4838 00:56:55.686432 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4839 00:56:55.689531 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4840 00:56:55.692267 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4841 00:56:55.699237 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4842 00:56:55.702113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4843 00:56:55.705436 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4844 00:56:55.708908 ===================================
4845 00:56:55.711717 LPDDR4 DRAM CONFIGURATION
4846 00:56:55.715584 ===================================
4847 00:56:55.719231 EX_ROW_EN[0] = 0x0
4848 00:56:55.719782 EX_ROW_EN[1] = 0x0
4849 00:56:55.721613 LP4Y_EN = 0x0
4850 00:56:55.722170 WORK_FSP = 0x0
4851 00:56:55.725044 WL = 0x3
4852 00:56:55.725499 RL = 0x3
4853 00:56:55.729377 BL = 0x2
4854 00:56:55.729927 RPST = 0x0
4855 00:56:55.732041 RD_PRE = 0x0
4856 00:56:55.732584 WR_PRE = 0x1
4857 00:56:55.735593 WR_PST = 0x0
4858 00:56:55.736147 DBI_WR = 0x0
4859 00:56:55.738444 DBI_RD = 0x0
4860 00:56:55.738893 OTF = 0x1
4861 00:56:55.742092 ===================================
4862 00:56:55.745569 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4863 00:56:55.751828 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4864 00:56:55.755957 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 00:56:55.758448 ===================================
4866 00:56:55.762071 LPDDR4 DRAM CONFIGURATION
4867 00:56:55.765661 ===================================
4868 00:56:55.766215 EX_ROW_EN[0] = 0x10
4869 00:56:55.768842 EX_ROW_EN[1] = 0x0
4870 00:56:55.772194 LP4Y_EN = 0x0
4871 00:56:55.772801 WORK_FSP = 0x0
4872 00:56:55.775264 WL = 0x3
4873 00:56:55.775817 RL = 0x3
4874 00:56:55.778582 BL = 0x2
4875 00:56:55.779028 RPST = 0x0
4876 00:56:55.782644 RD_PRE = 0x0
4877 00:56:55.783265 WR_PRE = 0x1
4878 00:56:55.784981 WR_PST = 0x0
4879 00:56:55.785433 DBI_WR = 0x0
4880 00:56:55.788330 DBI_RD = 0x0
4881 00:56:55.788846 OTF = 0x1
4882 00:56:55.791930 ===================================
4883 00:56:55.798235 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4884 00:56:55.802799 nWR fixed to 30
4885 00:56:55.806492 [ModeRegInit_LP4] CH0 RK0
4886 00:56:55.807078 [ModeRegInit_LP4] CH0 RK1
4887 00:56:55.809289 [ModeRegInit_LP4] CH1 RK0
4888 00:56:55.813046 [ModeRegInit_LP4] CH1 RK1
4889 00:56:55.813501 match AC timing 8
4890 00:56:55.819047 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4891 00:56:55.822822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4892 00:56:55.825634 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4893 00:56:55.832296 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4894 00:56:55.835854 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4895 00:56:55.836309 ==
4896 00:56:55.838905 Dram Type= 6, Freq= 0, CH_0, rank 0
4897 00:56:55.841854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4898 00:56:55.842342 ==
4899 00:56:55.848413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4900 00:56:55.856124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4901 00:56:55.858696 [CA 0] Center 38 (8~69) winsize 62
4902 00:56:55.862323 [CA 1] Center 38 (8~69) winsize 62
4903 00:56:55.865909 [CA 2] Center 36 (6~67) winsize 62
4904 00:56:55.869538 [CA 3] Center 35 (5~66) winsize 62
4905 00:56:55.871842 [CA 4] Center 34 (4~65) winsize 62
4906 00:56:55.875716 [CA 5] Center 34 (4~65) winsize 62
4907 00:56:55.876275
4908 00:56:55.879367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4909 00:56:55.879922
4910 00:56:55.882286 [CATrainingPosCal] consider 1 rank data
4911 00:56:55.885158 u2DelayCellTimex100 = 270/100 ps
4912 00:56:55.889083 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4913 00:56:55.891724 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4914 00:56:55.895408 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4915 00:56:55.898783 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4916 00:56:55.902482 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4917 00:56:55.908880 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4918 00:56:55.909482
4919 00:56:55.913617 CA PerBit enable=1, Macro0, CA PI delay=34
4920 00:56:55.914169
4921 00:56:55.914954 [CBTSetCACLKResult] CA Dly = 34
4922 00:56:55.915334 CS Dly: 7 (0~38)
4923 00:56:55.915699 ==
4924 00:56:55.918769 Dram Type= 6, Freq= 0, CH_0, rank 1
4925 00:56:55.922145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4926 00:56:55.925160 ==
4927 00:56:55.928796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4928 00:56:55.935079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4929 00:56:55.938259 [CA 0] Center 38 (8~69) winsize 62
4930 00:56:55.942146 [CA 1] Center 38 (7~69) winsize 63
4931 00:56:55.944850 [CA 2] Center 36 (6~67) winsize 62
4932 00:56:55.948506 [CA 3] Center 35 (5~66) winsize 62
4933 00:56:55.951869 [CA 4] Center 34 (4~65) winsize 62
4934 00:56:55.955467 [CA 5] Center 34 (4~65) winsize 62
4935 00:56:55.956020
4936 00:56:55.957811 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4937 00:56:55.958479
4938 00:56:55.961482 [CATrainingPosCal] consider 2 rank data
4939 00:56:55.965094 u2DelayCellTimex100 = 270/100 ps
4940 00:56:55.968449 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4941 00:56:55.971543 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4942 00:56:55.975038 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4943 00:56:55.981308 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4944 00:56:55.987245 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4945 00:56:55.988172 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4946 00:56:55.988557
4947 00:56:55.991390 CA PerBit enable=1, Macro0, CA PI delay=34
4948 00:56:55.991940
4949 00:56:55.994291 [CBTSetCACLKResult] CA Dly = 34
4950 00:56:55.994742 CS Dly: 7 (0~39)
4951 00:56:55.995102
4952 00:56:55.997975 ----->DramcWriteLeveling(PI) begin...
4953 00:56:55.998538 ==
4954 00:56:56.001630 Dram Type= 6, Freq= 0, CH_0, rank 0
4955 00:56:56.008110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4956 00:56:56.008670 ==
4957 00:56:56.011278 Write leveling (Byte 0): 28 => 28
4958 00:56:56.015050 Write leveling (Byte 1): 28 => 28
4959 00:56:56.017408 DramcWriteLeveling(PI) end<-----
4960 00:56:56.017858
4961 00:56:56.018215 ==
4962 00:56:56.021744 Dram Type= 6, Freq= 0, CH_0, rank 0
4963 00:56:56.024965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4964 00:56:56.025519 ==
4965 00:56:56.027274 [Gating] SW mode calibration
4966 00:56:56.034366 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4967 00:56:56.041207 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4968 00:56:56.044504 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 00:56:56.047421 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 00:56:56.054080 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4971 00:56:56.057030 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4972 00:56:56.060438 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4973 00:56:56.067459 0 10 20 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 1)
4974 00:56:56.070529 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4975 00:56:56.073742 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 00:56:56.076943 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 00:56:56.084312 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 00:56:56.086923 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4979 00:56:56.090551 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4980 00:56:56.096830 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4981 00:56:56.100301 0 11 20 | B1->B0 | 2525 3030 | 0 1 | (0 0) (1 1)
4982 00:56:56.103135 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4983 00:56:56.110183 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 00:56:56.113289 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 00:56:56.116579 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 00:56:56.123099 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4987 00:56:56.127138 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4988 00:56:56.130541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4989 00:56:56.136212 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4990 00:56:56.140092 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4991 00:56:56.143797 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 00:56:56.149780 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 00:56:56.153315 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 00:56:56.157046 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 00:56:56.162796 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 00:56:56.166441 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 00:56:56.169583 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 00:56:56.176157 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 00:56:56.180100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 00:56:56.182491 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 00:56:56.189130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 00:56:56.193274 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 00:56:56.196897 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 00:56:56.202242 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5005 00:56:56.206882 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5006 00:56:56.209032 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5007 00:56:56.216119 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5008 00:56:56.219260 Total UI for P1: 0, mck2ui 16
5009 00:56:56.222429 best dqsien dly found for B0: ( 0, 14, 20)
5010 00:56:56.222982 Total UI for P1: 0, mck2ui 16
5011 00:56:56.229394 best dqsien dly found for B1: ( 0, 14, 22)
5012 00:56:56.232555 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5013 00:56:56.235453 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5014 00:56:56.236008
5015 00:56:56.239700 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5016 00:56:56.242420 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5017 00:56:56.245499 [Gating] SW calibration Done
5018 00:56:56.246045 ==
5019 00:56:56.249689 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 00:56:56.252452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5021 00:56:56.253076 ==
5022 00:56:56.255159 RX Vref Scan: 0
5023 00:56:56.255709
5024 00:56:56.258670 RX Vref 0 -> 0, step: 1
5025 00:56:56.259339
5026 00:56:56.259708 RX Delay -80 -> 252, step: 8
5027 00:56:56.265206 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5028 00:56:56.268925 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5029 00:56:56.272659 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5030 00:56:56.275487 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5031 00:56:56.278810 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5032 00:56:56.281648 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5033 00:56:56.288871 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5034 00:56:56.292546 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5035 00:56:56.295107 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5036 00:56:56.298222 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5037 00:56:56.302030 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5038 00:56:56.308237 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5039 00:56:56.311959 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5040 00:56:56.314407 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5041 00:56:56.318788 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5042 00:56:56.321966 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5043 00:56:56.324463 ==
5044 00:56:56.324990 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 00:56:56.331333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5046 00:56:56.331881 ==
5047 00:56:56.332249 DQS Delay:
5048 00:56:56.334942 DQS0 = 0, DQS1 = 0
5049 00:56:56.335490 DQM Delay:
5050 00:56:56.338167 DQM0 = 95, DQM1 = 84
5051 00:56:56.338711 DQ Delay:
5052 00:56:56.341563 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5053 00:56:56.345054 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5054 00:56:56.347809 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5055 00:56:56.350983 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5056 00:56:56.351440
5057 00:56:56.351800
5058 00:56:56.352135 ==
5059 00:56:56.354930 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 00:56:56.357804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 00:56:56.358265 ==
5062 00:56:56.358625
5063 00:56:56.358957
5064 00:56:56.360820 TX Vref Scan disable
5065 00:56:56.364522 == TX Byte 0 ==
5066 00:56:56.367524 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5067 00:56:56.370801 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5068 00:56:56.374262 == TX Byte 1 ==
5069 00:56:56.377631 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5070 00:56:56.381246 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5071 00:56:56.381755 ==
5072 00:56:56.385027 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 00:56:56.391058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 00:56:56.391576 ==
5075 00:56:56.391913
5076 00:56:56.392218
5077 00:56:56.392510 TX Vref Scan disable
5078 00:56:56.394664 == TX Byte 0 ==
5079 00:56:56.398059 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5080 00:56:56.404751 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5081 00:56:56.405268 == TX Byte 1 ==
5082 00:56:56.408432 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5083 00:56:56.414951 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5084 00:56:56.415479
5085 00:56:56.415819 [DATLAT]
5086 00:56:56.416124 Freq=933, CH0 RK0
5087 00:56:56.416417
5088 00:56:56.418260 DATLAT Default: 0xd
5089 00:56:56.418765 0, 0xFFFF, sum = 0
5090 00:56:56.421660 1, 0xFFFF, sum = 0
5091 00:56:56.424585 2, 0xFFFF, sum = 0
5092 00:56:56.425085 3, 0xFFFF, sum = 0
5093 00:56:56.428275 4, 0xFFFF, sum = 0
5094 00:56:56.428860 5, 0xFFFF, sum = 0
5095 00:56:56.430982 6, 0xFFFF, sum = 0
5096 00:56:56.431504 7, 0xFFFF, sum = 0
5097 00:56:56.434959 8, 0xFFFF, sum = 0
5098 00:56:56.435472 9, 0xFFFF, sum = 0
5099 00:56:56.437944 10, 0x0, sum = 1
5100 00:56:56.438459 11, 0x0, sum = 2
5101 00:56:56.441009 12, 0x0, sum = 3
5102 00:56:56.441528 13, 0x0, sum = 4
5103 00:56:56.441865 best_step = 11
5104 00:56:56.444409
5105 00:56:56.444886 ==
5106 00:56:56.447598 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 00:56:56.450898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5108 00:56:56.451316 ==
5109 00:56:56.451647 RX Vref Scan: 1
5110 00:56:56.451950
5111 00:56:56.454740 RX Vref 0 -> 0, step: 1
5112 00:56:56.455253
5113 00:56:56.457652 RX Delay -69 -> 252, step: 4
5114 00:56:56.458189
5115 00:56:56.460853 Set Vref, RX VrefLevel [Byte0]: 46
5116 00:56:56.463984 [Byte1]: 49
5117 00:56:56.467059
5118 00:56:56.467468 Final RX Vref Byte 0 = 46 to rank0
5119 00:56:56.470441 Final RX Vref Byte 1 = 49 to rank0
5120 00:56:56.473824 Final RX Vref Byte 0 = 46 to rank1
5121 00:56:56.477755 Final RX Vref Byte 1 = 49 to rank1==
5122 00:56:56.480492 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 00:56:56.487062 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5124 00:56:56.487479 ==
5125 00:56:56.487804 DQS Delay:
5126 00:56:56.490271 DQS0 = 0, DQS1 = 0
5127 00:56:56.490683 DQM Delay:
5128 00:56:56.491010 DQM0 = 97, DQM1 = 87
5129 00:56:56.494445 DQ Delay:
5130 00:56:56.496599 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5131 00:56:56.499957 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =104
5132 00:56:56.503780 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5133 00:56:56.506493 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =98
5134 00:56:56.506720
5135 00:56:56.506897
5136 00:56:56.513548 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5137 00:56:56.516783 CH0 RK0: MR19=505, MR18=2121
5138 00:56:56.523437 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5139 00:56:56.523675
5140 00:56:56.526155 ----->DramcWriteLeveling(PI) begin...
5141 00:56:56.526344 ==
5142 00:56:56.530116 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 00:56:56.532970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5144 00:56:56.533155 ==
5145 00:56:56.536658 Write leveling (Byte 0): 28 => 28
5146 00:56:56.540545 Write leveling (Byte 1): 27 => 27
5147 00:56:56.543810 DramcWriteLeveling(PI) end<-----
5148 00:56:56.543995
5149 00:56:56.544183 ==
5150 00:56:56.545952 Dram Type= 6, Freq= 0, CH_0, rank 1
5151 00:56:56.550300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5152 00:56:56.553156 ==
5153 00:56:56.553340 [Gating] SW mode calibration
5154 00:56:56.562526 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5155 00:56:56.566159 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5156 00:56:56.569628 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 00:56:56.576463 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 00:56:56.580184 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 00:56:56.583034 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 00:56:56.589647 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 00:56:56.593012 0 10 20 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5162 00:56:56.595922 0 10 24 | B1->B0 | 2525 2525 | 0 0 | (1 0) (0 0)
5163 00:56:56.603276 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 00:56:56.606469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 00:56:56.609309 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 00:56:56.616255 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 00:56:56.619106 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 00:56:56.622694 0 11 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5169 00:56:56.629180 0 11 20 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5170 00:56:56.632247 0 11 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5171 00:56:56.635628 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 00:56:56.642231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 00:56:56.645523 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 00:56:56.648743 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 00:56:56.656254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 00:56:56.659039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 00:56:56.662099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5178 00:56:56.668524 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5179 00:56:56.672477 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 00:56:56.675626 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 00:56:56.681934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 00:56:56.685692 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 00:56:56.689111 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 00:56:56.695319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 00:56:56.698843 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 00:56:56.702310 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 00:56:56.709163 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 00:56:56.712481 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 00:56:56.715317 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 00:56:56.721722 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 00:56:56.725321 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 00:56:56.729054 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 00:56:56.735793 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5194 00:56:56.738896 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 00:56:56.742568 Total UI for P1: 0, mck2ui 16
5196 00:56:56.745492 best dqsien dly found for B0: ( 0, 14, 20)
5197 00:56:56.748512 Total UI for P1: 0, mck2ui 16
5198 00:56:56.751511 best dqsien dly found for B1: ( 0, 14, 20)
5199 00:56:56.755068 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5200 00:56:56.758659 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5201 00:56:56.759117
5202 00:56:56.761356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5203 00:56:56.765226 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5204 00:56:56.768782 [Gating] SW calibration Done
5205 00:56:56.769341 ==
5206 00:56:56.772105 Dram Type= 6, Freq= 0, CH_0, rank 1
5207 00:56:56.775402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5208 00:56:56.778291 ==
5209 00:56:56.778745 RX Vref Scan: 0
5210 00:56:56.779102
5211 00:56:56.781975 RX Vref 0 -> 0, step: 1
5212 00:56:56.782526
5213 00:56:56.782886 RX Delay -80 -> 252, step: 8
5214 00:56:56.788549 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5215 00:56:56.792511 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5216 00:56:56.794946 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5217 00:56:56.799548 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5218 00:56:56.802135 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5219 00:56:56.805084 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5220 00:56:56.812374 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5221 00:56:56.815510 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5222 00:56:56.818137 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5223 00:56:56.821239 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5224 00:56:56.824952 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5225 00:56:56.831297 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5226 00:56:56.834516 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5227 00:56:56.838233 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5228 00:56:56.841854 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5229 00:56:56.844641 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5230 00:56:56.845097 ==
5231 00:56:56.848025 Dram Type= 6, Freq= 0, CH_0, rank 1
5232 00:56:56.854529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5233 00:56:56.855085 ==
5234 00:56:56.855451 DQS Delay:
5235 00:56:56.858132 DQS0 = 0, DQS1 = 0
5236 00:56:56.858587 DQM Delay:
5237 00:56:56.858975 DQM0 = 96, DQM1 = 85
5238 00:56:56.861149 DQ Delay:
5239 00:56:56.864806 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =87
5240 00:56:56.867529 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5241 00:56:56.871041 DQ8 =71, DQ9 =71, DQ10 =83, DQ11 =75
5242 00:56:56.874485 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5243 00:56:56.875033
5244 00:56:56.875424
5245 00:56:56.875932 ==
5246 00:56:56.877661 Dram Type= 6, Freq= 0, CH_0, rank 1
5247 00:56:56.881548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5248 00:56:56.882102 ==
5249 00:56:56.882465
5250 00:56:56.882794
5251 00:56:56.884681 TX Vref Scan disable
5252 00:56:56.887827 == TX Byte 0 ==
5253 00:56:56.891170 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5254 00:56:56.894853 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5255 00:56:56.899166 == TX Byte 1 ==
5256 00:56:56.900643 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5257 00:56:56.904397 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5258 00:56:56.905041 ==
5259 00:56:56.907470 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 00:56:56.910779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5261 00:56:56.914566 ==
5262 00:56:56.915024
5263 00:56:56.915388
5264 00:56:56.915729 TX Vref Scan disable
5265 00:56:56.918002 == TX Byte 0 ==
5266 00:56:56.921213 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5267 00:56:56.927499 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5268 00:56:56.928058 == TX Byte 1 ==
5269 00:56:56.931025 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5270 00:56:56.937516 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5271 00:56:56.938070
5272 00:56:56.938433 [DATLAT]
5273 00:56:56.938775 Freq=933, CH0 RK1
5274 00:56:56.939106
5275 00:56:56.941284 DATLAT Default: 0xb
5276 00:56:56.941919 0, 0xFFFF, sum = 0
5277 00:56:56.944227 1, 0xFFFF, sum = 0
5278 00:56:56.944836 2, 0xFFFF, sum = 0
5279 00:56:56.948027 3, 0xFFFF, sum = 0
5280 00:56:56.951083 4, 0xFFFF, sum = 0
5281 00:56:56.951564 5, 0xFFFF, sum = 0
5282 00:56:56.954448 6, 0xFFFF, sum = 0
5283 00:56:56.955030 7, 0xFFFF, sum = 0
5284 00:56:56.957730 8, 0xFFFF, sum = 0
5285 00:56:56.958208 9, 0xFFFF, sum = 0
5286 00:56:56.960574 10, 0x0, sum = 1
5287 00:56:56.961301 11, 0x0, sum = 2
5288 00:56:56.964225 12, 0x0, sum = 3
5289 00:56:56.964862 13, 0x0, sum = 4
5290 00:56:56.965366 best_step = 11
5291 00:56:56.965823
5292 00:56:56.967829 ==
5293 00:56:56.971612 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 00:56:56.974103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5295 00:56:56.974596 ==
5296 00:56:56.975076 RX Vref Scan: 0
5297 00:56:56.975530
5298 00:56:56.977491 RX Vref 0 -> 0, step: 1
5299 00:56:56.977961
5300 00:56:56.980787 RX Delay -69 -> 252, step: 4
5301 00:56:56.984243 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5302 00:56:56.990609 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5303 00:56:56.994306 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5304 00:56:56.997289 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5305 00:56:57.000804 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5306 00:56:57.003996 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5307 00:56:57.010365 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5308 00:56:57.014563 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5309 00:56:57.017389 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5310 00:56:57.020296 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5311 00:56:57.023804 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5312 00:56:57.030196 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5313 00:56:57.033716 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5314 00:56:57.037256 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5315 00:56:57.040177 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5316 00:56:57.043243 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5317 00:56:57.043920 ==
5318 00:56:57.046605 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 00:56:57.053885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5320 00:56:57.054423 ==
5321 00:56:57.054869 DQS Delay:
5322 00:56:57.057115 DQS0 = 0, DQS1 = 0
5323 00:56:57.057650 DQM Delay:
5324 00:56:57.058095 DQM0 = 97, DQM1 = 86
5325 00:56:57.059737 DQ Delay:
5326 00:56:57.064243 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =92
5327 00:56:57.066865 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5328 00:56:57.070126 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5329 00:56:57.074242 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5330 00:56:57.074779
5331 00:56:57.075223
5332 00:56:57.080353 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5333 00:56:57.083633 CH0 RK1: MR19=505, MR18=2929
5334 00:56:57.090284 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5335 00:56:57.093077 [RxdqsGatingPostProcess] freq 933
5336 00:56:57.096643 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5337 00:56:57.099830 Pre-setting of DQS Precalculation
5338 00:56:57.106560 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5339 00:56:57.107122 ==
5340 00:56:57.109189 Dram Type= 6, Freq= 0, CH_1, rank 0
5341 00:56:57.112538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5342 00:56:57.113005 ==
5343 00:56:57.119588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5344 00:56:57.126183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5345 00:56:57.130254 [CA 0] Center 37 (7~68) winsize 62
5346 00:56:57.132377 [CA 1] Center 37 (6~68) winsize 63
5347 00:56:57.136201 [CA 2] Center 34 (4~65) winsize 62
5348 00:56:57.139549 [CA 3] Center 34 (4~65) winsize 62
5349 00:56:57.142389 [CA 4] Center 33 (2~64) winsize 63
5350 00:56:57.145766 [CA 5] Center 33 (2~64) winsize 63
5351 00:56:57.146180
5352 00:56:57.149195 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5353 00:56:57.149717
5354 00:56:57.152683 [CATrainingPosCal] consider 1 rank data
5355 00:56:57.156339 u2DelayCellTimex100 = 270/100 ps
5356 00:56:57.159458 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5357 00:56:57.162892 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5358 00:56:57.165745 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5359 00:56:57.169543 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5360 00:56:57.172213 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5361 00:56:57.175457 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5362 00:56:57.175865
5363 00:56:57.182716 CA PerBit enable=1, Macro0, CA PI delay=33
5364 00:56:57.183126
5365 00:56:57.185480 [CBTSetCACLKResult] CA Dly = 33
5366 00:56:57.185890 CS Dly: 5 (0~36)
5367 00:56:57.186215 ==
5368 00:56:57.189008 Dram Type= 6, Freq= 0, CH_1, rank 1
5369 00:56:57.192276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5370 00:56:57.192833 ==
5371 00:56:57.198809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5372 00:56:57.205760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5373 00:56:57.209346 [CA 0] Center 37 (7~68) winsize 62
5374 00:56:57.212222 [CA 1] Center 37 (6~68) winsize 63
5375 00:56:57.216034 [CA 2] Center 34 (4~65) winsize 62
5376 00:56:57.219167 [CA 3] Center 34 (4~65) winsize 62
5377 00:56:57.222410 [CA 4] Center 33 (3~64) winsize 62
5378 00:56:57.224997 [CA 5] Center 33 (2~64) winsize 63
5379 00:56:57.225407
5380 00:56:57.228329 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5381 00:56:57.228767
5382 00:56:57.232697 [CATrainingPosCal] consider 2 rank data
5383 00:56:57.235288 u2DelayCellTimex100 = 270/100 ps
5384 00:56:57.239122 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5385 00:56:57.241986 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5386 00:56:57.245085 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5387 00:56:57.248859 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5388 00:56:57.251705 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5389 00:56:57.258667 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5390 00:56:57.259211
5391 00:56:57.261611 CA PerBit enable=1, Macro0, CA PI delay=33
5392 00:56:57.262065
5393 00:56:57.265182 [CBTSetCACLKResult] CA Dly = 33
5394 00:56:57.265633 CS Dly: 5 (0~37)
5395 00:56:57.265986
5396 00:56:57.268577 ----->DramcWriteLeveling(PI) begin...
5397 00:56:57.269190 ==
5398 00:56:57.271516 Dram Type= 6, Freq= 0, CH_1, rank 0
5399 00:56:57.279059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5400 00:56:57.279614 ==
5401 00:56:57.281371 Write leveling (Byte 0): 23 => 23
5402 00:56:57.281823 Write leveling (Byte 1): 25 => 25
5403 00:56:57.285487 DramcWriteLeveling(PI) end<-----
5404 00:56:57.286028
5405 00:56:57.286403 ==
5406 00:56:57.288746 Dram Type= 6, Freq= 0, CH_1, rank 0
5407 00:56:57.294845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5408 00:56:57.295396 ==
5409 00:56:57.298336 [Gating] SW mode calibration
5410 00:56:57.304942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5411 00:56:57.308670 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5412 00:56:57.315473 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 00:56:57.317992 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5414 00:56:57.321687 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5415 00:56:57.328145 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5416 00:56:57.331509 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
5417 00:56:57.334731 0 10 20 | B1->B0 | 3131 2a2a | 0 0 | (1 1) (0 0)
5418 00:56:57.343073 0 10 24 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
5419 00:56:57.344947 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 00:56:57.347503 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 00:56:57.354983 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 00:56:57.357848 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5423 00:56:57.361321 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5424 00:56:57.367821 0 11 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5425 00:56:57.370945 0 11 20 | B1->B0 | 3232 4545 | 0 0 | (1 1) (0 0)
5426 00:56:57.374750 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5427 00:56:57.381229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 00:56:57.384510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 00:56:57.387391 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 00:56:57.394112 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 00:56:57.397331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 00:56:57.401073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5433 00:56:57.407375 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 00:56:57.410662 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 00:56:57.414059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 00:56:57.420898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 00:56:57.423831 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 00:56:57.427722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 00:56:57.433527 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 00:56:57.436905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 00:56:57.440901 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 00:56:57.446805 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 00:56:57.450137 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 00:56:57.453333 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 00:56:57.459687 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 00:56:57.464022 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 00:56:57.466508 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 00:56:57.469998 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5449 00:56:57.473091 Total UI for P1: 0, mck2ui 16
5450 00:56:57.476995 best dqsien dly found for B0: ( 0, 14, 14)
5451 00:56:57.483373 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5452 00:56:57.486804 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5453 00:56:57.489764 Total UI for P1: 0, mck2ui 16
5454 00:56:57.493622 best dqsien dly found for B1: ( 0, 14, 18)
5455 00:56:57.496763 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5456 00:56:57.499882 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5457 00:56:57.500434
5458 00:56:57.502700 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5459 00:56:57.510071 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5460 00:56:57.510628 [Gating] SW calibration Done
5461 00:56:57.511000 ==
5462 00:56:57.513288 Dram Type= 6, Freq= 0, CH_1, rank 0
5463 00:56:57.520699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5464 00:56:57.521305 ==
5465 00:56:57.521669 RX Vref Scan: 0
5466 00:56:57.522009
5467 00:56:57.522813 RX Vref 0 -> 0, step: 1
5468 00:56:57.523266
5469 00:56:57.526561 RX Delay -80 -> 252, step: 8
5470 00:56:57.530026 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5471 00:56:57.532890 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5472 00:56:57.536402 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5473 00:56:57.542813 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5474 00:56:57.546591 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5475 00:56:57.549595 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5476 00:56:57.552936 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5477 00:56:57.556414 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5478 00:56:57.559643 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5479 00:56:57.565738 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5480 00:56:57.569371 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5481 00:56:57.573007 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5482 00:56:57.576391 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5483 00:56:57.579624 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5484 00:56:57.585766 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5485 00:56:57.589397 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5486 00:56:57.589951 ==
5487 00:56:57.592364 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 00:56:57.595805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5489 00:56:57.596367 ==
5490 00:56:57.596772 DQS Delay:
5491 00:56:57.599023 DQS0 = 0, DQS1 = 0
5492 00:56:57.599575 DQM Delay:
5493 00:56:57.602430 DQM0 = 96, DQM1 = 89
5494 00:56:57.602985 DQ Delay:
5495 00:56:57.606420 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5496 00:56:57.609968 DQ4 =95, DQ5 =111, DQ6 =103, DQ7 =95
5497 00:56:57.612643 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =83
5498 00:56:57.615901 DQ12 =95, DQ13 =107, DQ14 =95, DQ15 =99
5499 00:56:57.616355
5500 00:56:57.616758
5501 00:56:57.617113 ==
5502 00:56:57.619467 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 00:56:57.625711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5504 00:56:57.626267 ==
5505 00:56:57.626630
5506 00:56:57.626963
5507 00:56:57.627279 TX Vref Scan disable
5508 00:56:57.628967 == TX Byte 0 ==
5509 00:56:57.632559 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5510 00:56:57.638692 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5511 00:56:57.639248 == TX Byte 1 ==
5512 00:56:57.642153 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5513 00:56:57.648838 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5514 00:56:57.649396 ==
5515 00:56:57.652197 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 00:56:57.655125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 00:56:57.655580 ==
5518 00:56:57.655938
5519 00:56:57.656268
5520 00:56:57.658365 TX Vref Scan disable
5521 00:56:57.658818 == TX Byte 0 ==
5522 00:56:57.665314 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5523 00:56:57.668798 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5524 00:56:57.669347 == TX Byte 1 ==
5525 00:56:57.675686 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5526 00:56:57.679097 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5527 00:56:57.679652
5528 00:56:57.680013 [DATLAT]
5529 00:56:57.681710 Freq=933, CH1 RK0
5530 00:56:57.682184
5531 00:56:57.682603 DATLAT Default: 0xd
5532 00:56:57.685618 0, 0xFFFF, sum = 0
5533 00:56:57.686175 1, 0xFFFF, sum = 0
5534 00:56:57.688497 2, 0xFFFF, sum = 0
5535 00:56:57.691904 3, 0xFFFF, sum = 0
5536 00:56:57.692457 4, 0xFFFF, sum = 0
5537 00:56:57.695164 5, 0xFFFF, sum = 0
5538 00:56:57.695750 6, 0xFFFF, sum = 0
5539 00:56:57.698279 7, 0xFFFF, sum = 0
5540 00:56:57.698836 8, 0xFFFF, sum = 0
5541 00:56:57.701565 9, 0xFFFF, sum = 0
5542 00:56:57.702123 10, 0x0, sum = 1
5543 00:56:57.705618 11, 0x0, sum = 2
5544 00:56:57.706219 12, 0x0, sum = 3
5545 00:56:57.708106 13, 0x0, sum = 4
5546 00:56:57.708566 best_step = 11
5547 00:56:57.708954
5548 00:56:57.709290 ==
5549 00:56:57.711597 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 00:56:57.715132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5551 00:56:57.715609 ==
5552 00:56:57.718347 RX Vref Scan: 1
5553 00:56:57.718902
5554 00:56:57.721274 RX Vref 0 -> 0, step: 1
5555 00:56:57.721731
5556 00:56:57.722090 RX Delay -69 -> 252, step: 4
5557 00:56:57.724422
5558 00:56:57.724921 Set Vref, RX VrefLevel [Byte0]: 52
5559 00:56:57.728182 [Byte1]: 49
5560 00:56:57.732759
5561 00:56:57.733217 Final RX Vref Byte 0 = 52 to rank0
5562 00:56:57.736465 Final RX Vref Byte 1 = 49 to rank0
5563 00:56:57.739497 Final RX Vref Byte 0 = 52 to rank1
5564 00:56:57.743391 Final RX Vref Byte 1 = 49 to rank1==
5565 00:56:57.746418 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 00:56:57.753342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5567 00:56:57.753895 ==
5568 00:56:57.754259 DQS Delay:
5569 00:56:57.754596 DQS0 = 0, DQS1 = 0
5570 00:56:57.755966 DQM Delay:
5571 00:56:57.756352 DQM0 = 96, DQM1 = 90
5572 00:56:57.759845 DQ Delay:
5573 00:56:57.763086 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =92
5574 00:56:57.766453 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5575 00:56:57.769320 DQ8 =74, DQ9 =78, DQ10 =92, DQ11 =82
5576 00:56:57.772762 DQ12 =96, DQ13 =102, DQ14 =98, DQ15 =100
5577 00:56:57.773320
5578 00:56:57.773679
5579 00:56:57.779454 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5580 00:56:57.783354 CH1 RK0: MR19=505, MR18=3131
5581 00:56:57.789413 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5582 00:56:57.790057
5583 00:56:57.792668 ----->DramcWriteLeveling(PI) begin...
5584 00:56:57.793264 ==
5585 00:56:57.795737 Dram Type= 6, Freq= 0, CH_1, rank 1
5586 00:56:57.799677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5587 00:56:57.800231 ==
5588 00:56:57.802688 Write leveling (Byte 0): 24 => 24
5589 00:56:57.805711 Write leveling (Byte 1): 24 => 24
5590 00:56:57.808834 DramcWriteLeveling(PI) end<-----
5591 00:56:57.809378
5592 00:56:57.809741 ==
5593 00:56:57.812217 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 00:56:57.815483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5595 00:56:57.819139 ==
5596 00:56:57.819702 [Gating] SW mode calibration
5597 00:56:57.828886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5598 00:56:57.832494 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5599 00:56:57.835560 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 00:56:57.841976 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 00:56:57.845553 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 00:56:57.848321 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5603 00:56:57.855247 0 10 16 | B1->B0 | 3333 2727 | 0 0 | (1 0) (1 1)
5604 00:56:57.858320 0 10 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5605 00:56:57.861880 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 00:56:57.868586 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 00:56:57.872034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 00:56:57.875531 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 00:56:57.881997 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 00:56:57.885070 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 00:56:57.889205 0 11 16 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
5612 00:56:57.896694 0 11 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5613 00:56:57.898346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 00:56:57.901641 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 00:56:57.908674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 00:56:57.911414 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 00:56:57.914682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 00:56:57.921256 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5619 00:56:57.924498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5620 00:56:57.927951 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5621 00:56:57.934734 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 00:56:57.937778 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 00:56:57.941644 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 00:56:57.947884 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 00:56:57.950885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 00:56:57.954464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 00:56:57.960633 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 00:56:57.964511 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 00:56:57.967857 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 00:56:57.973960 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 00:56:57.977293 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 00:56:57.980748 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 00:56:57.988359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 00:56:57.990739 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5635 00:56:57.994696 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5636 00:56:58.001217 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5637 00:56:58.001732 Total UI for P1: 0, mck2ui 16
5638 00:56:58.007302 best dqsien dly found for B0: ( 0, 14, 14)
5639 00:56:58.011306 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 00:56:58.014038 Total UI for P1: 0, mck2ui 16
5641 00:56:58.017002 best dqsien dly found for B1: ( 0, 14, 20)
5642 00:56:58.021289 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5643 00:56:58.023739 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5644 00:56:58.024153
5645 00:56:58.028053 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5646 00:56:58.030790 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5647 00:56:58.033505 [Gating] SW calibration Done
5648 00:56:58.033917 ==
5649 00:56:58.037425 Dram Type= 6, Freq= 0, CH_1, rank 1
5650 00:56:58.040206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5651 00:56:58.043945 ==
5652 00:56:58.044464 RX Vref Scan: 0
5653 00:56:58.044862
5654 00:56:58.047471 RX Vref 0 -> 0, step: 1
5655 00:56:58.047980
5656 00:56:58.050569 RX Delay -80 -> 252, step: 8
5657 00:56:58.053738 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5658 00:56:58.057042 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5659 00:56:58.060164 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5660 00:56:58.064115 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5661 00:56:58.067063 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5662 00:56:58.070343 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5663 00:56:58.076797 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5664 00:56:58.080927 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5665 00:56:58.083743 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5666 00:56:58.087005 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5667 00:56:58.090628 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5668 00:56:58.096875 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5669 00:56:58.100060 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5670 00:56:58.104134 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5671 00:56:58.106460 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5672 00:56:58.110004 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5673 00:56:58.110557 ==
5674 00:56:58.113249 Dram Type= 6, Freq= 0, CH_1, rank 1
5675 00:56:58.119970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5676 00:56:58.120526 ==
5677 00:56:58.120957 DQS Delay:
5678 00:56:58.123308 DQS0 = 0, DQS1 = 0
5679 00:56:58.123894 DQM Delay:
5680 00:56:58.124261 DQM0 = 97, DQM1 = 89
5681 00:56:58.126243 DQ Delay:
5682 00:56:58.129951 DQ0 =99, DQ1 =91, DQ2 =91, DQ3 =95
5683 00:56:58.133210 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5684 00:56:58.136483 DQ8 =75, DQ9 =75, DQ10 =95, DQ11 =83
5685 00:56:58.139792 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5686 00:56:58.140545
5687 00:56:58.140998
5688 00:56:58.141341 ==
5689 00:56:58.142838 Dram Type= 6, Freq= 0, CH_1, rank 1
5690 00:56:58.146450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5691 00:56:58.147006 ==
5692 00:56:58.147365
5693 00:56:58.147698
5694 00:56:58.149519 TX Vref Scan disable
5695 00:56:58.152851 == TX Byte 0 ==
5696 00:56:58.156316 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5697 00:56:58.159179 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5698 00:56:58.162652 == TX Byte 1 ==
5699 00:56:58.166453 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5700 00:56:58.169436 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5701 00:56:58.169892 ==
5702 00:56:58.173067 Dram Type= 6, Freq= 0, CH_1, rank 1
5703 00:56:58.175748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5704 00:56:58.179284 ==
5705 00:56:58.179837
5706 00:56:58.180199
5707 00:56:58.180535 TX Vref Scan disable
5708 00:56:58.183100 == TX Byte 0 ==
5709 00:56:58.186380 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5710 00:56:58.193318 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5711 00:56:58.193914 == TX Byte 1 ==
5712 00:56:58.196617 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5713 00:56:58.202602 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5714 00:56:58.203154
5715 00:56:58.203518 [DATLAT]
5716 00:56:58.203848 Freq=933, CH1 RK1
5717 00:56:58.204168
5718 00:56:58.206381 DATLAT Default: 0xb
5719 00:56:58.206934 0, 0xFFFF, sum = 0
5720 00:56:58.209291 1, 0xFFFF, sum = 0
5721 00:56:58.212612 2, 0xFFFF, sum = 0
5722 00:56:58.213211 3, 0xFFFF, sum = 0
5723 00:56:58.215607 4, 0xFFFF, sum = 0
5724 00:56:58.216190 5, 0xFFFF, sum = 0
5725 00:56:58.219001 6, 0xFFFF, sum = 0
5726 00:56:58.219559 7, 0xFFFF, sum = 0
5727 00:56:58.222847 8, 0xFFFF, sum = 0
5728 00:56:58.223426 9, 0xFFFF, sum = 0
5729 00:56:58.226459 10, 0x0, sum = 1
5730 00:56:58.227017 11, 0x0, sum = 2
5731 00:56:58.228650 12, 0x0, sum = 3
5732 00:56:58.229156 13, 0x0, sum = 4
5733 00:56:58.229525 best_step = 11
5734 00:56:58.232984
5735 00:56:58.233533 ==
5736 00:56:58.235939 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 00:56:58.238782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5738 00:56:58.239238 ==
5739 00:56:58.239595 RX Vref Scan: 0
5740 00:56:58.239927
5741 00:56:58.242434 RX Vref 0 -> 0, step: 1
5742 00:56:58.242988
5743 00:56:58.245342 RX Delay -69 -> 252, step: 4
5744 00:56:58.252107 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5745 00:56:58.255357 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5746 00:56:58.258614 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5747 00:56:58.262111 iDelay=203, Bit 3, Center 94 (7 ~ 182) 176
5748 00:56:58.265371 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5749 00:56:58.268810 iDelay=203, Bit 5, Center 110 (19 ~ 202) 184
5750 00:56:58.275302 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5751 00:56:58.279101 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5752 00:56:58.281967 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5753 00:56:58.285167 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5754 00:56:58.288703 iDelay=203, Bit 10, Center 88 (-1 ~ 178) 180
5755 00:56:58.295222 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5756 00:56:58.298858 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5757 00:56:58.301715 iDelay=203, Bit 13, Center 100 (15 ~ 186) 172
5758 00:56:58.305624 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5759 00:56:58.308824 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5760 00:56:58.309389 ==
5761 00:56:58.312332 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 00:56:58.318111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5763 00:56:58.318574 ==
5764 00:56:58.318940 DQS Delay:
5765 00:56:58.322241 DQS0 = 0, DQS1 = 0
5766 00:56:58.322791 DQM Delay:
5767 00:56:58.323153 DQM0 = 98, DQM1 = 89
5768 00:56:58.325102 DQ Delay:
5769 00:56:58.328997 DQ0 =98, DQ1 =92, DQ2 =90, DQ3 =94
5770 00:56:58.332272 DQ4 =98, DQ5 =110, DQ6 =106, DQ7 =96
5771 00:56:58.334636 DQ8 =76, DQ9 =78, DQ10 =88, DQ11 =82
5772 00:56:58.338334 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
5773 00:56:58.338890
5774 00:56:58.339250
5775 00:56:58.345184 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5776 00:56:58.348428 CH1 RK1: MR19=505, MR18=2525
5777 00:56:58.354647 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5778 00:56:58.358612 [RxdqsGatingPostProcess] freq 933
5779 00:56:58.364511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5780 00:56:58.365010 Pre-setting of DQS Precalculation
5781 00:56:58.371124 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5782 00:56:58.377659 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5783 00:56:58.384267 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5784 00:56:58.384864
5785 00:56:58.385234
5786 00:56:58.387689 [Calibration Summary] 1866 Mbps
5787 00:56:58.391740 CH 0, Rank 0
5788 00:56:58.392203 SW Impedance : PASS
5789 00:56:58.394452 DUTY Scan : NO K
5790 00:56:58.398042 ZQ Calibration : PASS
5791 00:56:58.398606 Jitter Meter : NO K
5792 00:56:58.400590 CBT Training : PASS
5793 00:56:58.404091 Write leveling : PASS
5794 00:56:58.404663 RX DQS gating : PASS
5795 00:56:58.407827 RX DQ/DQS(RDDQC) : PASS
5796 00:56:58.408399 TX DQ/DQS : PASS
5797 00:56:58.411171 RX DATLAT : PASS
5798 00:56:58.414669 RX DQ/DQS(Engine): PASS
5799 00:56:58.415130 TX OE : NO K
5800 00:56:58.417217 All Pass.
5801 00:56:58.417880
5802 00:56:58.418261 CH 0, Rank 1
5803 00:56:58.421059 SW Impedance : PASS
5804 00:56:58.421521 DUTY Scan : NO K
5805 00:56:58.424125 ZQ Calibration : PASS
5806 00:56:58.427744 Jitter Meter : NO K
5807 00:56:58.428301 CBT Training : PASS
5808 00:56:58.431189 Write leveling : PASS
5809 00:56:58.434555 RX DQS gating : PASS
5810 00:56:58.435113 RX DQ/DQS(RDDQC) : PASS
5811 00:56:58.437386 TX DQ/DQS : PASS
5812 00:56:58.440811 RX DATLAT : PASS
5813 00:56:58.441368 RX DQ/DQS(Engine): PASS
5814 00:56:58.443811 TX OE : NO K
5815 00:56:58.444276 All Pass.
5816 00:56:58.444643
5817 00:56:58.447964 CH 1, Rank 0
5818 00:56:58.448517 SW Impedance : PASS
5819 00:56:58.451209 DUTY Scan : NO K
5820 00:56:58.454173 ZQ Calibration : PASS
5821 00:56:58.454701 Jitter Meter : NO K
5822 00:56:58.457166 CBT Training : PASS
5823 00:56:58.460454 Write leveling : PASS
5824 00:56:58.460965 RX DQS gating : PASS
5825 00:56:58.463873 RX DQ/DQS(RDDQC) : PASS
5826 00:56:58.467341 TX DQ/DQS : PASS
5827 00:56:58.467818 RX DATLAT : PASS
5828 00:56:58.470488 RX DQ/DQS(Engine): PASS
5829 00:56:58.471046 TX OE : NO K
5830 00:56:58.474541 All Pass.
5831 00:56:58.475096
5832 00:56:58.475464 CH 1, Rank 1
5833 00:56:58.476639 SW Impedance : PASS
5834 00:56:58.477153 DUTY Scan : NO K
5835 00:56:58.480456 ZQ Calibration : PASS
5836 00:56:58.484758 Jitter Meter : NO K
5837 00:56:58.485319 CBT Training : PASS
5838 00:56:58.487027 Write leveling : PASS
5839 00:56:58.490228 RX DQS gating : PASS
5840 00:56:58.490689 RX DQ/DQS(RDDQC) : PASS
5841 00:56:58.493993 TX DQ/DQS : PASS
5842 00:56:58.497629 RX DATLAT : PASS
5843 00:56:58.498362 RX DQ/DQS(Engine): PASS
5844 00:56:58.499798 TX OE : NO K
5845 00:56:58.500261 All Pass.
5846 00:56:58.500623
5847 00:56:58.503325 DramC Write-DBI off
5848 00:56:58.506561 PER_BANK_REFRESH: Hybrid Mode
5849 00:56:58.507026 TX_TRACKING: ON
5850 00:56:58.516846 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5851 00:56:58.519836 [FAST_K] Save calibration result to emmc
5852 00:56:58.523243 dramc_set_vcore_voltage set vcore to 650000
5853 00:56:58.526531 Read voltage for 400, 6
5854 00:56:58.527096 Vio18 = 0
5855 00:56:58.527463 Vcore = 650000
5856 00:56:58.529574 Vdram = 0
5857 00:56:58.530031 Vddq = 0
5858 00:56:58.530395 Vmddr = 0
5859 00:56:58.536232 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5860 00:56:58.539464 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5861 00:56:58.543320 MEM_TYPE=3, freq_sel=20
5862 00:56:58.546248 sv_algorithm_assistance_LP4_800
5863 00:56:58.550609 ============ PULL DRAM RESETB DOWN ============
5864 00:56:58.552975 ========== PULL DRAM RESETB DOWN end =========
5865 00:56:58.560069 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5866 00:56:58.563141 ===================================
5867 00:56:58.566533 LPDDR4 DRAM CONFIGURATION
5868 00:56:58.569420 ===================================
5869 00:56:58.569879 EX_ROW_EN[0] = 0x0
5870 00:56:58.573799 EX_ROW_EN[1] = 0x0
5871 00:56:58.574351 LP4Y_EN = 0x0
5872 00:56:58.576575 WORK_FSP = 0x0
5873 00:56:58.577071 WL = 0x2
5874 00:56:58.579880 RL = 0x2
5875 00:56:58.580363 BL = 0x2
5876 00:56:58.582735 RPST = 0x0
5877 00:56:58.583288 RD_PRE = 0x0
5878 00:56:58.586735 WR_PRE = 0x1
5879 00:56:58.587290 WR_PST = 0x0
5880 00:56:58.589363 DBI_WR = 0x0
5881 00:56:58.589820 DBI_RD = 0x0
5882 00:56:58.592973 OTF = 0x1
5883 00:56:58.596435 ===================================
5884 00:56:58.599540 ===================================
5885 00:56:58.600105 ANA top config
5886 00:56:58.602499 ===================================
5887 00:56:58.605564 DLL_ASYNC_EN = 0
5888 00:56:58.609274 ALL_SLAVE_EN = 1
5889 00:56:58.612248 NEW_RANK_MODE = 1
5890 00:56:58.616024 DLL_IDLE_MODE = 1
5891 00:56:58.616485 LP45_APHY_COMB_EN = 1
5892 00:56:58.619011 TX_ODT_DIS = 1
5893 00:56:58.622181 NEW_8X_MODE = 1
5894 00:56:58.626472 ===================================
5895 00:56:58.629380 ===================================
5896 00:56:58.632672 data_rate = 800
5897 00:56:58.636073 CKR = 1
5898 00:56:58.636745 DQ_P2S_RATIO = 4
5899 00:56:58.638971 ===================================
5900 00:56:58.643065 CA_P2S_RATIO = 4
5901 00:56:58.645603 DQ_CA_OPEN = 0
5902 00:56:58.648895 DQ_SEMI_OPEN = 1
5903 00:56:58.653090 CA_SEMI_OPEN = 1
5904 00:56:58.655553 CA_FULL_RATE = 0
5905 00:56:58.656015 DQ_CKDIV4_EN = 0
5906 00:56:58.659222 CA_CKDIV4_EN = 1
5907 00:56:58.662627 CA_PREDIV_EN = 0
5908 00:56:58.665412 PH8_DLY = 0
5909 00:56:58.669534 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5910 00:56:58.672774 DQ_AAMCK_DIV = 0
5911 00:56:58.673323 CA_AAMCK_DIV = 0
5912 00:56:58.675879 CA_ADMCK_DIV = 4
5913 00:56:58.678728 DQ_TRACK_CA_EN = 0
5914 00:56:58.682352 CA_PICK = 800
5915 00:56:58.685670 CA_MCKIO = 400
5916 00:56:58.689157 MCKIO_SEMI = 400
5917 00:56:58.692808 PLL_FREQ = 3016
5918 00:56:58.693376 DQ_UI_PI_RATIO = 32
5919 00:56:58.695971 CA_UI_PI_RATIO = 32
5920 00:56:58.699163 ===================================
5921 00:56:58.702584 ===================================
5922 00:56:58.705341 memory_type:LPDDR4
5923 00:56:58.708693 GP_NUM : 10
5924 00:56:58.709319 SRAM_EN : 1
5925 00:56:58.712356 MD32_EN : 0
5926 00:56:58.715323 ===================================
5927 00:56:58.718180 [ANA_INIT] >>>>>>>>>>>>>>
5928 00:56:58.718737 <<<<<< [CONFIGURE PHASE]: ANA_TX
5929 00:56:58.725146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5930 00:56:58.728532 ===================================
5931 00:56:58.729156 data_rate = 800,PCW = 0X7400
5932 00:56:58.732022 ===================================
5933 00:56:58.735159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5934 00:56:58.741695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5935 00:56:58.751378 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5936 00:56:58.759329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5937 00:56:58.761371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5938 00:56:58.765026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5939 00:56:58.768239 [ANA_INIT] flow start
5940 00:56:58.768831 [ANA_INIT] PLL >>>>>>>>
5941 00:56:58.771503 [ANA_INIT] PLL <<<<<<<<
5942 00:56:58.774583 [ANA_INIT] MIDPI >>>>>>>>
5943 00:56:58.775131 [ANA_INIT] MIDPI <<<<<<<<
5944 00:56:58.778267 [ANA_INIT] DLL >>>>>>>>
5945 00:56:58.781968 [ANA_INIT] flow end
5946 00:56:58.784974 ============ LP4 DIFF to SE enter ============
5947 00:56:58.788204 ============ LP4 DIFF to SE exit ============
5948 00:56:58.791323 [ANA_INIT] <<<<<<<<<<<<<
5949 00:56:58.794664 [Flow] Enable top DCM control >>>>>
5950 00:56:58.798391 [Flow] Enable top DCM control <<<<<
5951 00:56:58.802161 Enable DLL master slave shuffle
5952 00:56:58.804572 ==============================================================
5953 00:56:58.807770 Gating Mode config
5954 00:56:58.814098 ==============================================================
5955 00:56:58.814657 Config description:
5956 00:56:58.824324 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5957 00:56:58.831127 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5958 00:56:58.838146 SELPH_MODE 0: By rank 1: By Phase
5959 00:56:58.840675 ==============================================================
5960 00:56:58.844218 GAT_TRACK_EN = 0
5961 00:56:58.847413 RX_GATING_MODE = 2
5962 00:56:58.850627 RX_GATING_TRACK_MODE = 2
5963 00:56:58.854069 SELPH_MODE = 1
5964 00:56:58.857291 PICG_EARLY_EN = 1
5965 00:56:58.860481 VALID_LAT_VALUE = 1
5966 00:56:58.864128 ==============================================================
5967 00:56:58.866765 Enter into Gating configuration >>>>
5968 00:56:58.870249 Exit from Gating configuration <<<<
5969 00:56:58.874635 Enter into DVFS_PRE_config >>>>>
5970 00:56:58.886901 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5971 00:56:58.890049 Exit from DVFS_PRE_config <<<<<
5972 00:56:58.893253 Enter into PICG configuration >>>>
5973 00:56:58.896978 Exit from PICG configuration <<<<
5974 00:56:58.897534 [RX_INPUT] configuration >>>>>
5975 00:56:58.900106 [RX_INPUT] configuration <<<<<
5976 00:56:58.907253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5977 00:56:58.912881 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5978 00:56:58.916317 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5979 00:56:58.922811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5980 00:56:58.929994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5981 00:56:58.936872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5982 00:56:58.939447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5983 00:56:58.942448 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5984 00:56:58.949400 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5985 00:56:58.953083 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5986 00:56:58.956411 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5987 00:56:58.962807 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5988 00:56:58.966190 ===================================
5989 00:56:58.966650 LPDDR4 DRAM CONFIGURATION
5990 00:56:58.969244 ===================================
5991 00:56:58.973103 EX_ROW_EN[0] = 0x0
5992 00:56:58.973647 EX_ROW_EN[1] = 0x0
5993 00:56:58.976654 LP4Y_EN = 0x0
5994 00:56:58.977280 WORK_FSP = 0x0
5995 00:56:58.980151 WL = 0x2
5996 00:56:58.980605 RL = 0x2
5997 00:56:58.982766 BL = 0x2
5998 00:56:58.985980 RPST = 0x0
5999 00:56:58.986531 RD_PRE = 0x0
6000 00:56:58.989353 WR_PRE = 0x1
6001 00:56:58.989956 WR_PST = 0x0
6002 00:56:58.992961 DBI_WR = 0x0
6003 00:56:58.993414 DBI_RD = 0x0
6004 00:56:58.995782 OTF = 0x1
6005 00:56:58.999518 ===================================
6006 00:56:59.002697 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6007 00:56:59.006568 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6008 00:56:59.009517 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6009 00:56:59.012257 ===================================
6010 00:56:59.015772 LPDDR4 DRAM CONFIGURATION
6011 00:56:59.019009 ===================================
6012 00:56:59.022156 EX_ROW_EN[0] = 0x10
6013 00:56:59.022612 EX_ROW_EN[1] = 0x0
6014 00:56:59.025281 LP4Y_EN = 0x0
6015 00:56:59.025743 WORK_FSP = 0x0
6016 00:56:59.028759 WL = 0x2
6017 00:56:59.032790 RL = 0x2
6018 00:56:59.033342 BL = 0x2
6019 00:56:59.035769 RPST = 0x0
6020 00:56:59.036221 RD_PRE = 0x0
6021 00:56:59.038550 WR_PRE = 0x1
6022 00:56:59.039005 WR_PST = 0x0
6023 00:56:59.041731 DBI_WR = 0x0
6024 00:56:59.042187 DBI_RD = 0x0
6025 00:56:59.045634 OTF = 0x1
6026 00:56:59.048997 ===================================
6027 00:56:59.055175 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6028 00:56:59.058385 nWR fixed to 30
6029 00:56:59.058939 [ModeRegInit_LP4] CH0 RK0
6030 00:56:59.062001 [ModeRegInit_LP4] CH0 RK1
6031 00:56:59.064799 [ModeRegInit_LP4] CH1 RK0
6032 00:56:59.065305 [ModeRegInit_LP4] CH1 RK1
6033 00:56:59.068182 match AC timing 18
6034 00:56:59.071751 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6035 00:56:59.077966 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6036 00:56:59.081734 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6037 00:56:59.084958 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6038 00:56:59.091525 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6039 00:56:59.092093 ==
6040 00:56:59.094433 Dram Type= 6, Freq= 0, CH_0, rank 0
6041 00:56:59.098909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6042 00:56:59.099460 ==
6043 00:56:59.105050 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6044 00:56:59.111597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6045 00:56:59.114994 [CA 0] Center 36 (8~64) winsize 57
6046 00:56:59.115555 [CA 1] Center 36 (8~64) winsize 57
6047 00:56:59.118148 [CA 2] Center 36 (8~64) winsize 57
6048 00:56:59.121209 [CA 3] Center 36 (8~64) winsize 57
6049 00:56:59.124090 [CA 4] Center 36 (8~64) winsize 57
6050 00:56:59.128022 [CA 5] Center 36 (8~64) winsize 57
6051 00:56:59.128478
6052 00:56:59.131493 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6053 00:56:59.131948
6054 00:56:59.135052 [CATrainingPosCal] consider 1 rank data
6055 00:56:59.137980 u2DelayCellTimex100 = 270/100 ps
6056 00:56:59.140979 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 00:56:59.147252 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 00:56:59.151177 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 00:56:59.155119 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6060 00:56:59.158023 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 00:56:59.162013 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 00:56:59.162564
6063 00:56:59.165080 CA PerBit enable=1, Macro0, CA PI delay=36
6064 00:56:59.165635
6065 00:56:59.167416 [CBTSetCACLKResult] CA Dly = 36
6066 00:56:59.170515 CS Dly: 1 (0~32)
6067 00:56:59.170972 ==
6068 00:56:59.173882 Dram Type= 6, Freq= 0, CH_0, rank 1
6069 00:56:59.177671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6070 00:56:59.178239 ==
6071 00:56:59.184581 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6072 00:56:59.187154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6073 00:56:59.190417 [CA 0] Center 36 (8~64) winsize 57
6074 00:56:59.193971 [CA 1] Center 36 (8~64) winsize 57
6075 00:56:59.197199 [CA 2] Center 36 (8~64) winsize 57
6076 00:56:59.200589 [CA 3] Center 36 (8~64) winsize 57
6077 00:56:59.203918 [CA 4] Center 36 (8~64) winsize 57
6078 00:56:59.207609 [CA 5] Center 36 (8~64) winsize 57
6079 00:56:59.208159
6080 00:56:59.210582 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6081 00:56:59.211137
6082 00:56:59.213974 [CATrainingPosCal] consider 2 rank data
6083 00:56:59.217902 u2DelayCellTimex100 = 270/100 ps
6084 00:56:59.220057 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 00:56:59.223679 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 00:56:59.227150 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6087 00:56:59.233433 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6088 00:56:59.237390 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6089 00:56:59.239816 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 00:56:59.240278
6091 00:56:59.243645 CA PerBit enable=1, Macro0, CA PI delay=36
6092 00:56:59.244262
6093 00:56:59.246464 [CBTSetCACLKResult] CA Dly = 36
6094 00:56:59.246929 CS Dly: 1 (0~32)
6095 00:56:59.247292
6096 00:56:59.250383 ----->DramcWriteLeveling(PI) begin...
6097 00:56:59.253676 ==
6098 00:56:59.254239 Dram Type= 6, Freq= 0, CH_0, rank 0
6099 00:56:59.260569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6100 00:56:59.261190 ==
6101 00:56:59.263899 Write leveling (Byte 0): 32 => 0
6102 00:56:59.266958 Write leveling (Byte 1): 32 => 0
6103 00:56:59.267418 DramcWriteLeveling(PI) end<-----
6104 00:56:59.270557
6105 00:56:59.271008 ==
6106 00:56:59.273125 Dram Type= 6, Freq= 0, CH_0, rank 0
6107 00:56:59.276811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6108 00:56:59.277386 ==
6109 00:56:59.280513 [Gating] SW mode calibration
6110 00:56:59.286937 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6111 00:56:59.289909 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6112 00:56:59.296467 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6113 00:56:59.299706 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6114 00:56:59.303335 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6115 00:56:59.309692 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6116 00:56:59.313165 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6117 00:56:59.316351 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6118 00:56:59.322750 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6119 00:56:59.326099 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6120 00:56:59.330073 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6121 00:56:59.332901 Total UI for P1: 0, mck2ui 16
6122 00:56:59.336197 best dqsien dly found for B0: ( 0, 10, 16)
6123 00:56:59.339223 Total UI for P1: 0, mck2ui 16
6124 00:56:59.342794 best dqsien dly found for B1: ( 0, 10, 24)
6125 00:56:59.346033 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6126 00:56:59.352880 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6127 00:56:59.353433
6128 00:56:59.355730 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6129 00:56:59.358877 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6130 00:56:59.362781 [Gating] SW calibration Done
6131 00:56:59.363352 ==
6132 00:56:59.365289 Dram Type= 6, Freq= 0, CH_0, rank 0
6133 00:56:59.369438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6134 00:56:59.369911 ==
6135 00:56:59.372939 RX Vref Scan: 0
6136 00:56:59.373507
6137 00:56:59.373997 RX Vref 0 -> 0, step: 1
6138 00:56:59.374455
6139 00:56:59.375814 RX Delay -410 -> 252, step: 16
6140 00:56:59.382550 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6141 00:56:59.385400 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6142 00:56:59.389078 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6143 00:56:59.392317 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6144 00:56:59.398748 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6145 00:56:59.402585 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6146 00:56:59.405016 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6147 00:56:59.408740 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6148 00:56:59.415678 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6149 00:56:59.418867 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6150 00:56:59.421531 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6151 00:56:59.424667 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6152 00:56:59.432123 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6153 00:56:59.435508 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6154 00:56:59.438528 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6155 00:56:59.441976 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6156 00:56:59.444623 ==
6157 00:56:59.448281 Dram Type= 6, Freq= 0, CH_0, rank 0
6158 00:56:59.451892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6159 00:56:59.452458 ==
6160 00:56:59.453008 DQS Delay:
6161 00:56:59.454888 DQS0 = 51, DQS1 = 59
6162 00:56:59.455418 DQM Delay:
6163 00:56:59.457938 DQM0 = 12, DQM1 = 16
6164 00:56:59.458410 DQ Delay:
6165 00:56:59.461545 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6166 00:56:59.465113 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6167 00:56:59.468073 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6168 00:56:59.471978 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6169 00:56:59.472450
6170 00:56:59.472967
6171 00:56:59.473426 ==
6172 00:56:59.474379 Dram Type= 6, Freq= 0, CH_0, rank 0
6173 00:56:59.478183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6174 00:56:59.478755 ==
6175 00:56:59.479240
6176 00:56:59.479688
6177 00:56:59.481286 TX Vref Scan disable
6178 00:56:59.481758 == TX Byte 0 ==
6179 00:56:59.487900 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6180 00:56:59.491690 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6181 00:56:59.492269 == TX Byte 1 ==
6182 00:56:59.498152 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6183 00:56:59.501160 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6184 00:56:59.501638 ==
6185 00:56:59.504785 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 00:56:59.507954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 00:56:59.508525 ==
6188 00:56:59.509062
6189 00:56:59.509517
6190 00:56:59.510770 TX Vref Scan disable
6191 00:56:59.514541 == TX Byte 0 ==
6192 00:56:59.518064 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6193 00:56:59.521025 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6194 00:56:59.524537 == TX Byte 1 ==
6195 00:56:59.527875 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6196 00:56:59.530898 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6197 00:56:59.531466
6198 00:56:59.531952 [DATLAT]
6199 00:56:59.534397 Freq=400, CH0 RK0
6200 00:56:59.534868
6201 00:56:59.537384 DATLAT Default: 0xf
6202 00:56:59.537954 0, 0xFFFF, sum = 0
6203 00:56:59.540687 1, 0xFFFF, sum = 0
6204 00:56:59.541317 2, 0xFFFF, sum = 0
6205 00:56:59.543806 3, 0xFFFF, sum = 0
6206 00:56:59.544286 4, 0xFFFF, sum = 0
6207 00:56:59.547625 5, 0xFFFF, sum = 0
6208 00:56:59.548198 6, 0xFFFF, sum = 0
6209 00:56:59.551098 7, 0xFFFF, sum = 0
6210 00:56:59.551675 8, 0xFFFF, sum = 0
6211 00:56:59.554347 9, 0xFFFF, sum = 0
6212 00:56:59.554821 10, 0xFFFF, sum = 0
6213 00:56:59.557197 11, 0xFFFF, sum = 0
6214 00:56:59.557676 12, 0x0, sum = 1
6215 00:56:59.560964 13, 0x0, sum = 2
6216 00:56:59.561443 14, 0x0, sum = 3
6217 00:56:59.563773 15, 0x0, sum = 4
6218 00:56:59.564251 best_step = 13
6219 00:56:59.564861
6220 00:56:59.565318 ==
6221 00:56:59.567427 Dram Type= 6, Freq= 0, CH_0, rank 0
6222 00:56:59.573484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6223 00:56:59.573958 ==
6224 00:56:59.574443 RX Vref Scan: 1
6225 00:56:59.574898
6226 00:56:59.577579 RX Vref 0 -> 0, step: 1
6227 00:56:59.578150
6228 00:56:59.580884 RX Delay -359 -> 252, step: 8
6229 00:56:59.581446
6230 00:56:59.584096 Set Vref, RX VrefLevel [Byte0]: 46
6231 00:56:59.587510 [Byte1]: 49
6232 00:56:59.587966
6233 00:56:59.591117 Final RX Vref Byte 0 = 46 to rank0
6234 00:56:59.593959 Final RX Vref Byte 1 = 49 to rank0
6235 00:56:59.597283 Final RX Vref Byte 0 = 46 to rank1
6236 00:56:59.600277 Final RX Vref Byte 1 = 49 to rank1==
6237 00:56:59.603666 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 00:56:59.607005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6239 00:56:59.610274 ==
6240 00:56:59.610825 DQS Delay:
6241 00:56:59.611188 DQS0 = 52, DQS1 = 68
6242 00:56:59.613421 DQM Delay:
6243 00:56:59.614055 DQM0 = 9, DQM1 = 17
6244 00:56:59.616687 DQ Delay:
6245 00:56:59.617293 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6246 00:56:59.619935 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6247 00:56:59.623490 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6248 00:56:59.626952 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6249 00:56:59.627503
6250 00:56:59.627859
6251 00:56:59.636542 [DQSOSCAuto] RK0, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6252 00:56:59.640159 CH0 RK0: MR19=C0C, MR18=ADAD
6253 00:56:59.646951 CH0_RK0: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6254 00:56:59.647581 ==
6255 00:56:59.649701 Dram Type= 6, Freq= 0, CH_0, rank 1
6256 00:56:59.653151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6257 00:56:59.653705 ==
6258 00:56:59.657012 [Gating] SW mode calibration
6259 00:56:59.663046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6260 00:56:59.666018 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6261 00:56:59.672583 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 00:56:59.675925 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 00:56:59.682736 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 00:56:59.686288 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6265 00:56:59.689335 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 00:56:59.696155 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 00:56:59.699256 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 00:56:59.702941 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6269 00:56:59.705872 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 00:56:59.708971 Total UI for P1: 0, mck2ui 16
6271 00:56:59.712589 best dqsien dly found for B0: ( 0, 10, 16)
6272 00:56:59.715344 Total UI for P1: 0, mck2ui 16
6273 00:56:59.718955 best dqsien dly found for B1: ( 0, 10, 16)
6274 00:56:59.726117 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6275 00:56:59.728905 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6276 00:56:59.729450
6277 00:56:59.732524 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6278 00:56:59.735581 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6279 00:56:59.738982 [Gating] SW calibration Done
6280 00:56:59.739535 ==
6281 00:56:59.742596 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 00:56:59.745940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6283 00:56:59.746498 ==
6284 00:56:59.749296 RX Vref Scan: 0
6285 00:56:59.749746
6286 00:56:59.750106 RX Vref 0 -> 0, step: 1
6287 00:56:59.750443
6288 00:56:59.751914 RX Delay -410 -> 252, step: 16
6289 00:56:59.758529 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6290 00:56:59.762001 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6291 00:56:59.764989 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6292 00:56:59.768879 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6293 00:56:59.776016 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6294 00:56:59.778323 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6295 00:56:59.781429 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6296 00:56:59.784938 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6297 00:56:59.791807 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6298 00:56:59.795214 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6299 00:56:59.798285 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6300 00:56:59.801602 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6301 00:56:59.808146 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6302 00:56:59.811561 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6303 00:56:59.814629 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6304 00:56:59.821318 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6305 00:56:59.821860 ==
6306 00:56:59.824745 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 00:56:59.827849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6308 00:56:59.828306 ==
6309 00:56:59.828668 DQS Delay:
6310 00:56:59.831587 DQS0 = 51, DQS1 = 59
6311 00:56:59.832133 DQM Delay:
6312 00:56:59.835081 DQM0 = 14, DQM1 = 14
6313 00:56:59.835623 DQ Delay:
6314 00:56:59.837397 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6315 00:56:59.841595 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6316 00:56:59.844315 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6317 00:56:59.848345 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6318 00:56:59.848949
6319 00:56:59.849316
6320 00:56:59.849649 ==
6321 00:56:59.851023 Dram Type= 6, Freq= 0, CH_0, rank 1
6322 00:56:59.854516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6323 00:56:59.855072 ==
6324 00:56:59.855436
6325 00:56:59.855766
6326 00:56:59.857384 TX Vref Scan disable
6327 00:56:59.857841 == TX Byte 0 ==
6328 00:56:59.864353 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6329 00:56:59.868207 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6330 00:56:59.868800 == TX Byte 1 ==
6331 00:56:59.874596 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6332 00:56:59.877510 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6333 00:56:59.878122 ==
6334 00:56:59.881260 Dram Type= 6, Freq= 0, CH_0, rank 1
6335 00:56:59.883907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6336 00:56:59.884410 ==
6337 00:56:59.884812
6338 00:56:59.885147
6339 00:56:59.888308 TX Vref Scan disable
6340 00:56:59.890739 == TX Byte 0 ==
6341 00:56:59.894609 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6342 00:56:59.896857 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6343 00:56:59.901063 == TX Byte 1 ==
6344 00:56:59.903691 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6345 00:56:59.907115 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6346 00:56:59.907673
6347 00:56:59.908032 [DATLAT]
6348 00:56:59.910306 Freq=400, CH0 RK1
6349 00:56:59.910758
6350 00:56:59.911140 DATLAT Default: 0xd
6351 00:56:59.913975 0, 0xFFFF, sum = 0
6352 00:56:59.914552 1, 0xFFFF, sum = 0
6353 00:56:59.917452 2, 0xFFFF, sum = 0
6354 00:56:59.920260 3, 0xFFFF, sum = 0
6355 00:56:59.920850 4, 0xFFFF, sum = 0
6356 00:56:59.923727 5, 0xFFFF, sum = 0
6357 00:56:59.924522 6, 0xFFFF, sum = 0
6358 00:56:59.927484 7, 0xFFFF, sum = 0
6359 00:56:59.927940 8, 0xFFFF, sum = 0
6360 00:56:59.930386 9, 0xFFFF, sum = 0
6361 00:56:59.930840 10, 0xFFFF, sum = 0
6362 00:56:59.933342 11, 0xFFFF, sum = 0
6363 00:56:59.933796 12, 0x0, sum = 1
6364 00:56:59.937118 13, 0x0, sum = 2
6365 00:56:59.937572 14, 0x0, sum = 3
6366 00:56:59.940822 15, 0x0, sum = 4
6367 00:56:59.941278 best_step = 13
6368 00:56:59.941632
6369 00:56:59.941961 ==
6370 00:56:59.943551 Dram Type= 6, Freq= 0, CH_0, rank 1
6371 00:56:59.946706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6372 00:56:59.947158 ==
6373 00:56:59.950133 RX Vref Scan: 0
6374 00:56:59.950581
6375 00:56:59.953024 RX Vref 0 -> 0, step: 1
6376 00:56:59.953469
6377 00:56:59.956881 RX Delay -359 -> 252, step: 8
6378 00:56:59.960308 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6379 00:56:59.966656 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6380 00:56:59.970854 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6381 00:56:59.973910 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6382 00:56:59.979613 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6383 00:56:59.982980 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6384 00:56:59.986334 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6385 00:56:59.989352 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6386 00:56:59.996319 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6387 00:56:59.999791 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6388 00:57:00.003662 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6389 00:57:00.005854 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6390 00:57:00.012981 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6391 00:57:00.016306 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6392 00:57:00.019767 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6393 00:57:00.022974 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6394 00:57:00.026181 ==
6395 00:57:00.026745 Dram Type= 6, Freq= 0, CH_0, rank 1
6396 00:57:00.032788 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6397 00:57:00.033517 ==
6398 00:57:00.033906 DQS Delay:
6399 00:57:00.036571 DQS0 = 52, DQS1 = 64
6400 00:57:00.037110 DQM Delay:
6401 00:57:00.039749 DQM0 = 10, DQM1 = 14
6402 00:57:00.040306 DQ Delay:
6403 00:57:00.042893 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6404 00:57:00.046025 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6405 00:57:00.049203 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6406 00:57:00.052517 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6407 00:57:00.053123
6408 00:57:00.053491
6409 00:57:00.060010 [DQSOSCAuto] RK1, (LSB)MR18= 0xbdbd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6410 00:57:00.062236 CH0 RK1: MR19=C0C, MR18=BDBD
6411 00:57:00.069116 CH0_RK1: MR19=0xC0C, MR18=0xBDBD, DQSOSC=386, MR23=63, INC=396, DEC=264
6412 00:57:00.072672 [RxdqsGatingPostProcess] freq 400
6413 00:57:00.076625 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6414 00:57:00.079135 Pre-setting of DQS Precalculation
6415 00:57:00.085658 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6416 00:57:00.086220 ==
6417 00:57:00.089021 Dram Type= 6, Freq= 0, CH_1, rank 0
6418 00:57:00.092053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6419 00:57:00.092533 ==
6420 00:57:00.098729 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6421 00:57:00.105043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6422 00:57:00.108909 [CA 0] Center 36 (8~64) winsize 57
6423 00:57:00.112266 [CA 1] Center 36 (8~64) winsize 57
6424 00:57:00.115815 [CA 2] Center 36 (8~64) winsize 57
6425 00:57:00.116439 [CA 3] Center 36 (8~64) winsize 57
6426 00:57:00.119183 [CA 4] Center 36 (8~64) winsize 57
6427 00:57:00.121929 [CA 5] Center 36 (8~64) winsize 57
6428 00:57:00.122389
6429 00:57:00.128570 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6430 00:57:00.129209
6431 00:57:00.131868 [CATrainingPosCal] consider 1 rank data
6432 00:57:00.135267 u2DelayCellTimex100 = 270/100 ps
6433 00:57:00.138275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 00:57:00.142062 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 00:57:00.144813 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6436 00:57:00.147964 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6437 00:57:00.151505 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 00:57:00.155019 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 00:57:00.155585
6440 00:57:00.158381 CA PerBit enable=1, Macro0, CA PI delay=36
6441 00:57:00.158842
6442 00:57:00.161905 [CBTSetCACLKResult] CA Dly = 36
6443 00:57:00.165091 CS Dly: 1 (0~32)
6444 00:57:00.165655 ==
6445 00:57:00.168126 Dram Type= 6, Freq= 0, CH_1, rank 1
6446 00:57:00.171253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6447 00:57:00.171716 ==
6448 00:57:00.178407 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6449 00:57:00.184631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6450 00:57:00.187941 [CA 0] Center 36 (8~64) winsize 57
6451 00:57:00.188509 [CA 1] Center 36 (8~64) winsize 57
6452 00:57:00.191198 [CA 2] Center 36 (8~64) winsize 57
6453 00:57:00.194515 [CA 3] Center 36 (8~64) winsize 57
6454 00:57:00.197974 [CA 4] Center 36 (8~64) winsize 57
6455 00:57:00.201402 [CA 5] Center 36 (8~64) winsize 57
6456 00:57:00.201865
6457 00:57:00.205084 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6458 00:57:00.205644
6459 00:57:00.207548 [CATrainingPosCal] consider 2 rank data
6460 00:57:00.210556 u2DelayCellTimex100 = 270/100 ps
6461 00:57:00.214762 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 00:57:00.221393 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 00:57:00.224141 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6464 00:57:00.227382 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6465 00:57:00.230962 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6466 00:57:00.234562 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 00:57:00.235139
6468 00:57:00.237959 CA PerBit enable=1, Macro0, CA PI delay=36
6469 00:57:00.238421
6470 00:57:00.240420 [CBTSetCACLKResult] CA Dly = 36
6471 00:57:00.240913 CS Dly: 1 (0~32)
6472 00:57:00.244133
6473 00:57:00.247105 ----->DramcWriteLeveling(PI) begin...
6474 00:57:00.247573 ==
6475 00:57:00.250816 Dram Type= 6, Freq= 0, CH_1, rank 0
6476 00:57:00.254035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6477 00:57:00.254673 ==
6478 00:57:00.257393 Write leveling (Byte 0): 32 => 0
6479 00:57:00.261170 Write leveling (Byte 1): 32 => 0
6480 00:57:00.264659 DramcWriteLeveling(PI) end<-----
6481 00:57:00.265260
6482 00:57:00.265626 ==
6483 00:57:00.267865 Dram Type= 6, Freq= 0, CH_1, rank 0
6484 00:57:00.271440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6485 00:57:00.271904 ==
6486 00:57:00.274490 [Gating] SW mode calibration
6487 00:57:00.281049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6488 00:57:00.287947 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6489 00:57:00.290861 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 00:57:00.293553 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 00:57:00.300877 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 00:57:00.303956 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 00:57:00.307403 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 00:57:00.313701 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 00:57:00.317353 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 00:57:00.320603 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6497 00:57:00.327708 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 00:57:00.328321 Total UI for P1: 0, mck2ui 16
6499 00:57:00.330568 best dqsien dly found for B0: ( 0, 10, 16)
6500 00:57:00.333511 Total UI for P1: 0, mck2ui 16
6501 00:57:00.336986 best dqsien dly found for B1: ( 0, 10, 16)
6502 00:57:00.343472 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6503 00:57:00.347065 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6504 00:57:00.347654
6505 00:57:00.350655 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6506 00:57:00.353859 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6507 00:57:00.356590 [Gating] SW calibration Done
6508 00:57:00.357215 ==
6509 00:57:00.359811 Dram Type= 6, Freq= 0, CH_1, rank 0
6510 00:57:00.362917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6511 00:57:00.363563 ==
6512 00:57:00.366522 RX Vref Scan: 0
6513 00:57:00.367087
6514 00:57:00.367596 RX Vref 0 -> 0, step: 1
6515 00:57:00.369212
6516 00:57:00.369846 RX Delay -410 -> 252, step: 16
6517 00:57:00.376156 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6518 00:57:00.380034 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6519 00:57:00.383210 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6520 00:57:00.386392 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6521 00:57:00.392891 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6522 00:57:00.396221 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6523 00:57:00.399800 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6524 00:57:00.403284 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6525 00:57:00.409123 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6526 00:57:00.412879 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6527 00:57:00.416131 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6528 00:57:00.422433 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6529 00:57:00.425712 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6530 00:57:00.428543 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6531 00:57:00.432466 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6532 00:57:00.439163 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6533 00:57:00.439727 ==
6534 00:57:00.442568 Dram Type= 6, Freq= 0, CH_1, rank 0
6535 00:57:00.445289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6536 00:57:00.445751 ==
6537 00:57:00.446115 DQS Delay:
6538 00:57:00.448426 DQS0 = 43, DQS1 = 59
6539 00:57:00.448920 DQM Delay:
6540 00:57:00.452234 DQM0 = 6, DQM1 = 16
6541 00:57:00.452692 DQ Delay:
6542 00:57:00.455902 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6543 00:57:00.458898 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6544 00:57:00.462099 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6545 00:57:00.465318 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6546 00:57:00.465883
6547 00:57:00.466251
6548 00:57:00.466584 ==
6549 00:57:00.468503 Dram Type= 6, Freq= 0, CH_1, rank 0
6550 00:57:00.472047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6551 00:57:00.472507 ==
6552 00:57:00.472941
6553 00:57:00.473290
6554 00:57:00.475572 TX Vref Scan disable
6555 00:57:00.478728 == TX Byte 0 ==
6556 00:57:00.481766 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6557 00:57:00.485458 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6558 00:57:00.488553 == TX Byte 1 ==
6559 00:57:00.492296 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6560 00:57:00.495290 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6561 00:57:00.495756 ==
6562 00:57:00.498144 Dram Type= 6, Freq= 0, CH_1, rank 0
6563 00:57:00.502287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 00:57:00.504661 ==
6565 00:57:00.505271
6566 00:57:00.505636
6567 00:57:00.505976 TX Vref Scan disable
6568 00:57:00.508173 == TX Byte 0 ==
6569 00:57:00.512114 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6570 00:57:00.514679 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6571 00:57:00.518081 == TX Byte 1 ==
6572 00:57:00.521553 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6573 00:57:00.524899 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6574 00:57:00.525369
6575 00:57:00.528062 [DATLAT]
6576 00:57:00.528520 Freq=400, CH1 RK0
6577 00:57:00.529157
6578 00:57:00.530933 DATLAT Default: 0xf
6579 00:57:00.531395 0, 0xFFFF, sum = 0
6580 00:57:00.534494 1, 0xFFFF, sum = 0
6581 00:57:00.534961 2, 0xFFFF, sum = 0
6582 00:57:00.538460 3, 0xFFFF, sum = 0
6583 00:57:00.539052 4, 0xFFFF, sum = 0
6584 00:57:00.541579 5, 0xFFFF, sum = 0
6585 00:57:00.542043 6, 0xFFFF, sum = 0
6586 00:57:00.544055 7, 0xFFFF, sum = 0
6587 00:57:00.544524 8, 0xFFFF, sum = 0
6588 00:57:00.547748 9, 0xFFFF, sum = 0
6589 00:57:00.551403 10, 0xFFFF, sum = 0
6590 00:57:00.551974 11, 0xFFFF, sum = 0
6591 00:57:00.554466 12, 0x0, sum = 1
6592 00:57:00.555037 13, 0x0, sum = 2
6593 00:57:00.555412 14, 0x0, sum = 3
6594 00:57:00.557506 15, 0x0, sum = 4
6595 00:57:00.557972 best_step = 13
6596 00:57:00.558335
6597 00:57:00.561220 ==
6598 00:57:00.564519 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 00:57:00.568271 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6600 00:57:00.568892 ==
6601 00:57:00.569266 RX Vref Scan: 1
6602 00:57:00.569605
6603 00:57:00.571046 RX Vref 0 -> 0, step: 1
6604 00:57:00.571507
6605 00:57:00.574104 RX Delay -359 -> 252, step: 8
6606 00:57:00.574566
6607 00:57:00.577969 Set Vref, RX VrefLevel [Byte0]: 52
6608 00:57:00.580827 [Byte1]: 49
6609 00:57:00.584648
6610 00:57:00.585249 Final RX Vref Byte 0 = 52 to rank0
6611 00:57:00.588207 Final RX Vref Byte 1 = 49 to rank0
6612 00:57:00.590867 Final RX Vref Byte 0 = 52 to rank1
6613 00:57:00.594649 Final RX Vref Byte 1 = 49 to rank1==
6614 00:57:00.598224 Dram Type= 6, Freq= 0, CH_1, rank 0
6615 00:57:00.605175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6616 00:57:00.605744 ==
6617 00:57:00.606108 DQS Delay:
6618 00:57:00.608068 DQS0 = 48, DQS1 = 64
6619 00:57:00.608631 DQM Delay:
6620 00:57:00.609047 DQM0 = 8, DQM1 = 16
6621 00:57:00.611329 DQ Delay:
6622 00:57:00.614435 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6623 00:57:00.614997 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6624 00:57:00.617665 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6625 00:57:00.620985 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6626 00:57:00.621548
6627 00:57:00.621913
6628 00:57:00.630820 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6629 00:57:00.634269 CH1 RK0: MR19=C0C, MR18=CDCD
6630 00:57:00.640494 CH1_RK0: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6631 00:57:00.641088 ==
6632 00:57:00.645696 Dram Type= 6, Freq= 0, CH_1, rank 1
6633 00:57:00.647483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6634 00:57:00.648114 ==
6635 00:57:00.650444 [Gating] SW mode calibration
6636 00:57:00.657304 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6637 00:57:00.660829 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6638 00:57:00.668057 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 00:57:00.670688 0 7 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
6640 00:57:00.674270 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 00:57:00.680913 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6642 00:57:00.684182 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 00:57:00.687209 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 00:57:00.693953 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 00:57:00.697441 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6646 00:57:00.700192 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 00:57:00.703735 Total UI for P1: 0, mck2ui 16
6648 00:57:00.707234 best dqsien dly found for B0: ( 0, 10, 16)
6649 00:57:00.710101 Total UI for P1: 0, mck2ui 16
6650 00:57:00.714143 best dqsien dly found for B1: ( 0, 10, 16)
6651 00:57:00.716841 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6652 00:57:00.723698 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6653 00:57:00.724263
6654 00:57:00.727426 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6655 00:57:00.729765 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6656 00:57:00.733155 [Gating] SW calibration Done
6657 00:57:00.733618 ==
6658 00:57:00.736646 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 00:57:00.740032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6660 00:57:00.740625 ==
6661 00:57:00.743338 RX Vref Scan: 0
6662 00:57:00.743897
6663 00:57:00.744260 RX Vref 0 -> 0, step: 1
6664 00:57:00.744603
6665 00:57:00.746696 RX Delay -410 -> 252, step: 16
6666 00:57:00.753635 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6667 00:57:00.757343 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6668 00:57:00.759569 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6669 00:57:00.763363 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6670 00:57:00.770219 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6671 00:57:00.773240 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6672 00:57:00.776685 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6673 00:57:00.780109 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6674 00:57:00.786467 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6675 00:57:00.790322 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6676 00:57:00.792753 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6677 00:57:00.796093 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6678 00:57:00.802999 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6679 00:57:00.806377 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6680 00:57:00.809990 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6681 00:57:00.812590 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6682 00:57:00.816463 ==
6683 00:57:00.819386 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 00:57:00.823137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6685 00:57:00.823703 ==
6686 00:57:00.824071 DQS Delay:
6687 00:57:00.825719 DQS0 = 35, DQS1 = 59
6688 00:57:00.826224 DQM Delay:
6689 00:57:00.829153 DQM0 = 3, DQM1 = 18
6690 00:57:00.829612 DQ Delay:
6691 00:57:00.832765 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6692 00:57:00.835880 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6693 00:57:00.838995 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6694 00:57:00.842995 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6695 00:57:00.843562
6696 00:57:00.843928
6697 00:57:00.844266 ==
6698 00:57:00.846150 Dram Type= 6, Freq= 0, CH_1, rank 1
6699 00:57:00.848967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6700 00:57:00.849432 ==
6701 00:57:00.849799
6702 00:57:00.850244
6703 00:57:00.852393 TX Vref Scan disable
6704 00:57:00.853025 == TX Byte 0 ==
6705 00:57:00.858984 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6706 00:57:00.862240 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6707 00:57:00.862813 == TX Byte 1 ==
6708 00:57:00.865905 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6709 00:57:00.871978 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6710 00:57:00.872439 ==
6711 00:57:00.875366 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 00:57:00.879026 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6713 00:57:00.879592 ==
6714 00:57:00.879960
6715 00:57:00.880299
6716 00:57:00.881940 TX Vref Scan disable
6717 00:57:00.882399 == TX Byte 0 ==
6718 00:57:00.888789 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6719 00:57:00.892748 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6720 00:57:00.893314 == TX Byte 1 ==
6721 00:57:00.899089 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6722 00:57:00.902574 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6723 00:57:00.903141
6724 00:57:00.903512 [DATLAT]
6725 00:57:00.905605 Freq=400, CH1 RK1
6726 00:57:00.906118
6727 00:57:00.906486 DATLAT Default: 0xd
6728 00:57:00.908797 0, 0xFFFF, sum = 0
6729 00:57:00.909369 1, 0xFFFF, sum = 0
6730 00:57:00.912285 2, 0xFFFF, sum = 0
6731 00:57:00.912781 3, 0xFFFF, sum = 0
6732 00:57:00.915177 4, 0xFFFF, sum = 0
6733 00:57:00.915744 5, 0xFFFF, sum = 0
6734 00:57:00.918538 6, 0xFFFF, sum = 0
6735 00:57:00.919111 7, 0xFFFF, sum = 0
6736 00:57:00.922104 8, 0xFFFF, sum = 0
6737 00:57:00.922674 9, 0xFFFF, sum = 0
6738 00:57:00.925865 10, 0xFFFF, sum = 0
6739 00:57:00.926434 11, 0xFFFF, sum = 0
6740 00:57:00.928637 12, 0x0, sum = 1
6741 00:57:00.929138 13, 0x0, sum = 2
6742 00:57:00.931834 14, 0x0, sum = 3
6743 00:57:00.932303 15, 0x0, sum = 4
6744 00:57:00.935398 best_step = 13
6745 00:57:00.935961
6746 00:57:00.936329 ==
6747 00:57:00.938631 Dram Type= 6, Freq= 0, CH_1, rank 1
6748 00:57:00.941990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6749 00:57:00.942458 ==
6750 00:57:00.945433 RX Vref Scan: 0
6751 00:57:00.945894
6752 00:57:00.946256 RX Vref 0 -> 0, step: 1
6753 00:57:00.946593
6754 00:57:00.948893 RX Delay -359 -> 252, step: 8
6755 00:57:00.956763 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6756 00:57:00.959865 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6757 00:57:00.963395 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6758 00:57:00.966916 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6759 00:57:00.973864 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6760 00:57:00.976836 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6761 00:57:00.980385 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6762 00:57:00.986563 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6763 00:57:00.989861 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6764 00:57:00.993035 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6765 00:57:00.996401 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6766 00:57:01.003267 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6767 00:57:01.007407 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6768 00:57:01.009328 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6769 00:57:01.012540 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6770 00:57:01.019314 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6771 00:57:01.019878 ==
6772 00:57:01.022809 Dram Type= 6, Freq= 0, CH_1, rank 1
6773 00:57:01.026145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6774 00:57:01.026718 ==
6775 00:57:01.027092 DQS Delay:
6776 00:57:01.029960 DQS0 = 48, DQS1 = 64
6777 00:57:01.030575 DQM Delay:
6778 00:57:01.032561 DQM0 = 10, DQM1 = 15
6779 00:57:01.033050 DQ Delay:
6780 00:57:01.036270 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6781 00:57:01.039527 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6782 00:57:01.042682 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6783 00:57:01.045506 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6784 00:57:01.046019
6785 00:57:01.046385
6786 00:57:01.052894 [DQSOSCAuto] RK1, (LSB)MR18= 0xb9b9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6787 00:57:01.055943 CH1 RK1: MR19=C0C, MR18=B9B9
6788 00:57:01.062755 CH1_RK1: MR19=0xC0C, MR18=0xB9B9, DQSOSC=386, MR23=63, INC=396, DEC=264
6789 00:57:01.066008 [RxdqsGatingPostProcess] freq 400
6790 00:57:01.072268 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6791 00:57:01.075538 Pre-setting of DQS Precalculation
6792 00:57:01.079310 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6793 00:57:01.085735 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6794 00:57:01.092440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6795 00:57:01.093041
6796 00:57:01.096075
6797 00:57:01.096656 [Calibration Summary] 800 Mbps
6798 00:57:01.099419 CH 0, Rank 0
6799 00:57:01.099982 SW Impedance : PASS
6800 00:57:01.102449 DUTY Scan : NO K
6801 00:57:01.105196 ZQ Calibration : PASS
6802 00:57:01.105652 Jitter Meter : NO K
6803 00:57:01.108563 CBT Training : PASS
6804 00:57:01.112545 Write leveling : PASS
6805 00:57:01.113272 RX DQS gating : PASS
6806 00:57:01.115867 RX DQ/DQS(RDDQC) : PASS
6807 00:57:01.118880 TX DQ/DQS : PASS
6808 00:57:01.119444 RX DATLAT : PASS
6809 00:57:01.122401 RX DQ/DQS(Engine): PASS
6810 00:57:01.125459 TX OE : NO K
6811 00:57:01.126024 All Pass.
6812 00:57:01.126391
6813 00:57:01.126730 CH 0, Rank 1
6814 00:57:01.128662 SW Impedance : PASS
6815 00:57:01.131742 DUTY Scan : NO K
6816 00:57:01.132200 ZQ Calibration : PASS
6817 00:57:01.135269 Jitter Meter : NO K
6818 00:57:01.138181 CBT Training : PASS
6819 00:57:01.138643 Write leveling : NO K
6820 00:57:01.141713 RX DQS gating : PASS
6821 00:57:01.142277 RX DQ/DQS(RDDQC) : PASS
6822 00:57:01.145406 TX DQ/DQS : PASS
6823 00:57:01.149057 RX DATLAT : PASS
6824 00:57:01.149518 RX DQ/DQS(Engine): PASS
6825 00:57:01.151461 TX OE : NO K
6826 00:57:01.151920 All Pass.
6827 00:57:01.152283
6828 00:57:01.154840 CH 1, Rank 0
6829 00:57:01.155350 SW Impedance : PASS
6830 00:57:01.158351 DUTY Scan : NO K
6831 00:57:01.161541 ZQ Calibration : PASS
6832 00:57:01.162001 Jitter Meter : NO K
6833 00:57:01.164761 CBT Training : PASS
6834 00:57:01.168517 Write leveling : PASS
6835 00:57:01.169027 RX DQS gating : PASS
6836 00:57:01.171652 RX DQ/DQS(RDDQC) : PASS
6837 00:57:01.174678 TX DQ/DQS : PASS
6838 00:57:01.175142 RX DATLAT : PASS
6839 00:57:01.178368 RX DQ/DQS(Engine): PASS
6840 00:57:01.181736 TX OE : NO K
6841 00:57:01.182301 All Pass.
6842 00:57:01.182668
6843 00:57:01.183008 CH 1, Rank 1
6844 00:57:01.184501 SW Impedance : PASS
6845 00:57:01.187664 DUTY Scan : NO K
6846 00:57:01.188123 ZQ Calibration : PASS
6847 00:57:01.190990 Jitter Meter : NO K
6848 00:57:01.194269 CBT Training : PASS
6849 00:57:01.194732 Write leveling : NO K
6850 00:57:01.198520 RX DQS gating : PASS
6851 00:57:01.201274 RX DQ/DQS(RDDQC) : PASS
6852 00:57:01.201733 TX DQ/DQS : PASS
6853 00:57:01.205000 RX DATLAT : PASS
6854 00:57:01.205560 RX DQ/DQS(Engine): PASS
6855 00:57:01.208442 TX OE : NO K
6856 00:57:01.209059 All Pass.
6857 00:57:01.209429
6858 00:57:01.211120 DramC Write-DBI off
6859 00:57:01.214430 PER_BANK_REFRESH: Hybrid Mode
6860 00:57:01.214893 TX_TRACKING: ON
6861 00:57:01.224500 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6862 00:57:01.228266 [FAST_K] Save calibration result to emmc
6863 00:57:01.230687 dramc_set_vcore_voltage set vcore to 725000
6864 00:57:01.234684 Read voltage for 1600, 0
6865 00:57:01.235250 Vio18 = 0
6866 00:57:01.238151 Vcore = 725000
6867 00:57:01.238611 Vdram = 0
6868 00:57:01.238976 Vddq = 0
6869 00:57:01.239313 Vmddr = 0
6870 00:57:01.244304 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6871 00:57:01.251571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6872 00:57:01.252121 MEM_TYPE=3, freq_sel=13
6873 00:57:01.254329 sv_algorithm_assistance_LP4_3733
6874 00:57:01.257443 ============ PULL DRAM RESETB DOWN ============
6875 00:57:01.264401 ========== PULL DRAM RESETB DOWN end =========
6876 00:57:01.267455 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6877 00:57:01.270435 ===================================
6878 00:57:01.273899 LPDDR4 DRAM CONFIGURATION
6879 00:57:01.276853 ===================================
6880 00:57:01.277438 EX_ROW_EN[0] = 0x0
6881 00:57:01.280487 EX_ROW_EN[1] = 0x0
6882 00:57:01.284452 LP4Y_EN = 0x0
6883 00:57:01.285096 WORK_FSP = 0x1
6884 00:57:01.287468 WL = 0x5
6885 00:57:01.288026 RL = 0x5
6886 00:57:01.290161 BL = 0x2
6887 00:57:01.290618 RPST = 0x0
6888 00:57:01.293424 RD_PRE = 0x0
6889 00:57:01.293886 WR_PRE = 0x1
6890 00:57:01.297912 WR_PST = 0x1
6891 00:57:01.298472 DBI_WR = 0x0
6892 00:57:01.301070 DBI_RD = 0x0
6893 00:57:01.301526 OTF = 0x1
6894 00:57:01.303309 ===================================
6895 00:57:01.307038 ===================================
6896 00:57:01.310164 ANA top config
6897 00:57:01.313322 ===================================
6898 00:57:01.313788 DLL_ASYNC_EN = 0
6899 00:57:01.316656 ALL_SLAVE_EN = 0
6900 00:57:01.320057 NEW_RANK_MODE = 1
6901 00:57:01.323673 DLL_IDLE_MODE = 1
6902 00:57:01.326962 LP45_APHY_COMB_EN = 1
6903 00:57:01.327522 TX_ODT_DIS = 0
6904 00:57:01.329793 NEW_8X_MODE = 1
6905 00:57:01.333227 ===================================
6906 00:57:01.337055 ===================================
6907 00:57:01.340141 data_rate = 3200
6908 00:57:01.343492 CKR = 1
6909 00:57:01.347015 DQ_P2S_RATIO = 8
6910 00:57:01.349589 ===================================
6911 00:57:01.352860 CA_P2S_RATIO = 8
6912 00:57:01.353322 DQ_CA_OPEN = 0
6913 00:57:01.356967 DQ_SEMI_OPEN = 0
6914 00:57:01.360066 CA_SEMI_OPEN = 0
6915 00:57:01.362970 CA_FULL_RATE = 0
6916 00:57:01.366070 DQ_CKDIV4_EN = 0
6917 00:57:01.369641 CA_CKDIV4_EN = 0
6918 00:57:01.370201 CA_PREDIV_EN = 0
6919 00:57:01.373029 PH8_DLY = 12
6920 00:57:01.376275 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6921 00:57:01.379664 DQ_AAMCK_DIV = 4
6922 00:57:01.382989 CA_AAMCK_DIV = 4
6923 00:57:01.385754 CA_ADMCK_DIV = 4
6924 00:57:01.386214 DQ_TRACK_CA_EN = 0
6925 00:57:01.389412 CA_PICK = 1600
6926 00:57:01.392769 CA_MCKIO = 1600
6927 00:57:01.396176 MCKIO_SEMI = 0
6928 00:57:01.399488 PLL_FREQ = 3068
6929 00:57:01.402753 DQ_UI_PI_RATIO = 32
6930 00:57:01.406006 CA_UI_PI_RATIO = 0
6931 00:57:01.410410 ===================================
6932 00:57:01.413230 ===================================
6933 00:57:01.413780 memory_type:LPDDR4
6934 00:57:01.415757 GP_NUM : 10
6935 00:57:01.419437 SRAM_EN : 1
6936 00:57:01.419982 MD32_EN : 0
6937 00:57:01.422770 ===================================
6938 00:57:01.425381 [ANA_INIT] >>>>>>>>>>>>>>
6939 00:57:01.429099 <<<<<< [CONFIGURE PHASE]: ANA_TX
6940 00:57:01.432561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6941 00:57:01.436029 ===================================
6942 00:57:01.439090 data_rate = 3200,PCW = 0X7600
6943 00:57:01.442644 ===================================
6944 00:57:01.446481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6945 00:57:01.448645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6946 00:57:01.456102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6947 00:57:01.459840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6948 00:57:01.462003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6949 00:57:01.469235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6950 00:57:01.469789 [ANA_INIT] flow start
6951 00:57:01.471868 [ANA_INIT] PLL >>>>>>>>
6952 00:57:01.475291 [ANA_INIT] PLL <<<<<<<<
6953 00:57:01.475744 [ANA_INIT] MIDPI >>>>>>>>
6954 00:57:01.479156 [ANA_INIT] MIDPI <<<<<<<<
6955 00:57:01.482210 [ANA_INIT] DLL >>>>>>>>
6956 00:57:01.482763 [ANA_INIT] DLL <<<<<<<<
6957 00:57:01.485657 [ANA_INIT] flow end
6958 00:57:01.488471 ============ LP4 DIFF to SE enter ============
6959 00:57:01.492006 ============ LP4 DIFF to SE exit ============
6960 00:57:01.495496 [ANA_INIT] <<<<<<<<<<<<<
6961 00:57:01.498480 [Flow] Enable top DCM control >>>>>
6962 00:57:01.501640 [Flow] Enable top DCM control <<<<<
6963 00:57:01.505251 Enable DLL master slave shuffle
6964 00:57:01.511619 ==============================================================
6965 00:57:01.512159 Gating Mode config
6966 00:57:01.518442 ==============================================================
6967 00:57:01.519000 Config description:
6968 00:57:01.528898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6969 00:57:01.534945 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6970 00:57:01.541480 SELPH_MODE 0: By rank 1: By Phase
6971 00:57:01.544982 ==============================================================
6972 00:57:01.548251 GAT_TRACK_EN = 1
6973 00:57:01.551756 RX_GATING_MODE = 2
6974 00:57:01.555347 RX_GATING_TRACK_MODE = 2
6975 00:57:01.558974 SELPH_MODE = 1
6976 00:57:01.561373 PICG_EARLY_EN = 1
6977 00:57:01.564781 VALID_LAT_VALUE = 1
6978 00:57:01.571338 ==============================================================
6979 00:57:01.574850 Enter into Gating configuration >>>>
6980 00:57:01.578463 Exit from Gating configuration <<<<
6981 00:57:01.581655 Enter into DVFS_PRE_config >>>>>
6982 00:57:01.592133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6983 00:57:01.595385 Exit from DVFS_PRE_config <<<<<
6984 00:57:01.598360 Enter into PICG configuration >>>>
6985 00:57:01.601445 Exit from PICG configuration <<<<
6986 00:57:01.605450 [RX_INPUT] configuration >>>>>
6987 00:57:01.606000 [RX_INPUT] configuration <<<<<
6988 00:57:01.611237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6989 00:57:01.617674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6990 00:57:01.624295 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6991 00:57:01.627303 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6992 00:57:01.633983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6993 00:57:01.640268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6994 00:57:01.644208 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6995 00:57:01.647957 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6996 00:57:01.654587 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6997 00:57:01.657205 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6998 00:57:01.660620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6999 00:57:01.666741 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7000 00:57:01.670522 ===================================
7001 00:57:01.670981 LPDDR4 DRAM CONFIGURATION
7002 00:57:01.673887 ===================================
7003 00:57:01.677173 EX_ROW_EN[0] = 0x0
7004 00:57:01.680818 EX_ROW_EN[1] = 0x0
7005 00:57:01.681371 LP4Y_EN = 0x0
7006 00:57:01.684112 WORK_FSP = 0x1
7007 00:57:01.684669 WL = 0x5
7008 00:57:01.686864 RL = 0x5
7009 00:57:01.687423 BL = 0x2
7010 00:57:01.690681 RPST = 0x0
7011 00:57:01.691237 RD_PRE = 0x0
7012 00:57:01.693582 WR_PRE = 0x1
7013 00:57:01.694036 WR_PST = 0x1
7014 00:57:01.696837 DBI_WR = 0x0
7015 00:57:01.697387 DBI_RD = 0x0
7016 00:57:01.700260 OTF = 0x1
7017 00:57:01.703905 ===================================
7018 00:57:01.707760 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7019 00:57:01.709892 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7020 00:57:01.717431 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7021 00:57:01.720182 ===================================
7022 00:57:01.720639 LPDDR4 DRAM CONFIGURATION
7023 00:57:01.723239 ===================================
7024 00:57:01.726309 EX_ROW_EN[0] = 0x10
7025 00:57:01.729963 EX_ROW_EN[1] = 0x0
7026 00:57:01.730514 LP4Y_EN = 0x0
7027 00:57:01.732928 WORK_FSP = 0x1
7028 00:57:01.733472 WL = 0x5
7029 00:57:01.737404 RL = 0x5
7030 00:57:01.737995 BL = 0x2
7031 00:57:01.740047 RPST = 0x0
7032 00:57:01.740513 RD_PRE = 0x0
7033 00:57:01.742792 WR_PRE = 0x1
7034 00:57:01.743256 WR_PST = 0x1
7035 00:57:01.745992 DBI_WR = 0x0
7036 00:57:01.746526 DBI_RD = 0x0
7037 00:57:01.749917 OTF = 0x1
7038 00:57:01.753552 ===================================
7039 00:57:01.759540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7040 00:57:01.760095 ==
7041 00:57:01.762805 Dram Type= 6, Freq= 0, CH_0, rank 0
7042 00:57:01.766249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7043 00:57:01.766850 ==
7044 00:57:01.769569 [Duty_Offset_Calibration]
7045 00:57:01.770059 B0:0 B1:2 CA:1
7046 00:57:01.770532
7047 00:57:01.772527 [DutyScan_Calibration_Flow] k_type=0
7048 00:57:01.784168
7049 00:57:01.784818 ==CLK 0==
7050 00:57:01.786727 Final CLK duty delay cell = 0
7051 00:57:01.790014 [0] MAX Duty = 5187%(X100), DQS PI = 24
7052 00:57:01.793369 [0] MIN Duty = 4938%(X100), DQS PI = 54
7053 00:57:01.796929 [0] AVG Duty = 5062%(X100)
7054 00:57:01.797401
7055 00:57:01.800020 CH0 CLK Duty spec in!! Max-Min= 249%
7056 00:57:01.802834 [DutyScan_Calibration_Flow] ====Done====
7057 00:57:01.803306
7058 00:57:01.806702 [DutyScan_Calibration_Flow] k_type=1
7059 00:57:01.824391
7060 00:57:01.825003 ==DQS 0 ==
7061 00:57:01.826780 Final DQS duty delay cell = 0
7062 00:57:01.830331 [0] MAX Duty = 5125%(X100), DQS PI = 22
7063 00:57:01.833495 [0] MIN Duty = 5031%(X100), DQS PI = 8
7064 00:57:01.836640 [0] AVG Duty = 5078%(X100)
7065 00:57:01.837187
7066 00:57:01.837660 ==DQS 1 ==
7067 00:57:01.840136 Final DQS duty delay cell = 0
7068 00:57:01.843517 [0] MAX Duty = 5031%(X100), DQS PI = 2
7069 00:57:01.846968 [0] MIN Duty = 4876%(X100), DQS PI = 18
7070 00:57:01.847435 [0] AVG Duty = 4953%(X100)
7071 00:57:01.850712
7072 00:57:01.853232 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7073 00:57:01.853699
7074 00:57:01.856506 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7075 00:57:01.859666 [DutyScan_Calibration_Flow] ====Done====
7076 00:57:01.860231
7077 00:57:01.863215 [DutyScan_Calibration_Flow] k_type=3
7078 00:57:01.881072
7079 00:57:01.881639 ==DQM 0 ==
7080 00:57:01.883961 Final DQM duty delay cell = 0
7081 00:57:01.887233 [0] MAX Duty = 5187%(X100), DQS PI = 22
7082 00:57:01.890856 [0] MIN Duty = 4907%(X100), DQS PI = 56
7083 00:57:01.893941 [0] AVG Duty = 5047%(X100)
7084 00:57:01.894509
7085 00:57:01.895099 ==DQM 1 ==
7086 00:57:01.896684 Final DQM duty delay cell = 0
7087 00:57:01.900790 [0] MAX Duty = 5062%(X100), DQS PI = 52
7088 00:57:01.903352 [0] MIN Duty = 4782%(X100), DQS PI = 14
7089 00:57:01.907496 [0] AVG Duty = 4922%(X100)
7090 00:57:01.908062
7091 00:57:01.910708 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7092 00:57:01.911277
7093 00:57:01.913253 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7094 00:57:01.917611 [DutyScan_Calibration_Flow] ====Done====
7095 00:57:01.918181
7096 00:57:01.919728 [DutyScan_Calibration_Flow] k_type=2
7097 00:57:01.936804
7098 00:57:01.937400 ==DQ 0 ==
7099 00:57:01.940418 Final DQ duty delay cell = 0
7100 00:57:01.944037 [0] MAX Duty = 5218%(X100), DQS PI = 18
7101 00:57:01.947399 [0] MIN Duty = 4938%(X100), DQS PI = 56
7102 00:57:01.947966 [0] AVG Duty = 5078%(X100)
7103 00:57:01.950789
7104 00:57:01.951339 ==DQ 1 ==
7105 00:57:01.953424 Final DQ duty delay cell = -4
7106 00:57:01.956964 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7107 00:57:01.960537 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7108 00:57:01.964520 [-4] AVG Duty = 4953%(X100)
7109 00:57:01.965121
7110 00:57:01.966624 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7111 00:57:01.967079
7112 00:57:01.970883 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7113 00:57:01.973493 [DutyScan_Calibration_Flow] ====Done====
7114 00:57:01.973960 ==
7115 00:57:01.976198 Dram Type= 6, Freq= 0, CH_1, rank 0
7116 00:57:01.979779 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7117 00:57:01.980243 ==
7118 00:57:01.983065 [Duty_Offset_Calibration]
7119 00:57:01.983524 B0:0 B1:4 CA:-5
7120 00:57:01.983892
7121 00:57:01.986382 [DutyScan_Calibration_Flow] k_type=0
7122 00:57:01.997681
7123 00:57:01.998232 ==CLK 0==
7124 00:57:02.000828 Final CLK duty delay cell = 0
7125 00:57:02.004693 [0] MAX Duty = 5156%(X100), DQS PI = 22
7126 00:57:02.007742 [0] MIN Duty = 4906%(X100), DQS PI = 50
7127 00:57:02.010673 [0] AVG Duty = 5031%(X100)
7128 00:57:02.011157
7129 00:57:02.013932 CH1 CLK Duty spec in!! Max-Min= 250%
7130 00:57:02.017576 [DutyScan_Calibration_Flow] ====Done====
7131 00:57:02.018131
7132 00:57:02.021207 [DutyScan_Calibration_Flow] k_type=1
7133 00:57:02.036539
7134 00:57:02.037161 ==DQS 0 ==
7135 00:57:02.039882 Final DQS duty delay cell = 0
7136 00:57:02.043689 [0] MAX Duty = 5187%(X100), DQS PI = 20
7137 00:57:02.046565 [0] MIN Duty = 4876%(X100), DQS PI = 42
7138 00:57:02.049737 [0] AVG Duty = 5031%(X100)
7139 00:57:02.050295
7140 00:57:02.050659 ==DQS 1 ==
7141 00:57:02.052533 Final DQS duty delay cell = -4
7142 00:57:02.056334 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7143 00:57:02.059558 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7144 00:57:02.062771 [-4] AVG Duty = 4922%(X100)
7145 00:57:02.063231
7146 00:57:02.066592 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7147 00:57:02.067145
7148 00:57:02.069673 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7149 00:57:02.073507 [DutyScan_Calibration_Flow] ====Done====
7150 00:57:02.074118
7151 00:57:02.076006 [DutyScan_Calibration_Flow] k_type=3
7152 00:57:02.092859
7153 00:57:02.093408 ==DQM 0 ==
7154 00:57:02.095565 Final DQM duty delay cell = -4
7155 00:57:02.098864 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7156 00:57:02.102405 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7157 00:57:02.105658 [-4] AVG Duty = 4922%(X100)
7158 00:57:02.106221
7159 00:57:02.106708 ==DQM 1 ==
7160 00:57:02.108294 Final DQM duty delay cell = -4
7161 00:57:02.111953 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7162 00:57:02.115618 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7163 00:57:02.119175 [-4] AVG Duty = 5000%(X100)
7164 00:57:02.119738
7165 00:57:02.121780 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7166 00:57:02.122250
7167 00:57:02.125532 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7168 00:57:02.128075 [DutyScan_Calibration_Flow] ====Done====
7169 00:57:02.128545
7170 00:57:02.131907 [DutyScan_Calibration_Flow] k_type=2
7171 00:57:02.149887
7172 00:57:02.150432 ==DQ 0 ==
7173 00:57:02.152612 Final DQ duty delay cell = 0
7174 00:57:02.156607 [0] MAX Duty = 5093%(X100), DQS PI = 2
7175 00:57:02.159862 [0] MIN Duty = 4969%(X100), DQS PI = 46
7176 00:57:02.160430 [0] AVG Duty = 5031%(X100)
7177 00:57:02.163395
7178 00:57:02.163900 ==DQ 1 ==
7179 00:57:02.166637 Final DQ duty delay cell = 0
7180 00:57:02.169608 [0] MAX Duty = 5031%(X100), DQS PI = 4
7181 00:57:02.172958 [0] MIN Duty = 4876%(X100), DQS PI = 28
7182 00:57:02.173430 [0] AVG Duty = 4953%(X100)
7183 00:57:02.174089
7184 00:57:02.179373 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7185 00:57:02.179946
7186 00:57:02.183341 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7187 00:57:02.186002 [DutyScan_Calibration_Flow] ====Done====
7188 00:57:02.189881 nWR fixed to 30
7189 00:57:02.190451 [ModeRegInit_LP4] CH0 RK0
7190 00:57:02.192968 [ModeRegInit_LP4] CH0 RK1
7191 00:57:02.195735 [ModeRegInit_LP4] CH1 RK0
7192 00:57:02.199221 [ModeRegInit_LP4] CH1 RK1
7193 00:57:02.199786 match AC timing 4
7194 00:57:02.203542 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7195 00:57:02.209175 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7196 00:57:02.212544 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7197 00:57:02.219556 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7198 00:57:02.222608 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7199 00:57:02.223082 [MiockJmeterHQA]
7200 00:57:02.223559
7201 00:57:02.225955 [DramcMiockJmeter] u1RxGatingPI = 0
7202 00:57:02.229007 0 : 4252, 4027
7203 00:57:02.229488 4 : 4253, 4027
7204 00:57:02.232607 8 : 4252, 4027
7205 00:57:02.233207 12 : 4252, 4027
7206 00:57:02.233697 16 : 4253, 4026
7207 00:57:02.235731 20 : 4252, 4027
7208 00:57:02.236205 24 : 4362, 4137
7209 00:57:02.238699 28 : 4363, 4137
7210 00:57:02.239175 32 : 4252, 4027
7211 00:57:02.242083 36 : 4253, 4027
7212 00:57:02.242557 40 : 4252, 4027
7213 00:57:02.245344 44 : 4363, 4137
7214 00:57:02.245820 48 : 4252, 4027
7215 00:57:02.246302 52 : 4364, 4137
7216 00:57:02.248433 56 : 4252, 4027
7217 00:57:02.248945 60 : 4253, 4027
7218 00:57:02.252035 64 : 4253, 4026
7219 00:57:02.252514 68 : 4255, 4029
7220 00:57:02.255065 72 : 4361, 4137
7221 00:57:02.255541 76 : 4250, 4026
7222 00:57:02.258887 80 : 4360, 4138
7223 00:57:02.259360 84 : 4250, 4027
7224 00:57:02.259943 88 : 4250, 4026
7225 00:57:02.262418 92 : 4250, 4027
7226 00:57:02.262897 96 : 4360, 4137
7227 00:57:02.265393 100 : 4250, 2203
7228 00:57:02.265871 104 : 4250, 0
7229 00:57:02.268824 108 : 4252, 0
7230 00:57:02.269300 112 : 4363, 0
7231 00:57:02.269779 116 : 4253, 0
7232 00:57:02.272228 120 : 4250, 0
7233 00:57:02.272701 124 : 4250, 0
7234 00:57:02.275441 128 : 4361, 0
7235 00:57:02.275917 132 : 4360, 0
7236 00:57:02.276400 136 : 4248, 0
7237 00:57:02.278595 140 : 4360, 0
7238 00:57:02.279072 144 : 4250, 0
7239 00:57:02.279560 148 : 4250, 0
7240 00:57:02.282569 152 : 4250, 0
7241 00:57:02.283143 156 : 4253, 0
7242 00:57:02.285597 160 : 4250, 0
7243 00:57:02.286391 164 : 4360, 0
7244 00:57:02.286915 168 : 4250, 0
7245 00:57:02.288191 172 : 4250, 0
7246 00:57:02.288652 176 : 4249, 0
7247 00:57:02.291775 180 : 4250, 0
7248 00:57:02.292207 184 : 4363, 0
7249 00:57:02.292485 188 : 4250, 0
7250 00:57:02.295157 192 : 4360, 0
7251 00:57:02.295479 196 : 4250, 0
7252 00:57:02.299205 200 : 4250, 0
7253 00:57:02.299625 204 : 4249, 0
7254 00:57:02.299890 208 : 4250, 0
7255 00:57:02.301247 212 : 4253, 0
7256 00:57:02.301571 216 : 4250, 0
7257 00:57:02.304961 220 : 4250, 477
7258 00:57:02.305383 224 : 4250, 3891
7259 00:57:02.305647 228 : 4250, 4026
7260 00:57:02.308203 232 : 4250, 4027
7261 00:57:02.308625 236 : 4360, 4138
7262 00:57:02.311765 240 : 4360, 4137
7263 00:57:02.312190 244 : 4250, 4026
7264 00:57:02.314824 248 : 4363, 4140
7265 00:57:02.315240 252 : 4250, 4027
7266 00:57:02.318455 256 : 4250, 4027
7267 00:57:02.318822 260 : 4250, 4026
7268 00:57:02.321285 264 : 4253, 4029
7269 00:57:02.321707 268 : 4250, 4027
7270 00:57:02.324806 272 : 4250, 4027
7271 00:57:02.325224 276 : 4250, 4026
7272 00:57:02.328475 280 : 4253, 4029
7273 00:57:02.328941 284 : 4250, 4027
7274 00:57:02.331433 288 : 4361, 4138
7275 00:57:02.331854 292 : 4360, 4137
7276 00:57:02.332125 296 : 4250, 4026
7277 00:57:02.334839 300 : 4363, 4140
7278 00:57:02.335260 304 : 4250, 4027
7279 00:57:02.338156 308 : 4250, 4027
7280 00:57:02.338563 312 : 4250, 4026
7281 00:57:02.340984 316 : 4253, 4029
7282 00:57:02.341307 320 : 4250, 4027
7283 00:57:02.344432 324 : 4250, 4027
7284 00:57:02.344789 328 : 4250, 4026
7285 00:57:02.348211 332 : 4253, 4029
7286 00:57:02.348795 336 : 4250, 3912
7287 00:57:02.351279 340 : 4361, 2029
7288 00:57:02.351698
7289 00:57:02.351958 MIOCK jitter meter ch=0
7290 00:57:02.352196
7291 00:57:02.354502 1T = (340-104) = 236 dly cells
7292 00:57:02.361324 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7293 00:57:02.361736 ==
7294 00:57:02.364564 Dram Type= 6, Freq= 0, CH_0, rank 0
7295 00:57:02.367723 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7296 00:57:02.368044 ==
7297 00:57:02.374474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7298 00:57:02.377492 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7299 00:57:02.384321 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7300 00:57:02.387539 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7301 00:57:02.397194 [CA 0] Center 42 (12~73) winsize 62
7302 00:57:02.400481 [CA 1] Center 42 (12~73) winsize 62
7303 00:57:02.403956 [CA 2] Center 39 (9~69) winsize 61
7304 00:57:02.407149 [CA 3] Center 38 (9~68) winsize 60
7305 00:57:02.409977 [CA 4] Center 37 (7~67) winsize 61
7306 00:57:02.413547 [CA 5] Center 36 (6~66) winsize 61
7307 00:57:02.414100
7308 00:57:02.416663 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7309 00:57:02.417267
7310 00:57:02.419973 [CATrainingPosCal] consider 1 rank data
7311 00:57:02.423614 u2DelayCellTimex100 = 275/100 ps
7312 00:57:02.430252 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7313 00:57:02.433284 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7314 00:57:02.437103 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7315 00:57:02.439783 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7316 00:57:02.443517 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7317 00:57:02.447319 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7318 00:57:02.447779
7319 00:57:02.450315 CA PerBit enable=1, Macro0, CA PI delay=36
7320 00:57:02.450919
7321 00:57:02.453243 [CBTSetCACLKResult] CA Dly = 36
7322 00:57:02.456391 CS Dly: 10 (0~41)
7323 00:57:02.459938 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7324 00:57:02.463036 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7325 00:57:02.463510 ==
7326 00:57:02.466542 Dram Type= 6, Freq= 0, CH_0, rank 1
7327 00:57:02.470141 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7328 00:57:02.473356 ==
7329 00:57:02.476628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7330 00:57:02.480100 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7331 00:57:02.486000 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7332 00:57:02.493153 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7333 00:57:02.499479 [CA 0] Center 42 (12~73) winsize 62
7334 00:57:02.502984 [CA 1] Center 42 (12~73) winsize 62
7335 00:57:02.506942 [CA 2] Center 38 (9~68) winsize 60
7336 00:57:02.509685 [CA 3] Center 38 (9~67) winsize 59
7337 00:57:02.512870 [CA 4] Center 36 (6~66) winsize 61
7338 00:57:02.516812 [CA 5] Center 36 (6~66) winsize 61
7339 00:57:02.517378
7340 00:57:02.519786 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7341 00:57:02.520354
7342 00:57:02.523073 [CATrainingPosCal] consider 2 rank data
7343 00:57:02.525959 u2DelayCellTimex100 = 275/100 ps
7344 00:57:02.529580 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7345 00:57:02.536123 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7346 00:57:02.539236 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7347 00:57:02.542217 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7348 00:57:02.545801 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7349 00:57:02.549177 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7350 00:57:02.549744
7351 00:57:02.553178 CA PerBit enable=1, Macro0, CA PI delay=36
7352 00:57:02.553746
7353 00:57:02.555519 [CBTSetCACLKResult] CA Dly = 36
7354 00:57:02.559519 CS Dly: 10 (0~42)
7355 00:57:02.562581 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7356 00:57:02.566056 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7357 00:57:02.566621
7358 00:57:02.569495 ----->DramcWriteLeveling(PI) begin...
7359 00:57:02.569972 ==
7360 00:57:02.571953 Dram Type= 6, Freq= 0, CH_0, rank 0
7361 00:57:02.578786 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7362 00:57:02.579371 ==
7363 00:57:02.582101 Write leveling (Byte 0): 29 => 29
7364 00:57:02.585216 Write leveling (Byte 1): 25 => 25
7365 00:57:02.585529 DramcWriteLeveling(PI) end<-----
7366 00:57:02.585774
7367 00:57:02.588316 ==
7368 00:57:02.591998 Dram Type= 6, Freq= 0, CH_0, rank 0
7369 00:57:02.596317 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7370 00:57:02.596590 ==
7371 00:57:02.598749 [Gating] SW mode calibration
7372 00:57:02.604890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7373 00:57:02.609069 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7374 00:57:02.615014 0 12 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7375 00:57:02.618644 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7376 00:57:02.621999 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 00:57:02.628853 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7378 00:57:02.632187 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7379 00:57:02.635611 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7380 00:57:02.641821 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7381 00:57:02.644775 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7382 00:57:02.648358 0 13 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
7383 00:57:02.654747 0 13 4 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
7384 00:57:02.658413 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 00:57:02.661405 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7386 00:57:02.668547 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7387 00:57:02.671679 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7388 00:57:02.674950 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7389 00:57:02.681017 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7390 00:57:02.685107 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
7391 00:57:02.688567 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7392 00:57:02.694493 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7393 00:57:02.697962 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7394 00:57:02.701267 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7395 00:57:02.707962 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7396 00:57:02.711575 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7397 00:57:02.714496 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 00:57:02.721043 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7399 00:57:02.724426 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7400 00:57:02.727691 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7401 00:57:02.734479 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 00:57:02.737626 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 00:57:02.741159 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 00:57:02.748078 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 00:57:02.751387 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 00:57:02.754272 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 00:57:02.761051 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 00:57:02.763669 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 00:57:02.767131 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 00:57:02.774492 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 00:57:02.777312 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 00:57:02.781363 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 00:57:02.787724 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7414 00:57:02.790943 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7415 00:57:02.794225 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7416 00:57:02.797249 Total UI for P1: 0, mck2ui 16
7417 00:57:02.800681 best dqsien dly found for B0: ( 1, 0, 30)
7418 00:57:02.804594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7419 00:57:02.807410 Total UI for P1: 0, mck2ui 16
7420 00:57:02.810672 best dqsien dly found for B1: ( 1, 1, 4)
7421 00:57:02.817257 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7422 00:57:02.820658 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7423 00:57:02.821446
7424 00:57:02.823421 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7425 00:57:02.826786 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7426 00:57:02.830715 [Gating] SW calibration Done
7427 00:57:02.831262 ==
7428 00:57:02.833549 Dram Type= 6, Freq= 0, CH_0, rank 0
7429 00:57:02.836882 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7430 00:57:02.837453 ==
7431 00:57:02.840305 RX Vref Scan: 0
7432 00:57:02.840823
7433 00:57:02.841193 RX Vref 0 -> 0, step: 1
7434 00:57:02.841524
7435 00:57:02.843833 RX Delay 0 -> 252, step: 8
7436 00:57:02.846719 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7437 00:57:02.850477 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7438 00:57:02.856474 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7439 00:57:02.859987 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7440 00:57:02.863925 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7441 00:57:02.866560 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7442 00:57:02.870252 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7443 00:57:02.876154 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7444 00:57:02.880068 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7445 00:57:02.883836 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7446 00:57:02.886584 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7447 00:57:02.893019 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7448 00:57:02.896302 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7449 00:57:02.900001 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7450 00:57:02.902896 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7451 00:57:02.906528 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7452 00:57:02.910104 ==
7453 00:57:02.910658 Dram Type= 6, Freq= 0, CH_0, rank 0
7454 00:57:02.916434 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7455 00:57:02.917049 ==
7456 00:57:02.917415 DQS Delay:
7457 00:57:02.919637 DQS0 = 0, DQS1 = 0
7458 00:57:02.920191 DQM Delay:
7459 00:57:02.922413 DQM0 = 131, DQM1 = 125
7460 00:57:02.922970 DQ Delay:
7461 00:57:02.926518 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7462 00:57:02.929317 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7463 00:57:02.932750 DQ8 =115, DQ9 =107, DQ10 =127, DQ11 =115
7464 00:57:02.935980 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7465 00:57:02.936433
7466 00:57:02.936837
7467 00:57:02.937180 ==
7468 00:57:02.939187 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 00:57:02.945416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7470 00:57:02.945874 ==
7471 00:57:02.946232
7472 00:57:02.946561
7473 00:57:02.946874 TX Vref Scan disable
7474 00:57:02.949237 == TX Byte 0 ==
7475 00:57:02.953408 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7476 00:57:02.959265 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7477 00:57:02.959821 == TX Byte 1 ==
7478 00:57:02.963025 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7479 00:57:02.969416 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7480 00:57:02.969974 ==
7481 00:57:02.972556 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 00:57:02.975942 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7483 00:57:02.976405 ==
7484 00:57:02.988651
7485 00:57:02.992531 TX Vref early break, caculate TX vref
7486 00:57:02.995272 TX Vref=16, minBit 8, minWin=22, winSum=369
7487 00:57:02.998082 TX Vref=18, minBit 10, minWin=22, winSum=380
7488 00:57:03.001457 TX Vref=20, minBit 8, minWin=23, winSum=389
7489 00:57:03.005482 TX Vref=22, minBit 4, minWin=24, winSum=396
7490 00:57:03.008125 TX Vref=24, minBit 1, minWin=24, winSum=402
7491 00:57:03.014874 TX Vref=26, minBit 9, minWin=24, winSum=412
7492 00:57:03.018833 TX Vref=28, minBit 4, minWin=25, winSum=415
7493 00:57:03.021903 TX Vref=30, minBit 6, minWin=24, winSum=408
7494 00:57:03.025142 TX Vref=32, minBit 6, minWin=24, winSum=400
7495 00:57:03.028760 TX Vref=34, minBit 8, minWin=23, winSum=393
7496 00:57:03.035299 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 28
7497 00:57:03.035884
7498 00:57:03.038519 Final TX Range 0 Vref 28
7499 00:57:03.039077
7500 00:57:03.039442 ==
7501 00:57:03.041300 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 00:57:03.044999 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7503 00:57:03.045461 ==
7504 00:57:03.045826
7505 00:57:03.046167
7506 00:57:03.048445 TX Vref Scan disable
7507 00:57:03.054441 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7508 00:57:03.054979 == TX Byte 0 ==
7509 00:57:03.058392 u2DelayCellOfst[0]=10 cells (3 PI)
7510 00:57:03.061594 u2DelayCellOfst[1]=17 cells (5 PI)
7511 00:57:03.064695 u2DelayCellOfst[2]=14 cells (4 PI)
7512 00:57:03.068438 u2DelayCellOfst[3]=14 cells (4 PI)
7513 00:57:03.071586 u2DelayCellOfst[4]=7 cells (2 PI)
7514 00:57:03.074705 u2DelayCellOfst[5]=0 cells (0 PI)
7515 00:57:03.077827 u2DelayCellOfst[6]=17 cells (5 PI)
7516 00:57:03.081597 u2DelayCellOfst[7]=17 cells (5 PI)
7517 00:57:03.084534 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7518 00:57:03.088269 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7519 00:57:03.091978 == TX Byte 1 ==
7520 00:57:03.092530 u2DelayCellOfst[8]=0 cells (0 PI)
7521 00:57:03.095236 u2DelayCellOfst[9]=0 cells (0 PI)
7522 00:57:03.097830 u2DelayCellOfst[10]=10 cells (3 PI)
7523 00:57:03.101283 u2DelayCellOfst[11]=7 cells (2 PI)
7524 00:57:03.104893 u2DelayCellOfst[12]=14 cells (4 PI)
7525 00:57:03.108483 u2DelayCellOfst[13]=14 cells (4 PI)
7526 00:57:03.111728 u2DelayCellOfst[14]=17 cells (5 PI)
7527 00:57:03.114417 u2DelayCellOfst[15]=14 cells (4 PI)
7528 00:57:03.118784 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7529 00:57:03.124576 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7530 00:57:03.125169 DramC Write-DBI on
7531 00:57:03.125598 ==
7532 00:57:03.128034 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 00:57:03.130918 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7534 00:57:03.134200 ==
7535 00:57:03.134751
7536 00:57:03.135111
7537 00:57:03.135451 TX Vref Scan disable
7538 00:57:03.137980 == TX Byte 0 ==
7539 00:57:03.141507 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7540 00:57:03.144914 == TX Byte 1 ==
7541 00:57:03.148101 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7542 00:57:03.152053 DramC Write-DBI off
7543 00:57:03.152657
7544 00:57:03.153138 [DATLAT]
7545 00:57:03.153486 Freq=1600, CH0 RK0
7546 00:57:03.153812
7547 00:57:03.154927 DATLAT Default: 0xf
7548 00:57:03.155324 0, 0xFFFF, sum = 0
7549 00:57:03.158317 1, 0xFFFF, sum = 0
7550 00:57:03.161067 2, 0xFFFF, sum = 0
7551 00:57:03.161536 3, 0xFFFF, sum = 0
7552 00:57:03.164235 4, 0xFFFF, sum = 0
7553 00:57:03.164734 5, 0xFFFF, sum = 0
7554 00:57:03.167999 6, 0xFFFF, sum = 0
7555 00:57:03.168555 7, 0xFFFF, sum = 0
7556 00:57:03.171749 8, 0xFFFF, sum = 0
7557 00:57:03.172336 9, 0xFFFF, sum = 0
7558 00:57:03.174848 10, 0xFFFF, sum = 0
7559 00:57:03.175410 11, 0xFFFF, sum = 0
7560 00:57:03.178261 12, 0x8FFF, sum = 0
7561 00:57:03.178725 13, 0x0, sum = 1
7562 00:57:03.181438 14, 0x0, sum = 2
7563 00:57:03.181900 15, 0x0, sum = 3
7564 00:57:03.185324 16, 0x0, sum = 4
7565 00:57:03.185883 best_step = 14
7566 00:57:03.186249
7567 00:57:03.186583 ==
7568 00:57:03.187425 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 00:57:03.191071 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7570 00:57:03.194471 ==
7571 00:57:03.195023 RX Vref Scan: 1
7572 00:57:03.195390
7573 00:57:03.198792 Set Vref Range= 24 -> 127
7574 00:57:03.199353
7575 00:57:03.201054 RX Vref 24 -> 127, step: 1
7576 00:57:03.201601
7577 00:57:03.201971 RX Delay 11 -> 252, step: 4
7578 00:57:03.202357
7579 00:57:03.204531 Set Vref, RX VrefLevel [Byte0]: 24
7580 00:57:03.207607 [Byte1]: 24
7581 00:57:03.211292
7582 00:57:03.211840 Set Vref, RX VrefLevel [Byte0]: 25
7583 00:57:03.214778 [Byte1]: 25
7584 00:57:03.219311
7585 00:57:03.219859 Set Vref, RX VrefLevel [Byte0]: 26
7586 00:57:03.222396 [Byte1]: 26
7587 00:57:03.226453
7588 00:57:03.227009 Set Vref, RX VrefLevel [Byte0]: 27
7589 00:57:03.230037 [Byte1]: 27
7590 00:57:03.234602
7591 00:57:03.235156 Set Vref, RX VrefLevel [Byte0]: 28
7592 00:57:03.237835 [Byte1]: 28
7593 00:57:03.242096
7594 00:57:03.242553 Set Vref, RX VrefLevel [Byte0]: 29
7595 00:57:03.245366 [Byte1]: 29
7596 00:57:03.249298
7597 00:57:03.249757 Set Vref, RX VrefLevel [Byte0]: 30
7598 00:57:03.252598 [Byte1]: 30
7599 00:57:03.257094
7600 00:57:03.257553 Set Vref, RX VrefLevel [Byte0]: 31
7601 00:57:03.260594 [Byte1]: 31
7602 00:57:03.264892
7603 00:57:03.265446 Set Vref, RX VrefLevel [Byte0]: 32
7604 00:57:03.268181 [Byte1]: 32
7605 00:57:03.272943
7606 00:57:03.273518 Set Vref, RX VrefLevel [Byte0]: 33
7607 00:57:03.275683 [Byte1]: 33
7608 00:57:03.279988
7609 00:57:03.280559 Set Vref, RX VrefLevel [Byte0]: 34
7610 00:57:03.284870 [Byte1]: 34
7611 00:57:03.287898
7612 00:57:03.288466 Set Vref, RX VrefLevel [Byte0]: 35
7613 00:57:03.291008 [Byte1]: 35
7614 00:57:03.295224
7615 00:57:03.295773 Set Vref, RX VrefLevel [Byte0]: 36
7616 00:57:03.299001 [Byte1]: 36
7617 00:57:03.302559
7618 00:57:03.302969 Set Vref, RX VrefLevel [Byte0]: 37
7619 00:57:03.306151 [Byte1]: 37
7620 00:57:03.310748
7621 00:57:03.311301 Set Vref, RX VrefLevel [Byte0]: 38
7622 00:57:03.313412 [Byte1]: 38
7623 00:57:03.318287
7624 00:57:03.318946 Set Vref, RX VrefLevel [Byte0]: 39
7625 00:57:03.321828 [Byte1]: 39
7626 00:57:03.325238
7627 00:57:03.325695 Set Vref, RX VrefLevel [Byte0]: 40
7628 00:57:03.328651 [Byte1]: 40
7629 00:57:03.333119
7630 00:57:03.333669 Set Vref, RX VrefLevel [Byte0]: 41
7631 00:57:03.336866 [Byte1]: 41
7632 00:57:03.341007
7633 00:57:03.341574 Set Vref, RX VrefLevel [Byte0]: 42
7634 00:57:03.344187 [Byte1]: 42
7635 00:57:03.348418
7636 00:57:03.348915 Set Vref, RX VrefLevel [Byte0]: 43
7637 00:57:03.351766 [Byte1]: 43
7638 00:57:03.355852
7639 00:57:03.356311 Set Vref, RX VrefLevel [Byte0]: 44
7640 00:57:03.359645 [Byte1]: 44
7641 00:57:03.363890
7642 00:57:03.364517 Set Vref, RX VrefLevel [Byte0]: 45
7643 00:57:03.367136 [Byte1]: 45
7644 00:57:03.371590
7645 00:57:03.372050 Set Vref, RX VrefLevel [Byte0]: 46
7646 00:57:03.374476 [Byte1]: 46
7647 00:57:03.378550
7648 00:57:03.379006 Set Vref, RX VrefLevel [Byte0]: 47
7649 00:57:03.381951 [Byte1]: 47
7650 00:57:03.386654
7651 00:57:03.387215 Set Vref, RX VrefLevel [Byte0]: 48
7652 00:57:03.389970 [Byte1]: 48
7653 00:57:03.394012
7654 00:57:03.394573 Set Vref, RX VrefLevel [Byte0]: 49
7655 00:57:03.398003 [Byte1]: 49
7656 00:57:03.402255
7657 00:57:03.402806 Set Vref, RX VrefLevel [Byte0]: 50
7658 00:57:03.404879 [Byte1]: 50
7659 00:57:03.409143
7660 00:57:03.409689 Set Vref, RX VrefLevel [Byte0]: 51
7661 00:57:03.412592 [Byte1]: 51
7662 00:57:03.416886
7663 00:57:03.417431 Set Vref, RX VrefLevel [Byte0]: 52
7664 00:57:03.421072 [Byte1]: 52
7665 00:57:03.424853
7666 00:57:03.425452 Set Vref, RX VrefLevel [Byte0]: 53
7667 00:57:03.427835 [Byte1]: 53
7668 00:57:03.432164
7669 00:57:03.432751 Set Vref, RX VrefLevel [Byte0]: 54
7670 00:57:03.435871 [Byte1]: 54
7671 00:57:03.439688
7672 00:57:03.440239 Set Vref, RX VrefLevel [Byte0]: 55
7673 00:57:03.443323 [Byte1]: 55
7674 00:57:03.448398
7675 00:57:03.449012 Set Vref, RX VrefLevel [Byte0]: 56
7676 00:57:03.450576 [Byte1]: 56
7677 00:57:03.455299
7678 00:57:03.455796 Set Vref, RX VrefLevel [Byte0]: 57
7679 00:57:03.458819 [Byte1]: 57
7680 00:57:03.462848
7681 00:57:03.463423 Set Vref, RX VrefLevel [Byte0]: 58
7682 00:57:03.465467 [Byte1]: 58
7683 00:57:03.470166
7684 00:57:03.470689 Set Vref, RX VrefLevel [Byte0]: 59
7685 00:57:03.474278 [Byte1]: 59
7686 00:57:03.477956
7687 00:57:03.478415 Set Vref, RX VrefLevel [Byte0]: 60
7688 00:57:03.480638 [Byte1]: 60
7689 00:57:03.485406
7690 00:57:03.485967 Set Vref, RX VrefLevel [Byte0]: 61
7691 00:57:03.488755 [Byte1]: 61
7692 00:57:03.493460
7693 00:57:03.494008 Set Vref, RX VrefLevel [Byte0]: 62
7694 00:57:03.496340 [Byte1]: 62
7695 00:57:03.500884
7696 00:57:03.501469 Set Vref, RX VrefLevel [Byte0]: 63
7697 00:57:03.503958 [Byte1]: 63
7698 00:57:03.508207
7699 00:57:03.508668 Set Vref, RX VrefLevel [Byte0]: 64
7700 00:57:03.511628 [Byte1]: 64
7701 00:57:03.516048
7702 00:57:03.516597 Set Vref, RX VrefLevel [Byte0]: 65
7703 00:57:03.519343 [Byte1]: 65
7704 00:57:03.523972
7705 00:57:03.524519 Set Vref, RX VrefLevel [Byte0]: 66
7706 00:57:03.527136 [Byte1]: 66
7707 00:57:03.531873
7708 00:57:03.532573 Set Vref, RX VrefLevel [Byte0]: 67
7709 00:57:03.534363 [Byte1]: 67
7710 00:57:03.539149
7711 00:57:03.539705 Set Vref, RX VrefLevel [Byte0]: 68
7712 00:57:03.541799 [Byte1]: 68
7713 00:57:03.545879
7714 00:57:03.546344 Set Vref, RX VrefLevel [Byte0]: 69
7715 00:57:03.550027 [Byte1]: 69
7716 00:57:03.554140
7717 00:57:03.554692 Final RX Vref Byte 0 = 52 to rank0
7718 00:57:03.557397 Final RX Vref Byte 1 = 55 to rank0
7719 00:57:03.561280 Final RX Vref Byte 0 = 52 to rank1
7720 00:57:03.564138 Final RX Vref Byte 1 = 55 to rank1==
7721 00:57:03.567536 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 00:57:03.574382 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7723 00:57:03.574940 ==
7724 00:57:03.575309 DQS Delay:
7725 00:57:03.575652 DQS0 = 0, DQS1 = 0
7726 00:57:03.577709 DQM Delay:
7727 00:57:03.578209 DQM0 = 127, DQM1 = 121
7728 00:57:03.580607 DQ Delay:
7729 00:57:03.584271 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7730 00:57:03.587349 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7731 00:57:03.591103 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7732 00:57:03.594548 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =132
7733 00:57:03.595100
7734 00:57:03.595463
7735 00:57:03.595796
7736 00:57:03.597301 [DramC_TX_OE_Calibration] TA2
7737 00:57:03.600938 Original DQ_B0 (3 6) =30, OEN = 27
7738 00:57:03.603704 Original DQ_B1 (3 6) =30, OEN = 27
7739 00:57:03.607288 24, 0x0, End_B0=24 End_B1=24
7740 00:57:03.607872 25, 0x0, End_B0=25 End_B1=25
7741 00:57:03.610804 26, 0x0, End_B0=26 End_B1=26
7742 00:57:03.613591 27, 0x0, End_B0=27 End_B1=27
7743 00:57:03.616828 28, 0x0, End_B0=28 End_B1=28
7744 00:57:03.617296 29, 0x0, End_B0=29 End_B1=29
7745 00:57:03.620492 30, 0x0, End_B0=30 End_B1=30
7746 00:57:03.624089 31, 0x4141, End_B0=30 End_B1=30
7747 00:57:03.626846 Byte0 end_step=30 best_step=27
7748 00:57:03.630545 Byte1 end_step=30 best_step=27
7749 00:57:03.633588 Byte0 TX OE(2T, 0.5T) = (3, 3)
7750 00:57:03.637082 Byte1 TX OE(2T, 0.5T) = (3, 3)
7751 00:57:03.637655
7752 00:57:03.638020
7753 00:57:03.643921 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7754 00:57:03.646620 CH0 RK0: MR19=303, MR18=1C1C
7755 00:57:03.653200 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7756 00:57:03.653763
7757 00:57:03.656772 ----->DramcWriteLeveling(PI) begin...
7758 00:57:03.657338 ==
7759 00:57:03.659923 Dram Type= 6, Freq= 0, CH_0, rank 1
7760 00:57:03.663223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7761 00:57:03.663785 ==
7762 00:57:03.666180 Write leveling (Byte 0): 29 => 29
7763 00:57:03.669568 Write leveling (Byte 1): 26 => 26
7764 00:57:03.673167 DramcWriteLeveling(PI) end<-----
7765 00:57:03.673627
7766 00:57:03.673988 ==
7767 00:57:03.676430 Dram Type= 6, Freq= 0, CH_0, rank 1
7768 00:57:03.680235 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7769 00:57:03.680858 ==
7770 00:57:03.682877 [Gating] SW mode calibration
7771 00:57:03.689452 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7772 00:57:03.696587 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7773 00:57:03.699586 0 12 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7774 00:57:03.706007 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
7775 00:57:03.709911 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7776 00:57:03.712945 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7777 00:57:03.719740 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7778 00:57:03.722645 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7779 00:57:03.725798 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7780 00:57:03.732625 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7781 00:57:03.736283 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
7782 00:57:03.739228 0 13 4 | B1->B0 | 3333 2323 | 1 0 | (0 1) (1 0)
7783 00:57:03.746478 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7784 00:57:03.749029 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7785 00:57:03.752791 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7786 00:57:03.759126 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7787 00:57:03.762969 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7788 00:57:03.765267 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7789 00:57:03.771991 0 14 0 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7790 00:57:03.775294 0 14 4 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7791 00:57:03.778664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7792 00:57:03.785298 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7793 00:57:03.788899 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7794 00:57:03.791747 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7795 00:57:03.799882 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7796 00:57:03.802294 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7797 00:57:03.805040 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7798 00:57:03.812034 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7799 00:57:03.815324 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7800 00:57:03.818620 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7801 00:57:03.825101 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7802 00:57:03.829074 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7803 00:57:03.831652 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7804 00:57:03.838056 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7805 00:57:03.841855 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7806 00:57:03.844882 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7807 00:57:03.848090 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 00:57:03.855522 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 00:57:03.858591 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 00:57:03.861440 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 00:57:03.868544 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7812 00:57:03.871625 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7813 00:57:03.875059 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7814 00:57:03.882216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7815 00:57:03.884814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 00:57:03.888580 Total UI for P1: 0, mck2ui 16
7817 00:57:03.891429 best dqsien dly found for B0: ( 1, 0, 30)
7818 00:57:03.894712 Total UI for P1: 0, mck2ui 16
7819 00:57:03.898176 best dqsien dly found for B1: ( 1, 1, 2)
7820 00:57:03.901803 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7821 00:57:03.904745 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7822 00:57:03.905212
7823 00:57:03.908087 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7824 00:57:03.911155 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7825 00:57:03.914471 [Gating] SW calibration Done
7826 00:57:03.915022 ==
7827 00:57:03.918021 Dram Type= 6, Freq= 0, CH_0, rank 1
7828 00:57:03.924215 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7829 00:57:03.925018 ==
7830 00:57:03.925402 RX Vref Scan: 0
7831 00:57:03.925737
7832 00:57:03.927977 RX Vref 0 -> 0, step: 1
7833 00:57:03.928638
7834 00:57:03.930564 RX Delay 0 -> 252, step: 8
7835 00:57:03.934742 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7836 00:57:03.937646 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7837 00:57:03.941330 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7838 00:57:03.943921 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7839 00:57:03.950650 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7840 00:57:03.953418 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7841 00:57:03.957099 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7842 00:57:03.960108 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7843 00:57:03.963575 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7844 00:57:03.970408 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7845 00:57:03.973335 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7846 00:57:03.976832 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7847 00:57:03.980324 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7848 00:57:03.986870 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7849 00:57:03.990794 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7850 00:57:03.993056 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7851 00:57:03.993509 ==
7852 00:57:03.996597 Dram Type= 6, Freq= 0, CH_0, rank 1
7853 00:57:03.999777 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7854 00:57:04.003572 ==
7855 00:57:04.004125 DQS Delay:
7856 00:57:04.004486 DQS0 = 0, DQS1 = 0
7857 00:57:04.006914 DQM Delay:
7858 00:57:04.007444 DQM0 = 131, DQM1 = 124
7859 00:57:04.010448 DQ Delay:
7860 00:57:04.013625 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
7861 00:57:04.016784 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7862 00:57:04.019897 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7863 00:57:04.023029 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7864 00:57:04.023507
7865 00:57:04.023861
7866 00:57:04.024194 ==
7867 00:57:04.026736 Dram Type= 6, Freq= 0, CH_0, rank 1
7868 00:57:04.030092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7869 00:57:04.030555 ==
7870 00:57:04.030916
7871 00:57:04.033034
7872 00:57:04.033665 TX Vref Scan disable
7873 00:57:04.036339 == TX Byte 0 ==
7874 00:57:04.039460 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7875 00:57:04.043185 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7876 00:57:04.046944 == TX Byte 1 ==
7877 00:57:04.049892 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7878 00:57:04.053185 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7879 00:57:04.053680 ==
7880 00:57:04.056340 Dram Type= 6, Freq= 0, CH_0, rank 1
7881 00:57:04.062904 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7882 00:57:04.063497 ==
7883 00:57:04.074821
7884 00:57:04.078181 TX Vref early break, caculate TX vref
7885 00:57:04.081051 TX Vref=16, minBit 8, minWin=22, winSum=374
7886 00:57:04.084574 TX Vref=18, minBit 8, minWin=22, winSum=381
7887 00:57:04.088105 TX Vref=20, minBit 8, minWin=23, winSum=389
7888 00:57:04.090747 TX Vref=22, minBit 8, minWin=23, winSum=398
7889 00:57:04.094498 TX Vref=24, minBit 8, minWin=24, winSum=401
7890 00:57:04.101046 TX Vref=26, minBit 8, minWin=24, winSum=415
7891 00:57:04.104249 TX Vref=28, minBit 8, minWin=24, winSum=414
7892 00:57:04.107781 TX Vref=30, minBit 8, minWin=24, winSum=407
7893 00:57:04.111639 TX Vref=32, minBit 8, minWin=24, winSum=404
7894 00:57:04.114982 TX Vref=34, minBit 8, minWin=23, winSum=393
7895 00:57:04.121507 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 26
7896 00:57:04.122084
7897 00:57:04.124225 Final TX Range 0 Vref 26
7898 00:57:04.124849
7899 00:57:04.125345 ==
7900 00:57:04.127598 Dram Type= 6, Freq= 0, CH_0, rank 1
7901 00:57:04.130480 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7902 00:57:04.130959 ==
7903 00:57:04.131445
7904 00:57:04.131906
7905 00:57:04.134230 TX Vref Scan disable
7906 00:57:04.141118 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7907 00:57:04.141675 == TX Byte 0 ==
7908 00:57:04.144521 u2DelayCellOfst[0]=14 cells (4 PI)
7909 00:57:04.147718 u2DelayCellOfst[1]=17 cells (5 PI)
7910 00:57:04.150475 u2DelayCellOfst[2]=10 cells (3 PI)
7911 00:57:04.154243 u2DelayCellOfst[3]=10 cells (3 PI)
7912 00:57:04.157471 u2DelayCellOfst[4]=10 cells (3 PI)
7913 00:57:04.160682 u2DelayCellOfst[5]=0 cells (0 PI)
7914 00:57:04.163828 u2DelayCellOfst[6]=17 cells (5 PI)
7915 00:57:04.167160 u2DelayCellOfst[7]=21 cells (6 PI)
7916 00:57:04.170730 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7917 00:57:04.173557 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7918 00:57:04.177711 == TX Byte 1 ==
7919 00:57:04.178171 u2DelayCellOfst[8]=0 cells (0 PI)
7920 00:57:04.180419 u2DelayCellOfst[9]=0 cells (0 PI)
7921 00:57:04.183921 u2DelayCellOfst[10]=7 cells (2 PI)
7922 00:57:04.187936 u2DelayCellOfst[11]=3 cells (1 PI)
7923 00:57:04.190375 u2DelayCellOfst[12]=17 cells (5 PI)
7924 00:57:04.194098 u2DelayCellOfst[13]=14 cells (4 PI)
7925 00:57:04.197056 u2DelayCellOfst[14]=17 cells (5 PI)
7926 00:57:04.200843 u2DelayCellOfst[15]=14 cells (4 PI)
7927 00:57:04.203617 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7928 00:57:04.210258 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7929 00:57:04.210798 DramC Write-DBI on
7930 00:57:04.211163 ==
7931 00:57:04.213500 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 00:57:04.220418 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 00:57:04.221025 ==
7934 00:57:04.221394
7935 00:57:04.221734
7936 00:57:04.222076 TX Vref Scan disable
7937 00:57:04.224358 == TX Byte 0 ==
7938 00:57:04.227031 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7939 00:57:04.231444 == TX Byte 1 ==
7940 00:57:04.233607 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7941 00:57:04.236697 DramC Write-DBI off
7942 00:57:04.237289
7943 00:57:04.237772 [DATLAT]
7944 00:57:04.238231 Freq=1600, CH0 RK1
7945 00:57:04.238681
7946 00:57:04.240777 DATLAT Default: 0xe
7947 00:57:04.243730 0, 0xFFFF, sum = 0
7948 00:57:04.244264 1, 0xFFFF, sum = 0
7949 00:57:04.246891 2, 0xFFFF, sum = 0
7950 00:57:04.247371 3, 0xFFFF, sum = 0
7951 00:57:04.250537 4, 0xFFFF, sum = 0
7952 00:57:04.251018 5, 0xFFFF, sum = 0
7953 00:57:04.254101 6, 0xFFFF, sum = 0
7954 00:57:04.254723 7, 0xFFFF, sum = 0
7955 00:57:04.257123 8, 0xFFFF, sum = 0
7956 00:57:04.257605 9, 0xFFFF, sum = 0
7957 00:57:04.259952 10, 0xFFFF, sum = 0
7958 00:57:04.260436 11, 0xFFFF, sum = 0
7959 00:57:04.263712 12, 0x8FFF, sum = 0
7960 00:57:04.264194 13, 0x0, sum = 1
7961 00:57:04.266847 14, 0x0, sum = 2
7962 00:57:04.267332 15, 0x0, sum = 3
7963 00:57:04.270222 16, 0x0, sum = 4
7964 00:57:04.270708 best_step = 14
7965 00:57:04.271191
7966 00:57:04.271646 ==
7967 00:57:04.273211 Dram Type= 6, Freq= 0, CH_0, rank 1
7968 00:57:04.276817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7969 00:57:04.280325 ==
7970 00:57:04.280853 RX Vref Scan: 0
7971 00:57:04.281335
7972 00:57:04.283649 RX Vref 0 -> 0, step: 1
7973 00:57:04.284202
7974 00:57:04.286928 RX Delay 11 -> 252, step: 4
7975 00:57:04.290550 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7976 00:57:04.293208 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7977 00:57:04.296667 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7978 00:57:04.303714 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7979 00:57:04.306798 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7980 00:57:04.310218 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7981 00:57:04.313104 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7982 00:57:04.316546 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7983 00:57:04.323856 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7984 00:57:04.326233 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7985 00:57:04.330165 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7986 00:57:04.333280 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7987 00:57:04.336067 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7988 00:57:04.343204 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7989 00:57:04.345990 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7990 00:57:04.349701 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7991 00:57:04.350224 ==
7992 00:57:04.353174 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 00:57:04.356519 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7994 00:57:04.359694 ==
7995 00:57:04.360151 DQS Delay:
7996 00:57:04.360515 DQS0 = 0, DQS1 = 0
7997 00:57:04.362501 DQM Delay:
7998 00:57:04.362960 DQM0 = 128, DQM1 = 120
7999 00:57:04.366194 DQ Delay:
8000 00:57:04.369495 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8001 00:57:04.372904 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8002 00:57:04.376422 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8003 00:57:04.379451 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8004 00:57:04.379915
8005 00:57:04.380317
8006 00:57:04.380793
8007 00:57:04.382483 [DramC_TX_OE_Calibration] TA2
8008 00:57:04.386073 Original DQ_B0 (3 6) =30, OEN = 27
8009 00:57:04.389609 Original DQ_B1 (3 6) =30, OEN = 27
8010 00:57:04.392481 24, 0x0, End_B0=24 End_B1=24
8011 00:57:04.393106 25, 0x0, End_B0=25 End_B1=25
8012 00:57:04.395703 26, 0x0, End_B0=26 End_B1=26
8013 00:57:04.399343 27, 0x0, End_B0=27 End_B1=27
8014 00:57:04.402964 28, 0x0, End_B0=28 End_B1=28
8015 00:57:04.403537 29, 0x0, End_B0=29 End_B1=29
8016 00:57:04.405442 30, 0x0, End_B0=30 End_B1=30
8017 00:57:04.409159 31, 0x4141, End_B0=30 End_B1=30
8018 00:57:04.412312 Byte0 end_step=30 best_step=27
8019 00:57:04.416023 Byte1 end_step=30 best_step=27
8020 00:57:04.418827 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 00:57:04.419279 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 00:57:04.419636
8023 00:57:04.422359
8024 00:57:04.429287 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8025 00:57:04.432210 CH0 RK1: MR19=303, MR18=2323
8026 00:57:04.439232 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8027 00:57:04.442473 [RxdqsGatingPostProcess] freq 1600
8028 00:57:04.446460 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8029 00:57:04.449530 Pre-setting of DQS Precalculation
8030 00:57:04.455931 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8031 00:57:04.456498 ==
8032 00:57:04.459110 Dram Type= 6, Freq= 0, CH_1, rank 0
8033 00:57:04.462926 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8034 00:57:04.463490 ==
8035 00:57:04.469278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8036 00:57:04.472816 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8037 00:57:04.475301 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8038 00:57:04.482130 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8039 00:57:04.490394 [CA 0] Center 41 (11~71) winsize 61
8040 00:57:04.493475 [CA 1] Center 40 (10~70) winsize 61
8041 00:57:04.496938 [CA 2] Center 36 (7~66) winsize 60
8042 00:57:04.500660 [CA 3] Center 35 (6~65) winsize 60
8043 00:57:04.503047 [CA 4] Center 33 (4~63) winsize 60
8044 00:57:04.506340 [CA 5] Center 33 (4~63) winsize 60
8045 00:57:04.506905
8046 00:57:04.509818 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8047 00:57:04.510463
8048 00:57:04.512979 [CATrainingPosCal] consider 1 rank data
8049 00:57:04.516044 u2DelayCellTimex100 = 275/100 ps
8050 00:57:04.523489 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8051 00:57:04.526269 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8052 00:57:04.529447 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8053 00:57:04.533395 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8054 00:57:04.536210 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8055 00:57:04.539365 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8056 00:57:04.539921
8057 00:57:04.543221 CA PerBit enable=1, Macro0, CA PI delay=33
8058 00:57:04.543784
8059 00:57:04.546200 [CBTSetCACLKResult] CA Dly = 33
8060 00:57:04.550012 CS Dly: 8 (0~39)
8061 00:57:04.553052 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8062 00:57:04.555993 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8063 00:57:04.556452 ==
8064 00:57:04.559688 Dram Type= 6, Freq= 0, CH_1, rank 1
8065 00:57:04.566386 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 00:57:04.566969 ==
8067 00:57:04.568936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8068 00:57:04.572628 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8069 00:57:04.579773 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8070 00:57:04.585610 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8071 00:57:04.592205 [CA 0] Center 40 (10~70) winsize 61
8072 00:57:04.596040 [CA 1] Center 39 (9~70) winsize 62
8073 00:57:04.598985 [CA 2] Center 35 (6~65) winsize 60
8074 00:57:04.602450 [CA 3] Center 35 (6~65) winsize 60
8075 00:57:04.605702 [CA 4] Center 33 (4~62) winsize 59
8076 00:57:04.608737 [CA 5] Center 33 (3~63) winsize 61
8077 00:57:04.609292
8078 00:57:04.612019 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8079 00:57:04.612567
8080 00:57:04.615907 [CATrainingPosCal] consider 2 rank data
8081 00:57:04.619074 u2DelayCellTimex100 = 275/100 ps
8082 00:57:04.622304 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8083 00:57:04.629337 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8084 00:57:04.632239 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8085 00:57:04.635094 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8086 00:57:04.638531 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8087 00:57:04.642028 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8088 00:57:04.642589
8089 00:57:04.644910 CA PerBit enable=1, Macro0, CA PI delay=33
8090 00:57:04.645374
8091 00:57:04.648623 [CBTSetCACLKResult] CA Dly = 33
8092 00:57:04.652829 CS Dly: 9 (0~41)
8093 00:57:04.655379 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8094 00:57:04.658421 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8095 00:57:04.658915
8096 00:57:04.661546 ----->DramcWriteLeveling(PI) begin...
8097 00:57:04.662061 ==
8098 00:57:04.665404 Dram Type= 6, Freq= 0, CH_1, rank 0
8099 00:57:04.672637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8100 00:57:04.673263 ==
8101 00:57:04.675088 Write leveling (Byte 0): 24 => 24
8102 00:57:04.675656 Write leveling (Byte 1): 21 => 21
8103 00:57:04.678363 DramcWriteLeveling(PI) end<-----
8104 00:57:04.678825
8105 00:57:04.681442 ==
8106 00:57:04.681904 Dram Type= 6, Freq= 0, CH_1, rank 0
8107 00:57:04.688805 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8108 00:57:04.689398 ==
8109 00:57:04.692033 [Gating] SW mode calibration
8110 00:57:04.698812 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8111 00:57:04.701050 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8112 00:57:04.708059 0 12 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8113 00:57:04.711259 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8114 00:57:04.714567 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8115 00:57:04.721638 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8116 00:57:04.724289 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8117 00:57:04.727768 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8118 00:57:04.734140 0 12 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8119 00:57:04.738388 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
8120 00:57:04.740927 0 13 0 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8121 00:57:04.748001 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8122 00:57:04.750898 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8123 00:57:04.754126 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8124 00:57:04.761246 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8125 00:57:04.764623 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8126 00:57:04.767649 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8127 00:57:04.774496 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8128 00:57:04.777307 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8129 00:57:04.780885 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 00:57:04.788010 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 00:57:04.791027 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8132 00:57:04.793826 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8133 00:57:04.800308 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8134 00:57:04.803995 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8135 00:57:04.807001 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8136 00:57:04.813951 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8137 00:57:04.817422 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8138 00:57:04.821429 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 00:57:04.827108 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 00:57:04.830242 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 00:57:04.833675 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 00:57:04.840228 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 00:57:04.843758 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 00:57:04.846790 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 00:57:04.853771 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 00:57:04.856517 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 00:57:04.860102 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 00:57:04.866617 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 00:57:04.870744 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 00:57:04.873361 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 00:57:04.879840 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8152 00:57:04.880291 Total UI for P1: 0, mck2ui 16
8153 00:57:04.882817 best dqsien dly found for B0: ( 1, 0, 26)
8154 00:57:04.889779 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8155 00:57:04.893108 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8156 00:57:04.896265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 00:57:04.900517 Total UI for P1: 0, mck2ui 16
8158 00:57:04.902830 best dqsien dly found for B1: ( 1, 1, 0)
8159 00:57:04.907168 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8160 00:57:04.913021 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8161 00:57:04.913647
8162 00:57:04.916532 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8163 00:57:04.919473 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8164 00:57:04.923278 [Gating] SW calibration Done
8165 00:57:04.923867 ==
8166 00:57:04.926028 Dram Type= 6, Freq= 0, CH_1, rank 0
8167 00:57:04.929245 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8168 00:57:04.929784 ==
8169 00:57:04.930229 RX Vref Scan: 0
8170 00:57:04.932760
8171 00:57:04.933239 RX Vref 0 -> 0, step: 1
8172 00:57:04.933602
8173 00:57:04.935939 RX Delay 0 -> 252, step: 8
8174 00:57:04.939255 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8175 00:57:04.942654 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8176 00:57:04.949930 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8177 00:57:04.952493 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8178 00:57:04.957061 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8179 00:57:04.959226 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8180 00:57:04.962759 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8181 00:57:04.969559 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8182 00:57:04.972899 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8183 00:57:04.975456 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8184 00:57:04.978685 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8185 00:57:04.982371 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8186 00:57:04.988833 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8187 00:57:04.992474 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8188 00:57:04.996107 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8189 00:57:04.998796 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8190 00:57:04.999356 ==
8191 00:57:05.002764 Dram Type= 6, Freq= 0, CH_1, rank 0
8192 00:57:05.009758 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8193 00:57:05.010320 ==
8194 00:57:05.010692 DQS Delay:
8195 00:57:05.011850 DQS0 = 0, DQS1 = 0
8196 00:57:05.012309 DQM Delay:
8197 00:57:05.015290 DQM0 = 129, DQM1 = 124
8198 00:57:05.015749 DQ Delay:
8199 00:57:05.018802 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8200 00:57:05.021858 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8201 00:57:05.025086 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8202 00:57:05.029246 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8203 00:57:05.029818
8204 00:57:05.030191
8205 00:57:05.030528 ==
8206 00:57:05.031825 Dram Type= 6, Freq= 0, CH_1, rank 0
8207 00:57:05.039076 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8208 00:57:05.039642 ==
8209 00:57:05.040008
8210 00:57:05.040348
8211 00:57:05.040668 TX Vref Scan disable
8212 00:57:05.042441 == TX Byte 0 ==
8213 00:57:05.045292 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8214 00:57:05.052600 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8215 00:57:05.053219 == TX Byte 1 ==
8216 00:57:05.054957 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8217 00:57:05.061993 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8218 00:57:05.062455 ==
8219 00:57:05.065188 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 00:57:05.068195 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 00:57:05.068658 ==
8222 00:57:05.081351
8223 00:57:05.084046 TX Vref early break, caculate TX vref
8224 00:57:05.087272 TX Vref=16, minBit 3, minWin=21, winSum=369
8225 00:57:05.090980 TX Vref=18, minBit 3, minWin=22, winSum=381
8226 00:57:05.094477 TX Vref=20, minBit 3, minWin=22, winSum=386
8227 00:57:05.097313 TX Vref=22, minBit 0, minWin=24, winSum=398
8228 00:57:05.100819 TX Vref=24, minBit 0, minWin=24, winSum=408
8229 00:57:05.108136 TX Vref=26, minBit 0, minWin=25, winSum=415
8230 00:57:05.110774 TX Vref=28, minBit 3, minWin=24, winSum=417
8231 00:57:05.113547 TX Vref=30, minBit 3, minWin=24, winSum=410
8232 00:57:05.117275 TX Vref=32, minBit 0, minWin=23, winSum=398
8233 00:57:05.120451 TX Vref=34, minBit 3, minWin=23, winSum=391
8234 00:57:05.127332 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8235 00:57:05.127885
8236 00:57:05.130320 Final TX Range 0 Vref 26
8237 00:57:05.130874
8238 00:57:05.131234 ==
8239 00:57:05.133687 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 00:57:05.136769 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8241 00:57:05.137230 ==
8242 00:57:05.137592
8243 00:57:05.138080
8244 00:57:05.140307 TX Vref Scan disable
8245 00:57:05.146855 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8246 00:57:05.147414 == TX Byte 0 ==
8247 00:57:05.150435 u2DelayCellOfst[0]=17 cells (5 PI)
8248 00:57:05.153501 u2DelayCellOfst[1]=10 cells (3 PI)
8249 00:57:05.156818 u2DelayCellOfst[2]=0 cells (0 PI)
8250 00:57:05.160575 u2DelayCellOfst[3]=3 cells (1 PI)
8251 00:57:05.163453 u2DelayCellOfst[4]=7 cells (2 PI)
8252 00:57:05.167364 u2DelayCellOfst[5]=14 cells (4 PI)
8253 00:57:05.170113 u2DelayCellOfst[6]=14 cells (4 PI)
8254 00:57:05.173238 u2DelayCellOfst[7]=7 cells (2 PI)
8255 00:57:05.176870 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8256 00:57:05.180029 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8257 00:57:05.183244 == TX Byte 1 ==
8258 00:57:05.183703 u2DelayCellOfst[8]=0 cells (0 PI)
8259 00:57:05.186538 u2DelayCellOfst[9]=7 cells (2 PI)
8260 00:57:05.189510 u2DelayCellOfst[10]=10 cells (3 PI)
8261 00:57:05.193634 u2DelayCellOfst[11]=7 cells (2 PI)
8262 00:57:05.196246 u2DelayCellOfst[12]=17 cells (5 PI)
8263 00:57:05.200010 u2DelayCellOfst[13]=21 cells (6 PI)
8264 00:57:05.203044 u2DelayCellOfst[14]=21 cells (6 PI)
8265 00:57:05.206374 u2DelayCellOfst[15]=17 cells (5 PI)
8266 00:57:05.209990 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8267 00:57:05.216592 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8268 00:57:05.217179 DramC Write-DBI on
8269 00:57:05.217541 ==
8270 00:57:05.220254 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 00:57:05.226314 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8272 00:57:05.226867 ==
8273 00:57:05.227230
8274 00:57:05.227567
8275 00:57:05.227885 TX Vref Scan disable
8276 00:57:05.230266 == TX Byte 0 ==
8277 00:57:05.233087 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8278 00:57:05.236199 == TX Byte 1 ==
8279 00:57:05.239852 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8280 00:57:05.243342 DramC Write-DBI off
8281 00:57:05.243894
8282 00:57:05.244254 [DATLAT]
8283 00:57:05.244587 Freq=1600, CH1 RK0
8284 00:57:05.244975
8285 00:57:05.246886 DATLAT Default: 0xf
8286 00:57:05.249889 0, 0xFFFF, sum = 0
8287 00:57:05.250462 1, 0xFFFF, sum = 0
8288 00:57:05.252819 2, 0xFFFF, sum = 0
8289 00:57:05.253371 3, 0xFFFF, sum = 0
8290 00:57:05.256651 4, 0xFFFF, sum = 0
8291 00:57:05.257158 5, 0xFFFF, sum = 0
8292 00:57:05.259379 6, 0xFFFF, sum = 0
8293 00:57:05.259837 7, 0xFFFF, sum = 0
8294 00:57:05.263088 8, 0xFFFF, sum = 0
8295 00:57:05.263648 9, 0xFFFF, sum = 0
8296 00:57:05.266471 10, 0xFFFF, sum = 0
8297 00:57:05.267028 11, 0xFFFF, sum = 0
8298 00:57:05.269878 12, 0xF7F, sum = 0
8299 00:57:05.270438 13, 0x0, sum = 1
8300 00:57:05.273172 14, 0x0, sum = 2
8301 00:57:05.273742 15, 0x0, sum = 3
8302 00:57:05.276353 16, 0x0, sum = 4
8303 00:57:05.276943 best_step = 14
8304 00:57:05.277315
8305 00:57:05.277650 ==
8306 00:57:05.279185 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 00:57:05.282470 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8308 00:57:05.285742 ==
8309 00:57:05.286197 RX Vref Scan: 1
8310 00:57:05.286552
8311 00:57:05.290014 Set Vref Range= 24 -> 127
8312 00:57:05.290562
8313 00:57:05.292516 RX Vref 24 -> 127, step: 1
8314 00:57:05.293133
8315 00:57:05.293498 RX Delay 3 -> 252, step: 4
8316 00:57:05.293832
8317 00:57:05.296402 Set Vref, RX VrefLevel [Byte0]: 24
8318 00:57:05.299018 [Byte1]: 24
8319 00:57:05.303289
8320 00:57:05.303836 Set Vref, RX VrefLevel [Byte0]: 25
8321 00:57:05.307292 [Byte1]: 25
8322 00:57:05.311020
8323 00:57:05.314449 Set Vref, RX VrefLevel [Byte0]: 26
8324 00:57:05.316993 [Byte1]: 26
8325 00:57:05.317452
8326 00:57:05.320699 Set Vref, RX VrefLevel [Byte0]: 27
8327 00:57:05.323793 [Byte1]: 27
8328 00:57:05.324363
8329 00:57:05.327427 Set Vref, RX VrefLevel [Byte0]: 28
8330 00:57:05.330473 [Byte1]: 28
8331 00:57:05.333772
8332 00:57:05.334227 Set Vref, RX VrefLevel [Byte0]: 29
8333 00:57:05.337066 [Byte1]: 29
8334 00:57:05.341475
8335 00:57:05.342043 Set Vref, RX VrefLevel [Byte0]: 30
8336 00:57:05.344741 [Byte1]: 30
8337 00:57:05.349320
8338 00:57:05.349871 Set Vref, RX VrefLevel [Byte0]: 31
8339 00:57:05.352428 [Byte1]: 31
8340 00:57:05.357008
8341 00:57:05.357469 Set Vref, RX VrefLevel [Byte0]: 32
8342 00:57:05.359684 [Byte1]: 32
8343 00:57:05.364594
8344 00:57:05.365199 Set Vref, RX VrefLevel [Byte0]: 33
8345 00:57:05.367597 [Byte1]: 33
8346 00:57:05.371825
8347 00:57:05.372283 Set Vref, RX VrefLevel [Byte0]: 34
8348 00:57:05.375474 [Byte1]: 34
8349 00:57:05.379752
8350 00:57:05.380299 Set Vref, RX VrefLevel [Byte0]: 35
8351 00:57:05.382672 [Byte1]: 35
8352 00:57:05.387795
8353 00:57:05.388343 Set Vref, RX VrefLevel [Byte0]: 36
8354 00:57:05.390901 [Byte1]: 36
8355 00:57:05.395448
8356 00:57:05.395999 Set Vref, RX VrefLevel [Byte0]: 37
8357 00:57:05.398274 [Byte1]: 37
8358 00:57:05.402508
8359 00:57:05.403064 Set Vref, RX VrefLevel [Byte0]: 38
8360 00:57:05.406572 [Byte1]: 38
8361 00:57:05.410638
8362 00:57:05.411089 Set Vref, RX VrefLevel [Byte0]: 39
8363 00:57:05.413598 [Byte1]: 39
8364 00:57:05.418008
8365 00:57:05.418460 Set Vref, RX VrefLevel [Byte0]: 40
8366 00:57:05.420894 [Byte1]: 40
8367 00:57:05.425490
8368 00:57:05.425943 Set Vref, RX VrefLevel [Byte0]: 41
8369 00:57:05.428770 [Byte1]: 41
8370 00:57:05.433221
8371 00:57:05.433675 Set Vref, RX VrefLevel [Byte0]: 42
8372 00:57:05.437291 [Byte1]: 42
8373 00:57:05.440896
8374 00:57:05.441351 Set Vref, RX VrefLevel [Byte0]: 43
8375 00:57:05.444141 [Byte1]: 43
8376 00:57:05.448613
8377 00:57:05.449222 Set Vref, RX VrefLevel [Byte0]: 44
8378 00:57:05.451931 [Byte1]: 44
8379 00:57:05.456599
8380 00:57:05.457136 Set Vref, RX VrefLevel [Byte0]: 45
8381 00:57:05.459753 [Byte1]: 45
8382 00:57:05.463986
8383 00:57:05.464435 Set Vref, RX VrefLevel [Byte0]: 46
8384 00:57:05.467265 [Byte1]: 46
8385 00:57:05.471391
8386 00:57:05.471839 Set Vref, RX VrefLevel [Byte0]: 47
8387 00:57:05.475055 [Byte1]: 47
8388 00:57:05.479428
8389 00:57:05.479877 Set Vref, RX VrefLevel [Byte0]: 48
8390 00:57:05.482525 [Byte1]: 48
8391 00:57:05.486679
8392 00:57:05.487129 Set Vref, RX VrefLevel [Byte0]: 49
8393 00:57:05.489818 [Byte1]: 49
8394 00:57:05.494487
8395 00:57:05.495034 Set Vref, RX VrefLevel [Byte0]: 50
8396 00:57:05.498000 [Byte1]: 50
8397 00:57:05.502528
8398 00:57:05.503073 Set Vref, RX VrefLevel [Byte0]: 51
8399 00:57:05.505229 [Byte1]: 51
8400 00:57:05.509873
8401 00:57:05.510416 Set Vref, RX VrefLevel [Byte0]: 52
8402 00:57:05.513605 [Byte1]: 52
8403 00:57:05.517467
8404 00:57:05.518020 Set Vref, RX VrefLevel [Byte0]: 53
8405 00:57:05.521275 [Byte1]: 53
8406 00:57:05.525281
8407 00:57:05.525824 Set Vref, RX VrefLevel [Byte0]: 54
8408 00:57:05.528539 [Byte1]: 54
8409 00:57:05.532676
8410 00:57:05.533287 Set Vref, RX VrefLevel [Byte0]: 55
8411 00:57:05.536301 [Byte1]: 55
8412 00:57:05.540534
8413 00:57:05.541147 Set Vref, RX VrefLevel [Byte0]: 56
8414 00:57:05.543659 [Byte1]: 56
8415 00:57:05.547965
8416 00:57:05.548505 Set Vref, RX VrefLevel [Byte0]: 57
8417 00:57:05.551799 [Byte1]: 57
8418 00:57:05.555657
8419 00:57:05.556296 Set Vref, RX VrefLevel [Byte0]: 58
8420 00:57:05.559004 [Byte1]: 58
8421 00:57:05.563296
8422 00:57:05.563840 Set Vref, RX VrefLevel [Byte0]: 59
8423 00:57:05.567123 [Byte1]: 59
8424 00:57:05.570698
8425 00:57:05.571167 Set Vref, RX VrefLevel [Byte0]: 60
8426 00:57:05.574165 [Byte1]: 60
8427 00:57:05.579168
8428 00:57:05.579712 Set Vref, RX VrefLevel [Byte0]: 61
8429 00:57:05.582289 [Byte1]: 61
8430 00:57:05.586330
8431 00:57:05.586782 Set Vref, RX VrefLevel [Byte0]: 62
8432 00:57:05.590523 [Byte1]: 62
8433 00:57:05.594321
8434 00:57:05.594873 Set Vref, RX VrefLevel [Byte0]: 63
8435 00:57:05.597662 [Byte1]: 63
8436 00:57:05.601514
8437 00:57:05.602061 Set Vref, RX VrefLevel [Byte0]: 64
8438 00:57:05.605633 [Byte1]: 64
8439 00:57:05.609142
8440 00:57:05.609695 Set Vref, RX VrefLevel [Byte0]: 65
8441 00:57:05.612596 [Byte1]: 65
8442 00:57:05.617000
8443 00:57:05.617544 Set Vref, RX VrefLevel [Byte0]: 66
8444 00:57:05.620998 [Byte1]: 66
8445 00:57:05.624520
8446 00:57:05.625054 Set Vref, RX VrefLevel [Byte0]: 67
8447 00:57:05.628535 [Byte1]: 67
8448 00:57:05.631906
8449 00:57:05.632471 Set Vref, RX VrefLevel [Byte0]: 68
8450 00:57:05.635544 [Byte1]: 68
8451 00:57:05.640111
8452 00:57:05.640667 Set Vref, RX VrefLevel [Byte0]: 69
8453 00:57:05.642975 [Byte1]: 69
8454 00:57:05.647335
8455 00:57:05.647903 Set Vref, RX VrefLevel [Byte0]: 70
8456 00:57:05.651129 [Byte1]: 70
8457 00:57:05.655349
8458 00:57:05.655810 Set Vref, RX VrefLevel [Byte0]: 71
8459 00:57:05.658487 [Byte1]: 71
8460 00:57:05.663076
8461 00:57:05.663625 Set Vref, RX VrefLevel [Byte0]: 72
8462 00:57:05.666758 [Byte1]: 72
8463 00:57:05.670146
8464 00:57:05.670607 Set Vref, RX VrefLevel [Byte0]: 73
8465 00:57:05.676813 [Byte1]: 73
8466 00:57:05.677340
8467 00:57:05.680204 Set Vref, RX VrefLevel [Byte0]: 74
8468 00:57:05.683560 [Byte1]: 74
8469 00:57:05.684019
8470 00:57:05.687074 Set Vref, RX VrefLevel [Byte0]: 75
8471 00:57:05.689882 [Byte1]: 75
8472 00:57:05.693621
8473 00:57:05.694074 Final RX Vref Byte 0 = 57 to rank0
8474 00:57:05.696875 Final RX Vref Byte 1 = 53 to rank0
8475 00:57:05.700599 Final RX Vref Byte 0 = 57 to rank1
8476 00:57:05.703927 Final RX Vref Byte 1 = 53 to rank1==
8477 00:57:05.707206 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 00:57:05.713612 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8479 00:57:05.714168 ==
8480 00:57:05.714528 DQS Delay:
8481 00:57:05.717088 DQS0 = 0, DQS1 = 0
8482 00:57:05.717638 DQM Delay:
8483 00:57:05.718001 DQM0 = 129, DQM1 = 123
8484 00:57:05.720259 DQ Delay:
8485 00:57:05.723089 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8486 00:57:05.726891 DQ4 =128, DQ5 =140, DQ6 =138, DQ7 =126
8487 00:57:05.729716 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =114
8488 00:57:05.733538 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8489 00:57:05.734083
8490 00:57:05.734441
8491 00:57:05.734775
8492 00:57:05.736107 [DramC_TX_OE_Calibration] TA2
8493 00:57:05.740555 Original DQ_B0 (3 6) =30, OEN = 27
8494 00:57:05.742785 Original DQ_B1 (3 6) =30, OEN = 27
8495 00:57:05.746296 24, 0x0, End_B0=24 End_B1=24
8496 00:57:05.746863 25, 0x0, End_B0=25 End_B1=25
8497 00:57:05.749358 26, 0x0, End_B0=26 End_B1=26
8498 00:57:05.753151 27, 0x0, End_B0=27 End_B1=27
8499 00:57:05.756358 28, 0x0, End_B0=28 End_B1=28
8500 00:57:05.759530 29, 0x0, End_B0=29 End_B1=29
8501 00:57:05.760013 30, 0x0, End_B0=30 End_B1=30
8502 00:57:05.762928 31, 0x4141, End_B0=30 End_B1=30
8503 00:57:05.766297 Byte0 end_step=30 best_step=27
8504 00:57:05.769408 Byte1 end_step=30 best_step=27
8505 00:57:05.772794 Byte0 TX OE(2T, 0.5T) = (3, 3)
8506 00:57:05.776379 Byte1 TX OE(2T, 0.5T) = (3, 3)
8507 00:57:05.777042
8508 00:57:05.777454
8509 00:57:05.782995 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8510 00:57:05.785932 CH1 RK0: MR19=303, MR18=2424
8511 00:57:05.792886 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8512 00:57:05.793424
8513 00:57:05.795938 ----->DramcWriteLeveling(PI) begin...
8514 00:57:05.796495 ==
8515 00:57:05.799038 Dram Type= 6, Freq= 0, CH_1, rank 1
8516 00:57:05.802313 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8517 00:57:05.802873 ==
8518 00:57:05.805673 Write leveling (Byte 0): 22 => 22
8519 00:57:05.809107 Write leveling (Byte 1): 20 => 20
8520 00:57:05.812288 DramcWriteLeveling(PI) end<-----
8521 00:57:05.812890
8522 00:57:05.813256 ==
8523 00:57:05.815798 Dram Type= 6, Freq= 0, CH_1, rank 1
8524 00:57:05.818724 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8525 00:57:05.819197 ==
8526 00:57:05.822282 [Gating] SW mode calibration
8527 00:57:05.829162 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8528 00:57:05.835820 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8529 00:57:05.839337 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8530 00:57:05.845426 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8531 00:57:05.848795 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8532 00:57:05.851816 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8533 00:57:05.858284 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8534 00:57:05.862303 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8535 00:57:05.865292 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
8536 00:57:05.871837 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
8537 00:57:05.874867 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8538 00:57:05.878351 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8539 00:57:05.885317 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8540 00:57:05.888079 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8541 00:57:05.891789 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8542 00:57:05.898520 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8543 00:57:05.901503 0 13 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8544 00:57:05.904987 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8545 00:57:05.911561 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
8546 00:57:05.914526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8547 00:57:05.917703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8548 00:57:05.924127 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8549 00:57:05.927692 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8550 00:57:05.931267 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8551 00:57:05.937875 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8552 00:57:05.940864 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8553 00:57:05.944787 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8554 00:57:05.950682 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 00:57:05.954105 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8556 00:57:05.957272 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 00:57:05.963841 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 00:57:05.967511 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 00:57:05.970847 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 00:57:05.977299 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 00:57:05.980407 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 00:57:05.984144 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 00:57:05.991323 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 00:57:05.994387 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 00:57:05.997212 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 00:57:06.004409 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8567 00:57:06.007204 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8568 00:57:06.010603 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8569 00:57:06.017108 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8570 00:57:06.017568 Total UI for P1: 0, mck2ui 16
8571 00:57:06.023356 best dqsien dly found for B0: ( 1, 0, 24)
8572 00:57:06.026819 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8573 00:57:06.030687 Total UI for P1: 0, mck2ui 16
8574 00:57:06.033420 best dqsien dly found for B1: ( 1, 1, 0)
8575 00:57:06.036934 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8576 00:57:06.039877 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8577 00:57:06.040337
8578 00:57:06.043840 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8579 00:57:06.046478 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8580 00:57:06.050524 [Gating] SW calibration Done
8581 00:57:06.051106 ==
8582 00:57:06.053042 Dram Type= 6, Freq= 0, CH_1, rank 1
8583 00:57:06.056914 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8584 00:57:06.057442 ==
8585 00:57:06.060175 RX Vref Scan: 0
8586 00:57:06.060738
8587 00:57:06.063948 RX Vref 0 -> 0, step: 1
8588 00:57:06.064510
8589 00:57:06.064937 RX Delay 0 -> 252, step: 8
8590 00:57:06.070181 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8591 00:57:06.073018 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8592 00:57:06.076103 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8593 00:57:06.080102 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8594 00:57:06.082784 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8595 00:57:06.089506 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8596 00:57:06.092961 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8597 00:57:06.096013 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8598 00:57:06.099428 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8599 00:57:06.102347 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8600 00:57:06.109721 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8601 00:57:06.113192 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8602 00:57:06.116395 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8603 00:57:06.118891 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8604 00:57:06.125956 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8605 00:57:06.129031 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8606 00:57:06.129501 ==
8607 00:57:06.132783 Dram Type= 6, Freq= 0, CH_1, rank 1
8608 00:57:06.135812 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8609 00:57:06.136383 ==
8610 00:57:06.138956 DQS Delay:
8611 00:57:06.139414 DQS0 = 0, DQS1 = 0
8612 00:57:06.139833 DQM Delay:
8613 00:57:06.142504 DQM0 = 130, DQM1 = 124
8614 00:57:06.142962 DQ Delay:
8615 00:57:06.146064 DQ0 =135, DQ1 =123, DQ2 =115, DQ3 =131
8616 00:57:06.148907 DQ4 =131, DQ5 =139, DQ6 =139, DQ7 =131
8617 00:57:06.156888 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8618 00:57:06.159218 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8619 00:57:06.159924
8620 00:57:06.160501
8621 00:57:06.161120 ==
8622 00:57:06.163138 Dram Type= 6, Freq= 0, CH_1, rank 1
8623 00:57:06.165491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8624 00:57:06.165957 ==
8625 00:57:06.166322
8626 00:57:06.166660
8627 00:57:06.168470 TX Vref Scan disable
8628 00:57:06.168971 == TX Byte 0 ==
8629 00:57:06.175040 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8630 00:57:06.178674 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8631 00:57:06.179137 == TX Byte 1 ==
8632 00:57:06.185934 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8633 00:57:06.188225 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8634 00:57:06.188688 ==
8635 00:57:06.192467 Dram Type= 6, Freq= 0, CH_1, rank 1
8636 00:57:06.195395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8637 00:57:06.195851 ==
8638 00:57:06.209927
8639 00:57:06.213360 TX Vref early break, caculate TX vref
8640 00:57:06.216677 TX Vref=16, minBit 0, minWin=22, winSum=381
8641 00:57:06.220729 TX Vref=18, minBit 1, minWin=23, winSum=389
8642 00:57:06.223151 TX Vref=20, minBit 0, minWin=24, winSum=400
8643 00:57:06.226400 TX Vref=22, minBit 1, minWin=24, winSum=404
8644 00:57:06.229874 TX Vref=24, minBit 0, minWin=25, winSum=413
8645 00:57:06.236055 TX Vref=26, minBit 0, minWin=25, winSum=418
8646 00:57:06.239912 TX Vref=28, minBit 0, minWin=25, winSum=420
8647 00:57:06.242985 TX Vref=30, minBit 5, minWin=23, winSum=412
8648 00:57:06.246147 TX Vref=32, minBit 0, minWin=24, winSum=411
8649 00:57:06.249248 TX Vref=34, minBit 0, minWin=22, winSum=400
8650 00:57:06.253349 TX Vref=36, minBit 0, minWin=23, winSum=394
8651 00:57:06.259318 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8652 00:57:06.259399
8653 00:57:06.262679 Final TX Range 0 Vref 28
8654 00:57:06.262761
8655 00:57:06.262825 ==
8656 00:57:06.266523 Dram Type= 6, Freq= 0, CH_1, rank 1
8657 00:57:06.269621 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8658 00:57:06.269701 ==
8659 00:57:06.269764
8660 00:57:06.272938
8661 00:57:06.273018 TX Vref Scan disable
8662 00:57:06.279390 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8663 00:57:06.279470 == TX Byte 0 ==
8664 00:57:06.282201 u2DelayCellOfst[0]=17 cells (5 PI)
8665 00:57:06.286227 u2DelayCellOfst[1]=10 cells (3 PI)
8666 00:57:06.289682 u2DelayCellOfst[2]=0 cells (0 PI)
8667 00:57:06.292502 u2DelayCellOfst[3]=10 cells (3 PI)
8668 00:57:06.295536 u2DelayCellOfst[4]=10 cells (3 PI)
8669 00:57:06.299054 u2DelayCellOfst[5]=14 cells (4 PI)
8670 00:57:06.302228 u2DelayCellOfst[6]=17 cells (5 PI)
8671 00:57:06.305480 u2DelayCellOfst[7]=7 cells (2 PI)
8672 00:57:06.309146 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8673 00:57:06.312358 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8674 00:57:06.315506 == TX Byte 1 ==
8675 00:57:06.319022 u2DelayCellOfst[8]=0 cells (0 PI)
8676 00:57:06.322286 u2DelayCellOfst[9]=3 cells (1 PI)
8677 00:57:06.326368 u2DelayCellOfst[10]=10 cells (3 PI)
8678 00:57:06.329138 u2DelayCellOfst[11]=3 cells (1 PI)
8679 00:57:06.329400 u2DelayCellOfst[12]=14 cells (4 PI)
8680 00:57:06.332301 u2DelayCellOfst[13]=17 cells (5 PI)
8681 00:57:06.335546 u2DelayCellOfst[14]=17 cells (5 PI)
8682 00:57:06.339470 u2DelayCellOfst[15]=17 cells (5 PI)
8683 00:57:06.345903 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8684 00:57:06.348676 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8685 00:57:06.349002 DramC Write-DBI on
8686 00:57:06.352800 ==
8687 00:57:06.356134 Dram Type= 6, Freq= 0, CH_1, rank 1
8688 00:57:06.358817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8689 00:57:06.359286 ==
8690 00:57:06.359649
8691 00:57:06.359986
8692 00:57:06.362102 TX Vref Scan disable
8693 00:57:06.362738 == TX Byte 0 ==
8694 00:57:06.368955 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8695 00:57:06.369417 == TX Byte 1 ==
8696 00:57:06.372146 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8697 00:57:06.376056 DramC Write-DBI off
8698 00:57:06.376605
8699 00:57:06.377048 [DATLAT]
8700 00:57:06.379052 Freq=1600, CH1 RK1
8701 00:57:06.379514
8702 00:57:06.379874 DATLAT Default: 0xe
8703 00:57:06.382055 0, 0xFFFF, sum = 0
8704 00:57:06.382522 1, 0xFFFF, sum = 0
8705 00:57:06.385755 2, 0xFFFF, sum = 0
8706 00:57:06.386226 3, 0xFFFF, sum = 0
8707 00:57:06.388474 4, 0xFFFF, sum = 0
8708 00:57:06.388995 5, 0xFFFF, sum = 0
8709 00:57:06.392058 6, 0xFFFF, sum = 0
8710 00:57:06.392520 7, 0xFFFF, sum = 0
8711 00:57:06.395885 8, 0xFFFF, sum = 0
8712 00:57:06.398658 9, 0xFFFF, sum = 0
8713 00:57:06.399209 10, 0xFFFF, sum = 0
8714 00:57:06.402161 11, 0xFFFF, sum = 0
8715 00:57:06.402644 12, 0x8F7F, sum = 0
8716 00:57:06.405310 13, 0x0, sum = 1
8717 00:57:06.405776 14, 0x0, sum = 2
8718 00:57:06.408922 15, 0x0, sum = 3
8719 00:57:06.409538 16, 0x0, sum = 4
8720 00:57:06.410053 best_step = 14
8721 00:57:06.410409
8722 00:57:06.412570 ==
8723 00:57:06.415264 Dram Type= 6, Freq= 0, CH_1, rank 1
8724 00:57:06.419221 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8725 00:57:06.419681 ==
8726 00:57:06.420040 RX Vref Scan: 0
8727 00:57:06.420379
8728 00:57:06.422015 RX Vref 0 -> 0, step: 1
8729 00:57:06.422468
8730 00:57:06.425637 RX Delay 3 -> 252, step: 4
8731 00:57:06.428944 iDelay=195, Bit 0, Center 130 (75 ~ 186) 112
8732 00:57:06.431789 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8733 00:57:06.439045 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8734 00:57:06.441815 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8735 00:57:06.445851 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8736 00:57:06.448832 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8737 00:57:06.451663 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8738 00:57:06.458709 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8739 00:57:06.461925 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8740 00:57:06.465002 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8741 00:57:06.468123 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8742 00:57:06.471271 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8743 00:57:06.477915 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8744 00:57:06.482149 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8745 00:57:06.484977 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8746 00:57:06.488171 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8747 00:57:06.488583 ==
8748 00:57:06.491759 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 00:57:06.498634 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8750 00:57:06.499071 ==
8751 00:57:06.499397 DQS Delay:
8752 00:57:06.501849 DQS0 = 0, DQS1 = 0
8753 00:57:06.502260 DQM Delay:
8754 00:57:06.505197 DQM0 = 127, DQM1 = 123
8755 00:57:06.505625 DQ Delay:
8756 00:57:06.508093 DQ0 =130, DQ1 =124, DQ2 =116, DQ3 =124
8757 00:57:06.511306 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8758 00:57:06.514591 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8759 00:57:06.517604 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8760 00:57:06.518019
8761 00:57:06.518347
8762 00:57:06.518648
8763 00:57:06.521179 [DramC_TX_OE_Calibration] TA2
8764 00:57:06.524319 Original DQ_B0 (3 6) =30, OEN = 27
8765 00:57:06.527955 Original DQ_B1 (3 6) =30, OEN = 27
8766 00:57:06.531221 24, 0x0, End_B0=24 End_B1=24
8767 00:57:06.535325 25, 0x0, End_B0=25 End_B1=25
8768 00:57:06.535744 26, 0x0, End_B0=26 End_B1=26
8769 00:57:06.538277 27, 0x0, End_B0=27 End_B1=27
8770 00:57:06.541381 28, 0x0, End_B0=28 End_B1=28
8771 00:57:06.543972 29, 0x0, End_B0=29 End_B1=29
8772 00:57:06.544393 30, 0x0, End_B0=30 End_B1=30
8773 00:57:06.547612 31, 0x5151, End_B0=30 End_B1=30
8774 00:57:06.551479 Byte0 end_step=30 best_step=27
8775 00:57:06.554358 Byte1 end_step=30 best_step=27
8776 00:57:06.557543 Byte0 TX OE(2T, 0.5T) = (3, 3)
8777 00:57:06.560806 Byte1 TX OE(2T, 0.5T) = (3, 3)
8778 00:57:06.561415
8779 00:57:06.561811
8780 00:57:06.567291 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8781 00:57:06.571016 CH1 RK1: MR19=303, MR18=1D1D
8782 00:57:06.577347 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8783 00:57:06.580274 [RxdqsGatingPostProcess] freq 1600
8784 00:57:06.587174 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8785 00:57:06.587772 Pre-setting of DQS Precalculation
8786 00:57:06.593407 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8787 00:57:06.599876 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8788 00:57:06.606400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8789 00:57:06.606481
8790 00:57:06.606544
8791 00:57:06.609867 [Calibration Summary] 3200 Mbps
8792 00:57:06.613462 CH 0, Rank 0
8793 00:57:06.613543 SW Impedance : PASS
8794 00:57:06.616599 DUTY Scan : NO K
8795 00:57:06.620123 ZQ Calibration : PASS
8796 00:57:06.620204 Jitter Meter : NO K
8797 00:57:06.623052 CBT Training : PASS
8798 00:57:06.627104 Write leveling : PASS
8799 00:57:06.627185 RX DQS gating : PASS
8800 00:57:06.629856 RX DQ/DQS(RDDQC) : PASS
8801 00:57:06.633040 TX DQ/DQS : PASS
8802 00:57:06.633121 RX DATLAT : PASS
8803 00:57:06.636482 RX DQ/DQS(Engine): PASS
8804 00:57:06.636561 TX OE : PASS
8805 00:57:06.640096 All Pass.
8806 00:57:06.640176
8807 00:57:06.640239 CH 0, Rank 1
8808 00:57:06.643255 SW Impedance : PASS
8809 00:57:06.643335 DUTY Scan : NO K
8810 00:57:06.646967 ZQ Calibration : PASS
8811 00:57:06.650004 Jitter Meter : NO K
8812 00:57:06.650083 CBT Training : PASS
8813 00:57:06.653967 Write leveling : PASS
8814 00:57:06.656311 RX DQS gating : PASS
8815 00:57:06.656390 RX DQ/DQS(RDDQC) : PASS
8816 00:57:06.659871 TX DQ/DQS : PASS
8817 00:57:06.662917 RX DATLAT : PASS
8818 00:57:06.662998 RX DQ/DQS(Engine): PASS
8819 00:57:06.666022 TX OE : PASS
8820 00:57:06.666103 All Pass.
8821 00:57:06.666166
8822 00:57:06.669930 CH 1, Rank 0
8823 00:57:06.670010 SW Impedance : PASS
8824 00:57:06.672831 DUTY Scan : NO K
8825 00:57:06.676221 ZQ Calibration : PASS
8826 00:57:06.676301 Jitter Meter : NO K
8827 00:57:06.680161 CBT Training : PASS
8828 00:57:06.683077 Write leveling : PASS
8829 00:57:06.683157 RX DQS gating : PASS
8830 00:57:06.686469 RX DQ/DQS(RDDQC) : PASS
8831 00:57:06.689040 TX DQ/DQS : PASS
8832 00:57:06.689123 RX DATLAT : PASS
8833 00:57:06.692645 RX DQ/DQS(Engine): PASS
8834 00:57:06.696301 TX OE : PASS
8835 00:57:06.696382 All Pass.
8836 00:57:06.696445
8837 00:57:06.696503 CH 1, Rank 1
8838 00:57:06.699875 SW Impedance : PASS
8839 00:57:06.702484 DUTY Scan : NO K
8840 00:57:06.702563 ZQ Calibration : PASS
8841 00:57:06.706380 Jitter Meter : NO K
8842 00:57:06.706460 CBT Training : PASS
8843 00:57:06.709196 Write leveling : PASS
8844 00:57:06.712876 RX DQS gating : PASS
8845 00:57:06.712956 RX DQ/DQS(RDDQC) : PASS
8846 00:57:06.715816 TX DQ/DQS : PASS
8847 00:57:06.719065 RX DATLAT : PASS
8848 00:57:06.719146 RX DQ/DQS(Engine): PASS
8849 00:57:06.722406 TX OE : PASS
8850 00:57:06.722493 All Pass.
8851 00:57:06.722561
8852 00:57:06.725811 DramC Write-DBI on
8853 00:57:06.729633 PER_BANK_REFRESH: Hybrid Mode
8854 00:57:06.729771 TX_TRACKING: ON
8855 00:57:06.739293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8856 00:57:06.745653 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8857 00:57:06.752653 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8858 00:57:06.759098 [FAST_K] Save calibration result to emmc
8859 00:57:06.759179 sync common calibartion params.
8860 00:57:06.762207 sync cbt_mode0:0, 1:0
8861 00:57:06.765378 dram_init: ddr_geometry: 0
8862 00:57:06.765459 dram_init: ddr_geometry: 0
8863 00:57:06.768906 dram_init: ddr_geometry: 0
8864 00:57:06.772231 0:dram_rank_size:80000000
8865 00:57:06.775692 1:dram_rank_size:80000000
8866 00:57:06.779576 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8867 00:57:06.782115 DFS_SHUFFLE_HW_MODE: ON
8868 00:57:06.785108 dramc_set_vcore_voltage set vcore to 725000
8869 00:57:06.788288 Read voltage for 1600, 0
8870 00:57:06.788368 Vio18 = 0
8871 00:57:06.788432 Vcore = 725000
8872 00:57:06.791961 Vdram = 0
8873 00:57:06.792041 Vddq = 0
8874 00:57:06.792104 Vmddr = 0
8875 00:57:06.795535 switch to 3200 Mbps bootup
8876 00:57:06.799030 [DramcRunTimeConfig]
8877 00:57:06.799110 PHYPLL
8878 00:57:06.799174 DPM_CONTROL_AFTERK: ON
8879 00:57:06.801922 PER_BANK_REFRESH: ON
8880 00:57:06.805712 REFRESH_OVERHEAD_REDUCTION: ON
8881 00:57:06.805792 CMD_PICG_NEW_MODE: OFF
8882 00:57:06.808630 XRTWTW_NEW_MODE: ON
8883 00:57:06.811354 XRTRTR_NEW_MODE: ON
8884 00:57:06.811436 TX_TRACKING: ON
8885 00:57:06.815351 RDSEL_TRACKING: OFF
8886 00:57:06.815431 DQS Precalculation for DVFS: ON
8887 00:57:06.818178 RX_TRACKING: OFF
8888 00:57:06.818252 HW_GATING DBG: ON
8889 00:57:06.821518 ZQCS_ENABLE_LP4: ON
8890 00:57:06.825231 RX_PICG_NEW_MODE: ON
8891 00:57:06.825312 TX_PICG_NEW_MODE: ON
8892 00:57:06.828616 ENABLE_RX_DCM_DPHY: ON
8893 00:57:06.831453 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8894 00:57:06.831534 DUMMY_READ_FOR_TRACKING: OFF
8895 00:57:06.835789 !!! SPM_CONTROL_AFTERK: OFF
8896 00:57:06.838456 !!! SPM could not control APHY
8897 00:57:06.841623 IMPEDANCE_TRACKING: ON
8898 00:57:06.841703 TEMP_SENSOR: ON
8899 00:57:06.845179 HW_SAVE_FOR_SR: OFF
8900 00:57:06.847823 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8901 00:57:06.851210 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8902 00:57:06.851290 Read ODT Tracking: ON
8903 00:57:06.854797 Refresh Rate DeBounce: ON
8904 00:57:06.857820 DFS_NO_QUEUE_FLUSH: ON
8905 00:57:06.860653 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8906 00:57:06.860756 ENABLE_DFS_RUNTIME_MRW: OFF
8907 00:57:06.864529 DDR_RESERVE_NEW_MODE: ON
8908 00:57:06.867973 MR_CBT_SWITCH_FREQ: ON
8909 00:57:06.868053 =========================
8910 00:57:06.887842 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8911 00:57:06.891059 dram_init: ddr_geometry: 0
8912 00:57:06.909049 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8913 00:57:06.912282 dram_init: dram init end (result: 0)
8914 00:57:06.919181 DRAM-K: Full calibration passed in 23375 msecs
8915 00:57:06.922329 MRC: failed to locate region type 0.
8916 00:57:06.922407 DRAM rank0 size:0x80000000,
8917 00:57:06.925058 DRAM rank1 size=0x80000000
8918 00:57:06.935447 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8919 00:57:06.941772 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8920 00:57:06.948078 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8921 00:57:06.958558 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8922 00:57:06.958639 DRAM rank0 size:0x80000000,
8923 00:57:06.961737 DRAM rank1 size=0x80000000
8924 00:57:06.961842 CBMEM:
8925 00:57:06.965041 IMD: root @ 0xfffff000 254 entries.
8926 00:57:06.968456 IMD: root @ 0xffffec00 62 entries.
8927 00:57:06.971546 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8928 00:57:06.978661 WARNING: RO_VPD is uninitialized or empty.
8929 00:57:06.981497 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8930 00:57:06.989606 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8931 00:57:07.001273 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8932 00:57:07.012934 BS: romstage times (exec / console): total (unknown) / 22920 ms
8933 00:57:07.013139
8934 00:57:07.013333
8935 00:57:07.022491 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8936 00:57:07.026137 ARM64: Exception handlers installed.
8937 00:57:07.029433 ARM64: Testing exception
8938 00:57:07.032610 ARM64: Done test exception
8939 00:57:07.033066 Enumerating buses...
8940 00:57:07.036122 Show all devs... Before device enumeration.
8941 00:57:07.039125 Root Device: enabled 1
8942 00:57:07.042471 CPU_CLUSTER: 0: enabled 1
8943 00:57:07.042894 CPU: 00: enabled 1
8944 00:57:07.046268 Compare with tree...
8945 00:57:07.046691 Root Device: enabled 1
8946 00:57:07.049074 CPU_CLUSTER: 0: enabled 1
8947 00:57:07.052681 CPU: 00: enabled 1
8948 00:57:07.053150 Root Device scanning...
8949 00:57:07.055936 scan_static_bus for Root Device
8950 00:57:07.059679 CPU_CLUSTER: 0 enabled
8951 00:57:07.062588 scan_static_bus for Root Device done
8952 00:57:07.065914 scan_bus: bus Root Device finished in 8 msecs
8953 00:57:07.066328 done
8954 00:57:07.072481 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8955 00:57:07.075638 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8956 00:57:07.082667 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8957 00:57:07.085391 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8958 00:57:07.088817 Allocating resources...
8959 00:57:07.092126 Reading resources...
8960 00:57:07.095497 Root Device read_resources bus 0 link: 0
8961 00:57:07.099442 DRAM rank0 size:0x80000000,
8962 00:57:07.099856 DRAM rank1 size=0x80000000
8963 00:57:07.102387 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8964 00:57:07.105906 CPU: 00 missing read_resources
8965 00:57:07.112297 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8966 00:57:07.115540 Root Device read_resources bus 0 link: 0 done
8967 00:57:07.115957 Done reading resources.
8968 00:57:07.122375 Show resources in subtree (Root Device)...After reading.
8969 00:57:07.125130 Root Device child on link 0 CPU_CLUSTER: 0
8970 00:57:07.128582 CPU_CLUSTER: 0 child on link 0 CPU: 00
8971 00:57:07.138589 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8972 00:57:07.139006 CPU: 00
8973 00:57:07.141722 Root Device assign_resources, bus 0 link: 0
8974 00:57:07.145138 CPU_CLUSTER: 0 missing set_resources
8975 00:57:07.151846 Root Device assign_resources, bus 0 link: 0 done
8976 00:57:07.152257 Done setting resources.
8977 00:57:07.158270 Show resources in subtree (Root Device)...After assigning values.
8978 00:57:07.161390 Root Device child on link 0 CPU_CLUSTER: 0
8979 00:57:07.164816 CPU_CLUSTER: 0 child on link 0 CPU: 00
8980 00:57:07.174775 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8981 00:57:07.175191 CPU: 00
8982 00:57:07.178146 Done allocating resources.
8983 00:57:07.185178 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8984 00:57:07.185592 Enabling resources...
8985 00:57:07.186022 done.
8986 00:57:07.191663 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8987 00:57:07.194492 Initializing devices...
8988 00:57:07.194908 Root Device init
8989 00:57:07.198072 init hardware done!
8990 00:57:07.198484 0x00000018: ctrlr->caps
8991 00:57:07.201227 52.000 MHz: ctrlr->f_max
8992 00:57:07.204795 0.400 MHz: ctrlr->f_min
8993 00:57:07.205216 0x40ff8080: ctrlr->voltages
8994 00:57:07.207952 sclk: 390625
8995 00:57:07.208390 Bus Width = 1
8996 00:57:07.208851 sclk: 390625
8997 00:57:07.211131 Bus Width = 1
8998 00:57:07.211550 Early init status = 3
8999 00:57:07.218228 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9000 00:57:07.221325 in-header: 03 fc 00 00 01 00 00 00
9001 00:57:07.224375 in-data: 00
9002 00:57:07.227770 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9003 00:57:07.233024 in-header: 03 fd 00 00 00 00 00 00
9004 00:57:07.235849 in-data:
9005 00:57:07.239561 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9006 00:57:07.242934 in-header: 03 fc 00 00 01 00 00 00
9007 00:57:07.246316 in-data: 00
9008 00:57:07.249271 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9009 00:57:07.255002 in-header: 03 fd 00 00 00 00 00 00
9010 00:57:07.258384 in-data:
9011 00:57:07.261189 [SSUSB] Setting up USB HOST controller...
9012 00:57:07.264746 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9013 00:57:07.267677 [SSUSB] phy power-on done.
9014 00:57:07.271503 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9015 00:57:07.277760 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9016 00:57:07.281194 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9017 00:57:07.287666 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9018 00:57:07.294735 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9019 00:57:07.301544 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9020 00:57:07.307700 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9021 00:57:07.314572 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9022 00:57:07.317745 SPM: binary array size = 0x9dc
9023 00:57:07.320485 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9024 00:57:07.327349 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9025 00:57:07.333954 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9026 00:57:07.340298 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9027 00:57:07.343864 configure_display: Starting display init
9028 00:57:07.378015 anx7625_power_on_init: Init interface.
9029 00:57:07.380765 anx7625_disable_pd_protocol: Disabled PD feature.
9030 00:57:07.384020 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9031 00:57:07.411903 anx7625_start_dp_work: Secure OCM version=00
9032 00:57:07.415349 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9033 00:57:07.429959 sp_tx_get_edid_block: EDID Block = 1
9034 00:57:07.532613 Extracted contents:
9035 00:57:07.536075 header: 00 ff ff ff ff ff ff 00
9036 00:57:07.539358 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9037 00:57:07.542637 version: 01 04
9038 00:57:07.546615 basic params: 95 1f 11 78 0a
9039 00:57:07.549281 chroma info: 76 90 94 55 54 90 27 21 50 54
9040 00:57:07.552580 established: 00 00 00
9041 00:57:07.558941 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9042 00:57:07.563026 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9043 00:57:07.569033 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9044 00:57:07.575503 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9045 00:57:07.582715 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9046 00:57:07.585683 extensions: 00
9047 00:57:07.585783 checksum: fb
9048 00:57:07.585863
9049 00:57:07.589253 Manufacturer: IVO Model 57d Serial Number 0
9050 00:57:07.592096 Made week 0 of 2020
9051 00:57:07.592215 EDID version: 1.4
9052 00:57:07.595960 Digital display
9053 00:57:07.598868 6 bits per primary color channel
9054 00:57:07.599005 DisplayPort interface
9055 00:57:07.602224 Maximum image size: 31 cm x 17 cm
9056 00:57:07.605278 Gamma: 220%
9057 00:57:07.605453 Check DPMS levels
9058 00:57:07.608937 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9059 00:57:07.616057 First detailed timing is preferred timing
9060 00:57:07.616257 Established timings supported:
9061 00:57:07.618943 Standard timings supported:
9062 00:57:07.622471 Detailed timings
9063 00:57:07.625664 Hex of detail: 383680a07038204018303c0035ae10000019
9064 00:57:07.632387 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9065 00:57:07.636185 0780 0798 07c8 0820 hborder 0
9066 00:57:07.638676 0438 043b 0447 0458 vborder 0
9067 00:57:07.642378 -hsync -vsync
9068 00:57:07.642793 Did detailed timing
9069 00:57:07.648933 Hex of detail: 000000000000000000000000000000000000
9070 00:57:07.652220 Manufacturer-specified data, tag 0
9071 00:57:07.655671 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9072 00:57:07.658502 ASCII string: InfoVision
9073 00:57:07.662121 Hex of detail: 000000fe00523134304e574635205248200a
9074 00:57:07.665055 ASCII string: R140NWF5 RH
9075 00:57:07.665137 Checksum
9076 00:57:07.668262 Checksum: 0xfb (valid)
9077 00:57:07.671261 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9078 00:57:07.674895 DSI data_rate: 832800000 bps
9079 00:57:07.682031 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9080 00:57:07.685418 anx7625_parse_edid: pixelclock(138800).
9081 00:57:07.688434 hactive(1920), hsync(48), hfp(24), hbp(88)
9082 00:57:07.691867 vactive(1080), vsync(12), vfp(3), vbp(17)
9083 00:57:07.695180 anx7625_dsi_config: config dsi.
9084 00:57:07.701841 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9085 00:57:07.715436 anx7625_dsi_config: success to config DSI
9086 00:57:07.718865 anx7625_dp_start: MIPI phy setup OK.
9087 00:57:07.721796 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9088 00:57:07.724842 mtk_ddp_mode_set invalid vrefresh 60
9089 00:57:07.729025 main_disp_path_setup
9090 00:57:07.729682 ovl_layer_smi_id_en
9091 00:57:07.731639 ovl_layer_smi_id_en
9092 00:57:07.732109 ccorr_config
9093 00:57:07.732581 aal_config
9094 00:57:07.735363 gamma_config
9095 00:57:07.735830 postmask_config
9096 00:57:07.737862 dither_config
9097 00:57:07.740810 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9098 00:57:07.748203 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9099 00:57:07.751594 Root Device init finished in 553 msecs
9100 00:57:07.754456 CPU_CLUSTER: 0 init
9101 00:57:07.760694 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9102 00:57:07.767394 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9103 00:57:07.767560 APU_MBOX 0x190000b0 = 0x10001
9104 00:57:07.771137 APU_MBOX 0x190001b0 = 0x10001
9105 00:57:07.774622 APU_MBOX 0x190005b0 = 0x10001
9106 00:57:07.777803 APU_MBOX 0x190006b0 = 0x10001
9107 00:57:07.780968 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9108 00:57:07.794197 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9109 00:57:07.806644 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9110 00:57:07.813187 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9111 00:57:07.824465 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9112 00:57:07.833718 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9113 00:57:07.836783 CPU_CLUSTER: 0 init finished in 81 msecs
9114 00:57:07.840164 Devices initialized
9115 00:57:07.843440 Show all devs... After init.
9116 00:57:07.843915 Root Device: enabled 1
9117 00:57:07.846890 CPU_CLUSTER: 0: enabled 1
9118 00:57:07.850492 CPU: 00: enabled 1
9119 00:57:07.854020 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9120 00:57:07.856780 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9121 00:57:07.860248 ELOG: NV offset 0x57f000 size 0x1000
9122 00:57:07.866660 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9123 00:57:07.873562 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9124 00:57:07.877164 ELOG: Event(17) added with size 13 at 2024-01-19 00:57:09 UTC
9125 00:57:07.883506 out: cmd=0x121: 03 db 21 01 00 00 00 00
9126 00:57:07.886860 in-header: 03 2b 00 00 2c 00 00 00
9127 00:57:07.899890 in-data: 38 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9128 00:57:07.903295 ELOG: Event(A1) added with size 10 at 2024-01-19 00:57:09 UTC
9129 00:57:07.910579 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9130 00:57:07.916968 ELOG: Event(A0) added with size 9 at 2024-01-19 00:57:09 UTC
9131 00:57:07.920537 elog_add_boot_reason: Logged dev mode boot
9132 00:57:07.926522 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9133 00:57:07.927035 Finalize devices...
9134 00:57:07.929617 Devices finalized
9135 00:57:07.933190 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9136 00:57:07.936821 Writing coreboot table at 0xffe64000
9137 00:57:07.939631 0. 000000000010a000-0000000000113fff: RAMSTAGE
9138 00:57:07.947016 1. 0000000040000000-00000000400fffff: RAM
9139 00:57:07.950090 2. 0000000040100000-000000004032afff: RAMSTAGE
9140 00:57:07.952548 3. 000000004032b000-00000000545fffff: RAM
9141 00:57:07.956438 4. 0000000054600000-000000005465ffff: BL31
9142 00:57:07.959654 5. 0000000054660000-00000000ffe63fff: RAM
9143 00:57:07.967216 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9144 00:57:07.969404 7. 0000000100000000-000000013fffffff: RAM
9145 00:57:07.973585 Passing 5 GPIOs to payload:
9146 00:57:07.976086 NAME | PORT | POLARITY | VALUE
9147 00:57:07.983249 EC in RW | 0x000000aa | low | undefined
9148 00:57:07.986228 EC interrupt | 0x00000005 | low | undefined
9149 00:57:07.989218 TPM interrupt | 0x000000ab | high | undefined
9150 00:57:07.995689 SD card detect | 0x00000011 | high | undefined
9151 00:57:07.999367 speaker enable | 0x00000093 | high | undefined
9152 00:57:08.002835 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9153 00:57:08.005928 in-header: 03 ef 00 00 02 00 00 00
9154 00:57:08.009507 in-data: 0c 00
9155 00:57:08.012367 ADC[4]: Raw value=668590 ID=5
9156 00:57:08.012802 ADC[3]: Raw value=212549 ID=1
9157 00:57:08.015481 RAM Code: 0x51
9158 00:57:08.018681 ADC[6]: Raw value=74410 ID=0
9159 00:57:08.018762 ADC[5]: Raw value=211444 ID=1
9160 00:57:08.021875 SKU Code: 0x1
9161 00:57:08.029411 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2788
9162 00:57:08.029491 coreboot table: 964 bytes.
9163 00:57:08.031873 IMD ROOT 0. 0xfffff000 0x00001000
9164 00:57:08.035022 IMD SMALL 1. 0xffffe000 0x00001000
9165 00:57:08.038620 RO MCACHE 2. 0xffffc000 0x00001104
9166 00:57:08.041902 CONSOLE 3. 0xfff7c000 0x00080000
9167 00:57:08.045461 FMAP 4. 0xfff7b000 0x00000452
9168 00:57:08.049746 TIME STAMP 5. 0xfff7a000 0x00000910
9169 00:57:08.052118 VBOOT WORK 6. 0xfff66000 0x00014000
9170 00:57:08.055441 RAMOOPS 7. 0xffe66000 0x00100000
9171 00:57:08.058775 COREBOOT 8. 0xffe64000 0x00002000
9172 00:57:08.062632 IMD small region:
9173 00:57:08.065899 IMD ROOT 0. 0xffffec00 0x00000400
9174 00:57:08.068614 VPD 1. 0xffffeb80 0x0000006c
9175 00:57:08.072130 MMC STATUS 2. 0xffffeb60 0x00000004
9176 00:57:08.075458 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9177 00:57:08.078952 Probing TPM: done!
9178 00:57:08.082047 Connected to device vid:did:rid of 1ae0:0028:00
9179 00:57:08.093421 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9180 00:57:08.096438 Initialized TPM device CR50 revision 0
9181 00:57:08.099806 Checking cr50 for pending updates
9182 00:57:08.103458 Reading cr50 TPM mode
9183 00:57:08.112168 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9184 00:57:08.118726 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9185 00:57:08.158720 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9186 00:57:08.161857 Checking segment from ROM address 0x40100000
9187 00:57:08.165606 Checking segment from ROM address 0x4010001c
9188 00:57:08.172314 Loading segment from ROM address 0x40100000
9189 00:57:08.172485 code (compression=0)
9190 00:57:08.183699 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9191 00:57:08.188256 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9192 00:57:08.188338 it's not compressed!
9193 00:57:08.195357 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9194 00:57:08.201785 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9195 00:57:08.218737 Loading segment from ROM address 0x4010001c
9196 00:57:08.218899 Entry Point 0x80000000
9197 00:57:08.222437 Loaded segments
9198 00:57:08.225684 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9199 00:57:08.232630 Jumping to boot code at 0x80000000(0xffe64000)
9200 00:57:08.238846 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9201 00:57:08.245545 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9202 00:57:08.253700 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9203 00:57:08.257146 Checking segment from ROM address 0x40100000
9204 00:57:08.260219 Checking segment from ROM address 0x4010001c
9205 00:57:08.266812 Loading segment from ROM address 0x40100000
9206 00:57:08.267052 code (compression=1)
9207 00:57:08.273835 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9208 00:57:08.284002 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9209 00:57:08.284469 using LZMA
9210 00:57:08.291937 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9211 00:57:08.299196 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9212 00:57:08.301960 Loading segment from ROM address 0x4010001c
9213 00:57:08.302423 Entry Point 0x54601000
9214 00:57:08.305601 Loaded segments
9215 00:57:08.309169 NOTICE: MT8192 bl31_setup
9216 00:57:08.315568 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9217 00:57:08.318959 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9218 00:57:08.322365 WARNING: region 0:
9219 00:57:08.325737 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9220 00:57:08.326201 WARNING: region 1:
9221 00:57:08.332375 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9222 00:57:08.336075 WARNING: region 2:
9223 00:57:08.339147 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9224 00:57:08.342245 WARNING: region 3:
9225 00:57:08.345336 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9226 00:57:08.348253 WARNING: region 4:
9227 00:57:08.355933 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9228 00:57:08.356015 WARNING: region 5:
9229 00:57:08.358639 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9230 00:57:08.361960 WARNING: region 6:
9231 00:57:08.365942 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9232 00:57:08.368476 WARNING: region 7:
9233 00:57:08.372155 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9234 00:57:08.378546 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9235 00:57:08.381990 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9236 00:57:08.384931 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9237 00:57:08.391987 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9238 00:57:08.395856 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9239 00:57:08.398397 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9240 00:57:08.405382 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9241 00:57:08.408176 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9242 00:57:08.415850 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9243 00:57:08.418758 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9244 00:57:08.422912 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9245 00:57:08.428623 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9246 00:57:08.432315 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9247 00:57:08.435811 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9248 00:57:08.442300 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9249 00:57:08.445796 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9250 00:57:08.452570 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9251 00:57:08.455744 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9252 00:57:08.458742 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9253 00:57:08.465513 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9254 00:57:08.469213 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9255 00:57:08.472291 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9256 00:57:08.478638 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9257 00:57:08.482485 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9258 00:57:08.488840 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9259 00:57:08.492166 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9260 00:57:08.495685 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9261 00:57:08.502497 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9262 00:57:08.506535 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9263 00:57:08.512261 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9264 00:57:08.515757 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9265 00:57:08.518953 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9266 00:57:08.525776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9267 00:57:08.528583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9268 00:57:08.532108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9269 00:57:08.535816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9270 00:57:08.541869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9271 00:57:08.545346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9272 00:57:08.548510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9273 00:57:08.552161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9274 00:57:08.558651 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9275 00:57:08.561943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9276 00:57:08.564788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9277 00:57:08.568498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9278 00:57:08.575116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9279 00:57:08.578345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9280 00:57:08.582414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9281 00:57:08.585630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9282 00:57:08.592444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9283 00:57:08.595430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9284 00:57:08.601594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9285 00:57:08.605238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9286 00:57:08.611980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9287 00:57:08.615518 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9288 00:57:08.621114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9289 00:57:08.625725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9290 00:57:08.628614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9291 00:57:08.635551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9292 00:57:08.638753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9293 00:57:08.645539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9294 00:57:08.649267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9295 00:57:08.652899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9296 00:57:08.659032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9297 00:57:08.662240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9298 00:57:08.668808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9299 00:57:08.672147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9300 00:57:08.678679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9301 00:57:08.682083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9302 00:57:08.685403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9303 00:57:08.691834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9304 00:57:08.695258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9305 00:57:08.701608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9306 00:57:08.705090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9307 00:57:08.711502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9308 00:57:08.714975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9309 00:57:08.718864 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9310 00:57:08.725133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9311 00:57:08.729282 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9312 00:57:08.735165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9313 00:57:08.738301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9314 00:57:08.745166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9315 00:57:08.748446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9316 00:57:08.755404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9317 00:57:08.758410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9318 00:57:08.762222 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9319 00:57:08.768966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9320 00:57:08.772191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9321 00:57:08.778644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9322 00:57:08.781560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9323 00:57:08.788177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9324 00:57:08.792183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9325 00:57:08.794894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9326 00:57:08.801555 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9327 00:57:08.805733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9328 00:57:08.812766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9329 00:57:08.814814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9330 00:57:08.818264 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9331 00:57:08.825411 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9332 00:57:08.828765 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9333 00:57:08.832072 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9334 00:57:08.835027 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9335 00:57:08.841519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9336 00:57:08.845106 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9337 00:57:08.852220 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9338 00:57:08.855108 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9339 00:57:08.858862 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9340 00:57:08.865511 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9341 00:57:08.869565 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9342 00:57:08.874924 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9343 00:57:08.878937 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9344 00:57:08.881998 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9345 00:57:08.888355 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9346 00:57:08.891811 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9347 00:57:08.898679 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9348 00:57:08.902074 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9349 00:57:08.905544 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9350 00:57:08.911920 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9351 00:57:08.915335 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9352 00:57:08.918833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9353 00:57:08.925153 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9354 00:57:08.928028 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9355 00:57:08.931745 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9356 00:57:08.934928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9357 00:57:08.941373 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9358 00:57:08.945006 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9359 00:57:08.948181 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9360 00:57:08.955376 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9361 00:57:08.958749 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9362 00:57:08.965026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9363 00:57:08.967769 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9364 00:57:08.971425 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9365 00:57:08.977983 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9366 00:57:08.981881 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9367 00:57:08.985086 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9368 00:57:08.991245 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9369 00:57:08.994511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9370 00:57:09.001110 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9371 00:57:09.004828 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9372 00:57:09.008836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9373 00:57:09.015238 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9374 00:57:09.018061 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9375 00:57:09.024818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9376 00:57:09.028221 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9377 00:57:09.031684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9378 00:57:09.038080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9379 00:57:09.041265 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9380 00:57:09.045023 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9381 00:57:09.050955 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9382 00:57:09.055082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9383 00:57:09.061040 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9384 00:57:09.064400 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9385 00:57:09.067461 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9386 00:57:09.074055 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9387 00:57:09.077953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9388 00:57:09.083918 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9389 00:57:09.087765 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9390 00:57:09.091005 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9391 00:57:09.098410 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9392 00:57:09.100968 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9393 00:57:09.107831 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9394 00:57:09.111392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9395 00:57:09.113978 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9396 00:57:09.120637 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9397 00:57:09.124361 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9398 00:57:09.131314 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9399 00:57:09.134151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9400 00:57:09.137538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9401 00:57:09.143948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9402 00:57:09.147179 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9403 00:57:09.150821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9404 00:57:09.157085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9405 00:57:09.160432 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9406 00:57:09.167361 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9407 00:57:09.170215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9408 00:57:09.174256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9409 00:57:09.180683 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9410 00:57:09.183831 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9411 00:57:09.190157 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9412 00:57:09.193566 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9413 00:57:09.197201 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9414 00:57:09.203894 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9415 00:57:09.207210 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9416 00:57:09.213788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9417 00:57:09.217489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9418 00:57:09.220883 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9419 00:57:09.227220 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9420 00:57:09.230479 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9421 00:57:09.236872 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9422 00:57:09.240216 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9423 00:57:09.243386 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9424 00:57:09.249958 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9425 00:57:09.253815 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9426 00:57:09.259963 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9427 00:57:09.263927 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9428 00:57:09.266530 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9429 00:57:09.274278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9430 00:57:09.276986 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9431 00:57:09.283248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9432 00:57:09.287328 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9433 00:57:09.293220 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9434 00:57:09.296491 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9435 00:57:09.300009 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9436 00:57:09.306830 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9437 00:57:09.309834 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9438 00:57:09.316269 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9439 00:57:09.319821 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9440 00:57:09.326158 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9441 00:57:09.330657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9442 00:57:09.332896 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9443 00:57:09.340018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9444 00:57:09.343241 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9445 00:57:09.349685 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9446 00:57:09.352466 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9447 00:57:09.359541 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9448 00:57:09.362569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9449 00:57:09.365762 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9450 00:57:09.372455 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9451 00:57:09.375905 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9452 00:57:09.382528 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9453 00:57:09.385465 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9454 00:57:09.392070 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9455 00:57:09.395609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9456 00:57:09.398631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9457 00:57:09.405313 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9458 00:57:09.408933 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9459 00:57:09.415357 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9460 00:57:09.418914 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9461 00:57:09.422973 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9462 00:57:09.428875 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9463 00:57:09.432388 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9464 00:57:09.435544 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9465 00:57:09.441678 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9466 00:57:09.445098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9467 00:57:09.448803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9468 00:57:09.452576 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9469 00:57:09.458113 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9470 00:57:09.461302 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9471 00:57:09.468503 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9472 00:57:09.471302 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9473 00:57:09.474735 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9474 00:57:09.481421 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9475 00:57:09.485164 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9476 00:57:09.491487 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9477 00:57:09.494666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9478 00:57:09.497789 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9479 00:57:09.504350 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9480 00:57:09.508099 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9481 00:57:09.511021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9482 00:57:09.517616 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9483 00:57:09.521471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9484 00:57:09.524207 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9485 00:57:09.530790 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9486 00:57:09.534224 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9487 00:57:09.537564 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9488 00:57:09.544274 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9489 00:57:09.547434 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9490 00:57:09.553937 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9491 00:57:09.557990 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9492 00:57:09.561585 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9493 00:57:09.567244 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9494 00:57:09.570853 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9495 00:57:09.577398 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9496 00:57:09.581225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9497 00:57:09.583511 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9498 00:57:09.590719 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9499 00:57:09.593945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9500 00:57:09.597382 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9501 00:57:09.603425 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9502 00:57:09.606590 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9503 00:57:09.610287 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9504 00:57:09.613446 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9505 00:57:09.620462 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9506 00:57:09.623620 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9507 00:57:09.627075 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9508 00:57:09.630227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9509 00:57:09.636603 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9510 00:57:09.639822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9511 00:57:09.643939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9512 00:57:09.646263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9513 00:57:09.653233 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9514 00:57:09.656482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9515 00:57:09.659407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9516 00:57:09.666137 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9517 00:57:09.669514 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9518 00:57:09.676173 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9519 00:57:09.679523 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9520 00:57:09.686062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9521 00:57:09.689582 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9522 00:57:09.692422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9523 00:57:09.699628 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9524 00:57:09.703188 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9525 00:57:09.709425 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9526 00:57:09.712743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9527 00:57:09.715997 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9528 00:57:09.723706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9529 00:57:09.725793 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9530 00:57:09.733202 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9531 00:57:09.735553 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9532 00:57:09.739084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9533 00:57:09.745882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9534 00:57:09.748771 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9535 00:57:09.755527 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9536 00:57:09.759227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9537 00:57:09.765824 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9538 00:57:09.769073 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9539 00:57:09.772200 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9540 00:57:09.779202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9541 00:57:09.781450 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9542 00:57:09.788180 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9543 00:57:09.791611 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9544 00:57:09.798155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9545 00:57:09.801779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9546 00:57:09.804824 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9547 00:57:09.811821 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9548 00:57:09.814959 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9549 00:57:09.821429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9550 00:57:09.825246 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9551 00:57:09.827926 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9552 00:57:09.834960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9553 00:57:09.838103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9554 00:57:09.844940 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9555 00:57:09.847800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9556 00:57:09.850996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9557 00:57:09.857725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9558 00:57:09.861844 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9559 00:57:09.867655 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9560 00:57:09.870958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9561 00:57:09.877709 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9562 00:57:09.880777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9563 00:57:09.884431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9564 00:57:09.890925 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9565 00:57:09.894259 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9566 00:57:09.900692 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9567 00:57:09.904445 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9568 00:57:09.907318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9569 00:57:09.914005 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9570 00:57:09.917551 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9571 00:57:09.924000 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9572 00:57:09.927499 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9573 00:57:09.931035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9574 00:57:09.937195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9575 00:57:09.940654 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9576 00:57:09.946974 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9577 00:57:09.950353 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9578 00:57:09.956914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9579 00:57:09.960309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9580 00:57:09.963847 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9581 00:57:09.970536 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9582 00:57:09.974083 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9583 00:57:09.980055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9584 00:57:09.983522 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9585 00:57:09.987295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9586 00:57:09.993542 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9587 00:57:09.996572 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9588 00:57:10.003837 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9589 00:57:10.006890 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9590 00:57:10.013149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9591 00:57:10.016924 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9592 00:57:10.019938 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9593 00:57:10.027508 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9594 00:57:10.029842 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9595 00:57:10.036342 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9596 00:57:10.040039 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9597 00:57:10.046401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9598 00:57:10.049498 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9599 00:57:10.056594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9600 00:57:10.059828 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9601 00:57:10.062827 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9602 00:57:10.069676 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9603 00:57:10.072987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9604 00:57:10.079378 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9605 00:57:10.083181 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9606 00:57:10.089274 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9607 00:57:10.092808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9608 00:57:10.096972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9609 00:57:10.103184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9610 00:57:10.106515 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9611 00:57:10.112843 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9612 00:57:10.116211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9613 00:57:10.122450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9614 00:57:10.126125 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9615 00:57:10.129673 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9616 00:57:10.135680 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9617 00:57:10.139174 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9618 00:57:10.145699 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9619 00:57:10.150319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9620 00:57:10.155621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9621 00:57:10.159008 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9622 00:57:10.162419 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9623 00:57:10.169306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9624 00:57:10.172377 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9625 00:57:10.179068 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9626 00:57:10.182242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9627 00:57:10.189178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9628 00:57:10.192229 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9629 00:57:10.199239 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9630 00:57:10.202474 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9631 00:57:10.205556 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9632 00:57:10.212258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9633 00:57:10.215020 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9634 00:57:10.222073 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9635 00:57:10.225359 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9636 00:57:10.228811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9637 00:57:10.234967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9638 00:57:10.238636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9639 00:57:10.245083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9640 00:57:10.248038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9641 00:57:10.255293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9642 00:57:10.258262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9643 00:57:10.265250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9644 00:57:10.268006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9645 00:57:10.274579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9646 00:57:10.278046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9647 00:57:10.284511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9648 00:57:10.287924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9649 00:57:10.294734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9650 00:57:10.298272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9651 00:57:10.304204 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9652 00:57:10.307752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9653 00:57:10.314775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9654 00:57:10.317924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9655 00:57:10.324314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9656 00:57:10.327699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9657 00:57:10.333886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9658 00:57:10.337833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9659 00:57:10.343908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9660 00:57:10.347368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9661 00:57:10.354008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9662 00:57:10.357603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9663 00:57:10.363619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9664 00:57:10.367435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9665 00:57:10.374341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9666 00:57:10.377285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9667 00:57:10.384750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9668 00:57:10.387533 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9669 00:57:10.390467 INFO: [APUAPC] vio 0
9670 00:57:10.394082 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9671 00:57:10.400595 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9672 00:57:10.404042 INFO: [APUAPC] D0_APC_0: 0x400510
9673 00:57:10.404126 INFO: [APUAPC] D0_APC_1: 0x0
9674 00:57:10.407046 INFO: [APUAPC] D0_APC_2: 0x1540
9675 00:57:10.410903 INFO: [APUAPC] D0_APC_3: 0x0
9676 00:57:10.413541 INFO: [APUAPC] D1_APC_0: 0xffffffff
9677 00:57:10.417298 INFO: [APUAPC] D1_APC_1: 0xffffffff
9678 00:57:10.420336 INFO: [APUAPC] D1_APC_2: 0x3fffff
9679 00:57:10.424421 INFO: [APUAPC] D1_APC_3: 0x0
9680 00:57:10.427345 INFO: [APUAPC] D2_APC_0: 0xffffffff
9681 00:57:10.429895 INFO: [APUAPC] D2_APC_1: 0xffffffff
9682 00:57:10.433479 INFO: [APUAPC] D2_APC_2: 0x3fffff
9683 00:57:10.436961 INFO: [APUAPC] D2_APC_3: 0x0
9684 00:57:10.440187 INFO: [APUAPC] D3_APC_0: 0xffffffff
9685 00:57:10.443301 INFO: [APUAPC] D3_APC_1: 0xffffffff
9686 00:57:10.446745 INFO: [APUAPC] D3_APC_2: 0x3fffff
9687 00:57:10.450260 INFO: [APUAPC] D3_APC_3: 0x0
9688 00:57:10.453208 INFO: [APUAPC] D4_APC_0: 0xffffffff
9689 00:57:10.456661 INFO: [APUAPC] D4_APC_1: 0xffffffff
9690 00:57:10.459661 INFO: [APUAPC] D4_APC_2: 0x3fffff
9691 00:57:10.462902 INFO: [APUAPC] D4_APC_3: 0x0
9692 00:57:10.466892 INFO: [APUAPC] D5_APC_0: 0xffffffff
9693 00:57:10.470336 INFO: [APUAPC] D5_APC_1: 0xffffffff
9694 00:57:10.472943 INFO: [APUAPC] D5_APC_2: 0x3fffff
9695 00:57:10.476192 INFO: [APUAPC] D5_APC_3: 0x0
9696 00:57:10.480333 INFO: [APUAPC] D6_APC_0: 0xffffffff
9697 00:57:10.483591 INFO: [APUAPC] D6_APC_1: 0xffffffff
9698 00:57:10.487026 INFO: [APUAPC] D6_APC_2: 0x3fffff
9699 00:57:10.489391 INFO: [APUAPC] D6_APC_3: 0x0
9700 00:57:10.492557 INFO: [APUAPC] D7_APC_0: 0xffffffff
9701 00:57:10.496652 INFO: [APUAPC] D7_APC_1: 0xffffffff
9702 00:57:10.499188 INFO: [APUAPC] D7_APC_2: 0x3fffff
9703 00:57:10.502759 INFO: [APUAPC] D7_APC_3: 0x0
9704 00:57:10.506134 INFO: [APUAPC] D8_APC_0: 0xffffffff
9705 00:57:10.509031 INFO: [APUAPC] D8_APC_1: 0xffffffff
9706 00:57:10.512500 INFO: [APUAPC] D8_APC_2: 0x3fffff
9707 00:57:10.515907 INFO: [APUAPC] D8_APC_3: 0x0
9708 00:57:10.519241 INFO: [APUAPC] D9_APC_0: 0xffffffff
9709 00:57:10.522333 INFO: [APUAPC] D9_APC_1: 0xffffffff
9710 00:57:10.526124 INFO: [APUAPC] D9_APC_2: 0x3fffff
9711 00:57:10.528916 INFO: [APUAPC] D9_APC_3: 0x0
9712 00:57:10.532540 INFO: [APUAPC] D10_APC_0: 0xffffffff
9713 00:57:10.535875 INFO: [APUAPC] D10_APC_1: 0xffffffff
9714 00:57:10.538712 INFO: [APUAPC] D10_APC_2: 0x3fffff
9715 00:57:10.542504 INFO: [APUAPC] D10_APC_3: 0x0
9716 00:57:10.545810 INFO: [APUAPC] D11_APC_0: 0xffffffff
9717 00:57:10.548798 INFO: [APUAPC] D11_APC_1: 0xffffffff
9718 00:57:10.552508 INFO: [APUAPC] D11_APC_2: 0x3fffff
9719 00:57:10.555284 INFO: [APUAPC] D11_APC_3: 0x0
9720 00:57:10.558898 INFO: [APUAPC] D12_APC_0: 0xffffffff
9721 00:57:10.561856 INFO: [APUAPC] D12_APC_1: 0xffffffff
9722 00:57:10.565022 INFO: [APUAPC] D12_APC_2: 0x3fffff
9723 00:57:10.569250 INFO: [APUAPC] D12_APC_3: 0x0
9724 00:57:10.572823 INFO: [APUAPC] D13_APC_0: 0xffffffff
9725 00:57:10.575385 INFO: [APUAPC] D13_APC_1: 0xffffffff
9726 00:57:10.578372 INFO: [APUAPC] D13_APC_2: 0x3fffff
9727 00:57:10.582093 INFO: [APUAPC] D13_APC_3: 0x0
9728 00:57:10.584873 INFO: [APUAPC] D14_APC_0: 0xffffffff
9729 00:57:10.588453 INFO: [APUAPC] D14_APC_1: 0xffffffff
9730 00:57:10.592086 INFO: [APUAPC] D14_APC_2: 0x3fffff
9731 00:57:10.595230 INFO: [APUAPC] D14_APC_3: 0x0
9732 00:57:10.598410 INFO: [APUAPC] D15_APC_0: 0xffffffff
9733 00:57:10.601748 INFO: [APUAPC] D15_APC_1: 0xffffffff
9734 00:57:10.605133 INFO: [APUAPC] D15_APC_2: 0x3fffff
9735 00:57:10.608908 INFO: [APUAPC] D15_APC_3: 0x0
9736 00:57:10.612008 INFO: [APUAPC] APC_CON: 0x4
9737 00:57:10.614990 INFO: [NOCDAPC] D0_APC_0: 0x0
9738 00:57:10.618828 INFO: [NOCDAPC] D0_APC_1: 0x0
9739 00:57:10.618912 INFO: [NOCDAPC] D1_APC_0: 0x0
9740 00:57:10.621760 INFO: [NOCDAPC] D1_APC_1: 0xfff
9741 00:57:10.625825 INFO: [NOCDAPC] D2_APC_0: 0x0
9742 00:57:10.628526 INFO: [NOCDAPC] D2_APC_1: 0xfff
9743 00:57:10.631555 INFO: [NOCDAPC] D3_APC_0: 0x0
9744 00:57:10.635159 INFO: [NOCDAPC] D3_APC_1: 0xfff
9745 00:57:10.639448 INFO: [NOCDAPC] D4_APC_0: 0x0
9746 00:57:10.641501 INFO: [NOCDAPC] D4_APC_1: 0xfff
9747 00:57:10.645707 INFO: [NOCDAPC] D5_APC_0: 0x0
9748 00:57:10.648394 INFO: [NOCDAPC] D5_APC_1: 0xfff
9749 00:57:10.648476 INFO: [NOCDAPC] D6_APC_0: 0x0
9750 00:57:10.651548 INFO: [NOCDAPC] D6_APC_1: 0xfff
9751 00:57:10.656010 INFO: [NOCDAPC] D7_APC_0: 0x0
9752 00:57:10.658658 INFO: [NOCDAPC] D7_APC_1: 0xfff
9753 00:57:10.661992 INFO: [NOCDAPC] D8_APC_0: 0x0
9754 00:57:10.665823 INFO: [NOCDAPC] D8_APC_1: 0xfff
9755 00:57:10.668150 INFO: [NOCDAPC] D9_APC_0: 0x0
9756 00:57:10.671843 INFO: [NOCDAPC] D9_APC_1: 0xfff
9757 00:57:10.675161 INFO: [NOCDAPC] D10_APC_0: 0x0
9758 00:57:10.678119 INFO: [NOCDAPC] D10_APC_1: 0xfff
9759 00:57:10.681874 INFO: [NOCDAPC] D11_APC_0: 0x0
9760 00:57:10.684683 INFO: [NOCDAPC] D11_APC_1: 0xfff
9761 00:57:10.687978 INFO: [NOCDAPC] D12_APC_0: 0x0
9762 00:57:10.688059 INFO: [NOCDAPC] D12_APC_1: 0xfff
9763 00:57:10.692952 INFO: [NOCDAPC] D13_APC_0: 0x0
9764 00:57:10.694489 INFO: [NOCDAPC] D13_APC_1: 0xfff
9765 00:57:10.698212 INFO: [NOCDAPC] D14_APC_0: 0x0
9766 00:57:10.701231 INFO: [NOCDAPC] D14_APC_1: 0xfff
9767 00:57:10.704633 INFO: [NOCDAPC] D15_APC_0: 0x0
9768 00:57:10.708782 INFO: [NOCDAPC] D15_APC_1: 0xfff
9769 00:57:10.711805 INFO: [NOCDAPC] APC_CON: 0x4
9770 00:57:10.714420 INFO: [APUAPC] set_apusys_apc done
9771 00:57:10.718063 INFO: [DEVAPC] devapc_init done
9772 00:57:10.721065 INFO: GICv3 without legacy support detected.
9773 00:57:10.724509 INFO: ARM GICv3 driver initialized in EL3
9774 00:57:10.731481 INFO: Maximum SPI INTID supported: 639
9775 00:57:10.734692 INFO: BL31: Initializing runtime services
9776 00:57:10.741114 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9777 00:57:10.741196 INFO: SPM: enable CPC mode
9778 00:57:10.747339 INFO: mcdi ready for mcusys-off-idle and system suspend
9779 00:57:10.750853 INFO: BL31: Preparing for EL3 exit to normal world
9780 00:57:10.753970 INFO: Entry point address = 0x80000000
9781 00:57:10.757668 INFO: SPSR = 0x8
9782 00:57:10.763602
9783 00:57:10.763683
9784 00:57:10.763748
9785 00:57:10.766428 Starting depthcharge on Spherion...
9786 00:57:10.766509
9787 00:57:10.766573 Wipe memory regions:
9788 00:57:10.766633
9789 00:57:10.767298 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9790 00:57:10.767398 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9791 00:57:10.767481 Setting prompt string to ['asurada:']
9792 00:57:10.767562 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9793 00:57:10.769854 [0x00000040000000, 0x00000054600000)
9794 00:57:10.892888
9795 00:57:10.893407 [0x00000054660000, 0x00000080000000)
9796 00:57:11.152929
9797 00:57:11.153430 [0x000000821a7280, 0x000000ffe64000)
9798 00:57:11.898637
9799 00:57:11.899184 [0x00000100000000, 0x00000140000000)
9800 00:57:12.278903
9801 00:57:12.281991 Initializing XHCI USB controller at 0x11200000.
9802 00:57:13.321085
9803 00:57:13.323546 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9804 00:57:13.324027
9805 00:57:13.324519
9806 00:57:13.325027
9807 00:57:13.325990 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9809 00:57:13.427349 asurada: tftpboot 192.168.201.1 12571063/tftp-deploy-81zhmeaq/kernel/image.itb 12571063/tftp-deploy-81zhmeaq/kernel/cmdline
9810 00:57:13.427959 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9811 00:57:13.428479 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9812 00:57:13.433296 tftpboot 192.168.201.1 12571063/tftp-deploy-81zhmeaq/kernel/image.ittp-deploy-81zhmeaq/kernel/cmdline
9813 00:57:13.433779
9814 00:57:13.434265 Waiting for link
9815 00:57:13.594187
9816 00:57:13.594751 R8152: Initializing
9817 00:57:13.595240
9818 00:57:13.597666 Version 9 (ocp_data = 6010)
9819 00:57:13.598144
9820 00:57:13.600628 R8152: Done initializing
9821 00:57:13.601154
9822 00:57:13.601638 Adding net device
9823 00:57:15.609316
9824 00:57:15.609896 done.
9825 00:57:15.610266
9826 00:57:15.610607 MAC: 00:e0:4c:68:03:bd
9827 00:57:15.610936
9828 00:57:15.611593 Sending DHCP discover... done.
9829 00:57:15.611961
9830 00:57:15.613966 Waiting for reply... done.
9831 00:57:15.614067
9832 00:57:15.617477 Sending DHCP request... done.
9833 00:57:15.617641
9834 00:57:15.621145 Waiting for reply... done.
9835 00:57:15.621282
9836 00:57:15.621358 My ip is 192.168.201.16
9837 00:57:15.621426
9838 00:57:15.624266 The DHCP server ip is 192.168.201.1
9839 00:57:15.624436
9840 00:57:15.630586 TFTP server IP predefined by user: 192.168.201.1
9841 00:57:15.630783
9842 00:57:15.636757 Bootfile predefined by user: 12571063/tftp-deploy-81zhmeaq/kernel/image.itb
9843 00:57:15.636924
9844 00:57:15.640735 Sending tftp read request... done.
9845 00:57:15.640939
9846 00:57:15.644344 Waiting for the transfer...
9847 00:57:15.644472
9848 00:57:16.010822 00000000 ################################################################
9849 00:57:16.011548
9850 00:57:16.299339 00080000 ################################################################
9851 00:57:16.299490
9852 00:57:16.574609 00100000 ################################################################
9853 00:57:16.574776
9854 00:57:16.850321 00180000 ################################################################
9855 00:57:16.850463
9856 00:57:17.141505 00200000 ################################################################
9857 00:57:17.142010
9858 00:57:17.480852 00280000 ################################################################
9859 00:57:17.481007
9860 00:57:17.730384 00300000 ################################################################
9861 00:57:17.730515
9862 00:57:17.981503 00380000 ################################################################
9863 00:57:17.981639
9864 00:57:18.231629 00400000 ################################################################
9865 00:57:18.231791
9866 00:57:18.479010 00480000 ################################################################
9867 00:57:18.479145
9868 00:57:18.753941 00500000 ################################################################
9869 00:57:18.754105
9870 00:57:19.006920 00580000 ################################################################
9871 00:57:19.007091
9872 00:57:19.285698 00600000 ################################################################
9873 00:57:19.285827
9874 00:57:19.583827 00680000 ################################################################
9875 00:57:19.583968
9876 00:57:19.879321 00700000 ################################################################
9877 00:57:19.879464
9878 00:57:20.152157 00780000 ################################################################
9879 00:57:20.152326
9880 00:57:20.401186 00800000 ################################################################
9881 00:57:20.401310
9882 00:57:20.657188 00880000 ################################################################
9883 00:57:20.657336
9884 00:57:20.920126 00900000 ################################################################
9885 00:57:20.920266
9886 00:57:21.190113 00980000 ################################################################
9887 00:57:21.190267
9888 00:57:21.465131 00a00000 ################################################################
9889 00:57:21.465266
9890 00:57:21.737545 00a80000 ################################################################
9891 00:57:21.737689
9892 00:57:21.990015 00b00000 ################################################################
9893 00:57:21.990145
9894 00:57:22.242154 00b80000 ################################################################
9895 00:57:22.242293
9896 00:57:22.499984 00c00000 ################################################################
9897 00:57:22.500125
9898 00:57:22.758151 00c80000 ################################################################
9899 00:57:22.758294
9900 00:57:23.012284 00d00000 ################################################################
9901 00:57:23.012428
9902 00:57:23.267373 00d80000 ################################################################
9903 00:57:23.267515
9904 00:57:23.546707 00e00000 ################################################################
9905 00:57:23.546844
9906 00:57:23.841049 00e80000 ################################################################
9907 00:57:23.841198
9908 00:57:24.122775 00f00000 ################################################################
9909 00:57:24.122916
9910 00:57:24.413768 00f80000 ################################################################
9911 00:57:24.413904
9912 00:57:24.694575 01000000 ################################################################
9913 00:57:24.694705
9914 00:57:24.990640 01080000 ################################################################
9915 00:57:24.990853
9916 00:57:25.415967 01100000 ################################################################
9917 00:57:25.416559
9918 00:57:25.818261 01180000 ################################################################
9919 00:57:25.818823
9920 00:57:26.125823 01200000 ################################################################
9921 00:57:26.125970
9922 00:57:26.451504 01280000 ################################################################
9923 00:57:26.452067
9924 00:57:26.747109 01300000 ################################################################
9925 00:57:26.747250
9926 00:57:26.997506 01380000 ################################################################
9927 00:57:26.997637
9928 00:57:27.337042 01400000 ################################################################
9929 00:57:27.337563
9930 00:57:27.720254 01480000 ################################################################
9931 00:57:27.720861
9932 00:57:28.099544 01500000 ################################################################
9933 00:57:28.100129
9934 00:57:28.426932 01580000 ################################################################
9935 00:57:28.427081
9936 00:57:28.717831 01600000 ################################################################
9937 00:57:28.717967
9938 00:57:29.015748 01680000 ################################################################
9939 00:57:29.015885
9940 00:57:29.310789 01700000 ################################################################
9941 00:57:29.310931
9942 00:57:29.589578 01780000 ################################################################
9943 00:57:29.589715
9944 00:57:29.887939 01800000 ################################################################
9945 00:57:29.888077
9946 00:57:30.178773 01880000 ################################################################
9947 00:57:30.178937
9948 00:57:30.460648 01900000 ################################################################
9949 00:57:30.460796
9950 00:57:30.741314 01980000 ################################################################
9951 00:57:30.741451
9952 00:57:31.027643 01a00000 ################################################################
9953 00:57:31.027778
9954 00:57:31.326720 01a80000 ################################################################
9955 00:57:31.326858
9956 00:57:31.611827 01b00000 ################################################################
9957 00:57:31.611989
9958 00:57:31.906961 01b80000 ################################################################
9959 00:57:31.907100
9960 00:57:32.203907 01c00000 ################################################################
9961 00:57:32.204042
9962 00:57:32.213266 01c80000 ## done.
9963 00:57:32.213370
9964 00:57:32.216562 The bootfile was 29898030 bytes long.
9965 00:57:32.216646
9966 00:57:32.216721 Sending tftp read request... done.
9967 00:57:32.220135
9968 00:57:32.220296 Waiting for the transfer...
9969 00:57:32.220365
9970 00:57:32.223577 00000000 # done.
9971 00:57:32.223672
9972 00:57:32.230401 Command line loaded dynamically from TFTP file: 12571063/tftp-deploy-81zhmeaq/kernel/cmdline
9973 00:57:32.230503
9974 00:57:32.253197 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9975 00:57:32.253461
9976 00:57:32.253608 Loading FIT.
9977 00:57:32.253741
9978 00:57:32.256495 Image ramdisk-1 has 17800094 bytes.
9979 00:57:32.256692
9980 00:57:32.259666 Image fdt-1 has 47278 bytes.
9981 00:57:32.259950
9982 00:57:32.263361 Image kernel-1 has 12048624 bytes.
9983 00:57:32.263684
9984 00:57:32.273860 Compat preference: google,spherion-rev12-sku1 google,spherion-rev12 google,spherion-sku1 google,spherion
9985 00:57:32.274347
9986 00:57:32.290371 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9987 00:57:32.290962
9988 00:57:32.293563 Choosing best match conf-1 for compat google,spherion.
9989 00:57:32.298825
9990 00:57:32.302938 Connected to device vid:did:rid of 1ae0:0028:00
9991 00:57:32.310123
9992 00:57:32.313855 tpm_get_response: command 0x17b, return code 0x0
9993 00:57:32.314410
9994 00:57:32.316779 ec_init: CrosEC protocol v3 supported (256, 248)
9995 00:57:32.321018
9996 00:57:32.324195 tpm_cleanup: add release locality here.
9997 00:57:32.324664
9998 00:57:32.325133 Shutting down all USB controllers.
9999 00:57:32.327151
10000 00:57:32.327703 Removing current net device
10001 00:57:32.328069
10002 00:57:32.334038 Exiting depthcharge with code 4 at timestamp: 49740839
10003 00:57:32.334492
10004 00:57:32.337308 LZMA decompressing kernel-1 to 0x821a6718
10005 00:57:32.337764
10006 00:57:32.341207 LZMA decompressing kernel-1 to 0x40000000
10007 00:57:33.839059
10008 00:57:33.839676 jumping to kernel
10009 00:57:33.841473 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10010 00:57:33.842004 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10011 00:57:33.842401 Setting prompt string to ['Linux version [0-9]']
10012 00:57:33.842767 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10013 00:57:33.843135 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10014 00:57:33.889514
10015 00:57:33.892258 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10016 00:57:33.896187 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10017 00:57:33.896889 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10018 00:57:33.897297 Setting prompt string to []
10019 00:57:33.897711 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10020 00:57:33.898099 Using line separator: #'\n'#
10021 00:57:33.898485 No login prompt set.
10022 00:57:33.898824 Parsing kernel messages
10023 00:57:33.899231 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10024 00:57:33.899802 [login-action] Waiting for messages, (timeout 00:04:03)
10025 00:57:33.915627 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10026 00:57:33.918948 [ 0.000000] random: crng init done
10027 00:57:33.925610 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10028 00:57:33.929175 [ 0.000000] efi: UEFI not found.
10029 00:57:33.935159 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10030 00:57:33.945008 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10031 00:57:33.951819 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10032 00:57:33.961659 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10033 00:57:33.968084 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10034 00:57:33.974530 [ 0.000000] printk: bootconsole [mtk8250] enabled
10035 00:57:33.981107 [ 0.000000] NUMA: No NUMA configuration found
10036 00:57:33.988237 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10037 00:57:33.991222 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10038 00:57:33.995449 [ 0.000000] Zone ranges:
10039 00:57:34.001401 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10040 00:57:34.004818 [ 0.000000] DMA32 empty
10041 00:57:34.011226 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10042 00:57:34.015457 [ 0.000000] Movable zone start for each node
10043 00:57:34.019542 [ 0.000000] Early memory node ranges
10044 00:57:34.024308 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10045 00:57:34.030935 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10046 00:57:34.037418 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10047 00:57:34.044552 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10048 00:57:34.051242 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10049 00:57:34.057280 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10050 00:57:34.088387 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10051 00:57:34.094274 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10052 00:57:34.101370 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10053 00:57:34.104871 [ 0.000000] psci: probing for conduit method from DT.
10054 00:57:34.111222 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10055 00:57:34.114634 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10056 00:57:34.121345 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10057 00:57:34.124218 [ 0.000000] psci: SMC Calling Convention v1.2
10058 00:57:34.131053 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10059 00:57:34.134052 [ 0.000000] Detected VIPT I-cache on CPU0
10060 00:57:34.141531 [ 0.000000] CPU features: detected: GIC system register CPU interface
10061 00:57:34.147696 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10062 00:57:34.154520 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10063 00:57:34.160426 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10064 00:57:34.167130 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10065 00:57:34.177311 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10066 00:57:34.180541 [ 0.000000] alternatives: applying boot alternatives
10067 00:57:34.188489 [ 0.000000] Fallback order for Node 0: 0
10068 00:57:34.193492 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10069 00:57:34.196964 [ 0.000000] Policy zone: Normal
10070 00:57:34.220209 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10071 00:57:34.229887 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10072 00:57:34.239657 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10073 00:57:34.246547 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10074 00:57:34.253213 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10075 00:57:34.259221 <6>[ 0.000000] software IO TLB: area num 8.
10076 00:57:34.315172 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10077 00:57:34.394262 <6>[ 0.000000] Memory: 3835464K/4191232K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 323000K reserved, 32768K cma-reserved)
10078 00:57:34.401253 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10079 00:57:34.407800 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10080 00:57:34.412382 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10081 00:57:34.417638 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10082 00:57:34.425305 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10083 00:57:34.427803 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10084 00:57:34.437550 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10085 00:57:34.443804 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10086 00:57:34.450160 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10087 00:57:34.456830 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10088 00:57:34.459913 <6>[ 0.000000] GICv3: 608 SPIs implemented
10089 00:57:34.463835 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10090 00:57:34.470925 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10091 00:57:34.474155 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10092 00:57:34.480359 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10093 00:57:34.493584 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10094 00:57:34.506756 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10095 00:57:34.513181 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10096 00:57:34.521640 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10097 00:57:34.534283 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10098 00:57:34.541216 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10099 00:57:34.548059 <6>[ 0.009180] Console: colour dummy device 80x25
10100 00:57:34.558988 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10101 00:57:34.564229 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10102 00:57:34.567353 <6>[ 0.029219] LSM: Security Framework initializing
10103 00:57:34.573911 <6>[ 0.034132] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10104 00:57:34.583713 <6>[ 0.041738] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10105 00:57:34.590422 <6>[ 0.051013] cblist_init_generic: Setting adjustable number of callback queues.
10106 00:57:34.597137 <6>[ 0.058501] cblist_init_generic: Setting shift to 3 and lim to 1.
10107 00:57:34.606825 <6>[ 0.064877] cblist_init_generic: Setting adjustable number of callback queues.
10108 00:57:34.614518 <6>[ 0.072303] cblist_init_generic: Setting shift to 3 and lim to 1.
10109 00:57:34.616998 <6>[ 0.078706] rcu: Hierarchical SRCU implementation.
10110 00:57:34.623780 <6>[ 0.083721] rcu: Max phase no-delay instances is 1000.
10111 00:57:34.630364 <6>[ 0.090740] EFI services will not be available.
10112 00:57:34.633239 <6>[ 0.095689] smp: Bringing up secondary CPUs ...
10113 00:57:34.641659 <6>[ 0.100738] Detected VIPT I-cache on CPU1
10114 00:57:34.648897 <6>[ 0.100808] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10115 00:57:34.655439 <6>[ 0.100839] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10116 00:57:34.659317 <6>[ 0.101176] Detected VIPT I-cache on CPU2
10117 00:57:34.665331 <6>[ 0.101225] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10118 00:57:34.674706 <6>[ 0.101242] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10119 00:57:34.678862 <6>[ 0.101496] Detected VIPT I-cache on CPU3
10120 00:57:34.684841 <6>[ 0.101544] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10121 00:57:34.691602 <6>[ 0.101558] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10122 00:57:34.694787 <6>[ 0.101862] CPU features: detected: Spectre-v4
10123 00:57:34.701191 <6>[ 0.101868] CPU features: detected: Spectre-BHB
10124 00:57:34.704153 <6>[ 0.101873] Detected PIPT I-cache on CPU4
10125 00:57:34.710908 <6>[ 0.101929] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10126 00:57:34.718800 <6>[ 0.101946] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10127 00:57:34.724299 <6>[ 0.102237] Detected PIPT I-cache on CPU5
10128 00:57:34.730701 <6>[ 0.102298] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10129 00:57:34.737324 <6>[ 0.102316] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10130 00:57:34.741025 <6>[ 0.102596] Detected PIPT I-cache on CPU6
10131 00:57:34.747457 <6>[ 0.102656] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10132 00:57:34.754270 <6>[ 0.102673] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10133 00:57:34.761012 <6>[ 0.102970] Detected PIPT I-cache on CPU7
10134 00:57:34.767847 <6>[ 0.103033] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10135 00:57:34.773710 <6>[ 0.103050] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10136 00:57:34.777693 <6>[ 0.103098] smp: Brought up 1 node, 8 CPUs
10137 00:57:34.783718 <6>[ 0.244563] SMP: Total of 8 processors activated.
10138 00:57:34.787533 <6>[ 0.249514] CPU features: detected: 32-bit EL0 Support
10139 00:57:34.796890 <6>[ 0.254877] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10140 00:57:34.803052 <6>[ 0.263677] CPU features: detected: Common not Private translations
10141 00:57:34.809907 <6>[ 0.270193] CPU features: detected: CRC32 instructions
10142 00:57:34.816245 <6>[ 0.275577] CPU features: detected: RCpc load-acquire (LDAPR)
10143 00:57:34.819856 <6>[ 0.281537] CPU features: detected: LSE atomic instructions
10144 00:57:34.826468 <6>[ 0.287354] CPU features: detected: Privileged Access Never
10145 00:57:34.832699 <6>[ 0.293134] CPU features: detected: RAS Extension Support
10146 00:57:34.839547 <6>[ 0.298742] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10147 00:57:34.842979 <6>[ 0.305962] CPU: All CPU(s) started at EL2
10148 00:57:34.849518 <6>[ 0.310305] alternatives: applying system-wide alternatives
10149 00:57:34.858579 <6>[ 0.320217] devtmpfs: initialized
10150 00:57:34.874047 <6>[ 0.328544] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10151 00:57:34.880407 <6>[ 0.338501] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10152 00:57:34.887331 <6>[ 0.346742] pinctrl core: initialized pinctrl subsystem
10153 00:57:34.890053 <6>[ 0.353387] DMI not present or invalid.
10154 00:57:34.896827 <6>[ 0.357792] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10155 00:57:34.906536 <6>[ 0.364659] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10156 00:57:34.913327 <6>[ 0.372094] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10157 00:57:34.923183 <6>[ 0.380183] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10158 00:57:34.926583 <6>[ 0.388341] audit: initializing netlink subsys (disabled)
10159 00:57:34.937074 <5>[ 0.394039] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10160 00:57:34.942793 <6>[ 0.394730] thermal_sys: Registered thermal governor 'step_wise'
10161 00:57:34.949462 <6>[ 0.402006] thermal_sys: Registered thermal governor 'power_allocator'
10162 00:57:34.952805 <6>[ 0.408261] cpuidle: using governor menu
10163 00:57:34.959489 <6>[ 0.419221] NET: Registered PF_QIPCRTR protocol family
10164 00:57:34.966213 <6>[ 0.424701] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10165 00:57:34.972557 <6>[ 0.431802] ASID allocator initialised with 32768 entries
10166 00:57:34.976408 <6>[ 0.438352] Serial: AMBA PL011 UART driver
10167 00:57:34.986114 <4>[ 0.447114] Trying to register duplicate clock ID: 134
10168 00:57:35.041818 <6>[ 0.506374] KASLR enabled
10169 00:57:35.056650 <6>[ 0.514163] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10170 00:57:35.062104 <6>[ 0.521175] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10171 00:57:35.068938 <6>[ 0.527663] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10172 00:57:35.075662 <6>[ 0.534670] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10173 00:57:35.082203 <6>[ 0.541155] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10174 00:57:35.088699 <6>[ 0.548160] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10175 00:57:35.095471 <6>[ 0.554648] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10176 00:57:35.102391 <6>[ 0.561650] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10177 00:57:35.105557 <6>[ 0.569152] ACPI: Interpreter disabled.
10178 00:57:35.114199 <6>[ 0.575552] iommu: Default domain type: Translated
10179 00:57:35.121170 <6>[ 0.580662] iommu: DMA domain TLB invalidation policy: strict mode
10180 00:57:35.123936 <5>[ 0.587319] SCSI subsystem initialized
10181 00:57:35.130971 <6>[ 0.591483] usbcore: registered new interface driver usbfs
10182 00:57:35.137421 <6>[ 0.597218] usbcore: registered new interface driver hub
10183 00:57:35.140554 <6>[ 0.602770] usbcore: registered new device driver usb
10184 00:57:35.147222 <6>[ 0.608874] pps_core: LinuxPPS API ver. 1 registered
10185 00:57:35.157167 <6>[ 0.614066] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10186 00:57:35.160332 <6>[ 0.623411] PTP clock support registered
10187 00:57:35.163978 <6>[ 0.627654] EDAC MC: Ver: 3.0.0
10188 00:57:35.171337 <6>[ 0.632810] FPGA manager framework
10189 00:57:35.175718 <6>[ 0.636490] Advanced Linux Sound Architecture Driver Initialized.
10190 00:57:35.178233 <6>[ 0.643274] vgaarb: loaded
10191 00:57:35.184786 <6>[ 0.646433] clocksource: Switched to clocksource arch_sys_counter
10192 00:57:35.191727 <5>[ 0.652873] VFS: Disk quotas dquot_6.6.0
10193 00:57:35.198324 <6>[ 0.657054] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10194 00:57:35.201266 <6>[ 0.664247] pnp: PnP ACPI: disabled
10195 00:57:35.209523 <6>[ 0.671019] NET: Registered PF_INET protocol family
10196 00:57:35.215887 <6>[ 0.676403] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10197 00:57:35.228307 <6>[ 0.686431] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10198 00:57:35.238447 <6>[ 0.695218] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10199 00:57:35.244857 <6>[ 0.703187] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10200 00:57:35.251463 <6>[ 0.711593] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10201 00:57:35.261701 <6>[ 0.720248] TCP: Hash tables configured (established 32768 bind 32768)
10202 00:57:35.268427 <6>[ 0.727106] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10203 00:57:35.275293 <6>[ 0.734123] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10204 00:57:35.282460 <6>[ 0.741647] NET: Registered PF_UNIX/PF_LOCAL protocol family
10205 00:57:35.289314 <6>[ 0.747792] RPC: Registered named UNIX socket transport module.
10206 00:57:35.291386 <6>[ 0.753944] RPC: Registered udp transport module.
10207 00:57:35.298683 <6>[ 0.758879] RPC: Registered tcp transport module.
10208 00:57:35.304986 <6>[ 0.763812] RPC: Registered tcp NFSv4.1 backchannel transport module.
10209 00:57:35.308156 <6>[ 0.770479] PCI: CLS 0 bytes, default 64
10210 00:57:35.311549 <6>[ 0.774809] Unpacking initramfs...
10211 00:57:35.336868 <6>[ 0.794525] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10212 00:57:35.346489 <6>[ 0.803188] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10213 00:57:35.349299 <6>[ 0.812033] kvm [1]: IPA Size Limit: 40 bits
10214 00:57:35.356608 <6>[ 0.816561] kvm [1]: GICv3: no GICV resource entry
10215 00:57:35.359402 <6>[ 0.821582] kvm [1]: disabling GICv2 emulation
10216 00:57:35.366183 <6>[ 0.826271] kvm [1]: GIC system register CPU interface enabled
10217 00:57:35.370044 <6>[ 0.832434] kvm [1]: vgic interrupt IRQ18
10218 00:57:35.375895 <6>[ 0.836790] kvm [1]: VHE mode initialized successfully
10219 00:57:35.383067 <5>[ 0.843282] Initialise system trusted keyrings
10220 00:57:35.389339 <6>[ 0.848122] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10221 00:57:35.397217 <6>[ 0.858111] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10222 00:57:35.403427 <5>[ 0.864500] NFS: Registering the id_resolver key type
10223 00:57:35.408020 <5>[ 0.869795] Key type id_resolver registered
10224 00:57:35.413145 <5>[ 0.874212] Key type id_legacy registered
10225 00:57:35.419803 <6>[ 0.878490] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10226 00:57:35.426427 <6>[ 0.885411] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10227 00:57:35.432980 <6>[ 0.893127] 9p: Installing v9fs 9p2000 file system support
10228 00:57:35.469095 <5>[ 0.930474] Key type asymmetric registered
10229 00:57:35.472549 <5>[ 0.934803] Asymmetric key parser 'x509' registered
10230 00:57:35.482911 <6>[ 0.939935] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10231 00:57:35.485386 <6>[ 0.947549] io scheduler mq-deadline registered
10232 00:57:35.488665 <6>[ 0.952327] io scheduler kyber registered
10233 00:57:35.508239 <6>[ 0.969227] EINJ: ACPI disabled.
10234 00:57:35.540190 <4>[ 0.995048] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10235 00:57:35.549880 <4>[ 1.005671] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10236 00:57:35.564480 <6>[ 1.026237] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10237 00:57:35.572175 <6>[ 1.034158] printk: console [ttyS0] disabled
10238 00:57:35.601130 <6>[ 1.058810] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10239 00:57:35.608372 <6>[ 1.068283] printk: console [ttyS0] enabled
10240 00:57:35.611156 <6>[ 1.068283] printk: console [ttyS0] enabled
10241 00:57:35.616865 <6>[ 1.077177] printk: bootconsole [mtk8250] disabled
10242 00:57:35.621092 <6>[ 1.077177] printk: bootconsole [mtk8250] disabled
10243 00:57:35.627183 <6>[ 1.088219] SuperH (H)SCI(F) driver initialized
10244 00:57:35.631332 <6>[ 1.093488] msm_serial: driver initialized
10245 00:57:35.644463 <6>[ 1.102377] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10246 00:57:35.653851 <6>[ 1.110928] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10247 00:57:35.660413 <6>[ 1.119472] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10248 00:57:35.671417 <6>[ 1.128100] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10249 00:57:35.680816 <6>[ 1.136807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10250 00:57:35.687573 <6>[ 1.145520] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10251 00:57:35.697725 <6>[ 1.154062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10252 00:57:35.704014 <6>[ 1.162851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10253 00:57:35.713538 <6>[ 1.171394] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10254 00:57:35.722484 <6>[ 1.186979] loop: module loaded
10255 00:57:35.731280 <6>[ 1.192873] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10256 00:57:35.754277 <4>[ 1.216249] mtk-pmic-keys: Failed to locate of_node [id: -1]
10257 00:57:35.761648 <6>[ 1.223060] megasas: 07.719.03.00-rc1
10258 00:57:35.771426 <6>[ 1.232758] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10259 00:57:35.781050 <6>[ 1.241820] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10260 00:57:35.797410 <6>[ 1.258533] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10261 00:57:35.853545 <6>[ 1.308300] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10262 00:57:36.050666 <6>[ 1.512573] Freeing initrd memory: 17376K
10263 00:57:36.061090 <6>[ 1.522814] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10264 00:57:36.071690 <6>[ 1.533707] tun: Universal TUN/TAP device driver, 1.6
10265 00:57:36.075131 <6>[ 1.539773] thunder_xcv, ver 1.0
10266 00:57:36.079045 <6>[ 1.543281] thunder_bgx, ver 1.0
10267 00:57:36.082183 <6>[ 1.546775] nicpf, ver 1.0
10268 00:57:36.093033 <6>[ 1.550801] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10269 00:57:36.095727 <6>[ 1.558276] hns3: Copyright (c) 2017 Huawei Corporation.
10270 00:57:36.100124 <6>[ 1.563864] hclge is initializing
10271 00:57:36.107371 <6>[ 1.567448] e1000: Intel(R) PRO/1000 Network Driver
10272 00:57:36.112802 <6>[ 1.572578] e1000: Copyright (c) 1999-2006 Intel Corporation.
10273 00:57:36.115567 <6>[ 1.578591] e1000e: Intel(R) PRO/1000 Network Driver
10274 00:57:36.122633 <6>[ 1.583807] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10275 00:57:36.128961 <6>[ 1.589996] igb: Intel(R) Gigabit Ethernet Network Driver
10276 00:57:36.135590 <6>[ 1.595646] igb: Copyright (c) 2007-2014 Intel Corporation.
10277 00:57:36.142454 <6>[ 1.601482] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10278 00:57:36.149084 <6>[ 1.607999] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10279 00:57:36.152676 <6>[ 1.614464] sky2: driver version 1.30
10280 00:57:36.158902 <6>[ 1.619464] VFIO - User Level meta-driver version: 0.3
10281 00:57:36.166575 <6>[ 1.627699] usbcore: registered new interface driver usb-storage
10282 00:57:36.173200 <6>[ 1.634141] usbcore: registered new device driver onboard-usb-hub
10283 00:57:36.182181 <6>[ 1.643314] mt6397-rtc mt6359-rtc: registered as rtc0
10284 00:57:36.191287 <6>[ 1.648785] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T00:57:37 UTC (1705625857)
10285 00:57:36.194598 <6>[ 1.658368] i2c_dev: i2c /dev entries driver
10286 00:57:36.211653 <6>[ 1.670127] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10287 00:57:36.232437 <6>[ 1.694113] cpu cpu0: EM: created perf domain
10288 00:57:36.235506 <6>[ 1.699049] cpu cpu4: EM: created perf domain
10289 00:57:36.243143 <6>[ 1.704617] sdhci: Secure Digital Host Controller Interface driver
10290 00:57:36.250875 <6>[ 1.711050] sdhci: Copyright(c) Pierre Ossman
10291 00:57:36.256582 <6>[ 1.715946] Synopsys Designware Multimedia Card Interface Driver
10292 00:57:36.262867 <6>[ 1.722560] sdhci-pltfm: SDHCI platform and OF driver helper
10293 00:57:36.266326 <6>[ 1.722655] mmc0: CQHCI version 5.10
10294 00:57:36.273191 <6>[ 1.732591] ledtrig-cpu: registered to indicate activity on CPUs
10295 00:57:36.280256 <6>[ 1.739629] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10296 00:57:36.285991 <6>[ 1.746644] usbcore: registered new interface driver usbhid
10297 00:57:36.289560 <6>[ 1.752465] usbhid: USB HID core driver
10298 00:57:36.295962 <6>[ 1.756665] spi_master spi0: will run message pump with realtime priority
10299 00:57:36.337339 <6>[ 1.792337] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10300 00:57:36.356908 <6>[ 1.808122] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10301 00:57:36.363720 <6>[ 1.822842] cros-ec-spi spi0.0: Chrome EC device registered
10302 00:57:36.367188 <6>[ 1.828873] mmc0: Command Queue Engine enabled
10303 00:57:36.374000 <6>[ 1.833631] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10304 00:57:36.380370 <6>[ 1.841423] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10305 00:57:36.397898 <6>[ 1.856094] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10306 00:57:36.404809 <6>[ 1.856542] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10307 00:57:36.411653 <6>[ 1.866451] NET: Registered PF_PACKET protocol family
10308 00:57:36.414368 <6>[ 1.872623] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10309 00:57:36.420894 <6>[ 1.876703] 9pnet: Installing 9P2000 support
10310 00:57:36.424153 <6>[ 1.882576] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10311 00:57:36.431011 <5>[ 1.886387] Key type dns_resolver registered
10312 00:57:36.437983 <6>[ 1.892223] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10313 00:57:36.441262 <6>[ 1.896490] registered taskstats version 1
10314 00:57:36.444314 <5>[ 1.906992] Loading compiled-in X.509 certificates
10315 00:57:36.474581 <4>[ 1.929312] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10316 00:57:36.484986 <4>[ 1.939992] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10317 00:57:36.490501 <3>[ 1.950572] debugfs: File 'uA_load' in directory '/' already present!
10318 00:57:36.498499 <3>[ 1.957277] debugfs: File 'min_uV' in directory '/' already present!
10319 00:57:36.504141 <3>[ 1.963928] debugfs: File 'max_uV' in directory '/' already present!
10320 00:57:36.510945 <3>[ 1.970550] debugfs: File 'constraint_flags' in directory '/' already present!
10321 00:57:36.521373 <3>[ 1.980026] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10322 00:57:36.531456 <6>[ 1.993086] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10323 00:57:36.538207 <6>[ 1.999837] xhci-mtk 11200000.usb: xHCI Host Controller
10324 00:57:36.544458 <6>[ 2.005333] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10325 00:57:36.554726 <6>[ 2.013162] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10326 00:57:36.561282 <6>[ 2.022588] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10327 00:57:36.568818 <6>[ 2.028637] xhci-mtk 11200000.usb: xHCI Host Controller
10328 00:57:36.574436 <6>[ 2.034112] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10329 00:57:36.581568 <6>[ 2.041756] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10330 00:57:36.587682 <6>[ 2.049411] hub 1-0:1.0: USB hub found
10331 00:57:36.591656 <6>[ 2.053422] hub 1-0:1.0: 1 port detected
10332 00:57:36.598230 <6>[ 2.057674] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10333 00:57:36.604318 <6>[ 2.066217] hub 2-0:1.0: USB hub found
10334 00:57:36.608226 <6>[ 2.070222] hub 2-0:1.0: 1 port detected
10335 00:57:36.616202 <6>[ 2.077496] mtk-msdc 11f70000.mmc: Got CD GPIO
10336 00:57:36.627115 <6>[ 2.085384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10337 00:57:36.633890 <6>[ 2.093423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10338 00:57:36.644346 <4>[ 2.101314] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10339 00:57:36.653467 <6>[ 2.110834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10340 00:57:36.660268 <6>[ 2.118910] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10341 00:57:36.667635 <6>[ 2.126933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10342 00:57:36.676963 <6>[ 2.134850] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10343 00:57:36.683593 <6>[ 2.142667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10344 00:57:36.693312 <6>[ 2.150486] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10345 00:57:36.703537 <6>[ 2.160813] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10346 00:57:36.711015 <6>[ 2.169171] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10347 00:57:36.720175 <6>[ 2.177514] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10348 00:57:36.727302 <6>[ 2.185853] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10349 00:57:36.737158 <6>[ 2.194191] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10350 00:57:36.743292 <6>[ 2.202532] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10351 00:57:36.753442 <6>[ 2.210871] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10352 00:57:36.760441 <6>[ 2.219209] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10353 00:57:36.769719 <6>[ 2.227549] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10354 00:57:36.776163 <6>[ 2.235887] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10355 00:57:36.786661 <6>[ 2.244226] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10356 00:57:36.793419 <6>[ 2.252570] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10357 00:57:36.802831 <6>[ 2.260909] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10358 00:57:36.812335 <6>[ 2.269248] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10359 00:57:36.819100 <6>[ 2.277589] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10360 00:57:36.825625 <6>[ 2.286298] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10361 00:57:36.832677 <6>[ 2.293463] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10362 00:57:36.839020 <6>[ 2.300255] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10363 00:57:36.845835 <6>[ 2.307007] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10364 00:57:36.855641 <6>[ 2.313929] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10365 00:57:36.861805 <6>[ 2.320774] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10366 00:57:36.872804 <6>[ 2.329902] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10367 00:57:36.881818 <6>[ 2.339020] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10368 00:57:36.892205 <6>[ 2.348314] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10369 00:57:36.901565 <6>[ 2.357780] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10370 00:57:36.908543 <6>[ 2.367246] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10371 00:57:36.918271 <6>[ 2.376363] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10372 00:57:36.928106 <6>[ 2.385829] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10373 00:57:36.938263 <6>[ 2.394949] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10374 00:57:36.948156 <6>[ 2.404241] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10375 00:57:36.957772 <6>[ 2.414402] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10376 00:57:36.968320 <6>[ 2.426377] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10377 00:57:36.975043 <6>[ 2.436001] Trying to probe devices needed for running init ...
10378 00:57:36.996804 <6>[ 2.454959] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10379 00:57:37.024857 <6>[ 2.486264] hub 2-1:1.0: USB hub found
10380 00:57:37.028400 <6>[ 2.490729] hub 2-1:1.0: 3 ports detected
10381 00:57:37.036350 <6>[ 2.498083] hub 2-1:1.0: USB hub found
10382 00:57:37.039905 <6>[ 2.502430] hub 2-1:1.0: 3 ports detected
10383 00:57:37.148048 <6>[ 2.606702] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10384 00:57:37.303075 <6>[ 2.764765] hub 1-1:1.0: USB hub found
10385 00:57:37.307155 <6>[ 2.769236] hub 1-1:1.0: 4 ports detected
10386 00:57:37.316883 <6>[ 2.777741] hub 1-1:1.0: USB hub found
10387 00:57:37.318878 <6>[ 2.782110] hub 1-1:1.0: 4 ports detected
10388 00:57:37.380367 <6>[ 2.838962] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10389 00:57:37.640203 <6>[ 3.098717] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10390 00:57:37.773486 <6>[ 3.234523] hub 1-1.4:1.0: USB hub found
10391 00:57:37.776174 <6>[ 3.239184] hub 1-1.4:1.0: 2 ports detected
10392 00:57:37.786148 <6>[ 3.247311] hub 1-1.4:1.0: USB hub found
10393 00:57:37.789214 <6>[ 3.251998] hub 1-1.4:1.0: 2 ports detected
10394 00:57:38.084617 <6>[ 3.542717] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10395 00:57:38.276270 <6>[ 3.734718] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10396 00:57:49.269559 <6>[ 14.735701] ALSA device list:
10397 00:57:49.276061 <6>[ 14.738993] No soundcards found.
10398 00:57:49.284511 <6>[ 14.746770] Freeing unused kernel memory: 8448K
10399 00:57:49.287336 <6>[ 14.751753] Run /init as init process
10400 00:57:49.298103 Loading, please wait...
10401 00:57:49.318196 Starting version 247.3-7+deb11u2
10402 00:57:49.492796 <6>[ 14.952591] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10403 00:57:49.502672 <6>[ 14.965887] remoteproc remoteproc0: scp is available
10404 00:57:49.509625 <6>[ 14.971731] remoteproc remoteproc0: powering up scp
10405 00:57:49.515905 <6>[ 14.977171] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10406 00:57:49.527198 <3>[ 14.986193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10407 00:57:49.532685 <6>[ 14.986269] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10408 00:57:49.539949 <3>[ 14.996370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10409 00:57:49.546538 <6>[ 15.001316] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10410 00:57:49.556105 <3>[ 15.008305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10411 00:57:49.562620 <6>[ 15.009403] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10412 00:57:49.573100 <6>[ 15.017052] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10413 00:57:49.580284 <3>[ 15.023919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10414 00:57:49.590236 <4>[ 15.031086] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10415 00:57:49.593387 <4>[ 15.031086] Fallback method does not support PEC.
10416 00:57:49.603362 <6>[ 15.031528] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10417 00:57:49.609862 <3>[ 15.040203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10418 00:57:49.619974 <3>[ 15.046581] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10419 00:57:49.623438 <6>[ 15.048744] mc: Linux media interface: v0.10
10420 00:57:49.629523 <4>[ 15.049278] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10421 00:57:49.640675 <4>[ 15.049425] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10422 00:57:49.646202 <3>[ 15.061912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 00:57:49.652977 <3>[ 15.061917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10424 00:57:49.662963 <3>[ 15.061920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 00:57:49.669625 <3>[ 15.061958] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 00:57:49.679628 <3>[ 15.067719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10427 00:57:49.685894 <6>[ 15.070958] usbcore: registered new device driver r8152-cfgselector
10428 00:57:49.692874 <3>[ 15.078759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10429 00:57:49.702388 <6>[ 15.125502] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10430 00:57:49.709710 <6>[ 15.125516] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10431 00:57:49.718663 <3>[ 15.130834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10432 00:57:49.725645 <3>[ 15.130839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10433 00:57:49.735551 <6>[ 15.132259] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10434 00:57:49.742077 <6>[ 15.133914] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10435 00:57:49.749072 <6>[ 15.138920] remoteproc remoteproc0: remote processor scp is now up
10436 00:57:49.755384 <3>[ 15.147813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 00:57:49.765085 <6>[ 15.157271] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10438 00:57:49.774889 <3>[ 15.162288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10439 00:57:49.781766 <3>[ 15.162290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10440 00:57:49.792224 <3>[ 15.162293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10441 00:57:49.798494 <3>[ 15.162295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10442 00:57:49.804940 <3>[ 15.162312] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10443 00:57:49.815130 <6>[ 15.167795] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10444 00:57:49.819430 <6>[ 15.167799] pci_bus 0000:00: root bus resource [bus 00-ff]
10445 00:57:49.824961 <6>[ 15.167803] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10446 00:57:49.835015 <6>[ 15.167806] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10447 00:57:49.841673 <6>[ 15.167831] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10448 00:57:49.851735 <6>[ 15.167844] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10449 00:57:49.854605 <6>[ 15.167909] pci 0000:00:00.0: supports D1 D2
10450 00:57:49.861384 <6>[ 15.167912] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10451 00:57:49.871884 <6>[ 15.168777] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10452 00:57:49.874920 <6>[ 15.168841] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10453 00:57:49.884520 <6>[ 15.168865] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10454 00:57:49.890733 <6>[ 15.168879] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10455 00:57:49.897667 <6>[ 15.168894] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10456 00:57:49.904635 <6>[ 15.168996] pci 0000:01:00.0: supports D1 D2
10457 00:57:49.910717 <6>[ 15.168998] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10458 00:57:49.918298 <6>[ 15.174467] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10459 00:57:49.924242 <6>[ 15.174973] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10460 00:57:49.934655 <6>[ 15.179559] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10461 00:57:49.945172 <6>[ 15.185938] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10462 00:57:49.954592 <6>[ 15.195125] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10463 00:57:49.960633 <4>[ 15.198270] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10464 00:57:49.970182 <4>[ 15.198279] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10465 00:57:49.977043 <6>[ 15.202504] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10466 00:57:49.983767 <6>[ 15.225520] videodev: Linux video capture interface: v2.00
10467 00:57:49.990126 <6>[ 15.234840] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10468 00:57:49.996580 <6>[ 15.250649] r8152 2-1.3:1.0 eth0: v1.12.13
10469 00:57:50.003273 <6>[ 15.258702] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10470 00:57:50.010714 <6>[ 15.258716] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10471 00:57:50.017020 <6>[ 15.258730] pci 0000:00:00.0: PCI bridge to [bus 01]
10472 00:57:50.023537 <6>[ 15.258739] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10473 00:57:50.029637 <6>[ 15.259075] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10474 00:57:50.036442 <6>[ 15.259731] Bluetooth: Core ver 2.22
10475 00:57:50.039561 <6>[ 15.259848] NET: Registered PF_BLUETOOTH protocol family
10476 00:57:50.046333 <6>[ 15.259851] Bluetooth: HCI device and connection manager initialized
10477 00:57:50.053154 <6>[ 15.259874] Bluetooth: HCI socket layer initialized
10478 00:57:50.057860 <6>[ 15.259885] Bluetooth: L2CAP socket layer initialized
10479 00:57:50.062709 <6>[ 15.259908] Bluetooth: SCO socket layer initialized
10480 00:57:50.069600 <6>[ 15.267100] usbcore: registered new interface driver r8152
10481 00:57:50.075646 <6>[ 15.275784] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10482 00:57:50.079660 <6>[ 15.311729] usbcore: registered new interface driver cdc_ether
10483 00:57:50.085838 <6>[ 15.312739] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10484 00:57:50.099053 <6>[ 15.314129] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10485 00:57:50.105671 <6>[ 15.314223] usbcore: registered new interface driver uvcvideo
10486 00:57:50.112031 <6>[ 15.319137] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10487 00:57:50.119429 <6>[ 15.319184] usbcore: registered new interface driver btusb
10488 00:57:50.128887 <4>[ 15.320004] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10489 00:57:50.135982 <3>[ 15.320018] Bluetooth: hci0: Failed to load firmware file (-2)
10490 00:57:50.139471 <3>[ 15.320023] Bluetooth: hci0: Failed to set up firmware (-2)
10491 00:57:50.152093 <4>[ 15.320029] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10492 00:57:50.154976 <6>[ 15.338063] usbcore: registered new interface driver r8153_ecm
10493 00:57:50.161737 <6>[ 15.338819] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10494 00:57:50.172111 <5>[ 15.361921] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10495 00:57:50.178311 <6>[ 15.373770] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10496 00:57:50.184549 <5>[ 15.389918] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10497 00:57:50.191569 <5>[ 15.652776] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10498 00:57:50.201517 <4>[ 15.661806] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10499 00:57:50.208517 <6>[ 15.670710] cfg80211: failed to load regulatory.db
10500 00:57:50.247254 <6>[ 15.707147] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10501 00:57:50.254098 <6>[ 15.714751] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10502 00:57:50.278540 <6>[ 15.741509] mt7921e 0000:01:00.0: ASIC revision: 79610010
10503 00:57:50.381811 <6>[ 15.841700] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10504 00:57:50.385067 <6>[ 15.841700]
10505 00:57:50.389894 Begin: Loading essential drivers ... done.
10506 00:57:50.391551 Begin: Running /scripts/init-premount ... done.
10507 00:57:50.398191 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10508 00:57:50.408493 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10509 00:57:50.411496 Device /sys/class/net/enx00e04c6803bd found
10510 00:57:50.412045 done.
10511 00:57:50.450718 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10512 00:57:50.651494 <6>[ 16.111624] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10513 00:57:51.375260 <6>[ 16.838375] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10514 00:57:51.492604 <6>[ 16.955466] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10515 00:57:51.685395 IP-Config: no response after 2 secs - giving up
10516 00:57:51.738377 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10517 00:57:51.767052 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10518 00:57:52.467281 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10519 00:57:52.475034 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10520 00:57:52.481027 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10521 00:57:52.488174 host : mt8192-asurada-spherion-r0-cbg-4
10522 00:57:52.494390 domain : lava-rack
10523 00:57:52.497462 rootserver: 192.168.201.1 rootpath:
10524 00:57:52.500622 filename :
10525 00:57:52.600822 done.
10526 00:57:52.607897 Begin: Running /scripts/nfs-bottom ... done.
10527 00:57:52.627283 Begin: Running /scripts/init-bottom ... done.
10528 00:57:53.831341 <6>[ 19.294778] NET: Registered PF_INET6 protocol family
10529 00:57:53.838770 <6>[ 19.302383] Segment Routing with IPv6
10530 00:57:53.842205 <6>[ 19.306372] In-situ OAM (IOAM) with IPv6
10531 00:57:53.962998 <30>[ 19.409878] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10532 00:57:53.970762 <30>[ 19.434238] systemd[1]: Detected architecture arm64.
10533 00:57:53.990405
10534 00:57:53.994246 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10535 00:57:53.994701
10536 00:57:54.009619 <30>[ 19.473282] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10537 00:57:54.869132 <30>[ 20.329327] systemd[1]: Queued start job for default target Graphical Interface.
10538 00:57:54.909660 <30>[ 20.373209] systemd[1]: Created slice system-getty.slice.
10539 00:57:54.916094 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10540 00:57:54.932491 <30>[ 20.396113] systemd[1]: Created slice system-modprobe.slice.
10541 00:57:54.938473 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10542 00:57:54.957045 <30>[ 20.420837] systemd[1]: Created slice system-serial\x2dgetty.slice.
10543 00:57:54.967911 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10544 00:57:54.980007 <30>[ 20.443780] systemd[1]: Created slice User and Session Slice.
10545 00:57:54.986289 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10546 00:57:55.007316 <30>[ 20.467574] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10547 00:57:55.017058 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10548 00:57:55.035447 <30>[ 20.495508] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10549 00:57:55.042519 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10550 00:57:55.065928 <30>[ 20.522859] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10551 00:57:55.072260 <30>[ 20.535009] systemd[1]: Reached target Local Encrypted Volumes.
10552 00:57:55.078799 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10553 00:57:55.096036 <30>[ 20.559305] systemd[1]: Reached target Paths.
10554 00:57:55.099006 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10555 00:57:55.115277 <30>[ 20.578716] systemd[1]: Reached target Remote File Systems.
10556 00:57:55.122242 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10557 00:57:55.134689 <30>[ 20.598689] systemd[1]: Reached target Slices.
10558 00:57:55.141437 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10559 00:57:55.155127 <30>[ 20.618723] systemd[1]: Reached target Swap.
10560 00:57:55.158107 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10561 00:57:55.179074 <30>[ 20.639178] systemd[1]: Listening on initctl Compatibility Named Pipe.
10562 00:57:55.185141 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10563 00:57:55.192025 <30>[ 20.655334] systemd[1]: Listening on Journal Audit Socket.
10564 00:57:55.198571 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10565 00:57:55.216783 <30>[ 20.680175] systemd[1]: Listening on Journal Socket (/dev/log).
10566 00:57:55.223518 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10567 00:57:55.239474 <30>[ 20.703339] systemd[1]: Listening on Journal Socket.
10568 00:57:55.246200 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10569 00:57:55.264389 <30>[ 20.724396] systemd[1]: Listening on Network Service Netlink Socket.
10570 00:57:55.270126 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10571 00:57:55.286077 <30>[ 20.749879] systemd[1]: Listening on udev Control Socket.
10572 00:57:55.292182 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10573 00:57:55.307217 <30>[ 20.771158] systemd[1]: Listening on udev Kernel Socket.
10574 00:57:55.314056 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10575 00:57:55.363673 <30>[ 20.827154] systemd[1]: Mounting Huge Pages File System...
10576 00:57:55.369556 Mounting [0;1;39mHuge Pages File System[0m...
10577 00:57:55.387702 <30>[ 20.851149] systemd[1]: Mounting POSIX Message Queue File System...
10578 00:57:55.394181 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10579 00:57:55.413124 <30>[ 20.877601] systemd[1]: Mounting Kernel Debug File System...
10580 00:57:55.419808 Mounting [0;1;39mKernel Debug File System[0m...
10581 00:57:55.438777 <30>[ 20.899192] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10582 00:57:55.455440 <30>[ 20.916096] systemd[1]: Starting Create list of static device nodes for the current kernel...
10583 00:57:55.461268 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10584 00:57:55.484009 <30>[ 20.947632] systemd[1]: Starting Load Kernel Module configfs...
10585 00:57:55.490728 Starting [0;1;39mLoad Kernel Module configfs[0m...
10586 00:57:55.508088 <30>[ 20.971522] systemd[1]: Starting Load Kernel Module drm...
10587 00:57:55.514458 Starting [0;1;39mLoad Kernel Module drm[0m...
10588 00:57:55.531836 <30>[ 20.995558] systemd[1]: Starting Load Kernel Module fuse...
10589 00:57:55.538725 Starting [0;1;39mLoad Kernel Module fuse[0m...
10590 00:57:55.575495 <30>[ 21.036378] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10591 00:57:55.582276 <6>[ 21.046611] fuse: init (API version 7.37)
10592 00:57:55.607618 <30>[ 21.071542] systemd[1]: Starting Journal Service...
10593 00:57:55.613936 Starting [0;1;39mJournal Service[0m...
10594 00:57:55.638968 <30>[ 21.103255] systemd[1]: Starting Load Kernel Modules...
10595 00:57:55.645525 Starting [0;1;39mLoad Kernel Modules[0m...
10596 00:57:55.668515 <30>[ 21.129491] systemd[1]: Starting Remount Root and Kernel File Systems...
10597 00:57:55.675255 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10598 00:57:55.696487 <30>[ 21.160395] systemd[1]: Starting Coldplug All udev Devices...
10599 00:57:55.703927 Starting [0;1;39mColdplug All udev Devices[0m...
10600 00:57:55.727289 <3>[ 21.187753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10601 00:57:55.733805 <30>[ 21.189806] systemd[1]: Mounted Huge Pages File System.
10602 00:57:55.739752 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10603 00:57:55.755381 <3>[ 21.215499] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10604 00:57:55.762291 <30>[ 21.225435] systemd[1]: Mounted POSIX Message Queue File System.
10605 00:57:55.768317 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10606 00:57:55.783689 <30>[ 21.247018] systemd[1]: Mounted Kernel Debug File System.
10607 00:57:55.797322 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 21.258002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10608 00:57:55.800131 m.
10609 00:57:55.819433 <30>[ 21.279510] systemd[1]: Finished Create list of static device nodes for the current kernel.
10610 00:57:55.829695 <3>[ 21.285750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 00:57:55.836549 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10612 00:57:55.851975 <30>[ 21.315630] systemd[1]: modprobe@configfs.service: Succeeded.
10613 00:57:55.863079 <3>[ 21.315911] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10614 00:57:55.869389 <30>[ 21.322216] systemd[1]: Finished Load Kernel Module configfs.
10615 00:57:55.875177 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10616 00:57:55.889617 <3>[ 21.350336] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 00:57:55.897288 <30>[ 21.360730] systemd[1]: modprobe@drm.service: Succeeded.
10618 00:57:55.903979 <30>[ 21.367594] systemd[1]: Finished Load Kernel Module drm.
10619 00:57:55.911264 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10620 00:57:55.920193 <3>[ 21.379907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10621 00:57:55.928609 <30>[ 21.392571] systemd[1]: modprobe@fuse.service: Succeeded.
10622 00:57:55.936301 <30>[ 21.399600] systemd[1]: Finished Load Kernel Module fuse.
10623 00:57:55.949880 [[0;32m OK [0m] Finished [0<3>[ 21.407615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10624 00:57:55.953089 ;1;39mLoad Kernel Module fuse[0m.
10625 00:57:55.968477 <30>[ 21.431790] systemd[1]: Finished Load Kernel Modules.
10626 00:57:55.978023 <3>[ 21.435976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10627 00:57:55.982367 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10628 00:57:56.000174 <30>[ 21.463404] systemd[1]: Finished Remount Root and Kernel File Systems.
10629 00:57:56.009577 <3>[ 21.464991] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10630 00:57:56.016546 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10631 00:57:56.056117 <30>[ 21.520028] systemd[1]: Mounting FUSE Control File System...
10632 00:57:56.062432 Mounting [0;1;39mFUSE Control File System[0m...
10633 00:57:56.086221 <30>[ 21.546714] systemd[1]: Mounting Kernel Configuration File System...
10634 00:57:56.089150 Mounting [0;1;39mKernel Configuration File System[0m...
10635 00:57:56.115270 <30>[ 21.575523] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10636 00:57:56.125010 <30>[ 21.584527] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10637 00:57:56.151890 <30>[ 21.615558] systemd[1]: Starting Load/Save Random Seed...
10638 00:57:56.157871 Starting [0;1;39mLoad/Save Random Seed[0m...
10639 00:57:56.175793 <30>[ 21.639402] systemd[1]: Starting Apply Kernel Variables...
10640 00:57:56.182509 Starting [0;1;39mApply Kernel Variables[0m...
10641 00:57:56.201307 <30>[ 21.665617] systemd[1]: Starting Create System Users...
10642 00:57:56.207822 Starting [0;1;39mCreate System Users[0m...
10643 00:57:56.227473 <4>[ 21.681451] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10644 00:57:56.233849 <3>[ 21.697143] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10645 00:57:56.242740 <30>[ 21.707179] systemd[1]: Started Journal Service.
10646 00:57:56.249788 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10647 00:57:56.268370 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10648 00:57:56.282757 See 'systemctl status systemd-udev-trigger.service' for details.
10649 00:57:56.299585 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10650 00:57:56.316003 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10651 00:57:56.332599 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10652 00:57:56.348895 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10653 00:57:56.364869 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10654 00:57:56.419990 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10655 00:57:56.438280 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10656 00:57:56.471560 <46>[ 21.931990] systemd-journald[289]: Received client request to flush runtime journal.
10657 00:57:57.232491 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10658 00:57:57.247254 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10659 00:57:57.262403 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10660 00:57:57.310440 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10661 00:57:57.876425 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10662 00:57:57.931150 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10663 00:57:57.974399 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10664 00:57:58.024155 Starting [0;1;39mNetwork Service[0m...
10665 00:57:58.322945 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10666 00:57:58.347265 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10667 00:57:58.407235 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10668 00:57:58.709057 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10669 00:57:58.726657 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10670 00:57:58.771811 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10671 00:57:58.793156 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10672 00:57:58.812824 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10673 00:57:58.831566 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10674 00:57:58.855784 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10675 00:57:58.931670 Starting [0;1;39mNetwork Name Resolution[0m...
10676 00:57:58.960249 Starting [0;1;39mNetwork Time Synchronization[0m...
10677 00:57:58.979731 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10678 00:57:59.045056 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10679 00:57:59.128769 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10680 00:57:59.150369 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10681 00:57:59.169228 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10682 00:57:59.182173 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10683 00:57:59.198209 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10684 00:57:59.305502 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10685 00:57:59.369034 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10686 00:57:59.405365 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10687 00:57:59.447186 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10688 00:57:59.459120 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10689 00:57:59.812647 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10690 00:57:59.826312 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10691 00:57:59.842053 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10692 00:57:59.898629 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10693 00:58:00.226500 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10694 00:58:00.607500 Starting [0;1;39mUser Login Management[0m...
10695 00:58:00.723029 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10696 00:58:00.738787 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10697 00:58:00.758302 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10698 00:58:00.799063 Starting [0;1;39mPermit User Sessions[0m...
10699 00:58:00.881980 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10700 00:58:00.923131 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10701 00:58:00.963541 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10702 00:58:00.981148 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10703 00:58:00.999993 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10704 00:58:01.018326 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10705 00:58:01.040178 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10706 00:58:01.054688 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10707 00:58:01.101775 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10708 00:58:01.153777 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10709 00:58:01.252759
10710 00:58:01.252935
10711 00:58:01.255832 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10712 00:58:01.255948
10713 00:58:01.258998 debian-bullseye-arm64 login: root (automatic login)
10714 00:58:01.259114
10715 00:58:01.259204
10716 00:58:01.611775 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
10717 00:58:01.611919
10718 00:58:01.618544 The programs included with the Debian GNU/Linux system are free software;
10719 00:58:01.626964 the exact distribution terms for each program are described in the
10720 00:58:01.628801 individual files in /usr/share/doc/*/copyright.
10721 00:58:01.628881
10722 00:58:01.634716 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10723 00:58:01.638185 permitted by applicable law.
10724 00:58:02.461898 Matched prompt #10: / #
10726 00:58:02.462185 Setting prompt string to ['/ #']
10727 00:58:02.462280 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10729 00:58:02.462476 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10730 00:58:02.462565 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10731 00:58:02.462634 Setting prompt string to ['/ #']
10732 00:58:02.462695 Forcing a shell prompt, looking for ['/ #']
10734 00:58:02.512971 / #
10735 00:58:02.513708 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10736 00:58:02.514267 Waiting using forced prompt support (timeout 00:02:30)
10737 00:58:02.519675
10738 00:58:02.520602 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10739 00:58:02.521199 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10741 00:58:02.622426 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr'
10742 00:58:02.629464 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12571063/extract-nfsrootfs-v30rekgr'
10744 00:58:02.730965 / # export NFS_SERVER_IP='192.168.201.1'
10745 00:58:02.738563 export NFS_SERVER_IP='192.168.201.1'
10746 00:58:02.739514 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10747 00:58:02.740062 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10748 00:58:02.740557 end: 2 depthcharge-action (duration 00:01:26) [common]
10749 00:58:02.741138 start: 3 lava-test-retry (timeout 00:07:50) [common]
10750 00:58:02.741678 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
10751 00:58:02.742097 Using namespace: common
10753 00:58:02.843234 / # #
10754 00:58:02.843881 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10755 00:58:02.851298 #
10756 00:58:02.852197 Using /lava-12571063
10758 00:58:02.953522 / # export SHELL=/bin/bash
10759 00:58:02.960603 export SHELL=/bin/bash
10761 00:58:03.062548 / # . /lava-12571063/environment
10762 00:58:03.069641 . /lava-12571063/environment
10764 00:58:03.176481 / # /lava-12571063/bin/lava-test-runner /lava-12571063/0
10765 00:58:03.177155 Test shell timeout: 10s (minimum of the action and connection timeout)
10766 00:58:03.183605 /lava-12571063/bin/lava-test-runner /lava-12571063/0
10767 00:58:03.467223 + export TESTRUN_ID=0_timesync-off
10768 00:58:03.470277 + TESTRUN_ID=0_timesync-off
10769 00:58:03.474884 + cd /lava-12571063/0/tests/0_timesync-off
10770 00:58:03.477331 ++ cat uuid
10771 00:58:03.481726 + UUID=12571063_1.6.2.3.1
10772 00:58:03.482139 + set +x
10773 00:58:03.488342 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12571063_1.6.2.3.1>
10774 00:58:03.489038 Received signal: <STARTRUN> 0_timesync-off 12571063_1.6.2.3.1
10775 00:58:03.489409 Starting test lava.0_timesync-off (12571063_1.6.2.3.1)
10776 00:58:03.489856 Skipping test definition patterns.
10777 00:58:03.491472 + systemctl stop systemd-timesyncd
10778 00:58:03.570151 + set +x
10779 00:58:03.573965 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12571063_1.6.2.3.1>
10780 00:58:03.574796 Received signal: <ENDRUN> 0_timesync-off 12571063_1.6.2.3.1
10781 00:58:03.575255 Ending use of test pattern.
10782 00:58:03.575639 Ending test lava.0_timesync-off (12571063_1.6.2.3.1), duration 0.09
10784 00:58:03.660084 + export TESTRUN_ID=1_kselftest-tpm2
10785 00:58:03.663476 + TESTRUN_ID=1_kselftest-tpm2
10786 00:58:03.669610 + cd /lava-12571063/0/tests/1_kselftest-tpm2
10787 00:58:03.670077 ++ cat uuid
10788 00:58:03.676190 + UUID=12571063_1.6.2.3.5
10789 00:58:03.676648 + set +x
10790 00:58:03.682397 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12571063_1.6.2.3.5>
10791 00:58:03.683121 Received signal: <STARTRUN> 1_kselftest-tpm2 12571063_1.6.2.3.5
10792 00:58:03.683505 Starting test lava.1_kselftest-tpm2 (12571063_1.6.2.3.5)
10793 00:58:03.683923 Skipping test definition patterns.
10794 00:58:03.685289 + cd ./automated/linux/kselftest/
10795 00:58:03.711231 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10796 00:58:03.750699 INFO: install_deps skipped
10797 00:58:03.866184 --2024-01-19 00:58:03-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10798 00:58:03.872948 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10799 00:58:04.004525 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10800 00:58:04.137935 HTTP request sent, awaiting response... 200 OK
10801 00:58:04.141706 Length: 2966476 (2.8M) [application/octet-stream]
10802 00:58:04.144384 Saving to: 'kselftest.tar.xz'
10803 00:58:04.144988
10804 00:58:04.145354
10805 00:58:04.406295 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10806 00:58:04.673808 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
10807 00:58:05.124636 kselftest.tar.xz 7%[> ] 218.91K 410KB/s
10808 00:58:05.398115 kselftest.tar.xz 28%[====> ] 812.82K 825KB/s
10809 00:58:05.404670 kselftest.tar.xz 81%[===============> ] 2.32M 1.84MB/s
10810 00:58:05.411322 kselftest.tar.xz 100%[===================>] 2.83M 2.23MB/s in 1.3s
10811 00:58:05.411433
10812 00:58:05.669751 2024-01-19 00:58:05 (2.23 MB/s) - 'kselftest.tar.xz' saved [2966476/2966476]
10813 00:58:05.670298
10814 00:58:11.035048 skiplist:
10815 00:58:11.038880 ========================================
10816 00:58:11.042557 ========================================
10817 00:58:11.084092 tpm2:test_smoke.sh
10818 00:58:11.088004 tpm2:test_space.sh
10819 00:58:11.103603 ============== Tests to run ===============
10820 00:58:11.104059 tpm2:test_smoke.sh
10821 00:58:11.106806 tpm2:test_space.sh
10822 00:58:11.111432 ===========End Tests to run ===============
10823 00:58:11.113761 shardfile-tpm2 pass
10824 00:58:11.225777 <12>[ 36.691512] kselftest: Running tests in tpm2
10825 00:58:11.237825 TAP version 13
10826 00:58:11.250367 1..2
10827 00:58:11.284559 # selftests: tpm2: test_smoke.sh
10828 00:58:12.768502 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
10829 00:58:12.772522 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
10830 00:58:12.778484 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10831 00:58:12.781848 # Traceback (most recent call last):
10832 00:58:12.791817 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10833 00:58:12.794961 # if self.tpm:
10834 00:58:12.798717 # AttributeError: 'Client' object has no attribute 'tpm'
10835 00:58:12.805038 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
10836 00:58:12.808430 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10837 00:58:12.811699 # Traceback (most recent call last):
10838 00:58:12.821484 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10839 00:58:12.824800 # if self.tpm:
10840 00:58:12.828180 # AttributeError: 'Client' object has no attribute 'tpm'
10841 00:58:12.834637 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
10842 00:58:12.841424 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10843 00:58:12.844285 # Traceback (most recent call last):
10844 00:58:12.854240 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10845 00:58:12.854820 # if self.tpm:
10846 00:58:12.861370 # AttributeError: 'Client' object has no attribute 'tpm'
10847 00:58:12.864504 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
10848 00:58:12.871574 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10849 00:58:12.874719 # Traceback (most recent call last):
10850 00:58:12.885260 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10851 00:58:12.887540 # if self.tpm:
10852 00:58:12.890788 # AttributeError: 'Client' object has no attribute 'tpm'
10853 00:58:12.897306 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
10854 00:58:12.900996 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10855 00:58:12.904104 # Traceback (most recent call last):
10856 00:58:12.914542 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10857 00:58:12.917166 # if self.tpm:
10858 00:58:12.923466 # AttributeError: 'Client' object has no attribute 'tpm'
10859 00:58:12.926855 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
10860 00:58:12.933661 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10861 00:58:12.937911 # Traceback (most recent call last):
10862 00:58:12.947162 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10863 00:58:12.947625 # if self.tpm:
10864 00:58:12.953487 # AttributeError: 'Client' object has no attribute 'tpm'
10865 00:58:12.956873 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
10866 00:58:12.963940 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10867 00:58:12.966985 # Traceback (most recent call last):
10868 00:58:12.976918 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10869 00:58:12.980477 # if self.tpm:
10870 00:58:12.983626 # AttributeError: 'Client' object has no attribute 'tpm'
10871 00:58:12.990506 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
10872 00:58:12.997353 # Exception ignored in: <function Client.__del__ at 0xffff8dbbad30>
10873 00:58:13.000150 # Traceback (most recent call last):
10874 00:58:13.010290 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10875 00:58:13.010858 # if self.tpm:
10876 00:58:13.016578 # AttributeError: 'Client' object has no attribute 'tpm'
10877 00:58:13.017250 #
10878 00:58:13.022964 # ======================================================================
10879 00:58:13.026390 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
10880 00:58:13.032861 # ----------------------------------------------------------------------
10881 00:58:13.036596 # Traceback (most recent call last):
10882 00:58:13.046963 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10883 00:58:13.052814 # self.root_key = self.client.create_root_key()
10884 00:58:13.063242 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10885 00:58:13.069995 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10886 00:58:13.079813 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10887 00:58:13.083666 # raise ProtocolError(cc, rc)
10888 00:58:13.085994 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10889 00:58:13.086650 #
10890 00:58:13.093227 # ======================================================================
10891 00:58:13.099230 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
10892 00:58:13.106573 # ----------------------------------------------------------------------
10893 00:58:13.110167 # Traceback (most recent call last):
10894 00:58:13.119530 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10895 00:58:13.122680 # self.client = tpm2.Client()
10896 00:58:13.132696 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10897 00:58:13.136159 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10898 00:58:13.144514 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10899 00:58:13.145056 #
10900 00:58:13.149403 # ======================================================================
10901 00:58:13.152593 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
10902 00:58:13.159038 # ----------------------------------------------------------------------
10903 00:58:13.162404 # Traceback (most recent call last):
10904 00:58:13.172334 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10905 00:58:13.176135 # self.client = tpm2.Client()
10906 00:58:13.185593 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10907 00:58:13.191792 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10908 00:58:13.195829 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10909 00:58:13.196245 #
10910 00:58:13.202186 # ======================================================================
10911 00:58:13.208990 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
10912 00:58:13.215739 # ----------------------------------------------------------------------
10913 00:58:13.218461 # Traceback (most recent call last):
10914 00:58:13.228675 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10915 00:58:13.232237 # self.client = tpm2.Client()
10916 00:58:13.241708 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10917 00:58:13.245022 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10918 00:58:13.251968 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10919 00:58:13.252487 #
10920 00:58:13.258423 # ======================================================================
10921 00:58:13.262236 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
10922 00:58:13.268562 # ----------------------------------------------------------------------
10923 00:58:13.271678 # Traceback (most recent call last):
10924 00:58:13.281689 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10925 00:58:13.284941 # self.client = tpm2.Client()
10926 00:58:13.295332 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10927 00:58:13.301742 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10928 00:58:13.304490 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10929 00:58:13.305053 #
10930 00:58:13.311179 # ======================================================================
10931 00:58:13.318011 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
10932 00:58:13.325137 # ----------------------------------------------------------------------
10933 00:58:13.327882 # Traceback (most recent call last):
10934 00:58:13.338163 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10935 00:58:13.341091 # self.client = tpm2.Client()
10936 00:58:13.352605 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10937 00:58:13.354487 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10938 00:58:13.361213 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10939 00:58:13.361671 #
10940 00:58:13.367631 # ======================================================================
10941 00:58:13.370890 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
10942 00:58:13.378278 # ----------------------------------------------------------------------
10943 00:58:13.380464 # Traceback (most recent call last):
10944 00:58:13.390806 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10945 00:58:13.394243 # self.client = tpm2.Client()
10946 00:58:13.405640 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10947 00:58:13.407842 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10948 00:58:13.414806 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10949 00:58:13.415358 #
10950 00:58:13.419774 # ======================================================================
10951 00:58:13.425542 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
10952 00:58:13.433845 # ----------------------------------------------------------------------
10953 00:58:13.435785 # Traceback (most recent call last):
10954 00:58:13.444554 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10955 00:58:13.448131 # self.client = tpm2.Client()
10956 00:58:13.461639 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10957 00:58:13.464955 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10958 00:58:13.469092 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10959 00:58:13.469665 #
10960 00:58:13.475127 # ======================================================================
10961 00:58:13.482395 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
10962 00:58:13.488300 # ----------------------------------------------------------------------
10963 00:58:13.491856 # Traceback (most recent call last):
10964 00:58:13.501748 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10965 00:58:13.505060 # self.client = tpm2.Client()
10966 00:58:13.515977 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10967 00:58:13.518393 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10968 00:58:13.524786 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10969 00:58:13.525457 #
10970 00:58:13.531786 # ----------------------------------------------------------------------
10971 00:58:13.532394 # Ran 9 tests in 0.051s
10972 00:58:13.532820 #
10973 00:58:13.535318 # FAILED (errors=9)
10974 00:58:13.537975 # test_async (tpm2_tests.AsyncTest) ... ok
10975 00:58:13.544347 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
10976 00:58:13.544851 #
10977 00:58:13.551625 # ----------------------------------------------------------------------
10978 00:58:13.552086 # Ran 2 tests in 0.039s
10979 00:58:13.555435 #
10980 00:58:13.555893 # OK
10981 00:58:13.557601 ok 1 selftests: tpm2: test_smoke.sh
10982 00:58:13.561310 # selftests: tpm2: test_space.sh
10983 00:58:13.565012 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
10984 00:58:13.568252 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
10985 00:58:13.574673 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
10986 00:58:13.577865 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
10987 00:58:13.578327 #
10988 00:58:13.583950 # ======================================================================
10989 00:58:13.590918 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
10990 00:58:13.598399 # ----------------------------------------------------------------------
10991 00:58:13.601305 # Traceback (most recent call last):
10992 00:58:13.610625 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
10993 00:58:13.614178 # root1 = space1.create_root_key()
10994 00:58:13.623849 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10995 00:58:13.630724 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10996 00:58:13.640945 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10997 00:58:13.644090 # raise ProtocolError(cc, rc)
10998 00:58:13.650682 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10999 00:58:13.651255 #
11000 00:58:13.657529 # ======================================================================
11001 00:58:13.660695 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11002 00:58:13.667488 # ----------------------------------------------------------------------
11003 00:58:13.670213 # Traceback (most recent call last):
11004 00:58:13.680814 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11005 00:58:13.684150 # space1.create_root_key()
11006 00:58:13.693320 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11007 00:58:13.700396 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11008 00:58:13.709708 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11009 00:58:13.713082 # raise ProtocolError(cc, rc)
11010 00:58:13.719752 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11011 00:58:13.720211 #
11012 00:58:13.726548 # ======================================================================
11013 00:58:13.730134 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11014 00:58:13.735994 # ----------------------------------------------------------------------
11015 00:58:13.739398 # Traceback (most recent call last):
11016 00:58:13.749358 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11017 00:58:13.752322 # root1 = space1.create_root_key()
11018 00:58:13.765653 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11019 00:58:13.770261 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11020 00:58:13.778872 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11021 00:58:13.782234 # raise ProtocolError(cc, rc)
11022 00:58:13.789071 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11023 00:58:13.789152 #
11024 00:58:13.795418 # ======================================================================
11025 00:58:13.798740 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11026 00:58:13.805911 # ----------------------------------------------------------------------
11027 00:58:13.808363 # Traceback (most recent call last):
11028 00:58:13.822768 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11029 00:58:13.825519 # root1 = space1.create_root_key()
11030 00:58:13.835214 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11031 00:58:13.842999 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11032 00:58:13.852609 # File "/lava-12571063/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11033 00:58:13.855171 # raise ProtocolError(cc, rc)
11034 00:58:13.858811 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11035 00:58:13.861773 #
11036 00:58:13.868374 # ----------------------------------------------------------------------
11037 00:58:13.868612 # Ran 4 tests in 0.083s
11038 00:58:13.868759 #
11039 00:58:13.871971 # FAILED (errors=4)
11040 00:58:13.874906 not ok 2 selftests: tpm2: test_space.sh # exit=1
11041 00:58:13.878241 tpm2_test_smoke_sh pass
11042 00:58:13.878537 tpm2_test_space_sh fail
11043 00:58:13.885259 + ../../utils/send-to-lava.sh ./output/result.txt
11044 00:58:13.888107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11045 00:58:13.888748 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11047 00:58:13.894902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11048 00:58:13.895677 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11050 00:58:13.902347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11051 00:58:13.902922 + set +x
11052 00:58:13.903576 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11054 00:58:13.908328 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12571063_1.6.2.3.5>
11055 00:58:13.908935 <LAVA_TEST_RUNNER EXIT>
11056 00:58:13.909583 Received signal: <ENDRUN> 1_kselftest-tpm2 12571063_1.6.2.3.5
11057 00:58:13.909973 Ending use of test pattern.
11058 00:58:13.910308 Ending test lava.1_kselftest-tpm2 (12571063_1.6.2.3.5), duration 10.23
11060 00:58:13.911497 ok: lava_test_shell seems to have completed
11061 00:58:13.912044 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11062 00:58:13.912485 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11063 00:58:13.912965 end: 3 lava-test-retry (duration 00:00:11) [common]
11064 00:58:13.913429 start: 4 finalize (timeout 00:07:39) [common]
11065 00:58:13.913919 start: 4.1 power-off (timeout 00:00:30) [common]
11066 00:58:13.914737 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11067 00:58:14.030825 >> Command sent successfully.
11068 00:58:14.034460 Returned 0 in 0 seconds
11069 00:58:14.135362 end: 4.1 power-off (duration 00:00:00) [common]
11071 00:58:14.137424 start: 4.2 read-feedback (timeout 00:07:38) [common]
11072 00:58:14.138739 Listened to connection for namespace 'common' for up to 1s
11073 00:58:14.139643 Listened to connection for namespace 'common' for up to 1s
11074 00:58:15.139372 Finalising connection for namespace 'common'
11075 00:58:15.140061 Disconnecting from shell: Finalise
11076 00:58:15.140495 / #
11077 00:58:15.241598 end: 4.2 read-feedback (duration 00:00:01) [common]
11078 00:58:15.242300 end: 4 finalize (duration 00:00:01) [common]
11079 00:58:15.242898 Cleaning after the job
11080 00:58:15.243426 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/ramdisk
11081 00:58:15.257333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/kernel
11082 00:58:15.292487 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/dtb
11083 00:58:15.292777 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/nfsrootfs
11084 00:58:15.387203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571063/tftp-deploy-81zhmeaq/modules
11085 00:58:15.394677 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571063
11086 00:58:16.030286 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571063
11087 00:58:16.030470 Job finished correctly