Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 7
- Errors: 3
- Kernel Errors: 5
- Boot result: FAIL
1 00:58:59.444058 lava-dispatcher, installed at version: 2023.10
2 00:58:59.444284 start: 0 validate
3 00:58:59.444424 Start time: 2024-01-19 00:58:59.444416+00:00 (UTC)
4 00:58:59.444542 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:58:59.444678 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 00:58:59.706125 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:58:59.706297 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:58:59.972471 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:58:59.972634 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:59:00.237885 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:59:00.238080 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:59:00.503494 Using caching service: 'http://localhost/cache/?uri=%s'
13 00:59:00.503666 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 00:59:00.772604 validate duration: 1.33
16 00:59:00.772904 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:59:00.773005 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:59:00.773092 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:59:00.773218 Not decompressing ramdisk as can be used compressed.
20 00:59:00.773303 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 00:59:00.773371 saving as /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/ramdisk/initrd.cpio.gz
22 00:59:00.773435 total size: 4665398 (4 MB)
23 00:59:00.774487 progress 0 % (0 MB)
24 00:59:00.776076 progress 5 % (0 MB)
25 00:59:00.777436 progress 10 % (0 MB)
26 00:59:00.778695 progress 15 % (0 MB)
27 00:59:00.779990 progress 20 % (0 MB)
28 00:59:00.781318 progress 25 % (1 MB)
29 00:59:00.782567 progress 30 % (1 MB)
30 00:59:00.783842 progress 35 % (1 MB)
31 00:59:00.785078 progress 40 % (1 MB)
32 00:59:00.786557 progress 45 % (2 MB)
33 00:59:00.787832 progress 50 % (2 MB)
34 00:59:00.789085 progress 55 % (2 MB)
35 00:59:00.790404 progress 60 % (2 MB)
36 00:59:00.791639 progress 65 % (2 MB)
37 00:59:00.792915 progress 70 % (3 MB)
38 00:59:00.794160 progress 75 % (3 MB)
39 00:59:00.795438 progress 80 % (3 MB)
40 00:59:00.796860 progress 85 % (3 MB)
41 00:59:00.798088 progress 90 % (4 MB)
42 00:59:00.799399 progress 95 % (4 MB)
43 00:59:00.800686 progress 100 % (4 MB)
44 00:59:00.800839 4 MB downloaded in 0.03 s (162.36 MB/s)
45 00:59:00.800988 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:59:00.801228 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:59:00.801315 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:59:00.801403 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:59:00.801534 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 00:59:00.801606 saving as /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/kernel/Image
52 00:59:00.801666 total size: 51532288 (49 MB)
53 00:59:00.801727 No compression specified
54 00:59:00.802799 progress 0 % (0 MB)
55 00:59:00.816598 progress 5 % (2 MB)
56 00:59:00.830352 progress 10 % (4 MB)
57 00:59:00.843998 progress 15 % (7 MB)
58 00:59:00.857850 progress 20 % (9 MB)
59 00:59:00.871553 progress 25 % (12 MB)
60 00:59:00.885643 progress 30 % (14 MB)
61 00:59:00.899403 progress 35 % (17 MB)
62 00:59:00.913184 progress 40 % (19 MB)
63 00:59:00.926779 progress 45 % (22 MB)
64 00:59:00.940510 progress 50 % (24 MB)
65 00:59:00.954009 progress 55 % (27 MB)
66 00:59:00.967522 progress 60 % (29 MB)
67 00:59:00.980904 progress 65 % (31 MB)
68 00:59:00.994179 progress 70 % (34 MB)
69 00:59:01.007625 progress 75 % (36 MB)
70 00:59:01.021125 progress 80 % (39 MB)
71 00:59:01.034397 progress 85 % (41 MB)
72 00:59:01.047874 progress 90 % (44 MB)
73 00:59:01.061841 progress 95 % (46 MB)
74 00:59:01.075055 progress 100 % (49 MB)
75 00:59:01.075268 49 MB downloaded in 0.27 s (179.62 MB/s)
76 00:59:01.075419 end: 1.2.1 http-download (duration 00:00:00) [common]
78 00:59:01.075650 end: 1.2 download-retry (duration 00:00:00) [common]
79 00:59:01.075747 start: 1.3 download-retry (timeout 00:10:00) [common]
80 00:59:01.075833 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 00:59:01.075972 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 00:59:01.076040 saving as /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/dtb/mt8192-asurada-spherion-r0.dtb
83 00:59:01.076100 total size: 47278 (0 MB)
84 00:59:01.076160 No compression specified
85 00:59:01.077273 progress 69 % (0 MB)
86 00:59:01.077627 progress 100 % (0 MB)
87 00:59:01.077861 0 MB downloaded in 0.00 s (25.65 MB/s)
88 00:59:01.077987 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:59:01.078209 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:59:01.078297 start: 1.4 download-retry (timeout 00:10:00) [common]
92 00:59:01.078380 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 00:59:01.078494 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 00:59:01.078560 saving as /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/nfsrootfs/full.rootfs.tar
95 00:59:01.078619 total size: 89451516 (85 MB)
96 00:59:01.078679 Using unxz to decompress xz
97 00:59:01.082880 progress 0 % (0 MB)
98 00:59:01.295686 progress 5 % (4 MB)
99 00:59:01.515069 progress 10 % (8 MB)
100 00:59:01.770639 progress 15 % (12 MB)
101 00:59:01.966548 progress 20 % (17 MB)
102 00:59:02.061553 progress 25 % (21 MB)
103 00:59:02.306796 progress 30 % (25 MB)
104 00:59:02.592015 progress 35 % (29 MB)
105 00:59:02.853898 progress 40 % (34 MB)
106 00:59:03.118184 progress 45 % (38 MB)
107 00:59:03.367293 progress 50 % (42 MB)
108 00:59:03.636386 progress 55 % (46 MB)
109 00:59:03.892175 progress 60 % (51 MB)
110 00:59:04.165075 progress 65 % (55 MB)
111 00:59:04.458579 progress 70 % (59 MB)
112 00:59:04.761167 progress 75 % (64 MB)
113 00:59:05.055704 progress 80 % (68 MB)
114 00:59:05.312211 progress 85 % (72 MB)
115 00:59:05.546970 progress 90 % (76 MB)
116 00:59:05.813453 progress 95 % (81 MB)
117 00:59:06.083747 progress 100 % (85 MB)
118 00:59:06.090139 85 MB downloaded in 5.01 s (17.02 MB/s)
119 00:59:06.090394 end: 1.4.1 http-download (duration 00:00:05) [common]
121 00:59:06.090663 end: 1.4 download-retry (duration 00:00:05) [common]
122 00:59:06.090756 start: 1.5 download-retry (timeout 00:09:55) [common]
123 00:59:06.090844 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 00:59:06.091005 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 00:59:06.091077 saving as /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/modules/modules.tar
126 00:59:06.091138 total size: 8625444 (8 MB)
127 00:59:06.091201 Using unxz to decompress xz
128 00:59:06.095513 progress 0 % (0 MB)
129 00:59:06.116489 progress 5 % (0 MB)
130 00:59:06.140037 progress 10 % (0 MB)
131 00:59:06.163492 progress 15 % (1 MB)
132 00:59:06.186710 progress 20 % (1 MB)
133 00:59:06.210529 progress 25 % (2 MB)
134 00:59:06.236235 progress 30 % (2 MB)
135 00:59:06.262262 progress 35 % (2 MB)
136 00:59:06.285347 progress 40 % (3 MB)
137 00:59:06.309253 progress 45 % (3 MB)
138 00:59:06.334415 progress 50 % (4 MB)
139 00:59:06.358833 progress 55 % (4 MB)
140 00:59:06.383966 progress 60 % (4 MB)
141 00:59:06.413167 progress 65 % (5 MB)
142 00:59:06.439713 progress 70 % (5 MB)
143 00:59:06.464789 progress 75 % (6 MB)
144 00:59:06.491971 progress 80 % (6 MB)
145 00:59:06.517472 progress 85 % (7 MB)
146 00:59:06.542241 progress 90 % (7 MB)
147 00:59:06.573482 progress 95 % (7 MB)
148 00:59:06.601082 progress 100 % (8 MB)
149 00:59:06.605950 8 MB downloaded in 0.51 s (15.98 MB/s)
150 00:59:06.606200 end: 1.5.1 http-download (duration 00:00:01) [common]
152 00:59:06.606468 end: 1.5 download-retry (duration 00:00:01) [common]
153 00:59:06.606564 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 00:59:06.606661 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 00:59:08.318206 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12571106/extract-nfsrootfs-3febsd3o
156 00:59:08.318402 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 00:59:08.318506 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 00:59:08.318667 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig
159 00:59:08.318798 makedir: /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin
160 00:59:08.318904 makedir: /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/tests
161 00:59:08.319004 makedir: /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/results
162 00:59:08.319103 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-add-keys
163 00:59:08.319246 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-add-sources
164 00:59:08.319377 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-background-process-start
165 00:59:08.319506 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-background-process-stop
166 00:59:08.319632 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-common-functions
167 00:59:08.319802 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-echo-ipv4
168 00:59:08.319928 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-install-packages
169 00:59:08.320054 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-installed-packages
170 00:59:08.320179 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-os-build
171 00:59:08.320305 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-probe-channel
172 00:59:08.320429 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-probe-ip
173 00:59:08.320553 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-target-ip
174 00:59:08.320676 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-target-mac
175 00:59:08.320801 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-target-storage
176 00:59:08.320931 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-case
177 00:59:08.321057 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-event
178 00:59:08.321181 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-feedback
179 00:59:08.321307 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-raise
180 00:59:08.321431 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-reference
181 00:59:08.321556 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-runner
182 00:59:08.321681 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-set
183 00:59:08.321806 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-test-shell
184 00:59:08.321932 Updating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-install-packages (oe)
185 00:59:08.322103 Updating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/bin/lava-installed-packages (oe)
186 00:59:08.322245 Creating /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/environment
187 00:59:08.322365 LAVA metadata
188 00:59:08.322444 - LAVA_JOB_ID=12571106
189 00:59:08.322523 - LAVA_DISPATCHER_IP=192.168.201.1
190 00:59:08.322648 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 00:59:08.322722 skipped lava-vland-overlay
192 00:59:08.322841 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 00:59:08.322964 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 00:59:08.323059 skipped lava-multinode-overlay
195 00:59:08.323177 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 00:59:08.323299 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 00:59:08.323410 Loading test definitions
198 00:59:08.323541 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 00:59:08.323648 Using /lava-12571106 at stage 0
200 00:59:08.324240 uuid=12571106_1.6.2.3.1 testdef=None
201 00:59:08.324339 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 00:59:08.324440 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 00:59:08.324943 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 00:59:08.325190 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 00:59:08.325811 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 00:59:08.326065 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 00:59:08.326910 runner path: /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/0/tests/0_lc-compliance test_uuid 12571106_1.6.2.3.1
210 00:59:08.327076 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 00:59:08.327398 Creating lava-test-runner.conf files
213 00:59:08.327498 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571106/lava-overlay-kw2obwig/lava-12571106/0 for stage 0
214 00:59:08.327633 - 0_lc-compliance
215 00:59:08.327801 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 00:59:08.327900 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 00:59:08.334584 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 00:59:08.334702 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 00:59:08.334829 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 00:59:08.334951 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 00:59:08.335035 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 00:59:08.454048 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 00:59:08.454436 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 00:59:08.454563 extracting modules file /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571106/extract-nfsrootfs-3febsd3o
225 00:59:08.682301 extracting modules file /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571106/extract-overlay-ramdisk-o566drg7/ramdisk
226 00:59:08.917928 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 00:59:08.918087 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 00:59:08.918183 [common] Applying overlay to NFS
229 00:59:08.918257 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571106/compress-overlay-_dx45iov/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571106/extract-nfsrootfs-3febsd3o
230 00:59:08.924771 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 00:59:08.924880 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 00:59:08.924966 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 00:59:08.925056 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 00:59:08.925128 Building ramdisk /var/lib/lava/dispatcher/tmp/12571106/extract-overlay-ramdisk-o566drg7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571106/extract-overlay-ramdisk-o566drg7/ramdisk
235 00:59:09.258667 >> 119414 blocks
236 00:59:11.217573 rename /var/lib/lava/dispatcher/tmp/12571106/extract-overlay-ramdisk-o566drg7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/ramdisk/ramdisk.cpio.gz
237 00:59:11.218022 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 00:59:11.218143 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 00:59:11.218247 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 00:59:11.218358 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/kernel/Image'
241 00:59:23.551464 Returned 0 in 12 seconds
242 00:59:23.652459 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/kernel/image.itb
243 00:59:24.139037 output: FIT description: Kernel Image image with one or more FDT blobs
244 00:59:24.139411 output: Created: Fri Jan 19 00:59:24 2024
245 00:59:24.139488 output: Image 0 (kernel-1)
246 00:59:24.139551 output: Description:
247 00:59:24.139611 output: Created: Fri Jan 19 00:59:24 2024
248 00:59:24.139678 output: Type: Kernel Image
249 00:59:24.139770 output: Compression: lzma compressed
250 00:59:24.139827 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
251 00:59:24.139884 output: Architecture: AArch64
252 00:59:24.139943 output: OS: Linux
253 00:59:24.139997 output: Load Address: 0x00000000
254 00:59:24.140054 output: Entry Point: 0x00000000
255 00:59:24.140111 output: Hash algo: crc32
256 00:59:24.140189 output: Hash value: a52aa383
257 00:59:24.140260 output: Image 1 (fdt-1)
258 00:59:24.140316 output: Description: mt8192-asurada-spherion-r0
259 00:59:24.140368 output: Created: Fri Jan 19 00:59:24 2024
260 00:59:24.140420 output: Type: Flat Device Tree
261 00:59:24.140471 output: Compression: uncompressed
262 00:59:24.140523 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 00:59:24.140574 output: Architecture: AArch64
264 00:59:24.140625 output: Hash algo: crc32
265 00:59:24.140677 output: Hash value: cc4352de
266 00:59:24.140728 output: Image 2 (ramdisk-1)
267 00:59:24.140779 output: Description: unavailable
268 00:59:24.140831 output: Created: Fri Jan 19 00:59:24 2024
269 00:59:24.140883 output: Type: RAMDisk Image
270 00:59:24.140934 output: Compression: Unknown Compression
271 00:59:24.140985 output: Data Size: 17804040 Bytes = 17386.76 KiB = 16.98 MiB
272 00:59:24.141037 output: Architecture: AArch64
273 00:59:24.141088 output: OS: Linux
274 00:59:24.141140 output: Load Address: unavailable
275 00:59:24.141191 output: Entry Point: unavailable
276 00:59:24.141242 output: Hash algo: crc32
277 00:59:24.141294 output: Hash value: f82bcd62
278 00:59:24.141345 output: Default Configuration: 'conf-1'
279 00:59:24.141397 output: Configuration 0 (conf-1)
280 00:59:24.141448 output: Description: mt8192-asurada-spherion-r0
281 00:59:24.141500 output: Kernel: kernel-1
282 00:59:24.141551 output: Init Ramdisk: ramdisk-1
283 00:59:24.141602 output: FDT: fdt-1
284 00:59:24.141669 output: Loadables: kernel-1
285 00:59:24.141722 output:
286 00:59:24.141937 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 00:59:24.142054 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 00:59:24.142199 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 00:59:24.142294 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 00:59:24.142402 No LXC device requested
291 00:59:24.142510 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 00:59:24.142622 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 00:59:24.142729 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 00:59:24.142796 Checking files for TFTP limit of 4294967296 bytes.
295 00:59:24.143292 end: 1 tftp-deploy (duration 00:00:23) [common]
296 00:59:24.143400 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 00:59:24.143493 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 00:59:24.143616 substitutions:
299 00:59:24.143712 - {DTB}: 12571106/tftp-deploy-jxn96ay5/dtb/mt8192-asurada-spherion-r0.dtb
300 00:59:24.143797 - {INITRD}: 12571106/tftp-deploy-jxn96ay5/ramdisk/ramdisk.cpio.gz
301 00:59:24.143858 - {KERNEL}: 12571106/tftp-deploy-jxn96ay5/kernel/Image
302 00:59:24.143916 - {LAVA_MAC}: None
303 00:59:24.143973 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12571106/extract-nfsrootfs-3febsd3o
304 00:59:24.144030 - {NFS_SERVER_IP}: 192.168.201.1
305 00:59:24.144084 - {PRESEED_CONFIG}: None
306 00:59:24.144138 - {PRESEED_LOCAL}: None
307 00:59:24.144192 - {RAMDISK}: 12571106/tftp-deploy-jxn96ay5/ramdisk/ramdisk.cpio.gz
308 00:59:24.144247 - {ROOT_PART}: None
309 00:59:24.144301 - {ROOT}: None
310 00:59:24.144354 - {SERVER_IP}: 192.168.201.1
311 00:59:24.144407 - {TEE}: None
312 00:59:24.144460 Parsed boot commands:
313 00:59:24.144514 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 00:59:24.144702 Parsed boot commands: tftpboot 192.168.201.1 12571106/tftp-deploy-jxn96ay5/kernel/image.itb 12571106/tftp-deploy-jxn96ay5/kernel/cmdline
315 00:59:24.144789 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 00:59:24.144875 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 00:59:24.144968 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 00:59:24.145055 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 00:59:24.145125 Not connected, no need to disconnect.
320 00:59:24.145199 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 00:59:24.145280 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 00:59:24.145349 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 00:59:24.149335 Setting prompt string to ['lava-test: # ']
324 00:59:24.149753 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 00:59:24.149861 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 00:59:24.149976 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 00:59:24.150096 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 00:59:24.150378 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
329 00:59:29.293566 >> Command sent successfully.
330 00:59:29.296016 Returned 0 in 5 seconds
331 00:59:29.396422 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 00:59:29.396760 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 00:59:29.396864 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 00:59:29.396952 Setting prompt string to 'Starting depthcharge on Spherion...'
336 00:59:29.397024 Changing prompt to 'Starting depthcharge on Spherion...'
337 00:59:29.397095 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 00:59:29.397368 [Enter `^Ec?' for help]
339 00:59:29.569511
340 00:59:29.570072
341 00:59:29.570437 F0: 102B 0000
342 00:59:29.570777
343 00:59:29.571080 F3: 1001 0000 [0200]
344 00:59:29.571384
345 00:59:29.573099 F3: 1001 0000
346 00:59:29.573672
347 00:59:29.574269 F7: 102D 0000
348 00:59:29.574821
349 00:59:29.575269 F1: 0000 0000
350 00:59:29.575590
351 00:59:29.577163 V0: 0000 0000 [0001]
352 00:59:29.577587
353 00:59:29.577922 00: 0007 8000
354 00:59:29.578262
355 00:59:29.580509 01: 0000 0000
356 00:59:29.580937
357 00:59:29.581283 BP: 0C00 0209 [0000]
358 00:59:29.581601
359 00:59:29.584644 G0: 1182 0000
360 00:59:29.585069
361 00:59:29.585403 EC: 0000 0021 [4000]
362 00:59:29.585721
363 00:59:29.588477 S7: 0000 0000 [0000]
364 00:59:29.588901
365 00:59:29.589236 CC: 0000 0000 [0001]
366 00:59:29.589548
367 00:59:29.591093 T0: 0000 0040 [010F]
368 00:59:29.591520
369 00:59:29.591911 Jump to BL
370 00:59:29.592241
371 00:59:29.615971
372 00:59:29.616487
373 00:59:29.616827
374 00:59:29.625972 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 00:59:29.629873 ARM64: Exception handlers installed.
376 00:59:29.630317 ARM64: Testing exception
377 00:59:29.633027 ARM64: Done test exception
378 00:59:29.640477 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 00:59:29.651627 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 00:59:29.658650 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 00:59:29.669408 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 00:59:29.676077 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 00:59:29.683009 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 00:59:29.692565 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 00:59:29.699186 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 00:59:29.718925 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 00:59:29.722654 WDT: Last reset was cold boot
388 00:59:29.725833 SPI1(PAD0) initialized at 2873684 Hz
389 00:59:29.729068 SPI5(PAD0) initialized at 992727 Hz
390 00:59:29.732025 VBOOT: Loading verstage.
391 00:59:29.738992 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 00:59:29.742666 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 00:59:29.745404 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 00:59:29.749211 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 00:59:29.757189 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 00:59:29.762984 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 00:59:29.773835 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 00:59:29.774321
399 00:59:29.774658
400 00:59:29.783812 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 00:59:29.786824 ARM64: Exception handlers installed.
402 00:59:29.790811 ARM64: Testing exception
403 00:59:29.791262 ARM64: Done test exception
404 00:59:29.797074 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 00:59:29.800815 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 00:59:29.815561 Probing TPM: . done!
407 00:59:29.816131 TPM ready after 0 ms
408 00:59:29.821954 Connected to device vid:did:rid of 1ae0:0028:00
409 00:59:29.831928 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 00:59:29.869997 Initialized TPM device CR50 revision 0
411 00:59:29.882251 tlcl_send_startup: Startup return code is 0
412 00:59:29.882727 TPM: setup succeeded
413 00:59:29.893301 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 00:59:29.901700 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 00:59:29.908694 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 00:59:29.920966 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 00:59:29.924276 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 00:59:29.927528 in-header: 03 07 00 00 08 00 00 00
419 00:59:29.931274 in-data: aa e4 47 04 13 02 00 00
420 00:59:29.934821 Chrome EC: UHEPI supported
421 00:59:29.940507 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 00:59:29.944394 in-header: 03 ad 00 00 08 00 00 00
423 00:59:29.947854 in-data: 00 20 20 08 00 00 00 00
424 00:59:29.948290 Phase 1
425 00:59:29.950747 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 00:59:29.957372 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 00:59:29.963933 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 00:59:29.967455 Recovery requested (1009000e)
429 00:59:29.971180 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 00:59:29.979799 tlcl_extend: response is 0
431 00:59:29.988173 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 00:59:29.992961 tlcl_extend: response is 0
433 00:59:29.999560 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 00:59:30.020636 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 00:59:30.027823 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 00:59:30.028388
437 00:59:30.028767
438 00:59:30.037863 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 00:59:30.041344 ARM64: Exception handlers installed.
440 00:59:30.041773 ARM64: Testing exception
441 00:59:30.044331 ARM64: Done test exception
442 00:59:30.066513 pmic_efuse_setting: Set efuses in 11 msecs
443 00:59:30.069251 pmwrap_interface_init: Select PMIF_VLD_RDY
444 00:59:30.076575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 00:59:30.080371 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 00:59:30.083473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 00:59:30.089646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 00:59:30.092990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 00:59:30.099801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 00:59:30.103155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 00:59:30.110096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 00:59:30.113423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 00:59:30.116652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 00:59:30.123188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 00:59:30.127000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 00:59:30.133101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 00:59:30.136856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 00:59:30.143234 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 00:59:30.150240 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 00:59:30.156236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 00:59:30.159457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 00:59:30.166782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 00:59:30.172994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 00:59:30.176723 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 00:59:30.183280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 00:59:30.190752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 00:59:30.194533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 00:59:30.197767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 00:59:30.204220 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 00:59:30.211887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 00:59:30.215039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 00:59:30.218038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 00:59:30.225505 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 00:59:30.229441 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 00:59:30.235836 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 00:59:30.239034 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 00:59:30.245649 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 00:59:30.249167 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 00:59:30.255631 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 00:59:30.259408 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 00:59:30.265442 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 00:59:30.268452 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 00:59:30.272067 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 00:59:30.279619 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 00:59:30.282927 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 00:59:30.286572 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 00:59:30.293040 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 00:59:30.295981 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 00:59:30.299392 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 00:59:30.302640 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 00:59:30.309644 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 00:59:30.312411 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 00:59:30.315629 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 00:59:30.319482 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 00:59:30.329664 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 00:59:30.335853 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 00:59:30.342681 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 00:59:30.349153 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 00:59:30.358749 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 00:59:30.362334 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 00:59:30.368764 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 00:59:30.372484 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 00:59:30.378884 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x14
504 00:59:30.385556 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 00:59:30.388918 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 00:59:30.391849 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 00:59:30.403412 [RTC]rtc_get_frequency_meter,154: input=15, output=835
508 00:59:30.413041 [RTC]rtc_get_frequency_meter,154: input=7, output=709
509 00:59:30.421738 [RTC]rtc_get_frequency_meter,154: input=11, output=772
510 00:59:30.431315 [RTC]rtc_get_frequency_meter,154: input=13, output=803
511 00:59:30.441161 [RTC]rtc_get_frequency_meter,154: input=12, output=788
512 00:59:30.450648 [RTC]rtc_get_frequency_meter,154: input=12, output=788
513 00:59:30.459949 [RTC]rtc_get_frequency_meter,154: input=13, output=804
514 00:59:30.463654 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 00:59:30.470560 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 00:59:30.473625 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 00:59:30.477086 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 00:59:30.483916 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 00:59:30.487231 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 00:59:30.490582 ADC[4]: Raw value=904509 ID=7
521 00:59:30.491020 ADC[3]: Raw value=213282 ID=1
522 00:59:30.493580 RAM Code: 0x71
523 00:59:30.497073 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 00:59:30.504044 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 00:59:30.510307 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 00:59:30.517515 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 00:59:30.519895 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 00:59:30.524045 in-header: 03 07 00 00 08 00 00 00
529 00:59:30.527052 in-data: aa e4 47 04 13 02 00 00
530 00:59:30.530328 Chrome EC: UHEPI supported
531 00:59:30.537217 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 00:59:30.540533 in-header: 03 dd 00 00 08 00 00 00
533 00:59:30.543767 in-data: 90 20 60 08 00 00 00 00
534 00:59:30.547238 MRC: failed to locate region type 0.
535 00:59:30.553926 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 00:59:30.556907 DRAM-K: Running full calibration
537 00:59:30.563655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 00:59:30.564135 header.status = 0x0
539 00:59:30.567755 header.version = 0x6 (expected: 0x6)
540 00:59:30.570600 header.size = 0xd00 (expected: 0xd00)
541 00:59:30.573871 header.flags = 0x0
542 00:59:30.580454 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 00:59:30.597353 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
544 00:59:30.604044 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 00:59:30.607592 dram_init: ddr_geometry: 2
546 00:59:30.610609 [EMI] MDL number = 2
547 00:59:30.611032 [EMI] Get MDL freq = 0
548 00:59:30.614407 dram_init: ddr_type: 0
549 00:59:30.614836 is_discrete_lpddr4: 1
550 00:59:30.617257 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 00:59:30.617682
552 00:59:30.618017
553 00:59:30.621418 [Bian_co] ETT version 0.0.0.1
554 00:59:30.627208 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 00:59:30.627636
556 00:59:30.630084 dramc_set_vcore_voltage set vcore to 650000
557 00:59:30.633596 Read voltage for 800, 4
558 00:59:30.634023 Vio18 = 0
559 00:59:30.634368 Vcore = 650000
560 00:59:30.637192 Vdram = 0
561 00:59:30.637778 Vddq = 0
562 00:59:30.638135 Vmddr = 0
563 00:59:30.640683 dram_init: config_dvfs: 1
564 00:59:30.643576 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 00:59:30.649921 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 00:59:30.653721 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 00:59:30.656890 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 00:59:30.660231 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 00:59:30.666615 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 00:59:30.667042 MEM_TYPE=3, freq_sel=18
571 00:59:30.670247 sv_algorithm_assistance_LP4_1600
572 00:59:30.673151 ============ PULL DRAM RESETB DOWN ============
573 00:59:30.680038 ========== PULL DRAM RESETB DOWN end =========
574 00:59:30.683656 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 00:59:30.686516 ===================================
576 00:59:30.689723 LPDDR4 DRAM CONFIGURATION
577 00:59:30.693413 ===================================
578 00:59:30.693838 EX_ROW_EN[0] = 0x0
579 00:59:30.697133 EX_ROW_EN[1] = 0x0
580 00:59:30.697558 LP4Y_EN = 0x0
581 00:59:30.700060 WORK_FSP = 0x0
582 00:59:30.702769 WL = 0x2
583 00:59:30.703192 RL = 0x2
584 00:59:30.706117 BL = 0x2
585 00:59:30.706542 RPST = 0x0
586 00:59:30.710013 RD_PRE = 0x0
587 00:59:30.710440 WR_PRE = 0x1
588 00:59:30.713103 WR_PST = 0x0
589 00:59:30.713528 DBI_WR = 0x0
590 00:59:30.716693 DBI_RD = 0x0
591 00:59:30.717119 OTF = 0x1
592 00:59:30.719553 ===================================
593 00:59:30.723277 ===================================
594 00:59:30.726274 ANA top config
595 00:59:30.730064 ===================================
596 00:59:30.730509 DLL_ASYNC_EN = 0
597 00:59:30.732734 ALL_SLAVE_EN = 1
598 00:59:30.736628 NEW_RANK_MODE = 1
599 00:59:30.739434 DLL_IDLE_MODE = 1
600 00:59:30.739908 LP45_APHY_COMB_EN = 1
601 00:59:30.742974 TX_ODT_DIS = 1
602 00:59:30.745929 NEW_8X_MODE = 1
603 00:59:30.750016 ===================================
604 00:59:30.752820 ===================================
605 00:59:30.757089 data_rate = 1600
606 00:59:30.759409 CKR = 1
607 00:59:30.763100 DQ_P2S_RATIO = 8
608 00:59:30.765769 ===================================
609 00:59:30.766222 CA_P2S_RATIO = 8
610 00:59:30.769540 DQ_CA_OPEN = 0
611 00:59:30.772381 DQ_SEMI_OPEN = 0
612 00:59:30.775806 CA_SEMI_OPEN = 0
613 00:59:30.779299 CA_FULL_RATE = 0
614 00:59:30.782822 DQ_CKDIV4_EN = 1
615 00:59:30.783246 CA_CKDIV4_EN = 1
616 00:59:30.785957 CA_PREDIV_EN = 0
617 00:59:30.789200 PH8_DLY = 0
618 00:59:30.792326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 00:59:30.796685 DQ_AAMCK_DIV = 4
620 00:59:30.799286 CA_AAMCK_DIV = 4
621 00:59:30.799735 CA_ADMCK_DIV = 4
622 00:59:30.802845 DQ_TRACK_CA_EN = 0
623 00:59:30.806451 CA_PICK = 800
624 00:59:30.808844 CA_MCKIO = 800
625 00:59:30.812101 MCKIO_SEMI = 0
626 00:59:30.815499 PLL_FREQ = 3068
627 00:59:30.819080 DQ_UI_PI_RATIO = 32
628 00:59:30.819512 CA_UI_PI_RATIO = 0
629 00:59:30.821828 ===================================
630 00:59:30.825723 ===================================
631 00:59:30.828620 memory_type:LPDDR4
632 00:59:30.832540 GP_NUM : 10
633 00:59:30.832969 SRAM_EN : 1
634 00:59:30.835077 MD32_EN : 0
635 00:59:30.838988 ===================================
636 00:59:30.841924 [ANA_INIT] >>>>>>>>>>>>>>
637 00:59:30.845712 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 00:59:30.848753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 00:59:30.851741 ===================================
640 00:59:30.855052 data_rate = 1600,PCW = 0X7600
641 00:59:30.858932 ===================================
642 00:59:30.861913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 00:59:30.865101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 00:59:30.871793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 00:59:30.874878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 00:59:30.877961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 00:59:30.881681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 00:59:30.884960 [ANA_INIT] flow start
649 00:59:30.888205 [ANA_INIT] PLL >>>>>>>>
650 00:59:30.888633 [ANA_INIT] PLL <<<<<<<<
651 00:59:30.891412 [ANA_INIT] MIDPI >>>>>>>>
652 00:59:30.894922 [ANA_INIT] MIDPI <<<<<<<<
653 00:59:30.898208 [ANA_INIT] DLL >>>>>>>>
654 00:59:30.898636 [ANA_INIT] flow end
655 00:59:30.900969 ============ LP4 DIFF to SE enter ============
656 00:59:30.908067 ============ LP4 DIFF to SE exit ============
657 00:59:30.908495 [ANA_INIT] <<<<<<<<<<<<<
658 00:59:30.911284 [Flow] Enable top DCM control >>>>>
659 00:59:30.915564 [Flow] Enable top DCM control <<<<<
660 00:59:30.918173 Enable DLL master slave shuffle
661 00:59:30.925421 ==============================================================
662 00:59:30.925951 Gating Mode config
663 00:59:30.931871 ==============================================================
664 00:59:30.934618 Config description:
665 00:59:30.944118 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 00:59:30.952352 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 00:59:30.954179 SELPH_MODE 0: By rank 1: By Phase
668 00:59:30.961051 ==============================================================
669 00:59:30.964400 GAT_TRACK_EN = 1
670 00:59:30.964827 RX_GATING_MODE = 2
671 00:59:30.967476 RX_GATING_TRACK_MODE = 2
672 00:59:30.971077 SELPH_MODE = 1
673 00:59:30.974327 PICG_EARLY_EN = 1
674 00:59:30.977352 VALID_LAT_VALUE = 1
675 00:59:30.984561 ==============================================================
676 00:59:30.987493 Enter into Gating configuration >>>>
677 00:59:30.990438 Exit from Gating configuration <<<<
678 00:59:30.994473 Enter into DVFS_PRE_config >>>>>
679 00:59:31.004638 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 00:59:31.007319 Exit from DVFS_PRE_config <<<<<
681 00:59:31.010496 Enter into PICG configuration >>>>
682 00:59:31.014226 Exit from PICG configuration <<<<
683 00:59:31.017325 [RX_INPUT] configuration >>>>>
684 00:59:31.021056 [RX_INPUT] configuration <<<<<
685 00:59:31.024219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 00:59:31.031546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 00:59:31.034180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 00:59:31.041564 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 00:59:31.049582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 00:59:31.056579 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 00:59:31.059819 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 00:59:31.063344 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 00:59:31.066927 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 00:59:31.069973 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 00:59:31.074350 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 00:59:31.077414 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 00:59:31.081373 ===================================
698 00:59:31.084779 LPDDR4 DRAM CONFIGURATION
699 00:59:31.089136 ===================================
700 00:59:31.091783 EX_ROW_EN[0] = 0x0
701 00:59:31.092230 EX_ROW_EN[1] = 0x0
702 00:59:31.095915 LP4Y_EN = 0x0
703 00:59:31.096369 WORK_FSP = 0x0
704 00:59:31.099592 WL = 0x2
705 00:59:31.100091 RL = 0x2
706 00:59:31.100429 BL = 0x2
707 00:59:31.102689 RPST = 0x0
708 00:59:31.103145 RD_PRE = 0x0
709 00:59:31.106546 WR_PRE = 0x1
710 00:59:31.107036 WR_PST = 0x0
711 00:59:31.110973 DBI_WR = 0x0
712 00:59:31.111724 DBI_RD = 0x0
713 00:59:31.114417 OTF = 0x1
714 00:59:31.117872 ===================================
715 00:59:31.121443 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 00:59:31.125162 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 00:59:31.128677 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 00:59:31.131889 ===================================
719 00:59:31.135729 LPDDR4 DRAM CONFIGURATION
720 00:59:31.139952 ===================================
721 00:59:31.140393 EX_ROW_EN[0] = 0x10
722 00:59:31.142899 EX_ROW_EN[1] = 0x0
723 00:59:31.143351 LP4Y_EN = 0x0
724 00:59:31.146516 WORK_FSP = 0x0
725 00:59:31.147195 WL = 0x2
726 00:59:31.150552 RL = 0x2
727 00:59:31.151111 BL = 0x2
728 00:59:31.151595 RPST = 0x0
729 00:59:31.154283 RD_PRE = 0x0
730 00:59:31.154836 WR_PRE = 0x1
731 00:59:31.158174 WR_PST = 0x0
732 00:59:31.158854 DBI_WR = 0x0
733 00:59:31.161494 DBI_RD = 0x0
734 00:59:31.162207 OTF = 0x1
735 00:59:31.165335 ===================================
736 00:59:31.172015 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 00:59:31.176027 nWR fixed to 40
738 00:59:31.180210 [ModeRegInit_LP4] CH0 RK0
739 00:59:31.180636 [ModeRegInit_LP4] CH0 RK1
740 00:59:31.183548 [ModeRegInit_LP4] CH1 RK0
741 00:59:31.184026 [ModeRegInit_LP4] CH1 RK1
742 00:59:31.187369 match AC timing 13
743 00:59:31.191159 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 00:59:31.194281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 00:59:31.200389 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 00:59:31.204028 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 00:59:31.207832 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 00:59:31.210744 [EMI DOE] emi_dcm 0
749 00:59:31.214415 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 00:59:31.214849 ==
751 00:59:31.217453 Dram Type= 6, Freq= 0, CH_0, rank 0
752 00:59:31.224167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 00:59:31.224602 ==
754 00:59:31.228033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 00:59:31.234330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 00:59:31.243030 [CA 0] Center 37 (6~68) winsize 63
757 00:59:31.246350 [CA 1] Center 37 (6~68) winsize 63
758 00:59:31.249926 [CA 2] Center 34 (4~65) winsize 62
759 00:59:31.253810 [CA 3] Center 34 (4~65) winsize 62
760 00:59:31.257342 [CA 4] Center 33 (3~64) winsize 62
761 00:59:31.260114 [CA 5] Center 33 (3~64) winsize 62
762 00:59:31.260644
763 00:59:31.263116 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 00:59:31.263540
765 00:59:31.266465 [CATrainingPosCal] consider 1 rank data
766 00:59:31.270035 u2DelayCellTimex100 = 270/100 ps
767 00:59:31.273185 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
768 00:59:31.276593 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 00:59:31.283498 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 00:59:31.286301 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 00:59:31.289681 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 00:59:31.293556 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 00:59:31.293984
774 00:59:31.296624 CA PerBit enable=1, Macro0, CA PI delay=33
775 00:59:31.297125
776 00:59:31.299607 [CBTSetCACLKResult] CA Dly = 33
777 00:59:31.300140 CS Dly: 6 (0~37)
778 00:59:31.300490 ==
779 00:59:31.303082 Dram Type= 6, Freq= 0, CH_0, rank 1
780 00:59:31.310038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 00:59:31.310468 ==
782 00:59:31.312786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 00:59:31.319387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 00:59:31.329051 [CA 0] Center 37 (6~68) winsize 63
785 00:59:31.332650 [CA 1] Center 37 (7~68) winsize 62
786 00:59:31.336616 [CA 2] Center 34 (4~65) winsize 62
787 00:59:31.339437 [CA 3] Center 34 (4~65) winsize 62
788 00:59:31.342651 [CA 4] Center 33 (3~64) winsize 62
789 00:59:31.345830 [CA 5] Center 33 (2~64) winsize 63
790 00:59:31.346267
791 00:59:31.349086 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 00:59:31.349616
793 00:59:31.352436 [CATrainingPosCal] consider 2 rank data
794 00:59:31.356154 u2DelayCellTimex100 = 270/100 ps
795 00:59:31.359465 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
796 00:59:31.362570 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 00:59:31.369347 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 00:59:31.372611 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 00:59:31.375656 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 00:59:31.379366 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 00:59:31.379843
802 00:59:31.383240 CA PerBit enable=1, Macro0, CA PI delay=33
803 00:59:31.383663
804 00:59:31.386880 [CBTSetCACLKResult] CA Dly = 33
805 00:59:31.387305 CS Dly: 6 (0~38)
806 00:59:31.387646
807 00:59:31.390252 ----->DramcWriteLeveling(PI) begin...
808 00:59:31.390700 ==
809 00:59:31.393656 Dram Type= 6, Freq= 0, CH_0, rank 0
810 00:59:31.397048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 00:59:31.397550 ==
812 00:59:31.400710 Write leveling (Byte 0): 35 => 35
813 00:59:31.404251 Write leveling (Byte 1): 28 => 28
814 00:59:31.407925 DramcWriteLeveling(PI) end<-----
815 00:59:31.408352
816 00:59:31.408689 ==
817 00:59:31.411496 Dram Type= 6, Freq= 0, CH_0, rank 0
818 00:59:31.414196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 00:59:31.417834 ==
820 00:59:31.418262 [Gating] SW mode calibration
821 00:59:31.424664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 00:59:31.430704 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 00:59:31.434212 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 00:59:31.440594 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 00:59:31.443743 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 00:59:31.447518 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
827 00:59:31.453804 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 00:59:31.456883 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:59:31.460124 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:59:31.467874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:59:31.470158 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:59:31.473460 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:59:31.480007 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 00:59:31.483864 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 00:59:31.487043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 00:59:31.493493 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 00:59:31.497221 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 00:59:31.500176 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 00:59:31.506734 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 00:59:31.510527 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 00:59:31.513480 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
842 00:59:31.520013 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 00:59:31.523765 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 00:59:31.526158 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 00:59:31.532741 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 00:59:31.536231 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 00:59:31.539738 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 00:59:31.546245 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 00:59:31.549856 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
850 00:59:31.552465 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
851 00:59:31.559143 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 00:59:31.562273 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 00:59:31.565999 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 00:59:31.572098 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 00:59:31.575371 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 00:59:31.579645 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
857 00:59:31.585634 0 10 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
858 00:59:31.588833 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
859 00:59:31.592244 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 00:59:31.598692 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 00:59:31.601989 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 00:59:31.605379 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 00:59:31.611961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 00:59:31.615748 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
865 00:59:31.618458 0 11 8 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
866 00:59:31.624843 0 11 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
867 00:59:31.628339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 00:59:31.632049 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 00:59:31.638558 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 00:59:31.641235 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 00:59:31.644858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 00:59:31.651407 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 00:59:31.654606 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 00:59:31.658285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 00:59:31.665194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 00:59:31.668996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 00:59:31.672170 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 00:59:31.675954 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 00:59:31.682146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 00:59:31.685396 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 00:59:31.688318 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 00:59:31.695469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 00:59:31.698186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 00:59:31.701524 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 00:59:31.708297 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 00:59:31.711394 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 00:59:31.714932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 00:59:31.721551 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 00:59:31.724560 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 00:59:31.728365 Total UI for P1: 0, mck2ui 16
891 00:59:31.730986 best dqsien dly found for B0: ( 0, 14, 6)
892 00:59:31.734529 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
893 00:59:31.741049 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 00:59:31.744090 Total UI for P1: 0, mck2ui 16
895 00:59:31.747581 best dqsien dly found for B1: ( 0, 14, 10)
896 00:59:31.751292 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
897 00:59:31.753666 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
898 00:59:31.753750
899 00:59:31.757517 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
900 00:59:31.760836 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
901 00:59:31.764497 [Gating] SW calibration Done
902 00:59:31.764593 ==
903 00:59:31.768239 Dram Type= 6, Freq= 0, CH_0, rank 0
904 00:59:31.771353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 00:59:31.771457 ==
906 00:59:31.774668 RX Vref Scan: 0
907 00:59:31.774783
908 00:59:31.774873 RX Vref 0 -> 0, step: 1
909 00:59:31.774959
910 00:59:31.778433 RX Delay -130 -> 252, step: 16
911 00:59:31.781252 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
912 00:59:31.788009 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
913 00:59:31.791370 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
914 00:59:31.794483 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
915 00:59:31.797850 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
916 00:59:31.801148 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
917 00:59:31.808529 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
918 00:59:31.811481 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
919 00:59:31.814950 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
920 00:59:31.818362 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
921 00:59:31.821839 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
922 00:59:31.828209 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
923 00:59:31.832952 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
924 00:59:31.835185 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
925 00:59:31.838114 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
926 00:59:31.842059 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
927 00:59:31.845067 ==
928 00:59:31.845500 Dram Type= 6, Freq= 0, CH_0, rank 0
929 00:59:31.852102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 00:59:31.852536 ==
931 00:59:31.852881 DQS Delay:
932 00:59:31.854766 DQS0 = 0, DQS1 = 0
933 00:59:31.855196 DQM Delay:
934 00:59:31.858190 DQM0 = 84, DQM1 = 71
935 00:59:31.858713 DQ Delay:
936 00:59:31.863055 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
937 00:59:31.864969 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
938 00:59:31.867981 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
939 00:59:31.871221 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
940 00:59:31.871647
941 00:59:31.872028
942 00:59:31.872347 ==
943 00:59:31.874857 Dram Type= 6, Freq= 0, CH_0, rank 0
944 00:59:31.878536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 00:59:31.878971 ==
946 00:59:31.879309
947 00:59:31.879622
948 00:59:31.882276 TX Vref Scan disable
949 00:59:31.882811 == TX Byte 0 ==
950 00:59:31.886225 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
951 00:59:31.893740 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
952 00:59:31.894169 == TX Byte 1 ==
953 00:59:31.897897 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
954 00:59:31.901096 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
955 00:59:31.901522 ==
956 00:59:31.905066 Dram Type= 6, Freq= 0, CH_0, rank 0
957 00:59:31.908345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 00:59:31.908770 ==
959 00:59:31.923926 TX Vref=22, minBit 3, minWin=27, winSum=440
960 00:59:31.927873 TX Vref=24, minBit 8, minWin=27, winSum=443
961 00:59:31.932162 TX Vref=26, minBit 8, minWin=27, winSum=442
962 00:59:31.935103 TX Vref=28, minBit 3, minWin=27, winSum=446
963 00:59:31.938549 TX Vref=30, minBit 9, minWin=27, winSum=447
964 00:59:31.941898 TX Vref=32, minBit 0, minWin=27, winSum=440
965 00:59:31.948265 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 30
966 00:59:31.948697
967 00:59:31.951218 Final TX Range 1 Vref 30
968 00:59:31.951838
969 00:59:31.952325 ==
970 00:59:31.954914 Dram Type= 6, Freq= 0, CH_0, rank 0
971 00:59:31.958404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 00:59:31.958926 ==
973 00:59:31.959448
974 00:59:31.959956
975 00:59:31.961146 TX Vref Scan disable
976 00:59:31.964719 == TX Byte 0 ==
977 00:59:31.968045 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
978 00:59:31.971209 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
979 00:59:31.974378 == TX Byte 1 ==
980 00:59:31.977972 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
981 00:59:31.980890 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
982 00:59:31.981334
983 00:59:31.981673 [DATLAT]
984 00:59:31.984850 Freq=800, CH0 RK0
985 00:59:31.985273
986 00:59:31.985607 DATLAT Default: 0xa
987 00:59:31.988346 0, 0xFFFF, sum = 0
988 00:59:31.988780 1, 0xFFFF, sum = 0
989 00:59:31.991936 2, 0xFFFF, sum = 0
990 00:59:31.992368 3, 0xFFFF, sum = 0
991 00:59:31.995208 4, 0xFFFF, sum = 0
992 00:59:31.995643 5, 0xFFFF, sum = 0
993 00:59:31.998379 6, 0xFFFF, sum = 0
994 00:59:31.998829 7, 0xFFFF, sum = 0
995 00:59:32.002807 8, 0xFFFF, sum = 0
996 00:59:32.003401 9, 0x0, sum = 1
997 00:59:32.006352 10, 0x0, sum = 2
998 00:59:32.006787 11, 0x0, sum = 3
999 00:59:32.007129 12, 0x0, sum = 4
1000 00:59:32.009698 best_step = 10
1001 00:59:32.010124
1002 00:59:32.010464 ==
1003 00:59:32.013722 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 00:59:32.016827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 00:59:32.017259 ==
1006 00:59:32.019498 RX Vref Scan: 1
1007 00:59:32.019968
1008 00:59:32.020310 Set Vref Range= 32 -> 127
1009 00:59:32.023036
1010 00:59:32.023491 RX Vref 32 -> 127, step: 1
1011 00:59:32.023949
1012 00:59:32.027518 RX Delay -111 -> 252, step: 8
1013 00:59:32.028021
1014 00:59:32.029478 Set Vref, RX VrefLevel [Byte0]: 32
1015 00:59:32.033113 [Byte1]: 32
1016 00:59:32.033554
1017 00:59:32.036328 Set Vref, RX VrefLevel [Byte0]: 33
1018 00:59:32.039523 [Byte1]: 33
1019 00:59:32.043779
1020 00:59:32.044205 Set Vref, RX VrefLevel [Byte0]: 34
1021 00:59:32.046955 [Byte1]: 34
1022 00:59:32.051741
1023 00:59:32.052168 Set Vref, RX VrefLevel [Byte0]: 35
1024 00:59:32.054955 [Byte1]: 35
1025 00:59:32.058920
1026 00:59:32.059335 Set Vref, RX VrefLevel [Byte0]: 36
1027 00:59:32.062412 [Byte1]: 36
1028 00:59:32.066527
1029 00:59:32.067010 Set Vref, RX VrefLevel [Byte0]: 37
1030 00:59:32.069914 [Byte1]: 37
1031 00:59:32.074124
1032 00:59:32.074639 Set Vref, RX VrefLevel [Byte0]: 38
1033 00:59:32.077801 [Byte1]: 38
1034 00:59:32.082294
1035 00:59:32.082811 Set Vref, RX VrefLevel [Byte0]: 39
1036 00:59:32.085721 [Byte1]: 39
1037 00:59:32.089618
1038 00:59:32.090182 Set Vref, RX VrefLevel [Byte0]: 40
1039 00:59:32.092757 [Byte1]: 40
1040 00:59:32.096876
1041 00:59:32.097290 Set Vref, RX VrefLevel [Byte0]: 41
1042 00:59:32.100819 [Byte1]: 41
1043 00:59:32.105313
1044 00:59:32.105729 Set Vref, RX VrefLevel [Byte0]: 42
1045 00:59:32.108281 [Byte1]: 42
1046 00:59:32.112309
1047 00:59:32.112724 Set Vref, RX VrefLevel [Byte0]: 43
1048 00:59:32.116187 [Byte1]: 43
1049 00:59:32.120085
1050 00:59:32.120508 Set Vref, RX VrefLevel [Byte0]: 44
1051 00:59:32.127024 [Byte1]: 44
1052 00:59:32.127443
1053 00:59:32.130063 Set Vref, RX VrefLevel [Byte0]: 45
1054 00:59:32.133492 [Byte1]: 45
1055 00:59:32.133914
1056 00:59:32.136350 Set Vref, RX VrefLevel [Byte0]: 46
1057 00:59:32.139714 [Byte1]: 46
1058 00:59:32.143593
1059 00:59:32.144065 Set Vref, RX VrefLevel [Byte0]: 47
1060 00:59:32.146810 [Byte1]: 47
1061 00:59:32.151040
1062 00:59:32.151459 Set Vref, RX VrefLevel [Byte0]: 48
1063 00:59:32.154656 [Byte1]: 48
1064 00:59:32.158854
1065 00:59:32.159371 Set Vref, RX VrefLevel [Byte0]: 49
1066 00:59:32.161818 [Byte1]: 49
1067 00:59:32.165774
1068 00:59:32.166194 Set Vref, RX VrefLevel [Byte0]: 50
1069 00:59:32.169812 [Byte1]: 50
1070 00:59:32.174129
1071 00:59:32.174544 Set Vref, RX VrefLevel [Byte0]: 51
1072 00:59:32.177287 [Byte1]: 51
1073 00:59:32.181327
1074 00:59:32.181747 Set Vref, RX VrefLevel [Byte0]: 52
1075 00:59:32.185044 [Byte1]: 52
1076 00:59:32.189356
1077 00:59:32.189771 Set Vref, RX VrefLevel [Byte0]: 53
1078 00:59:32.192511 [Byte1]: 53
1079 00:59:32.196741
1080 00:59:32.197158 Set Vref, RX VrefLevel [Byte0]: 54
1081 00:59:32.200289 [Byte1]: 54
1082 00:59:32.204697
1083 00:59:32.205211 Set Vref, RX VrefLevel [Byte0]: 55
1084 00:59:32.207558 [Byte1]: 55
1085 00:59:32.212103
1086 00:59:32.212611 Set Vref, RX VrefLevel [Byte0]: 56
1087 00:59:32.215402 [Byte1]: 56
1088 00:59:32.219471
1089 00:59:32.220083 Set Vref, RX VrefLevel [Byte0]: 57
1090 00:59:32.226309 [Byte1]: 57
1091 00:59:32.226821
1092 00:59:32.229483 Set Vref, RX VrefLevel [Byte0]: 58
1093 00:59:32.233480 [Byte1]: 58
1094 00:59:32.233907
1095 00:59:32.235977 Set Vref, RX VrefLevel [Byte0]: 59
1096 00:59:32.239737 [Byte1]: 59
1097 00:59:32.240161
1098 00:59:32.242541 Set Vref, RX VrefLevel [Byte0]: 60
1099 00:59:32.245920 [Byte1]: 60
1100 00:59:32.250168
1101 00:59:32.250742 Set Vref, RX VrefLevel [Byte0]: 61
1102 00:59:32.253625 [Byte1]: 61
1103 00:59:32.258320
1104 00:59:32.259030 Set Vref, RX VrefLevel [Byte0]: 62
1105 00:59:32.261285 [Byte1]: 62
1106 00:59:32.265403
1107 00:59:32.265961 Set Vref, RX VrefLevel [Byte0]: 63
1108 00:59:32.269063 [Byte1]: 63
1109 00:59:32.273433
1110 00:59:32.273894 Set Vref, RX VrefLevel [Byte0]: 64
1111 00:59:32.276475 [Byte1]: 64
1112 00:59:32.280863
1113 00:59:32.281325 Set Vref, RX VrefLevel [Byte0]: 65
1114 00:59:32.284095 [Byte1]: 65
1115 00:59:32.288042
1116 00:59:32.288121 Set Vref, RX VrefLevel [Byte0]: 66
1117 00:59:32.291533 [Byte1]: 66
1118 00:59:32.295841
1119 00:59:32.295997 Set Vref, RX VrefLevel [Byte0]: 67
1120 00:59:32.299816 [Byte1]: 67
1121 00:59:32.303408
1122 00:59:32.303501 Set Vref, RX VrefLevel [Byte0]: 68
1123 00:59:32.306753 [Byte1]: 68
1124 00:59:32.310900
1125 00:59:32.310981 Set Vref, RX VrefLevel [Byte0]: 69
1126 00:59:32.314275 [Byte1]: 69
1127 00:59:32.319137
1128 00:59:32.319219 Set Vref, RX VrefLevel [Byte0]: 70
1129 00:59:32.325007 [Byte1]: 70
1130 00:59:32.325090
1131 00:59:32.328235 Set Vref, RX VrefLevel [Byte0]: 71
1132 00:59:32.331822 [Byte1]: 71
1133 00:59:32.331906
1134 00:59:32.334963 Set Vref, RX VrefLevel [Byte0]: 72
1135 00:59:32.338333 [Byte1]: 72
1136 00:59:32.338414
1137 00:59:32.342028 Set Vref, RX VrefLevel [Byte0]: 73
1138 00:59:32.345103 [Byte1]: 73
1139 00:59:32.349425
1140 00:59:32.349507 Set Vref, RX VrefLevel [Byte0]: 74
1141 00:59:32.352463 [Byte1]: 74
1142 00:59:32.356809
1143 00:59:32.356890 Set Vref, RX VrefLevel [Byte0]: 75
1144 00:59:32.359836 [Byte1]: 75
1145 00:59:32.364544
1146 00:59:32.364625 Set Vref, RX VrefLevel [Byte0]: 76
1147 00:59:32.368234 [Byte1]: 76
1148 00:59:32.372390
1149 00:59:32.372472 Set Vref, RX VrefLevel [Byte0]: 77
1150 00:59:32.375383 [Byte1]: 77
1151 00:59:32.379950
1152 00:59:32.380031 Set Vref, RX VrefLevel [Byte0]: 78
1153 00:59:32.383279 [Byte1]: 78
1154 00:59:32.387051
1155 00:59:32.390540 Set Vref, RX VrefLevel [Byte0]: 79
1156 00:59:32.394154 [Byte1]: 79
1157 00:59:32.394256
1158 00:59:32.396948 Set Vref, RX VrefLevel [Byte0]: 80
1159 00:59:32.400740 [Byte1]: 80
1160 00:59:32.400851
1161 00:59:32.403645 Set Vref, RX VrefLevel [Byte0]: 81
1162 00:59:32.407412 [Byte1]: 81
1163 00:59:32.410237
1164 00:59:32.410414 Set Vref, RX VrefLevel [Byte0]: 82
1165 00:59:32.413351 [Byte1]: 82
1166 00:59:32.417623
1167 00:59:32.417705 Set Vref, RX VrefLevel [Byte0]: 83
1168 00:59:32.421661 [Byte1]: 83
1169 00:59:32.425798
1170 00:59:32.425879 Set Vref, RX VrefLevel [Byte0]: 84
1171 00:59:32.429465 [Byte1]: 84
1172 00:59:32.433326
1173 00:59:32.433408 Final RX Vref Byte 0 = 60 to rank0
1174 00:59:32.436833 Final RX Vref Byte 1 = 59 to rank0
1175 00:59:32.440631 Final RX Vref Byte 0 = 60 to rank1
1176 00:59:32.444154 Final RX Vref Byte 1 = 59 to rank1==
1177 00:59:32.447639 Dram Type= 6, Freq= 0, CH_0, rank 0
1178 00:59:32.451038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 00:59:32.451120 ==
1180 00:59:32.454721 DQS Delay:
1181 00:59:32.454803 DQS0 = 0, DQS1 = 0
1182 00:59:32.454868 DQM Delay:
1183 00:59:32.458129 DQM0 = 87, DQM1 = 76
1184 00:59:32.458210 DQ Delay:
1185 00:59:32.461674 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1186 00:59:32.465119 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1187 00:59:32.468477 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1188 00:59:32.472025 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1189 00:59:32.472107
1190 00:59:32.472171
1191 00:59:32.479347 [DQSOSCAuto] RK0, (LSB)MR18= 0x4728, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1192 00:59:32.483712 CH0 RK0: MR19=606, MR18=4728
1193 00:59:32.530911 CH0_RK0: MR19=0x606, MR18=0x4728, DQSOSC=392, MR23=63, INC=96, DEC=64
1194 00:59:32.531030
1195 00:59:32.531097 ----->DramcWriteLeveling(PI) begin...
1196 00:59:32.531160 ==
1197 00:59:32.531446 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 00:59:32.531793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 00:59:32.531876 ==
1200 00:59:32.531940 Write leveling (Byte 0): 32 => 32
1201 00:59:32.532068 Write leveling (Byte 1): 31 => 31
1202 00:59:32.532149 DramcWriteLeveling(PI) end<-----
1203 00:59:32.532214
1204 00:59:32.532272 ==
1205 00:59:32.532359 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 00:59:32.532443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 00:59:32.532503 ==
1208 00:59:32.532594 [Gating] SW mode calibration
1209 00:59:32.532845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1210 00:59:32.532908 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1211 00:59:32.574902 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 00:59:32.575318 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1213 00:59:32.575868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1214 00:59:32.576500 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1215 00:59:32.576582 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 00:59:32.576831 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 00:59:32.577123 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 00:59:32.577829 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 00:59:32.578094 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 00:59:32.578164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 00:59:32.619453 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 00:59:32.619580 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 00:59:32.619838 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 00:59:32.620244 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 00:59:32.620327 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 00:59:32.620887 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 00:59:32.621179 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 00:59:32.621574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1229 00:59:32.622066 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1230 00:59:32.622147 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 00:59:32.641034 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 00:59:32.641657 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 00:59:32.642122 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 00:59:32.642389 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 00:59:32.642458 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 00:59:32.645404 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 00:59:32.649736 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (1 1) (0 0)
1238 00:59:32.657008 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 00:59:32.660530 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 00:59:32.664406 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 00:59:32.668024 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 00:59:32.671826 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 00:59:32.679433 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 00:59:32.682322 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1245 00:59:32.685776 0 10 8 | B1->B0 | 3232 2b2b | 1 1 | (1 0) (1 0)
1246 00:59:32.689809 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 00:59:32.693142 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 00:59:32.700880 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 00:59:32.704808 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 00:59:32.708223 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 00:59:32.711875 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 00:59:32.715566 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 00:59:32.722279 0 11 8 | B1->B0 | 2b2b 3b3b | 0 1 | (0 0) (0 0)
1254 00:59:32.725979 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1255 00:59:32.729894 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 00:59:32.733687 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 00:59:32.737550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 00:59:32.745166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 00:59:32.748915 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 00:59:32.752457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1261 00:59:32.756102 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1262 00:59:32.759653 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1263 00:59:32.766308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 00:59:32.770485 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 00:59:32.774033 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 00:59:32.777480 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 00:59:32.781582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 00:59:32.788609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 00:59:32.792285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 00:59:32.796601 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 00:59:32.799179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 00:59:32.806893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 00:59:32.810624 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 00:59:32.813574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 00:59:32.817087 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 00:59:32.820727 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 00:59:32.827836 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1278 00:59:32.831893 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 00:59:32.835149 Total UI for P1: 0, mck2ui 16
1280 00:59:32.838659 best dqsien dly found for B0: ( 0, 14, 8)
1281 00:59:32.838742 Total UI for P1: 0, mck2ui 16
1282 00:59:32.842137 best dqsien dly found for B1: ( 0, 14, 8)
1283 00:59:32.845877 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1284 00:59:32.849457 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1285 00:59:32.849541
1286 00:59:32.854101 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1287 00:59:32.858513 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1288 00:59:32.861056 [Gating] SW calibration Done
1289 00:59:32.861176 ==
1290 00:59:32.864656 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 00:59:32.868043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 00:59:32.868148 ==
1293 00:59:32.871772 RX Vref Scan: 0
1294 00:59:32.871884
1295 00:59:32.871973 RX Vref 0 -> 0, step: 1
1296 00:59:32.872057
1297 00:59:32.874874 RX Delay -130 -> 252, step: 16
1298 00:59:32.878837 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1299 00:59:32.885491 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1300 00:59:32.890051 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1301 00:59:32.893554 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1302 00:59:32.896866 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1303 00:59:32.900741 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1304 00:59:32.904481 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1305 00:59:32.908265 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1306 00:59:32.911615 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1307 00:59:32.915040 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1308 00:59:32.921148 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1309 00:59:32.924521 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1310 00:59:32.927966 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1311 00:59:32.931114 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1312 00:59:32.934577 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1313 00:59:32.941691 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1314 00:59:32.941859 ==
1315 00:59:32.944553 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 00:59:32.947954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 00:59:32.948121 ==
1318 00:59:32.948253 DQS Delay:
1319 00:59:32.951315 DQS0 = 0, DQS1 = 0
1320 00:59:32.951481 DQM Delay:
1321 00:59:32.954417 DQM0 = 83, DQM1 = 78
1322 00:59:32.954611 DQ Delay:
1323 00:59:32.957763 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1324 00:59:32.961273 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1325 00:59:32.964650 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1326 00:59:32.967485 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1327 00:59:32.967809
1328 00:59:32.968037
1329 00:59:32.968245 ==
1330 00:59:32.971177 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 00:59:32.974781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 00:59:32.975060 ==
1333 00:59:32.977615
1334 00:59:32.977891
1335 00:59:32.978107 TX Vref Scan disable
1336 00:59:32.980733 == TX Byte 0 ==
1337 00:59:32.984481 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1338 00:59:32.987752 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1339 00:59:32.990942 == TX Byte 1 ==
1340 00:59:32.994404 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1341 00:59:32.997940 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1342 00:59:32.998220 ==
1343 00:59:33.001068 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 00:59:33.007854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 00:59:33.008139 ==
1346 00:59:33.019404 TX Vref=22, minBit 0, minWin=27, winSum=447
1347 00:59:33.023719 TX Vref=24, minBit 11, minWin=27, winSum=449
1348 00:59:33.026134 TX Vref=26, minBit 9, minWin=27, winSum=449
1349 00:59:33.029350 TX Vref=28, minBit 9, minWin=27, winSum=447
1350 00:59:33.033185 TX Vref=30, minBit 9, minWin=27, winSum=446
1351 00:59:33.039148 TX Vref=32, minBit 9, minWin=27, winSum=445
1352 00:59:33.042673 [TxChooseVref] Worse bit 11, Min win 27, Win sum 449, Final Vref 24
1353 00:59:33.042802
1354 00:59:33.045946 Final TX Range 1 Vref 24
1355 00:59:33.046058
1356 00:59:33.046145 ==
1357 00:59:33.048890 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 00:59:33.056101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 00:59:33.056192 ==
1360 00:59:33.056263
1361 00:59:33.056332
1362 00:59:33.056397 TX Vref Scan disable
1363 00:59:33.059719 == TX Byte 0 ==
1364 00:59:33.063085 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1365 00:59:33.069554 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1366 00:59:33.069643 == TX Byte 1 ==
1367 00:59:33.073150 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1368 00:59:33.079379 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1369 00:59:33.079469
1370 00:59:33.079539 [DATLAT]
1371 00:59:33.079607 Freq=800, CH0 RK1
1372 00:59:33.079682
1373 00:59:33.082445 DATLAT Default: 0xa
1374 00:59:33.082564 0, 0xFFFF, sum = 0
1375 00:59:33.086037 1, 0xFFFF, sum = 0
1376 00:59:33.089373 2, 0xFFFF, sum = 0
1377 00:59:33.089463 3, 0xFFFF, sum = 0
1378 00:59:33.120426 4, 0xFFFF, sum = 0
1379 00:59:33.120867 5, 0xFFFF, sum = 0
1380 00:59:33.121204 6, 0xFFFF, sum = 0
1381 00:59:33.121519 7, 0xFFFF, sum = 0
1382 00:59:33.121822 8, 0xFFFF, sum = 0
1383 00:59:33.122117 9, 0x0, sum = 1
1384 00:59:33.122441 10, 0x0, sum = 2
1385 00:59:33.122891 11, 0x0, sum = 3
1386 00:59:33.123254 12, 0x0, sum = 4
1387 00:59:33.123550 best_step = 10
1388 00:59:33.123922
1389 00:59:33.124214 ==
1390 00:59:33.124497 Dram Type= 6, Freq= 0, CH_0, rank 1
1391 00:59:33.124782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 00:59:33.125066 ==
1393 00:59:33.125346 RX Vref Scan: 0
1394 00:59:33.125625
1395 00:59:33.125915 RX Vref 0 -> 0, step: 1
1396 00:59:33.126195
1397 00:59:33.126472 RX Delay -95 -> 252, step: 8
1398 00:59:33.127084 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1399 00:59:33.130536 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1400 00:59:33.133252 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1401 00:59:33.136627 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1402 00:59:33.139756 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1403 00:59:33.146024 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1404 00:59:33.149757 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1405 00:59:33.153305 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1406 00:59:33.156165 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1407 00:59:33.159548 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1408 00:59:33.166184 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1409 00:59:33.169535 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1410 00:59:33.172981 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1411 00:59:33.176309 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1412 00:59:33.182317 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1413 00:59:33.185710 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1414 00:59:33.186345 ==
1415 00:59:33.189309 Dram Type= 6, Freq= 0, CH_0, rank 1
1416 00:59:33.192578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 00:59:33.193119 ==
1418 00:59:33.195617 DQS Delay:
1419 00:59:33.196151 DQS0 = 0, DQS1 = 0
1420 00:59:33.196715 DQM Delay:
1421 00:59:33.199629 DQM0 = 85, DQM1 = 77
1422 00:59:33.200275 DQ Delay:
1423 00:59:33.202553 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =84
1424 00:59:33.205826 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1425 00:59:33.209222 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1426 00:59:33.212727 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1427 00:59:33.213160
1428 00:59:33.213563
1429 00:59:33.222141 [DQSOSCAuto] RK1, (LSB)MR18= 0x4006, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1430 00:59:33.225325 CH0 RK1: MR19=606, MR18=4006
1431 00:59:33.228961 CH0_RK1: MR19=0x606, MR18=0x4006, DQSOSC=393, MR23=63, INC=95, DEC=63
1432 00:59:33.233000 [RxdqsGatingPostProcess] freq 800
1433 00:59:33.239607 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1434 00:59:33.242915 Pre-setting of DQS Precalculation
1435 00:59:33.245211 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1436 00:59:33.245627 ==
1437 00:59:33.248612 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 00:59:33.255156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 00:59:33.255456 ==
1440 00:59:33.258764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 00:59:33.264786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 00:59:33.274570 [CA 0] Center 36 (6~67) winsize 62
1443 00:59:33.277675 [CA 1] Center 36 (6~67) winsize 62
1444 00:59:33.281913 [CA 2] Center 34 (4~65) winsize 62
1445 00:59:33.284386 [CA 3] Center 34 (3~65) winsize 63
1446 00:59:33.287977 [CA 4] Center 34 (4~65) winsize 62
1447 00:59:33.290631 [CA 5] Center 34 (4~65) winsize 62
1448 00:59:33.290721
1449 00:59:33.294514 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1450 00:59:33.294596
1451 00:59:33.297956 [CATrainingPosCal] consider 1 rank data
1452 00:59:33.301098 u2DelayCellTimex100 = 270/100 ps
1453 00:59:33.304120 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 00:59:33.307878 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1455 00:59:33.314343 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 00:59:33.318008 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1457 00:59:33.320690 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 00:59:33.324189 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 00:59:33.324286
1460 00:59:33.327749 CA PerBit enable=1, Macro0, CA PI delay=34
1461 00:59:33.327830
1462 00:59:33.331015 [CBTSetCACLKResult] CA Dly = 34
1463 00:59:33.331095 CS Dly: 5 (0~36)
1464 00:59:33.334086 ==
1465 00:59:33.337400 Dram Type= 6, Freq= 0, CH_1, rank 1
1466 00:59:33.342317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1467 00:59:33.342398 ==
1468 00:59:33.344508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1469 00:59:33.350383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1470 00:59:33.360525 [CA 0] Center 36 (6~67) winsize 62
1471 00:59:33.364011 [CA 1] Center 37 (6~68) winsize 63
1472 00:59:33.366923 [CA 2] Center 34 (4~65) winsize 62
1473 00:59:33.370117 [CA 3] Center 34 (3~65) winsize 63
1474 00:59:33.373555 [CA 4] Center 34 (4~65) winsize 62
1475 00:59:33.377419 [CA 5] Center 33 (3~64) winsize 62
1476 00:59:33.377499
1477 00:59:33.380285 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1478 00:59:33.380365
1479 00:59:33.383331 [CATrainingPosCal] consider 2 rank data
1480 00:59:33.386872 u2DelayCellTimex100 = 270/100 ps
1481 00:59:33.390072 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 00:59:33.397095 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1483 00:59:33.400164 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 00:59:33.403148 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 00:59:33.406458 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 00:59:33.409831 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1487 00:59:33.409912
1488 00:59:33.413270 CA PerBit enable=1, Macro0, CA PI delay=34
1489 00:59:33.413352
1490 00:59:33.416454 [CBTSetCACLKResult] CA Dly = 34
1491 00:59:33.419922 CS Dly: 6 (0~38)
1492 00:59:33.420002
1493 00:59:33.423431 ----->DramcWriteLeveling(PI) begin...
1494 00:59:33.423512 ==
1495 00:59:33.426974 Dram Type= 6, Freq= 0, CH_1, rank 0
1496 00:59:33.429871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1497 00:59:33.429951 ==
1498 00:59:33.433243 Write leveling (Byte 0): 27 => 27
1499 00:59:33.436779 Write leveling (Byte 1): 28 => 28
1500 00:59:33.440241 DramcWriteLeveling(PI) end<-----
1501 00:59:33.440322
1502 00:59:33.440386 ==
1503 00:59:33.443570 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 00:59:33.446852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 00:59:33.446933 ==
1506 00:59:33.450072 [Gating] SW mode calibration
1507 00:59:33.456577 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1508 00:59:33.464245 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1509 00:59:33.466602 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1510 00:59:33.469707 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1511 00:59:33.476559 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1512 00:59:33.479666 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 00:59:33.483293 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 00:59:33.490507 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 00:59:33.493091 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 00:59:33.496802 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 00:59:33.503002 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 00:59:33.506592 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 00:59:33.509911 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 00:59:33.516175 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 00:59:33.519623 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 00:59:33.522897 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 00:59:33.529744 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 00:59:33.532992 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 00:59:33.536842 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1526 00:59:33.539747 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1527 00:59:33.546183 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1528 00:59:33.549620 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 00:59:33.553035 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 00:59:33.559365 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 00:59:33.563021 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 00:59:33.565841 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 00:59:33.572756 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 00:59:33.575746 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 00:59:33.579477 0 9 8 | B1->B0 | 2c2c 3434 | 1 0 | (1 1) (0 0)
1536 00:59:33.585912 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 00:59:33.589464 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 00:59:33.592450 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 00:59:33.599042 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 00:59:33.602268 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 00:59:33.606056 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1542 00:59:33.612800 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1543 00:59:33.615588 0 10 8 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
1544 00:59:33.619266 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1545 00:59:33.625853 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 00:59:33.628993 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 00:59:33.632787 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 00:59:33.638867 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 00:59:33.642282 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 00:59:33.645472 0 11 4 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
1551 00:59:33.652104 0 11 8 | B1->B0 | 3a3a 3f3f | 0 1 | (0 0) (0 0)
1552 00:59:33.655584 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 00:59:33.658818 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 00:59:33.665542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 00:59:33.668649 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 00:59:33.672531 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 00:59:33.679277 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 00:59:33.681822 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 00:59:33.685046 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1560 00:59:33.691830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 00:59:33.695718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 00:59:33.698565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 00:59:33.705620 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 00:59:33.708514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 00:59:33.712341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 00:59:33.718471 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 00:59:33.722255 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 00:59:33.725299 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 00:59:33.731629 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 00:59:33.734794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 00:59:33.738820 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 00:59:33.744948 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 00:59:33.748615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 00:59:33.751647 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 00:59:33.758113 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 00:59:33.758545 Total UI for P1: 0, mck2ui 16
1577 00:59:33.761665 best dqsien dly found for B0: ( 0, 14, 6)
1578 00:59:33.764855 Total UI for P1: 0, mck2ui 16
1579 00:59:33.768442 best dqsien dly found for B1: ( 0, 14, 6)
1580 00:59:33.775056 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1581 00:59:33.778341 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1582 00:59:33.778780
1583 00:59:33.781278 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1584 00:59:33.784578 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1585 00:59:33.788275 [Gating] SW calibration Done
1586 00:59:33.788704 ==
1587 00:59:33.791155 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 00:59:33.794637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 00:59:33.795072 ==
1590 00:59:33.797965 RX Vref Scan: 0
1591 00:59:33.798393
1592 00:59:33.798828 RX Vref 0 -> 0, step: 1
1593 00:59:33.799237
1594 00:59:33.801670 RX Delay -130 -> 252, step: 16
1595 00:59:33.804421 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1596 00:59:33.811563 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1597 00:59:33.814604 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1598 00:59:33.817701 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1599 00:59:33.821851 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1600 00:59:33.824325 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1601 00:59:33.830918 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1602 00:59:33.834288 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1603 00:59:33.837501 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1604 00:59:33.841100 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1605 00:59:33.844480 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1606 00:59:33.850947 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1607 00:59:33.854227 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1608 00:59:33.857214 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1609 00:59:33.861138 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1610 00:59:33.867742 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1611 00:59:33.868176 ==
1612 00:59:33.870511 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 00:59:33.873733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 00:59:33.874155 ==
1615 00:59:33.874519 DQS Delay:
1616 00:59:33.877362 DQS0 = 0, DQS1 = 0
1617 00:59:33.877776 DQM Delay:
1618 00:59:33.880379 DQM0 = 89, DQM1 = 78
1619 00:59:33.880797 DQ Delay:
1620 00:59:33.883639 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1621 00:59:33.887043 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1622 00:59:33.890587 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1623 00:59:33.893800 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1624 00:59:33.894316
1625 00:59:33.894739
1626 00:59:33.895057 ==
1627 00:59:33.897195 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 00:59:33.900258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 00:59:33.900679 ==
1630 00:59:33.903441
1631 00:59:33.903890
1632 00:59:33.904219 TX Vref Scan disable
1633 00:59:33.907362 == TX Byte 0 ==
1634 00:59:33.910479 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1635 00:59:33.913564 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1636 00:59:33.917033 == TX Byte 1 ==
1637 00:59:33.920252 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1638 00:59:33.924179 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1639 00:59:33.924597 ==
1640 00:59:33.927052 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 00:59:33.933267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 00:59:33.933688 ==
1643 00:59:33.946970 TX Vref=22, minBit 10, minWin=26, winSum=444
1644 00:59:33.948746 TX Vref=24, minBit 3, minWin=27, winSum=450
1645 00:59:33.953128 TX Vref=26, minBit 8, minWin=27, winSum=452
1646 00:59:33.955951 TX Vref=28, minBit 15, minWin=27, winSum=454
1647 00:59:33.958773 TX Vref=30, minBit 9, minWin=27, winSum=448
1648 00:59:33.965528 TX Vref=32, minBit 9, minWin=27, winSum=447
1649 00:59:33.968244 [TxChooseVref] Worse bit 15, Min win 27, Win sum 454, Final Vref 28
1650 00:59:33.968731
1651 00:59:33.972116 Final TX Range 1 Vref 28
1652 00:59:33.972552
1653 00:59:33.972988 ==
1654 00:59:33.975046 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 00:59:33.978568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 00:59:33.981570 ==
1657 00:59:33.982001
1658 00:59:33.982441
1659 00:59:33.982856 TX Vref Scan disable
1660 00:59:33.985817 == TX Byte 0 ==
1661 00:59:33.988998 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1662 00:59:33.995442 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1663 00:59:33.995939 == TX Byte 1 ==
1664 00:59:33.998878 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1665 00:59:34.005726 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1666 00:59:34.006159
1667 00:59:34.006596 [DATLAT]
1668 00:59:34.007010 Freq=800, CH1 RK0
1669 00:59:34.007415
1670 00:59:34.009085 DATLAT Default: 0xa
1671 00:59:34.009514 0, 0xFFFF, sum = 0
1672 00:59:34.011928 1, 0xFFFF, sum = 0
1673 00:59:34.015134 2, 0xFFFF, sum = 0
1674 00:59:34.015566 3, 0xFFFF, sum = 0
1675 00:59:34.019093 4, 0xFFFF, sum = 0
1676 00:59:34.019529 5, 0xFFFF, sum = 0
1677 00:59:34.022058 6, 0xFFFF, sum = 0
1678 00:59:34.022621 7, 0xFFFF, sum = 0
1679 00:59:34.025655 8, 0xFFFF, sum = 0
1680 00:59:34.026113 9, 0x0, sum = 1
1681 00:59:34.028610 10, 0x0, sum = 2
1682 00:59:34.029038 11, 0x0, sum = 3
1683 00:59:34.029373 12, 0x0, sum = 4
1684 00:59:34.031946 best_step = 10
1685 00:59:34.032364
1686 00:59:34.032691 ==
1687 00:59:34.035227 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 00:59:34.038722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 00:59:34.039142 ==
1690 00:59:34.041987 RX Vref Scan: 1
1691 00:59:34.042505
1692 00:59:34.045346 Set Vref Range= 32 -> 127
1693 00:59:34.045762
1694 00:59:34.046090 RX Vref 32 -> 127, step: 1
1695 00:59:34.046400
1696 00:59:34.048533 RX Delay -95 -> 252, step: 8
1697 00:59:34.049010
1698 00:59:34.051773 Set Vref, RX VrefLevel [Byte0]: 32
1699 00:59:34.054988 [Byte1]: 32
1700 00:59:34.058705
1701 00:59:34.059122 Set Vref, RX VrefLevel [Byte0]: 33
1702 00:59:34.061878 [Byte1]: 33
1703 00:59:34.066118
1704 00:59:34.069302 Set Vref, RX VrefLevel [Byte0]: 34
1705 00:59:34.072702 [Byte1]: 34
1706 00:59:34.073122
1707 00:59:34.075784 Set Vref, RX VrefLevel [Byte0]: 35
1708 00:59:34.079775 [Byte1]: 35
1709 00:59:34.080192
1710 00:59:34.082236 Set Vref, RX VrefLevel [Byte0]: 36
1711 00:59:34.085683 [Byte1]: 36
1712 00:59:34.089234
1713 00:59:34.089649 Set Vref, RX VrefLevel [Byte0]: 37
1714 00:59:34.092364 [Byte1]: 37
1715 00:59:34.096610
1716 00:59:34.097026 Set Vref, RX VrefLevel [Byte0]: 38
1717 00:59:34.099397 [Byte1]: 38
1718 00:59:34.103825
1719 00:59:34.104246 Set Vref, RX VrefLevel [Byte0]: 39
1720 00:59:34.107367 [Byte1]: 39
1721 00:59:34.111414
1722 00:59:34.111873 Set Vref, RX VrefLevel [Byte0]: 40
1723 00:59:34.114761 [Byte1]: 40
1724 00:59:34.119021
1725 00:59:34.119436 Set Vref, RX VrefLevel [Byte0]: 41
1726 00:59:34.122162 [Byte1]: 41
1727 00:59:34.126367
1728 00:59:34.126791 Set Vref, RX VrefLevel [Byte0]: 42
1729 00:59:34.129591 [Byte1]: 42
1730 00:59:34.134235
1731 00:59:34.134654 Set Vref, RX VrefLevel [Byte0]: 43
1732 00:59:34.137297 [Byte1]: 43
1733 00:59:34.142041
1734 00:59:34.142457 Set Vref, RX VrefLevel [Byte0]: 44
1735 00:59:34.144977 [Byte1]: 44
1736 00:59:34.149614
1737 00:59:34.150031 Set Vref, RX VrefLevel [Byte0]: 45
1738 00:59:34.152825 [Byte1]: 45
1739 00:59:34.157124
1740 00:59:34.157629 Set Vref, RX VrefLevel [Byte0]: 46
1741 00:59:34.160273 [Byte1]: 46
1742 00:59:34.164281
1743 00:59:34.167560 Set Vref, RX VrefLevel [Byte0]: 47
1744 00:59:34.167668 [Byte1]: 47
1745 00:59:34.172321
1746 00:59:34.172409 Set Vref, RX VrefLevel [Byte0]: 48
1747 00:59:34.175243 [Byte1]: 48
1748 00:59:34.179434
1749 00:59:34.179567 Set Vref, RX VrefLevel [Byte0]: 49
1750 00:59:34.183294 [Byte1]: 49
1751 00:59:34.187153
1752 00:59:34.187263 Set Vref, RX VrefLevel [Byte0]: 50
1753 00:59:34.190389 [Byte1]: 50
1754 00:59:34.194616
1755 00:59:34.194749 Set Vref, RX VrefLevel [Byte0]: 51
1756 00:59:34.198136 [Byte1]: 51
1757 00:59:34.202627
1758 00:59:34.202707 Set Vref, RX VrefLevel [Byte0]: 52
1759 00:59:34.205497 [Byte1]: 52
1760 00:59:34.210069
1761 00:59:34.210150 Set Vref, RX VrefLevel [Byte0]: 53
1762 00:59:34.212825 [Byte1]: 53
1763 00:59:34.218032
1764 00:59:34.218113 Set Vref, RX VrefLevel [Byte0]: 54
1765 00:59:34.220696 [Byte1]: 54
1766 00:59:34.224873
1767 00:59:34.224965 Set Vref, RX VrefLevel [Byte0]: 55
1768 00:59:34.228752 [Byte1]: 55
1769 00:59:34.233175
1770 00:59:34.233255 Set Vref, RX VrefLevel [Byte0]: 56
1771 00:59:34.236035 [Byte1]: 56
1772 00:59:34.240517
1773 00:59:34.240598 Set Vref, RX VrefLevel [Byte0]: 57
1774 00:59:34.243541 [Byte1]: 57
1775 00:59:34.248226
1776 00:59:34.248307 Set Vref, RX VrefLevel [Byte0]: 58
1777 00:59:34.250905 [Byte1]: 58
1778 00:59:34.255383
1779 00:59:34.255464 Set Vref, RX VrefLevel [Byte0]: 59
1780 00:59:34.258988 [Byte1]: 59
1781 00:59:34.263247
1782 00:59:34.263328 Set Vref, RX VrefLevel [Byte0]: 60
1783 00:59:34.267129 [Byte1]: 60
1784 00:59:34.271211
1785 00:59:34.271291 Set Vref, RX VrefLevel [Byte0]: 61
1786 00:59:34.274322 [Byte1]: 61
1787 00:59:34.278190
1788 00:59:34.278270 Set Vref, RX VrefLevel [Byte0]: 62
1789 00:59:34.281321 [Byte1]: 62
1790 00:59:34.285926
1791 00:59:34.286007 Set Vref, RX VrefLevel [Byte0]: 63
1792 00:59:34.288968 [Byte1]: 63
1793 00:59:34.293646
1794 00:59:34.293727 Set Vref, RX VrefLevel [Byte0]: 64
1795 00:59:34.299609 [Byte1]: 64
1796 00:59:34.299746
1797 00:59:34.302958 Set Vref, RX VrefLevel [Byte0]: 65
1798 00:59:34.307065 [Byte1]: 65
1799 00:59:34.307145
1800 00:59:34.310989 Set Vref, RX VrefLevel [Byte0]: 66
1801 00:59:34.313320 [Byte1]: 66
1802 00:59:34.313427
1803 00:59:34.316839 Set Vref, RX VrefLevel [Byte0]: 67
1804 00:59:34.319883 [Byte1]: 67
1805 00:59:34.323914
1806 00:59:34.323996 Set Vref, RX VrefLevel [Byte0]: 68
1807 00:59:34.326988 [Byte1]: 68
1808 00:59:34.331360
1809 00:59:34.331440 Set Vref, RX VrefLevel [Byte0]: 69
1810 00:59:34.335500 [Byte1]: 69
1811 00:59:34.339289
1812 00:59:34.339370 Set Vref, RX VrefLevel [Byte0]: 70
1813 00:59:34.342209 [Byte1]: 70
1814 00:59:34.346378
1815 00:59:34.346464 Set Vref, RX VrefLevel [Byte0]: 71
1816 00:59:34.350137 [Byte1]: 71
1817 00:59:34.354082
1818 00:59:34.354182 Set Vref, RX VrefLevel [Byte0]: 72
1819 00:59:34.357462 [Byte1]: 72
1820 00:59:34.361846
1821 00:59:34.361955 Set Vref, RX VrefLevel [Byte0]: 73
1822 00:59:34.365297 [Byte1]: 73
1823 00:59:34.370183
1824 00:59:34.370601 Set Vref, RX VrefLevel [Byte0]: 74
1825 00:59:34.373576 [Byte1]: 74
1826 00:59:34.377467
1827 00:59:34.377882 Final RX Vref Byte 0 = 56 to rank0
1828 00:59:34.380668 Final RX Vref Byte 1 = 64 to rank0
1829 00:59:34.383981 Final RX Vref Byte 0 = 56 to rank1
1830 00:59:34.387556 Final RX Vref Byte 1 = 64 to rank1==
1831 00:59:34.390571 Dram Type= 6, Freq= 0, CH_1, rank 0
1832 00:59:34.397215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 00:59:34.397634 ==
1834 00:59:34.397968 DQS Delay:
1835 00:59:34.400628 DQS0 = 0, DQS1 = 0
1836 00:59:34.401045 DQM Delay:
1837 00:59:34.401373 DQM0 = 86, DQM1 = 79
1838 00:59:34.404600 DQ Delay:
1839 00:59:34.406865 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1840 00:59:34.410338 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1841 00:59:34.414029 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1842 00:59:34.416900 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1843 00:59:34.417318
1844 00:59:34.417647
1845 00:59:34.424090 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e1a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1846 00:59:34.427332 CH1 RK0: MR19=606, MR18=2E1A
1847 00:59:34.433816 CH1_RK0: MR19=0x606, MR18=0x2E1A, DQSOSC=398, MR23=63, INC=93, DEC=62
1848 00:59:34.434237
1849 00:59:34.437515 ----->DramcWriteLeveling(PI) begin...
1850 00:59:34.437947 ==
1851 00:59:34.440447 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 00:59:34.443788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 00:59:34.444228 ==
1854 00:59:34.447278 Write leveling (Byte 0): 27 => 27
1855 00:59:34.450487 Write leveling (Byte 1): 30 => 30
1856 00:59:34.454029 DramcWriteLeveling(PI) end<-----
1857 00:59:34.454575
1858 00:59:34.455153 ==
1859 00:59:34.456603 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 00:59:34.460192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 00:59:34.460618 ==
1862 00:59:34.463907 [Gating] SW mode calibration
1863 00:59:34.470568 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1864 00:59:34.477009 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1865 00:59:34.479581 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1866 00:59:34.486647 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1867 00:59:34.489873 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1868 00:59:34.493385 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 00:59:34.500106 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 00:59:34.502766 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 00:59:34.506310 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 00:59:34.513372 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 00:59:34.516250 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 00:59:34.519567 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 00:59:34.526170 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 00:59:34.529309 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 00:59:34.532983 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 00:59:34.539414 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 00:59:34.543049 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 00:59:34.545964 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 00:59:34.552535 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 00:59:34.556177 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1883 00:59:34.559645 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 00:59:34.565960 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 00:59:34.569712 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 00:59:34.572911 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 00:59:34.579198 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 00:59:34.582070 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 00:59:34.585446 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 00:59:34.592156 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 00:59:34.596462 0 9 8 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 1)
1892 00:59:34.598650 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 00:59:34.605553 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 00:59:34.608561 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 00:59:34.611985 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 00:59:34.619663 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 00:59:34.622131 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 00:59:34.625179 0 10 4 | B1->B0 | 3030 3434 | 0 1 | (1 0) (1 1)
1899 00:59:34.628854 0 10 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 0)
1900 00:59:34.635362 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 00:59:34.638794 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 00:59:34.642127 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 00:59:34.648825 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 00:59:34.651862 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 00:59:34.655742 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 00:59:34.662003 0 11 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1907 00:59:34.665014 0 11 8 | B1->B0 | 4343 3a3a | 0 0 | (0 0) (0 0)
1908 00:59:34.668152 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 00:59:34.675209 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 00:59:34.679165 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 00:59:34.681502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 00:59:34.688368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 00:59:34.691515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 00:59:34.695032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 00:59:34.701405 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 00:59:34.704660 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 00:59:34.708129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 00:59:34.715174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 00:59:34.718131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 00:59:34.721559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 00:59:34.728482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 00:59:34.731529 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 00:59:34.734579 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 00:59:34.741351 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 00:59:34.744564 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 00:59:34.748133 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 00:59:34.755007 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 00:59:34.757825 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 00:59:34.760994 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 00:59:34.767518 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 00:59:34.770978 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 00:59:34.774272 Total UI for P1: 0, mck2ui 16
1933 00:59:34.777493 best dqsien dly found for B0: ( 0, 14, 6)
1934 00:59:34.781313 Total UI for P1: 0, mck2ui 16
1935 00:59:34.784429 best dqsien dly found for B1: ( 0, 14, 6)
1936 00:59:34.788068 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1937 00:59:34.790643 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1938 00:59:34.791058
1939 00:59:34.794138 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1940 00:59:34.797649 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1941 00:59:34.800502 [Gating] SW calibration Done
1942 00:59:34.800917 ==
1943 00:59:34.804384 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 00:59:34.808350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 00:59:34.808762 ==
1946 00:59:34.810547 RX Vref Scan: 0
1947 00:59:34.810992
1948 00:59:34.813900 RX Vref 0 -> 0, step: 1
1949 00:59:34.814310
1950 00:59:34.817135 RX Delay -130 -> 252, step: 16
1951 00:59:34.820884 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1952 00:59:34.823851 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1953 00:59:34.826999 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1954 00:59:34.830988 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1955 00:59:34.837706 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1956 00:59:34.840604 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1957 00:59:34.844073 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1958 00:59:34.847623 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1959 00:59:34.850506 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1960 00:59:34.853592 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1961 00:59:34.860977 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1962 00:59:34.863541 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1963 00:59:34.867125 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1964 00:59:34.870874 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1965 00:59:34.877145 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1966 00:59:34.880362 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1967 00:59:34.880448 ==
1968 00:59:34.883847 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 00:59:34.887536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 00:59:34.887617 ==
1971 00:59:34.887689 DQS Delay:
1972 00:59:34.890722 DQS0 = 0, DQS1 = 0
1973 00:59:34.890808 DQM Delay:
1974 00:59:34.893593 DQM0 = 86, DQM1 = 78
1975 00:59:34.893673 DQ Delay:
1976 00:59:34.898643 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1977 00:59:34.900527 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1978 00:59:34.903535 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1979 00:59:34.906740 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1980 00:59:34.906848
1981 00:59:34.906911
1982 00:59:34.906971 ==
1983 00:59:34.910136 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 00:59:34.916594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 00:59:34.916676 ==
1986 00:59:34.916739
1987 00:59:34.916799
1988 00:59:34.916855 TX Vref Scan disable
1989 00:59:34.920072 == TX Byte 0 ==
1990 00:59:34.924091 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 00:59:34.930019 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 00:59:34.930100 == TX Byte 1 ==
1993 00:59:34.933190 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1994 00:59:34.940017 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1995 00:59:34.940105 ==
1996 00:59:34.943501 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 00:59:34.946868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 00:59:34.946942 ==
1999 00:59:34.959472 TX Vref=22, minBit 1, minWin=27, winSum=442
2000 00:59:34.963091 TX Vref=24, minBit 8, minWin=27, winSum=449
2001 00:59:34.965884 TX Vref=26, minBit 8, minWin=27, winSum=451
2002 00:59:34.969653 TX Vref=28, minBit 13, minWin=27, winSum=451
2003 00:59:34.972463 TX Vref=30, minBit 8, minWin=27, winSum=449
2004 00:59:34.979082 TX Vref=32, minBit 8, minWin=27, winSum=450
2005 00:59:34.982962 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 26
2006 00:59:34.983069
2007 00:59:34.986407 Final TX Range 1 Vref 26
2008 00:59:34.986484
2009 00:59:34.986550 ==
2010 00:59:34.989597 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 00:59:34.992611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 00:59:34.995963 ==
2013 00:59:34.996035
2014 00:59:34.996096
2015 00:59:34.996153 TX Vref Scan disable
2016 00:59:34.999791 == TX Byte 0 ==
2017 00:59:35.002784 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2018 00:59:35.010252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2019 00:59:35.010330 == TX Byte 1 ==
2020 00:59:35.012669 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2021 00:59:35.019847 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2022 00:59:35.019964
2023 00:59:35.020057 [DATLAT]
2024 00:59:35.020177 Freq=800, CH1 RK1
2025 00:59:35.020265
2026 00:59:35.023171 DATLAT Default: 0xa
2027 00:59:35.023267 0, 0xFFFF, sum = 0
2028 00:59:35.025782 1, 0xFFFF, sum = 0
2029 00:59:35.025854 2, 0xFFFF, sum = 0
2030 00:59:35.029552 3, 0xFFFF, sum = 0
2031 00:59:35.029622 4, 0xFFFF, sum = 0
2032 00:59:35.033199 5, 0xFFFF, sum = 0
2033 00:59:35.035952 6, 0xFFFF, sum = 0
2034 00:59:35.036062 7, 0xFFFF, sum = 0
2035 00:59:35.039121 8, 0xFFFF, sum = 0
2036 00:59:35.039196 9, 0x0, sum = 1
2037 00:59:35.039258 10, 0x0, sum = 2
2038 00:59:35.042610 11, 0x0, sum = 3
2039 00:59:35.042682 12, 0x0, sum = 4
2040 00:59:35.046368 best_step = 10
2041 00:59:35.046465
2042 00:59:35.046562 ==
2043 00:59:35.049100 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 00:59:35.053113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 00:59:35.053189 ==
2046 00:59:35.055627 RX Vref Scan: 0
2047 00:59:35.055761
2048 00:59:35.055824 RX Vref 0 -> 0, step: 1
2049 00:59:35.059303
2050 00:59:35.059408 RX Delay -95 -> 252, step: 8
2051 00:59:35.065945 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2052 00:59:35.069448 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2053 00:59:35.072563 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2054 00:59:35.076227 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2055 00:59:35.079288 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2056 00:59:35.086165 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2057 00:59:35.089470 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2058 00:59:35.092772 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2059 00:59:35.096087 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2060 00:59:35.102472 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2061 00:59:35.106216 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2062 00:59:35.108873 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2063 00:59:35.112605 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2064 00:59:35.119194 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2065 00:59:35.122490 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2066 00:59:35.125703 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2067 00:59:35.126325 ==
2068 00:59:35.128986 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 00:59:35.132423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 00:59:35.132865 ==
2071 00:59:35.135778 DQS Delay:
2072 00:59:35.136214 DQS0 = 0, DQS1 = 0
2073 00:59:35.136652 DQM Delay:
2074 00:59:35.138780 DQM0 = 87, DQM1 = 78
2075 00:59:35.139212 DQ Delay:
2076 00:59:35.142114 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2077 00:59:35.145552 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2078 00:59:35.149354 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2079 00:59:35.152394 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
2080 00:59:35.152827
2081 00:59:35.153260
2082 00:59:35.162136 [DQSOSCAuto] RK1, (LSB)MR18= 0x1810, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2083 00:59:35.165646 CH1 RK1: MR19=606, MR18=1810
2084 00:59:35.168474 CH1_RK1: MR19=0x606, MR18=0x1810, DQSOSC=403, MR23=63, INC=90, DEC=60
2085 00:59:35.171966 [RxdqsGatingPostProcess] freq 800
2086 00:59:35.178381 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2087 00:59:35.181885 Pre-setting of DQS Precalculation
2088 00:59:35.185393 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2089 00:59:35.195100 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2090 00:59:35.202247 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2091 00:59:35.202764
2092 00:59:35.203096
2093 00:59:35.205118 [Calibration Summary] 1600 Mbps
2094 00:59:35.205533 CH 0, Rank 0
2095 00:59:35.208530 SW Impedance : PASS
2096 00:59:35.208944 DUTY Scan : NO K
2097 00:59:35.212153 ZQ Calibration : PASS
2098 00:59:35.215872 Jitter Meter : NO K
2099 00:59:35.216528 CBT Training : PASS
2100 00:59:35.218813 Write leveling : PASS
2101 00:59:35.221653 RX DQS gating : PASS
2102 00:59:35.222085 RX DQ/DQS(RDDQC) : PASS
2103 00:59:35.224926 TX DQ/DQS : PASS
2104 00:59:35.228144 RX DATLAT : PASS
2105 00:59:35.228574 RX DQ/DQS(Engine): PASS
2106 00:59:35.231983 TX OE : NO K
2107 00:59:35.232417 All Pass.
2108 00:59:35.232856
2109 00:59:35.234951 CH 0, Rank 1
2110 00:59:35.235382 SW Impedance : PASS
2111 00:59:35.237922 DUTY Scan : NO K
2112 00:59:35.241233 ZQ Calibration : PASS
2113 00:59:35.241665 Jitter Meter : NO K
2114 00:59:35.244898 CBT Training : PASS
2115 00:59:35.248097 Write leveling : PASS
2116 00:59:35.248528 RX DQS gating : PASS
2117 00:59:35.251380 RX DQ/DQS(RDDQC) : PASS
2118 00:59:35.254562 TX DQ/DQS : PASS
2119 00:59:35.255036 RX DATLAT : PASS
2120 00:59:35.257747 RX DQ/DQS(Engine): PASS
2121 00:59:35.258191 TX OE : NO K
2122 00:59:35.261244 All Pass.
2123 00:59:35.261790
2124 00:59:35.262281 CH 1, Rank 0
2125 00:59:35.264472 SW Impedance : PASS
2126 00:59:35.264890 DUTY Scan : NO K
2127 00:59:35.267854 ZQ Calibration : PASS
2128 00:59:35.271093 Jitter Meter : NO K
2129 00:59:35.271508 CBT Training : PASS
2130 00:59:35.274829 Write leveling : PASS
2131 00:59:35.277743 RX DQS gating : PASS
2132 00:59:35.278162 RX DQ/DQS(RDDQC) : PASS
2133 00:59:35.281534 TX DQ/DQS : PASS
2134 00:59:35.284457 RX DATLAT : PASS
2135 00:59:35.284874 RX DQ/DQS(Engine): PASS
2136 00:59:35.287367 TX OE : NO K
2137 00:59:35.287823 All Pass.
2138 00:59:35.288159
2139 00:59:35.291203 CH 1, Rank 1
2140 00:59:35.291621 SW Impedance : PASS
2141 00:59:35.294540 DUTY Scan : NO K
2142 00:59:35.297675 ZQ Calibration : PASS
2143 00:59:35.298123 Jitter Meter : NO K
2144 00:59:35.300739 CBT Training : PASS
2145 00:59:35.303747 Write leveling : PASS
2146 00:59:35.304272 RX DQS gating : PASS
2147 00:59:35.307210 RX DQ/DQS(RDDQC) : PASS
2148 00:59:35.310534 TX DQ/DQS : PASS
2149 00:59:35.310958 RX DATLAT : PASS
2150 00:59:35.313848 RX DQ/DQS(Engine): PASS
2151 00:59:35.317944 TX OE : NO K
2152 00:59:35.318387 All Pass.
2153 00:59:35.318723
2154 00:59:35.319034 DramC Write-DBI off
2155 00:59:35.320821 PER_BANK_REFRESH: Hybrid Mode
2156 00:59:35.323870 TX_TRACKING: ON
2157 00:59:35.327110 [GetDramInforAfterCalByMRR] Vendor 6.
2158 00:59:35.330753 [GetDramInforAfterCalByMRR] Revision 606.
2159 00:59:35.333937 [GetDramInforAfterCalByMRR] Revision 2 0.
2160 00:59:35.334358 MR0 0x3b3b
2161 00:59:35.337587 MR8 0x5151
2162 00:59:35.340528 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 00:59:35.340943
2164 00:59:35.341275 MR0 0x3b3b
2165 00:59:35.341580 MR8 0x5151
2166 00:59:35.346889 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 00:59:35.347322
2168 00:59:35.353562 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2169 00:59:35.356696 [FAST_K] Save calibration result to emmc
2170 00:59:35.360585 [FAST_K] Save calibration result to emmc
2171 00:59:35.363400 dram_init: config_dvfs: 1
2172 00:59:35.367519 dramc_set_vcore_voltage set vcore to 662500
2173 00:59:35.370305 Read voltage for 1200, 2
2174 00:59:35.370734 Vio18 = 0
2175 00:59:35.373386 Vcore = 662500
2176 00:59:35.373803 Vdram = 0
2177 00:59:35.374134 Vddq = 0
2178 00:59:35.376678 Vmddr = 0
2179 00:59:35.380048 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2180 00:59:35.386931 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2181 00:59:35.387347 MEM_TYPE=3, freq_sel=15
2182 00:59:35.390230 sv_algorithm_assistance_LP4_1600
2183 00:59:35.393868 ============ PULL DRAM RESETB DOWN ============
2184 00:59:35.400184 ========== PULL DRAM RESETB DOWN end =========
2185 00:59:35.403514 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2186 00:59:35.406921 ===================================
2187 00:59:35.410091 LPDDR4 DRAM CONFIGURATION
2188 00:59:35.413484 ===================================
2189 00:59:35.413917 EX_ROW_EN[0] = 0x0
2190 00:59:35.416789 EX_ROW_EN[1] = 0x0
2191 00:59:35.419932 LP4Y_EN = 0x0
2192 00:59:35.420389 WORK_FSP = 0x0
2193 00:59:35.423462 WL = 0x4
2194 00:59:35.423942 RL = 0x4
2195 00:59:35.426359 BL = 0x2
2196 00:59:35.426778 RPST = 0x0
2197 00:59:35.429912 RD_PRE = 0x0
2198 00:59:35.430334 WR_PRE = 0x1
2199 00:59:35.433118 WR_PST = 0x0
2200 00:59:35.433543 DBI_WR = 0x0
2201 00:59:35.436572 DBI_RD = 0x0
2202 00:59:35.436994 OTF = 0x1
2203 00:59:35.439724 ===================================
2204 00:59:35.443227 ===================================
2205 00:59:35.446223 ANA top config
2206 00:59:35.449669 ===================================
2207 00:59:35.450084 DLL_ASYNC_EN = 0
2208 00:59:35.453410 ALL_SLAVE_EN = 0
2209 00:59:35.456457 NEW_RANK_MODE = 1
2210 00:59:35.459743 DLL_IDLE_MODE = 1
2211 00:59:35.462959 LP45_APHY_COMB_EN = 1
2212 00:59:35.463373 TX_ODT_DIS = 1
2213 00:59:35.466965 NEW_8X_MODE = 1
2214 00:59:35.469477 ===================================
2215 00:59:35.472682 ===================================
2216 00:59:35.476506 data_rate = 2400
2217 00:59:35.479433 CKR = 1
2218 00:59:35.483043 DQ_P2S_RATIO = 8
2219 00:59:35.487122 ===================================
2220 00:59:35.489418 CA_P2S_RATIO = 8
2221 00:59:35.489875 DQ_CA_OPEN = 0
2222 00:59:35.493155 DQ_SEMI_OPEN = 0
2223 00:59:35.496823 CA_SEMI_OPEN = 0
2224 00:59:35.500022 CA_FULL_RATE = 0
2225 00:59:35.502683 DQ_CKDIV4_EN = 0
2226 00:59:35.506012 CA_CKDIV4_EN = 0
2227 00:59:35.506435 CA_PREDIV_EN = 0
2228 00:59:35.509229 PH8_DLY = 17
2229 00:59:35.512731 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2230 00:59:35.516106 DQ_AAMCK_DIV = 4
2231 00:59:35.519309 CA_AAMCK_DIV = 4
2232 00:59:35.522465 CA_ADMCK_DIV = 4
2233 00:59:35.522888 DQ_TRACK_CA_EN = 0
2234 00:59:35.526373 CA_PICK = 1200
2235 00:59:35.529097 CA_MCKIO = 1200
2236 00:59:35.532251 MCKIO_SEMI = 0
2237 00:59:35.536105 PLL_FREQ = 2366
2238 00:59:35.539511 DQ_UI_PI_RATIO = 32
2239 00:59:35.542355 CA_UI_PI_RATIO = 0
2240 00:59:35.545650 ===================================
2241 00:59:35.549001 ===================================
2242 00:59:35.549416 memory_type:LPDDR4
2243 00:59:35.552133 GP_NUM : 10
2244 00:59:35.556198 SRAM_EN : 1
2245 00:59:35.556615 MD32_EN : 0
2246 00:59:35.559145 ===================================
2247 00:59:35.562440 [ANA_INIT] >>>>>>>>>>>>>>
2248 00:59:35.566157 <<<<<< [CONFIGURE PHASE]: ANA_TX
2249 00:59:35.568973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2250 00:59:35.572505 ===================================
2251 00:59:35.575350 data_rate = 2400,PCW = 0X5b00
2252 00:59:35.579230 ===================================
2253 00:59:35.582727 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2254 00:59:35.586372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 00:59:35.592426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 00:59:35.595809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2257 00:59:35.598408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2258 00:59:35.602075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2259 00:59:35.605402 [ANA_INIT] flow start
2260 00:59:35.608323 [ANA_INIT] PLL >>>>>>>>
2261 00:59:35.608404 [ANA_INIT] PLL <<<<<<<<
2262 00:59:35.611795 [ANA_INIT] MIDPI >>>>>>>>
2263 00:59:35.615553 [ANA_INIT] MIDPI <<<<<<<<
2264 00:59:35.618068 [ANA_INIT] DLL >>>>>>>>
2265 00:59:35.618149 [ANA_INIT] DLL <<<<<<<<
2266 00:59:35.622067 [ANA_INIT] flow end
2267 00:59:35.624842 ============ LP4 DIFF to SE enter ============
2268 00:59:35.628671 ============ LP4 DIFF to SE exit ============
2269 00:59:35.631581 [ANA_INIT] <<<<<<<<<<<<<
2270 00:59:35.635088 [Flow] Enable top DCM control >>>>>
2271 00:59:35.638350 [Flow] Enable top DCM control <<<<<
2272 00:59:35.641846 Enable DLL master slave shuffle
2273 00:59:35.648102 ==============================================================
2274 00:59:35.648242 Gating Mode config
2275 00:59:35.655527 ==============================================================
2276 00:59:35.655615 Config description:
2277 00:59:35.665329 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2278 00:59:35.671628 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2279 00:59:35.677901 SELPH_MODE 0: By rank 1: By Phase
2280 00:59:35.681124 ==============================================================
2281 00:59:35.684527 GAT_TRACK_EN = 1
2282 00:59:35.688428 RX_GATING_MODE = 2
2283 00:59:35.691220 RX_GATING_TRACK_MODE = 2
2284 00:59:35.694722 SELPH_MODE = 1
2285 00:59:35.697756 PICG_EARLY_EN = 1
2286 00:59:35.700925 VALID_LAT_VALUE = 1
2287 00:59:35.704553 ==============================================================
2288 00:59:35.707889 Enter into Gating configuration >>>>
2289 00:59:35.711313 Exit from Gating configuration <<<<
2290 00:59:35.714706 Enter into DVFS_PRE_config >>>>>
2291 00:59:35.727558 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2292 00:59:35.730798 Exit from DVFS_PRE_config <<<<<
2293 00:59:35.733938 Enter into PICG configuration >>>>
2294 00:59:35.737578 Exit from PICG configuration <<<<
2295 00:59:35.737659 [RX_INPUT] configuration >>>>>
2296 00:59:35.741149 [RX_INPUT] configuration <<<<<
2297 00:59:35.747279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2298 00:59:35.750621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2299 00:59:35.757063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 00:59:35.763593 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 00:59:35.770262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 00:59:35.777824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 00:59:35.780541 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2304 00:59:35.783802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2305 00:59:35.790604 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2306 00:59:35.793730 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2307 00:59:35.796829 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2308 00:59:35.801166 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 00:59:35.804257 ===================================
2310 00:59:35.807031 LPDDR4 DRAM CONFIGURATION
2311 00:59:35.810190 ===================================
2312 00:59:35.814266 EX_ROW_EN[0] = 0x0
2313 00:59:35.814348 EX_ROW_EN[1] = 0x0
2314 00:59:35.817588 LP4Y_EN = 0x0
2315 00:59:35.817669 WORK_FSP = 0x0
2316 00:59:35.820770 WL = 0x4
2317 00:59:35.820932 RL = 0x4
2318 00:59:35.823910 BL = 0x2
2319 00:59:35.824079 RPST = 0x0
2320 00:59:35.826801 RD_PRE = 0x0
2321 00:59:35.826899 WR_PRE = 0x1
2322 00:59:35.830303 WR_PST = 0x0
2323 00:59:35.833440 DBI_WR = 0x0
2324 00:59:35.833521 DBI_RD = 0x0
2325 00:59:35.836654 OTF = 0x1
2326 00:59:35.840121 ===================================
2327 00:59:35.843868 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2328 00:59:35.846969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2329 00:59:35.850192 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 00:59:35.853497 ===================================
2331 00:59:35.856500 LPDDR4 DRAM CONFIGURATION
2332 00:59:35.859919 ===================================
2333 00:59:35.863337 EX_ROW_EN[0] = 0x10
2334 00:59:35.863418 EX_ROW_EN[1] = 0x0
2335 00:59:35.866643 LP4Y_EN = 0x0
2336 00:59:35.866724 WORK_FSP = 0x0
2337 00:59:35.870226 WL = 0x4
2338 00:59:35.870306 RL = 0x4
2339 00:59:35.873639 BL = 0x2
2340 00:59:35.873719 RPST = 0x0
2341 00:59:35.876460 RD_PRE = 0x0
2342 00:59:35.876540 WR_PRE = 0x1
2343 00:59:35.879519 WR_PST = 0x0
2344 00:59:35.883182 DBI_WR = 0x0
2345 00:59:35.883262 DBI_RD = 0x0
2346 00:59:35.886282 OTF = 0x1
2347 00:59:35.889880 ===================================
2348 00:59:35.892948 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2349 00:59:35.893055 ==
2350 00:59:35.896361 Dram Type= 6, Freq= 0, CH_0, rank 0
2351 00:59:35.902847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2352 00:59:35.902929 ==
2353 00:59:35.905969 [Duty_Offset_Calibration]
2354 00:59:35.906049 B0:1 B1:-1 CA:0
2355 00:59:35.906113
2356 00:59:35.909321 [DutyScan_Calibration_Flow] k_type=0
2357 00:59:35.918857
2358 00:59:35.919036 ==CLK 0==
2359 00:59:35.922868 Final CLK duty delay cell = 0
2360 00:59:35.926055 [0] MAX Duty = 5125%(X100), DQS PI = 24
2361 00:59:35.929055 [0] MIN Duty = 4875%(X100), DQS PI = 8
2362 00:59:35.929137 [0] AVG Duty = 5000%(X100)
2363 00:59:35.932281
2364 00:59:35.935358 CH0 CLK Duty spec in!! Max-Min= 250%
2365 00:59:35.939229 [DutyScan_Calibration_Flow] ====Done====
2366 00:59:35.939311
2367 00:59:35.942063 [DutyScan_Calibration_Flow] k_type=1
2368 00:59:35.958035
2369 00:59:35.958119 ==DQS 0 ==
2370 00:59:35.961706 Final DQS duty delay cell = -4
2371 00:59:35.963996 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2372 00:59:35.967278 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2373 00:59:35.970983 [-4] AVG Duty = 4968%(X100)
2374 00:59:35.971064
2375 00:59:35.971127 ==DQS 1 ==
2376 00:59:35.973778 Final DQS duty delay cell = 0
2377 00:59:35.977842 [0] MAX Duty = 5124%(X100), DQS PI = 4
2378 00:59:35.980695 [0] MIN Duty = 5000%(X100), DQS PI = 22
2379 00:59:35.984235 [0] AVG Duty = 5062%(X100)
2380 00:59:35.984315
2381 00:59:35.987460 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2382 00:59:35.987540
2383 00:59:35.990610 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2384 00:59:35.994168 [DutyScan_Calibration_Flow] ====Done====
2385 00:59:35.994248
2386 00:59:35.997709 [DutyScan_Calibration_Flow] k_type=3
2387 00:59:36.015207
2388 00:59:36.015286 ==DQM 0 ==
2389 00:59:36.018585 Final DQM duty delay cell = 0
2390 00:59:36.021654 [0] MAX Duty = 5031%(X100), DQS PI = 16
2391 00:59:36.025326 [0] MIN Duty = 4875%(X100), DQS PI = 6
2392 00:59:36.025428 [0] AVG Duty = 4953%(X100)
2393 00:59:36.028338
2394 00:59:36.028417 ==DQM 1 ==
2395 00:59:36.031627 Final DQM duty delay cell = 4
2396 00:59:36.035315 [4] MAX Duty = 5187%(X100), DQS PI = 16
2397 00:59:36.039174 [4] MIN Duty = 5000%(X100), DQS PI = 24
2398 00:59:36.041486 [4] AVG Duty = 5093%(X100)
2399 00:59:36.041565
2400 00:59:36.044784 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2401 00:59:36.044864
2402 00:59:36.048261 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2403 00:59:36.052301 [DutyScan_Calibration_Flow] ====Done====
2404 00:59:36.052380
2405 00:59:36.054591 [DutyScan_Calibration_Flow] k_type=2
2406 00:59:36.071014
2407 00:59:36.071096 ==DQ 0 ==
2408 00:59:36.074551 Final DQ duty delay cell = -4
2409 00:59:36.077924 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2410 00:59:36.080584 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2411 00:59:36.084256 [-4] AVG Duty = 4969%(X100)
2412 00:59:36.084350
2413 00:59:36.084414 ==DQ 1 ==
2414 00:59:36.087518 Final DQ duty delay cell = 0
2415 00:59:36.090840 [0] MAX Duty = 5094%(X100), DQS PI = 50
2416 00:59:36.094279 [0] MIN Duty = 4969%(X100), DQS PI = 40
2417 00:59:36.097182 [0] AVG Duty = 5031%(X100)
2418 00:59:36.097262
2419 00:59:36.100467 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2420 00:59:36.100547
2421 00:59:36.103992 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2422 00:59:36.107189 [DutyScan_Calibration_Flow] ====Done====
2423 00:59:36.107269 ==
2424 00:59:36.110383 Dram Type= 6, Freq= 0, CH_1, rank 0
2425 00:59:36.113558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2426 00:59:36.113651 ==
2427 00:59:36.117667 [Duty_Offset_Calibration]
2428 00:59:36.117749 B0:-1 B1:1 CA:1
2429 00:59:36.117814
2430 00:59:36.121494 [DutyScan_Calibration_Flow] k_type=0
2431 00:59:36.131312
2432 00:59:36.131493 ==CLK 0==
2433 00:59:36.134498 Final CLK duty delay cell = 0
2434 00:59:36.138329 [0] MAX Duty = 5156%(X100), DQS PI = 4
2435 00:59:36.141431 [0] MIN Duty = 5000%(X100), DQS PI = 28
2436 00:59:36.141600 [0] AVG Duty = 5078%(X100)
2437 00:59:36.144543
2438 00:59:36.148030 CH1 CLK Duty spec in!! Max-Min= 156%
2439 00:59:36.151020 [DutyScan_Calibration_Flow] ====Done====
2440 00:59:36.151172
2441 00:59:36.154762 [DutyScan_Calibration_Flow] k_type=1
2442 00:59:36.171234
2443 00:59:36.171535 ==DQS 0 ==
2444 00:59:36.174471 Final DQS duty delay cell = 0
2445 00:59:36.177452 [0] MAX Duty = 5156%(X100), DQS PI = 16
2446 00:59:36.180891 [0] MIN Duty = 4907%(X100), DQS PI = 38
2447 00:59:36.184185 [0] AVG Duty = 5031%(X100)
2448 00:59:36.184642
2449 00:59:36.185059 ==DQS 1 ==
2450 00:59:36.187274 Final DQS duty delay cell = 0
2451 00:59:36.190806 [0] MAX Duty = 5094%(X100), DQS PI = 44
2452 00:59:36.193955 [0] MIN Duty = 4969%(X100), DQS PI = 26
2453 00:59:36.197258 [0] AVG Duty = 5031%(X100)
2454 00:59:36.197685
2455 00:59:36.200724 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2456 00:59:36.201150
2457 00:59:36.204073 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2458 00:59:36.207541 [DutyScan_Calibration_Flow] ====Done====
2459 00:59:36.208074
2460 00:59:36.210762 [DutyScan_Calibration_Flow] k_type=3
2461 00:59:36.227373
2462 00:59:36.227839 ==DQM 0 ==
2463 00:59:36.230315 Final DQM duty delay cell = -4
2464 00:59:36.233431 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2465 00:59:36.236668 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2466 00:59:36.240097 [-4] AVG Duty = 4953%(X100)
2467 00:59:36.240535
2468 00:59:36.240868 ==DQM 1 ==
2469 00:59:36.242990 Final DQM duty delay cell = 0
2470 00:59:36.246781 [0] MAX Duty = 5187%(X100), DQS PI = 36
2471 00:59:36.250404 [0] MIN Duty = 4969%(X100), DQS PI = 2
2472 00:59:36.253443 [0] AVG Duty = 5078%(X100)
2473 00:59:36.253985
2474 00:59:36.256568 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2475 00:59:36.256992
2476 00:59:36.259929 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2477 00:59:36.262967 [DutyScan_Calibration_Flow] ====Done====
2478 00:59:36.263394
2479 00:59:36.266407 [DutyScan_Calibration_Flow] k_type=2
2480 00:59:36.283123
2481 00:59:36.283617 ==DQ 0 ==
2482 00:59:36.287425 Final DQ duty delay cell = 0
2483 00:59:36.290230 [0] MAX Duty = 5156%(X100), DQS PI = 0
2484 00:59:36.293302 [0] MIN Duty = 4907%(X100), DQS PI = 38
2485 00:59:36.293730 [0] AVG Duty = 5031%(X100)
2486 00:59:36.294069
2487 00:59:36.296790 ==DQ 1 ==
2488 00:59:36.299956 Final DQ duty delay cell = 0
2489 00:59:36.303321 [0] MAX Duty = 5124%(X100), DQS PI = 42
2490 00:59:36.306923 [0] MIN Duty = 4969%(X100), DQS PI = 28
2491 00:59:36.307453 [0] AVG Duty = 5046%(X100)
2492 00:59:36.307862
2493 00:59:36.311076 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2494 00:59:36.314452
2495 00:59:36.316726 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2496 00:59:36.320520 [DutyScan_Calibration_Flow] ====Done====
2497 00:59:36.323352 nWR fixed to 30
2498 00:59:36.323878 [ModeRegInit_LP4] CH0 RK0
2499 00:59:36.326542 [ModeRegInit_LP4] CH0 RK1
2500 00:59:36.329991 [ModeRegInit_LP4] CH1 RK0
2501 00:59:36.333600 [ModeRegInit_LP4] CH1 RK1
2502 00:59:36.334147 match AC timing 7
2503 00:59:36.336865 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2504 00:59:36.343364 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2505 00:59:36.346675 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2506 00:59:36.353510 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2507 00:59:36.356374 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2508 00:59:36.356844 ==
2509 00:59:36.360224 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 00:59:36.363461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 00:59:36.364045 ==
2512 00:59:36.369336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2513 00:59:36.376387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2514 00:59:36.383426 [CA 0] Center 39 (9~70) winsize 62
2515 00:59:36.386443 [CA 1] Center 39 (9~70) winsize 62
2516 00:59:36.389910 [CA 2] Center 35 (5~66) winsize 62
2517 00:59:36.393914 [CA 3] Center 35 (5~65) winsize 61
2518 00:59:36.396698 [CA 4] Center 34 (4~64) winsize 61
2519 00:59:36.399627 [CA 5] Center 33 (3~63) winsize 61
2520 00:59:36.400134
2521 00:59:36.403395 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2522 00:59:36.404015
2523 00:59:36.406847 [CATrainingPosCal] consider 1 rank data
2524 00:59:36.409776 u2DelayCellTimex100 = 270/100 ps
2525 00:59:36.413051 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2526 00:59:36.420515 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2527 00:59:36.422974 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2528 00:59:36.426445 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2529 00:59:36.429656 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2530 00:59:36.433533 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2531 00:59:36.434106
2532 00:59:36.436027 CA PerBit enable=1, Macro0, CA PI delay=33
2533 00:59:36.436496
2534 00:59:36.439785 [CBTSetCACLKResult] CA Dly = 33
2535 00:59:36.440459 CS Dly: 8 (0~39)
2536 00:59:36.442629 ==
2537 00:59:36.446575 Dram Type= 6, Freq= 0, CH_0, rank 1
2538 00:59:36.449484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 00:59:36.449950 ==
2540 00:59:36.452742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2541 00:59:36.459424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2542 00:59:36.469053 [CA 0] Center 39 (8~70) winsize 63
2543 00:59:36.472688 [CA 1] Center 39 (9~70) winsize 62
2544 00:59:36.476003 [CA 2] Center 35 (5~66) winsize 62
2545 00:59:36.478998 [CA 3] Center 34 (4~65) winsize 62
2546 00:59:36.482656 [CA 4] Center 33 (3~64) winsize 62
2547 00:59:36.485785 [CA 5] Center 33 (3~63) winsize 61
2548 00:59:36.486206
2549 00:59:36.489106 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2550 00:59:36.489527
2551 00:59:36.492247 [CATrainingPosCal] consider 2 rank data
2552 00:59:36.495422 u2DelayCellTimex100 = 270/100 ps
2553 00:59:36.498580 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2554 00:59:36.505609 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2555 00:59:36.509210 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 00:59:36.512360 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2557 00:59:36.515501 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2558 00:59:36.518773 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2559 00:59:36.519264
2560 00:59:36.521760 CA PerBit enable=1, Macro0, CA PI delay=33
2561 00:59:36.522412
2562 00:59:36.525383 [CBTSetCACLKResult] CA Dly = 33
2563 00:59:36.525844 CS Dly: 8 (0~40)
2564 00:59:36.528650
2565 00:59:36.531750 ----->DramcWriteLeveling(PI) begin...
2566 00:59:36.532177 ==
2567 00:59:36.534977 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 00:59:36.538763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 00:59:36.539233 ==
2570 00:59:36.541797 Write leveling (Byte 0): 33 => 33
2571 00:59:36.545069 Write leveling (Byte 1): 30 => 30
2572 00:59:36.548427 DramcWriteLeveling(PI) end<-----
2573 00:59:36.548843
2574 00:59:36.549169 ==
2575 00:59:36.551922 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 00:59:36.555386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 00:59:36.555848 ==
2578 00:59:36.558792 [Gating] SW mode calibration
2579 00:59:36.566624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2580 00:59:36.572258 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2581 00:59:36.575974 0 15 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2582 00:59:36.578542 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2583 00:59:36.585615 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 00:59:36.588467 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 00:59:36.591783 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 00:59:36.598362 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 00:59:36.602795 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2588 00:59:36.605415 0 15 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
2589 00:59:36.611796 1 0 0 | B1->B0 | 3131 2323 | 1 0 | (0 1) (0 0)
2590 00:59:36.614756 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2591 00:59:36.618293 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 00:59:36.621912 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 00:59:36.628400 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 00:59:36.631539 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 00:59:36.634665 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 00:59:36.641436 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
2597 00:59:36.645054 1 1 0 | B1->B0 | 2525 4342 | 0 1 | (0 0) (0 0)
2598 00:59:36.647751 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2599 00:59:36.655316 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 00:59:36.657933 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 00:59:36.661624 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 00:59:36.668569 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 00:59:36.671042 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 00:59:36.674242 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2605 00:59:36.680607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2606 00:59:36.684152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 00:59:36.687255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 00:59:36.694041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 00:59:36.698004 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 00:59:36.700846 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 00:59:36.707129 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 00:59:36.710512 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 00:59:36.713794 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 00:59:36.720241 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 00:59:36.724197 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 00:59:36.727274 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 00:59:36.734097 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 00:59:36.736851 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 00:59:36.741012 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 00:59:36.747647 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 00:59:36.750252 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 00:59:36.753694 Total UI for P1: 0, mck2ui 16
2623 00:59:36.756870 best dqsien dly found for B0: ( 1, 3, 28)
2624 00:59:36.760271 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 00:59:36.766938 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 00:59:36.767143 Total UI for P1: 0, mck2ui 16
2627 00:59:36.773454 best dqsien dly found for B1: ( 1, 4, 2)
2628 00:59:36.777046 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2629 00:59:36.780450 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2630 00:59:36.780841
2631 00:59:36.783701 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2632 00:59:36.786705 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2633 00:59:36.790498 [Gating] SW calibration Done
2634 00:59:36.790918 ==
2635 00:59:36.793612 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 00:59:36.798104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 00:59:36.798528 ==
2638 00:59:36.801568 RX Vref Scan: 0
2639 00:59:36.801990
2640 00:59:36.802325 RX Vref 0 -> 0, step: 1
2641 00:59:36.802677
2642 00:59:36.803843 RX Delay -40 -> 252, step: 8
2643 00:59:36.806815 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2644 00:59:36.813408 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2645 00:59:36.816906 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2646 00:59:36.819987 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2647 00:59:36.823846 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2648 00:59:36.826722 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2649 00:59:36.833315 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2650 00:59:36.836772 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2651 00:59:36.839986 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2652 00:59:36.843627 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2653 00:59:36.846686 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2654 00:59:36.854049 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2655 00:59:36.856627 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2656 00:59:36.860765 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2657 00:59:36.863105 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2658 00:59:36.866612 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2659 00:59:36.870022 ==
2660 00:59:36.870440 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 00:59:36.876298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 00:59:36.876725 ==
2663 00:59:36.877065 DQS Delay:
2664 00:59:36.880508 DQS0 = 0, DQS1 = 0
2665 00:59:36.880929 DQM Delay:
2666 00:59:36.883164 DQM0 = 119, DQM1 = 107
2667 00:59:36.883583 DQ Delay:
2668 00:59:36.886527 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2669 00:59:36.889715 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2670 00:59:36.893287 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2671 00:59:36.896427 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2672 00:59:36.896850
2673 00:59:36.897302
2674 00:59:36.897866 ==
2675 00:59:36.900041 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 00:59:36.906303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 00:59:36.906729 ==
2678 00:59:36.907066
2679 00:59:36.907377
2680 00:59:36.907705 TX Vref Scan disable
2681 00:59:36.909897 == TX Byte 0 ==
2682 00:59:36.913013 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2683 00:59:36.920141 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2684 00:59:36.920624 == TX Byte 1 ==
2685 00:59:36.923417 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2686 00:59:36.929971 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2687 00:59:36.930393 ==
2688 00:59:36.933340 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 00:59:36.936631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 00:59:36.937201 ==
2691 00:59:36.947853 TX Vref=22, minBit 6, minWin=25, winSum=421
2692 00:59:36.951199 TX Vref=24, minBit 0, minWin=26, winSum=430
2693 00:59:36.954385 TX Vref=26, minBit 1, minWin=26, winSum=433
2694 00:59:36.957899 TX Vref=28, minBit 4, minWin=26, winSum=438
2695 00:59:36.961126 TX Vref=30, minBit 14, minWin=26, winSum=440
2696 00:59:36.967810 TX Vref=32, minBit 4, minWin=26, winSum=433
2697 00:59:36.970747 [TxChooseVref] Worse bit 14, Min win 26, Win sum 440, Final Vref 30
2698 00:59:36.971168
2699 00:59:36.974245 Final TX Range 1 Vref 30
2700 00:59:36.974664
2701 00:59:36.974993 ==
2702 00:59:36.977635 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 00:59:36.980442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 00:59:36.984173 ==
2705 00:59:36.984596
2706 00:59:36.984929
2707 00:59:36.985238 TX Vref Scan disable
2708 00:59:36.987640 == TX Byte 0 ==
2709 00:59:36.991393 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2710 00:59:36.994261 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2711 00:59:36.997496 == TX Byte 1 ==
2712 00:59:37.001754 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2713 00:59:37.007621 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2714 00:59:37.008101
2715 00:59:37.008439 [DATLAT]
2716 00:59:37.008754 Freq=1200, CH0 RK0
2717 00:59:37.009060
2718 00:59:37.010844 DATLAT Default: 0xd
2719 00:59:37.011322 0, 0xFFFF, sum = 0
2720 00:59:37.014073 1, 0xFFFF, sum = 0
2721 00:59:37.017244 2, 0xFFFF, sum = 0
2722 00:59:37.017671 3, 0xFFFF, sum = 0
2723 00:59:37.020638 4, 0xFFFF, sum = 0
2724 00:59:37.021068 5, 0xFFFF, sum = 0
2725 00:59:37.024349 6, 0xFFFF, sum = 0
2726 00:59:37.024779 7, 0xFFFF, sum = 0
2727 00:59:37.027254 8, 0xFFFF, sum = 0
2728 00:59:37.027735 9, 0xFFFF, sum = 0
2729 00:59:37.030825 10, 0xFFFF, sum = 0
2730 00:59:37.031248 11, 0xFFFF, sum = 0
2731 00:59:37.034094 12, 0x0, sum = 1
2732 00:59:37.034521 13, 0x0, sum = 2
2733 00:59:37.037576 14, 0x0, sum = 3
2734 00:59:37.037998 15, 0x0, sum = 4
2735 00:59:37.040554 best_step = 13
2736 00:59:37.040978
2737 00:59:37.041314 ==
2738 00:59:37.043630 Dram Type= 6, Freq= 0, CH_0, rank 0
2739 00:59:37.047409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2740 00:59:37.047874 ==
2741 00:59:37.048219 RX Vref Scan: 1
2742 00:59:37.050664
2743 00:59:37.051087 Set Vref Range= 32 -> 127
2744 00:59:37.051422
2745 00:59:37.054105 RX Vref 32 -> 127, step: 1
2746 00:59:37.054529
2747 00:59:37.057209 RX Delay -21 -> 252, step: 4
2748 00:59:37.057631
2749 00:59:37.061037 Set Vref, RX VrefLevel [Byte0]: 32
2750 00:59:37.064212 [Byte1]: 32
2751 00:59:37.064635
2752 00:59:37.066835 Set Vref, RX VrefLevel [Byte0]: 33
2753 00:59:37.070322 [Byte1]: 33
2754 00:59:37.073806
2755 00:59:37.074228 Set Vref, RX VrefLevel [Byte0]: 34
2756 00:59:37.077514 [Byte1]: 34
2757 00:59:37.082240
2758 00:59:37.082662 Set Vref, RX VrefLevel [Byte0]: 35
2759 00:59:37.085454 [Byte1]: 35
2760 00:59:37.089956
2761 00:59:37.090377 Set Vref, RX VrefLevel [Byte0]: 36
2762 00:59:37.093201 [Byte1]: 36
2763 00:59:37.097561
2764 00:59:37.098102 Set Vref, RX VrefLevel [Byte0]: 37
2765 00:59:37.101378 [Byte1]: 37
2766 00:59:37.105736
2767 00:59:37.106236 Set Vref, RX VrefLevel [Byte0]: 38
2768 00:59:37.108938 [Byte1]: 38
2769 00:59:37.113642
2770 00:59:37.114061 Set Vref, RX VrefLevel [Byte0]: 39
2771 00:59:37.116980 [Byte1]: 39
2772 00:59:37.121988
2773 00:59:37.122640 Set Vref, RX VrefLevel [Byte0]: 40
2774 00:59:37.124978 [Byte1]: 40
2775 00:59:37.129525
2776 00:59:37.129607 Set Vref, RX VrefLevel [Byte0]: 41
2777 00:59:37.132875 [Byte1]: 41
2778 00:59:37.137131
2779 00:59:37.137213 Set Vref, RX VrefLevel [Byte0]: 42
2780 00:59:37.141482 [Byte1]: 42
2781 00:59:37.145572
2782 00:59:37.145994 Set Vref, RX VrefLevel [Byte0]: 43
2783 00:59:37.148955 [Byte1]: 43
2784 00:59:37.153591
2785 00:59:37.154042 Set Vref, RX VrefLevel [Byte0]: 44
2786 00:59:37.156602 [Byte1]: 44
2787 00:59:37.161418
2788 00:59:37.161943 Set Vref, RX VrefLevel [Byte0]: 45
2789 00:59:37.164874 [Byte1]: 45
2790 00:59:37.169519
2791 00:59:37.170030 Set Vref, RX VrefLevel [Byte0]: 46
2792 00:59:37.172966 [Byte1]: 46
2793 00:59:37.178235
2794 00:59:37.178750 Set Vref, RX VrefLevel [Byte0]: 47
2795 00:59:37.180665 [Byte1]: 47
2796 00:59:37.184970
2797 00:59:37.185624 Set Vref, RX VrefLevel [Byte0]: 48
2798 00:59:37.188605 [Byte1]: 48
2799 00:59:37.193504
2800 00:59:37.193920 Set Vref, RX VrefLevel [Byte0]: 49
2801 00:59:37.196525 [Byte1]: 49
2802 00:59:37.201266
2803 00:59:37.201761 Set Vref, RX VrefLevel [Byte0]: 50
2804 00:59:37.204368 [Byte1]: 50
2805 00:59:37.209024
2806 00:59:37.209517 Set Vref, RX VrefLevel [Byte0]: 51
2807 00:59:37.211950 [Byte1]: 51
2808 00:59:37.217034
2809 00:59:37.217627 Set Vref, RX VrefLevel [Byte0]: 52
2810 00:59:37.220369 [Byte1]: 52
2811 00:59:37.224639
2812 00:59:37.225320 Set Vref, RX VrefLevel [Byte0]: 53
2813 00:59:37.228642 [Byte1]: 53
2814 00:59:37.232648
2815 00:59:37.233196 Set Vref, RX VrefLevel [Byte0]: 54
2816 00:59:37.236151 [Byte1]: 54
2817 00:59:37.240285
2818 00:59:37.240838 Set Vref, RX VrefLevel [Byte0]: 55
2819 00:59:37.244082 [Byte1]: 55
2820 00:59:37.249035
2821 00:59:37.249453 Set Vref, RX VrefLevel [Byte0]: 56
2822 00:59:37.251641 [Byte1]: 56
2823 00:59:37.256312
2824 00:59:37.256728 Set Vref, RX VrefLevel [Byte0]: 57
2825 00:59:37.260050 [Byte1]: 57
2826 00:59:37.264566
2827 00:59:37.265122 Set Vref, RX VrefLevel [Byte0]: 58
2828 00:59:37.267836 [Byte1]: 58
2829 00:59:37.272448
2830 00:59:37.273013 Set Vref, RX VrefLevel [Byte0]: 59
2831 00:59:37.276483 [Byte1]: 59
2832 00:59:37.280388
2833 00:59:37.280949 Set Vref, RX VrefLevel [Byte0]: 60
2834 00:59:37.284009 [Byte1]: 60
2835 00:59:37.289086
2836 00:59:37.289665 Set Vref, RX VrefLevel [Byte0]: 61
2837 00:59:37.291607 [Byte1]: 61
2838 00:59:37.296215
2839 00:59:37.296773 Set Vref, RX VrefLevel [Byte0]: 62
2840 00:59:37.299296 [Byte1]: 62
2841 00:59:37.304100
2842 00:59:37.307202 Set Vref, RX VrefLevel [Byte0]: 63
2843 00:59:37.310453 [Byte1]: 63
2844 00:59:37.310916
2845 00:59:37.314745 Set Vref, RX VrefLevel [Byte0]: 64
2846 00:59:37.316951 [Byte1]: 64
2847 00:59:37.317412
2848 00:59:37.320347 Set Vref, RX VrefLevel [Byte0]: 65
2849 00:59:37.323499 [Byte1]: 65
2850 00:59:37.327642
2851 00:59:37.328216 Set Vref, RX VrefLevel [Byte0]: 66
2852 00:59:37.331341 [Byte1]: 66
2853 00:59:37.335393
2854 00:59:37.335852 Set Vref, RX VrefLevel [Byte0]: 67
2855 00:59:37.339247 [Byte1]: 67
2856 00:59:37.344133
2857 00:59:37.344550 Set Vref, RX VrefLevel [Byte0]: 68
2858 00:59:37.347635 [Byte1]: 68
2859 00:59:37.351289
2860 00:59:37.351737 Set Vref, RX VrefLevel [Byte0]: 69
2861 00:59:37.354760 [Byte1]: 69
2862 00:59:37.359643
2863 00:59:37.360093 Set Vref, RX VrefLevel [Byte0]: 70
2864 00:59:37.362903 [Byte1]: 70
2865 00:59:37.367334
2866 00:59:37.368023 Set Vref, RX VrefLevel [Byte0]: 71
2867 00:59:37.370527 [Byte1]: 71
2868 00:59:37.375167
2869 00:59:37.375863 Set Vref, RX VrefLevel [Byte0]: 72
2870 00:59:37.378818 [Byte1]: 72
2871 00:59:37.383770
2872 00:59:37.384408 Set Vref, RX VrefLevel [Byte0]: 73
2873 00:59:37.386437 [Byte1]: 73
2874 00:59:37.391154
2875 00:59:37.391574 Set Vref, RX VrefLevel [Byte0]: 74
2876 00:59:37.394316 [Byte1]: 74
2877 00:59:37.399159
2878 00:59:37.399592 Set Vref, RX VrefLevel [Byte0]: 75
2879 00:59:37.405315 [Byte1]: 75
2880 00:59:37.405740
2881 00:59:37.408969 Set Vref, RX VrefLevel [Byte0]: 76
2882 00:59:37.412238 [Byte1]: 76
2883 00:59:37.412662
2884 00:59:37.415728 Set Vref, RX VrefLevel [Byte0]: 77
2885 00:59:37.418444 [Byte1]: 77
2886 00:59:37.423262
2887 00:59:37.423841 Set Vref, RX VrefLevel [Byte0]: 78
2888 00:59:37.426205 [Byte1]: 78
2889 00:59:37.430665
2890 00:59:37.431088 Final RX Vref Byte 0 = 60 to rank0
2891 00:59:37.434841 Final RX Vref Byte 1 = 49 to rank0
2892 00:59:37.437482 Final RX Vref Byte 0 = 60 to rank1
2893 00:59:37.441433 Final RX Vref Byte 1 = 49 to rank1==
2894 00:59:37.443941 Dram Type= 6, Freq= 0, CH_0, rank 0
2895 00:59:37.450788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 00:59:37.451275 ==
2897 00:59:37.451710 DQS Delay:
2898 00:59:37.452101 DQS0 = 0, DQS1 = 0
2899 00:59:37.454264 DQM Delay:
2900 00:59:37.454688 DQM0 = 119, DQM1 = 106
2901 00:59:37.457472 DQ Delay:
2902 00:59:37.461034 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2903 00:59:37.464336 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2904 00:59:37.467556 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2905 00:59:37.470711 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2906 00:59:37.471235
2907 00:59:37.471571
2908 00:59:37.477378 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2909 00:59:37.480678 CH0 RK0: MR19=403, MR18=10FC
2910 00:59:37.487232 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2911 00:59:37.487844
2912 00:59:37.491134 ----->DramcWriteLeveling(PI) begin...
2913 00:59:37.491745 ==
2914 00:59:37.494955 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 00:59:37.497822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 00:59:37.500658 ==
2917 00:59:37.501280 Write leveling (Byte 0): 34 => 34
2918 00:59:37.504188 Write leveling (Byte 1): 30 => 30
2919 00:59:37.507373 DramcWriteLeveling(PI) end<-----
2920 00:59:37.507970
2921 00:59:37.508368 ==
2922 00:59:37.510711 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 00:59:37.517529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 00:59:37.517998 ==
2925 00:59:37.520673 [Gating] SW mode calibration
2926 00:59:37.527483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2927 00:59:37.530792 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2928 00:59:37.537042 0 15 0 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
2929 00:59:37.540565 0 15 4 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
2930 00:59:37.543498 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 00:59:37.551470 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 00:59:37.553560 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 00:59:37.556712 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 00:59:37.563447 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2935 00:59:37.566562 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2936 00:59:37.570339 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2937 00:59:37.577041 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 00:59:37.579858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 00:59:37.583975 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 00:59:37.590285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 00:59:37.593386 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 00:59:37.596955 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 00:59:37.603211 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2944 00:59:37.606859 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2945 00:59:37.610192 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 00:59:37.616681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 00:59:37.620211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 00:59:37.623896 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 00:59:37.627102 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 00:59:37.633255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 00:59:37.637005 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2952 00:59:37.639982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2953 00:59:37.646290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 00:59:37.649590 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 00:59:37.653359 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 00:59:37.659588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 00:59:37.662523 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 00:59:37.666537 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 00:59:37.672514 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 00:59:37.676251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 00:59:37.679447 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 00:59:37.685604 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 00:59:37.689334 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 00:59:37.692361 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 00:59:37.699202 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 00:59:37.702559 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 00:59:37.706426 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2968 00:59:37.712536 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2969 00:59:37.716888 Total UI for P1: 0, mck2ui 16
2970 00:59:37.719395 best dqsien dly found for B0: ( 1, 3, 28)
2971 00:59:37.723364 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 00:59:37.726304 Total UI for P1: 0, mck2ui 16
2973 00:59:37.729417 best dqsien dly found for B1: ( 1, 3, 30)
2974 00:59:37.732390 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2975 00:59:37.736352 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2976 00:59:37.736914
2977 00:59:37.739181 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2978 00:59:37.742632 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2979 00:59:37.745888 [Gating] SW calibration Done
2980 00:59:37.746463 ==
2981 00:59:37.748941 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 00:59:37.753315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 00:59:37.755900 ==
2984 00:59:37.756456 RX Vref Scan: 0
2985 00:59:37.756825
2986 00:59:37.758989 RX Vref 0 -> 0, step: 1
2987 00:59:37.759547
2988 00:59:37.762434 RX Delay -40 -> 252, step: 8
2989 00:59:37.766189 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2990 00:59:37.769207 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2991 00:59:37.772061 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2992 00:59:37.775841 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2993 00:59:37.782636 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2994 00:59:37.785337 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2995 00:59:37.789332 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2996 00:59:37.792622 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2997 00:59:37.795410 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2998 00:59:37.802656 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2999 00:59:37.805166 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3000 00:59:37.808569 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3001 00:59:37.811663 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3002 00:59:37.815085 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3003 00:59:37.821854 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3004 00:59:37.825308 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3005 00:59:37.825929 ==
3006 00:59:37.828881 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 00:59:37.831870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 00:59:37.832631 ==
3009 00:59:37.835074 DQS Delay:
3010 00:59:37.835869 DQS0 = 0, DQS1 = 0
3011 00:59:37.836565 DQM Delay:
3012 00:59:37.838652 DQM0 = 116, DQM1 = 108
3013 00:59:37.839205 DQ Delay:
3014 00:59:37.842246 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3015 00:59:37.844800 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3016 00:59:37.848367 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3017 00:59:37.855058 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
3018 00:59:37.855617
3019 00:59:37.856059
3020 00:59:37.856400 ==
3021 00:59:37.858252 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 00:59:37.861970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 00:59:37.862532 ==
3024 00:59:37.862898
3025 00:59:37.863233
3026 00:59:37.865021 TX Vref Scan disable
3027 00:59:37.865580 == TX Byte 0 ==
3028 00:59:37.872339 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3029 00:59:37.874946 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3030 00:59:37.875607 == TX Byte 1 ==
3031 00:59:37.881183 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3032 00:59:37.884905 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3033 00:59:37.885578 ==
3034 00:59:37.887663 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 00:59:37.891204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 00:59:37.891883 ==
3037 00:59:37.904839 TX Vref=22, minBit 3, minWin=25, winSum=421
3038 00:59:37.907859 TX Vref=24, minBit 1, minWin=26, winSum=428
3039 00:59:37.911384 TX Vref=26, minBit 0, minWin=26, winSum=431
3040 00:59:37.914326 TX Vref=28, minBit 1, minWin=26, winSum=431
3041 00:59:37.917535 TX Vref=30, minBit 1, minWin=26, winSum=433
3042 00:59:37.924176 TX Vref=32, minBit 5, minWin=26, winSum=432
3043 00:59:37.927370 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3044 00:59:37.928013
3045 00:59:37.930779 Final TX Range 1 Vref 30
3046 00:59:37.931334
3047 00:59:37.931928 ==
3048 00:59:37.934066 Dram Type= 6, Freq= 0, CH_0, rank 1
3049 00:59:37.937456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 00:59:37.941298 ==
3051 00:59:37.941892
3052 00:59:37.942449
3053 00:59:37.942967 TX Vref Scan disable
3054 00:59:37.944084 == TX Byte 0 ==
3055 00:59:37.947637 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3056 00:59:37.954321 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3057 00:59:37.954909 == TX Byte 1 ==
3058 00:59:37.957963 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3059 00:59:37.964136 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3060 00:59:37.964563
3061 00:59:37.964897 [DATLAT]
3062 00:59:37.965207 Freq=1200, CH0 RK1
3063 00:59:37.965504
3064 00:59:37.967578 DATLAT Default: 0xd
3065 00:59:37.971280 0, 0xFFFF, sum = 0
3066 00:59:37.971848 1, 0xFFFF, sum = 0
3067 00:59:37.973958 2, 0xFFFF, sum = 0
3068 00:59:37.974382 3, 0xFFFF, sum = 0
3069 00:59:37.977530 4, 0xFFFF, sum = 0
3070 00:59:37.977975 5, 0xFFFF, sum = 0
3071 00:59:37.980775 6, 0xFFFF, sum = 0
3072 00:59:37.981200 7, 0xFFFF, sum = 0
3073 00:59:37.984611 8, 0xFFFF, sum = 0
3074 00:59:37.985174 9, 0xFFFF, sum = 0
3075 00:59:37.987401 10, 0xFFFF, sum = 0
3076 00:59:37.988073 11, 0xFFFF, sum = 0
3077 00:59:37.990587 12, 0x0, sum = 1
3078 00:59:37.991264 13, 0x0, sum = 2
3079 00:59:37.993747 14, 0x0, sum = 3
3080 00:59:37.994171 15, 0x0, sum = 4
3081 00:59:37.997484 best_step = 13
3082 00:59:37.997900
3083 00:59:37.998229 ==
3084 00:59:38.000264 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 00:59:38.003492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 00:59:38.004049 ==
3087 00:59:38.004633 RX Vref Scan: 0
3088 00:59:38.007210
3089 00:59:38.007828 RX Vref 0 -> 0, step: 1
3090 00:59:38.008199
3091 00:59:38.010827 RX Delay -21 -> 252, step: 4
3092 00:59:38.017119 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3093 00:59:38.020493 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3094 00:59:38.023635 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3095 00:59:38.027194 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3096 00:59:38.030545 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3097 00:59:38.036714 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3098 00:59:38.040420 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3099 00:59:38.043260 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3100 00:59:38.046646 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3101 00:59:38.049829 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3102 00:59:38.053528 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3103 00:59:38.060361 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3104 00:59:38.063601 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3105 00:59:38.066651 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3106 00:59:38.070433 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3107 00:59:38.076573 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3108 00:59:38.077078 ==
3109 00:59:38.080312 Dram Type= 6, Freq= 0, CH_0, rank 1
3110 00:59:38.083530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 00:59:38.083993 ==
3112 00:59:38.084333 DQS Delay:
3113 00:59:38.086855 DQS0 = 0, DQS1 = 0
3114 00:59:38.087272 DQM Delay:
3115 00:59:38.090136 DQM0 = 116, DQM1 = 107
3116 00:59:38.090747 DQ Delay:
3117 00:59:38.093367 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3118 00:59:38.097446 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3119 00:59:38.100055 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3120 00:59:38.103035 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3121 00:59:38.103597
3122 00:59:38.104054
3123 00:59:38.113612 [DQSOSCAuto] RK1, (LSB)MR18= 0xee8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 404 ps
3124 00:59:38.116819 CH0 RK1: MR19=403, MR18=EE8
3125 00:59:38.119801 CH0_RK1: MR19=0x403, MR18=0xEE8, DQSOSC=404, MR23=63, INC=40, DEC=26
3126 00:59:38.122991 [RxdqsGatingPostProcess] freq 1200
3127 00:59:38.130580 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3128 00:59:38.133349 best DQS0 dly(2T, 0.5T) = (0, 11)
3129 00:59:38.136930 best DQS1 dly(2T, 0.5T) = (0, 12)
3130 00:59:38.139719 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3131 00:59:38.143340 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3132 00:59:38.146721 best DQS0 dly(2T, 0.5T) = (0, 11)
3133 00:59:38.150357 best DQS1 dly(2T, 0.5T) = (0, 11)
3134 00:59:38.153281 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3135 00:59:38.156565 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3136 00:59:38.156980 Pre-setting of DQS Precalculation
3137 00:59:38.163543 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3138 00:59:38.164186 ==
3139 00:59:38.166575 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 00:59:38.169559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 00:59:38.170206 ==
3142 00:59:38.176325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 00:59:38.182912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3144 00:59:38.190511 [CA 0] Center 37 (7~67) winsize 61
3145 00:59:38.193646 [CA 1] Center 37 (7~68) winsize 62
3146 00:59:38.197918 [CA 2] Center 34 (4~64) winsize 61
3147 00:59:38.200982 [CA 3] Center 33 (3~64) winsize 62
3148 00:59:38.204232 [CA 4] Center 34 (4~64) winsize 61
3149 00:59:38.207403 [CA 5] Center 33 (3~64) winsize 62
3150 00:59:38.207866
3151 00:59:38.210893 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3152 00:59:38.211366
3153 00:59:38.214431 [CATrainingPosCal] consider 1 rank data
3154 00:59:38.217371 u2DelayCellTimex100 = 270/100 ps
3155 00:59:38.220267 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3156 00:59:38.227561 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 00:59:38.230510 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3158 00:59:38.233747 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3159 00:59:38.237494 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 00:59:38.241099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3161 00:59:38.241637
3162 00:59:38.243962 CA PerBit enable=1, Macro0, CA PI delay=33
3163 00:59:38.244425
3164 00:59:38.246759 [CBTSetCACLKResult] CA Dly = 33
3165 00:59:38.247220 CS Dly: 5 (0~36)
3166 00:59:38.249966 ==
3167 00:59:38.253826 Dram Type= 6, Freq= 0, CH_1, rank 1
3168 00:59:38.256852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 00:59:38.257415 ==
3170 00:59:38.259789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3171 00:59:38.267093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3172 00:59:38.276663 [CA 0] Center 37 (7~67) winsize 61
3173 00:59:38.279780 [CA 1] Center 38 (8~68) winsize 61
3174 00:59:38.282825 [CA 2] Center 34 (4~65) winsize 62
3175 00:59:38.285793 [CA 3] Center 33 (3~64) winsize 62
3176 00:59:38.289388 [CA 4] Center 34 (3~65) winsize 63
3177 00:59:38.292811 [CA 5] Center 33 (3~64) winsize 62
3178 00:59:38.293277
3179 00:59:38.296172 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3180 00:59:38.296636
3181 00:59:38.299311 [CATrainingPosCal] consider 2 rank data
3182 00:59:38.302469 u2DelayCellTimex100 = 270/100 ps
3183 00:59:38.306063 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3184 00:59:38.312073 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3185 00:59:38.315888 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3186 00:59:38.319076 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3187 00:59:38.322522 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3188 00:59:38.326224 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3189 00:59:38.326781
3190 00:59:38.329144 CA PerBit enable=1, Macro0, CA PI delay=33
3191 00:59:38.329608
3192 00:59:38.333142 [CBTSetCACLKResult] CA Dly = 33
3193 00:59:38.335578 CS Dly: 7 (0~40)
3194 00:59:38.336088
3195 00:59:38.338758 ----->DramcWriteLeveling(PI) begin...
3196 00:59:38.339229 ==
3197 00:59:38.342444 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 00:59:38.345723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 00:59:38.346190 ==
3200 00:59:38.348876 Write leveling (Byte 0): 24 => 24
3201 00:59:38.352108 Write leveling (Byte 1): 28 => 28
3202 00:59:38.355319 DramcWriteLeveling(PI) end<-----
3203 00:59:38.355770
3204 00:59:38.356103 ==
3205 00:59:38.358756 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 00:59:38.361981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 00:59:38.362404 ==
3208 00:59:38.365423 [Gating] SW mode calibration
3209 00:59:38.371951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3210 00:59:38.378631 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3211 00:59:38.381990 0 15 0 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
3212 00:59:38.385735 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 00:59:38.391786 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 00:59:38.395848 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 00:59:38.398793 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 00:59:38.404778 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 00:59:38.408143 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
3218 00:59:38.412166 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3219 00:59:38.418310 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 00:59:38.421948 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 00:59:38.424639 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 00:59:38.431469 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 00:59:38.434862 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 00:59:38.437838 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3225 00:59:38.444738 1 0 24 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
3226 00:59:38.448329 1 0 28 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3227 00:59:38.451024 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3228 00:59:38.457465 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 00:59:38.460888 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 00:59:38.464429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 00:59:38.470576 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 00:59:38.473962 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 00:59:38.477551 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3234 00:59:38.484034 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3235 00:59:38.487909 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 00:59:38.490356 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 00:59:38.497411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 00:59:38.501368 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 00:59:38.503941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 00:59:38.510829 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 00:59:38.514644 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 00:59:38.517880 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 00:59:38.523923 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 00:59:38.527241 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 00:59:38.530748 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 00:59:38.537100 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 00:59:38.540747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 00:59:38.543464 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 00:59:38.550384 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3250 00:59:38.553481 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3251 00:59:38.557065 Total UI for P1: 0, mck2ui 16
3252 00:59:38.560494 best dqsien dly found for B0: ( 1, 3, 24)
3253 00:59:38.563680 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 00:59:38.566919 Total UI for P1: 0, mck2ui 16
3255 00:59:38.570395 best dqsien dly found for B1: ( 1, 3, 28)
3256 00:59:38.573316 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3257 00:59:38.576936 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3258 00:59:38.577034
3259 00:59:38.579696 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3260 00:59:38.586347 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3261 00:59:38.586438 [Gating] SW calibration Done
3262 00:59:38.586505 ==
3263 00:59:38.589600 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 00:59:38.596318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 00:59:38.596402 ==
3266 00:59:38.596468 RX Vref Scan: 0
3267 00:59:38.596529
3268 00:59:38.599843 RX Vref 0 -> 0, step: 1
3269 00:59:38.599926
3270 00:59:38.603049 RX Delay -40 -> 252, step: 8
3271 00:59:38.606442 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3272 00:59:38.610195 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3273 00:59:38.613601 iDelay=208, Bit 2, Center 115 (48 ~ 183) 136
3274 00:59:38.619802 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3275 00:59:38.623486 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3276 00:59:38.626907 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3277 00:59:38.629776 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3278 00:59:38.633231 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3279 00:59:38.636690 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3280 00:59:38.643234 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3281 00:59:38.646588 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3282 00:59:38.649505 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3283 00:59:38.653328 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3284 00:59:38.659547 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3285 00:59:38.663599 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3286 00:59:38.666465 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3287 00:59:38.666893 ==
3288 00:59:38.669802 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 00:59:38.673230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 00:59:38.673663 ==
3291 00:59:38.676122 DQS Delay:
3292 00:59:38.676550 DQS0 = 0, DQS1 = 0
3293 00:59:38.679262 DQM Delay:
3294 00:59:38.679563 DQM0 = 119, DQM1 = 110
3295 00:59:38.679893 DQ Delay:
3296 00:59:38.685690 DQ0 =123, DQ1 =115, DQ2 =115, DQ3 =115
3297 00:59:38.689522 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3298 00:59:38.693241 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3299 00:59:38.696214 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3300 00:59:38.696366
3301 00:59:38.696484
3302 00:59:38.696594 ==
3303 00:59:38.699064 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 00:59:38.702258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 00:59:38.702390 ==
3306 00:59:38.702494
3307 00:59:38.702589
3308 00:59:38.706168 TX Vref Scan disable
3309 00:59:38.710303 == TX Byte 0 ==
3310 00:59:38.712641 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3311 00:59:38.715611 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3312 00:59:38.719446 == TX Byte 1 ==
3313 00:59:38.722185 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3314 00:59:38.725720 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3315 00:59:38.725807 ==
3316 00:59:38.728727 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 00:59:38.732626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 00:59:38.735810 ==
3319 00:59:38.746010 TX Vref=22, minBit 11, minWin=24, winSum=417
3320 00:59:38.749052 TX Vref=24, minBit 0, minWin=26, winSum=426
3321 00:59:38.752543 TX Vref=26, minBit 3, minWin=26, winSum=434
3322 00:59:38.755718 TX Vref=28, minBit 0, minWin=27, winSum=435
3323 00:59:38.759195 TX Vref=30, minBit 1, minWin=27, winSum=436
3324 00:59:38.766056 TX Vref=32, minBit 3, minWin=26, winSum=429
3325 00:59:38.769331 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 30
3326 00:59:38.769413
3327 00:59:38.772310 Final TX Range 1 Vref 30
3328 00:59:38.772392
3329 00:59:38.772457 ==
3330 00:59:38.775311 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 00:59:38.778963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 00:59:38.782136 ==
3333 00:59:38.782218
3334 00:59:38.782281
3335 00:59:38.782340 TX Vref Scan disable
3336 00:59:38.785815 == TX Byte 0 ==
3337 00:59:38.788656 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3338 00:59:38.795302 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3339 00:59:38.795384 == TX Byte 1 ==
3340 00:59:38.798742 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3341 00:59:38.805243 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3342 00:59:38.805330
3343 00:59:38.805399 [DATLAT]
3344 00:59:38.805462 Freq=1200, CH1 RK0
3345 00:59:38.805529
3346 00:59:38.809072 DATLAT Default: 0xd
3347 00:59:38.809165 0, 0xFFFF, sum = 0
3348 00:59:38.812006 1, 0xFFFF, sum = 0
3349 00:59:38.815344 2, 0xFFFF, sum = 0
3350 00:59:38.815446 3, 0xFFFF, sum = 0
3351 00:59:38.819153 4, 0xFFFF, sum = 0
3352 00:59:38.819342 5, 0xFFFF, sum = 0
3353 00:59:38.822751 6, 0xFFFF, sum = 0
3354 00:59:38.822936 7, 0xFFFF, sum = 0
3355 00:59:38.825266 8, 0xFFFF, sum = 0
3356 00:59:38.825425 9, 0xFFFF, sum = 0
3357 00:59:38.828932 10, 0xFFFF, sum = 0
3358 00:59:38.829147 11, 0xFFFF, sum = 0
3359 00:59:38.832277 12, 0x0, sum = 1
3360 00:59:38.832517 13, 0x0, sum = 2
3361 00:59:38.835193 14, 0x0, sum = 3
3362 00:59:38.835422 15, 0x0, sum = 4
3363 00:59:38.839317 best_step = 13
3364 00:59:38.839573
3365 00:59:38.839760 ==
3366 00:59:38.842116 Dram Type= 6, Freq= 0, CH_1, rank 0
3367 00:59:38.845171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3368 00:59:38.845372 ==
3369 00:59:38.845531 RX Vref Scan: 1
3370 00:59:38.849583
3371 00:59:38.849819 Set Vref Range= 32 -> 127
3372 00:59:38.850008
3373 00:59:38.852126 RX Vref 32 -> 127, step: 1
3374 00:59:38.852363
3375 00:59:38.855823 RX Delay -21 -> 252, step: 4
3376 00:59:38.856116
3377 00:59:38.859217 Set Vref, RX VrefLevel [Byte0]: 32
3378 00:59:38.862605 [Byte1]: 32
3379 00:59:38.863085
3380 00:59:38.865842 Set Vref, RX VrefLevel [Byte0]: 33
3381 00:59:38.868958 [Byte1]: 33
3382 00:59:38.872292
3383 00:59:38.872748 Set Vref, RX VrefLevel [Byte0]: 34
3384 00:59:38.876820 [Byte1]: 34
3385 00:59:38.880804
3386 00:59:38.881402 Set Vref, RX VrefLevel [Byte0]: 35
3387 00:59:38.883865 [Byte1]: 35
3388 00:59:38.888263
3389 00:59:38.888721 Set Vref, RX VrefLevel [Byte0]: 36
3390 00:59:38.891410 [Byte1]: 36
3391 00:59:38.896248
3392 00:59:38.896801 Set Vref, RX VrefLevel [Byte0]: 37
3393 00:59:38.899244 [Byte1]: 37
3394 00:59:38.903964
3395 00:59:38.904422 Set Vref, RX VrefLevel [Byte0]: 38
3396 00:59:38.907409 [Byte1]: 38
3397 00:59:38.912269
3398 00:59:38.912739 Set Vref, RX VrefLevel [Byte0]: 39
3399 00:59:38.915118 [Byte1]: 39
3400 00:59:38.919945
3401 00:59:38.920358 Set Vref, RX VrefLevel [Byte0]: 40
3402 00:59:38.923325 [Byte1]: 40
3403 00:59:38.927605
3404 00:59:38.928062 Set Vref, RX VrefLevel [Byte0]: 41
3405 00:59:38.930967 [Byte1]: 41
3406 00:59:38.936450
3407 00:59:38.936866 Set Vref, RX VrefLevel [Byte0]: 42
3408 00:59:38.939192 [Byte1]: 42
3409 00:59:38.944120
3410 00:59:38.944535 Set Vref, RX VrefLevel [Byte0]: 43
3411 00:59:38.946855 [Byte1]: 43
3412 00:59:38.951829
3413 00:59:38.952247 Set Vref, RX VrefLevel [Byte0]: 44
3414 00:59:38.958245 [Byte1]: 44
3415 00:59:38.958666
3416 00:59:38.961089 Set Vref, RX VrefLevel [Byte0]: 45
3417 00:59:38.964463 [Byte1]: 45
3418 00:59:38.964883
3419 00:59:38.967960 Set Vref, RX VrefLevel [Byte0]: 46
3420 00:59:38.970895 [Byte1]: 46
3421 00:59:38.975377
3422 00:59:38.975843 Set Vref, RX VrefLevel [Byte0]: 47
3423 00:59:38.979073 [Byte1]: 47
3424 00:59:38.983387
3425 00:59:38.983830 Set Vref, RX VrefLevel [Byte0]: 48
3426 00:59:38.987151 [Byte1]: 48
3427 00:59:38.991106
3428 00:59:38.991523 Set Vref, RX VrefLevel [Byte0]: 49
3429 00:59:38.994168 [Byte1]: 49
3430 00:59:38.999027
3431 00:59:38.999444 Set Vref, RX VrefLevel [Byte0]: 50
3432 00:59:39.002092 [Byte1]: 50
3433 00:59:39.007116
3434 00:59:39.007532 Set Vref, RX VrefLevel [Byte0]: 51
3435 00:59:39.010132 [Byte1]: 51
3436 00:59:39.015578
3437 00:59:39.016041 Set Vref, RX VrefLevel [Byte0]: 52
3438 00:59:39.017990 [Byte1]: 52
3439 00:59:39.022781
3440 00:59:39.022862 Set Vref, RX VrefLevel [Byte0]: 53
3441 00:59:39.025885 [Byte1]: 53
3442 00:59:39.030347
3443 00:59:39.030428 Set Vref, RX VrefLevel [Byte0]: 54
3444 00:59:39.033803 [Byte1]: 54
3445 00:59:39.038728
3446 00:59:39.038810 Set Vref, RX VrefLevel [Byte0]: 55
3447 00:59:39.041614 [Byte1]: 55
3448 00:59:39.046641
3449 00:59:39.046721 Set Vref, RX VrefLevel [Byte0]: 56
3450 00:59:39.049366 [Byte1]: 56
3451 00:59:39.053802
3452 00:59:39.053884 Set Vref, RX VrefLevel [Byte0]: 57
3453 00:59:39.057674 [Byte1]: 57
3454 00:59:39.061922
3455 00:59:39.062003 Set Vref, RX VrefLevel [Byte0]: 58
3456 00:59:39.065097 [Byte1]: 58
3457 00:59:39.069872
3458 00:59:39.069953 Set Vref, RX VrefLevel [Byte0]: 59
3459 00:59:39.073063 [Byte1]: 59
3460 00:59:39.077650
3461 00:59:39.077731 Set Vref, RX VrefLevel [Byte0]: 60
3462 00:59:39.081558 [Byte1]: 60
3463 00:59:39.086088
3464 00:59:39.086169 Set Vref, RX VrefLevel [Byte0]: 61
3465 00:59:39.089127 [Byte1]: 61
3466 00:59:39.093991
3467 00:59:39.094071 Set Vref, RX VrefLevel [Byte0]: 62
3468 00:59:39.096955 [Byte1]: 62
3469 00:59:39.101618
3470 00:59:39.101698 Set Vref, RX VrefLevel [Byte0]: 63
3471 00:59:39.105478 [Byte1]: 63
3472 00:59:39.110293
3473 00:59:39.110376 Set Vref, RX VrefLevel [Byte0]: 64
3474 00:59:39.112863 [Byte1]: 64
3475 00:59:39.117531
3476 00:59:39.117612 Set Vref, RX VrefLevel [Byte0]: 65
3477 00:59:39.121011 [Byte1]: 65
3478 00:59:39.125970
3479 00:59:39.126051 Set Vref, RX VrefLevel [Byte0]: 66
3480 00:59:39.129343 [Byte1]: 66
3481 00:59:39.133384
3482 00:59:39.133492 Set Vref, RX VrefLevel [Byte0]: 67
3483 00:59:39.137571 [Byte1]: 67
3484 00:59:39.141540
3485 00:59:39.141647 Set Vref, RX VrefLevel [Byte0]: 68
3486 00:59:39.144219 [Byte1]: 68
3487 00:59:39.148987
3488 00:59:39.149067 Final RX Vref Byte 0 = 50 to rank0
3489 00:59:39.152551 Final RX Vref Byte 1 = 54 to rank0
3490 00:59:39.155313 Final RX Vref Byte 0 = 50 to rank1
3491 00:59:39.158565 Final RX Vref Byte 1 = 54 to rank1==
3492 00:59:39.162173 Dram Type= 6, Freq= 0, CH_1, rank 0
3493 00:59:39.169012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 00:59:39.169098 ==
3495 00:59:39.169162 DQS Delay:
3496 00:59:39.171740 DQS0 = 0, DQS1 = 0
3497 00:59:39.171821 DQM Delay:
3498 00:59:39.175428 DQM0 = 117, DQM1 = 111
3499 00:59:39.175509 DQ Delay:
3500 00:59:39.178614 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =112
3501 00:59:39.181730 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3502 00:59:39.184973 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =100
3503 00:59:39.188243 DQ12 =118, DQ13 =120, DQ14 =122, DQ15 =120
3504 00:59:39.188325
3505 00:59:39.188389
3506 00:59:39.198944 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3507 00:59:39.199027 CH1 RK0: MR19=403, MR18=3F6
3508 00:59:39.205335 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3509 00:59:39.205418
3510 00:59:39.208439 ----->DramcWriteLeveling(PI) begin...
3511 00:59:39.208548 ==
3512 00:59:39.211798 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 00:59:39.218504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 00:59:39.218592 ==
3515 00:59:39.221545 Write leveling (Byte 0): 24 => 24
3516 00:59:39.224785 Write leveling (Byte 1): 28 => 28
3517 00:59:39.224886 DramcWriteLeveling(PI) end<-----
3518 00:59:39.228364
3519 00:59:39.228468 ==
3520 00:59:39.231827 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 00:59:39.235804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 00:59:39.235927 ==
3523 00:59:39.238255 [Gating] SW mode calibration
3524 00:59:39.244495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3525 00:59:39.248273 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3526 00:59:39.254580 0 15 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3527 00:59:39.257805 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 00:59:39.261185 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 00:59:39.268334 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 00:59:39.271133 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 00:59:39.274467 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 00:59:39.281911 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
3533 00:59:39.284334 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3534 00:59:39.287863 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 00:59:39.294427 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 00:59:39.298100 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 00:59:39.301202 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 00:59:39.307172 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 00:59:39.310646 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 00:59:39.314322 1 0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
3541 00:59:39.320269 1 0 28 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
3542 00:59:39.323753 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 00:59:39.327345 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 00:59:39.333619 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 00:59:39.337639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 00:59:39.340339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 00:59:39.346617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 00:59:39.350491 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3549 00:59:39.353541 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3550 00:59:39.360304 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 00:59:39.363462 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 00:59:39.366673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 00:59:39.373419 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 00:59:39.376737 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 00:59:39.380050 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 00:59:39.386159 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 00:59:39.389730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 00:59:39.393250 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 00:59:39.400138 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 00:59:39.403551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 00:59:39.406441 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 00:59:39.412625 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 00:59:39.416212 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 00:59:39.419668 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3565 00:59:39.426238 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3566 00:59:39.429315 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 00:59:39.432725 Total UI for P1: 0, mck2ui 16
3568 00:59:39.435931 best dqsien dly found for B0: ( 1, 3, 26)
3569 00:59:39.439377 Total UI for P1: 0, mck2ui 16
3570 00:59:39.442718 best dqsien dly found for B1: ( 1, 3, 26)
3571 00:59:39.446212 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3572 00:59:39.448913 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3573 00:59:39.448987
3574 00:59:39.452795 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3575 00:59:39.455426 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3576 00:59:39.459114 [Gating] SW calibration Done
3577 00:59:39.459191 ==
3578 00:59:39.462316 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 00:59:39.468690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 00:59:39.468790 ==
3581 00:59:39.468881 RX Vref Scan: 0
3582 00:59:39.468971
3583 00:59:39.472040 RX Vref 0 -> 0, step: 1
3584 00:59:39.472121
3585 00:59:39.475880 RX Delay -40 -> 252, step: 8
3586 00:59:39.478601 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3587 00:59:39.482507 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3588 00:59:39.485071 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3589 00:59:39.491830 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3590 00:59:39.494993 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3591 00:59:39.498326 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3592 00:59:39.502566 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3593 00:59:39.505109 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3594 00:59:39.511782 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3595 00:59:39.514698 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3596 00:59:39.519049 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3597 00:59:39.521577 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3598 00:59:39.528159 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3599 00:59:39.531065 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3600 00:59:39.534647 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3601 00:59:39.537896 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3602 00:59:39.538173 ==
3603 00:59:39.541421 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 00:59:39.544741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 00:59:39.548413 ==
3606 00:59:39.548790 DQS Delay:
3607 00:59:39.549142 DQS0 = 0, DQS1 = 0
3608 00:59:39.551190 DQM Delay:
3609 00:59:39.551725 DQM0 = 117, DQM1 = 110
3610 00:59:39.554737 DQ Delay:
3611 00:59:39.558095 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3612 00:59:39.561570 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3613 00:59:39.565019 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3614 00:59:39.567918 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3615 00:59:39.568433
3616 00:59:39.568906
3617 00:59:39.569382 ==
3618 00:59:39.571618 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 00:59:39.574657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 00:59:39.575041 ==
3621 00:59:39.578169
3622 00:59:39.578554
3623 00:59:39.578856 TX Vref Scan disable
3624 00:59:39.580957 == TX Byte 0 ==
3625 00:59:39.584108 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3626 00:59:39.587870 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3627 00:59:39.591329 == TX Byte 1 ==
3628 00:59:39.594335 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3629 00:59:39.597740 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3630 00:59:39.600969 ==
3631 00:59:39.601488 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 00:59:39.607689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 00:59:39.608198 ==
3634 00:59:39.619162 TX Vref=22, minBit 9, minWin=25, winSum=426
3635 00:59:39.621447 TX Vref=24, minBit 1, minWin=26, winSum=430
3636 00:59:39.625303 TX Vref=26, minBit 1, minWin=26, winSum=434
3637 00:59:39.628766 TX Vref=28, minBit 7, minWin=26, winSum=433
3638 00:59:39.631659 TX Vref=30, minBit 5, minWin=26, winSum=430
3639 00:59:39.638156 TX Vref=32, minBit 1, minWin=26, winSum=428
3640 00:59:39.642139 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 26
3641 00:59:39.642699
3642 00:59:39.644639 Final TX Range 1 Vref 26
3643 00:59:39.645120
3644 00:59:39.645485 ==
3645 00:59:39.647854 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 00:59:39.651304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 00:59:39.654433 ==
3648 00:59:39.654889
3649 00:59:39.655248
3650 00:59:39.655592 TX Vref Scan disable
3651 00:59:39.658383 == TX Byte 0 ==
3652 00:59:39.661885 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3653 00:59:39.668275 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3654 00:59:39.668832 == TX Byte 1 ==
3655 00:59:39.671539 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3656 00:59:39.678851 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3657 00:59:39.679412
3658 00:59:39.679816 [DATLAT]
3659 00:59:39.680161 Freq=1200, CH1 RK1
3660 00:59:39.680495
3661 00:59:39.681298 DATLAT Default: 0xd
3662 00:59:39.684539 0, 0xFFFF, sum = 0
3663 00:59:39.685030 1, 0xFFFF, sum = 0
3664 00:59:39.687653 2, 0xFFFF, sum = 0
3665 00:59:39.688146 3, 0xFFFF, sum = 0
3666 00:59:39.691323 4, 0xFFFF, sum = 0
3667 00:59:39.692008 5, 0xFFFF, sum = 0
3668 00:59:39.694753 6, 0xFFFF, sum = 0
3669 00:59:39.695329 7, 0xFFFF, sum = 0
3670 00:59:39.697852 8, 0xFFFF, sum = 0
3671 00:59:39.698331 9, 0xFFFF, sum = 0
3672 00:59:39.701717 10, 0xFFFF, sum = 0
3673 00:59:39.702301 11, 0xFFFF, sum = 0
3674 00:59:39.704921 12, 0x0, sum = 1
3675 00:59:39.705397 13, 0x0, sum = 2
3676 00:59:39.708111 14, 0x0, sum = 3
3677 00:59:39.708595 15, 0x0, sum = 4
3678 00:59:39.710942 best_step = 13
3679 00:59:39.711413
3680 00:59:39.711945 ==
3681 00:59:39.715060 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 00:59:39.718006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 00:59:39.718570 ==
3684 00:59:39.718942 RX Vref Scan: 0
3685 00:59:39.722189
3686 00:59:39.722745 RX Vref 0 -> 0, step: 1
3687 00:59:39.723114
3688 00:59:39.724203 RX Delay -21 -> 252, step: 4
3689 00:59:39.731048 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3690 00:59:39.735195 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3691 00:59:39.737772 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3692 00:59:39.741326 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3693 00:59:39.744442 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3694 00:59:39.750991 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3695 00:59:39.754266 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3696 00:59:39.757761 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3697 00:59:39.761010 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3698 00:59:39.764143 iDelay=199, Bit 9, Center 102 (39 ~ 166) 128
3699 00:59:39.771096 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3700 00:59:39.774527 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3701 00:59:39.777616 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3702 00:59:39.781098 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3703 00:59:39.784004 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3704 00:59:39.790558 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3705 00:59:39.791132 ==
3706 00:59:39.794229 Dram Type= 6, Freq= 0, CH_1, rank 1
3707 00:59:39.797394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3708 00:59:39.797952 ==
3709 00:59:39.798326 DQS Delay:
3710 00:59:39.800934 DQS0 = 0, DQS1 = 0
3711 00:59:39.801489 DQM Delay:
3712 00:59:39.804183 DQM0 = 118, DQM1 = 111
3713 00:59:39.804739 DQ Delay:
3714 00:59:39.807443 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3715 00:59:39.810511 DQ4 =116, DQ5 =128, DQ6 =132, DQ7 =116
3716 00:59:39.813947 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =102
3717 00:59:39.816547 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3718 00:59:39.819895
3719 00:59:39.820353
3720 00:59:39.826481 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3721 00:59:39.830432 CH1 RK1: MR19=303, MR18=F3EF
3722 00:59:39.837192 CH1_RK1: MR19=0x303, MR18=0xF3EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3723 00:59:39.840071 [RxdqsGatingPostProcess] freq 1200
3724 00:59:39.843125 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3725 00:59:39.846557 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 00:59:39.849822 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 00:59:39.853560 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 00:59:39.856107 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 00:59:39.859956 best DQS0 dly(2T, 0.5T) = (0, 11)
3730 00:59:39.863125 best DQS1 dly(2T, 0.5T) = (0, 11)
3731 00:59:39.866022 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3732 00:59:39.869241 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3733 00:59:39.873217 Pre-setting of DQS Precalculation
3734 00:59:39.876212 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3735 00:59:39.886288 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3736 00:59:39.892557 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3737 00:59:39.893104
3738 00:59:39.893474
3739 00:59:39.896611 [Calibration Summary] 2400 Mbps
3740 00:59:39.897172 CH 0, Rank 0
3741 00:59:39.899561 SW Impedance : PASS
3742 00:59:39.900148 DUTY Scan : NO K
3743 00:59:39.902591 ZQ Calibration : PASS
3744 00:59:39.905664 Jitter Meter : NO K
3745 00:59:39.906130 CBT Training : PASS
3746 00:59:39.909110 Write leveling : PASS
3747 00:59:39.912524 RX DQS gating : PASS
3748 00:59:39.912986 RX DQ/DQS(RDDQC) : PASS
3749 00:59:39.915559 TX DQ/DQS : PASS
3750 00:59:39.919153 RX DATLAT : PASS
3751 00:59:39.919752 RX DQ/DQS(Engine): PASS
3752 00:59:39.922638 TX OE : NO K
3753 00:59:39.923195 All Pass.
3754 00:59:39.923622
3755 00:59:39.926418 CH 0, Rank 1
3756 00:59:39.927021 SW Impedance : PASS
3757 00:59:39.929577 DUTY Scan : NO K
3758 00:59:39.932091 ZQ Calibration : PASS
3759 00:59:39.932560 Jitter Meter : NO K
3760 00:59:39.935411 CBT Training : PASS
3761 00:59:39.939141 Write leveling : PASS
3762 00:59:39.939744 RX DQS gating : PASS
3763 00:59:39.942338 RX DQ/DQS(RDDQC) : PASS
3764 00:59:39.945638 TX DQ/DQS : PASS
3765 00:59:39.946101 RX DATLAT : PASS
3766 00:59:39.949288 RX DQ/DQS(Engine): PASS
3767 00:59:39.949751 TX OE : NO K
3768 00:59:39.952034 All Pass.
3769 00:59:39.952495
3770 00:59:39.952860 CH 1, Rank 0
3771 00:59:39.955112 SW Impedance : PASS
3772 00:59:39.959424 DUTY Scan : NO K
3773 00:59:39.960052 ZQ Calibration : PASS
3774 00:59:39.962440 Jitter Meter : NO K
3775 00:59:39.963002 CBT Training : PASS
3776 00:59:39.965450 Write leveling : PASS
3777 00:59:39.968840 RX DQS gating : PASS
3778 00:59:39.969407 RX DQ/DQS(RDDQC) : PASS
3779 00:59:39.971967 TX DQ/DQS : PASS
3780 00:59:39.975837 RX DATLAT : PASS
3781 00:59:39.976396 RX DQ/DQS(Engine): PASS
3782 00:59:39.978812 TX OE : NO K
3783 00:59:39.979333 All Pass.
3784 00:59:39.979948
3785 00:59:39.981809 CH 1, Rank 1
3786 00:59:39.982268 SW Impedance : PASS
3787 00:59:39.985319 DUTY Scan : NO K
3788 00:59:39.988397 ZQ Calibration : PASS
3789 00:59:39.988860 Jitter Meter : NO K
3790 00:59:39.991314 CBT Training : PASS
3791 00:59:39.995366 Write leveling : PASS
3792 00:59:39.995915 RX DQS gating : PASS
3793 00:59:39.998235 RX DQ/DQS(RDDQC) : PASS
3794 00:59:40.001857 TX DQ/DQS : PASS
3795 00:59:40.002415 RX DATLAT : PASS
3796 00:59:40.004371 RX DQ/DQS(Engine): PASS
3797 00:59:40.008058 TX OE : NO K
3798 00:59:40.008527 All Pass.
3799 00:59:40.008899
3800 00:59:40.011050 DramC Write-DBI off
3801 00:59:40.011515 PER_BANK_REFRESH: Hybrid Mode
3802 00:59:40.014666 TX_TRACKING: ON
3803 00:59:40.024667 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3804 00:59:40.028064 [FAST_K] Save calibration result to emmc
3805 00:59:40.031544 dramc_set_vcore_voltage set vcore to 650000
3806 00:59:40.032175 Read voltage for 600, 5
3807 00:59:40.034070 Vio18 = 0
3808 00:59:40.034536 Vcore = 650000
3809 00:59:40.034905 Vdram = 0
3810 00:59:40.037230 Vddq = 0
3811 00:59:40.037697 Vmddr = 0
3812 00:59:40.043745 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3813 00:59:40.046917 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3814 00:59:40.050517 MEM_TYPE=3, freq_sel=19
3815 00:59:40.053799 sv_algorithm_assistance_LP4_1600
3816 00:59:40.057351 ============ PULL DRAM RESETB DOWN ============
3817 00:59:40.060529 ========== PULL DRAM RESETB DOWN end =========
3818 00:59:40.067312 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3819 00:59:40.070392 ===================================
3820 00:59:40.070973 LPDDR4 DRAM CONFIGURATION
3821 00:59:40.073475 ===================================
3822 00:59:40.077040 EX_ROW_EN[0] = 0x0
3823 00:59:40.080092 EX_ROW_EN[1] = 0x0
3824 00:59:40.080697 LP4Y_EN = 0x0
3825 00:59:40.082949 WORK_FSP = 0x0
3826 00:59:40.083413 WL = 0x2
3827 00:59:40.087332 RL = 0x2
3828 00:59:40.087863 BL = 0x2
3829 00:59:40.090260 RPST = 0x0
3830 00:59:40.090729 RD_PRE = 0x0
3831 00:59:40.093604 WR_PRE = 0x1
3832 00:59:40.094085 WR_PST = 0x0
3833 00:59:40.096285 DBI_WR = 0x0
3834 00:59:40.096743 DBI_RD = 0x0
3835 00:59:40.099838 OTF = 0x1
3836 00:59:40.103084 ===================================
3837 00:59:40.106863 ===================================
3838 00:59:40.107332 ANA top config
3839 00:59:40.109758 ===================================
3840 00:59:40.112817 DLL_ASYNC_EN = 0
3841 00:59:40.116903 ALL_SLAVE_EN = 1
3842 00:59:40.120061 NEW_RANK_MODE = 1
3843 00:59:40.120627 DLL_IDLE_MODE = 1
3844 00:59:40.123063 LP45_APHY_COMB_EN = 1
3845 00:59:40.125982 TX_ODT_DIS = 1
3846 00:59:40.129540 NEW_8X_MODE = 1
3847 00:59:40.133108 ===================================
3848 00:59:40.136495 ===================================
3849 00:59:40.139660 data_rate = 1200
3850 00:59:40.143352 CKR = 1
3851 00:59:40.143970 DQ_P2S_RATIO = 8
3852 00:59:40.146248 ===================================
3853 00:59:40.150180 CA_P2S_RATIO = 8
3854 00:59:40.153173 DQ_CA_OPEN = 0
3855 00:59:40.155954 DQ_SEMI_OPEN = 0
3856 00:59:40.159846 CA_SEMI_OPEN = 0
3857 00:59:40.162624 CA_FULL_RATE = 0
3858 00:59:40.163086 DQ_CKDIV4_EN = 1
3859 00:59:40.166265 CA_CKDIV4_EN = 1
3860 00:59:40.168919 CA_PREDIV_EN = 0
3861 00:59:40.172325 PH8_DLY = 0
3862 00:59:40.175697 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3863 00:59:40.178735 DQ_AAMCK_DIV = 4
3864 00:59:40.179196 CA_AAMCK_DIV = 4
3865 00:59:40.182017 CA_ADMCK_DIV = 4
3866 00:59:40.184992 DQ_TRACK_CA_EN = 0
3867 00:59:40.188652 CA_PICK = 600
3868 00:59:40.192831 CA_MCKIO = 600
3869 00:59:40.195507 MCKIO_SEMI = 0
3870 00:59:40.199169 PLL_FREQ = 2288
3871 00:59:40.202395 DQ_UI_PI_RATIO = 32
3872 00:59:40.202960 CA_UI_PI_RATIO = 0
3873 00:59:40.205589 ===================================
3874 00:59:40.208453 ===================================
3875 00:59:40.211478 memory_type:LPDDR4
3876 00:59:40.215036 GP_NUM : 10
3877 00:59:40.215518 SRAM_EN : 1
3878 00:59:40.218320 MD32_EN : 0
3879 00:59:40.221699 ===================================
3880 00:59:40.225256 [ANA_INIT] >>>>>>>>>>>>>>
3881 00:59:40.228885 <<<<<< [CONFIGURE PHASE]: ANA_TX
3882 00:59:40.231592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3883 00:59:40.234981 ===================================
3884 00:59:40.235402 data_rate = 1200,PCW = 0X5800
3885 00:59:40.238492 ===================================
3886 00:59:40.241730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3887 00:59:40.248145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3888 00:59:40.254747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 00:59:40.257884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3890 00:59:40.261878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3891 00:59:40.264595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3892 00:59:40.267954 [ANA_INIT] flow start
3893 00:59:40.271416 [ANA_INIT] PLL >>>>>>>>
3894 00:59:40.271879 [ANA_INIT] PLL <<<<<<<<
3895 00:59:40.274303 [ANA_INIT] MIDPI >>>>>>>>
3896 00:59:40.277588 [ANA_INIT] MIDPI <<<<<<<<
3897 00:59:40.278021 [ANA_INIT] DLL >>>>>>>>
3898 00:59:40.280619 [ANA_INIT] flow end
3899 00:59:40.283733 ============ LP4 DIFF to SE enter ============
3900 00:59:40.287797 ============ LP4 DIFF to SE exit ============
3901 00:59:40.290750 [ANA_INIT] <<<<<<<<<<<<<
3902 00:59:40.294038 [Flow] Enable top DCM control >>>>>
3903 00:59:40.297456 [Flow] Enable top DCM control <<<<<
3904 00:59:40.300393 Enable DLL master slave shuffle
3905 00:59:40.307589 ==============================================================
3906 00:59:40.308184 Gating Mode config
3907 00:59:40.313511 ==============================================================
3908 00:59:40.317025 Config description:
3909 00:59:40.324047 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3910 00:59:40.330678 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3911 00:59:40.337414 SELPH_MODE 0: By rank 1: By Phase
3912 00:59:40.343384 ==============================================================
3913 00:59:40.346801 GAT_TRACK_EN = 1
3914 00:59:40.347261 RX_GATING_MODE = 2
3915 00:59:40.350544 RX_GATING_TRACK_MODE = 2
3916 00:59:40.353095 SELPH_MODE = 1
3917 00:59:40.356785 PICG_EARLY_EN = 1
3918 00:59:40.360060 VALID_LAT_VALUE = 1
3919 00:59:40.366562 ==============================================================
3920 00:59:40.370197 Enter into Gating configuration >>>>
3921 00:59:40.373740 Exit from Gating configuration <<<<
3922 00:59:40.376360 Enter into DVFS_PRE_config >>>>>
3923 00:59:40.386813 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3924 00:59:40.390036 Exit from DVFS_PRE_config <<<<<
3925 00:59:40.393357 Enter into PICG configuration >>>>
3926 00:59:40.396923 Exit from PICG configuration <<<<
3927 00:59:40.399930 [RX_INPUT] configuration >>>>>
3928 00:59:40.403168 [RX_INPUT] configuration <<<<<
3929 00:59:40.406117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3930 00:59:40.412783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3931 00:59:40.419401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 00:59:40.426099 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 00:59:40.432624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3934 00:59:40.435447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3935 00:59:40.442593 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3936 00:59:40.445251 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3937 00:59:40.448545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3938 00:59:40.452007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3939 00:59:40.458856 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3940 00:59:40.462098 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3941 00:59:40.466035 ===================================
3942 00:59:40.469265 LPDDR4 DRAM CONFIGURATION
3943 00:59:40.472169 ===================================
3944 00:59:40.472649 EX_ROW_EN[0] = 0x0
3945 00:59:40.474904 EX_ROW_EN[1] = 0x0
3946 00:59:40.474986 LP4Y_EN = 0x0
3947 00:59:40.478072 WORK_FSP = 0x0
3948 00:59:40.478170 WL = 0x2
3949 00:59:40.481276 RL = 0x2
3950 00:59:40.481368 BL = 0x2
3951 00:59:40.484885 RPST = 0x0
3952 00:59:40.484960 RD_PRE = 0x0
3953 00:59:40.488188 WR_PRE = 0x1
3954 00:59:40.488278 WR_PST = 0x0
3955 00:59:40.491581 DBI_WR = 0x0
3956 00:59:40.494565 DBI_RD = 0x0
3957 00:59:40.494637 OTF = 0x1
3958 00:59:40.498081 ===================================
3959 00:59:40.501185 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3960 00:59:40.507995 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3961 00:59:40.511452 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 00:59:40.514872 ===================================
3963 00:59:40.518415 LPDDR4 DRAM CONFIGURATION
3964 00:59:40.521263 ===================================
3965 00:59:40.521419 EX_ROW_EN[0] = 0x10
3966 00:59:40.524605 EX_ROW_EN[1] = 0x0
3967 00:59:40.524785 LP4Y_EN = 0x0
3968 00:59:40.528255 WORK_FSP = 0x0
3969 00:59:40.528453 WL = 0x2
3970 00:59:40.531956 RL = 0x2
3971 00:59:40.532142 BL = 0x2
3972 00:59:40.534809 RPST = 0x0
3973 00:59:40.535008 RD_PRE = 0x0
3974 00:59:40.537588 WR_PRE = 0x1
3975 00:59:40.541391 WR_PST = 0x0
3976 00:59:40.541602 DBI_WR = 0x0
3977 00:59:40.544253 DBI_RD = 0x0
3978 00:59:40.544485 OTF = 0x1
3979 00:59:40.547607 ===================================
3980 00:59:40.554767 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3981 00:59:40.558773 nWR fixed to 30
3982 00:59:40.561395 [ModeRegInit_LP4] CH0 RK0
3983 00:59:40.561652 [ModeRegInit_LP4] CH0 RK1
3984 00:59:40.565342 [ModeRegInit_LP4] CH1 RK0
3985 00:59:40.567830 [ModeRegInit_LP4] CH1 RK1
3986 00:59:40.568217 match AC timing 17
3987 00:59:40.574781 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3988 00:59:40.578195 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3989 00:59:40.581725 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3990 00:59:40.587807 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3991 00:59:40.591440 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3992 00:59:40.591951 ==
3993 00:59:40.594671 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 00:59:40.597961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 00:59:40.598533 ==
3996 00:59:40.604185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 00:59:40.610227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3998 00:59:40.614252 [CA 0] Center 36 (6~66) winsize 61
3999 00:59:40.617171 [CA 1] Center 36 (6~66) winsize 61
4000 00:59:40.620369 [CA 2] Center 33 (3~64) winsize 62
4001 00:59:40.624109 [CA 3] Center 33 (3~64) winsize 62
4002 00:59:40.627061 [CA 4] Center 33 (3~64) winsize 62
4003 00:59:40.630357 [CA 5] Center 33 (3~64) winsize 62
4004 00:59:40.630438
4005 00:59:40.633687 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4006 00:59:40.633768
4007 00:59:40.636929 [CATrainingPosCal] consider 1 rank data
4008 00:59:40.640293 u2DelayCellTimex100 = 270/100 ps
4009 00:59:40.643650 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4010 00:59:40.646782 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4011 00:59:40.650191 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4012 00:59:40.656790 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 00:59:40.660365 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4014 00:59:40.663625 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4015 00:59:40.663795
4016 00:59:40.666861 CA PerBit enable=1, Macro0, CA PI delay=33
4017 00:59:40.667060
4018 00:59:40.670189 [CBTSetCACLKResult] CA Dly = 33
4019 00:59:40.670411 CS Dly: 5 (0~36)
4020 00:59:40.670532 ==
4021 00:59:40.673619 Dram Type= 6, Freq= 0, CH_0, rank 1
4022 00:59:40.680120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 00:59:40.680382 ==
4024 00:59:40.683536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4025 00:59:40.689898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4026 00:59:40.693480 [CA 0] Center 36 (6~66) winsize 61
4027 00:59:40.697099 [CA 1] Center 36 (6~66) winsize 61
4028 00:59:40.700216 [CA 2] Center 34 (4~65) winsize 62
4029 00:59:40.703472 [CA 3] Center 34 (4~65) winsize 62
4030 00:59:40.707267 [CA 4] Center 33 (3~64) winsize 62
4031 00:59:40.709707 [CA 5] Center 33 (3~64) winsize 62
4032 00:59:40.710175
4033 00:59:40.713252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4034 00:59:40.713729
4035 00:59:40.716957 [CATrainingPosCal] consider 2 rank data
4036 00:59:40.720639 u2DelayCellTimex100 = 270/100 ps
4037 00:59:40.726079 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4038 00:59:40.729915 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4039 00:59:40.733184 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4040 00:59:40.736691 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4041 00:59:40.739444 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4042 00:59:40.742940 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4043 00:59:40.743412
4044 00:59:40.746257 CA PerBit enable=1, Macro0, CA PI delay=33
4045 00:59:40.746984
4046 00:59:40.749356 [CBTSetCACLKResult] CA Dly = 33
4047 00:59:40.752865 CS Dly: 5 (0~37)
4048 00:59:40.753455
4049 00:59:40.756521 ----->DramcWriteLeveling(PI) begin...
4050 00:59:40.757108 ==
4051 00:59:40.759155 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 00:59:40.762743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 00:59:40.763231 ==
4054 00:59:40.765747 Write leveling (Byte 0): 34 => 34
4055 00:59:40.769379 Write leveling (Byte 1): 31 => 31
4056 00:59:40.772344 DramcWriteLeveling(PI) end<-----
4057 00:59:40.772765
4058 00:59:40.773228 ==
4059 00:59:40.775786 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 00:59:40.779837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 00:59:40.780277 ==
4062 00:59:40.782097 [Gating] SW mode calibration
4063 00:59:40.790059 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4064 00:59:40.795581 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4065 00:59:40.799451 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 00:59:40.802873 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 00:59:40.808565 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 00:59:40.812610 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4069 00:59:40.815719 0 9 16 | B1->B0 | 2f2f 2a2a | 0 0 | (1 1) (1 1)
4070 00:59:40.821778 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 00:59:40.825259 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 00:59:40.829294 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 00:59:40.835702 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 00:59:40.838697 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 00:59:40.841997 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 00:59:40.849634 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4077 00:59:40.851895 0 10 16 | B1->B0 | 3333 3e3e | 0 1 | (0 0) (0 0)
4078 00:59:40.855061 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 00:59:40.861638 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 00:59:40.865254 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 00:59:40.868335 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 00:59:40.875187 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 00:59:40.877950 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 00:59:40.881554 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4085 00:59:40.887668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 00:59:40.891274 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 00:59:40.894586 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 00:59:40.900449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 00:59:40.904090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 00:59:40.907016 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 00:59:40.913889 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 00:59:40.917140 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 00:59:40.920364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 00:59:40.926879 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 00:59:40.931291 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 00:59:40.933851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 00:59:40.940269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 00:59:40.943782 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 00:59:40.947159 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 00:59:40.954365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 00:59:40.957569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 00:59:40.960466 Total UI for P1: 0, mck2ui 16
4103 00:59:40.964683 best dqsien dly found for B0: ( 0, 13, 14)
4104 00:59:40.967043 Total UI for P1: 0, mck2ui 16
4105 00:59:40.970418 best dqsien dly found for B1: ( 0, 13, 14)
4106 00:59:40.974165 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4107 00:59:40.977354 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4108 00:59:40.977815
4109 00:59:40.980097 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4110 00:59:40.987591 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4111 00:59:40.988213 [Gating] SW calibration Done
4112 00:59:40.988599 ==
4113 00:59:40.990075 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 00:59:40.997049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 00:59:40.997510 ==
4116 00:59:40.997869 RX Vref Scan: 0
4117 00:59:40.998210
4118 00:59:41.000232 RX Vref 0 -> 0, step: 1
4119 00:59:41.000690
4120 00:59:41.003598 RX Delay -230 -> 252, step: 16
4121 00:59:41.006878 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4122 00:59:41.009834 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4123 00:59:41.016191 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4124 00:59:41.019428 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4125 00:59:41.022822 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4126 00:59:41.026997 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4127 00:59:41.029617 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4128 00:59:41.035997 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4129 00:59:41.040064 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4130 00:59:41.042500 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4131 00:59:41.045762 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4132 00:59:41.052930 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4133 00:59:41.056283 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4134 00:59:41.059734 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4135 00:59:41.062380 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4136 00:59:41.068869 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4137 00:59:41.069290 ==
4138 00:59:41.072479 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 00:59:41.075848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 00:59:41.076269 ==
4141 00:59:41.076599 DQS Delay:
4142 00:59:41.079517 DQS0 = 0, DQS1 = 0
4143 00:59:41.079968 DQM Delay:
4144 00:59:41.082353 DQM0 = 41, DQM1 = 30
4145 00:59:41.082790 DQ Delay:
4146 00:59:41.085484 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4147 00:59:41.088800 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4148 00:59:41.091805 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4149 00:59:41.095170 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4150 00:59:41.095396
4151 00:59:41.095575
4152 00:59:41.095760 ==
4153 00:59:41.098519 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 00:59:41.101789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 00:59:41.105581 ==
4156 00:59:41.105806
4157 00:59:41.105984
4158 00:59:41.106150 TX Vref Scan disable
4159 00:59:41.108858 == TX Byte 0 ==
4160 00:59:41.112379 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4161 00:59:41.118602 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4162 00:59:41.118829 == TX Byte 1 ==
4163 00:59:41.121807 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4164 00:59:41.128444 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4165 00:59:41.128670 ==
4166 00:59:41.131859 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 00:59:41.135445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 00:59:41.135689 ==
4169 00:59:41.135879
4170 00:59:41.136045
4171 00:59:41.138102 TX Vref Scan disable
4172 00:59:41.141804 == TX Byte 0 ==
4173 00:59:41.144890 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4174 00:59:41.147932 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4175 00:59:41.152051 == TX Byte 1 ==
4176 00:59:41.155015 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4177 00:59:41.158195 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4178 00:59:41.158419
4179 00:59:41.158594 [DATLAT]
4180 00:59:41.161305 Freq=600, CH0 RK0
4181 00:59:41.161534
4182 00:59:41.164730 DATLAT Default: 0x9
4183 00:59:41.164965 0, 0xFFFF, sum = 0
4184 00:59:41.167952 1, 0xFFFF, sum = 0
4185 00:59:41.168181 2, 0xFFFF, sum = 0
4186 00:59:41.171196 3, 0xFFFF, sum = 0
4187 00:59:41.171423 4, 0xFFFF, sum = 0
4188 00:59:41.174808 5, 0xFFFF, sum = 0
4189 00:59:41.175037 6, 0xFFFF, sum = 0
4190 00:59:41.177680 7, 0xFFFF, sum = 0
4191 00:59:41.177908 8, 0x0, sum = 1
4192 00:59:41.181294 9, 0x0, sum = 2
4193 00:59:41.181531 10, 0x0, sum = 3
4194 00:59:41.184410 11, 0x0, sum = 4
4195 00:59:41.184637 best_step = 9
4196 00:59:41.184817
4197 00:59:41.184982 ==
4198 00:59:41.187582 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 00:59:41.191320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 00:59:41.191545 ==
4201 00:59:41.194604 RX Vref Scan: 1
4202 00:59:41.194831
4203 00:59:41.197747 RX Vref 0 -> 0, step: 1
4204 00:59:41.197988
4205 00:59:41.198171 RX Delay -195 -> 252, step: 8
4206 00:59:41.201124
4207 00:59:41.201368 Set Vref, RX VrefLevel [Byte0]: 60
4208 00:59:41.204046 [Byte1]: 49
4209 00:59:41.209095
4210 00:59:41.209322 Final RX Vref Byte 0 = 60 to rank0
4211 00:59:41.212881 Final RX Vref Byte 1 = 49 to rank0
4212 00:59:41.215516 Final RX Vref Byte 0 = 60 to rank1
4213 00:59:41.218861 Final RX Vref Byte 1 = 49 to rank1==
4214 00:59:41.221856 Dram Type= 6, Freq= 0, CH_0, rank 0
4215 00:59:41.228555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 00:59:41.228781 ==
4217 00:59:41.228960 DQS Delay:
4218 00:59:41.231852 DQS0 = 0, DQS1 = 0
4219 00:59:41.232077 DQM Delay:
4220 00:59:41.232255 DQM0 = 43, DQM1 = 32
4221 00:59:41.235488 DQ Delay:
4222 00:59:41.240113 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4223 00:59:41.242509 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4224 00:59:41.245432 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4225 00:59:41.249061 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4226 00:59:41.249617
4227 00:59:41.250095
4228 00:59:41.255649 [DQSOSCAuto] RK0, (LSB)MR18= 0x6138, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4229 00:59:41.258564 CH0 RK0: MR19=808, MR18=6138
4230 00:59:41.265601 CH0_RK0: MR19=0x808, MR18=0x6138, DQSOSC=391, MR23=63, INC=171, DEC=114
4231 00:59:41.266055
4232 00:59:41.268467 ----->DramcWriteLeveling(PI) begin...
4233 00:59:41.268927 ==
4234 00:59:41.272155 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 00:59:41.275299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 00:59:41.275987 ==
4237 00:59:41.278464 Write leveling (Byte 0): 30 => 30
4238 00:59:41.281692 Write leveling (Byte 1): 30 => 30
4239 00:59:41.285570 DramcWriteLeveling(PI) end<-----
4240 00:59:41.285962
4241 00:59:41.286277 ==
4242 00:59:41.288303 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 00:59:41.291751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 00:59:41.294794 ==
4245 00:59:41.295087 [Gating] SW mode calibration
4246 00:59:41.305013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4247 00:59:41.308487 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4248 00:59:41.311923 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 00:59:41.318105 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 00:59:41.321837 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 00:59:41.324357 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4252 00:59:41.331845 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4253 00:59:41.334520 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 00:59:41.337583 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 00:59:41.344568 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 00:59:41.347912 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 00:59:41.351227 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 00:59:41.358032 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 00:59:41.361509 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4260 00:59:41.364328 0 10 16 | B1->B0 | 3b3b 3f3f | 0 1 | (1 1) (1 1)
4261 00:59:41.371160 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 00:59:41.374758 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 00:59:41.377539 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 00:59:41.384373 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 00:59:41.387281 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 00:59:41.390759 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 00:59:41.397122 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 00:59:41.400664 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 00:59:41.403797 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 00:59:41.410609 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 00:59:41.414262 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 00:59:41.416714 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 00:59:41.423630 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 00:59:41.427491 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 00:59:41.430319 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 00:59:41.436831 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 00:59:41.440072 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 00:59:41.442943 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 00:59:41.449624 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 00:59:41.453095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 00:59:41.456304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 00:59:41.462745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 00:59:41.466745 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4284 00:59:41.469821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 00:59:41.472862 Total UI for P1: 0, mck2ui 16
4286 00:59:41.476440 best dqsien dly found for B0: ( 0, 13, 12)
4287 00:59:41.479586 Total UI for P1: 0, mck2ui 16
4288 00:59:41.483453 best dqsien dly found for B1: ( 0, 13, 14)
4289 00:59:41.486166 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4290 00:59:41.492607 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4291 00:59:41.493029
4292 00:59:41.496295 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4293 00:59:41.499264 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4294 00:59:41.502559 [Gating] SW calibration Done
4295 00:59:41.502977 ==
4296 00:59:41.505843 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 00:59:41.509203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 00:59:41.509624 ==
4299 00:59:41.513689 RX Vref Scan: 0
4300 00:59:41.514105
4301 00:59:41.514434 RX Vref 0 -> 0, step: 1
4302 00:59:41.514742
4303 00:59:41.515746 RX Delay -230 -> 252, step: 16
4304 00:59:41.519265 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4305 00:59:41.525545 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4306 00:59:41.529157 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4307 00:59:41.532134 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4308 00:59:41.536069 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4309 00:59:41.539333 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4310 00:59:41.545757 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4311 00:59:41.549877 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4312 00:59:41.552293 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4313 00:59:41.555547 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4314 00:59:41.562633 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4315 00:59:41.565607 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4316 00:59:41.568597 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4317 00:59:41.572046 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4318 00:59:41.578604 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4319 00:59:41.581946 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4320 00:59:41.582343 ==
4321 00:59:41.585087 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 00:59:41.588725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 00:59:41.589149 ==
4324 00:59:41.591961 DQS Delay:
4325 00:59:41.592524 DQS0 = 0, DQS1 = 0
4326 00:59:41.595110 DQM Delay:
4327 00:59:41.595554 DQM0 = 41, DQM1 = 35
4328 00:59:41.596004 DQ Delay:
4329 00:59:41.598687 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4330 00:59:41.602141 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4331 00:59:41.605046 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4332 00:59:41.608695 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4333 00:59:41.609151
4334 00:59:41.609509
4335 00:59:41.609861 ==
4336 00:59:41.612061 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 00:59:41.618502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 00:59:41.618962 ==
4339 00:59:41.619603
4340 00:59:41.620041
4341 00:59:41.620399 TX Vref Scan disable
4342 00:59:41.622326 == TX Byte 0 ==
4343 00:59:41.625513 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4344 00:59:41.631907 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4345 00:59:41.632349 == TX Byte 1 ==
4346 00:59:41.635422 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4347 00:59:41.642155 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4348 00:59:41.642639 ==
4349 00:59:41.645387 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 00:59:41.649176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 00:59:41.649593 ==
4352 00:59:41.649921
4353 00:59:41.650228
4354 00:59:41.652684 TX Vref Scan disable
4355 00:59:41.655893 == TX Byte 0 ==
4356 00:59:41.658389 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4357 00:59:41.662255 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4358 00:59:41.665296 == TX Byte 1 ==
4359 00:59:41.668742 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4360 00:59:41.672143 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4361 00:59:41.672560
4362 00:59:41.672887 [DATLAT]
4363 00:59:41.675136 Freq=600, CH0 RK1
4364 00:59:41.675551
4365 00:59:41.678735 DATLAT Default: 0x9
4366 00:59:41.679151 0, 0xFFFF, sum = 0
4367 00:59:41.681970 1, 0xFFFF, sum = 0
4368 00:59:41.682392 2, 0xFFFF, sum = 0
4369 00:59:41.685067 3, 0xFFFF, sum = 0
4370 00:59:41.685488 4, 0xFFFF, sum = 0
4371 00:59:41.688205 5, 0xFFFF, sum = 0
4372 00:59:41.688722 6, 0xFFFF, sum = 0
4373 00:59:41.691369 7, 0xFFFF, sum = 0
4374 00:59:41.691825 8, 0x0, sum = 1
4375 00:59:41.695188 9, 0x0, sum = 2
4376 00:59:41.695750 10, 0x0, sum = 3
4377 00:59:41.698190 11, 0x0, sum = 4
4378 00:59:41.698611 best_step = 9
4379 00:59:41.698938
4380 00:59:41.699242 ==
4381 00:59:41.701843 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 00:59:41.705236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 00:59:41.705655 ==
4384 00:59:41.708314 RX Vref Scan: 0
4385 00:59:41.708727
4386 00:59:41.711230 RX Vref 0 -> 0, step: 1
4387 00:59:41.711644
4388 00:59:41.712019 RX Delay -195 -> 252, step: 8
4389 00:59:41.719027 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4390 00:59:41.722366 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4391 00:59:41.726171 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4392 00:59:41.728926 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4393 00:59:41.736052 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4394 00:59:41.739366 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4395 00:59:41.742355 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4396 00:59:41.745469 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4397 00:59:41.752603 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4398 00:59:41.755426 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4399 00:59:41.759473 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4400 00:59:41.762713 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4401 00:59:41.768466 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4402 00:59:41.772716 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4403 00:59:41.775641 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4404 00:59:41.778813 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4405 00:59:41.779329 ==
4406 00:59:41.782544 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 00:59:41.788960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 00:59:41.789460 ==
4409 00:59:41.789825 DQS Delay:
4410 00:59:41.791909 DQS0 = 0, DQS1 = 0
4411 00:59:41.792367 DQM Delay:
4412 00:59:41.792796 DQM0 = 41, DQM1 = 35
4413 00:59:41.795424 DQ Delay:
4414 00:59:41.798733 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4415 00:59:41.801699 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4416 00:59:41.805280 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4417 00:59:41.808709 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4418 00:59:41.809291
4419 00:59:41.809725
4420 00:59:41.815109 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4421 00:59:41.818139 CH0 RK1: MR19=808, MR18=5E10
4422 00:59:41.824658 CH0_RK1: MR19=0x808, MR18=0x5E10, DQSOSC=392, MR23=63, INC=170, DEC=113
4423 00:59:41.827884 [RxdqsGatingPostProcess] freq 600
4424 00:59:41.834450 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4425 00:59:41.835033 Pre-setting of DQS Precalculation
4426 00:59:41.841323 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4427 00:59:41.841917 ==
4428 00:59:41.844192 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 00:59:41.847651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 00:59:41.848116 ==
4431 00:59:41.853789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 00:59:41.860768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4433 00:59:41.863619 [CA 0] Center 35 (5~66) winsize 62
4434 00:59:41.867561 [CA 1] Center 35 (5~66) winsize 62
4435 00:59:41.870549 [CA 2] Center 34 (3~65) winsize 63
4436 00:59:41.873782 [CA 3] Center 33 (3~64) winsize 62
4437 00:59:41.877739 [CA 4] Center 34 (4~64) winsize 61
4438 00:59:41.880268 [CA 5] Center 33 (3~64) winsize 62
4439 00:59:41.880692
4440 00:59:41.883877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4441 00:59:41.884294
4442 00:59:41.887033 [CATrainingPosCal] consider 1 rank data
4443 00:59:41.890322 u2DelayCellTimex100 = 270/100 ps
4444 00:59:41.893727 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 00:59:41.896830 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 00:59:41.900792 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4447 00:59:41.903651 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 00:59:41.910048 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4449 00:59:41.913220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 00:59:41.913634
4451 00:59:41.916849 CA PerBit enable=1, Macro0, CA PI delay=33
4452 00:59:41.917263
4453 00:59:41.919871 [CBTSetCACLKResult] CA Dly = 33
4454 00:59:41.920313 CS Dly: 5 (0~36)
4455 00:59:41.920682 ==
4456 00:59:41.923177 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 00:59:41.930101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 00:59:41.930519 ==
4459 00:59:41.932913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 00:59:41.939420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4461 00:59:41.942794 [CA 0] Center 35 (5~66) winsize 62
4462 00:59:41.946207 [CA 1] Center 36 (6~66) winsize 61
4463 00:59:41.949556 [CA 2] Center 34 (4~65) winsize 62
4464 00:59:41.952821 [CA 3] Center 34 (3~65) winsize 63
4465 00:59:41.956446 [CA 4] Center 34 (4~65) winsize 62
4466 00:59:41.959385 [CA 5] Center 34 (3~65) winsize 63
4467 00:59:41.959953
4468 00:59:41.962665 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4469 00:59:41.963109
4470 00:59:41.965894 [CATrainingPosCal] consider 2 rank data
4471 00:59:41.969410 u2DelayCellTimex100 = 270/100 ps
4472 00:59:41.972543 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4473 00:59:41.979733 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 00:59:41.982524 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 00:59:41.985800 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4476 00:59:41.989555 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4477 00:59:41.992606 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 00:59:41.993230
4479 00:59:41.995956 CA PerBit enable=1, Macro0, CA PI delay=33
4480 00:59:41.996379
4481 00:59:41.999220 [CBTSetCACLKResult] CA Dly = 33
4482 00:59:41.999641 CS Dly: 5 (0~36)
4483 00:59:42.002443
4484 00:59:42.005993 ----->DramcWriteLeveling(PI) begin...
4485 00:59:42.006422 ==
4486 00:59:42.011014 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 00:59:42.012559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 00:59:42.012984 ==
4489 00:59:42.016026 Write leveling (Byte 0): 29 => 29
4490 00:59:42.018921 Write leveling (Byte 1): 28 => 28
4491 00:59:42.022388 DramcWriteLeveling(PI) end<-----
4492 00:59:42.022804
4493 00:59:42.023132 ==
4494 00:59:42.025587 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 00:59:42.029194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 00:59:42.029611 ==
4497 00:59:42.032107 [Gating] SW mode calibration
4498 00:59:42.038880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4499 00:59:42.045435 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4500 00:59:42.048541 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 00:59:42.051820 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 00:59:42.058796 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4503 00:59:42.062262 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
4504 00:59:42.065254 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 00:59:42.072117 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 00:59:42.075162 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 00:59:42.078793 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 00:59:42.085085 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 00:59:42.088341 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 00:59:42.091324 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 00:59:42.098257 0 10 12 | B1->B0 | 3333 3a39 | 0 1 | (0 0) (1 1)
4512 00:59:42.101777 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4513 00:59:42.104781 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 00:59:42.111721 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 00:59:42.114930 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 00:59:42.118656 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 00:59:42.124793 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 00:59:42.127740 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 00:59:42.131125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 00:59:42.137674 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 00:59:42.141067 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 00:59:42.144590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 00:59:42.151375 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 00:59:42.154988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 00:59:42.157277 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 00:59:42.164496 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 00:59:42.167410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 00:59:42.170520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 00:59:42.177090 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 00:59:42.180831 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 00:59:42.184157 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 00:59:42.190655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 00:59:42.193809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 00:59:42.196748 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 00:59:42.203984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4536 00:59:42.206865 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 00:59:42.209970 Total UI for P1: 0, mck2ui 16
4538 00:59:42.213326 best dqsien dly found for B0: ( 0, 13, 12)
4539 00:59:42.217120 Total UI for P1: 0, mck2ui 16
4540 00:59:42.219801 best dqsien dly found for B1: ( 0, 13, 12)
4541 00:59:42.223342 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4542 00:59:42.227052 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4543 00:59:42.227465
4544 00:59:42.229965 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4545 00:59:42.236228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4546 00:59:42.236645 [Gating] SW calibration Done
4547 00:59:42.236972 ==
4548 00:59:42.239968 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 00:59:42.246192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 00:59:42.246610 ==
4551 00:59:42.246945 RX Vref Scan: 0
4552 00:59:42.247250
4553 00:59:42.249709 RX Vref 0 -> 0, step: 1
4554 00:59:42.250122
4555 00:59:42.253159 RX Delay -230 -> 252, step: 16
4556 00:59:42.256231 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4557 00:59:42.259591 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4558 00:59:42.266293 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4559 00:59:42.269222 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4560 00:59:42.273060 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4561 00:59:42.276072 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4562 00:59:42.279088 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4563 00:59:42.286081 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4564 00:59:42.289040 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4565 00:59:42.293005 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4566 00:59:42.295716 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4567 00:59:42.302564 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4568 00:59:42.305828 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4569 00:59:42.309140 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4570 00:59:42.313062 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4571 00:59:42.319401 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4572 00:59:42.319855 ==
4573 00:59:42.321954 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 00:59:42.325358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 00:59:42.325772 ==
4576 00:59:42.326101 DQS Delay:
4577 00:59:42.328571 DQS0 = 0, DQS1 = 0
4578 00:59:42.328984 DQM Delay:
4579 00:59:42.332139 DQM0 = 47, DQM1 = 37
4580 00:59:42.332552 DQ Delay:
4581 00:59:42.335803 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4582 00:59:42.338524 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4583 00:59:42.342428 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4584 00:59:42.345590 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4585 00:59:42.346006
4586 00:59:42.346335
4587 00:59:42.346640 ==
4588 00:59:42.348716 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 00:59:42.351750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 00:59:42.355450 ==
4591 00:59:42.355915
4592 00:59:42.356376
4593 00:59:42.356782 TX Vref Scan disable
4594 00:59:42.358626 == TX Byte 0 ==
4595 00:59:42.362547 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 00:59:42.364995 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 00:59:42.368492 == TX Byte 1 ==
4598 00:59:42.372054 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4599 00:59:42.374739 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4600 00:59:42.378816 ==
4601 00:59:42.382087 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 00:59:42.385183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 00:59:42.385602 ==
4604 00:59:42.385930
4605 00:59:42.386232
4606 00:59:42.388060 TX Vref Scan disable
4607 00:59:42.388709 == TX Byte 0 ==
4608 00:59:42.395022 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4609 00:59:42.398300 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4610 00:59:42.401133 == TX Byte 1 ==
4611 00:59:42.404733 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4612 00:59:42.407769 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4613 00:59:42.408186
4614 00:59:42.408514 [DATLAT]
4615 00:59:42.410966 Freq=600, CH1 RK0
4616 00:59:42.411384
4617 00:59:42.414342 DATLAT Default: 0x9
4618 00:59:42.414755 0, 0xFFFF, sum = 0
4619 00:59:42.418263 1, 0xFFFF, sum = 0
4620 00:59:42.418683 2, 0xFFFF, sum = 0
4621 00:59:42.421524 3, 0xFFFF, sum = 0
4622 00:59:42.421946 4, 0xFFFF, sum = 0
4623 00:59:42.424137 5, 0xFFFF, sum = 0
4624 00:59:42.424555 6, 0xFFFF, sum = 0
4625 00:59:42.427714 7, 0xFFFF, sum = 0
4626 00:59:42.428161 8, 0x0, sum = 1
4627 00:59:42.431009 9, 0x0, sum = 2
4628 00:59:42.431430 10, 0x0, sum = 3
4629 00:59:42.434225 11, 0x0, sum = 4
4630 00:59:42.434645 best_step = 9
4631 00:59:42.434975
4632 00:59:42.435280 ==
4633 00:59:42.437415 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 00:59:42.441103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 00:59:42.441517 ==
4636 00:59:42.444185 RX Vref Scan: 1
4637 00:59:42.444650
4638 00:59:42.448233 RX Vref 0 -> 0, step: 1
4639 00:59:42.448647
4640 00:59:42.448973 RX Delay -195 -> 252, step: 8
4641 00:59:42.449279
4642 00:59:42.450689 Set Vref, RX VrefLevel [Byte0]: 50
4643 00:59:42.454200 [Byte1]: 54
4644 00:59:42.459311
4645 00:59:42.459751 Final RX Vref Byte 0 = 50 to rank0
4646 00:59:42.461836 Final RX Vref Byte 1 = 54 to rank0
4647 00:59:42.465422 Final RX Vref Byte 0 = 50 to rank1
4648 00:59:42.468924 Final RX Vref Byte 1 = 54 to rank1==
4649 00:59:42.472083 Dram Type= 6, Freq= 0, CH_1, rank 0
4650 00:59:42.479041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 00:59:42.479457 ==
4652 00:59:42.479833 DQS Delay:
4653 00:59:42.481781 DQS0 = 0, DQS1 = 0
4654 00:59:42.482194 DQM Delay:
4655 00:59:42.482522 DQM0 = 46, DQM1 = 37
4656 00:59:42.485038 DQ Delay:
4657 00:59:42.488386 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =40
4658 00:59:42.492185 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4659 00:59:42.494968 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4660 00:59:42.498254 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4661 00:59:42.498690
4662 00:59:42.499024
4663 00:59:42.504584 [DQSOSCAuto] RK0, (LSB)MR18= 0x5238, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4664 00:59:42.508132 CH1 RK0: MR19=808, MR18=5238
4665 00:59:42.514382 CH1_RK0: MR19=0x808, MR18=0x5238, DQSOSC=394, MR23=63, INC=168, DEC=112
4666 00:59:42.514810
4667 00:59:42.518241 ----->DramcWriteLeveling(PI) begin...
4668 00:59:42.518672 ==
4669 00:59:42.521146 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 00:59:42.525087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 00:59:42.525513 ==
4672 00:59:42.527884 Write leveling (Byte 0): 28 => 28
4673 00:59:42.531251 Write leveling (Byte 1): 30 => 30
4674 00:59:42.534273 DramcWriteLeveling(PI) end<-----
4675 00:59:42.534693
4676 00:59:42.535026 ==
4677 00:59:42.537451 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 00:59:42.544232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 00:59:42.544677 ==
4680 00:59:42.545019 [Gating] SW mode calibration
4681 00:59:42.554435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4682 00:59:42.557447 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4683 00:59:42.560867 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 00:59:42.567397 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 00:59:42.571445 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 00:59:42.574055 0 9 12 | B1->B0 | 3030 3333 | 0 1 | (1 0) (1 0)
4687 00:59:42.580523 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4688 00:59:42.584214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 00:59:42.587371 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 00:59:42.593570 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 00:59:42.597197 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 00:59:42.600210 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 00:59:42.606933 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 00:59:42.610298 0 10 12 | B1->B0 | 3737 2b2b | 0 0 | (0 0) (1 1)
4695 00:59:42.613282 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4696 00:59:42.620819 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 00:59:42.623481 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 00:59:42.626869 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 00:59:42.633304 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 00:59:42.636824 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 00:59:42.639962 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 00:59:42.646423 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4703 00:59:42.649804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4704 00:59:42.653070 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 00:59:42.659712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 00:59:42.662811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 00:59:42.666321 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 00:59:42.672543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 00:59:42.676814 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 00:59:42.679420 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 00:59:42.685891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 00:59:42.689539 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 00:59:42.692806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 00:59:42.699549 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 00:59:42.702662 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 00:59:42.706697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 00:59:42.712461 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 00:59:42.715663 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4719 00:59:42.719044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 00:59:42.722401 Total UI for P1: 0, mck2ui 16
4721 00:59:42.725850 best dqsien dly found for B0: ( 0, 13, 12)
4722 00:59:42.729351 Total UI for P1: 0, mck2ui 16
4723 00:59:42.732228 best dqsien dly found for B1: ( 0, 13, 14)
4724 00:59:42.735309 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4725 00:59:42.742137 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4726 00:59:42.742574
4727 00:59:42.745866 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4728 00:59:42.749051 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4729 00:59:42.751914 [Gating] SW calibration Done
4730 00:59:42.752335 ==
4731 00:59:42.755509 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 00:59:42.758906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 00:59:42.759379 ==
4734 00:59:42.761803 RX Vref Scan: 0
4735 00:59:42.762333
4736 00:59:42.762673 RX Vref 0 -> 0, step: 1
4737 00:59:42.762988
4738 00:59:42.764876 RX Delay -230 -> 252, step: 16
4739 00:59:42.768233 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4740 00:59:42.775469 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4741 00:59:42.778714 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4742 00:59:42.781711 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4743 00:59:42.784741 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4744 00:59:42.791127 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4745 00:59:42.794603 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4746 00:59:42.798036 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4747 00:59:42.801061 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4748 00:59:42.807769 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4749 00:59:42.811288 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4750 00:59:42.814292 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4751 00:59:42.818048 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4752 00:59:42.824520 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4753 00:59:42.828413 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4754 00:59:42.831039 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4755 00:59:42.831453 ==
4756 00:59:42.834522 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 00:59:42.837527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 00:59:42.837958 ==
4759 00:59:42.840845 DQS Delay:
4760 00:59:42.841260 DQS0 = 0, DQS1 = 0
4761 00:59:42.844131 DQM Delay:
4762 00:59:42.844544 DQM0 = 44, DQM1 = 39
4763 00:59:42.844870 DQ Delay:
4764 00:59:42.847226 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4765 00:59:42.850385 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4766 00:59:42.853644 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4767 00:59:42.857056 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4768 00:59:42.860557
4769 00:59:42.861032
4770 00:59:42.861367 ==
4771 00:59:42.863752 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 00:59:42.867031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 00:59:42.867444 ==
4774 00:59:42.867804
4775 00:59:42.868115
4776 00:59:42.870818 TX Vref Scan disable
4777 00:59:42.871232 == TX Byte 0 ==
4778 00:59:42.877077 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4779 00:59:42.880136 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4780 00:59:42.880554 == TX Byte 1 ==
4781 00:59:42.887162 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4782 00:59:42.890018 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4783 00:59:42.890529 ==
4784 00:59:42.893965 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 00:59:42.896717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 00:59:42.897135 ==
4787 00:59:42.897463
4788 00:59:42.897767
4789 00:59:42.900450 TX Vref Scan disable
4790 00:59:42.903251 == TX Byte 0 ==
4791 00:59:42.906552 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4792 00:59:42.909866 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4793 00:59:42.912973 == TX Byte 1 ==
4794 00:59:42.916886 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4795 00:59:42.923504 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4796 00:59:42.923956
4797 00:59:42.924284 [DATLAT]
4798 00:59:42.924589 Freq=600, CH1 RK1
4799 00:59:42.924886
4800 00:59:42.926583 DATLAT Default: 0x9
4801 00:59:42.926995 0, 0xFFFF, sum = 0
4802 00:59:42.930448 1, 0xFFFF, sum = 0
4803 00:59:42.932897 2, 0xFFFF, sum = 0
4804 00:59:42.933327 3, 0xFFFF, sum = 0
4805 00:59:42.936117 4, 0xFFFF, sum = 0
4806 00:59:42.936548 5, 0xFFFF, sum = 0
4807 00:59:42.939634 6, 0xFFFF, sum = 0
4808 00:59:42.940115 7, 0xFFFF, sum = 0
4809 00:59:42.942877 8, 0x0, sum = 1
4810 00:59:42.943306 9, 0x0, sum = 2
4811 00:59:42.943762 10, 0x0, sum = 3
4812 00:59:42.946110 11, 0x0, sum = 4
4813 00:59:42.946540 best_step = 9
4814 00:59:42.946878
4815 00:59:42.949537 ==
4816 00:59:42.949961 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 00:59:42.956442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 00:59:42.956883 ==
4819 00:59:42.957249 RX Vref Scan: 0
4820 00:59:42.957566
4821 00:59:42.959340 RX Vref 0 -> 0, step: 1
4822 00:59:42.959797
4823 00:59:42.962322 RX Delay -195 -> 252, step: 8
4824 00:59:42.969188 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4825 00:59:42.973098 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4826 00:59:42.975392 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4827 00:59:42.978825 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4828 00:59:42.985537 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4829 00:59:42.988943 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4830 00:59:42.992203 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4831 00:59:42.995755 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4832 00:59:42.998585 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4833 00:59:43.005653 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4834 00:59:43.008503 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4835 00:59:43.012928 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4836 00:59:43.015428 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4837 00:59:43.021821 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4838 00:59:43.025017 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4839 00:59:43.029247 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4840 00:59:43.029729 ==
4841 00:59:43.032406 Dram Type= 6, Freq= 0, CH_1, rank 1
4842 00:59:43.035553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4843 00:59:43.036017 ==
4844 00:59:43.038615 DQS Delay:
4845 00:59:43.039029 DQS0 = 0, DQS1 = 0
4846 00:59:43.041877 DQM Delay:
4847 00:59:43.042293 DQM0 = 45, DQM1 = 37
4848 00:59:43.042624 DQ Delay:
4849 00:59:43.044866 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4850 00:59:43.048848 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4851 00:59:43.051506 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4852 00:59:43.055273 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4853 00:59:43.057942
4854 00:59:43.058355
4855 00:59:43.064760 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4856 00:59:43.067962 CH1 RK1: MR19=808, MR18=2D23
4857 00:59:43.074991 CH1_RK1: MR19=0x808, MR18=0x2D23, DQSOSC=401, MR23=63, INC=163, DEC=108
4858 00:59:43.078396 [RxdqsGatingPostProcess] freq 600
4859 00:59:43.081238 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4860 00:59:43.084366 Pre-setting of DQS Precalculation
4861 00:59:43.090927 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4862 00:59:43.097700 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4863 00:59:43.104348 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4864 00:59:43.104769
4865 00:59:43.105099
4866 00:59:43.107518 [Calibration Summary] 1200 Mbps
4867 00:59:43.108042 CH 0, Rank 0
4868 00:59:43.111058 SW Impedance : PASS
4869 00:59:43.114544 DUTY Scan : NO K
4870 00:59:43.114960 ZQ Calibration : PASS
4871 00:59:43.117652 Jitter Meter : NO K
4872 00:59:43.122325 CBT Training : PASS
4873 00:59:43.122744 Write leveling : PASS
4874 00:59:43.123972 RX DQS gating : PASS
4875 00:59:43.127031 RX DQ/DQS(RDDQC) : PASS
4876 00:59:43.127450 TX DQ/DQS : PASS
4877 00:59:43.130755 RX DATLAT : PASS
4878 00:59:43.133519 RX DQ/DQS(Engine): PASS
4879 00:59:43.133938 TX OE : NO K
4880 00:59:43.137187 All Pass.
4881 00:59:43.137603
4882 00:59:43.137934 CH 0, Rank 1
4883 00:59:43.140486 SW Impedance : PASS
4884 00:59:43.140903 DUTY Scan : NO K
4885 00:59:43.143640 ZQ Calibration : PASS
4886 00:59:43.147196 Jitter Meter : NO K
4887 00:59:43.147612 CBT Training : PASS
4888 00:59:43.150077 Write leveling : PASS
4889 00:59:43.153532 RX DQS gating : PASS
4890 00:59:43.153952 RX DQ/DQS(RDDQC) : PASS
4891 00:59:43.157163 TX DQ/DQS : PASS
4892 00:59:43.157582 RX DATLAT : PASS
4893 00:59:43.160176 RX DQ/DQS(Engine): PASS
4894 00:59:43.163664 TX OE : NO K
4895 00:59:43.164131 All Pass.
4896 00:59:43.164461
4897 00:59:43.164769 CH 1, Rank 0
4898 00:59:43.167247 SW Impedance : PASS
4899 00:59:43.169943 DUTY Scan : NO K
4900 00:59:43.170361 ZQ Calibration : PASS
4901 00:59:43.173366 Jitter Meter : NO K
4902 00:59:43.176490 CBT Training : PASS
4903 00:59:43.176908 Write leveling : PASS
4904 00:59:43.179943 RX DQS gating : PASS
4905 00:59:43.183725 RX DQ/DQS(RDDQC) : PASS
4906 00:59:43.184150 TX DQ/DQS : PASS
4907 00:59:43.186468 RX DATLAT : PASS
4908 00:59:43.190315 RX DQ/DQS(Engine): PASS
4909 00:59:43.190734 TX OE : NO K
4910 00:59:43.193170 All Pass.
4911 00:59:43.193586
4912 00:59:43.193914 CH 1, Rank 1
4913 00:59:43.196982 SW Impedance : PASS
4914 00:59:43.197399 DUTY Scan : NO K
4915 00:59:43.200207 ZQ Calibration : PASS
4916 00:59:43.202903 Jitter Meter : NO K
4917 00:59:43.203326 CBT Training : PASS
4918 00:59:43.206759 Write leveling : PASS
4919 00:59:43.210009 RX DQS gating : PASS
4920 00:59:43.210434 RX DQ/DQS(RDDQC) : PASS
4921 00:59:43.212857 TX DQ/DQS : PASS
4922 00:59:43.216342 RX DATLAT : PASS
4923 00:59:43.216765 RX DQ/DQS(Engine): PASS
4924 00:59:43.219708 TX OE : NO K
4925 00:59:43.220154 All Pass.
4926 00:59:43.220493
4927 00:59:43.223766 DramC Write-DBI off
4928 00:59:43.226466 PER_BANK_REFRESH: Hybrid Mode
4929 00:59:43.226884 TX_TRACKING: ON
4930 00:59:43.236514 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4931 00:59:43.239781 [FAST_K] Save calibration result to emmc
4932 00:59:43.243157 dramc_set_vcore_voltage set vcore to 662500
4933 00:59:43.246771 Read voltage for 933, 3
4934 00:59:43.247194 Vio18 = 0
4935 00:59:43.247527 Vcore = 662500
4936 00:59:43.249709 Vdram = 0
4937 00:59:43.250131 Vddq = 0
4938 00:59:43.250468 Vmddr = 0
4939 00:59:43.256221 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4940 00:59:43.259423 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4941 00:59:43.262530 MEM_TYPE=3, freq_sel=17
4942 00:59:43.266152 sv_algorithm_assistance_LP4_1600
4943 00:59:43.269279 ============ PULL DRAM RESETB DOWN ============
4944 00:59:43.272167 ========== PULL DRAM RESETB DOWN end =========
4945 00:59:43.278720 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4946 00:59:43.282323 ===================================
4947 00:59:43.282405 LPDDR4 DRAM CONFIGURATION
4948 00:59:43.285138 ===================================
4949 00:59:43.288770 EX_ROW_EN[0] = 0x0
4950 00:59:43.292198 EX_ROW_EN[1] = 0x0
4951 00:59:43.292297 LP4Y_EN = 0x0
4952 00:59:43.295051 WORK_FSP = 0x0
4953 00:59:43.295133 WL = 0x3
4954 00:59:43.298421 RL = 0x3
4955 00:59:43.298503 BL = 0x2
4956 00:59:43.301835 RPST = 0x0
4957 00:59:43.301917 RD_PRE = 0x0
4958 00:59:43.305299 WR_PRE = 0x1
4959 00:59:43.305382 WR_PST = 0x0
4960 00:59:43.308195 DBI_WR = 0x0
4961 00:59:43.308276 DBI_RD = 0x0
4962 00:59:43.311655 OTF = 0x1
4963 00:59:43.314805 ===================================
4964 00:59:43.318126 ===================================
4965 00:59:43.318208 ANA top config
4966 00:59:43.322149 ===================================
4967 00:59:43.324577 DLL_ASYNC_EN = 0
4968 00:59:43.328529 ALL_SLAVE_EN = 1
4969 00:59:43.331394 NEW_RANK_MODE = 1
4970 00:59:43.331476 DLL_IDLE_MODE = 1
4971 00:59:43.334578 LP45_APHY_COMB_EN = 1
4972 00:59:43.338083 TX_ODT_DIS = 1
4973 00:59:43.341299 NEW_8X_MODE = 1
4974 00:59:43.344371 ===================================
4975 00:59:43.348350 ===================================
4976 00:59:43.350882 data_rate = 1866
4977 00:59:43.354319 CKR = 1
4978 00:59:43.354406 DQ_P2S_RATIO = 8
4979 00:59:43.357635 ===================================
4980 00:59:43.360881 CA_P2S_RATIO = 8
4981 00:59:43.364293 DQ_CA_OPEN = 0
4982 00:59:43.367724 DQ_SEMI_OPEN = 0
4983 00:59:43.371449 CA_SEMI_OPEN = 0
4984 00:59:43.374491 CA_FULL_RATE = 0
4985 00:59:43.374572 DQ_CKDIV4_EN = 1
4986 00:59:43.377965 CA_CKDIV4_EN = 1
4987 00:59:43.380912 CA_PREDIV_EN = 0
4988 00:59:43.385305 PH8_DLY = 0
4989 00:59:43.387541 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4990 00:59:43.390863 DQ_AAMCK_DIV = 4
4991 00:59:43.390944 CA_AAMCK_DIV = 4
4992 00:59:43.394755 CA_ADMCK_DIV = 4
4993 00:59:43.397844 DQ_TRACK_CA_EN = 0
4994 00:59:43.401087 CA_PICK = 933
4995 00:59:43.404228 CA_MCKIO = 933
4996 00:59:43.407697 MCKIO_SEMI = 0
4997 00:59:43.410571 PLL_FREQ = 3732
4998 00:59:43.410656 DQ_UI_PI_RATIO = 32
4999 00:59:43.413969 CA_UI_PI_RATIO = 0
5000 00:59:43.417445 ===================================
5001 00:59:43.420389 ===================================
5002 00:59:43.423662 memory_type:LPDDR4
5003 00:59:43.426871 GP_NUM : 10
5004 00:59:43.426953 SRAM_EN : 1
5005 00:59:43.430965 MD32_EN : 0
5006 00:59:43.433849 ===================================
5007 00:59:43.437061 [ANA_INIT] >>>>>>>>>>>>>>
5008 00:59:43.437149 <<<<<< [CONFIGURE PHASE]: ANA_TX
5009 00:59:43.443536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5010 00:59:43.446733 ===================================
5011 00:59:43.446815 data_rate = 1866,PCW = 0X8f00
5012 00:59:43.450211 ===================================
5013 00:59:43.453649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5014 00:59:43.460025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 00:59:43.466568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 00:59:43.470472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5017 00:59:43.473430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5018 00:59:43.476722 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5019 00:59:43.479871 [ANA_INIT] flow start
5020 00:59:43.479953 [ANA_INIT] PLL >>>>>>>>
5021 00:59:43.483396 [ANA_INIT] PLL <<<<<<<<
5022 00:59:43.486618 [ANA_INIT] MIDPI >>>>>>>>
5023 00:59:43.489707 [ANA_INIT] MIDPI <<<<<<<<
5024 00:59:43.489788 [ANA_INIT] DLL >>>>>>>>
5025 00:59:43.493580 [ANA_INIT] flow end
5026 00:59:43.496455 ============ LP4 DIFF to SE enter ============
5027 00:59:43.499637 ============ LP4 DIFF to SE exit ============
5028 00:59:43.502854 [ANA_INIT] <<<<<<<<<<<<<
5029 00:59:43.506465 [Flow] Enable top DCM control >>>>>
5030 00:59:43.509529 [Flow] Enable top DCM control <<<<<
5031 00:59:43.513326 Enable DLL master slave shuffle
5032 00:59:43.519545 ==============================================================
5033 00:59:43.519692 Gating Mode config
5034 00:59:43.526043 ==============================================================
5035 00:59:43.526130 Config description:
5036 00:59:43.536149 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5037 00:59:43.542651 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5038 00:59:43.549641 SELPH_MODE 0: By rank 1: By Phase
5039 00:59:43.556028 ==============================================================
5040 00:59:43.556111 GAT_TRACK_EN = 1
5041 00:59:43.558901 RX_GATING_MODE = 2
5042 00:59:43.562168 RX_GATING_TRACK_MODE = 2
5043 00:59:43.566340 SELPH_MODE = 1
5044 00:59:43.568630 PICG_EARLY_EN = 1
5045 00:59:43.571881 VALID_LAT_VALUE = 1
5046 00:59:43.579178 ==============================================================
5047 00:59:43.582181 Enter into Gating configuration >>>>
5048 00:59:43.585725 Exit from Gating configuration <<<<
5049 00:59:43.588571 Enter into DVFS_PRE_config >>>>>
5050 00:59:43.599171 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5051 00:59:43.602322 Exit from DVFS_PRE_config <<<<<
5052 00:59:43.605218 Enter into PICG configuration >>>>
5053 00:59:43.608789 Exit from PICG configuration <<<<
5054 00:59:43.611950 [RX_INPUT] configuration >>>>>
5055 00:59:43.615040 [RX_INPUT] configuration <<<<<
5056 00:59:43.618183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5057 00:59:43.625321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5058 00:59:43.631636 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5059 00:59:43.634721 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5060 00:59:43.642144 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5061 00:59:43.648397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5062 00:59:43.652505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5063 00:59:43.658594 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5064 00:59:43.661693 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5065 00:59:43.665268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5066 00:59:43.667935 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5067 00:59:43.674871 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 00:59:43.677943 ===================================
5069 00:59:43.681549 LPDDR4 DRAM CONFIGURATION
5070 00:59:43.684251 ===================================
5071 00:59:43.684674 EX_ROW_EN[0] = 0x0
5072 00:59:43.688289 EX_ROW_EN[1] = 0x0
5073 00:59:43.688712 LP4Y_EN = 0x0
5074 00:59:43.691150 WORK_FSP = 0x0
5075 00:59:43.691573 WL = 0x3
5076 00:59:43.694451 RL = 0x3
5077 00:59:43.694893 BL = 0x2
5078 00:59:43.698067 RPST = 0x0
5079 00:59:43.698490 RD_PRE = 0x0
5080 00:59:43.701425 WR_PRE = 0x1
5081 00:59:43.701866 WR_PST = 0x0
5082 00:59:43.704588 DBI_WR = 0x0
5083 00:59:43.705009 DBI_RD = 0x0
5084 00:59:43.708110 OTF = 0x1
5085 00:59:43.711047 ===================================
5086 00:59:43.714446 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5087 00:59:43.717516 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5088 00:59:43.724052 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 00:59:43.727618 ===================================
5090 00:59:43.731511 LPDDR4 DRAM CONFIGURATION
5091 00:59:43.734016 ===================================
5092 00:59:43.734542 EX_ROW_EN[0] = 0x10
5093 00:59:43.737313 EX_ROW_EN[1] = 0x0
5094 00:59:43.737927 LP4Y_EN = 0x0
5095 00:59:43.741428 WORK_FSP = 0x0
5096 00:59:43.741989 WL = 0x3
5097 00:59:43.744337 RL = 0x3
5098 00:59:43.744777 BL = 0x2
5099 00:59:43.747109 RPST = 0x0
5100 00:59:43.747618 RD_PRE = 0x0
5101 00:59:43.750953 WR_PRE = 0x1
5102 00:59:43.751395 WR_PST = 0x0
5103 00:59:43.753956 DBI_WR = 0x0
5104 00:59:43.754411 DBI_RD = 0x0
5105 00:59:43.757151 OTF = 0x1
5106 00:59:43.760728 ===================================
5107 00:59:43.766934 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5108 00:59:43.770462 nWR fixed to 30
5109 00:59:43.774095 [ModeRegInit_LP4] CH0 RK0
5110 00:59:43.774555 [ModeRegInit_LP4] CH0 RK1
5111 00:59:43.777213 [ModeRegInit_LP4] CH1 RK0
5112 00:59:43.780524 [ModeRegInit_LP4] CH1 RK1
5113 00:59:43.781032 match AC timing 9
5114 00:59:43.786865 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5115 00:59:43.790445 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5116 00:59:43.793354 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5117 00:59:43.800405 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5118 00:59:43.803153 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5119 00:59:43.803740 ==
5120 00:59:43.806876 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 00:59:43.810367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 00:59:43.810825 ==
5123 00:59:43.816441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 00:59:43.823561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 00:59:43.826805 [CA 0] Center 37 (7~68) winsize 62
5126 00:59:43.829662 [CA 1] Center 37 (7~68) winsize 62
5127 00:59:43.832892 [CA 2] Center 34 (4~65) winsize 62
5128 00:59:43.836352 [CA 3] Center 35 (5~65) winsize 61
5129 00:59:43.839744 [CA 4] Center 33 (3~64) winsize 62
5130 00:59:43.843001 [CA 5] Center 33 (3~63) winsize 61
5131 00:59:43.843531
5132 00:59:43.846195 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 00:59:43.846765
5134 00:59:43.849953 [CATrainingPosCal] consider 1 rank data
5135 00:59:43.853372 u2DelayCellTimex100 = 270/100 ps
5136 00:59:43.856088 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5137 00:59:43.859573 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5138 00:59:43.862795 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5139 00:59:43.869506 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5140 00:59:43.873402 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5141 00:59:43.875936 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5142 00:59:43.876322
5143 00:59:43.879718 CA PerBit enable=1, Macro0, CA PI delay=33
5144 00:59:43.880185
5145 00:59:43.882752 [CBTSetCACLKResult] CA Dly = 33
5146 00:59:43.883151 CS Dly: 7 (0~38)
5147 00:59:43.883516 ==
5148 00:59:43.886068 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 00:59:43.892170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 00:59:43.892592 ==
5151 00:59:43.895600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 00:59:43.903288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5153 00:59:43.905907 [CA 0] Center 37 (7~68) winsize 62
5154 00:59:43.909223 [CA 1] Center 37 (7~68) winsize 62
5155 00:59:43.912245 [CA 2] Center 34 (4~65) winsize 62
5156 00:59:43.915752 [CA 3] Center 34 (4~65) winsize 62
5157 00:59:43.918491 [CA 4] Center 33 (3~64) winsize 62
5158 00:59:43.921871 [CA 5] Center 33 (3~63) winsize 61
5159 00:59:43.922262
5160 00:59:43.925260 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5161 00:59:43.925677
5162 00:59:43.928301 [CATrainingPosCal] consider 2 rank data
5163 00:59:43.931892 u2DelayCellTimex100 = 270/100 ps
5164 00:59:43.935471 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5165 00:59:43.941767 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5166 00:59:43.945250 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5167 00:59:43.948423 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5168 00:59:43.951772 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5169 00:59:43.954760 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5170 00:59:43.955178
5171 00:59:43.958427 CA PerBit enable=1, Macro0, CA PI delay=33
5172 00:59:43.958878
5173 00:59:43.962074 [CBTSetCACLKResult] CA Dly = 33
5174 00:59:43.965595 CS Dly: 7 (0~39)
5175 00:59:43.966009
5176 00:59:43.968571 ----->DramcWriteLeveling(PI) begin...
5177 00:59:43.968997 ==
5178 00:59:43.971761 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 00:59:43.974728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 00:59:43.975147 ==
5181 00:59:43.978071 Write leveling (Byte 0): 32 => 32
5182 00:59:43.981900 Write leveling (Byte 1): 29 => 29
5183 00:59:43.984767 DramcWriteLeveling(PI) end<-----
5184 00:59:43.985203
5185 00:59:43.985699 ==
5186 00:59:43.987803 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 00:59:43.991425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 00:59:43.991890 ==
5189 00:59:43.994607 [Gating] SW mode calibration
5190 00:59:44.000755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5191 00:59:44.007421 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5192 00:59:44.011477 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5193 00:59:44.017786 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5194 00:59:44.021337 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 00:59:44.024270 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 00:59:44.027880 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 00:59:44.034817 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 00:59:44.037090 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 00:59:44.040971 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
5200 00:59:44.047107 0 15 0 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
5201 00:59:44.050847 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 00:59:44.053711 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 00:59:44.060174 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 00:59:44.063461 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 00:59:44.070129 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 00:59:44.073542 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 00:59:44.076429 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5208 00:59:44.083094 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
5209 00:59:44.086320 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 00:59:44.090757 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 00:59:44.096667 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 00:59:44.099621 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 00:59:44.103768 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 00:59:44.110023 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 00:59:44.113095 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5216 00:59:44.116149 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5217 00:59:44.123130 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 00:59:44.126090 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 00:59:44.129676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 00:59:44.133005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 00:59:44.139728 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 00:59:44.142449 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 00:59:44.145930 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 00:59:44.152459 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 00:59:44.156757 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 00:59:44.159320 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 00:59:44.166367 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 00:59:44.168814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 00:59:44.172729 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 00:59:44.178942 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 00:59:44.182519 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5232 00:59:44.188870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5233 00:59:44.189310 Total UI for P1: 0, mck2ui 16
5234 00:59:44.192507 best dqsien dly found for B0: ( 1, 2, 28)
5235 00:59:44.198661 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 00:59:44.202127 Total UI for P1: 0, mck2ui 16
5237 00:59:44.205418 best dqsien dly found for B1: ( 1, 3, 0)
5238 00:59:44.208713 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5239 00:59:44.211857 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5240 00:59:44.212277
5241 00:59:44.215065 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5242 00:59:44.218629 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5243 00:59:44.222127 [Gating] SW calibration Done
5244 00:59:44.222721 ==
5245 00:59:44.225713 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 00:59:44.228614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 00:59:44.229050 ==
5248 00:59:44.231988 RX Vref Scan: 0
5249 00:59:44.232409
5250 00:59:44.234888 RX Vref 0 -> 0, step: 1
5251 00:59:44.235377
5252 00:59:44.235766 RX Delay -80 -> 252, step: 8
5253 00:59:44.241764 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5254 00:59:44.245166 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5255 00:59:44.248568 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5256 00:59:44.252003 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5257 00:59:44.255116 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5258 00:59:44.258314 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5259 00:59:44.264572 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5260 00:59:44.267912 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5261 00:59:44.271308 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5262 00:59:44.274482 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5263 00:59:44.277940 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5264 00:59:44.284189 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5265 00:59:44.287519 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5266 00:59:44.290879 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5267 00:59:44.294414 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5268 00:59:44.297316 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5269 00:59:44.297398 ==
5270 00:59:44.300475 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 00:59:44.307845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 00:59:44.307928 ==
5273 00:59:44.307993 DQS Delay:
5274 00:59:44.310495 DQS0 = 0, DQS1 = 0
5275 00:59:44.310576 DQM Delay:
5276 00:59:44.313860 DQM0 = 97, DQM1 = 86
5277 00:59:44.313941 DQ Delay:
5278 00:59:44.316857 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5279 00:59:44.320643 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5280 00:59:44.324066 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =79
5281 00:59:44.327287 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5282 00:59:44.327368
5283 00:59:44.327432
5284 00:59:44.327492 ==
5285 00:59:44.330798 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 00:59:44.333887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 00:59:44.333969 ==
5288 00:59:44.334033
5289 00:59:44.334092
5290 00:59:44.337069 TX Vref Scan disable
5291 00:59:44.340532 == TX Byte 0 ==
5292 00:59:44.343181 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5293 00:59:44.346728 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5294 00:59:44.351380 == TX Byte 1 ==
5295 00:59:44.353637 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5296 00:59:44.357176 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5297 00:59:44.357256 ==
5298 00:59:44.360877 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 00:59:44.366727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 00:59:44.366808 ==
5301 00:59:44.366872
5302 00:59:44.366931
5303 00:59:44.366988 TX Vref Scan disable
5304 00:59:44.370818 == TX Byte 0 ==
5305 00:59:44.373925 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5306 00:59:44.381044 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5307 00:59:44.381126 == TX Byte 1 ==
5308 00:59:44.383945 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5309 00:59:44.391314 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5310 00:59:44.391395
5311 00:59:44.391459 [DATLAT]
5312 00:59:44.391519 Freq=933, CH0 RK0
5313 00:59:44.391577
5314 00:59:44.394104 DATLAT Default: 0xd
5315 00:59:44.397129 0, 0xFFFF, sum = 0
5316 00:59:44.397217 1, 0xFFFF, sum = 0
5317 00:59:44.400487 2, 0xFFFF, sum = 0
5318 00:59:44.400582 3, 0xFFFF, sum = 0
5319 00:59:44.403610 4, 0xFFFF, sum = 0
5320 00:59:44.403712 5, 0xFFFF, sum = 0
5321 00:59:44.406960 6, 0xFFFF, sum = 0
5322 00:59:44.407139 7, 0xFFFF, sum = 0
5323 00:59:44.410337 8, 0xFFFF, sum = 0
5324 00:59:44.410526 9, 0xFFFF, sum = 0
5325 00:59:44.414615 10, 0x0, sum = 1
5326 00:59:44.414816 11, 0x0, sum = 2
5327 00:59:44.417274 12, 0x0, sum = 3
5328 00:59:44.417475 13, 0x0, sum = 4
5329 00:59:44.420227 best_step = 11
5330 00:59:44.420399
5331 00:59:44.420505 ==
5332 00:59:44.423601 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 00:59:44.426594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 00:59:44.426744 ==
5335 00:59:44.426861 RX Vref Scan: 1
5336 00:59:44.430452
5337 00:59:44.430701 RX Vref 0 -> 0, step: 1
5338 00:59:44.430844
5339 00:59:44.433954 RX Delay -61 -> 252, step: 4
5340 00:59:44.434239
5341 00:59:44.436582 Set Vref, RX VrefLevel [Byte0]: 60
5342 00:59:44.440321 [Byte1]: 49
5343 00:59:44.444261
5344 00:59:44.444649 Final RX Vref Byte 0 = 60 to rank0
5345 00:59:44.446948 Final RX Vref Byte 1 = 49 to rank0
5346 00:59:44.450242 Final RX Vref Byte 0 = 60 to rank1
5347 00:59:44.453028 Final RX Vref Byte 1 = 49 to rank1==
5348 00:59:44.456797 Dram Type= 6, Freq= 0, CH_0, rank 0
5349 00:59:44.463572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 00:59:44.463654 ==
5351 00:59:44.463730 DQS Delay:
5352 00:59:44.466253 DQS0 = 0, DQS1 = 0
5353 00:59:44.466334 DQM Delay:
5354 00:59:44.466399 DQM0 = 96, DQM1 = 85
5355 00:59:44.469403 DQ Delay:
5356 00:59:44.473092 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5357 00:59:44.476414 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5358 00:59:44.479168 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5359 00:59:44.482709 DQ12 =88, DQ13 =90, DQ14 =96, DQ15 =92
5360 00:59:44.482790
5361 00:59:44.482852
5362 00:59:44.489480 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5363 00:59:44.492359 CH0 RK0: MR19=505, MR18=2F15
5364 00:59:44.499387 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5365 00:59:44.499857
5366 00:59:44.502742 ----->DramcWriteLeveling(PI) begin...
5367 00:59:44.503167 ==
5368 00:59:44.506513 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 00:59:44.509853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 00:59:44.510384 ==
5371 00:59:44.513520 Write leveling (Byte 0): 32 => 32
5372 00:59:44.516271 Write leveling (Byte 1): 31 => 31
5373 00:59:44.519544 DramcWriteLeveling(PI) end<-----
5374 00:59:44.520044
5375 00:59:44.520407 ==
5376 00:59:44.522481 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 00:59:44.529365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 00:59:44.529830 ==
5379 00:59:44.530194 [Gating] SW mode calibration
5380 00:59:44.538904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5381 00:59:44.542552 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5382 00:59:44.549236 0 14 0 | B1->B0 | 2828 3333 | 1 0 | (1 1) (0 0)
5383 00:59:44.552119 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 00:59:44.554990 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 00:59:44.562277 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 00:59:44.565052 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 00:59:44.568995 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 00:59:44.575487 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5389 00:59:44.577998 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
5390 00:59:44.581165 0 15 0 | B1->B0 | 2d2d 2727 | 0 0 | (0 1) (1 1)
5391 00:59:44.588318 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 00:59:44.591043 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 00:59:44.595093 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 00:59:44.600864 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 00:59:44.604145 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 00:59:44.607594 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 00:59:44.614070 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5398 00:59:44.617763 1 0 0 | B1->B0 | 403f 4646 | 1 0 | (0 0) (0 0)
5399 00:59:44.620854 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 00:59:44.627573 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 00:59:44.630965 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 00:59:44.634253 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 00:59:44.640717 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 00:59:44.643668 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 00:59:44.647013 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5406 00:59:44.653662 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5407 00:59:44.657290 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 00:59:44.660183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 00:59:44.666982 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 00:59:44.670810 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 00:59:44.673637 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 00:59:44.680306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 00:59:44.683802 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 00:59:44.686859 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 00:59:44.693298 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 00:59:44.696870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 00:59:44.700186 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 00:59:44.706990 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 00:59:44.710402 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 00:59:44.712799 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 00:59:44.720084 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5422 00:59:44.722980 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5423 00:59:44.726159 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 00:59:44.729197 Total UI for P1: 0, mck2ui 16
5425 00:59:44.732392 best dqsien dly found for B0: ( 1, 2, 30)
5426 00:59:44.736068 Total UI for P1: 0, mck2ui 16
5427 00:59:44.739520 best dqsien dly found for B1: ( 1, 3, 2)
5428 00:59:44.742605 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5429 00:59:44.746536 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5430 00:59:44.747068
5431 00:59:44.752558 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5432 00:59:44.755899 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5433 00:59:44.756328 [Gating] SW calibration Done
5434 00:59:44.759497 ==
5435 00:59:44.763073 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 00:59:44.765803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 00:59:44.766271 ==
5438 00:59:44.766640 RX Vref Scan: 0
5439 00:59:44.766979
5440 00:59:44.769427 RX Vref 0 -> 0, step: 1
5441 00:59:44.769889
5442 00:59:44.772239 RX Delay -80 -> 252, step: 8
5443 00:59:44.776337 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5444 00:59:44.778849 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5445 00:59:44.782452 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5446 00:59:44.788719 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5447 00:59:44.792003 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5448 00:59:44.795078 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5449 00:59:44.798622 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5450 00:59:44.801917 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5451 00:59:44.805087 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5452 00:59:44.811467 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5453 00:59:44.815088 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5454 00:59:44.818205 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5455 00:59:44.821607 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5456 00:59:44.826283 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5457 00:59:44.832040 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5458 00:59:44.834829 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5459 00:59:44.835002 ==
5460 00:59:44.838521 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 00:59:44.841786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 00:59:44.841967 ==
5463 00:59:44.844631 DQS Delay:
5464 00:59:44.844818 DQS0 = 0, DQS1 = 0
5465 00:59:44.844915 DQM Delay:
5466 00:59:44.848361 DQM0 = 96, DQM1 = 87
5467 00:59:44.848539 DQ Delay:
5468 00:59:44.851549 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5469 00:59:44.854845 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5470 00:59:44.858380 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5471 00:59:44.861114 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5472 00:59:44.861318
5473 00:59:44.861501
5474 00:59:44.865242 ==
5475 00:59:44.865486 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 00:59:44.871297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 00:59:44.871502 ==
5478 00:59:44.871663
5479 00:59:44.871838
5480 00:59:44.874745 TX Vref Scan disable
5481 00:59:44.874982 == TX Byte 0 ==
5482 00:59:44.878961 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5483 00:59:44.885090 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5484 00:59:44.885519 == TX Byte 1 ==
5485 00:59:44.888029 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5486 00:59:44.895103 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5487 00:59:44.895491 ==
5488 00:59:44.898386 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 00:59:44.901502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 00:59:44.901884 ==
5491 00:59:44.902196
5492 00:59:44.902476
5493 00:59:44.904674 TX Vref Scan disable
5494 00:59:44.908517 == TX Byte 0 ==
5495 00:59:44.911917 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5496 00:59:44.914946 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5497 00:59:44.917984 == TX Byte 1 ==
5498 00:59:44.921318 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5499 00:59:44.924679 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5500 00:59:44.925256
5501 00:59:44.927907 [DATLAT]
5502 00:59:44.928545 Freq=933, CH0 RK1
5503 00:59:44.929012
5504 00:59:44.930898 DATLAT Default: 0xb
5505 00:59:44.931480 0, 0xFFFF, sum = 0
5506 00:59:44.934039 1, 0xFFFF, sum = 0
5507 00:59:44.934150 2, 0xFFFF, sum = 0
5508 00:59:44.937068 3, 0xFFFF, sum = 0
5509 00:59:44.937151 4, 0xFFFF, sum = 0
5510 00:59:44.940491 5, 0xFFFF, sum = 0
5511 00:59:44.940573 6, 0xFFFF, sum = 0
5512 00:59:44.943937 7, 0xFFFF, sum = 0
5513 00:59:44.944014 8, 0xFFFF, sum = 0
5514 00:59:44.946805 9, 0xFFFF, sum = 0
5515 00:59:44.946909 10, 0x0, sum = 1
5516 00:59:44.950428 11, 0x0, sum = 2
5517 00:59:44.950540 12, 0x0, sum = 3
5518 00:59:44.953772 13, 0x0, sum = 4
5519 00:59:44.953848 best_step = 11
5520 00:59:44.953908
5521 00:59:44.953985 ==
5522 00:59:44.957741 Dram Type= 6, Freq= 0, CH_0, rank 1
5523 00:59:44.963370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 00:59:44.963474 ==
5525 00:59:44.963576 RX Vref Scan: 0
5526 00:59:44.963665
5527 00:59:44.966887 RX Vref 0 -> 0, step: 1
5528 00:59:44.966958
5529 00:59:44.970433 RX Delay -61 -> 252, step: 4
5530 00:59:44.973623 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5531 00:59:44.976589 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5532 00:59:44.983571 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5533 00:59:44.987199 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5534 00:59:44.990061 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5535 00:59:44.993445 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5536 00:59:44.997141 iDelay=203, Bit 6, Center 108 (15 ~ 202) 188
5537 00:59:45.003876 iDelay=203, Bit 7, Center 102 (7 ~ 198) 192
5538 00:59:45.007399 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5539 00:59:45.010259 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5540 00:59:45.013358 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5541 00:59:45.016423 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5542 00:59:45.023642 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5543 00:59:45.026586 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5544 00:59:45.029731 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5545 00:59:45.032952 iDelay=203, Bit 15, Center 90 (-5 ~ 186) 192
5546 00:59:45.033246 ==
5547 00:59:45.036299 Dram Type= 6, Freq= 0, CH_0, rank 1
5548 00:59:45.039936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 00:59:45.042819 ==
5550 00:59:45.043376 DQS Delay:
5551 00:59:45.043886 DQS0 = 0, DQS1 = 0
5552 00:59:45.046475 DQM Delay:
5553 00:59:45.047178 DQM0 = 95, DQM1 = 86
5554 00:59:45.049696 DQ Delay:
5555 00:59:45.052937 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5556 00:59:45.056454 DQ4 =96, DQ5 =86, DQ6 =108, DQ7 =102
5557 00:59:45.057133 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5558 00:59:45.062642 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =90
5559 00:59:45.063297
5560 00:59:45.063956
5561 00:59:45.069207 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5562 00:59:45.072333 CH0 RK1: MR19=504, MR18=28F8
5563 00:59:45.079270 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5564 00:59:45.083103 [RxdqsGatingPostProcess] freq 933
5565 00:59:45.085656 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5566 00:59:45.089523 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 00:59:45.092486 best DQS1 dly(2T, 0.5T) = (0, 11)
5568 00:59:45.096055 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 00:59:45.099028 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5570 00:59:45.102865 best DQS0 dly(2T, 0.5T) = (0, 10)
5571 00:59:45.105790 best DQS1 dly(2T, 0.5T) = (0, 11)
5572 00:59:45.109181 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5573 00:59:45.112644 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5574 00:59:45.115531 Pre-setting of DQS Precalculation
5575 00:59:45.119074 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5576 00:59:45.119590 ==
5577 00:59:45.122307 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 00:59:45.128680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 00:59:45.129106 ==
5580 00:59:45.131938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 00:59:45.138979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5582 00:59:45.142153 [CA 0] Center 37 (7~67) winsize 61
5583 00:59:45.145195 [CA 1] Center 37 (7~68) winsize 62
5584 00:59:45.148797 [CA 2] Center 34 (4~65) winsize 62
5585 00:59:45.151918 [CA 3] Center 33 (3~64) winsize 62
5586 00:59:45.156245 [CA 4] Center 34 (4~65) winsize 62
5587 00:59:45.158513 [CA 5] Center 33 (3~64) winsize 62
5588 00:59:45.158932
5589 00:59:45.161980 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5590 00:59:45.162401
5591 00:59:45.165313 [CATrainingPosCal] consider 1 rank data
5592 00:59:45.168841 u2DelayCellTimex100 = 270/100 ps
5593 00:59:45.171775 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5594 00:59:45.178629 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5595 00:59:45.182931 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5596 00:59:45.186030 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5597 00:59:45.188405 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5598 00:59:45.191441 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 00:59:45.191975
5600 00:59:45.195352 CA PerBit enable=1, Macro0, CA PI delay=33
5601 00:59:45.195984
5602 00:59:45.198544 [CBTSetCACLKResult] CA Dly = 33
5603 00:59:45.201663 CS Dly: 6 (0~37)
5604 00:59:45.202079 ==
5605 00:59:45.204739 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 00:59:45.208042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 00:59:45.208478 ==
5608 00:59:45.214873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5609 00:59:45.218169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5610 00:59:45.221619 [CA 0] Center 36 (6~67) winsize 62
5611 00:59:45.225501 [CA 1] Center 37 (7~68) winsize 62
5612 00:59:45.228468 [CA 2] Center 34 (4~65) winsize 62
5613 00:59:45.232124 [CA 3] Center 34 (4~65) winsize 62
5614 00:59:45.234746 [CA 4] Center 34 (4~65) winsize 62
5615 00:59:45.237863 [CA 5] Center 33 (3~64) winsize 62
5616 00:59:45.238296
5617 00:59:45.241439 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5618 00:59:45.241854
5619 00:59:45.247903 [CATrainingPosCal] consider 2 rank data
5620 00:59:45.248464 u2DelayCellTimex100 = 270/100 ps
5621 00:59:45.254429 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5622 00:59:45.257628 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5623 00:59:45.261144 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5624 00:59:45.264561 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5625 00:59:45.268742 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5626 00:59:45.270858 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5627 00:59:45.271375
5628 00:59:45.274470 CA PerBit enable=1, Macro0, CA PI delay=33
5629 00:59:45.275024
5630 00:59:45.277821 [CBTSetCACLKResult] CA Dly = 33
5631 00:59:45.281473 CS Dly: 7 (0~39)
5632 00:59:45.282000
5633 00:59:45.284734 ----->DramcWriteLeveling(PI) begin...
5634 00:59:45.285156 ==
5635 00:59:45.287221 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 00:59:45.290565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 00:59:45.291117 ==
5638 00:59:45.293817 Write leveling (Byte 0): 25 => 25
5639 00:59:45.297591 Write leveling (Byte 1): 29 => 29
5640 00:59:45.300599 DramcWriteLeveling(PI) end<-----
5641 00:59:45.301134
5642 00:59:45.301678 ==
5643 00:59:45.303873 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 00:59:45.306972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 00:59:45.307584 ==
5646 00:59:45.310502 [Gating] SW mode calibration
5647 00:59:45.317170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5648 00:59:45.323957 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5649 00:59:45.326960 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 00:59:45.333764 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 00:59:45.336693 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 00:59:45.340474 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 00:59:45.347605 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 00:59:45.350622 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 00:59:45.353295 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5656 00:59:45.360999 0 14 28 | B1->B0 | 2d2d 2828 | 0 0 | (1 0) (1 0)
5657 00:59:45.363273 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 00:59:45.367351 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 00:59:45.373182 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 00:59:45.376978 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 00:59:45.380535 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 00:59:45.386795 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 00:59:45.389878 0 15 24 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
5664 00:59:45.393011 0 15 28 | B1->B0 | 3232 3838 | 1 0 | (0 0) (0 0)
5665 00:59:45.399858 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 00:59:45.403215 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 00:59:45.406751 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 00:59:45.413310 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 00:59:45.416521 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 00:59:45.419377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 00:59:45.426078 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5672 00:59:45.429875 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5673 00:59:45.432812 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 00:59:45.439139 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 00:59:45.443324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 00:59:45.446121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 00:59:45.452913 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 00:59:45.456301 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 00:59:45.459336 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 00:59:45.465846 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 00:59:45.469167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 00:59:45.472338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 00:59:45.478985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 00:59:45.481909 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 00:59:45.485462 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 00:59:45.492165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5687 00:59:45.495407 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5688 00:59:45.498572 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 00:59:45.502081 Total UI for P1: 0, mck2ui 16
5690 00:59:45.505363 best dqsien dly found for B0: ( 1, 2, 22)
5691 00:59:45.508942 Total UI for P1: 0, mck2ui 16
5692 00:59:45.512522 best dqsien dly found for B1: ( 1, 2, 24)
5693 00:59:45.515492 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5694 00:59:45.518926 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5695 00:59:45.519341
5696 00:59:45.522104 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5697 00:59:45.528411 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5698 00:59:45.528832 [Gating] SW calibration Done
5699 00:59:45.529165 ==
5700 00:59:45.532379 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 00:59:45.538368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 00:59:45.538791 ==
5703 00:59:45.539125 RX Vref Scan: 0
5704 00:59:45.539435
5705 00:59:45.542087 RX Vref 0 -> 0, step: 1
5706 00:59:45.542603
5707 00:59:45.544912 RX Delay -80 -> 252, step: 8
5708 00:59:45.549301 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5709 00:59:45.551658 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5710 00:59:45.555453 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5711 00:59:45.558500 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5712 00:59:45.565269 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5713 00:59:45.568444 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5714 00:59:45.571902 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5715 00:59:45.574858 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5716 00:59:45.578251 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5717 00:59:45.584499 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5718 00:59:45.588026 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5719 00:59:45.591244 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5720 00:59:45.594790 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5721 00:59:45.598330 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5722 00:59:45.604628 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5723 00:59:45.607615 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5724 00:59:45.608200 ==
5725 00:59:45.610820 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 00:59:45.614201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 00:59:45.614622 ==
5728 00:59:45.618076 DQS Delay:
5729 00:59:45.618553 DQS0 = 0, DQS1 = 0
5730 00:59:45.618893 DQM Delay:
5731 00:59:45.621412 DQM0 = 102, DQM1 = 93
5732 00:59:45.621935 DQ Delay:
5733 00:59:45.624436 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5734 00:59:45.627337 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5735 00:59:45.630923 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =79
5736 00:59:45.634021 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5737 00:59:45.634439
5738 00:59:45.634869
5739 00:59:45.637591 ==
5740 00:59:45.640711 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 00:59:45.644035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 00:59:45.644497 ==
5743 00:59:45.644858
5744 00:59:45.645170
5745 00:59:45.647120 TX Vref Scan disable
5746 00:59:45.647536 == TX Byte 0 ==
5747 00:59:45.650611 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5748 00:59:45.657111 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5749 00:59:45.657538 == TX Byte 1 ==
5750 00:59:45.660230 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 00:59:45.667048 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 00:59:45.667472 ==
5753 00:59:45.670012 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 00:59:45.673890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 00:59:45.674309 ==
5756 00:59:45.674637
5757 00:59:45.674946
5758 00:59:45.676941 TX Vref Scan disable
5759 00:59:45.680185 == TX Byte 0 ==
5760 00:59:45.683448 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5761 00:59:45.687009 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5762 00:59:45.690004 == TX Byte 1 ==
5763 00:59:45.693183 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5764 00:59:45.696830 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5765 00:59:45.697540
5766 00:59:45.700266 [DATLAT]
5767 00:59:45.700778 Freq=933, CH1 RK0
5768 00:59:45.701146
5769 00:59:45.703268 DATLAT Default: 0xd
5770 00:59:45.703792 0, 0xFFFF, sum = 0
5771 00:59:45.706723 1, 0xFFFF, sum = 0
5772 00:59:45.707196 2, 0xFFFF, sum = 0
5773 00:59:45.710165 3, 0xFFFF, sum = 0
5774 00:59:45.710581 4, 0xFFFF, sum = 0
5775 00:59:45.713190 5, 0xFFFF, sum = 0
5776 00:59:45.713611 6, 0xFFFF, sum = 0
5777 00:59:45.716589 7, 0xFFFF, sum = 0
5778 00:59:45.717037 8, 0xFFFF, sum = 0
5779 00:59:45.719964 9, 0xFFFF, sum = 0
5780 00:59:45.720391 10, 0x0, sum = 1
5781 00:59:45.723141 11, 0x0, sum = 2
5782 00:59:45.723729 12, 0x0, sum = 3
5783 00:59:45.726242 13, 0x0, sum = 4
5784 00:59:45.726666 best_step = 11
5785 00:59:45.726998
5786 00:59:45.727307 ==
5787 00:59:45.729527 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 00:59:45.736236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 00:59:45.736788 ==
5790 00:59:45.737227 RX Vref Scan: 1
5791 00:59:45.737551
5792 00:59:45.739212 RX Vref 0 -> 0, step: 1
5793 00:59:45.739629
5794 00:59:45.743115 RX Delay -61 -> 252, step: 4
5795 00:59:45.743532
5796 00:59:45.746222 Set Vref, RX VrefLevel [Byte0]: 50
5797 00:59:45.749702 [Byte1]: 54
5798 00:59:45.750121
5799 00:59:45.752409 Final RX Vref Byte 0 = 50 to rank0
5800 00:59:45.755862 Final RX Vref Byte 1 = 54 to rank0
5801 00:59:45.759283 Final RX Vref Byte 0 = 50 to rank1
5802 00:59:45.763354 Final RX Vref Byte 1 = 54 to rank1==
5803 00:59:45.765672 Dram Type= 6, Freq= 0, CH_1, rank 0
5804 00:59:45.769422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 00:59:45.769844 ==
5806 00:59:45.772474 DQS Delay:
5807 00:59:45.772891 DQS0 = 0, DQS1 = 0
5808 00:59:45.776037 DQM Delay:
5809 00:59:45.776455 DQM0 = 101, DQM1 = 94
5810 00:59:45.779000 DQ Delay:
5811 00:59:45.779415 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5812 00:59:45.783151 DQ4 =98, DQ5 =112, DQ6 =112, DQ7 =96
5813 00:59:45.785918 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =84
5814 00:59:45.792194 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5815 00:59:45.792641
5816 00:59:45.793009
5817 00:59:45.799192 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5818 00:59:45.802385 CH1 RK0: MR19=505, MR18=1909
5819 00:59:45.808636 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5820 00:59:45.809058
5821 00:59:45.811715 ----->DramcWriteLeveling(PI) begin...
5822 00:59:45.812147 ==
5823 00:59:45.815190 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 00:59:45.818364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 00:59:45.818854 ==
5826 00:59:45.821701 Write leveling (Byte 0): 28 => 28
5827 00:59:45.825218 Write leveling (Byte 1): 29 => 29
5828 00:59:45.828293 DramcWriteLeveling(PI) end<-----
5829 00:59:45.828709
5830 00:59:45.829042 ==
5831 00:59:45.831232 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 00:59:45.836183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 00:59:45.838302 ==
5834 00:59:45.838799 [Gating] SW mode calibration
5835 00:59:45.844717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5836 00:59:45.852205 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5837 00:59:45.855215 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
5838 00:59:45.861418 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 00:59:45.865176 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 00:59:45.867818 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 00:59:45.874728 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 00:59:45.878305 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 00:59:45.881757 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (1 0) (1 1)
5844 00:59:45.888374 0 14 28 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 1)
5845 00:59:45.890909 0 15 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5846 00:59:45.894319 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 00:59:45.901761 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 00:59:45.904851 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 00:59:45.907496 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 00:59:45.914238 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 00:59:45.917354 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5852 00:59:45.920618 0 15 28 | B1->B0 | 3b3b 2e2e | 0 0 | (0 0) (0 0)
5853 00:59:45.927752 1 0 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5854 00:59:45.930809 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 00:59:45.933483 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 00:59:45.940018 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 00:59:45.943512 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 00:59:45.946597 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 00:59:45.953921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5860 00:59:45.957164 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5861 00:59:45.961002 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 00:59:45.966724 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 00:59:45.969929 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 00:59:45.973901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 00:59:45.980263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 00:59:45.983525 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 00:59:45.986772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 00:59:45.992983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 00:59:45.996047 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 00:59:45.999645 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 00:59:46.006414 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 00:59:46.009345 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 00:59:46.012625 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 00:59:46.019379 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5875 00:59:46.022735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5876 00:59:46.026089 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5877 00:59:46.029586 Total UI for P1: 0, mck2ui 16
5878 00:59:46.032688 best dqsien dly found for B1: ( 1, 2, 22)
5879 00:59:46.039488 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 00:59:46.039963 Total UI for P1: 0, mck2ui 16
5881 00:59:46.045928 best dqsien dly found for B0: ( 1, 2, 28)
5882 00:59:46.049514 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5883 00:59:46.053151 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5884 00:59:46.053670
5885 00:59:46.056263 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5886 00:59:46.059005 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5887 00:59:46.062758 [Gating] SW calibration Done
5888 00:59:46.063277 ==
5889 00:59:46.065804 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 00:59:46.068892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 00:59:46.069315 ==
5892 00:59:46.072764 RX Vref Scan: 0
5893 00:59:46.073181
5894 00:59:46.073512 RX Vref 0 -> 0, step: 1
5895 00:59:46.075910
5896 00:59:46.076327 RX Delay -80 -> 252, step: 8
5897 00:59:46.082146 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5898 00:59:46.085794 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5899 00:59:46.088651 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5900 00:59:46.093444 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5901 00:59:46.095633 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5902 00:59:46.098806 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5903 00:59:46.105469 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5904 00:59:46.108727 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5905 00:59:46.111668 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5906 00:59:46.114960 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5907 00:59:46.118536 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5908 00:59:46.125042 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5909 00:59:46.128673 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5910 00:59:46.131842 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5911 00:59:46.135173 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5912 00:59:46.138077 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5913 00:59:46.138509 ==
5914 00:59:46.141408 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 00:59:46.147898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 00:59:46.148437 ==
5917 00:59:46.148878 DQS Delay:
5918 00:59:46.151452 DQS0 = 0, DQS1 = 0
5919 00:59:46.151928 DQM Delay:
5920 00:59:46.154335 DQM0 = 100, DQM1 = 91
5921 00:59:46.154764 DQ Delay:
5922 00:59:46.157749 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5923 00:59:46.161269 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5924 00:59:46.164261 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5925 00:59:46.167997 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5926 00:59:46.168425
5927 00:59:46.168854
5928 00:59:46.169260 ==
5929 00:59:46.170978 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 00:59:46.174013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 00:59:46.174443 ==
5932 00:59:46.174878
5933 00:59:46.178599
5934 00:59:46.179108 TX Vref Scan disable
5935 00:59:46.181666 == TX Byte 0 ==
5936 00:59:46.184970 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5937 00:59:46.187415 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5938 00:59:46.190596 == TX Byte 1 ==
5939 00:59:46.194202 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5940 00:59:46.197895 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5941 00:59:46.198552 ==
5942 00:59:46.201544 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 00:59:46.208367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 00:59:46.209004 ==
5945 00:59:46.209533
5946 00:59:46.210053
5947 00:59:46.210578 TX Vref Scan disable
5948 00:59:46.211763 == TX Byte 0 ==
5949 00:59:46.215848 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5950 00:59:46.221613 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5951 00:59:46.222199 == TX Byte 1 ==
5952 00:59:46.224842 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5953 00:59:46.231172 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5954 00:59:46.231601
5955 00:59:46.232127 [DATLAT]
5956 00:59:46.232476 Freq=933, CH1 RK1
5957 00:59:46.232880
5958 00:59:46.234487 DATLAT Default: 0xb
5959 00:59:46.234938 0, 0xFFFF, sum = 0
5960 00:59:46.237880 1, 0xFFFF, sum = 0
5961 00:59:46.241092 2, 0xFFFF, sum = 0
5962 00:59:46.241544 3, 0xFFFF, sum = 0
5963 00:59:46.244710 4, 0xFFFF, sum = 0
5964 00:59:46.245142 5, 0xFFFF, sum = 0
5965 00:59:46.247988 6, 0xFFFF, sum = 0
5966 00:59:46.248424 7, 0xFFFF, sum = 0
5967 00:59:46.250996 8, 0xFFFF, sum = 0
5968 00:59:46.251432 9, 0xFFFF, sum = 0
5969 00:59:46.254654 10, 0x0, sum = 1
5970 00:59:46.255082 11, 0x0, sum = 2
5971 00:59:46.257691 12, 0x0, sum = 3
5972 00:59:46.258122 13, 0x0, sum = 4
5973 00:59:46.260855 best_step = 11
5974 00:59:46.261281
5975 00:59:46.261711 ==
5976 00:59:46.264228 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 00:59:46.267600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 00:59:46.268068 ==
5979 00:59:46.268405 RX Vref Scan: 0
5980 00:59:46.268715
5981 00:59:46.271657 RX Vref 0 -> 0, step: 1
5982 00:59:46.272107
5983 00:59:46.274389 RX Delay -61 -> 252, step: 4
5984 00:59:46.280664 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5985 00:59:46.284176 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5986 00:59:46.287560 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5987 00:59:46.290870 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5988 00:59:46.294101 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5989 00:59:46.300549 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5990 00:59:46.303645 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5991 00:59:46.306952 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5992 00:59:46.310266 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5993 00:59:46.313305 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5994 00:59:46.317518 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5995 00:59:46.323869 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5996 00:59:46.327774 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5997 00:59:46.330283 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
5998 00:59:46.333124 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5999 00:59:46.340128 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6000 00:59:46.340548 ==
6001 00:59:46.342796 Dram Type= 6, Freq= 0, CH_1, rank 1
6002 00:59:46.346737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6003 00:59:46.347195 ==
6004 00:59:46.347529 DQS Delay:
6005 00:59:46.349363 DQS0 = 0, DQS1 = 0
6006 00:59:46.349777 DQM Delay:
6007 00:59:46.352809 DQM0 = 101, DQM1 = 94
6008 00:59:46.353396 DQ Delay:
6009 00:59:46.356787 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6010 00:59:46.359241 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
6011 00:59:46.363017 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
6012 00:59:46.366077 DQ12 =104, DQ13 =100, DQ14 =100, DQ15 =102
6013 00:59:46.366495
6014 00:59:46.366825
6015 00:59:46.375560 [DQSOSCAuto] RK1, (LSB)MR18= 0x601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 420 ps
6016 00:59:46.379038 CH1 RK1: MR19=505, MR18=601
6017 00:59:46.382263 CH1_RK1: MR19=0x505, MR18=0x601, DQSOSC=420, MR23=63, INC=61, DEC=40
6018 00:59:46.386131 [RxdqsGatingPostProcess] freq 933
6019 00:59:46.391901 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6020 00:59:46.395696 best DQS0 dly(2T, 0.5T) = (0, 10)
6021 00:59:46.398719 best DQS1 dly(2T, 0.5T) = (0, 10)
6022 00:59:46.402068 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6023 00:59:46.405561 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6024 00:59:46.408657 best DQS0 dly(2T, 0.5T) = (0, 10)
6025 00:59:46.412185 best DQS1 dly(2T, 0.5T) = (0, 10)
6026 00:59:46.415635 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6027 00:59:46.418720 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6028 00:59:46.422592 Pre-setting of DQS Precalculation
6029 00:59:46.425854 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6030 00:59:46.432043 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6031 00:59:46.438162 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6032 00:59:46.441842
6033 00:59:46.442269
6034 00:59:46.442707 [Calibration Summary] 1866 Mbps
6035 00:59:46.445136 CH 0, Rank 0
6036 00:59:46.445564 SW Impedance : PASS
6037 00:59:46.448109 DUTY Scan : NO K
6038 00:59:46.451390 ZQ Calibration : PASS
6039 00:59:46.451849 Jitter Meter : NO K
6040 00:59:46.454790 CBT Training : PASS
6041 00:59:46.457910 Write leveling : PASS
6042 00:59:46.458339 RX DQS gating : PASS
6043 00:59:46.461673 RX DQ/DQS(RDDQC) : PASS
6044 00:59:46.464903 TX DQ/DQS : PASS
6045 00:59:46.465334 RX DATLAT : PASS
6046 00:59:46.468316 RX DQ/DQS(Engine): PASS
6047 00:59:46.471281 TX OE : NO K
6048 00:59:46.471741 All Pass.
6049 00:59:46.472177
6050 00:59:46.472584 CH 0, Rank 1
6051 00:59:46.474373 SW Impedance : PASS
6052 00:59:46.477632 DUTY Scan : NO K
6053 00:59:46.478061 ZQ Calibration : PASS
6054 00:59:46.481266 Jitter Meter : NO K
6055 00:59:46.484569 CBT Training : PASS
6056 00:59:46.484999 Write leveling : PASS
6057 00:59:46.488001 RX DQS gating : PASS
6058 00:59:46.491235 RX DQ/DQS(RDDQC) : PASS
6059 00:59:46.491662 TX DQ/DQS : PASS
6060 00:59:46.494219 RX DATLAT : PASS
6061 00:59:46.497885 RX DQ/DQS(Engine): PASS
6062 00:59:46.498312 TX OE : NO K
6063 00:59:46.498816 All Pass.
6064 00:59:46.501010
6065 00:59:46.501447 CH 1, Rank 0
6066 00:59:46.504689 SW Impedance : PASS
6067 00:59:46.505119 DUTY Scan : NO K
6068 00:59:46.508035 ZQ Calibration : PASS
6069 00:59:46.510810 Jitter Meter : NO K
6070 00:59:46.511272 CBT Training : PASS
6071 00:59:46.514299 Write leveling : PASS
6072 00:59:46.514729 RX DQS gating : PASS
6073 00:59:46.517539 RX DQ/DQS(RDDQC) : PASS
6074 00:59:46.520758 TX DQ/DQS : PASS
6075 00:59:46.521185 RX DATLAT : PASS
6076 00:59:46.523780 RX DQ/DQS(Engine): PASS
6077 00:59:46.528043 TX OE : NO K
6078 00:59:46.528474 All Pass.
6079 00:59:46.528914
6080 00:59:46.529326 CH 1, Rank 1
6081 00:59:46.530302 SW Impedance : PASS
6082 00:59:46.534346 DUTY Scan : NO K
6083 00:59:46.534775 ZQ Calibration : PASS
6084 00:59:46.537291 Jitter Meter : NO K
6085 00:59:46.540744 CBT Training : PASS
6086 00:59:46.541173 Write leveling : PASS
6087 00:59:46.543566 RX DQS gating : PASS
6088 00:59:46.547208 RX DQ/DQS(RDDQC) : PASS
6089 00:59:46.547636 TX DQ/DQS : PASS
6090 00:59:46.550266 RX DATLAT : PASS
6091 00:59:46.553939 RX DQ/DQS(Engine): PASS
6092 00:59:46.554366 TX OE : NO K
6093 00:59:46.557077 All Pass.
6094 00:59:46.557502
6095 00:59:46.557933 DramC Write-DBI off
6096 00:59:46.560060 PER_BANK_REFRESH: Hybrid Mode
6097 00:59:46.563836 TX_TRACKING: ON
6098 00:59:46.569976 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6099 00:59:46.573632 [FAST_K] Save calibration result to emmc
6100 00:59:46.576648 dramc_set_vcore_voltage set vcore to 650000
6101 00:59:46.579595 Read voltage for 400, 6
6102 00:59:46.580070 Vio18 = 0
6103 00:59:46.583077 Vcore = 650000
6104 00:59:46.583501 Vdram = 0
6105 00:59:46.583979 Vddq = 0
6106 00:59:46.586807 Vmddr = 0
6107 00:59:46.589704 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6108 00:59:46.596551 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6109 00:59:46.596975 MEM_TYPE=3, freq_sel=20
6110 00:59:46.599499 sv_algorithm_assistance_LP4_800
6111 00:59:46.606335 ============ PULL DRAM RESETB DOWN ============
6112 00:59:46.609601 ========== PULL DRAM RESETB DOWN end =========
6113 00:59:46.612661 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6114 00:59:46.616790 ===================================
6115 00:59:46.619629 LPDDR4 DRAM CONFIGURATION
6116 00:59:46.622766 ===================================
6117 00:59:46.626007 EX_ROW_EN[0] = 0x0
6118 00:59:46.626429 EX_ROW_EN[1] = 0x0
6119 00:59:46.628949 LP4Y_EN = 0x0
6120 00:59:46.629368 WORK_FSP = 0x0
6121 00:59:46.632356 WL = 0x2
6122 00:59:46.632774 RL = 0x2
6123 00:59:46.635594 BL = 0x2
6124 00:59:46.636043 RPST = 0x0
6125 00:59:46.639057 RD_PRE = 0x0
6126 00:59:46.639551 WR_PRE = 0x1
6127 00:59:46.642760 WR_PST = 0x0
6128 00:59:46.643177 DBI_WR = 0x0
6129 00:59:46.645954 DBI_RD = 0x0
6130 00:59:46.649262 OTF = 0x1
6131 00:59:46.652270 ===================================
6132 00:59:46.655359 ===================================
6133 00:59:46.655800 ANA top config
6134 00:59:46.658659 ===================================
6135 00:59:46.662406 DLL_ASYNC_EN = 0
6136 00:59:46.662860 ALL_SLAVE_EN = 1
6137 00:59:46.665366 NEW_RANK_MODE = 1
6138 00:59:46.668889 DLL_IDLE_MODE = 1
6139 00:59:46.671919 LP45_APHY_COMB_EN = 1
6140 00:59:46.675204 TX_ODT_DIS = 1
6141 00:59:46.675616 NEW_8X_MODE = 1
6142 00:59:46.678495 ===================================
6143 00:59:46.681981 ===================================
6144 00:59:46.685383 data_rate = 800
6145 00:59:46.689351 CKR = 1
6146 00:59:46.691852 DQ_P2S_RATIO = 4
6147 00:59:46.694755 ===================================
6148 00:59:46.698645 CA_P2S_RATIO = 4
6149 00:59:46.701480 DQ_CA_OPEN = 0
6150 00:59:46.705305 DQ_SEMI_OPEN = 1
6151 00:59:46.705719 CA_SEMI_OPEN = 1
6152 00:59:46.708247 CA_FULL_RATE = 0
6153 00:59:46.711855 DQ_CKDIV4_EN = 0
6154 00:59:46.714853 CA_CKDIV4_EN = 1
6155 00:59:46.718076 CA_PREDIV_EN = 0
6156 00:59:46.721425 PH8_DLY = 0
6157 00:59:46.721890 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6158 00:59:46.724799 DQ_AAMCK_DIV = 0
6159 00:59:46.728064 CA_AAMCK_DIV = 0
6160 00:59:46.731235 CA_ADMCK_DIV = 4
6161 00:59:46.734565 DQ_TRACK_CA_EN = 0
6162 00:59:46.737781 CA_PICK = 800
6163 00:59:46.738199 CA_MCKIO = 400
6164 00:59:46.740906 MCKIO_SEMI = 400
6165 00:59:46.745009 PLL_FREQ = 3016
6166 00:59:46.747804 DQ_UI_PI_RATIO = 32
6167 00:59:46.751289 CA_UI_PI_RATIO = 32
6168 00:59:46.754167 ===================================
6169 00:59:46.757711 ===================================
6170 00:59:46.760709 memory_type:LPDDR4
6171 00:59:46.761125 GP_NUM : 10
6172 00:59:46.764333 SRAM_EN : 1
6173 00:59:46.767742 MD32_EN : 0
6174 00:59:46.770894 ===================================
6175 00:59:46.771424 [ANA_INIT] >>>>>>>>>>>>>>
6176 00:59:46.774581 <<<<<< [CONFIGURE PHASE]: ANA_TX
6177 00:59:46.778087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6178 00:59:46.780621 ===================================
6179 00:59:46.783916 data_rate = 800,PCW = 0X7400
6180 00:59:46.787707 ===================================
6181 00:59:46.790442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6182 00:59:46.797655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6183 00:59:46.806924 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6184 00:59:46.813632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6185 00:59:46.817285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6186 00:59:46.820085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6187 00:59:46.820505 [ANA_INIT] flow start
6188 00:59:46.823320 [ANA_INIT] PLL >>>>>>>>
6189 00:59:46.826552 [ANA_INIT] PLL <<<<<<<<
6190 00:59:46.826970 [ANA_INIT] MIDPI >>>>>>>>
6191 00:59:46.830486 [ANA_INIT] MIDPI <<<<<<<<
6192 00:59:46.833112 [ANA_INIT] DLL >>>>>>>>
6193 00:59:46.833547 [ANA_INIT] flow end
6194 00:59:46.839825 ============ LP4 DIFF to SE enter ============
6195 00:59:46.843441 ============ LP4 DIFF to SE exit ============
6196 00:59:46.846596 [ANA_INIT] <<<<<<<<<<<<<
6197 00:59:46.849619 [Flow] Enable top DCM control >>>>>
6198 00:59:46.853287 [Flow] Enable top DCM control <<<<<
6199 00:59:46.856365 Enable DLL master slave shuffle
6200 00:59:46.859279 ==============================================================
6201 00:59:46.862701 Gating Mode config
6202 00:59:46.869536 ==============================================================
6203 00:59:46.869966 Config description:
6204 00:59:46.879225 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6205 00:59:46.886243 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6206 00:59:46.889083 SELPH_MODE 0: By rank 1: By Phase
6207 00:59:46.896215 ==============================================================
6208 00:59:46.899501 GAT_TRACK_EN = 0
6209 00:59:46.902088 RX_GATING_MODE = 2
6210 00:59:46.905586 RX_GATING_TRACK_MODE = 2
6211 00:59:46.908884 SELPH_MODE = 1
6212 00:59:46.912186 PICG_EARLY_EN = 1
6213 00:59:46.915464 VALID_LAT_VALUE = 1
6214 00:59:46.919124 ==============================================================
6215 00:59:46.922320 Enter into Gating configuration >>>>
6216 00:59:46.925355 Exit from Gating configuration <<<<
6217 00:59:46.928651 Enter into DVFS_PRE_config >>>>>
6218 00:59:46.942351 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6219 00:59:46.945088 Exit from DVFS_PRE_config <<<<<
6220 00:59:46.948948 Enter into PICG configuration >>>>
6221 00:59:46.949408 Exit from PICG configuration <<<<
6222 00:59:46.951748 [RX_INPUT] configuration >>>>>
6223 00:59:46.955087 [RX_INPUT] configuration <<<<<
6224 00:59:46.962023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6225 00:59:46.965043 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6226 00:59:46.971759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6227 00:59:46.978536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6228 00:59:46.984901 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6229 00:59:46.991649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6230 00:59:46.995112 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6231 00:59:46.998220 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6232 00:59:47.004709 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6233 00:59:47.007851 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6234 00:59:47.011584 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6235 00:59:47.014620 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6236 00:59:47.018027 ===================================
6237 00:59:47.021275 LPDDR4 DRAM CONFIGURATION
6238 00:59:47.024451 ===================================
6239 00:59:47.027634 EX_ROW_EN[0] = 0x0
6240 00:59:47.028226 EX_ROW_EN[1] = 0x0
6241 00:59:47.031199 LP4Y_EN = 0x0
6242 00:59:47.031864 WORK_FSP = 0x0
6243 00:59:47.034280 WL = 0x2
6244 00:59:47.034735 RL = 0x2
6245 00:59:47.037254 BL = 0x2
6246 00:59:47.037714 RPST = 0x0
6247 00:59:47.040976 RD_PRE = 0x0
6248 00:59:47.044156 WR_PRE = 0x1
6249 00:59:47.044581 WR_PST = 0x0
6250 00:59:47.047822 DBI_WR = 0x0
6251 00:59:47.048288 DBI_RD = 0x0
6252 00:59:47.050372 OTF = 0x1
6253 00:59:47.054090 ===================================
6254 00:59:47.057386 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6255 00:59:47.060564 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6256 00:59:47.063847 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6257 00:59:47.067256 ===================================
6258 00:59:47.070585 LPDDR4 DRAM CONFIGURATION
6259 00:59:47.074255 ===================================
6260 00:59:47.077431 EX_ROW_EN[0] = 0x10
6261 00:59:47.077844 EX_ROW_EN[1] = 0x0
6262 00:59:47.080569 LP4Y_EN = 0x0
6263 00:59:47.080983 WORK_FSP = 0x0
6264 00:59:47.083971 WL = 0x2
6265 00:59:47.084386 RL = 0x2
6266 00:59:47.087144 BL = 0x2
6267 00:59:47.087555 RPST = 0x0
6268 00:59:47.090754 RD_PRE = 0x0
6269 00:59:47.091168 WR_PRE = 0x1
6270 00:59:47.093686 WR_PST = 0x0
6271 00:59:47.096911 DBI_WR = 0x0
6272 00:59:47.097325 DBI_RD = 0x0
6273 00:59:47.100584 OTF = 0x1
6274 00:59:47.103622 ===================================
6275 00:59:47.106653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6276 00:59:47.112456 nWR fixed to 30
6277 00:59:47.115285 [ModeRegInit_LP4] CH0 RK0
6278 00:59:47.115726 [ModeRegInit_LP4] CH0 RK1
6279 00:59:47.119190 [ModeRegInit_LP4] CH1 RK0
6280 00:59:47.121841 [ModeRegInit_LP4] CH1 RK1
6281 00:59:47.122255 match AC timing 19
6282 00:59:47.128800 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6283 00:59:47.132722 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6284 00:59:47.135412 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6285 00:59:47.141633 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6286 00:59:47.145515 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6287 00:59:47.145932 ==
6288 00:59:47.148478 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 00:59:47.151760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 00:59:47.152183 ==
6291 00:59:47.158025 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 00:59:47.164526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 00:59:47.168140 [CA 0] Center 36 (8~64) winsize 57
6294 00:59:47.172054 [CA 1] Center 36 (8~64) winsize 57
6295 00:59:47.174146 [CA 2] Center 36 (8~64) winsize 57
6296 00:59:47.178192 [CA 3] Center 36 (8~64) winsize 57
6297 00:59:47.181197 [CA 4] Center 36 (8~64) winsize 57
6298 00:59:47.184363 [CA 5] Center 36 (8~64) winsize 57
6299 00:59:47.184784
6300 00:59:47.187340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 00:59:47.187816
6302 00:59:47.190791 [CATrainingPosCal] consider 1 rank data
6303 00:59:47.194123 u2DelayCellTimex100 = 270/100 ps
6304 00:59:47.197632 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 00:59:47.200334 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 00:59:47.203627 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 00:59:47.207359 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 00:59:47.210204 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 00:59:47.213542 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 00:59:47.213624
6311 00:59:47.220284 CA PerBit enable=1, Macro0, CA PI delay=36
6312 00:59:47.220366
6313 00:59:47.224022 [CBTSetCACLKResult] CA Dly = 36
6314 00:59:47.224103 CS Dly: 1 (0~32)
6315 00:59:47.224166 ==
6316 00:59:47.226617 Dram Type= 6, Freq= 0, CH_0, rank 1
6317 00:59:47.230853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 00:59:47.230934 ==
6319 00:59:47.236846 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6320 00:59:47.243223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6321 00:59:47.246873 [CA 0] Center 36 (8~64) winsize 57
6322 00:59:47.250324 [CA 1] Center 36 (8~64) winsize 57
6323 00:59:47.253504 [CA 2] Center 36 (8~64) winsize 57
6324 00:59:47.256678 [CA 3] Center 36 (8~64) winsize 57
6325 00:59:47.259823 [CA 4] Center 36 (8~64) winsize 57
6326 00:59:47.259904 [CA 5] Center 36 (8~64) winsize 57
6327 00:59:47.263197
6328 00:59:47.265901 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6329 00:59:47.265982
6330 00:59:47.270114 [CATrainingPosCal] consider 2 rank data
6331 00:59:47.272712 u2DelayCellTimex100 = 270/100 ps
6332 00:59:47.276207 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 00:59:47.279288 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 00:59:47.282927 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 00:59:47.285785 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 00:59:47.289355 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 00:59:47.292928 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 00:59:47.293008
6339 00:59:47.299195 CA PerBit enable=1, Macro0, CA PI delay=36
6340 00:59:47.299276
6341 00:59:47.302997 [CBTSetCACLKResult] CA Dly = 36
6342 00:59:47.303079 CS Dly: 1 (0~32)
6343 00:59:47.303149
6344 00:59:47.305604 ----->DramcWriteLeveling(PI) begin...
6345 00:59:47.305685 ==
6346 00:59:47.308886 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 00:59:47.312505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 00:59:47.312586 ==
6349 00:59:47.315351 Write leveling (Byte 0): 40 => 8
6350 00:59:47.318825 Write leveling (Byte 1): 32 => 0
6351 00:59:47.322123 DramcWriteLeveling(PI) end<-----
6352 00:59:47.322203
6353 00:59:47.322266 ==
6354 00:59:47.325153 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 00:59:47.332131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 00:59:47.332211 ==
6357 00:59:47.332275 [Gating] SW mode calibration
6358 00:59:47.342286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6359 00:59:47.345467 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6360 00:59:47.349010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6361 00:59:47.354847 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6362 00:59:47.358046 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 00:59:47.361665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 00:59:47.368424 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 00:59:47.371221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 00:59:47.374634 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 00:59:47.381558 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 00:59:47.384577 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6369 00:59:47.387972 Total UI for P1: 0, mck2ui 16
6370 00:59:47.390862 best dqsien dly found for B0: ( 0, 14, 24)
6371 00:59:47.394392 Total UI for P1: 0, mck2ui 16
6372 00:59:47.397774 best dqsien dly found for B1: ( 0, 14, 24)
6373 00:59:47.401247 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6374 00:59:47.404194 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6375 00:59:47.404274
6376 00:59:47.411065 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6377 00:59:47.413978 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6378 00:59:47.414059 [Gating] SW calibration Done
6379 00:59:47.417878 ==
6380 00:59:47.420850 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 00:59:47.423975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 00:59:47.424055 ==
6383 00:59:47.424119 RX Vref Scan: 0
6384 00:59:47.424177
6385 00:59:47.427259 RX Vref 0 -> 0, step: 1
6386 00:59:47.427339
6387 00:59:47.430767 RX Delay -410 -> 252, step: 16
6388 00:59:47.434079 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6389 00:59:47.437813 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6390 00:59:47.443733 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6391 00:59:47.447177 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6392 00:59:47.450549 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6393 00:59:47.454375 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6394 00:59:47.460405 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6395 00:59:47.464560 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6396 00:59:47.467710 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6397 00:59:47.471112 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6398 00:59:47.477121 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6399 00:59:47.480988 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6400 00:59:47.484051 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6401 00:59:47.490803 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6402 00:59:47.493848 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6403 00:59:47.497161 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6404 00:59:47.497575 ==
6405 00:59:47.500471 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 00:59:47.506879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 00:59:47.507301 ==
6408 00:59:47.507635 DQS Delay:
6409 00:59:47.510703 DQS0 = 43, DQS1 = 59
6410 00:59:47.511120 DQM Delay:
6411 00:59:47.511492 DQM0 = 9, DQM1 = 12
6412 00:59:47.513440 DQ Delay:
6413 00:59:47.513850 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6414 00:59:47.517040 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6415 00:59:47.520713 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6416 00:59:47.523498 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6417 00:59:47.523960
6418 00:59:47.524289
6419 00:59:47.526968 ==
6420 00:59:47.530517 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 00:59:47.533684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 00:59:47.534101 ==
6423 00:59:47.534431
6424 00:59:47.534734
6425 00:59:47.537383 TX Vref Scan disable
6426 00:59:47.537799 == TX Byte 0 ==
6427 00:59:47.540602 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 00:59:47.546441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 00:59:47.546868 == TX Byte 1 ==
6430 00:59:47.549541 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6431 00:59:47.556718 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6432 00:59:47.557141 ==
6433 00:59:47.559859 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 00:59:47.563315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 00:59:47.563761 ==
6436 00:59:47.564092
6437 00:59:47.564451
6438 00:59:47.566209 TX Vref Scan disable
6439 00:59:47.566788 == TX Byte 0 ==
6440 00:59:47.573300 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 00:59:47.576691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 00:59:47.577107 == TX Byte 1 ==
6443 00:59:47.582986 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 00:59:47.586779 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 00:59:47.587193
6446 00:59:47.587523 [DATLAT]
6447 00:59:47.589720 Freq=400, CH0 RK0
6448 00:59:47.590424
6449 00:59:47.591058 DATLAT Default: 0xf
6450 00:59:47.593451 0, 0xFFFF, sum = 0
6451 00:59:47.594146 1, 0xFFFF, sum = 0
6452 00:59:47.596423 2, 0xFFFF, sum = 0
6453 00:59:47.597141 3, 0xFFFF, sum = 0
6454 00:59:47.599583 4, 0xFFFF, sum = 0
6455 00:59:47.600312 5, 0xFFFF, sum = 0
6456 00:59:47.602580 6, 0xFFFF, sum = 0
6457 00:59:47.603179 7, 0xFFFF, sum = 0
6458 00:59:47.605932 8, 0xFFFF, sum = 0
6459 00:59:47.606353 9, 0xFFFF, sum = 0
6460 00:59:47.609940 10, 0xFFFF, sum = 0
6461 00:59:47.612388 11, 0xFFFF, sum = 0
6462 00:59:47.613103 12, 0xFFFF, sum = 0
6463 00:59:47.615887 13, 0x0, sum = 1
6464 00:59:47.616572 14, 0x0, sum = 2
6465 00:59:47.617204 15, 0x0, sum = 3
6466 00:59:47.619458 16, 0x0, sum = 4
6467 00:59:47.620148 best_step = 14
6468 00:59:47.620732
6469 00:59:47.622937 ==
6470 00:59:47.623550 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 00:59:47.629151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 00:59:47.629805 ==
6473 00:59:47.630412 RX Vref Scan: 1
6474 00:59:47.631005
6475 00:59:47.632747 RX Vref 0 -> 0, step: 1
6476 00:59:47.633211
6477 00:59:47.635867 RX Delay -359 -> 252, step: 8
6478 00:59:47.636288
6479 00:59:47.639633 Set Vref, RX VrefLevel [Byte0]: 60
6480 00:59:47.642020 [Byte1]: 49
6481 00:59:47.646304
6482 00:59:47.646734 Final RX Vref Byte 0 = 60 to rank0
6483 00:59:47.649029 Final RX Vref Byte 1 = 49 to rank0
6484 00:59:47.652879 Final RX Vref Byte 0 = 60 to rank1
6485 00:59:47.655581 Final RX Vref Byte 1 = 49 to rank1==
6486 00:59:47.659473 Dram Type= 6, Freq= 0, CH_0, rank 0
6487 00:59:47.665428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 00:59:47.665509 ==
6489 00:59:47.665573 DQS Delay:
6490 00:59:47.668405 DQS0 = 48, DQS1 = 60
6491 00:59:47.668485 DQM Delay:
6492 00:59:47.668549 DQM0 = 12, DQM1 = 12
6493 00:59:47.672292 DQ Delay:
6494 00:59:47.676327 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6495 00:59:47.678490 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6496 00:59:47.682507 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6497 00:59:47.685167 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6498 00:59:47.685248
6499 00:59:47.685311
6500 00:59:47.691798 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6501 00:59:47.695706 CH0 RK0: MR19=C0C, MR18=BE80
6502 00:59:47.701757 CH0_RK0: MR19=0xC0C, MR18=0xBE80, DQSOSC=386, MR23=63, INC=396, DEC=264
6503 00:59:47.701837 ==
6504 00:59:47.705283 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 00:59:47.708304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 00:59:47.708385 ==
6507 00:59:47.711696 [Gating] SW mode calibration
6508 00:59:47.718491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6509 00:59:47.724692 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6510 00:59:47.727913 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6511 00:59:47.731606 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6512 00:59:47.738362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 00:59:47.741152 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 00:59:47.745182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 00:59:47.751711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 00:59:47.755109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 00:59:47.757871 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 00:59:47.764602 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 00:59:47.767628 Total UI for P1: 0, mck2ui 16
6520 00:59:47.770834 best dqsien dly found for B0: ( 0, 14, 24)
6521 00:59:47.774220 Total UI for P1: 0, mck2ui 16
6522 00:59:47.777266 best dqsien dly found for B1: ( 0, 14, 24)
6523 00:59:47.781160 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6524 00:59:47.784148 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6525 00:59:47.784229
6526 00:59:47.787887 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6527 00:59:47.790795 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6528 00:59:47.793837 [Gating] SW calibration Done
6529 00:59:47.793916 ==
6530 00:59:47.797541 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 00:59:47.800928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 00:59:47.801008 ==
6533 00:59:47.803880 RX Vref Scan: 0
6534 00:59:47.803960
6535 00:59:47.807439 RX Vref 0 -> 0, step: 1
6536 00:59:47.807519
6537 00:59:47.810193 RX Delay -410 -> 252, step: 16
6538 00:59:47.813414 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6539 00:59:47.816826 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6540 00:59:47.820202 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6541 00:59:47.826936 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6542 00:59:47.830522 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6543 00:59:47.833547 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6544 00:59:47.836323 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6545 00:59:47.843839 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6546 00:59:47.846378 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6547 00:59:47.849517 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6548 00:59:47.853256 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6549 00:59:47.859555 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6550 00:59:47.863045 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6551 00:59:47.866050 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6552 00:59:47.872504 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6553 00:59:47.876412 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6554 00:59:47.876494 ==
6555 00:59:47.879037 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 00:59:47.882500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 00:59:47.882612 ==
6558 00:59:47.885714 DQS Delay:
6559 00:59:47.885795 DQS0 = 43, DQS1 = 51
6560 00:59:47.889291 DQM Delay:
6561 00:59:47.889371 DQM0 = 10, DQM1 = 9
6562 00:59:47.889436 DQ Delay:
6563 00:59:47.892770 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6564 00:59:47.895861 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6565 00:59:47.899615 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6566 00:59:47.902401 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6567 00:59:47.902488
6568 00:59:47.902556
6569 00:59:47.902620 ==
6570 00:59:47.905728 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 00:59:47.908774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 00:59:47.912044 ==
6573 00:59:47.912125
6574 00:59:47.912189
6575 00:59:47.912247 TX Vref Scan disable
6576 00:59:47.915381 == TX Byte 0 ==
6577 00:59:47.918805 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6578 00:59:47.922483 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6579 00:59:47.925397 == TX Byte 1 ==
6580 00:59:47.929187 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6581 00:59:47.932499 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6582 00:59:47.932581 ==
6583 00:59:47.935183 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 00:59:47.942095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 00:59:47.942177 ==
6586 00:59:47.942241
6587 00:59:47.942300
6588 00:59:47.942357 TX Vref Scan disable
6589 00:59:47.946173 == TX Byte 0 ==
6590 00:59:47.948994 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6591 00:59:47.951923 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6592 00:59:47.955116 == TX Byte 1 ==
6593 00:59:47.958877 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6594 00:59:47.962570 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6595 00:59:47.962657
6596 00:59:47.964979 [DATLAT]
6597 00:59:47.965072 Freq=400, CH0 RK1
6598 00:59:47.965147
6599 00:59:47.968476 DATLAT Default: 0xe
6600 00:59:47.968577 0, 0xFFFF, sum = 0
6601 00:59:47.971977 1, 0xFFFF, sum = 0
6602 00:59:47.972060 2, 0xFFFF, sum = 0
6603 00:59:47.975398 3, 0xFFFF, sum = 0
6604 00:59:47.975480 4, 0xFFFF, sum = 0
6605 00:59:47.978452 5, 0xFFFF, sum = 0
6606 00:59:47.978540 6, 0xFFFF, sum = 0
6607 00:59:47.981490 7, 0xFFFF, sum = 0
6608 00:59:47.981573 8, 0xFFFF, sum = 0
6609 00:59:47.984839 9, 0xFFFF, sum = 0
6610 00:59:47.987962 10, 0xFFFF, sum = 0
6611 00:59:47.988045 11, 0xFFFF, sum = 0
6612 00:59:47.991310 12, 0xFFFF, sum = 0
6613 00:59:47.991392 13, 0x0, sum = 1
6614 00:59:47.994597 14, 0x0, sum = 2
6615 00:59:47.994679 15, 0x0, sum = 3
6616 00:59:47.998156 16, 0x0, sum = 4
6617 00:59:47.998238 best_step = 14
6618 00:59:47.998302
6619 00:59:47.998361 ==
6620 00:59:48.001459 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 00:59:48.004535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 00:59:48.004617 ==
6623 00:59:48.007621 RX Vref Scan: 0
6624 00:59:48.007724
6625 00:59:48.011026 RX Vref 0 -> 0, step: 1
6626 00:59:48.011107
6627 00:59:48.011171 RX Delay -343 -> 252, step: 8
6628 00:59:48.019911 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6629 00:59:48.023293 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6630 00:59:48.027003 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6631 00:59:48.033511 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6632 00:59:48.036364 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6633 00:59:48.040201 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6634 00:59:48.042997 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6635 00:59:48.049902 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6636 00:59:48.054790 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6637 00:59:48.056323 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6638 00:59:48.059691 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6639 00:59:48.065993 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6640 00:59:48.069568 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6641 00:59:48.072593 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6642 00:59:48.076063 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6643 00:59:48.082742 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6644 00:59:48.082823 ==
6645 00:59:48.085538 Dram Type= 6, Freq= 0, CH_0, rank 1
6646 00:59:48.089596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 00:59:48.089679 ==
6648 00:59:48.092750 DQS Delay:
6649 00:59:48.092831 DQS0 = 44, DQS1 = 60
6650 00:59:48.092895 DQM Delay:
6651 00:59:48.095849 DQM0 = 7, DQM1 = 14
6652 00:59:48.095956 DQ Delay:
6653 00:59:48.098729 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6654 00:59:48.102138 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6655 00:59:48.105422 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6656 00:59:48.108804 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6657 00:59:48.108885
6658 00:59:48.108949
6659 00:59:48.115623 [DQSOSCAuto] RK1, (LSB)MR18= 0xb640, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6660 00:59:48.118737 CH0 RK1: MR19=C0C, MR18=B640
6661 00:59:48.125327 CH0_RK1: MR19=0xC0C, MR18=0xB640, DQSOSC=387, MR23=63, INC=394, DEC=262
6662 00:59:48.128624 [RxdqsGatingPostProcess] freq 400
6663 00:59:48.134958 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6664 00:59:48.138525 best DQS0 dly(2T, 0.5T) = (0, 10)
6665 00:59:48.141906 best DQS1 dly(2T, 0.5T) = (0, 10)
6666 00:59:48.145722 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6667 00:59:48.148560 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6668 00:59:48.151982 best DQS0 dly(2T, 0.5T) = (0, 10)
6669 00:59:48.152063 best DQS1 dly(2T, 0.5T) = (0, 10)
6670 00:59:48.154949 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6671 00:59:48.158355 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6672 00:59:48.162192 Pre-setting of DQS Precalculation
6673 00:59:48.168366 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6674 00:59:48.168448 ==
6675 00:59:48.171760 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 00:59:48.175187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 00:59:48.175269 ==
6678 00:59:48.181500 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 00:59:48.188316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6680 00:59:48.191192 [CA 0] Center 36 (8~64) winsize 57
6681 00:59:48.194537 [CA 1] Center 36 (8~64) winsize 57
6682 00:59:48.197853 [CA 2] Center 36 (8~64) winsize 57
6683 00:59:48.197934 [CA 3] Center 36 (8~64) winsize 57
6684 00:59:48.201310 [CA 4] Center 36 (8~64) winsize 57
6685 00:59:48.205062 [CA 5] Center 36 (8~64) winsize 57
6686 00:59:48.205144
6687 00:59:48.211173 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6688 00:59:48.211255
6689 00:59:48.214189 [CATrainingPosCal] consider 1 rank data
6690 00:59:48.217508 u2DelayCellTimex100 = 270/100 ps
6691 00:59:48.221069 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 00:59:48.223929 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 00:59:48.227629 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 00:59:48.230860 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 00:59:48.233901 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 00:59:48.237285 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 00:59:48.237366
6698 00:59:48.240644 CA PerBit enable=1, Macro0, CA PI delay=36
6699 00:59:48.240726
6700 00:59:48.243650 [CBTSetCACLKResult] CA Dly = 36
6701 00:59:48.246940 CS Dly: 1 (0~32)
6702 00:59:48.247022 ==
6703 00:59:48.250688 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 00:59:48.253795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 00:59:48.253876 ==
6706 00:59:48.260050 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6707 00:59:48.267135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6708 00:59:48.270364 [CA 0] Center 36 (8~64) winsize 57
6709 00:59:48.270446 [CA 1] Center 36 (8~64) winsize 57
6710 00:59:48.273758 [CA 2] Center 36 (8~64) winsize 57
6711 00:59:48.277021 [CA 3] Center 36 (8~64) winsize 57
6712 00:59:48.280040 [CA 4] Center 36 (8~64) winsize 57
6713 00:59:48.283153 [CA 5] Center 36 (8~64) winsize 57
6714 00:59:48.283233
6715 00:59:48.286700 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6716 00:59:48.286781
6717 00:59:48.293265 [CATrainingPosCal] consider 2 rank data
6718 00:59:48.293346 u2DelayCellTimex100 = 270/100 ps
6719 00:59:48.299990 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 00:59:48.303284 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 00:59:48.306130 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 00:59:48.309512 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 00:59:48.313010 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 00:59:48.316181 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 00:59:48.316262
6726 00:59:48.319585 CA PerBit enable=1, Macro0, CA PI delay=36
6727 00:59:48.319729
6728 00:59:48.323013 [CBTSetCACLKResult] CA Dly = 36
6729 00:59:48.326481 CS Dly: 1 (0~32)
6730 00:59:48.326562
6731 00:59:48.329645 ----->DramcWriteLeveling(PI) begin...
6732 00:59:48.329727 ==
6733 00:59:48.332697 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 00:59:48.336151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 00:59:48.336233 ==
6736 00:59:48.339362 Write leveling (Byte 0): 40 => 8
6737 00:59:48.342582 Write leveling (Byte 1): 32 => 0
6738 00:59:48.345976 DramcWriteLeveling(PI) end<-----
6739 00:59:48.346058
6740 00:59:48.346122 ==
6741 00:59:48.348806 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 00:59:48.352146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 00:59:48.352227 ==
6744 00:59:48.355800 [Gating] SW mode calibration
6745 00:59:48.362390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6746 00:59:48.368598 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6747 00:59:48.372237 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6748 00:59:48.378670 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6749 00:59:48.381988 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 00:59:48.385065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 00:59:48.392265 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 00:59:48.394927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 00:59:48.398546 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 00:59:48.405074 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 00:59:48.408576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6756 00:59:48.411480 Total UI for P1: 0, mck2ui 16
6757 00:59:48.415285 best dqsien dly found for B0: ( 0, 14, 24)
6758 00:59:48.418910 Total UI for P1: 0, mck2ui 16
6759 00:59:48.421241 best dqsien dly found for B1: ( 0, 14, 24)
6760 00:59:48.424698 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6761 00:59:48.428001 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6762 00:59:48.428082
6763 00:59:48.431355 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6764 00:59:48.434487 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6765 00:59:48.438422 [Gating] SW calibration Done
6766 00:59:48.438503 ==
6767 00:59:48.441336 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 00:59:48.445044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 00:59:48.448090 ==
6770 00:59:48.448171 RX Vref Scan: 0
6771 00:59:48.448236
6772 00:59:48.451093 RX Vref 0 -> 0, step: 1
6773 00:59:48.451173
6774 00:59:48.454228 RX Delay -410 -> 252, step: 16
6775 00:59:48.457639 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6776 00:59:48.460789 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6777 00:59:48.468061 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6778 00:59:48.471041 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6779 00:59:48.474105 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6780 00:59:48.477273 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6781 00:59:48.484140 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6782 00:59:48.487401 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6783 00:59:48.490747 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6784 00:59:48.494087 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6785 00:59:48.500222 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6786 00:59:48.504105 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6787 00:59:48.507159 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6788 00:59:48.510431 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6789 00:59:48.516800 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6790 00:59:48.520572 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6791 00:59:48.520654 ==
6792 00:59:48.523413 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 00:59:48.527448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 00:59:48.527530 ==
6795 00:59:48.529695 DQS Delay:
6796 00:59:48.529776 DQS0 = 43, DQS1 = 51
6797 00:59:48.533592 DQM Delay:
6798 00:59:48.533673 DQM0 = 12, DQM1 = 15
6799 00:59:48.536366 DQ Delay:
6800 00:59:48.536447 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6801 00:59:48.539931 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6802 00:59:48.543052 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6803 00:59:48.546296 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6804 00:59:48.546376
6805 00:59:48.546440
6806 00:59:48.546500 ==
6807 00:59:48.549670 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 00:59:48.556593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 00:59:48.556676 ==
6810 00:59:48.556740
6811 00:59:48.556799
6812 00:59:48.556856 TX Vref Scan disable
6813 00:59:48.559606 == TX Byte 0 ==
6814 00:59:48.562663 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 00:59:48.566272 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 00:59:48.569760 == TX Byte 1 ==
6817 00:59:48.573523 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6818 00:59:48.576310 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6819 00:59:48.579159 ==
6820 00:59:48.582713 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 00:59:48.585847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 00:59:48.585932 ==
6823 00:59:48.585997
6824 00:59:48.586056
6825 00:59:48.589172 TX Vref Scan disable
6826 00:59:48.589253 == TX Byte 0 ==
6827 00:59:48.592481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 00:59:48.598844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 00:59:48.598926 == TX Byte 1 ==
6830 00:59:48.602907 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6831 00:59:48.608904 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6832 00:59:48.608986
6833 00:59:48.609050 [DATLAT]
6834 00:59:48.612949 Freq=400, CH1 RK0
6835 00:59:48.613030
6836 00:59:48.613095 DATLAT Default: 0xf
6837 00:59:48.615896 0, 0xFFFF, sum = 0
6838 00:59:48.615979 1, 0xFFFF, sum = 0
6839 00:59:48.618789 2, 0xFFFF, sum = 0
6840 00:59:48.618910 3, 0xFFFF, sum = 0
6841 00:59:48.622045 4, 0xFFFF, sum = 0
6842 00:59:48.622128 5, 0xFFFF, sum = 0
6843 00:59:48.625076 6, 0xFFFF, sum = 0
6844 00:59:48.625158 7, 0xFFFF, sum = 0
6845 00:59:48.628562 8, 0xFFFF, sum = 0
6846 00:59:48.628645 9, 0xFFFF, sum = 0
6847 00:59:48.632162 10, 0xFFFF, sum = 0
6848 00:59:48.632244 11, 0xFFFF, sum = 0
6849 00:59:48.635966 12, 0xFFFF, sum = 0
6850 00:59:48.636048 13, 0x0, sum = 1
6851 00:59:48.639027 14, 0x0, sum = 2
6852 00:59:48.639451 15, 0x0, sum = 3
6853 00:59:48.642957 16, 0x0, sum = 4
6854 00:59:48.643381 best_step = 14
6855 00:59:48.643804
6856 00:59:48.644135 ==
6857 00:59:48.645786 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 00:59:48.652671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 00:59:48.653093 ==
6860 00:59:48.653429 RX Vref Scan: 1
6861 00:59:48.653737
6862 00:59:48.655735 RX Vref 0 -> 0, step: 1
6863 00:59:48.656157
6864 00:59:48.658664 RX Delay -343 -> 252, step: 8
6865 00:59:48.659079
6866 00:59:48.662341 Set Vref, RX VrefLevel [Byte0]: 50
6867 00:59:48.665343 [Byte1]: 54
6868 00:59:48.668776
6869 00:59:48.669193 Final RX Vref Byte 0 = 50 to rank0
6870 00:59:48.672220 Final RX Vref Byte 1 = 54 to rank0
6871 00:59:48.675648 Final RX Vref Byte 0 = 50 to rank1
6872 00:59:48.678582 Final RX Vref Byte 1 = 54 to rank1==
6873 00:59:48.681695 Dram Type= 6, Freq= 0, CH_1, rank 0
6874 00:59:48.688734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 00:59:48.689167 ==
6876 00:59:48.689501 DQS Delay:
6877 00:59:48.692176 DQS0 = 44, DQS1 = 56
6878 00:59:48.692593 DQM Delay:
6879 00:59:48.692924 DQM0 = 7, DQM1 = 12
6880 00:59:48.695469 DQ Delay:
6881 00:59:48.698634 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6882 00:59:48.699053 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6883 00:59:48.702139 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6884 00:59:48.705640 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6885 00:59:48.706056
6886 00:59:48.706383
6887 00:59:48.715289 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6888 00:59:48.718391 CH1 RK0: MR19=C0C, MR18=9B73
6889 00:59:48.725531 CH1_RK0: MR19=0xC0C, MR18=0x9B73, DQSOSC=390, MR23=63, INC=388, DEC=258
6890 00:59:48.725952 ==
6891 00:59:48.728266 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 00:59:48.732188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 00:59:48.732613 ==
6894 00:59:48.734890 [Gating] SW mode calibration
6895 00:59:48.742149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6896 00:59:48.748106 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6897 00:59:48.751833 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6898 00:59:48.755117 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6899 00:59:48.761328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 00:59:48.764624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 00:59:48.767711 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 00:59:48.774710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 00:59:48.777492 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 00:59:48.780883 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 00:59:48.788024 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6906 00:59:48.788445 Total UI for P1: 0, mck2ui 16
6907 00:59:48.794074 best dqsien dly found for B0: ( 0, 14, 24)
6908 00:59:48.794516 Total UI for P1: 0, mck2ui 16
6909 00:59:48.800485 best dqsien dly found for B1: ( 0, 14, 24)
6910 00:59:48.804606 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6911 00:59:48.807165 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6912 00:59:48.807245
6913 00:59:48.810859 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6914 00:59:48.814184 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6915 00:59:48.817991 [Gating] SW calibration Done
6916 00:59:48.818073 ==
6917 00:59:48.820454 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 00:59:48.823245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 00:59:48.823327 ==
6920 00:59:48.826642 RX Vref Scan: 0
6921 00:59:48.826723
6922 00:59:48.826787 RX Vref 0 -> 0, step: 1
6923 00:59:48.826848
6924 00:59:48.830514 RX Delay -410 -> 252, step: 16
6925 00:59:48.836945 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6926 00:59:48.839761 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6927 00:59:48.843343 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6928 00:59:48.846504 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6929 00:59:48.852878 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6930 00:59:48.856432 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6931 00:59:48.860148 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6932 00:59:48.863465 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6933 00:59:48.869783 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6934 00:59:48.872869 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6935 00:59:48.876342 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6936 00:59:48.879391 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6937 00:59:48.886140 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6938 00:59:48.889674 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6939 00:59:48.892912 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6940 00:59:48.899793 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6941 00:59:48.899875 ==
6942 00:59:48.902792 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 00:59:48.906314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 00:59:48.906396 ==
6945 00:59:48.906473 DQS Delay:
6946 00:59:48.908991 DQS0 = 51, DQS1 = 51
6947 00:59:48.909102 DQM Delay:
6948 00:59:48.912929 DQM0 = 19, DQM1 = 14
6949 00:59:48.913010 DQ Delay:
6950 00:59:48.915603 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6951 00:59:48.919052 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6952 00:59:48.923157 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6953 00:59:48.925768 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6954 00:59:48.925849
6955 00:59:48.925913
6956 00:59:48.925972 ==
6957 00:59:48.929239 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 00:59:48.932323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 00:59:48.932431 ==
6960 00:59:48.935793
6961 00:59:48.935874
6962 00:59:48.935939 TX Vref Scan disable
6963 00:59:48.939057 == TX Byte 0 ==
6964 00:59:48.941814 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6965 00:59:48.946424 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6966 00:59:48.949121 == TX Byte 1 ==
6967 00:59:48.952574 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6968 00:59:48.955723 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6969 00:59:48.956150 ==
6970 00:59:48.959107 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 00:59:48.962813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 00:59:48.965720 ==
6973 00:59:48.966396
6974 00:59:48.966987
6975 00:59:48.967472 TX Vref Scan disable
6976 00:59:48.969142 == TX Byte 0 ==
6977 00:59:48.971970 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6978 00:59:48.976456 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6979 00:59:48.979087 == TX Byte 1 ==
6980 00:59:48.982458 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6981 00:59:48.985354 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6982 00:59:48.985774
6983 00:59:48.988453 [DATLAT]
6984 00:59:48.988866 Freq=400, CH1 RK1
6985 00:59:48.989198
6986 00:59:48.992055 DATLAT Default: 0xe
6987 00:59:48.992471 0, 0xFFFF, sum = 0
6988 00:59:48.996039 1, 0xFFFF, sum = 0
6989 00:59:48.996462 2, 0xFFFF, sum = 0
6990 00:59:48.999001 3, 0xFFFF, sum = 0
6991 00:59:48.999424 4, 0xFFFF, sum = 0
6992 00:59:49.001470 5, 0xFFFF, sum = 0
6993 00:59:49.001891 6, 0xFFFF, sum = 0
6994 00:59:49.004974 7, 0xFFFF, sum = 0
6995 00:59:49.005400 8, 0xFFFF, sum = 0
6996 00:59:49.008439 9, 0xFFFF, sum = 0
6997 00:59:49.008862 10, 0xFFFF, sum = 0
6998 00:59:49.011507 11, 0xFFFF, sum = 0
6999 00:59:49.015056 12, 0xFFFF, sum = 0
7000 00:59:49.015484 13, 0x0, sum = 1
7001 00:59:49.015881 14, 0x0, sum = 2
7002 00:59:49.018186 15, 0x0, sum = 3
7003 00:59:49.018621 16, 0x0, sum = 4
7004 00:59:49.021353 best_step = 14
7005 00:59:49.021769
7006 00:59:49.022094 ==
7007 00:59:49.024810 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 00:59:49.028389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 00:59:49.028840 ==
7010 00:59:49.031894 RX Vref Scan: 0
7011 00:59:49.032351
7012 00:59:49.032697 RX Vref 0 -> 0, step: 1
7013 00:59:49.034978
7014 00:59:49.035397 RX Delay -343 -> 252, step: 8
7015 00:59:49.043174 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7016 00:59:49.046959 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7017 00:59:49.049772 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7018 00:59:49.056715 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7019 00:59:49.060204 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7020 00:59:49.062751 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7021 00:59:49.066115 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7022 00:59:49.072584 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7023 00:59:49.075977 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7024 00:59:49.079998 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7025 00:59:49.082757 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7026 00:59:49.089618 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7027 00:59:49.092677 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7028 00:59:49.096067 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7029 00:59:49.099651 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7030 00:59:49.106175 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7031 00:59:49.106715 ==
7032 00:59:49.109412 Dram Type= 6, Freq= 0, CH_1, rank 1
7033 00:59:49.112514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7034 00:59:49.113172 ==
7035 00:59:49.113648 DQS Delay:
7036 00:59:49.116444 DQS0 = 44, DQS1 = 56
7037 00:59:49.116862 DQM Delay:
7038 00:59:49.118867 DQM0 = 10, DQM1 = 11
7039 00:59:49.119287 DQ Delay:
7040 00:59:49.122572 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7041 00:59:49.125454 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7042 00:59:49.128925 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7043 00:59:49.132120 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7044 00:59:49.132201
7045 00:59:49.132265
7046 00:59:49.138270 [DQSOSCAuto] RK1, (LSB)MR18= 0x6655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 396 ps
7047 00:59:49.141777 CH1 RK1: MR19=C0C, MR18=6655
7048 00:59:49.148011 CH1_RK1: MR19=0xC0C, MR18=0x6655, DQSOSC=396, MR23=63, INC=376, DEC=251
7049 00:59:49.151385 [RxdqsGatingPostProcess] freq 400
7050 00:59:49.158407 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7051 00:59:49.161440 best DQS0 dly(2T, 0.5T) = (0, 10)
7052 00:59:49.164939 best DQS1 dly(2T, 0.5T) = (0, 10)
7053 00:59:49.168262 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7054 00:59:49.171446 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7055 00:59:49.174744 best DQS0 dly(2T, 0.5T) = (0, 10)
7056 00:59:49.174825 best DQS1 dly(2T, 0.5T) = (0, 10)
7057 00:59:49.177811 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7058 00:59:49.181126 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7059 00:59:49.184308 Pre-setting of DQS Precalculation
7060 00:59:49.191265 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7061 00:59:49.197951 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7062 00:59:49.204851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7063 00:59:49.204932
7064 00:59:49.204996
7065 00:59:49.207592 [Calibration Summary] 800 Mbps
7066 00:59:49.210620 CH 0, Rank 0
7067 00:59:49.210700 SW Impedance : PASS
7068 00:59:49.213892 DUTY Scan : NO K
7069 00:59:49.217846 ZQ Calibration : PASS
7070 00:59:49.217927 Jitter Meter : NO K
7071 00:59:49.221046 CBT Training : PASS
7072 00:59:49.221127 Write leveling : PASS
7073 00:59:49.224824 RX DQS gating : PASS
7074 00:59:49.227153 RX DQ/DQS(RDDQC) : PASS
7075 00:59:49.227255 TX DQ/DQS : PASS
7076 00:59:49.230429 RX DATLAT : PASS
7077 00:59:49.233609 RX DQ/DQS(Engine): PASS
7078 00:59:49.233690 TX OE : NO K
7079 00:59:49.237033 All Pass.
7080 00:59:49.237114
7081 00:59:49.237177 CH 0, Rank 1
7082 00:59:49.240387 SW Impedance : PASS
7083 00:59:49.240468 DUTY Scan : NO K
7084 00:59:49.243931 ZQ Calibration : PASS
7085 00:59:49.246973 Jitter Meter : NO K
7086 00:59:49.247055 CBT Training : PASS
7087 00:59:49.250236 Write leveling : NO K
7088 00:59:49.253411 RX DQS gating : PASS
7089 00:59:49.253492 RX DQ/DQS(RDDQC) : PASS
7090 00:59:49.256508 TX DQ/DQS : PASS
7091 00:59:49.260006 RX DATLAT : PASS
7092 00:59:49.260087 RX DQ/DQS(Engine): PASS
7093 00:59:49.263929 TX OE : NO K
7094 00:59:49.264010 All Pass.
7095 00:59:49.264073
7096 00:59:49.266861 CH 1, Rank 0
7097 00:59:49.266942 SW Impedance : PASS
7098 00:59:49.269915 DUTY Scan : NO K
7099 00:59:49.273220 ZQ Calibration : PASS
7100 00:59:49.273302 Jitter Meter : NO K
7101 00:59:49.276681 CBT Training : PASS
7102 00:59:49.279873 Write leveling : PASS
7103 00:59:49.279954 RX DQS gating : PASS
7104 00:59:49.283852 RX DQ/DQS(RDDQC) : PASS
7105 00:59:49.286627 TX DQ/DQS : PASS
7106 00:59:49.286708 RX DATLAT : PASS
7107 00:59:49.289333 RX DQ/DQS(Engine): PASS
7108 00:59:49.293408 TX OE : NO K
7109 00:59:49.293489 All Pass.
7110 00:59:49.293553
7111 00:59:49.293612 CH 1, Rank 1
7112 00:59:49.296792 SW Impedance : PASS
7113 00:59:49.299494 DUTY Scan : NO K
7114 00:59:49.299575 ZQ Calibration : PASS
7115 00:59:49.302643 Jitter Meter : NO K
7116 00:59:49.306346 CBT Training : PASS
7117 00:59:49.306427 Write leveling : NO K
7118 00:59:49.309526 RX DQS gating : PASS
7119 00:59:49.312855 RX DQ/DQS(RDDQC) : PASS
7120 00:59:49.312936 TX DQ/DQS : PASS
7121 00:59:49.315612 RX DATLAT : PASS
7122 00:59:49.319434 RX DQ/DQS(Engine): PASS
7123 00:59:49.319515 TX OE : NO K
7124 00:59:49.319580 All Pass.
7125 00:59:49.322696
7126 00:59:49.322777 DramC Write-DBI off
7127 00:59:49.325705 PER_BANK_REFRESH: Hybrid Mode
7128 00:59:49.325786 TX_TRACKING: ON
7129 00:59:49.335840 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7130 00:59:49.338839 [FAST_K] Save calibration result to emmc
7131 00:59:49.341861 dramc_set_vcore_voltage set vcore to 725000
7132 00:59:49.345085 Read voltage for 1600, 0
7133 00:59:49.345167 Vio18 = 0
7134 00:59:49.348338 Vcore = 725000
7135 00:59:49.348456 Vdram = 0
7136 00:59:49.348525 Vddq = 0
7137 00:59:49.352187 Vmddr = 0
7138 00:59:49.355291 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7139 00:59:49.361518 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7140 00:59:49.361600 MEM_TYPE=3, freq_sel=13
7141 00:59:49.365611 sv_algorithm_assistance_LP4_3733
7142 00:59:49.371556 ============ PULL DRAM RESETB DOWN ============
7143 00:59:49.374880 ========== PULL DRAM RESETB DOWN end =========
7144 00:59:49.377988 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7145 00:59:49.381680 ===================================
7146 00:59:49.384560 LPDDR4 DRAM CONFIGURATION
7147 00:59:49.387776 ===================================
7148 00:59:49.391091 EX_ROW_EN[0] = 0x0
7149 00:59:49.391172 EX_ROW_EN[1] = 0x0
7150 00:59:49.394559 LP4Y_EN = 0x0
7151 00:59:49.394639 WORK_FSP = 0x1
7152 00:59:49.399008 WL = 0x5
7153 00:59:49.399114 RL = 0x5
7154 00:59:49.401090 BL = 0x2
7155 00:59:49.401171 RPST = 0x0
7156 00:59:49.405133 RD_PRE = 0x0
7157 00:59:49.405214 WR_PRE = 0x1
7158 00:59:49.407757 WR_PST = 0x1
7159 00:59:49.407838 DBI_WR = 0x0
7160 00:59:49.411374 DBI_RD = 0x0
7161 00:59:49.411455 OTF = 0x1
7162 00:59:49.414203 ===================================
7163 00:59:49.418065 ===================================
7164 00:59:49.421181 ANA top config
7165 00:59:49.424387 ===================================
7166 00:59:49.427327 DLL_ASYNC_EN = 0
7167 00:59:49.427408 ALL_SLAVE_EN = 0
7168 00:59:49.431201 NEW_RANK_MODE = 1
7169 00:59:49.434227 DLL_IDLE_MODE = 1
7170 00:59:49.437256 LP45_APHY_COMB_EN = 1
7171 00:59:49.440914 TX_ODT_DIS = 0
7172 00:59:49.440996 NEW_8X_MODE = 1
7173 00:59:49.444768 ===================================
7174 00:59:49.447562 ===================================
7175 00:59:49.450983 data_rate = 3200
7176 00:59:49.454190 CKR = 1
7177 00:59:49.457237 DQ_P2S_RATIO = 8
7178 00:59:49.460639 ===================================
7179 00:59:49.464525 CA_P2S_RATIO = 8
7180 00:59:49.467188 DQ_CA_OPEN = 0
7181 00:59:49.467268 DQ_SEMI_OPEN = 0
7182 00:59:49.470232 CA_SEMI_OPEN = 0
7183 00:59:49.473792 CA_FULL_RATE = 0
7184 00:59:49.477159 DQ_CKDIV4_EN = 0
7185 00:59:49.480619 CA_CKDIV4_EN = 0
7186 00:59:49.483623 CA_PREDIV_EN = 0
7187 00:59:49.483788 PH8_DLY = 12
7188 00:59:49.486730 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7189 00:59:49.490487 DQ_AAMCK_DIV = 4
7190 00:59:49.493515 CA_AAMCK_DIV = 4
7191 00:59:49.496972 CA_ADMCK_DIV = 4
7192 00:59:49.500160 DQ_TRACK_CA_EN = 0
7193 00:59:49.503562 CA_PICK = 1600
7194 00:59:49.503717 CA_MCKIO = 1600
7195 00:59:49.506790 MCKIO_SEMI = 0
7196 00:59:49.510331 PLL_FREQ = 3068
7197 00:59:49.513433 DQ_UI_PI_RATIO = 32
7198 00:59:49.516847 CA_UI_PI_RATIO = 0
7199 00:59:49.519870 ===================================
7200 00:59:49.523394 ===================================
7201 00:59:49.526708 memory_type:LPDDR4
7202 00:59:49.526787 GP_NUM : 10
7203 00:59:49.529661 SRAM_EN : 1
7204 00:59:49.529739 MD32_EN : 0
7205 00:59:49.533115 ===================================
7206 00:59:49.536731 [ANA_INIT] >>>>>>>>>>>>>>
7207 00:59:49.540006 <<<<<< [CONFIGURE PHASE]: ANA_TX
7208 00:59:49.542780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7209 00:59:49.546172 ===================================
7210 00:59:49.549713 data_rate = 3200,PCW = 0X7600
7211 00:59:49.552776 ===================================
7212 00:59:49.556461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7213 00:59:49.562781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7214 00:59:49.566390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7215 00:59:49.572494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7216 00:59:49.576423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7217 00:59:49.579593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7218 00:59:49.579695 [ANA_INIT] flow start
7219 00:59:49.582751 [ANA_INIT] PLL >>>>>>>>
7220 00:59:49.586615 [ANA_INIT] PLL <<<<<<<<
7221 00:59:49.586693 [ANA_INIT] MIDPI >>>>>>>>
7222 00:59:49.589079 [ANA_INIT] MIDPI <<<<<<<<
7223 00:59:49.592490 [ANA_INIT] DLL >>>>>>>>
7224 00:59:49.596708 [ANA_INIT] DLL <<<<<<<<
7225 00:59:49.596786 [ANA_INIT] flow end
7226 00:59:49.599359 ============ LP4 DIFF to SE enter ============
7227 00:59:49.606659 ============ LP4 DIFF to SE exit ============
7228 00:59:49.606738 [ANA_INIT] <<<<<<<<<<<<<
7229 00:59:49.609487 [Flow] Enable top DCM control >>>>>
7230 00:59:49.612280 [Flow] Enable top DCM control <<<<<
7231 00:59:49.615897 Enable DLL master slave shuffle
7232 00:59:49.622368 ==============================================================
7233 00:59:49.622448 Gating Mode config
7234 00:59:49.629185 ==============================================================
7235 00:59:49.631897 Config description:
7236 00:59:49.642412 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7237 00:59:49.648800 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7238 00:59:49.651946 SELPH_MODE 0: By rank 1: By Phase
7239 00:59:49.658415 ==============================================================
7240 00:59:49.661995 GAT_TRACK_EN = 1
7241 00:59:49.664950 RX_GATING_MODE = 2
7242 00:59:49.668268 RX_GATING_TRACK_MODE = 2
7243 00:59:49.668346 SELPH_MODE = 1
7244 00:59:49.672000 PICG_EARLY_EN = 1
7245 00:59:49.674523 VALID_LAT_VALUE = 1
7246 00:59:49.681417 ==============================================================
7247 00:59:49.684958 Enter into Gating configuration >>>>
7248 00:59:49.687854 Exit from Gating configuration <<<<
7249 00:59:49.691199 Enter into DVFS_PRE_config >>>>>
7250 00:59:49.701140 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7251 00:59:49.704811 Exit from DVFS_PRE_config <<<<<
7252 00:59:49.708675 Enter into PICG configuration >>>>
7253 00:59:49.711120 Exit from PICG configuration <<<<
7254 00:59:49.714306 [RX_INPUT] configuration >>>>>
7255 00:59:49.717784 [RX_INPUT] configuration <<<<<
7256 00:59:49.721019 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7257 00:59:49.728123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7258 00:59:49.734972 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7259 00:59:49.741010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7260 00:59:49.747562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7261 00:59:49.754097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7262 00:59:49.757302 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7263 00:59:49.760982 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7264 00:59:49.764002 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7265 00:59:49.771305 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7266 00:59:49.774208 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7267 00:59:49.777387 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7268 00:59:49.780779 ===================================
7269 00:59:49.783776 LPDDR4 DRAM CONFIGURATION
7270 00:59:49.787347 ===================================
7271 00:59:49.787799 EX_ROW_EN[0] = 0x0
7272 00:59:49.790787 EX_ROW_EN[1] = 0x0
7273 00:59:49.793639 LP4Y_EN = 0x0
7274 00:59:49.794050 WORK_FSP = 0x1
7275 00:59:49.797499 WL = 0x5
7276 00:59:49.797926 RL = 0x5
7277 00:59:49.800493 BL = 0x2
7278 00:59:49.800906 RPST = 0x0
7279 00:59:49.803778 RD_PRE = 0x0
7280 00:59:49.804195 WR_PRE = 0x1
7281 00:59:49.806977 WR_PST = 0x1
7282 00:59:49.807390 DBI_WR = 0x0
7283 00:59:49.810221 DBI_RD = 0x0
7284 00:59:49.810634 OTF = 0x1
7285 00:59:49.813659 ===================================
7286 00:59:49.816861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7287 00:59:49.823811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7288 00:59:49.827284 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7289 00:59:49.830364 ===================================
7290 00:59:49.833267 LPDDR4 DRAM CONFIGURATION
7291 00:59:49.836650 ===================================
7292 00:59:49.837083 EX_ROW_EN[0] = 0x10
7293 00:59:49.840253 EX_ROW_EN[1] = 0x0
7294 00:59:49.843085 LP4Y_EN = 0x0
7295 00:59:49.843496 WORK_FSP = 0x1
7296 00:59:49.846723 WL = 0x5
7297 00:59:49.847149 RL = 0x5
7298 00:59:49.849895 BL = 0x2
7299 00:59:49.850308 RPST = 0x0
7300 00:59:49.853155 RD_PRE = 0x0
7301 00:59:49.853568 WR_PRE = 0x1
7302 00:59:49.856477 WR_PST = 0x1
7303 00:59:49.856889 DBI_WR = 0x0
7304 00:59:49.860235 DBI_RD = 0x0
7305 00:59:49.860666 OTF = 0x1
7306 00:59:49.863259 ===================================
7307 00:59:49.869710 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7308 00:59:49.870132 ==
7309 00:59:49.872972 Dram Type= 6, Freq= 0, CH_0, rank 0
7310 00:59:49.876208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 00:59:49.879532 ==
7312 00:59:49.879983 [Duty_Offset_Calibration]
7313 00:59:49.882842 B0:1 B1:-1 CA:0
7314 00:59:49.883256
7315 00:59:49.886343 [DutyScan_Calibration_Flow] k_type=0
7316 00:59:49.896053
7317 00:59:49.896483 ==CLK 0==
7318 00:59:49.898693 Final CLK duty delay cell = 0
7319 00:59:49.902063 [0] MAX Duty = 5124%(X100), DQS PI = 22
7320 00:59:49.905293 [0] MIN Duty = 4907%(X100), DQS PI = 4
7321 00:59:49.905711 [0] AVG Duty = 5015%(X100)
7322 00:59:49.908727
7323 00:59:49.912083 CH0 CLK Duty spec in!! Max-Min= 217%
7324 00:59:49.915037 [DutyScan_Calibration_Flow] ====Done====
7325 00:59:49.915538
7326 00:59:49.918357 [DutyScan_Calibration_Flow] k_type=1
7327 00:59:49.934423
7328 00:59:49.934840 ==DQS 0 ==
7329 00:59:49.938080 Final DQS duty delay cell = -4
7330 00:59:49.941055 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7331 00:59:49.944541 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7332 00:59:49.947343 [-4] AVG Duty = 4906%(X100)
7333 00:59:49.947797
7334 00:59:49.948134 ==DQS 1 ==
7335 00:59:49.951284 Final DQS duty delay cell = 0
7336 00:59:49.953993 [0] MAX Duty = 5187%(X100), DQS PI = 4
7337 00:59:49.957517 [0] MIN Duty = 5031%(X100), DQS PI = 16
7338 00:59:49.960954 [0] AVG Duty = 5109%(X100)
7339 00:59:49.961368
7340 00:59:49.965122 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7341 00:59:49.965538
7342 00:59:49.967443 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7343 00:59:49.970521 [DutyScan_Calibration_Flow] ====Done====
7344 00:59:49.970934
7345 00:59:49.973702 [DutyScan_Calibration_Flow] k_type=3
7346 00:59:49.992111
7347 00:59:49.992583 ==DQM 0 ==
7348 00:59:49.995662 Final DQM duty delay cell = 0
7349 00:59:49.998671 [0] MAX Duty = 5124%(X100), DQS PI = 20
7350 00:59:50.001608 [0] MIN Duty = 4907%(X100), DQS PI = 10
7351 00:59:50.005470 [0] AVG Duty = 5015%(X100)
7352 00:59:50.005885
7353 00:59:50.006211 ==DQM 1 ==
7354 00:59:50.008081 Final DQM duty delay cell = 0
7355 00:59:50.011571 [0] MAX Duty = 5000%(X100), DQS PI = 4
7356 00:59:50.015076 [0] MIN Duty = 4813%(X100), DQS PI = 20
7357 00:59:50.018281 [0] AVG Duty = 4906%(X100)
7358 00:59:50.018990
7359 00:59:50.021362 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7360 00:59:50.021956
7361 00:59:50.024721 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7362 00:59:50.027989 [DutyScan_Calibration_Flow] ====Done====
7363 00:59:50.028401
7364 00:59:50.031557 [DutyScan_Calibration_Flow] k_type=2
7365 00:59:50.048529
7366 00:59:50.048941 ==DQ 0 ==
7367 00:59:50.052178 Final DQ duty delay cell = -4
7368 00:59:50.054984 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7369 00:59:50.058606 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7370 00:59:50.061380 [-4] AVG Duty = 4953%(X100)
7371 00:59:50.061858
7372 00:59:50.062393 ==DQ 1 ==
7373 00:59:50.064680 Final DQ duty delay cell = 0
7374 00:59:50.069174 [0] MAX Duty = 5125%(X100), DQS PI = 4
7375 00:59:50.072121 [0] MIN Duty = 5000%(X100), DQS PI = 36
7376 00:59:50.074619 [0] AVG Duty = 5062%(X100)
7377 00:59:50.075062
7378 00:59:50.077730 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7379 00:59:50.078170
7380 00:59:50.081260 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7381 00:59:50.084453 [DutyScan_Calibration_Flow] ====Done====
7382 00:59:50.084876 ==
7383 00:59:50.088143 Dram Type= 6, Freq= 0, CH_1, rank 0
7384 00:59:50.090943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7385 00:59:50.091368 ==
7386 00:59:50.094355 [Duty_Offset_Calibration]
7387 00:59:50.094771 B0:-1 B1:1 CA:2
7388 00:59:50.097498
7389 00:59:50.101060 [DutyScan_Calibration_Flow] k_type=0
7390 00:59:50.109177
7391 00:59:50.109607 ==CLK 0==
7392 00:59:50.112214 Final CLK duty delay cell = 0
7393 00:59:50.115838 [0] MAX Duty = 5187%(X100), DQS PI = 26
7394 00:59:50.118767 [0] MIN Duty = 4969%(X100), DQS PI = 0
7395 00:59:50.119185 [0] AVG Duty = 5078%(X100)
7396 00:59:50.122384
7397 00:59:50.125459 CH1 CLK Duty spec in!! Max-Min= 218%
7398 00:59:50.128719 [DutyScan_Calibration_Flow] ====Done====
7399 00:59:50.129137
7400 00:59:50.132161 [DutyScan_Calibration_Flow] k_type=1
7401 00:59:50.149051
7402 00:59:50.149653 ==DQS 0 ==
7403 00:59:50.152196 Final DQS duty delay cell = 0
7404 00:59:50.155601 [0] MAX Duty = 5124%(X100), DQS PI = 18
7405 00:59:50.158585 [0] MIN Duty = 4907%(X100), DQS PI = 10
7406 00:59:50.161804 [0] AVG Duty = 5015%(X100)
7407 00:59:50.162223
7408 00:59:50.162615 ==DQS 1 ==
7409 00:59:50.165065 Final DQS duty delay cell = 0
7410 00:59:50.168402 [0] MAX Duty = 5093%(X100), DQS PI = 24
7411 00:59:50.171874 [0] MIN Duty = 4969%(X100), DQS PI = 56
7412 00:59:50.174974 [0] AVG Duty = 5031%(X100)
7413 00:59:50.175481
7414 00:59:50.178491 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7415 00:59:50.179019
7416 00:59:50.181974 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7417 00:59:50.185877 [DutyScan_Calibration_Flow] ====Done====
7418 00:59:50.186392
7419 00:59:50.187757 [DutyScan_Calibration_Flow] k_type=3
7420 00:59:50.205170
7421 00:59:50.205724 ==DQM 0 ==
7422 00:59:50.208148 Final DQM duty delay cell = -4
7423 00:59:50.211813 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7424 00:59:50.214948 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7425 00:59:50.218576 [-4] AVG Duty = 4937%(X100)
7426 00:59:50.219040
7427 00:59:50.219403 ==DQM 1 ==
7428 00:59:50.221490 Final DQM duty delay cell = 0
7429 00:59:50.224452 [0] MAX Duty = 5156%(X100), DQS PI = 8
7430 00:59:50.227978 [0] MIN Duty = 4969%(X100), DQS PI = 34
7431 00:59:50.231269 [0] AVG Duty = 5062%(X100)
7432 00:59:50.231717
7433 00:59:50.234411 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7434 00:59:50.234885
7435 00:59:50.238206 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7436 00:59:50.241182 [DutyScan_Calibration_Flow] ====Done====
7437 00:59:50.241644
7438 00:59:50.244418 [DutyScan_Calibration_Flow] k_type=2
7439 00:59:50.262047
7440 00:59:50.262617 ==DQ 0 ==
7441 00:59:50.265540 Final DQ duty delay cell = 0
7442 00:59:50.268751 [0] MAX Duty = 5187%(X100), DQS PI = 32
7443 00:59:50.271836 [0] MIN Duty = 4906%(X100), DQS PI = 10
7444 00:59:50.272391 [0] AVG Duty = 5046%(X100)
7445 00:59:50.275469
7446 00:59:50.276175 ==DQ 1 ==
7447 00:59:50.278769 Final DQ duty delay cell = 0
7448 00:59:50.281679 [0] MAX Duty = 5156%(X100), DQS PI = 8
7449 00:59:50.285482 [0] MIN Duty = 4938%(X100), DQS PI = 60
7450 00:59:50.286032 [0] AVG Duty = 5047%(X100)
7451 00:59:50.286398
7452 00:59:50.292026 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7453 00:59:50.292489
7454 00:59:50.295326 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7455 00:59:50.298448 [DutyScan_Calibration_Flow] ====Done====
7456 00:59:50.301984 nWR fixed to 30
7457 00:59:50.302535 [ModeRegInit_LP4] CH0 RK0
7458 00:59:50.305129 [ModeRegInit_LP4] CH0 RK1
7459 00:59:50.308619 [ModeRegInit_LP4] CH1 RK0
7460 00:59:50.311195 [ModeRegInit_LP4] CH1 RK1
7461 00:59:50.311709 match AC timing 5
7462 00:59:50.317985 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7463 00:59:50.322041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7464 00:59:50.325180 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7465 00:59:50.331162 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7466 00:59:50.334855 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7467 00:59:50.335335 [MiockJmeterHQA]
7468 00:59:50.335738
7469 00:59:50.338038 [DramcMiockJmeter] u1RxGatingPI = 0
7470 00:59:50.341280 0 : 4363, 4137
7471 00:59:50.341749 4 : 4252, 4027
7472 00:59:50.344650 8 : 4365, 4140
7473 00:59:50.345119 12 : 4253, 4027
7474 00:59:50.345492 16 : 4255, 4029
7475 00:59:50.348829 20 : 4368, 4140
7476 00:59:50.349296 24 : 4252, 4027
7477 00:59:50.351171 28 : 4252, 4027
7478 00:59:50.351661 32 : 4252, 4026
7479 00:59:50.354608 36 : 4255, 4030
7480 00:59:50.355172 40 : 4252, 4027
7481 00:59:50.357637 44 : 4252, 4027
7482 00:59:50.358154 48 : 4366, 4140
7483 00:59:50.358531 52 : 4252, 4027
7484 00:59:50.361119 56 : 4255, 4029
7485 00:59:50.361585 60 : 4250, 4026
7486 00:59:50.364212 64 : 4361, 4137
7487 00:59:50.364680 68 : 4250, 4027
7488 00:59:50.367731 72 : 4361, 4137
7489 00:59:50.368203 76 : 4250, 4027
7490 00:59:50.371027 80 : 4250, 4027
7491 00:59:50.371582 84 : 4250, 4026
7492 00:59:50.372030 88 : 4252, 4029
7493 00:59:50.374061 92 : 4361, 553
7494 00:59:50.374536 96 : 4253, 0
7495 00:59:50.377583 100 : 4362, 0
7496 00:59:50.378050 104 : 4361, 0
7497 00:59:50.378420 108 : 4363, 0
7498 00:59:50.380705 112 : 4250, 0
7499 00:59:50.381174 116 : 4250, 0
7500 00:59:50.384039 120 : 4249, 0
7501 00:59:50.384502 124 : 4253, 0
7502 00:59:50.384907 128 : 4250, 0
7503 00:59:50.387392 132 : 4249, 0
7504 00:59:50.387857 136 : 4252, 0
7505 00:59:50.391030 140 : 4361, 0
7506 00:59:50.391551 144 : 4249, 0
7507 00:59:50.391952 148 : 4250, 0
7508 00:59:50.393905 152 : 4360, 0
7509 00:59:50.394331 156 : 4360, 0
7510 00:59:50.397416 160 : 4363, 0
7511 00:59:50.397839 164 : 4250, 0
7512 00:59:50.398178 168 : 4361, 0
7513 00:59:50.400366 172 : 4250, 0
7514 00:59:50.400789 176 : 4250, 0
7515 00:59:50.401300 180 : 4250, 0
7516 00:59:50.403859 184 : 4250, 0
7517 00:59:50.404286 188 : 4252, 0
7518 00:59:50.406951 192 : 4361, 0
7519 00:59:50.407374 196 : 4250, 0
7520 00:59:50.407752 200 : 4249, 0
7521 00:59:50.410457 204 : 4360, 0
7522 00:59:50.410878 208 : 4361, 0
7523 00:59:50.413727 212 : 4363, 0
7524 00:59:50.414149 216 : 4250, 0
7525 00:59:50.414483 220 : 4250, 0
7526 00:59:50.416997 224 : 4363, 341
7527 00:59:50.417422 228 : 4252, 3488
7528 00:59:50.420437 232 : 4250, 4027
7529 00:59:50.420864 236 : 4250, 4027
7530 00:59:50.423437 240 : 4250, 4027
7531 00:59:50.423963 244 : 4250, 4026
7532 00:59:50.427060 248 : 4250, 4027
7533 00:59:50.427484 252 : 4252, 4030
7534 00:59:50.430107 256 : 4250, 4027
7535 00:59:50.430528 260 : 4360, 4137
7536 00:59:50.434069 264 : 4361, 4137
7537 00:59:50.434492 268 : 4250, 4027
7538 00:59:50.434831 272 : 4363, 4140
7539 00:59:50.437147 276 : 4249, 4027
7540 00:59:50.437571 280 : 4250, 4026
7541 00:59:50.440538 284 : 4250, 4027
7542 00:59:50.440964 288 : 4252, 4030
7543 00:59:50.443353 292 : 4250, 4027
7544 00:59:50.443925 296 : 4250, 4027
7545 00:59:50.446600 300 : 4250, 4027
7546 00:59:50.447023 304 : 4252, 4030
7547 00:59:50.450048 308 : 4249, 4027
7548 00:59:50.450475 312 : 4360, 4137
7549 00:59:50.453370 316 : 4361, 4137
7550 00:59:50.453774 320 : 4250, 4027
7551 00:59:50.456413 324 : 4363, 4140
7552 00:59:50.456839 328 : 4249, 4027
7553 00:59:50.459805 332 : 4250, 4026
7554 00:59:50.460226 336 : 4250, 3919
7555 00:59:50.460564 340 : 4252, 2194
7556 00:59:50.463395 344 : 4249, 74
7557 00:59:50.463859
7558 00:59:50.466895 MIOCK jitter meter ch=0
7559 00:59:50.467311
7560 00:59:50.467642 1T = (344-92) = 252 dly cells
7561 00:59:50.473187 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7562 00:59:50.473693 ==
7563 00:59:50.476417 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 00:59:50.483040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 00:59:50.483554 ==
7566 00:59:50.486385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 00:59:50.490434 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 00:59:50.496153 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 00:59:50.502989 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 00:59:50.510526 [CA 0] Center 43 (13~74) winsize 62
7571 00:59:50.513462 [CA 1] Center 43 (13~74) winsize 62
7572 00:59:50.517198 [CA 2] Center 39 (10~69) winsize 60
7573 00:59:50.520373 [CA 3] Center 38 (9~68) winsize 60
7574 00:59:50.523735 [CA 4] Center 37 (8~66) winsize 59
7575 00:59:50.527269 [CA 5] Center 36 (7~66) winsize 60
7576 00:59:50.527783
7577 00:59:50.529994 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 00:59:50.530456
7579 00:59:50.536493 [CATrainingPosCal] consider 1 rank data
7580 00:59:50.536956 u2DelayCellTimex100 = 258/100 ps
7581 00:59:50.543034 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7582 00:59:50.547083 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7583 00:59:50.549799 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7584 00:59:50.552767 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7585 00:59:50.556833 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7586 00:59:50.559949 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7587 00:59:50.560499
7588 00:59:50.562747 CA PerBit enable=1, Macro0, CA PI delay=36
7589 00:59:50.563231
7590 00:59:50.566610 [CBTSetCACLKResult] CA Dly = 36
7591 00:59:50.569198 CS Dly: 12 (0~43)
7592 00:59:50.572710 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 00:59:50.575994 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 00:59:50.579531 ==
7595 00:59:50.580076 Dram Type= 6, Freq= 0, CH_0, rank 1
7596 00:59:50.585791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 00:59:50.586354 ==
7598 00:59:50.589538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7599 00:59:50.596313 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7600 00:59:50.599058 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7601 00:59:50.605551 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7602 00:59:50.613712 [CA 0] Center 43 (13~74) winsize 62
7603 00:59:50.617674 [CA 1] Center 44 (14~74) winsize 61
7604 00:59:50.620405 [CA 2] Center 38 (9~68) winsize 60
7605 00:59:50.624408 [CA 3] Center 38 (9~68) winsize 60
7606 00:59:50.627227 [CA 4] Center 36 (7~66) winsize 60
7607 00:59:50.630908 [CA 5] Center 36 (7~66) winsize 60
7608 00:59:50.631468
7609 00:59:50.633949 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7610 00:59:50.634412
7611 00:59:50.640556 [CATrainingPosCal] consider 2 rank data
7612 00:59:50.641019 u2DelayCellTimex100 = 258/100 ps
7613 00:59:50.646747 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7614 00:59:50.649737 CA1 delay=44 (14~74),Diff = 8 PI (30 cell)
7615 00:59:50.653541 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7616 00:59:50.657046 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7617 00:59:50.660078 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7618 00:59:50.663435 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7619 00:59:50.663973
7620 00:59:50.666496 CA PerBit enable=1, Macro0, CA PI delay=36
7621 00:59:50.666954
7622 00:59:50.670542 [CBTSetCACLKResult] CA Dly = 36
7623 00:59:50.673276 CS Dly: 12 (0~44)
7624 00:59:50.676440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7625 00:59:50.680150 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7626 00:59:50.680612
7627 00:59:50.683395 ----->DramcWriteLeveling(PI) begin...
7628 00:59:50.684028 ==
7629 00:59:50.686811 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 00:59:50.693340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 00:59:50.693899 ==
7632 00:59:50.696290 Write leveling (Byte 0): 35 => 35
7633 00:59:50.699788 Write leveling (Byte 1): 26 => 26
7634 00:59:50.702871 DramcWriteLeveling(PI) end<-----
7635 00:59:50.703330
7636 00:59:50.703728 ==
7637 00:59:50.706076 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 00:59:50.709420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 00:59:50.709883 ==
7640 00:59:50.712894 [Gating] SW mode calibration
7641 00:59:50.719350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7642 00:59:50.726078 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7643 00:59:50.729395 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 00:59:50.732656 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 00:59:50.739392 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 00:59:50.742686 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7647 00:59:50.746575 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7648 00:59:50.752274 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
7649 00:59:50.755858 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7650 00:59:50.758654 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 00:59:50.765632 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 00:59:50.768616 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 00:59:50.771886 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 00:59:50.778633 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7655 00:59:50.782582 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7656 00:59:50.785957 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7657 00:59:50.792917 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7658 00:59:50.795602 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 00:59:50.798439 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 00:59:50.805374 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 00:59:50.809049 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 00:59:50.811943 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7663 00:59:50.818254 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7664 00:59:50.821852 1 6 20 | B1->B0 | 3030 4646 | 1 0 | (1 1) (0 0)
7665 00:59:50.824810 1 6 24 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7666 00:59:50.831791 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 00:59:50.834726 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 00:59:50.838541 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 00:59:50.844638 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 00:59:50.847957 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7671 00:59:50.851137 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7672 00:59:50.858031 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7673 00:59:50.860863 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7674 00:59:50.864308 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 00:59:50.871021 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 00:59:50.874146 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 00:59:50.877577 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 00:59:50.884413 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 00:59:50.887433 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 00:59:50.890574 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 00:59:50.897326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 00:59:50.900812 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 00:59:50.903940 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 00:59:50.910277 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 00:59:50.913817 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7686 00:59:50.916799 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7687 00:59:50.923781 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7688 00:59:50.924212 Total UI for P1: 0, mck2ui 16
7689 00:59:50.930123 best dqsien dly found for B0: ( 1, 9, 10)
7690 00:59:50.933747 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7691 00:59:50.937070 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 00:59:50.943437 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 00:59:50.943519 Total UI for P1: 0, mck2ui 16
7694 00:59:50.946226 best dqsien dly found for B1: ( 1, 9, 20)
7695 00:59:50.952955 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7696 00:59:50.956280 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7697 00:59:50.956362
7698 00:59:50.959508 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7699 00:59:50.962958 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7700 00:59:50.966243 [Gating] SW calibration Done
7701 00:59:50.966335 ==
7702 00:59:50.969526 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 00:59:50.972288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 00:59:50.972398 ==
7705 00:59:50.976196 RX Vref Scan: 0
7706 00:59:50.976278
7707 00:59:50.976381 RX Vref 0 -> 0, step: 1
7708 00:59:50.976471
7709 00:59:50.979273 RX Delay 0 -> 252, step: 8
7710 00:59:50.982499 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7711 00:59:50.989655 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7712 00:59:50.992775 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7713 00:59:50.995697 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7714 00:59:50.998794 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7715 00:59:51.002515 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7716 00:59:51.009425 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7717 00:59:51.012232 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7718 00:59:51.016306 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7719 00:59:51.019323 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7720 00:59:51.022535 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7721 00:59:51.029234 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7722 00:59:51.032634 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7723 00:59:51.035494 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7724 00:59:51.038870 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7725 00:59:51.045696 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7726 00:59:51.045778 ==
7727 00:59:51.048502 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 00:59:51.051980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 00:59:51.052069 ==
7730 00:59:51.052138 DQS Delay:
7731 00:59:51.054997 DQS0 = 0, DQS1 = 0
7732 00:59:51.055091 DQM Delay:
7733 00:59:51.058635 DQM0 = 136, DQM1 = 126
7734 00:59:51.058737 DQ Delay:
7735 00:59:51.061990 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7736 00:59:51.065011 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7737 00:59:51.068701 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7738 00:59:51.072632 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7739 00:59:51.072754
7740 00:59:51.072851
7741 00:59:51.075524 ==
7742 00:59:51.078449 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 00:59:51.081782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 00:59:51.081935 ==
7745 00:59:51.082055
7746 00:59:51.082167
7747 00:59:51.085101 TX Vref Scan disable
7748 00:59:51.085275 == TX Byte 0 ==
7749 00:59:51.091417 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7750 00:59:51.094818 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7751 00:59:51.095060 == TX Byte 1 ==
7752 00:59:51.101589 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7753 00:59:51.105089 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7754 00:59:51.105400 ==
7755 00:59:51.108494 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 00:59:51.111472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 00:59:51.111805 ==
7758 00:59:51.126702
7759 00:59:51.129128 TX Vref early break, caculate TX vref
7760 00:59:51.131829 TX Vref=16, minBit 4, minWin=22, winSum=370
7761 00:59:51.135483 TX Vref=18, minBit 1, minWin=23, winSum=376
7762 00:59:51.138869 TX Vref=20, minBit 0, minWin=24, winSum=388
7763 00:59:51.142113 TX Vref=22, minBit 0, minWin=24, winSum=400
7764 00:59:51.144851 TX Vref=24, minBit 0, minWin=25, winSum=408
7765 00:59:51.152108 TX Vref=26, minBit 1, minWin=25, winSum=414
7766 00:59:51.154910 TX Vref=28, minBit 4, minWin=25, winSum=417
7767 00:59:51.158499 TX Vref=30, minBit 0, minWin=25, winSum=410
7768 00:59:51.161930 TX Vref=32, minBit 5, minWin=23, winSum=397
7769 00:59:51.165389 TX Vref=34, minBit 4, minWin=22, winSum=387
7770 00:59:51.171339 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
7771 00:59:51.171427
7772 00:59:51.175082 Final TX Range 0 Vref 28
7773 00:59:51.175177
7774 00:59:51.175252 ==
7775 00:59:51.177997 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 00:59:51.181595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 00:59:51.181704 ==
7778 00:59:51.181785
7779 00:59:51.181859
7780 00:59:51.185051 TX Vref Scan disable
7781 00:59:51.191312 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7782 00:59:51.191434 == TX Byte 0 ==
7783 00:59:51.194542 u2DelayCellOfst[0]=15 cells (4 PI)
7784 00:59:51.197849 u2DelayCellOfst[1]=18 cells (5 PI)
7785 00:59:51.201514 u2DelayCellOfst[2]=15 cells (4 PI)
7786 00:59:51.204819 u2DelayCellOfst[3]=15 cells (4 PI)
7787 00:59:51.208067 u2DelayCellOfst[4]=11 cells (3 PI)
7788 00:59:51.211090 u2DelayCellOfst[5]=0 cells (0 PI)
7789 00:59:51.214832 u2DelayCellOfst[6]=18 cells (5 PI)
7790 00:59:51.218251 u2DelayCellOfst[7]=22 cells (6 PI)
7791 00:59:51.221053 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7792 00:59:51.224303 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7793 00:59:51.227427 == TX Byte 1 ==
7794 00:59:51.231040 u2DelayCellOfst[8]=0 cells (0 PI)
7795 00:59:51.234203 u2DelayCellOfst[9]=3 cells (1 PI)
7796 00:59:51.237605 u2DelayCellOfst[10]=7 cells (2 PI)
7797 00:59:51.237723 u2DelayCellOfst[11]=3 cells (1 PI)
7798 00:59:51.241307 u2DelayCellOfst[12]=15 cells (4 PI)
7799 00:59:51.244475 u2DelayCellOfst[13]=15 cells (4 PI)
7800 00:59:51.247499 u2DelayCellOfst[14]=18 cells (5 PI)
7801 00:59:51.250550 u2DelayCellOfst[15]=15 cells (4 PI)
7802 00:59:51.257896 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7803 00:59:51.260740 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7804 00:59:51.260928 DramC Write-DBI on
7805 00:59:51.264832 ==
7806 00:59:51.264991 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 00:59:51.270671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 00:59:51.270909 ==
7809 00:59:51.271067
7810 00:59:51.271248
7811 00:59:51.274223 TX Vref Scan disable
7812 00:59:51.274535 == TX Byte 0 ==
7813 00:59:51.280814 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7814 00:59:51.281203 == TX Byte 1 ==
7815 00:59:51.284153 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7816 00:59:51.287588 DramC Write-DBI off
7817 00:59:51.287952
7818 00:59:51.288187 [DATLAT]
7819 00:59:51.290569 Freq=1600, CH0 RK0
7820 00:59:51.290902
7821 00:59:51.291144 DATLAT Default: 0xf
7822 00:59:51.294180 0, 0xFFFF, sum = 0
7823 00:59:51.294593 1, 0xFFFF, sum = 0
7824 00:59:51.296978 2, 0xFFFF, sum = 0
7825 00:59:51.297398 3, 0xFFFF, sum = 0
7826 00:59:51.300462 4, 0xFFFF, sum = 0
7827 00:59:51.300940 5, 0xFFFF, sum = 0
7828 00:59:51.303797 6, 0xFFFF, sum = 0
7829 00:59:51.306683 7, 0xFFFF, sum = 0
7830 00:59:51.306759 8, 0xFFFF, sum = 0
7831 00:59:51.309803 9, 0xFFFF, sum = 0
7832 00:59:51.309880 10, 0xFFFF, sum = 0
7833 00:59:51.313657 11, 0xFFFF, sum = 0
7834 00:59:51.313767 12, 0xFFFF, sum = 0
7835 00:59:51.316420 13, 0xFFFF, sum = 0
7836 00:59:51.316561 14, 0x0, sum = 1
7837 00:59:51.319815 15, 0x0, sum = 2
7838 00:59:51.319923 16, 0x0, sum = 3
7839 00:59:51.323493 17, 0x0, sum = 4
7840 00:59:51.323609 best_step = 15
7841 00:59:51.323726
7842 00:59:51.323792 ==
7843 00:59:51.326674 Dram Type= 6, Freq= 0, CH_0, rank 0
7844 00:59:51.329935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7845 00:59:51.333100 ==
7846 00:59:51.333227 RX Vref Scan: 1
7847 00:59:51.333319
7848 00:59:51.336424 Set Vref Range= 24 -> 127
7849 00:59:51.336513
7850 00:59:51.340482 RX Vref 24 -> 127, step: 1
7851 00:59:51.340585
7852 00:59:51.340670 RX Delay 11 -> 252, step: 4
7853 00:59:51.340759
7854 00:59:51.342935 Set Vref, RX VrefLevel [Byte0]: 24
7855 00:59:51.346537 [Byte1]: 24
7856 00:59:51.350247
7857 00:59:51.350412 Set Vref, RX VrefLevel [Byte0]: 25
7858 00:59:51.353206 [Byte1]: 25
7859 00:59:51.358557
7860 00:59:51.358787 Set Vref, RX VrefLevel [Byte0]: 26
7861 00:59:51.361044 [Byte1]: 26
7862 00:59:51.366326
7863 00:59:51.366533 Set Vref, RX VrefLevel [Byte0]: 27
7864 00:59:51.368570 [Byte1]: 27
7865 00:59:51.372990
7866 00:59:51.373228 Set Vref, RX VrefLevel [Byte0]: 28
7867 00:59:51.376360 [Byte1]: 28
7868 00:59:51.380478
7869 00:59:51.380716 Set Vref, RX VrefLevel [Byte0]: 29
7870 00:59:51.384217 [Byte1]: 29
7871 00:59:51.388038
7872 00:59:51.388277 Set Vref, RX VrefLevel [Byte0]: 30
7873 00:59:51.391756 [Byte1]: 30
7874 00:59:51.395991
7875 00:59:51.396229 Set Vref, RX VrefLevel [Byte0]: 31
7876 00:59:51.400095 [Byte1]: 31
7877 00:59:51.403936
7878 00:59:51.404177 Set Vref, RX VrefLevel [Byte0]: 32
7879 00:59:51.406793 [Byte1]: 32
7880 00:59:51.411609
7881 00:59:51.411874 Set Vref, RX VrefLevel [Byte0]: 33
7882 00:59:51.414277 [Byte1]: 33
7883 00:59:51.419522
7884 00:59:51.419779 Set Vref, RX VrefLevel [Byte0]: 34
7885 00:59:51.422493 [Byte1]: 34
7886 00:59:51.426246
7887 00:59:51.426484 Set Vref, RX VrefLevel [Byte0]: 35
7888 00:59:51.429620 [Byte1]: 35
7889 00:59:51.434726
7890 00:59:51.434964 Set Vref, RX VrefLevel [Byte0]: 36
7891 00:59:51.437337 [Byte1]: 36
7892 00:59:51.441701
7893 00:59:51.441940 Set Vref, RX VrefLevel [Byte0]: 37
7894 00:59:51.444491 [Byte1]: 37
7895 00:59:51.449791
7896 00:59:51.449872 Set Vref, RX VrefLevel [Byte0]: 38
7897 00:59:51.452222 [Byte1]: 38
7898 00:59:51.457010
7899 00:59:51.457091 Set Vref, RX VrefLevel [Byte0]: 39
7900 00:59:51.460266 [Byte1]: 39
7901 00:59:51.464168
7902 00:59:51.464249 Set Vref, RX VrefLevel [Byte0]: 40
7903 00:59:51.467584 [Byte1]: 40
7904 00:59:51.471881
7905 00:59:51.471962 Set Vref, RX VrefLevel [Byte0]: 41
7906 00:59:51.475155 [Byte1]: 41
7907 00:59:51.479713
7908 00:59:51.479794 Set Vref, RX VrefLevel [Byte0]: 42
7909 00:59:51.483279 [Byte1]: 42
7910 00:59:51.487290
7911 00:59:51.487371 Set Vref, RX VrefLevel [Byte0]: 43
7912 00:59:51.493810 [Byte1]: 43
7913 00:59:51.493891
7914 00:59:51.496791 Set Vref, RX VrefLevel [Byte0]: 44
7915 00:59:51.500913 [Byte1]: 44
7916 00:59:51.500994
7917 00:59:51.503970 Set Vref, RX VrefLevel [Byte0]: 45
7918 00:59:51.507408 [Byte1]: 45
7919 00:59:51.507489
7920 00:59:51.510479 Set Vref, RX VrefLevel [Byte0]: 46
7921 00:59:51.514205 [Byte1]: 46
7922 00:59:51.517583
7923 00:59:51.517661 Set Vref, RX VrefLevel [Byte0]: 47
7924 00:59:51.520605 [Byte1]: 47
7925 00:59:51.525614
7926 00:59:51.525711 Set Vref, RX VrefLevel [Byte0]: 48
7927 00:59:51.528589 [Byte1]: 48
7928 00:59:51.532956
7929 00:59:51.533033 Set Vref, RX VrefLevel [Byte0]: 49
7930 00:59:51.536319 [Byte1]: 49
7931 00:59:51.540410
7932 00:59:51.540491 Set Vref, RX VrefLevel [Byte0]: 50
7933 00:59:51.544334 [Byte1]: 50
7934 00:59:51.548357
7935 00:59:51.548437 Set Vref, RX VrefLevel [Byte0]: 51
7936 00:59:51.551134 [Byte1]: 51
7937 00:59:51.555421
7938 00:59:51.555505 Set Vref, RX VrefLevel [Byte0]: 52
7939 00:59:51.559633 [Byte1]: 52
7940 00:59:51.563290
7941 00:59:51.563371 Set Vref, RX VrefLevel [Byte0]: 53
7942 00:59:51.567355 [Byte1]: 53
7943 00:59:51.570823
7944 00:59:51.570904 Set Vref, RX VrefLevel [Byte0]: 54
7945 00:59:51.574458 [Byte1]: 54
7946 00:59:51.578441
7947 00:59:51.578522 Set Vref, RX VrefLevel [Byte0]: 55
7948 00:59:51.581705 [Byte1]: 55
7949 00:59:51.586305
7950 00:59:51.586386 Set Vref, RX VrefLevel [Byte0]: 56
7951 00:59:51.592923 [Byte1]: 56
7952 00:59:51.593005
7953 00:59:51.596167 Set Vref, RX VrefLevel [Byte0]: 57
7954 00:59:51.598917 [Byte1]: 57
7955 00:59:51.598998
7956 00:59:51.602585 Set Vref, RX VrefLevel [Byte0]: 58
7957 00:59:51.606050 [Byte1]: 58
7958 00:59:51.606131
7959 00:59:51.609173 Set Vref, RX VrefLevel [Byte0]: 59
7960 00:59:51.612249 [Byte1]: 59
7961 00:59:51.616557
7962 00:59:51.616637 Set Vref, RX VrefLevel [Byte0]: 60
7963 00:59:51.619823 [Byte1]: 60
7964 00:59:51.624701
7965 00:59:51.624781 Set Vref, RX VrefLevel [Byte0]: 61
7966 00:59:51.627334 [Byte1]: 61
7967 00:59:51.631701
7968 00:59:51.631801 Set Vref, RX VrefLevel [Byte0]: 62
7969 00:59:51.635470 [Byte1]: 62
7970 00:59:51.639282
7971 00:59:51.639363 Set Vref, RX VrefLevel [Byte0]: 63
7972 00:59:51.642848 [Byte1]: 63
7973 00:59:51.646784
7974 00:59:51.646864 Set Vref, RX VrefLevel [Byte0]: 64
7975 00:59:51.650041 [Byte1]: 64
7976 00:59:51.654876
7977 00:59:51.655000 Set Vref, RX VrefLevel [Byte0]: 65
7978 00:59:51.657782 [Byte1]: 65
7979 00:59:51.662089
7980 00:59:51.662170 Set Vref, RX VrefLevel [Byte0]: 66
7981 00:59:51.666073 [Byte1]: 66
7982 00:59:51.669638
7983 00:59:51.669723 Set Vref, RX VrefLevel [Byte0]: 67
7984 00:59:51.673856 [Byte1]: 67
7985 00:59:51.677604
7986 00:59:51.677689 Set Vref, RX VrefLevel [Byte0]: 68
7987 00:59:51.680479 [Byte1]: 68
7988 00:59:51.685448
7989 00:59:51.685529 Set Vref, RX VrefLevel [Byte0]: 69
7990 00:59:51.691731 [Byte1]: 69
7991 00:59:51.691815
7992 00:59:51.694737 Set Vref, RX VrefLevel [Byte0]: 70
7993 00:59:51.698010 [Byte1]: 70
7994 00:59:51.698101
7995 00:59:51.700973 Set Vref, RX VrefLevel [Byte0]: 71
7996 00:59:51.704515 [Byte1]: 71
7997 00:59:51.708035
7998 00:59:51.708116 Set Vref, RX VrefLevel [Byte0]: 72
7999 00:59:51.710872 [Byte1]: 72
8000 00:59:51.716094
8001 00:59:51.716175 Set Vref, RX VrefLevel [Byte0]: 73
8002 00:59:51.718922 [Byte1]: 73
8003 00:59:51.723619
8004 00:59:51.723737 Set Vref, RX VrefLevel [Byte0]: 74
8005 00:59:51.726427 [Byte1]: 74
8006 00:59:51.731071
8007 00:59:51.731152 Set Vref, RX VrefLevel [Byte0]: 75
8008 00:59:51.734617 [Byte1]: 75
8009 00:59:51.738520
8010 00:59:51.738601 Set Vref, RX VrefLevel [Byte0]: 76
8011 00:59:51.741886 [Byte1]: 76
8012 00:59:51.746151
8013 00:59:51.746232 Set Vref, RX VrefLevel [Byte0]: 77
8014 00:59:51.749959 [Byte1]: 77
8015 00:59:51.753525
8016 00:59:51.753606 Set Vref, RX VrefLevel [Byte0]: 78
8017 00:59:51.756761 [Byte1]: 78
8018 00:59:51.761002
8019 00:59:51.761085 Final RX Vref Byte 0 = 66 to rank0
8020 00:59:51.764173 Final RX Vref Byte 1 = 57 to rank0
8021 00:59:51.767570 Final RX Vref Byte 0 = 66 to rank1
8022 00:59:51.770819 Final RX Vref Byte 1 = 57 to rank1==
8023 00:59:51.774618 Dram Type= 6, Freq= 0, CH_0, rank 0
8024 00:59:51.780786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 00:59:51.780894 ==
8026 00:59:51.780987 DQS Delay:
8027 00:59:51.783887 DQS0 = 0, DQS1 = 0
8028 00:59:51.783968 DQM Delay:
8029 00:59:51.787010 DQM0 = 133, DQM1 = 123
8030 00:59:51.787097 DQ Delay:
8031 00:59:51.790496 DQ0 =130, DQ1 =134, DQ2 =132, DQ3 =132
8032 00:59:51.793993 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8033 00:59:51.798391 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =116
8034 00:59:51.800849 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
8035 00:59:51.800930
8036 00:59:51.800994
8037 00:59:51.801053
8038 00:59:51.803563 [DramC_TX_OE_Calibration] TA2
8039 00:59:51.807752 Original DQ_B0 (3 6) =30, OEN = 27
8040 00:59:51.810679 Original DQ_B1 (3 6) =30, OEN = 27
8041 00:59:51.813819 24, 0x0, End_B0=24 End_B1=24
8042 00:59:51.816750 25, 0x0, End_B0=25 End_B1=25
8043 00:59:51.816833 26, 0x0, End_B0=26 End_B1=26
8044 00:59:51.820414 27, 0x0, End_B0=27 End_B1=27
8045 00:59:51.823635 28, 0x0, End_B0=28 End_B1=28
8046 00:59:51.826736 29, 0x0, End_B0=29 End_B1=29
8047 00:59:51.830136 30, 0x0, End_B0=30 End_B1=30
8048 00:59:51.830219 31, 0x4141, End_B0=30 End_B1=30
8049 00:59:51.833923 Byte0 end_step=30 best_step=27
8050 00:59:51.836585 Byte1 end_step=30 best_step=27
8051 00:59:51.840166 Byte0 TX OE(2T, 0.5T) = (3, 3)
8052 00:59:51.843212 Byte1 TX OE(2T, 0.5T) = (3, 3)
8053 00:59:51.843300
8054 00:59:51.843365
8055 00:59:51.849616 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8056 00:59:51.853189 CH0 RK0: MR19=303, MR18=2415
8057 00:59:51.859591 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8058 00:59:51.859681
8059 00:59:51.863037 ----->DramcWriteLeveling(PI) begin...
8060 00:59:51.863119 ==
8061 00:59:51.866254 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 00:59:51.869528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 00:59:51.872899 ==
8064 00:59:51.872980 Write leveling (Byte 0): 34 => 34
8065 00:59:51.876070 Write leveling (Byte 1): 28 => 28
8066 00:59:51.879692 DramcWriteLeveling(PI) end<-----
8067 00:59:51.879787
8068 00:59:51.879851 ==
8069 00:59:51.882579 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 00:59:51.889255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 00:59:51.889347 ==
8072 00:59:51.892745 [Gating] SW mode calibration
8073 00:59:51.898960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8074 00:59:51.903178 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8075 00:59:51.908964 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 00:59:51.912114 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 00:59:51.915866 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 00:59:51.922609 1 4 12 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8079 00:59:51.925703 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8080 00:59:51.928880 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8081 00:59:51.935946 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 00:59:51.938836 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 00:59:51.942335 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 00:59:51.949197 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 00:59:51.951976 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8086 00:59:51.955368 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8087 00:59:51.962652 1 5 16 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 0)
8088 00:59:51.965146 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8089 00:59:51.968949 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 00:59:51.975522 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 00:59:51.978905 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 00:59:51.981923 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 00:59:51.988670 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 00:59:51.991992 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8095 00:59:51.995035 1 6 16 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8096 00:59:52.001674 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8097 00:59:52.005221 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 00:59:52.008248 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 00:59:52.015152 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 00:59:52.018352 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 00:59:52.021616 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8102 00:59:52.028053 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8103 00:59:52.031215 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 00:59:52.034718 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8105 00:59:52.041036 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 00:59:52.044358 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 00:59:52.049467 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 00:59:52.054299 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 00:59:52.057616 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 00:59:52.061036 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 00:59:52.067911 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 00:59:52.070816 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 00:59:52.074527 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 00:59:52.080856 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 00:59:52.084006 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 00:59:52.088138 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 00:59:52.094591 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8118 00:59:52.097776 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8119 00:59:52.100845 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8120 00:59:52.104262 Total UI for P1: 0, mck2ui 16
8121 00:59:52.107235 best dqsien dly found for B0: ( 1, 9, 10)
8122 00:59:52.113789 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8123 00:59:52.117249 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 00:59:52.121149 Total UI for P1: 0, mck2ui 16
8125 00:59:52.124363 best dqsien dly found for B1: ( 1, 9, 18)
8126 00:59:52.127487 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8127 00:59:52.130561 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8128 00:59:52.131120
8129 00:59:52.134211 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8130 00:59:52.137908 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8131 00:59:52.140033 [Gating] SW calibration Done
8132 00:59:52.140498 ==
8133 00:59:52.143780 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 00:59:52.149863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 00:59:52.150406 ==
8136 00:59:52.150780 RX Vref Scan: 0
8137 00:59:52.151123
8138 00:59:52.153935 RX Vref 0 -> 0, step: 1
8139 00:59:52.154395
8140 00:59:52.156719 RX Delay 0 -> 252, step: 8
8141 00:59:52.160067 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8142 00:59:52.163916 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8143 00:59:52.166479 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8144 00:59:52.169899 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8145 00:59:52.176895 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8146 00:59:52.179817 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8147 00:59:52.182890 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8148 00:59:52.186154 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8149 00:59:52.189670 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8150 00:59:52.196695 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8151 00:59:52.199812 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8152 00:59:52.203440 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8153 00:59:52.206854 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8154 00:59:52.212891 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8155 00:59:52.215830 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8156 00:59:52.219626 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8157 00:59:52.220248 ==
8158 00:59:52.222518 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 00:59:52.226224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 00:59:52.226804 ==
8161 00:59:52.229155 DQS Delay:
8162 00:59:52.229614 DQS0 = 0, DQS1 = 0
8163 00:59:52.232237 DQM Delay:
8164 00:59:52.232694 DQM0 = 133, DQM1 = 129
8165 00:59:52.235660 DQ Delay:
8166 00:59:52.238917 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8167 00:59:52.242216 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8168 00:59:52.245815 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8169 00:59:52.249280 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8170 00:59:52.249740
8171 00:59:52.250097
8172 00:59:52.250434 ==
8173 00:59:52.252296 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 00:59:52.256097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 00:59:52.256513 ==
8176 00:59:52.256841
8177 00:59:52.257356
8178 00:59:52.258613 TX Vref Scan disable
8179 00:59:52.261845 == TX Byte 0 ==
8180 00:59:52.265614 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8181 00:59:52.268542 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8182 00:59:52.271664 == TX Byte 1 ==
8183 00:59:52.275138 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8184 00:59:52.279109 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8185 00:59:52.279523 ==
8186 00:59:52.281994 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 00:59:52.289066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 00:59:52.289485 ==
8189 00:59:52.300227
8190 00:59:52.302801 TX Vref early break, caculate TX vref
8191 00:59:52.306443 TX Vref=16, minBit 1, minWin=22, winSum=376
8192 00:59:52.309493 TX Vref=18, minBit 4, minWin=23, winSum=387
8193 00:59:52.312618 TX Vref=20, minBit 2, minWin=23, winSum=395
8194 00:59:52.315579 TX Vref=22, minBit 1, minWin=24, winSum=404
8195 00:59:52.319001 TX Vref=24, minBit 1, minWin=24, winSum=409
8196 00:59:52.325559 TX Vref=26, minBit 0, minWin=25, winSum=416
8197 00:59:52.329156 TX Vref=28, minBit 0, minWin=25, winSum=412
8198 00:59:52.332434 TX Vref=30, minBit 0, minWin=24, winSum=405
8199 00:59:52.335898 TX Vref=32, minBit 5, minWin=23, winSum=394
8200 00:59:52.342477 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8201 00:59:52.343051
8202 00:59:52.345768 Final TX Range 0 Vref 26
8203 00:59:52.346330
8204 00:59:52.346693 ==
8205 00:59:52.348982 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 00:59:52.352016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 00:59:52.352475 ==
8208 00:59:52.352837
8209 00:59:52.353173
8210 00:59:52.355081 TX Vref Scan disable
8211 00:59:52.362039 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8212 00:59:52.362603 == TX Byte 0 ==
8213 00:59:52.365186 u2DelayCellOfst[0]=11 cells (3 PI)
8214 00:59:52.368372 u2DelayCellOfst[1]=15 cells (4 PI)
8215 00:59:52.371895 u2DelayCellOfst[2]=11 cells (3 PI)
8216 00:59:52.375719 u2DelayCellOfst[3]=15 cells (4 PI)
8217 00:59:52.379256 u2DelayCellOfst[4]=7 cells (2 PI)
8218 00:59:52.381457 u2DelayCellOfst[5]=0 cells (0 PI)
8219 00:59:52.384751 u2DelayCellOfst[6]=15 cells (4 PI)
8220 00:59:52.389093 u2DelayCellOfst[7]=18 cells (5 PI)
8221 00:59:52.391531 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8222 00:59:52.395467 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8223 00:59:52.398725 == TX Byte 1 ==
8224 00:59:52.401392 u2DelayCellOfst[8]=0 cells (0 PI)
8225 00:59:52.401867 u2DelayCellOfst[9]=3 cells (1 PI)
8226 00:59:52.405357 u2DelayCellOfst[10]=7 cells (2 PI)
8227 00:59:52.408211 u2DelayCellOfst[11]=3 cells (1 PI)
8228 00:59:52.411541 u2DelayCellOfst[12]=15 cells (4 PI)
8229 00:59:52.414585 u2DelayCellOfst[13]=15 cells (4 PI)
8230 00:59:52.417794 u2DelayCellOfst[14]=18 cells (5 PI)
8231 00:59:52.421125 u2DelayCellOfst[15]=11 cells (3 PI)
8232 00:59:52.427441 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8233 00:59:52.431084 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8234 00:59:52.431542 DramC Write-DBI on
8235 00:59:52.431946 ==
8236 00:59:52.434036 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 00:59:52.441095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 00:59:52.441645 ==
8239 00:59:52.442008
8240 00:59:52.442345
8241 00:59:52.443968 TX Vref Scan disable
8242 00:59:52.444427 == TX Byte 0 ==
8243 00:59:52.450646 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8244 00:59:52.451276 == TX Byte 1 ==
8245 00:59:52.454134 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8246 00:59:52.457097 DramC Write-DBI off
8247 00:59:52.457663
8248 00:59:52.458029 [DATLAT]
8249 00:59:52.461282 Freq=1600, CH0 RK1
8250 00:59:52.461839
8251 00:59:52.462199 DATLAT Default: 0xf
8252 00:59:52.463645 0, 0xFFFF, sum = 0
8253 00:59:52.464153 1, 0xFFFF, sum = 0
8254 00:59:52.466853 2, 0xFFFF, sum = 0
8255 00:59:52.467317 3, 0xFFFF, sum = 0
8256 00:59:52.470617 4, 0xFFFF, sum = 0
8257 00:59:52.471179 5, 0xFFFF, sum = 0
8258 00:59:52.473413 6, 0xFFFF, sum = 0
8259 00:59:52.474042 7, 0xFFFF, sum = 0
8260 00:59:52.477029 8, 0xFFFF, sum = 0
8261 00:59:52.480493 9, 0xFFFF, sum = 0
8262 00:59:52.481061 10, 0xFFFF, sum = 0
8263 00:59:52.483738 11, 0xFFFF, sum = 0
8264 00:59:52.484316 12, 0xFFFF, sum = 0
8265 00:59:52.486817 13, 0xFFFF, sum = 0
8266 00:59:52.487384 14, 0x0, sum = 1
8267 00:59:52.490282 15, 0x0, sum = 2
8268 00:59:52.490849 16, 0x0, sum = 3
8269 00:59:52.494054 17, 0x0, sum = 4
8270 00:59:52.494618 best_step = 15
8271 00:59:52.494979
8272 00:59:52.495354 ==
8273 00:59:52.497247 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 00:59:52.500115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 00:59:52.504690 ==
8276 00:59:52.505248 RX Vref Scan: 0
8277 00:59:52.505613
8278 00:59:52.507183 RX Vref 0 -> 0, step: 1
8279 00:59:52.507896
8280 00:59:52.508275 RX Delay 11 -> 252, step: 4
8281 00:59:52.514342 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8282 00:59:52.516867 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8283 00:59:52.520930 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8284 00:59:52.523729 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8285 00:59:52.530399 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8286 00:59:52.533784 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8287 00:59:52.537166 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8288 00:59:52.540399 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8289 00:59:52.543738 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8290 00:59:52.550053 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8291 00:59:52.553946 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8292 00:59:52.557039 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8293 00:59:52.559664 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8294 00:59:52.563796 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8295 00:59:52.569978 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8296 00:59:52.572752 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8297 00:59:52.573207 ==
8298 00:59:52.576537 Dram Type= 6, Freq= 0, CH_0, rank 1
8299 00:59:52.579949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 00:59:52.580501 ==
8301 00:59:52.583021 DQS Delay:
8302 00:59:52.583571 DQS0 = 0, DQS1 = 0
8303 00:59:52.587237 DQM Delay:
8304 00:59:52.587735 DQM0 = 130, DQM1 = 125
8305 00:59:52.588108 DQ Delay:
8306 00:59:52.589311 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8307 00:59:52.596082 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8308 00:59:52.599558 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8309 00:59:52.602352 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8310 00:59:52.602809
8311 00:59:52.603165
8312 00:59:52.603493
8313 00:59:52.605974 [DramC_TX_OE_Calibration] TA2
8314 00:59:52.609607 Original DQ_B0 (3 6) =30, OEN = 27
8315 00:59:52.612625 Original DQ_B1 (3 6) =30, OEN = 27
8316 00:59:52.613177 24, 0x0, End_B0=24 End_B1=24
8317 00:59:52.616195 25, 0x0, End_B0=25 End_B1=25
8318 00:59:52.619302 26, 0x0, End_B0=26 End_B1=26
8319 00:59:52.622601 27, 0x0, End_B0=27 End_B1=27
8320 00:59:52.626640 28, 0x0, End_B0=28 End_B1=28
8321 00:59:52.627203 29, 0x0, End_B0=29 End_B1=29
8322 00:59:52.629097 30, 0x0, End_B0=30 End_B1=30
8323 00:59:52.632757 31, 0x4141, End_B0=30 End_B1=30
8324 00:59:52.636792 Byte0 end_step=30 best_step=27
8325 00:59:52.639298 Byte1 end_step=30 best_step=27
8326 00:59:52.639905 Byte0 TX OE(2T, 0.5T) = (3, 3)
8327 00:59:52.643230 Byte1 TX OE(2T, 0.5T) = (3, 3)
8328 00:59:52.643827
8329 00:59:52.644192
8330 00:59:52.652139 [DQSOSCAuto] RK1, (LSB)MR18= 0x2205, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
8331 00:59:52.655438 CH0 RK1: MR19=303, MR18=2205
8332 00:59:52.662536 CH0_RK1: MR19=0x303, MR18=0x2205, DQSOSC=392, MR23=63, INC=24, DEC=16
8333 00:59:52.662997 [RxdqsGatingPostProcess] freq 1600
8334 00:59:52.668680 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8335 00:59:52.671981 best DQS0 dly(2T, 0.5T) = (1, 1)
8336 00:59:52.675801 best DQS1 dly(2T, 0.5T) = (1, 1)
8337 00:59:52.678908 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8338 00:59:52.681917 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8339 00:59:52.685601 best DQS0 dly(2T, 0.5T) = (1, 1)
8340 00:59:52.688360 best DQS1 dly(2T, 0.5T) = (1, 1)
8341 00:59:52.691975 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8342 00:59:52.695612 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8343 00:59:52.696205 Pre-setting of DQS Precalculation
8344 00:59:52.702091 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8345 00:59:52.702567 ==
8346 00:59:52.705237 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 00:59:52.708685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 00:59:52.709145 ==
8349 00:59:52.715138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8350 00:59:52.718234 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8351 00:59:52.724951 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8352 00:59:52.728307 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8353 00:59:52.738428 [CA 0] Center 41 (12~70) winsize 59
8354 00:59:52.741442 [CA 1] Center 41 (12~71) winsize 60
8355 00:59:52.744973 [CA 2] Center 37 (8~66) winsize 59
8356 00:59:52.748366 [CA 3] Center 36 (7~65) winsize 59
8357 00:59:52.751531 [CA 4] Center 37 (7~67) winsize 61
8358 00:59:52.754617 [CA 5] Center 36 (7~65) winsize 59
8359 00:59:52.755177
8360 00:59:52.757980 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8361 00:59:52.758541
8362 00:59:52.764623 [CATrainingPosCal] consider 1 rank data
8363 00:59:52.765199 u2DelayCellTimex100 = 258/100 ps
8364 00:59:52.771431 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8365 00:59:52.774068 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8366 00:59:52.777690 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8367 00:59:52.781374 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8368 00:59:52.784066 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8369 00:59:52.787124 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8370 00:59:52.787728
8371 00:59:52.790584 CA PerBit enable=1, Macro0, CA PI delay=36
8372 00:59:52.791143
8373 00:59:52.794053 [CBTSetCACLKResult] CA Dly = 36
8374 00:59:52.797388 CS Dly: 10 (0~41)
8375 00:59:52.800840 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8376 00:59:52.803796 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8377 00:59:52.804358 ==
8378 00:59:52.807877 Dram Type= 6, Freq= 0, CH_1, rank 1
8379 00:59:52.813872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 00:59:52.814414 ==
8381 00:59:52.816821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8382 00:59:52.824224 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8383 00:59:52.827097 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8384 00:59:52.833101 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8385 00:59:52.842223 [CA 0] Center 42 (13~72) winsize 60
8386 00:59:52.844386 [CA 1] Center 42 (13~72) winsize 60
8387 00:59:52.847821 [CA 2] Center 37 (8~67) winsize 60
8388 00:59:52.851564 [CA 3] Center 37 (8~66) winsize 59
8389 00:59:52.854960 [CA 4] Center 37 (8~67) winsize 60
8390 00:59:52.858056 [CA 5] Center 37 (8~66) winsize 59
8391 00:59:52.858609
8392 00:59:52.861245 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8393 00:59:52.861704
8394 00:59:52.867798 [CATrainingPosCal] consider 2 rank data
8395 00:59:52.868256 u2DelayCellTimex100 = 258/100 ps
8396 00:59:52.874338 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8397 00:59:52.877728 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8398 00:59:52.881643 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8399 00:59:52.884073 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8400 00:59:52.887198 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8401 00:59:52.890593 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8402 00:59:52.891155
8403 00:59:52.894294 CA PerBit enable=1, Macro0, CA PI delay=36
8404 00:59:52.894852
8405 00:59:52.897285 [CBTSetCACLKResult] CA Dly = 36
8406 00:59:52.901256 CS Dly: 11 (0~44)
8407 00:59:52.903918 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8408 00:59:52.906802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8409 00:59:52.907263
8410 00:59:52.910759 ----->DramcWriteLeveling(PI) begin...
8411 00:59:52.911322 ==
8412 00:59:52.913951 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 00:59:52.920359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 00:59:52.920824 ==
8415 00:59:52.923815 Write leveling (Byte 0): 25 => 25
8416 00:59:52.926933 Write leveling (Byte 1): 26 => 26
8417 00:59:52.930575 DramcWriteLeveling(PI) end<-----
8418 00:59:52.931038
8419 00:59:52.931404 ==
8420 00:59:52.933366 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 00:59:52.936644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 00:59:52.937113 ==
8423 00:59:52.940057 [Gating] SW mode calibration
8424 00:59:52.946474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8425 00:59:52.953135 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8426 00:59:52.956209 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 00:59:52.960125 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 00:59:52.966127 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
8429 00:59:52.969776 1 4 12 | B1->B0 | 2929 2f2f | 1 1 | (0 0) (1 1)
8430 00:59:52.972701 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 00:59:52.979783 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 00:59:52.983120 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 00:59:52.986591 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 00:59:52.992729 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 00:59:52.996406 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 00:59:52.999292 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8437 00:59:53.006449 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8438 00:59:53.009239 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8439 00:59:53.012936 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 00:59:53.018982 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 00:59:53.022708 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 00:59:53.027002 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 00:59:53.032640 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 00:59:53.035403 1 6 8 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (0 0)
8445 00:59:53.039190 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8446 00:59:53.045642 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 00:59:53.048748 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 00:59:53.052245 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 00:59:53.058698 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 00:59:53.061968 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 00:59:53.066248 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 00:59:53.071784 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 00:59:53.075038 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8454 00:59:53.078353 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 00:59:53.085033 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 00:59:53.088209 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 00:59:53.091591 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 00:59:53.098206 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 00:59:53.101085 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 00:59:53.104285 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 00:59:53.112034 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 00:59:53.114597 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 00:59:53.117662 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 00:59:53.124312 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 00:59:53.127476 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 00:59:53.130728 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 00:59:53.137236 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 00:59:53.140267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8469 00:59:53.143550 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8470 00:59:53.150053 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8471 00:59:53.153563 Total UI for P1: 0, mck2ui 16
8472 00:59:53.156890 best dqsien dly found for B0: ( 1, 9, 10)
8473 00:59:53.160206 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 00:59:53.163595 Total UI for P1: 0, mck2ui 16
8475 00:59:53.166291 best dqsien dly found for B1: ( 1, 9, 12)
8476 00:59:53.169573 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8477 00:59:53.172972 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8478 00:59:53.173091
8479 00:59:53.176669 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8480 00:59:53.182956 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8481 00:59:53.183051 [Gating] SW calibration Done
8482 00:59:53.183126 ==
8483 00:59:53.186185 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 00:59:53.192591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 00:59:53.192679 ==
8486 00:59:53.192746 RX Vref Scan: 0
8487 00:59:53.192810
8488 00:59:53.195879 RX Vref 0 -> 0, step: 1
8489 00:59:53.195961
8490 00:59:53.199451 RX Delay 0 -> 252, step: 8
8491 00:59:53.203316 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8492 00:59:53.206073 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8493 00:59:53.209290 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8494 00:59:53.215941 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8495 00:59:53.218978 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8496 00:59:53.222354 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8497 00:59:53.225789 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8498 00:59:53.229146 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8499 00:59:53.235241 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8500 00:59:53.238804 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8501 00:59:53.242304 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8502 00:59:53.245299 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8503 00:59:53.248883 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8504 00:59:53.255961 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8505 00:59:53.258950 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8506 00:59:53.261874 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8507 00:59:53.261957 ==
8508 00:59:53.265304 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 00:59:53.268416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 00:59:53.271874 ==
8511 00:59:53.271956 DQS Delay:
8512 00:59:53.272020 DQS0 = 0, DQS1 = 0
8513 00:59:53.275326 DQM Delay:
8514 00:59:53.275407 DQM0 = 138, DQM1 = 130
8515 00:59:53.278356 DQ Delay:
8516 00:59:53.282097 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8517 00:59:53.285498 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8518 00:59:53.288060 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8519 00:59:53.292274 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8520 00:59:53.292355
8521 00:59:53.292419
8522 00:59:53.292478 ==
8523 00:59:53.295129 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 00:59:53.298605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 00:59:53.298686 ==
8526 00:59:53.301447
8527 00:59:53.301527
8528 00:59:53.301590 TX Vref Scan disable
8529 00:59:53.304856 == TX Byte 0 ==
8530 00:59:53.308166 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8531 00:59:53.311791 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8532 00:59:53.314542 == TX Byte 1 ==
8533 00:59:53.319875 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8534 00:59:53.322566 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8535 00:59:53.322647 ==
8536 00:59:53.325910 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 00:59:53.331346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 00:59:53.331448 ==
8539 00:59:53.342951
8540 00:59:53.346658 TX Vref early break, caculate TX vref
8541 00:59:53.349274 TX Vref=16, minBit 0, minWin=22, winSum=381
8542 00:59:53.352967 TX Vref=18, minBit 0, minWin=23, winSum=390
8543 00:59:53.355860 TX Vref=20, minBit 10, minWin=23, winSum=397
8544 00:59:53.359306 TX Vref=22, minBit 5, minWin=24, winSum=405
8545 00:59:53.365954 TX Vref=24, minBit 5, minWin=24, winSum=416
8546 00:59:53.369522 TX Vref=26, minBit 5, minWin=25, winSum=426
8547 00:59:53.372506 TX Vref=28, minBit 5, minWin=25, winSum=426
8548 00:59:53.375675 TX Vref=30, minBit 0, minWin=24, winSum=416
8549 00:59:53.379064 TX Vref=32, minBit 1, minWin=24, winSum=410
8550 00:59:53.382229 TX Vref=34, minBit 1, minWin=23, winSum=399
8551 00:59:53.388929 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 26
8552 00:59:53.389016
8553 00:59:53.392011 Final TX Range 0 Vref 26
8554 00:59:53.392094
8555 00:59:53.392159 ==
8556 00:59:53.395402 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 00:59:53.398917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 00:59:53.399003 ==
8559 00:59:53.399072
8560 00:59:53.401820
8561 00:59:53.401900 TX Vref Scan disable
8562 00:59:53.408955 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8563 00:59:53.409037 == TX Byte 0 ==
8564 00:59:53.411529 u2DelayCellOfst[0]=18 cells (5 PI)
8565 00:59:53.414986 u2DelayCellOfst[1]=15 cells (4 PI)
8566 00:59:53.418525 u2DelayCellOfst[2]=0 cells (0 PI)
8567 00:59:53.421529 u2DelayCellOfst[3]=7 cells (2 PI)
8568 00:59:53.425492 u2DelayCellOfst[4]=7 cells (2 PI)
8569 00:59:53.428228 u2DelayCellOfst[5]=22 cells (6 PI)
8570 00:59:53.432712 u2DelayCellOfst[6]=18 cells (5 PI)
8571 00:59:53.435039 u2DelayCellOfst[7]=7 cells (2 PI)
8572 00:59:53.438388 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8573 00:59:53.441871 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8574 00:59:53.445116 == TX Byte 1 ==
8575 00:59:53.448242 u2DelayCellOfst[8]=0 cells (0 PI)
8576 00:59:53.451592 u2DelayCellOfst[9]=3 cells (1 PI)
8577 00:59:53.454678 u2DelayCellOfst[10]=11 cells (3 PI)
8578 00:59:53.458174 u2DelayCellOfst[11]=3 cells (1 PI)
8579 00:59:53.458256 u2DelayCellOfst[12]=15 cells (4 PI)
8580 00:59:53.461258 u2DelayCellOfst[13]=18 cells (5 PI)
8581 00:59:53.464540 u2DelayCellOfst[14]=18 cells (5 PI)
8582 00:59:53.468082 u2DelayCellOfst[15]=18 cells (5 PI)
8583 00:59:53.474349 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8584 00:59:53.477486 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8585 00:59:53.477568 DramC Write-DBI on
8586 00:59:53.481122 ==
8587 00:59:53.484322 Dram Type= 6, Freq= 0, CH_1, rank 0
8588 00:59:53.487393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8589 00:59:53.487474 ==
8590 00:59:53.487539
8591 00:59:53.487599
8592 00:59:53.490852 TX Vref Scan disable
8593 00:59:53.490933 == TX Byte 0 ==
8594 00:59:53.498017 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8595 00:59:53.498099 == TX Byte 1 ==
8596 00:59:53.500695 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8597 00:59:53.503915 DramC Write-DBI off
8598 00:59:53.503996
8599 00:59:53.504060 [DATLAT]
8600 00:59:53.507707 Freq=1600, CH1 RK0
8601 00:59:53.507803
8602 00:59:53.507867 DATLAT Default: 0xf
8603 00:59:53.510932 0, 0xFFFF, sum = 0
8604 00:59:53.511015 1, 0xFFFF, sum = 0
8605 00:59:53.513893 2, 0xFFFF, sum = 0
8606 00:59:53.513975 3, 0xFFFF, sum = 0
8607 00:59:53.517639 4, 0xFFFF, sum = 0
8608 00:59:53.520881 5, 0xFFFF, sum = 0
8609 00:59:53.520964 6, 0xFFFF, sum = 0
8610 00:59:53.523457 7, 0xFFFF, sum = 0
8611 00:59:53.523539 8, 0xFFFF, sum = 0
8612 00:59:53.527101 9, 0xFFFF, sum = 0
8613 00:59:53.527184 10, 0xFFFF, sum = 0
8614 00:59:53.530510 11, 0xFFFF, sum = 0
8615 00:59:53.530592 12, 0xFFFF, sum = 0
8616 00:59:53.533838 13, 0xFFFF, sum = 0
8617 00:59:53.533920 14, 0x0, sum = 1
8618 00:59:53.536917 15, 0x0, sum = 2
8619 00:59:53.536999 16, 0x0, sum = 3
8620 00:59:53.540204 17, 0x0, sum = 4
8621 00:59:53.540286 best_step = 15
8622 00:59:53.540350
8623 00:59:53.540409 ==
8624 00:59:53.543789 Dram Type= 6, Freq= 0, CH_1, rank 0
8625 00:59:53.550964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8626 00:59:53.551047 ==
8627 00:59:53.551111 RX Vref Scan: 1
8628 00:59:53.551170
8629 00:59:53.553560 Set Vref Range= 24 -> 127
8630 00:59:53.553641
8631 00:59:53.556493 RX Vref 24 -> 127, step: 1
8632 00:59:53.556574
8633 00:59:53.556638 RX Delay 19 -> 252, step: 4
8634 00:59:53.556699
8635 00:59:53.559792 Set Vref, RX VrefLevel [Byte0]: 24
8636 00:59:53.563231 [Byte1]: 24
8637 00:59:53.567464
8638 00:59:53.567546 Set Vref, RX VrefLevel [Byte0]: 25
8639 00:59:53.570510 [Byte1]: 25
8640 00:59:53.575348
8641 00:59:53.575429 Set Vref, RX VrefLevel [Byte0]: 26
8642 00:59:53.578140 [Byte1]: 26
8643 00:59:53.582319
8644 00:59:53.582400 Set Vref, RX VrefLevel [Byte0]: 27
8645 00:59:53.585915 [Byte1]: 27
8646 00:59:53.590744
8647 00:59:53.590825 Set Vref, RX VrefLevel [Byte0]: 28
8648 00:59:53.593754 [Byte1]: 28
8649 00:59:53.598010
8650 00:59:53.598091 Set Vref, RX VrefLevel [Byte0]: 29
8651 00:59:53.601236 [Byte1]: 29
8652 00:59:53.605232
8653 00:59:53.605314 Set Vref, RX VrefLevel [Byte0]: 30
8654 00:59:53.608693 [Byte1]: 30
8655 00:59:53.614261
8656 00:59:53.614341 Set Vref, RX VrefLevel [Byte0]: 31
8657 00:59:53.616187 [Byte1]: 31
8658 00:59:53.620819
8659 00:59:53.620900 Set Vref, RX VrefLevel [Byte0]: 32
8660 00:59:53.623666 [Byte1]: 32
8661 00:59:53.627649
8662 00:59:53.627767 Set Vref, RX VrefLevel [Byte0]: 33
8663 00:59:53.630942 [Byte1]: 33
8664 00:59:53.636119
8665 00:59:53.638590 Set Vref, RX VrefLevel [Byte0]: 34
8666 00:59:53.638672 [Byte1]: 34
8667 00:59:53.643289
8668 00:59:53.643370 Set Vref, RX VrefLevel [Byte0]: 35
8669 00:59:53.646517 [Byte1]: 35
8670 00:59:53.650748
8671 00:59:53.650829 Set Vref, RX VrefLevel [Byte0]: 36
8672 00:59:53.654176 [Byte1]: 36
8673 00:59:53.658969
8674 00:59:53.659050 Set Vref, RX VrefLevel [Byte0]: 37
8675 00:59:53.663952 [Byte1]: 37
8676 00:59:53.665937
8677 00:59:53.666038 Set Vref, RX VrefLevel [Byte0]: 38
8678 00:59:53.669480 [Byte1]: 38
8679 00:59:53.673222
8680 00:59:53.673304 Set Vref, RX VrefLevel [Byte0]: 39
8681 00:59:53.676732 [Byte1]: 39
8682 00:59:53.681042
8683 00:59:53.681122 Set Vref, RX VrefLevel [Byte0]: 40
8684 00:59:53.684227 [Byte1]: 40
8685 00:59:53.688536
8686 00:59:53.688617 Set Vref, RX VrefLevel [Byte0]: 41
8687 00:59:53.692203 [Byte1]: 41
8688 00:59:53.695987
8689 00:59:53.696068 Set Vref, RX VrefLevel [Byte0]: 42
8690 00:59:53.700271 [Byte1]: 42
8691 00:59:53.704597
8692 00:59:53.704678 Set Vref, RX VrefLevel [Byte0]: 43
8693 00:59:53.707458 [Byte1]: 43
8694 00:59:53.711090
8695 00:59:53.711171 Set Vref, RX VrefLevel [Byte0]: 44
8696 00:59:53.714421 [Byte1]: 44
8697 00:59:53.720120
8698 00:59:53.720201 Set Vref, RX VrefLevel [Byte0]: 45
8699 00:59:53.721828 [Byte1]: 45
8700 00:59:53.726685
8701 00:59:53.726766 Set Vref, RX VrefLevel [Byte0]: 46
8702 00:59:53.729607 [Byte1]: 46
8703 00:59:53.734259
8704 00:59:53.737051 Set Vref, RX VrefLevel [Byte0]: 47
8705 00:59:53.740379 [Byte1]: 47
8706 00:59:53.740460
8707 00:59:53.743311 Set Vref, RX VrefLevel [Byte0]: 48
8708 00:59:53.747024 [Byte1]: 48
8709 00:59:53.747108
8710 00:59:53.749995 Set Vref, RX VrefLevel [Byte0]: 49
8711 00:59:53.753381 [Byte1]: 49
8712 00:59:53.757264
8713 00:59:53.757344 Set Vref, RX VrefLevel [Byte0]: 50
8714 00:59:53.759837 [Byte1]: 50
8715 00:59:53.764357
8716 00:59:53.764438 Set Vref, RX VrefLevel [Byte0]: 51
8717 00:59:53.767335 [Byte1]: 51
8718 00:59:53.772848
8719 00:59:53.772931 Set Vref, RX VrefLevel [Byte0]: 52
8720 00:59:53.774946 [Byte1]: 52
8721 00:59:53.779509
8722 00:59:53.779591 Set Vref, RX VrefLevel [Byte0]: 53
8723 00:59:53.782492 [Byte1]: 53
8724 00:59:53.787158
8725 00:59:53.787240 Set Vref, RX VrefLevel [Byte0]: 54
8726 00:59:53.790009 [Byte1]: 54
8727 00:59:53.794282
8728 00:59:53.794364 Set Vref, RX VrefLevel [Byte0]: 55
8729 00:59:53.798714 [Byte1]: 55
8730 00:59:53.802324
8731 00:59:53.802406 Set Vref, RX VrefLevel [Byte0]: 56
8732 00:59:53.805925 [Byte1]: 56
8733 00:59:53.809773
8734 00:59:53.809855 Set Vref, RX VrefLevel [Byte0]: 57
8735 00:59:53.813624 [Byte1]: 57
8736 00:59:53.817374
8737 00:59:53.817455 Set Vref, RX VrefLevel [Byte0]: 58
8738 00:59:53.820833 [Byte1]: 58
8739 00:59:53.825370
8740 00:59:53.825452 Set Vref, RX VrefLevel [Byte0]: 59
8741 00:59:53.828042 [Byte1]: 59
8742 00:59:53.832466
8743 00:59:53.832547 Set Vref, RX VrefLevel [Byte0]: 60
8744 00:59:53.835653 [Byte1]: 60
8745 00:59:53.839646
8746 00:59:53.839766 Set Vref, RX VrefLevel [Byte0]: 61
8747 00:59:53.843425 [Byte1]: 61
8748 00:59:53.847474
8749 00:59:53.847555 Set Vref, RX VrefLevel [Byte0]: 62
8750 00:59:53.850753 [Byte1]: 62
8751 00:59:53.855066
8752 00:59:53.855148 Set Vref, RX VrefLevel [Byte0]: 63
8753 00:59:53.858527 [Byte1]: 63
8754 00:59:53.863034
8755 00:59:53.863116 Set Vref, RX VrefLevel [Byte0]: 64
8756 00:59:53.868830 [Byte1]: 64
8757 00:59:53.868914
8758 00:59:53.872158 Set Vref, RX VrefLevel [Byte0]: 65
8759 00:59:53.876388 [Byte1]: 65
8760 00:59:53.876470
8761 00:59:53.879047 Set Vref, RX VrefLevel [Byte0]: 66
8762 00:59:53.883328 [Byte1]: 66
8763 00:59:53.883410
8764 00:59:53.886605 Set Vref, RX VrefLevel [Byte0]: 67
8765 00:59:53.889758 [Byte1]: 67
8766 00:59:53.892941
8767 00:59:53.893022 Set Vref, RX VrefLevel [Byte0]: 68
8768 00:59:53.896225 [Byte1]: 68
8769 00:59:53.900438
8770 00:59:53.900519 Set Vref, RX VrefLevel [Byte0]: 69
8771 00:59:53.903602 [Byte1]: 69
8772 00:59:53.908114
8773 00:59:53.908196 Set Vref, RX VrefLevel [Byte0]: 70
8774 00:59:53.911674 [Byte1]: 70
8775 00:59:53.916793
8776 00:59:53.917113 Set Vref, RX VrefLevel [Byte0]: 71
8777 00:59:53.919262 [Byte1]: 71
8778 00:59:53.923162
8779 00:59:53.923402 Set Vref, RX VrefLevel [Byte0]: 72
8780 00:59:53.926728 [Byte1]: 72
8781 00:59:53.931508
8782 00:59:53.931861 Final RX Vref Byte 0 = 53 to rank0
8783 00:59:53.934698 Final RX Vref Byte 1 = 59 to rank0
8784 00:59:53.937828 Final RX Vref Byte 0 = 53 to rank1
8785 00:59:53.940899 Final RX Vref Byte 1 = 59 to rank1==
8786 00:59:53.944009 Dram Type= 6, Freq= 0, CH_1, rank 0
8787 00:59:53.950876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 00:59:53.951254 ==
8789 00:59:53.951491 DQS Delay:
8790 00:59:53.954514 DQS0 = 0, DQS1 = 0
8791 00:59:53.955008 DQM Delay:
8792 00:59:53.955322 DQM0 = 135, DQM1 = 129
8793 00:59:53.958195 DQ Delay:
8794 00:59:53.961380 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8795 00:59:53.963825 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8796 00:59:53.967300 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8797 00:59:53.970781 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8798 00:59:53.971240
8799 00:59:53.971602
8800 00:59:53.972005
8801 00:59:53.973939 [DramC_TX_OE_Calibration] TA2
8802 00:59:53.977184 Original DQ_B0 (3 6) =30, OEN = 27
8803 00:59:53.980496 Original DQ_B1 (3 6) =30, OEN = 27
8804 00:59:53.983847 24, 0x0, End_B0=24 End_B1=24
8805 00:59:53.987581 25, 0x0, End_B0=25 End_B1=25
8806 00:59:53.988196 26, 0x0, End_B0=26 End_B1=26
8807 00:59:53.991459 27, 0x0, End_B0=27 End_B1=27
8808 00:59:53.993994 28, 0x0, End_B0=28 End_B1=28
8809 00:59:53.996956 29, 0x0, End_B0=29 End_B1=29
8810 00:59:53.997526 30, 0x0, End_B0=30 End_B1=30
8811 00:59:54.001431 31, 0x4141, End_B0=30 End_B1=30
8812 00:59:54.003780 Byte0 end_step=30 best_step=27
8813 00:59:54.006970 Byte1 end_step=30 best_step=27
8814 00:59:54.011562 Byte0 TX OE(2T, 0.5T) = (3, 3)
8815 00:59:54.013905 Byte1 TX OE(2T, 0.5T) = (3, 3)
8816 00:59:54.014366
8817 00:59:54.014729
8818 00:59:54.020099 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8819 00:59:54.023200 CH1 RK0: MR19=303, MR18=1B10
8820 00:59:54.029631 CH1_RK0: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8821 00:59:54.030400
8822 00:59:54.034466 ----->DramcWriteLeveling(PI) begin...
8823 00:59:54.035221 ==
8824 00:59:54.036343 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 00:59:54.039793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 00:59:54.040262 ==
8827 00:59:54.043192 Write leveling (Byte 0): 23 => 23
8828 00:59:54.045817 Write leveling (Byte 1): 25 => 25
8829 00:59:54.049333 DramcWriteLeveling(PI) end<-----
8830 00:59:54.049474
8831 00:59:54.049544 ==
8832 00:59:54.052239 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 00:59:54.059369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 00:59:54.059517 ==
8835 00:59:54.059592 [Gating] SW mode calibration
8836 00:59:54.069457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8837 00:59:54.073053 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8838 00:59:54.079297 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 00:59:54.083083 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 00:59:54.085360 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8841 00:59:54.093056 1 4 12 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8842 00:59:54.095399 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 00:59:54.098998 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 00:59:54.105580 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 00:59:54.109258 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 00:59:54.112257 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 00:59:54.118796 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 00:59:54.121552 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8849 00:59:54.125601 1 5 12 | B1->B0 | 2626 3434 | 1 0 | (1 0) (0 1)
8850 00:59:54.132271 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 00:59:54.135647 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 00:59:54.139242 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 00:59:54.145154 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 00:59:54.149158 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 00:59:54.151824 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 00:59:54.158491 1 6 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8857 00:59:54.162214 1 6 12 | B1->B0 | 4444 2929 | 0 1 | (0 0) (0 0)
8858 00:59:54.165360 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 00:59:54.171601 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 00:59:54.175202 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 00:59:54.178486 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 00:59:54.182044 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 00:59:54.187889 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 00:59:54.191901 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8865 00:59:54.195368 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8866 00:59:54.201969 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8867 00:59:54.204962 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 00:59:54.211222 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 00:59:54.214322 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 00:59:54.218372 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 00:59:54.221073 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 00:59:54.228087 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 00:59:54.231341 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 00:59:54.234702 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 00:59:54.242295 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 00:59:54.244311 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 00:59:54.248050 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 00:59:54.254044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 00:59:54.257219 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 00:59:54.264233 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8881 00:59:54.267503 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8882 00:59:54.270092 Total UI for P1: 0, mck2ui 16
8883 00:59:54.273951 best dqsien dly found for B1: ( 1, 9, 8)
8884 00:59:54.277342 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 00:59:54.280166 Total UI for P1: 0, mck2ui 16
8886 00:59:54.283858 best dqsien dly found for B0: ( 1, 9, 12)
8887 00:59:54.286983 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8888 00:59:54.290319 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8889 00:59:54.290882
8890 00:59:54.293571 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8891 00:59:54.301001 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8892 00:59:54.301558 [Gating] SW calibration Done
8893 00:59:54.301925 ==
8894 00:59:54.304032 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 00:59:54.310522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 00:59:54.311068 ==
8897 00:59:54.311439 RX Vref Scan: 0
8898 00:59:54.311837
8899 00:59:54.313797 RX Vref 0 -> 0, step: 1
8900 00:59:54.314359
8901 00:59:54.316261 RX Delay 0 -> 252, step: 8
8902 00:59:54.319615 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8903 00:59:54.322883 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8904 00:59:54.326757 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8905 00:59:54.333700 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8906 00:59:54.336634 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8907 00:59:54.340421 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8908 00:59:54.343308 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8909 00:59:54.346531 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8910 00:59:54.352833 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8911 00:59:54.356701 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8912 00:59:54.359931 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8913 00:59:54.363734 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8914 00:59:54.367166 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8915 00:59:54.373250 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8916 00:59:54.376079 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8917 00:59:54.379952 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8918 00:59:54.380557 ==
8919 00:59:54.383785 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 00:59:54.386101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 00:59:54.389812 ==
8922 00:59:54.390423 DQS Delay:
8923 00:59:54.390806 DQS0 = 0, DQS1 = 0
8924 00:59:54.392376 DQM Delay:
8925 00:59:54.392867 DQM0 = 136, DQM1 = 129
8926 00:59:54.395924 DQ Delay:
8927 00:59:54.399050 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8928 00:59:54.402842 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8929 00:59:54.405757 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8930 00:59:54.409069 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8931 00:59:54.409532
8932 00:59:54.409913
8933 00:59:54.410365 ==
8934 00:59:54.412260 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 00:59:54.415741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 00:59:54.416210 ==
8937 00:59:54.418955
8938 00:59:54.419387
8939 00:59:54.419758 TX Vref Scan disable
8940 00:59:54.422184 == TX Byte 0 ==
8941 00:59:54.425857 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8942 00:59:54.429234 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8943 00:59:54.432227 == TX Byte 1 ==
8944 00:59:54.435833 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8945 00:59:54.438734 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8946 00:59:54.439292 ==
8947 00:59:54.442411 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 00:59:54.448459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 00:59:54.448881 ==
8950 00:59:54.460363
8951 00:59:54.463538 TX Vref early break, caculate TX vref
8952 00:59:54.467752 TX Vref=16, minBit 0, minWin=22, winSum=383
8953 00:59:54.470087 TX Vref=18, minBit 0, minWin=23, winSum=391
8954 00:59:54.475527 TX Vref=20, minBit 5, minWin=23, winSum=399
8955 00:59:54.477841 TX Vref=22, minBit 1, minWin=24, winSum=410
8956 00:59:54.480126 TX Vref=24, minBit 0, minWin=24, winSum=412
8957 00:59:54.487419 TX Vref=26, minBit 0, minWin=25, winSum=420
8958 00:59:54.490845 TX Vref=28, minBit 0, minWin=25, winSum=424
8959 00:59:54.493429 TX Vref=30, minBit 0, minWin=24, winSum=411
8960 00:59:54.497033 TX Vref=32, minBit 0, minWin=23, winSum=404
8961 00:59:54.499763 TX Vref=34, minBit 0, minWin=22, winSum=392
8962 00:59:54.506710 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8963 00:59:54.507304
8964 00:59:54.509999 Final TX Range 0 Vref 28
8965 00:59:54.510629
8966 00:59:54.510996 ==
8967 00:59:54.513201 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 00:59:54.516432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 00:59:54.517155 ==
8970 00:59:54.517544
8971 00:59:54.517890
8972 00:59:54.519881 TX Vref Scan disable
8973 00:59:54.526746 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8974 00:59:54.527304 == TX Byte 0 ==
8975 00:59:54.529260 u2DelayCellOfst[0]=18 cells (5 PI)
8976 00:59:54.533272 u2DelayCellOfst[1]=11 cells (3 PI)
8977 00:59:54.536485 u2DelayCellOfst[2]=0 cells (0 PI)
8978 00:59:54.539592 u2DelayCellOfst[3]=7 cells (2 PI)
8979 00:59:54.542496 u2DelayCellOfst[4]=3 cells (1 PI)
8980 00:59:54.546069 u2DelayCellOfst[5]=22 cells (6 PI)
8981 00:59:54.549209 u2DelayCellOfst[6]=18 cells (5 PI)
8982 00:59:54.552666 u2DelayCellOfst[7]=3 cells (1 PI)
8983 00:59:54.555723 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8984 00:59:54.559159 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8985 00:59:54.563152 == TX Byte 1 ==
8986 00:59:54.565888 u2DelayCellOfst[8]=0 cells (0 PI)
8987 00:59:54.568964 u2DelayCellOfst[9]=3 cells (1 PI)
8988 00:59:54.572713 u2DelayCellOfst[10]=15 cells (4 PI)
8989 00:59:54.573171 u2DelayCellOfst[11]=7 cells (2 PI)
8990 00:59:54.576101 u2DelayCellOfst[12]=15 cells (4 PI)
8991 00:59:54.578969 u2DelayCellOfst[13]=18 cells (5 PI)
8992 00:59:54.582743 u2DelayCellOfst[14]=18 cells (5 PI)
8993 00:59:54.585607 u2DelayCellOfst[15]=18 cells (5 PI)
8994 00:59:54.592722 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8995 00:59:54.595574 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8996 00:59:54.596113 DramC Write-DBI on
8997 00:59:54.598933 ==
8998 00:59:54.602518 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 00:59:54.605342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 00:59:54.605802 ==
9001 00:59:54.606163
9002 00:59:54.606497
9003 00:59:54.609136 TX Vref Scan disable
9004 00:59:54.609592 == TX Byte 0 ==
9005 00:59:54.615434 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9006 00:59:54.616155 == TX Byte 1 ==
9007 00:59:54.618586 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9008 00:59:54.622179 DramC Write-DBI off
9009 00:59:54.622731
9010 00:59:54.623096 [DATLAT]
9011 00:59:54.625122 Freq=1600, CH1 RK1
9012 00:59:54.625582
9013 00:59:54.625943 DATLAT Default: 0xf
9014 00:59:54.628799 0, 0xFFFF, sum = 0
9015 00:59:54.629310 1, 0xFFFF, sum = 0
9016 00:59:54.631847 2, 0xFFFF, sum = 0
9017 00:59:54.632410 3, 0xFFFF, sum = 0
9018 00:59:54.635243 4, 0xFFFF, sum = 0
9019 00:59:54.635737 5, 0xFFFF, sum = 0
9020 00:59:54.638728 6, 0xFFFF, sum = 0
9021 00:59:54.639189 7, 0xFFFF, sum = 0
9022 00:59:54.642056 8, 0xFFFF, sum = 0
9023 00:59:54.645085 9, 0xFFFF, sum = 0
9024 00:59:54.645549 10, 0xFFFF, sum = 0
9025 00:59:54.648767 11, 0xFFFF, sum = 0
9026 00:59:54.649337 12, 0xFFFF, sum = 0
9027 00:59:54.651820 13, 0xFFFF, sum = 0
9028 00:59:54.652565 14, 0x0, sum = 1
9029 00:59:54.655394 15, 0x0, sum = 2
9030 00:59:54.656126 16, 0x0, sum = 3
9031 00:59:54.658340 17, 0x0, sum = 4
9032 00:59:54.658917 best_step = 15
9033 00:59:54.659285
9034 00:59:54.659619 ==
9035 00:59:54.661163 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 00:59:54.664868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 00:59:54.668386 ==
9038 00:59:54.668880 RX Vref Scan: 0
9039 00:59:54.669263
9040 00:59:54.671029 RX Vref 0 -> 0, step: 1
9041 00:59:54.671484
9042 00:59:54.674429 RX Delay 11 -> 252, step: 4
9043 00:59:54.677747 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9044 00:59:54.680948 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9045 00:59:54.684827 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9046 00:59:54.691761 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9047 00:59:54.694618 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9048 00:59:54.697796 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9049 00:59:54.700713 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9050 00:59:54.704491 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9051 00:59:54.710952 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9052 00:59:54.713798 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9053 00:59:54.717925 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9054 00:59:54.720705 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9055 00:59:54.723998 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9056 00:59:54.731051 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9057 00:59:54.734798 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9058 00:59:54.736979 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9059 00:59:54.737443 ==
9060 00:59:54.740600 Dram Type= 6, Freq= 0, CH_1, rank 1
9061 00:59:54.743993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9062 00:59:54.747938 ==
9063 00:59:54.748493 DQS Delay:
9064 00:59:54.748857 DQS0 = 0, DQS1 = 0
9065 00:59:54.750869 DQM Delay:
9066 00:59:54.751424 DQM0 = 134, DQM1 = 126
9067 00:59:54.753544 DQ Delay:
9068 00:59:54.756715 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9069 00:59:54.760244 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9070 00:59:54.763827 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =116
9071 00:59:54.766918 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9072 00:59:54.767648
9073 00:59:54.768137
9074 00:59:54.768478
9075 00:59:54.770258 [DramC_TX_OE_Calibration] TA2
9076 00:59:54.773710 Original DQ_B0 (3 6) =30, OEN = 27
9077 00:59:54.776641 Original DQ_B1 (3 6) =30, OEN = 27
9078 00:59:54.779869 24, 0x0, End_B0=24 End_B1=24
9079 00:59:54.780347 25, 0x0, End_B0=25 End_B1=25
9080 00:59:54.783535 26, 0x0, End_B0=26 End_B1=26
9081 00:59:54.786635 27, 0x0, End_B0=27 End_B1=27
9082 00:59:54.790153 28, 0x0, End_B0=28 End_B1=28
9083 00:59:54.793286 29, 0x0, End_B0=29 End_B1=29
9084 00:59:54.793861 30, 0x0, End_B0=30 End_B1=30
9085 00:59:54.796304 31, 0x5151, End_B0=30 End_B1=30
9086 00:59:54.799797 Byte0 end_step=30 best_step=27
9087 00:59:54.803390 Byte1 end_step=30 best_step=27
9088 00:59:54.806771 Byte0 TX OE(2T, 0.5T) = (3, 3)
9089 00:59:54.810217 Byte1 TX OE(2T, 0.5T) = (3, 3)
9090 00:59:54.810776
9091 00:59:54.811240
9092 00:59:54.816604 [DQSOSCAuto] RK1, (LSB)MR18= 0xd08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9093 00:59:54.820361 CH1 RK1: MR19=303, MR18=D08
9094 00:59:54.826393 CH1_RK1: MR19=0x303, MR18=0xD08, DQSOSC=403, MR23=63, INC=22, DEC=15
9095 00:59:54.829692 [RxdqsGatingPostProcess] freq 1600
9096 00:59:54.832510 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9097 00:59:54.836805 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 00:59:54.839433 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 00:59:54.843399 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 00:59:54.845965 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 00:59:54.849367 best DQS0 dly(2T, 0.5T) = (1, 1)
9102 00:59:54.852823 best DQS1 dly(2T, 0.5T) = (1, 1)
9103 00:59:54.855760 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9104 00:59:54.859739 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9105 00:59:54.862954 Pre-setting of DQS Precalculation
9106 00:59:54.866187 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9107 00:59:54.872626 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9108 00:59:54.882347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 00:59:54.882908
9110 00:59:54.883270
9111 00:59:54.886474 [Calibration Summary] 3200 Mbps
9112 00:59:54.887029 CH 0, Rank 0
9113 00:59:54.888882 SW Impedance : PASS
9114 00:59:54.889339 DUTY Scan : NO K
9115 00:59:54.892417 ZQ Calibration : PASS
9116 00:59:54.892875 Jitter Meter : NO K
9117 00:59:54.895570 CBT Training : PASS
9118 00:59:54.899136 Write leveling : PASS
9119 00:59:54.899597 RX DQS gating : PASS
9120 00:59:54.902271 RX DQ/DQS(RDDQC) : PASS
9121 00:59:54.905531 TX DQ/DQS : PASS
9122 00:59:54.906003 RX DATLAT : PASS
9123 00:59:54.908845 RX DQ/DQS(Engine): PASS
9124 00:59:54.911934 TX OE : PASS
9125 00:59:54.912392 All Pass.
9126 00:59:54.912752
9127 00:59:54.913087 CH 0, Rank 1
9128 00:59:54.915855 SW Impedance : PASS
9129 00:59:54.919328 DUTY Scan : NO K
9130 00:59:54.919941 ZQ Calibration : PASS
9131 00:59:54.921826 Jitter Meter : NO K
9132 00:59:54.926118 CBT Training : PASS
9133 00:59:54.926585 Write leveling : PASS
9134 00:59:54.930099 RX DQS gating : PASS
9135 00:59:54.931931 RX DQ/DQS(RDDQC) : PASS
9136 00:59:54.932490 TX DQ/DQS : PASS
9137 00:59:54.935308 RX DATLAT : PASS
9138 00:59:54.938611 RX DQ/DQS(Engine): PASS
9139 00:59:54.939177 TX OE : PASS
9140 00:59:54.941998 All Pass.
9141 00:59:54.942564
9142 00:59:54.942991 CH 1, Rank 0
9143 00:59:54.944934 SW Impedance : PASS
9144 00:59:54.945478 DUTY Scan : NO K
9145 00:59:54.948313 ZQ Calibration : PASS
9146 00:59:54.951800 Jitter Meter : NO K
9147 00:59:54.952266 CBT Training : PASS
9148 00:59:54.955385 Write leveling : PASS
9149 00:59:54.958943 RX DQS gating : PASS
9150 00:59:54.959414 RX DQ/DQS(RDDQC) : PASS
9151 00:59:54.961601 TX DQ/DQS : PASS
9152 00:59:54.964953 RX DATLAT : PASS
9153 00:59:54.965516 RX DQ/DQS(Engine): PASS
9154 00:59:54.968311 TX OE : PASS
9155 00:59:54.969110 All Pass.
9156 00:59:54.969499
9157 00:59:54.971429 CH 1, Rank 1
9158 00:59:54.971950 SW Impedance : PASS
9159 00:59:54.975049 DUTY Scan : NO K
9160 00:59:54.975513 ZQ Calibration : PASS
9161 00:59:54.977787 Jitter Meter : NO K
9162 00:59:54.980858 CBT Training : PASS
9163 00:59:54.981347 Write leveling : PASS
9164 00:59:54.984979 RX DQS gating : PASS
9165 00:59:54.987732 RX DQ/DQS(RDDQC) : PASS
9166 00:59:54.988207 TX DQ/DQS : PASS
9167 00:59:54.991558 RX DATLAT : PASS
9168 00:59:54.994207 RX DQ/DQS(Engine): PASS
9169 00:59:54.994678 TX OE : PASS
9170 00:59:54.998337 All Pass.
9171 00:59:54.998897
9172 00:59:54.999265 DramC Write-DBI on
9173 00:59:55.001167 PER_BANK_REFRESH: Hybrid Mode
9174 00:59:55.005059 TX_TRACKING: ON
9175 00:59:55.010687 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9176 00:59:55.020766 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9177 00:59:55.027394 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9178 00:59:55.030230 [FAST_K] Save calibration result to emmc
9179 00:59:55.034126 sync common calibartion params.
9180 00:59:55.034819 sync cbt_mode0:1, 1:1
9181 00:59:55.036974 dram_init: ddr_geometry: 2
9182 00:59:55.040912 dram_init: ddr_geometry: 2
9183 00:59:55.044219 dram_init: ddr_geometry: 2
9184 00:59:55.044790 0:dram_rank_size:100000000
9185 00:59:55.047882 1:dram_rank_size:100000000
9186 00:59:55.053428 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9187 00:59:55.053997 DFS_SHUFFLE_HW_MODE: ON
9188 00:59:55.060166 dramc_set_vcore_voltage set vcore to 725000
9189 00:59:55.060885 Read voltage for 1600, 0
9190 00:59:55.063371 Vio18 = 0
9191 00:59:55.063999 Vcore = 725000
9192 00:59:55.064421 Vdram = 0
9193 00:59:55.066942 Vddq = 0
9194 00:59:55.067511 Vmddr = 0
9195 00:59:55.069874 switch to 3200 Mbps bootup
9196 00:59:55.070340 [DramcRunTimeConfig]
9197 00:59:55.070707 PHYPLL
9198 00:59:55.072916 DPM_CONTROL_AFTERK: ON
9199 00:59:55.076663 PER_BANK_REFRESH: ON
9200 00:59:55.077192 REFRESH_OVERHEAD_REDUCTION: ON
9201 00:59:55.079791 CMD_PICG_NEW_MODE: OFF
9202 00:59:55.083514 XRTWTW_NEW_MODE: ON
9203 00:59:55.084142 XRTRTR_NEW_MODE: ON
9204 00:59:55.086599 TX_TRACKING: ON
9205 00:59:55.087061 RDSEL_TRACKING: OFF
9206 00:59:55.089452 DQS Precalculation for DVFS: ON
9207 00:59:55.093382 RX_TRACKING: OFF
9208 00:59:55.093948 HW_GATING DBG: ON
9209 00:59:55.096810 ZQCS_ENABLE_LP4: ON
9210 00:59:55.097273 RX_PICG_NEW_MODE: ON
9211 00:59:55.099891 TX_PICG_NEW_MODE: ON
9212 00:59:55.100457 ENABLE_RX_DCM_DPHY: ON
9213 00:59:55.102690 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9214 00:59:55.105962 DUMMY_READ_FOR_TRACKING: OFF
9215 00:59:55.109711 !!! SPM_CONTROL_AFTERK: OFF
9216 00:59:55.113055 !!! SPM could not control APHY
9217 00:59:55.113617 IMPEDANCE_TRACKING: ON
9218 00:59:55.116163 TEMP_SENSOR: ON
9219 00:59:55.116722 HW_SAVE_FOR_SR: OFF
9220 00:59:55.119150 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9221 00:59:55.123240 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9222 00:59:55.126245 Read ODT Tracking: ON
9223 00:59:55.129313 Refresh Rate DeBounce: ON
9224 00:59:55.129869 DFS_NO_QUEUE_FLUSH: ON
9225 00:59:55.132341 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9226 00:59:55.135830 ENABLE_DFS_RUNTIME_MRW: OFF
9227 00:59:55.139412 DDR_RESERVE_NEW_MODE: ON
9228 00:59:55.140011 MR_CBT_SWITCH_FREQ: ON
9229 00:59:55.141681 =========================
9230 00:59:55.161309 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9231 00:59:55.164608 dram_init: ddr_geometry: 2
9232 00:59:55.182539 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9233 00:59:55.185817 dram_init: dram init end (result: 0)
9234 00:59:55.193293 DRAM-K: Full calibration passed in 24623 msecs
9235 00:59:55.195867 MRC: failed to locate region type 0.
9236 00:59:55.196563 DRAM rank0 size:0x100000000,
9237 00:59:55.199161 DRAM rank1 size=0x100000000
9238 00:59:55.208834 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9239 00:59:55.215379 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9240 00:59:55.222151 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9241 00:59:55.232155 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9242 00:59:55.232718 DRAM rank0 size:0x100000000,
9243 00:59:55.236346 DRAM rank1 size=0x100000000
9244 00:59:55.236907 CBMEM:
9245 00:59:55.238987 IMD: root @ 0xfffff000 254 entries.
9246 00:59:55.242711 IMD: root @ 0xffffec00 62 entries.
9247 00:59:55.245452 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9248 00:59:55.252226 WARNING: RO_VPD is uninitialized or empty.
9249 00:59:55.255175 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9250 00:59:55.263971 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9251 00:59:55.276425 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9252 00:59:55.286756 BS: romstage times (exec / console): total (unknown) / 24115 ms
9253 00:59:55.287315
9254 00:59:55.287713
9255 00:59:55.296389 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9256 00:59:55.300220 ARM64: Exception handlers installed.
9257 00:59:55.303518 ARM64: Testing exception
9258 00:59:55.306576 ARM64: Done test exception
9259 00:59:55.307034 Enumerating buses...
9260 00:59:55.309922 Show all devs... Before device enumeration.
9261 00:59:55.313981 Root Device: enabled 1
9262 00:59:55.316620 CPU_CLUSTER: 0: enabled 1
9263 00:59:55.317175 CPU: 00: enabled 1
9264 00:59:55.320242 Compare with tree...
9265 00:59:55.320803 Root Device: enabled 1
9266 00:59:55.323156 CPU_CLUSTER: 0: enabled 1
9267 00:59:55.326626 CPU: 00: enabled 1
9268 00:59:55.327084 Root Device scanning...
9269 00:59:55.330102 scan_static_bus for Root Device
9270 00:59:55.333676 CPU_CLUSTER: 0 enabled
9271 00:59:55.336547 scan_static_bus for Root Device done
9272 00:59:55.339667 scan_bus: bus Root Device finished in 8 msecs
9273 00:59:55.340255 done
9274 00:59:55.346517 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9275 00:59:55.349399 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9276 00:59:55.356235 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9277 00:59:55.362711 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9278 00:59:55.363273 Allocating resources...
9279 00:59:55.366006 Reading resources...
9280 00:59:55.369028 Root Device read_resources bus 0 link: 0
9281 00:59:55.372291 DRAM rank0 size:0x100000000,
9282 00:59:55.372751 DRAM rank1 size=0x100000000
9283 00:59:55.379304 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9284 00:59:55.379902 CPU: 00 missing read_resources
9285 00:59:55.386287 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9286 00:59:55.389277 Root Device read_resources bus 0 link: 0 done
9287 00:59:55.392977 Done reading resources.
9288 00:59:55.395551 Show resources in subtree (Root Device)...After reading.
9289 00:59:55.398881 Root Device child on link 0 CPU_CLUSTER: 0
9290 00:59:55.402330 CPU_CLUSTER: 0 child on link 0 CPU: 00
9291 00:59:55.411910 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9292 00:59:55.412552 CPU: 00
9293 00:59:55.418611 Root Device assign_resources, bus 0 link: 0
9294 00:59:55.421738 CPU_CLUSTER: 0 missing set_resources
9295 00:59:55.424824 Root Device assign_resources, bus 0 link: 0 done
9296 00:59:55.425284 Done setting resources.
9297 00:59:55.432199 Show resources in subtree (Root Device)...After assigning values.
9298 00:59:55.435928 Root Device child on link 0 CPU_CLUSTER: 0
9299 00:59:55.442563 CPU_CLUSTER: 0 child on link 0 CPU: 00
9300 00:59:55.448800 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9301 00:59:55.449353 CPU: 00
9302 00:59:55.451856 Done allocating resources.
9303 00:59:55.457980 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9304 00:59:55.458518 Enabling resources...
9305 00:59:55.461245 done.
9306 00:59:55.465030 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9307 00:59:55.468461 Initializing devices...
9308 00:59:55.469126 Root Device init
9309 00:59:55.471397 init hardware done!
9310 00:59:55.471991 0x00000018: ctrlr->caps
9311 00:59:55.474916 52.000 MHz: ctrlr->f_max
9312 00:59:55.477746 0.400 MHz: ctrlr->f_min
9313 00:59:55.478214 0x40ff8080: ctrlr->voltages
9314 00:59:55.481446 sclk: 390625
9315 00:59:55.481902 Bus Width = 1
9316 00:59:55.485039 sclk: 390625
9317 00:59:55.485596 Bus Width = 1
9318 00:59:55.487744 Early init status = 3
9319 00:59:55.491789 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9320 00:59:55.495524 in-header: 03 fc 00 00 01 00 00 00
9321 00:59:55.498228 in-data: 00
9322 00:59:55.501420 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9323 00:59:55.507162 in-header: 03 fd 00 00 00 00 00 00
9324 00:59:55.510035 in-data:
9325 00:59:55.513224 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9326 00:59:55.517852 in-header: 03 fc 00 00 01 00 00 00
9327 00:59:55.521745 in-data: 00
9328 00:59:55.524341 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9329 00:59:55.529113 in-header: 03 fd 00 00 00 00 00 00
9330 00:59:55.532152 in-data:
9331 00:59:55.535595 [SSUSB] Setting up USB HOST controller...
9332 00:59:55.539098 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9333 00:59:55.542216 [SSUSB] phy power-on done.
9334 00:59:55.545363 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9335 00:59:55.552741 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9336 00:59:55.555790 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9337 00:59:55.562246 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9338 00:59:55.568716 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9339 00:59:55.575174 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9340 00:59:55.581473 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9341 00:59:55.588440 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9342 00:59:55.592068 SPM: binary array size = 0x9dc
9343 00:59:55.594752 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9344 00:59:55.601748 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9345 00:59:55.608132 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9346 00:59:55.614682 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9347 00:59:55.618241 configure_display: Starting display init
9348 00:59:55.652390 anx7625_power_on_init: Init interface.
9349 00:59:55.656112 anx7625_disable_pd_protocol: Disabled PD feature.
9350 00:59:55.658938 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9351 00:59:55.686719 anx7625_start_dp_work: Secure OCM version=00
9352 00:59:55.690458 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9353 00:59:55.704522 sp_tx_get_edid_block: EDID Block = 1
9354 00:59:55.807738 Extracted contents:
9355 00:59:55.810892 header: 00 ff ff ff ff ff ff 00
9356 00:59:55.813777 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9357 00:59:55.817393 version: 01 04
9358 00:59:55.820808 basic params: 95 1f 11 78 0a
9359 00:59:55.823970 chroma info: 76 90 94 55 54 90 27 21 50 54
9360 00:59:55.827038 established: 00 00 00
9361 00:59:55.833596 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9362 00:59:55.840357 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9363 00:59:55.843999 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 00:59:55.850057 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9365 00:59:55.857278 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9366 00:59:55.859829 extensions: 00
9367 00:59:55.860287 checksum: fb
9368 00:59:55.860668
9369 00:59:55.863919 Manufacturer: IVO Model 57d Serial Number 0
9370 00:59:55.867515 Made week 0 of 2020
9371 00:59:55.869747 EDID version: 1.4
9372 00:59:55.870302 Digital display
9373 00:59:55.873630 6 bits per primary color channel
9374 00:59:55.874096 DisplayPort interface
9375 00:59:55.876784 Maximum image size: 31 cm x 17 cm
9376 00:59:55.879804 Gamma: 220%
9377 00:59:55.880280 Check DPMS levels
9378 00:59:55.887064 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9379 00:59:55.889646 First detailed timing is preferred timing
9380 00:59:55.890112 Established timings supported:
9381 00:59:55.893099 Standard timings supported:
9382 00:59:55.896894 Detailed timings
9383 00:59:55.900279 Hex of detail: 383680a07038204018303c0035ae10000019
9384 00:59:55.906332 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9385 00:59:55.909405 0780 0798 07c8 0820 hborder 0
9386 00:59:55.912801 0438 043b 0447 0458 vborder 0
9387 00:59:55.916360 -hsync -vsync
9388 00:59:55.916922 Did detailed timing
9389 00:59:55.922585 Hex of detail: 000000000000000000000000000000000000
9390 00:59:55.925800 Manufacturer-specified data, tag 0
9391 00:59:55.929671 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9392 00:59:55.932536 ASCII string: InfoVision
9393 00:59:55.936352 Hex of detail: 000000fe00523134304e574635205248200a
9394 00:59:55.939538 ASCII string: R140NWF5 RH
9395 00:59:55.940130 Checksum
9396 00:59:55.942704 Checksum: 0xfb (valid)
9397 00:59:55.946267 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9398 00:59:55.948818 DSI data_rate: 832800000 bps
9399 00:59:55.956309 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9400 00:59:55.959159 anx7625_parse_edid: pixelclock(138800).
9401 00:59:55.963215 hactive(1920), hsync(48), hfp(24), hbp(88)
9402 00:59:55.965910 vactive(1080), vsync(12), vfp(3), vbp(17)
9403 00:59:55.968777 anx7625_dsi_config: config dsi.
9404 00:59:55.975152 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9405 00:59:55.989849 anx7625_dsi_config: success to config DSI
9406 00:59:55.992303 anx7625_dp_start: MIPI phy setup OK.
9407 00:59:55.996155 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9408 00:59:55.999606 mtk_ddp_mode_set invalid vrefresh 60
9409 00:59:56.002613 main_disp_path_setup
9410 00:59:56.003169 ovl_layer_smi_id_en
9411 00:59:56.006364 ovl_layer_smi_id_en
9412 00:59:56.006919 ccorr_config
9413 00:59:56.007279 aal_config
9414 00:59:56.008712 gamma_config
9415 00:59:56.009165 postmask_config
9416 00:59:56.012305 dither_config
9417 00:59:56.016442 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9418 00:59:56.022385 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9419 00:59:56.025498 Root Device init finished in 553 msecs
9420 00:59:56.029139 CPU_CLUSTER: 0 init
9421 00:59:56.035367 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9422 00:59:56.043228 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9423 00:59:56.043818 APU_MBOX 0x190000b0 = 0x10001
9424 00:59:56.045056 APU_MBOX 0x190001b0 = 0x10001
9425 00:59:56.048810 APU_MBOX 0x190005b0 = 0x10001
9426 00:59:56.051968 APU_MBOX 0x190006b0 = 0x10001
9427 00:59:56.058694 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9428 00:59:56.068386 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9429 00:59:56.081035 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9430 00:59:56.087125 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9431 00:59:56.099111 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9432 00:59:56.108317 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9433 00:59:56.111527 CPU_CLUSTER: 0 init finished in 81 msecs
9434 00:59:56.115412 Devices initialized
9435 00:59:56.117813 Show all devs... After init.
9436 00:59:56.118273 Root Device: enabled 1
9437 00:59:56.120882 CPU_CLUSTER: 0: enabled 1
9438 00:59:56.124360 CPU: 00: enabled 1
9439 00:59:56.128360 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9440 00:59:56.130994 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9441 00:59:56.134569 ELOG: NV offset 0x57f000 size 0x1000
9442 00:59:56.140979 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9443 00:59:56.147982 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9444 00:59:56.150872 ELOG: Event(17) added with size 13 at 2024-01-19 00:59:56 UTC
9445 00:59:56.157924 out: cmd=0x121: 03 db 21 01 00 00 00 00
9446 00:59:56.161030 in-header: 03 c9 00 00 2c 00 00 00
9447 00:59:56.173655 in-data: 96 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9448 00:59:56.177232 ELOG: Event(A1) added with size 10 at 2024-01-19 00:59:56 UTC
9449 00:59:56.184994 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9450 00:59:56.190942 ELOG: Event(A0) added with size 9 at 2024-01-19 00:59:56 UTC
9451 00:59:56.194026 elog_add_boot_reason: Logged dev mode boot
9452 00:59:56.200853 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9453 00:59:56.201409 Finalize devices...
9454 00:59:56.203421 Devices finalized
9455 00:59:56.207603 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9456 00:59:56.210429 Writing coreboot table at 0xffe64000
9457 00:59:56.216915 0. 000000000010a000-0000000000113fff: RAMSTAGE
9458 00:59:56.220113 1. 0000000040000000-00000000400fffff: RAM
9459 00:59:56.223966 2. 0000000040100000-000000004032afff: RAMSTAGE
9460 00:59:56.226609 3. 000000004032b000-00000000545fffff: RAM
9461 00:59:56.230297 4. 0000000054600000-000000005465ffff: BL31
9462 00:59:56.237095 5. 0000000054660000-00000000ffe63fff: RAM
9463 00:59:56.240305 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9464 00:59:56.243744 7. 0000000100000000-000000023fffffff: RAM
9465 00:59:56.246683 Passing 5 GPIOs to payload:
9466 00:59:56.250416 NAME | PORT | POLARITY | VALUE
9467 00:59:56.256063 EC in RW | 0x000000aa | low | undefined
9468 00:59:56.260188 EC interrupt | 0x00000005 | low | undefined
9469 00:59:56.266229 TPM interrupt | 0x000000ab | high | undefined
9470 00:59:56.269289 SD card detect | 0x00000011 | high | undefined
9471 00:59:56.275900 speaker enable | 0x00000093 | high | undefined
9472 00:59:56.279385 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9473 00:59:56.283063 in-header: 03 f9 00 00 02 00 00 00
9474 00:59:56.283620 in-data: 02 00
9475 00:59:56.285905 ADC[4]: Raw value=903031 ID=7
9476 00:59:56.289277 ADC[3]: Raw value=213652 ID=1
9477 00:59:56.289833 RAM Code: 0x71
9478 00:59:56.292370 ADC[6]: Raw value=75036 ID=0
9479 00:59:56.295858 ADC[5]: Raw value=214021 ID=1
9480 00:59:56.296617 SKU Code: 0x1
9481 00:59:56.302680 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 41a5
9482 00:59:56.306081 coreboot table: 964 bytes.
9483 00:59:56.308708 IMD ROOT 0. 0xfffff000 0x00001000
9484 00:59:56.312632 IMD SMALL 1. 0xffffe000 0x00001000
9485 00:59:56.315902 RO MCACHE 2. 0xffffc000 0x00001104
9486 00:59:56.319170 CONSOLE 3. 0xfff7c000 0x00080000
9487 00:59:56.321900 FMAP 4. 0xfff7b000 0x00000452
9488 00:59:56.325404 TIME STAMP 5. 0xfff7a000 0x00000910
9489 00:59:56.328550 VBOOT WORK 6. 0xfff66000 0x00014000
9490 00:59:56.332125 RAMOOPS 7. 0xffe66000 0x00100000
9491 00:59:56.335651 COREBOOT 8. 0xffe64000 0x00002000
9492 00:59:56.336265 IMD small region:
9493 00:59:56.338898 IMD ROOT 0. 0xffffec00 0x00000400
9494 00:59:56.341955 VPD 1. 0xffffeb80 0x0000006c
9495 00:59:56.345061 MMC STATUS 2. 0xffffeb60 0x00000004
9496 00:59:56.352637 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9497 00:59:56.353195 Probing TPM: done!
9498 00:59:56.358385 Connected to device vid:did:rid of 1ae0:0028:00
9499 00:59:56.368943 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9500 00:59:56.372235 Initialized TPM device CR50 revision 0
9501 00:59:56.372696 Checking cr50 for pending updates
9502 00:59:56.378963 Reading cr50 TPM mode
9503 00:59:56.387265 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9504 00:59:56.393653 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9505 00:59:56.435152 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9506 00:59:56.437881 Checking segment from ROM address 0x40100000
9507 00:59:56.441591 Checking segment from ROM address 0x4010001c
9508 00:59:56.447227 Loading segment from ROM address 0x40100000
9509 00:59:56.447838 code (compression=0)
9510 00:59:56.457370 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9511 00:59:56.463959 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9512 00:59:56.464424 it's not compressed!
9513 00:59:56.470218 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9514 00:59:56.476488 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9515 00:59:56.494671 Loading segment from ROM address 0x4010001c
9516 00:59:56.495230 Entry Point 0x80000000
9517 00:59:56.498036 Loaded segments
9518 00:59:56.501432 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9519 00:59:56.507964 Jumping to boot code at 0x80000000(0xffe64000)
9520 00:59:56.514883 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9521 00:59:56.520751 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9522 00:59:56.528663 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9523 00:59:56.531643 Checking segment from ROM address 0x40100000
9524 00:59:56.535230 Checking segment from ROM address 0x4010001c
9525 00:59:56.542022 Loading segment from ROM address 0x40100000
9526 00:59:56.542583 code (compression=1)
9527 00:59:56.548182 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9528 00:59:56.558227 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9529 00:59:56.558781 using LZMA
9530 00:59:56.566972 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9531 00:59:56.573760 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9532 00:59:56.576965 Loading segment from ROM address 0x4010001c
9533 00:59:56.577429 Entry Point 0x54601000
9534 00:59:56.580438 Loaded segments
9535 00:59:56.583613 NOTICE: MT8192 bl31_setup
9536 00:59:56.590982 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9537 00:59:56.594061 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9538 00:59:56.597158 WARNING: region 0:
9539 00:59:56.602098 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 00:59:56.602657 WARNING: region 1:
9541 00:59:56.607565 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9542 00:59:56.610675 WARNING: region 2:
9543 00:59:56.613853 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9544 00:59:56.616877 WARNING: region 3:
9545 00:59:56.620331 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 00:59:56.624047 WARNING: region 4:
9547 00:59:56.630987 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9548 00:59:56.631451 WARNING: region 5:
9549 00:59:56.634305 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 00:59:56.636513 WARNING: region 6:
9551 00:59:56.640149 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 00:59:56.643401 WARNING: region 7:
9553 00:59:56.648103 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9554 00:59:56.653515 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9555 00:59:56.656410 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9556 00:59:56.663451 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9557 00:59:56.667015 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9558 00:59:56.670044 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9559 00:59:56.676770 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9560 00:59:56.679859 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9561 00:59:56.683181 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9562 00:59:56.690423 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9563 00:59:56.692672 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9564 00:59:56.699816 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9565 00:59:56.702845 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9566 00:59:56.706196 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9567 00:59:56.712884 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9568 00:59:56.716258 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9569 00:59:56.719089 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9570 00:59:56.726048 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9571 00:59:56.729440 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9572 00:59:56.736072 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9573 00:59:56.739711 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9574 00:59:56.742749 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9575 00:59:56.749473 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9576 00:59:56.752550 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9577 00:59:56.759106 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9578 00:59:56.762452 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9579 00:59:56.766330 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9580 00:59:56.772642 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9581 00:59:56.776165 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9582 00:59:56.782334 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9583 00:59:56.785890 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9584 00:59:56.792027 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9585 00:59:56.795390 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9586 00:59:56.799043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9587 00:59:56.802093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9588 00:59:56.808554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9589 00:59:56.811826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9590 00:59:56.815293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9591 00:59:56.819066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9592 00:59:56.825098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9593 00:59:56.828297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9594 00:59:56.831637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9595 00:59:56.835088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9596 00:59:56.841762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9597 00:59:56.844933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9598 00:59:56.848891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9599 00:59:56.854631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9600 00:59:56.858268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9601 00:59:56.861140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9602 00:59:56.867993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9603 00:59:56.871440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9604 00:59:56.874921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9605 00:59:56.881739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9606 00:59:56.884421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9607 00:59:56.891278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9608 00:59:56.895056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9609 00:59:56.900901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9610 00:59:56.904889 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9611 00:59:56.908055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9612 00:59:56.914383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9613 00:59:56.917338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9614 00:59:56.923987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9615 00:59:56.927257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9616 00:59:56.934075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9617 00:59:56.937344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9618 00:59:56.944402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9619 00:59:56.946882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9620 00:59:56.954156 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9621 00:59:56.957225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9622 00:59:56.960567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9623 00:59:56.967576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9624 00:59:56.970347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9625 00:59:56.977251 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9626 00:59:56.980063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9627 00:59:56.986888 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9628 00:59:56.990122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9629 00:59:56.997004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9630 00:59:57.000149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9631 00:59:57.003643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9632 00:59:57.010071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9633 00:59:57.013453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9634 00:59:57.021232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9635 00:59:57.024424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9636 00:59:57.029483 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9637 00:59:57.033078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9638 00:59:57.039974 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9639 00:59:57.043556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9640 00:59:57.046528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9641 00:59:57.053276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9642 00:59:57.056266 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9643 00:59:57.062822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9644 00:59:57.066244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9645 00:59:57.072645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9646 00:59:57.076017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9647 00:59:57.084159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9648 00:59:57.085920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9649 00:59:57.089419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9650 00:59:57.096571 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9651 00:59:57.099167 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9652 00:59:57.102219 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9653 00:59:57.105433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9654 00:59:57.113261 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9655 00:59:57.115587 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9656 00:59:57.122506 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9657 00:59:57.125584 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9658 00:59:57.128741 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9659 00:59:57.135427 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9660 00:59:57.138620 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9661 00:59:57.145436 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9662 00:59:57.149069 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9663 00:59:57.155739 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9664 00:59:57.158468 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9665 00:59:57.161683 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9666 00:59:57.169148 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9667 00:59:57.171780 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9668 00:59:57.178343 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9669 00:59:57.181644 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9670 00:59:57.185076 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9671 00:59:57.188000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9672 00:59:57.195370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9673 00:59:57.198458 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9674 00:59:57.201612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9675 00:59:57.205148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9676 00:59:57.211644 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9677 00:59:57.214736 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9678 00:59:57.218445 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9679 00:59:57.224885 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9680 00:59:57.228664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9681 00:59:57.233913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9682 00:59:57.237914 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9683 00:59:57.244140 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9684 00:59:57.247492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9685 00:59:57.251081 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9686 00:59:57.257563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9687 00:59:57.260841 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9688 00:59:57.267666 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9689 00:59:57.270653 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9690 00:59:57.273713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9691 00:59:57.281197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9692 00:59:57.283917 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9693 00:59:57.287535 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9694 00:59:57.294416 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9695 00:59:57.297330 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9696 00:59:57.304009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9697 00:59:57.307261 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9698 00:59:57.310388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9699 00:59:57.316665 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9700 00:59:57.320286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9701 00:59:57.327077 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9702 00:59:57.329780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9703 00:59:57.336860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9704 00:59:57.339611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9705 00:59:57.342932 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9706 00:59:57.349860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9707 00:59:57.352735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9708 00:59:57.360055 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9709 00:59:57.362713 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9710 00:59:57.366324 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9711 00:59:57.373151 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9712 00:59:57.376262 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9713 00:59:57.379441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9714 00:59:57.386539 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9715 00:59:57.390431 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9716 00:59:57.396568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9717 00:59:57.399914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9718 00:59:57.406076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9719 00:59:57.408896 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9720 00:59:57.412546 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9721 00:59:57.418948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9722 00:59:57.422819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9723 00:59:57.429303 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9724 00:59:57.431894 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9725 00:59:57.435288 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9726 00:59:57.442310 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9727 00:59:57.445576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9728 00:59:57.452314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9729 00:59:57.455341 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9730 00:59:57.458387 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9731 00:59:57.465491 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9732 00:59:57.468356 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9733 00:59:57.474785 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9734 00:59:57.478059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9735 00:59:57.481157 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9736 00:59:57.488949 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9737 00:59:57.491737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9738 00:59:57.498225 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9739 00:59:57.501779 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9740 00:59:57.504597 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9741 00:59:57.511031 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9742 00:59:57.514496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9743 00:59:57.521680 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9744 00:59:57.524267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9745 00:59:57.531191 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9746 00:59:57.534698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9747 00:59:57.538206 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9748 00:59:57.544285 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9749 00:59:57.547770 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9750 00:59:57.554525 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9751 00:59:57.557375 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9752 00:59:57.564285 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9753 00:59:57.567585 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9754 00:59:57.570718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9755 00:59:57.577807 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9756 00:59:57.580476 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9757 00:59:57.586625 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9758 00:59:57.590353 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9759 00:59:57.594551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9760 00:59:57.600515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9761 00:59:57.603751 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9762 00:59:57.610266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9763 00:59:57.613645 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9764 00:59:57.620402 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9765 00:59:57.623300 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9766 00:59:57.627024 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9767 00:59:57.633550 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9768 00:59:57.636806 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9769 00:59:57.642818 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9770 00:59:57.646671 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9771 00:59:57.650404 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9772 00:59:57.656244 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9773 00:59:57.659987 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9774 00:59:57.666795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9775 00:59:57.670021 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9776 00:59:57.675943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9777 00:59:57.679746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9778 00:59:57.682901 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9779 00:59:57.690212 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9780 00:59:57.692918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9781 00:59:57.699158 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9782 00:59:57.703517 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9783 00:59:57.706107 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9784 00:59:57.712325 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9785 00:59:57.716060 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9786 00:59:57.718637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9787 00:59:57.722488 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9788 00:59:57.729168 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9789 00:59:57.732134 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9790 00:59:57.738881 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9791 00:59:57.742252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9792 00:59:57.745428 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9793 00:59:57.752181 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9794 00:59:57.755124 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9795 00:59:57.758762 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9796 00:59:57.765361 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9797 00:59:57.768386 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9798 00:59:57.772500 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9799 00:59:57.778645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9800 00:59:57.781322 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9801 00:59:57.788230 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9802 00:59:57.791660 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9803 00:59:57.794767 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9804 00:59:57.801361 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9805 00:59:57.804483 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9806 00:59:57.811583 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9807 00:59:57.814471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9808 00:59:57.817861 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9809 00:59:57.825447 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9810 00:59:57.827556 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9811 00:59:57.831442 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9812 00:59:57.837411 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9813 00:59:57.841600 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9814 00:59:57.848026 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9815 00:59:57.850386 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9816 00:59:57.854201 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9817 00:59:57.860877 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9818 00:59:57.863958 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9819 00:59:57.867445 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9820 00:59:57.873761 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9821 00:59:57.876920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9822 00:59:57.884345 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9823 00:59:57.887321 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9824 00:59:57.890121 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9825 00:59:57.893528 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9826 00:59:57.896997 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9827 00:59:57.903649 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9828 00:59:57.906983 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9829 00:59:57.910572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9830 00:59:57.913184 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9831 00:59:57.919996 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9832 00:59:57.923405 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9833 00:59:57.926872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9834 00:59:57.933573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9835 00:59:57.936744 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9836 00:59:57.939589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9837 00:59:57.947614 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9838 00:59:57.950407 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9839 00:59:57.956874 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9840 00:59:57.959520 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9841 00:59:57.963106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9842 00:59:57.969823 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9843 00:59:57.972844 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9844 00:59:57.979884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9845 00:59:57.982669 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9846 00:59:57.986445 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9847 00:59:57.992652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9848 00:59:57.996210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9849 00:59:58.002550 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9850 00:59:58.005482 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9851 00:59:58.012313 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9852 00:59:58.016496 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9853 00:59:58.018559 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9854 00:59:58.026179 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9855 00:59:58.029308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9856 00:59:58.035276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9857 00:59:58.038532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9858 00:59:58.045206 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9859 00:59:58.048835 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9860 00:59:58.051730 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9861 00:59:58.058411 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9862 00:59:58.061827 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9863 00:59:58.068895 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9864 00:59:58.071930 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9865 00:59:58.075170 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9866 00:59:58.081579 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9867 00:59:58.084545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9868 00:59:58.091438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9869 00:59:58.094516 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9870 00:59:58.101026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9871 00:59:58.104236 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9872 00:59:58.107794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9873 00:59:58.114629 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9874 00:59:58.118013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9875 00:59:58.126116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9876 00:59:58.127250 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9877 00:59:58.130739 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9878 00:59:58.137591 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9879 00:59:58.140604 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9880 00:59:58.147307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9881 00:59:58.150359 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9882 00:59:58.156760 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9883 00:59:58.160763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9884 00:59:58.163583 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9885 00:59:58.170657 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9886 00:59:58.173721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9887 00:59:58.180390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9888 00:59:58.183796 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9889 00:59:58.191003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9890 00:59:58.193862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9891 00:59:58.196369 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9892 00:59:58.203329 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9893 00:59:58.206608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9894 00:59:58.213327 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9895 00:59:58.216407 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9896 00:59:58.219701 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9897 00:59:58.226722 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9898 00:59:58.230103 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9899 00:59:58.236396 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9900 00:59:58.240070 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9901 00:59:58.246104 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9902 00:59:58.249421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9903 00:59:58.252488 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9904 00:59:58.259233 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9905 00:59:58.262200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9906 00:59:58.268965 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9907 00:59:58.272536 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9908 00:59:58.275899 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9909 00:59:58.282552 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9910 00:59:58.286309 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9911 00:59:58.292988 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9912 00:59:58.296095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9913 00:59:58.302344 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9914 00:59:58.305857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9915 00:59:58.309361 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9916 00:59:58.315218 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9917 00:59:58.318372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9918 00:59:58.325597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9919 00:59:58.328413 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9920 00:59:58.334919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9921 00:59:58.338557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9922 00:59:58.344885 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9923 00:59:58.348384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9924 00:59:58.354644 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9925 00:59:58.358466 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9926 00:59:58.361491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9927 00:59:58.368560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9928 00:59:58.371234 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9929 00:59:58.377764 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9930 00:59:58.381007 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9931 00:59:58.387577 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9932 00:59:58.391076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9933 00:59:58.398315 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9934 00:59:58.401729 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9935 00:59:58.407610 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9936 00:59:58.411457 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9937 00:59:58.413962 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9938 00:59:58.420960 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9939 00:59:58.423958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9940 00:59:58.431070 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9941 00:59:58.433994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9942 00:59:58.441042 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9943 00:59:58.443793 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9944 00:59:58.446978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9945 00:59:58.453808 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9946 00:59:58.456983 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9947 00:59:58.464708 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9948 00:59:58.467421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9949 00:59:58.473757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9950 00:59:58.476830 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9951 00:59:58.484076 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9952 00:59:58.487545 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9953 00:59:58.490221 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9954 00:59:58.496851 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9955 00:59:58.499756 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9956 00:59:58.506465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9957 00:59:58.509939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9958 00:59:58.513982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9959 00:59:58.520203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9960 00:59:58.523179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9961 00:59:58.529402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9962 00:59:58.532827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9963 00:59:58.539741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9964 00:59:58.543074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9965 00:59:58.549700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9966 00:59:58.553393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9967 00:59:58.559731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9968 00:59:58.562591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9969 00:59:58.569101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9970 00:59:58.572259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9971 00:59:58.579486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9972 00:59:58.582243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9973 00:59:58.589896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9974 00:59:58.592499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9975 00:59:58.598559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9976 00:59:58.602847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9977 00:59:58.609280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9978 00:59:58.611891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9979 00:59:58.619050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9980 00:59:58.622327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9981 00:59:58.628812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9982 00:59:58.635194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9983 00:59:58.639034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9984 00:59:58.644862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9985 00:59:58.648378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9986 00:59:58.655155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9987 00:59:58.658881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9988 00:59:58.661992 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9989 00:59:58.664433 INFO: [APUAPC] vio 0
9990 00:59:58.671001 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9991 00:59:58.674596 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9992 00:59:58.677910 INFO: [APUAPC] D0_APC_0: 0x400510
9993 00:59:58.681207 INFO: [APUAPC] D0_APC_1: 0x0
9994 00:59:58.684422 INFO: [APUAPC] D0_APC_2: 0x1540
9995 00:59:58.687771 INFO: [APUAPC] D0_APC_3: 0x0
9996 00:59:58.691735 INFO: [APUAPC] D1_APC_0: 0xffffffff
9997 00:59:58.695006 INFO: [APUAPC] D1_APC_1: 0xffffffff
9998 00:59:58.697655 INFO: [APUAPC] D1_APC_2: 0x3fffff
9999 00:59:58.701175 INFO: [APUAPC] D1_APC_3: 0x0
10000 00:59:58.704093 INFO: [APUAPC] D2_APC_0: 0xffffffff
10001 00:59:58.707971 INFO: [APUAPC] D2_APC_1: 0xffffffff
10002 00:59:58.710859 INFO: [APUAPC] D2_APC_2: 0x3fffff
10003 00:59:58.711325 INFO: [APUAPC] D2_APC_3: 0x0
10004 00:59:58.717043 INFO: [APUAPC] D3_APC_0: 0xffffffff
10005 00:59:58.720766 INFO: [APUAPC] D3_APC_1: 0xffffffff
10006 00:59:58.723877 INFO: [APUAPC] D3_APC_2: 0x3fffff
10007 00:59:58.724352 INFO: [APUAPC] D3_APC_3: 0x0
10008 00:59:58.730541 INFO: [APUAPC] D4_APC_0: 0xffffffff
10009 00:59:58.733789 INFO: [APUAPC] D4_APC_1: 0xffffffff
10010 00:59:58.737409 INFO: [APUAPC] D4_APC_2: 0x3fffff
10011 00:59:58.737995 INFO: [APUAPC] D4_APC_3: 0x0
10012 00:59:58.740386 INFO: [APUAPC] D5_APC_0: 0xffffffff
10013 00:59:58.746901 INFO: [APUAPC] D5_APC_1: 0xffffffff
10014 00:59:58.750227 INFO: [APUAPC] D5_APC_2: 0x3fffff
10015 00:59:58.750756 INFO: [APUAPC] D5_APC_3: 0x0
10016 00:59:58.753663 INFO: [APUAPC] D6_APC_0: 0xffffffff
10017 00:59:58.756428 INFO: [APUAPC] D6_APC_1: 0xffffffff
10018 00:59:58.759956 INFO: [APUAPC] D6_APC_2: 0x3fffff
10019 00:59:58.764069 INFO: [APUAPC] D6_APC_3: 0x0
10020 00:59:58.766699 INFO: [APUAPC] D7_APC_0: 0xffffffff
10021 00:59:58.770879 INFO: [APUAPC] D7_APC_1: 0xffffffff
10022 00:59:58.773360 INFO: [APUAPC] D7_APC_2: 0x3fffff
10023 00:59:58.776691 INFO: [APUAPC] D7_APC_3: 0x0
10024 00:59:58.779721 INFO: [APUAPC] D8_APC_0: 0xffffffff
10025 00:59:58.783598 INFO: [APUAPC] D8_APC_1: 0xffffffff
10026 00:59:58.786427 INFO: [APUAPC] D8_APC_2: 0x3fffff
10027 00:59:58.790216 INFO: [APUAPC] D8_APC_3: 0x0
10028 00:59:58.793009 INFO: [APUAPC] D9_APC_0: 0xffffffff
10029 00:59:58.796198 INFO: [APUAPC] D9_APC_1: 0xffffffff
10030 00:59:58.799653 INFO: [APUAPC] D9_APC_2: 0x3fffff
10031 00:59:58.803303 INFO: [APUAPC] D9_APC_3: 0x0
10032 00:59:58.806477 INFO: [APUAPC] D10_APC_0: 0xffffffff
10033 00:59:58.810129 INFO: [APUAPC] D10_APC_1: 0xffffffff
10034 00:59:58.813393 INFO: [APUAPC] D10_APC_2: 0x3fffff
10035 00:59:58.816028 INFO: [APUAPC] D10_APC_3: 0x0
10036 00:59:58.819647 INFO: [APUAPC] D11_APC_0: 0xffffffff
10037 00:59:58.822659 INFO: [APUAPC] D11_APC_1: 0xffffffff
10038 00:59:58.826284 INFO: [APUAPC] D11_APC_2: 0x3fffff
10039 00:59:58.829101 INFO: [APUAPC] D11_APC_3: 0x0
10040 00:59:58.832700 INFO: [APUAPC] D12_APC_0: 0xffffffff
10041 00:59:58.836276 INFO: [APUAPC] D12_APC_1: 0xffffffff
10042 00:59:58.839206 INFO: [APUAPC] D12_APC_2: 0x3fffff
10043 00:59:58.842342 INFO: [APUAPC] D12_APC_3: 0x0
10044 00:59:58.846240 INFO: [APUAPC] D13_APC_0: 0xffffffff
10045 00:59:58.849827 INFO: [APUAPC] D13_APC_1: 0xffffffff
10046 00:59:58.852157 INFO: [APUAPC] D13_APC_2: 0x3fffff
10047 00:59:58.856453 INFO: [APUAPC] D13_APC_3: 0x0
10048 00:59:58.859216 INFO: [APUAPC] D14_APC_0: 0xffffffff
10049 00:59:58.862700 INFO: [APUAPC] D14_APC_1: 0xffffffff
10050 00:59:58.869006 INFO: [APUAPC] D14_APC_2: 0x3fffff
10051 00:59:58.869568 INFO: [APUAPC] D14_APC_3: 0x0
10052 00:59:58.872643 INFO: [APUAPC] D15_APC_0: 0xffffffff
10053 00:59:58.878918 INFO: [APUAPC] D15_APC_1: 0xffffffff
10054 00:59:58.882518 INFO: [APUAPC] D15_APC_2: 0x3fffff
10055 00:59:58.883025 INFO: [APUAPC] D15_APC_3: 0x0
10056 00:59:58.885349 INFO: [APUAPC] APC_CON: 0x4
10057 00:59:58.888730 INFO: [NOCDAPC] D0_APC_0: 0x0
10058 00:59:58.892037 INFO: [NOCDAPC] D0_APC_1: 0x0
10059 00:59:58.895730 INFO: [NOCDAPC] D1_APC_0: 0x0
10060 00:59:58.899728 INFO: [NOCDAPC] D1_APC_1: 0xfff
10061 00:59:58.901978 INFO: [NOCDAPC] D2_APC_0: 0x0
10062 00:59:58.905410 INFO: [NOCDAPC] D2_APC_1: 0xfff
10063 00:59:58.908218 INFO: [NOCDAPC] D3_APC_0: 0x0
10064 00:59:58.911770 INFO: [NOCDAPC] D3_APC_1: 0xfff
10065 00:59:58.912365 INFO: [NOCDAPC] D4_APC_0: 0x0
10066 00:59:58.915856 INFO: [NOCDAPC] D4_APC_1: 0xfff
10067 00:59:58.918676 INFO: [NOCDAPC] D5_APC_0: 0x0
10068 00:59:58.921741 INFO: [NOCDAPC] D5_APC_1: 0xfff
10069 00:59:58.924648 INFO: [NOCDAPC] D6_APC_0: 0x0
10070 00:59:58.928129 INFO: [NOCDAPC] D6_APC_1: 0xfff
10071 00:59:58.931614 INFO: [NOCDAPC] D7_APC_0: 0x0
10072 00:59:58.934895 INFO: [NOCDAPC] D7_APC_1: 0xfff
10073 00:59:58.939282 INFO: [NOCDAPC] D8_APC_0: 0x0
10074 00:59:58.941268 INFO: [NOCDAPC] D8_APC_1: 0xfff
10075 00:59:58.944982 INFO: [NOCDAPC] D9_APC_0: 0x0
10076 00:59:58.948240 INFO: [NOCDAPC] D9_APC_1: 0xfff
10077 00:59:58.948804 INFO: [NOCDAPC] D10_APC_0: 0x0
10078 00:59:58.951445 INFO: [NOCDAPC] D10_APC_1: 0xfff
10079 00:59:58.954859 INFO: [NOCDAPC] D11_APC_0: 0x0
10080 00:59:58.957843 INFO: [NOCDAPC] D11_APC_1: 0xfff
10081 00:59:58.961351 INFO: [NOCDAPC] D12_APC_0: 0x0
10082 00:59:58.964345 INFO: [NOCDAPC] D12_APC_1: 0xfff
10083 00:59:58.968029 INFO: [NOCDAPC] D13_APC_0: 0x0
10084 00:59:58.971618 INFO: [NOCDAPC] D13_APC_1: 0xfff
10085 00:59:58.974574 INFO: [NOCDAPC] D14_APC_0: 0x0
10086 00:59:58.977644 INFO: [NOCDAPC] D14_APC_1: 0xfff
10087 00:59:58.981242 INFO: [NOCDAPC] D15_APC_0: 0x0
10088 00:59:58.984225 INFO: [NOCDAPC] D15_APC_1: 0xfff
10089 00:59:58.987453 INFO: [NOCDAPC] APC_CON: 0x4
10090 00:59:58.990833 INFO: [APUAPC] set_apusys_apc done
10091 00:59:58.994281 INFO: [DEVAPC] devapc_init done
10092 00:59:58.998270 INFO: GICv3 without legacy support detected.
10093 00:59:59.001099 INFO: ARM GICv3 driver initialized in EL3
10094 00:59:59.004503 INFO: Maximum SPI INTID supported: 639
10095 00:59:59.007705 INFO: BL31: Initializing runtime services
10096 00:59:59.014121 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10097 00:59:59.017388 INFO: SPM: enable CPC mode
10098 00:59:59.024612 INFO: mcdi ready for mcusys-off-idle and system suspend
10099 00:59:59.027300 INFO: BL31: Preparing for EL3 exit to normal world
10100 00:59:59.030707 INFO: Entry point address = 0x80000000
10101 00:59:59.033252 INFO: SPSR = 0x8
10102 00:59:59.039105
10103 00:59:59.039733
10104 00:59:59.040219
10105 00:59:59.041978 Starting depthcharge on Spherion...
10106 00:59:59.042565
10107 00:59:59.043049 Wipe memory regions:
10108 00:59:59.043498
10109 00:59:59.046417 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10110 00:59:59.047068 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10111 00:59:59.047564 Setting prompt string to ['asurada:']
10112 00:59:59.048167 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10113 00:59:59.049071 [0x00000040000000, 0x00000054600000)
10114 00:59:59.167820
10115 00:59:59.168386 [0x00000054660000, 0x00000080000000)
10116 00:59:59.428293
10117 00:59:59.428907 [0x000000821a7280, 0x000000ffe64000)
10118 01:00:00.173302
10119 01:00:00.173873 [0x00000100000000, 0x00000240000000)
10120 01:00:02.063830
10121 01:00:02.066980 Initializing XHCI USB controller at 0x11200000.
10122 01:00:03.048242
10123 01:00:03.048792 R8152: Initializing
10124 01:00:03.049161
10125 01:00:03.051192 Version 9 (ocp_data = 6010)
10126 01:00:03.051800
10127 01:00:03.055168 R8152: Done initializing
10128 01:00:03.055779
10129 01:00:03.056162 Adding net device
10130 01:00:03.452352
10131 01:00:03.455626 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10132 01:00:03.456449
10133 01:00:03.456851
10134 01:00:03.457203
10135 01:00:03.458028 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 01:00:03.559302 asurada: tftpboot 192.168.201.1 12571106/tftp-deploy-jxn96ay5/kernel/image.itb 12571106/tftp-deploy-jxn96ay5/kernel/cmdline
10138 01:00:03.560019 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10139 01:00:03.560502 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10140 01:00:03.565422 tftpboot 192.168.201.1 12571106/tftp-deploy-jxn96ay5/kernel/image.itp-deploy-jxn96ay5/kernel/cmdline
10141 01:00:03.565897
10142 01:00:03.566266 Waiting for link
10143 01:00:03.766915
10144 01:00:03.767479 done.
10145 01:00:03.767894
10146 01:00:03.768241 MAC: f4:f5:e8:50:de:0a
10147 01:00:03.768573
10148 01:00:03.770510 Sending DHCP discover... done.
10149 01:00:03.770973
10150 01:00:03.773286 Waiting for reply... done.
10151 01:00:03.773945
10152 01:00:03.776710 Sending DHCP request... done.
10153 01:00:03.777204
10154 01:00:03.780614 Waiting for reply... done.
10155 01:00:03.781176
10156 01:00:03.781610 My ip is 192.168.201.14
10157 01:00:03.781961
10158 01:00:03.783648 The DHCP server ip is 192.168.201.1
10159 01:00:03.784290
10160 01:00:03.790233 TFTP server IP predefined by user: 192.168.201.1
10161 01:00:03.790778
10162 01:00:03.796841 Bootfile predefined by user: 12571106/tftp-deploy-jxn96ay5/kernel/image.itb
10163 01:00:03.797401
10164 01:00:03.800619 Sending tftp read request... done.
10165 01:00:03.801140
10166 01:00:03.806540 Waiting for the transfer...
10167 01:00:03.807028
10168 01:00:04.092223 00000000 ################################################################
10169 01:00:04.092361
10170 01:00:04.357655 00080000 ################################################################
10171 01:00:04.357801
10172 01:00:04.608283 00100000 ################################################################
10173 01:00:04.608416
10174 01:00:04.847400 00180000 ################################################################
10175 01:00:04.847571
10176 01:00:05.110592 00200000 ################################################################
10177 01:00:05.110725
10178 01:00:05.369320 00280000 ################################################################
10179 01:00:05.369464
10180 01:00:05.613428 00300000 ################################################################
10181 01:00:05.613558
10182 01:00:05.856533 00380000 ################################################################
10183 01:00:05.856664
10184 01:00:06.109347 00400000 ################################################################
10185 01:00:06.109502
10186 01:00:06.359600 00480000 ################################################################
10187 01:00:06.359749
10188 01:00:06.610002 00500000 ################################################################
10189 01:00:06.610137
10190 01:00:06.882458 00580000 ################################################################
10191 01:00:06.882587
10192 01:00:07.132450 00600000 ################################################################
10193 01:00:07.132583
10194 01:00:07.370927 00680000 ################################################################
10195 01:00:07.371060
10196 01:00:07.637083 00700000 ################################################################
10197 01:00:07.637222
10198 01:00:07.910360 00780000 ################################################################
10199 01:00:07.910497
10200 01:00:08.169011 00800000 ################################################################
10201 01:00:08.169149
10202 01:00:08.401423 00880000 ################################################################
10203 01:00:08.401556
10204 01:00:08.654093 00900000 ################################################################
10205 01:00:08.654241
10206 01:00:08.900392 00980000 ################################################################
10207 01:00:08.900531
10208 01:00:09.164257 00a00000 ################################################################
10209 01:00:09.164391
10210 01:00:09.434089 00a80000 ################################################################
10211 01:00:09.434231
10212 01:00:09.686713 00b00000 ################################################################
10213 01:00:09.686858
10214 01:00:09.920170 00b80000 ################################################################
10215 01:00:09.920301
10216 01:00:10.148974 00c00000 ################################################################
10217 01:00:10.149106
10218 01:00:10.379506 00c80000 ################################################################
10219 01:00:10.379644
10220 01:00:10.606725 00d00000 ################################################################
10221 01:00:10.606849
10222 01:00:10.850368 00d80000 ################################################################
10223 01:00:10.850509
10224 01:00:11.082150 00e00000 ################################################################
10225 01:00:11.082286
10226 01:00:11.308910 00e80000 ################################################################
10227 01:00:11.309040
10228 01:00:11.551341 00f00000 ################################################################
10229 01:00:11.551474
10230 01:00:11.820617 00f80000 ################################################################
10231 01:00:11.820757
10232 01:00:12.071441 01000000 ################################################################
10233 01:00:12.071579
10234 01:00:12.340569 01080000 ################################################################
10235 01:00:12.340707
10236 01:00:12.611125 01100000 ################################################################
10237 01:00:12.611261
10238 01:00:12.854174 01180000 ################################################################
10239 01:00:12.854320
10240 01:00:13.105370 01200000 ################################################################
10241 01:00:13.105517
10242 01:00:13.336408 01280000 ################################################################
10243 01:00:13.336542
10244 01:00:13.578675 01300000 ################################################################
10245 01:00:13.578807
10246 01:00:13.839222 01380000 ################################################################
10247 01:00:13.839448
10248 01:00:14.083908 01400000 ################################################################
10249 01:00:14.084083
10250 01:00:14.343622 01480000 ################################################################
10251 01:00:14.343800
10252 01:00:14.599026 01500000 ################################################################
10253 01:00:14.599180
10254 01:00:14.851856 01580000 ################################################################
10255 01:00:14.852012
10256 01:00:15.096111 01600000 ################################################################
10257 01:00:15.096266
10258 01:00:15.353824 01680000 ################################################################
10259 01:00:15.353965
10260 01:00:15.603485 01700000 ################################################################
10261 01:00:15.603644
10262 01:00:15.865626 01780000 ################################################################
10263 01:00:15.865766
10264 01:00:16.105828 01800000 ################################################################
10265 01:00:16.105986
10266 01:00:16.345979 01880000 ################################################################
10267 01:00:16.346140
10268 01:00:16.583391 01900000 ################################################################
10269 01:00:16.583519
10270 01:00:16.843099 01980000 ################################################################
10271 01:00:16.843238
10272 01:00:17.105276 01a00000 ################################################################
10273 01:00:17.105435
10274 01:00:17.362084 01a80000 ################################################################
10275 01:00:17.362247
10276 01:00:17.623549 01b00000 ################################################################
10277 01:00:17.623723
10278 01:00:17.873836 01b80000 ################################################################
10279 01:00:17.873995
10280 01:00:18.124718 01c00000 ################################################################
10281 01:00:18.124849
10282 01:00:18.133044 01c80000 ### done.
10283 01:00:18.133121
10284 01:00:18.136326 The bootfile was 29901974 bytes long.
10285 01:00:18.136499
10286 01:00:18.139664 Sending tftp read request... done.
10287 01:00:18.139788
10288 01:00:18.142606 Waiting for the transfer...
10289 01:00:18.142698
10290 01:00:18.142772 00000000 # done.
10291 01:00:18.142842
10292 01:00:18.152540 Command line loaded dynamically from TFTP file: 12571106/tftp-deploy-jxn96ay5/kernel/cmdline
10293 01:00:18.152728
10294 01:00:18.172771 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571106/extract-nfsrootfs-3febsd3o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10295 01:00:18.173029
10296 01:00:18.175988 Loading FIT.
10297 01:00:18.176190
10298 01:00:18.179069 Image ramdisk-1 has 17804040 bytes.
10299 01:00:18.179353
10300 01:00:18.179527 Image fdt-1 has 47278 bytes.
10301 01:00:18.179705
10302 01:00:18.182413 Image kernel-1 has 12048624 bytes.
10303 01:00:18.182748
10304 01:00:18.192418 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 01:00:18.192799
10306 01:00:18.208643 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 01:00:18.209218
10308 01:00:18.215297 Choosing best match conf-1 for compat google,spherion-rev2.
10309 01:00:18.220079
10310 01:00:18.223866 Connected to device vid:did:rid of 1ae0:0028:00
10311 01:00:18.231792
10312 01:00:18.234248 tpm_get_response: command 0x17b, return code 0x0
10313 01:00:18.234704
10314 01:00:18.237485 ec_init: CrosEC protocol v3 supported (256, 248)
10315 01:00:18.241520
10316 01:00:18.245578 tpm_cleanup: add release locality here.
10317 01:00:18.246075
10318 01:00:18.246438 Shutting down all USB controllers.
10319 01:00:18.249408
10320 01:00:18.249961 Removing current net device
10321 01:00:18.250328
10322 01:00:18.254706 Exiting depthcharge with code 4 at timestamp: 48634876
10323 01:00:18.255163
10324 01:00:18.258443 LZMA decompressing kernel-1 to 0x821a6718
10325 01:00:18.258968
10326 01:00:18.261606 LZMA decompressing kernel-1 to 0x40000000
10327 01:00:19.760649
10328 01:00:19.761206 jumping to kernel
10329 01:00:19.762911 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10330 01:00:19.763445 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10331 01:00:19.763897 Setting prompt string to ['Linux version [0-9]']
10332 01:00:19.764303 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 01:00:19.764678 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 01:00:19.843592
10335 01:00:19.847035 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 01:00:19.850576 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10337 01:00:19.851102 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 01:00:19.851504 Setting prompt string to []
10339 01:00:19.851976 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10340 01:00:19.852370 Using line separator: #'\n'#
10341 01:00:19.852890 No login prompt set.
10342 01:00:19.853532 Parsing kernel messages
10343 01:00:19.853878 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10344 01:00:19.854449 [login-action] Waiting for messages, (timeout 00:04:04)
10345 01:00:19.869776 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10346 01:00:19.873109 [ 0.000000] random: crng init done
10347 01:00:19.880365 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10348 01:00:19.882749 [ 0.000000] efi: UEFI not found.
10349 01:00:19.890065 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10350 01:00:19.896605 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10351 01:00:19.906314 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10352 01:00:19.916214 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10353 01:00:19.922539 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10354 01:00:19.929513 [ 0.000000] printk: bootconsole [mtk8250] enabled
10355 01:00:19.936139 [ 0.000000] NUMA: No NUMA configuration found
10356 01:00:19.942986 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10357 01:00:19.946394 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10358 01:00:19.949360 [ 0.000000] Zone ranges:
10359 01:00:19.955876 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10360 01:00:19.959263 [ 0.000000] DMA32 empty
10361 01:00:19.965740 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10362 01:00:19.969403 [ 0.000000] Movable zone start for each node
10363 01:00:19.972914 [ 0.000000] Early memory node ranges
10364 01:00:19.979259 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10365 01:00:19.986093 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10366 01:00:19.992249 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10367 01:00:19.998960 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10368 01:00:20.005904 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10369 01:00:20.012121 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10370 01:00:20.068237 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10371 01:00:20.074440 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10372 01:00:20.082534 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10373 01:00:20.085394 [ 0.000000] psci: probing for conduit method from DT.
10374 01:00:20.090936 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10375 01:00:20.094116 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10376 01:00:20.100611 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10377 01:00:20.104167 [ 0.000000] psci: SMC Calling Convention v1.2
10378 01:00:20.110873 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10379 01:00:20.114270 [ 0.000000] Detected VIPT I-cache on CPU0
10380 01:00:20.121119 [ 0.000000] CPU features: detected: GIC system register CPU interface
10381 01:00:20.127813 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10382 01:00:20.134025 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10383 01:00:20.141862 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10384 01:00:20.150559 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10385 01:00:20.156802 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10386 01:00:20.160389 [ 0.000000] alternatives: applying boot alternatives
10387 01:00:20.167517 [ 0.000000] Fallback order for Node 0: 0
10388 01:00:20.173471 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10389 01:00:20.177256 [ 0.000000] Policy zone: Normal
10390 01:00:20.200154 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12571106/extract-nfsrootfs-3febsd3o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10391 01:00:20.209885 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10392 01:00:20.220914 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10393 01:00:20.230753 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10394 01:00:20.237457 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10395 01:00:20.240738 <6>[ 0.000000] software IO TLB: area num 8.
10396 01:00:20.297768 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10397 01:00:20.447046 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10398 01:00:20.453080 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10399 01:00:20.460565 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10400 01:00:20.463002 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10401 01:00:20.470359 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10402 01:00:20.476652 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10403 01:00:20.479624 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10404 01:00:20.489469 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10405 01:00:20.496005 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10406 01:00:20.502747 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10407 01:00:20.509075 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10408 01:00:20.512344 <6>[ 0.000000] GICv3: 608 SPIs implemented
10409 01:00:20.515514 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10410 01:00:20.522349 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10411 01:00:20.525488 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10412 01:00:20.532280 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10413 01:00:20.545582 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10414 01:00:20.558650 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10415 01:00:20.564912 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10416 01:00:20.573593 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10417 01:00:20.587073 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10418 01:00:20.592897 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10419 01:00:20.600230 <6>[ 0.009187] Console: colour dummy device 80x25
10420 01:00:20.609892 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10421 01:00:20.616067 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10422 01:00:20.619323 <6>[ 0.029282] LSM: Security Framework initializing
10423 01:00:20.625869 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 01:00:20.636012 <6>[ 0.042037] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 01:00:20.645813 <6>[ 0.051449] cblist_init_generic: Setting adjustable number of callback queues.
10426 01:00:20.652505 <6>[ 0.058893] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 01:00:20.659033 <6>[ 0.065233] cblist_init_generic: Setting adjustable number of callback queues.
10428 01:00:20.665428 <6>[ 0.072659] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 01:00:20.668844 <6>[ 0.079100] rcu: Hierarchical SRCU implementation.
10430 01:00:20.675349 <6>[ 0.084146] rcu: Max phase no-delay instances is 1000.
10431 01:00:20.682306 <6>[ 0.091203] EFI services will not be available.
10432 01:00:20.685278 <6>[ 0.096187] smp: Bringing up secondary CPUs ...
10433 01:00:20.693761 <6>[ 0.101235] Detected VIPT I-cache on CPU1
10434 01:00:20.700929 <6>[ 0.101302] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10435 01:00:20.707737 <6>[ 0.101335] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10436 01:00:20.710648 <6>[ 0.101671] Detected VIPT I-cache on CPU2
10437 01:00:20.720363 <6>[ 0.101719] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10438 01:00:20.727054 <6>[ 0.101734] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10439 01:00:20.730558 <6>[ 0.101990] Detected VIPT I-cache on CPU3
10440 01:00:20.737433 <6>[ 0.102036] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10441 01:00:20.744061 <6>[ 0.102050] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10442 01:00:20.747475 <6>[ 0.102355] CPU features: detected: Spectre-v4
10443 01:00:20.753844 <6>[ 0.102362] CPU features: detected: Spectre-BHB
10444 01:00:20.756556 <6>[ 0.102366] Detected PIPT I-cache on CPU4
10445 01:00:20.763638 <6>[ 0.102423] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10446 01:00:20.770308 <6>[ 0.102439] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10447 01:00:20.777342 <6>[ 0.102731] Detected PIPT I-cache on CPU5
10448 01:00:20.783610 <6>[ 0.102793] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10449 01:00:20.790207 <6>[ 0.102811] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10450 01:00:20.793880 <6>[ 0.103094] Detected PIPT I-cache on CPU6
10451 01:00:20.800057 <6>[ 0.103158] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10452 01:00:20.806440 <6>[ 0.103174] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10453 01:00:20.813297 <6>[ 0.103472] Detected PIPT I-cache on CPU7
10454 01:00:20.820284 <6>[ 0.103537] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10455 01:00:20.826084 <6>[ 0.103553] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10456 01:00:20.829503 <6>[ 0.103600] smp: Brought up 1 node, 8 CPUs
10457 01:00:20.836366 <6>[ 0.244959] SMP: Total of 8 processors activated.
10458 01:00:20.839830 <6>[ 0.249879] CPU features: detected: 32-bit EL0 Support
10459 01:00:20.849802 <6>[ 0.255242] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10460 01:00:20.855641 <6>[ 0.264097] CPU features: detected: Common not Private translations
10461 01:00:20.862279 <6>[ 0.270572] CPU features: detected: CRC32 instructions
10462 01:00:20.869548 <6>[ 0.275923] CPU features: detected: RCpc load-acquire (LDAPR)
10463 01:00:20.872240 <6>[ 0.281920] CPU features: detected: LSE atomic instructions
10464 01:00:20.878465 <6>[ 0.287702] CPU features: detected: Privileged Access Never
10465 01:00:20.885633 <6>[ 0.293481] CPU features: detected: RAS Extension Support
10466 01:00:20.892153 <6>[ 0.299090] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10467 01:00:20.895743 <6>[ 0.306354] CPU: All CPU(s) started at EL2
10468 01:00:20.901881 <6>[ 0.310697] alternatives: applying system-wide alternatives
10469 01:00:20.911915 <6>[ 0.321450] devtmpfs: initialized
10470 01:00:20.927639 <6>[ 0.330361] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10471 01:00:20.933942 <6>[ 0.340324] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10472 01:00:20.940461 <6>[ 0.348562] pinctrl core: initialized pinctrl subsystem
10473 01:00:20.944118 <6>[ 0.355204] DMI not present or invalid.
10474 01:00:20.950819 <6>[ 0.359612] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10475 01:00:20.959981 <6>[ 0.366434] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10476 01:00:20.966271 <6>[ 0.374016] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10477 01:00:20.975932 <6>[ 0.382246] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10478 01:00:20.982513 <6>[ 0.390489] audit: initializing netlink subsys (disabled)
10479 01:00:20.989254 <5>[ 0.396182] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10480 01:00:20.996232 <6>[ 0.396872] thermal_sys: Registered thermal governor 'step_wise'
10481 01:00:21.002873 <6>[ 0.404151] thermal_sys: Registered thermal governor 'power_allocator'
10482 01:00:21.006101 <6>[ 0.410404] cpuidle: using governor menu
10483 01:00:21.012993 <6>[ 0.421365] NET: Registered PF_QIPCRTR protocol family
10484 01:00:21.019442 <6>[ 0.426848] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10485 01:00:21.026342 <6>[ 0.433949] ASID allocator initialised with 32768 entries
10486 01:00:21.028776 <6>[ 0.440500] Serial: AMBA PL011 UART driver
10487 01:00:21.039395 <4>[ 0.449240] Trying to register duplicate clock ID: 134
10488 01:00:21.093292 <6>[ 0.506472] KASLR enabled
10489 01:00:21.107662 <6>[ 0.514207] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10490 01:00:21.114072 <6>[ 0.521223] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10491 01:00:21.121009 <6>[ 0.527712] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10492 01:00:21.127618 <6>[ 0.534714] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10493 01:00:21.133903 <6>[ 0.541202] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10494 01:00:21.140873 <6>[ 0.548206] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10495 01:00:21.147437 <6>[ 0.554695] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10496 01:00:21.154491 <6>[ 0.561699] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10497 01:00:21.156670 <6>[ 0.569195] ACPI: Interpreter disabled.
10498 01:00:21.165312 <6>[ 0.575604] iommu: Default domain type: Translated
10499 01:00:21.172055 <6>[ 0.580717] iommu: DMA domain TLB invalidation policy: strict mode
10500 01:00:21.175823 <5>[ 0.587379] SCSI subsystem initialized
10501 01:00:21.181808 <6>[ 0.591542] usbcore: registered new interface driver usbfs
10502 01:00:21.188705 <6>[ 0.597277] usbcore: registered new interface driver hub
10503 01:00:21.191868 <6>[ 0.602830] usbcore: registered new device driver usb
10504 01:00:21.198631 <6>[ 0.608927] pps_core: LinuxPPS API ver. 1 registered
10505 01:00:21.208620 <6>[ 0.614120] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10506 01:00:21.212140 <6>[ 0.623468] PTP clock support registered
10507 01:00:21.215006 <6>[ 0.627710] EDAC MC: Ver: 3.0.0
10508 01:00:21.223213 <6>[ 0.632867] FPGA manager framework
10509 01:00:21.229407 <6>[ 0.636546] Advanced Linux Sound Architecture Driver Initialized.
10510 01:00:21.233224 <6>[ 0.643318] vgaarb: loaded
10511 01:00:21.239343 <6>[ 0.646474] clocksource: Switched to clocksource arch_sys_counter
10512 01:00:21.243667 <5>[ 0.652911] VFS: Disk quotas dquot_6.6.0
10513 01:00:21.249454 <6>[ 0.657096] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10514 01:00:21.252953 <6>[ 0.664286] pnp: PnP ACPI: disabled
10515 01:00:21.261298 <6>[ 0.670999] NET: Registered PF_INET protocol family
10516 01:00:21.271098 <6>[ 0.676598] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10517 01:00:21.282322 <6>[ 0.688919] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10518 01:00:21.292039 <6>[ 0.697734] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10519 01:00:21.299658 <6>[ 0.705706] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10520 01:00:21.308389 <6>[ 0.714402] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10521 01:00:21.315541 <6>[ 0.724163] TCP: Hash tables configured (established 65536 bind 65536)
10522 01:00:21.321617 <6>[ 0.731029] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 01:00:21.331666 <6>[ 0.738232] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 01:00:21.338523 <6>[ 0.745933] NET: Registered PF_UNIX/PF_LOCAL protocol family
10525 01:00:21.345004 <6>[ 0.752080] RPC: Registered named UNIX socket transport module.
10526 01:00:21.347808 <6>[ 0.758231] RPC: Registered udp transport module.
10527 01:00:21.355275 <6>[ 0.763162] RPC: Registered tcp transport module.
10528 01:00:21.361108 <6>[ 0.768095] RPC: Registered tcp NFSv4.1 backchannel transport module.
10529 01:00:21.364264 <6>[ 0.774760] PCI: CLS 0 bytes, default 64
10530 01:00:21.367640 <6>[ 0.779085] Unpacking initramfs...
10531 01:00:21.391846 <6>[ 0.798606] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10532 01:00:21.402310 <6>[ 0.807272] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10533 01:00:21.405549 <6>[ 0.816115] kvm [1]: IPA Size Limit: 40 bits
10534 01:00:21.411846 <6>[ 0.820643] kvm [1]: GICv3: no GICV resource entry
10535 01:00:21.415221 <6>[ 0.825663] kvm [1]: disabling GICv2 emulation
10536 01:00:21.421757 <6>[ 0.830352] kvm [1]: GIC system register CPU interface enabled
10537 01:00:21.424879 <6>[ 0.836519] kvm [1]: vgic interrupt IRQ18
10538 01:00:21.431533 <6>[ 0.840877] kvm [1]: VHE mode initialized successfully
10539 01:00:21.437959 <5>[ 0.847368] Initialise system trusted keyrings
10540 01:00:21.444983 <6>[ 0.852195] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10541 01:00:21.452064 <6>[ 0.862220] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10542 01:00:21.459498 <5>[ 0.868561] NFS: Registering the id_resolver key type
10543 01:00:21.461906 <5>[ 0.873861] Key type id_resolver registered
10544 01:00:21.469153 <5>[ 0.878277] Key type id_legacy registered
10545 01:00:21.475133 <6>[ 0.882554] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10546 01:00:21.482188 <6>[ 0.889476] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10547 01:00:21.488337 <6>[ 0.897173] 9p: Installing v9fs 9p2000 file system support
10548 01:00:21.525340 <5>[ 0.935257] Key type asymmetric registered
10549 01:00:21.528213 <5>[ 0.939586] Asymmetric key parser 'x509' registered
10550 01:00:21.538125 <6>[ 0.944718] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10551 01:00:21.541379 <6>[ 0.952343] io scheduler mq-deadline registered
10552 01:00:21.545156 <6>[ 0.957123] io scheduler kyber registered
10553 01:00:21.564113 <6>[ 0.974133] EINJ: ACPI disabled.
10554 01:00:21.596133 <4>[ 0.999426] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 01:00:21.605683 <4>[ 1.010048] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 01:00:21.620473 <6>[ 1.030581] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10557 01:00:21.628478 <6>[ 1.038452] printk: console [ttyS0] disabled
10558 01:00:21.656147 <6>[ 1.063099] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10559 01:00:21.662699 <6>[ 1.072571] printk: console [ttyS0] enabled
10560 01:00:21.666129 <6>[ 1.072571] printk: console [ttyS0] enabled
10561 01:00:21.673237 <6>[ 1.081464] printk: bootconsole [mtk8250] disabled
10562 01:00:21.676443 <6>[ 1.081464] printk: bootconsole [mtk8250] disabled
10563 01:00:21.682882 <6>[ 1.092454] SuperH (H)SCI(F) driver initialized
10564 01:00:21.685903 <6>[ 1.097725] msm_serial: driver initialized
10565 01:00:21.699575 <6>[ 1.106648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10566 01:00:21.710019 <6>[ 1.115193] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10567 01:00:21.716481 <6>[ 1.123735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10568 01:00:21.726104 <6>[ 1.132366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10569 01:00:21.736085 <6>[ 1.141074] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10570 01:00:21.742626 <6>[ 1.149787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10571 01:00:21.752647 <6>[ 1.158333] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10572 01:00:21.759268 <6>[ 1.167128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10573 01:00:21.768949 <6>[ 1.175670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10574 01:00:21.781266 <6>[ 1.191154] loop: module loaded
10575 01:00:21.787577 <6>[ 1.197048] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10576 01:00:21.810516 <4>[ 1.220246] mtk-pmic-keys: Failed to locate of_node [id: -1]
10577 01:00:21.817092 <6>[ 1.227022] megasas: 07.719.03.00-rc1
10578 01:00:21.826704 <6>[ 1.236637] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10579 01:00:21.836084 <6>[ 1.245875] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10580 01:00:21.852809 <6>[ 1.262484] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10581 01:00:21.912776 <6>[ 1.316406] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10582 01:00:22.105936 <6>[ 1.516096] Freeing initrd memory: 17380K
10583 01:00:22.115879 <6>[ 1.526027] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10584 01:00:22.127141 <6>[ 1.537152] tun: Universal TUN/TAP device driver, 1.6
10585 01:00:22.130247 <6>[ 1.543227] thunder_xcv, ver 1.0
10586 01:00:22.134382 <6>[ 1.546734] thunder_bgx, ver 1.0
10587 01:00:22.137301 <6>[ 1.550226] nicpf, ver 1.0
10588 01:00:22.147316 <6>[ 1.554240] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10589 01:00:22.150753 <6>[ 1.561717] hns3: Copyright (c) 2017 Huawei Corporation.
10590 01:00:22.157546 <6>[ 1.567307] hclge is initializing
10591 01:00:22.160494 <6>[ 1.570889] e1000: Intel(R) PRO/1000 Network Driver
10592 01:00:22.167045 <6>[ 1.576017] e1000: Copyright (c) 1999-2006 Intel Corporation.
10593 01:00:22.170561 <6>[ 1.582030] e1000e: Intel(R) PRO/1000 Network Driver
10594 01:00:22.177514 <6>[ 1.587245] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10595 01:00:22.183929 <6>[ 1.593431] igb: Intel(R) Gigabit Ethernet Network Driver
10596 01:00:22.190459 <6>[ 1.599081] igb: Copyright (c) 2007-2014 Intel Corporation.
10597 01:00:22.196909 <6>[ 1.604918] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10598 01:00:22.203604 <6>[ 1.611436] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10599 01:00:22.206749 <6>[ 1.617900] sky2: driver version 1.30
10600 01:00:22.214116 <6>[ 1.622899] VFIO - User Level meta-driver version: 0.3
10601 01:00:22.221633 <6>[ 1.631142] usbcore: registered new interface driver usb-storage
10602 01:00:22.228308 <6>[ 1.637590] usbcore: registered new device driver onboard-usb-hub
10603 01:00:22.236692 <6>[ 1.646776] mt6397-rtc mt6359-rtc: registered as rtc0
10604 01:00:22.247703 <6>[ 1.652244] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:00:22 UTC (1705626022)
10605 01:00:22.250220 <6>[ 1.661813] i2c_dev: i2c /dev entries driver
10606 01:00:22.267115 <6>[ 1.673610] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10607 01:00:22.287789 <6>[ 1.697598] cpu cpu0: EM: created perf domain
10608 01:00:22.290758 <6>[ 1.702530] cpu cpu4: EM: created perf domain
10609 01:00:22.297989 <6>[ 1.708153] sdhci: Secure Digital Host Controller Interface driver
10610 01:00:22.304935 <6>[ 1.714588] sdhci: Copyright(c) Pierre Ossman
10611 01:00:22.311944 <6>[ 1.719549] Synopsys Designware Multimedia Card Interface Driver
10612 01:00:22.318193 <6>[ 1.726191] sdhci-pltfm: SDHCI platform and OF driver helper
10613 01:00:22.321124 <6>[ 1.726225] mmc0: CQHCI version 5.10
10614 01:00:22.327780 <6>[ 1.736554] ledtrig-cpu: registered to indicate activity on CPUs
10615 01:00:22.335022 <6>[ 1.743600] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10616 01:00:22.340887 <6>[ 1.750658] usbcore: registered new interface driver usbhid
10617 01:00:22.344632 <6>[ 1.756480] usbhid: USB HID core driver
10618 01:00:22.351650 <6>[ 1.760684] spi_master spi0: will run message pump with realtime priority
10619 01:00:22.400426 <6>[ 1.804020] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10620 01:00:22.420776 <6>[ 1.820330] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10621 01:00:22.424633 <6>[ 1.833879] mmc0: Command Queue Engine enabled
10622 01:00:22.430686 <6>[ 1.835326] cros-ec-spi spi0.0: Chrome EC device registered
10623 01:00:22.437494 <6>[ 1.838628] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10624 01:00:22.440965 <6>[ 1.851629] mmcblk0: mmc0:0001 DA4128 116 GiB
10625 01:00:22.450894 <6>[ 1.857630] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10626 01:00:22.457724 <6>[ 1.861340] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10627 01:00:22.464308 <6>[ 1.868059] NET: Registered PF_PACKET protocol family
10628 01:00:22.468142 <6>[ 1.874136] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10629 01:00:22.473901 <6>[ 1.878274] 9pnet: Installing 9P2000 support
10630 01:00:22.478088 <6>[ 1.884104] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10631 01:00:22.483888 <5>[ 1.887949] Key type dns_resolver registered
10632 01:00:22.490995 <6>[ 1.893807] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10633 01:00:22.494390 <6>[ 1.898147] registered taskstats version 1
10634 01:00:22.497073 <5>[ 1.908593] Loading compiled-in X.509 certificates
10635 01:00:22.526573 <4>[ 1.929882] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 01:00:22.536113 <4>[ 1.940604] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 01:00:22.543513 <3>[ 1.951150] debugfs: File 'uA_load' in directory '/' already present!
10638 01:00:22.549381 <3>[ 1.957852] debugfs: File 'min_uV' in directory '/' already present!
10639 01:00:22.556243 <3>[ 1.964461] debugfs: File 'max_uV' in directory '/' already present!
10640 01:00:22.562930 <3>[ 1.971116] debugfs: File 'constraint_flags' in directory '/' already present!
10641 01:00:22.573640 <3>[ 1.980634] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10642 01:00:22.582482 <6>[ 1.992776] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10643 01:00:22.589569 <6>[ 1.999490] xhci-mtk 11200000.usb: xHCI Host Controller
10644 01:00:22.596079 <6>[ 2.004988] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10645 01:00:22.606108 <6>[ 2.012827] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10646 01:00:22.613115 <6>[ 2.022244] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10647 01:00:22.619598 <6>[ 2.028300] xhci-mtk 11200000.usb: xHCI Host Controller
10648 01:00:22.626008 <6>[ 2.033775] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10649 01:00:22.632103 <6>[ 2.041418] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10650 01:00:22.638806 <6>[ 2.049162] hub 1-0:1.0: USB hub found
10651 01:00:22.642179 <6>[ 2.053181] hub 1-0:1.0: 1 port detected
10652 01:00:22.652183 <6>[ 2.057463] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10653 01:00:22.655353 <6>[ 2.066172] hub 2-0:1.0: USB hub found
10654 01:00:22.659099 <6>[ 2.070189] hub 2-0:1.0: 1 port detected
10655 01:00:22.668750 <6>[ 2.077970] mtk-msdc 11f70000.mmc: Got CD GPIO
10656 01:00:22.679281 <6>[ 2.086220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10657 01:00:22.686124 <6>[ 2.094311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10658 01:00:22.695553 <4>[ 2.102219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10659 01:00:22.706026 <6>[ 2.111745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10660 01:00:22.712118 <6>[ 2.119826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10661 01:00:22.719230 <6>[ 2.127944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10662 01:00:22.729247 <6>[ 2.135879] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10663 01:00:22.735947 <6>[ 2.143697] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10664 01:00:22.745487 <6>[ 2.151515] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10665 01:00:22.755680 <6>[ 2.161995] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10666 01:00:22.762312 <6>[ 2.170380] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10667 01:00:22.772536 <6>[ 2.178720] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10668 01:00:22.778402 <6>[ 2.187059] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10669 01:00:22.788394 <6>[ 2.195398] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10670 01:00:22.798436 <6>[ 2.203737] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10671 01:00:22.804959 <6>[ 2.212074] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10672 01:00:22.815525 <6>[ 2.220413] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10673 01:00:22.822124 <6>[ 2.228752] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10674 01:00:22.831566 <6>[ 2.237091] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10675 01:00:22.838457 <6>[ 2.245429] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10676 01:00:22.848241 <6>[ 2.253779] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10677 01:00:22.855020 <6>[ 2.262118] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10678 01:00:22.865024 <6>[ 2.270457] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10679 01:00:22.872285 <6>[ 2.278797] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10680 01:00:22.877979 <6>[ 2.287583] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10681 01:00:22.884801 <6>[ 2.294755] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10682 01:00:22.892661 <6>[ 2.301519] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10683 01:00:22.901407 <6>[ 2.308281] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10684 01:00:22.907856 <6>[ 2.315220] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10685 01:00:22.914698 <6>[ 2.322083] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10686 01:00:22.924868 <6>[ 2.331211] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10687 01:00:22.934356 <6>[ 2.340330] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10688 01:00:22.945333 <6>[ 2.349623] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10689 01:00:22.954048 <6>[ 2.359104] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10690 01:00:22.961030 <6>[ 2.368570] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10691 01:00:22.971313 <6>[ 2.377689] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10692 01:00:22.981013 <6>[ 2.387154] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10693 01:00:22.990945 <6>[ 2.396273] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10694 01:00:23.000515 <6>[ 2.405566] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10695 01:00:23.010185 <6>[ 2.415726] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10696 01:00:23.020303 <6>[ 2.427331] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10697 01:00:23.027589 <6>[ 2.437208] Trying to probe devices needed for running init ...
10698 01:00:23.047934 <6>[ 2.454823] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10699 01:00:23.075760 <6>[ 2.486192] hub 2-1:1.0: USB hub found
10700 01:00:23.079951 <6>[ 2.490654] hub 2-1:1.0: 3 ports detected
10701 01:00:23.087627 <6>[ 2.497983] hub 2-1:1.0: USB hub found
10702 01:00:23.092075 <6>[ 2.502333] hub 2-1:1.0: 3 ports detected
10703 01:00:23.199766 <6>[ 2.606755] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10704 01:00:23.359292 <6>[ 2.768978] hub 1-1:1.0: USB hub found
10705 01:00:23.361865 <6>[ 2.773527] hub 1-1:1.0: 4 ports detected
10706 01:00:23.371199 <6>[ 2.781773] hub 1-1:1.0: USB hub found
10707 01:00:23.374626 <6>[ 2.786048] hub 1-1:1.0: 4 ports detected
10708 01:00:23.695863 <6>[ 3.102790] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10709 01:00:23.826595 <6>[ 3.236873] hub 1-1.1:1.0: USB hub found
10710 01:00:23.829552 <6>[ 3.241219] hub 1-1.1:1.0: 4 ports detected
10711 01:00:23.943528 <6>[ 3.350882] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10712 01:00:24.077490 <6>[ 3.486135] hub 1-1.4:1.0: USB hub found
10713 01:00:24.078813 <6>[ 3.490775] hub 1-1.4:1.0: 2 ports detected
10714 01:00:24.087903 <6>[ 3.498313] hub 1-1.4:1.0: USB hub found
10715 01:00:24.091928 <6>[ 3.502840] hub 1-1.4:1.0: 2 ports detected
10716 01:00:24.155561 <6>[ 3.562730] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10717 01:00:24.387565 <6>[ 3.794763] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10718 01:00:24.580098 <6>[ 3.986762] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10720 01:04:23.850983 end: 2.2.5.1 login-action (duration 00:04:04) [common]
10722 01:04:23.851194 auto-login-action failed: 1 of 1 attempts. 'login-action timed out after 244 seconds'
10724 01:04:23.851355 end: 2.2.5 auto-login-action (duration 00:04:04) [common]
10726 01:04:23.851555 depthcharge-retry failed: 1 of 1 attempts. 'login-action timed out after 244 seconds'
10728 01:04:23.851788 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10731 01:04:23.852099 end: 2 depthcharge-action (duration 00:05:00) [common]
10733 01:04:23.852335 Cleaning after the job
10734 01:04:23.852429 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/ramdisk
10735 01:04:23.854960 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/kernel
10736 01:04:23.867461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/dtb
10737 01:04:23.867633 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/nfsrootfs
10738 01:04:23.924078 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571106/tftp-deploy-jxn96ay5/modules
10739 01:04:23.931449 start: 4.1 power-off (timeout 00:00:30) [common]
10740 01:04:23.931631 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
10741 01:04:24.003459 >> Command sent successfully.
10742 01:04:24.007883 Returned 0 in 0 seconds
10743 01:04:24.108814 end: 4.1 power-off (duration 00:00:00) [common]
10745 01:04:24.110518 start: 4.2 read-feedback (timeout 00:10:00) [common]
10746 01:04:24.111928 Listened to connection for namespace 'common' for up to 1s
10747 01:04:25.111975 Finalising connection for namespace 'common'
10748 01:04:25.112664 Disconnecting from shell: Finalise
10749 01:04:25.213689 end: 4.2 read-feedback (duration 00:00:01) [common]
10750 01:04:25.214323 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571106
10751 01:04:25.567652 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571106
10752 01:04:25.568230 JobError: Your job cannot terminate cleanly.