Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 36
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 00:58:33.183873 lava-dispatcher, installed at version: 2023.10
2 00:58:33.184091 start: 0 validate
3 00:58:33.184228 Start time: 2024-01-19 00:58:33.184215+00:00 (UTC)
4 00:58:33.184343 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:58:33.184476 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:58:33.453613 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:58:33.453789 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:58:33.719525 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:58:33.719698 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:58:33.977853 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:58:33.978035 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:58:34.244977 validate duration: 1.06
14 00:58:34.245251 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:58:34.245347 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:58:34.245438 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:58:34.245565 Not decompressing ramdisk as can be used compressed.
18 00:58:34.245649 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 00:58:34.245713 saving as /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/ramdisk/rootfs.cpio.gz
20 00:58:34.245777 total size: 84918747 (80 MB)
21 00:58:34.250800 progress 0 % (0 MB)
22 00:58:34.272782 progress 5 % (4 MB)
23 00:58:34.294727 progress 10 % (8 MB)
24 00:58:34.316612 progress 15 % (12 MB)
25 00:58:34.338477 progress 20 % (16 MB)
26 00:58:34.360556 progress 25 % (20 MB)
27 00:58:34.382795 progress 30 % (24 MB)
28 00:58:34.404830 progress 35 % (28 MB)
29 00:58:34.426790 progress 40 % (32 MB)
30 00:58:34.448786 progress 45 % (36 MB)
31 00:58:34.470672 progress 50 % (40 MB)
32 00:58:34.492841 progress 55 % (44 MB)
33 00:58:34.515028 progress 60 % (48 MB)
34 00:58:34.536992 progress 65 % (52 MB)
35 00:58:34.558854 progress 70 % (56 MB)
36 00:58:34.580659 progress 75 % (60 MB)
37 00:58:34.602722 progress 80 % (64 MB)
38 00:58:34.624737 progress 85 % (68 MB)
39 00:58:34.646583 progress 90 % (72 MB)
40 00:58:34.668267 progress 95 % (76 MB)
41 00:58:34.689795 progress 100 % (80 MB)
42 00:58:34.690004 80 MB downloaded in 0.44 s (182.31 MB/s)
43 00:58:34.690183 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:58:34.690428 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:58:34.690515 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:58:34.690598 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:58:34.690737 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:58:34.690811 saving as /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/kernel/Image
50 00:58:34.690871 total size: 51532288 (49 MB)
51 00:58:34.690932 No compression specified
52 00:58:34.692102 progress 0 % (0 MB)
53 00:58:34.705414 progress 5 % (2 MB)
54 00:58:34.718827 progress 10 % (4 MB)
55 00:58:34.732108 progress 15 % (7 MB)
56 00:58:34.745723 progress 20 % (9 MB)
57 00:58:34.759027 progress 25 % (12 MB)
58 00:58:34.772222 progress 30 % (14 MB)
59 00:58:34.785562 progress 35 % (17 MB)
60 00:58:34.798936 progress 40 % (19 MB)
61 00:58:34.812225 progress 45 % (22 MB)
62 00:58:34.825587 progress 50 % (24 MB)
63 00:58:34.838789 progress 55 % (27 MB)
64 00:58:34.852349 progress 60 % (29 MB)
65 00:58:34.865849 progress 65 % (31 MB)
66 00:58:34.879067 progress 70 % (34 MB)
67 00:58:34.892412 progress 75 % (36 MB)
68 00:58:34.905825 progress 80 % (39 MB)
69 00:58:34.919037 progress 85 % (41 MB)
70 00:58:34.932342 progress 90 % (44 MB)
71 00:58:34.945462 progress 95 % (46 MB)
72 00:58:34.958465 progress 100 % (49 MB)
73 00:58:34.958687 49 MB downloaded in 0.27 s (183.51 MB/s)
74 00:58:34.958840 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:58:34.959069 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:58:34.959156 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:58:34.959245 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:58:34.959423 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:58:34.959516 saving as /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/dtb/mt8192-asurada-spherion-r0.dtb
81 00:58:34.959578 total size: 47278 (0 MB)
82 00:58:34.959640 No compression specified
83 00:58:34.960788 progress 69 % (0 MB)
84 00:58:34.961061 progress 100 % (0 MB)
85 00:58:34.961219 0 MB downloaded in 0.00 s (27.53 MB/s)
86 00:58:34.961340 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:58:34.961558 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:58:34.961646 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:58:34.961732 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:58:34.961844 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:58:34.961914 saving as /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/modules/modules.tar
93 00:58:34.961974 total size: 8625444 (8 MB)
94 00:58:34.962035 Using unxz to decompress xz
95 00:58:34.966264 progress 0 % (0 MB)
96 00:58:34.987315 progress 5 % (0 MB)
97 00:58:35.010900 progress 10 % (0 MB)
98 00:58:35.034228 progress 15 % (1 MB)
99 00:58:35.057461 progress 20 % (1 MB)
100 00:58:35.081156 progress 25 % (2 MB)
101 00:58:35.106793 progress 30 % (2 MB)
102 00:58:35.133088 progress 35 % (2 MB)
103 00:58:35.156054 progress 40 % (3 MB)
104 00:58:35.180154 progress 45 % (3 MB)
105 00:58:35.205480 progress 50 % (4 MB)
106 00:58:35.230125 progress 55 % (4 MB)
107 00:58:35.255202 progress 60 % (4 MB)
108 00:58:35.282471 progress 65 % (5 MB)
109 00:58:35.307537 progress 70 % (5 MB)
110 00:58:35.330764 progress 75 % (6 MB)
111 00:58:35.357522 progress 80 % (6 MB)
112 00:58:35.383218 progress 85 % (7 MB)
113 00:58:35.408204 progress 90 % (7 MB)
114 00:58:35.439451 progress 95 % (7 MB)
115 00:58:35.466957 progress 100 % (8 MB)
116 00:58:35.471995 8 MB downloaded in 0.51 s (16.13 MB/s)
117 00:58:35.472242 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:58:35.472505 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:58:35.472600 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:58:35.472697 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:58:35.472777 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:58:35.472867 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:58:35.473094 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9
125 00:58:35.473232 makedir: /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin
126 00:58:35.473338 makedir: /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/tests
127 00:58:35.473472 makedir: /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/results
128 00:58:35.473590 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-add-keys
129 00:58:35.473738 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-add-sources
130 00:58:35.473871 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-background-process-start
131 00:58:35.474002 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-background-process-stop
132 00:58:35.474129 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-common-functions
133 00:58:35.474255 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-echo-ipv4
134 00:58:35.474383 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-install-packages
135 00:58:35.474513 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-installed-packages
136 00:58:35.474640 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-os-build
137 00:58:35.474766 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-probe-channel
138 00:58:35.474892 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-probe-ip
139 00:58:35.475017 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-target-ip
140 00:58:35.475143 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-target-mac
141 00:58:35.475268 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-target-storage
142 00:58:35.475453 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-case
143 00:58:35.475585 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-event
144 00:58:35.475712 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-feedback
145 00:58:35.475840 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-raise
146 00:58:35.475969 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-reference
147 00:58:35.476096 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-runner
148 00:58:35.476223 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-set
149 00:58:35.476353 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-test-shell
150 00:58:35.476484 Updating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-install-packages (oe)
151 00:58:35.476638 Updating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/bin/lava-installed-packages (oe)
152 00:58:35.476763 Creating /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/environment
153 00:58:35.476863 LAVA metadata
154 00:58:35.476936 - LAVA_JOB_ID=12571095
155 00:58:35.477001 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:58:35.477103 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:58:35.477169 skipped lava-vland-overlay
158 00:58:35.477242 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:58:35.477323 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:58:35.477388 skipped lava-multinode-overlay
161 00:58:35.477463 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:58:35.477547 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:58:35.477622 Loading test definitions
164 00:58:35.477711 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 00:58:35.477789 Using /lava-12571095 at stage 0
166 00:58:35.477885 Fetching tests from https://github.com/kernelci/kernelci-core
167 00:58:35.477978 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/0/tests/0_sleep'
168 00:58:36.098038 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/0/tests/0_sleep
169 00:58:36.099419 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 00:58:36.099847 uuid=12571095_1.5.2.3.1 testdef=None
171 00:58:36.100017 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 00:58:36.100284 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 00:58:36.100854 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 00:58:36.101082 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 00:58:36.101787 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 00:58:36.102022 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 00:58:36.102692 runner path: /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/0/tests/0_sleep test_uuid 12571095_1.5.2.3.1
181 00:58:36.102781 sleep_params='mem'
182 00:58:36.102927 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 00:58:36.103138 Creating lava-test-runner.conf files
185 00:58:36.103203 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571095/lava-overlay-kv1f6pj9/lava-12571095/0 for stage 0
186 00:58:36.103296 - 0_sleep
187 00:58:36.103440 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 00:58:36.103531 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 00:58:36.235834 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 00:58:36.235984 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 00:58:36.236076 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 00:58:36.236175 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 00:58:36.236266 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 00:58:38.684969 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 00:58:38.685360 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 00:58:38.685475 extracting modules file /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571095/extract-overlay-ramdisk-yk7axmxj/ramdisk
197 00:58:38.913445 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 00:58:38.913621 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 00:58:38.913720 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571095/compress-overlay-jcz_9s5_/overlay-1.5.2.4.tar.gz to ramdisk
200 00:58:38.913796 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571095/compress-overlay-jcz_9s5_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571095/extract-overlay-ramdisk-yk7axmxj/ramdisk
201 00:58:39.013200 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 00:58:39.013368 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 00:58:39.013460 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 00:58:39.013550 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 00:58:39.013632 Building ramdisk /var/lib/lava/dispatcher/tmp/12571095/extract-overlay-ramdisk-yk7axmxj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571095/extract-overlay-ramdisk-yk7axmxj/ramdisk
206 00:58:40.572144 >> 563673 blocks
207 00:58:50.096892 rename /var/lib/lava/dispatcher/tmp/12571095/extract-overlay-ramdisk-yk7axmxj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/ramdisk/ramdisk.cpio.gz
208 00:58:50.097461 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 00:58:50.097639 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 00:58:50.097782 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 00:58:50.097937 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/kernel/Image'
212 00:59:02.724790 Returned 0 in 12 seconds
213 00:59:02.825883 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/kernel/image.itb
214 00:59:04.222468 output: FIT description: Kernel Image image with one or more FDT blobs
215 00:59:04.222846 output: Created: Fri Jan 19 00:59:03 2024
216 00:59:04.222920 output: Image 0 (kernel-1)
217 00:59:04.222984 output: Description:
218 00:59:04.223044 output: Created: Fri Jan 19 00:59:03 2024
219 00:59:04.223101 output: Type: Kernel Image
220 00:59:04.223160 output: Compression: lzma compressed
221 00:59:04.223216 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
222 00:59:04.223272 output: Architecture: AArch64
223 00:59:04.223325 output: OS: Linux
224 00:59:04.223410 output: Load Address: 0x00000000
225 00:59:04.223496 output: Entry Point: 0x00000000
226 00:59:04.223552 output: Hash algo: crc32
227 00:59:04.223609 output: Hash value: a52aa383
228 00:59:04.223666 output: Image 1 (fdt-1)
229 00:59:04.223721 output: Description: mt8192-asurada-spherion-r0
230 00:59:04.223774 output: Created: Fri Jan 19 00:59:03 2024
231 00:59:04.223844 output: Type: Flat Device Tree
232 00:59:04.223911 output: Compression: uncompressed
233 00:59:04.223963 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 00:59:04.224014 output: Architecture: AArch64
235 00:59:04.224065 output: Hash algo: crc32
236 00:59:04.224116 output: Hash value: cc4352de
237 00:59:04.224167 output: Image 2 (ramdisk-1)
238 00:59:04.224218 output: Description: unavailable
239 00:59:04.224269 output: Created: Fri Jan 19 00:59:03 2024
240 00:59:04.224320 output: Type: RAMDisk Image
241 00:59:04.224371 output: Compression: Unknown Compression
242 00:59:04.224422 output: Data Size: 98341459 Bytes = 96036.58 KiB = 93.79 MiB
243 00:59:04.224474 output: Architecture: AArch64
244 00:59:04.224525 output: OS: Linux
245 00:59:04.224576 output: Load Address: unavailable
246 00:59:04.224627 output: Entry Point: unavailable
247 00:59:04.224678 output: Hash algo: crc32
248 00:59:04.224728 output: Hash value: 3d0e4582
249 00:59:04.224779 output: Default Configuration: 'conf-1'
250 00:59:04.224830 output: Configuration 0 (conf-1)
251 00:59:04.224881 output: Description: mt8192-asurada-spherion-r0
252 00:59:04.224932 output: Kernel: kernel-1
253 00:59:04.224983 output: Init Ramdisk: ramdisk-1
254 00:59:04.225033 output: FDT: fdt-1
255 00:59:04.225084 output: Loadables: kernel-1
256 00:59:04.225135 output:
257 00:59:04.225332 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 00:59:04.225428 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 00:59:04.225530 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 00:59:04.225626 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:30) [common]
261 00:59:04.225708 No LXC device requested
262 00:59:04.225786 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 00:59:04.225868 start: 1.7 deploy-device-env (timeout 00:09:30) [common]
264 00:59:04.225944 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 00:59:04.226012 Checking files for TFTP limit of 4294967296 bytes.
266 00:59:04.226500 end: 1 tftp-deploy (duration 00:00:30) [common]
267 00:59:04.226602 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 00:59:04.226693 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 00:59:04.226813 substitutions:
270 00:59:04.226880 - {DTB}: 12571095/tftp-deploy-b12l71ur/dtb/mt8192-asurada-spherion-r0.dtb
271 00:59:04.226942 - {INITRD}: 12571095/tftp-deploy-b12l71ur/ramdisk/ramdisk.cpio.gz
272 00:59:04.226999 - {KERNEL}: 12571095/tftp-deploy-b12l71ur/kernel/Image
273 00:59:04.227055 - {LAVA_MAC}: None
274 00:59:04.227110 - {PRESEED_CONFIG}: None
275 00:59:04.227164 - {PRESEED_LOCAL}: None
276 00:59:04.227217 - {RAMDISK}: 12571095/tftp-deploy-b12l71ur/ramdisk/ramdisk.cpio.gz
277 00:59:04.227270 - {ROOT_PART}: None
278 00:59:04.227323 - {ROOT}: None
279 00:59:04.227398 - {SERVER_IP}: 192.168.201.1
280 00:59:04.227465 - {TEE}: None
281 00:59:04.227517 Parsed boot commands:
282 00:59:04.227571 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 00:59:04.227750 Parsed boot commands: tftpboot 192.168.201.1 12571095/tftp-deploy-b12l71ur/kernel/image.itb 12571095/tftp-deploy-b12l71ur/kernel/cmdline
284 00:59:04.227837 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 00:59:04.227918 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 00:59:04.228010 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 00:59:04.228098 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 00:59:04.228165 Not connected, no need to disconnect.
289 00:59:04.228236 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 00:59:04.228312 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 00:59:04.228375 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
292 00:59:04.232767 Setting prompt string to ['lava-test: # ']
293 00:59:04.233125 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 00:59:04.233234 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 00:59:04.233329 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 00:59:04.233461 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 00:59:04.233694 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
298 00:59:09.384231 >> Command sent successfully.
299 00:59:09.395039 Returned 0 in 5 seconds
300 00:59:09.496428 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 00:59:09.497786 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 00:59:09.498300 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 00:59:09.498758 Setting prompt string to 'Starting depthcharge on Spherion...'
305 00:59:09.499121 Changing prompt to 'Starting depthcharge on Spherion...'
306 00:59:09.499528 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 00:59:09.500757 [Enter `^Ec?' for help]
308 00:59:09.658947
309 00:59:09.659650
310 00:59:09.660069 F0: 102B 0000
311 00:59:09.660449
312 00:59:09.660765 F3: 1001 0000 [0200]
313 00:59:09.661064
314 00:59:09.662045 F3: 1001 0000
315 00:59:09.662470
316 00:59:09.662800 F7: 102D 0000
317 00:59:09.663113
318 00:59:09.665748 F1: 0000 0000
319 00:59:09.666274
320 00:59:09.666623 V0: 0000 0000 [0001]
321 00:59:09.666949
322 00:59:09.669180 00: 0007 8000
323 00:59:09.669722
324 00:59:09.670058 01: 0000 0000
325 00:59:09.670385
326 00:59:09.670691 BP: 0C00 0209 [0000]
327 00:59:09.672128
328 00:59:09.672553 G0: 1182 0000
329 00:59:09.672890
330 00:59:09.673205 EC: 0000 0021 [4000]
331 00:59:09.673507
332 00:59:09.675485 S7: 0000 0000 [0000]
333 00:59:09.675908
334 00:59:09.679403 CC: 0000 0000 [0001]
335 00:59:09.679846
336 00:59:09.680187 T0: 0000 0040 [010F]
337 00:59:09.680503
338 00:59:09.680873 Jump to BL
339 00:59:09.681178
340 00:59:09.706200
341 00:59:09.706944
342 00:59:09.707419
343 00:59:09.713218 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 00:59:09.718135 ARM64: Exception handlers installed.
345 00:59:09.720822 ARM64: Testing exception
346 00:59:09.724027 ARM64: Done test exception
347 00:59:09.730643 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 00:59:09.741049 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 00:59:09.747778 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 00:59:09.758094 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 00:59:09.764434 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 00:59:09.771094 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 00:59:09.782343 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 00:59:09.789024 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 00:59:09.808540 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 00:59:09.812021 WDT: Last reset was cold boot
357 00:59:09.815656 SPI1(PAD0) initialized at 2873684 Hz
358 00:59:09.818371 SPI5(PAD0) initialized at 992727 Hz
359 00:59:09.822230 VBOOT: Loading verstage.
360 00:59:09.828453 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 00:59:09.831767 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 00:59:09.835614 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 00:59:09.838146 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 00:59:09.846018 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 00:59:09.852683 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 00:59:09.863615 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 00:59:09.864142
368 00:59:09.864478
369 00:59:09.873430 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 00:59:09.876813 ARM64: Exception handlers installed.
371 00:59:09.880120 ARM64: Testing exception
372 00:59:09.880723 ARM64: Done test exception
373 00:59:09.887216 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 00:59:09.890385 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 00:59:09.904416 Probing TPM: . done!
376 00:59:09.904850 TPM ready after 0 ms
377 00:59:09.911715 Connected to device vid:did:rid of 1ae0:0028:00
378 00:59:09.918410 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 00:59:09.976839 Initialized TPM device CR50 revision 0
380 00:59:09.988213 tlcl_send_startup: Startup return code is 0
381 00:59:09.988378 TPM: setup succeeded
382 00:59:09.999417 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 00:59:10.008793 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 00:59:10.020420 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 00:59:10.029160 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 00:59:10.033111 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 00:59:10.040235 in-header: 03 07 00 00 08 00 00 00
388 00:59:10.043266 in-data: aa e4 47 04 13 02 00 00
389 00:59:10.046821 Chrome EC: UHEPI supported
390 00:59:10.054238 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 00:59:10.057905 in-header: 03 95 00 00 08 00 00 00
392 00:59:10.061643 in-data: 18 20 20 08 00 00 00 00
393 00:59:10.061814 Phase 1
394 00:59:10.065598 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 00:59:10.072524 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 00:59:10.076471 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 00:59:10.079897 Recovery requested (1009000e)
398 00:59:10.088764 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 00:59:10.095219 tlcl_extend: response is 0
400 00:59:10.103421 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 00:59:10.109069 tlcl_extend: response is 0
402 00:59:10.116664 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 00:59:10.136149 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 00:59:10.143355 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 00:59:10.143948
406 00:59:10.144293
407 00:59:10.153042 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 00:59:10.156014 ARM64: Exception handlers installed.
409 00:59:10.160125 ARM64: Testing exception
410 00:59:10.160651 ARM64: Done test exception
411 00:59:10.182246 pmic_efuse_setting: Set efuses in 11 msecs
412 00:59:10.185361 pmwrap_interface_init: Select PMIF_VLD_RDY
413 00:59:10.191328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 00:59:10.195209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 00:59:10.201736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 00:59:10.205624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 00:59:10.209008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 00:59:10.215887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 00:59:10.219457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 00:59:10.223317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 00:59:10.231082 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 00:59:10.235263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 00:59:10.238057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 00:59:10.242521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 00:59:10.246192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 00:59:10.253512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 00:59:10.261118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 00:59:10.264312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 00:59:10.271632 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 00:59:10.275775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 00:59:10.282570 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 00:59:10.289664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 00:59:10.293844 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 00:59:10.297368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 00:59:10.305025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 00:59:10.308581 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 00:59:10.315892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 00:59:10.319552 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 00:59:10.326413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 00:59:10.329863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 00:59:10.333461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 00:59:10.341163 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 00:59:10.345040 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 00:59:10.348789 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 00:59:10.356082 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 00:59:10.360221 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 00:59:10.363989 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 00:59:10.371009 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 00:59:10.375328 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 00:59:10.382245 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 00:59:10.385882 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 00:59:10.389475 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 00:59:10.393561 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 00:59:10.397262 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 00:59:10.403837 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 00:59:10.407739 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 00:59:10.411093 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 00:59:10.415347 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 00:59:10.418192 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 00:59:10.425312 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 00:59:10.429392 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 00:59:10.433027 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 00:59:10.436991 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 00:59:10.444701 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 00:59:10.451808 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 00:59:10.459230 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 00:59:10.466010 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 00:59:10.473994 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 00:59:10.477723 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 00:59:10.481441 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 00:59:10.487990 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 00:59:10.495685 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
473 00:59:10.499107 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 00:59:10.506861 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
475 00:59:10.510224 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 00:59:10.518879 [RTC]rtc_get_frequency_meter,154: input=15, output=853
477 00:59:10.528941 [RTC]rtc_get_frequency_meter,154: input=7, output=723
478 00:59:10.538541 [RTC]rtc_get_frequency_meter,154: input=11, output=789
479 00:59:10.547909 [RTC]rtc_get_frequency_meter,154: input=13, output=819
480 00:59:10.557035 [RTC]rtc_get_frequency_meter,154: input=12, output=805
481 00:59:10.566516 [RTC]rtc_get_frequency_meter,154: input=11, output=788
482 00:59:10.576831 [RTC]rtc_get_frequency_meter,154: input=12, output=804
483 00:59:10.580637 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
484 00:59:10.583968 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
485 00:59:10.587406 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 00:59:10.594609 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 00:59:10.598408 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 00:59:10.602345 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 00:59:10.606215 ADC[4]: Raw value=903694 ID=7
490 00:59:10.606423 ADC[3]: Raw value=213916 ID=1
491 00:59:10.609779 RAM Code: 0x71
492 00:59:10.613808 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 00:59:10.617255 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 00:59:10.628284 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 00:59:10.631932 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 00:59:10.635032 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 00:59:10.639411 in-header: 03 07 00 00 08 00 00 00
498 00:59:10.643549 in-data: aa e4 47 04 13 02 00 00
499 00:59:10.646531 Chrome EC: UHEPI supported
500 00:59:10.654021 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 00:59:10.657738 in-header: 03 95 00 00 08 00 00 00
502 00:59:10.661826 in-data: 18 20 20 08 00 00 00 00
503 00:59:10.664916 MRC: failed to locate region type 0.
504 00:59:10.669468 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 00:59:10.673104 DRAM-K: Running full calibration
506 00:59:10.680279 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 00:59:10.680716 header.status = 0x0
508 00:59:10.683188 header.version = 0x6 (expected: 0x6)
509 00:59:10.687213 header.size = 0xd00 (expected: 0xd00)
510 00:59:10.690780 header.flags = 0x0
511 00:59:10.694389 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 00:59:10.714275 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
513 00:59:10.721449 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 00:59:10.725457 dram_init: ddr_geometry: 2
515 00:59:10.726174 [EMI] MDL number = 2
516 00:59:10.728410 [EMI] Get MDL freq = 0
517 00:59:10.728841 dram_init: ddr_type: 0
518 00:59:10.732481 is_discrete_lpddr4: 1
519 00:59:10.735935 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 00:59:10.736359
521 00:59:10.736695
522 00:59:10.737008 [Bian_co] ETT version 0.0.0.1
523 00:59:10.743225 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 00:59:10.743685
525 00:59:10.747161 dramc_set_vcore_voltage set vcore to 650000
526 00:59:10.747647 Read voltage for 800, 4
527 00:59:10.751105 Vio18 = 0
528 00:59:10.751565 Vcore = 650000
529 00:59:10.751906 Vdram = 0
530 00:59:10.753652 Vddq = 0
531 00:59:10.754080 Vmddr = 0
532 00:59:10.757000 dram_init: config_dvfs: 1
533 00:59:10.760206 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 00:59:10.767526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 00:59:10.770928 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 00:59:10.774366 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 00:59:10.777951 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 00:59:10.781836 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 00:59:10.785311 MEM_TYPE=3, freq_sel=18
540 00:59:10.785883 sv_algorithm_assistance_LP4_1600
541 00:59:10.792663 ============ PULL DRAM RESETB DOWN ============
542 00:59:10.796154 ========== PULL DRAM RESETB DOWN end =========
543 00:59:10.799274 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 00:59:10.802302 ===================================
545 00:59:10.805656 LPDDR4 DRAM CONFIGURATION
546 00:59:10.809091 ===================================
547 00:59:10.809522 EX_ROW_EN[0] = 0x0
548 00:59:10.813380 EX_ROW_EN[1] = 0x0
549 00:59:10.813904 LP4Y_EN = 0x0
550 00:59:10.815845 WORK_FSP = 0x0
551 00:59:10.819148 WL = 0x2
552 00:59:10.819611 RL = 0x2
553 00:59:10.822527 BL = 0x2
554 00:59:10.822956 RPST = 0x0
555 00:59:10.825477 RD_PRE = 0x0
556 00:59:10.825909 WR_PRE = 0x1
557 00:59:10.828826 WR_PST = 0x0
558 00:59:10.829255 DBI_WR = 0x0
559 00:59:10.832397 DBI_RD = 0x0
560 00:59:10.832828 OTF = 0x1
561 00:59:10.836862 ===================================
562 00:59:10.839188 ===================================
563 00:59:10.842124 ANA top config
564 00:59:10.845472 ===================================
565 00:59:10.845917 DLL_ASYNC_EN = 0
566 00:59:10.848942 ALL_SLAVE_EN = 1
567 00:59:10.852188 NEW_RANK_MODE = 1
568 00:59:10.855399 DLL_IDLE_MODE = 1
569 00:59:10.855848 LP45_APHY_COMB_EN = 1
570 00:59:10.858771 TX_ODT_DIS = 1
571 00:59:10.862428 NEW_8X_MODE = 1
572 00:59:10.865399 ===================================
573 00:59:10.868990 ===================================
574 00:59:10.872072 data_rate = 1600
575 00:59:10.875555 CKR = 1
576 00:59:10.878785 DQ_P2S_RATIO = 8
577 00:59:10.881927 ===================================
578 00:59:10.882356 CA_P2S_RATIO = 8
579 00:59:10.885778 DQ_CA_OPEN = 0
580 00:59:10.889354 DQ_SEMI_OPEN = 0
581 00:59:10.892699 CA_SEMI_OPEN = 0
582 00:59:10.896200 CA_FULL_RATE = 0
583 00:59:10.896625 DQ_CKDIV4_EN = 1
584 00:59:10.899720 CA_CKDIV4_EN = 1
585 00:59:10.902900 CA_PREDIV_EN = 0
586 00:59:10.906217 PH8_DLY = 0
587 00:59:10.910069 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 00:59:10.910622 DQ_AAMCK_DIV = 4
589 00:59:10.913129 CA_AAMCK_DIV = 4
590 00:59:10.916238 CA_ADMCK_DIV = 4
591 00:59:10.919940 DQ_TRACK_CA_EN = 0
592 00:59:10.923064 CA_PICK = 800
593 00:59:10.926150 CA_MCKIO = 800
594 00:59:10.930196 MCKIO_SEMI = 0
595 00:59:10.930626 PLL_FREQ = 3068
596 00:59:10.933837 DQ_UI_PI_RATIO = 32
597 00:59:10.936902 CA_UI_PI_RATIO = 0
598 00:59:10.941068 ===================================
599 00:59:10.944183 ===================================
600 00:59:10.944614 memory_type:LPDDR4
601 00:59:10.948625 GP_NUM : 10
602 00:59:10.952062 SRAM_EN : 1
603 00:59:10.952492 MD32_EN : 0
604 00:59:10.955827 ===================================
605 00:59:10.958868 [ANA_INIT] >>>>>>>>>>>>>>
606 00:59:10.959296 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 00:59:10.962624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 00:59:10.966490 ===================================
609 00:59:10.969463 data_rate = 1600,PCW = 0X7600
610 00:59:10.972497 ===================================
611 00:59:10.976381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 00:59:10.982928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 00:59:10.985925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 00:59:10.993095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 00:59:10.996773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 00:59:10.999453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 00:59:10.999892 [ANA_INIT] flow start
618 00:59:11.002866 [ANA_INIT] PLL >>>>>>>>
619 00:59:11.006440 [ANA_INIT] PLL <<<<<<<<
620 00:59:11.009264 [ANA_INIT] MIDPI >>>>>>>>
621 00:59:11.009789 [ANA_INIT] MIDPI <<<<<<<<
622 00:59:11.012783 [ANA_INIT] DLL >>>>>>>>
623 00:59:11.015883 [ANA_INIT] flow end
624 00:59:11.019430 ============ LP4 DIFF to SE enter ============
625 00:59:11.022648 ============ LP4 DIFF to SE exit ============
626 00:59:11.026035 [ANA_INIT] <<<<<<<<<<<<<
627 00:59:11.029756 [Flow] Enable top DCM control >>>>>
628 00:59:11.032284 [Flow] Enable top DCM control <<<<<
629 00:59:11.035873 Enable DLL master slave shuffle
630 00:59:11.039174 ==============================================================
631 00:59:11.042489 Gating Mode config
632 00:59:11.045865 ==============================================================
633 00:59:11.049236 Config description:
634 00:59:11.059044 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 00:59:11.065476 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 00:59:11.069186 SELPH_MODE 0: By rank 1: By Phase
637 00:59:11.075394 ==============================================================
638 00:59:11.078887 GAT_TRACK_EN = 1
639 00:59:11.082137 RX_GATING_MODE = 2
640 00:59:11.085064 RX_GATING_TRACK_MODE = 2
641 00:59:11.088376 SELPH_MODE = 1
642 00:59:11.091641 PICG_EARLY_EN = 1
643 00:59:11.091762 VALID_LAT_VALUE = 1
644 00:59:11.098439 ==============================================================
645 00:59:11.102281 Enter into Gating configuration >>>>
646 00:59:11.104928 Exit from Gating configuration <<<<
647 00:59:11.108362 Enter into DVFS_PRE_config >>>>>
648 00:59:11.118631 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 00:59:11.122075 Exit from DVFS_PRE_config <<<<<
650 00:59:11.125133 Enter into PICG configuration >>>>
651 00:59:11.128572 Exit from PICG configuration <<<<
652 00:59:11.131737 [RX_INPUT] configuration >>>>>
653 00:59:11.135062 [RX_INPUT] configuration <<<<<
654 00:59:11.141447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 00:59:11.145453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 00:59:11.151679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 00:59:11.158223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 00:59:11.165545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 00:59:11.171565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 00:59:11.175232 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 00:59:11.178757 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 00:59:11.181585 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 00:59:11.188492 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 00:59:11.191789 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 00:59:11.194903 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 00:59:11.198346 ===================================
667 00:59:11.201401 LPDDR4 DRAM CONFIGURATION
668 00:59:11.205147 ===================================
669 00:59:11.205732 EX_ROW_EN[0] = 0x0
670 00:59:11.208071 EX_ROW_EN[1] = 0x0
671 00:59:11.211336 LP4Y_EN = 0x0
672 00:59:11.211843 WORK_FSP = 0x0
673 00:59:11.215208 WL = 0x2
674 00:59:11.215800 RL = 0x2
675 00:59:11.217999 BL = 0x2
676 00:59:11.218507 RPST = 0x0
677 00:59:11.221671 RD_PRE = 0x0
678 00:59:11.222100 WR_PRE = 0x1
679 00:59:11.225819 WR_PST = 0x0
680 00:59:11.226386 DBI_WR = 0x0
681 00:59:11.228645 DBI_RD = 0x0
682 00:59:11.229136 OTF = 0x1
683 00:59:11.231542 ===================================
684 00:59:11.235274 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 00:59:11.242009 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 00:59:11.245057 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 00:59:11.247813 ===================================
688 00:59:11.251694 LPDDR4 DRAM CONFIGURATION
689 00:59:11.255144 ===================================
690 00:59:11.255608 EX_ROW_EN[0] = 0x10
691 00:59:11.258067 EX_ROW_EN[1] = 0x0
692 00:59:11.258606 LP4Y_EN = 0x0
693 00:59:11.261757 WORK_FSP = 0x0
694 00:59:11.262283 WL = 0x2
695 00:59:11.265073 RL = 0x2
696 00:59:11.267904 BL = 0x2
697 00:59:11.268332 RPST = 0x0
698 00:59:11.271417 RD_PRE = 0x0
699 00:59:11.271951 WR_PRE = 0x1
700 00:59:11.274574 WR_PST = 0x0
701 00:59:11.274998 DBI_WR = 0x0
702 00:59:11.277800 DBI_RD = 0x0
703 00:59:11.278225 OTF = 0x1
704 00:59:11.281046 ===================================
705 00:59:11.287548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 00:59:11.291747 nWR fixed to 40
707 00:59:11.295284 [ModeRegInit_LP4] CH0 RK0
708 00:59:11.295861 [ModeRegInit_LP4] CH0 RK1
709 00:59:11.299283 [ModeRegInit_LP4] CH1 RK0
710 00:59:11.302337 [ModeRegInit_LP4] CH1 RK1
711 00:59:11.302899 match AC timing 13
712 00:59:11.308303 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 00:59:11.311615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 00:59:11.315023 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 00:59:11.321764 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 00:59:11.325132 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 00:59:11.325655 [EMI DOE] emi_dcm 0
718 00:59:11.331843 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 00:59:11.332364 ==
720 00:59:11.335344 Dram Type= 6, Freq= 0, CH_0, rank 0
721 00:59:11.338232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 00:59:11.338713 ==
723 00:59:11.344703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 00:59:11.351716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 00:59:11.359434 [CA 0] Center 38 (7~69) winsize 63
726 00:59:11.363146 [CA 1] Center 37 (7~68) winsize 62
727 00:59:11.366181 [CA 2] Center 34 (4~65) winsize 62
728 00:59:11.369652 [CA 3] Center 35 (4~66) winsize 63
729 00:59:11.372662 [CA 4] Center 34 (3~65) winsize 63
730 00:59:11.376144 [CA 5] Center 33 (3~64) winsize 62
731 00:59:11.376631
732 00:59:11.379212 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 00:59:11.379737
734 00:59:11.382877 [CATrainingPosCal] consider 1 rank data
735 00:59:11.385547 u2DelayCellTimex100 = 270/100 ps
736 00:59:11.388853 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
737 00:59:11.396512 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
738 00:59:11.399315 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 00:59:11.402817 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
740 00:59:11.405976 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
741 00:59:11.409417 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 00:59:11.409953
743 00:59:11.412283 CA PerBit enable=1, Macro0, CA PI delay=33
744 00:59:11.412727
745 00:59:11.415966 [CBTSetCACLKResult] CA Dly = 33
746 00:59:11.416508 CS Dly: 5 (0~36)
747 00:59:11.419015 ==
748 00:59:11.422179 Dram Type= 6, Freq= 0, CH_0, rank 1
749 00:59:11.426051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 00:59:11.426611 ==
751 00:59:11.428836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 00:59:11.435737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 00:59:11.445736 [CA 0] Center 37 (7~68) winsize 62
754 00:59:11.449015 [CA 1] Center 37 (7~68) winsize 62
755 00:59:11.452264 [CA 2] Center 35 (4~66) winsize 63
756 00:59:11.455778 [CA 3] Center 34 (4~65) winsize 62
757 00:59:11.459294 [CA 4] Center 34 (3~65) winsize 63
758 00:59:11.462605 [CA 5] Center 33 (3~64) winsize 62
759 00:59:11.463149
760 00:59:11.465658 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 00:59:11.466104
762 00:59:11.469278 [CATrainingPosCal] consider 2 rank data
763 00:59:11.473017 u2DelayCellTimex100 = 270/100 ps
764 00:59:11.475630 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 00:59:11.479444 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 00:59:11.485672 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 00:59:11.488933 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 00:59:11.491925 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
769 00:59:11.495767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 00:59:11.496302
771 00:59:11.499055 CA PerBit enable=1, Macro0, CA PI delay=33
772 00:59:11.499548
773 00:59:11.502215 [CBTSetCACLKResult] CA Dly = 33
774 00:59:11.502657 CS Dly: 6 (0~38)
775 00:59:11.503105
776 00:59:11.505684 ----->DramcWriteLeveling(PI) begin...
777 00:59:11.509486 ==
778 00:59:11.510024 Dram Type= 6, Freq= 0, CH_0, rank 0
779 00:59:11.516553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 00:59:11.516997 ==
781 00:59:11.517448 Write leveling (Byte 0): 32 => 32
782 00:59:11.519942 Write leveling (Byte 1): 29 => 29
783 00:59:11.523978 DramcWriteLeveling(PI) end<-----
784 00:59:11.524505
785 00:59:11.524955 ==
786 00:59:11.527478 Dram Type= 6, Freq= 0, CH_0, rank 0
787 00:59:11.530753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 00:59:11.531279 ==
789 00:59:11.534328 [Gating] SW mode calibration
790 00:59:11.541251 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 00:59:11.548503 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 00:59:11.551556 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 00:59:11.554661 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
794 00:59:11.562159 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 00:59:11.564810 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:59:11.567785 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 00:59:11.574848 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 00:59:11.578319 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:59:11.581321 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:59:11.588031 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:59:11.590857 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:59:11.594621 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:59:11.601312 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:59:11.604232 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:59:11.607711 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 00:59:11.614755 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 00:59:11.617778 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 00:59:11.621103 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 00:59:11.627835 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 00:59:11.631447 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 00:59:11.634204 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 00:59:11.640924 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 00:59:11.644227 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 00:59:11.647510 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 00:59:11.651032 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:59:11.657149 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:59:11.660560 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:59:11.664265 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
819 00:59:11.670827 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
820 00:59:11.673832 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 00:59:11.677237 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 00:59:11.683546 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 00:59:11.687855 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 00:59:11.690228 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 00:59:11.696600 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
826 00:59:11.699962 0 10 8 | B1->B0 | 3232 2525 | 1 0 | (1 0) (0 0)
827 00:59:11.703341 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
828 00:59:11.709970 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 00:59:11.713503 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 00:59:11.716848 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 00:59:11.723830 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 00:59:11.727295 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 00:59:11.730364 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
834 00:59:11.737319 0 11 8 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (0 0)
835 00:59:11.741081 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
836 00:59:11.743967 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 00:59:11.750326 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 00:59:11.753437 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 00:59:11.757357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 00:59:11.764155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 00:59:11.766716 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 00:59:11.770150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 00:59:11.776586 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
844 00:59:11.780253 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:59:11.783542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 00:59:11.790266 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 00:59:11.793882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 00:59:11.796738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 00:59:11.800330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 00:59:11.806964 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 00:59:11.810309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 00:59:11.813883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 00:59:11.820399 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 00:59:11.823460 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 00:59:11.827149 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 00:59:11.833327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 00:59:11.836593 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 00:59:11.839899 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 00:59:11.843094 Total UI for P1: 0, mck2ui 16
860 00:59:11.846756 best dqsien dly found for B0: ( 0, 14, 4)
861 00:59:11.852834 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 00:59:11.856237 Total UI for P1: 0, mck2ui 16
863 00:59:11.859597 best dqsien dly found for B1: ( 0, 14, 8)
864 00:59:11.863146 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
865 00:59:11.866499 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 00:59:11.867021
867 00:59:11.869307 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
868 00:59:11.873023 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 00:59:11.876315 [Gating] SW calibration Done
870 00:59:11.876746 ==
871 00:59:11.879403 Dram Type= 6, Freq= 0, CH_0, rank 0
872 00:59:11.883281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 00:59:11.883746 ==
874 00:59:11.887213 RX Vref Scan: 0
875 00:59:11.887688
876 00:59:11.888031 RX Vref 0 -> 0, step: 1
877 00:59:11.888350
878 00:59:11.890176 RX Delay -130 -> 252, step: 16
879 00:59:11.893597 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 00:59:11.900430 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 00:59:11.903799 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 00:59:11.906881 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 00:59:11.910331 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 00:59:11.913141 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 00:59:11.920111 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 00:59:11.923508 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
887 00:59:11.926937 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 00:59:11.930482 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
889 00:59:11.933792 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
890 00:59:11.940459 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 00:59:11.943743 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
892 00:59:11.946751 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 00:59:11.949973 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 00:59:11.953575 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 00:59:11.957158 ==
896 00:59:11.957683 Dram Type= 6, Freq= 0, CH_0, rank 0
897 00:59:11.963275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 00:59:11.963819 ==
899 00:59:11.964159 DQS Delay:
900 00:59:11.967409 DQS0 = 0, DQS1 = 0
901 00:59:11.967938 DQM Delay:
902 00:59:11.970266 DQM0 = 90, DQM1 = 75
903 00:59:11.970692 DQ Delay:
904 00:59:11.973892 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
905 00:59:11.976828 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
906 00:59:11.979841 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
907 00:59:11.983429 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
908 00:59:11.983954
909 00:59:11.984294
910 00:59:11.984604 ==
911 00:59:11.987012 Dram Type= 6, Freq= 0, CH_0, rank 0
912 00:59:11.990142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 00:59:11.990666 ==
914 00:59:11.991004
915 00:59:11.991319
916 00:59:11.993399 TX Vref Scan disable
917 00:59:11.996940 == TX Byte 0 ==
918 00:59:11.999819 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
919 00:59:12.003169 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
920 00:59:12.006679 == TX Byte 1 ==
921 00:59:12.009925 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
922 00:59:12.013126 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
923 00:59:12.013556 ==
924 00:59:12.016732 Dram Type= 6, Freq= 0, CH_0, rank 0
925 00:59:12.020153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 00:59:12.023213 ==
927 00:59:12.034898 TX Vref=22, minBit 1, minWin=27, winSum=440
928 00:59:12.038186 TX Vref=24, minBit 0, minWin=27, winSum=441
929 00:59:12.041082 TX Vref=26, minBit 3, minWin=27, winSum=450
930 00:59:12.044392 TX Vref=28, minBit 5, minWin=27, winSum=453
931 00:59:12.048209 TX Vref=30, minBit 1, minWin=27, winSum=450
932 00:59:12.054717 TX Vref=32, minBit 1, minWin=27, winSum=449
933 00:59:12.057811 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 28
934 00:59:12.058335
935 00:59:12.061154 Final TX Range 1 Vref 28
936 00:59:12.061678
937 00:59:12.062019 ==
938 00:59:12.064760 Dram Type= 6, Freq= 0, CH_0, rank 0
939 00:59:12.068192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 00:59:12.068721 ==
941 00:59:12.071820
942 00:59:12.072340
943 00:59:12.072676 TX Vref Scan disable
944 00:59:12.074864 == TX Byte 0 ==
945 00:59:12.078107 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
946 00:59:12.084411 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
947 00:59:12.084838 == TX Byte 1 ==
948 00:59:12.087817 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 00:59:12.094596 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 00:59:12.095024
951 00:59:12.095355 [DATLAT]
952 00:59:12.095725 Freq=800, CH0 RK0
953 00:59:12.096028
954 00:59:12.098055 DATLAT Default: 0xa
955 00:59:12.098480 0, 0xFFFF, sum = 0
956 00:59:12.101191 1, 0xFFFF, sum = 0
957 00:59:12.101627 2, 0xFFFF, sum = 0
958 00:59:12.105049 3, 0xFFFF, sum = 0
959 00:59:12.107921 4, 0xFFFF, sum = 0
960 00:59:12.108352 5, 0xFFFF, sum = 0
961 00:59:12.110936 6, 0xFFFF, sum = 0
962 00:59:12.111404 7, 0xFFFF, sum = 0
963 00:59:12.114609 8, 0xFFFF, sum = 0
964 00:59:12.115042 9, 0x0, sum = 1
965 00:59:12.117376 10, 0x0, sum = 2
966 00:59:12.117811 11, 0x0, sum = 3
967 00:59:12.118230 12, 0x0, sum = 4
968 00:59:12.120945 best_step = 10
969 00:59:12.121369
970 00:59:12.121704 ==
971 00:59:12.124239 Dram Type= 6, Freq= 0, CH_0, rank 0
972 00:59:12.128180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 00:59:12.128731 ==
974 00:59:12.130572 RX Vref Scan: 1
975 00:59:12.131076
976 00:59:12.134141 Set Vref Range= 32 -> 127
977 00:59:12.134649
978 00:59:12.134995 RX Vref 32 -> 127, step: 1
979 00:59:12.135316
980 00:59:12.137632 RX Delay -111 -> 252, step: 8
981 00:59:12.138056
982 00:59:12.140998 Set Vref, RX VrefLevel [Byte0]: 32
983 00:59:12.144224 [Byte1]: 32
984 00:59:12.147820
985 00:59:12.148336 Set Vref, RX VrefLevel [Byte0]: 33
986 00:59:12.151065 [Byte1]: 33
987 00:59:12.155317
988 00:59:12.155896 Set Vref, RX VrefLevel [Byte0]: 34
989 00:59:12.158470 [Byte1]: 34
990 00:59:12.162431
991 00:59:12.166296 Set Vref, RX VrefLevel [Byte0]: 35
992 00:59:12.169143 [Byte1]: 35
993 00:59:12.169662
994 00:59:12.172393 Set Vref, RX VrefLevel [Byte0]: 36
995 00:59:12.175995 [Byte1]: 36
996 00:59:12.176423
997 00:59:12.180030 Set Vref, RX VrefLevel [Byte0]: 37
998 00:59:12.183320 [Byte1]: 37
999 00:59:12.183770
1000 00:59:12.187190 Set Vref, RX VrefLevel [Byte0]: 38
1001 00:59:12.191017 [Byte1]: 38
1002 00:59:12.191772
1003 00:59:12.195219 Set Vref, RX VrefLevel [Byte0]: 39
1004 00:59:12.198323 [Byte1]: 39
1005 00:59:12.198745
1006 00:59:12.201921 Set Vref, RX VrefLevel [Byte0]: 40
1007 00:59:12.205411 [Byte1]: 40
1008 00:59:12.205833
1009 00:59:12.209830 Set Vref, RX VrefLevel [Byte0]: 41
1010 00:59:12.212783 [Byte1]: 41
1011 00:59:12.216159
1012 00:59:12.216587 Set Vref, RX VrefLevel [Byte0]: 42
1013 00:59:12.220030 [Byte1]: 42
1014 00:59:12.223863
1015 00:59:12.224285 Set Vref, RX VrefLevel [Byte0]: 43
1016 00:59:12.227700 [Byte1]: 43
1017 00:59:12.231807
1018 00:59:12.232231 Set Vref, RX VrefLevel [Byte0]: 44
1019 00:59:12.235290 [Byte1]: 44
1020 00:59:12.238900
1021 00:59:12.239318 Set Vref, RX VrefLevel [Byte0]: 45
1022 00:59:12.242990 [Byte1]: 45
1023 00:59:12.246810
1024 00:59:12.247328 Set Vref, RX VrefLevel [Byte0]: 46
1025 00:59:12.250057 [Byte1]: 46
1026 00:59:12.254350
1027 00:59:12.254764 Set Vref, RX VrefLevel [Byte0]: 47
1028 00:59:12.257900 [Byte1]: 47
1029 00:59:12.262072
1030 00:59:12.262603 Set Vref, RX VrefLevel [Byte0]: 48
1031 00:59:12.265290 [Byte1]: 48
1032 00:59:12.269491
1033 00:59:12.269918 Set Vref, RX VrefLevel [Byte0]: 49
1034 00:59:12.272864 [Byte1]: 49
1035 00:59:12.277564
1036 00:59:12.277981 Set Vref, RX VrefLevel [Byte0]: 50
1037 00:59:12.280655 [Byte1]: 50
1038 00:59:12.284824
1039 00:59:12.285239 Set Vref, RX VrefLevel [Byte0]: 51
1040 00:59:12.287933 [Byte1]: 51
1041 00:59:12.292464
1042 00:59:12.292688 Set Vref, RX VrefLevel [Byte0]: 52
1043 00:59:12.295794 [Byte1]: 52
1044 00:59:12.300067
1045 00:59:12.300247 Set Vref, RX VrefLevel [Byte0]: 53
1046 00:59:12.303384 [Byte1]: 53
1047 00:59:12.307672
1048 00:59:12.307802 Set Vref, RX VrefLevel [Byte0]: 54
1049 00:59:12.310938 [Byte1]: 54
1050 00:59:12.315354
1051 00:59:12.315480 Set Vref, RX VrefLevel [Byte0]: 55
1052 00:59:12.318387 [Byte1]: 55
1053 00:59:12.323059
1054 00:59:12.323151 Set Vref, RX VrefLevel [Byte0]: 56
1055 00:59:12.326164 [Byte1]: 56
1056 00:59:12.330647
1057 00:59:12.330806 Set Vref, RX VrefLevel [Byte0]: 57
1058 00:59:12.334450 [Byte1]: 57
1059 00:59:12.338740
1060 00:59:12.338903 Set Vref, RX VrefLevel [Byte0]: 58
1061 00:59:12.341562 [Byte1]: 58
1062 00:59:12.346554
1063 00:59:12.346709 Set Vref, RX VrefLevel [Byte0]: 59
1064 00:59:12.349425 [Byte1]: 59
1065 00:59:12.353555
1066 00:59:12.353713 Set Vref, RX VrefLevel [Byte0]: 60
1067 00:59:12.356934 [Byte1]: 60
1068 00:59:12.361446
1069 00:59:12.361603 Set Vref, RX VrefLevel [Byte0]: 61
1070 00:59:12.364305 [Byte1]: 61
1071 00:59:12.368866
1072 00:59:12.369035 Set Vref, RX VrefLevel [Byte0]: 62
1073 00:59:12.372450 [Byte1]: 62
1074 00:59:12.376354
1075 00:59:12.376492 Set Vref, RX VrefLevel [Byte0]: 63
1076 00:59:12.379565 [Byte1]: 63
1077 00:59:12.384058
1078 00:59:12.384253 Set Vref, RX VrefLevel [Byte0]: 64
1079 00:59:12.387545 [Byte1]: 64
1080 00:59:12.391755
1081 00:59:12.391975 Set Vref, RX VrefLevel [Byte0]: 65
1082 00:59:12.395339 [Byte1]: 65
1083 00:59:12.399926
1084 00:59:12.400181 Set Vref, RX VrefLevel [Byte0]: 66
1085 00:59:12.402902 [Byte1]: 66
1086 00:59:12.407453
1087 00:59:12.407777 Set Vref, RX VrefLevel [Byte0]: 67
1088 00:59:12.410251 [Byte1]: 67
1089 00:59:12.414958
1090 00:59:12.415249 Set Vref, RX VrefLevel [Byte0]: 68
1091 00:59:12.418447 [Byte1]: 68
1092 00:59:12.422468
1093 00:59:12.422973 Set Vref, RX VrefLevel [Byte0]: 69
1094 00:59:12.425895 [Byte1]: 69
1095 00:59:12.430227
1096 00:59:12.430657 Set Vref, RX VrefLevel [Byte0]: 70
1097 00:59:12.433398 [Byte1]: 70
1098 00:59:12.437729
1099 00:59:12.438143 Set Vref, RX VrefLevel [Byte0]: 71
1100 00:59:12.440961 [Byte1]: 71
1101 00:59:12.445736
1102 00:59:12.446243 Set Vref, RX VrefLevel [Byte0]: 72
1103 00:59:12.448946 [Byte1]: 72
1104 00:59:12.453038
1105 00:59:12.453456 Set Vref, RX VrefLevel [Byte0]: 73
1106 00:59:12.456384 [Byte1]: 73
1107 00:59:12.461272
1108 00:59:12.461787 Set Vref, RX VrefLevel [Byte0]: 74
1109 00:59:12.464120 [Byte1]: 74
1110 00:59:12.468586
1111 00:59:12.469001 Final RX Vref Byte 0 = 57 to rank0
1112 00:59:12.471560 Final RX Vref Byte 1 = 58 to rank0
1113 00:59:12.475237 Final RX Vref Byte 0 = 57 to rank1
1114 00:59:12.478566 Final RX Vref Byte 1 = 58 to rank1==
1115 00:59:12.481543 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 00:59:12.488380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 00:59:12.489009 ==
1118 00:59:12.489346 DQS Delay:
1119 00:59:12.489653 DQS0 = 0, DQS1 = 0
1120 00:59:12.491980 DQM Delay:
1121 00:59:12.492414 DQM0 = 88, DQM1 = 76
1122 00:59:12.494967 DQ Delay:
1123 00:59:12.498254 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1124 00:59:12.501494 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1125 00:59:12.504766 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1126 00:59:12.508599 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1127 00:59:12.509110
1128 00:59:12.509442
1129 00:59:12.514585 [DQSOSCAuto] RK0, (LSB)MR18= 0x302a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1130 00:59:12.518746 CH0 RK0: MR19=606, MR18=302A
1131 00:59:12.525554 CH0_RK0: MR19=0x606, MR18=0x302A, DQSOSC=397, MR23=63, INC=93, DEC=62
1132 00:59:12.526074
1133 00:59:12.528653 ----->DramcWriteLeveling(PI) begin...
1134 00:59:12.529173 ==
1135 00:59:12.531447 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 00:59:12.535112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 00:59:12.535566 ==
1138 00:59:12.538586 Write leveling (Byte 0): 29 => 29
1139 00:59:12.541654 Write leveling (Byte 1): 28 => 28
1140 00:59:12.545666 DramcWriteLeveling(PI) end<-----
1141 00:59:12.546191
1142 00:59:12.546523 ==
1143 00:59:12.548615 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 00:59:12.551455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 00:59:12.551971 ==
1146 00:59:12.555244 [Gating] SW mode calibration
1147 00:59:12.561514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 00:59:12.568239 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 00:59:12.571398 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 00:59:12.615451 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 00:59:12.616320 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 00:59:12.616678 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 00:59:12.616990 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 00:59:12.617378 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 00:59:12.617920 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:59:12.618257 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:59:12.618556 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:59:12.618845 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:59:12.619125 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:59:12.659919 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:59:12.660855 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:59:12.661250 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:59:12.661594 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:59:12.661926 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:59:12.662244 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:59:12.662625 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1167 00:59:12.662952 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 00:59:12.663263 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:59:12.663602 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 00:59:12.665026 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 00:59:12.667945 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:59:12.671559 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:59:12.678155 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:59:12.681494 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:59:12.684615 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1176 00:59:12.691608 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1177 00:59:12.694617 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 00:59:12.697734 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 00:59:12.704366 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:59:12.708291 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:59:12.711321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:59:12.717587 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1183 00:59:12.721002 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1184 00:59:12.724759 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1185 00:59:12.731328 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 00:59:12.734720 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 00:59:12.737984 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 00:59:12.744493 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:59:12.748005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:59:12.751206 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1191 00:59:12.758787 0 11 8 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
1192 00:59:12.762666 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1193 00:59:12.765859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 00:59:12.769775 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 00:59:12.774270 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 00:59:12.779828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:59:12.783202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:59:12.787052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 00:59:12.790536 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 00:59:12.797120 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 00:59:12.800305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 00:59:12.803772 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 00:59:12.810463 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:59:12.813967 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:59:12.816976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:59:12.823449 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:59:12.827015 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:59:12.830563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:59:12.836847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:59:12.840207 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:59:12.843520 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:59:12.850353 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:59:12.853809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:59:12.857400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 00:59:12.860027 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 00:59:12.863441 Total UI for P1: 0, mck2ui 16
1217 00:59:12.867079 best dqsien dly found for B0: ( 0, 14, 4)
1218 00:59:12.873342 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 00:59:12.876993 Total UI for P1: 0, mck2ui 16
1220 00:59:12.880215 best dqsien dly found for B1: ( 0, 14, 8)
1221 00:59:12.884009 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 00:59:12.886603 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 00:59:12.887027
1224 00:59:12.890208 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 00:59:12.893356 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 00:59:12.896447 [Gating] SW calibration Done
1227 00:59:12.897100 ==
1228 00:59:12.899890 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 00:59:12.903536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 00:59:12.904052 ==
1231 00:59:12.906699 RX Vref Scan: 0
1232 00:59:12.907238
1233 00:59:12.909910 RX Vref 0 -> 0, step: 1
1234 00:59:12.910562
1235 00:59:12.911031 RX Delay -130 -> 252, step: 16
1236 00:59:12.916750 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1237 00:59:12.919681 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1238 00:59:12.923029 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1239 00:59:12.926319 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1240 00:59:12.929436 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1241 00:59:12.936494 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1242 00:59:12.939357 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1243 00:59:12.942590 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1244 00:59:12.946559 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1245 00:59:12.949602 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1246 00:59:12.956294 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1247 00:59:12.959580 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1248 00:59:12.963171 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1249 00:59:12.966664 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1250 00:59:12.973474 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1251 00:59:12.976328 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1252 00:59:12.976884 ==
1253 00:59:12.979645 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 00:59:12.983214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 00:59:12.983862 ==
1256 00:59:12.984232 DQS Delay:
1257 00:59:12.985835 DQS0 = 0, DQS1 = 0
1258 00:59:12.986293 DQM Delay:
1259 00:59:12.989342 DQM0 = 86, DQM1 = 77
1260 00:59:12.989754 DQ Delay:
1261 00:59:12.992298 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1262 00:59:12.995909 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1263 00:59:12.999541 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1264 00:59:13.002739 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1265 00:59:13.003247
1266 00:59:13.003638
1267 00:59:13.004055 ==
1268 00:59:13.005523 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 00:59:13.008922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 00:59:13.012288 ==
1271 00:59:13.012705
1272 00:59:13.013029
1273 00:59:13.013329 TX Vref Scan disable
1274 00:59:13.015939 == TX Byte 0 ==
1275 00:59:13.019303 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1276 00:59:13.025461 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1277 00:59:13.025881 == TX Byte 1 ==
1278 00:59:13.028629 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 00:59:13.035107 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 00:59:13.035611 ==
1281 00:59:13.038931 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 00:59:13.042493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 00:59:13.042930 ==
1284 00:59:13.054510 TX Vref=22, minBit 0, minWin=27, winSum=442
1285 00:59:13.057776 TX Vref=24, minBit 0, minWin=27, winSum=444
1286 00:59:13.061298 TX Vref=26, minBit 3, minWin=27, winSum=449
1287 00:59:13.064551 TX Vref=28, minBit 2, minWin=27, winSum=449
1288 00:59:13.068250 TX Vref=30, minBit 2, minWin=27, winSum=451
1289 00:59:13.071450 TX Vref=32, minBit 2, minWin=27, winSum=446
1290 00:59:13.077555 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1291 00:59:13.077973
1292 00:59:13.081442 Final TX Range 1 Vref 30
1293 00:59:13.081957
1294 00:59:13.082286 ==
1295 00:59:13.084615 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 00:59:13.087630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 00:59:13.088142 ==
1298 00:59:13.090684
1299 00:59:13.091093
1300 00:59:13.091462 TX Vref Scan disable
1301 00:59:13.094490 == TX Byte 0 ==
1302 00:59:13.098240 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1303 00:59:13.101079 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1304 00:59:13.104325 == TX Byte 1 ==
1305 00:59:13.107429 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 00:59:13.114118 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 00:59:13.114639
1308 00:59:13.114963 [DATLAT]
1309 00:59:13.115277 Freq=800, CH0 RK1
1310 00:59:13.115675
1311 00:59:13.117330 DATLAT Default: 0xa
1312 00:59:13.117622 0, 0xFFFF, sum = 0
1313 00:59:13.120958 1, 0xFFFF, sum = 0
1314 00:59:13.123931 2, 0xFFFF, sum = 0
1315 00:59:13.124155 3, 0xFFFF, sum = 0
1316 00:59:13.127266 4, 0xFFFF, sum = 0
1317 00:59:13.127472 5, 0xFFFF, sum = 0
1318 00:59:13.130901 6, 0xFFFF, sum = 0
1319 00:59:13.131087 7, 0xFFFF, sum = 0
1320 00:59:13.133514 8, 0xFFFF, sum = 0
1321 00:59:13.133695 9, 0x0, sum = 1
1322 00:59:13.137142 10, 0x0, sum = 2
1323 00:59:13.137560 11, 0x0, sum = 3
1324 00:59:13.137890 12, 0x0, sum = 4
1325 00:59:13.140771 best_step = 10
1326 00:59:13.141278
1327 00:59:13.141601 ==
1328 00:59:13.144037 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 00:59:13.147019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 00:59:13.147572 ==
1331 00:59:13.150506 RX Vref Scan: 0
1332 00:59:13.150916
1333 00:59:13.151235 RX Vref 0 -> 0, step: 1
1334 00:59:13.154003
1335 00:59:13.154361 RX Delay -95 -> 252, step: 8
1336 00:59:13.161077 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1337 00:59:13.164237 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1338 00:59:13.167943 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1339 00:59:13.171535 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1340 00:59:13.174424 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 00:59:13.181504 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 00:59:13.184399 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 00:59:13.187498 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 00:59:13.190790 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1345 00:59:13.194154 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1346 00:59:13.200687 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 00:59:13.203732 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 00:59:13.207905 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 00:59:13.210582 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 00:59:13.217725 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 00:59:13.220570 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1352 00:59:13.220987 ==
1353 00:59:13.223570 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 00:59:13.227243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 00:59:13.227789 ==
1356 00:59:13.230834 DQS Delay:
1357 00:59:13.231336 DQS0 = 0, DQS1 = 0
1358 00:59:13.231717 DQM Delay:
1359 00:59:13.234249 DQM0 = 86, DQM1 = 77
1360 00:59:13.234756 DQ Delay:
1361 00:59:13.238504 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1362 00:59:13.240402 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 00:59:13.243652 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1364 00:59:13.247070 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1365 00:59:13.247525
1366 00:59:13.247855
1367 00:59:13.257380 [DQSOSCAuto] RK1, (LSB)MR18= 0x2621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1368 00:59:13.257896 CH0 RK1: MR19=606, MR18=2621
1369 00:59:13.263784 CH0_RK1: MR19=0x606, MR18=0x2621, DQSOSC=400, MR23=63, INC=92, DEC=61
1370 00:59:13.266856 [RxdqsGatingPostProcess] freq 800
1371 00:59:13.273904 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 00:59:13.276940 Pre-setting of DQS Precalculation
1373 00:59:13.280210 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 00:59:13.280631 ==
1375 00:59:13.283512 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 00:59:13.290312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 00:59:13.290731 ==
1378 00:59:13.293319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 00:59:13.299951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 00:59:13.309734 [CA 0] Center 37 (6~68) winsize 63
1381 00:59:13.312590 [CA 1] Center 37 (6~68) winsize 63
1382 00:59:13.315940 [CA 2] Center 35 (5~66) winsize 62
1383 00:59:13.319268 [CA 3] Center 34 (4~65) winsize 62
1384 00:59:13.323012 [CA 4] Center 35 (4~66) winsize 63
1385 00:59:13.326644 [CA 5] Center 34 (4~65) winsize 62
1386 00:59:13.327191
1387 00:59:13.329472 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 00:59:13.330018
1389 00:59:13.333034 [CATrainingPosCal] consider 1 rank data
1390 00:59:13.335869 u2DelayCellTimex100 = 270/100 ps
1391 00:59:13.339761 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1392 00:59:13.346130 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1393 00:59:13.349507 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1394 00:59:13.352507 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 00:59:13.356470 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1396 00:59:13.359423 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 00:59:13.359937
1398 00:59:13.362803 CA PerBit enable=1, Macro0, CA PI delay=34
1399 00:59:13.363324
1400 00:59:13.366078 [CBTSetCACLKResult] CA Dly = 34
1401 00:59:13.366584 CS Dly: 5 (0~36)
1402 00:59:13.369652 ==
1403 00:59:13.372328 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 00:59:13.375798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 00:59:13.376307 ==
1406 00:59:13.378952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 00:59:13.385335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 00:59:13.395635 [CA 0] Center 37 (6~68) winsize 63
1409 00:59:13.398731 [CA 1] Center 36 (6~67) winsize 62
1410 00:59:13.402062 [CA 2] Center 35 (4~66) winsize 63
1411 00:59:13.405646 [CA 3] Center 34 (4~65) winsize 62
1412 00:59:13.408767 [CA 4] Center 34 (4~65) winsize 62
1413 00:59:13.412248 [CA 5] Center 34 (4~65) winsize 62
1414 00:59:13.412664
1415 00:59:13.415474 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 00:59:13.416027
1417 00:59:13.418336 [CATrainingPosCal] consider 2 rank data
1418 00:59:13.421886 u2DelayCellTimex100 = 270/100 ps
1419 00:59:13.425704 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1420 00:59:13.429391 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 00:59:13.432715 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1422 00:59:13.436152 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 00:59:13.440212 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 00:59:13.443793 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 00:59:13.443875
1426 00:59:13.447139 CA PerBit enable=1, Macro0, CA PI delay=34
1427 00:59:13.447238
1428 00:59:13.451434 [CBTSetCACLKResult] CA Dly = 34
1429 00:59:13.451516 CS Dly: 5 (0~37)
1430 00:59:13.455065
1431 00:59:13.455146 ----->DramcWriteLeveling(PI) begin...
1432 00:59:13.458685 ==
1433 00:59:13.458767 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 00:59:13.464918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 00:59:13.465001 ==
1436 00:59:13.468826 Write leveling (Byte 0): 25 => 25
1437 00:59:13.472455 Write leveling (Byte 1): 26 => 26
1438 00:59:13.472537 DramcWriteLeveling(PI) end<-----
1439 00:59:13.474890
1440 00:59:13.474971 ==
1441 00:59:13.478767 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 00:59:13.481594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 00:59:13.481709 ==
1444 00:59:13.485257 [Gating] SW mode calibration
1445 00:59:13.491992 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 00:59:13.494778 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 00:59:13.501301 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 00:59:13.505096 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1449 00:59:13.508311 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 00:59:13.514688 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 00:59:13.518131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 00:59:13.521425 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:59:13.527957 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:59:13.531671 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:59:13.535025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:59:13.541288 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:59:13.544836 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:59:13.547820 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:59:13.554528 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:59:13.557953 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:59:13.561041 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:59:13.567720 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:59:13.571144 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:59:13.574211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 00:59:13.580868 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:59:13.584341 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:59:13.587586 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:59:13.594104 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 00:59:13.597743 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:59:13.600631 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:59:13.607616 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:59:13.610558 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1473 00:59:13.613910 0 9 8 | B1->B0 | 2b2b 3333 | 0 0 | (0 0) (0 0)
1474 00:59:13.620529 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 00:59:13.623842 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 00:59:13.627553 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 00:59:13.634199 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:59:13.637220 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:59:13.640550 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1480 00:59:13.647073 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (0 1) (1 1)
1481 00:59:13.650817 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 00:59:13.653685 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 00:59:13.660026 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 00:59:13.663512 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 00:59:13.666704 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:59:13.673625 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:59:13.676973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:59:13.680134 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1489 00:59:13.687004 0 11 8 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
1490 00:59:13.690202 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 00:59:13.694282 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 00:59:13.700110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 00:59:13.703160 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:59:13.706669 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:59:13.713069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:59:13.716531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 00:59:13.719985 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1498 00:59:13.726190 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 00:59:13.729918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 00:59:13.732801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 00:59:13.740096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 00:59:13.742992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:59:13.746217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:59:13.749490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:59:13.756185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:59:13.759519 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:59:13.762733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:59:13.769426 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:59:13.772785 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:59:13.776048 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:59:13.782683 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:59:13.786417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 00:59:13.789246 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 00:59:13.793024 Total UI for P1: 0, mck2ui 16
1515 00:59:13.796090 best dqsien dly found for B0: ( 0, 14, 4)
1516 00:59:13.799335 Total UI for P1: 0, mck2ui 16
1517 00:59:13.802847 best dqsien dly found for B1: ( 0, 14, 4)
1518 00:59:13.806153 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1519 00:59:13.809602 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1520 00:59:13.812500
1521 00:59:13.815766 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 00:59:13.819202 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 00:59:13.822679 [Gating] SW calibration Done
1524 00:59:13.822760 ==
1525 00:59:13.826098 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 00:59:13.829440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 00:59:13.829521 ==
1528 00:59:13.829585 RX Vref Scan: 0
1529 00:59:13.829643
1530 00:59:13.832639 RX Vref 0 -> 0, step: 1
1531 00:59:13.832719
1532 00:59:13.835971 RX Delay -130 -> 252, step: 16
1533 00:59:13.839304 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1534 00:59:13.842307 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1535 00:59:13.849165 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1536 00:59:13.852563 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1537 00:59:13.855903 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1538 00:59:13.859523 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1539 00:59:13.862157 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1540 00:59:13.869279 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1541 00:59:13.872270 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1542 00:59:13.875647 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1543 00:59:13.879724 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1544 00:59:13.882005 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1545 00:59:13.888734 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1546 00:59:13.891891 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1547 00:59:13.895477 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1548 00:59:13.898714 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1549 00:59:13.898831 ==
1550 00:59:13.901844 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 00:59:13.908501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 00:59:13.908582 ==
1553 00:59:13.908645 DQS Delay:
1554 00:59:13.912131 DQS0 = 0, DQS1 = 0
1555 00:59:13.912215 DQM Delay:
1556 00:59:13.915194 DQM0 = 89, DQM1 = 82
1557 00:59:13.915299 DQ Delay:
1558 00:59:13.918943 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1559 00:59:13.922129 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1560 00:59:13.925294 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1561 00:59:13.928671 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =93
1562 00:59:13.928751
1563 00:59:13.928814
1564 00:59:13.928872 ==
1565 00:59:13.931770 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 00:59:13.935099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 00:59:13.935180 ==
1568 00:59:13.935243
1569 00:59:13.935301
1570 00:59:13.938388 TX Vref Scan disable
1571 00:59:13.941569 == TX Byte 0 ==
1572 00:59:13.945211 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1573 00:59:13.948523 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1574 00:59:13.951849 == TX Byte 1 ==
1575 00:59:13.955281 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1576 00:59:13.958730 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1577 00:59:13.958810 ==
1578 00:59:13.961987 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 00:59:13.965362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 00:59:13.968225 ==
1581 00:59:13.979705 TX Vref=22, minBit 4, minWin=26, winSum=441
1582 00:59:13.983030 TX Vref=24, minBit 4, minWin=26, winSum=443
1583 00:59:13.986460 TX Vref=26, minBit 4, minWin=26, winSum=445
1584 00:59:13.989530 TX Vref=28, minBit 2, minWin=27, winSum=453
1585 00:59:13.992701 TX Vref=30, minBit 1, minWin=27, winSum=452
1586 00:59:13.999472 TX Vref=32, minBit 1, minWin=27, winSum=451
1587 00:59:14.003584 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 28
1588 00:59:14.003666
1589 00:59:14.007280 Final TX Range 1 Vref 28
1590 00:59:14.007383
1591 00:59:14.007462 ==
1592 00:59:14.010295 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 00:59:14.013625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 00:59:14.013721 ==
1595 00:59:14.013815
1596 00:59:14.013888
1597 00:59:14.017156 TX Vref Scan disable
1598 00:59:14.020014 == TX Byte 0 ==
1599 00:59:14.023419 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1600 00:59:14.026817 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1601 00:59:14.030273 == TX Byte 1 ==
1602 00:59:14.033760 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 00:59:14.036934 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 00:59:14.037014
1605 00:59:14.040332 [DATLAT]
1606 00:59:14.040413 Freq=800, CH1 RK0
1607 00:59:14.040476
1608 00:59:14.043257 DATLAT Default: 0xa
1609 00:59:14.043336 0, 0xFFFF, sum = 0
1610 00:59:14.046715 1, 0xFFFF, sum = 0
1611 00:59:14.046806 2, 0xFFFF, sum = 0
1612 00:59:14.050105 3, 0xFFFF, sum = 0
1613 00:59:14.050187 4, 0xFFFF, sum = 0
1614 00:59:14.053501 5, 0xFFFF, sum = 0
1615 00:59:14.053583 6, 0xFFFF, sum = 0
1616 00:59:14.057008 7, 0xFFFF, sum = 0
1617 00:59:14.057092 8, 0xFFFF, sum = 0
1618 00:59:14.060464 9, 0x0, sum = 1
1619 00:59:14.060546 10, 0x0, sum = 2
1620 00:59:14.063521 11, 0x0, sum = 3
1621 00:59:14.063603 12, 0x0, sum = 4
1622 00:59:14.066801 best_step = 10
1623 00:59:14.066881
1624 00:59:14.066943 ==
1625 00:59:14.069881 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 00:59:14.073406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 00:59:14.073487 ==
1628 00:59:14.076378 RX Vref Scan: 1
1629 00:59:14.076458
1630 00:59:14.076521 Set Vref Range= 32 -> 127
1631 00:59:14.076579
1632 00:59:14.079766 RX Vref 32 -> 127, step: 1
1633 00:59:14.079846
1634 00:59:14.082968 RX Delay -95 -> 252, step: 8
1635 00:59:14.083048
1636 00:59:14.086450 Set Vref, RX VrefLevel [Byte0]: 32
1637 00:59:14.090373 [Byte1]: 32
1638 00:59:14.090453
1639 00:59:14.093163 Set Vref, RX VrefLevel [Byte0]: 33
1640 00:59:14.096512 [Byte1]: 33
1641 00:59:14.099936
1642 00:59:14.100017 Set Vref, RX VrefLevel [Byte0]: 34
1643 00:59:14.103143 [Byte1]: 34
1644 00:59:14.107189
1645 00:59:14.107269 Set Vref, RX VrefLevel [Byte0]: 35
1646 00:59:14.110568 [Byte1]: 35
1647 00:59:14.115277
1648 00:59:14.115367 Set Vref, RX VrefLevel [Byte0]: 36
1649 00:59:14.118274 [Byte1]: 36
1650 00:59:14.122903
1651 00:59:14.122983 Set Vref, RX VrefLevel [Byte0]: 37
1652 00:59:14.125895 [Byte1]: 37
1653 00:59:14.129981
1654 00:59:14.130080 Set Vref, RX VrefLevel [Byte0]: 38
1655 00:59:14.133684 [Byte1]: 38
1656 00:59:14.137938
1657 00:59:14.138019 Set Vref, RX VrefLevel [Byte0]: 39
1658 00:59:14.141193 [Byte1]: 39
1659 00:59:14.145302
1660 00:59:14.145383 Set Vref, RX VrefLevel [Byte0]: 40
1661 00:59:14.149047 [Byte1]: 40
1662 00:59:14.153227
1663 00:59:14.153307 Set Vref, RX VrefLevel [Byte0]: 41
1664 00:59:14.156564 [Byte1]: 41
1665 00:59:14.160571
1666 00:59:14.160652 Set Vref, RX VrefLevel [Byte0]: 42
1667 00:59:14.163986 [Byte1]: 42
1668 00:59:14.168395
1669 00:59:14.168476 Set Vref, RX VrefLevel [Byte0]: 43
1670 00:59:14.171608 [Byte1]: 43
1671 00:59:14.175532
1672 00:59:14.175612 Set Vref, RX VrefLevel [Byte0]: 44
1673 00:59:14.179235 [Byte1]: 44
1674 00:59:14.183732
1675 00:59:14.183813 Set Vref, RX VrefLevel [Byte0]: 45
1676 00:59:14.186777 [Byte1]: 45
1677 00:59:14.191024
1678 00:59:14.191105 Set Vref, RX VrefLevel [Byte0]: 46
1679 00:59:14.194543 [Byte1]: 46
1680 00:59:14.198415
1681 00:59:14.198496 Set Vref, RX VrefLevel [Byte0]: 47
1682 00:59:14.202305 [Byte1]: 47
1683 00:59:14.206153
1684 00:59:14.206235 Set Vref, RX VrefLevel [Byte0]: 48
1685 00:59:14.209587 [Byte1]: 48
1686 00:59:14.213555
1687 00:59:14.213635 Set Vref, RX VrefLevel [Byte0]: 49
1688 00:59:14.217656 [Byte1]: 49
1689 00:59:14.221615
1690 00:59:14.221696 Set Vref, RX VrefLevel [Byte0]: 50
1691 00:59:14.224791 [Byte1]: 50
1692 00:59:14.228832
1693 00:59:14.228915 Set Vref, RX VrefLevel [Byte0]: 51
1694 00:59:14.232049 [Byte1]: 51
1695 00:59:14.236731
1696 00:59:14.236811 Set Vref, RX VrefLevel [Byte0]: 52
1697 00:59:14.239731 [Byte1]: 52
1698 00:59:14.244223
1699 00:59:14.244304 Set Vref, RX VrefLevel [Byte0]: 53
1700 00:59:14.247316 [Byte1]: 53
1701 00:59:14.251964
1702 00:59:14.252084 Set Vref, RX VrefLevel [Byte0]: 54
1703 00:59:14.254712 [Byte1]: 54
1704 00:59:14.259271
1705 00:59:14.259352 Set Vref, RX VrefLevel [Byte0]: 55
1706 00:59:14.262336 [Byte1]: 55
1707 00:59:14.266890
1708 00:59:14.266971 Set Vref, RX VrefLevel [Byte0]: 56
1709 00:59:14.270754 [Byte1]: 56
1710 00:59:14.274604
1711 00:59:14.274688 Set Vref, RX VrefLevel [Byte0]: 57
1712 00:59:14.277668 [Byte1]: 57
1713 00:59:14.282169
1714 00:59:14.282249 Set Vref, RX VrefLevel [Byte0]: 58
1715 00:59:14.285685 [Byte1]: 58
1716 00:59:14.290199
1717 00:59:14.290280 Set Vref, RX VrefLevel [Byte0]: 59
1718 00:59:14.292755 [Byte1]: 59
1719 00:59:14.297342
1720 00:59:14.297424 Set Vref, RX VrefLevel [Byte0]: 60
1721 00:59:14.300643 [Byte1]: 60
1722 00:59:14.304793
1723 00:59:14.304874 Set Vref, RX VrefLevel [Byte0]: 61
1724 00:59:14.308118 [Byte1]: 61
1725 00:59:14.312636
1726 00:59:14.312718 Set Vref, RX VrefLevel [Byte0]: 62
1727 00:59:14.316116 [Byte1]: 62
1728 00:59:14.320241
1729 00:59:14.320321 Set Vref, RX VrefLevel [Byte0]: 63
1730 00:59:14.323415 [Byte1]: 63
1731 00:59:14.327939
1732 00:59:14.328020 Set Vref, RX VrefLevel [Byte0]: 64
1733 00:59:14.331230 [Byte1]: 64
1734 00:59:14.335521
1735 00:59:14.335602 Set Vref, RX VrefLevel [Byte0]: 65
1736 00:59:14.338401 [Byte1]: 65
1737 00:59:14.342916
1738 00:59:14.342997 Set Vref, RX VrefLevel [Byte0]: 66
1739 00:59:14.346336 [Byte1]: 66
1740 00:59:14.350587
1741 00:59:14.350668 Set Vref, RX VrefLevel [Byte0]: 67
1742 00:59:14.353573 [Byte1]: 67
1743 00:59:14.358470
1744 00:59:14.358551 Set Vref, RX VrefLevel [Byte0]: 68
1745 00:59:14.361735 [Byte1]: 68
1746 00:59:14.365718
1747 00:59:14.365799 Set Vref, RX VrefLevel [Byte0]: 69
1748 00:59:14.368823 [Byte1]: 69
1749 00:59:14.373286
1750 00:59:14.373367 Set Vref, RX VrefLevel [Byte0]: 70
1751 00:59:14.376498 [Byte1]: 70
1752 00:59:14.380863
1753 00:59:14.380944 Set Vref, RX VrefLevel [Byte0]: 71
1754 00:59:14.384655 [Byte1]: 71
1755 00:59:14.388579
1756 00:59:14.388660 Set Vref, RX VrefLevel [Byte0]: 72
1757 00:59:14.391732 [Byte1]: 72
1758 00:59:14.396229
1759 00:59:14.396309 Set Vref, RX VrefLevel [Byte0]: 73
1760 00:59:14.399786 [Byte1]: 73
1761 00:59:14.404051
1762 00:59:14.404131 Final RX Vref Byte 0 = 57 to rank0
1763 00:59:14.406803 Final RX Vref Byte 1 = 56 to rank0
1764 00:59:14.410354 Final RX Vref Byte 0 = 57 to rank1
1765 00:59:14.413601 Final RX Vref Byte 1 = 56 to rank1==
1766 00:59:14.416887 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 00:59:14.423776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 00:59:14.423858 ==
1769 00:59:14.423922 DQS Delay:
1770 00:59:14.426717 DQS0 = 0, DQS1 = 0
1771 00:59:14.426798 DQM Delay:
1772 00:59:14.426861 DQM0 = 86, DQM1 = 80
1773 00:59:14.430163 DQ Delay:
1774 00:59:14.433542 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1775 00:59:14.436628 DQ4 =80, DQ5 =96, DQ6 =100, DQ7 =84
1776 00:59:14.440175 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =72
1777 00:59:14.443698 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1778 00:59:14.443804
1779 00:59:14.443894
1780 00:59:14.450147 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b2e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1781 00:59:14.453247 CH1 RK0: MR19=606, MR18=1B2E
1782 00:59:14.459856 CH1_RK0: MR19=0x606, MR18=0x1B2E, DQSOSC=398, MR23=63, INC=93, DEC=62
1783 00:59:14.459963
1784 00:59:14.462908 ----->DramcWriteLeveling(PI) begin...
1785 00:59:14.462990 ==
1786 00:59:14.466513 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 00:59:14.469709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 00:59:14.469791 ==
1789 00:59:14.473075 Write leveling (Byte 0): 25 => 25
1790 00:59:14.476424 Write leveling (Byte 1): 31 => 31
1791 00:59:14.479725 DramcWriteLeveling(PI) end<-----
1792 00:59:14.479806
1793 00:59:14.479870 ==
1794 00:59:14.483161 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 00:59:14.486140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 00:59:14.486222 ==
1797 00:59:14.489907 [Gating] SW mode calibration
1798 00:59:14.496663 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 00:59:14.503107 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 00:59:14.506519 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 00:59:14.512928 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1802 00:59:14.516311 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 00:59:14.519549 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 00:59:14.525922 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 00:59:14.529308 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 00:59:14.532710 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 00:59:14.539414 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 00:59:14.542836 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 00:59:14.546177 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 00:59:14.552360 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:59:14.555742 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:59:14.559303 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:59:14.565783 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:59:14.569055 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:59:14.572107 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:59:14.578973 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:59:14.582102 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1818 00:59:14.585618 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:59:14.591959 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:59:14.595491 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:59:14.599017 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:59:14.605693 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:59:14.608611 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:59:14.611986 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 00:59:14.616093 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1826 00:59:14.621815 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1827 00:59:14.625291 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 00:59:14.628870 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 00:59:14.635094 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 00:59:14.638425 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 00:59:14.641835 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 00:59:14.648439 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1833 00:59:14.651968 0 10 4 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (0 0)
1834 00:59:14.655304 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1835 00:59:14.662058 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 00:59:14.665130 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 00:59:14.668425 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 00:59:14.674806 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 00:59:14.678386 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 00:59:14.681615 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1841 00:59:14.688330 0 11 4 | B1->B0 | 2626 3838 | 0 0 | (0 0) (1 1)
1842 00:59:14.691682 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1843 00:59:14.695498 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 00:59:14.701267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 00:59:14.704830 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 00:59:14.708145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 00:59:14.714659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 00:59:14.717870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 00:59:14.721543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1850 00:59:14.728408 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 00:59:14.731187 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 00:59:14.734816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 00:59:14.741612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 00:59:14.744836 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 00:59:14.748538 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 00:59:14.754864 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 00:59:14.757784 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 00:59:14.761466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:59:14.768086 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:59:14.771115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:59:14.774684 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:59:14.777689 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:59:14.784485 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:59:14.788475 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1865 00:59:14.791258 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 00:59:14.794598 Total UI for P1: 0, mck2ui 16
1867 00:59:14.797813 best dqsien dly found for B0: ( 0, 14, 0)
1868 00:59:14.801114 Total UI for P1: 0, mck2ui 16
1869 00:59:14.804440 best dqsien dly found for B1: ( 0, 14, 2)
1870 00:59:14.807764 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1871 00:59:14.814330 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1872 00:59:14.814411
1873 00:59:14.817761 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1874 00:59:14.820818 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1875 00:59:14.824699 [Gating] SW calibration Done
1876 00:59:14.824781 ==
1877 00:59:14.827742 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 00:59:14.831491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 00:59:14.831572 ==
1880 00:59:14.831637 RX Vref Scan: 0
1881 00:59:14.831697
1882 00:59:14.834435 RX Vref 0 -> 0, step: 1
1883 00:59:14.834516
1884 00:59:14.837928 RX Delay -130 -> 252, step: 16
1885 00:59:14.841072 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1886 00:59:14.844495 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1887 00:59:14.851571 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1888 00:59:14.854178 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1889 00:59:14.857775 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1890 00:59:14.860891 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1891 00:59:14.864201 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1892 00:59:14.870905 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1893 00:59:14.873993 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1894 00:59:14.877250 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1895 00:59:14.880530 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1896 00:59:14.884162 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1897 00:59:14.890837 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1898 00:59:14.893887 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1899 00:59:14.897086 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1900 00:59:14.900698 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1901 00:59:14.900832 ==
1902 00:59:14.903861 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 00:59:14.910658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 00:59:14.910742 ==
1905 00:59:14.910806 DQS Delay:
1906 00:59:14.913964 DQS0 = 0, DQS1 = 0
1907 00:59:14.914045 DQM Delay:
1908 00:59:14.914108 DQM0 = 83, DQM1 = 81
1909 00:59:14.916895 DQ Delay:
1910 00:59:14.920417 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1911 00:59:14.923952 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1912 00:59:14.926853 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1913 00:59:14.930439 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1914 00:59:14.930520
1915 00:59:14.930584
1916 00:59:14.930643 ==
1917 00:59:14.933628 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 00:59:14.936797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 00:59:14.936878 ==
1920 00:59:14.936943
1921 00:59:14.937001
1922 00:59:14.940271 TX Vref Scan disable
1923 00:59:14.943335 == TX Byte 0 ==
1924 00:59:14.946993 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1925 00:59:14.950446 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1926 00:59:14.953427 == TX Byte 1 ==
1927 00:59:14.956832 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1928 00:59:14.960541 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1929 00:59:14.960622 ==
1930 00:59:14.963543 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 00:59:14.967256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 00:59:14.967337 ==
1933 00:59:14.981809 TX Vref=22, minBit 1, minWin=26, winSum=440
1934 00:59:14.985431 TX Vref=24, minBit 1, minWin=26, winSum=444
1935 00:59:14.988715 TX Vref=26, minBit 1, minWin=27, winSum=448
1936 00:59:14.991907 TX Vref=28, minBit 2, minWin=27, winSum=451
1937 00:59:14.995092 TX Vref=30, minBit 2, minWin=27, winSum=452
1938 00:59:15.001914 TX Vref=32, minBit 2, minWin=27, winSum=449
1939 00:59:15.004833 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1940 00:59:15.004916
1941 00:59:15.008363 Final TX Range 1 Vref 30
1942 00:59:15.008445
1943 00:59:15.008509 ==
1944 00:59:15.011630 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 00:59:15.015026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 00:59:15.018086 ==
1947 00:59:15.018167
1948 00:59:15.018231
1949 00:59:15.018337 TX Vref Scan disable
1950 00:59:15.022009 == TX Byte 0 ==
1951 00:59:15.024965 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1952 00:59:15.028565 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1953 00:59:15.031749 == TX Byte 1 ==
1954 00:59:15.035061 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1955 00:59:15.038928 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1956 00:59:15.041599
1957 00:59:15.041679 [DATLAT]
1958 00:59:15.041742 Freq=800, CH1 RK1
1959 00:59:15.041802
1960 00:59:15.045069 DATLAT Default: 0xa
1961 00:59:15.045173 0, 0xFFFF, sum = 0
1962 00:59:15.048757 1, 0xFFFF, sum = 0
1963 00:59:15.048838 2, 0xFFFF, sum = 0
1964 00:59:15.051750 3, 0xFFFF, sum = 0
1965 00:59:15.055261 4, 0xFFFF, sum = 0
1966 00:59:15.055343 5, 0xFFFF, sum = 0
1967 00:59:15.058209 6, 0xFFFF, sum = 0
1968 00:59:15.058291 7, 0xFFFF, sum = 0
1969 00:59:15.061372 8, 0xFFFF, sum = 0
1970 00:59:15.061455 9, 0x0, sum = 1
1971 00:59:15.065630 10, 0x0, sum = 2
1972 00:59:15.065712 11, 0x0, sum = 3
1973 00:59:15.065777 12, 0x0, sum = 4
1974 00:59:15.068511 best_step = 10
1975 00:59:15.068591
1976 00:59:15.068655 ==
1977 00:59:15.072197 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 00:59:15.074956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 00:59:15.075038 ==
1980 00:59:15.077869 RX Vref Scan: 0
1981 00:59:15.077950
1982 00:59:15.078014 RX Vref 0 -> 0, step: 1
1983 00:59:15.081182
1984 00:59:15.081262 RX Delay -95 -> 252, step: 8
1985 00:59:15.088369 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1986 00:59:15.091816 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1987 00:59:15.095075 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1988 00:59:15.098609 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1989 00:59:15.105027 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1990 00:59:15.108594 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1991 00:59:15.111388 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1992 00:59:15.115115 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1993 00:59:15.117840 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1994 00:59:15.124924 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1995 00:59:15.128087 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1996 00:59:15.131034 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1997 00:59:15.134359 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1998 00:59:15.137759 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1999 00:59:15.144390 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2000 00:59:15.147537 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2001 00:59:15.147618 ==
2002 00:59:15.151262 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 00:59:15.154211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 00:59:15.154293 ==
2005 00:59:15.157783 DQS Delay:
2006 00:59:15.157864 DQS0 = 0, DQS1 = 0
2007 00:59:15.157927 DQM Delay:
2008 00:59:15.160584 DQM0 = 88, DQM1 = 84
2009 00:59:15.160665 DQ Delay:
2010 00:59:15.164368 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2011 00:59:15.167720 DQ4 =88, DQ5 =100, DQ6 =96, DQ7 =84
2012 00:59:15.171072 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
2013 00:59:15.173969 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =88
2014 00:59:15.174051
2015 00:59:15.174115
2016 00:59:15.183998 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2017 00:59:15.187574 CH1 RK1: MR19=606, MR18=1B36
2018 00:59:15.190883 CH1_RK1: MR19=0x606, MR18=0x1B36, DQSOSC=396, MR23=63, INC=94, DEC=62
2019 00:59:15.194141 [RxdqsGatingPostProcess] freq 800
2020 00:59:15.200923 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 00:59:15.203950 Pre-setting of DQS Precalculation
2022 00:59:15.207187 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 00:59:15.217186 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 00:59:15.223607 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 00:59:15.223690
2026 00:59:15.223753
2027 00:59:15.227080 [Calibration Summary] 1600 Mbps
2028 00:59:15.227161 CH 0, Rank 0
2029 00:59:15.230494 SW Impedance : PASS
2030 00:59:15.230576 DUTY Scan : NO K
2031 00:59:15.234087 ZQ Calibration : PASS
2032 00:59:15.237286 Jitter Meter : NO K
2033 00:59:15.237367 CBT Training : PASS
2034 00:59:15.240722 Write leveling : PASS
2035 00:59:15.243737 RX DQS gating : PASS
2036 00:59:15.243818 RX DQ/DQS(RDDQC) : PASS
2037 00:59:15.247043 TX DQ/DQS : PASS
2038 00:59:15.250533 RX DATLAT : PASS
2039 00:59:15.250614 RX DQ/DQS(Engine): PASS
2040 00:59:15.253620 TX OE : NO K
2041 00:59:15.253702 All Pass.
2042 00:59:15.253766
2043 00:59:15.256739 CH 0, Rank 1
2044 00:59:15.256819 SW Impedance : PASS
2045 00:59:15.260054 DUTY Scan : NO K
2046 00:59:15.263588 ZQ Calibration : PASS
2047 00:59:15.263669 Jitter Meter : NO K
2048 00:59:15.267348 CBT Training : PASS
2049 00:59:15.270299 Write leveling : PASS
2050 00:59:15.270381 RX DQS gating : PASS
2051 00:59:15.273651 RX DQ/DQS(RDDQC) : PASS
2052 00:59:15.276557 TX DQ/DQS : PASS
2053 00:59:15.276638 RX DATLAT : PASS
2054 00:59:15.280085 RX DQ/DQS(Engine): PASS
2055 00:59:15.283025 TX OE : NO K
2056 00:59:15.283113 All Pass.
2057 00:59:15.283255
2058 00:59:15.283343 CH 1, Rank 0
2059 00:59:15.286279 SW Impedance : PASS
2060 00:59:15.290092 DUTY Scan : NO K
2061 00:59:15.290173 ZQ Calibration : PASS
2062 00:59:15.292990 Jitter Meter : NO K
2063 00:59:15.293070 CBT Training : PASS
2064 00:59:15.296988 Write leveling : PASS
2065 00:59:15.300061 RX DQS gating : PASS
2066 00:59:15.300143 RX DQ/DQS(RDDQC) : PASS
2067 00:59:15.303013 TX DQ/DQS : PASS
2068 00:59:15.306249 RX DATLAT : PASS
2069 00:59:15.306336 RX DQ/DQS(Engine): PASS
2070 00:59:15.309814 TX OE : NO K
2071 00:59:15.309895 All Pass.
2072 00:59:15.309958
2073 00:59:15.313405 CH 1, Rank 1
2074 00:59:15.313486 SW Impedance : PASS
2075 00:59:15.316119 DUTY Scan : NO K
2076 00:59:15.319585 ZQ Calibration : PASS
2077 00:59:15.319666 Jitter Meter : NO K
2078 00:59:15.322833 CBT Training : PASS
2079 00:59:15.326084 Write leveling : PASS
2080 00:59:15.326165 RX DQS gating : PASS
2081 00:59:15.329470 RX DQ/DQS(RDDQC) : PASS
2082 00:59:15.333169 TX DQ/DQS : PASS
2083 00:59:15.333250 RX DATLAT : PASS
2084 00:59:15.336090 RX DQ/DQS(Engine): PASS
2085 00:59:15.336171 TX OE : NO K
2086 00:59:15.339532 All Pass.
2087 00:59:15.339638
2088 00:59:15.339720 DramC Write-DBI off
2089 00:59:15.342813 PER_BANK_REFRESH: Hybrid Mode
2090 00:59:15.346476 TX_TRACKING: ON
2091 00:59:15.349508 [GetDramInforAfterCalByMRR] Vendor 6.
2092 00:59:15.353144 [GetDramInforAfterCalByMRR] Revision 606.
2093 00:59:15.356144 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 00:59:15.356225 MR0 0x3b3b
2095 00:59:15.359767 MR8 0x5151
2096 00:59:15.363109 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 00:59:15.363190
2098 00:59:15.363256 MR0 0x3b3b
2099 00:59:15.363351 MR8 0x5151
2100 00:59:15.366255 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 00:59:15.366336
2102 00:59:15.376151 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 00:59:15.379779 [FAST_K] Save calibration result to emmc
2104 00:59:15.383162 [FAST_K] Save calibration result to emmc
2105 00:59:15.386200 dram_init: config_dvfs: 1
2106 00:59:15.389278 dramc_set_vcore_voltage set vcore to 662500
2107 00:59:15.392552 Read voltage for 1200, 2
2108 00:59:15.392633 Vio18 = 0
2109 00:59:15.396287 Vcore = 662500
2110 00:59:15.396369 Vdram = 0
2111 00:59:15.396432 Vddq = 0
2112 00:59:15.396491 Vmddr = 0
2113 00:59:15.402818 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 00:59:15.409173 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 00:59:15.409254 MEM_TYPE=3, freq_sel=15
2116 00:59:15.412964 sv_algorithm_assistance_LP4_1600
2117 00:59:15.416259 ============ PULL DRAM RESETB DOWN ============
2118 00:59:15.422534 ========== PULL DRAM RESETB DOWN end =========
2119 00:59:15.425728 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 00:59:15.429134 ===================================
2121 00:59:15.432340 LPDDR4 DRAM CONFIGURATION
2122 00:59:15.435518 ===================================
2123 00:59:15.435600 EX_ROW_EN[0] = 0x0
2124 00:59:15.439080 EX_ROW_EN[1] = 0x0
2125 00:59:15.439161 LP4Y_EN = 0x0
2126 00:59:15.442399 WORK_FSP = 0x0
2127 00:59:15.442480 WL = 0x4
2128 00:59:15.445613 RL = 0x4
2129 00:59:15.445695 BL = 0x2
2130 00:59:15.449052 RPST = 0x0
2131 00:59:15.452244 RD_PRE = 0x0
2132 00:59:15.452324 WR_PRE = 0x1
2133 00:59:15.455922 WR_PST = 0x0
2134 00:59:15.456002 DBI_WR = 0x0
2135 00:59:15.459198 DBI_RD = 0x0
2136 00:59:15.459279 OTF = 0x1
2137 00:59:15.462466 ===================================
2138 00:59:15.465406 ===================================
2139 00:59:15.468980 ANA top config
2140 00:59:15.472550 ===================================
2141 00:59:15.472632 DLL_ASYNC_EN = 0
2142 00:59:15.475341 ALL_SLAVE_EN = 0
2143 00:59:15.478587 NEW_RANK_MODE = 1
2144 00:59:15.482247 DLL_IDLE_MODE = 1
2145 00:59:15.482328 LP45_APHY_COMB_EN = 1
2146 00:59:15.485381 TX_ODT_DIS = 1
2147 00:59:15.489025 NEW_8X_MODE = 1
2148 00:59:15.492174 ===================================
2149 00:59:15.495236 ===================================
2150 00:59:15.498540 data_rate = 2400
2151 00:59:15.502192 CKR = 1
2152 00:59:15.505055 DQ_P2S_RATIO = 8
2153 00:59:15.508464 ===================================
2154 00:59:15.508545 CA_P2S_RATIO = 8
2155 00:59:15.512160 DQ_CA_OPEN = 0
2156 00:59:15.515287 DQ_SEMI_OPEN = 0
2157 00:59:15.518373 CA_SEMI_OPEN = 0
2158 00:59:15.521822 CA_FULL_RATE = 0
2159 00:59:15.525168 DQ_CKDIV4_EN = 0
2160 00:59:15.525285 CA_CKDIV4_EN = 0
2161 00:59:15.528426 CA_PREDIV_EN = 0
2162 00:59:15.531554 PH8_DLY = 17
2163 00:59:15.534985 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 00:59:15.538695 DQ_AAMCK_DIV = 4
2165 00:59:15.541532 CA_AAMCK_DIV = 4
2166 00:59:15.541614 CA_ADMCK_DIV = 4
2167 00:59:15.544884 DQ_TRACK_CA_EN = 0
2168 00:59:15.548226 CA_PICK = 1200
2169 00:59:15.551325 CA_MCKIO = 1200
2170 00:59:15.554636 MCKIO_SEMI = 0
2171 00:59:15.558073 PLL_FREQ = 2366
2172 00:59:15.561629 DQ_UI_PI_RATIO = 32
2173 00:59:15.565068 CA_UI_PI_RATIO = 0
2174 00:59:15.565149 ===================================
2175 00:59:15.568164 ===================================
2176 00:59:15.571302 memory_type:LPDDR4
2177 00:59:15.574556 GP_NUM : 10
2178 00:59:15.574637 SRAM_EN : 1
2179 00:59:15.578000 MD32_EN : 0
2180 00:59:15.581288 ===================================
2181 00:59:15.584529 [ANA_INIT] >>>>>>>>>>>>>>
2182 00:59:15.587795 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 00:59:15.591705 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 00:59:15.594403 ===================================
2185 00:59:15.594484 data_rate = 2400,PCW = 0X5b00
2186 00:59:15.597872 ===================================
2187 00:59:15.604474 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 00:59:15.607751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 00:59:15.614276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 00:59:15.617896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 00:59:15.621068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 00:59:15.624233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 00:59:15.627468 [ANA_INIT] flow start
2194 00:59:15.630979 [ANA_INIT] PLL >>>>>>>>
2195 00:59:15.631061 [ANA_INIT] PLL <<<<<<<<
2196 00:59:15.634285 [ANA_INIT] MIDPI >>>>>>>>
2197 00:59:15.637518 [ANA_INIT] MIDPI <<<<<<<<
2198 00:59:15.637600 [ANA_INIT] DLL >>>>>>>>
2199 00:59:15.640998 [ANA_INIT] DLL <<<<<<<<
2200 00:59:15.644196 [ANA_INIT] flow end
2201 00:59:15.647248 ============ LP4 DIFF to SE enter ============
2202 00:59:15.650827 ============ LP4 DIFF to SE exit ============
2203 00:59:15.653982 [ANA_INIT] <<<<<<<<<<<<<
2204 00:59:15.657608 [Flow] Enable top DCM control >>>>>
2205 00:59:15.660766 [Flow] Enable top DCM control <<<<<
2206 00:59:15.663759 Enable DLL master slave shuffle
2207 00:59:15.667477 ==============================================================
2208 00:59:15.670724 Gating Mode config
2209 00:59:15.677099 ==============================================================
2210 00:59:15.677182 Config description:
2211 00:59:15.687097 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 00:59:15.693903 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 00:59:15.700533 SELPH_MODE 0: By rank 1: By Phase
2214 00:59:15.703563 ==============================================================
2215 00:59:15.707294 GAT_TRACK_EN = 1
2216 00:59:15.710223 RX_GATING_MODE = 2
2217 00:59:15.713941 RX_GATING_TRACK_MODE = 2
2218 00:59:15.716839 SELPH_MODE = 1
2219 00:59:15.720259 PICG_EARLY_EN = 1
2220 00:59:15.724012 VALID_LAT_VALUE = 1
2221 00:59:15.727160 ==============================================================
2222 00:59:15.730078 Enter into Gating configuration >>>>
2223 00:59:15.733758 Exit from Gating configuration <<<<
2224 00:59:15.736842 Enter into DVFS_PRE_config >>>>>
2225 00:59:15.750466 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 00:59:15.753266 Exit from DVFS_PRE_config <<<<<
2227 00:59:15.756709 Enter into PICG configuration >>>>
2228 00:59:15.756791 Exit from PICG configuration <<<<
2229 00:59:15.760305 [RX_INPUT] configuration >>>>>
2230 00:59:15.763483 [RX_INPUT] configuration <<<<<
2231 00:59:15.770548 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 00:59:15.773442 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 00:59:15.780089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 00:59:15.786850 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 00:59:15.793092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 00:59:15.799885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 00:59:15.803417 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 00:59:15.806550 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 00:59:15.809530 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 00:59:15.816725 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 00:59:15.820514 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 00:59:15.822878 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 00:59:15.826209 ===================================
2244 00:59:15.829903 LPDDR4 DRAM CONFIGURATION
2245 00:59:15.833547 ===================================
2246 00:59:15.836145 EX_ROW_EN[0] = 0x0
2247 00:59:15.836226 EX_ROW_EN[1] = 0x0
2248 00:59:15.839902 LP4Y_EN = 0x0
2249 00:59:15.839983 WORK_FSP = 0x0
2250 00:59:15.843224 WL = 0x4
2251 00:59:15.843305 RL = 0x4
2252 00:59:15.846721 BL = 0x2
2253 00:59:15.846802 RPST = 0x0
2254 00:59:15.849550 RD_PRE = 0x0
2255 00:59:15.849631 WR_PRE = 0x1
2256 00:59:15.853173 WR_PST = 0x0
2257 00:59:15.853253 DBI_WR = 0x0
2258 00:59:15.856178 DBI_RD = 0x0
2259 00:59:15.856258 OTF = 0x1
2260 00:59:15.860243 ===================================
2261 00:59:15.866140 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 00:59:15.869653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 00:59:15.872727 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 00:59:15.875892 ===================================
2265 00:59:15.879294 LPDDR4 DRAM CONFIGURATION
2266 00:59:15.882860 ===================================
2267 00:59:15.886761 EX_ROW_EN[0] = 0x10
2268 00:59:15.886842 EX_ROW_EN[1] = 0x0
2269 00:59:15.889490 LP4Y_EN = 0x0
2270 00:59:15.889571 WORK_FSP = 0x0
2271 00:59:15.892649 WL = 0x4
2272 00:59:15.892729 RL = 0x4
2273 00:59:15.895864 BL = 0x2
2274 00:59:15.895945 RPST = 0x0
2275 00:59:15.899264 RD_PRE = 0x0
2276 00:59:15.899345 WR_PRE = 0x1
2277 00:59:15.902489 WR_PST = 0x0
2278 00:59:15.902570 DBI_WR = 0x0
2279 00:59:15.906152 DBI_RD = 0x0
2280 00:59:15.906234 OTF = 0x1
2281 00:59:15.909413 ===================================
2282 00:59:15.915557 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 00:59:15.915638 ==
2284 00:59:15.918975 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 00:59:15.925692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 00:59:15.925774 ==
2287 00:59:15.925838 [Duty_Offset_Calibration]
2288 00:59:15.929228 B0:2 B1:0 CA:4
2289 00:59:15.929309
2290 00:59:15.932236 [DutyScan_Calibration_Flow] k_type=0
2291 00:59:15.940211
2292 00:59:15.940291 ==CLK 0==
2293 00:59:15.943946 Final CLK duty delay cell = -4
2294 00:59:15.947196 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2295 00:59:15.950685 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2296 00:59:15.953854 [-4] AVG Duty = 4937%(X100)
2297 00:59:15.953935
2298 00:59:15.957300 CH0 CLK Duty spec in!! Max-Min= 187%
2299 00:59:15.960589 [DutyScan_Calibration_Flow] ====Done====
2300 00:59:15.960670
2301 00:59:15.963883 [DutyScan_Calibration_Flow] k_type=1
2302 00:59:15.980061
2303 00:59:15.980141 ==DQS 0 ==
2304 00:59:15.983505 Final DQS duty delay cell = 0
2305 00:59:15.986424 [0] MAX Duty = 5156%(X100), DQS PI = 18
2306 00:59:15.989769 [0] MIN Duty = 5093%(X100), DQS PI = 2
2307 00:59:15.993012 [0] AVG Duty = 5124%(X100)
2308 00:59:15.993093
2309 00:59:15.993156 ==DQS 1 ==
2310 00:59:15.996656 Final DQS duty delay cell = 0
2311 00:59:15.999540 [0] MAX Duty = 5125%(X100), DQS PI = 50
2312 00:59:16.003493 [0] MIN Duty = 5000%(X100), DQS PI = 0
2313 00:59:16.006751 [0] AVG Duty = 5062%(X100)
2314 00:59:16.006831
2315 00:59:16.009635 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2316 00:59:16.009716
2317 00:59:16.013185 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2318 00:59:16.016199 [DutyScan_Calibration_Flow] ====Done====
2319 00:59:16.016279
2320 00:59:16.020181 [DutyScan_Calibration_Flow] k_type=3
2321 00:59:16.036603
2322 00:59:16.036682 ==DQM 0 ==
2323 00:59:16.039755 Final DQM duty delay cell = 0
2324 00:59:16.042991 [0] MAX Duty = 5125%(X100), DQS PI = 20
2325 00:59:16.046189 [0] MIN Duty = 4844%(X100), DQS PI = 50
2326 00:59:16.049501 [0] AVG Duty = 4984%(X100)
2327 00:59:16.049581
2328 00:59:16.049644 ==DQM 1 ==
2329 00:59:16.052954 Final DQM duty delay cell = 0
2330 00:59:16.056162 [0] MAX Duty = 5000%(X100), DQS PI = 6
2331 00:59:16.059775 [0] MIN Duty = 4875%(X100), DQS PI = 20
2332 00:59:16.062705 [0] AVG Duty = 4937%(X100)
2333 00:59:16.062785
2334 00:59:16.066394 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2335 00:59:16.066475
2336 00:59:16.069848 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2337 00:59:16.072657 [DutyScan_Calibration_Flow] ====Done====
2338 00:59:16.072737
2339 00:59:16.076621 [DutyScan_Calibration_Flow] k_type=2
2340 00:59:16.093091
2341 00:59:16.093193 ==DQ 0 ==
2342 00:59:16.095972 Final DQ duty delay cell = 0
2343 00:59:16.099183 [0] MAX Duty = 5156%(X100), DQS PI = 18
2344 00:59:16.102491 [0] MIN Duty = 4969%(X100), DQS PI = 52
2345 00:59:16.105937 [0] AVG Duty = 5062%(X100)
2346 00:59:16.106019
2347 00:59:16.106082 ==DQ 1 ==
2348 00:59:16.109269 Final DQ duty delay cell = 0
2349 00:59:16.112531 [0] MAX Duty = 5125%(X100), DQS PI = 4
2350 00:59:16.115817 [0] MIN Duty = 4938%(X100), DQS PI = 16
2351 00:59:16.115898 [0] AVG Duty = 5031%(X100)
2352 00:59:16.119022
2353 00:59:16.122655 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2354 00:59:16.122739
2355 00:59:16.126152 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2356 00:59:16.128919 [DutyScan_Calibration_Flow] ====Done====
2357 00:59:16.128999 ==
2358 00:59:16.132643 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 00:59:16.135505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 00:59:16.135587 ==
2361 00:59:16.139098 [Duty_Offset_Calibration]
2362 00:59:16.139203 B0:0 B1:-1 CA:3
2363 00:59:16.139298
2364 00:59:16.142495 [DutyScan_Calibration_Flow] k_type=0
2365 00:59:16.153115
2366 00:59:16.153196 ==CLK 0==
2367 00:59:16.156367 Final CLK duty delay cell = 0
2368 00:59:16.160085 [0] MAX Duty = 5156%(X100), DQS PI = 12
2369 00:59:16.162611 [0] MIN Duty = 5000%(X100), DQS PI = 4
2370 00:59:16.162714 [0] AVG Duty = 5078%(X100)
2371 00:59:16.166081
2372 00:59:16.169480 CH1 CLK Duty spec in!! Max-Min= 156%
2373 00:59:16.172986 [DutyScan_Calibration_Flow] ====Done====
2374 00:59:16.173066
2375 00:59:16.175982 [DutyScan_Calibration_Flow] k_type=1
2376 00:59:16.191834
2377 00:59:16.191939 ==DQS 0 ==
2378 00:59:16.195299 Final DQS duty delay cell = 0
2379 00:59:16.198473 [0] MAX Duty = 5124%(X100), DQS PI = 0
2380 00:59:16.201892 [0] MIN Duty = 4907%(X100), DQS PI = 6
2381 00:59:16.201995 [0] AVG Duty = 5015%(X100)
2382 00:59:16.205071
2383 00:59:16.205181 ==DQS 1 ==
2384 00:59:16.208450 Final DQS duty delay cell = 0
2385 00:59:16.212051 [0] MAX Duty = 5156%(X100), DQS PI = 0
2386 00:59:16.215073 [0] MIN Duty = 5000%(X100), DQS PI = 56
2387 00:59:16.215154 [0] AVG Duty = 5078%(X100)
2388 00:59:16.218784
2389 00:59:16.221810 CH1 DQS 0 Duty spec in!! Max-Min= 217%
2390 00:59:16.221917
2391 00:59:16.224942 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2392 00:59:16.228431 [DutyScan_Calibration_Flow] ====Done====
2393 00:59:16.228512
2394 00:59:16.232398 [DutyScan_Calibration_Flow] k_type=3
2395 00:59:16.249248
2396 00:59:16.249330 ==DQM 0 ==
2397 00:59:16.252889 Final DQM duty delay cell = 0
2398 00:59:16.255727 [0] MAX Duty = 5031%(X100), DQS PI = 60
2399 00:59:16.259501 [0] MIN Duty = 4813%(X100), DQS PI = 6
2400 00:59:16.259582 [0] AVG Duty = 4922%(X100)
2401 00:59:16.262343
2402 00:59:16.262422 ==DQM 1 ==
2403 00:59:16.265805 Final DQM duty delay cell = 4
2404 00:59:16.269083 [4] MAX Duty = 5187%(X100), DQS PI = 2
2405 00:59:16.272639 [4] MIN Duty = 5062%(X100), DQS PI = 34
2406 00:59:16.272720 [4] AVG Duty = 5124%(X100)
2407 00:59:16.275891
2408 00:59:16.278852 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2409 00:59:16.278932
2410 00:59:16.282698 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2411 00:59:16.285785 [DutyScan_Calibration_Flow] ====Done====
2412 00:59:16.285859
2413 00:59:16.288790 [DutyScan_Calibration_Flow] k_type=2
2414 00:59:16.304557
2415 00:59:16.304650 ==DQ 0 ==
2416 00:59:16.307990 Final DQ duty delay cell = -4
2417 00:59:16.311287 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2418 00:59:16.314946 [-4] MIN Duty = 4813%(X100), DQS PI = 4
2419 00:59:16.315072 [-4] AVG Duty = 4922%(X100)
2420 00:59:16.317998
2421 00:59:16.318103 ==DQ 1 ==
2422 00:59:16.321236 Final DQ duty delay cell = 0
2423 00:59:16.324853 [0] MAX Duty = 5031%(X100), DQS PI = 2
2424 00:59:16.328058 [0] MIN Duty = 4844%(X100), DQS PI = 30
2425 00:59:16.328139 [0] AVG Duty = 4937%(X100)
2426 00:59:16.328203
2427 00:59:16.334452 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2428 00:59:16.334536
2429 00:59:16.338173 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2430 00:59:16.341286 [DutyScan_Calibration_Flow] ====Done====
2431 00:59:16.345094 nWR fixed to 30
2432 00:59:16.345175 [ModeRegInit_LP4] CH0 RK0
2433 00:59:16.347870 [ModeRegInit_LP4] CH0 RK1
2434 00:59:16.351539 [ModeRegInit_LP4] CH1 RK0
2435 00:59:16.354432 [ModeRegInit_LP4] CH1 RK1
2436 00:59:16.354538 match AC timing 7
2437 00:59:16.360987 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 00:59:16.364658 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 00:59:16.367521 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 00:59:16.374995 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 00:59:16.377589 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 00:59:16.377670 ==
2443 00:59:16.381280 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 00:59:16.384506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 00:59:16.384588 ==
2446 00:59:16.390904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 00:59:16.397719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 00:59:16.404696 [CA 0] Center 40 (10~70) winsize 61
2449 00:59:16.408596 [CA 1] Center 39 (9~69) winsize 61
2450 00:59:16.411736 [CA 2] Center 35 (5~66) winsize 62
2451 00:59:16.414689 [CA 3] Center 35 (5~66) winsize 62
2452 00:59:16.417964 [CA 4] Center 33 (3~64) winsize 62
2453 00:59:16.421334 [CA 5] Center 33 (3~64) winsize 62
2454 00:59:16.421414
2455 00:59:16.424803 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2456 00:59:16.424885
2457 00:59:16.428087 [CATrainingPosCal] consider 1 rank data
2458 00:59:16.431801 u2DelayCellTimex100 = 270/100 ps
2459 00:59:16.434796 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2460 00:59:16.441479 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2461 00:59:16.445465 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2462 00:59:16.448015 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 00:59:16.451222 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2464 00:59:16.454788 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2465 00:59:16.454869
2466 00:59:16.458325 CA PerBit enable=1, Macro0, CA PI delay=33
2467 00:59:16.458406
2468 00:59:16.461166 [CBTSetCACLKResult] CA Dly = 33
2469 00:59:16.464551 CS Dly: 7 (0~38)
2470 00:59:16.464631 ==
2471 00:59:16.467721 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 00:59:16.470842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 00:59:16.470923 ==
2474 00:59:16.477759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 00:59:16.481295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2476 00:59:16.491011 [CA 0] Center 39 (9~70) winsize 62
2477 00:59:16.494303 [CA 1] Center 39 (9~70) winsize 62
2478 00:59:16.497241 [CA 2] Center 35 (5~66) winsize 62
2479 00:59:16.501157 [CA 3] Center 35 (5~66) winsize 62
2480 00:59:16.503985 [CA 4] Center 34 (4~65) winsize 62
2481 00:59:16.507229 [CA 5] Center 33 (3~64) winsize 62
2482 00:59:16.507334
2483 00:59:16.510519 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2484 00:59:16.510600
2485 00:59:16.514368 [CATrainingPosCal] consider 2 rank data
2486 00:59:16.517231 u2DelayCellTimex100 = 270/100 ps
2487 00:59:16.520859 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2488 00:59:16.527150 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2489 00:59:16.530768 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2490 00:59:16.533723 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 00:59:16.536997 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2492 00:59:16.540647 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2493 00:59:16.540730
2494 00:59:16.544345 CA PerBit enable=1, Macro0, CA PI delay=33
2495 00:59:16.544451
2496 00:59:16.546935 [CBTSetCACLKResult] CA Dly = 33
2497 00:59:16.547021 CS Dly: 8 (0~41)
2498 00:59:16.550200
2499 00:59:16.553874 ----->DramcWriteLeveling(PI) begin...
2500 00:59:16.553957 ==
2501 00:59:16.557199 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 00:59:16.560202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 00:59:16.560287 ==
2504 00:59:16.563493 Write leveling (Byte 0): 31 => 31
2505 00:59:16.566711 Write leveling (Byte 1): 27 => 27
2506 00:59:16.570473 DramcWriteLeveling(PI) end<-----
2507 00:59:16.570581
2508 00:59:16.570686 ==
2509 00:59:16.573463 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 00:59:16.576860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 00:59:16.576964 ==
2512 00:59:16.580367 [Gating] SW mode calibration
2513 00:59:16.587312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 00:59:16.593826 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 00:59:16.596967 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2516 00:59:16.600490 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2517 00:59:16.607340 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 00:59:16.610610 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 00:59:16.613493 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 00:59:16.620083 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 00:59:16.623800 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2522 00:59:16.626843 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2523 00:59:16.630323 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2524 00:59:16.636961 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2525 00:59:16.640537 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 00:59:16.643763 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 00:59:16.650424 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 00:59:16.653215 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 00:59:16.656804 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2530 00:59:16.663513 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2531 00:59:16.666691 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2532 00:59:16.670274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 00:59:16.676327 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 00:59:16.680020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 00:59:16.683131 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 00:59:16.689893 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 00:59:16.693061 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2538 00:59:16.696464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 00:59:16.703096 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 00:59:16.706633 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 00:59:16.710179 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 00:59:16.716588 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 00:59:16.719493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 00:59:16.723115 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 00:59:16.729693 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 00:59:16.733347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 00:59:16.736330 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 00:59:16.743016 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 00:59:16.746588 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 00:59:16.749827 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:59:16.756412 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:59:16.759739 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:59:16.762823 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 00:59:16.769883 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 00:59:16.772886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 00:59:16.776064 Total UI for P1: 0, mck2ui 16
2557 00:59:16.779663 best dqsien dly found for B0: ( 1, 3, 26)
2558 00:59:16.782892 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 00:59:16.786399 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 00:59:16.789230 Total UI for P1: 0, mck2ui 16
2561 00:59:16.792739 best dqsien dly found for B1: ( 1, 4, 2)
2562 00:59:16.796126 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2563 00:59:16.802588 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2564 00:59:16.802692
2565 00:59:16.806137 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2566 00:59:16.809408 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2567 00:59:16.813015 [Gating] SW calibration Done
2568 00:59:16.813092 ==
2569 00:59:16.816041 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 00:59:16.819561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 00:59:16.819643 ==
2572 00:59:16.819707 RX Vref Scan: 0
2573 00:59:16.822706
2574 00:59:16.822786 RX Vref 0 -> 0, step: 1
2575 00:59:16.822849
2576 00:59:16.826021 RX Delay -40 -> 252, step: 8
2577 00:59:16.829401 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2578 00:59:16.832633 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2579 00:59:16.839239 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 00:59:16.842541 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2581 00:59:16.845838 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 00:59:16.849297 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2583 00:59:16.852278 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 00:59:16.859347 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 00:59:16.862493 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2586 00:59:16.865871 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2587 00:59:16.869228 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2588 00:59:16.872154 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2589 00:59:16.879323 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 00:59:16.882142 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2591 00:59:16.885261 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2592 00:59:16.889133 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2593 00:59:16.889247 ==
2594 00:59:16.892196 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 00:59:16.899179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 00:59:16.899283 ==
2597 00:59:16.899402 DQS Delay:
2598 00:59:16.902693 DQS0 = 0, DQS1 = 0
2599 00:59:16.902765 DQM Delay:
2600 00:59:16.902825 DQM0 = 118, DQM1 = 108
2601 00:59:16.905739 DQ Delay:
2602 00:59:16.909167 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2603 00:59:16.911965 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2604 00:59:16.915314 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2605 00:59:16.918793 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2606 00:59:16.918890
2607 00:59:16.918991
2608 00:59:16.919079 ==
2609 00:59:16.922060 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 00:59:16.925271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 00:59:16.928844 ==
2612 00:59:16.928951
2613 00:59:16.929045
2614 00:59:16.929131 TX Vref Scan disable
2615 00:59:16.931575 == TX Byte 0 ==
2616 00:59:16.935077 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2617 00:59:16.938879 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2618 00:59:16.941701 == TX Byte 1 ==
2619 00:59:16.945339 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2620 00:59:16.948651 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2621 00:59:16.951989 ==
2622 00:59:16.952095 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 00:59:16.958696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 00:59:16.958796 ==
2625 00:59:16.969583 TX Vref=22, minBit 1, minWin=25, winSum=412
2626 00:59:16.973273 TX Vref=24, minBit 3, minWin=25, winSum=416
2627 00:59:16.976659 TX Vref=26, minBit 5, minWin=25, winSum=419
2628 00:59:16.979945 TX Vref=28, minBit 0, minWin=26, winSum=427
2629 00:59:16.983531 TX Vref=30, minBit 0, minWin=26, winSum=426
2630 00:59:16.986399 TX Vref=32, minBit 3, minWin=26, winSum=427
2631 00:59:16.993277 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
2632 00:59:16.993353
2633 00:59:16.996564 Final TX Range 1 Vref 28
2634 00:59:16.996645
2635 00:59:16.996709 ==
2636 00:59:17.000157 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 00:59:17.002870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 00:59:17.002951 ==
2639 00:59:17.003015
2640 00:59:17.006181
2641 00:59:17.006262 TX Vref Scan disable
2642 00:59:17.010148 == TX Byte 0 ==
2643 00:59:17.013083 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2644 00:59:17.016286 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2645 00:59:17.019701 == TX Byte 1 ==
2646 00:59:17.023000 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2647 00:59:17.026606 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2648 00:59:17.030081
2649 00:59:17.030162 [DATLAT]
2650 00:59:17.030226 Freq=1200, CH0 RK0
2651 00:59:17.030285
2652 00:59:17.032736 DATLAT Default: 0xd
2653 00:59:17.032817 0, 0xFFFF, sum = 0
2654 00:59:17.036325 1, 0xFFFF, sum = 0
2655 00:59:17.036408 2, 0xFFFF, sum = 0
2656 00:59:17.039415 3, 0xFFFF, sum = 0
2657 00:59:17.042642 4, 0xFFFF, sum = 0
2658 00:59:17.042724 5, 0xFFFF, sum = 0
2659 00:59:17.045976 6, 0xFFFF, sum = 0
2660 00:59:17.046059 7, 0xFFFF, sum = 0
2661 00:59:17.049373 8, 0xFFFF, sum = 0
2662 00:59:17.049455 9, 0xFFFF, sum = 0
2663 00:59:17.052587 10, 0xFFFF, sum = 0
2664 00:59:17.052669 11, 0xFFFF, sum = 0
2665 00:59:17.055681 12, 0x0, sum = 1
2666 00:59:17.055764 13, 0x0, sum = 2
2667 00:59:17.059467 14, 0x0, sum = 3
2668 00:59:17.059549 15, 0x0, sum = 4
2669 00:59:17.062765 best_step = 13
2670 00:59:17.062845
2671 00:59:17.062908 ==
2672 00:59:17.066081 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 00:59:17.069311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 00:59:17.069392 ==
2675 00:59:17.069456 RX Vref Scan: 1
2676 00:59:17.069516
2677 00:59:17.072718 Set Vref Range= 32 -> 127
2678 00:59:17.072800
2679 00:59:17.076334 RX Vref 32 -> 127, step: 1
2680 00:59:17.076415
2681 00:59:17.079643 RX Delay -21 -> 252, step: 4
2682 00:59:17.079724
2683 00:59:17.082672 Set Vref, RX VrefLevel [Byte0]: 32
2684 00:59:17.085816 [Byte1]: 32
2685 00:59:17.085898
2686 00:59:17.089090 Set Vref, RX VrefLevel [Byte0]: 33
2687 00:59:17.093240 [Byte1]: 33
2688 00:59:17.096415
2689 00:59:17.096498 Set Vref, RX VrefLevel [Byte0]: 34
2690 00:59:17.099310 [Byte1]: 34
2691 00:59:17.103762
2692 00:59:17.103842 Set Vref, RX VrefLevel [Byte0]: 35
2693 00:59:17.106915 [Byte1]: 35
2694 00:59:17.111747
2695 00:59:17.111828 Set Vref, RX VrefLevel [Byte0]: 36
2696 00:59:17.115042 [Byte1]: 36
2697 00:59:17.119623
2698 00:59:17.119704 Set Vref, RX VrefLevel [Byte0]: 37
2699 00:59:17.123228 [Byte1]: 37
2700 00:59:17.128045
2701 00:59:17.128126 Set Vref, RX VrefLevel [Byte0]: 38
2702 00:59:17.130694 [Byte1]: 38
2703 00:59:17.135864
2704 00:59:17.135946 Set Vref, RX VrefLevel [Byte0]: 39
2705 00:59:17.139271 [Byte1]: 39
2706 00:59:17.143732
2707 00:59:17.143813 Set Vref, RX VrefLevel [Byte0]: 40
2708 00:59:17.146825 [Byte1]: 40
2709 00:59:17.151450
2710 00:59:17.151531 Set Vref, RX VrefLevel [Byte0]: 41
2711 00:59:17.154804 [Byte1]: 41
2712 00:59:17.159162
2713 00:59:17.159242 Set Vref, RX VrefLevel [Byte0]: 42
2714 00:59:17.162840 [Byte1]: 42
2715 00:59:17.167182
2716 00:59:17.170608 Set Vref, RX VrefLevel [Byte0]: 43
2717 00:59:17.170689 [Byte1]: 43
2718 00:59:17.175258
2719 00:59:17.175339 Set Vref, RX VrefLevel [Byte0]: 44
2720 00:59:17.178433 [Byte1]: 44
2721 00:59:17.182993
2722 00:59:17.183074 Set Vref, RX VrefLevel [Byte0]: 45
2723 00:59:17.186867 [Byte1]: 45
2724 00:59:17.190945
2725 00:59:17.191025 Set Vref, RX VrefLevel [Byte0]: 46
2726 00:59:17.194391 [Byte1]: 46
2727 00:59:17.199098
2728 00:59:17.199179 Set Vref, RX VrefLevel [Byte0]: 47
2729 00:59:17.202358 [Byte1]: 47
2730 00:59:17.207771
2731 00:59:17.207853 Set Vref, RX VrefLevel [Byte0]: 48
2732 00:59:17.210667 [Byte1]: 48
2733 00:59:17.215248
2734 00:59:17.215328 Set Vref, RX VrefLevel [Byte0]: 49
2735 00:59:17.218401 [Byte1]: 49
2736 00:59:17.222717
2737 00:59:17.222797 Set Vref, RX VrefLevel [Byte0]: 50
2738 00:59:17.226187 [Byte1]: 50
2739 00:59:17.230839
2740 00:59:17.230919 Set Vref, RX VrefLevel [Byte0]: 51
2741 00:59:17.233917 [Byte1]: 51
2742 00:59:17.238429
2743 00:59:17.238535 Set Vref, RX VrefLevel [Byte0]: 52
2744 00:59:17.241837 [Byte1]: 52
2745 00:59:17.246521
2746 00:59:17.246607 Set Vref, RX VrefLevel [Byte0]: 53
2747 00:59:17.249887 [Byte1]: 53
2748 00:59:17.254274
2749 00:59:17.254355 Set Vref, RX VrefLevel [Byte0]: 54
2750 00:59:17.257568 [Byte1]: 54
2751 00:59:17.262263
2752 00:59:17.262347 Set Vref, RX VrefLevel [Byte0]: 55
2753 00:59:17.268938 [Byte1]: 55
2754 00:59:17.269019
2755 00:59:17.272471 Set Vref, RX VrefLevel [Byte0]: 56
2756 00:59:17.275732 [Byte1]: 56
2757 00:59:17.275814
2758 00:59:17.278734 Set Vref, RX VrefLevel [Byte0]: 57
2759 00:59:17.282031 [Byte1]: 57
2760 00:59:17.286416
2761 00:59:17.286501 Set Vref, RX VrefLevel [Byte0]: 58
2762 00:59:17.289798 [Byte1]: 58
2763 00:59:17.293961
2764 00:59:17.294042 Set Vref, RX VrefLevel [Byte0]: 59
2765 00:59:17.297220 [Byte1]: 59
2766 00:59:17.302275
2767 00:59:17.302375 Set Vref, RX VrefLevel [Byte0]: 60
2768 00:59:17.305338 [Byte1]: 60
2769 00:59:17.309690
2770 00:59:17.309772 Set Vref, RX VrefLevel [Byte0]: 61
2771 00:59:17.313617 [Byte1]: 61
2772 00:59:17.318377
2773 00:59:17.318458 Set Vref, RX VrefLevel [Byte0]: 62
2774 00:59:17.321184 [Byte1]: 62
2775 00:59:17.325782
2776 00:59:17.325864 Set Vref, RX VrefLevel [Byte0]: 63
2777 00:59:17.329249 [Byte1]: 63
2778 00:59:17.334138
2779 00:59:17.334218 Set Vref, RX VrefLevel [Byte0]: 64
2780 00:59:17.337461 [Byte1]: 64
2781 00:59:17.341552
2782 00:59:17.341640 Set Vref, RX VrefLevel [Byte0]: 65
2783 00:59:17.345009 [Byte1]: 65
2784 00:59:17.349550
2785 00:59:17.349630 Set Vref, RX VrefLevel [Byte0]: 66
2786 00:59:17.352753 [Byte1]: 66
2787 00:59:17.357532
2788 00:59:17.357612 Set Vref, RX VrefLevel [Byte0]: 67
2789 00:59:17.360975 [Byte1]: 67
2790 00:59:17.365330
2791 00:59:17.365409 Set Vref, RX VrefLevel [Byte0]: 68
2792 00:59:17.368639 [Byte1]: 68
2793 00:59:17.373143
2794 00:59:17.373227 Set Vref, RX VrefLevel [Byte0]: 69
2795 00:59:17.376479 [Byte1]: 69
2796 00:59:17.381401
2797 00:59:17.381486 Final RX Vref Byte 0 = 54 to rank0
2798 00:59:17.384696 Final RX Vref Byte 1 = 59 to rank0
2799 00:59:17.387976 Final RX Vref Byte 0 = 54 to rank1
2800 00:59:17.391172 Final RX Vref Byte 1 = 59 to rank1==
2801 00:59:17.394629 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 00:59:17.401309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 00:59:17.401390 ==
2804 00:59:17.401454 DQS Delay:
2805 00:59:17.401513 DQS0 = 0, DQS1 = 0
2806 00:59:17.404707 DQM Delay:
2807 00:59:17.404814 DQM0 = 117, DQM1 = 105
2808 00:59:17.407520 DQ Delay:
2809 00:59:17.411157 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2810 00:59:17.414463 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2811 00:59:17.417587 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2812 00:59:17.421095 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2813 00:59:17.421167
2814 00:59:17.421227
2815 00:59:17.431233 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2816 00:59:17.431342 CH0 RK0: MR19=303, MR18=FFFA
2817 00:59:17.437569 CH0_RK0: MR19=0x303, MR18=0xFFFA, DQSOSC=410, MR23=63, INC=39, DEC=26
2818 00:59:17.437657
2819 00:59:17.440767 ----->DramcWriteLeveling(PI) begin...
2820 00:59:17.440849 ==
2821 00:59:17.444059 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 00:59:17.450657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 00:59:17.450758 ==
2824 00:59:17.454162 Write leveling (Byte 0): 32 => 32
2825 00:59:17.454237 Write leveling (Byte 1): 25 => 25
2826 00:59:17.457319 DramcWriteLeveling(PI) end<-----
2827 00:59:17.457389
2828 00:59:17.460595 ==
2829 00:59:17.460693 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 00:59:17.467186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 00:59:17.467286 ==
2832 00:59:17.470831 [Gating] SW mode calibration
2833 00:59:17.477562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 00:59:17.480532 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 00:59:17.487509 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2836 00:59:17.490831 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2837 00:59:17.493821 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 00:59:17.500265 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 00:59:17.503884 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 00:59:17.506874 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 00:59:17.513879 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2842 00:59:17.516647 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2843 00:59:17.520398 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
2844 00:59:17.526997 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 00:59:17.530130 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 00:59:17.533643 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 00:59:17.540018 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 00:59:17.543384 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 00:59:17.547076 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2850 00:59:17.553621 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
2851 00:59:17.556994 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
2852 00:59:17.560195 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 00:59:17.566850 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 00:59:17.570046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 00:59:17.573242 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 00:59:17.580597 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 00:59:17.583263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2858 00:59:17.586360 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2859 00:59:17.593249 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2860 00:59:17.596223 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 00:59:17.599904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 00:59:17.603090 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 00:59:17.609810 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 00:59:17.612994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 00:59:17.616181 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 00:59:17.623148 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 00:59:17.626337 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 00:59:17.629841 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 00:59:17.636766 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 00:59:17.639646 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 00:59:17.642944 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 00:59:17.649619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 00:59:17.652799 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2874 00:59:17.656113 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2875 00:59:17.663161 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2876 00:59:17.663243 Total UI for P1: 0, mck2ui 16
2877 00:59:17.669395 best dqsien dly found for B0: ( 1, 3, 26)
2878 00:59:17.672752 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 00:59:17.676216 Total UI for P1: 0, mck2ui 16
2880 00:59:17.679788 best dqsien dly found for B1: ( 1, 3, 30)
2881 00:59:17.682697 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2882 00:59:17.685984 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2883 00:59:17.686065
2884 00:59:17.689090 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2885 00:59:17.692643 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2886 00:59:17.696162 [Gating] SW calibration Done
2887 00:59:17.696243 ==
2888 00:59:17.699106 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 00:59:17.702537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 00:59:17.705995 ==
2891 00:59:17.706081 RX Vref Scan: 0
2892 00:59:17.706145
2893 00:59:17.709251 RX Vref 0 -> 0, step: 1
2894 00:59:17.709332
2895 00:59:17.712680 RX Delay -40 -> 252, step: 8
2896 00:59:17.715663 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2897 00:59:17.718855 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 00:59:17.722392 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2899 00:59:17.725902 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2900 00:59:17.732323 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2901 00:59:17.735324 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2902 00:59:17.738773 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 00:59:17.742418 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2904 00:59:17.745816 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 00:59:17.752443 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2906 00:59:17.755691 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2907 00:59:17.758731 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2908 00:59:17.762218 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2909 00:59:17.765161 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2910 00:59:17.771849 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2911 00:59:17.775316 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2912 00:59:17.775437 ==
2913 00:59:17.778590 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 00:59:17.781970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 00:59:17.782052 ==
2916 00:59:17.785226 DQS Delay:
2917 00:59:17.785307 DQS0 = 0, DQS1 = 0
2918 00:59:17.785370 DQM Delay:
2919 00:59:17.788752 DQM0 = 115, DQM1 = 109
2920 00:59:17.788832 DQ Delay:
2921 00:59:17.791730 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2922 00:59:17.798182 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2923 00:59:17.801786 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2924 00:59:17.805251 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2925 00:59:17.805368
2926 00:59:17.805435
2927 00:59:17.805504 ==
2928 00:59:17.808327 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 00:59:17.811679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 00:59:17.811761 ==
2931 00:59:17.811826
2932 00:59:17.811884
2933 00:59:17.815004 TX Vref Scan disable
2934 00:59:17.818315 == TX Byte 0 ==
2935 00:59:17.821781 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2936 00:59:17.825313 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2937 00:59:17.828183 == TX Byte 1 ==
2938 00:59:17.831798 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2939 00:59:17.835211 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2940 00:59:17.835318 ==
2941 00:59:17.838544 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 00:59:17.841292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 00:59:17.844676 ==
2944 00:59:17.855017 TX Vref=22, minBit 1, minWin=26, winSum=421
2945 00:59:17.858421 TX Vref=24, minBit 2, minWin=26, winSum=427
2946 00:59:17.861938 TX Vref=26, minBit 2, minWin=26, winSum=430
2947 00:59:17.864881 TX Vref=28, minBit 2, minWin=26, winSum=428
2948 00:59:17.868636 TX Vref=30, minBit 8, minWin=26, winSum=431
2949 00:59:17.874912 TX Vref=32, minBit 4, minWin=26, winSum=427
2950 00:59:17.878405 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
2951 00:59:17.878487
2952 00:59:17.881733 Final TX Range 1 Vref 30
2953 00:59:17.881814
2954 00:59:17.881878 ==
2955 00:59:17.884892 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 00:59:17.888670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 00:59:17.891771 ==
2958 00:59:17.891852
2959 00:59:17.891915
2960 00:59:17.891975 TX Vref Scan disable
2961 00:59:17.895163 == TX Byte 0 ==
2962 00:59:17.898608 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2963 00:59:17.905116 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2964 00:59:17.905197 == TX Byte 1 ==
2965 00:59:17.908347 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2966 00:59:17.914992 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2967 00:59:17.915074
2968 00:59:17.915138 [DATLAT]
2969 00:59:17.915197 Freq=1200, CH0 RK1
2970 00:59:17.915255
2971 00:59:17.918339 DATLAT Default: 0xd
2972 00:59:17.918420 0, 0xFFFF, sum = 0
2973 00:59:17.921962 1, 0xFFFF, sum = 0
2974 00:59:17.922045 2, 0xFFFF, sum = 0
2975 00:59:17.925230 3, 0xFFFF, sum = 0
2976 00:59:17.928452 4, 0xFFFF, sum = 0
2977 00:59:17.928539 5, 0xFFFF, sum = 0
2978 00:59:17.932189 6, 0xFFFF, sum = 0
2979 00:59:17.932270 7, 0xFFFF, sum = 0
2980 00:59:17.934951 8, 0xFFFF, sum = 0
2981 00:59:17.935059 9, 0xFFFF, sum = 0
2982 00:59:17.938231 10, 0xFFFF, sum = 0
2983 00:59:17.938312 11, 0xFFFF, sum = 0
2984 00:59:17.941544 12, 0x0, sum = 1
2985 00:59:17.941626 13, 0x0, sum = 2
2986 00:59:17.944687 14, 0x0, sum = 3
2987 00:59:17.944772 15, 0x0, sum = 4
2988 00:59:17.944838 best_step = 13
2989 00:59:17.948219
2990 00:59:17.948328 ==
2991 00:59:17.951926 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 00:59:17.954879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 00:59:17.954985 ==
2994 00:59:17.955076 RX Vref Scan: 0
2995 00:59:17.955163
2996 00:59:17.958457 RX Vref 0 -> 0, step: 1
2997 00:59:17.958538
2998 00:59:17.961512 RX Delay -21 -> 252, step: 4
2999 00:59:17.964638 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
3000 00:59:17.971635 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
3001 00:59:17.974797 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
3002 00:59:17.977907 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3003 00:59:17.981219 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
3004 00:59:17.984782 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
3005 00:59:17.991528 iDelay=191, Bit 6, Center 124 (59 ~ 190) 132
3006 00:59:17.994644 iDelay=191, Bit 7, Center 120 (55 ~ 186) 132
3007 00:59:17.997718 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3008 00:59:18.001334 iDelay=191, Bit 9, Center 92 (27 ~ 158) 132
3009 00:59:18.004826 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3010 00:59:18.011385 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3011 00:59:18.014651 iDelay=191, Bit 12, Center 112 (47 ~ 178) 132
3012 00:59:18.017545 iDelay=191, Bit 13, Center 112 (47 ~ 178) 132
3013 00:59:18.020862 iDelay=191, Bit 14, Center 120 (55 ~ 186) 132
3014 00:59:18.024359 iDelay=191, Bit 15, Center 114 (51 ~ 178) 128
3015 00:59:18.027785 ==
3016 00:59:18.030935 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 00:59:18.034686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 00:59:18.034767 ==
3019 00:59:18.034831 DQS Delay:
3020 00:59:18.037450 DQS0 = 0, DQS1 = 0
3021 00:59:18.037530 DQM Delay:
3022 00:59:18.041167 DQM0 = 115, DQM1 = 107
3023 00:59:18.041247 DQ Delay:
3024 00:59:18.044047 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3025 00:59:18.047310 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
3026 00:59:18.051018 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3027 00:59:18.054485 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3028 00:59:18.054566
3029 00:59:18.054630
3030 00:59:18.063920 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3031 00:59:18.067779 CH0 RK1: MR19=303, MR18=FAF7
3032 00:59:18.070715 CH0_RK1: MR19=0x303, MR18=0xFAF7, DQSOSC=412, MR23=63, INC=38, DEC=25
3033 00:59:18.073935 [RxdqsGatingPostProcess] freq 1200
3034 00:59:18.080817 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 00:59:18.083843 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 00:59:18.087651 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 00:59:18.090700 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 00:59:18.094221 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 00:59:18.097364 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 00:59:18.100735 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 00:59:18.104363 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 00:59:18.107160 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 00:59:18.107240 Pre-setting of DQS Precalculation
3044 00:59:18.114239 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 00:59:18.114321 ==
3046 00:59:18.117379 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 00:59:18.120869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 00:59:18.120949 ==
3049 00:59:18.127268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 00:59:18.133548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3051 00:59:18.141517 [CA 0] Center 38 (8~68) winsize 61
3052 00:59:18.145018 [CA 1] Center 37 (7~68) winsize 62
3053 00:59:18.148046 [CA 2] Center 35 (5~65) winsize 61
3054 00:59:18.151560 [CA 3] Center 34 (4~64) winsize 61
3055 00:59:18.154590 [CA 4] Center 34 (4~64) winsize 61
3056 00:59:18.158110 [CA 5] Center 33 (3~64) winsize 62
3057 00:59:18.158191
3058 00:59:18.161545 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3059 00:59:18.161625
3060 00:59:18.164897 [CATrainingPosCal] consider 1 rank data
3061 00:59:18.167927 u2DelayCellTimex100 = 270/100 ps
3062 00:59:18.171695 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3063 00:59:18.174498 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 00:59:18.181606 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 00:59:18.184733 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 00:59:18.187863 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3067 00:59:18.191121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3068 00:59:18.191201
3069 00:59:18.194709 CA PerBit enable=1, Macro0, CA PI delay=33
3070 00:59:18.194790
3071 00:59:18.197704 [CBTSetCACLKResult] CA Dly = 33
3072 00:59:18.197784 CS Dly: 5 (0~36)
3073 00:59:18.201679 ==
3074 00:59:18.204447 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 00:59:18.207551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 00:59:18.207633 ==
3077 00:59:18.211319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 00:59:18.217613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3079 00:59:18.227265 [CA 0] Center 37 (7~68) winsize 62
3080 00:59:18.230054 [CA 1] Center 38 (8~68) winsize 61
3081 00:59:18.233511 [CA 2] Center 35 (5~65) winsize 61
3082 00:59:18.236771 [CA 3] Center 33 (3~64) winsize 62
3083 00:59:18.240126 [CA 4] Center 34 (4~64) winsize 61
3084 00:59:18.243685 [CA 5] Center 33 (3~63) winsize 61
3085 00:59:18.243765
3086 00:59:18.247007 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3087 00:59:18.247088
3088 00:59:18.250556 [CATrainingPosCal] consider 2 rank data
3089 00:59:18.254405 u2DelayCellTimex100 = 270/100 ps
3090 00:59:18.257014 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3091 00:59:18.263715 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3092 00:59:18.266807 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 00:59:18.270272 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 00:59:18.273470 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 00:59:18.276528 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3096 00:59:18.276632
3097 00:59:18.279777 CA PerBit enable=1, Macro0, CA PI delay=33
3098 00:59:18.279880
3099 00:59:18.283719 [CBTSetCACLKResult] CA Dly = 33
3100 00:59:18.283825 CS Dly: 6 (0~39)
3101 00:59:18.286834
3102 00:59:18.289655 ----->DramcWriteLeveling(PI) begin...
3103 00:59:18.289728 ==
3104 00:59:18.292946 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 00:59:18.296839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 00:59:18.296942 ==
3107 00:59:18.299552 Write leveling (Byte 0): 25 => 25
3108 00:59:18.303064 Write leveling (Byte 1): 27 => 27
3109 00:59:18.306342 DramcWriteLeveling(PI) end<-----
3110 00:59:18.306423
3111 00:59:18.306488 ==
3112 00:59:18.309710 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 00:59:18.312748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 00:59:18.312829 ==
3115 00:59:18.316351 [Gating] SW mode calibration
3116 00:59:18.322900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 00:59:18.329696 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 00:59:18.332911 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
3119 00:59:18.335872 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 00:59:18.342913 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 00:59:18.346306 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 00:59:18.349079 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 00:59:18.355884 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 00:59:18.359042 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3125 00:59:18.362282 0 15 28 | B1->B0 | 2828 2424 | 0 0 | (1 0) (0 0)
3126 00:59:18.369619 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 00:59:18.372414 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 00:59:18.375804 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 00:59:18.382270 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 00:59:18.385983 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 00:59:18.389027 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 00:59:18.395632 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3133 00:59:18.398882 1 0 28 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
3134 00:59:18.402446 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 00:59:18.408726 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 00:59:18.411957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 00:59:18.415283 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 00:59:18.421942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 00:59:18.425243 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 00:59:18.428555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3141 00:59:18.435159 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3142 00:59:18.439344 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 00:59:18.441921 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 00:59:18.448366 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 00:59:18.452051 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 00:59:18.455132 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 00:59:18.461845 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 00:59:18.464953 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 00:59:18.468435 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 00:59:18.474789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 00:59:18.478250 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 00:59:18.481921 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 00:59:18.488240 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 00:59:18.491349 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 00:59:18.495026 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 00:59:18.501623 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 00:59:18.504779 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 00:59:18.508146 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:59:18.511294 Total UI for P1: 0, mck2ui 16
3160 00:59:18.514871 best dqsien dly found for B0: ( 1, 3, 28)
3161 00:59:18.518274 Total UI for P1: 0, mck2ui 16
3162 00:59:18.521232 best dqsien dly found for B1: ( 1, 3, 28)
3163 00:59:18.524778 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3164 00:59:18.527809 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3165 00:59:18.527890
3166 00:59:18.531266 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3167 00:59:18.537810 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3168 00:59:18.537891 [Gating] SW calibration Done
3169 00:59:18.537975 ==
3170 00:59:18.541146 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 00:59:18.547996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 00:59:18.548077 ==
3173 00:59:18.548140 RX Vref Scan: 0
3174 00:59:18.548199
3175 00:59:18.551538 RX Vref 0 -> 0, step: 1
3176 00:59:18.551619
3177 00:59:18.554611 RX Delay -40 -> 252, step: 8
3178 00:59:18.558297 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3179 00:59:18.561762 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3180 00:59:18.564467 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3181 00:59:18.571266 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3182 00:59:18.574522 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3183 00:59:18.577960 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3184 00:59:18.581295 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3185 00:59:18.584495 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3186 00:59:18.591262 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3187 00:59:18.594549 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3188 00:59:18.597398 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3189 00:59:18.601329 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3190 00:59:18.604229 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 00:59:18.610892 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3192 00:59:18.615001 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3193 00:59:18.617360 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3194 00:59:18.617441 ==
3195 00:59:18.620935 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 00:59:18.623833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 00:59:18.627109 ==
3198 00:59:18.627217 DQS Delay:
3199 00:59:18.627308 DQS0 = 0, DQS1 = 0
3200 00:59:18.630475 DQM Delay:
3201 00:59:18.630555 DQM0 = 117, DQM1 = 113
3202 00:59:18.634414 DQ Delay:
3203 00:59:18.637575 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3204 00:59:18.640410 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3205 00:59:18.643951 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
3206 00:59:18.647389 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3207 00:59:18.647484
3208 00:59:18.647547
3209 00:59:18.647605 ==
3210 00:59:18.650738 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 00:59:18.653953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 00:59:18.654059 ==
3213 00:59:18.654157
3214 00:59:18.656932
3215 00:59:18.657028 TX Vref Scan disable
3216 00:59:18.660190 == TX Byte 0 ==
3217 00:59:18.663386 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3218 00:59:18.667099 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3219 00:59:18.670779 == TX Byte 1 ==
3220 00:59:18.673625 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3221 00:59:18.677379 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3222 00:59:18.677459 ==
3223 00:59:18.680360 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 00:59:18.686685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 00:59:18.686767 ==
3226 00:59:18.697286 TX Vref=22, minBit 1, minWin=24, winSum=407
3227 00:59:18.700637 TX Vref=24, minBit 5, minWin=25, winSum=418
3228 00:59:18.703838 TX Vref=26, minBit 9, minWin=25, winSum=422
3229 00:59:18.707299 TX Vref=28, minBit 9, minWin=25, winSum=426
3230 00:59:18.710863 TX Vref=30, minBit 1, minWin=26, winSum=427
3231 00:59:18.714195 TX Vref=32, minBit 0, minWin=26, winSum=428
3232 00:59:18.720728 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 32
3233 00:59:18.720809
3234 00:59:18.724133 Final TX Range 1 Vref 32
3235 00:59:18.724214
3236 00:59:18.724277 ==
3237 00:59:18.727311 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 00:59:18.730454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 00:59:18.730535 ==
3240 00:59:18.730598
3241 00:59:18.734179
3242 00:59:18.734259 TX Vref Scan disable
3243 00:59:18.737563 == TX Byte 0 ==
3244 00:59:18.740651 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3245 00:59:18.743861 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3246 00:59:18.747130 == TX Byte 1 ==
3247 00:59:18.750633 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 00:59:18.754155 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 00:59:18.757038
3250 00:59:18.757118 [DATLAT]
3251 00:59:18.757181 Freq=1200, CH1 RK0
3252 00:59:18.757240
3253 00:59:18.760745 DATLAT Default: 0xd
3254 00:59:18.760825 0, 0xFFFF, sum = 0
3255 00:59:18.763580 1, 0xFFFF, sum = 0
3256 00:59:18.763662 2, 0xFFFF, sum = 0
3257 00:59:18.767180 3, 0xFFFF, sum = 0
3258 00:59:18.767287 4, 0xFFFF, sum = 0
3259 00:59:18.770674 5, 0xFFFF, sum = 0
3260 00:59:18.773894 6, 0xFFFF, sum = 0
3261 00:59:18.773977 7, 0xFFFF, sum = 0
3262 00:59:18.776980 8, 0xFFFF, sum = 0
3263 00:59:18.777062 9, 0xFFFF, sum = 0
3264 00:59:18.780628 10, 0xFFFF, sum = 0
3265 00:59:18.780710 11, 0xFFFF, sum = 0
3266 00:59:18.784039 12, 0x0, sum = 1
3267 00:59:18.784120 13, 0x0, sum = 2
3268 00:59:18.787254 14, 0x0, sum = 3
3269 00:59:18.787336 15, 0x0, sum = 4
3270 00:59:18.787441 best_step = 13
3271 00:59:18.787501
3272 00:59:18.790240 ==
3273 00:59:18.793763 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 00:59:18.797200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 00:59:18.797281 ==
3276 00:59:18.797344 RX Vref Scan: 1
3277 00:59:18.797404
3278 00:59:18.800451 Set Vref Range= 32 -> 127
3279 00:59:18.800531
3280 00:59:18.803340 RX Vref 32 -> 127, step: 1
3281 00:59:18.803462
3282 00:59:18.806761 RX Delay -13 -> 252, step: 4
3283 00:59:18.806842
3284 00:59:18.810224 Set Vref, RX VrefLevel [Byte0]: 32
3285 00:59:18.813408 [Byte1]: 32
3286 00:59:18.813489
3287 00:59:18.816743 Set Vref, RX VrefLevel [Byte0]: 33
3288 00:59:18.819999 [Byte1]: 33
3289 00:59:18.823201
3290 00:59:18.823307 Set Vref, RX VrefLevel [Byte0]: 34
3291 00:59:18.826588 [Byte1]: 34
3292 00:59:18.831161
3293 00:59:18.831266 Set Vref, RX VrefLevel [Byte0]: 35
3294 00:59:18.834642 [Byte1]: 35
3295 00:59:18.838938
3296 00:59:18.839019 Set Vref, RX VrefLevel [Byte0]: 36
3297 00:59:18.842397 [Byte1]: 36
3298 00:59:18.847262
3299 00:59:18.847347 Set Vref, RX VrefLevel [Byte0]: 37
3300 00:59:18.850368 [Byte1]: 37
3301 00:59:18.854854
3302 00:59:18.854941 Set Vref, RX VrefLevel [Byte0]: 38
3303 00:59:18.858530 [Byte1]: 38
3304 00:59:18.862834
3305 00:59:18.862921 Set Vref, RX VrefLevel [Byte0]: 39
3306 00:59:18.866343 [Byte1]: 39
3307 00:59:18.870637
3308 00:59:18.870732 Set Vref, RX VrefLevel [Byte0]: 40
3309 00:59:18.874145 [Byte1]: 40
3310 00:59:18.878897
3311 00:59:18.879005 Set Vref, RX VrefLevel [Byte0]: 41
3312 00:59:18.882056 [Byte1]: 41
3313 00:59:18.886737
3314 00:59:18.886869 Set Vref, RX VrefLevel [Byte0]: 42
3315 00:59:18.890022 [Byte1]: 42
3316 00:59:18.894295
3317 00:59:18.894374 Set Vref, RX VrefLevel [Byte0]: 43
3318 00:59:18.897714 [Byte1]: 43
3319 00:59:18.902559
3320 00:59:18.902639 Set Vref, RX VrefLevel [Byte0]: 44
3321 00:59:18.906026 [Byte1]: 44
3322 00:59:18.910292
3323 00:59:18.910376 Set Vref, RX VrefLevel [Byte0]: 45
3324 00:59:18.913408 [Byte1]: 45
3325 00:59:18.918048
3326 00:59:18.918127 Set Vref, RX VrefLevel [Byte0]: 46
3327 00:59:18.921156 [Byte1]: 46
3328 00:59:18.926005
3329 00:59:18.926084 Set Vref, RX VrefLevel [Byte0]: 47
3330 00:59:18.929038 [Byte1]: 47
3331 00:59:18.933973
3332 00:59:18.934051 Set Vref, RX VrefLevel [Byte0]: 48
3333 00:59:18.937163 [Byte1]: 48
3334 00:59:18.941746
3335 00:59:18.941825 Set Vref, RX VrefLevel [Byte0]: 49
3336 00:59:18.945194 [Byte1]: 49
3337 00:59:18.949622
3338 00:59:18.949701 Set Vref, RX VrefLevel [Byte0]: 50
3339 00:59:18.953174 [Byte1]: 50
3340 00:59:18.957372
3341 00:59:18.957454 Set Vref, RX VrefLevel [Byte0]: 51
3342 00:59:18.960689 [Byte1]: 51
3343 00:59:18.965402
3344 00:59:18.965480 Set Vref, RX VrefLevel [Byte0]: 52
3345 00:59:18.968774 [Byte1]: 52
3346 00:59:18.973036
3347 00:59:18.973114 Set Vref, RX VrefLevel [Byte0]: 53
3348 00:59:18.976863 [Byte1]: 53
3349 00:59:18.980847
3350 00:59:18.980926 Set Vref, RX VrefLevel [Byte0]: 54
3351 00:59:18.984299 [Byte1]: 54
3352 00:59:18.988828
3353 00:59:18.988906 Set Vref, RX VrefLevel [Byte0]: 55
3354 00:59:18.992178 [Byte1]: 55
3355 00:59:18.996662
3356 00:59:18.996741 Set Vref, RX VrefLevel [Byte0]: 56
3357 00:59:19.000389 [Byte1]: 56
3358 00:59:19.004717
3359 00:59:19.004797 Set Vref, RX VrefLevel [Byte0]: 57
3360 00:59:19.008293 [Byte1]: 57
3361 00:59:19.012588
3362 00:59:19.012667 Set Vref, RX VrefLevel [Byte0]: 58
3363 00:59:19.015981 [Byte1]: 58
3364 00:59:19.020304
3365 00:59:19.020384 Set Vref, RX VrefLevel [Byte0]: 59
3366 00:59:19.024242 [Byte1]: 59
3367 00:59:19.028380
3368 00:59:19.028461 Set Vref, RX VrefLevel [Byte0]: 60
3369 00:59:19.031633 [Byte1]: 60
3370 00:59:19.036513
3371 00:59:19.036597 Set Vref, RX VrefLevel [Byte0]: 61
3372 00:59:19.039751 [Byte1]: 61
3373 00:59:19.044397
3374 00:59:19.044477 Set Vref, RX VrefLevel [Byte0]: 62
3375 00:59:19.047180 [Byte1]: 62
3376 00:59:19.051993
3377 00:59:19.052072 Set Vref, RX VrefLevel [Byte0]: 63
3378 00:59:19.055052 [Byte1]: 63
3379 00:59:19.059599
3380 00:59:19.059687 Set Vref, RX VrefLevel [Byte0]: 64
3381 00:59:19.062876 [Byte1]: 64
3382 00:59:19.067824
3383 00:59:19.067903 Set Vref, RX VrefLevel [Byte0]: 65
3384 00:59:19.070834 [Byte1]: 65
3385 00:59:19.076002
3386 00:59:19.076082 Final RX Vref Byte 0 = 52 to rank0
3387 00:59:19.079170 Final RX Vref Byte 1 = 53 to rank0
3388 00:59:19.082251 Final RX Vref Byte 0 = 52 to rank1
3389 00:59:19.085548 Final RX Vref Byte 1 = 53 to rank1==
3390 00:59:19.089050 Dram Type= 6, Freq= 0, CH_1, rank 0
3391 00:59:19.095911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3392 00:59:19.095991 ==
3393 00:59:19.096054 DQS Delay:
3394 00:59:19.096112 DQS0 = 0, DQS1 = 0
3395 00:59:19.098810 DQM Delay:
3396 00:59:19.098890 DQM0 = 116, DQM1 = 114
3397 00:59:19.101974 DQ Delay:
3398 00:59:19.105688 DQ0 =124, DQ1 =114, DQ2 =106, DQ3 =116
3399 00:59:19.108735 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3400 00:59:19.112089 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =108
3401 00:59:19.115415 DQ12 =124, DQ13 =122, DQ14 =122, DQ15 =122
3402 00:59:19.115496
3403 00:59:19.115558
3404 00:59:19.125475 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
3405 00:59:19.125558 CH1 RK0: MR19=303, MR18=F1FE
3406 00:59:19.132435 CH1_RK0: MR19=0x303, MR18=0xF1FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3407 00:59:19.132515
3408 00:59:19.135664 ----->DramcWriteLeveling(PI) begin...
3409 00:59:19.135781 ==
3410 00:59:19.138547 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 00:59:19.145232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 00:59:19.145313 ==
3413 00:59:19.148715 Write leveling (Byte 0): 22 => 22
3414 00:59:19.148796 Write leveling (Byte 1): 27 => 27
3415 00:59:19.152233 DramcWriteLeveling(PI) end<-----
3416 00:59:19.152313
3417 00:59:19.155516 ==
3418 00:59:19.155596 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 00:59:19.161727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 00:59:19.161808 ==
3421 00:59:19.165001 [Gating] SW mode calibration
3422 00:59:19.171568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3423 00:59:19.174854 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3424 00:59:19.181732 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 00:59:19.185030 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 00:59:19.188485 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 00:59:19.195550 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 00:59:19.198600 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 00:59:19.201449 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3430 00:59:19.208405 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
3431 00:59:19.212152 0 15 28 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
3432 00:59:19.214913 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 00:59:19.221668 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 00:59:19.224879 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 00:59:19.228609 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 00:59:19.231961 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 00:59:19.238112 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3438 00:59:19.241520 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3439 00:59:19.244989 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3440 00:59:19.251266 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 00:59:19.254512 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 00:59:19.257999 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 00:59:19.265028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 00:59:19.267983 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 00:59:19.271314 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 00:59:19.277760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3447 00:59:19.281261 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3448 00:59:19.287804 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 00:59:19.290801 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 00:59:19.294567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 00:59:19.300552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 00:59:19.303903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 00:59:19.307137 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 00:59:19.313861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 00:59:19.317141 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 00:59:19.320527 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 00:59:19.326940 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 00:59:19.330400 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 00:59:19.333544 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 00:59:19.340359 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 00:59:19.343394 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3462 00:59:19.346686 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3463 00:59:19.353130 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3464 00:59:19.353210 Total UI for P1: 0, mck2ui 16
3465 00:59:19.359807 best dqsien dly found for B0: ( 1, 3, 22)
3466 00:59:19.363153 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:59:19.366325 Total UI for P1: 0, mck2ui 16
3468 00:59:19.370474 best dqsien dly found for B1: ( 1, 3, 26)
3469 00:59:19.372901 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3470 00:59:19.375986 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3471 00:59:19.376067
3472 00:59:19.379680 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3473 00:59:19.383091 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3474 00:59:19.385889 [Gating] SW calibration Done
3475 00:59:19.385969 ==
3476 00:59:19.389597 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 00:59:19.392601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 00:59:19.395703 ==
3479 00:59:19.395782 RX Vref Scan: 0
3480 00:59:19.395846
3481 00:59:19.399218 RX Vref 0 -> 0, step: 1
3482 00:59:19.399323
3483 00:59:19.402868 RX Delay -40 -> 252, step: 8
3484 00:59:19.405685 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3485 00:59:19.409392 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3486 00:59:19.412546 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3487 00:59:19.415991 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3488 00:59:19.422756 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3489 00:59:19.425480 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3490 00:59:19.429198 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3491 00:59:19.432438 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3492 00:59:19.435482 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3493 00:59:19.442140 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3494 00:59:19.445636 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3495 00:59:19.448824 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3496 00:59:19.451840 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3497 00:59:19.458552 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3498 00:59:19.462161 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3499 00:59:19.465306 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3500 00:59:19.465386 ==
3501 00:59:19.468388 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 00:59:19.471865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 00:59:19.474935 ==
3504 00:59:19.475015 DQS Delay:
3505 00:59:19.475077 DQS0 = 0, DQS1 = 0
3506 00:59:19.478459 DQM Delay:
3507 00:59:19.478538 DQM0 = 115, DQM1 = 113
3508 00:59:19.481714 DQ Delay:
3509 00:59:19.484650 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3510 00:59:19.488208 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3511 00:59:19.491411 DQ8 =103, DQ9 =99, DQ10 =111, DQ11 =107
3512 00:59:19.494594 DQ12 =123, DQ13 =123, DQ14 =115, DQ15 =123
3513 00:59:19.494685
3514 00:59:19.494748
3515 00:59:19.494806 ==
3516 00:59:19.497882 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 00:59:19.501009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 00:59:19.501090 ==
3519 00:59:19.501152
3520 00:59:19.504488
3521 00:59:19.504568 TX Vref Scan disable
3522 00:59:19.507856 == TX Byte 0 ==
3523 00:59:19.510789 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3524 00:59:19.514178 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3525 00:59:19.517887 == TX Byte 1 ==
3526 00:59:19.521224 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3527 00:59:19.524462 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3528 00:59:19.524559 ==
3529 00:59:19.527368 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 00:59:19.533860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 00:59:19.533941 ==
3532 00:59:19.544970 TX Vref=22, minBit 2, minWin=25, winSum=420
3533 00:59:19.548476 TX Vref=24, minBit 2, minWin=25, winSum=423
3534 00:59:19.551459 TX Vref=26, minBit 9, minWin=25, winSum=428
3535 00:59:19.555353 TX Vref=28, minBit 9, minWin=24, winSum=428
3536 00:59:19.558180 TX Vref=30, minBit 2, minWin=26, winSum=433
3537 00:59:19.564950 TX Vref=32, minBit 2, minWin=26, winSum=434
3538 00:59:19.567919 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3539 00:59:19.567999
3540 00:59:19.571643 Final TX Range 1 Vref 32
3541 00:59:19.571724
3542 00:59:19.571786 ==
3543 00:59:19.574792 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 00:59:19.577721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 00:59:19.581063 ==
3546 00:59:19.581145
3547 00:59:19.581208
3548 00:59:19.581266 TX Vref Scan disable
3549 00:59:19.585159 == TX Byte 0 ==
3550 00:59:19.588052 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3551 00:59:19.594840 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3552 00:59:19.594921 == TX Byte 1 ==
3553 00:59:19.597765 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3554 00:59:19.604431 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3555 00:59:19.604511
3556 00:59:19.604574 [DATLAT]
3557 00:59:19.604632 Freq=1200, CH1 RK1
3558 00:59:19.604689
3559 00:59:19.608158 DATLAT Default: 0xd
3560 00:59:19.611514 0, 0xFFFF, sum = 0
3561 00:59:19.611596 1, 0xFFFF, sum = 0
3562 00:59:19.614668 2, 0xFFFF, sum = 0
3563 00:59:19.614748 3, 0xFFFF, sum = 0
3564 00:59:19.617757 4, 0xFFFF, sum = 0
3565 00:59:19.617838 5, 0xFFFF, sum = 0
3566 00:59:19.621278 6, 0xFFFF, sum = 0
3567 00:59:19.621359 7, 0xFFFF, sum = 0
3568 00:59:19.624780 8, 0xFFFF, sum = 0
3569 00:59:19.624861 9, 0xFFFF, sum = 0
3570 00:59:19.627989 10, 0xFFFF, sum = 0
3571 00:59:19.628070 11, 0xFFFF, sum = 0
3572 00:59:19.631142 12, 0x0, sum = 1
3573 00:59:19.631250 13, 0x0, sum = 2
3574 00:59:19.634520 14, 0x0, sum = 3
3575 00:59:19.634601 15, 0x0, sum = 4
3576 00:59:19.637668 best_step = 13
3577 00:59:19.637748
3578 00:59:19.637810 ==
3579 00:59:19.640929 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 00:59:19.644251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 00:59:19.644332 ==
3582 00:59:19.647632 RX Vref Scan: 0
3583 00:59:19.647711
3584 00:59:19.647773 RX Vref 0 -> 0, step: 1
3585 00:59:19.647832
3586 00:59:19.650547 RX Delay -13 -> 252, step: 4
3587 00:59:19.657769 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3588 00:59:19.660355 iDelay=195, Bit 1, Center 114 (47 ~ 182) 136
3589 00:59:19.664054 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3590 00:59:19.667429 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3591 00:59:19.670745 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3592 00:59:19.677036 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3593 00:59:19.680150 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3594 00:59:19.683497 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3595 00:59:19.687487 iDelay=195, Bit 8, Center 102 (43 ~ 162) 120
3596 00:59:19.690119 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3597 00:59:19.696646 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3598 00:59:19.699974 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3599 00:59:19.703329 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3600 00:59:19.707356 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3601 00:59:19.713386 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3602 00:59:19.716934 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3603 00:59:19.717014 ==
3604 00:59:19.719910 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 00:59:19.722999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 00:59:19.723105 ==
3607 00:59:19.726218 DQS Delay:
3608 00:59:19.726299 DQS0 = 0, DQS1 = 0
3609 00:59:19.726362 DQM Delay:
3610 00:59:19.729427 DQM0 = 116, DQM1 = 114
3611 00:59:19.729507 DQ Delay:
3612 00:59:19.732803 DQ0 =118, DQ1 =114, DQ2 =108, DQ3 =114
3613 00:59:19.736106 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =114
3614 00:59:19.742861 DQ8 =102, DQ9 =104, DQ10 =116, DQ11 =108
3615 00:59:19.745912 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3616 00:59:19.745996
3617 00:59:19.746059
3618 00:59:19.752525 [DQSOSCAuto] RK1, (LSB)MR18= 0xf406, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
3619 00:59:19.756117 CH1 RK1: MR19=304, MR18=F406
3620 00:59:19.762473 CH1_RK1: MR19=0x304, MR18=0xF406, DQSOSC=407, MR23=63, INC=39, DEC=26
3621 00:59:19.765714 [RxdqsGatingPostProcess] freq 1200
3622 00:59:19.772466 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3623 00:59:19.775713 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 00:59:19.775794 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 00:59:19.778939 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 00:59:19.782301 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 00:59:19.785367 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 00:59:19.788854 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 00:59:19.792135 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 00:59:19.795317 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 00:59:19.798810 Pre-setting of DQS Precalculation
3632 00:59:19.805134 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3633 00:59:19.811685 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3634 00:59:19.818206 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3635 00:59:19.818287
3636 00:59:19.818350
3637 00:59:19.821440 [Calibration Summary] 2400 Mbps
3638 00:59:19.821520 CH 0, Rank 0
3639 00:59:19.825122 SW Impedance : PASS
3640 00:59:19.828082 DUTY Scan : NO K
3641 00:59:19.828163 ZQ Calibration : PASS
3642 00:59:19.831489 Jitter Meter : NO K
3643 00:59:19.834838 CBT Training : PASS
3644 00:59:19.834918 Write leveling : PASS
3645 00:59:19.838245 RX DQS gating : PASS
3646 00:59:19.841487 RX DQ/DQS(RDDQC) : PASS
3647 00:59:19.841567 TX DQ/DQS : PASS
3648 00:59:19.844813 RX DATLAT : PASS
3649 00:59:19.848059 RX DQ/DQS(Engine): PASS
3650 00:59:19.848139 TX OE : NO K
3651 00:59:19.850928 All Pass.
3652 00:59:19.851008
3653 00:59:19.851070 CH 0, Rank 1
3654 00:59:19.854278 SW Impedance : PASS
3655 00:59:19.854358 DUTY Scan : NO K
3656 00:59:19.857569 ZQ Calibration : PASS
3657 00:59:19.861065 Jitter Meter : NO K
3658 00:59:19.861145 CBT Training : PASS
3659 00:59:19.864368 Write leveling : PASS
3660 00:59:19.867590 RX DQS gating : PASS
3661 00:59:19.867670 RX DQ/DQS(RDDQC) : PASS
3662 00:59:19.871186 TX DQ/DQS : PASS
3663 00:59:19.874045 RX DATLAT : PASS
3664 00:59:19.874125 RX DQ/DQS(Engine): PASS
3665 00:59:19.877380 TX OE : NO K
3666 00:59:19.877460 All Pass.
3667 00:59:19.877522
3668 00:59:19.880748 CH 1, Rank 0
3669 00:59:19.880828 SW Impedance : PASS
3670 00:59:19.884303 DUTY Scan : NO K
3671 00:59:19.887565 ZQ Calibration : PASS
3672 00:59:19.887650 Jitter Meter : NO K
3673 00:59:19.890746 CBT Training : PASS
3674 00:59:19.893825 Write leveling : PASS
3675 00:59:19.893930 RX DQS gating : PASS
3676 00:59:19.897374 RX DQ/DQS(RDDQC) : PASS
3677 00:59:19.897454 TX DQ/DQS : PASS
3678 00:59:19.900799 RX DATLAT : PASS
3679 00:59:19.903872 RX DQ/DQS(Engine): PASS
3680 00:59:19.903980 TX OE : NO K
3681 00:59:19.907434 All Pass.
3682 00:59:19.907539
3683 00:59:19.907629 CH 1, Rank 1
3684 00:59:19.910457 SW Impedance : PASS
3685 00:59:19.910537 DUTY Scan : NO K
3686 00:59:19.913682 ZQ Calibration : PASS
3687 00:59:19.916925 Jitter Meter : NO K
3688 00:59:19.917005 CBT Training : PASS
3689 00:59:19.920413 Write leveling : PASS
3690 00:59:19.923582 RX DQS gating : PASS
3691 00:59:19.923662 RX DQ/DQS(RDDQC) : PASS
3692 00:59:19.926831 TX DQ/DQS : PASS
3693 00:59:19.930073 RX DATLAT : PASS
3694 00:59:19.930153 RX DQ/DQS(Engine): PASS
3695 00:59:19.933513 TX OE : NO K
3696 00:59:19.933593 All Pass.
3697 00:59:19.933656
3698 00:59:19.937136 DramC Write-DBI off
3699 00:59:19.939979 PER_BANK_REFRESH: Hybrid Mode
3700 00:59:19.940059 TX_TRACKING: ON
3701 00:59:19.949640 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3702 00:59:19.952672 [FAST_K] Save calibration result to emmc
3703 00:59:19.955974 dramc_set_vcore_voltage set vcore to 650000
3704 00:59:19.959443 Read voltage for 600, 5
3705 00:59:19.959523 Vio18 = 0
3706 00:59:19.962636 Vcore = 650000
3707 00:59:19.962716 Vdram = 0
3708 00:59:19.962779 Vddq = 0
3709 00:59:19.962837 Vmddr = 0
3710 00:59:19.969247 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3711 00:59:19.976137 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3712 00:59:19.976218 MEM_TYPE=3, freq_sel=19
3713 00:59:19.979324 sv_algorithm_assistance_LP4_1600
3714 00:59:19.982446 ============ PULL DRAM RESETB DOWN ============
3715 00:59:19.988939 ========== PULL DRAM RESETB DOWN end =========
3716 00:59:19.992507 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3717 00:59:19.995851 ===================================
3718 00:59:19.998662 LPDDR4 DRAM CONFIGURATION
3719 00:59:20.001829 ===================================
3720 00:59:20.001910 EX_ROW_EN[0] = 0x0
3721 00:59:20.005576 EX_ROW_EN[1] = 0x0
3722 00:59:20.008818 LP4Y_EN = 0x0
3723 00:59:20.008944 WORK_FSP = 0x0
3724 00:59:20.012135 WL = 0x2
3725 00:59:20.012215 RL = 0x2
3726 00:59:20.015612 BL = 0x2
3727 00:59:20.015692 RPST = 0x0
3728 00:59:20.018363 RD_PRE = 0x0
3729 00:59:20.018446 WR_PRE = 0x1
3730 00:59:20.021563 WR_PST = 0x0
3731 00:59:20.021644 DBI_WR = 0x0
3732 00:59:20.024977 DBI_RD = 0x0
3733 00:59:20.025060 OTF = 0x1
3734 00:59:20.028624 ===================================
3735 00:59:20.031492 ===================================
3736 00:59:20.034634 ANA top config
3737 00:59:20.038053 ===================================
3738 00:59:20.041820 DLL_ASYNC_EN = 0
3739 00:59:20.041900 ALL_SLAVE_EN = 1
3740 00:59:20.044809 NEW_RANK_MODE = 1
3741 00:59:20.048062 DLL_IDLE_MODE = 1
3742 00:59:20.051352 LP45_APHY_COMB_EN = 1
3743 00:59:20.051469 TX_ODT_DIS = 1
3744 00:59:20.054543 NEW_8X_MODE = 1
3745 00:59:20.057897 ===================================
3746 00:59:20.061252 ===================================
3747 00:59:20.065045 data_rate = 1200
3748 00:59:20.067806 CKR = 1
3749 00:59:20.071488 DQ_P2S_RATIO = 8
3750 00:59:20.074435 ===================================
3751 00:59:20.078002 CA_P2S_RATIO = 8
3752 00:59:20.078082 DQ_CA_OPEN = 0
3753 00:59:20.081238 DQ_SEMI_OPEN = 0
3754 00:59:20.084682 CA_SEMI_OPEN = 0
3755 00:59:20.087634 CA_FULL_RATE = 0
3756 00:59:20.091038 DQ_CKDIV4_EN = 1
3757 00:59:20.094183 CA_CKDIV4_EN = 1
3758 00:59:20.094263 CA_PREDIV_EN = 0
3759 00:59:20.097777 PH8_DLY = 0
3760 00:59:20.100618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3761 00:59:20.103953 DQ_AAMCK_DIV = 4
3762 00:59:20.107250 CA_AAMCK_DIV = 4
3763 00:59:20.111051 CA_ADMCK_DIV = 4
3764 00:59:20.113929 DQ_TRACK_CA_EN = 0
3765 00:59:20.114010 CA_PICK = 600
3766 00:59:20.117139 CA_MCKIO = 600
3767 00:59:20.120429 MCKIO_SEMI = 0
3768 00:59:20.124188 PLL_FREQ = 2288
3769 00:59:20.127832 DQ_UI_PI_RATIO = 32
3770 00:59:20.130368 CA_UI_PI_RATIO = 0
3771 00:59:20.133733 ===================================
3772 00:59:20.137310 ===================================
3773 00:59:20.140269 memory_type:LPDDR4
3774 00:59:20.140349 GP_NUM : 10
3775 00:59:20.143647 SRAM_EN : 1
3776 00:59:20.143731 MD32_EN : 0
3777 00:59:20.147039 ===================================
3778 00:59:20.150267 [ANA_INIT] >>>>>>>>>>>>>>
3779 00:59:20.153193 <<<<<< [CONFIGURE PHASE]: ANA_TX
3780 00:59:20.156985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3781 00:59:20.159863 ===================================
3782 00:59:20.163388 data_rate = 1200,PCW = 0X5800
3783 00:59:20.166970 ===================================
3784 00:59:20.169676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3785 00:59:20.176555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3786 00:59:20.180169 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 00:59:20.186252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3788 00:59:20.189506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3789 00:59:20.192806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3790 00:59:20.192887 [ANA_INIT] flow start
3791 00:59:20.196170 [ANA_INIT] PLL >>>>>>>>
3792 00:59:20.199705 [ANA_INIT] PLL <<<<<<<<
3793 00:59:20.199784 [ANA_INIT] MIDPI >>>>>>>>
3794 00:59:20.202620 [ANA_INIT] MIDPI <<<<<<<<
3795 00:59:20.205838 [ANA_INIT] DLL >>>>>>>>
3796 00:59:20.205918 [ANA_INIT] flow end
3797 00:59:20.212722 ============ LP4 DIFF to SE enter ============
3798 00:59:20.215929 ============ LP4 DIFF to SE exit ============
3799 00:59:20.219032 [ANA_INIT] <<<<<<<<<<<<<
3800 00:59:20.222717 [Flow] Enable top DCM control >>>>>
3801 00:59:20.225772 [Flow] Enable top DCM control <<<<<
3802 00:59:20.229057 Enable DLL master slave shuffle
3803 00:59:20.232731 ==============================================================
3804 00:59:20.235943 Gating Mode config
3805 00:59:20.238888 ==============================================================
3806 00:59:20.242528 Config description:
3807 00:59:20.252295 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3808 00:59:20.258537 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3809 00:59:20.262021 SELPH_MODE 0: By rank 1: By Phase
3810 00:59:20.268487 ==============================================================
3811 00:59:20.272116 GAT_TRACK_EN = 1
3812 00:59:20.275253 RX_GATING_MODE = 2
3813 00:59:20.278389 RX_GATING_TRACK_MODE = 2
3814 00:59:20.282341 SELPH_MODE = 1
3815 00:59:20.285148 PICG_EARLY_EN = 1
3816 00:59:20.288674 VALID_LAT_VALUE = 1
3817 00:59:20.291747 ==============================================================
3818 00:59:20.294977 Enter into Gating configuration >>>>
3819 00:59:20.298145 Exit from Gating configuration <<<<
3820 00:59:20.302002 Enter into DVFS_PRE_config >>>>>
3821 00:59:20.314283 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3822 00:59:20.318142 Exit from DVFS_PRE_config <<<<<
3823 00:59:20.318222 Enter into PICG configuration >>>>
3824 00:59:20.321243 Exit from PICG configuration <<<<
3825 00:59:20.324619 [RX_INPUT] configuration >>>>>
3826 00:59:20.327838 [RX_INPUT] configuration <<<<<
3827 00:59:20.334231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3828 00:59:20.337586 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3829 00:59:20.344154 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3830 00:59:20.350869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3831 00:59:20.357561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 00:59:20.364098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 00:59:20.367303 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3834 00:59:20.370935 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3835 00:59:20.377201 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3836 00:59:20.380290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3837 00:59:20.384039 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3838 00:59:20.387177 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3839 00:59:20.390223 ===================================
3840 00:59:20.393640 LPDDR4 DRAM CONFIGURATION
3841 00:59:20.397132 ===================================
3842 00:59:20.400235 EX_ROW_EN[0] = 0x0
3843 00:59:20.400313 EX_ROW_EN[1] = 0x0
3844 00:59:20.403660 LP4Y_EN = 0x0
3845 00:59:20.403756 WORK_FSP = 0x0
3846 00:59:20.407206 WL = 0x2
3847 00:59:20.407301 RL = 0x2
3848 00:59:20.410330 BL = 0x2
3849 00:59:20.413125 RPST = 0x0
3850 00:59:20.413229 RD_PRE = 0x0
3851 00:59:20.416554 WR_PRE = 0x1
3852 00:59:20.416654 WR_PST = 0x0
3853 00:59:20.419552 DBI_WR = 0x0
3854 00:59:20.419648 DBI_RD = 0x0
3855 00:59:20.423262 OTF = 0x1
3856 00:59:20.426435 ===================================
3857 00:59:20.429477 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3858 00:59:20.432857 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3859 00:59:20.439462 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 00:59:20.442964 ===================================
3861 00:59:20.443045 LPDDR4 DRAM CONFIGURATION
3862 00:59:20.446884 ===================================
3863 00:59:20.449808 EX_ROW_EN[0] = 0x10
3864 00:59:20.449888 EX_ROW_EN[1] = 0x0
3865 00:59:20.453094 LP4Y_EN = 0x0
3866 00:59:20.453174 WORK_FSP = 0x0
3867 00:59:20.456292 WL = 0x2
3868 00:59:20.459372 RL = 0x2
3869 00:59:20.459484 BL = 0x2
3870 00:59:20.462635 RPST = 0x0
3871 00:59:20.462715 RD_PRE = 0x0
3872 00:59:20.466273 WR_PRE = 0x1
3873 00:59:20.466353 WR_PST = 0x0
3874 00:59:20.469328 DBI_WR = 0x0
3875 00:59:20.469408 DBI_RD = 0x0
3876 00:59:20.472642 OTF = 0x1
3877 00:59:20.476143 ===================================
3878 00:59:20.482359 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3879 00:59:20.485662 nWR fixed to 30
3880 00:59:20.485746 [ModeRegInit_LP4] CH0 RK0
3881 00:59:20.488992 [ModeRegInit_LP4] CH0 RK1
3882 00:59:20.492619 [ModeRegInit_LP4] CH1 RK0
3883 00:59:20.492702 [ModeRegInit_LP4] CH1 RK1
3884 00:59:20.495531 match AC timing 17
3885 00:59:20.498990 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3886 00:59:20.506126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3887 00:59:20.509152 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3888 00:59:20.512021 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3889 00:59:20.518928 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3890 00:59:20.519033 ==
3891 00:59:20.521860 Dram Type= 6, Freq= 0, CH_0, rank 0
3892 00:59:20.525540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3893 00:59:20.525621 ==
3894 00:59:20.532122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3895 00:59:20.538847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3896 00:59:20.541956 [CA 0] Center 36 (6~67) winsize 62
3897 00:59:20.545098 [CA 1] Center 36 (5~67) winsize 63
3898 00:59:20.548314 [CA 2] Center 34 (4~65) winsize 62
3899 00:59:20.551621 [CA 3] Center 34 (4~65) winsize 62
3900 00:59:20.554993 [CA 4] Center 33 (3~64) winsize 62
3901 00:59:20.558401 [CA 5] Center 33 (2~64) winsize 63
3902 00:59:20.558482
3903 00:59:20.561567 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3904 00:59:20.561647
3905 00:59:20.565225 [CATrainingPosCal] consider 1 rank data
3906 00:59:20.568661 u2DelayCellTimex100 = 270/100 ps
3907 00:59:20.571281 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3908 00:59:20.575055 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3909 00:59:20.578389 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3910 00:59:20.581406 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3911 00:59:20.584860 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3912 00:59:20.587919 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3913 00:59:20.591129
3914 00:59:20.594675 CA PerBit enable=1, Macro0, CA PI delay=33
3915 00:59:20.594755
3916 00:59:20.597967 [CBTSetCACLKResult] CA Dly = 33
3917 00:59:20.598048 CS Dly: 5 (0~36)
3918 00:59:20.598111 ==
3919 00:59:20.600854 Dram Type= 6, Freq= 0, CH_0, rank 1
3920 00:59:20.604321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3921 00:59:20.607710 ==
3922 00:59:20.610844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3923 00:59:20.617549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3924 00:59:20.620740 [CA 0] Center 36 (6~67) winsize 62
3925 00:59:20.623968 [CA 1] Center 36 (6~67) winsize 62
3926 00:59:20.627726 [CA 2] Center 34 (4~65) winsize 62
3927 00:59:20.631019 [CA 3] Center 34 (3~65) winsize 63
3928 00:59:20.634117 [CA 4] Center 34 (3~65) winsize 63
3929 00:59:20.637304 [CA 5] Center 33 (3~64) winsize 62
3930 00:59:20.637385
3931 00:59:20.640798 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3932 00:59:20.640879
3933 00:59:20.643667 [CATrainingPosCal] consider 2 rank data
3934 00:59:20.647315 u2DelayCellTimex100 = 270/100 ps
3935 00:59:20.650763 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 00:59:20.653598 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 00:59:20.661251 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3938 00:59:20.663813 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 00:59:20.666751 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 00:59:20.670334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 00:59:20.670415
3942 00:59:20.673518 CA PerBit enable=1, Macro0, CA PI delay=33
3943 00:59:20.673604
3944 00:59:20.676517 [CBTSetCACLKResult] CA Dly = 33
3945 00:59:20.676590 CS Dly: 5 (0~36)
3946 00:59:20.676652
3947 00:59:20.679959 ----->DramcWriteLeveling(PI) begin...
3948 00:59:20.683268 ==
3949 00:59:20.686652 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 00:59:20.690642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 00:59:20.690723 ==
3952 00:59:20.693446 Write leveling (Byte 0): 33 => 33
3953 00:59:20.696959 Write leveling (Byte 1): 29 => 29
3954 00:59:20.700528 DramcWriteLeveling(PI) end<-----
3955 00:59:20.700607
3956 00:59:20.700670 ==
3957 00:59:20.703078 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 00:59:20.706410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 00:59:20.706490 ==
3960 00:59:20.710044 [Gating] SW mode calibration
3961 00:59:20.716386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3962 00:59:20.722879 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3963 00:59:20.726642 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3964 00:59:20.729375 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 00:59:20.736213 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 00:59:20.739310 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
3967 00:59:20.742558 0 9 16 | B1->B0 | 2e2e 2424 | 1 1 | (1 0) (0 0)
3968 00:59:20.749508 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 00:59:20.752701 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 00:59:20.755981 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 00:59:20.762486 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 00:59:20.766193 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 00:59:20.768937 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 00:59:20.775454 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3975 00:59:20.778730 0 10 16 | B1->B0 | 3939 4343 | 0 1 | (1 1) (0 0)
3976 00:59:20.782120 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 00:59:20.788691 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 00:59:20.792219 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 00:59:20.795224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 00:59:20.802218 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 00:59:20.804756 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 00:59:20.808559 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 00:59:20.814819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 00:59:20.818214 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 00:59:20.821515 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 00:59:20.828019 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 00:59:20.831229 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 00:59:20.834666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 00:59:20.840951 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 00:59:20.844578 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 00:59:20.847552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 00:59:20.854254 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 00:59:20.857573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 00:59:20.860749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 00:59:20.867854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 00:59:20.871295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 00:59:20.874695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 00:59:20.880371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3999 00:59:20.883912 Total UI for P1: 0, mck2ui 16
4000 00:59:20.886943 best dqsien dly found for B0: ( 0, 13, 10)
4001 00:59:20.890573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4002 00:59:20.893705 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:59:20.897309 Total UI for P1: 0, mck2ui 16
4004 00:59:20.900368 best dqsien dly found for B1: ( 0, 13, 16)
4005 00:59:20.903913 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4006 00:59:20.910501 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4007 00:59:20.910581
4008 00:59:20.913353 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4009 00:59:20.917348 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4010 00:59:20.919973 [Gating] SW calibration Done
4011 00:59:20.920053 ==
4012 00:59:20.923208 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 00:59:20.927021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 00:59:20.927102 ==
4015 00:59:20.930038 RX Vref Scan: 0
4016 00:59:20.930117
4017 00:59:20.930179 RX Vref 0 -> 0, step: 1
4018 00:59:20.930237
4019 00:59:20.934643 RX Delay -230 -> 252, step: 16
4020 00:59:20.936973 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4021 00:59:20.943593 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4022 00:59:20.946265 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4023 00:59:20.949992 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4024 00:59:20.953000 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4025 00:59:20.959897 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4026 00:59:20.962859 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4027 00:59:20.966138 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4028 00:59:20.969449 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4029 00:59:20.973172 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4030 00:59:20.980060 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4031 00:59:20.983129 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4032 00:59:20.986146 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4033 00:59:20.992971 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4034 00:59:20.995788 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4035 00:59:20.999534 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4036 00:59:20.999620 ==
4037 00:59:21.002765 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 00:59:21.005855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 00:59:21.005934 ==
4040 00:59:21.009308 DQS Delay:
4041 00:59:21.009388 DQS0 = 0, DQS1 = 0
4042 00:59:21.012693 DQM Delay:
4043 00:59:21.012772 DQM0 = 43, DQM1 = 34
4044 00:59:21.012835 DQ Delay:
4045 00:59:21.015913 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4046 00:59:21.018915 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4047 00:59:21.022554 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =33
4048 00:59:21.025819 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4049 00:59:21.025899
4050 00:59:21.028657
4051 00:59:21.028737 ==
4052 00:59:21.032538 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 00:59:21.035556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 00:59:21.035636 ==
4055 00:59:21.035707
4056 00:59:21.035771
4057 00:59:21.038462 TX Vref Scan disable
4058 00:59:21.038542 == TX Byte 0 ==
4059 00:59:21.045517 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4060 00:59:21.048378 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4061 00:59:21.048458 == TX Byte 1 ==
4062 00:59:21.055873 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4063 00:59:21.058660 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4064 00:59:21.058740 ==
4065 00:59:21.062186 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 00:59:21.065208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 00:59:21.065288 ==
4068 00:59:21.065351
4069 00:59:21.065408
4070 00:59:21.068065 TX Vref Scan disable
4071 00:59:21.071576 == TX Byte 0 ==
4072 00:59:21.074971 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4073 00:59:21.081507 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4074 00:59:21.081605 == TX Byte 1 ==
4075 00:59:21.084855 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4076 00:59:21.091509 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4077 00:59:21.091592
4078 00:59:21.091656 [DATLAT]
4079 00:59:21.091714 Freq=600, CH0 RK0
4080 00:59:21.091773
4081 00:59:21.094612 DATLAT Default: 0x9
4082 00:59:21.098244 0, 0xFFFF, sum = 0
4083 00:59:21.098327 1, 0xFFFF, sum = 0
4084 00:59:21.101040 2, 0xFFFF, sum = 0
4085 00:59:21.101123 3, 0xFFFF, sum = 0
4086 00:59:21.104454 4, 0xFFFF, sum = 0
4087 00:59:21.104536 5, 0xFFFF, sum = 0
4088 00:59:21.107599 6, 0xFFFF, sum = 0
4089 00:59:21.107680 7, 0xFFFF, sum = 0
4090 00:59:21.110916 8, 0x0, sum = 1
4091 00:59:21.111027 9, 0x0, sum = 2
4092 00:59:21.114323 10, 0x0, sum = 3
4093 00:59:21.114405 11, 0x0, sum = 4
4094 00:59:21.114470 best_step = 9
4095 00:59:21.114530
4096 00:59:21.117588 ==
4097 00:59:21.120773 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 00:59:21.124533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 00:59:21.124615 ==
4100 00:59:21.124679 RX Vref Scan: 1
4101 00:59:21.124739
4102 00:59:21.128204 RX Vref 0 -> 0, step: 1
4103 00:59:21.128285
4104 00:59:21.130806 RX Delay -195 -> 252, step: 8
4105 00:59:21.130887
4106 00:59:21.134053 Set Vref, RX VrefLevel [Byte0]: 54
4107 00:59:21.137459 [Byte1]: 59
4108 00:59:21.140596
4109 00:59:21.140677 Final RX Vref Byte 0 = 54 to rank0
4110 00:59:21.144060 Final RX Vref Byte 1 = 59 to rank0
4111 00:59:21.147323 Final RX Vref Byte 0 = 54 to rank1
4112 00:59:21.150639 Final RX Vref Byte 1 = 59 to rank1==
4113 00:59:21.153805 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 00:59:21.160165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 00:59:21.160247 ==
4116 00:59:21.160312 DQS Delay:
4117 00:59:21.163833 DQS0 = 0, DQS1 = 0
4118 00:59:21.163915 DQM Delay:
4119 00:59:21.163978 DQM0 = 42, DQM1 = 33
4120 00:59:21.166893 DQ Delay:
4121 00:59:21.170011 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4122 00:59:21.173218 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4123 00:59:21.176910 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4124 00:59:21.180153 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4125 00:59:21.180234
4126 00:59:21.180298
4127 00:59:21.186748 [DQSOSCAuto] RK0, (LSB)MR18= 0x4941, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4128 00:59:21.189620 CH0 RK0: MR19=808, MR18=4941
4129 00:59:21.196523 CH0_RK0: MR19=0x808, MR18=0x4941, DQSOSC=396, MR23=63, INC=167, DEC=111
4130 00:59:21.196606
4131 00:59:21.200104 ----->DramcWriteLeveling(PI) begin...
4132 00:59:21.200186 ==
4133 00:59:21.202974 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 00:59:21.206543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 00:59:21.206626 ==
4136 00:59:21.209935 Write leveling (Byte 0): 36 => 36
4137 00:59:21.213581 Write leveling (Byte 1): 30 => 30
4138 00:59:21.216447 DramcWriteLeveling(PI) end<-----
4139 00:59:21.216528
4140 00:59:21.216592 ==
4141 00:59:21.219931 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 00:59:21.222900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 00:59:21.226182 ==
4144 00:59:21.226263 [Gating] SW mode calibration
4145 00:59:21.236585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4146 00:59:21.239243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4147 00:59:21.243120 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 00:59:21.249361 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 00:59:21.252562 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 00:59:21.255908 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 1)
4151 00:59:21.262463 0 9 16 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
4152 00:59:21.266106 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 00:59:21.268858 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 00:59:21.275355 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 00:59:21.278855 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 00:59:21.282192 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 00:59:21.288705 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 00:59:21.291873 0 10 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
4159 00:59:21.295178 0 10 16 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
4160 00:59:21.301741 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 00:59:21.305132 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 00:59:21.308432 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 00:59:21.315002 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 00:59:21.318691 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 00:59:21.321707 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4166 00:59:21.328030 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 00:59:21.331627 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4168 00:59:21.335061 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 00:59:21.341754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 00:59:21.344469 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 00:59:21.347777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 00:59:21.354331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 00:59:21.357999 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 00:59:21.361553 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 00:59:21.367845 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 00:59:21.371206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 00:59:21.374682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 00:59:21.381244 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 00:59:21.384085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 00:59:21.387800 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 00:59:21.394410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 00:59:21.397692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4183 00:59:21.401277 Total UI for P1: 0, mck2ui 16
4184 00:59:21.404125 best dqsien dly found for B0: ( 0, 13, 10)
4185 00:59:21.407434 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4186 00:59:21.414241 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:59:21.417222 Total UI for P1: 0, mck2ui 16
4188 00:59:21.420524 best dqsien dly found for B1: ( 0, 13, 16)
4189 00:59:21.423768 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4190 00:59:21.427378 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4191 00:59:21.427478
4192 00:59:21.430720 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4193 00:59:21.433786 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4194 00:59:21.437005 [Gating] SW calibration Done
4195 00:59:21.437087 ==
4196 00:59:21.440496 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 00:59:21.443624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 00:59:21.443707 ==
4199 00:59:21.446719 RX Vref Scan: 0
4200 00:59:21.446801
4201 00:59:21.450102 RX Vref 0 -> 0, step: 1
4202 00:59:21.450183
4203 00:59:21.453714 RX Delay -230 -> 252, step: 16
4204 00:59:21.457109 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4205 00:59:21.459963 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4206 00:59:21.463351 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4207 00:59:21.466862 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4208 00:59:21.473097 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4209 00:59:21.476372 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4210 00:59:21.479589 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4211 00:59:21.483012 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4212 00:59:21.489814 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4213 00:59:21.492886 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4214 00:59:21.496118 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4215 00:59:21.499600 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4216 00:59:21.505957 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4217 00:59:21.509274 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4218 00:59:21.512694 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4219 00:59:21.515869 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4220 00:59:21.519222 ==
4221 00:59:21.522114 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 00:59:21.525940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 00:59:21.526022 ==
4224 00:59:21.526085 DQS Delay:
4225 00:59:21.529062 DQS0 = 0, DQS1 = 0
4226 00:59:21.529143 DQM Delay:
4227 00:59:21.532396 DQM0 = 48, DQM1 = 32
4228 00:59:21.532478 DQ Delay:
4229 00:59:21.535887 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =49
4230 00:59:21.539116 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4231 00:59:21.541867 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4232 00:59:21.545505 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =33
4233 00:59:21.545586
4234 00:59:21.545649
4235 00:59:21.545708 ==
4236 00:59:21.548593 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 00:59:21.552085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 00:59:21.552170 ==
4239 00:59:21.552234
4240 00:59:21.555313
4241 00:59:21.555417 TX Vref Scan disable
4242 00:59:21.558382 == TX Byte 0 ==
4243 00:59:21.561875 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4244 00:59:21.565373 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4245 00:59:21.568350 == TX Byte 1 ==
4246 00:59:21.571544 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4247 00:59:21.574548 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4248 00:59:21.578231 ==
4249 00:59:21.581477 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 00:59:21.584441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 00:59:21.584523 ==
4252 00:59:21.584586
4253 00:59:21.584645
4254 00:59:21.588108 TX Vref Scan disable
4255 00:59:21.591128 == TX Byte 0 ==
4256 00:59:21.594255 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4257 00:59:21.597683 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4258 00:59:21.600821 == TX Byte 1 ==
4259 00:59:21.604722 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4260 00:59:21.607522 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4261 00:59:21.607604
4262 00:59:21.607667 [DATLAT]
4263 00:59:21.610679 Freq=600, CH0 RK1
4264 00:59:21.610760
4265 00:59:21.614317 DATLAT Default: 0x9
4266 00:59:21.614399 0, 0xFFFF, sum = 0
4267 00:59:21.617451 1, 0xFFFF, sum = 0
4268 00:59:21.617534 2, 0xFFFF, sum = 0
4269 00:59:21.620936 3, 0xFFFF, sum = 0
4270 00:59:21.621019 4, 0xFFFF, sum = 0
4271 00:59:21.624274 5, 0xFFFF, sum = 0
4272 00:59:21.624357 6, 0xFFFF, sum = 0
4273 00:59:21.627302 7, 0xFFFF, sum = 0
4274 00:59:21.627412 8, 0x0, sum = 1
4275 00:59:21.630664 9, 0x0, sum = 2
4276 00:59:21.630747 10, 0x0, sum = 3
4277 00:59:21.633653 11, 0x0, sum = 4
4278 00:59:21.633736 best_step = 9
4279 00:59:21.633798
4280 00:59:21.633858 ==
4281 00:59:21.637422 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 00:59:21.640872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 00:59:21.640953 ==
4284 00:59:21.644136 RX Vref Scan: 0
4285 00:59:21.644218
4286 00:59:21.647007 RX Vref 0 -> 0, step: 1
4287 00:59:21.647088
4288 00:59:21.647152 RX Delay -195 -> 252, step: 8
4289 00:59:21.655095 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4290 00:59:21.658283 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4291 00:59:21.662247 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4292 00:59:21.664840 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4293 00:59:21.671700 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4294 00:59:21.674946 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4295 00:59:21.678590 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4296 00:59:21.682088 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4297 00:59:21.687931 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4298 00:59:21.691274 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4299 00:59:21.694696 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4300 00:59:21.697845 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4301 00:59:21.704816 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4302 00:59:21.707676 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4303 00:59:21.711321 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4304 00:59:21.714274 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4305 00:59:21.714356 ==
4306 00:59:21.717644 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 00:59:21.724439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 00:59:21.724537 ==
4309 00:59:21.724600 DQS Delay:
4310 00:59:21.727521 DQS0 = 0, DQS1 = 0
4311 00:59:21.727631 DQM Delay:
4312 00:59:21.731007 DQM0 = 41, DQM1 = 33
4313 00:59:21.731111 DQ Delay:
4314 00:59:21.733919 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4315 00:59:21.737968 DQ4 =44, DQ5 =32, DQ6 =56, DQ7 =44
4316 00:59:21.740874 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4317 00:59:21.744275 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4318 00:59:21.744391
4319 00:59:21.744455
4320 00:59:21.750465 [DQSOSCAuto] RK1, (LSB)MR18= 0x413c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4321 00:59:21.753872 CH0 RK1: MR19=808, MR18=413C
4322 00:59:21.760419 CH0_RK1: MR19=0x808, MR18=0x413C, DQSOSC=397, MR23=63, INC=166, DEC=110
4323 00:59:21.763690 [RxdqsGatingPostProcess] freq 600
4324 00:59:21.769959 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 00:59:21.773805 Pre-setting of DQS Precalculation
4326 00:59:21.777429 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 00:59:21.777510 ==
4328 00:59:21.780117 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 00:59:21.783404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 00:59:21.783486 ==
4331 00:59:21.789889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 00:59:21.796614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4333 00:59:21.799910 [CA 0] Center 35 (5~66) winsize 62
4334 00:59:21.803269 [CA 1] Center 35 (5~66) winsize 62
4335 00:59:21.806842 [CA 2] Center 34 (4~65) winsize 62
4336 00:59:21.809629 [CA 3] Center 34 (3~65) winsize 63
4337 00:59:21.813211 [CA 4] Center 34 (4~65) winsize 62
4338 00:59:21.816361 [CA 5] Center 34 (3~65) winsize 63
4339 00:59:21.816442
4340 00:59:21.819910 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4341 00:59:21.819991
4342 00:59:21.822981 [CATrainingPosCal] consider 1 rank data
4343 00:59:21.826197 u2DelayCellTimex100 = 270/100 ps
4344 00:59:21.829914 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4345 00:59:21.832668 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4346 00:59:21.836285 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4347 00:59:21.839656 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4348 00:59:21.842730 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4349 00:59:21.849465 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4350 00:59:21.849547
4351 00:59:21.852567 CA PerBit enable=1, Macro0, CA PI delay=34
4352 00:59:21.852647
4353 00:59:21.856172 [CBTSetCACLKResult] CA Dly = 34
4354 00:59:21.856254 CS Dly: 3 (0~34)
4355 00:59:21.856317 ==
4356 00:59:21.859500 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 00:59:21.862904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 00:59:21.865964 ==
4359 00:59:21.869426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 00:59:21.875616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4361 00:59:21.878968 [CA 0] Center 35 (5~66) winsize 62
4362 00:59:21.882219 [CA 1] Center 36 (6~66) winsize 61
4363 00:59:21.885638 [CA 2] Center 34 (4~65) winsize 62
4364 00:59:21.889336 [CA 3] Center 34 (3~65) winsize 63
4365 00:59:21.892298 [CA 4] Center 34 (4~65) winsize 62
4366 00:59:21.895460 [CA 5] Center 33 (3~64) winsize 62
4367 00:59:21.895541
4368 00:59:21.898816 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4369 00:59:21.898898
4370 00:59:21.902655 [CATrainingPosCal] consider 2 rank data
4371 00:59:21.905243 u2DelayCellTimex100 = 270/100 ps
4372 00:59:21.908668 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 00:59:21.911952 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4374 00:59:21.918710 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 00:59:21.921786 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4376 00:59:21.925406 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 00:59:21.928230 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 00:59:21.928311
4379 00:59:21.931606 CA PerBit enable=1, Macro0, CA PI delay=33
4380 00:59:21.931688
4381 00:59:21.934809 [CBTSetCACLKResult] CA Dly = 33
4382 00:59:21.934889 CS Dly: 3 (0~35)
4383 00:59:21.938212
4384 00:59:21.941450 ----->DramcWriteLeveling(PI) begin...
4385 00:59:21.941533 ==
4386 00:59:21.944857 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 00:59:21.948595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 00:59:21.948678 ==
4389 00:59:21.951487 Write leveling (Byte 0): 28 => 28
4390 00:59:21.954625 Write leveling (Byte 1): 28 => 28
4391 00:59:21.957723 DramcWriteLeveling(PI) end<-----
4392 00:59:21.957804
4393 00:59:21.957867 ==
4394 00:59:21.961364 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 00:59:21.964710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 00:59:21.964792 ==
4397 00:59:21.967881 [Gating] SW mode calibration
4398 00:59:21.974445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 00:59:21.980827 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 00:59:21.984010 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 00:59:21.987330 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 00:59:21.993871 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 00:59:21.997370 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 1)
4404 00:59:22.000752 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 00:59:22.007440 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 00:59:22.010640 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 00:59:22.013897 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 00:59:22.020502 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 00:59:22.023631 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 00:59:22.027193 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4411 00:59:22.033703 0 10 12 | B1->B0 | 2d2d 3535 | 1 1 | (0 0) (0 0)
4412 00:59:22.036893 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 00:59:22.040063 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 00:59:22.046684 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 00:59:22.049754 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 00:59:22.053364 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 00:59:22.059865 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 00:59:22.062849 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 00:59:22.069454 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 00:59:22.073145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4421 00:59:22.076033 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 00:59:22.083237 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 00:59:22.086093 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 00:59:22.089370 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 00:59:22.096001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 00:59:22.099190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 00:59:22.102541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 00:59:22.108926 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 00:59:22.112436 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 00:59:22.115333 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 00:59:22.122147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 00:59:22.125367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 00:59:22.128565 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 00:59:22.135442 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 00:59:22.138714 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4436 00:59:22.141670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 00:59:22.145834 Total UI for P1: 0, mck2ui 16
4438 00:59:22.148353 best dqsien dly found for B0: ( 0, 13, 12)
4439 00:59:22.152018 Total UI for P1: 0, mck2ui 16
4440 00:59:22.154913 best dqsien dly found for B1: ( 0, 13, 12)
4441 00:59:22.158431 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4442 00:59:22.161412 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4443 00:59:22.161494
4444 00:59:22.168008 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4445 00:59:22.171224 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4446 00:59:22.175716 [Gating] SW calibration Done
4447 00:59:22.175796 ==
4448 00:59:22.177957 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 00:59:22.181034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 00:59:22.181117 ==
4451 00:59:22.181180 RX Vref Scan: 0
4452 00:59:22.181240
4453 00:59:22.184692 RX Vref 0 -> 0, step: 1
4454 00:59:22.184773
4455 00:59:22.187563 RX Delay -230 -> 252, step: 16
4456 00:59:22.190970 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4457 00:59:22.197858 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4458 00:59:22.200701 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4459 00:59:22.204489 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4460 00:59:22.207751 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4461 00:59:22.210729 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4462 00:59:22.217535 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4463 00:59:22.220886 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4464 00:59:22.224120 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4465 00:59:22.227532 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4466 00:59:22.233869 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4467 00:59:22.237490 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4468 00:59:22.240398 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4469 00:59:22.243751 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4470 00:59:22.250228 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4471 00:59:22.253802 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4472 00:59:22.253884 ==
4473 00:59:22.257030 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 00:59:22.260237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 00:59:22.260319 ==
4476 00:59:22.263204 DQS Delay:
4477 00:59:22.263286 DQS0 = 0, DQS1 = 0
4478 00:59:22.263350 DQM Delay:
4479 00:59:22.266805 DQM0 = 46, DQM1 = 39
4480 00:59:22.266886 DQ Delay:
4481 00:59:22.270016 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4482 00:59:22.273538 DQ4 =41, DQ5 =65, DQ6 =49, DQ7 =41
4483 00:59:22.276643 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4484 00:59:22.279917 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4485 00:59:22.279999
4486 00:59:22.280062
4487 00:59:22.280121 ==
4488 00:59:22.283486 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 00:59:22.289887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 00:59:22.289979 ==
4491 00:59:22.290043
4492 00:59:22.290101
4493 00:59:22.292928 TX Vref Scan disable
4494 00:59:22.293009 == TX Byte 0 ==
4495 00:59:22.296578 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4496 00:59:22.303415 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4497 00:59:22.303497 == TX Byte 1 ==
4498 00:59:22.309561 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 00:59:22.312947 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 00:59:22.313030 ==
4501 00:59:22.316291 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 00:59:22.319819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 00:59:22.319900 ==
4504 00:59:22.319964
4505 00:59:22.320024
4506 00:59:22.322528 TX Vref Scan disable
4507 00:59:22.326339 == TX Byte 0 ==
4508 00:59:22.329445 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4509 00:59:22.332423 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4510 00:59:22.335970 == TX Byte 1 ==
4511 00:59:22.339143 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 00:59:22.342294 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 00:59:22.342375
4514 00:59:22.346117 [DATLAT]
4515 00:59:22.346198 Freq=600, CH1 RK0
4516 00:59:22.346263
4517 00:59:22.348816 DATLAT Default: 0x9
4518 00:59:22.348898 0, 0xFFFF, sum = 0
4519 00:59:22.352359 1, 0xFFFF, sum = 0
4520 00:59:22.352442 2, 0xFFFF, sum = 0
4521 00:59:22.355335 3, 0xFFFF, sum = 0
4522 00:59:22.355483 4, 0xFFFF, sum = 0
4523 00:59:22.358735 5, 0xFFFF, sum = 0
4524 00:59:22.362374 6, 0xFFFF, sum = 0
4525 00:59:22.362457 7, 0xFFFF, sum = 0
4526 00:59:22.362522 8, 0x0, sum = 1
4527 00:59:22.365330 9, 0x0, sum = 2
4528 00:59:22.365412 10, 0x0, sum = 3
4529 00:59:22.368750 11, 0x0, sum = 4
4530 00:59:22.368832 best_step = 9
4531 00:59:22.368896
4532 00:59:22.368955 ==
4533 00:59:22.371811 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 00:59:22.378382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 00:59:22.378464 ==
4536 00:59:22.378528 RX Vref Scan: 1
4537 00:59:22.378587
4538 00:59:22.381765 RX Vref 0 -> 0, step: 1
4539 00:59:22.381846
4540 00:59:22.385097 RX Delay -179 -> 252, step: 8
4541 00:59:22.385178
4542 00:59:22.388297 Set Vref, RX VrefLevel [Byte0]: 52
4543 00:59:22.391466 [Byte1]: 53
4544 00:59:22.391548
4545 00:59:22.395290 Final RX Vref Byte 0 = 52 to rank0
4546 00:59:22.398217 Final RX Vref Byte 1 = 53 to rank0
4547 00:59:22.401422 Final RX Vref Byte 0 = 52 to rank1
4548 00:59:22.404849 Final RX Vref Byte 1 = 53 to rank1==
4549 00:59:22.408114 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 00:59:22.411524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 00:59:22.411606 ==
4552 00:59:22.415274 DQS Delay:
4553 00:59:22.415354 DQS0 = 0, DQS1 = 0
4554 00:59:22.417893 DQM Delay:
4555 00:59:22.417974 DQM0 = 45, DQM1 = 37
4556 00:59:22.418037 DQ Delay:
4557 00:59:22.421400 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4558 00:59:22.424463 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4559 00:59:22.427747 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4560 00:59:22.431062 DQ12 =44, DQ13 =48, DQ14 =44, DQ15 =44
4561 00:59:22.431143
4562 00:59:22.431206
4563 00:59:22.441316 [DQSOSCAuto] RK0, (LSB)MR18= 0x2640, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4564 00:59:22.444727 CH1 RK0: MR19=808, MR18=2640
4565 00:59:22.450785 CH1_RK0: MR19=0x808, MR18=0x2640, DQSOSC=397, MR23=63, INC=166, DEC=110
4566 00:59:22.450867
4567 00:59:22.454268 ----->DramcWriteLeveling(PI) begin...
4568 00:59:22.454352 ==
4569 00:59:22.457628 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 00:59:22.461019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 00:59:22.461101 ==
4572 00:59:22.463900 Write leveling (Byte 0): 29 => 29
4573 00:59:22.467217 Write leveling (Byte 1): 29 => 29
4574 00:59:22.470462 DramcWriteLeveling(PI) end<-----
4575 00:59:22.470543
4576 00:59:22.470606 ==
4577 00:59:22.473911 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 00:59:22.477116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 00:59:22.477198 ==
4580 00:59:22.480824 [Gating] SW mode calibration
4581 00:59:22.486779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4582 00:59:22.493574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4583 00:59:22.496877 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 00:59:22.503265 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 00:59:22.506835 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4586 00:59:22.510223 0 9 12 | B1->B0 | 3131 2a2a | 1 1 | (1 1) (1 0)
4587 00:59:22.516938 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 00:59:22.519823 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 00:59:22.523340 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 00:59:22.530048 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 00:59:22.533680 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 00:59:22.536525 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 00:59:22.543227 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4594 00:59:22.546377 0 10 12 | B1->B0 | 3333 4343 | 0 0 | (0 0) (0 0)
4595 00:59:22.549841 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 00:59:22.556206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 00:59:22.559667 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 00:59:22.562707 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 00:59:22.569513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 00:59:22.572558 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 00:59:22.576091 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4602 00:59:22.582274 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4603 00:59:22.585778 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 00:59:22.588871 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 00:59:22.595645 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 00:59:22.598989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 00:59:22.602184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 00:59:22.608627 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 00:59:22.612101 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 00:59:22.615223 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 00:59:22.621811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 00:59:22.625513 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 00:59:22.628646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 00:59:22.635128 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 00:59:22.638255 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 00:59:22.641814 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 00:59:22.648314 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4618 00:59:22.651731 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 00:59:22.654607 Total UI for P1: 0, mck2ui 16
4620 00:59:22.658176 best dqsien dly found for B0: ( 0, 13, 8)
4621 00:59:22.661626 Total UI for P1: 0, mck2ui 16
4622 00:59:22.664810 best dqsien dly found for B1: ( 0, 13, 10)
4623 00:59:22.667755 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4624 00:59:22.671153 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4625 00:59:22.671233
4626 00:59:22.674677 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4627 00:59:22.678479 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4628 00:59:22.681286 [Gating] SW calibration Done
4629 00:59:22.681382 ==
4630 00:59:22.684362 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 00:59:22.691030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 00:59:22.691115 ==
4633 00:59:22.691178 RX Vref Scan: 0
4634 00:59:22.691237
4635 00:59:22.694500 RX Vref 0 -> 0, step: 1
4636 00:59:22.694611
4637 00:59:22.697598 RX Delay -230 -> 252, step: 16
4638 00:59:22.700618 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4639 00:59:22.703892 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4640 00:59:22.707672 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4641 00:59:22.713710 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4642 00:59:22.717017 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4643 00:59:22.720768 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4644 00:59:22.723898 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4645 00:59:22.730368 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4646 00:59:22.733888 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4647 00:59:22.736852 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4648 00:59:22.740476 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4649 00:59:22.746956 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4650 00:59:22.750090 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4651 00:59:22.753272 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4652 00:59:22.756914 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4653 00:59:22.763349 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4654 00:59:22.763450 ==
4655 00:59:22.766359 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 00:59:22.769941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 00:59:22.770022 ==
4658 00:59:22.770086 DQS Delay:
4659 00:59:22.773722 DQS0 = 0, DQS1 = 0
4660 00:59:22.773803 DQM Delay:
4661 00:59:22.776321 DQM0 = 42, DQM1 = 39
4662 00:59:22.776402 DQ Delay:
4663 00:59:22.779746 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4664 00:59:22.783526 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4665 00:59:22.786715 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4666 00:59:22.789797 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4667 00:59:22.789878
4668 00:59:22.789942
4669 00:59:22.790000 ==
4670 00:59:22.793374 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 00:59:22.796387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 00:59:22.799738 ==
4673 00:59:22.799819
4674 00:59:22.799883
4675 00:59:22.799943 TX Vref Scan disable
4676 00:59:22.802840 == TX Byte 0 ==
4677 00:59:22.806074 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4678 00:59:22.809789 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4679 00:59:22.812575 == TX Byte 1 ==
4680 00:59:22.816063 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4681 00:59:22.819745 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4682 00:59:22.822438 ==
4683 00:59:22.825674 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 00:59:22.828989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 00:59:22.829070 ==
4686 00:59:22.829134
4687 00:59:22.829194
4688 00:59:22.832591 TX Vref Scan disable
4689 00:59:22.835873 == TX Byte 0 ==
4690 00:59:22.839174 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 00:59:22.843266 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 00:59:22.845600 == TX Byte 1 ==
4693 00:59:22.849665 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 00:59:22.852091 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 00:59:22.852173
4696 00:59:22.852236 [DATLAT]
4697 00:59:22.855117 Freq=600, CH1 RK1
4698 00:59:22.855198
4699 00:59:22.858966 DATLAT Default: 0x9
4700 00:59:22.859047 0, 0xFFFF, sum = 0
4701 00:59:22.862031 1, 0xFFFF, sum = 0
4702 00:59:22.862113 2, 0xFFFF, sum = 0
4703 00:59:22.865035 3, 0xFFFF, sum = 0
4704 00:59:22.865117 4, 0xFFFF, sum = 0
4705 00:59:22.868555 5, 0xFFFF, sum = 0
4706 00:59:22.868637 6, 0xFFFF, sum = 0
4707 00:59:22.871866 7, 0xFFFF, sum = 0
4708 00:59:22.871949 8, 0x0, sum = 1
4709 00:59:22.875304 9, 0x0, sum = 2
4710 00:59:22.875408 10, 0x0, sum = 3
4711 00:59:22.878710 11, 0x0, sum = 4
4712 00:59:22.878791 best_step = 9
4713 00:59:22.878855
4714 00:59:22.878914 ==
4715 00:59:22.881527 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 00:59:22.885368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 00:59:22.885450 ==
4718 00:59:22.889463 RX Vref Scan: 0
4719 00:59:22.889543
4720 00:59:22.891807 RX Vref 0 -> 0, step: 1
4721 00:59:22.891888
4722 00:59:22.891952 RX Delay -179 -> 252, step: 8
4723 00:59:22.899339 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4724 00:59:22.902612 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4725 00:59:22.905989 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4726 00:59:22.909190 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4727 00:59:22.915863 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4728 00:59:22.919489 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4729 00:59:22.922902 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4730 00:59:22.926003 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4731 00:59:22.932564 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4732 00:59:22.935704 iDelay=205, Bit 9, Center 28 (-123 ~ 180) 304
4733 00:59:22.939027 iDelay=205, Bit 10, Center 44 (-107 ~ 196) 304
4734 00:59:22.942193 iDelay=205, Bit 11, Center 32 (-123 ~ 188) 312
4735 00:59:22.948799 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4736 00:59:22.952394 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4737 00:59:22.955704 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4738 00:59:22.958765 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4739 00:59:22.958846 ==
4740 00:59:22.962139 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 00:59:22.968520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 00:59:22.968602 ==
4743 00:59:22.968666 DQS Delay:
4744 00:59:22.971689 DQS0 = 0, DQS1 = 0
4745 00:59:22.971770 DQM Delay:
4746 00:59:22.975499 DQM0 = 40, DQM1 = 38
4747 00:59:22.975580 DQ Delay:
4748 00:59:22.978226 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =40
4749 00:59:22.981795 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4750 00:59:22.984851 DQ8 =24, DQ9 =28, DQ10 =44, DQ11 =32
4751 00:59:22.988522 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4752 00:59:22.988604
4753 00:59:22.988667
4754 00:59:22.995152 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d53, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
4755 00:59:22.998673 CH1 RK1: MR19=808, MR18=2D53
4756 00:59:23.005667 CH1_RK1: MR19=0x808, MR18=0x2D53, DQSOSC=394, MR23=63, INC=168, DEC=112
4757 00:59:23.008212 [RxdqsGatingPostProcess] freq 600
4758 00:59:23.014702 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4759 00:59:23.014785 Pre-setting of DQS Precalculation
4760 00:59:23.021664 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4761 00:59:23.027923 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4762 00:59:23.035195 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4763 00:59:23.035277
4764 00:59:23.035341
4765 00:59:23.038435 [Calibration Summary] 1200 Mbps
4766 00:59:23.041351 CH 0, Rank 0
4767 00:59:23.041432 SW Impedance : PASS
4768 00:59:23.044687 DUTY Scan : NO K
4769 00:59:23.048171 ZQ Calibration : PASS
4770 00:59:23.048252 Jitter Meter : NO K
4771 00:59:23.051314 CBT Training : PASS
4772 00:59:23.051443 Write leveling : PASS
4773 00:59:23.054827 RX DQS gating : PASS
4774 00:59:23.058116 RX DQ/DQS(RDDQC) : PASS
4775 00:59:23.058197 TX DQ/DQS : PASS
4776 00:59:23.061257 RX DATLAT : PASS
4777 00:59:23.064616 RX DQ/DQS(Engine): PASS
4778 00:59:23.064697 TX OE : NO K
4779 00:59:23.067747 All Pass.
4780 00:59:23.067827
4781 00:59:23.067891 CH 0, Rank 1
4782 00:59:23.071091 SW Impedance : PASS
4783 00:59:23.071172 DUTY Scan : NO K
4784 00:59:23.074265 ZQ Calibration : PASS
4785 00:59:23.077995 Jitter Meter : NO K
4786 00:59:23.078077 CBT Training : PASS
4787 00:59:23.081109 Write leveling : PASS
4788 00:59:23.084378 RX DQS gating : PASS
4789 00:59:23.084459 RX DQ/DQS(RDDQC) : PASS
4790 00:59:23.087659 TX DQ/DQS : PASS
4791 00:59:23.090595 RX DATLAT : PASS
4792 00:59:23.090675 RX DQ/DQS(Engine): PASS
4793 00:59:23.093910 TX OE : NO K
4794 00:59:23.094015 All Pass.
4795 00:59:23.094101
4796 00:59:23.097151 CH 1, Rank 0
4797 00:59:23.097232 SW Impedance : PASS
4798 00:59:23.100682 DUTY Scan : NO K
4799 00:59:23.104049 ZQ Calibration : PASS
4800 00:59:23.104132 Jitter Meter : NO K
4801 00:59:23.107166 CBT Training : PASS
4802 00:59:23.110490 Write leveling : PASS
4803 00:59:23.110578 RX DQS gating : PASS
4804 00:59:23.113725 RX DQ/DQS(RDDQC) : PASS
4805 00:59:23.116718 TX DQ/DQS : PASS
4806 00:59:23.116797 RX DATLAT : PASS
4807 00:59:23.120148 RX DQ/DQS(Engine): PASS
4808 00:59:23.123328 TX OE : NO K
4809 00:59:23.123466 All Pass.
4810 00:59:23.123560
4811 00:59:23.123621 CH 1, Rank 1
4812 00:59:23.126792 SW Impedance : PASS
4813 00:59:23.129944 DUTY Scan : NO K
4814 00:59:23.130047 ZQ Calibration : PASS
4815 00:59:23.133496 Jitter Meter : NO K
4816 00:59:23.136401 CBT Training : PASS
4817 00:59:23.136474 Write leveling : PASS
4818 00:59:23.139748 RX DQS gating : PASS
4819 00:59:23.143264 RX DQ/DQS(RDDQC) : PASS
4820 00:59:23.143346 TX DQ/DQS : PASS
4821 00:59:23.146678 RX DATLAT : PASS
4822 00:59:23.146759 RX DQ/DQS(Engine): PASS
4823 00:59:23.149593 TX OE : NO K
4824 00:59:23.149674 All Pass.
4825 00:59:23.149738
4826 00:59:23.153050 DramC Write-DBI off
4827 00:59:23.156373 PER_BANK_REFRESH: Hybrid Mode
4828 00:59:23.156454 TX_TRACKING: ON
4829 00:59:23.166071 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4830 00:59:23.169739 [FAST_K] Save calibration result to emmc
4831 00:59:23.173236 dramc_set_vcore_voltage set vcore to 662500
4832 00:59:23.176073 Read voltage for 933, 3
4833 00:59:23.176153 Vio18 = 0
4834 00:59:23.179785 Vcore = 662500
4835 00:59:23.179866 Vdram = 0
4836 00:59:23.179930 Vddq = 0
4837 00:59:23.179989 Vmddr = 0
4838 00:59:23.185887 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4839 00:59:23.192546 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4840 00:59:23.192628 MEM_TYPE=3, freq_sel=17
4841 00:59:23.195781 sv_algorithm_assistance_LP4_1600
4842 00:59:23.198869 ============ PULL DRAM RESETB DOWN ============
4843 00:59:23.205498 ========== PULL DRAM RESETB DOWN end =========
4844 00:59:23.208872 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 00:59:23.212335 ===================================
4846 00:59:23.215308 LPDDR4 DRAM CONFIGURATION
4847 00:59:23.219117 ===================================
4848 00:59:23.219199 EX_ROW_EN[0] = 0x0
4849 00:59:23.222058 EX_ROW_EN[1] = 0x0
4850 00:59:23.225351 LP4Y_EN = 0x0
4851 00:59:23.225431 WORK_FSP = 0x0
4852 00:59:23.228805 WL = 0x3
4853 00:59:23.228886 RL = 0x3
4854 00:59:23.232223 BL = 0x2
4855 00:59:23.232303 RPST = 0x0
4856 00:59:23.235246 RD_PRE = 0x0
4857 00:59:23.235327 WR_PRE = 0x1
4858 00:59:23.239034 WR_PST = 0x0
4859 00:59:23.239164 DBI_WR = 0x0
4860 00:59:23.242650 DBI_RD = 0x0
4861 00:59:23.242770 OTF = 0x1
4862 00:59:23.245212 ===================================
4863 00:59:23.248299 ===================================
4864 00:59:23.251808 ANA top config
4865 00:59:23.255211 ===================================
4866 00:59:23.258616 DLL_ASYNC_EN = 0
4867 00:59:23.258697 ALL_SLAVE_EN = 1
4868 00:59:23.261812 NEW_RANK_MODE = 1
4869 00:59:23.264928 DLL_IDLE_MODE = 1
4870 00:59:23.268182 LP45_APHY_COMB_EN = 1
4871 00:59:23.268256 TX_ODT_DIS = 1
4872 00:59:23.271908 NEW_8X_MODE = 1
4873 00:59:23.274633 ===================================
4874 00:59:23.277893 ===================================
4875 00:59:23.281348 data_rate = 1866
4876 00:59:23.284977 CKR = 1
4877 00:59:23.287742 DQ_P2S_RATIO = 8
4878 00:59:23.291206 ===================================
4879 00:59:23.294293 CA_P2S_RATIO = 8
4880 00:59:23.294374 DQ_CA_OPEN = 0
4881 00:59:23.297476 DQ_SEMI_OPEN = 0
4882 00:59:23.301362 CA_SEMI_OPEN = 0
4883 00:59:23.304524 CA_FULL_RATE = 0
4884 00:59:23.308070 DQ_CKDIV4_EN = 1
4885 00:59:23.310848 CA_CKDIV4_EN = 1
4886 00:59:23.314162 CA_PREDIV_EN = 0
4887 00:59:23.314243 PH8_DLY = 0
4888 00:59:23.317262 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4889 00:59:23.320695 DQ_AAMCK_DIV = 4
4890 00:59:23.324010 CA_AAMCK_DIV = 4
4891 00:59:23.327158 CA_ADMCK_DIV = 4
4892 00:59:23.330860 DQ_TRACK_CA_EN = 0
4893 00:59:23.330942 CA_PICK = 933
4894 00:59:23.334246 CA_MCKIO = 933
4895 00:59:23.337242 MCKIO_SEMI = 0
4896 00:59:23.340187 PLL_FREQ = 3732
4897 00:59:23.343648 DQ_UI_PI_RATIO = 32
4898 00:59:23.346910 CA_UI_PI_RATIO = 0
4899 00:59:23.350714 ===================================
4900 00:59:23.353934 ===================================
4901 00:59:23.357206 memory_type:LPDDR4
4902 00:59:23.357287 GP_NUM : 10
4903 00:59:23.360051 SRAM_EN : 1
4904 00:59:23.360132 MD32_EN : 0
4905 00:59:23.363891 ===================================
4906 00:59:23.366569 [ANA_INIT] >>>>>>>>>>>>>>
4907 00:59:23.370043 <<<<<< [CONFIGURE PHASE]: ANA_TX
4908 00:59:23.373089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4909 00:59:23.377040 ===================================
4910 00:59:23.379494 data_rate = 1866,PCW = 0X8f00
4911 00:59:23.383117 ===================================
4912 00:59:23.386242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4913 00:59:23.393400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4914 00:59:23.396332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 00:59:23.403232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4916 00:59:23.405832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4917 00:59:23.409469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4918 00:59:23.409550 [ANA_INIT] flow start
4919 00:59:23.412864 [ANA_INIT] PLL >>>>>>>>
4920 00:59:23.415900 [ANA_INIT] PLL <<<<<<<<
4921 00:59:23.419340 [ANA_INIT] MIDPI >>>>>>>>
4922 00:59:23.419466 [ANA_INIT] MIDPI <<<<<<<<
4923 00:59:23.422407 [ANA_INIT] DLL >>>>>>>>
4924 00:59:23.422503 [ANA_INIT] flow end
4925 00:59:23.429397 ============ LP4 DIFF to SE enter ============
4926 00:59:23.432783 ============ LP4 DIFF to SE exit ============
4927 00:59:23.435811 [ANA_INIT] <<<<<<<<<<<<<
4928 00:59:23.439159 [Flow] Enable top DCM control >>>>>
4929 00:59:23.442730 [Flow] Enable top DCM control <<<<<
4930 00:59:23.446066 Enable DLL master slave shuffle
4931 00:59:23.448798 ==============================================================
4932 00:59:23.452330 Gating Mode config
4933 00:59:23.458787 ==============================================================
4934 00:59:23.458870 Config description:
4935 00:59:23.468677 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4936 00:59:23.475688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4937 00:59:23.478593 SELPH_MODE 0: By rank 1: By Phase
4938 00:59:23.484939 ==============================================================
4939 00:59:23.488614 GAT_TRACK_EN = 1
4940 00:59:23.491626 RX_GATING_MODE = 2
4941 00:59:23.495206 RX_GATING_TRACK_MODE = 2
4942 00:59:23.498122 SELPH_MODE = 1
4943 00:59:23.501326 PICG_EARLY_EN = 1
4944 00:59:23.504904 VALID_LAT_VALUE = 1
4945 00:59:23.508094 ==============================================================
4946 00:59:23.511077 Enter into Gating configuration >>>>
4947 00:59:23.514773 Exit from Gating configuration <<<<
4948 00:59:23.517799 Enter into DVFS_PRE_config >>>>>
4949 00:59:23.531143 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4950 00:59:23.534463 Exit from DVFS_PRE_config <<<<<
4951 00:59:23.537939 Enter into PICG configuration >>>>
4952 00:59:23.541067 Exit from PICG configuration <<<<
4953 00:59:23.541149 [RX_INPUT] configuration >>>>>
4954 00:59:23.544143 [RX_INPUT] configuration <<<<<
4955 00:59:23.550730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4956 00:59:23.553993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4957 00:59:23.560543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 00:59:23.567027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 00:59:23.573760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 00:59:23.580371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 00:59:23.583576 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4962 00:59:23.587019 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4963 00:59:23.593408 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4964 00:59:23.596731 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4965 00:59:23.599948 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4966 00:59:23.606261 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 00:59:23.609788 ===================================
4968 00:59:23.609869 LPDDR4 DRAM CONFIGURATION
4969 00:59:23.612962 ===================================
4970 00:59:23.616415 EX_ROW_EN[0] = 0x0
4971 00:59:23.619855 EX_ROW_EN[1] = 0x0
4972 00:59:23.619935 LP4Y_EN = 0x0
4973 00:59:23.623107 WORK_FSP = 0x0
4974 00:59:23.623188 WL = 0x3
4975 00:59:23.626474 RL = 0x3
4976 00:59:23.626556 BL = 0x2
4977 00:59:23.629554 RPST = 0x0
4978 00:59:23.629636 RD_PRE = 0x0
4979 00:59:23.632731 WR_PRE = 0x1
4980 00:59:23.632813 WR_PST = 0x0
4981 00:59:23.636420 DBI_WR = 0x0
4982 00:59:23.636501 DBI_RD = 0x0
4983 00:59:23.639425 OTF = 0x1
4984 00:59:23.643021 ===================================
4985 00:59:23.646243 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4986 00:59:23.649299 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4987 00:59:23.656150 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 00:59:23.659240 ===================================
4989 00:59:23.659321 LPDDR4 DRAM CONFIGURATION
4990 00:59:23.662881 ===================================
4991 00:59:23.666234 EX_ROW_EN[0] = 0x10
4992 00:59:23.666315 EX_ROW_EN[1] = 0x0
4993 00:59:23.669523 LP4Y_EN = 0x0
4994 00:59:23.672600 WORK_FSP = 0x0
4995 00:59:23.672681 WL = 0x3
4996 00:59:23.676040 RL = 0x3
4997 00:59:23.676121 BL = 0x2
4998 00:59:23.678937 RPST = 0x0
4999 00:59:23.679017 RD_PRE = 0x0
5000 00:59:23.682445 WR_PRE = 0x1
5001 00:59:23.682526 WR_PST = 0x0
5002 00:59:23.685727 DBI_WR = 0x0
5003 00:59:23.685808 DBI_RD = 0x0
5004 00:59:23.689487 OTF = 0x1
5005 00:59:23.692279 ===================================
5006 00:59:23.698704 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5007 00:59:23.702103 nWR fixed to 30
5008 00:59:23.702188 [ModeRegInit_LP4] CH0 RK0
5009 00:59:23.705586 [ModeRegInit_LP4] CH0 RK1
5010 00:59:23.708907 [ModeRegInit_LP4] CH1 RK0
5011 00:59:23.712013 [ModeRegInit_LP4] CH1 RK1
5012 00:59:23.712093 match AC timing 9
5013 00:59:23.718764 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5014 00:59:23.722151 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5015 00:59:23.725359 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5016 00:59:23.731941 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5017 00:59:23.735516 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5018 00:59:23.735598 ==
5019 00:59:23.738366 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 00:59:23.742280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5021 00:59:23.742362 ==
5022 00:59:23.748065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5023 00:59:23.754563 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5024 00:59:23.757859 [CA 0] Center 37 (7~68) winsize 62
5025 00:59:23.761678 [CA 1] Center 37 (7~68) winsize 62
5026 00:59:23.764641 [CA 2] Center 34 (5~64) winsize 60
5027 00:59:23.768036 [CA 3] Center 34 (4~65) winsize 62
5028 00:59:23.771341 [CA 4] Center 33 (3~64) winsize 62
5029 00:59:23.774532 [CA 5] Center 32 (2~63) winsize 62
5030 00:59:23.774614
5031 00:59:23.777786 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5032 00:59:23.777867
5033 00:59:23.781608 [CATrainingPosCal] consider 1 rank data
5034 00:59:23.784424 u2DelayCellTimex100 = 270/100 ps
5035 00:59:23.787390 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5036 00:59:23.791118 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5037 00:59:23.794253 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5038 00:59:23.797213 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5039 00:59:23.804334 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5040 00:59:23.807666 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5041 00:59:23.807747
5042 00:59:23.810737 CA PerBit enable=1, Macro0, CA PI delay=32
5043 00:59:23.810818
5044 00:59:23.813913 [CBTSetCACLKResult] CA Dly = 32
5045 00:59:23.813994 CS Dly: 6 (0~37)
5046 00:59:23.814058 ==
5047 00:59:23.817109 Dram Type= 6, Freq= 0, CH_0, rank 1
5048 00:59:23.823799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 00:59:23.823881 ==
5050 00:59:23.827528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 00:59:23.833840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5052 00:59:23.837223 [CA 0] Center 38 (8~68) winsize 61
5053 00:59:23.840164 [CA 1] Center 37 (7~68) winsize 62
5054 00:59:23.843761 [CA 2] Center 34 (4~65) winsize 62
5055 00:59:23.847018 [CA 3] Center 34 (4~65) winsize 62
5056 00:59:23.850362 [CA 4] Center 33 (3~64) winsize 62
5057 00:59:23.853766 [CA 5] Center 32 (2~63) winsize 62
5058 00:59:23.853848
5059 00:59:23.857046 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5060 00:59:23.857128
5061 00:59:23.860157 [CATrainingPosCal] consider 2 rank data
5062 00:59:23.863639 u2DelayCellTimex100 = 270/100 ps
5063 00:59:23.866638 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5064 00:59:23.873070 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 00:59:23.876446 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5066 00:59:23.879906 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5067 00:59:23.882842 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5068 00:59:23.886410 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5069 00:59:23.886491
5070 00:59:23.889699 CA PerBit enable=1, Macro0, CA PI delay=32
5071 00:59:23.889780
5072 00:59:23.892962 [CBTSetCACLKResult] CA Dly = 32
5073 00:59:23.896056 CS Dly: 7 (0~39)
5074 00:59:23.896163
5075 00:59:23.899227 ----->DramcWriteLeveling(PI) begin...
5076 00:59:23.899326 ==
5077 00:59:23.902787 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 00:59:23.906108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 00:59:23.906190 ==
5080 00:59:23.909516 Write leveling (Byte 0): 35 => 35
5081 00:59:23.912651 Write leveling (Byte 1): 27 => 27
5082 00:59:23.915802 DramcWriteLeveling(PI) end<-----
5083 00:59:23.915884
5084 00:59:23.915947 ==
5085 00:59:23.919065 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 00:59:23.922339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 00:59:23.922421 ==
5088 00:59:23.925934 [Gating] SW mode calibration
5089 00:59:23.932363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 00:59:23.938961 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5091 00:59:23.942524 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5092 00:59:23.945616 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5093 00:59:23.952142 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 00:59:23.955352 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 00:59:23.962329 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 00:59:23.965506 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 00:59:23.968976 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 00:59:23.975520 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5099 00:59:23.978688 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5100 00:59:23.981729 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 00:59:23.988158 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 00:59:23.991884 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 00:59:23.994836 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 00:59:24.001631 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 00:59:24.004878 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 00:59:24.008010 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5107 00:59:24.014765 1 0 0 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
5108 00:59:24.018157 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 00:59:24.021047 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 00:59:24.028010 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 00:59:24.030802 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 00:59:24.034032 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 00:59:24.040818 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 00:59:24.044110 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5115 00:59:24.047578 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5116 00:59:24.054062 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 00:59:24.057068 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 00:59:24.060677 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 00:59:24.067724 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 00:59:24.070243 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 00:59:24.073513 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 00:59:24.080569 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 00:59:24.083477 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 00:59:24.087128 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 00:59:24.093629 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 00:59:24.096470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 00:59:24.100325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 00:59:24.106657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 00:59:24.110003 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5130 00:59:24.113324 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 00:59:24.119633 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 00:59:24.119716 Total UI for P1: 0, mck2ui 16
5133 00:59:24.126840 best dqsien dly found for B0: ( 1, 2, 26)
5134 00:59:24.129848 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5135 00:59:24.133099 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:59:24.136296 Total UI for P1: 0, mck2ui 16
5137 00:59:24.139517 best dqsien dly found for B1: ( 1, 3, 2)
5138 00:59:24.142576 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5139 00:59:24.145873 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5140 00:59:24.145955
5141 00:59:24.152783 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5142 00:59:24.156035 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5143 00:59:24.159700 [Gating] SW calibration Done
5144 00:59:24.159781 ==
5145 00:59:24.162759 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 00:59:24.165777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 00:59:24.165858 ==
5148 00:59:24.165922 RX Vref Scan: 0
5149 00:59:24.165982
5150 00:59:24.168937 RX Vref 0 -> 0, step: 1
5151 00:59:24.169017
5152 00:59:24.172415 RX Delay -80 -> 252, step: 8
5153 00:59:24.176015 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5154 00:59:24.178970 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5155 00:59:24.182453 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5156 00:59:24.189170 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5157 00:59:24.192231 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5158 00:59:24.195358 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5159 00:59:24.198454 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5160 00:59:24.202083 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5161 00:59:24.208789 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5162 00:59:24.211734 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5163 00:59:24.215544 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5164 00:59:24.218455 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5165 00:59:24.222022 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5166 00:59:24.224807 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5167 00:59:24.231355 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5168 00:59:24.235036 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5169 00:59:24.235117 ==
5170 00:59:24.237969 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 00:59:24.241829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 00:59:24.241910 ==
5173 00:59:24.245884 DQS Delay:
5174 00:59:24.245965 DQS0 = 0, DQS1 = 0
5175 00:59:24.246028 DQM Delay:
5176 00:59:24.247748 DQM0 = 99, DQM1 = 88
5177 00:59:24.247854 DQ Delay:
5178 00:59:24.251325 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5179 00:59:24.254516 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5180 00:59:24.258117 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5181 00:59:24.261324 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5182 00:59:24.261405
5183 00:59:24.261469
5184 00:59:24.264672 ==
5185 00:59:24.264753 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 00:59:24.271325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 00:59:24.271459 ==
5188 00:59:24.271523
5189 00:59:24.271583
5190 00:59:24.274309 TX Vref Scan disable
5191 00:59:24.274390 == TX Byte 0 ==
5192 00:59:24.277572 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5193 00:59:24.284539 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5194 00:59:24.284621 == TX Byte 1 ==
5195 00:59:24.290758 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5196 00:59:24.294183 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5197 00:59:24.294264 ==
5198 00:59:24.297262 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 00:59:24.301002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 00:59:24.301083 ==
5201 00:59:24.301146
5202 00:59:24.301205
5203 00:59:24.303812 TX Vref Scan disable
5204 00:59:24.307580 == TX Byte 0 ==
5205 00:59:24.310310 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5206 00:59:24.313553 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5207 00:59:24.316825 == TX Byte 1 ==
5208 00:59:24.320486 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5209 00:59:24.323357 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5210 00:59:24.323481
5211 00:59:24.327019 [DATLAT]
5212 00:59:24.327100 Freq=933, CH0 RK0
5213 00:59:24.327163
5214 00:59:24.330482 DATLAT Default: 0xd
5215 00:59:24.330563 0, 0xFFFF, sum = 0
5216 00:59:24.333449 1, 0xFFFF, sum = 0
5217 00:59:24.333531 2, 0xFFFF, sum = 0
5218 00:59:24.336963 3, 0xFFFF, sum = 0
5219 00:59:24.337045 4, 0xFFFF, sum = 0
5220 00:59:24.340252 5, 0xFFFF, sum = 0
5221 00:59:24.340335 6, 0xFFFF, sum = 0
5222 00:59:24.343482 7, 0xFFFF, sum = 0
5223 00:59:24.346536 8, 0xFFFF, sum = 0
5224 00:59:24.346617 9, 0xFFFF, sum = 0
5225 00:59:24.350192 10, 0x0, sum = 1
5226 00:59:24.350274 11, 0x0, sum = 2
5227 00:59:24.350338 12, 0x0, sum = 3
5228 00:59:24.353180 13, 0x0, sum = 4
5229 00:59:24.353262 best_step = 11
5230 00:59:24.353326
5231 00:59:24.357134 ==
5232 00:59:24.357215 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 00:59:24.362916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 00:59:24.362998 ==
5235 00:59:24.363062 RX Vref Scan: 1
5236 00:59:24.363121
5237 00:59:24.366778 RX Vref 0 -> 0, step: 1
5238 00:59:24.366859
5239 00:59:24.369712 RX Delay -61 -> 252, step: 4
5240 00:59:24.369793
5241 00:59:24.373025 Set Vref, RX VrefLevel [Byte0]: 54
5242 00:59:24.376842 [Byte1]: 59
5243 00:59:24.376923
5244 00:59:24.379441 Final RX Vref Byte 0 = 54 to rank0
5245 00:59:24.382693 Final RX Vref Byte 1 = 59 to rank0
5246 00:59:24.386016 Final RX Vref Byte 0 = 54 to rank1
5247 00:59:24.389253 Final RX Vref Byte 1 = 59 to rank1==
5248 00:59:24.392404 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 00:59:24.399023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 00:59:24.399106 ==
5251 00:59:24.399183 DQS Delay:
5252 00:59:24.399243 DQS0 = 0, DQS1 = 0
5253 00:59:24.402269 DQM Delay:
5254 00:59:24.402350 DQM0 = 99, DQM1 = 88
5255 00:59:24.405920 DQ Delay:
5256 00:59:24.408918 DQ0 =100, DQ1 =98, DQ2 =96, DQ3 =96
5257 00:59:24.412366 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5258 00:59:24.415591 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5259 00:59:24.418974 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =94
5260 00:59:24.419055
5261 00:59:24.419119
5262 00:59:24.425892 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5263 00:59:24.428903 CH0 RK0: MR19=505, MR18=1812
5264 00:59:24.435427 CH0_RK0: MR19=0x505, MR18=0x1812, DQSOSC=414, MR23=63, INC=63, DEC=42
5265 00:59:24.435510
5266 00:59:24.438474 ----->DramcWriteLeveling(PI) begin...
5267 00:59:24.438556 ==
5268 00:59:24.442090 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 00:59:24.445233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 00:59:24.445315 ==
5271 00:59:24.448947 Write leveling (Byte 0): 32 => 32
5272 00:59:24.451822 Write leveling (Byte 1): 30 => 30
5273 00:59:24.455152 DramcWriteLeveling(PI) end<-----
5274 00:59:24.455233
5275 00:59:24.455296 ==
5276 00:59:24.458307 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 00:59:24.461601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 00:59:24.464742 ==
5279 00:59:24.464822 [Gating] SW mode calibration
5280 00:59:24.475038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5281 00:59:24.478143 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5282 00:59:24.481909 0 14 0 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5283 00:59:24.488106 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 00:59:24.491167 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 00:59:24.494368 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 00:59:24.500828 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 00:59:24.504738 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 00:59:24.507585 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 00:59:24.514019 0 14 28 | B1->B0 | 3434 2828 | 0 0 | (1 0) (1 0)
5290 00:59:24.517346 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5291 00:59:24.520556 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 00:59:24.527105 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 00:59:24.530499 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 00:59:24.533835 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 00:59:24.540721 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 00:59:24.544484 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5297 00:59:24.547171 0 15 28 | B1->B0 | 2929 3b3b | 0 1 | (0 0) (0 0)
5298 00:59:24.553476 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5299 00:59:24.556922 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 00:59:24.560043 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 00:59:24.566850 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 00:59:24.570100 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 00:59:24.576636 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 00:59:24.579575 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 00:59:24.583215 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5306 00:59:24.589693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5307 00:59:24.593100 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 00:59:24.596343 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 00:59:24.603366 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 00:59:24.606071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 00:59:24.609358 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 00:59:24.616653 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 00:59:24.619243 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 00:59:24.622381 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 00:59:24.629007 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 00:59:24.632448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 00:59:24.635705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 00:59:24.642205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 00:59:24.645616 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 00:59:24.648953 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 00:59:24.655405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5322 00:59:24.655486 Total UI for P1: 0, mck2ui 16
5323 00:59:24.661871 best dqsien dly found for B0: ( 1, 2, 26)
5324 00:59:24.665820 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5325 00:59:24.668737 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:59:24.672082 Total UI for P1: 0, mck2ui 16
5327 00:59:24.675542 best dqsien dly found for B1: ( 1, 2, 30)
5328 00:59:24.678708 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5329 00:59:24.681547 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5330 00:59:24.681627
5331 00:59:24.688711 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5332 00:59:24.691810 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5333 00:59:24.695027 [Gating] SW calibration Done
5334 00:59:24.695107 ==
5335 00:59:24.698139 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 00:59:24.701551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 00:59:24.701632 ==
5338 00:59:24.701696 RX Vref Scan: 0
5339 00:59:24.701755
5340 00:59:24.704847 RX Vref 0 -> 0, step: 1
5341 00:59:24.704928
5342 00:59:24.708012 RX Delay -80 -> 252, step: 8
5343 00:59:24.711515 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5344 00:59:24.714175 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5345 00:59:24.721456 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5346 00:59:24.724177 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5347 00:59:24.727522 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5348 00:59:24.731310 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5349 00:59:24.734362 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5350 00:59:24.738186 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5351 00:59:24.744252 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5352 00:59:24.747337 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5353 00:59:24.750648 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5354 00:59:24.754085 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5355 00:59:24.757376 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5356 00:59:24.760690 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5357 00:59:24.767642 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5358 00:59:24.770528 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5359 00:59:24.770610 ==
5360 00:59:24.774003 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 00:59:24.777271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 00:59:24.777354 ==
5363 00:59:24.780728 DQS Delay:
5364 00:59:24.780810 DQS0 = 0, DQS1 = 0
5365 00:59:24.780874 DQM Delay:
5366 00:59:24.783784 DQM0 = 98, DQM1 = 91
5367 00:59:24.783866 DQ Delay:
5368 00:59:24.787129 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5369 00:59:24.790397 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5370 00:59:24.793629 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =83
5371 00:59:24.796835 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5372 00:59:24.796917
5373 00:59:24.796981
5374 00:59:24.797041 ==
5375 00:59:24.800481 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 00:59:24.806628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 00:59:24.806711 ==
5378 00:59:24.806777
5379 00:59:24.806836
5380 00:59:24.809896 TX Vref Scan disable
5381 00:59:24.809977 == TX Byte 0 ==
5382 00:59:24.813204 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5383 00:59:24.820140 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5384 00:59:24.820227 == TX Byte 1 ==
5385 00:59:24.826431 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5386 00:59:24.829702 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5387 00:59:24.829801 ==
5388 00:59:24.833086 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 00:59:24.836599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 00:59:24.836681 ==
5391 00:59:24.836746
5392 00:59:24.836804
5393 00:59:24.839446 TX Vref Scan disable
5394 00:59:24.842820 == TX Byte 0 ==
5395 00:59:24.846243 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5396 00:59:24.849329 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5397 00:59:24.852705 == TX Byte 1 ==
5398 00:59:24.855938 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5399 00:59:24.859111 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5400 00:59:24.859193
5401 00:59:24.862936 [DATLAT]
5402 00:59:24.863018 Freq=933, CH0 RK1
5403 00:59:24.863082
5404 00:59:24.865724 DATLAT Default: 0xb
5405 00:59:24.865805 0, 0xFFFF, sum = 0
5406 00:59:24.869520 1, 0xFFFF, sum = 0
5407 00:59:24.869603 2, 0xFFFF, sum = 0
5408 00:59:24.872284 3, 0xFFFF, sum = 0
5409 00:59:24.872367 4, 0xFFFF, sum = 0
5410 00:59:24.876344 5, 0xFFFF, sum = 0
5411 00:59:24.876427 6, 0xFFFF, sum = 0
5412 00:59:24.878982 7, 0xFFFF, sum = 0
5413 00:59:24.879064 8, 0xFFFF, sum = 0
5414 00:59:24.882752 9, 0xFFFF, sum = 0
5415 00:59:24.882836 10, 0x0, sum = 1
5416 00:59:24.885572 11, 0x0, sum = 2
5417 00:59:24.885655 12, 0x0, sum = 3
5418 00:59:24.889219 13, 0x0, sum = 4
5419 00:59:24.889301 best_step = 11
5420 00:59:24.889365
5421 00:59:24.889425 ==
5422 00:59:24.892612 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 00:59:24.898753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 00:59:24.898837 ==
5425 00:59:24.898901 RX Vref Scan: 0
5426 00:59:24.898962
5427 00:59:24.902116 RX Vref 0 -> 0, step: 1
5428 00:59:24.902198
5429 00:59:24.905235 RX Delay -53 -> 252, step: 4
5430 00:59:24.908491 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5431 00:59:24.915211 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5432 00:59:24.918190 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5433 00:59:24.921672 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5434 00:59:24.924874 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5435 00:59:24.928456 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5436 00:59:24.931861 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5437 00:59:24.938810 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5438 00:59:24.942105 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5439 00:59:24.944429 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5440 00:59:24.947997 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5441 00:59:24.951637 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5442 00:59:24.957778 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5443 00:59:24.961290 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5444 00:59:24.964540 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5445 00:59:24.967862 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5446 00:59:24.967945 ==
5447 00:59:24.971561 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 00:59:24.974382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 00:59:24.977548 ==
5450 00:59:24.977630 DQS Delay:
5451 00:59:24.977694 DQS0 = 0, DQS1 = 0
5452 00:59:24.981102 DQM Delay:
5453 00:59:24.981184 DQM0 = 97, DQM1 = 89
5454 00:59:24.984140 DQ Delay:
5455 00:59:24.988318 DQ0 =96, DQ1 =98, DQ2 =90, DQ3 =94
5456 00:59:24.990917 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =106
5457 00:59:24.994316 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5458 00:59:24.997700 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5459 00:59:24.997782
5460 00:59:24.997847
5461 00:59:25.004190 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5462 00:59:25.007191 CH0 RK1: MR19=505, MR18=1310
5463 00:59:25.014065 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5464 00:59:25.017516 [RxdqsGatingPostProcess] freq 933
5465 00:59:25.020534 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5466 00:59:25.023885 best DQS0 dly(2T, 0.5T) = (0, 10)
5467 00:59:25.027301 best DQS1 dly(2T, 0.5T) = (0, 11)
5468 00:59:25.030697 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5469 00:59:25.033792 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5470 00:59:25.037119 best DQS0 dly(2T, 0.5T) = (0, 10)
5471 00:59:25.040837 best DQS1 dly(2T, 0.5T) = (0, 10)
5472 00:59:25.043549 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5473 00:59:25.046709 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5474 00:59:25.050678 Pre-setting of DQS Precalculation
5475 00:59:25.056611 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5476 00:59:25.056696 ==
5477 00:59:25.060025 Dram Type= 6, Freq= 0, CH_1, rank 0
5478 00:59:25.063221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 00:59:25.063303 ==
5480 00:59:25.069899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5481 00:59:25.074357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5482 00:59:25.076995 [CA 0] Center 36 (6~67) winsize 62
5483 00:59:25.080563 [CA 1] Center 37 (6~68) winsize 63
5484 00:59:25.083806 [CA 2] Center 34 (4~65) winsize 62
5485 00:59:25.087134 [CA 3] Center 34 (4~65) winsize 62
5486 00:59:25.090432 [CA 4] Center 34 (4~65) winsize 62
5487 00:59:25.093844 [CA 5] Center 33 (3~64) winsize 62
5488 00:59:25.093925
5489 00:59:25.096755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5490 00:59:25.096837
5491 00:59:25.100455 [CATrainingPosCal] consider 1 rank data
5492 00:59:25.103946 u2DelayCellTimex100 = 270/100 ps
5493 00:59:25.107045 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 00:59:25.113416 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5495 00:59:25.116683 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5496 00:59:25.120058 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5497 00:59:25.123252 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 00:59:25.127141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5499 00:59:25.127224
5500 00:59:25.129877 CA PerBit enable=1, Macro0, CA PI delay=33
5501 00:59:25.129959
5502 00:59:25.133507 [CBTSetCACLKResult] CA Dly = 33
5503 00:59:25.136542 CS Dly: 5 (0~36)
5504 00:59:25.136627 ==
5505 00:59:25.139762 Dram Type= 6, Freq= 0, CH_1, rank 1
5506 00:59:25.142941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 00:59:25.143024 ==
5508 00:59:25.150608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5509 00:59:25.152839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5510 00:59:25.157310 [CA 0] Center 36 (6~67) winsize 62
5511 00:59:25.160340 [CA 1] Center 37 (7~67) winsize 61
5512 00:59:25.163810 [CA 2] Center 34 (4~65) winsize 62
5513 00:59:25.167165 [CA 3] Center 34 (3~65) winsize 63
5514 00:59:25.170216 [CA 4] Center 34 (4~65) winsize 62
5515 00:59:25.173346 [CA 5] Center 33 (3~64) winsize 62
5516 00:59:25.173429
5517 00:59:25.176571 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5518 00:59:25.176652
5519 00:59:25.180247 [CATrainingPosCal] consider 2 rank data
5520 00:59:25.183227 u2DelayCellTimex100 = 270/100 ps
5521 00:59:25.186843 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 00:59:25.193187 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5523 00:59:25.196277 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5524 00:59:25.199680 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5525 00:59:25.202974 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5526 00:59:25.206304 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 00:59:25.206386
5528 00:59:25.209810 CA PerBit enable=1, Macro0, CA PI delay=33
5529 00:59:25.209891
5530 00:59:25.212982 [CBTSetCACLKResult] CA Dly = 33
5531 00:59:25.216978 CS Dly: 6 (0~38)
5532 00:59:25.217060
5533 00:59:25.219734 ----->DramcWriteLeveling(PI) begin...
5534 00:59:25.219818 ==
5535 00:59:25.222795 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 00:59:25.226303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 00:59:25.226418 ==
5538 00:59:25.229518 Write leveling (Byte 0): 24 => 24
5539 00:59:25.232343 Write leveling (Byte 1): 24 => 24
5540 00:59:25.235927 DramcWriteLeveling(PI) end<-----
5541 00:59:25.236009
5542 00:59:25.236073 ==
5543 00:59:25.239321 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 00:59:25.242818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 00:59:25.242901 ==
5546 00:59:25.245485 [Gating] SW mode calibration
5547 00:59:25.252590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 00:59:25.258696 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5549 00:59:25.262388 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 00:59:25.269053 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 00:59:25.272177 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 00:59:25.275376 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 00:59:25.281946 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 00:59:25.285060 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 00:59:25.288537 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
5556 00:59:25.295502 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5557 00:59:25.298232 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 00:59:25.301602 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 00:59:25.308307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 00:59:25.311688 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 00:59:25.315019 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 00:59:25.321755 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 00:59:25.324430 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5564 00:59:25.328632 0 15 28 | B1->B0 | 3636 4040 | 1 1 | (0 0) (0 0)
5565 00:59:25.334482 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 00:59:25.337952 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 00:59:25.340959 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 00:59:25.347907 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 00:59:25.350712 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 00:59:25.354190 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 00:59:25.361052 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5572 00:59:25.364906 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5573 00:59:25.367840 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 00:59:25.374175 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 00:59:25.377432 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 00:59:25.380490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 00:59:25.387034 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 00:59:25.390546 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 00:59:25.393923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 00:59:25.400491 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 00:59:25.403356 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 00:59:25.406994 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 00:59:25.413627 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 00:59:25.416701 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 00:59:25.420079 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 00:59:25.426653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 00:59:25.429707 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5588 00:59:25.433655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5589 00:59:25.437090 Total UI for P1: 0, mck2ui 16
5590 00:59:25.439888 best dqsien dly found for B1: ( 1, 2, 24)
5591 00:59:25.447257 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:59:25.447342 Total UI for P1: 0, mck2ui 16
5593 00:59:25.453123 best dqsien dly found for B0: ( 1, 2, 28)
5594 00:59:25.456577 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5595 00:59:25.460168 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5596 00:59:25.460255
5597 00:59:25.463074 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5598 00:59:25.466069 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5599 00:59:25.469472 [Gating] SW calibration Done
5600 00:59:25.469555 ==
5601 00:59:25.472869 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 00:59:25.475894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 00:59:25.475976 ==
5604 00:59:25.479566 RX Vref Scan: 0
5605 00:59:25.479647
5606 00:59:25.479711 RX Vref 0 -> 0, step: 1
5607 00:59:25.482653
5608 00:59:25.482778 RX Delay -80 -> 252, step: 8
5609 00:59:25.489229 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5610 00:59:25.492542 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5611 00:59:25.496059 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5612 00:59:25.499246 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5613 00:59:25.502506 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5614 00:59:25.505713 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5615 00:59:25.512536 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5616 00:59:25.515659 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5617 00:59:25.518973 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5618 00:59:25.522389 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5619 00:59:25.525767 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5620 00:59:25.532119 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5621 00:59:25.535625 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5622 00:59:25.538987 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5623 00:59:25.542032 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5624 00:59:25.545284 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5625 00:59:25.545508 ==
5626 00:59:25.548964 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 00:59:25.555626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 00:59:25.555882 ==
5629 00:59:25.556042 DQS Delay:
5630 00:59:25.558314 DQS0 = 0, DQS1 = 0
5631 00:59:25.558518 DQM Delay:
5632 00:59:25.558674 DQM0 = 98, DQM1 = 93
5633 00:59:25.561478 DQ Delay:
5634 00:59:25.564906 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5635 00:59:25.568059 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5636 00:59:25.571547 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5637 00:59:25.574998 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5638 00:59:25.575105
5639 00:59:25.575171
5640 00:59:25.575231 ==
5641 00:59:25.577915 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 00:59:25.581107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 00:59:25.581190 ==
5644 00:59:25.581254
5645 00:59:25.581314
5646 00:59:25.584703 TX Vref Scan disable
5647 00:59:25.587805 == TX Byte 0 ==
5648 00:59:25.591006 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5649 00:59:25.594375 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5650 00:59:25.597792 == TX Byte 1 ==
5651 00:59:25.601080 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5652 00:59:25.604187 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5653 00:59:25.604268 ==
5654 00:59:25.607847 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 00:59:25.613947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 00:59:25.614028 ==
5657 00:59:25.614091
5658 00:59:25.614150
5659 00:59:25.614205 TX Vref Scan disable
5660 00:59:25.618171 == TX Byte 0 ==
5661 00:59:25.621364 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5662 00:59:25.627844 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5663 00:59:25.627924 == TX Byte 1 ==
5664 00:59:25.631630 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5665 00:59:25.637505 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5666 00:59:25.637586
5667 00:59:25.637649 [DATLAT]
5668 00:59:25.637709 Freq=933, CH1 RK0
5669 00:59:25.637765
5670 00:59:25.641200 DATLAT Default: 0xd
5671 00:59:25.644312 0, 0xFFFF, sum = 0
5672 00:59:25.644393 1, 0xFFFF, sum = 0
5673 00:59:25.647599 2, 0xFFFF, sum = 0
5674 00:59:25.647680 3, 0xFFFF, sum = 0
5675 00:59:25.651339 4, 0xFFFF, sum = 0
5676 00:59:25.651433 5, 0xFFFF, sum = 0
5677 00:59:25.654315 6, 0xFFFF, sum = 0
5678 00:59:25.654403 7, 0xFFFF, sum = 0
5679 00:59:25.657166 8, 0xFFFF, sum = 0
5680 00:59:25.657248 9, 0xFFFF, sum = 0
5681 00:59:25.661150 10, 0x0, sum = 1
5682 00:59:25.661232 11, 0x0, sum = 2
5683 00:59:25.663882 12, 0x0, sum = 3
5684 00:59:25.663963 13, 0x0, sum = 4
5685 00:59:25.667503 best_step = 11
5686 00:59:25.667584
5687 00:59:25.667645 ==
5688 00:59:25.671447 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 00:59:25.674307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 00:59:25.674388 ==
5691 00:59:25.677296 RX Vref Scan: 1
5692 00:59:25.677375
5693 00:59:25.677438 RX Vref 0 -> 0, step: 1
5694 00:59:25.677496
5695 00:59:25.680853 RX Delay -61 -> 252, step: 4
5696 00:59:25.680934
5697 00:59:25.683663 Set Vref, RX VrefLevel [Byte0]: 52
5698 00:59:25.686806 [Byte1]: 53
5699 00:59:25.690761
5700 00:59:25.690863 Final RX Vref Byte 0 = 52 to rank0
5701 00:59:25.694441 Final RX Vref Byte 1 = 53 to rank0
5702 00:59:25.697172 Final RX Vref Byte 0 = 52 to rank1
5703 00:59:25.700548 Final RX Vref Byte 1 = 53 to rank1==
5704 00:59:25.703925 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 00:59:25.710286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 00:59:25.710367 ==
5707 00:59:25.710430 DQS Delay:
5708 00:59:25.714086 DQS0 = 0, DQS1 = 0
5709 00:59:25.714167 DQM Delay:
5710 00:59:25.714230 DQM0 = 98, DQM1 = 96
5711 00:59:25.717477 DQ Delay:
5712 00:59:25.720486 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5713 00:59:25.723838 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5714 00:59:25.727181 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5715 00:59:25.730290 DQ12 =106, DQ13 =106, DQ14 =104, DQ15 =102
5716 00:59:25.730372
5717 00:59:25.730434
5718 00:59:25.737652 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5719 00:59:25.740394 CH1 RK0: MR19=505, MR18=818
5720 00:59:25.746796 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5721 00:59:25.746877
5722 00:59:25.749804 ----->DramcWriteLeveling(PI) begin...
5723 00:59:25.749885 ==
5724 00:59:25.753262 Dram Type= 6, Freq= 0, CH_1, rank 1
5725 00:59:25.756706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 00:59:25.756788 ==
5727 00:59:25.760112 Write leveling (Byte 0): 27 => 27
5728 00:59:25.763215 Write leveling (Byte 1): 29 => 29
5729 00:59:25.766362 DramcWriteLeveling(PI) end<-----
5730 00:59:25.766443
5731 00:59:25.766506 ==
5732 00:59:25.769819 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 00:59:25.776348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 00:59:25.776429 ==
5735 00:59:25.776493 [Gating] SW mode calibration
5736 00:59:25.786471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5737 00:59:25.789752 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5738 00:59:25.792593 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5739 00:59:25.799266 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 00:59:25.802716 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 00:59:25.805881 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 00:59:25.812932 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 00:59:25.816280 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 00:59:25.819506 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
5745 00:59:25.825876 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5746 00:59:25.828961 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5747 00:59:25.832531 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 00:59:25.839225 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 00:59:25.842829 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 00:59:25.845692 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 00:59:25.852654 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 00:59:25.856134 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5753 00:59:25.858944 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5754 00:59:25.866058 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 00:59:25.868803 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 00:59:25.871896 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 00:59:25.878835 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 00:59:25.881850 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 00:59:25.885561 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 00:59:25.891841 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5761 00:59:25.895074 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 00:59:25.898446 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 00:59:25.905475 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 00:59:25.908348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 00:59:25.911742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 00:59:25.918163 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 00:59:25.921999 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 00:59:25.924692 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 00:59:25.931691 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 00:59:25.934685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 00:59:25.937811 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 00:59:25.944903 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 00:59:25.948552 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 00:59:25.951294 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 00:59:25.958254 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 00:59:25.960869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5777 00:59:25.964336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:59:25.967639 Total UI for P1: 0, mck2ui 16
5779 00:59:25.971030 best dqsien dly found for B0: ( 1, 2, 24)
5780 00:59:25.974057 Total UI for P1: 0, mck2ui 16
5781 00:59:25.977256 best dqsien dly found for B1: ( 1, 2, 26)
5782 00:59:25.980724 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5783 00:59:25.987219 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5784 00:59:25.987301
5785 00:59:25.990974 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5786 00:59:25.993840 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5787 00:59:25.997484 [Gating] SW calibration Done
5788 00:59:25.997565 ==
5789 00:59:26.000682 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 00:59:26.003837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 00:59:26.003918 ==
5792 00:59:26.006879 RX Vref Scan: 0
5793 00:59:26.006959
5794 00:59:26.007022 RX Vref 0 -> 0, step: 1
5795 00:59:26.007080
5796 00:59:26.010534 RX Delay -80 -> 252, step: 8
5797 00:59:26.013491 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5798 00:59:26.020450 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5799 00:59:26.023101 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5800 00:59:26.026845 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5801 00:59:26.029760 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5802 00:59:26.033766 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5803 00:59:26.036545 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5804 00:59:26.043388 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5805 00:59:26.046626 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5806 00:59:26.049700 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5807 00:59:26.052980 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5808 00:59:26.056481 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5809 00:59:26.063145 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5810 00:59:26.066081 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5811 00:59:26.069553 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5812 00:59:26.073022 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5813 00:59:26.073104 ==
5814 00:59:26.076231 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 00:59:26.082505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 00:59:26.082587 ==
5817 00:59:26.082651 DQS Delay:
5818 00:59:26.082709 DQS0 = 0, DQS1 = 0
5819 00:59:26.085788 DQM Delay:
5820 00:59:26.085895 DQM0 = 96, DQM1 = 93
5821 00:59:26.089009 DQ Delay:
5822 00:59:26.093226 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =95
5823 00:59:26.096578 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5824 00:59:26.099296 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5825 00:59:26.102248 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5826 00:59:26.102328
5827 00:59:26.102392
5828 00:59:26.102450 ==
5829 00:59:26.105876 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 00:59:26.109134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 00:59:26.109215 ==
5832 00:59:26.109278
5833 00:59:26.109336
5834 00:59:26.112524 TX Vref Scan disable
5835 00:59:26.116133 == TX Byte 0 ==
5836 00:59:26.118774 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5837 00:59:26.122055 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5838 00:59:26.125541 == TX Byte 1 ==
5839 00:59:26.129182 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5840 00:59:26.132193 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5841 00:59:26.132274 ==
5842 00:59:26.135558 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 00:59:26.138786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 00:59:26.141658 ==
5845 00:59:26.141739
5846 00:59:26.141801
5847 00:59:26.141859 TX Vref Scan disable
5848 00:59:26.146166 == TX Byte 0 ==
5849 00:59:26.148819 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 00:59:26.155327 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 00:59:26.155444 == TX Byte 1 ==
5852 00:59:26.158697 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5853 00:59:26.165304 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5854 00:59:26.165385
5855 00:59:26.165448 [DATLAT]
5856 00:59:26.165507 Freq=933, CH1 RK1
5857 00:59:26.165564
5858 00:59:26.168869 DATLAT Default: 0xb
5859 00:59:26.168950 0, 0xFFFF, sum = 0
5860 00:59:26.172215 1, 0xFFFF, sum = 0
5861 00:59:26.175765 2, 0xFFFF, sum = 0
5862 00:59:26.175846 3, 0xFFFF, sum = 0
5863 00:59:26.179037 4, 0xFFFF, sum = 0
5864 00:59:26.179118 5, 0xFFFF, sum = 0
5865 00:59:26.181770 6, 0xFFFF, sum = 0
5866 00:59:26.181852 7, 0xFFFF, sum = 0
5867 00:59:26.185441 8, 0xFFFF, sum = 0
5868 00:59:26.185523 9, 0xFFFF, sum = 0
5869 00:59:26.188293 10, 0x0, sum = 1
5870 00:59:26.188375 11, 0x0, sum = 2
5871 00:59:26.192461 12, 0x0, sum = 3
5872 00:59:26.192543 13, 0x0, sum = 4
5873 00:59:26.195570 best_step = 11
5874 00:59:26.195650
5875 00:59:26.195712 ==
5876 00:59:26.198267 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 00:59:26.201395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 00:59:26.201476 ==
5879 00:59:26.201539 RX Vref Scan: 0
5880 00:59:26.205150
5881 00:59:26.205230 RX Vref 0 -> 0, step: 1
5882 00:59:26.205292
5883 00:59:26.207943 RX Delay -61 -> 252, step: 4
5884 00:59:26.214357 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5885 00:59:26.218111 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5886 00:59:26.221533 iDelay=199, Bit 2, Center 88 (-1 ~ 178) 180
5887 00:59:26.224449 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5888 00:59:26.227861 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5889 00:59:26.234228 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5890 00:59:26.237470 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5891 00:59:26.240724 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5892 00:59:26.244115 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5893 00:59:26.247384 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5894 00:59:26.253922 iDelay=199, Bit 10, Center 96 (7 ~ 186) 180
5895 00:59:26.257116 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5896 00:59:26.260217 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5897 00:59:26.263650 iDelay=199, Bit 13, Center 104 (15 ~ 194) 180
5898 00:59:26.267631 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5899 00:59:26.273559 iDelay=199, Bit 15, Center 104 (15 ~ 194) 180
5900 00:59:26.273640 ==
5901 00:59:26.277269 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 00:59:26.280102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 00:59:26.280183 ==
5904 00:59:26.280247 DQS Delay:
5905 00:59:26.283342 DQS0 = 0, DQS1 = 0
5906 00:59:26.283475 DQM Delay:
5907 00:59:26.286512 DQM0 = 97, DQM1 = 95
5908 00:59:26.286592 DQ Delay:
5909 00:59:26.290373 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =96
5910 00:59:26.293487 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5911 00:59:26.296864 DQ8 =82, DQ9 =86, DQ10 =96, DQ11 =88
5912 00:59:26.300036 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104
5913 00:59:26.300116
5914 00:59:26.300179
5915 00:59:26.309810 [DQSOSCAuto] RK1, (LSB)MR18= 0x920, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 419 ps
5916 00:59:26.313056 CH1 RK1: MR19=505, MR18=920
5917 00:59:26.316234 CH1_RK1: MR19=0x505, MR18=0x920, DQSOSC=411, MR23=63, INC=64, DEC=42
5918 00:59:26.319567 [RxdqsGatingPostProcess] freq 933
5919 00:59:26.326544 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5920 00:59:26.329762 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 00:59:26.332966 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 00:59:26.336054 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 00:59:26.339300 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 00:59:26.342852 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 00:59:26.345931 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 00:59:26.349320 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 00:59:26.352628 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 00:59:26.352709 Pre-setting of DQS Precalculation
5929 00:59:26.359828 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5930 00:59:26.365590 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5931 00:59:26.372361 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5932 00:59:26.372443
5933 00:59:26.375313
5934 00:59:26.375430 [Calibration Summary] 1866 Mbps
5935 00:59:26.378779 CH 0, Rank 0
5936 00:59:26.378861 SW Impedance : PASS
5937 00:59:26.382325 DUTY Scan : NO K
5938 00:59:26.385750 ZQ Calibration : PASS
5939 00:59:26.385829 Jitter Meter : NO K
5940 00:59:26.388398 CBT Training : PASS
5941 00:59:26.391924 Write leveling : PASS
5942 00:59:26.392004 RX DQS gating : PASS
5943 00:59:26.395218 RX DQ/DQS(RDDQC) : PASS
5944 00:59:26.398491 TX DQ/DQS : PASS
5945 00:59:26.398572 RX DATLAT : PASS
5946 00:59:26.401895 RX DQ/DQS(Engine): PASS
5947 00:59:26.405726 TX OE : NO K
5948 00:59:26.405807 All Pass.
5949 00:59:26.405869
5950 00:59:26.405928 CH 0, Rank 1
5951 00:59:26.408185 SW Impedance : PASS
5952 00:59:26.412472 DUTY Scan : NO K
5953 00:59:26.412552 ZQ Calibration : PASS
5954 00:59:26.414810 Jitter Meter : NO K
5955 00:59:26.419208 CBT Training : PASS
5956 00:59:26.419289 Write leveling : PASS
5957 00:59:26.421857 RX DQS gating : PASS
5958 00:59:26.424732 RX DQ/DQS(RDDQC) : PASS
5959 00:59:26.424812 TX DQ/DQS : PASS
5960 00:59:26.428209 RX DATLAT : PASS
5961 00:59:26.431162 RX DQ/DQS(Engine): PASS
5962 00:59:26.431242 TX OE : NO K
5963 00:59:26.434518 All Pass.
5964 00:59:26.434601
5965 00:59:26.434664 CH 1, Rank 0
5966 00:59:26.438093 SW Impedance : PASS
5967 00:59:26.438173 DUTY Scan : NO K
5968 00:59:26.441055 ZQ Calibration : PASS
5969 00:59:26.444873 Jitter Meter : NO K
5970 00:59:26.444954 CBT Training : PASS
5971 00:59:26.447759 Write leveling : PASS
5972 00:59:26.447839 RX DQS gating : PASS
5973 00:59:26.451214 RX DQ/DQS(RDDQC) : PASS
5974 00:59:26.454318 TX DQ/DQS : PASS
5975 00:59:26.454399 RX DATLAT : PASS
5976 00:59:26.458009 RX DQ/DQS(Engine): PASS
5977 00:59:26.461035 TX OE : NO K
5978 00:59:26.461116 All Pass.
5979 00:59:26.461180
5980 00:59:26.461238 CH 1, Rank 1
5981 00:59:26.464241 SW Impedance : PASS
5982 00:59:26.467677 DUTY Scan : NO K
5983 00:59:26.467780 ZQ Calibration : PASS
5984 00:59:26.470669 Jitter Meter : NO K
5985 00:59:26.474043 CBT Training : PASS
5986 00:59:26.474124 Write leveling : PASS
5987 00:59:26.477508 RX DQS gating : PASS
5988 00:59:26.481009 RX DQ/DQS(RDDQC) : PASS
5989 00:59:26.481090 TX DQ/DQS : PASS
5990 00:59:26.484040 RX DATLAT : PASS
5991 00:59:26.487051 RX DQ/DQS(Engine): PASS
5992 00:59:26.487131 TX OE : NO K
5993 00:59:26.490609 All Pass.
5994 00:59:26.490689
5995 00:59:26.490751 DramC Write-DBI off
5996 00:59:26.493614 PER_BANK_REFRESH: Hybrid Mode
5997 00:59:26.496992 TX_TRACKING: ON
5998 00:59:26.504075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5999 00:59:26.507388 [FAST_K] Save calibration result to emmc
6000 00:59:26.510502 dramc_set_vcore_voltage set vcore to 650000
6001 00:59:26.513462 Read voltage for 400, 6
6002 00:59:26.513542 Vio18 = 0
6003 00:59:26.516767 Vcore = 650000
6004 00:59:26.516847 Vdram = 0
6005 00:59:26.516910 Vddq = 0
6006 00:59:26.520536 Vmddr = 0
6007 00:59:26.524146 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6008 00:59:26.530182 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6009 00:59:26.533242 MEM_TYPE=3, freq_sel=20
6010 00:59:26.533323 sv_algorithm_assistance_LP4_800
6011 00:59:26.539402 ============ PULL DRAM RESETB DOWN ============
6012 00:59:26.543193 ========== PULL DRAM RESETB DOWN end =========
6013 00:59:26.546210 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 00:59:26.549265 ===================================
6015 00:59:26.552775 LPDDR4 DRAM CONFIGURATION
6016 00:59:26.555802 ===================================
6017 00:59:26.559005 EX_ROW_EN[0] = 0x0
6018 00:59:26.559086 EX_ROW_EN[1] = 0x0
6019 00:59:26.562304 LP4Y_EN = 0x0
6020 00:59:26.562385 WORK_FSP = 0x0
6021 00:59:26.565833 WL = 0x2
6022 00:59:26.565912 RL = 0x2
6023 00:59:26.569556 BL = 0x2
6024 00:59:26.572103 RPST = 0x0
6025 00:59:26.572183 RD_PRE = 0x0
6026 00:59:26.575485 WR_PRE = 0x1
6027 00:59:26.575565 WR_PST = 0x0
6028 00:59:26.578687 DBI_WR = 0x0
6029 00:59:26.578767 DBI_RD = 0x0
6030 00:59:26.581841 OTF = 0x1
6031 00:59:26.585232 ===================================
6032 00:59:26.588674 ===================================
6033 00:59:26.588755 ANA top config
6034 00:59:26.591816 ===================================
6035 00:59:26.595275 DLL_ASYNC_EN = 0
6036 00:59:26.598247 ALL_SLAVE_EN = 1
6037 00:59:26.598327 NEW_RANK_MODE = 1
6038 00:59:26.601654 DLL_IDLE_MODE = 1
6039 00:59:26.604946 LP45_APHY_COMB_EN = 1
6040 00:59:26.608428 TX_ODT_DIS = 1
6041 00:59:26.611533 NEW_8X_MODE = 1
6042 00:59:26.614638 ===================================
6043 00:59:26.618314 ===================================
6044 00:59:26.621818 data_rate = 800
6045 00:59:26.621899 CKR = 1
6046 00:59:26.624403 DQ_P2S_RATIO = 4
6047 00:59:26.627915 ===================================
6048 00:59:26.631428 CA_P2S_RATIO = 4
6049 00:59:26.634560 DQ_CA_OPEN = 0
6050 00:59:26.638001 DQ_SEMI_OPEN = 1
6051 00:59:26.641466 CA_SEMI_OPEN = 1
6052 00:59:26.641547 CA_FULL_RATE = 0
6053 00:59:26.644672 DQ_CKDIV4_EN = 0
6054 00:59:26.647600 CA_CKDIV4_EN = 1
6055 00:59:26.651274 CA_PREDIV_EN = 0
6056 00:59:26.654679 PH8_DLY = 0
6057 00:59:26.657983 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6058 00:59:26.658064 DQ_AAMCK_DIV = 0
6059 00:59:26.660913 CA_AAMCK_DIV = 0
6060 00:59:26.663911 CA_ADMCK_DIV = 4
6061 00:59:26.667309 DQ_TRACK_CA_EN = 0
6062 00:59:26.670500 CA_PICK = 800
6063 00:59:26.674513 CA_MCKIO = 400
6064 00:59:26.677387 MCKIO_SEMI = 400
6065 00:59:26.680779 PLL_FREQ = 3016
6066 00:59:26.680860 DQ_UI_PI_RATIO = 32
6067 00:59:26.684016 CA_UI_PI_RATIO = 32
6068 00:59:26.687411 ===================================
6069 00:59:26.690642 ===================================
6070 00:59:26.693863 memory_type:LPDDR4
6071 00:59:26.697211 GP_NUM : 10
6072 00:59:26.697290 SRAM_EN : 1
6073 00:59:26.700234 MD32_EN : 0
6074 00:59:26.703663 ===================================
6075 00:59:26.707005 [ANA_INIT] >>>>>>>>>>>>>>
6076 00:59:26.707087 <<<<<< [CONFIGURE PHASE]: ANA_TX
6077 00:59:26.713650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6078 00:59:26.716878 ===================================
6079 00:59:26.716959 data_rate = 800,PCW = 0X7400
6080 00:59:26.720535 ===================================
6081 00:59:26.723526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6082 00:59:26.729846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 00:59:26.742816 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 00:59:26.746470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6085 00:59:26.749759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6086 00:59:26.752744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6087 00:59:26.756015 [ANA_INIT] flow start
6088 00:59:26.756096 [ANA_INIT] PLL >>>>>>>>
6089 00:59:26.759611 [ANA_INIT] PLL <<<<<<<<
6090 00:59:26.762909 [ANA_INIT] MIDPI >>>>>>>>
6091 00:59:26.766137 [ANA_INIT] MIDPI <<<<<<<<
6092 00:59:26.766218 [ANA_INIT] DLL >>>>>>>>
6093 00:59:26.769268 [ANA_INIT] flow end
6094 00:59:26.772682 ============ LP4 DIFF to SE enter ============
6095 00:59:26.776166 ============ LP4 DIFF to SE exit ============
6096 00:59:26.779242 [ANA_INIT] <<<<<<<<<<<<<
6097 00:59:26.783087 [Flow] Enable top DCM control >>>>>
6098 00:59:26.786045 [Flow] Enable top DCM control <<<<<
6099 00:59:26.789538 Enable DLL master slave shuffle
6100 00:59:26.795287 ==============================================================
6101 00:59:26.795398 Gating Mode config
6102 00:59:26.802175 ==============================================================
6103 00:59:26.802257 Config description:
6104 00:59:26.811783 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6105 00:59:26.818824 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6106 00:59:26.825353 SELPH_MODE 0: By rank 1: By Phase
6107 00:59:26.828640 ==============================================================
6108 00:59:26.832015 GAT_TRACK_EN = 0
6109 00:59:26.834807 RX_GATING_MODE = 2
6110 00:59:26.838542 RX_GATING_TRACK_MODE = 2
6111 00:59:26.841504 SELPH_MODE = 1
6112 00:59:26.845028 PICG_EARLY_EN = 1
6113 00:59:26.848347 VALID_LAT_VALUE = 1
6114 00:59:26.854856 ==============================================================
6115 00:59:26.858388 Enter into Gating configuration >>>>
6116 00:59:26.861508 Exit from Gating configuration <<<<
6117 00:59:26.864693 Enter into DVFS_PRE_config >>>>>
6118 00:59:26.874581 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6119 00:59:26.878163 Exit from DVFS_PRE_config <<<<<
6120 00:59:26.881135 Enter into PICG configuration >>>>
6121 00:59:26.884495 Exit from PICG configuration <<<<
6122 00:59:26.887850 [RX_INPUT] configuration >>>>>
6123 00:59:26.887931 [RX_INPUT] configuration <<<<<
6124 00:59:26.894447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6125 00:59:26.900674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6126 00:59:26.907642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 00:59:26.910717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 00:59:26.917631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 00:59:26.924063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 00:59:26.927100 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6131 00:59:26.933961 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6132 00:59:26.936854 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6133 00:59:26.940305 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6134 00:59:26.943902 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6135 00:59:26.950397 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 00:59:26.953785 ===================================
6137 00:59:26.957181 LPDDR4 DRAM CONFIGURATION
6138 00:59:26.959731 ===================================
6139 00:59:26.959813 EX_ROW_EN[0] = 0x0
6140 00:59:26.963846 EX_ROW_EN[1] = 0x0
6141 00:59:26.963927 LP4Y_EN = 0x0
6142 00:59:26.966662 WORK_FSP = 0x0
6143 00:59:26.966743 WL = 0x2
6144 00:59:26.969675 RL = 0x2
6145 00:59:26.969756 BL = 0x2
6146 00:59:26.972935 RPST = 0x0
6147 00:59:26.973016 RD_PRE = 0x0
6148 00:59:26.976778 WR_PRE = 0x1
6149 00:59:26.976858 WR_PST = 0x0
6150 00:59:26.979521 DBI_WR = 0x0
6151 00:59:26.983119 DBI_RD = 0x0
6152 00:59:26.983200 OTF = 0x1
6153 00:59:26.986065 ===================================
6154 00:59:26.989342 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6155 00:59:26.995997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6156 00:59:26.999612 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 00:59:27.003265 ===================================
6158 00:59:27.005954 LPDDR4 DRAM CONFIGURATION
6159 00:59:27.009311 ===================================
6160 00:59:27.009393 EX_ROW_EN[0] = 0x10
6161 00:59:27.012764 EX_ROW_EN[1] = 0x0
6162 00:59:27.012845 LP4Y_EN = 0x0
6163 00:59:27.015662 WORK_FSP = 0x0
6164 00:59:27.015743 WL = 0x2
6165 00:59:27.019034 RL = 0x2
6166 00:59:27.019146 BL = 0x2
6167 00:59:27.022324 RPST = 0x0
6168 00:59:27.022405 RD_PRE = 0x0
6169 00:59:27.025672 WR_PRE = 0x1
6170 00:59:27.029036 WR_PST = 0x0
6171 00:59:27.029117 DBI_WR = 0x0
6172 00:59:27.032424 DBI_RD = 0x0
6173 00:59:27.032505 OTF = 0x1
6174 00:59:27.036099 ===================================
6175 00:59:27.042056 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6176 00:59:27.046752 nWR fixed to 30
6177 00:59:27.048915 [ModeRegInit_LP4] CH0 RK0
6178 00:59:27.048995 [ModeRegInit_LP4] CH0 RK1
6179 00:59:27.052669 [ModeRegInit_LP4] CH1 RK0
6180 00:59:27.055607 [ModeRegInit_LP4] CH1 RK1
6181 00:59:27.055688 match AC timing 19
6182 00:59:27.062091 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6183 00:59:27.065733 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6184 00:59:27.069196 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6185 00:59:27.075267 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6186 00:59:27.079082 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6187 00:59:27.079163 ==
6188 00:59:27.081946 Dram Type= 6, Freq= 0, CH_0, rank 0
6189 00:59:27.085129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6190 00:59:27.085212 ==
6191 00:59:27.091957 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6192 00:59:27.098125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6193 00:59:27.102009 [CA 0] Center 36 (8~64) winsize 57
6194 00:59:27.105315 [CA 1] Center 36 (8~64) winsize 57
6195 00:59:27.108526 [CA 2] Center 36 (8~64) winsize 57
6196 00:59:27.112065 [CA 3] Center 36 (8~64) winsize 57
6197 00:59:27.115069 [CA 4] Center 36 (8~64) winsize 57
6198 00:59:27.118089 [CA 5] Center 36 (8~64) winsize 57
6199 00:59:27.118169
6200 00:59:27.121827 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6201 00:59:27.121908
6202 00:59:27.124779 [CATrainingPosCal] consider 1 rank data
6203 00:59:27.128066 u2DelayCellTimex100 = 270/100 ps
6204 00:59:27.131074 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 00:59:27.135598 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 00:59:27.138207 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 00:59:27.141088 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 00:59:27.144331 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 00:59:27.147797 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 00:59:27.147878
6211 00:59:27.154453 CA PerBit enable=1, Macro0, CA PI delay=36
6212 00:59:27.154534
6213 00:59:27.157810 [CBTSetCACLKResult] CA Dly = 36
6214 00:59:27.157894 CS Dly: 1 (0~32)
6215 00:59:27.158006 ==
6216 00:59:27.160876 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 00:59:27.164933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 00:59:27.165015 ==
6219 00:59:27.170622 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 00:59:27.177628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6221 00:59:27.180553 [CA 0] Center 36 (8~64) winsize 57
6222 00:59:27.184227 [CA 1] Center 36 (8~64) winsize 57
6223 00:59:27.187087 [CA 2] Center 36 (8~64) winsize 57
6224 00:59:27.190722 [CA 3] Center 36 (8~64) winsize 57
6225 00:59:27.193417 [CA 4] Center 36 (8~64) winsize 57
6226 00:59:27.196934 [CA 5] Center 36 (8~64) winsize 57
6227 00:59:27.197128
6228 00:59:27.200045 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6229 00:59:27.200126
6230 00:59:27.203444 [CATrainingPosCal] consider 2 rank data
6231 00:59:27.206491 u2DelayCellTimex100 = 270/100 ps
6232 00:59:27.210080 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 00:59:27.213764 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 00:59:27.216324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 00:59:27.219651 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 00:59:27.223590 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 00:59:27.226448 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 00:59:27.226529
6239 00:59:27.233254 CA PerBit enable=1, Macro0, CA PI delay=36
6240 00:59:27.233336
6241 00:59:27.236601 [CBTSetCACLKResult] CA Dly = 36
6242 00:59:27.236683 CS Dly: 1 (0~32)
6243 00:59:27.236746
6244 00:59:27.239391 ----->DramcWriteLeveling(PI) begin...
6245 00:59:27.239487 ==
6246 00:59:27.242834 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 00:59:27.245919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 00:59:27.249765 ==
6249 00:59:27.249847 Write leveling (Byte 0): 40 => 8
6250 00:59:27.252654 Write leveling (Byte 1): 40 => 8
6251 00:59:27.255734 DramcWriteLeveling(PI) end<-----
6252 00:59:27.255831
6253 00:59:27.255924 ==
6254 00:59:27.258961 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 00:59:27.265721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 00:59:27.265804 ==
6257 00:59:27.269163 [Gating] SW mode calibration
6258 00:59:27.275511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6259 00:59:27.278999 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6260 00:59:27.285675 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 00:59:27.288950 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 00:59:27.291889 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 00:59:27.298372 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 00:59:27.301925 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 00:59:27.305425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 00:59:27.311583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 00:59:27.315111 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 00:59:27.318866 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 00:59:27.321985 Total UI for P1: 0, mck2ui 16
6270 00:59:27.324876 best dqsien dly found for B0: ( 0, 14, 24)
6271 00:59:27.328479 Total UI for P1: 0, mck2ui 16
6272 00:59:27.332278 best dqsien dly found for B1: ( 0, 14, 24)
6273 00:59:27.335268 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6274 00:59:27.338330 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6275 00:59:27.338411
6276 00:59:27.344557 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 00:59:27.347893 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 00:59:27.351277 [Gating] SW calibration Done
6279 00:59:27.351358 ==
6280 00:59:27.355058 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 00:59:27.357760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 00:59:27.357842 ==
6283 00:59:27.357905 RX Vref Scan: 0
6284 00:59:27.357963
6285 00:59:27.361258 RX Vref 0 -> 0, step: 1
6286 00:59:27.361340
6287 00:59:27.364362 RX Delay -410 -> 252, step: 16
6288 00:59:27.367400 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6289 00:59:27.374111 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6290 00:59:27.378009 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6291 00:59:27.380600 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6292 00:59:27.384098 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6293 00:59:27.390549 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6294 00:59:27.394047 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6295 00:59:27.397545 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6296 00:59:27.400588 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6297 00:59:27.407043 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6298 00:59:27.410178 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6299 00:59:27.413564 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6300 00:59:27.421007 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6301 00:59:27.423276 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6302 00:59:27.426794 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6303 00:59:27.429900 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6304 00:59:27.433849 ==
6305 00:59:27.433934 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 00:59:27.440187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 00:59:27.440268 ==
6308 00:59:27.440332 DQS Delay:
6309 00:59:27.443348 DQS0 = 35, DQS1 = 51
6310 00:59:27.443462 DQM Delay:
6311 00:59:27.446448 DQM0 = 4, DQM1 = 11
6312 00:59:27.446527 DQ Delay:
6313 00:59:27.449727 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6314 00:59:27.453260 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6315 00:59:27.456709 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6316 00:59:27.459661 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6317 00:59:27.459742
6318 00:59:27.459805
6319 00:59:27.459863 ==
6320 00:59:27.462861 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 00:59:27.466012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 00:59:27.466093 ==
6323 00:59:27.466156
6324 00:59:27.466215
6325 00:59:27.469748 TX Vref Scan disable
6326 00:59:27.469828 == TX Byte 0 ==
6327 00:59:27.476111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 00:59:27.479196 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 00:59:27.479276 == TX Byte 1 ==
6330 00:59:27.486001 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 00:59:27.489669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 00:59:27.489749 ==
6333 00:59:27.492837 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 00:59:27.495952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 00:59:27.496033 ==
6336 00:59:27.496095
6337 00:59:27.496153
6338 00:59:27.498767 TX Vref Scan disable
6339 00:59:27.503843 == TX Byte 0 ==
6340 00:59:27.505622 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 00:59:27.509119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 00:59:27.509199 == TX Byte 1 ==
6343 00:59:27.515517 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 00:59:27.518660 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 00:59:27.518739
6346 00:59:27.518802 [DATLAT]
6347 00:59:27.522061 Freq=400, CH0 RK0
6348 00:59:27.522141
6349 00:59:27.522204 DATLAT Default: 0xf
6350 00:59:27.525504 0, 0xFFFF, sum = 0
6351 00:59:27.525585 1, 0xFFFF, sum = 0
6352 00:59:27.528547 2, 0xFFFF, sum = 0
6353 00:59:27.532348 3, 0xFFFF, sum = 0
6354 00:59:27.532429 4, 0xFFFF, sum = 0
6355 00:59:27.535236 5, 0xFFFF, sum = 0
6356 00:59:27.535343 6, 0xFFFF, sum = 0
6357 00:59:27.538614 7, 0xFFFF, sum = 0
6358 00:59:27.538694 8, 0xFFFF, sum = 0
6359 00:59:27.541690 9, 0xFFFF, sum = 0
6360 00:59:27.541771 10, 0xFFFF, sum = 0
6361 00:59:27.544865 11, 0xFFFF, sum = 0
6362 00:59:27.544945 12, 0xFFFF, sum = 0
6363 00:59:27.548555 13, 0x0, sum = 1
6364 00:59:27.548636 14, 0x0, sum = 2
6365 00:59:27.551701 15, 0x0, sum = 3
6366 00:59:27.551783 16, 0x0, sum = 4
6367 00:59:27.554827 best_step = 14
6368 00:59:27.554906
6369 00:59:27.554968 ==
6370 00:59:27.558091 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 00:59:27.561680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 00:59:27.561761 ==
6373 00:59:27.564962 RX Vref Scan: 1
6374 00:59:27.565047
6375 00:59:27.565110 RX Vref 0 -> 0, step: 1
6376 00:59:27.565169
6377 00:59:27.568339 RX Delay -343 -> 252, step: 8
6378 00:59:27.568420
6379 00:59:27.571683 Set Vref, RX VrefLevel [Byte0]: 54
6380 00:59:27.574865 [Byte1]: 59
6381 00:59:27.579092
6382 00:59:27.579177 Final RX Vref Byte 0 = 54 to rank0
6383 00:59:27.582353 Final RX Vref Byte 1 = 59 to rank0
6384 00:59:27.586024 Final RX Vref Byte 0 = 54 to rank1
6385 00:59:27.588807 Final RX Vref Byte 1 = 59 to rank1==
6386 00:59:27.592340 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 00:59:27.598859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 00:59:27.598939 ==
6389 00:59:27.599002 DQS Delay:
6390 00:59:27.602518 DQS0 = 44, DQS1 = 60
6391 00:59:27.602623 DQM Delay:
6392 00:59:27.605596 DQM0 = 10, DQM1 = 16
6393 00:59:27.605677 DQ Delay:
6394 00:59:27.610020 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6395 00:59:27.611702 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6396 00:59:27.615597 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6397 00:59:27.618352 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6398 00:59:27.618437
6399 00:59:27.618509
6400 00:59:27.625044 [DQSOSCAuto] RK0, (LSB)MR18= 0x9285, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6401 00:59:27.628069 CH0 RK0: MR19=C0C, MR18=9285
6402 00:59:27.635142 CH0_RK0: MR19=0xC0C, MR18=0x9285, DQSOSC=391, MR23=63, INC=386, DEC=257
6403 00:59:27.635248 ==
6404 00:59:27.638547 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 00:59:27.641578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 00:59:27.641661 ==
6407 00:59:27.644657 [Gating] SW mode calibration
6408 00:59:27.651664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6409 00:59:27.658114 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6410 00:59:27.661318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 00:59:27.667813 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 00:59:27.671133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 00:59:27.674643 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 00:59:27.680996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 00:59:27.684066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 00:59:27.687546 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 00:59:27.694352 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 00:59:27.697420 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 00:59:27.700599 Total UI for P1: 0, mck2ui 16
6420 00:59:27.704620 best dqsien dly found for B0: ( 0, 14, 24)
6421 00:59:27.707527 Total UI for P1: 0, mck2ui 16
6422 00:59:27.711032 best dqsien dly found for B1: ( 0, 14, 24)
6423 00:59:27.713989 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6424 00:59:27.717558 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6425 00:59:27.717640
6426 00:59:27.720772 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 00:59:27.724837 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 00:59:27.726966 [Gating] SW calibration Done
6429 00:59:27.727047 ==
6430 00:59:27.730495 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 00:59:27.733688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 00:59:27.736891 ==
6433 00:59:27.736972 RX Vref Scan: 0
6434 00:59:27.737035
6435 00:59:27.739963 RX Vref 0 -> 0, step: 1
6436 00:59:27.740045
6437 00:59:27.743430 RX Delay -410 -> 252, step: 16
6438 00:59:27.746780 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6439 00:59:27.749994 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6440 00:59:27.756543 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6441 00:59:27.759936 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6442 00:59:27.762890 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6443 00:59:27.766651 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6444 00:59:27.772897 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6445 00:59:27.776076 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6446 00:59:27.779514 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6447 00:59:27.782734 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6448 00:59:27.789364 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6449 00:59:27.792822 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6450 00:59:27.796085 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6451 00:59:27.802366 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6452 00:59:27.806173 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6453 00:59:27.809391 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6454 00:59:27.809472 ==
6455 00:59:27.812688 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 00:59:27.815978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 00:59:27.816059 ==
6458 00:59:27.819140 DQS Delay:
6459 00:59:27.819220 DQS0 = 35, DQS1 = 59
6460 00:59:27.822136 DQM Delay:
6461 00:59:27.822217 DQM0 = 7, DQM1 = 16
6462 00:59:27.825452 DQ Delay:
6463 00:59:27.825532 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6464 00:59:27.828968 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6465 00:59:27.831882 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6466 00:59:27.835283 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6467 00:59:27.835421
6468 00:59:27.835486
6469 00:59:27.835544 ==
6470 00:59:27.838503 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 00:59:27.844990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 00:59:27.845071 ==
6473 00:59:27.845134
6474 00:59:27.845192
6475 00:59:27.845249 TX Vref Scan disable
6476 00:59:27.848924 == TX Byte 0 ==
6477 00:59:27.852168 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6478 00:59:27.855116 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6479 00:59:27.858385 == TX Byte 1 ==
6480 00:59:27.861538 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6481 00:59:27.865602 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6482 00:59:27.868906 ==
6483 00:59:27.871717 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 00:59:27.875033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 00:59:27.875114 ==
6486 00:59:27.875177
6487 00:59:27.875235
6488 00:59:27.878287 TX Vref Scan disable
6489 00:59:27.878367 == TX Byte 0 ==
6490 00:59:27.881958 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 00:59:27.888149 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 00:59:27.888230 == TX Byte 1 ==
6493 00:59:27.891225 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6494 00:59:27.898160 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6495 00:59:27.898242
6496 00:59:27.898305 [DATLAT]
6497 00:59:27.898364 Freq=400, CH0 RK1
6498 00:59:27.898421
6499 00:59:27.901001 DATLAT Default: 0xe
6500 00:59:27.904319 0, 0xFFFF, sum = 0
6501 00:59:27.904402 1, 0xFFFF, sum = 0
6502 00:59:27.907543 2, 0xFFFF, sum = 0
6503 00:59:27.907625 3, 0xFFFF, sum = 0
6504 00:59:27.910888 4, 0xFFFF, sum = 0
6505 00:59:27.910971 5, 0xFFFF, sum = 0
6506 00:59:27.914033 6, 0xFFFF, sum = 0
6507 00:59:27.914115 7, 0xFFFF, sum = 0
6508 00:59:27.918346 8, 0xFFFF, sum = 0
6509 00:59:27.918428 9, 0xFFFF, sum = 0
6510 00:59:27.921297 10, 0xFFFF, sum = 0
6511 00:59:27.921374 11, 0xFFFF, sum = 0
6512 00:59:27.923921 12, 0xFFFF, sum = 0
6513 00:59:27.923992 13, 0x0, sum = 1
6514 00:59:27.927263 14, 0x0, sum = 2
6515 00:59:27.927360 15, 0x0, sum = 3
6516 00:59:27.930744 16, 0x0, sum = 4
6517 00:59:27.930826 best_step = 14
6518 00:59:27.930889
6519 00:59:27.930946 ==
6520 00:59:27.933944 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 00:59:27.940943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 00:59:27.941024 ==
6523 00:59:27.941086 RX Vref Scan: 0
6524 00:59:27.941145
6525 00:59:27.944116 RX Vref 0 -> 0, step: 1
6526 00:59:27.944196
6527 00:59:27.946915 RX Delay -359 -> 252, step: 8
6528 00:59:27.953627 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6529 00:59:27.956931 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6530 00:59:27.960506 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6531 00:59:27.963625 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6532 00:59:27.970147 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6533 00:59:27.973491 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6534 00:59:27.977076 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6535 00:59:27.979772 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6536 00:59:27.986654 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6537 00:59:27.989948 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6538 00:59:27.993067 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6539 00:59:27.999785 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6540 00:59:28.003052 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6541 00:59:28.006479 iDelay=209, Bit 13, Center -40 (-287 ~ 208) 496
6542 00:59:28.009649 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6543 00:59:28.016530 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6544 00:59:28.016611 ==
6545 00:59:28.019619 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 00:59:28.023022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 00:59:28.023103 ==
6548 00:59:28.023166 DQS Delay:
6549 00:59:28.026083 DQS0 = 44, DQS1 = 60
6550 00:59:28.026164 DQM Delay:
6551 00:59:28.029598 DQM0 = 9, DQM1 = 15
6552 00:59:28.029678 DQ Delay:
6553 00:59:28.032704 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6554 00:59:28.036081 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6555 00:59:28.039372 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6556 00:59:28.043156 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6557 00:59:28.043236
6558 00:59:28.043313
6559 00:59:28.049356 [DQSOSCAuto] RK1, (LSB)MR18= 0x867d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6560 00:59:28.052441 CH0 RK1: MR19=C0C, MR18=867D
6561 00:59:28.059635 CH0_RK1: MR19=0xC0C, MR18=0x867D, DQSOSC=393, MR23=63, INC=382, DEC=254
6562 00:59:28.062838 [RxdqsGatingPostProcess] freq 400
6563 00:59:28.069216 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6564 00:59:28.072420 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 00:59:28.075459 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 00:59:28.078921 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 00:59:28.081982 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 00:59:28.082063 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 00:59:28.085446 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 00:59:28.088695 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 00:59:28.092127 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 00:59:28.095450 Pre-setting of DQS Precalculation
6573 00:59:28.102337 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6574 00:59:28.102419 ==
6575 00:59:28.105522 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 00:59:28.108339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 00:59:28.108420 ==
6578 00:59:28.114858 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6579 00:59:28.122399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6580 00:59:28.125152 [CA 0] Center 36 (8~64) winsize 57
6581 00:59:28.128483 [CA 1] Center 36 (8~64) winsize 57
6582 00:59:28.132006 [CA 2] Center 36 (8~64) winsize 57
6583 00:59:28.132419 [CA 3] Center 36 (8~64) winsize 57
6584 00:59:28.135719 [CA 4] Center 36 (8~64) winsize 57
6585 00:59:28.138769 [CA 5] Center 36 (8~64) winsize 57
6586 00:59:28.139185
6587 00:59:28.145269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6588 00:59:28.145684
6589 00:59:28.148346 [CATrainingPosCal] consider 1 rank data
6590 00:59:28.152077 u2DelayCellTimex100 = 270/100 ps
6591 00:59:28.154904 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 00:59:28.158563 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 00:59:28.162087 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 00:59:28.164612 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 00:59:28.168035 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 00:59:28.171654 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 00:59:28.172071
6598 00:59:28.174690 CA PerBit enable=1, Macro0, CA PI delay=36
6599 00:59:28.175103
6600 00:59:28.177765 [CBTSetCACLKResult] CA Dly = 36
6601 00:59:28.181295 CS Dly: 1 (0~32)
6602 00:59:28.181704 ==
6603 00:59:28.184593 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 00:59:28.187790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 00:59:28.188210 ==
6606 00:59:28.194751 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 00:59:28.201132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6608 00:59:28.204279 [CA 0] Center 36 (8~64) winsize 57
6609 00:59:28.207614 [CA 1] Center 36 (8~64) winsize 57
6610 00:59:28.208033 [CA 2] Center 36 (8~64) winsize 57
6611 00:59:28.210618 [CA 3] Center 36 (8~64) winsize 57
6612 00:59:28.213825 [CA 4] Center 36 (8~64) winsize 57
6613 00:59:28.217676 [CA 5] Center 36 (8~64) winsize 57
6614 00:59:28.218090
6615 00:59:28.221109 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6616 00:59:28.223887
6617 00:59:28.227325 [CATrainingPosCal] consider 2 rank data
6618 00:59:28.227794 u2DelayCellTimex100 = 270/100 ps
6619 00:59:28.233595 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 00:59:28.236944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 00:59:28.240280 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 00:59:28.245461 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 00:59:28.246437 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 00:59:28.249971 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 00:59:28.250054
6626 00:59:28.253002 CA PerBit enable=1, Macro0, CA PI delay=36
6627 00:59:28.253083
6628 00:59:28.256281 [CBTSetCACLKResult] CA Dly = 36
6629 00:59:28.259369 CS Dly: 1 (0~32)
6630 00:59:28.259465
6631 00:59:28.263050 ----->DramcWriteLeveling(PI) begin...
6632 00:59:28.263513 ==
6633 00:59:28.266326 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 00:59:28.269630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 00:59:28.270284 ==
6636 00:59:28.273426 Write leveling (Byte 0): 40 => 8
6637 00:59:28.276369 Write leveling (Byte 1): 40 => 8
6638 00:59:28.279651 DramcWriteLeveling(PI) end<-----
6639 00:59:28.280065
6640 00:59:28.280389 ==
6641 00:59:28.282965 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 00:59:28.286066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 00:59:28.286483 ==
6644 00:59:28.289870 [Gating] SW mode calibration
6645 00:59:28.296255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 00:59:28.302739 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6647 00:59:28.306311 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 00:59:28.312556 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 00:59:28.316331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 00:59:28.319129 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 00:59:28.325956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 00:59:28.329224 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 00:59:28.333214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 00:59:28.339227 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 00:59:28.342487 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 00:59:28.345451 Total UI for P1: 0, mck2ui 16
6657 00:59:28.349301 best dqsien dly found for B0: ( 0, 14, 24)
6658 00:59:28.352051 Total UI for P1: 0, mck2ui 16
6659 00:59:28.355687 best dqsien dly found for B1: ( 0, 14, 24)
6660 00:59:28.358350 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6661 00:59:28.362332 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6662 00:59:28.362848
6663 00:59:28.365349 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 00:59:28.371546 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 00:59:28.372054 [Gating] SW calibration Done
6666 00:59:28.372389 ==
6667 00:59:28.375278 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 00:59:28.381479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 00:59:28.382033 ==
6670 00:59:28.382402 RX Vref Scan: 0
6671 00:59:28.382794
6672 00:59:28.385706 RX Vref 0 -> 0, step: 1
6673 00:59:28.386255
6674 00:59:28.388093 RX Delay -410 -> 252, step: 16
6675 00:59:28.391427 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6676 00:59:28.394754 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6677 00:59:28.401055 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6678 00:59:28.404321 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6679 00:59:28.407728 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6680 00:59:28.412345 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6681 00:59:28.418331 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6682 00:59:28.420772 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6683 00:59:28.423991 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6684 00:59:28.427278 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6685 00:59:28.434160 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6686 00:59:28.437734 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6687 00:59:28.440887 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6688 00:59:28.448190 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6689 00:59:28.450718 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6690 00:59:28.453314 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6691 00:59:28.453900 ==
6692 00:59:28.456855 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 00:59:28.463189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 00:59:28.463655 ==
6695 00:59:28.464002 DQS Delay:
6696 00:59:28.466642 DQS0 = 35, DQS1 = 51
6697 00:59:28.467055 DQM Delay:
6698 00:59:28.467436 DQM0 = 6, DQM1 = 13
6699 00:59:28.470321 DQ Delay:
6700 00:59:28.473618 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6701 00:59:28.474034 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6702 00:59:28.476670 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 00:59:28.480265 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6704 00:59:28.480768
6705 00:59:28.483934
6706 00:59:28.484347 ==
6707 00:59:28.487235 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 00:59:28.489879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 00:59:28.490387 ==
6710 00:59:28.490717
6711 00:59:28.491021
6712 00:59:28.493732 TX Vref Scan disable
6713 00:59:28.494238 == TX Byte 0 ==
6714 00:59:28.496631 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 00:59:28.503320 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 00:59:28.503874 == TX Byte 1 ==
6717 00:59:28.506024 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 00:59:28.513177 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 00:59:28.513732 ==
6720 00:59:28.516397 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 00:59:28.520007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 00:59:28.520566 ==
6723 00:59:28.520930
6724 00:59:28.521269
6725 00:59:28.522373 TX Vref Scan disable
6726 00:59:28.522852 == TX Byte 0 ==
6727 00:59:28.528840 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 00:59:28.532983 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 00:59:28.533525 == TX Byte 1 ==
6730 00:59:28.539101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 00:59:28.542299 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 00:59:28.542819
6733 00:59:28.543148 [DATLAT]
6734 00:59:28.546196 Freq=400, CH1 RK0
6735 00:59:28.546657
6736 00:59:28.547012 DATLAT Default: 0xf
6737 00:59:28.548936 0, 0xFFFF, sum = 0
6738 00:59:28.549491 1, 0xFFFF, sum = 0
6739 00:59:28.552326 2, 0xFFFF, sum = 0
6740 00:59:28.552900 3, 0xFFFF, sum = 0
6741 00:59:28.555506 4, 0xFFFF, sum = 0
6742 00:59:28.556039 5, 0xFFFF, sum = 0
6743 00:59:28.559460 6, 0xFFFF, sum = 0
6744 00:59:28.560037 7, 0xFFFF, sum = 0
6745 00:59:28.561923 8, 0xFFFF, sum = 0
6746 00:59:28.565648 9, 0xFFFF, sum = 0
6747 00:59:28.566118 10, 0xFFFF, sum = 0
6748 00:59:28.568611 11, 0xFFFF, sum = 0
6749 00:59:28.569168 12, 0xFFFF, sum = 0
6750 00:59:28.571860 13, 0x0, sum = 1
6751 00:59:28.572424 14, 0x0, sum = 2
6752 00:59:28.575212 15, 0x0, sum = 3
6753 00:59:28.576053 16, 0x0, sum = 4
6754 00:59:28.578704 best_step = 14
6755 00:59:28.579163
6756 00:59:28.579583 ==
6757 00:59:28.582337 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 00:59:28.584865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 00:59:28.585418 ==
6760 00:59:28.585785 RX Vref Scan: 1
6761 00:59:28.588064
6762 00:59:28.588521 RX Vref 0 -> 0, step: 1
6763 00:59:28.588882
6764 00:59:28.591401 RX Delay -343 -> 252, step: 8
6765 00:59:28.591969
6766 00:59:28.594672 Set Vref, RX VrefLevel [Byte0]: 52
6767 00:59:28.598025 [Byte1]: 53
6768 00:59:28.602747
6769 00:59:28.603302 Final RX Vref Byte 0 = 52 to rank0
6770 00:59:28.605357 Final RX Vref Byte 1 = 53 to rank0
6771 00:59:28.609108 Final RX Vref Byte 0 = 52 to rank1
6772 00:59:28.613295 Final RX Vref Byte 1 = 53 to rank1==
6773 00:59:28.615073 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 00:59:28.622110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 00:59:28.622781 ==
6776 00:59:28.623153 DQS Delay:
6777 00:59:28.625152 DQS0 = 44, DQS1 = 52
6778 00:59:28.625609 DQM Delay:
6779 00:59:28.625963 DQM0 = 11, DQM1 = 10
6780 00:59:28.628643 DQ Delay:
6781 00:59:28.632031 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6782 00:59:28.635287 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6783 00:59:28.635907 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6784 00:59:28.642024 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6785 00:59:28.642575
6786 00:59:28.642937
6787 00:59:28.648799 [DQSOSCAuto] RK0, (LSB)MR18= 0x678e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6788 00:59:28.651483 CH1 RK0: MR19=C0C, MR18=678E
6789 00:59:28.658040 CH1_RK0: MR19=0xC0C, MR18=0x678E, DQSOSC=392, MR23=63, INC=384, DEC=256
6790 00:59:28.658602 ==
6791 00:59:28.661870 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 00:59:28.664527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 00:59:28.664994 ==
6794 00:59:28.668340 [Gating] SW mode calibration
6795 00:59:28.674693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6796 00:59:28.681358 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6797 00:59:28.684446 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 00:59:28.687842 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 00:59:28.695206 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 00:59:28.697797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 00:59:28.701103 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 00:59:28.707461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 00:59:28.710731 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 00:59:28.714106 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 00:59:28.720388 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 00:59:28.723712 Total UI for P1: 0, mck2ui 16
6807 00:59:28.726977 best dqsien dly found for B0: ( 0, 14, 24)
6808 00:59:28.730929 Total UI for P1: 0, mck2ui 16
6809 00:59:28.733706 best dqsien dly found for B1: ( 0, 14, 24)
6810 00:59:28.736791 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6811 00:59:28.740269 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6812 00:59:28.740685
6813 00:59:28.743679 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 00:59:28.746533 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 00:59:28.750228 [Gating] SW calibration Done
6816 00:59:28.750737 ==
6817 00:59:28.753442 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 00:59:28.756756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 00:59:28.757176 ==
6820 00:59:28.759762 RX Vref Scan: 0
6821 00:59:28.760179
6822 00:59:28.763134 RX Vref 0 -> 0, step: 1
6823 00:59:28.763602
6824 00:59:28.766946 RX Delay -410 -> 252, step: 16
6825 00:59:28.770291 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6826 00:59:28.773098 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6827 00:59:28.777068 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6828 00:59:28.783267 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6829 00:59:28.786824 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6830 00:59:28.789888 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6831 00:59:28.792889 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6832 00:59:28.800285 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6833 00:59:28.802792 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6834 00:59:28.805914 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6835 00:59:28.809314 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6836 00:59:28.816290 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6837 00:59:28.819793 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6838 00:59:28.822791 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6839 00:59:28.829150 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6840 00:59:28.832799 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6841 00:59:28.833317 ==
6842 00:59:28.836031 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 00:59:28.838895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 00:59:28.839313 ==
6845 00:59:28.842356 DQS Delay:
6846 00:59:28.842873 DQS0 = 43, DQS1 = 51
6847 00:59:28.843202 DQM Delay:
6848 00:59:28.845864 DQM0 = 10, DQM1 = 14
6849 00:59:28.846361 DQ Delay:
6850 00:59:28.848631 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6851 00:59:28.852125 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6852 00:59:28.855430 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6853 00:59:28.858660 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6854 00:59:28.859193
6855 00:59:28.859651
6856 00:59:28.859970 ==
6857 00:59:28.862818 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 00:59:28.868651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 00:59:28.869169 ==
6860 00:59:28.869502
6861 00:59:28.869810
6862 00:59:28.870103 TX Vref Scan disable
6863 00:59:28.872271 == TX Byte 0 ==
6864 00:59:28.874960 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6865 00:59:28.878715 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6866 00:59:28.881958 == TX Byte 1 ==
6867 00:59:28.885344 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6868 00:59:28.888125 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6869 00:59:28.888557 ==
6870 00:59:28.891785 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 00:59:28.899734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 00:59:28.900248 ==
6873 00:59:28.900623
6874 00:59:28.900935
6875 00:59:28.901231 TX Vref Scan disable
6876 00:59:28.901863 == TX Byte 0 ==
6877 00:59:28.904780 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 00:59:28.908089 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 00:59:28.911534 == TX Byte 1 ==
6880 00:59:28.914684 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6881 00:59:28.918029 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6882 00:59:28.921086
6883 00:59:28.921498 [DATLAT]
6884 00:59:28.921824 Freq=400, CH1 RK1
6885 00:59:28.922132
6886 00:59:28.924428 DATLAT Default: 0xe
6887 00:59:28.924859 0, 0xFFFF, sum = 0
6888 00:59:28.927477 1, 0xFFFF, sum = 0
6889 00:59:28.928075 2, 0xFFFF, sum = 0
6890 00:59:28.930924 3, 0xFFFF, sum = 0
6891 00:59:28.934666 4, 0xFFFF, sum = 0
6892 00:59:28.935182 5, 0xFFFF, sum = 0
6893 00:59:28.937800 6, 0xFFFF, sum = 0
6894 00:59:28.938335 7, 0xFFFF, sum = 0
6895 00:59:28.941121 8, 0xFFFF, sum = 0
6896 00:59:28.941638 9, 0xFFFF, sum = 0
6897 00:59:28.944326 10, 0xFFFF, sum = 0
6898 00:59:28.944751 11, 0xFFFF, sum = 0
6899 00:59:28.947132 12, 0xFFFF, sum = 0
6900 00:59:28.947617 13, 0x0, sum = 1
6901 00:59:28.950979 14, 0x0, sum = 2
6902 00:59:28.951541 15, 0x0, sum = 3
6903 00:59:28.954326 16, 0x0, sum = 4
6904 00:59:28.954842 best_step = 14
6905 00:59:28.955179
6906 00:59:28.955544 ==
6907 00:59:28.957658 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 00:59:28.960418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 00:59:28.964066 ==
6910 00:59:28.964743 RX Vref Scan: 0
6911 00:59:28.965093
6912 00:59:28.967433 RX Vref 0 -> 0, step: 1
6913 00:59:28.967850
6914 00:59:28.970288 RX Delay -343 -> 252, step: 8
6915 00:59:28.977199 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6916 00:59:28.981064 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6917 00:59:28.983708 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6918 00:59:28.987207 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6919 00:59:28.993816 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6920 00:59:28.997259 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6921 00:59:28.999991 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6922 00:59:29.003676 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6923 00:59:29.010495 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6924 00:59:29.013415 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6925 00:59:29.016827 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6926 00:59:29.020017 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6927 00:59:29.026317 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6928 00:59:29.029467 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6929 00:59:29.033249 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6930 00:59:29.039680 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6931 00:59:29.040240 ==
6932 00:59:29.043127 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 00:59:29.046386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 00:59:29.046912 ==
6935 00:59:29.047282 DQS Delay:
6936 00:59:29.049727 DQS0 = 48, DQS1 = 52
6937 00:59:29.050186 DQM Delay:
6938 00:59:29.053175 DQM0 = 11, DQM1 = 10
6939 00:59:29.053726 DQ Delay:
6940 00:59:29.056029 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6941 00:59:29.059597 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6942 00:59:29.063023 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6943 00:59:29.067089 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6944 00:59:29.067698
6945 00:59:29.068069
6946 00:59:29.072783 [DQSOSCAuto] RK1, (LSB)MR18= 0x6fa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6947 00:59:29.076448 CH1 RK1: MR19=C0C, MR18=6FA7
6948 00:59:29.082721 CH1_RK1: MR19=0xC0C, MR18=0x6FA7, DQSOSC=389, MR23=63, INC=390, DEC=260
6949 00:59:29.085935 [RxdqsGatingPostProcess] freq 400
6950 00:59:29.092629 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6951 00:59:29.096203 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 00:59:29.098972 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 00:59:29.102818 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 00:59:29.105188 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 00:59:29.105654 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 00:59:29.108584 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 00:59:29.112311 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 00:59:29.115032 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 00:59:29.118633 Pre-setting of DQS Precalculation
6960 00:59:29.125194 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6961 00:59:29.132059 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6962 00:59:29.139083 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6963 00:59:29.139703
6964 00:59:29.140068
6965 00:59:29.141781 [Calibration Summary] 800 Mbps
6966 00:59:29.142244 CH 0, Rank 0
6967 00:59:29.145010 SW Impedance : PASS
6968 00:59:29.148560 DUTY Scan : NO K
6969 00:59:29.149020 ZQ Calibration : PASS
6970 00:59:29.151577 Jitter Meter : NO K
6971 00:59:29.155051 CBT Training : PASS
6972 00:59:29.155662 Write leveling : PASS
6973 00:59:29.157821 RX DQS gating : PASS
6974 00:59:29.161418 RX DQ/DQS(RDDQC) : PASS
6975 00:59:29.161940 TX DQ/DQS : PASS
6976 00:59:29.164623 RX DATLAT : PASS
6977 00:59:29.167861 RX DQ/DQS(Engine): PASS
6978 00:59:29.168281 TX OE : NO K
6979 00:59:29.171469 All Pass.
6980 00:59:29.171975
6981 00:59:29.172308 CH 0, Rank 1
6982 00:59:29.174669 SW Impedance : PASS
6983 00:59:29.175179 DUTY Scan : NO K
6984 00:59:29.177942 ZQ Calibration : PASS
6985 00:59:29.181369 Jitter Meter : NO K
6986 00:59:29.181885 CBT Training : PASS
6987 00:59:29.184547 Write leveling : NO K
6988 00:59:29.187433 RX DQS gating : PASS
6989 00:59:29.187888 RX DQ/DQS(RDDQC) : PASS
6990 00:59:29.191734 TX DQ/DQS : PASS
6991 00:59:29.194769 RX DATLAT : PASS
6992 00:59:29.195282 RX DQ/DQS(Engine): PASS
6993 00:59:29.198265 TX OE : NO K
6994 00:59:29.198785 All Pass.
6995 00:59:29.199155
6996 00:59:29.200835 CH 1, Rank 0
6997 00:59:29.201286 SW Impedance : PASS
6998 00:59:29.204349 DUTY Scan : NO K
6999 00:59:29.207200 ZQ Calibration : PASS
7000 00:59:29.207663 Jitter Meter : NO K
7001 00:59:29.211712 CBT Training : PASS
7002 00:59:29.212223 Write leveling : PASS
7003 00:59:29.214158 RX DQS gating : PASS
7004 00:59:29.217114 RX DQ/DQS(RDDQC) : PASS
7005 00:59:29.217534 TX DQ/DQS : PASS
7006 00:59:29.220931 RX DATLAT : PASS
7007 00:59:29.223939 RX DQ/DQS(Engine): PASS
7008 00:59:29.224447 TX OE : NO K
7009 00:59:29.227408 All Pass.
7010 00:59:29.227933
7011 00:59:29.228263 CH 1, Rank 1
7012 00:59:29.230247 SW Impedance : PASS
7013 00:59:29.230664 DUTY Scan : NO K
7014 00:59:29.233649 ZQ Calibration : PASS
7015 00:59:29.236869 Jitter Meter : NO K
7016 00:59:29.237289 CBT Training : PASS
7017 00:59:29.240034 Write leveling : NO K
7018 00:59:29.243874 RX DQS gating : PASS
7019 00:59:29.244387 RX DQ/DQS(RDDQC) : PASS
7020 00:59:29.247190 TX DQ/DQS : PASS
7021 00:59:29.250263 RX DATLAT : PASS
7022 00:59:29.250773 RX DQ/DQS(Engine): PASS
7023 00:59:29.253527 TX OE : NO K
7024 00:59:29.254042 All Pass.
7025 00:59:29.254375
7026 00:59:29.256605 DramC Write-DBI off
7027 00:59:29.259802 PER_BANK_REFRESH: Hybrid Mode
7028 00:59:29.260264 TX_TRACKING: ON
7029 00:59:29.269802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7030 00:59:29.273512 [FAST_K] Save calibration result to emmc
7031 00:59:29.276515 dramc_set_vcore_voltage set vcore to 725000
7032 00:59:29.280170 Read voltage for 1600, 0
7033 00:59:29.280592 Vio18 = 0
7034 00:59:29.283519 Vcore = 725000
7035 00:59:29.284048 Vdram = 0
7036 00:59:29.284725 Vddq = 0
7037 00:59:29.285172 Vmddr = 0
7038 00:59:29.289400 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7039 00:59:29.296038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7040 00:59:29.296462 MEM_TYPE=3, freq_sel=13
7041 00:59:29.299505 sv_algorithm_assistance_LP4_3733
7042 00:59:29.302542 ============ PULL DRAM RESETB DOWN ============
7043 00:59:29.309818 ========== PULL DRAM RESETB DOWN end =========
7044 00:59:29.312466 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7045 00:59:29.315716 ===================================
7046 00:59:29.318930 LPDDR4 DRAM CONFIGURATION
7047 00:59:29.322587 ===================================
7048 00:59:29.323003 EX_ROW_EN[0] = 0x0
7049 00:59:29.325729 EX_ROW_EN[1] = 0x0
7050 00:59:29.326144 LP4Y_EN = 0x0
7051 00:59:29.329133 WORK_FSP = 0x1
7052 00:59:29.332500 WL = 0x5
7053 00:59:29.332914 RL = 0x5
7054 00:59:29.335922 BL = 0x2
7055 00:59:29.336335 RPST = 0x0
7056 00:59:29.339054 RD_PRE = 0x0
7057 00:59:29.339493 WR_PRE = 0x1
7058 00:59:29.341968 WR_PST = 0x1
7059 00:59:29.342318 DBI_WR = 0x0
7060 00:59:29.345533 DBI_RD = 0x0
7061 00:59:29.345948 OTF = 0x1
7062 00:59:29.348713 ===================================
7063 00:59:29.351912 ===================================
7064 00:59:29.355474 ANA top config
7065 00:59:29.358639 ===================================
7066 00:59:29.359061 DLL_ASYNC_EN = 0
7067 00:59:29.361788 ALL_SLAVE_EN = 0
7068 00:59:29.366004 NEW_RANK_MODE = 1
7069 00:59:29.368722 DLL_IDLE_MODE = 1
7070 00:59:29.371728 LP45_APHY_COMB_EN = 1
7071 00:59:29.372147 TX_ODT_DIS = 0
7072 00:59:29.375150 NEW_8X_MODE = 1
7073 00:59:29.378478 ===================================
7074 00:59:29.381684 ===================================
7075 00:59:29.385085 data_rate = 3200
7076 00:59:29.388497 CKR = 1
7077 00:59:29.392228 DQ_P2S_RATIO = 8
7078 00:59:29.394664 ===================================
7079 00:59:29.398188 CA_P2S_RATIO = 8
7080 00:59:29.398701 DQ_CA_OPEN = 0
7081 00:59:29.402237 DQ_SEMI_OPEN = 0
7082 00:59:29.404598 CA_SEMI_OPEN = 0
7083 00:59:29.407913 CA_FULL_RATE = 0
7084 00:59:29.411651 DQ_CKDIV4_EN = 0
7085 00:59:29.414901 CA_CKDIV4_EN = 0
7086 00:59:29.415453 CA_PREDIV_EN = 0
7087 00:59:29.417976 PH8_DLY = 12
7088 00:59:29.421270 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7089 00:59:29.424832 DQ_AAMCK_DIV = 4
7090 00:59:29.428041 CA_AAMCK_DIV = 4
7091 00:59:29.431283 CA_ADMCK_DIV = 4
7092 00:59:29.431732 DQ_TRACK_CA_EN = 0
7093 00:59:29.434643 CA_PICK = 1600
7094 00:59:29.437552 CA_MCKIO = 1600
7095 00:59:29.440783 MCKIO_SEMI = 0
7096 00:59:29.444047 PLL_FREQ = 3068
7097 00:59:29.447495 DQ_UI_PI_RATIO = 32
7098 00:59:29.450911 CA_UI_PI_RATIO = 0
7099 00:59:29.454510 ===================================
7100 00:59:29.457644 ===================================
7101 00:59:29.460392 memory_type:LPDDR4
7102 00:59:29.460912 GP_NUM : 10
7103 00:59:29.463727 SRAM_EN : 1
7104 00:59:29.464142 MD32_EN : 0
7105 00:59:29.467295 ===================================
7106 00:59:29.470204 [ANA_INIT] >>>>>>>>>>>>>>
7107 00:59:29.473792 <<<<<< [CONFIGURE PHASE]: ANA_TX
7108 00:59:29.476612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7109 00:59:29.480078 ===================================
7110 00:59:29.483748 data_rate = 3200,PCW = 0X7600
7111 00:59:29.487077 ===================================
7112 00:59:29.490274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7113 00:59:29.496736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 00:59:29.500003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 00:59:29.506438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7116 00:59:29.510324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7117 00:59:29.512969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7118 00:59:29.513387 [ANA_INIT] flow start
7119 00:59:29.516151 [ANA_INIT] PLL >>>>>>>>
7120 00:59:29.519892 [ANA_INIT] PLL <<<<<<<<
7121 00:59:29.522971 [ANA_INIT] MIDPI >>>>>>>>
7122 00:59:29.523529 [ANA_INIT] MIDPI <<<<<<<<
7123 00:59:29.526493 [ANA_INIT] DLL >>>>>>>>
7124 00:59:29.529381 [ANA_INIT] DLL <<<<<<<<
7125 00:59:29.529798 [ANA_INIT] flow end
7126 00:59:29.532987 ============ LP4 DIFF to SE enter ============
7127 00:59:29.539322 ============ LP4 DIFF to SE exit ============
7128 00:59:29.539783 [ANA_INIT] <<<<<<<<<<<<<
7129 00:59:29.542719 [Flow] Enable top DCM control >>>>>
7130 00:59:29.546078 [Flow] Enable top DCM control <<<<<
7131 00:59:29.549675 Enable DLL master slave shuffle
7132 00:59:29.555738 ==============================================================
7133 00:59:29.559154 Gating Mode config
7134 00:59:29.563163 ==============================================================
7135 00:59:29.566150 Config description:
7136 00:59:29.576566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7137 00:59:29.582643 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7138 00:59:29.585569 SELPH_MODE 0: By rank 1: By Phase
7139 00:59:29.592066 ==============================================================
7140 00:59:29.595774 GAT_TRACK_EN = 1
7141 00:59:29.598999 RX_GATING_MODE = 2
7142 00:59:29.602238 RX_GATING_TRACK_MODE = 2
7143 00:59:29.602653 SELPH_MODE = 1
7144 00:59:29.605503 PICG_EARLY_EN = 1
7145 00:59:29.608240 VALID_LAT_VALUE = 1
7146 00:59:29.614892 ==============================================================
7147 00:59:29.618191 Enter into Gating configuration >>>>
7148 00:59:29.622022 Exit from Gating configuration <<<<
7149 00:59:29.625117 Enter into DVFS_PRE_config >>>>>
7150 00:59:29.635053 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7151 00:59:29.638342 Exit from DVFS_PRE_config <<<<<
7152 00:59:29.641995 Enter into PICG configuration >>>>
7153 00:59:29.644867 Exit from PICG configuration <<<<
7154 00:59:29.648112 [RX_INPUT] configuration >>>>>
7155 00:59:29.651248 [RX_INPUT] configuration <<<<<
7156 00:59:29.657698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7157 00:59:29.661227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7158 00:59:29.668673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 00:59:29.674325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 00:59:29.681059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 00:59:29.687737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 00:59:29.690618 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7163 00:59:29.694401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7164 00:59:29.697710 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7165 00:59:29.704072 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7166 00:59:29.707146 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7167 00:59:29.710982 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 00:59:29.713970 ===================================
7169 00:59:29.717674 LPDDR4 DRAM CONFIGURATION
7170 00:59:29.720621 ===================================
7171 00:59:29.723932 EX_ROW_EN[0] = 0x0
7172 00:59:29.724346 EX_ROW_EN[1] = 0x0
7173 00:59:29.726943 LP4Y_EN = 0x0
7174 00:59:29.727500 WORK_FSP = 0x1
7175 00:59:29.730550 WL = 0x5
7176 00:59:29.730966 RL = 0x5
7177 00:59:29.733867 BL = 0x2
7178 00:59:29.734295 RPST = 0x0
7179 00:59:29.736979 RD_PRE = 0x0
7180 00:59:29.737395 WR_PRE = 0x1
7181 00:59:29.740350 WR_PST = 0x1
7182 00:59:29.740813 DBI_WR = 0x0
7183 00:59:29.743447 DBI_RD = 0x0
7184 00:59:29.743874 OTF = 0x1
7185 00:59:29.746678 ===================================
7186 00:59:29.753668 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7187 00:59:29.756653 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7188 00:59:29.759863 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 00:59:29.763886 ===================================
7190 00:59:29.767240 LPDDR4 DRAM CONFIGURATION
7191 00:59:29.770159 ===================================
7192 00:59:29.773262 EX_ROW_EN[0] = 0x10
7193 00:59:29.773879 EX_ROW_EN[1] = 0x0
7194 00:59:29.777063 LP4Y_EN = 0x0
7195 00:59:29.777620 WORK_FSP = 0x1
7196 00:59:29.780006 WL = 0x5
7197 00:59:29.780464 RL = 0x5
7198 00:59:29.783532 BL = 0x2
7199 00:59:29.784081 RPST = 0x0
7200 00:59:29.786819 RD_PRE = 0x0
7201 00:59:29.787438 WR_PRE = 0x1
7202 00:59:29.790212 WR_PST = 0x1
7203 00:59:29.790760 DBI_WR = 0x0
7204 00:59:29.793453 DBI_RD = 0x0
7205 00:59:29.794006 OTF = 0x1
7206 00:59:29.796194 ===================================
7207 00:59:29.803263 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7208 00:59:29.803848 ==
7209 00:59:29.805901 Dram Type= 6, Freq= 0, CH_0, rank 0
7210 00:59:29.812884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7211 00:59:29.813445 ==
7212 00:59:29.813810 [Duty_Offset_Calibration]
7213 00:59:29.815938 B0:2 B1:0 CA:4
7214 00:59:29.816487
7215 00:59:29.819183 [DutyScan_Calibration_Flow] k_type=0
7216 00:59:29.828161
7217 00:59:29.828722 ==CLK 0==
7218 00:59:29.831097 Final CLK duty delay cell = -4
7219 00:59:29.834655 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7220 00:59:29.837515 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7221 00:59:29.841076 [-4] AVG Duty = 4937%(X100)
7222 00:59:29.841494
7223 00:59:29.844200 CH0 CLK Duty spec in!! Max-Min= 187%
7224 00:59:29.847345 [DutyScan_Calibration_Flow] ====Done====
7225 00:59:29.847828
7226 00:59:29.851044 [DutyScan_Calibration_Flow] k_type=1
7227 00:59:29.868233
7228 00:59:29.868803 ==DQS 0 ==
7229 00:59:29.871545 Final DQS duty delay cell = 0
7230 00:59:29.874892 [0] MAX Duty = 5249%(X100), DQS PI = 38
7231 00:59:29.878058 [0] MIN Duty = 5093%(X100), DQS PI = 4
7232 00:59:29.881544 [0] AVG Duty = 5171%(X100)
7233 00:59:29.882088
7234 00:59:29.882447 ==DQS 1 ==
7235 00:59:29.884872 Final DQS duty delay cell = 0
7236 00:59:29.888244 [0] MAX Duty = 5187%(X100), DQS PI = 2
7237 00:59:29.891449 [0] MIN Duty = 4969%(X100), DQS PI = 10
7238 00:59:29.894445 [0] AVG Duty = 5078%(X100)
7239 00:59:29.894993
7240 00:59:29.898125 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7241 00:59:29.898677
7242 00:59:29.900972 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7243 00:59:29.904404 [DutyScan_Calibration_Flow] ====Done====
7244 00:59:29.904954
7245 00:59:29.907492 [DutyScan_Calibration_Flow] k_type=3
7246 00:59:29.925387
7247 00:59:29.925932 ==DQM 0 ==
7248 00:59:29.928537 Final DQM duty delay cell = 0
7249 00:59:29.931766 [0] MAX Duty = 5124%(X100), DQS PI = 22
7250 00:59:29.935007 [0] MIN Duty = 4875%(X100), DQS PI = 54
7251 00:59:29.938291 [0] AVG Duty = 4999%(X100)
7252 00:59:29.938751
7253 00:59:29.939111 ==DQM 1 ==
7254 00:59:29.941288 Final DQM duty delay cell = 0
7255 00:59:29.945061 [0] MAX Duty = 5000%(X100), DQS PI = 4
7256 00:59:29.947868 [0] MIN Duty = 4844%(X100), DQS PI = 14
7257 00:59:29.951795 [0] AVG Duty = 4922%(X100)
7258 00:59:29.952334
7259 00:59:29.954560 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7260 00:59:29.954980
7261 00:59:29.958514 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7262 00:59:29.961848 [DutyScan_Calibration_Flow] ====Done====
7263 00:59:29.962339
7264 00:59:29.964401 [DutyScan_Calibration_Flow] k_type=2
7265 00:59:29.982896
7266 00:59:29.983483 ==DQ 0 ==
7267 00:59:29.985788 Final DQ duty delay cell = 0
7268 00:59:29.988899 [0] MAX Duty = 5124%(X100), DQS PI = 22
7269 00:59:29.992365 [0] MIN Duty = 4938%(X100), DQS PI = 12
7270 00:59:29.992925 [0] AVG Duty = 5031%(X100)
7271 00:59:29.996242
7272 00:59:29.996796 ==DQ 1 ==
7273 00:59:29.998751 Final DQ duty delay cell = 0
7274 00:59:30.002034 [0] MAX Duty = 5187%(X100), DQS PI = 2
7275 00:59:30.005372 [0] MIN Duty = 4907%(X100), DQS PI = 32
7276 00:59:30.005839 [0] AVG Duty = 5047%(X100)
7277 00:59:30.008727
7278 00:59:30.012319 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7279 00:59:30.012867
7280 00:59:30.015608 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7281 00:59:30.018928 [DutyScan_Calibration_Flow] ====Done====
7282 00:59:30.019529 ==
7283 00:59:30.022019 Dram Type= 6, Freq= 0, CH_1, rank 0
7284 00:59:30.025790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 00:59:30.026347 ==
7286 00:59:30.028613 [Duty_Offset_Calibration]
7287 00:59:30.029072 B0:0 B1:-1 CA:3
7288 00:59:30.029429
7289 00:59:30.031337 [DutyScan_Calibration_Flow] k_type=0
7290 00:59:30.041885
7291 00:59:30.042437 ==CLK 0==
7292 00:59:30.045581 Final CLK duty delay cell = -4
7293 00:59:30.048525 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7294 00:59:30.051547 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7295 00:59:30.055002 [-4] AVG Duty = 4937%(X100)
7296 00:59:30.055487
7297 00:59:30.058279 CH1 CLK Duty spec in!! Max-Min= 187%
7298 00:59:30.061492 [DutyScan_Calibration_Flow] ====Done====
7299 00:59:30.061906
7300 00:59:30.064219 [DutyScan_Calibration_Flow] k_type=1
7301 00:59:30.081032
7302 00:59:30.081495 ==DQS 0 ==
7303 00:59:30.084172 Final DQS duty delay cell = 0
7304 00:59:30.087828 [0] MAX Duty = 5218%(X100), DQS PI = 20
7305 00:59:30.090857 [0] MIN Duty = 4907%(X100), DQS PI = 58
7306 00:59:30.094635 [0] AVG Duty = 5062%(X100)
7307 00:59:30.095142
7308 00:59:30.095522 ==DQS 1 ==
7309 00:59:30.097577 Final DQS duty delay cell = -4
7310 00:59:30.100750 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7311 00:59:30.104303 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7312 00:59:30.107716 [-4] AVG Duty = 4922%(X100)
7313 00:59:30.108129
7314 00:59:30.110976 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7315 00:59:30.111436
7316 00:59:30.114301 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7317 00:59:30.117116 [DutyScan_Calibration_Flow] ====Done====
7318 00:59:30.117528
7319 00:59:30.120251 [DutyScan_Calibration_Flow] k_type=3
7320 00:59:30.138971
7321 00:59:30.139577 ==DQM 0 ==
7322 00:59:30.141787 Final DQM duty delay cell = 0
7323 00:59:30.144889 [0] MAX Duty = 5062%(X100), DQS PI = 30
7324 00:59:30.148218 [0] MIN Duty = 4782%(X100), DQS PI = 38
7325 00:59:30.151638 [0] AVG Duty = 4922%(X100)
7326 00:59:30.152182
7327 00:59:30.152538 ==DQM 1 ==
7328 00:59:30.154744 Final DQM duty delay cell = 0
7329 00:59:30.158366 [0] MAX Duty = 5000%(X100), DQS PI = 32
7330 00:59:30.161334 [0] MIN Duty = 4813%(X100), DQS PI = 0
7331 00:59:30.164588 [0] AVG Duty = 4906%(X100)
7332 00:59:30.165143
7333 00:59:30.168141 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7334 00:59:30.168692
7335 00:59:30.171570 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7336 00:59:30.174663 [DutyScan_Calibration_Flow] ====Done====
7337 00:59:30.175207
7338 00:59:30.177908 [DutyScan_Calibration_Flow] k_type=2
7339 00:59:30.194879
7340 00:59:30.195473 ==DQ 0 ==
7341 00:59:30.197612 Final DQ duty delay cell = -4
7342 00:59:30.200908 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7343 00:59:30.204748 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7344 00:59:30.207353 [-4] AVG Duty = 4891%(X100)
7345 00:59:30.207869
7346 00:59:30.208230 ==DQ 1 ==
7347 00:59:30.211331 Final DQ duty delay cell = 0
7348 00:59:30.214349 [0] MAX Duty = 5031%(X100), DQS PI = 30
7349 00:59:30.217788 [0] MIN Duty = 4875%(X100), DQS PI = 0
7350 00:59:30.218339 [0] AVG Duty = 4953%(X100)
7351 00:59:30.221142
7352 00:59:30.224530 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7353 00:59:30.225101
7354 00:59:30.227493 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7355 00:59:30.230868 [DutyScan_Calibration_Flow] ====Done====
7356 00:59:30.234072 nWR fixed to 30
7357 00:59:30.237687 [ModeRegInit_LP4] CH0 RK0
7358 00:59:30.238199 [ModeRegInit_LP4] CH0 RK1
7359 00:59:30.240506 [ModeRegInit_LP4] CH1 RK0
7360 00:59:30.244038 [ModeRegInit_LP4] CH1 RK1
7361 00:59:30.244451 match AC timing 5
7362 00:59:30.250409 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7363 00:59:30.253988 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7364 00:59:30.257314 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7365 00:59:30.263899 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7366 00:59:30.267190 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7367 00:59:30.267701 [MiockJmeterHQA]
7368 00:59:30.268031
7369 00:59:30.270522 [DramcMiockJmeter] u1RxGatingPI = 0
7370 00:59:30.273892 0 : 4366, 4137
7371 00:59:30.274408 4 : 4252, 4027
7372 00:59:30.277306 8 : 4363, 4137
7373 00:59:30.277818 12 : 4253, 4026
7374 00:59:30.279896 16 : 4363, 4138
7375 00:59:30.280318 20 : 4252, 4026
7376 00:59:30.284050 24 : 4361, 4137
7377 00:59:30.284563 28 : 4252, 4027
7378 00:59:30.284896 32 : 4250, 4027
7379 00:59:30.286876 36 : 4250, 4027
7380 00:59:30.287435 40 : 4363, 4140
7381 00:59:30.290767 44 : 4361, 4137
7382 00:59:30.291275 48 : 4249, 4027
7383 00:59:30.293978 52 : 4250, 4026
7384 00:59:30.294506 56 : 4250, 4027
7385 00:59:30.296608 60 : 4249, 4027
7386 00:59:30.297124 64 : 4253, 4029
7387 00:59:30.297455 68 : 4361, 4137
7388 00:59:30.299614 72 : 4250, 4026
7389 00:59:30.300130 76 : 4249, 4027
7390 00:59:30.303115 80 : 4249, 4027
7391 00:59:30.303560 84 : 4252, 4030
7392 00:59:30.306389 88 : 4249, 4027
7393 00:59:30.306861 92 : 4360, 4137
7394 00:59:30.309808 96 : 4360, 3151
7395 00:59:30.310225 100 : 4249, 0
7396 00:59:30.310551 104 : 4363, 0
7397 00:59:30.313378 108 : 4252, 0
7398 00:59:30.313887 112 : 4250, 0
7399 00:59:30.315995 116 : 4250, 0
7400 00:59:30.316461 120 : 4253, 0
7401 00:59:30.316797 124 : 4249, 0
7402 00:59:30.319804 128 : 4250, 0
7403 00:59:30.320316 132 : 4253, 0
7404 00:59:30.320644 136 : 4360, 0
7405 00:59:30.323117 140 : 4249, 0
7406 00:59:30.323659 144 : 4361, 0
7407 00:59:30.326497 148 : 4253, 0
7408 00:59:30.327186 152 : 4360, 0
7409 00:59:30.327585 156 : 4249, 0
7410 00:59:30.329251 160 : 4250, 0
7411 00:59:30.329666 164 : 4250, 0
7412 00:59:30.332595 168 : 4249, 0
7413 00:59:30.333036 172 : 4253, 0
7414 00:59:30.333365 176 : 4249, 0
7415 00:59:30.335681 180 : 4249, 0
7416 00:59:30.336098 184 : 4253, 0
7417 00:59:30.339351 188 : 4360, 0
7418 00:59:30.339834 192 : 4249, 0
7419 00:59:30.340208 196 : 4361, 0
7420 00:59:30.342482 200 : 4361, 0
7421 00:59:30.342904 204 : 4360, 0
7422 00:59:30.346609 208 : 4363, 0
7423 00:59:30.347142 212 : 4250, 0
7424 00:59:30.347536 216 : 4250, 0
7425 00:59:30.349458 220 : 4250, 762
7426 00:59:30.349895 224 : 4255, 4020
7427 00:59:30.352102 228 : 4250, 4026
7428 00:59:30.352555 232 : 4361, 4137
7429 00:59:30.355488 236 : 4250, 4027
7430 00:59:30.355917 240 : 4250, 4027
7431 00:59:30.358971 244 : 4250, 4026
7432 00:59:30.359434 248 : 4253, 4029
7433 00:59:30.362122 252 : 4250, 4027
7434 00:59:30.362544 256 : 4250, 4027
7435 00:59:30.362932 260 : 4360, 4137
7436 00:59:30.365879 264 : 4250, 4026
7437 00:59:30.366342 268 : 4250, 4027
7438 00:59:30.369441 272 : 4360, 4138
7439 00:59:30.369865 276 : 4249, 4027
7440 00:59:30.372027 280 : 4250, 4026
7441 00:59:30.372663 284 : 4363, 4140
7442 00:59:30.375304 288 : 4250, 4027
7443 00:59:30.375770 292 : 4250, 4027
7444 00:59:30.378685 296 : 4250, 4026
7445 00:59:30.379229 300 : 4253, 4029
7446 00:59:30.382454 304 : 4250, 4027
7447 00:59:30.382881 308 : 4249, 4027
7448 00:59:30.385327 312 : 4360, 4137
7449 00:59:30.385752 316 : 4250, 4026
7450 00:59:30.388448 320 : 4250, 4027
7451 00:59:30.388873 324 : 4361, 4137
7452 00:59:30.389210 328 : 4249, 4027
7453 00:59:30.392105 332 : 4250, 3953
7454 00:59:30.392529 336 : 4363, 1755
7455 00:59:30.392863
7456 00:59:30.395078 MIOCK jitter meter ch=0
7457 00:59:30.395541
7458 00:59:30.398418 1T = (336-100) = 236 dly cells
7459 00:59:30.404942 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7460 00:59:30.405364 ==
7461 00:59:30.408842 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 00:59:30.411569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7463 00:59:30.411984 ==
7464 00:59:30.418184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7465 00:59:30.421770 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7466 00:59:30.425104 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7467 00:59:30.431139 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7468 00:59:30.441217 [CA 0] Center 44 (14~74) winsize 61
7469 00:59:30.444621 [CA 1] Center 43 (13~74) winsize 62
7470 00:59:30.447513 [CA 2] Center 39 (10~68) winsize 59
7471 00:59:30.450719 [CA 3] Center 38 (9~68) winsize 60
7472 00:59:30.454513 [CA 4] Center 36 (7~66) winsize 60
7473 00:59:30.457801 [CA 5] Center 36 (6~66) winsize 61
7474 00:59:30.458318
7475 00:59:30.461130 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7476 00:59:30.461553
7477 00:59:30.463906 [CATrainingPosCal] consider 1 rank data
7478 00:59:30.467168 u2DelayCellTimex100 = 275/100 ps
7479 00:59:30.473680 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7480 00:59:30.477344 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7481 00:59:30.480249 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7482 00:59:30.483953 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7483 00:59:30.487395 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7484 00:59:30.490652 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7485 00:59:30.491169
7486 00:59:30.493749 CA PerBit enable=1, Macro0, CA PI delay=36
7487 00:59:30.494255
7488 00:59:30.497084 [CBTSetCACLKResult] CA Dly = 36
7489 00:59:30.501151 CS Dly: 10 (0~41)
7490 00:59:30.503949 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7491 00:59:30.506788 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7492 00:59:30.507209 ==
7493 00:59:30.509991 Dram Type= 6, Freq= 0, CH_0, rank 1
7494 00:59:30.516773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 00:59:30.517256 ==
7496 00:59:30.519795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 00:59:30.526576 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 00:59:30.529972 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 00:59:30.536331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 00:59:30.544907 [CA 0] Center 44 (14~75) winsize 62
7501 00:59:30.547899 [CA 1] Center 43 (13~74) winsize 62
7502 00:59:30.551446 [CA 2] Center 38 (9~68) winsize 60
7503 00:59:30.554513 [CA 3] Center 38 (9~68) winsize 60
7504 00:59:30.557889 [CA 4] Center 37 (7~67) winsize 61
7505 00:59:30.560816 [CA 5] Center 36 (7~66) winsize 60
7506 00:59:30.561238
7507 00:59:30.563987 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 00:59:30.564408
7509 00:59:30.570785 [CATrainingPosCal] consider 2 rank data
7510 00:59:30.571544 u2DelayCellTimex100 = 275/100 ps
7511 00:59:30.577133 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7512 00:59:30.580909 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7513 00:59:30.584085 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7514 00:59:30.587517 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7515 00:59:30.590913 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7516 00:59:30.594230 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7517 00:59:30.594746
7518 00:59:30.597344 CA PerBit enable=1, Macro0, CA PI delay=36
7519 00:59:30.597857
7520 00:59:30.600198 [CBTSetCACLKResult] CA Dly = 36
7521 00:59:30.603836 CS Dly: 11 (0~43)
7522 00:59:30.606761 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 00:59:30.610241 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 00:59:30.610663
7525 00:59:30.613967 ----->DramcWriteLeveling(PI) begin...
7526 00:59:30.617181 ==
7527 00:59:30.620135 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 00:59:30.623616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 00:59:30.624124 ==
7530 00:59:30.626917 Write leveling (Byte 0): 33 => 33
7531 00:59:30.630203 Write leveling (Byte 1): 25 => 25
7532 00:59:30.633256 DramcWriteLeveling(PI) end<-----
7533 00:59:30.633681
7534 00:59:30.634101 ==
7535 00:59:30.636377 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 00:59:30.639838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 00:59:30.640263 ==
7538 00:59:30.643060 [Gating] SW mode calibration
7539 00:59:30.649970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7540 00:59:30.656982 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7541 00:59:30.659679 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 00:59:30.662922 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 00:59:30.669492 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 00:59:30.672878 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7545 00:59:30.675995 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7546 00:59:30.682573 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7547 00:59:30.685996 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 00:59:30.689230 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 00:59:30.695875 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 00:59:30.699338 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 00:59:30.702725 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7552 00:59:30.709081 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (0 1)
7553 00:59:30.712369 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7554 00:59:30.715579 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
7555 00:59:30.721856 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7556 00:59:30.725687 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 00:59:30.729005 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 00:59:30.735305 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 00:59:30.738727 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7560 00:59:30.742057 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7561 00:59:30.748193 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7562 00:59:30.751738 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7563 00:59:30.755747 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 00:59:30.761405 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 00:59:30.764820 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 00:59:30.767879 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 00:59:30.775577 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7568 00:59:30.778200 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 00:59:30.781211 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 00:59:30.787800 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 00:59:30.791553 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7572 00:59:30.794321 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 00:59:30.801780 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 00:59:30.804234 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 00:59:30.807747 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 00:59:30.814566 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 00:59:30.817547 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 00:59:30.821285 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 00:59:30.827491 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 00:59:30.831191 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 00:59:30.833993 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 00:59:30.840275 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 00:59:30.843553 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 00:59:30.847021 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 00:59:30.853747 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7586 00:59:30.856907 Total UI for P1: 0, mck2ui 16
7587 00:59:30.860342 best dqsien dly found for B0: ( 1, 9, 8)
7588 00:59:30.863604 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 00:59:30.866796 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 00:59:30.873328 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 00:59:30.877076 Total UI for P1: 0, mck2ui 16
7592 00:59:30.879935 best dqsien dly found for B1: ( 1, 9, 22)
7593 00:59:30.883213 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7594 00:59:30.886739 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7595 00:59:30.887278
7596 00:59:30.890686 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7597 00:59:30.893123 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7598 00:59:30.896297 [Gating] SW calibration Done
7599 00:59:30.896806 ==
7600 00:59:30.899749 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 00:59:30.903218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 00:59:30.903776 ==
7603 00:59:30.906706 RX Vref Scan: 0
7604 00:59:30.907216
7605 00:59:30.909645 RX Vref 0 -> 0, step: 1
7606 00:59:30.910078
7607 00:59:30.910421 RX Delay 0 -> 252, step: 8
7608 00:59:30.916155 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7609 00:59:30.918989 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7610 00:59:30.923260 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7611 00:59:30.926436 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7612 00:59:30.929258 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7613 00:59:30.935748 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7614 00:59:30.939055 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7615 00:59:30.942638 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7616 00:59:30.946026 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7617 00:59:30.948846 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7618 00:59:30.955731 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7619 00:59:30.959238 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7620 00:59:30.962322 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7621 00:59:30.966112 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7622 00:59:30.972462 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7623 00:59:30.975290 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7624 00:59:30.975733 ==
7625 00:59:30.978747 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 00:59:30.982247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 00:59:30.982793 ==
7628 00:59:30.985592 DQS Delay:
7629 00:59:30.986105 DQS0 = 0, DQS1 = 0
7630 00:59:30.986437 DQM Delay:
7631 00:59:30.988354 DQM0 = 131, DQM1 = 127
7632 00:59:30.988769 DQ Delay:
7633 00:59:30.992075 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7634 00:59:30.994710 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7635 00:59:31.002194 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7636 00:59:31.005343 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7637 00:59:31.005874
7638 00:59:31.006219
7639 00:59:31.006520 ==
7640 00:59:31.008561 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 00:59:31.011786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 00:59:31.012220 ==
7643 00:59:31.012651
7644 00:59:31.013061
7645 00:59:31.014819 TX Vref Scan disable
7646 00:59:31.019313 == TX Byte 0 ==
7647 00:59:31.021268 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7648 00:59:31.025072 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7649 00:59:31.028087 == TX Byte 1 ==
7650 00:59:31.031114 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7651 00:59:31.034236 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7652 00:59:31.034649 ==
7653 00:59:31.037558 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 00:59:31.041420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 00:59:31.044327 ==
7656 00:59:31.057229
7657 00:59:31.061081 TX Vref early break, caculate TX vref
7658 00:59:31.064047 TX Vref=16, minBit 4, minWin=22, winSum=368
7659 00:59:31.067516 TX Vref=18, minBit 1, minWin=23, winSum=381
7660 00:59:31.070316 TX Vref=20, minBit 1, minWin=23, winSum=387
7661 00:59:31.073678 TX Vref=22, minBit 4, minWin=24, winSum=395
7662 00:59:31.077501 TX Vref=24, minBit 8, minWin=24, winSum=408
7663 00:59:31.083810 TX Vref=26, minBit 1, minWin=25, winSum=416
7664 00:59:31.087530 TX Vref=28, minBit 0, minWin=25, winSum=418
7665 00:59:31.090678 TX Vref=30, minBit 2, minWin=25, winSum=416
7666 00:59:31.093310 TX Vref=32, minBit 4, minWin=24, winSum=412
7667 00:59:31.096922 TX Vref=34, minBit 0, minWin=24, winSum=397
7668 00:59:31.103717 TX Vref=36, minBit 1, minWin=23, winSum=384
7669 00:59:31.107137 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7670 00:59:31.107776
7671 00:59:31.110367 Final TX Range 0 Vref 28
7672 00:59:31.110807
7673 00:59:31.111240 ==
7674 00:59:31.113287 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 00:59:31.116676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 00:59:31.120014 ==
7677 00:59:31.120438
7678 00:59:31.120873
7679 00:59:31.121281 TX Vref Scan disable
7680 00:59:31.126899 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7681 00:59:31.127497 == TX Byte 0 ==
7682 00:59:31.130613 u2DelayCellOfst[0]=14 cells (4 PI)
7683 00:59:31.133268 u2DelayCellOfst[1]=17 cells (5 PI)
7684 00:59:31.136533 u2DelayCellOfst[2]=10 cells (3 PI)
7685 00:59:31.139828 u2DelayCellOfst[3]=10 cells (3 PI)
7686 00:59:31.142720 u2DelayCellOfst[4]=10 cells (3 PI)
7687 00:59:31.146115 u2DelayCellOfst[5]=0 cells (0 PI)
7688 00:59:31.149801 u2DelayCellOfst[6]=17 cells (5 PI)
7689 00:59:31.152891 u2DelayCellOfst[7]=17 cells (5 PI)
7690 00:59:31.156647 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7691 00:59:31.159256 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7692 00:59:31.162791 == TX Byte 1 ==
7693 00:59:31.166212 u2DelayCellOfst[8]=0 cells (0 PI)
7694 00:59:31.169420 u2DelayCellOfst[9]=0 cells (0 PI)
7695 00:59:31.173067 u2DelayCellOfst[10]=3 cells (1 PI)
7696 00:59:31.176623 u2DelayCellOfst[11]=0 cells (0 PI)
7697 00:59:31.179451 u2DelayCellOfst[12]=10 cells (3 PI)
7698 00:59:31.182538 u2DelayCellOfst[13]=7 cells (2 PI)
7699 00:59:31.186129 u2DelayCellOfst[14]=14 cells (4 PI)
7700 00:59:31.186646 u2DelayCellOfst[15]=7 cells (2 PI)
7701 00:59:31.193184 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7702 00:59:31.195941 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7703 00:59:31.199268 DramC Write-DBI on
7704 00:59:31.199718 ==
7705 00:59:31.202527 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 00:59:31.205417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 00:59:31.205852 ==
7708 00:59:31.206377
7709 00:59:31.206786
7710 00:59:31.208718 TX Vref Scan disable
7711 00:59:31.212298 == TX Byte 0 ==
7712 00:59:31.215351 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7713 00:59:31.215830 == TX Byte 1 ==
7714 00:59:31.222377 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7715 00:59:31.222909 DramC Write-DBI off
7716 00:59:31.223353
7717 00:59:31.223798 [DATLAT]
7718 00:59:31.225604 Freq=1600, CH0 RK0
7719 00:59:31.226174
7720 00:59:31.228730 DATLAT Default: 0xf
7721 00:59:31.229307 0, 0xFFFF, sum = 0
7722 00:59:31.231932 1, 0xFFFF, sum = 0
7723 00:59:31.232367 2, 0xFFFF, sum = 0
7724 00:59:31.235535 3, 0xFFFF, sum = 0
7725 00:59:31.236085 4, 0xFFFF, sum = 0
7726 00:59:31.238568 5, 0xFFFF, sum = 0
7727 00:59:31.238999 6, 0xFFFF, sum = 0
7728 00:59:31.241901 7, 0xFFFF, sum = 0
7729 00:59:31.242334 8, 0xFFFF, sum = 0
7730 00:59:31.245105 9, 0xFFFF, sum = 0
7731 00:59:31.245633 10, 0xFFFF, sum = 0
7732 00:59:31.247959 11, 0xFFFF, sum = 0
7733 00:59:31.248378 12, 0xFFFF, sum = 0
7734 00:59:31.251506 13, 0xFFFF, sum = 0
7735 00:59:31.251931 14, 0x0, sum = 1
7736 00:59:31.254877 15, 0x0, sum = 2
7737 00:59:31.255293 16, 0x0, sum = 3
7738 00:59:31.257967 17, 0x0, sum = 4
7739 00:59:31.258386 best_step = 15
7740 00:59:31.258827
7741 00:59:31.259184 ==
7742 00:59:31.261183 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 00:59:31.268157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 00:59:31.268575 ==
7745 00:59:31.268900 RX Vref Scan: 1
7746 00:59:31.269207
7747 00:59:31.271218 Set Vref Range= 24 -> 127
7748 00:59:31.271665
7749 00:59:31.274544 RX Vref 24 -> 127, step: 1
7750 00:59:31.274957
7751 00:59:31.278507 RX Delay 19 -> 252, step: 4
7752 00:59:31.279038
7753 00:59:31.281034 Set Vref, RX VrefLevel [Byte0]: 24
7754 00:59:31.284360 [Byte1]: 24
7755 00:59:31.284778
7756 00:59:31.287763 Set Vref, RX VrefLevel [Byte0]: 25
7757 00:59:31.291192 [Byte1]: 25
7758 00:59:31.291756
7759 00:59:31.295065 Set Vref, RX VrefLevel [Byte0]: 26
7760 00:59:31.297572 [Byte1]: 26
7761 00:59:31.300756
7762 00:59:31.301168 Set Vref, RX VrefLevel [Byte0]: 27
7763 00:59:31.304002 [Byte1]: 27
7764 00:59:31.308839
7765 00:59:31.309382 Set Vref, RX VrefLevel [Byte0]: 28
7766 00:59:31.312143 [Byte1]: 28
7767 00:59:31.316084
7768 00:59:31.316499 Set Vref, RX VrefLevel [Byte0]: 29
7769 00:59:31.319637 [Byte1]: 29
7770 00:59:31.323725
7771 00:59:31.324389 Set Vref, RX VrefLevel [Byte0]: 30
7772 00:59:31.327055 [Byte1]: 30
7773 00:59:31.331171
7774 00:59:31.331715 Set Vref, RX VrefLevel [Byte0]: 31
7775 00:59:31.334651 [Byte1]: 31
7776 00:59:31.338743
7777 00:59:31.339188 Set Vref, RX VrefLevel [Byte0]: 32
7778 00:59:31.342148 [Byte1]: 32
7779 00:59:31.346889
7780 00:59:31.347456 Set Vref, RX VrefLevel [Byte0]: 33
7781 00:59:31.349706 [Byte1]: 33
7782 00:59:31.353963
7783 00:59:31.354449 Set Vref, RX VrefLevel [Byte0]: 34
7784 00:59:31.357371 [Byte1]: 34
7785 00:59:31.361293
7786 00:59:31.361714 Set Vref, RX VrefLevel [Byte0]: 35
7787 00:59:31.365217 [Byte1]: 35
7788 00:59:31.368934
7789 00:59:31.369350 Set Vref, RX VrefLevel [Byte0]: 36
7790 00:59:31.372244 [Byte1]: 36
7791 00:59:31.376664
7792 00:59:31.377152 Set Vref, RX VrefLevel [Byte0]: 37
7793 00:59:31.379717 [Byte1]: 37
7794 00:59:31.383962
7795 00:59:31.384381 Set Vref, RX VrefLevel [Byte0]: 38
7796 00:59:31.387303 [Byte1]: 38
7797 00:59:31.392169
7798 00:59:31.392658 Set Vref, RX VrefLevel [Byte0]: 39
7799 00:59:31.395456 [Byte1]: 39
7800 00:59:31.399593
7801 00:59:31.400096 Set Vref, RX VrefLevel [Byte0]: 40
7802 00:59:31.403414 [Byte1]: 40
7803 00:59:31.406937
7804 00:59:31.407500 Set Vref, RX VrefLevel [Byte0]: 41
7805 00:59:31.410183 [Byte1]: 41
7806 00:59:31.414529
7807 00:59:31.415047 Set Vref, RX VrefLevel [Byte0]: 42
7808 00:59:31.418458 [Byte1]: 42
7809 00:59:31.422053
7810 00:59:31.422474 Set Vref, RX VrefLevel [Byte0]: 43
7811 00:59:31.425350 [Byte1]: 43
7812 00:59:31.429743
7813 00:59:31.430279 Set Vref, RX VrefLevel [Byte0]: 44
7814 00:59:31.432950 [Byte1]: 44
7815 00:59:31.437211
7816 00:59:31.437630 Set Vref, RX VrefLevel [Byte0]: 45
7817 00:59:31.440298 [Byte1]: 45
7818 00:59:31.444921
7819 00:59:31.445339 Set Vref, RX VrefLevel [Byte0]: 46
7820 00:59:31.448457 [Byte1]: 46
7821 00:59:31.453095
7822 00:59:31.453509 Set Vref, RX VrefLevel [Byte0]: 47
7823 00:59:31.456006 [Byte1]: 47
7824 00:59:31.459581
7825 00:59:31.460002 Set Vref, RX VrefLevel [Byte0]: 48
7826 00:59:31.463219 [Byte1]: 48
7827 00:59:31.467750
7828 00:59:31.468169 Set Vref, RX VrefLevel [Byte0]: 49
7829 00:59:31.470856 [Byte1]: 49
7830 00:59:31.474882
7831 00:59:31.475299 Set Vref, RX VrefLevel [Byte0]: 50
7832 00:59:31.478395 [Byte1]: 50
7833 00:59:31.482547
7834 00:59:31.482983 Set Vref, RX VrefLevel [Byte0]: 51
7835 00:59:31.486031 [Byte1]: 51
7836 00:59:31.490381
7837 00:59:31.490810 Set Vref, RX VrefLevel [Byte0]: 52
7838 00:59:31.493445 [Byte1]: 52
7839 00:59:31.497758
7840 00:59:31.498460 Set Vref, RX VrefLevel [Byte0]: 53
7841 00:59:31.501045 [Byte1]: 53
7842 00:59:31.505658
7843 00:59:31.506075 Set Vref, RX VrefLevel [Byte0]: 54
7844 00:59:31.508496 [Byte1]: 54
7845 00:59:31.512609
7846 00:59:31.513148 Set Vref, RX VrefLevel [Byte0]: 55
7847 00:59:31.516750 [Byte1]: 55
7848 00:59:31.520964
7849 00:59:31.521376 Set Vref, RX VrefLevel [Byte0]: 56
7850 00:59:31.523511 [Byte1]: 56
7851 00:59:31.528086
7852 00:59:31.528496 Set Vref, RX VrefLevel [Byte0]: 57
7853 00:59:31.531102 [Byte1]: 57
7854 00:59:31.535517
7855 00:59:31.535930 Set Vref, RX VrefLevel [Byte0]: 58
7856 00:59:31.540018 [Byte1]: 58
7857 00:59:31.543489
7858 00:59:31.543905 Set Vref, RX VrefLevel [Byte0]: 59
7859 00:59:31.546550 [Byte1]: 59
7860 00:59:31.550770
7861 00:59:31.551267 Set Vref, RX VrefLevel [Byte0]: 60
7862 00:59:31.554476 [Byte1]: 60
7863 00:59:31.558460
7864 00:59:31.559140 Set Vref, RX VrefLevel [Byte0]: 61
7865 00:59:31.561707 [Byte1]: 61
7866 00:59:31.565873
7867 00:59:31.566317 Set Vref, RX VrefLevel [Byte0]: 62
7868 00:59:31.569521 [Byte1]: 62
7869 00:59:31.573841
7870 00:59:31.574365 Set Vref, RX VrefLevel [Byte0]: 63
7871 00:59:31.576835 [Byte1]: 63
7872 00:59:31.581085
7873 00:59:31.581516 Set Vref, RX VrefLevel [Byte0]: 64
7874 00:59:31.584609 [Byte1]: 64
7875 00:59:31.588480
7876 00:59:31.589049 Set Vref, RX VrefLevel [Byte0]: 65
7877 00:59:31.591980 [Byte1]: 65
7878 00:59:31.596537
7879 00:59:31.596955 Set Vref, RX VrefLevel [Byte0]: 66
7880 00:59:31.599278 [Byte1]: 66
7881 00:59:31.603711
7882 00:59:31.604211 Set Vref, RX VrefLevel [Byte0]: 67
7883 00:59:31.607094 [Byte1]: 67
7884 00:59:31.611168
7885 00:59:31.611650 Set Vref, RX VrefLevel [Byte0]: 68
7886 00:59:31.614740 [Byte1]: 68
7887 00:59:31.618861
7888 00:59:31.619513 Set Vref, RX VrefLevel [Byte0]: 69
7889 00:59:31.622131 [Byte1]: 69
7890 00:59:31.626821
7891 00:59:31.627332 Set Vref, RX VrefLevel [Byte0]: 70
7892 00:59:31.629622 [Byte1]: 70
7893 00:59:31.634309
7894 00:59:31.634745 Set Vref, RX VrefLevel [Byte0]: 71
7895 00:59:31.637828 [Byte1]: 71
7896 00:59:31.641478
7897 00:59:31.642083 Set Vref, RX VrefLevel [Byte0]: 72
7898 00:59:31.644783 [Byte1]: 72
7899 00:59:31.648993
7900 00:59:31.649528 Set Vref, RX VrefLevel [Byte0]: 73
7901 00:59:31.652392 [Byte1]: 73
7902 00:59:31.656760
7903 00:59:31.657270 Final RX Vref Byte 0 = 55 to rank0
7904 00:59:31.660674 Final RX Vref Byte 1 = 57 to rank0
7905 00:59:31.663808 Final RX Vref Byte 0 = 55 to rank1
7906 00:59:31.666752 Final RX Vref Byte 1 = 57 to rank1==
7907 00:59:31.669660 Dram Type= 6, Freq= 0, CH_0, rank 0
7908 00:59:31.676955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7909 00:59:31.677466 ==
7910 00:59:31.677800 DQS Delay:
7911 00:59:31.679949 DQS0 = 0, DQS1 = 0
7912 00:59:31.680369 DQM Delay:
7913 00:59:31.680687 DQM0 = 129, DQM1 = 124
7914 00:59:31.683510 DQ Delay:
7915 00:59:31.686297 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7916 00:59:31.690123 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
7917 00:59:31.692887 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7918 00:59:31.696342 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7919 00:59:31.696843
7920 00:59:31.697167
7921 00:59:31.697467
7922 00:59:31.699732 [DramC_TX_OE_Calibration] TA2
7923 00:59:31.703415 Original DQ_B0 (3 6) =30, OEN = 27
7924 00:59:31.706213 Original DQ_B1 (3 6) =30, OEN = 27
7925 00:59:31.709542 24, 0x0, End_B0=24 End_B1=24
7926 00:59:31.710096 25, 0x0, End_B0=25 End_B1=25
7927 00:59:31.713016 26, 0x0, End_B0=26 End_B1=26
7928 00:59:31.716080 27, 0x0, End_B0=27 End_B1=27
7929 00:59:31.719336 28, 0x0, End_B0=28 End_B1=28
7930 00:59:31.722540 29, 0x0, End_B0=29 End_B1=29
7931 00:59:31.722961 30, 0x0, End_B0=30 End_B1=30
7932 00:59:31.726090 31, 0x4141, End_B0=30 End_B1=30
7933 00:59:31.729553 Byte0 end_step=30 best_step=27
7934 00:59:31.732326 Byte1 end_step=30 best_step=27
7935 00:59:31.735820 Byte0 TX OE(2T, 0.5T) = (3, 3)
7936 00:59:31.739305 Byte1 TX OE(2T, 0.5T) = (3, 3)
7937 00:59:31.739793
7938 00:59:31.740338
7939 00:59:31.745859 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7940 00:59:31.748797 CH0 RK0: MR19=303, MR18=1512
7941 00:59:31.756384 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
7942 00:59:31.756839
7943 00:59:31.759257 ----->DramcWriteLeveling(PI) begin...
7944 00:59:31.759824 ==
7945 00:59:31.762415 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 00:59:31.765389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 00:59:31.765821 ==
7948 00:59:31.768857 Write leveling (Byte 0): 33 => 33
7949 00:59:31.771871 Write leveling (Byte 1): 27 => 27
7950 00:59:31.775275 DramcWriteLeveling(PI) end<-----
7951 00:59:31.775734
7952 00:59:31.776061 ==
7953 00:59:31.778792 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 00:59:31.784992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 00:59:31.785494 ==
7956 00:59:31.785827 [Gating] SW mode calibration
7957 00:59:31.795205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7958 00:59:31.798570 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7959 00:59:31.805003 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 00:59:31.808227 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7961 00:59:31.811844 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7962 00:59:31.818198 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7963 00:59:31.821784 1 4 16 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7964 00:59:31.824716 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7965 00:59:31.831491 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7966 00:59:31.835027 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7967 00:59:31.837915 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7968 00:59:31.844407 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7969 00:59:31.847740 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
7970 00:59:31.851320 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7971 00:59:31.857300 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7972 00:59:31.860753 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7973 00:59:31.863870 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 00:59:31.870479 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7975 00:59:31.874118 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7976 00:59:31.876984 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7977 00:59:31.883645 1 6 8 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7978 00:59:31.886931 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7979 00:59:31.890203 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7980 00:59:31.897294 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7981 00:59:31.901481 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 00:59:31.903794 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 00:59:31.910020 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 00:59:31.913250 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7985 00:59:31.916950 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7986 00:59:31.923535 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7987 00:59:31.926987 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7988 00:59:31.930624 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7989 00:59:31.936735 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 00:59:31.939810 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 00:59:31.943394 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 00:59:31.949660 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 00:59:31.952973 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 00:59:31.956058 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 00:59:31.962761 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 00:59:31.965952 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 00:59:31.969337 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 00:59:31.976074 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 00:59:31.979291 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 00:59:31.982475 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 00:59:31.989365 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8002 00:59:31.992547 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8003 00:59:31.995899 Total UI for P1: 0, mck2ui 16
8004 00:59:31.999235 best dqsien dly found for B0: ( 1, 9, 8)
8005 00:59:32.002160 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8006 00:59:32.008926 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8007 00:59:32.012121 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 00:59:32.015273 Total UI for P1: 0, mck2ui 16
8009 00:59:32.018678 best dqsien dly found for B1: ( 1, 9, 16)
8010 00:59:32.021939 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8011 00:59:32.025371 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8012 00:59:32.025877
8013 00:59:32.028305 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8014 00:59:32.032099 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8015 00:59:32.035346 [Gating] SW calibration Done
8016 00:59:32.035833 ==
8017 00:59:32.038412 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 00:59:32.045103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 00:59:32.045536 ==
8020 00:59:32.045979 RX Vref Scan: 0
8021 00:59:32.046391
8022 00:59:32.048112 RX Vref 0 -> 0, step: 1
8023 00:59:32.048542
8024 00:59:32.051513 RX Delay 0 -> 252, step: 8
8025 00:59:32.054870 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8026 00:59:32.058827 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8027 00:59:32.061498 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8028 00:59:32.064684 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8029 00:59:32.071325 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8030 00:59:32.074671 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8031 00:59:32.077911 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8032 00:59:32.081636 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8033 00:59:32.085121 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8034 00:59:32.091206 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8035 00:59:32.094182 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8036 00:59:32.097779 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8037 00:59:32.100875 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8038 00:59:32.107554 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8039 00:59:32.110598 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8040 00:59:32.113830 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8041 00:59:32.114248 ==
8042 00:59:32.117675 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 00:59:32.120531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 00:59:32.120948 ==
8045 00:59:32.124031 DQS Delay:
8046 00:59:32.124445 DQS0 = 0, DQS1 = 0
8047 00:59:32.127126 DQM Delay:
8048 00:59:32.127648 DQM0 = 132, DQM1 = 128
8049 00:59:32.130866 DQ Delay:
8050 00:59:32.133711 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8051 00:59:32.136889 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8052 00:59:32.140645 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8053 00:59:32.143790 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8054 00:59:32.144209
8055 00:59:32.144534
8056 00:59:32.144837 ==
8057 00:59:32.147228 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 00:59:32.150028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 00:59:32.150440 ==
8060 00:59:32.150764
8061 00:59:32.154245
8062 00:59:32.154652 TX Vref Scan disable
8063 00:59:32.157044 == TX Byte 0 ==
8064 00:59:32.160135 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8065 00:59:32.163844 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8066 00:59:32.166880 == TX Byte 1 ==
8067 00:59:32.170099 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8068 00:59:32.174016 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8069 00:59:32.174525 ==
8070 00:59:32.176991 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 00:59:32.183183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 00:59:32.183771 ==
8073 00:59:32.195453
8074 00:59:32.199147 TX Vref early break, caculate TX vref
8075 00:59:32.202197 TX Vref=16, minBit 1, minWin=23, winSum=381
8076 00:59:32.205499 TX Vref=18, minBit 8, minWin=23, winSum=391
8077 00:59:32.208605 TX Vref=20, minBit 0, minWin=24, winSum=402
8078 00:59:32.212162 TX Vref=22, minBit 0, minWin=25, winSum=407
8079 00:59:32.215398 TX Vref=24, minBit 3, minWin=25, winSum=414
8080 00:59:32.222302 TX Vref=26, minBit 3, minWin=25, winSum=423
8081 00:59:32.225193 TX Vref=28, minBit 0, minWin=26, winSum=426
8082 00:59:32.228589 TX Vref=30, minBit 1, minWin=25, winSum=418
8083 00:59:32.232131 TX Vref=32, minBit 0, minWin=25, winSum=411
8084 00:59:32.235528 TX Vref=34, minBit 1, minWin=24, winSum=403
8085 00:59:32.241805 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8086 00:59:32.242449
8087 00:59:32.244750 Final TX Range 0 Vref 28
8088 00:59:32.245211
8089 00:59:32.245566 ==
8090 00:59:32.248605 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 00:59:32.251990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 00:59:32.252538 ==
8093 00:59:32.252897
8094 00:59:32.253201
8095 00:59:32.255016 TX Vref Scan disable
8096 00:59:32.261244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8097 00:59:32.261908 == TX Byte 0 ==
8098 00:59:32.264494 u2DelayCellOfst[0]=10 cells (3 PI)
8099 00:59:32.267693 u2DelayCellOfst[1]=14 cells (4 PI)
8100 00:59:32.271479 u2DelayCellOfst[2]=7 cells (2 PI)
8101 00:59:32.274424 u2DelayCellOfst[3]=10 cells (3 PI)
8102 00:59:32.278078 u2DelayCellOfst[4]=7 cells (2 PI)
8103 00:59:32.281600 u2DelayCellOfst[5]=0 cells (0 PI)
8104 00:59:32.284120 u2DelayCellOfst[6]=14 cells (4 PI)
8105 00:59:32.287603 u2DelayCellOfst[7]=14 cells (4 PI)
8106 00:59:32.291145 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8107 00:59:32.294130 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8108 00:59:32.297823 == TX Byte 1 ==
8109 00:59:32.300902 u2DelayCellOfst[8]=0 cells (0 PI)
8110 00:59:32.304683 u2DelayCellOfst[9]=0 cells (0 PI)
8111 00:59:32.307748 u2DelayCellOfst[10]=7 cells (2 PI)
8112 00:59:32.308257 u2DelayCellOfst[11]=3 cells (1 PI)
8113 00:59:32.310917 u2DelayCellOfst[12]=10 cells (3 PI)
8114 00:59:32.313992 u2DelayCellOfst[13]=10 cells (3 PI)
8115 00:59:32.317375 u2DelayCellOfst[14]=17 cells (5 PI)
8116 00:59:32.321331 u2DelayCellOfst[15]=10 cells (3 PI)
8117 00:59:32.327559 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8118 00:59:32.330657 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8119 00:59:32.331076 DramC Write-DBI on
8120 00:59:32.333573 ==
8121 00:59:32.337177 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 00:59:32.340180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 00:59:32.340597 ==
8124 00:59:32.340925
8125 00:59:32.341229
8126 00:59:32.344401 TX Vref Scan disable
8127 00:59:32.344815 == TX Byte 0 ==
8128 00:59:32.351142 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8129 00:59:32.351712 == TX Byte 1 ==
8130 00:59:32.353372 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8131 00:59:32.357056 DramC Write-DBI off
8132 00:59:32.357468
8133 00:59:32.357793 [DATLAT]
8134 00:59:32.360172 Freq=1600, CH0 RK1
8135 00:59:32.360590
8136 00:59:32.360915 DATLAT Default: 0xf
8137 00:59:32.363915 0, 0xFFFF, sum = 0
8138 00:59:32.364337 1, 0xFFFF, sum = 0
8139 00:59:32.367157 2, 0xFFFF, sum = 0
8140 00:59:32.367661 3, 0xFFFF, sum = 0
8141 00:59:32.370120 4, 0xFFFF, sum = 0
8142 00:59:32.373453 5, 0xFFFF, sum = 0
8143 00:59:32.373868 6, 0xFFFF, sum = 0
8144 00:59:32.376652 7, 0xFFFF, sum = 0
8145 00:59:32.377171 8, 0xFFFF, sum = 0
8146 00:59:32.379827 9, 0xFFFF, sum = 0
8147 00:59:32.380245 10, 0xFFFF, sum = 0
8148 00:59:32.383187 11, 0xFFFF, sum = 0
8149 00:59:32.383752 12, 0xFFFF, sum = 0
8150 00:59:32.386347 13, 0xFFFF, sum = 0
8151 00:59:32.386761 14, 0x0, sum = 1
8152 00:59:32.390081 15, 0x0, sum = 2
8153 00:59:32.390565 16, 0x0, sum = 3
8154 00:59:32.393077 17, 0x0, sum = 4
8155 00:59:32.393508 best_step = 15
8156 00:59:32.393831
8157 00:59:32.394131 ==
8158 00:59:32.396320 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 00:59:32.402760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 00:59:32.403240 ==
8161 00:59:32.403603 RX Vref Scan: 0
8162 00:59:32.403907
8163 00:59:32.405921 RX Vref 0 -> 0, step: 1
8164 00:59:32.406335
8165 00:59:32.409596 RX Delay 11 -> 252, step: 4
8166 00:59:32.412711 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8167 00:59:32.416450 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8168 00:59:32.419703 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8169 00:59:32.426322 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8170 00:59:32.429457 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8171 00:59:32.432429 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8172 00:59:32.435622 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8173 00:59:32.439320 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8174 00:59:32.446541 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8175 00:59:32.449085 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8176 00:59:32.452430 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8177 00:59:32.455814 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8178 00:59:32.459260 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8179 00:59:32.465677 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8180 00:59:32.468686 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8181 00:59:32.472218 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8182 00:59:32.472634 ==
8183 00:59:32.476035 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 00:59:32.481899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 00:59:32.482411 ==
8186 00:59:32.482745 DQS Delay:
8187 00:59:32.483050 DQS0 = 0, DQS1 = 0
8188 00:59:32.485385 DQM Delay:
8189 00:59:32.485793 DQM0 = 129, DQM1 = 124
8190 00:59:32.488708 DQ Delay:
8191 00:59:32.492117 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8192 00:59:32.495182 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8193 00:59:32.498505 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8194 00:59:32.501899 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8195 00:59:32.502485
8196 00:59:32.502819
8197 00:59:32.503119
8198 00:59:32.505096 [DramC_TX_OE_Calibration] TA2
8199 00:59:32.508608 Original DQ_B0 (3 6) =30, OEN = 27
8200 00:59:32.511480 Original DQ_B1 (3 6) =30, OEN = 27
8201 00:59:32.515056 24, 0x0, End_B0=24 End_B1=24
8202 00:59:32.515642 25, 0x0, End_B0=25 End_B1=25
8203 00:59:32.518246 26, 0x0, End_B0=26 End_B1=26
8204 00:59:32.521660 27, 0x0, End_B0=27 End_B1=27
8205 00:59:32.525193 28, 0x0, End_B0=28 End_B1=28
8206 00:59:32.528310 29, 0x0, End_B0=29 End_B1=29
8207 00:59:32.528904 30, 0x0, End_B0=30 End_B1=30
8208 00:59:32.531138 31, 0x4141, End_B0=30 End_B1=30
8209 00:59:32.534539 Byte0 end_step=30 best_step=27
8210 00:59:32.538116 Byte1 end_step=30 best_step=27
8211 00:59:32.541080 Byte0 TX OE(2T, 0.5T) = (3, 3)
8212 00:59:32.544563 Byte1 TX OE(2T, 0.5T) = (3, 3)
8213 00:59:32.544980
8214 00:59:32.545310
8215 00:59:32.551212 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8216 00:59:32.554761 CH0 RK1: MR19=303, MR18=1311
8217 00:59:32.560903 CH0_RK1: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
8218 00:59:32.564197 [RxdqsGatingPostProcess] freq 1600
8219 00:59:32.570908 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8220 00:59:32.571325 best DQS0 dly(2T, 0.5T) = (1, 1)
8221 00:59:32.575106 best DQS1 dly(2T, 0.5T) = (1, 1)
8222 00:59:32.577504 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8223 00:59:32.581259 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8224 00:59:32.584479 best DQS0 dly(2T, 0.5T) = (1, 1)
8225 00:59:32.587325 best DQS1 dly(2T, 0.5T) = (1, 1)
8226 00:59:32.590689 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8227 00:59:32.593920 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8228 00:59:32.597439 Pre-setting of DQS Precalculation
8229 00:59:32.601069 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8230 00:59:32.601568 ==
8231 00:59:32.603628 Dram Type= 6, Freq= 0, CH_1, rank 0
8232 00:59:32.610965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 00:59:32.611408 ==
8234 00:59:32.613726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8235 00:59:32.620119 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8236 00:59:32.623825 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8237 00:59:32.629746 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8238 00:59:32.638213 [CA 0] Center 42 (13~72) winsize 60
8239 00:59:32.641772 [CA 1] Center 42 (12~72) winsize 61
8240 00:59:32.644947 [CA 2] Center 39 (9~69) winsize 61
8241 00:59:32.647957 [CA 3] Center 37 (8~67) winsize 60
8242 00:59:32.651229 [CA 4] Center 38 (8~69) winsize 62
8243 00:59:32.654776 [CA 5] Center 37 (7~67) winsize 61
8244 00:59:32.655191
8245 00:59:32.658090 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8246 00:59:32.658613
8247 00:59:32.661621 [CATrainingPosCal] consider 1 rank data
8248 00:59:32.664804 u2DelayCellTimex100 = 275/100 ps
8249 00:59:32.671448 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8250 00:59:32.674137 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8251 00:59:32.678041 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8252 00:59:32.680734 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8253 00:59:32.684074 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8254 00:59:32.687623 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8255 00:59:32.688040
8256 00:59:32.691173 CA PerBit enable=1, Macro0, CA PI delay=37
8257 00:59:32.691723
8258 00:59:32.694409 [CBTSetCACLKResult] CA Dly = 37
8259 00:59:32.697276 CS Dly: 8 (0~39)
8260 00:59:32.701398 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8261 00:59:32.703862 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8262 00:59:32.704278 ==
8263 00:59:32.707090 Dram Type= 6, Freq= 0, CH_1, rank 1
8264 00:59:32.714462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 00:59:32.714879 ==
8266 00:59:32.716980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 00:59:32.723507 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 00:59:32.727221 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 00:59:32.733850 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 00:59:32.741421 [CA 0] Center 41 (11~71) winsize 61
8271 00:59:32.744475 [CA 1] Center 41 (12~71) winsize 60
8272 00:59:32.747811 [CA 2] Center 37 (8~67) winsize 60
8273 00:59:32.751306 [CA 3] Center 36 (7~66) winsize 60
8274 00:59:32.754669 [CA 4] Center 37 (7~67) winsize 61
8275 00:59:32.757807 [CA 5] Center 36 (7~66) winsize 60
8276 00:59:32.758229
8277 00:59:32.761304 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8278 00:59:32.761814
8279 00:59:32.764573 [CATrainingPosCal] consider 2 rank data
8280 00:59:32.767560 u2DelayCellTimex100 = 275/100 ps
8281 00:59:32.774645 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8282 00:59:32.777686 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8283 00:59:32.781321 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8284 00:59:32.784019 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8285 00:59:32.787851 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8286 00:59:32.790806 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8287 00:59:32.791230
8288 00:59:32.794373 CA PerBit enable=1, Macro0, CA PI delay=36
8289 00:59:32.794785
8290 00:59:32.797974 [CBTSetCACLKResult] CA Dly = 36
8291 00:59:32.800880 CS Dly: 9 (0~42)
8292 00:59:32.804081 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 00:59:32.807498 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 00:59:32.807917
8295 00:59:32.811173 ----->DramcWriteLeveling(PI) begin...
8296 00:59:32.811736 ==
8297 00:59:32.814190 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 00:59:32.820572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 00:59:32.820987 ==
8300 00:59:32.823620 Write leveling (Byte 0): 25 => 25
8301 00:59:32.824034 Write leveling (Byte 1): 27 => 27
8302 00:59:32.826913 DramcWriteLeveling(PI) end<-----
8303 00:59:32.827319
8304 00:59:32.830482 ==
8305 00:59:32.830890 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 00:59:32.836849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 00:59:32.837265 ==
8308 00:59:32.840633 [Gating] SW mode calibration
8309 00:59:32.847064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8310 00:59:32.850692 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8311 00:59:32.856616 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 00:59:32.860061 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 00:59:32.863868 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8314 00:59:32.869812 1 4 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
8315 00:59:32.873541 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 00:59:32.876585 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 00:59:32.882902 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 00:59:32.886777 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 00:59:32.889717 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 00:59:32.896283 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 00:59:32.900283 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8322 00:59:32.903310 1 5 12 | B1->B0 | 3333 2727 | 1 0 | (0 1) (1 0)
8323 00:59:32.909984 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8324 00:59:32.912447 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 00:59:32.915803 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 00:59:32.922471 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 00:59:32.925627 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 00:59:32.929177 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 00:59:32.936346 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 00:59:32.939215 1 6 12 | B1->B0 | 3333 4545 | 0 0 | (1 1) (0 0)
8331 00:59:32.945484 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8332 00:59:32.948612 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 00:59:32.952163 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 00:59:32.955233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 00:59:32.962030 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 00:59:32.965417 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 00:59:32.968793 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8338 00:59:32.975484 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 00:59:32.978151 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8340 00:59:32.982135 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 00:59:32.988145 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 00:59:32.991699 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 00:59:32.995232 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 00:59:33.001586 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 00:59:33.005372 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 00:59:33.008245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 00:59:33.014667 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 00:59:33.018281 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 00:59:33.021719 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 00:59:33.028129 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 00:59:33.030911 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 00:59:33.037432 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 00:59:33.040825 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8354 00:59:33.044251 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 00:59:33.047473 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 00:59:33.050644 Total UI for P1: 0, mck2ui 16
8357 00:59:33.054142 best dqsien dly found for B0: ( 1, 9, 10)
8358 00:59:33.057480 Total UI for P1: 0, mck2ui 16
8359 00:59:33.061000 best dqsien dly found for B1: ( 1, 9, 12)
8360 00:59:33.064000 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8361 00:59:33.070361 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8362 00:59:33.070776
8363 00:59:33.074496 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8364 00:59:33.077458 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8365 00:59:33.080508 [Gating] SW calibration Done
8366 00:59:33.080926 ==
8367 00:59:33.083667 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 00:59:33.087250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 00:59:33.087699 ==
8370 00:59:33.090352 RX Vref Scan: 0
8371 00:59:33.090765
8372 00:59:33.091089 RX Vref 0 -> 0, step: 1
8373 00:59:33.091424
8374 00:59:33.093665 RX Delay 0 -> 252, step: 8
8375 00:59:33.096872 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8376 00:59:33.103830 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8377 00:59:33.107076 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8378 00:59:33.110062 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8379 00:59:33.113984 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8380 00:59:33.117224 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8381 00:59:33.123500 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8382 00:59:33.126397 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8383 00:59:33.130023 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8384 00:59:33.134088 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8385 00:59:33.136315 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8386 00:59:33.143437 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8387 00:59:33.146683 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8388 00:59:33.149947 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8389 00:59:33.153728 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8390 00:59:33.159792 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8391 00:59:33.160310 ==
8392 00:59:33.162755 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 00:59:33.166015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 00:59:33.166431 ==
8395 00:59:33.166757 DQS Delay:
8396 00:59:33.169198 DQS0 = 0, DQS1 = 0
8397 00:59:33.169666 DQM Delay:
8398 00:59:33.173071 DQM0 = 134, DQM1 = 130
8399 00:59:33.173596 DQ Delay:
8400 00:59:33.175845 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8401 00:59:33.179271 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8402 00:59:33.182422 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8403 00:59:33.186218 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8404 00:59:33.186632
8405 00:59:33.189662
8406 00:59:33.190169 ==
8407 00:59:33.192717 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 00:59:33.195852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 00:59:33.196270 ==
8410 00:59:33.196597
8411 00:59:33.196899
8412 00:59:33.199718 TX Vref Scan disable
8413 00:59:33.200229 == TX Byte 0 ==
8414 00:59:33.205795 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8415 00:59:33.209123 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8416 00:59:33.209639 == TX Byte 1 ==
8417 00:59:33.215323 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8418 00:59:33.218480 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8419 00:59:33.218898 ==
8420 00:59:33.222472 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 00:59:33.224996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 00:59:33.225417 ==
8423 00:59:33.239250
8424 00:59:33.242080 TX Vref early break, caculate TX vref
8425 00:59:33.245408 TX Vref=16, minBit 8, minWin=21, winSum=367
8426 00:59:33.248742 TX Vref=18, minBit 1, minWin=23, winSum=378
8427 00:59:33.251991 TX Vref=20, minBit 3, minWin=23, winSum=390
8428 00:59:33.255245 TX Vref=22, minBit 0, minWin=24, winSum=395
8429 00:59:33.258812 TX Vref=24, minBit 8, minWin=23, winSum=403
8430 00:59:33.265183 TX Vref=26, minBit 9, minWin=24, winSum=410
8431 00:59:33.268311 TX Vref=28, minBit 0, minWin=25, winSum=418
8432 00:59:33.271719 TX Vref=30, minBit 0, minWin=25, winSum=416
8433 00:59:33.274965 TX Vref=32, minBit 9, minWin=24, winSum=410
8434 00:59:33.278078 TX Vref=34, minBit 0, minWin=23, winSum=394
8435 00:59:33.284993 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8436 00:59:33.285509
8437 00:59:33.288021 Final TX Range 0 Vref 28
8438 00:59:33.288437
8439 00:59:33.288758 ==
8440 00:59:33.291433 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 00:59:33.295095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 00:59:33.295633 ==
8443 00:59:33.295961
8444 00:59:33.296266
8445 00:59:33.298031 TX Vref Scan disable
8446 00:59:33.304607 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8447 00:59:33.305023 == TX Byte 0 ==
8448 00:59:33.307594 u2DelayCellOfst[0]=14 cells (4 PI)
8449 00:59:33.310943 u2DelayCellOfst[1]=10 cells (3 PI)
8450 00:59:33.314064 u2DelayCellOfst[2]=0 cells (0 PI)
8451 00:59:33.317466 u2DelayCellOfst[3]=7 cells (2 PI)
8452 00:59:33.321004 u2DelayCellOfst[4]=10 cells (3 PI)
8453 00:59:33.324476 u2DelayCellOfst[5]=17 cells (5 PI)
8454 00:59:33.327551 u2DelayCellOfst[6]=17 cells (5 PI)
8455 00:59:33.330662 u2DelayCellOfst[7]=7 cells (2 PI)
8456 00:59:33.334753 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8457 00:59:33.337747 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8458 00:59:33.340797 == TX Byte 1 ==
8459 00:59:33.343868 u2DelayCellOfst[8]=0 cells (0 PI)
8460 00:59:33.346979 u2DelayCellOfst[9]=3 cells (1 PI)
8461 00:59:33.350587 u2DelayCellOfst[10]=10 cells (3 PI)
8462 00:59:33.353783 u2DelayCellOfst[11]=3 cells (1 PI)
8463 00:59:33.356864 u2DelayCellOfst[12]=14 cells (4 PI)
8464 00:59:33.360028 u2DelayCellOfst[13]=17 cells (5 PI)
8465 00:59:33.363583 u2DelayCellOfst[14]=17 cells (5 PI)
8466 00:59:33.364095 u2DelayCellOfst[15]=17 cells (5 PI)
8467 00:59:33.369793 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8468 00:59:33.373325 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8469 00:59:33.376838 DramC Write-DBI on
8470 00:59:33.377342 ==
8471 00:59:33.379790 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 00:59:33.383442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 00:59:33.383956 ==
8474 00:59:33.384287
8475 00:59:33.384590
8476 00:59:33.386902 TX Vref Scan disable
8477 00:59:33.387455 == TX Byte 0 ==
8478 00:59:33.393540 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8479 00:59:33.394045 == TX Byte 1 ==
8480 00:59:33.396422 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8481 00:59:33.400048 DramC Write-DBI off
8482 00:59:33.400586
8483 00:59:33.400933 [DATLAT]
8484 00:59:33.402803 Freq=1600, CH1 RK0
8485 00:59:33.403223
8486 00:59:33.403682 DATLAT Default: 0xf
8487 00:59:33.406510 0, 0xFFFF, sum = 0
8488 00:59:33.409298 1, 0xFFFF, sum = 0
8489 00:59:33.409715 2, 0xFFFF, sum = 0
8490 00:59:33.412662 3, 0xFFFF, sum = 0
8491 00:59:33.413082 4, 0xFFFF, sum = 0
8492 00:59:33.415893 5, 0xFFFF, sum = 0
8493 00:59:33.416316 6, 0xFFFF, sum = 0
8494 00:59:33.419735 7, 0xFFFF, sum = 0
8495 00:59:33.420160 8, 0xFFFF, sum = 0
8496 00:59:33.422771 9, 0xFFFF, sum = 0
8497 00:59:33.423241 10, 0xFFFF, sum = 0
8498 00:59:33.425746 11, 0xFFFF, sum = 0
8499 00:59:33.426163 12, 0xFFFF, sum = 0
8500 00:59:33.429258 13, 0xFFFF, sum = 0
8501 00:59:33.429679 14, 0x0, sum = 1
8502 00:59:33.432279 15, 0x0, sum = 2
8503 00:59:33.432698 16, 0x0, sum = 3
8504 00:59:33.435836 17, 0x0, sum = 4
8505 00:59:33.436357 best_step = 15
8506 00:59:33.436687
8507 00:59:33.436989 ==
8508 00:59:33.439053 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 00:59:33.445374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 00:59:33.445888 ==
8511 00:59:33.446218 RX Vref Scan: 1
8512 00:59:33.446589
8513 00:59:33.448910 Set Vref Range= 24 -> 127
8514 00:59:33.449398
8515 00:59:33.452160 RX Vref 24 -> 127, step: 1
8516 00:59:33.452615
8517 00:59:33.455854 RX Delay 19 -> 252, step: 4
8518 00:59:33.456268
8519 00:59:33.458713 Set Vref, RX VrefLevel [Byte0]: 24
8520 00:59:33.462442 [Byte1]: 24
8521 00:59:33.463082
8522 00:59:33.465433 Set Vref, RX VrefLevel [Byte0]: 25
8523 00:59:33.468386 [Byte1]: 25
8524 00:59:33.468803
8525 00:59:33.471883 Set Vref, RX VrefLevel [Byte0]: 26
8526 00:59:33.474813 [Byte1]: 26
8527 00:59:33.479550
8528 00:59:33.480051 Set Vref, RX VrefLevel [Byte0]: 27
8529 00:59:33.481988 [Byte1]: 27
8530 00:59:33.485899
8531 00:59:33.486315 Set Vref, RX VrefLevel [Byte0]: 28
8532 00:59:33.489141 [Byte1]: 28
8533 00:59:33.493739
8534 00:59:33.494218 Set Vref, RX VrefLevel [Byte0]: 29
8535 00:59:33.497047 [Byte1]: 29
8536 00:59:33.501005
8537 00:59:33.501441 Set Vref, RX VrefLevel [Byte0]: 30
8538 00:59:33.507493 [Byte1]: 30
8539 00:59:33.508145
8540 00:59:33.510730 Set Vref, RX VrefLevel [Byte0]: 31
8541 00:59:33.514224 [Byte1]: 31
8542 00:59:33.514636
8543 00:59:33.517282 Set Vref, RX VrefLevel [Byte0]: 32
8544 00:59:33.521050 [Byte1]: 32
8545 00:59:33.521472
8546 00:59:33.524287 Set Vref, RX VrefLevel [Byte0]: 33
8547 00:59:33.527450 [Byte1]: 33
8548 00:59:33.531855
8549 00:59:33.532371 Set Vref, RX VrefLevel [Byte0]: 34
8550 00:59:33.535156 [Byte1]: 34
8551 00:59:33.539912
8552 00:59:33.540327 Set Vref, RX VrefLevel [Byte0]: 35
8553 00:59:33.542334 [Byte1]: 35
8554 00:59:33.547001
8555 00:59:33.547489 Set Vref, RX VrefLevel [Byte0]: 36
8556 00:59:33.549535 [Byte1]: 36
8557 00:59:33.554192
8558 00:59:33.554704 Set Vref, RX VrefLevel [Byte0]: 37
8559 00:59:33.557295 [Byte1]: 37
8560 00:59:33.561859
8561 00:59:33.562370 Set Vref, RX VrefLevel [Byte0]: 38
8562 00:59:33.564976 [Byte1]: 38
8563 00:59:33.569771
8564 00:59:33.570271 Set Vref, RX VrefLevel [Byte0]: 39
8565 00:59:33.572496 [Byte1]: 39
8566 00:59:33.577122
8567 00:59:33.577621 Set Vref, RX VrefLevel [Byte0]: 40
8568 00:59:33.580185 [Byte1]: 40
8569 00:59:33.584284
8570 00:59:33.584786 Set Vref, RX VrefLevel [Byte0]: 41
8571 00:59:33.587505 [Byte1]: 41
8572 00:59:33.592282
8573 00:59:33.592799 Set Vref, RX VrefLevel [Byte0]: 42
8574 00:59:33.595278 [Byte1]: 42
8575 00:59:33.599744
8576 00:59:33.600232 Set Vref, RX VrefLevel [Byte0]: 43
8577 00:59:33.606442 [Byte1]: 43
8578 00:59:33.606962
8579 00:59:33.609679 Set Vref, RX VrefLevel [Byte0]: 44
8580 00:59:33.612598 [Byte1]: 44
8581 00:59:33.613042
8582 00:59:33.615799 Set Vref, RX VrefLevel [Byte0]: 45
8583 00:59:33.618964 [Byte1]: 45
8584 00:59:33.619418
8585 00:59:33.622660 Set Vref, RX VrefLevel [Byte0]: 46
8586 00:59:33.625935 [Byte1]: 46
8587 00:59:33.629597
8588 00:59:33.630014 Set Vref, RX VrefLevel [Byte0]: 47
8589 00:59:33.632989 [Byte1]: 47
8590 00:59:33.637297
8591 00:59:33.637737 Set Vref, RX VrefLevel [Byte0]: 48
8592 00:59:33.640889 [Byte1]: 48
8593 00:59:33.645126
8594 00:59:33.645538 Set Vref, RX VrefLevel [Byte0]: 49
8595 00:59:33.648347 [Byte1]: 49
8596 00:59:33.652385
8597 00:59:33.652797 Set Vref, RX VrefLevel [Byte0]: 50
8598 00:59:33.655889 [Byte1]: 50
8599 00:59:33.660188
8600 00:59:33.660696 Set Vref, RX VrefLevel [Byte0]: 51
8601 00:59:33.663740 [Byte1]: 51
8602 00:59:33.667661
8603 00:59:33.668072 Set Vref, RX VrefLevel [Byte0]: 52
8604 00:59:33.670972 [Byte1]: 52
8605 00:59:33.675591
8606 00:59:33.676083 Set Vref, RX VrefLevel [Byte0]: 53
8607 00:59:33.678734 [Byte1]: 53
8608 00:59:33.683238
8609 00:59:33.683699 Set Vref, RX VrefLevel [Byte0]: 54
8610 00:59:33.686888 [Byte1]: 54
8611 00:59:33.690295
8612 00:59:33.690707 Set Vref, RX VrefLevel [Byte0]: 55
8613 00:59:33.694366 [Byte1]: 55
8614 00:59:33.698506
8615 00:59:33.698920 Set Vref, RX VrefLevel [Byte0]: 56
8616 00:59:33.701719 [Byte1]: 56
8617 00:59:33.705500
8618 00:59:33.705917 Set Vref, RX VrefLevel [Byte0]: 57
8619 00:59:33.708751 [Byte1]: 57
8620 00:59:33.714125
8621 00:59:33.714539 Set Vref, RX VrefLevel [Byte0]: 58
8622 00:59:33.716644 [Byte1]: 58
8623 00:59:33.720577
8624 00:59:33.721004 Set Vref, RX VrefLevel [Byte0]: 59
8625 00:59:33.723903 [Byte1]: 59
8626 00:59:33.728715
8627 00:59:33.729231 Set Vref, RX VrefLevel [Byte0]: 60
8628 00:59:33.731616 [Byte1]: 60
8629 00:59:33.736300
8630 00:59:33.736812 Set Vref, RX VrefLevel [Byte0]: 61
8631 00:59:33.739328 [Byte1]: 61
8632 00:59:33.744079
8633 00:59:33.744491 Set Vref, RX VrefLevel [Byte0]: 62
8634 00:59:33.746387 [Byte1]: 62
8635 00:59:33.751083
8636 00:59:33.751531 Set Vref, RX VrefLevel [Byte0]: 63
8637 00:59:33.753967 [Byte1]: 63
8638 00:59:33.758803
8639 00:59:33.759215 Set Vref, RX VrefLevel [Byte0]: 64
8640 00:59:33.762548 [Byte1]: 64
8641 00:59:33.766415
8642 00:59:33.766941 Set Vref, RX VrefLevel [Byte0]: 65
8643 00:59:33.769401 [Byte1]: 65
8644 00:59:33.773433
8645 00:59:33.773854 Set Vref, RX VrefLevel [Byte0]: 66
8646 00:59:33.777248 [Byte1]: 66
8647 00:59:33.781910
8648 00:59:33.782417 Set Vref, RX VrefLevel [Byte0]: 67
8649 00:59:33.784355 [Byte1]: 67
8650 00:59:33.789552
8651 00:59:33.790065 Set Vref, RX VrefLevel [Byte0]: 68
8652 00:59:33.792491 [Byte1]: 68
8653 00:59:33.796623
8654 00:59:33.797133 Set Vref, RX VrefLevel [Byte0]: 69
8655 00:59:33.803545 [Byte1]: 69
8656 00:59:33.804056
8657 00:59:33.806573 Set Vref, RX VrefLevel [Byte0]: 70
8658 00:59:33.809704 [Byte1]: 70
8659 00:59:33.810122
8660 00:59:33.812939 Set Vref, RX VrefLevel [Byte0]: 71
8661 00:59:33.816449 [Byte1]: 71
8662 00:59:33.816861
8663 00:59:33.819905 Set Vref, RX VrefLevel [Byte0]: 72
8664 00:59:33.822459 [Byte1]: 72
8665 00:59:33.826921
8666 00:59:33.827484 Final RX Vref Byte 0 = 59 to rank0
8667 00:59:33.829779 Final RX Vref Byte 1 = 62 to rank0
8668 00:59:33.833188 Final RX Vref Byte 0 = 59 to rank1
8669 00:59:33.836658 Final RX Vref Byte 1 = 62 to rank1==
8670 00:59:33.839691 Dram Type= 6, Freq= 0, CH_1, rank 0
8671 00:59:33.846495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8672 00:59:33.846910 ==
8673 00:59:33.847237 DQS Delay:
8674 00:59:33.849933 DQS0 = 0, DQS1 = 0
8675 00:59:33.850370 DQM Delay:
8676 00:59:33.850912 DQM0 = 132, DQM1 = 128
8677 00:59:33.852814 DQ Delay:
8678 00:59:33.856065 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =130
8679 00:59:33.859240 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8680 00:59:33.862805 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8681 00:59:33.867328 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8682 00:59:33.867525
8683 00:59:33.867665
8684 00:59:33.867795
8685 00:59:33.869312 [DramC_TX_OE_Calibration] TA2
8686 00:59:33.873148 Original DQ_B0 (3 6) =30, OEN = 27
8687 00:59:33.875744 Original DQ_B1 (3 6) =30, OEN = 27
8688 00:59:33.878920 24, 0x0, End_B0=24 End_B1=24
8689 00:59:33.882617 25, 0x0, End_B0=25 End_B1=25
8690 00:59:33.882808 26, 0x0, End_B0=26 End_B1=26
8691 00:59:33.885750 27, 0x0, End_B0=27 End_B1=27
8692 00:59:33.889821 28, 0x0, End_B0=28 End_B1=28
8693 00:59:33.892001 29, 0x0, End_B0=29 End_B1=29
8694 00:59:33.895676 30, 0x0, End_B0=30 End_B1=30
8695 00:59:33.895868 31, 0x4141, End_B0=30 End_B1=30
8696 00:59:33.898584 Byte0 end_step=30 best_step=27
8697 00:59:33.902562 Byte1 end_step=30 best_step=27
8698 00:59:33.905426 Byte0 TX OE(2T, 0.5T) = (3, 3)
8699 00:59:33.909324 Byte1 TX OE(2T, 0.5T) = (3, 3)
8700 00:59:33.909514
8701 00:59:33.909660
8702 00:59:33.914840 [DQSOSCAuto] RK0, (LSB)MR18= 0xb13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
8703 00:59:33.918752 CH1 RK0: MR19=303, MR18=B13
8704 00:59:33.925009 CH1_RK0: MR19=0x303, MR18=0xB13, DQSOSC=400, MR23=63, INC=23, DEC=15
8705 00:59:33.925200
8706 00:59:33.928465 ----->DramcWriteLeveling(PI) begin...
8707 00:59:33.928739 ==
8708 00:59:33.931740 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 00:59:33.934565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 00:59:33.934756 ==
8711 00:59:33.938122 Write leveling (Byte 0): 24 => 24
8712 00:59:33.941304 Write leveling (Byte 1): 24 => 24
8713 00:59:33.944510 DramcWriteLeveling(PI) end<-----
8714 00:59:33.944700
8715 00:59:33.944849 ==
8716 00:59:33.948102 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 00:59:33.954529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 00:59:33.954721 ==
8719 00:59:33.954868 [Gating] SW mode calibration
8720 00:59:33.964576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8721 00:59:33.967551 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8722 00:59:33.974328 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8723 00:59:33.977882 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8724 00:59:33.981071 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8725 00:59:33.987720 1 4 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8726 00:59:33.991173 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 00:59:33.994947 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 00:59:34.001430 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8729 00:59:34.004165 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 00:59:34.007755 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 00:59:34.013801 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8732 00:59:34.017659 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8733 00:59:34.020794 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8734 00:59:34.027237 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8735 00:59:34.030708 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 00:59:34.034075 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 00:59:34.040540 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 00:59:34.044165 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 00:59:34.047196 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8740 00:59:34.053185 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8741 00:59:34.056817 1 6 12 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
8742 00:59:34.059922 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 00:59:34.066650 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 00:59:34.069739 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8745 00:59:34.073125 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 00:59:34.079991 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 00:59:34.083149 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 00:59:34.086120 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8749 00:59:34.093674 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8750 00:59:34.096485 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8751 00:59:34.099562 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 00:59:34.105926 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 00:59:34.109447 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 00:59:34.112829 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 00:59:34.119520 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 00:59:34.123355 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 00:59:34.125868 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 00:59:34.132256 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 00:59:34.135735 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 00:59:34.138790 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 00:59:34.146430 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 00:59:34.148908 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 00:59:34.152269 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8764 00:59:34.158618 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8765 00:59:34.162289 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8766 00:59:34.165824 Total UI for P1: 0, mck2ui 16
8767 00:59:34.168619 best dqsien dly found for B0: ( 1, 9, 6)
8768 00:59:34.171550 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 00:59:34.174870 Total UI for P1: 0, mck2ui 16
8770 00:59:34.178076 best dqsien dly found for B1: ( 1, 9, 10)
8771 00:59:34.181869 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8772 00:59:34.184844 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8773 00:59:34.185351
8774 00:59:34.191526 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8775 00:59:34.195091 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8776 00:59:34.198335 [Gating] SW calibration Done
8777 00:59:34.198841 ==
8778 00:59:34.201946 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 00:59:34.205154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 00:59:34.205670 ==
8781 00:59:34.205999 RX Vref Scan: 0
8782 00:59:34.206300
8783 00:59:34.207933 RX Vref 0 -> 0, step: 1
8784 00:59:34.208347
8785 00:59:34.211782 RX Delay 0 -> 252, step: 8
8786 00:59:34.214899 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8787 00:59:34.218092 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8788 00:59:34.224767 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8789 00:59:34.228297 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8790 00:59:34.231065 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8791 00:59:34.234336 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8792 00:59:34.237683 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8793 00:59:34.244233 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8794 00:59:34.247554 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8795 00:59:34.250986 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8796 00:59:34.254910 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8797 00:59:34.257625 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8798 00:59:34.263864 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8799 00:59:34.267454 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8800 00:59:34.270675 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8801 00:59:34.273780 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8802 00:59:34.274194 ==
8803 00:59:34.277323 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 00:59:34.284261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 00:59:34.284773 ==
8806 00:59:34.285100 DQS Delay:
8807 00:59:34.287286 DQS0 = 0, DQS1 = 0
8808 00:59:34.287753 DQM Delay:
8809 00:59:34.291027 DQM0 = 133, DQM1 = 130
8810 00:59:34.291585 DQ Delay:
8811 00:59:34.293818 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8812 00:59:34.297418 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8813 00:59:34.300208 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8814 00:59:34.303743 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8815 00:59:34.304249
8816 00:59:34.304579
8817 00:59:34.304881 ==
8818 00:59:34.306811 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 00:59:34.313361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 00:59:34.313914 ==
8821 00:59:34.314252
8822 00:59:34.314555
8823 00:59:34.314845 TX Vref Scan disable
8824 00:59:34.317105 == TX Byte 0 ==
8825 00:59:34.320567 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8826 00:59:34.326953 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8827 00:59:34.327497 == TX Byte 1 ==
8828 00:59:34.330271 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8829 00:59:34.336650 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8830 00:59:34.337192 ==
8831 00:59:34.340072 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 00:59:34.343185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 00:59:34.343771 ==
8834 00:59:34.356597
8835 00:59:34.359931 TX Vref early break, caculate TX vref
8836 00:59:34.364197 TX Vref=16, minBit 9, minWin=22, winSum=376
8837 00:59:34.366382 TX Vref=18, minBit 9, minWin=22, winSum=384
8838 00:59:34.369761 TX Vref=20, minBit 9, minWin=23, winSum=397
8839 00:59:34.372959 TX Vref=22, minBit 9, minWin=24, winSum=405
8840 00:59:34.376068 TX Vref=24, minBit 1, minWin=25, winSum=413
8841 00:59:34.383095 TX Vref=26, minBit 1, minWin=25, winSum=420
8842 00:59:34.386090 TX Vref=28, minBit 9, minWin=25, winSum=422
8843 00:59:34.390274 TX Vref=30, minBit 9, minWin=25, winSum=420
8844 00:59:34.392986 TX Vref=32, minBit 0, minWin=24, winSum=413
8845 00:59:34.395653 TX Vref=34, minBit 0, minWin=24, winSum=404
8846 00:59:34.402752 TX Vref=36, minBit 0, minWin=24, winSum=398
8847 00:59:34.406283 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
8848 00:59:34.406807
8849 00:59:34.409692 Final TX Range 0 Vref 28
8850 00:59:34.410208
8851 00:59:34.410539 ==
8852 00:59:34.412230 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 00:59:34.415656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 00:59:34.419187 ==
8855 00:59:34.419638
8856 00:59:34.419968
8857 00:59:34.420273 TX Vref Scan disable
8858 00:59:34.425663 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8859 00:59:34.426160 == TX Byte 0 ==
8860 00:59:34.429215 u2DelayCellOfst[0]=14 cells (4 PI)
8861 00:59:34.433049 u2DelayCellOfst[1]=10 cells (3 PI)
8862 00:59:34.435806 u2DelayCellOfst[2]=0 cells (0 PI)
8863 00:59:34.438930 u2DelayCellOfst[3]=3 cells (1 PI)
8864 00:59:34.442567 u2DelayCellOfst[4]=7 cells (2 PI)
8865 00:59:34.445814 u2DelayCellOfst[5]=17 cells (5 PI)
8866 00:59:34.448787 u2DelayCellOfst[6]=14 cells (4 PI)
8867 00:59:34.451949 u2DelayCellOfst[7]=7 cells (2 PI)
8868 00:59:34.456131 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8869 00:59:34.458682 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8870 00:59:34.462107 == TX Byte 1 ==
8871 00:59:34.465452 u2DelayCellOfst[8]=0 cells (0 PI)
8872 00:59:34.468472 u2DelayCellOfst[9]=0 cells (0 PI)
8873 00:59:34.471722 u2DelayCellOfst[10]=10 cells (3 PI)
8874 00:59:34.475394 u2DelayCellOfst[11]=3 cells (1 PI)
8875 00:59:34.478064 u2DelayCellOfst[12]=14 cells (4 PI)
8876 00:59:34.482153 u2DelayCellOfst[13]=14 cells (4 PI)
8877 00:59:34.484694 u2DelayCellOfst[14]=17 cells (5 PI)
8878 00:59:34.487980 u2DelayCellOfst[15]=17 cells (5 PI)
8879 00:59:34.491495 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8880 00:59:34.495071 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8881 00:59:34.498676 DramC Write-DBI on
8882 00:59:34.499181 ==
8883 00:59:34.501002 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 00:59:34.504384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 00:59:34.504832 ==
8886 00:59:34.505162
8887 00:59:34.505462
8888 00:59:34.507691 TX Vref Scan disable
8889 00:59:34.511082 == TX Byte 0 ==
8890 00:59:34.514435 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8891 00:59:34.514851 == TX Byte 1 ==
8892 00:59:34.520870 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8893 00:59:34.521371 DramC Write-DBI off
8894 00:59:34.521699
8895 00:59:34.522002 [DATLAT]
8896 00:59:34.524586 Freq=1600, CH1 RK1
8897 00:59:34.525088
8898 00:59:34.527790 DATLAT Default: 0xf
8899 00:59:34.528298 0, 0xFFFF, sum = 0
8900 00:59:34.531187 1, 0xFFFF, sum = 0
8901 00:59:34.531742 2, 0xFFFF, sum = 0
8902 00:59:34.534421 3, 0xFFFF, sum = 0
8903 00:59:34.534929 4, 0xFFFF, sum = 0
8904 00:59:34.537482 5, 0xFFFF, sum = 0
8905 00:59:34.537998 6, 0xFFFF, sum = 0
8906 00:59:34.540917 7, 0xFFFF, sum = 0
8907 00:59:34.541427 8, 0xFFFF, sum = 0
8908 00:59:34.543986 9, 0xFFFF, sum = 0
8909 00:59:34.544492 10, 0xFFFF, sum = 0
8910 00:59:34.547347 11, 0xFFFF, sum = 0
8911 00:59:34.547910 12, 0xFFFF, sum = 0
8912 00:59:34.550494 13, 0xFFFF, sum = 0
8913 00:59:34.550913 14, 0x0, sum = 1
8914 00:59:34.553700 15, 0x0, sum = 2
8915 00:59:34.554319 16, 0x0, sum = 3
8916 00:59:34.557335 17, 0x0, sum = 4
8917 00:59:34.557754 best_step = 15
8918 00:59:34.558190
8919 00:59:34.558502 ==
8920 00:59:34.560285 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 00:59:34.566809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 00:59:34.567299 ==
8923 00:59:34.567679 RX Vref Scan: 0
8924 00:59:34.568047
8925 00:59:34.570476 RX Vref 0 -> 0, step: 1
8926 00:59:34.570893
8927 00:59:34.573585 RX Delay 19 -> 252, step: 4
8928 00:59:34.577442 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8929 00:59:34.580193 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8930 00:59:34.586774 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8931 00:59:34.590686 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8932 00:59:34.593204 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8933 00:59:34.596607 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8934 00:59:34.600741 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8935 00:59:34.606314 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8936 00:59:34.610359 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8937 00:59:34.613083 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8938 00:59:34.616425 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8939 00:59:34.619839 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8940 00:59:34.626633 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8941 00:59:34.629629 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8942 00:59:34.633225 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8943 00:59:34.636336 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8944 00:59:34.636849 ==
8945 00:59:34.639674 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 00:59:34.646709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 00:59:34.647221 ==
8948 00:59:34.647607 DQS Delay:
8949 00:59:34.649663 DQS0 = 0, DQS1 = 0
8950 00:59:34.650075 DQM Delay:
8951 00:59:34.653306 DQM0 = 131, DQM1 = 127
8952 00:59:34.653816 DQ Delay:
8953 00:59:34.656327 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8954 00:59:34.659179 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =128
8955 00:59:34.663015 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8956 00:59:34.666210 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8957 00:59:34.666717
8958 00:59:34.667041
8959 00:59:34.667341
8960 00:59:34.669248 [DramC_TX_OE_Calibration] TA2
8961 00:59:34.672787 Original DQ_B0 (3 6) =30, OEN = 27
8962 00:59:34.676583 Original DQ_B1 (3 6) =30, OEN = 27
8963 00:59:34.679268 24, 0x0, End_B0=24 End_B1=24
8964 00:59:34.682425 25, 0x0, End_B0=25 End_B1=25
8965 00:59:34.682991 26, 0x0, End_B0=26 End_B1=26
8966 00:59:34.685865 27, 0x0, End_B0=27 End_B1=27
8967 00:59:34.689761 28, 0x0, End_B0=28 End_B1=28
8968 00:59:34.692187 29, 0x0, End_B0=29 End_B1=29
8969 00:59:34.695449 30, 0x0, End_B0=30 End_B1=30
8970 00:59:34.695876 31, 0x4141, End_B0=30 End_B1=30
8971 00:59:34.698925 Byte0 end_step=30 best_step=27
8972 00:59:34.702388 Byte1 end_step=30 best_step=27
8973 00:59:34.706041 Byte0 TX OE(2T, 0.5T) = (3, 3)
8974 00:59:34.709074 Byte1 TX OE(2T, 0.5T) = (3, 3)
8975 00:59:34.709596
8976 00:59:34.709923
8977 00:59:34.715854 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
8978 00:59:34.719166 CH1 RK1: MR19=303, MR18=101E
8979 00:59:34.725029 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
8980 00:59:34.728358 [RxdqsGatingPostProcess] freq 1600
8981 00:59:34.735524 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8982 00:59:34.739097 best DQS0 dly(2T, 0.5T) = (1, 1)
8983 00:59:34.739661 best DQS1 dly(2T, 0.5T) = (1, 1)
8984 00:59:34.741877 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8985 00:59:34.745236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8986 00:59:34.748079 best DQS0 dly(2T, 0.5T) = (1, 1)
8987 00:59:34.751123 best DQS1 dly(2T, 0.5T) = (1, 1)
8988 00:59:34.755021 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8989 00:59:34.757964 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8990 00:59:34.761152 Pre-setting of DQS Precalculation
8991 00:59:34.767652 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8992 00:59:34.774256 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8993 00:59:34.781125 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8994 00:59:34.781543
8995 00:59:34.781959
8996 00:59:34.784196 [Calibration Summary] 3200 Mbps
8997 00:59:34.784613 CH 0, Rank 0
8998 00:59:34.787481 SW Impedance : PASS
8999 00:59:34.790837 DUTY Scan : NO K
9000 00:59:34.791255 ZQ Calibration : PASS
9001 00:59:34.794366 Jitter Meter : NO K
9002 00:59:34.797674 CBT Training : PASS
9003 00:59:34.798087 Write leveling : PASS
9004 00:59:34.800955 RX DQS gating : PASS
9005 00:59:34.803806 RX DQ/DQS(RDDQC) : PASS
9006 00:59:34.804341 TX DQ/DQS : PASS
9007 00:59:34.807761 RX DATLAT : PASS
9008 00:59:34.808268 RX DQ/DQS(Engine): PASS
9009 00:59:34.810748 TX OE : PASS
9010 00:59:34.811260 All Pass.
9011 00:59:34.811654
9012 00:59:34.814290 CH 0, Rank 1
9013 00:59:34.817496 SW Impedance : PASS
9014 00:59:34.817913 DUTY Scan : NO K
9015 00:59:34.821001 ZQ Calibration : PASS
9016 00:59:34.821513 Jitter Meter : NO K
9017 00:59:34.823884 CBT Training : PASS
9018 00:59:34.827798 Write leveling : PASS
9019 00:59:34.828311 RX DQS gating : PASS
9020 00:59:34.831108 RX DQ/DQS(RDDQC) : PASS
9021 00:59:34.833703 TX DQ/DQS : PASS
9022 00:59:34.834120 RX DATLAT : PASS
9023 00:59:34.836863 RX DQ/DQS(Engine): PASS
9024 00:59:34.840537 TX OE : PASS
9025 00:59:34.841122 All Pass.
9026 00:59:34.841453
9027 00:59:34.841758 CH 1, Rank 0
9028 00:59:34.843905 SW Impedance : PASS
9029 00:59:34.846848 DUTY Scan : NO K
9030 00:59:34.847358 ZQ Calibration : PASS
9031 00:59:34.850209 Jitter Meter : NO K
9032 00:59:34.853498 CBT Training : PASS
9033 00:59:34.854007 Write leveling : PASS
9034 00:59:34.856738 RX DQS gating : PASS
9035 00:59:34.859879 RX DQ/DQS(RDDQC) : PASS
9036 00:59:34.860294 TX DQ/DQS : PASS
9037 00:59:34.863596 RX DATLAT : PASS
9038 00:59:34.866744 RX DQ/DQS(Engine): PASS
9039 00:59:34.867251 TX OE : PASS
9040 00:59:34.870324 All Pass.
9041 00:59:34.870738
9042 00:59:34.871060 CH 1, Rank 1
9043 00:59:34.873530 SW Impedance : PASS
9044 00:59:34.874006 DUTY Scan : NO K
9045 00:59:34.876378 ZQ Calibration : PASS
9046 00:59:34.880125 Jitter Meter : NO K
9047 00:59:34.880541 CBT Training : PASS
9048 00:59:34.883114 Write leveling : PASS
9049 00:59:34.886633 RX DQS gating : PASS
9050 00:59:34.887049 RX DQ/DQS(RDDQC) : PASS
9051 00:59:34.889869 TX DQ/DQS : PASS
9052 00:59:34.890287 RX DATLAT : PASS
9053 00:59:34.893437 RX DQ/DQS(Engine): PASS
9054 00:59:34.896342 TX OE : PASS
9055 00:59:34.896853 All Pass.
9056 00:59:34.897180
9057 00:59:34.899719 DramC Write-DBI on
9058 00:59:34.902960 PER_BANK_REFRESH: Hybrid Mode
9059 00:59:34.903498 TX_TRACKING: ON
9060 00:59:34.912779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9061 00:59:34.919531 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9062 00:59:34.925899 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9063 00:59:34.929080 [FAST_K] Save calibration result to emmc
9064 00:59:34.932831 sync common calibartion params.
9065 00:59:34.935806 sync cbt_mode0:1, 1:1
9066 00:59:34.940227 dram_init: ddr_geometry: 2
9067 00:59:34.940738 dram_init: ddr_geometry: 2
9068 00:59:34.942894 dram_init: ddr_geometry: 2
9069 00:59:34.945962 0:dram_rank_size:100000000
9070 00:59:34.948990 1:dram_rank_size:100000000
9071 00:59:34.952389 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9072 00:59:34.955730 DFS_SHUFFLE_HW_MODE: ON
9073 00:59:34.958819 dramc_set_vcore_voltage set vcore to 725000
9074 00:59:34.962237 Read voltage for 1600, 0
9075 00:59:34.962748 Vio18 = 0
9076 00:59:34.963077 Vcore = 725000
9077 00:59:34.965713 Vdram = 0
9078 00:59:34.966218 Vddq = 0
9079 00:59:34.966544 Vmddr = 0
9080 00:59:34.968723 switch to 3200 Mbps bootup
9081 00:59:34.971833 [DramcRunTimeConfig]
9082 00:59:34.972246 PHYPLL
9083 00:59:34.972565 DPM_CONTROL_AFTERK: ON
9084 00:59:34.975423 PER_BANK_REFRESH: ON
9085 00:59:34.978504 REFRESH_OVERHEAD_REDUCTION: ON
9086 00:59:34.978920 CMD_PICG_NEW_MODE: OFF
9087 00:59:34.981817 XRTWTW_NEW_MODE: ON
9088 00:59:34.985072 XRTRTR_NEW_MODE: ON
9089 00:59:34.985483 TX_TRACKING: ON
9090 00:59:34.988749 RDSEL_TRACKING: OFF
9091 00:59:34.989161 DQS Precalculation for DVFS: ON
9092 00:59:34.992103 RX_TRACKING: OFF
9093 00:59:34.992614 HW_GATING DBG: ON
9094 00:59:34.995446 ZQCS_ENABLE_LP4: ON
9095 00:59:34.998110 RX_PICG_NEW_MODE: ON
9096 00:59:34.998525 TX_PICG_NEW_MODE: ON
9097 00:59:35.001684 ENABLE_RX_DCM_DPHY: ON
9098 00:59:35.005086 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9099 00:59:35.005599 DUMMY_READ_FOR_TRACKING: OFF
9100 00:59:35.008090 !!! SPM_CONTROL_AFTERK: OFF
9101 00:59:35.012044 !!! SPM could not control APHY
9102 00:59:35.014812 IMPEDANCE_TRACKING: ON
9103 00:59:35.015284 TEMP_SENSOR: ON
9104 00:59:35.018481 HW_SAVE_FOR_SR: OFF
9105 00:59:35.021691 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9106 00:59:35.025232 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9107 00:59:35.025752 Read ODT Tracking: ON
9108 00:59:35.028192 Refresh Rate DeBounce: ON
9109 00:59:35.031721 DFS_NO_QUEUE_FLUSH: ON
9110 00:59:35.035195 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9111 00:59:35.035815 ENABLE_DFS_RUNTIME_MRW: OFF
9112 00:59:35.037927 DDR_RESERVE_NEW_MODE: ON
9113 00:59:35.040990 MR_CBT_SWITCH_FREQ: ON
9114 00:59:35.041472 =========================
9115 00:59:35.061457 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9116 00:59:35.064676 dram_init: ddr_geometry: 2
9117 00:59:35.082684 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9118 00:59:35.085783 dram_init: dram init end (result: 0)
9119 00:59:35.092897 DRAM-K: Full calibration passed in 24407 msecs
9120 00:59:35.096295 MRC: failed to locate region type 0.
9121 00:59:35.096852 DRAM rank0 size:0x100000000,
9122 00:59:35.099515 DRAM rank1 size=0x100000000
9123 00:59:35.109237 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9124 00:59:35.115713 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9125 00:59:35.125612 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9126 00:59:35.132076 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9127 00:59:35.132633 DRAM rank0 size:0x100000000,
9128 00:59:35.135578 DRAM rank1 size=0x100000000
9129 00:59:35.136137 CBMEM:
9130 00:59:35.138774 IMD: root @ 0xfffff000 254 entries.
9131 00:59:35.141900 IMD: root @ 0xffffec00 62 entries.
9132 00:59:35.145337 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9133 00:59:35.152152 WARNING: RO_VPD is uninitialized or empty.
9134 00:59:35.155020 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9135 00:59:35.163064 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9136 00:59:35.175614 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9137 00:59:35.187050 BS: romstage times (exec / console): total (unknown) / 23939 ms
9138 00:59:35.187651
9139 00:59:35.188017
9140 00:59:35.197125 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9141 00:59:35.200254 ARM64: Exception handlers installed.
9142 00:59:35.203682 ARM64: Testing exception
9143 00:59:35.206695 ARM64: Done test exception
9144 00:59:35.207244 Enumerating buses...
9145 00:59:35.210214 Show all devs... Before device enumeration.
9146 00:59:35.212839 Root Device: enabled 1
9147 00:59:35.216648 CPU_CLUSTER: 0: enabled 1
9148 00:59:35.217158 CPU: 00: enabled 1
9149 00:59:35.220200 Compare with tree...
9150 00:59:35.220712 Root Device: enabled 1
9151 00:59:35.223466 CPU_CLUSTER: 0: enabled 1
9152 00:59:35.226470 CPU: 00: enabled 1
9153 00:59:35.226884 Root Device scanning...
9154 00:59:35.229428 scan_static_bus for Root Device
9155 00:59:35.232833 CPU_CLUSTER: 0 enabled
9156 00:59:35.236515 scan_static_bus for Root Device done
9157 00:59:35.239356 scan_bus: bus Root Device finished in 8 msecs
9158 00:59:35.239808 done
9159 00:59:35.246374 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9160 00:59:35.249092 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9161 00:59:35.255865 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9162 00:59:35.262188 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9163 00:59:35.262608 Allocating resources...
9164 00:59:35.265633 Reading resources...
9165 00:59:35.268981 Root Device read_resources bus 0 link: 0
9166 00:59:35.272165 DRAM rank0 size:0x100000000,
9167 00:59:35.272581 DRAM rank1 size=0x100000000
9168 00:59:35.278903 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9169 00:59:35.279466 CPU: 00 missing read_resources
9170 00:59:35.285608 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9171 00:59:35.288639 Root Device read_resources bus 0 link: 0 done
9172 00:59:35.292067 Done reading resources.
9173 00:59:35.295318 Show resources in subtree (Root Device)...After reading.
9174 00:59:35.298625 Root Device child on link 0 CPU_CLUSTER: 0
9175 00:59:35.302315 CPU_CLUSTER: 0 child on link 0 CPU: 00
9176 00:59:35.312143 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9177 00:59:35.314882 CPU: 00
9178 00:59:35.317964 Root Device assign_resources, bus 0 link: 0
9179 00:59:35.321414 CPU_CLUSTER: 0 missing set_resources
9180 00:59:35.324584 Root Device assign_resources, bus 0 link: 0 done
9181 00:59:35.327979 Done setting resources.
9182 00:59:35.331812 Show resources in subtree (Root Device)...After assigning values.
9183 00:59:35.338330 Root Device child on link 0 CPU_CLUSTER: 0
9184 00:59:35.340933 CPU_CLUSTER: 0 child on link 0 CPU: 00
9185 00:59:35.347898 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9186 00:59:35.351324 CPU: 00
9187 00:59:35.351778 Done allocating resources.
9188 00:59:35.357664 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9189 00:59:35.360906 Enabling resources...
9190 00:59:35.361354 done.
9191 00:59:35.364133 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9192 00:59:35.367232 Initializing devices...
9193 00:59:35.367684 Root Device init
9194 00:59:35.370701 init hardware done!
9195 00:59:35.374484 0x00000018: ctrlr->caps
9196 00:59:35.374910 52.000 MHz: ctrlr->f_max
9197 00:59:35.377206 0.400 MHz: ctrlr->f_min
9198 00:59:35.380635 0x40ff8080: ctrlr->voltages
9199 00:59:35.381176 sclk: 390625
9200 00:59:35.381509 Bus Width = 1
9201 00:59:35.383567 sclk: 390625
9202 00:59:35.383982 Bus Width = 1
9203 00:59:35.387652 Early init status = 3
9204 00:59:35.390488 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9205 00:59:35.395990 in-header: 03 fc 00 00 01 00 00 00
9206 00:59:35.398966 in-data: 00
9207 00:59:35.402210 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9208 00:59:35.407827 in-header: 03 fd 00 00 00 00 00 00
9209 00:59:35.410964 in-data:
9210 00:59:35.414476 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9211 00:59:35.418478 in-header: 03 fc 00 00 01 00 00 00
9212 00:59:35.421983 in-data: 00
9213 00:59:35.425106 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9214 00:59:35.431619 in-header: 03 fd 00 00 00 00 00 00
9215 00:59:35.435186 in-data:
9216 00:59:35.437703 [SSUSB] Setting up USB HOST controller...
9217 00:59:35.441525 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9218 00:59:35.444483 [SSUSB] phy power-on done.
9219 00:59:35.447798 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9220 00:59:35.454584 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9221 00:59:35.457647 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9222 00:59:35.463909 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9223 00:59:35.470457 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9224 00:59:35.477237 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9225 00:59:35.483465 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9226 00:59:35.490626 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9227 00:59:35.494379 SPM: binary array size = 0x9dc
9228 00:59:35.496545 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9229 00:59:35.503292 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9230 00:59:35.509925 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9231 00:59:35.516780 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9232 00:59:35.519865 configure_display: Starting display init
9233 00:59:35.554300 anx7625_power_on_init: Init interface.
9234 00:59:35.558079 anx7625_disable_pd_protocol: Disabled PD feature.
9235 00:59:35.560801 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9236 00:59:35.589000 anx7625_start_dp_work: Secure OCM version=00
9237 00:59:35.592299 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9238 00:59:35.607177 sp_tx_get_edid_block: EDID Block = 1
9239 00:59:35.709675 Extracted contents:
9240 00:59:35.712588 header: 00 ff ff ff ff ff ff 00
9241 00:59:35.716613 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9242 00:59:35.719625 version: 01 04
9243 00:59:35.722551 basic params: 95 1f 11 78 0a
9244 00:59:35.725834 chroma info: 76 90 94 55 54 90 27 21 50 54
9245 00:59:35.729591 established: 00 00 00
9246 00:59:35.735898 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9247 00:59:35.739419 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9248 00:59:35.745906 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9249 00:59:35.752580 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9250 00:59:35.759510 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9251 00:59:35.762319 extensions: 00
9252 00:59:35.762819 checksum: fb
9253 00:59:35.763461
9254 00:59:35.768730 Manufacturer: IVO Model 57d Serial Number 0
9255 00:59:35.769237 Made week 0 of 2020
9256 00:59:35.771966 EDID version: 1.4
9257 00:59:35.772382 Digital display
9258 00:59:35.774790 6 bits per primary color channel
9259 00:59:35.775214 DisplayPort interface
9260 00:59:35.778771 Maximum image size: 31 cm x 17 cm
9261 00:59:35.782111 Gamma: 220%
9262 00:59:35.782629 Check DPMS levels
9263 00:59:35.788608 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9264 00:59:35.792153 First detailed timing is preferred timing
9265 00:59:35.792739 Established timings supported:
9266 00:59:35.795447 Standard timings supported:
9267 00:59:35.798534 Detailed timings
9268 00:59:35.802112 Hex of detail: 383680a07038204018303c0035ae10000019
9269 00:59:35.808231 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9270 00:59:35.811398 0780 0798 07c8 0820 hborder 0
9271 00:59:35.814523 0438 043b 0447 0458 vborder 0
9272 00:59:35.817807 -hsync -vsync
9273 00:59:35.818401 Did detailed timing
9274 00:59:35.824625 Hex of detail: 000000000000000000000000000000000000
9275 00:59:35.827653 Manufacturer-specified data, tag 0
9276 00:59:35.831328 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9277 00:59:35.834809 ASCII string: InfoVision
9278 00:59:35.837737 Hex of detail: 000000fe00523134304e574635205248200a
9279 00:59:35.841550 ASCII string: R140NWF5 RH
9280 00:59:35.842272 Checksum
9281 00:59:35.844102 Checksum: 0xfb (valid)
9282 00:59:35.847698 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9283 00:59:35.850815 DSI data_rate: 832800000 bps
9284 00:59:35.857807 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9285 00:59:35.861072 anx7625_parse_edid: pixelclock(138800).
9286 00:59:35.864018 hactive(1920), hsync(48), hfp(24), hbp(88)
9287 00:59:35.867558 vactive(1080), vsync(12), vfp(3), vbp(17)
9288 00:59:35.870775 anx7625_dsi_config: config dsi.
9289 00:59:35.877260 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9290 00:59:35.891244 anx7625_dsi_config: success to config DSI
9291 00:59:35.894505 anx7625_dp_start: MIPI phy setup OK.
9292 00:59:35.898247 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9293 00:59:35.901014 mtk_ddp_mode_set invalid vrefresh 60
9294 00:59:35.904680 main_disp_path_setup
9295 00:59:35.905093 ovl_layer_smi_id_en
9296 00:59:35.908227 ovl_layer_smi_id_en
9297 00:59:35.908643 ccorr_config
9298 00:59:35.908972 aal_config
9299 00:59:35.910931 gamma_config
9300 00:59:35.911345 postmask_config
9301 00:59:35.914716 dither_config
9302 00:59:35.917872 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9303 00:59:35.923947 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9304 00:59:35.927558 Root Device init finished in 555 msecs
9305 00:59:35.930724 CPU_CLUSTER: 0 init
9306 00:59:35.937238 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9307 00:59:35.943958 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9308 00:59:35.944448 APU_MBOX 0x190000b0 = 0x10001
9309 00:59:35.947597 APU_MBOX 0x190001b0 = 0x10001
9310 00:59:35.950806 APU_MBOX 0x190005b0 = 0x10001
9311 00:59:35.954010 APU_MBOX 0x190006b0 = 0x10001
9312 00:59:35.960550 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9313 00:59:35.970779 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9314 00:59:35.982840 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9315 00:59:35.989858 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9316 00:59:36.001539 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9317 00:59:36.010508 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9318 00:59:36.013704 CPU_CLUSTER: 0 init finished in 81 msecs
9319 00:59:36.016870 Devices initialized
9320 00:59:36.019967 Show all devs... After init.
9321 00:59:36.020426 Root Device: enabled 1
9322 00:59:36.022995 CPU_CLUSTER: 0: enabled 1
9323 00:59:36.026774 CPU: 00: enabled 1
9324 00:59:36.029783 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9325 00:59:36.033517 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9326 00:59:36.036285 ELOG: NV offset 0x57f000 size 0x1000
9327 00:59:36.043253 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9328 00:59:36.050549 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9329 00:59:36.053148 ELOG: Event(17) added with size 13 at 2024-01-19 00:59:36 UTC
9330 00:59:36.060032 out: cmd=0x121: 03 db 21 01 00 00 00 00
9331 00:59:36.063048 in-header: 03 3a 00 00 2c 00 00 00
9332 00:59:36.074342 in-data: 25 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9333 00:59:36.079961 ELOG: Event(A1) added with size 10 at 2024-01-19 00:59:36 UTC
9334 00:59:36.086359 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9335 00:59:36.093344 ELOG: Event(A0) added with size 9 at 2024-01-19 00:59:36 UTC
9336 00:59:36.096322 elog_add_boot_reason: Logged dev mode boot
9337 00:59:36.102723 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9338 00:59:36.103284 Finalize devices...
9339 00:59:36.106232 Devices finalized
9340 00:59:36.109697 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9341 00:59:36.112937 Writing coreboot table at 0xffe64000
9342 00:59:36.116085 0. 000000000010a000-0000000000113fff: RAMSTAGE
9343 00:59:36.122626 1. 0000000040000000-00000000400fffff: RAM
9344 00:59:36.126082 2. 0000000040100000-000000004032afff: RAMSTAGE
9345 00:59:36.129023 3. 000000004032b000-00000000545fffff: RAM
9346 00:59:36.132064 4. 0000000054600000-000000005465ffff: BL31
9347 00:59:36.135820 5. 0000000054660000-00000000ffe63fff: RAM
9348 00:59:36.142376 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9349 00:59:36.145657 7. 0000000100000000-000000023fffffff: RAM
9350 00:59:36.148670 Passing 5 GPIOs to payload:
9351 00:59:36.152427 NAME | PORT | POLARITY | VALUE
9352 00:59:36.159057 EC in RW | 0x000000aa | low | undefined
9353 00:59:36.162113 EC interrupt | 0x00000005 | low | undefined
9354 00:59:36.165212 TPM interrupt | 0x000000ab | high | undefined
9355 00:59:36.172348 SD card detect | 0x00000011 | high | undefined
9356 00:59:36.175303 speaker enable | 0x00000093 | high | undefined
9357 00:59:36.178322 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9358 00:59:36.182225 in-header: 03 f9 00 00 02 00 00 00
9359 00:59:36.185445 in-data: 02 00
9360 00:59:36.188897 ADC[4]: Raw value=902216 ID=7
9361 00:59:36.189445 ADC[3]: Raw value=213916 ID=1
9362 00:59:36.191654 RAM Code: 0x71
9363 00:59:36.195285 ADC[6]: Raw value=75000 ID=0
9364 00:59:36.198190 ADC[5]: Raw value=213916 ID=1
9365 00:59:36.198695 SKU Code: 0x1
9366 00:59:36.205571 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 27f4
9367 00:59:36.206064 coreboot table: 964 bytes.
9368 00:59:36.208200 IMD ROOT 0. 0xfffff000 0x00001000
9369 00:59:36.211291 IMD SMALL 1. 0xffffe000 0x00001000
9370 00:59:36.214678 RO MCACHE 2. 0xffffc000 0x00001104
9371 00:59:36.218092 CONSOLE 3. 0xfff7c000 0x00080000
9372 00:59:36.221256 FMAP 4. 0xfff7b000 0x00000452
9373 00:59:36.225193 TIME STAMP 5. 0xfff7a000 0x00000910
9374 00:59:36.228009 VBOOT WORK 6. 0xfff66000 0x00014000
9375 00:59:36.231516 RAMOOPS 7. 0xffe66000 0x00100000
9376 00:59:36.234415 COREBOOT 8. 0xffe64000 0x00002000
9377 00:59:36.237707 IMD small region:
9378 00:59:36.241170 IMD ROOT 0. 0xffffec00 0x00000400
9379 00:59:36.244438 VPD 1. 0xffffeb80 0x0000006c
9380 00:59:36.247435 MMC STATUS 2. 0xffffeb60 0x00000004
9381 00:59:36.254758 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9382 00:59:36.255284 Probing TPM: done!
9383 00:59:36.261134 Connected to device vid:did:rid of 1ae0:0028:00
9384 00:59:36.267109 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9385 00:59:36.271003 Initialized TPM device CR50 revision 0
9386 00:59:36.273978 Checking cr50 for pending updates
9387 00:59:36.279556 Reading cr50 TPM mode
9388 00:59:36.288629 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9389 00:59:36.295215 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9390 00:59:36.335075 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9391 00:59:36.338559 Checking segment from ROM address 0x40100000
9392 00:59:36.342440 Checking segment from ROM address 0x4010001c
9393 00:59:36.348325 Loading segment from ROM address 0x40100000
9394 00:59:36.348879 code (compression=0)
9395 00:59:36.358401 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9396 00:59:36.365175 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9397 00:59:36.365767 it's not compressed!
9398 00:59:36.371536 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9399 00:59:36.377805 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9400 00:59:36.395997 Loading segment from ROM address 0x4010001c
9401 00:59:36.396536 Entry Point 0x80000000
9402 00:59:36.399306 Loaded segments
9403 00:59:36.402421 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9404 00:59:36.409095 Jumping to boot code at 0x80000000(0xffe64000)
9405 00:59:36.415593 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9406 00:59:36.421871 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9407 00:59:36.430228 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9408 00:59:36.433324 Checking segment from ROM address 0x40100000
9409 00:59:36.436398 Checking segment from ROM address 0x4010001c
9410 00:59:36.443268 Loading segment from ROM address 0x40100000
9411 00:59:36.443836 code (compression=1)
9412 00:59:36.450167 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9413 00:59:36.460288 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9414 00:59:36.460803 using LZMA
9415 00:59:36.468705 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9416 00:59:36.474644 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9417 00:59:36.478021 Loading segment from ROM address 0x4010001c
9418 00:59:36.478477 Entry Point 0x54601000
9419 00:59:36.481858 Loaded segments
9420 00:59:36.485254 NOTICE: MT8192 bl31_setup
9421 00:59:36.491845 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9422 00:59:36.495984 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9423 00:59:36.498493 WARNING: region 0:
9424 00:59:36.501792 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9425 00:59:36.502304 WARNING: region 1:
9426 00:59:36.508765 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9427 00:59:36.512585 WARNING: region 2:
9428 00:59:36.514712 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9429 00:59:36.518232 WARNING: region 3:
9430 00:59:36.521567 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9431 00:59:36.525032 WARNING: region 4:
9432 00:59:36.531433 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9433 00:59:36.531926 WARNING: region 5:
9434 00:59:36.535295 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 00:59:36.538838 WARNING: region 6:
9436 00:59:36.542207 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 00:59:36.545382 WARNING: region 7:
9438 00:59:36.548833 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 00:59:36.555409 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9440 00:59:36.558476 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9441 00:59:36.561842 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9442 00:59:36.568860 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9443 00:59:36.571786 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9444 00:59:36.575104 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9445 00:59:36.581783 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9446 00:59:36.585143 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9447 00:59:36.591715 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9448 00:59:36.595228 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9449 00:59:36.598427 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9450 00:59:36.605060 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9451 00:59:36.607999 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9452 00:59:36.611058 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9453 00:59:36.618622 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9454 00:59:36.621368 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9455 00:59:36.628016 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9456 00:59:36.631354 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9457 00:59:36.635211 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9458 00:59:36.641353 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9459 00:59:36.644795 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9460 00:59:36.651178 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9461 00:59:36.654418 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9462 00:59:36.657887 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9463 00:59:36.664694 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9464 00:59:36.667886 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9465 00:59:36.674613 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9466 00:59:36.677975 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9467 00:59:36.680861 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9468 00:59:36.687533 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9469 00:59:36.691083 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9470 00:59:36.697616 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9471 00:59:36.701136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9472 00:59:36.704335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9473 00:59:36.707777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9474 00:59:36.714930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9475 00:59:36.717999 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9476 00:59:36.720623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9477 00:59:36.724201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9478 00:59:36.731148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9479 00:59:36.734812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9480 00:59:36.737931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9481 00:59:36.741028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9482 00:59:36.747526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9483 00:59:36.751042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9484 00:59:36.754098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9485 00:59:36.758008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9486 00:59:36.764632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9487 00:59:36.767299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9488 00:59:36.773755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9489 00:59:36.777039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9490 00:59:36.780241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9491 00:59:36.786985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9492 00:59:36.790141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9493 00:59:36.797081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9494 00:59:36.800549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9495 00:59:36.807105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9496 00:59:36.810678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9497 00:59:36.813704 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9498 00:59:36.820031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9499 00:59:36.823635 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9500 00:59:36.830389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9501 00:59:36.833706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9502 00:59:36.840320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9503 00:59:36.843530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9504 00:59:36.850281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9505 00:59:36.853650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9506 00:59:36.856559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9507 00:59:36.863492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9508 00:59:36.866499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9509 00:59:36.874214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9510 00:59:36.876723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9511 00:59:36.882712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9512 00:59:36.886464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9513 00:59:36.892645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9514 00:59:36.896512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9515 00:59:36.899341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9516 00:59:36.906029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9517 00:59:36.910051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9518 00:59:36.916137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9519 00:59:36.919322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9520 00:59:36.925916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9521 00:59:36.929559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9522 00:59:36.935973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9523 00:59:36.939607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9524 00:59:36.943064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9525 00:59:36.950150 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9526 00:59:36.952747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9527 00:59:36.960253 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9528 00:59:36.962669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9529 00:59:36.969235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9530 00:59:36.972848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9531 00:59:36.975905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9532 00:59:36.982928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9533 00:59:36.986218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9534 00:59:36.992415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9535 00:59:36.995919 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9536 00:59:36.999201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9537 00:59:37.006096 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9538 00:59:37.009582 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9539 00:59:37.012901 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9540 00:59:37.015896 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9541 00:59:37.022980 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9542 00:59:37.025533 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9543 00:59:37.032266 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9544 00:59:37.035503 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9545 00:59:37.039029 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9546 00:59:37.045270 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9547 00:59:37.049356 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9548 00:59:37.055664 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9549 00:59:37.058664 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9550 00:59:37.066038 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9551 00:59:37.068714 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9552 00:59:37.072179 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9553 00:59:37.078463 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9554 00:59:37.082128 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9555 00:59:37.085917 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9556 00:59:37.092027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9557 00:59:37.095099 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9558 00:59:37.098376 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9559 00:59:37.102307 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9560 00:59:37.108833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9561 00:59:37.112057 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9562 00:59:37.115440 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9563 00:59:37.122270 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9564 00:59:37.124838 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9565 00:59:37.128350 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9566 00:59:37.135932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9567 00:59:37.138332 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9568 00:59:37.144946 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9569 00:59:37.148732 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9570 00:59:37.151876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9571 00:59:37.158629 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9572 00:59:37.162088 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9573 00:59:37.168381 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9574 00:59:37.172033 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9575 00:59:37.175419 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9576 00:59:37.181767 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9577 00:59:37.185220 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9578 00:59:37.188513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9579 00:59:37.194879 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9580 00:59:37.198533 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9581 00:59:37.204939 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9582 00:59:37.208495 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9583 00:59:37.212227 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9584 00:59:37.218553 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9585 00:59:37.221395 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9586 00:59:37.229139 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9587 00:59:37.231678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9588 00:59:37.234961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9589 00:59:37.241980 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9590 00:59:37.246000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9591 00:59:37.251517 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9592 00:59:37.254648 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9593 00:59:37.258213 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9594 00:59:37.264489 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9595 00:59:37.268428 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9596 00:59:37.274430 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9597 00:59:37.277752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9598 00:59:37.281122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9599 00:59:37.287874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9600 00:59:37.291164 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9601 00:59:37.298247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9602 00:59:37.300838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9603 00:59:37.303798 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9604 00:59:37.310700 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9605 00:59:37.313735 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9606 00:59:37.320200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9607 00:59:37.323740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9608 00:59:37.327115 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9609 00:59:37.333949 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9610 00:59:37.337305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9611 00:59:37.343523 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9612 00:59:37.346658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9613 00:59:37.350447 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9614 00:59:37.356683 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9615 00:59:37.360136 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9616 00:59:37.366673 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9617 00:59:37.369675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9618 00:59:37.373373 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9619 00:59:37.380049 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9620 00:59:37.382959 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9621 00:59:37.389731 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9622 00:59:37.392501 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9623 00:59:37.399333 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9624 00:59:37.402862 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9625 00:59:37.406018 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9626 00:59:37.412266 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9627 00:59:37.415979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9628 00:59:37.422680 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9629 00:59:37.425626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9630 00:59:37.429012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9631 00:59:37.435507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9632 00:59:37.438855 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9633 00:59:37.445114 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9634 00:59:37.448821 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9635 00:59:37.455768 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9636 00:59:37.458248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9637 00:59:37.464702 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9638 00:59:37.468846 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9639 00:59:37.471565 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9640 00:59:37.478998 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9641 00:59:37.481646 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9642 00:59:37.487885 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9643 00:59:37.491632 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9644 00:59:37.498269 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9645 00:59:37.501477 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9646 00:59:37.504649 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9647 00:59:37.511515 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9648 00:59:37.514728 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9649 00:59:37.520985 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9650 00:59:37.524377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9651 00:59:37.531105 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9652 00:59:37.534344 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9653 00:59:37.537565 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9654 00:59:37.544171 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9655 00:59:37.547486 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9656 00:59:37.554273 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9657 00:59:37.557626 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9658 00:59:37.563757 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9659 00:59:37.567208 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9660 00:59:37.570485 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9661 00:59:37.577245 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9662 00:59:37.580186 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9663 00:59:37.586880 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9664 00:59:37.590148 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9665 00:59:37.596492 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9666 00:59:37.599843 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9667 00:59:37.603732 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9668 00:59:37.609734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9669 00:59:37.612978 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9670 00:59:37.616969 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9671 00:59:37.619749 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9672 00:59:37.626191 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9673 00:59:37.630003 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9674 00:59:37.632998 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9675 00:59:37.639631 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9676 00:59:37.642513 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9677 00:59:37.646022 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9678 00:59:37.652441 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9679 00:59:37.656383 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9680 00:59:37.663013 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9681 00:59:37.665913 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9682 00:59:37.669319 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9683 00:59:37.675439 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9684 00:59:37.678663 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9685 00:59:37.682618 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9686 00:59:37.688967 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9687 00:59:37.692750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9688 00:59:37.699247 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9689 00:59:37.702505 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9690 00:59:37.705681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9691 00:59:37.712025 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9692 00:59:37.715795 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9693 00:59:37.718754 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9694 00:59:37.725414 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9695 00:59:37.728749 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9696 00:59:37.735428 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9697 00:59:37.738457 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9698 00:59:37.741685 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9699 00:59:37.748592 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9700 00:59:37.751255 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9701 00:59:37.757820 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9702 00:59:37.761385 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9703 00:59:37.764953 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9704 00:59:37.771332 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9705 00:59:37.774849 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9706 00:59:37.777974 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9707 00:59:37.783983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9708 00:59:37.787214 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9709 00:59:37.790657 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9710 00:59:37.794463 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9711 00:59:37.801017 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9712 00:59:37.803725 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9713 00:59:37.806943 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9714 00:59:37.810939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9715 00:59:37.817513 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9716 00:59:37.820208 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9717 00:59:37.823763 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9718 00:59:37.827239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9719 00:59:37.833612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9720 00:59:37.837225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9721 00:59:37.840402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9722 00:59:37.847102 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9723 00:59:37.850632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9724 00:59:37.856995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9725 00:59:37.860067 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9726 00:59:37.866528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9727 00:59:37.869788 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9728 00:59:37.873122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9729 00:59:37.879762 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9730 00:59:37.882992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9731 00:59:37.889441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9732 00:59:37.893001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9733 00:59:37.899555 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9734 00:59:37.902596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9735 00:59:37.909114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9736 00:59:37.912511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9737 00:59:37.915842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9738 00:59:37.923068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9739 00:59:37.925700 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9740 00:59:37.932171 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9741 00:59:37.935884 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9742 00:59:37.939157 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9743 00:59:37.945608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9744 00:59:37.948894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9745 00:59:37.955417 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9746 00:59:37.958276 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9747 00:59:37.961647 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9748 00:59:37.967990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9749 00:59:37.972361 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9750 00:59:37.978382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9751 00:59:37.981349 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9752 00:59:37.988707 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9753 00:59:37.991437 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9754 00:59:37.995470 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9755 00:59:38.001668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9756 00:59:38.004895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9757 00:59:38.011459 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9758 00:59:38.014246 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9759 00:59:38.020828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9760 00:59:38.023983 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9761 00:59:38.027600 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9762 00:59:38.034375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9763 00:59:38.037294 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9764 00:59:38.044255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9765 00:59:38.047334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9766 00:59:38.054122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9767 00:59:38.057638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9768 00:59:38.060235 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9769 00:59:38.067068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9770 00:59:38.070651 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9771 00:59:38.076763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9772 00:59:38.080108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9773 00:59:38.086591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9774 00:59:38.089837 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9775 00:59:38.093835 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9776 00:59:38.100439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9777 00:59:38.103135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9778 00:59:38.109934 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9779 00:59:38.113203 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9780 00:59:38.116272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9781 00:59:38.123452 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9782 00:59:38.126227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9783 00:59:38.132705 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9784 00:59:38.136129 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9785 00:59:38.143022 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9786 00:59:38.145990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9787 00:59:38.149271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9788 00:59:38.155396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9789 00:59:38.159046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9790 00:59:38.165509 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9791 00:59:38.168860 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9792 00:59:38.172326 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9793 00:59:38.178672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9794 00:59:38.182048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9795 00:59:38.188805 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9796 00:59:38.192095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9797 00:59:38.198622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9798 00:59:38.201616 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9799 00:59:38.208562 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9800 00:59:38.211878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9801 00:59:38.214912 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9802 00:59:38.221564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9803 00:59:38.224869 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9804 00:59:38.231827 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9805 00:59:38.234845 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9806 00:59:38.241857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9807 00:59:38.244707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9808 00:59:38.251590 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9809 00:59:38.254845 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9810 00:59:38.261092 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9811 00:59:38.264225 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9812 00:59:38.267758 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9813 00:59:38.274181 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9814 00:59:38.277272 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9815 00:59:38.283717 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9816 00:59:38.287285 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9817 00:59:38.294270 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9818 00:59:38.298038 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9819 00:59:38.303811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9820 00:59:38.307010 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9821 00:59:38.313458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9822 00:59:38.317167 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9823 00:59:38.320190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9824 00:59:38.326815 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9825 00:59:38.330481 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9826 00:59:38.337374 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9827 00:59:38.340081 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9828 00:59:38.346199 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9829 00:59:38.349541 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9830 00:59:38.356060 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9831 00:59:38.359817 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9832 00:59:38.363194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9833 00:59:38.369686 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9834 00:59:38.373156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9835 00:59:38.379636 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9836 00:59:38.383159 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9837 00:59:38.389638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9838 00:59:38.392504 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9839 00:59:38.399258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9840 00:59:38.402340 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9841 00:59:38.405787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9842 00:59:38.412228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9843 00:59:38.416018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9844 00:59:38.422042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9845 00:59:38.425707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9846 00:59:38.431852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9847 00:59:38.435589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9848 00:59:38.441969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9849 00:59:38.445404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9850 00:59:38.452086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9851 00:59:38.455232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9852 00:59:38.461712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9853 00:59:38.465459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9854 00:59:38.472412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9855 00:59:38.474930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9856 00:59:38.481445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9857 00:59:38.484752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9858 00:59:38.491064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9859 00:59:38.494669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9860 00:59:38.501140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9861 00:59:38.504490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9862 00:59:38.510969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9863 00:59:38.514660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9864 00:59:38.521022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9865 00:59:38.524039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9866 00:59:38.531146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9867 00:59:38.534369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9868 00:59:38.540773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9869 00:59:38.543760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9870 00:59:38.550271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9871 00:59:38.553872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9872 00:59:38.560701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9873 00:59:38.563972 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9874 00:59:38.567027 INFO: [APUAPC] vio 0
9875 00:59:38.570627 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9876 00:59:38.577278 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9877 00:59:38.581009 INFO: [APUAPC] D0_APC_0: 0x400510
9878 00:59:38.581472 INFO: [APUAPC] D0_APC_1: 0x0
9879 00:59:38.583575 INFO: [APUAPC] D0_APC_2: 0x1540
9880 00:59:38.587420 INFO: [APUAPC] D0_APC_3: 0x0
9881 00:59:38.590134 INFO: [APUAPC] D1_APC_0: 0xffffffff
9882 00:59:38.593513 INFO: [APUAPC] D1_APC_1: 0xffffffff
9883 00:59:38.596265 INFO: [APUAPC] D1_APC_2: 0x3fffff
9884 00:59:38.599854 INFO: [APUAPC] D1_APC_3: 0x0
9885 00:59:38.603566 INFO: [APUAPC] D2_APC_0: 0xffffffff
9886 00:59:38.606770 INFO: [APUAPC] D2_APC_1: 0xffffffff
9887 00:59:38.609783 INFO: [APUAPC] D2_APC_2: 0x3fffff
9888 00:59:38.613509 INFO: [APUAPC] D2_APC_3: 0x0
9889 00:59:38.616119 INFO: [APUAPC] D3_APC_0: 0xffffffff
9890 00:59:38.619763 INFO: [APUAPC] D3_APC_1: 0xffffffff
9891 00:59:38.623147 INFO: [APUAPC] D3_APC_2: 0x3fffff
9892 00:59:38.626186 INFO: [APUAPC] D3_APC_3: 0x0
9893 00:59:38.630014 INFO: [APUAPC] D4_APC_0: 0xffffffff
9894 00:59:38.632740 INFO: [APUAPC] D4_APC_1: 0xffffffff
9895 00:59:38.635842 INFO: [APUAPC] D4_APC_2: 0x3fffff
9896 00:59:38.639776 INFO: [APUAPC] D4_APC_3: 0x0
9897 00:59:38.642513 INFO: [APUAPC] D5_APC_0: 0xffffffff
9898 00:59:38.646164 INFO: [APUAPC] D5_APC_1: 0xffffffff
9899 00:59:38.650010 INFO: [APUAPC] D5_APC_2: 0x3fffff
9900 00:59:38.652390 INFO: [APUAPC] D5_APC_3: 0x0
9901 00:59:38.655828 INFO: [APUAPC] D6_APC_0: 0xffffffff
9902 00:59:38.659434 INFO: [APUAPC] D6_APC_1: 0xffffffff
9903 00:59:38.662297 INFO: [APUAPC] D6_APC_2: 0x3fffff
9904 00:59:38.665824 INFO: [APUAPC] D6_APC_3: 0x0
9905 00:59:38.668875 INFO: [APUAPC] D7_APC_0: 0xffffffff
9906 00:59:38.672307 INFO: [APUAPC] D7_APC_1: 0xffffffff
9907 00:59:38.675671 INFO: [APUAPC] D7_APC_2: 0x3fffff
9908 00:59:38.678749 INFO: [APUAPC] D7_APC_3: 0x0
9909 00:59:38.682132 INFO: [APUAPC] D8_APC_0: 0xffffffff
9910 00:59:38.684915 INFO: [APUAPC] D8_APC_1: 0xffffffff
9911 00:59:38.688598 INFO: [APUAPC] D8_APC_2: 0x3fffff
9912 00:59:38.691843 INFO: [APUAPC] D8_APC_3: 0x0
9913 00:59:38.695396 INFO: [APUAPC] D9_APC_0: 0xffffffff
9914 00:59:38.699103 INFO: [APUAPC] D9_APC_1: 0xffffffff
9915 00:59:38.701875 INFO: [APUAPC] D9_APC_2: 0x3fffff
9916 00:59:38.704877 INFO: [APUAPC] D9_APC_3: 0x0
9917 00:59:38.708722 INFO: [APUAPC] D10_APC_0: 0xffffffff
9918 00:59:38.711781 INFO: [APUAPC] D10_APC_1: 0xffffffff
9919 00:59:38.715192 INFO: [APUAPC] D10_APC_2: 0x3fffff
9920 00:59:38.718172 INFO: [APUAPC] D10_APC_3: 0x0
9921 00:59:38.721968 INFO: [APUAPC] D11_APC_0: 0xffffffff
9922 00:59:38.724729 INFO: [APUAPC] D11_APC_1: 0xffffffff
9923 00:59:38.727971 INFO: [APUAPC] D11_APC_2: 0x3fffff
9924 00:59:38.731266 INFO: [APUAPC] D11_APC_3: 0x0
9925 00:59:38.734931 INFO: [APUAPC] D12_APC_0: 0xffffffff
9926 00:59:38.737998 INFO: [APUAPC] D12_APC_1: 0xffffffff
9927 00:59:38.741402 INFO: [APUAPC] D12_APC_2: 0x3fffff
9928 00:59:38.744535 INFO: [APUAPC] D12_APC_3: 0x0
9929 00:59:38.748192 INFO: [APUAPC] D13_APC_0: 0xffffffff
9930 00:59:38.750830 INFO: [APUAPC] D13_APC_1: 0xffffffff
9931 00:59:38.754600 INFO: [APUAPC] D13_APC_2: 0x3fffff
9932 00:59:38.758155 INFO: [APUAPC] D13_APC_3: 0x0
9933 00:59:38.760993 INFO: [APUAPC] D14_APC_0: 0xffffffff
9934 00:59:38.764027 INFO: [APUAPC] D14_APC_1: 0xffffffff
9935 00:59:38.768296 INFO: [APUAPC] D14_APC_2: 0x3fffff
9936 00:59:38.770935 INFO: [APUAPC] D14_APC_3: 0x0
9937 00:59:38.774627 INFO: [APUAPC] D15_APC_0: 0xffffffff
9938 00:59:38.777342 INFO: [APUAPC] D15_APC_1: 0xffffffff
9939 00:59:38.781003 INFO: [APUAPC] D15_APC_2: 0x3fffff
9940 00:59:38.784563 INFO: [APUAPC] D15_APC_3: 0x0
9941 00:59:38.787275 INFO: [APUAPC] APC_CON: 0x4
9942 00:59:38.791159 INFO: [NOCDAPC] D0_APC_0: 0x0
9943 00:59:38.794140 INFO: [NOCDAPC] D0_APC_1: 0x0
9944 00:59:38.797104 INFO: [NOCDAPC] D1_APC_0: 0x0
9945 00:59:38.800227 INFO: [NOCDAPC] D1_APC_1: 0xfff
9946 00:59:38.803689 INFO: [NOCDAPC] D2_APC_0: 0x0
9947 00:59:38.807616 INFO: [NOCDAPC] D2_APC_1: 0xfff
9948 00:59:38.808151 INFO: [NOCDAPC] D3_APC_0: 0x0
9949 00:59:38.810527 INFO: [NOCDAPC] D3_APC_1: 0xfff
9950 00:59:38.814057 INFO: [NOCDAPC] D4_APC_0: 0x0
9951 00:59:38.817061 INFO: [NOCDAPC] D4_APC_1: 0xfff
9952 00:59:38.820887 INFO: [NOCDAPC] D5_APC_0: 0x0
9953 00:59:38.823736 INFO: [NOCDAPC] D5_APC_1: 0xfff
9954 00:59:38.827340 INFO: [NOCDAPC] D6_APC_0: 0x0
9955 00:59:38.830531 INFO: [NOCDAPC] D6_APC_1: 0xfff
9956 00:59:38.833593 INFO: [NOCDAPC] D7_APC_0: 0x0
9957 00:59:38.836724 INFO: [NOCDAPC] D7_APC_1: 0xfff
9958 00:59:38.840470 INFO: [NOCDAPC] D8_APC_0: 0x0
9959 00:59:38.843096 INFO: [NOCDAPC] D8_APC_1: 0xfff
9960 00:59:38.843857 INFO: [NOCDAPC] D9_APC_0: 0x0
9961 00:59:38.846064 INFO: [NOCDAPC] D9_APC_1: 0xfff
9962 00:59:38.850278 INFO: [NOCDAPC] D10_APC_0: 0x0
9963 00:59:38.852969 INFO: [NOCDAPC] D10_APC_1: 0xfff
9964 00:59:38.856458 INFO: [NOCDAPC] D11_APC_0: 0x0
9965 00:59:38.859905 INFO: [NOCDAPC] D11_APC_1: 0xfff
9966 00:59:38.862855 INFO: [NOCDAPC] D12_APC_0: 0x0
9967 00:59:38.866706 INFO: [NOCDAPC] D12_APC_1: 0xfff
9968 00:59:38.869373 INFO: [NOCDAPC] D13_APC_0: 0x0
9969 00:59:38.873236 INFO: [NOCDAPC] D13_APC_1: 0xfff
9970 00:59:38.876070 INFO: [NOCDAPC] D14_APC_0: 0x0
9971 00:59:38.879337 INFO: [NOCDAPC] D14_APC_1: 0xfff
9972 00:59:38.882611 INFO: [NOCDAPC] D15_APC_0: 0x0
9973 00:59:38.886326 INFO: [NOCDAPC] D15_APC_1: 0xfff
9974 00:59:38.889517 INFO: [NOCDAPC] APC_CON: 0x4
9975 00:59:38.892444 INFO: [APUAPC] set_apusys_apc done
9976 00:59:38.895634 INFO: [DEVAPC] devapc_init done
9977 00:59:38.899397 INFO: GICv3 without legacy support detected.
9978 00:59:38.902314 INFO: ARM GICv3 driver initialized in EL3
9979 00:59:38.905932 INFO: Maximum SPI INTID supported: 639
9980 00:59:38.909090 INFO: BL31: Initializing runtime services
9981 00:59:38.916697 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9982 00:59:38.918611 INFO: SPM: enable CPC mode
9983 00:59:38.925551 INFO: mcdi ready for mcusys-off-idle and system suspend
9984 00:59:38.929088 INFO: BL31: Preparing for EL3 exit to normal world
9985 00:59:38.932055 INFO: Entry point address = 0x80000000
9986 00:59:38.935282 INFO: SPSR = 0x8
9987 00:59:38.940397
9988 00:59:38.940962
9989 00:59:38.941320
9990 00:59:38.943006 Starting depthcharge on Spherion...
9991 00:59:38.943484
9992 00:59:38.943845 Wipe memory regions:
9993 00:59:38.944180
9994 00:59:38.946830 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9995 00:59:38.947420 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9996 00:59:38.947870 Setting prompt string to ['asurada:']
9997 00:59:38.948378 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9998 00:59:38.949096 [0x00000040000000, 0x00000054600000)
9999 00:59:39.068728
10000 00:59:39.069287 [0x00000054660000, 0x00000080000000)
10001 00:59:39.329607
10002 00:59:39.330158 [0x000000821a7280, 0x000000ffe64000)
10003 00:59:40.074868
10004 00:59:40.075446 [0x00000100000000, 0x00000240000000)
10005 00:59:41.964454
10006 00:59:41.967241 Initializing XHCI USB controller at 0x11200000.
10007 00:59:43.006967
10008 00:59:43.009653 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10009 00:59:43.010226
10010 00:59:43.010591
10011 00:59:43.010925
10012 00:59:43.011729 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10014 00:59:43.113132 asurada: tftpboot 192.168.201.1 12571095/tftp-deploy-b12l71ur/kernel/image.itb 12571095/tftp-deploy-b12l71ur/kernel/cmdline
10015 00:59:43.113785 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10016 00:59:43.114367 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10017 00:59:43.118936 tftpboot 192.168.201.1 12571095/tftp-deploy-b12l71ur/kernel/image.ittp-deploy-b12l71ur/kernel/cmdline
10018 00:59:43.119557
10019 00:59:43.119969 Waiting for link
10020 00:59:43.279704
10021 00:59:43.280258 R8152: Initializing
10022 00:59:43.280731
10023 00:59:43.282718 Version 6 (ocp_data = 5c30)
10024 00:59:43.283172
10025 00:59:43.286184 R8152: Done initializing
10026 00:59:43.286737
10027 00:59:43.287092 Adding net device
10028 00:59:45.247661
10029 00:59:45.248219 done.
10030 00:59:45.248575
10031 00:59:45.248905 MAC: 00:24:32:30:7c:7b
10032 00:59:45.249221
10033 00:59:45.250884 Sending DHCP discover... done.
10034 00:59:45.251337
10035 00:59:51.623604 Waiting for reply... done.
10036 00:59:51.624154
10037 00:59:51.624516 Sending DHCP request... done.
10038 00:59:51.627065
10039 00:59:51.630965 Waiting for reply... done.
10040 00:59:51.631561
10041 00:59:51.631924 My ip is 192.168.201.14
10042 00:59:51.632261
10043 00:59:51.633927 The DHCP server ip is 192.168.201.1
10044 00:59:51.634344
10045 00:59:51.641125 TFTP server IP predefined by user: 192.168.201.1
10046 00:59:51.641210
10047 00:59:51.646834 Bootfile predefined by user: 12571095/tftp-deploy-b12l71ur/kernel/image.itb
10048 00:59:51.646925
10049 00:59:51.650286 Sending tftp read request... done.
10050 00:59:51.650443
10051 00:59:51.654812 Waiting for the transfer...
10052 00:59:51.654918
10053 00:59:52.320162 00000000 ################################################################
10054 00:59:52.320767
10055 00:59:53.008799 00080000 ################################################################
10056 00:59:53.009311
10057 00:59:53.631531 00100000 ################################################################
10058 00:59:53.632167
10059 00:59:54.325106 00180000 ################################################################
10060 00:59:54.325602
10061 00:59:54.931553 00200000 ################################################################
10062 00:59:54.931691
10063 00:59:55.506880 00280000 ################################################################
10064 00:59:55.507013
10065 00:59:56.061772 00300000 ################################################################
10066 00:59:56.061927
10067 00:59:56.620049 00380000 ################################################################
10068 00:59:56.620240
10069 00:59:57.168406 00400000 ################################################################
10070 00:59:57.168540
10071 00:59:57.725588 00480000 ################################################################
10072 00:59:57.725734
10073 00:59:58.308359 00500000 ################################################################
10074 00:59:58.308501
10075 00:59:58.884399 00580000 ################################################################
10076 00:59:58.884529
10077 00:59:59.461089 00600000 ################################################################
10078 00:59:59.461244
10079 01:00:00.042228 00680000 ################################################################
10080 01:00:00.042364
10081 01:00:00.625829 00700000 ################################################################
10082 01:00:00.626010
10083 01:00:01.205356 00780000 ################################################################
10084 01:00:01.205504
10085 01:00:01.789949 00800000 ################################################################
10086 01:00:01.790100
10087 01:00:02.377379 00880000 ################################################################
10088 01:00:02.377530
10089 01:00:02.948171 00900000 ################################################################
10090 01:00:02.948313
10091 01:00:03.510239 00980000 ################################################################
10092 01:00:03.510396
10093 01:00:04.091276 00a00000 ################################################################
10094 01:00:04.091473
10095 01:00:04.674107 00a80000 ################################################################
10096 01:00:04.674306
10097 01:00:05.256902 00b00000 ################################################################
10098 01:00:05.257059
10099 01:00:05.827399 00b80000 ################################################################
10100 01:00:05.827565
10101 01:00:06.386757 00c00000 ################################################################
10102 01:00:06.386923
10103 01:00:06.934736 00c80000 ################################################################
10104 01:00:06.934910
10105 01:00:07.483025 00d00000 ################################################################
10106 01:00:07.483183
10107 01:00:08.039985 00d80000 ################################################################
10108 01:00:08.040146
10109 01:00:08.578847 00e00000 ################################################################
10110 01:00:08.579000
10111 01:00:09.124639 00e80000 ################################################################
10112 01:00:09.124815
10113 01:00:09.681394 00f00000 ################################################################
10114 01:00:09.681547
10115 01:00:10.221973 00f80000 ################################################################
10116 01:00:10.222126
10117 01:00:10.777952 01000000 ################################################################
10118 01:00:10.778139
10119 01:00:11.335929 01080000 ################################################################
10120 01:00:11.336081
10121 01:00:11.907523 01100000 ################################################################
10122 01:00:11.907693
10123 01:00:12.482838 01180000 ################################################################
10124 01:00:12.482988
10125 01:00:13.047740 01200000 ################################################################
10126 01:00:13.047892
10127 01:00:13.634364 01280000 ################################################################
10128 01:00:13.634519
10129 01:00:14.220459 01300000 ################################################################
10130 01:00:14.220595
10131 01:00:14.805610 01380000 ################################################################
10132 01:00:14.805747
10133 01:00:15.374783 01400000 ################################################################
10134 01:00:15.374924
10135 01:00:15.995719 01480000 ################################################################
10136 01:00:15.996181
10137 01:00:16.659087 01500000 ################################################################
10138 01:00:16.659580
10139 01:00:17.397822 01580000 ################################################################
10140 01:00:17.398341
10141 01:00:18.110664 01600000 ################################################################
10142 01:00:18.111174
10143 01:00:18.819125 01680000 ################################################################
10144 01:00:18.819712
10145 01:00:19.519496 01700000 ################################################################
10146 01:00:19.520043
10147 01:00:20.233098 01780000 ################################################################
10148 01:00:20.233652
10149 01:00:20.951687 01800000 ################################################################
10150 01:00:20.952233
10151 01:00:21.667577 01880000 ################################################################
10152 01:00:21.668070
10153 01:00:22.385220 01900000 ################################################################
10154 01:00:22.385754
10155 01:00:23.091770 01980000 ################################################################
10156 01:00:23.092291
10157 01:00:23.797212 01a00000 ################################################################
10158 01:00:23.797745
10159 01:00:24.528143 01a80000 ################################################################
10160 01:00:24.528673
10161 01:00:25.243249 01b00000 ################################################################
10162 01:00:25.243778
10163 01:00:25.783862 01b80000 ################################################################
10164 01:00:25.784010
10165 01:00:26.334321 01c00000 ################################################################
10166 01:00:26.334480
10167 01:00:26.854938 01c80000 ################################################################
10168 01:00:26.855083
10169 01:00:27.384090 01d00000 ################################################################
10170 01:00:27.384226
10171 01:00:27.910295 01d80000 ################################################################
10172 01:00:27.910427
10173 01:00:28.447945 01e00000 ################################################################
10174 01:00:28.448080
10175 01:00:29.014511 01e80000 ################################################################
10176 01:00:29.014651
10177 01:00:29.549681 01f00000 ################################################################
10178 01:00:29.549843
10179 01:00:30.080824 01f80000 ################################################################
10180 01:00:30.080961
10181 01:00:30.608918 02000000 ################################################################
10182 01:00:30.609054
10183 01:00:31.151118 02080000 ################################################################
10184 01:00:31.151253
10185 01:00:31.686884 02100000 ################################################################
10186 01:00:31.687021
10187 01:00:32.246497 02180000 ################################################################
10188 01:00:32.246630
10189 01:00:32.803009 02200000 ################################################################
10190 01:00:32.803210
10191 01:00:33.355545 02280000 ################################################################
10192 01:00:33.355680
10193 01:00:33.897986 02300000 ################################################################
10194 01:00:33.898152
10195 01:00:34.446011 02380000 ################################################################
10196 01:00:34.446147
10197 01:00:34.983967 02400000 ################################################################
10198 01:00:34.984110
10199 01:00:35.531940 02480000 ################################################################
10200 01:00:35.532082
10201 01:00:36.066479 02500000 ################################################################
10202 01:00:36.066614
10203 01:00:36.589379 02580000 ################################################################
10204 01:00:36.589516
10205 01:00:37.124370 02600000 ################################################################
10206 01:00:37.124504
10207 01:00:37.655577 02680000 ################################################################
10208 01:00:37.655712
10209 01:00:38.175840 02700000 ################################################################
10210 01:00:38.175974
10211 01:00:38.721933 02780000 ################################################################
10212 01:00:38.722065
10213 01:00:39.266369 02800000 ################################################################
10214 01:00:39.266504
10215 01:00:39.792116 02880000 ################################################################
10216 01:00:39.792253
10217 01:00:40.321724 02900000 ################################################################
10218 01:00:40.321858
10219 01:00:40.857724 02980000 ################################################################
10220 01:00:40.857860
10221 01:00:41.384259 02a00000 ################################################################
10222 01:00:41.384394
10223 01:00:41.923555 02a80000 ################################################################
10224 01:00:41.923694
10225 01:00:42.469317 02b00000 ################################################################
10226 01:00:42.469466
10227 01:00:43.012881 02b80000 ################################################################
10228 01:00:43.013027
10229 01:00:43.538998 02c00000 ################################################################
10230 01:00:43.539163
10231 01:00:44.095974 02c80000 ################################################################
10232 01:00:44.096123
10233 01:00:44.648445 02d00000 ################################################################
10234 01:00:44.648591
10235 01:00:45.192415 02d80000 ################################################################
10236 01:00:45.192564
10237 01:00:45.729905 02e00000 ################################################################
10238 01:00:45.730054
10239 01:00:46.252175 02e80000 ################################################################
10240 01:00:46.252320
10241 01:00:46.797936 02f00000 ################################################################
10242 01:00:46.798084
10243 01:00:47.342316 02f80000 ################################################################
10244 01:00:47.342460
10245 01:00:47.869529 03000000 ################################################################
10246 01:00:47.869668
10247 01:00:48.392758 03080000 ################################################################
10248 01:00:48.392898
10249 01:00:48.931090 03100000 ################################################################
10250 01:00:48.931231
10251 01:00:49.470519 03180000 ################################################################
10252 01:00:49.470655
10253 01:00:49.994421 03200000 ################################################################
10254 01:00:49.994557
10255 01:00:50.513913 03280000 ################################################################
10256 01:00:50.514048
10257 01:00:51.039214 03300000 ################################################################
10258 01:00:51.039370
10259 01:00:51.565966 03380000 ################################################################
10260 01:00:51.566135
10261 01:00:52.099781 03400000 ################################################################
10262 01:00:52.099916
10263 01:00:52.628090 03480000 ################################################################
10264 01:00:52.628231
10265 01:00:53.146634 03500000 ################################################################
10266 01:00:53.146781
10267 01:00:53.674226 03580000 ################################################################
10268 01:00:53.674370
10269 01:00:54.201348 03600000 ################################################################
10270 01:00:54.201498
10271 01:00:54.725044 03680000 ################################################################
10272 01:00:54.725190
10273 01:00:55.261984 03700000 ################################################################
10274 01:00:55.262123
10275 01:00:55.794427 03780000 ################################################################
10276 01:00:55.794563
10277 01:00:56.330513 03800000 ################################################################
10278 01:00:56.330650
10279 01:00:56.995336 03880000 ################################################################
10280 01:00:56.995881
10281 01:00:57.715044 03900000 ################################################################
10282 01:00:57.715594
10283 01:00:58.439203 03980000 ################################################################
10284 01:00:58.439739
10285 01:00:59.140758 03a00000 ################################################################
10286 01:00:59.141285
10287 01:00:59.856670 03a80000 ################################################################
10288 01:00:59.857182
10289 01:01:00.576921 03b00000 ################################################################
10290 01:01:00.577460
10291 01:01:01.288598 03b80000 ################################################################
10292 01:01:01.289218
10293 01:01:01.986842 03c00000 ################################################################
10294 01:01:01.987334
10295 01:01:02.699437 03c80000 ################################################################
10296 01:01:02.699922
10297 01:01:03.412078 03d00000 ################################################################
10298 01:01:03.412662
10299 01:01:04.131858 03d80000 ################################################################
10300 01:01:04.132409
10301 01:01:04.839489 03e00000 ################################################################
10302 01:01:04.840003
10303 01:01:05.561937 03e80000 ################################################################
10304 01:01:05.562470
10305 01:01:06.273092 03f00000 ################################################################
10306 01:01:06.273611
10307 01:01:06.995190 03f80000 ################################################################
10308 01:01:06.995728
10309 01:01:07.699141 04000000 ################################################################
10310 01:01:07.699684
10311 01:01:08.423096 04080000 ################################################################
10312 01:01:08.423812
10313 01:01:09.146271 04100000 ################################################################
10314 01:01:09.146794
10315 01:01:09.852988 04180000 ################################################################
10316 01:01:09.853515
10317 01:01:10.575190 04200000 ################################################################
10318 01:01:10.575770
10319 01:01:11.289618 04280000 ################################################################
10320 01:01:11.290126
10321 01:01:11.991634 04300000 ################################################################
10322 01:01:11.992291
10323 01:01:12.694697 04380000 ################################################################
10324 01:01:12.695210
10325 01:01:13.431922 04400000 ################################################################
10326 01:01:13.432428
10327 01:01:14.162168 04480000 ################################################################
10328 01:01:14.162743
10329 01:01:14.879273 04500000 ################################################################
10330 01:01:14.879816
10331 01:01:15.596567 04580000 ################################################################
10332 01:01:15.597140
10333 01:01:16.305156 04600000 ################################################################
10334 01:01:16.305667
10335 01:01:17.014320 04680000 ################################################################
10336 01:01:17.014850
10337 01:01:17.728772 04700000 ################################################################
10338 01:01:17.729266
10339 01:01:18.442497 04780000 ################################################################
10340 01:01:18.443137
10341 01:01:19.148452 04800000 ################################################################
10342 01:01:19.149020
10343 01:01:19.856714 04880000 ################################################################
10344 01:01:19.857271
10345 01:01:20.577576 04900000 ################################################################
10346 01:01:20.578092
10347 01:01:21.259909 04980000 ################################################################
10348 01:01:21.260426
10349 01:01:21.981255 04a00000 ################################################################
10350 01:01:21.981768
10351 01:01:22.673035 04a80000 ################################################################
10352 01:01:22.673554
10353 01:01:23.386927 04b00000 ################################################################
10354 01:01:23.387517
10355 01:01:24.112057 04b80000 ################################################################
10356 01:01:24.112627
10357 01:01:24.848795 04c00000 ################################################################
10358 01:01:24.849351
10359 01:01:25.571325 04c80000 ################################################################
10360 01:01:25.571941
10361 01:01:26.317720 04d00000 ################################################################
10362 01:01:26.318284
10363 01:01:27.029650 04d80000 ################################################################
10364 01:01:27.030181
10365 01:01:27.748610 04e00000 ################################################################
10366 01:01:27.749160
10367 01:01:28.463224 04e80000 ################################################################
10368 01:01:28.463789
10369 01:01:29.183262 04f00000 ################################################################
10370 01:01:29.183936
10371 01:01:29.898378 04f80000 ################################################################
10372 01:01:29.898929
10373 01:01:30.597162 05000000 ################################################################
10374 01:01:30.597714
10375 01:01:31.308153 05080000 ################################################################
10376 01:01:31.308699
10377 01:01:32.022309 05100000 ################################################################
10378 01:01:32.022853
10379 01:01:32.748536 05180000 ################################################################
10380 01:01:32.749116
10381 01:01:33.459160 05200000 ################################################################
10382 01:01:33.459764
10383 01:01:34.167690 05280000 ################################################################
10384 01:01:34.168203
10385 01:01:34.886657 05300000 ################################################################
10386 01:01:34.887209
10387 01:01:35.605389 05380000 ################################################################
10388 01:01:35.605908
10389 01:01:36.319445 05400000 ################################################################
10390 01:01:36.319958
10391 01:01:37.034833 05480000 ################################################################
10392 01:01:37.035562
10393 01:01:37.753737 05500000 ################################################################
10394 01:01:37.754389
10395 01:01:38.487090 05580000 ################################################################
10396 01:01:38.487693
10397 01:01:39.202694 05600000 ################################################################
10398 01:01:39.203223
10399 01:01:39.923604 05680000 ################################################################
10400 01:01:39.924117
10401 01:01:40.643676 05700000 ################################################################
10402 01:01:40.644197
10403 01:01:41.356884 05780000 ################################################################
10404 01:01:41.357403
10405 01:01:42.075102 05800000 ################################################################
10406 01:01:42.075672
10407 01:01:42.795762 05880000 ################################################################
10408 01:01:42.796343
10409 01:01:43.513863 05900000 ################################################################
10410 01:01:43.514433
10411 01:01:44.232502 05980000 ################################################################
10412 01:01:44.233038
10413 01:01:44.952244 05a00000 ################################################################
10414 01:01:44.952930
10415 01:01:45.676176 05a80000 ################################################################
10416 01:01:45.676730
10417 01:01:46.392201 05b00000 ################################################################
10418 01:01:46.392725
10419 01:01:47.098330 05b80000 ################################################################
10420 01:01:47.098844
10421 01:01:47.805601 05c00000 ################################################################
10422 01:01:47.806126
10423 01:01:48.526106 05c80000 ################################################################
10424 01:01:48.526615
10425 01:01:49.254076 05d00000 ################################################################
10426 01:01:49.254611
10427 01:01:49.964694 05d80000 ################################################################
10428 01:01:49.965233
10429 01:01:50.686673 05e00000 ################################################################
10430 01:01:50.687182
10431 01:01:51.413699 05e80000 ################################################################
10432 01:01:51.414202
10433 01:01:52.136764 05f00000 ################################################################
10434 01:01:52.137291
10435 01:01:52.861660 05f80000 ################################################################
10436 01:01:52.862192
10437 01:01:53.595740 06000000 ################################################################
10438 01:01:53.596262
10439 01:01:54.324244 06080000 ################################################################
10440 01:01:54.324754
10441 01:01:55.050097 06100000 ################################################################
10442 01:01:55.050629
10443 01:01:55.782310 06180000 ################################################################
10444 01:01:55.782827
10445 01:01:56.503853 06200000 ################################################################
10446 01:01:56.504433
10447 01:01:57.229765 06280000 ################################################################
10448 01:01:57.230268
10449 01:01:57.955264 06300000 ################################################################
10450 01:01:57.956019
10451 01:01:58.674873 06380000 ################################################################
10452 01:01:58.675430
10453 01:01:59.399444 06400000 ################################################################
10454 01:01:59.399948
10455 01:02:00.098720 06480000 ################################################################
10456 01:02:00.099232
10457 01:02:00.819419 06500000 ################################################################
10458 01:02:00.819937
10459 01:02:01.536553 06580000 ################################################################
10460 01:02:01.537270
10461 01:02:02.260785 06600000 ################################################################
10462 01:02:02.261329
10463 01:02:02.978157 06680000 ################################################################
10464 01:02:02.978663
10465 01:02:03.698083 06700000 ################################################################
10466 01:02:03.698597
10467 01:02:04.407736 06780000 ################################################################
10468 01:02:04.408243
10469 01:02:05.095186 06800000 ################################################################
10470 01:02:05.095745
10471 01:02:05.826859 06880000 ################################################################
10472 01:02:05.827440
10473 01:02:06.274799 06900000 ########################################## done.
10474 01:02:06.275348
10475 01:02:06.277808 The bootfile was 110439394 bytes long.
10476 01:02:06.278227
10477 01:02:06.280512 Sending tftp read request... done.
10478 01:02:06.280927
10479 01:02:06.284740 Waiting for the transfer...
10480 01:02:06.285154
10481 01:02:06.285481 00000000 # done.
10482 01:02:06.285792
10483 01:02:06.291183 Command line loaded dynamically from TFTP file: 12571095/tftp-deploy-b12l71ur/kernel/cmdline
10484 01:02:06.294532
10485 01:02:06.308080 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10486 01:02:06.308606
10487 01:02:06.308933 Loading FIT.
10488 01:02:06.309238
10489 01:02:06.311022 Image ramdisk-1 has 98341459 bytes.
10490 01:02:06.311472
10491 01:02:06.314358 Image fdt-1 has 47278 bytes.
10492 01:02:06.314864
10493 01:02:06.317563 Image kernel-1 has 12048624 bytes.
10494 01:02:06.317982
10495 01:02:06.324949 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10496 01:02:06.325466
10497 01:02:06.343973 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10498 01:02:06.344495
10499 01:02:06.347325 Choosing best match conf-1 for compat google,spherion-rev2.
10500 01:02:06.352223
10501 01:02:06.357074 Connected to device vid:did:rid of 1ae0:0028:00
10502 01:02:06.364969
10503 01:02:06.368228 tpm_get_response: command 0x17b, return code 0x0
10504 01:02:06.368659
10505 01:02:06.371732 ec_init: CrosEC protocol v3 supported (256, 248)
10506 01:02:06.375810
10507 01:02:06.379149 tpm_cleanup: add release locality here.
10508 01:02:06.379607
10509 01:02:06.379949 Shutting down all USB controllers.
10510 01:02:06.382341
10511 01:02:06.382754 Removing current net device
10512 01:02:06.383082
10513 01:02:06.389170 Exiting depthcharge with code 4 at timestamp: 176679832
10514 01:02:06.389690
10515 01:02:06.393240 LZMA decompressing kernel-1 to 0x821a6718
10516 01:02:06.393762
10517 01:02:06.395351 LZMA decompressing kernel-1 to 0x40000000
10518 01:02:07.895476
10519 01:02:07.896035 jumping to kernel
10520 01:02:07.898348 end: 2.2.4 bootloader-commands (duration 00:02:29) [common]
10521 01:02:07.898862 start: 2.2.5 auto-login-action (timeout 00:01:56) [common]
10522 01:02:07.899266 Setting prompt string to ['Linux version [0-9]']
10523 01:02:07.899677 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10524 01:02:07.900057 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10525 01:02:07.977285
10526 01:02:07.980376 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10527 01:02:07.983759 start: 2.2.5.1 login-action (timeout 00:01:56) [common]
10528 01:02:07.984342 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10529 01:02:07.984741 Setting prompt string to []
10530 01:02:07.985165 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10531 01:02:07.985549 Using line separator: #'\n'#
10532 01:02:07.985878 No login prompt set.
10533 01:02:07.986215 Parsing kernel messages
10534 01:02:07.986521 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10535 01:02:07.987069 [login-action] Waiting for messages, (timeout 00:01:56)
10536 01:02:08.004141 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10537 01:02:08.006777 [ 0.000000] random: crng init done
10538 01:02:08.012600 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10539 01:02:08.016172 [ 0.000000] efi: UEFI not found.
10540 01:02:08.022796 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10541 01:02:08.032699 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10542 01:02:08.040244 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10543 01:02:08.049606 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10544 01:02:08.056303 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10545 01:02:08.062550 [ 0.000000] printk: bootconsole [mtk8250] enabled
10546 01:02:08.069272 [ 0.000000] NUMA: No NUMA configuration found
10547 01:02:08.075676 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10548 01:02:08.082371 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10549 01:02:08.082938 [ 0.000000] Zone ranges:
10550 01:02:08.089694 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10551 01:02:08.092273 [ 0.000000] DMA32 empty
10552 01:02:08.098976 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10553 01:02:08.103190 [ 0.000000] Movable zone start for each node
10554 01:02:08.105234 [ 0.000000] Early memory node ranges
10555 01:02:08.112130 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10556 01:02:08.119149 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10557 01:02:08.125161 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10558 01:02:08.131446 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10559 01:02:08.138718 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10560 01:02:08.145066 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10561 01:02:08.201496 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10562 01:02:08.208065 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10563 01:02:08.214477 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10564 01:02:08.218110 [ 0.000000] psci: probing for conduit method from DT.
10565 01:02:08.225643 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10566 01:02:08.227514 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10567 01:02:08.234167 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10568 01:02:08.237579 [ 0.000000] psci: SMC Calling Convention v1.2
10569 01:02:08.244120 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10570 01:02:08.247550 [ 0.000000] Detected VIPT I-cache on CPU0
10571 01:02:08.254181 [ 0.000000] CPU features: detected: GIC system register CPU interface
10572 01:02:08.260994 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10573 01:02:08.266850 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10574 01:02:08.273800 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10575 01:02:08.283724 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10576 01:02:08.290283 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10577 01:02:08.294161 [ 0.000000] alternatives: applying boot alternatives
10578 01:02:08.300330 [ 0.000000] Fallback order for Node 0: 0
10579 01:02:08.307331 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10580 01:02:08.310393 [ 0.000000] Policy zone: Normal
10581 01:02:08.323665 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10582 01:02:08.332993 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10583 01:02:08.345666 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10584 01:02:08.355885 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10585 01:02:08.361954 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10586 01:02:08.365500 <6>[ 0.000000] software IO TLB: area num 8.
10587 01:02:08.422286 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10588 01:02:08.571189 <6>[ 0.000000] Memory: 7871220K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 481548K reserved, 32768K cma-reserved)
10589 01:02:08.578230 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10590 01:02:08.585039 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10591 01:02:08.587939 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10592 01:02:08.594879 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10593 01:02:08.602398 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10594 01:02:08.604755 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10595 01:02:08.614229 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10596 01:02:08.620710 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10597 01:02:08.627765 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10598 01:02:08.634068 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10599 01:02:08.636883 <6>[ 0.000000] GICv3: 608 SPIs implemented
10600 01:02:08.640197 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10601 01:02:08.647054 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10602 01:02:08.650594 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10603 01:02:08.656836 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10604 01:02:08.670598 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10605 01:02:08.684015 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10606 01:02:08.690273 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10607 01:02:08.698464 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10608 01:02:08.711535 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10609 01:02:08.717935 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10610 01:02:08.724131 <6>[ 0.009189] Console: colour dummy device 80x25
10611 01:02:08.734874 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10612 01:02:08.741134 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10613 01:02:08.744350 <6>[ 0.029219] LSM: Security Framework initializing
10614 01:02:08.751115 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10615 01:02:08.760115 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10616 01:02:08.770333 <6>[ 0.051417] cblist_init_generic: Setting adjustable number of callback queues.
10617 01:02:08.776860 <6>[ 0.058858] cblist_init_generic: Setting shift to 3 and lim to 1.
10618 01:02:08.783421 <6>[ 0.065196] cblist_init_generic: Setting adjustable number of callback queues.
10619 01:02:08.790664 <6>[ 0.072669] cblist_init_generic: Setting shift to 3 and lim to 1.
10620 01:02:08.793716 <6>[ 0.079071] rcu: Hierarchical SRCU implementation.
10621 01:02:08.800583 <6>[ 0.084087] rcu: Max phase no-delay instances is 1000.
10622 01:02:08.806921 <6>[ 0.091104] EFI services will not be available.
10623 01:02:08.809938 <6>[ 0.096087] smp: Bringing up secondary CPUs ...
10624 01:02:08.818853 <6>[ 0.101134] Detected VIPT I-cache on CPU1
10625 01:02:08.824971 <6>[ 0.101203] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10626 01:02:08.831994 <6>[ 0.101233] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10627 01:02:08.834993 <6>[ 0.101571] Detected VIPT I-cache on CPU2
10628 01:02:08.845132 <6>[ 0.101621] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10629 01:02:08.851598 <6>[ 0.101638] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10630 01:02:08.855225 <6>[ 0.101892] Detected VIPT I-cache on CPU3
10631 01:02:08.861088 <6>[ 0.101939] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10632 01:02:08.868181 <6>[ 0.101953] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10633 01:02:08.874201 <6>[ 0.102259] CPU features: detected: Spectre-v4
10634 01:02:08.877693 <6>[ 0.102266] CPU features: detected: Spectre-BHB
10635 01:02:08.881236 <6>[ 0.102271] Detected PIPT I-cache on CPU4
10636 01:02:08.888919 <6>[ 0.102327] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10637 01:02:08.897562 <6>[ 0.102343] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10638 01:02:08.900453 <6>[ 0.102634] Detected PIPT I-cache on CPU5
10639 01:02:08.907312 <6>[ 0.102697] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10640 01:02:08.913927 <6>[ 0.102714] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10641 01:02:08.917076 <6>[ 0.102995] Detected PIPT I-cache on CPU6
10642 01:02:08.927218 <6>[ 0.103060] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10643 01:02:08.933725 <6>[ 0.103078] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10644 01:02:08.937152 <6>[ 0.103375] Detected PIPT I-cache on CPU7
10645 01:02:08.944308 <6>[ 0.103439] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10646 01:02:08.950994 <6>[ 0.103455] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10647 01:02:08.953945 <6>[ 0.103504] smp: Brought up 1 node, 8 CPUs
10648 01:02:08.960070 <6>[ 0.244731] SMP: Total of 8 processors activated.
10649 01:02:08.966191 <6>[ 0.249652] CPU features: detected: 32-bit EL0 Support
10650 01:02:08.972833 <6>[ 0.255015] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10651 01:02:08.979415 <6>[ 0.263815] CPU features: detected: Common not Private translations
10652 01:02:08.985867 <6>[ 0.270291] CPU features: detected: CRC32 instructions
10653 01:02:08.992988 <6>[ 0.275675] CPU features: detected: RCpc load-acquire (LDAPR)
10654 01:02:08.996775 <6>[ 0.281635] CPU features: detected: LSE atomic instructions
10655 01:02:09.002883 <6>[ 0.287416] CPU features: detected: Privileged Access Never
10656 01:02:09.009482 <6>[ 0.293196] CPU features: detected: RAS Extension Support
10657 01:02:09.015636 <6>[ 0.298805] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10658 01:02:09.019295 <6>[ 0.306024] CPU: All CPU(s) started at EL2
10659 01:02:09.025836 <6>[ 0.310340] alternatives: applying system-wide alternatives
10660 01:02:09.036725 <6>[ 0.321089] devtmpfs: initialized
10661 01:02:09.051965 <6>[ 0.330061] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10662 01:02:09.058242 <6>[ 0.340023] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10663 01:02:09.065267 <6>[ 0.348277] pinctrl core: initialized pinctrl subsystem
10664 01:02:09.068094 <6>[ 0.354927] DMI not present or invalid.
10665 01:02:09.074839 <6>[ 0.359342] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10666 01:02:09.084730 <6>[ 0.366128] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10667 01:02:09.091936 <6>[ 0.373709] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10668 01:02:09.101407 <6>[ 0.381939] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10669 01:02:09.104613 <6>[ 0.390181] audit: initializing netlink subsys (disabled)
10670 01:02:09.114860 <5>[ 0.395871] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10671 01:02:09.121822 <6>[ 0.396569] thermal_sys: Registered thermal governor 'step_wise'
10672 01:02:09.127815 <6>[ 0.403837] thermal_sys: Registered thermal governor 'power_allocator'
10673 01:02:09.131271 <6>[ 0.410091] cpuidle: using governor menu
10674 01:02:09.137805 <6>[ 0.421054] NET: Registered PF_QIPCRTR protocol family
10675 01:02:09.144102 <6>[ 0.426529] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10676 01:02:09.151133 <6>[ 0.433635] ASID allocator initialised with 32768 entries
10677 01:02:09.154112 <6>[ 0.440197] Serial: AMBA PL011 UART driver
10678 01:02:09.163903 <4>[ 0.448931] Trying to register duplicate clock ID: 134
10679 01:02:09.218132 <6>[ 0.506234] KASLR enabled
10680 01:02:09.233248 <6>[ 0.513961] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10681 01:02:09.238740 <6>[ 0.520978] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10682 01:02:09.245160 <6>[ 0.527468] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10683 01:02:09.252186 <6>[ 0.534474] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10684 01:02:09.258489 <6>[ 0.540963] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10685 01:02:09.265075 <6>[ 0.547965] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10686 01:02:09.271844 <6>[ 0.554450] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10687 01:02:09.279543 <6>[ 0.561452] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10688 01:02:09.281600 <6>[ 0.568915] ACPI: Interpreter disabled.
10689 01:02:09.290288 <6>[ 0.575349] iommu: Default domain type: Translated
10690 01:02:09.297641 <6>[ 0.580463] iommu: DMA domain TLB invalidation policy: strict mode
10691 01:02:09.300545 <5>[ 0.587122] SCSI subsystem initialized
10692 01:02:09.307316 <6>[ 0.591369] usbcore: registered new interface driver usbfs
10693 01:02:09.313428 <6>[ 0.597098] usbcore: registered new interface driver hub
10694 01:02:09.316988 <6>[ 0.602653] usbcore: registered new device driver usb
10695 01:02:09.324321 <6>[ 0.608767] pps_core: LinuxPPS API ver. 1 registered
10696 01:02:09.334103 <6>[ 0.613960] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10697 01:02:09.337242 <6>[ 0.623303] PTP clock support registered
10698 01:02:09.340441 <6>[ 0.627546] EDAC MC: Ver: 3.0.0
10699 01:02:09.347988 <6>[ 0.632739] FPGA manager framework
10700 01:02:09.354935 <6>[ 0.636416] Advanced Linux Sound Architecture Driver Initialized.
10701 01:02:09.358028 <6>[ 0.643179] vgaarb: loaded
10702 01:02:09.364360 <6>[ 0.646318] clocksource: Switched to clocksource arch_sys_counter
10703 01:02:09.367449 <5>[ 0.652766] VFS: Disk quotas dquot_6.6.0
10704 01:02:09.374017 <6>[ 0.656953] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10705 01:02:09.377537 <6>[ 0.664144] pnp: PnP ACPI: disabled
10706 01:02:09.386134 <6>[ 0.670891] NET: Registered PF_INET protocol family
10707 01:02:09.395572 <6>[ 0.676474] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10708 01:02:09.407770 <6>[ 0.688782] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10709 01:02:09.417243 <6>[ 0.697597] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10710 01:02:09.424024 <6>[ 0.705567] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10711 01:02:09.433483 <6>[ 0.714268] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10712 01:02:09.440263 <6>[ 0.724009] TCP: Hash tables configured (established 65536 bind 65536)
10713 01:02:09.447032 <6>[ 0.730871] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10714 01:02:09.456946 <6>[ 0.738069] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10715 01:02:09.463126 <6>[ 0.745777] NET: Registered PF_UNIX/PF_LOCAL protocol family
10716 01:02:09.467013 <6>[ 0.751946] RPC: Registered named UNIX socket transport module.
10717 01:02:09.474330 <6>[ 0.758098] RPC: Registered udp transport module.
10718 01:02:09.476481 <6>[ 0.763029] RPC: Registered tcp transport module.
10719 01:02:09.486501 <6>[ 0.767962] RPC: Registered tcp NFSv4.1 backchannel transport module.
10720 01:02:09.489392 <6>[ 0.774628] PCI: CLS 0 bytes, default 64
10721 01:02:09.494488 <6>[ 0.779030] Unpacking initramfs...
10722 01:02:09.516758 <6>[ 0.798467] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10723 01:02:09.527068 <6>[ 0.807137] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10724 01:02:09.530695 <6>[ 0.815991] kvm [1]: IPA Size Limit: 40 bits
10725 01:02:09.536778 <6>[ 0.820519] kvm [1]: GICv3: no GICV resource entry
10726 01:02:09.540176 <6>[ 0.825542] kvm [1]: disabling GICv2 emulation
10727 01:02:09.546673 <6>[ 0.830225] kvm [1]: GIC system register CPU interface enabled
10728 01:02:09.551185 <6>[ 0.836400] kvm [1]: vgic interrupt IRQ18
10729 01:02:09.557174 <6>[ 0.840773] kvm [1]: VHE mode initialized successfully
10730 01:02:09.563510 <5>[ 0.847283] Initialise system trusted keyrings
10731 01:02:09.569937 <6>[ 0.852062] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10732 01:02:09.577453 <6>[ 0.862082] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10733 01:02:09.583819 <5>[ 0.868456] NFS: Registering the id_resolver key type
10734 01:02:09.587064 <5>[ 0.873754] Key type id_resolver registered
10735 01:02:09.593943 <5>[ 0.878171] Key type id_legacy registered
10736 01:02:09.600556 <6>[ 0.882457] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10737 01:02:09.607129 <6>[ 0.889377] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10738 01:02:09.613622 <6>[ 0.897072] 9p: Installing v9fs 9p2000 file system support
10739 01:02:09.650352 <5>[ 0.934585] Key type asymmetric registered
10740 01:02:09.652782 <5>[ 0.938917] Asymmetric key parser 'x509' registered
10741 01:02:09.662850 <6>[ 0.944087] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10742 01:02:09.666920 <6>[ 0.951703] io scheduler mq-deadline registered
10743 01:02:09.669747 <6>[ 0.956471] io scheduler kyber registered
10744 01:02:09.688379 <6>[ 0.973431] EINJ: ACPI disabled.
10745 01:02:09.720556 <4>[ 0.998853] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10746 01:02:09.730671 <4>[ 1.009484] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10747 01:02:09.744833 <6>[ 1.030007] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10748 01:02:09.752614 <6>[ 1.037918] printk: console [ttyS0] disabled
10749 01:02:09.780916 <6>[ 1.062568] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10750 01:02:09.787520 <6>[ 1.072037] printk: console [ttyS0] enabled
10751 01:02:09.790744 <6>[ 1.072037] printk: console [ttyS0] enabled
10752 01:02:09.797619 <6>[ 1.080933] printk: bootconsole [mtk8250] disabled
10753 01:02:09.800808 <6>[ 1.080933] printk: bootconsole [mtk8250] disabled
10754 01:02:09.807683 <6>[ 1.091999] SuperH (H)SCI(F) driver initialized
10755 01:02:09.810822 <6>[ 1.097278] msm_serial: driver initialized
10756 01:02:09.824609 <6>[ 1.106199] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10757 01:02:09.834739 <6>[ 1.114747] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10758 01:02:09.841506 <6>[ 1.123289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10759 01:02:09.851322 <6>[ 1.131918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10760 01:02:09.861127 <6>[ 1.140628] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10761 01:02:09.867281 <6>[ 1.149342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10762 01:02:09.877782 <6>[ 1.157882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10763 01:02:09.883722 <6>[ 1.166680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10764 01:02:09.894347 <6>[ 1.175222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10765 01:02:09.906066 <6>[ 1.190752] loop: module loaded
10766 01:02:09.912246 <6>[ 1.196558] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10767 01:02:09.934482 <4>[ 1.219615] mtk-pmic-keys: Failed to locate of_node [id: -1]
10768 01:02:09.941243 <6>[ 1.226401] megasas: 07.719.03.00-rc1
10769 01:02:09.951442 <6>[ 1.236096] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10770 01:02:09.960725 <6>[ 1.245701] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10771 01:02:09.977460 <6>[ 1.262415] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10772 01:02:10.034931 <6>[ 1.312290] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10773 01:02:13.495160 <6>[ 4.779988] Freeing initrd memory: 96032K
10774 01:02:13.505370 <6>[ 4.790237] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10775 01:02:13.515480 <6>[ 4.801200] tun: Universal TUN/TAP device driver, 1.6
10776 01:02:13.518583 <6>[ 4.807263] thunder_xcv, ver 1.0
10777 01:02:13.522053 <6>[ 4.810772] thunder_bgx, ver 1.0
10778 01:02:13.525537 <6>[ 4.814263] nicpf, ver 1.0
10779 01:02:13.535924 <6>[ 4.818286] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10780 01:02:13.539380 <6>[ 4.825763] hns3: Copyright (c) 2017 Huawei Corporation.
10781 01:02:13.546023 <6>[ 4.831350] hclge is initializing
10782 01:02:13.549505 <6>[ 4.834925] e1000: Intel(R) PRO/1000 Network Driver
10783 01:02:13.555858 <6>[ 4.840055] e1000: Copyright (c) 1999-2006 Intel Corporation.
10784 01:02:13.559827 <6>[ 4.846066] e1000e: Intel(R) PRO/1000 Network Driver
10785 01:02:13.566532 <6>[ 4.851281] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10786 01:02:13.572600 <6>[ 4.857466] igb: Intel(R) Gigabit Ethernet Network Driver
10787 01:02:13.579979 <6>[ 4.863116] igb: Copyright (c) 2007-2014 Intel Corporation.
10788 01:02:13.585503 <6>[ 4.868959] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10789 01:02:13.592880 <6>[ 4.875477] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10790 01:02:13.595801 <6>[ 4.881937] sky2: driver version 1.30
10791 01:02:13.602169 <6>[ 4.886939] VFIO - User Level meta-driver version: 0.3
10792 01:02:13.609955 <6>[ 4.895195] usbcore: registered new interface driver usb-storage
10793 01:02:13.616598 <6>[ 4.901657] usbcore: registered new device driver onboard-usb-hub
10794 01:02:13.625732 <6>[ 4.910845] mt6397-rtc mt6359-rtc: registered as rtc0
10795 01:02:13.635916 <6>[ 4.916314] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:02:13 UTC (1705626133)
10796 01:02:13.639060 <6>[ 4.925879] i2c_dev: i2c /dev entries driver
10797 01:02:13.655936 <6>[ 4.937623] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10798 01:02:13.675796 <6>[ 4.960613] cpu cpu0: EM: created perf domain
10799 01:02:13.678833 <6>[ 4.965554] cpu cpu4: EM: created perf domain
10800 01:02:13.686461 <6>[ 4.971179] sdhci: Secure Digital Host Controller Interface driver
10801 01:02:13.692395 <6>[ 4.977611] sdhci: Copyright(c) Pierre Ossman
10802 01:02:13.699178 <6>[ 4.982557] Synopsys Designware Multimedia Card Interface Driver
10803 01:02:13.705575 <6>[ 4.989191] sdhci-pltfm: SDHCI platform and OF driver helper
10804 01:02:13.709465 <6>[ 4.989232] mmc0: CQHCI version 5.10
10805 01:02:13.716078 <6>[ 4.999518] ledtrig-cpu: registered to indicate activity on CPUs
10806 01:02:13.722272 <6>[ 5.006548] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10807 01:02:13.728695 <6>[ 5.013606] usbcore: registered new interface driver usbhid
10808 01:02:13.732305 <6>[ 5.019427] usbhid: USB HID core driver
10809 01:02:13.738778 <6>[ 5.023637] spi_master spi0: will run message pump with realtime priority
10810 01:02:13.783721 <6>[ 5.062046] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10811 01:02:13.802406 <6>[ 5.077979] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10812 01:02:13.805787 <6>[ 5.091526] mmc0: Command Queue Engine enabled
10813 01:02:13.812801 <6>[ 5.096283] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10814 01:02:13.819412 <6>[ 5.103986] mmcblk0: mmc0:0001 DA4128 116 GiB
10815 01:02:13.822713 <6>[ 5.108812] cros-ec-spi spi0.0: Chrome EC device registered
10816 01:02:13.829929 <6>[ 5.112679] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10817 01:02:13.836943 <6>[ 5.122269] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10818 01:02:13.844594 <6>[ 5.128248] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10819 01:02:13.850294 <6>[ 5.134107] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10820 01:02:13.867746 <6>[ 5.149912] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10821 01:02:13.875570 <6>[ 5.160561] NET: Registered PF_PACKET protocol family
10822 01:02:13.878749 <6>[ 5.165966] 9pnet: Installing 9P2000 support
10823 01:02:13.885109 <5>[ 5.170532] Key type dns_resolver registered
10824 01:02:13.888775 <6>[ 5.175476] registered taskstats version 1
10825 01:02:13.895075 <5>[ 5.179865] Loading compiled-in X.509 certificates
10826 01:02:13.926717 <4>[ 5.204861] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10827 01:02:13.936384 <4>[ 5.215665] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10828 01:02:13.942821 <3>[ 5.226207] debugfs: File 'uA_load' in directory '/' already present!
10829 01:02:13.949697 <3>[ 5.232909] debugfs: File 'min_uV' in directory '/' already present!
10830 01:02:13.955846 <3>[ 5.239520] debugfs: File 'max_uV' in directory '/' already present!
10831 01:02:13.962540 <3>[ 5.246128] debugfs: File 'constraint_flags' in directory '/' already present!
10832 01:02:13.974754 <3>[ 5.256242] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10833 01:02:13.986663 <6>[ 5.271983] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10834 01:02:13.993464 <6>[ 5.278854] xhci-mtk 11200000.usb: xHCI Host Controller
10835 01:02:14.000138 <6>[ 5.284378] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10836 01:02:14.010208 <6>[ 5.292327] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10837 01:02:14.016681 <6>[ 5.301760] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10838 01:02:14.023617 <6>[ 5.307837] xhci-mtk 11200000.usb: xHCI Host Controller
10839 01:02:14.030121 <6>[ 5.313316] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10840 01:02:14.036339 <6>[ 5.320972] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10841 01:02:14.043457 <6>[ 5.328788] hub 1-0:1.0: USB hub found
10842 01:02:14.046943 <6>[ 5.332813] hub 1-0:1.0: 1 port detected
10843 01:02:14.056587 <6>[ 5.337091] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10844 01:02:14.059545 <6>[ 5.345790] hub 2-0:1.0: USB hub found
10845 01:02:14.063767 <6>[ 5.349810] hub 2-0:1.0: 1 port detected
10846 01:02:14.071632 <6>[ 5.356699] mtk-msdc 11f70000.mmc: Got CD GPIO
10847 01:02:14.084099 <6>[ 5.365645] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10848 01:02:14.089921 <6>[ 5.373677] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10849 01:02:14.100045 <4>[ 5.381582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10850 01:02:14.110127 <6>[ 5.391107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10851 01:02:14.116353 <6>[ 5.399184] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10852 01:02:14.123556 <6>[ 5.407230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10853 01:02:14.133511 <6>[ 5.415143] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10854 01:02:14.139593 <6>[ 5.422966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10855 01:02:14.149786 <6>[ 5.430783] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10856 01:02:14.159335 <6>[ 5.441169] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10857 01:02:14.165958 <6>[ 5.449529] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10858 01:02:14.176275 <6>[ 5.457880] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10859 01:02:14.182776 <6>[ 5.466218] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10860 01:02:14.193311 <6>[ 5.474567] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10861 01:02:14.203212 <6>[ 5.482907] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10862 01:02:14.209223 <6>[ 5.491246] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10863 01:02:14.219308 <6>[ 5.499584] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10864 01:02:14.225472 <6>[ 5.507923] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10865 01:02:14.235734 <6>[ 5.516261] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10866 01:02:14.242369 <6>[ 5.524599] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10867 01:02:14.252069 <6>[ 5.532938] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10868 01:02:14.258515 <6>[ 5.541276] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10869 01:02:14.269384 <6>[ 5.549624] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10870 01:02:14.274790 <6>[ 5.557964] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10871 01:02:14.281510 <6>[ 5.566705] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10872 01:02:14.288291 <6>[ 5.573863] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10873 01:02:14.295238 <6>[ 5.580616] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10874 01:02:14.304975 <6>[ 5.587374] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10875 01:02:14.311769 <6>[ 5.594303] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10876 01:02:14.318789 <6>[ 5.601164] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10877 01:02:14.328204 <6>[ 5.610297] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10878 01:02:14.338368 <6>[ 5.619416] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10879 01:02:14.348111 <6>[ 5.628710] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10880 01:02:14.358200 <6>[ 5.638177] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10881 01:02:14.365008 <6>[ 5.647642] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10882 01:02:14.374447 <6>[ 5.656760] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10883 01:02:14.384495 <6>[ 5.666226] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10884 01:02:14.394355 <6>[ 5.675344] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10885 01:02:14.404067 <6>[ 5.684639] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10886 01:02:14.414221 <6>[ 5.694799] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10887 01:02:14.424767 <6>[ 5.706514] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10888 01:02:14.472426 <6>[ 5.754592] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10889 01:02:14.626945 <6>[ 5.912668] hub 1-1:1.0: USB hub found
10890 01:02:14.630175 <6>[ 5.917206] hub 1-1:1.0: 4 ports detected
10891 01:02:14.640070 <6>[ 5.925582] hub 1-1:1.0: USB hub found
10892 01:02:14.643235 <6>[ 5.929903] hub 1-1:1.0: 4 ports detected
10893 01:02:14.752890 <6>[ 6.034921] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10894 01:02:14.779421 <6>[ 6.064490] hub 2-1:1.0: USB hub found
10895 01:02:14.782450 <6>[ 6.069002] hub 2-1:1.0: 3 ports detected
10896 01:02:14.791937 <6>[ 6.077405] hub 2-1:1.0: USB hub found
10897 01:02:14.795218 <6>[ 6.081888] hub 2-1:1.0: 3 ports detected
10898 01:02:14.968393 <6>[ 6.250625] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10899 01:02:15.101379 <6>[ 6.386123] hub 1-1.4:1.0: USB hub found
10900 01:02:15.104237 <6>[ 6.390787] hub 1-1.4:1.0: 2 ports detected
10901 01:02:15.113743 <6>[ 6.399452] hub 1-1.4:1.0: USB hub found
10902 01:02:15.117412 <6>[ 6.404081] hub 1-1.4:1.0: 2 ports detected
10903 01:02:15.184705 <6>[ 6.466831] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10904 01:02:15.416134 <6>[ 6.698630] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10905 01:02:15.608365 <6>[ 6.890611] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10906 01:02:26.709198 <6>[ 17.999618] ALSA device list:
10907 01:02:26.715846 <6>[ 18.002905] No soundcards found.
10908 01:02:26.724061 <6>[ 18.010990] Freeing unused kernel memory: 8448K
10909 01:02:26.726669 <6>[ 18.015964] Run /init as init process
10910 01:02:26.773704 <6>[ 18.060644] NET: Registered PF_INET6 protocol family
10911 01:02:26.780318 <6>[ 18.067187] Segment Routing with IPv6
10912 01:02:26.783496 <6>[ 18.071149] In-situ OAM (IOAM) with IPv6
10913 01:02:26.818991 <30>[ 18.086126] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10914 01:02:26.822492 <30>[ 18.109819] systemd[1]: Detected architecture arm64.
10915 01:02:26.823046
10916 01:02:26.829042 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10917 01:02:26.829582
10918 01:02:26.843822 <30>[ 18.130539] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10919 01:02:26.969979 <30>[ 18.253666] systemd[1]: Queued start job for default target Graphical Interface.
10920 01:02:27.016235 <30>[ 18.303235] systemd[1]: Created slice system-getty.slice.
10921 01:02:27.023170 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10922 01:02:27.040119 <30>[ 18.327148] systemd[1]: Created slice system-modprobe.slice.
10923 01:02:27.047283 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10924 01:02:27.065298 <30>[ 18.351989] systemd[1]: Created slice system-serial\x2dgetty.slice.
10925 01:02:27.075340 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10926 01:02:27.088017 <30>[ 18.375044] systemd[1]: Created slice User and Session Slice.
10927 01:02:27.094648 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10928 01:02:27.115740 <30>[ 18.399258] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10929 01:02:27.125705 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10930 01:02:27.143699 <30>[ 18.426829] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10931 01:02:27.150868 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10932 01:02:27.170805 <30>[ 18.450672] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10933 01:02:27.176828 <30>[ 18.462848] systemd[1]: Reached target Local Encrypted Volumes.
10934 01:02:27.183269 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10935 01:02:27.201002 <30>[ 18.487165] systemd[1]: Reached target Paths.
10936 01:02:27.206770 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10937 01:02:27.220196 <30>[ 18.506633] systemd[1]: Reached target Remote File Systems.
10938 01:02:27.226193 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10939 01:02:27.240150 <30>[ 18.526610] systemd[1]: Reached target Slices.
10940 01:02:27.246367 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10941 01:02:27.259767 <30>[ 18.546629] systemd[1]: Reached target Swap.
10942 01:02:27.263476 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10943 01:02:27.283266 <30>[ 18.567136] systemd[1]: Listening on initctl Compatibility Named Pipe.
10944 01:02:27.290348 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10945 01:02:27.296791 <30>[ 18.582457] systemd[1]: Listening on Journal Audit Socket.
10946 01:02:27.303700 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10947 01:02:27.316441 <30>[ 18.603185] systemd[1]: Listening on Journal Socket (/dev/log).
10948 01:02:27.322716 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10949 01:02:27.341175 <30>[ 18.627971] systemd[1]: Listening on Journal Socket.
10950 01:02:27.348129 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10951 01:02:27.360325 <30>[ 18.647274] systemd[1]: Listening on udev Control Socket.
10952 01:02:27.366981 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10953 01:02:27.384811 <30>[ 18.671722] systemd[1]: Listening on udev Kernel Socket.
10954 01:02:27.392606 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10955 01:02:27.448122 <30>[ 18.734869] systemd[1]: Mounting Huge Pages File System...
10956 01:02:27.454501 Mounting [0;1;39mHuge Pages File System[0m...
10957 01:02:27.471199 <30>[ 18.758181] systemd[1]: Mounting POSIX Message Queue File System...
10958 01:02:27.478309 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10959 01:02:27.531875 <30>[ 18.818759] systemd[1]: Mounting Kernel Debug File System...
10960 01:02:27.538594 Mounting [0;1;39mKernel Debug File System[0m...
10961 01:02:27.555530 <30>[ 18.838888] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10962 01:02:27.568824 <30>[ 18.851738] systemd[1]: Starting Create list of static device nodes for the current kernel...
10963 01:02:27.575110 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10964 01:02:27.596655 <30>[ 18.883571] systemd[1]: Starting Load Kernel Module configfs...
10965 01:02:27.602772 Starting [0;1;39mLoad Kernel Module configfs[0m...
10966 01:02:27.620869 <30>[ 18.907677] systemd[1]: Starting Load Kernel Module drm...
10967 01:02:27.627584 Starting [0;1;39mLoad Kernel Module drm[0m...
10968 01:02:27.643636 <30>[ 18.927064] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10969 01:02:27.658574 <30>[ 18.945553] systemd[1]: Starting Journal Service...
10970 01:02:27.662128 Starting [0;1;39mJournal Service[0m...
10971 01:02:27.682772 <30>[ 18.969199] systemd[1]: Starting Load Kernel Modules...
10972 01:02:27.688879 Starting [0;1;39mLoad Kernel Modules[0m...
10973 01:02:27.711480 <30>[ 18.995298] systemd[1]: Starting Remount Root and Kernel File Systems...
10974 01:02:27.718198 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10975 01:02:27.734383 <30>[ 19.021690] systemd[1]: Starting Coldplug All udev Devices...
10976 01:02:27.741110 Starting [0;1;39mColdplug All udev Devices[0m...
10977 01:02:27.759029 <30>[ 19.046068] systemd[1]: Started Journal Service.
10978 01:02:27.765850 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10979 01:02:27.783176 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10980 01:02:27.799978 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10981 01:02:27.816229 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10982 01:02:27.836671 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10983 01:02:27.857548 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10984 01:02:27.878204 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10985 01:02:27.896792 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10986 01:02:27.918474 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10987 01:02:27.936237 See 'systemctl status systemd-remount-fs.service' for details.
10988 01:02:27.981089 Mounting [0;1;39mKernel Configuration File System[0m...
10989 01:02:28.002652 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10990 01:02:28.019849 <46>[ 19.303886] systemd-journald[183]: Received client request to flush runtime journal.
10991 01:02:28.029367 Starting [0;1;39mLoad/Save Random Seed[0m...
10992 01:02:28.048215 Starting [0;1;39mApply Kernel Variables[0m...
10993 01:02:28.070302 Starting [0;1;39mCreate System Users[0m...
10994 01:02:28.088898 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10995 01:02:28.104767 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10996 01:02:28.124638 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10997 01:02:28.141881 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10998 01:02:28.162463 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10999 01:02:28.169615 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11000 01:02:28.216805 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11001 01:02:28.242449 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11002 01:02:28.260924 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11003 01:02:28.275893 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11004 01:02:28.315912 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11005 01:02:28.344502 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11006 01:02:28.366246 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11007 01:02:28.385411 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11008 01:02:28.428804 Starting [0;1;39mNetwork Time Synchronization[0m...
11009 01:02:28.463263 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11010 01:02:28.505900 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11011 01:02:28.523910 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11012 01:02:28.544598 <6>[ 19.828159] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11013 01:02:28.551462 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11014 01:02:28.557722 <6>[ 19.843444] remoteproc remoteproc0: scp is available
11015 01:02:28.560743 <6>[ 19.849004] remoteproc remoteproc0: powering up scp
11016 01:02:28.570875 <6>[ 19.854806] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11017 01:02:28.577357 <6>[ 19.855019] usbcore: registered new device driver r8152-cfgselector
11018 01:02:28.584562 <6>[ 19.855603] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11019 01:02:28.594483 <6>[ 19.855620] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11020 01:02:28.603520 <6>[ 19.855625] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11021 01:02:28.607064 <6>[ 19.863261] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11022 01:02:28.613993 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11023 01:02:28.643306 [[0;32m OK [0m] Reached targ<4>[ 19.924128] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11024 01:02:28.645491 et [0;1;39mSystem Time Synchronized[0m.
11025 01:02:28.651980 <4>[ 19.935930] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11026 01:02:28.659105 <6>[ 19.945893] mc: Linux media interface: v0.10
11027 01:02:28.665288 <3>[ 19.947108] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11028 01:02:28.675292 <3>[ 19.958572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11029 01:02:28.682079 <6>[ 19.959579] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11030 01:02:28.692089 <3>[ 19.966660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11031 01:02:28.700063 <3>[ 19.968571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11032 01:02:28.705161 <6>[ 19.969326] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11033 01:02:28.715606 <6>[ 19.979671] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11034 01:02:28.722028 <3>[ 19.983178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11035 01:02:28.728669 <6>[ 19.991236] pci_bus 0000:00: root bus resource [bus 00-ff]
11036 01:02:28.735482 <4>[ 19.995375] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11037 01:02:28.742034 <4>[ 19.995375] Fallback method does not support PEC.
11038 01:02:28.748910 <3>[ 19.999012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11039 01:02:28.755477 <6>[ 20.005863] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11040 01:02:28.766283 <3>[ 20.013936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11041 01:02:28.772531 <3>[ 20.013949] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11042 01:02:28.782196 <3>[ 20.014884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 01:02:28.789520 <4>[ 20.016311] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11044 01:02:28.799006 <4>[ 20.016324] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11045 01:02:28.808860 <6>[ 20.016999] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11046 01:02:28.819461 <6>[ 20.019938] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11047 01:02:28.828812 <6>[ 20.020418] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11048 01:02:28.835029 <3>[ 20.023805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 01:02:28.845009 <6>[ 20.025711] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11050 01:02:28.852000 <6>[ 20.025719] remoteproc remoteproc0: remote processor scp is now up
11051 01:02:28.859048 <6>[ 20.025758] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11052 01:02:28.865361 <3>[ 20.033498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 01:02:28.871703 <6>[ 20.041635] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11054 01:02:28.878685 <3>[ 20.048594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11055 01:02:28.889177 <6>[ 20.056702] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11056 01:02:28.896102 <6>[ 20.062372] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11057 01:02:28.906548 <3>[ 20.067598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11058 01:02:28.912842 <3>[ 20.072922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 01:02:28.919509 <6>[ 20.072973] pci 0000:00:00.0: supports D1 D2
11060 01:02:28.926982 <6>[ 20.072975] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11061 01:02:28.930363 <6>[ 20.073071] r8152 2-1.3:1.0 eth0: v1.12.13
11062 01:02:28.936742 <6>[ 20.073189] usbcore: registered new interface driver r8152
11063 01:02:28.943664 <6>[ 20.074520] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11064 01:02:28.949967 <6>[ 20.074708] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11065 01:02:28.956865 <6>[ 20.074737] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11066 01:02:28.963288 <6>[ 20.074758] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11067 01:02:28.973667 <6>[ 20.074773] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11068 01:02:28.976375 <6>[ 20.074890] pci 0000:01:00.0: supports D1 D2
11069 01:02:28.983102 <6>[ 20.074894] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11070 01:02:28.993078 <6>[ 20.076909] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11071 01:02:28.999950 <3>[ 20.082291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11072 01:02:29.006684 <6>[ 20.082632] videodev: Linux video capture interface: v2.00
11073 01:02:29.012684 <6>[ 20.086374] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11074 01:02:29.019452 <6>[ 20.086409] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11075 01:02:29.029674 <6>[ 20.086413] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11076 01:02:29.035855 <6>[ 20.086422] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11077 01:02:29.045734 <6>[ 20.086435] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11078 01:02:29.052133 <6>[ 20.086449] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11079 01:02:29.059242 <6>[ 20.086461] pci 0000:00:00.0: PCI bridge to [bus 01]
11080 01:02:29.066024 <6>[ 20.086466] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11081 01:02:29.072679 <6>[ 20.086605] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11082 01:02:29.078857 <6>[ 20.087173] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11083 01:02:29.085920 <6>[ 20.087332] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11084 01:02:29.092085 <3>[ 20.091549] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11085 01:02:29.102072 <3>[ 20.100597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11086 01:02:29.108270 <6>[ 20.100953] usbcore: registered new interface driver cdc_ether
11087 01:02:29.115799 <6>[ 20.102461] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11088 01:02:29.121627 <6>[ 20.111086] usbcore: registered new interface driver r8153_ecm
11089 01:02:29.128465 <3>[ 20.119208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11090 01:02:29.135636 <6>[ 20.119974] Bluetooth: Core ver 2.22
11091 01:02:29.138638 <6>[ 20.120027] NET: Registered PF_BLUETOOTH protocol family
11092 01:02:29.144970 <6>[ 20.120029] Bluetooth: HCI device and connection manager initialized
11093 01:02:29.152192 <6>[ 20.120043] Bluetooth: HCI socket layer initialized
11094 01:02:29.155171 <6>[ 20.120047] Bluetooth: L2CAP socket layer initialized
11095 01:02:29.161961 <6>[ 20.120054] Bluetooth: SCO socket layer initialized
11096 01:02:29.167737 <5>[ 20.122715] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11097 01:02:29.174832 <5>[ 20.141703] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11098 01:02:29.184877 <3>[ 20.142891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11099 01:02:29.191005 <3>[ 20.142899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11100 01:02:29.198076 <6>[ 20.144341] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11101 01:02:29.211240 <6>[ 20.145645] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11102 01:02:29.217460 <6>[ 20.145860] usbcore: registered new interface driver uvcvideo
11103 01:02:29.228076 <5>[ 20.150935] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11104 01:02:29.230973 <6>[ 20.151521] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11105 01:02:29.241400 <3>[ 20.158104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11106 01:02:29.247581 <6>[ 20.173537] usbcore: registered new interface driver btusb
11107 01:02:29.257696 <4>[ 20.174912] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11108 01:02:29.263962 <3>[ 20.174933] Bluetooth: hci0: Failed to load firmware file (-2)
11109 01:02:29.267067 <3>[ 20.174939] Bluetooth: hci0: Failed to set up firmware (-2)
11110 01:02:29.280686 <4>[ 20.174948] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11111 01:02:29.286776 <3>[ 20.179881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11112 01:02:29.293292 <6>[ 20.180555] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11113 01:02:29.303519 <3>[ 20.180600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11114 01:02:29.310469 <3>[ 20.185303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11115 01:02:29.319953 <3>[ 20.218546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11116 01:02:29.337744 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd<4>[ 20.619057] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11117 01:02:29.344577 _backlight[0m..<6>[ 20.629547] cfg80211: failed to load regulatory.db
11118 01:02:29.351464 <3>[ 20.635262] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11119 01:02:29.352045 .
11120 01:02:29.375786 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11121 01:02:29.382395 <3>[ 20.666221] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11122 01:02:29.393196 <6>[ 20.674550] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11123 01:02:29.399082 <6>[ 20.683393] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11124 01:02:29.402157 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11125 01:02:29.413679 <3>[ 20.697726] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11126 01:02:29.422689 <6>[ 20.710052] mt7921e 0000:01:00.0: ASIC revision: 79610010
11127 01:02:29.526260 <6>[ 20.809980] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11128 01:02:29.529369 <6>[ 20.809980]
11129 01:02:29.539137 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11130 01:02:29.556019 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11131 01:02:29.579303 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11132 01:02:29.594691 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11133 01:02:29.607828 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11134 01:02:29.631230 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11135 01:02:29.647686 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11136 01:02:29.667524 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11137 01:02:29.688040 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11138 01:02:29.744935 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11139 01:02:29.798686 <6>[ 21.082165] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11140 01:02:29.812614 Starting [0;1;39mUser Login Management[0m...
11141 01:02:29.830737 Starting [0;1;39mPermit User Sessions[0m...
11142 01:02:29.846241 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11143 01:02:29.869780 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11144 01:02:29.890435 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11145 01:02:29.908302 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11146 01:02:29.928127 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11147 01:02:29.944456 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11148 01:02:29.961768 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11149 01:02:29.981503 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11150 01:02:30.000143 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11151 01:02:30.052877 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11152 01:02:30.088884 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11153 01:02:30.128215
11154 01:02:30.128780
11155 01:02:30.131565 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11156 01:02:30.132037
11157 01:02:30.135076 debian-bullseye-arm64 login: root (automatic login)
11158 01:02:30.135705
11159 01:02:30.136260
11160 01:02:30.154752 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
11161 01:02:30.155332
11162 01:02:30.161164 The programs included with the Debian GNU/Linux system are free software;
11163 01:02:30.167609 the exact distribution terms for each program are described in the
11164 01:02:30.171058 individual files in /usr/share/doc/*/copyright.
11165 01:02:30.171677
11166 01:02:30.177966 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11167 01:02:30.180700 permitted by applicable law.
11168 01:02:30.182239 Matched prompt #10: / #
11170 01:02:30.183816 Setting prompt string to ['/ #']
11171 01:02:30.184410 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11173 01:02:30.185651 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11174 01:02:30.186228 start: 2.2.6 expect-shell-connection (timeout 00:01:34) [common]
11175 01:02:30.186647 Setting prompt string to ['/ #']
11176 01:02:30.187068 Forcing a shell prompt, looking for ['/ #']
11178 01:02:30.238242 / #
11179 01:02:30.238940 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11180 01:02:30.239516 Waiting using forced prompt support (timeout 00:02:30)
11181 01:02:30.245465
11182 01:02:30.246463 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11183 01:02:30.247060 start: 2.2.7 export-device-env (timeout 00:01:34) [common]
11184 01:02:30.247700 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11185 01:02:30.248284 end: 2.2 depthcharge-retry (duration 00:03:26) [common]
11186 01:02:30.248862 end: 2 depthcharge-action (duration 00:03:26) [common]
11187 01:02:30.249414 start: 3 lava-test-retry (timeout 00:05:00) [common]
11188 01:02:30.249984 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11189 01:02:30.250436 Using namespace: common
11191 01:02:30.351850 / # #
11192 01:02:30.352529 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11193 01:02:30.358823 #
11194 01:02:30.359796 Using /lava-12571095
11196 01:02:30.461399 / # export SHELL=/bin/sh
11197 01:02:30.469247 export SHELL=/bin/sh
11199 01:02:30.571084 / # . /lava-12571095/environment
11200 01:02:30.577868 . /lava-12571095/environment
11202 01:02:30.679683 / # /lava-12571095/bin/lava-test-runner /lava-12571095/0
11203 01:02:30.680356 Test shell timeout: 10s (minimum of the action and connection timeout)
11204 01:02:30.682167 /lava-12571095/bin/lava-test-runner /lava-12571095/0<6>[ 21.944937] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11205 01:02:30.686525
11206 01:02:30.731814 + export TESTRUN_ID=0_sleep
11207 01:02:30.732387 + cd /lava-12571095/0/tests/0_sleep
11208 01:02:30.732871 + cat uuid
11209 01:02:30.733338 + UUID=12571095_1.5.2.3.1
11210 01:02:30.733777 + set +x
11211 01:02:30.734205 <LAVA_SIGNAL_STARTRUN 0_sleep 12571095_1.5.2.3.1>
11212 01:02:30.734669 + ./config/lava/sleep/sleep.sh mem
11213 01:02:30.735112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11214 01:02:30.735896 Received signal: <STARTRUN> 0_sleep 12571095_1.5.2.3.1
11215 01:02:30.736313 Starting test lava.0_sleep (12571095_1.5.2.3.1)
11216 01:02:30.736849 Skipping test definition patterns.
11217 01:02:30.737576 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11219 01:02:30.739918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11220 01:02:30.740629 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11222 01:02:30.741946 rtcwake: assuming RTC uses UTC ...
11223 01:02:30.748198 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:02:36 2024
11224 01:02:30.751937 <6>[ 22.039020] PM: suspend entry (deep)
11225 01:02:30.756187 <6>[ 22.044068] Filesystems sync: 0.000 seconds
11226 01:02:30.762809 <6>[ 22.050174] Freezing user space processes
11227 01:02:30.772597 <6>[ 22.056187] Freezing user space processes completed (elapsed 0.001 seconds)
11228 01:02:30.776324 <6>[ 22.063407] OOM killer disabled.
11229 01:02:30.778920 <6>[ 22.066888] Freezing remaining freezable tasks
11230 01:02:30.789256 <6>[ 22.072825] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11231 01:02:30.796145 <6>[ 22.080493] printk: Suspending console(s) (use no_console_suspend to debug)
11232 01:02:36.332320 <6>[ 22.231317] Disabling non-boot CPUs ...
11233 01:02:36.336185 <4>[ 22.232360] IRQ282: set affinity failed(-22).
11234 01:02:36.342500 <4>[ 22.232379] IRQ284: set affinity failed(-22).
11235 01:02:36.346262 <6>[ 22.232465] psci: CPU1 killed (polled 0 ms)
11236 01:02:36.348696 <4>[ 22.234078] IRQ282: set affinity failed(-22).
11237 01:02:36.355886 <4>[ 22.234091] IRQ284: set affinity failed(-22).
11238 01:02:36.358405 <6>[ 22.234162] psci: CPU2 killed (polled 0 ms)
11239 01:02:36.362553 <4>[ 22.235410] IRQ282: set affinity failed(-22).
11240 01:02:36.368923 <4>[ 22.235423] IRQ284: set affinity failed(-22).
11241 01:02:36.371759 <6>[ 22.236498] psci: CPU3 killed (polled 0 ms)
11242 01:02:36.378490 <4>[ 22.237174] IRQ282: set affinity failed(-22).
11243 01:02:36.382537 <4>[ 22.237180] IRQ284: set affinity failed(-22).
11244 01:02:36.385705 <6>[ 22.237217] psci: CPU4 killed (polled 0 ms)
11245 01:02:36.392299 <4>[ 22.238261] IRQ282: set affinity failed(-22).
11246 01:02:36.395205 <4>[ 22.238268] IRQ284: set affinity failed(-22).
11247 01:02:36.398547 <6>[ 22.238355] psci: CPU5 killed (polled 4 ms)
11248 01:02:36.405451 <6>[ 22.239249] psci: CPU6 killed (polled 0 ms)
11249 01:02:36.408777 <6>[ 22.239856] psci: CPU7 killed (polled 0 ms)
11250 01:02:36.412049 <6>[ 22.240695] Enabling non-boot CPUs ...
11251 01:02:36.419177 <6>[ 22.240953] Detected VIPT I-cache on CPU1
11252 01:02:36.425094 <6>[ 22.241049] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11253 01:02:36.431117 <6>[ 22.241117] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11254 01:02:36.434971 <6>[ 22.241774] CPU1 is up
11255 01:02:36.437947 <6>[ 22.241935] Detected VIPT I-cache on CPU2
11256 01:02:36.444832 <6>[ 22.242001] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11257 01:02:36.450789 <6>[ 22.242045] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11258 01:02:36.454535 <6>[ 22.242648] CPU2 is up
11259 01:02:36.457692 <6>[ 22.242811] Detected VIPT I-cache on CPU3
11260 01:02:36.467810 <6>[ 22.242877] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11261 01:02:36.474400 <6>[ 22.242921] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11262 01:02:36.474968 <6>[ 22.243488] CPU3 is up
11263 01:02:36.481110 <6>[ 22.243618] CPU features: detected: Hardware dirty bit management
11264 01:02:36.487839 <6>[ 22.243639] Detected PIPT I-cache on CPU4
11265 01:02:36.494284 <6>[ 22.243666] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11266 01:02:36.500696 <6>[ 22.243686] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11267 01:02:36.504326 <6>[ 22.244026] CPU4 is up
11268 01:02:36.507357 <6>[ 22.244170] Detected PIPT I-cache on CPU5
11269 01:02:36.514598 <6>[ 22.244200] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11270 01:02:36.520823 <6>[ 22.244219] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11271 01:02:36.523588 <6>[ 22.244524] CPU5 is up
11272 01:02:36.527084 <6>[ 22.244667] Detected PIPT I-cache on CPU6
11273 01:02:36.536744 <6>[ 22.244696] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11274 01:02:36.543259 <6>[ 22.244715] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11275 01:02:36.543751 <6>[ 22.245024] CPU6 is up
11276 01:02:36.550012 <6>[ 22.245169] Detected PIPT I-cache on CPU7
11277 01:02:36.556729 <6>[ 22.245200] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11278 01:02:36.563493 <6>[ 22.245220] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11279 01:02:36.566223 <6>[ 22.245541] CPU7 is up
11280 01:02:36.573684 <4>[ 22.388348] typec port0-partner: PM: parent port0 should not be sleeping
11281 01:02:36.576775 <6>[ 22.846022] OOM killer enabled.
11282 01:02:36.579904 <6>[ 22.849414] Restarting tasks ... done.
11283 01:02:36.586974 <5>[ 22.853838] random: crng reseeded on system resumption
11284 01:02:36.589798 <6>[ 22.860103] PM: suspend exit
11285 01:02:36.598897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11286 01:02:36.599766 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11288 01:02:36.602885 rtcwake: assuming RTC uses UTC ...
11289 01:02:36.608981 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:02:42 2024
11290 01:02:36.621140 <6>[ 22.889404] PM: suspend entry (deep)
11291 01:02:36.624450 <6>[ 22.893270] Filesystems sync: 0.000 seconds
11292 01:02:36.628005 <6>[ 22.898016] Freezing user space processes
11293 01:02:36.638606 <6>[ 22.903717] Freezing user space processes completed (elapsed 0.001 seconds)
11294 01:02:36.641685 <6>[ 22.910966] OOM killer disabled.
11295 01:02:36.645538 <6>[ 22.914449] Freezing remaining freezable tasks
11296 01:02:36.655593 <6>[ 22.920359] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11297 01:02:36.662555 <6>[ 22.928024] printk: Suspending console(s) (use no_console_suspend to debug)
11298 01:02:42.337282 <6>[ 23.012124] Disabling non-boot CPUs ...
11299 01:02:42.341530 <6>[ 23.013172] psci: CPU1 killed (polled 0 ms)
11300 01:02:42.345786 <6>[ 23.014405] psci: CPU2 killed (polled 0 ms)
11301 01:02:42.350489 <6>[ 23.016498] psci: CPU3 killed (polled 0 ms)
11302 01:02:42.353317 <6>[ 23.017145] psci: CPU4 killed (polled 0 ms)
11303 01:02:42.356692 <6>[ 23.017803] psci: CPU5 killed (polled 0 ms)
11304 01:02:42.363895 <6>[ 23.018419] psci: CPU6 killed (polled 0 ms)
11305 01:02:42.367155 <6>[ 23.018997] psci: CPU7 killed (polled 0 ms)
11306 01:02:42.370258 <6>[ 23.019376] Enabling non-boot CPUs ...
11307 01:02:42.377439 <6>[ 23.019625] Detected VIPT I-cache on CPU1
11308 01:02:42.383613 <6>[ 23.019716] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11309 01:02:42.390671 <6>[ 23.019781] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11310 01:02:42.393503 <6>[ 23.020496] CPU1 is up
11311 01:02:42.396819 <6>[ 23.020651] Detected VIPT I-cache on CPU2
11312 01:02:42.403327 <6>[ 23.020715] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11313 01:02:42.409982 <6>[ 23.020758] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11314 01:02:42.413517 <6>[ 23.021364] CPU2 is up
11315 01:02:42.416792 <6>[ 23.021514] Detected VIPT I-cache on CPU3
11316 01:02:42.424251 <6>[ 23.021577] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11317 01:02:42.429923 <6>[ 23.021619] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11318 01:02:42.432952 <6>[ 23.022262] CPU3 is up
11319 01:02:42.439672 <6>[ 23.022398] Detected PIPT I-cache on CPU4
11320 01:02:42.446371 <6>[ 23.022420] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11321 01:02:42.453299 <6>[ 23.022434] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11322 01:02:42.456089 <6>[ 23.022720] CPU4 is up
11323 01:02:42.459598 <6>[ 23.022849] Detected PIPT I-cache on CPU5
11324 01:02:42.466798 <6>[ 23.022871] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11325 01:02:42.472993 <6>[ 23.022885] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11326 01:02:42.476573 <6>[ 23.023126] CPU5 is up
11327 01:02:42.479039 <6>[ 23.023261] Detected PIPT I-cache on CPU6
11328 01:02:42.485916 <6>[ 23.023283] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11329 01:02:42.496128 <6>[ 23.023297] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11330 01:02:42.496680 <6>[ 23.023550] CPU6 is up
11331 01:02:42.502270 <6>[ 23.023679] Detected PIPT I-cache on CPU7
11332 01:02:42.509098 <6>[ 23.023702] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11333 01:02:42.515971 <6>[ 23.023716] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11334 01:02:42.518986 <6>[ 23.023977] CPU7 is up
11335 01:02:42.522521 <6>[ 23.570706] OOM killer enabled.
11336 01:02:42.525871 <6>[ 23.574096] Restarting tasks ... done.
11337 01:02:42.532151 <5>[ 23.578482] random: crng reseeded on system resumption
11338 01:02:42.535590 <6>[ 23.584743] PM: suspend exit
11339 01:02:42.544231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11340 01:02:42.545104 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11342 01:02:42.547600 rtcwake: assuming RTC uses UTC ...
11343 01:02:42.553739 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:02:48 2024
11344 01:02:42.567106 <6>[ 23.614465] PM: suspend entry (deep)
11345 01:02:42.569943 <6>[ 23.618329] Filesystems sync: 0.000 seconds
11346 01:02:42.573443 <6>[ 23.623077] Freezing user space processes
11347 01:02:42.584499 <6>[ 23.628715] Freezing user space processes completed (elapsed 0.001 seconds)
11348 01:02:42.587174 <6>[ 23.635938] OOM killer disabled.
11349 01:02:42.591015 <6>[ 23.639418] Freezing remaining freezable tasks
11350 01:02:42.601150 <6>[ 23.645316] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11351 01:02:42.607534 <6>[ 23.652982] printk: Suspending console(s) (use no_console_suspend to debug)
11352 01:02:48.333888 <6>[ 23.726026] Disabling non-boot CPUs ...
11353 01:02:48.337234 <6>[ 23.727065] psci: CPU1 killed (polled 0 ms)
11354 01:02:48.340704 <6>[ 23.729197] psci: CPU2 killed (polled 0 ms)
11355 01:02:48.347280 <6>[ 23.730346] psci: CPU3 killed (polled 0 ms)
11356 01:02:48.350670 <6>[ 23.730952] psci: CPU4 killed (polled 0 ms)
11357 01:02:48.354127 <6>[ 23.731585] psci: CPU5 killed (polled 0 ms)
11358 01:02:48.360755 <6>[ 23.732176] psci: CPU6 killed (polled 0 ms)
11359 01:02:48.363741 <6>[ 23.732748] psci: CPU7 killed (polled 0 ms)
11360 01:02:48.367869 <6>[ 23.733141] Enabling non-boot CPUs ...
11361 01:02:48.373768 <6>[ 23.733386] Detected VIPT I-cache on CPU1
11362 01:02:48.380272 <6>[ 23.733480] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11363 01:02:48.387420 <6>[ 23.733544] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11364 01:02:48.390722 <6>[ 23.734288] CPU1 is up
11365 01:02:48.394031 <6>[ 23.734444] Detected VIPT I-cache on CPU2
11366 01:02:48.401108 <6>[ 23.734509] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11367 01:02:48.406848 <6>[ 23.734551] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11368 01:02:48.410517 <6>[ 23.735156] CPU2 is up
11369 01:02:48.414249 <6>[ 23.735313] Detected VIPT I-cache on CPU3
11370 01:02:48.420160 <6>[ 23.735377] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11371 01:02:48.430316 <6>[ 23.735418] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11372 01:02:48.430878 <6>[ 23.736004] CPU3 is up
11373 01:02:48.437017 <6>[ 23.736136] Detected PIPT I-cache on CPU4
11374 01:02:48.443464 <6>[ 23.736156] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11375 01:02:48.450654 <6>[ 23.736168] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11376 01:02:48.453746 <6>[ 23.736433] CPU4 is up
11377 01:02:48.456896 <6>[ 23.736573] Detected PIPT I-cache on CPU5
11378 01:02:48.463155 <6>[ 23.736594] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11379 01:02:48.470099 <6>[ 23.736607] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11380 01:02:48.473273 <6>[ 23.736847] CPU5 is up
11381 01:02:48.476709 <6>[ 23.736996] Detected PIPT I-cache on CPU6
11382 01:02:48.486821 <6>[ 23.737016] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11383 01:02:48.493292 <6>[ 23.737029] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11384 01:02:48.493861 <6>[ 23.737263] CPU6 is up
11385 01:02:48.499553 <6>[ 23.737391] Detected PIPT I-cache on CPU7
11386 01:02:48.506455 <6>[ 23.737411] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11387 01:02:48.512675 <6>[ 23.737424] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11388 01:02:48.516171 <6>[ 23.737674] CPU7 is up
11389 01:02:48.519485 <6>[ 24.282460] OOM killer enabled.
11390 01:02:48.523025 <6>[ 24.285850] Restarting tasks ... done.
11391 01:02:48.529202 <5>[ 24.290196] random: crng reseeded on system resumption
11392 01:02:48.532749 <6>[ 24.297007] PM: suspend exit
11393 01:02:48.541733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11394 01:02:48.542617 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11396 01:02:48.545030 rtcwake: assuming RTC uses UTC ...
11397 01:02:48.551628 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:02:54 2024
11398 01:02:48.564230 <6>[ 24.326758] PM: suspend entry (deep)
11399 01:02:48.567314 <6>[ 24.330622] Filesystems sync: 0.000 seconds
11400 01:02:48.571232 <6>[ 24.335367] Freezing user space processes
11401 01:02:48.581932 <6>[ 24.341055] Freezing user space processes completed (elapsed 0.001 seconds)
11402 01:02:48.585439 <6>[ 24.348285] OOM killer disabled.
11403 01:02:48.588472 <6>[ 24.351767] Freezing remaining freezable tasks
11404 01:02:48.598675 <6>[ 24.357688] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11405 01:02:48.605447 <6>[ 24.365356] printk: Suspending console(s) (use no_console_suspend to debug)
11406 01:02:54.330655 <6>[ 24.438187] Disabling non-boot CPUs ...
11407 01:02:54.333474 <6>[ 24.439050] psci: CPU1 killed (polled 0 ms)
11408 01:02:54.336293 <6>[ 24.440029] psci: CPU2 killed (polled 0 ms)
11409 01:02:54.342828 <6>[ 24.441894] psci: CPU3 killed (polled 0 ms)
11410 01:02:54.345987 <6>[ 24.442451] psci: CPU4 killed (polled 0 ms)
11411 01:02:54.350003 <6>[ 24.443055] psci: CPU5 killed (polled 0 ms)
11412 01:02:54.356145 <6>[ 24.443712] psci: CPU6 killed (polled 0 ms)
11413 01:02:54.359812 <6>[ 24.444325] psci: CPU7 killed (polled 0 ms)
11414 01:02:54.362314 <6>[ 24.444647] Enabling non-boot CPUs ...
11415 01:02:54.369303 <6>[ 24.444871] Detected VIPT I-cache on CPU1
11416 01:02:54.375560 <6>[ 24.444950] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11417 01:02:54.382298 <6>[ 24.445006] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11418 01:02:54.385490 <6>[ 24.445608] CPU1 is up
11419 01:02:54.389135 <6>[ 24.445738] Detected VIPT I-cache on CPU2
11420 01:02:54.395998 <6>[ 24.445789] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11421 01:02:54.402894 <6>[ 24.445823] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11422 01:02:54.406699 <6>[ 24.446320] CPU2 is up
11423 01:02:54.409777 <6>[ 24.446447] Detected VIPT I-cache on CPU3
11424 01:02:54.416012 <6>[ 24.446497] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11425 01:02:54.425419 <6>[ 24.446531] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11426 01:02:54.425979 <6>[ 24.446997] CPU3 is up
11427 01:02:54.431923 <6>[ 24.447118] Detected PIPT I-cache on CPU4
11428 01:02:54.439040 <6>[ 24.447141] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11429 01:02:54.445617 <6>[ 24.447156] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11430 01:02:54.449125 <6>[ 24.447450] CPU4 is up
11431 01:02:54.451728 <6>[ 24.447578] Detected PIPT I-cache on CPU5
11432 01:02:54.458784 <6>[ 24.447602] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11433 01:02:54.465391 <6>[ 24.447617] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11434 01:02:54.468608 <6>[ 24.447862] CPU5 is up
11435 01:02:54.471729 <6>[ 24.447980] Detected PIPT I-cache on CPU6
11436 01:02:54.481654 <6>[ 24.448003] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11437 01:02:54.488381 <6>[ 24.448018] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11438 01:02:54.488944 <6>[ 24.448273] CPU6 is up
11439 01:02:54.494938 <6>[ 24.448390] Detected PIPT I-cache on CPU7
11440 01:02:54.501454 <6>[ 24.448413] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11441 01:02:54.508220 <6>[ 24.448428] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11442 01:02:54.511621 <6>[ 24.448693] CPU7 is up
11443 01:02:54.514814 <6>[ 24.990232] OOM killer enabled.
11444 01:02:54.518657 <6>[ 24.993622] Restarting tasks ... done.
11445 01:02:54.524823 <5>[ 24.997995] random: crng reseeded on system resumption
11446 01:02:54.528038 <6>[ 25.004259] PM: suspend exit
11447 01:02:54.536810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11448 01:02:54.537678 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11450 01:02:54.540241 rtcwake: assuming RTC uses UTC ...
11451 01:02:54.546460 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:03:00 2024
11452 01:02:54.558813 <6>[ 25.033638] PM: suspend entry (deep)
11453 01:02:54.562386 <6>[ 25.037508] Filesystems sync: 0.000 seconds
11454 01:02:54.565884 <6>[ 25.042276] Freezing user space processes
11455 01:02:54.576588 <6>[ 25.047969] Freezing user space processes completed (elapsed 0.001 seconds)
11456 01:02:54.579698 <6>[ 25.055196] OOM killer disabled.
11457 01:02:54.583191 <6>[ 25.058682] Freezing remaining freezable tasks
11458 01:02:54.593185 <6>[ 25.064601] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11459 01:02:54.599892 <6>[ 25.072270] printk: Suspending console(s) (use no_console_suspend to debug)
11460 01:03:00.330504 <6>[ 25.146765] Disabling non-boot CPUs ...
11461 01:03:00.334037 <6>[ 25.147792] psci: CPU1 killed (polled 0 ms)
11462 01:03:00.337732 <6>[ 25.150160] psci: CPU2 killed (polled 4 ms)
11463 01:03:00.343622 <6>[ 25.152170] psci: CPU3 killed (polled 0 ms)
11464 01:03:00.347055 <6>[ 25.152820] psci: CPU4 killed (polled 0 ms)
11465 01:03:00.350420 <6>[ 25.153469] psci: CPU5 killed (polled 0 ms)
11466 01:03:00.357058 <6>[ 25.154087] psci: CPU6 killed (polled 0 ms)
11467 01:03:00.360152 <6>[ 25.154746] psci: CPU7 killed (polled 0 ms)
11468 01:03:00.363476 <6>[ 25.155154] Enabling non-boot CPUs ...
11469 01:03:00.370473 <6>[ 25.155398] Detected VIPT I-cache on CPU1
11470 01:03:00.377308 <6>[ 25.155493] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11471 01:03:00.383591 <6>[ 25.155557] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11472 01:03:00.387058 <6>[ 25.156287] CPU1 is up
11473 01:03:00.389825 <6>[ 25.156442] Detected VIPT I-cache on CPU2
11474 01:03:00.396607 <6>[ 25.156505] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11475 01:03:00.403224 <6>[ 25.156547] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11476 01:03:00.406812 <6>[ 25.157164] CPU2 is up
11477 01:03:00.410013 <6>[ 25.157313] Detected VIPT I-cache on CPU3
11478 01:03:00.419776 <6>[ 25.157376] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11479 01:03:00.427010 <6>[ 25.157418] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11480 01:03:00.427617 <6>[ 25.158041] CPU3 is up
11481 01:03:00.433385 <6>[ 25.158248] Detected PIPT I-cache on CPU4
11482 01:03:00.440211 <6>[ 25.158269] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11483 01:03:00.446570 <6>[ 25.158283] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11484 01:03:00.449539 <6>[ 25.158554] CPU4 is up
11485 01:03:00.453156 <6>[ 25.158687] Detected PIPT I-cache on CPU5
11486 01:03:00.459568 <6>[ 25.158710] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11487 01:03:00.466150 <6>[ 25.158724] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11488 01:03:00.469732 <6>[ 25.158964] CPU5 is up
11489 01:03:00.472975 <6>[ 25.159095] Detected PIPT I-cache on CPU6
11490 01:03:00.482672 <6>[ 25.159117] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11491 01:03:00.489861 <6>[ 25.159131] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11492 01:03:00.490419 <6>[ 25.159377] CPU6 is up
11493 01:03:00.496040 <6>[ 25.159507] Detected PIPT I-cache on CPU7
11494 01:03:00.502611 <6>[ 25.159529] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11495 01:03:00.509214 <6>[ 25.159543] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11496 01:03:00.512798 <6>[ 25.159808] CPU7 is up
11497 01:03:00.516107 <6>[ 25.702633] OOM killer enabled.
11498 01:03:00.520115 <6>[ 25.706022] Restarting tasks ... done.
11499 01:03:00.526009 <5>[ 25.710394] random: crng reseeded on system resumption
11500 01:03:00.529127 <6>[ 25.716683] PM: suspend exit
11501 01:03:00.537502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11502 01:03:00.538393 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11504 01:03:00.540895 rtcwake: assuming RTC uses UTC ...
11505 01:03:00.547523 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:03:06 2024
11506 01:03:00.559769 <6>[ 25.745584] PM: suspend entry (deep)
11507 01:03:00.563979 <6>[ 25.749456] Filesystems sync: 0.000 seconds
11508 01:03:00.565731 <6>[ 25.754216] Freezing user space processes
11509 01:03:00.576811 <6>[ 25.759857] Freezing user space processes completed (elapsed 0.001 seconds)
11510 01:03:00.580352 <6>[ 25.767086] OOM killer disabled.
11511 01:03:00.583445 <6>[ 25.770596] Freezing remaining freezable tasks
11512 01:03:00.593490 <6>[ 25.776521] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11513 01:03:00.599789 <6>[ 25.784184] printk: Suspending console(s) (use no_console_suspend to debug)
11514 01:03:06.328773 <6>[ 25.857522] Disabling non-boot CPUs ...
11515 01:03:06.331658 <6>[ 25.858453] psci: CPU1 killed (polled 0 ms)
11516 01:03:06.335453 <6>[ 25.859425] psci: CPU2 killed (polled 0 ms)
11517 01:03:06.341959 <6>[ 25.861299] psci: CPU3 killed (polled 0 ms)
11518 01:03:06.344741 <6>[ 25.861835] psci: CPU4 killed (polled 0 ms)
11519 01:03:06.348067 <6>[ 25.862435] psci: CPU5 killed (polled 0 ms)
11520 01:03:06.354953 <6>[ 25.862974] psci: CPU6 killed (polled 0 ms)
11521 01:03:06.358230 <6>[ 25.863607] psci: CPU7 killed (polled 0 ms)
11522 01:03:06.361571 <6>[ 25.863921] Enabling non-boot CPUs ...
11523 01:03:06.368330 <6>[ 25.864141] Detected VIPT I-cache on CPU1
11524 01:03:06.374349 <6>[ 25.864221] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11525 01:03:06.381368 <6>[ 25.864276] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11526 01:03:06.384792 <6>[ 25.864878] CPU1 is up
11527 01:03:06.387590 <6>[ 25.865008] Detected VIPT I-cache on CPU2
11528 01:03:06.394626 <6>[ 25.865059] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11529 01:03:06.401464 <6>[ 25.865093] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11530 01:03:06.404770 <6>[ 25.865578] CPU2 is up
11531 01:03:06.408251 <6>[ 25.865702] Detected VIPT I-cache on CPU3
11532 01:03:06.417998 <6>[ 25.865752] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11533 01:03:06.424089 <6>[ 25.865785] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11534 01:03:06.424508 <6>[ 25.866277] CPU3 is up
11535 01:03:06.430934 <6>[ 25.866408] Detected PIPT I-cache on CPU4
11536 01:03:06.437538 <6>[ 25.866430] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11537 01:03:06.444423 <6>[ 25.866444] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11538 01:03:06.447537 <6>[ 25.866711] CPU4 is up
11539 01:03:06.450826 <6>[ 25.866827] Detected PIPT I-cache on CPU5
11540 01:03:06.457533 <6>[ 25.866848] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11541 01:03:06.463812 <6>[ 25.866862] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11542 01:03:06.467298 <6>[ 25.867093] CPU5 is up
11543 01:03:06.470646 <6>[ 25.867207] Detected PIPT I-cache on CPU6
11544 01:03:06.480157 <6>[ 25.867229] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11545 01:03:06.486835 <6>[ 25.867243] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11546 01:03:06.490283 <6>[ 25.867496] CPU6 is up
11547 01:03:06.493546 <6>[ 25.867622] Detected PIPT I-cache on CPU7
11548 01:03:06.500346 <6>[ 25.867643] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11549 01:03:06.506987 <6>[ 25.867657] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11550 01:03:06.510582 <6>[ 25.867912] CPU7 is up
11551 01:03:06.513331 <6>[ 26.410304] OOM killer enabled.
11552 01:03:06.517185 <6>[ 26.413695] Restarting tasks ... done.
11553 01:03:06.523166 <5>[ 26.418078] random: crng reseeded on system resumption
11554 01:03:06.527049 <6>[ 26.424395] PM: suspend exit
11555 01:03:06.535643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11556 01:03:06.536436 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11558 01:03:06.539155 rtcwake: assuming RTC uses UTC ...
11559 01:03:06.545581 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:03:12 2024
11560 01:03:06.558326 <6>[ 26.454209] PM: suspend entry (deep)
11561 01:03:06.561777 <6>[ 26.458080] Filesystems sync: 0.000 seconds
11562 01:03:06.565458 <6>[ 26.462819] Freezing user space processes
11563 01:03:06.576323 <6>[ 26.468490] Freezing user space processes completed (elapsed 0.001 seconds)
11564 01:03:06.579790 <6>[ 26.475725] OOM killer disabled.
11565 01:03:06.583250 <6>[ 26.479210] Freezing remaining freezable tasks
11566 01:03:06.592615 <6>[ 26.485132] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11567 01:03:06.599349 <6>[ 26.492800] printk: Suspending console(s) (use no_console_suspend to debug)
11568 01:03:12.333028 <6>[ 26.579727] Disabling non-boot CPUs ...
11569 01:03:12.336262 <6>[ 26.580826] psci: CPU1 killed (polled 0 ms)
11570 01:03:12.340100 <6>[ 26.582023] psci: CPU2 killed (polled 0 ms)
11571 01:03:12.346354 <6>[ 26.584128] psci: CPU3 killed (polled 0 ms)
11572 01:03:12.349138 <6>[ 26.584783] psci: CPU4 killed (polled 0 ms)
11573 01:03:12.353115 <6>[ 26.585442] psci: CPU5 killed (polled 0 ms)
11574 01:03:12.359179 <6>[ 26.586146] psci: CPU6 killed (polled 0 ms)
11575 01:03:12.362520 <6>[ 26.586715] psci: CPU7 killed (polled 0 ms)
11576 01:03:12.366428 <6>[ 26.587027] Enabling non-boot CPUs ...
11577 01:03:12.372335 <6>[ 26.587272] Detected VIPT I-cache on CPU1
11578 01:03:12.379541 <6>[ 26.587366] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11579 01:03:12.385566 <6>[ 26.587431] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11580 01:03:12.389411 <6>[ 26.588166] CPU1 is up
11581 01:03:12.392247 <6>[ 26.588320] Detected VIPT I-cache on CPU2
11582 01:03:12.399081 <6>[ 26.588384] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11583 01:03:12.405812 <6>[ 26.588426] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11584 01:03:12.409302 <6>[ 26.589038] CPU2 is up
11585 01:03:12.412331 <6>[ 26.589189] Detected VIPT I-cache on CPU3
11586 01:03:12.422701 <6>[ 26.589253] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11587 01:03:12.429098 <6>[ 26.589295] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11588 01:03:12.429657 <6>[ 26.589895] CPU3 is up
11589 01:03:12.435976 <6>[ 26.590032] Detected PIPT I-cache on CPU4
11590 01:03:12.442463 <6>[ 26.590055] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11591 01:03:12.448839 <6>[ 26.590070] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11592 01:03:12.452313 <6>[ 26.590358] CPU4 is up
11593 01:03:12.455434 <6>[ 26.590492] Detected PIPT I-cache on CPU5
11594 01:03:12.462470 <6>[ 26.590515] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11595 01:03:12.468909 <6>[ 26.590530] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11596 01:03:12.472045 <6>[ 26.590778] CPU5 is up
11597 01:03:12.475757 <6>[ 26.590915] Detected PIPT I-cache on CPU6
11598 01:03:12.485471 <6>[ 26.590939] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11599 01:03:12.491560 <6>[ 26.590953] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11600 01:03:12.492037 <6>[ 26.591216] CPU6 is up
11601 01:03:12.498423 <6>[ 26.591346] Detected PIPT I-cache on CPU7
11602 01:03:12.504636 <6>[ 26.591375] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11603 01:03:12.511233 <6>[ 26.591390] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11604 01:03:12.514717 <6>[ 26.591666] CPU7 is up
11605 01:03:12.518385 <6>[ 27.138700] OOM killer enabled.
11606 01:03:12.521568 <6>[ 27.142092] Restarting tasks ... done.
11607 01:03:12.528022 <5>[ 27.146460] random: crng reseeded on system resumption
11608 01:03:12.531941 <6>[ 27.152683] PM: suspend exit
11609 01:03:12.540644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11610 01:03:12.541552 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11612 01:03:12.544136 rtcwake: assuming RTC uses UTC ...
11613 01:03:12.550540 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:03:18 2024
11614 01:03:12.563602 <6>[ 27.183297] PM: suspend entry (deep)
11615 01:03:12.566824 <6>[ 27.187161] Filesystems sync: 0.000 seconds
11616 01:03:12.569811 <6>[ 27.191912] Freezing user space processes
11617 01:03:12.581474 <6>[ 27.197608] Freezing user space processes completed (elapsed 0.001 seconds)
11618 01:03:12.584589 <6>[ 27.204839] OOM killer disabled.
11619 01:03:12.587764 <6>[ 27.208320] Freezing remaining freezable tasks
11620 01:03:12.598126 <6>[ 27.214193] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11621 01:03:12.604598 <6>[ 27.221849] printk: Suspending console(s) (use no_console_suspend to debug)
11622 01:03:18.324118 <6>[ 27.298390] Disabling non-boot CPUs ...
11623 01:03:18.327471 <4>[ 27.299361] migrate_one_irq: 88 callbacks suppressed
11624 01:03:18.333941 <4>[ 27.299376] IRQ282: set affinity failed(-22).
11625 01:03:18.338188 <4>[ 27.299388] IRQ284: set affinity failed(-22).
11626 01:03:18.340657 <6>[ 27.299474] psci: CPU1 killed (polled 0 ms)
11627 01:03:18.346951 <4>[ 27.300566] IRQ282: set affinity failed(-22).
11628 01:03:18.350868 <4>[ 27.300578] IRQ284: set affinity failed(-22).
11629 01:03:18.357295 <6>[ 27.301651] psci: CPU2 killed (polled 0 ms)
11630 01:03:18.360903 <4>[ 27.302679] IRQ282: set affinity failed(-22).
11631 01:03:18.363941 <4>[ 27.302692] IRQ284: set affinity failed(-22).
11632 01:03:18.370610 <6>[ 27.303762] psci: CPU3 killed (polled 0 ms)
11633 01:03:18.374203 <4>[ 27.304434] IRQ282: set affinity failed(-22).
11634 01:03:18.378052 <4>[ 27.304438] IRQ284: set affinity failed(-22).
11635 01:03:18.384293 <6>[ 27.304470] psci: CPU4 killed (polled 0 ms)
11636 01:03:18.387440 <4>[ 27.305154] IRQ282: set affinity failed(-22).
11637 01:03:18.393961 <4>[ 27.305159] IRQ284: set affinity failed(-22).
11638 01:03:18.396670 <6>[ 27.305197] psci: CPU5 killed (polled 0 ms)
11639 01:03:18.401009 <6>[ 27.305815] psci: CPU6 killed (polled 0 ms)
11640 01:03:18.407112 <6>[ 27.306492] psci: CPU7 killed (polled 0 ms)
11641 01:03:18.410499 <6>[ 27.306858] Enabling non-boot CPUs ...
11642 01:03:18.413887 <6>[ 27.307103] Detected VIPT I-cache on CPU1
11643 01:03:18.420683 <6>[ 27.307196] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11644 01:03:18.426992 <6>[ 27.307263] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11645 01:03:18.430577 <6>[ 27.307998] CPU1 is up
11646 01:03:18.434496 <6>[ 27.308149] Detected VIPT I-cache on CPU2
11647 01:03:18.443564 <6>[ 27.308213] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11648 01:03:18.450546 <6>[ 27.308255] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11649 01:03:18.451113 <6>[ 27.308859] CPU2 is up
11650 01:03:18.457067 <6>[ 27.309009] Detected VIPT I-cache on CPU3
11651 01:03:18.463444 <6>[ 27.309074] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11652 01:03:18.469797 <6>[ 27.309116] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11653 01:03:18.473318 <6>[ 27.309703] CPU3 is up
11654 01:03:18.477235 <6>[ 27.309836] Detected PIPT I-cache on CPU4
11655 01:03:18.484052 <6>[ 27.309858] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11656 01:03:18.490274 <6>[ 27.309872] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11657 01:03:18.492800 <6>[ 27.310162] CPU4 is up
11658 01:03:18.497402 <6>[ 27.310294] Detected PIPT I-cache on CPU5
11659 01:03:18.506472 <6>[ 27.310317] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11660 01:03:18.512692 <6>[ 27.310331] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11661 01:03:18.513237 <6>[ 27.310573] CPU5 is up
11662 01:03:18.519279 <6>[ 27.310709] Detected PIPT I-cache on CPU6
11663 01:03:18.526003 <6>[ 27.310730] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11664 01:03:18.532770 <6>[ 27.310744] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11665 01:03:18.535735 <6>[ 27.310996] CPU6 is up
11666 01:03:18.540105 <6>[ 27.311125] Detected PIPT I-cache on CPU7
11667 01:03:18.545793 <6>[ 27.311153] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11668 01:03:18.552873 <6>[ 27.311167] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11669 01:03:18.556112 <6>[ 27.311426] CPU7 is up
11670 01:03:18.559808 <6>[ 27.901743] OOM killer enabled.
11671 01:03:18.562802 <6>[ 27.905134] Restarting tasks ... done.
11672 01:03:18.569073 <5>[ 27.909493] random: crng reseeded on system resumption
11673 01:03:18.572394 <6>[ 27.915820] PM: suspend exit
11674 01:03:18.582562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11675 01:03:18.583472 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11677 01:03:18.585320 rtcwake: assuming RTC uses UTC ...
11678 01:03:18.592265 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:03:24 2024
11679 01:03:18.605341 <6>[ 27.945617] PM: suspend entry (deep)
11680 01:03:18.608342 <6>[ 27.949487] Filesystems sync: 0.000 seconds
11681 01:03:18.611768 <6>[ 27.954260] Freezing user space processes
11682 01:03:18.622925 <6>[ 27.959935] Freezing user space processes completed (elapsed 0.001 seconds)
11683 01:03:18.626092 <6>[ 27.967168] OOM killer disabled.
11684 01:03:18.629381 <6>[ 27.970657] Freezing remaining freezable tasks
11685 01:03:18.639773 <6>[ 27.976595] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11686 01:03:18.646221 <6>[ 27.984259] printk: Suspending console(s) (use no_console_suspend to debug)
11687 01:03:24.320247 <6>[ 28.067193] Disabling non-boot CPUs ...
11688 01:03:24.323551 <6>[ 28.067999] psci: CPU1 killed (polled 0 ms)
11689 01:03:24.327258 <6>[ 28.068992] psci: CPU2 killed (polled 0 ms)
11690 01:03:24.333673 <6>[ 28.070792] psci: CPU3 killed (polled 4 ms)
11691 01:03:24.337136 <6>[ 28.071260] psci: CPU4 killed (polled 0 ms)
11692 01:03:24.343345 <6>[ 28.071855] psci: CPU5 killed (polled 0 ms)
11693 01:03:24.346752 <6>[ 28.072407] psci: CPU6 killed (polled 0 ms)
11694 01:03:24.350114 <6>[ 28.072903] psci: CPU7 killed (polled 0 ms)
11695 01:03:24.353200 <6>[ 28.073192] Enabling non-boot CPUs ...
11696 01:03:24.360524 <6>[ 28.073401] Detected VIPT I-cache on CPU1
11697 01:03:24.367497 <6>[ 28.073478] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11698 01:03:24.373102 <6>[ 28.073531] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11699 01:03:24.376074 <6>[ 28.074117] CPU1 is up
11700 01:03:24.379857 <6>[ 28.074238] Detected VIPT I-cache on CPU2
11701 01:03:24.386292 <6>[ 28.074285] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11702 01:03:24.393148 <6>[ 28.074316] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11703 01:03:24.396070 <6>[ 28.074752] CPU2 is up
11704 01:03:24.400122 <6>[ 28.074870] Detected VIPT I-cache on CPU3
11705 01:03:24.409185 <6>[ 28.074917] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11706 01:03:24.417117 <6>[ 28.074948] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11707 01:03:24.417678 <6>[ 28.075369] CPU3 is up
11708 01:03:24.422579 <6>[ 28.075486] Detected PIPT I-cache on CPU4
11709 01:03:24.429422 <6>[ 28.075509] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11710 01:03:24.436132 <6>[ 28.075524] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11711 01:03:24.439826 <6>[ 28.075800] CPU4 is up
11712 01:03:24.443154 <6>[ 28.075912] Detected PIPT I-cache on CPU5
11713 01:03:24.449420 <6>[ 28.075936] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11714 01:03:24.456273 <6>[ 28.075951] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11715 01:03:24.460058 <6>[ 28.076188] CPU5 is up
11716 01:03:24.463556 <6>[ 28.076306] Detected PIPT I-cache on CPU6
11717 01:03:24.472396 <6>[ 28.076330] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11718 01:03:24.479114 <6>[ 28.076345] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11719 01:03:24.479718 <6>[ 28.076606] CPU6 is up
11720 01:03:24.486051 <6>[ 28.076719] Detected PIPT I-cache on CPU7
11721 01:03:24.492594 <6>[ 28.076747] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11722 01:03:24.499296 <6>[ 28.076762] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11723 01:03:24.502447 <6>[ 28.077025] CPU7 is up
11724 01:03:24.505842 <6>[ 28.614123] OOM killer enabled.
11725 01:03:24.508957 <6>[ 28.617514] Restarting tasks ... done.
11726 01:03:24.515472 <5>[ 28.621887] random: crng reseeded on system resumption
11727 01:03:24.518690 <6>[ 28.628289] PM: suspend exit
11728 01:03:24.527901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11729 01:03:24.528759 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11731 01:03:24.531218 rtcwake: assuming RTC uses UTC ...
11732 01:03:24.537832 rtcwake: wakeup from "mem" using rtc0 at Fri Jan 19 01:03:30 2024
11733 01:03:24.550268 <6>[ 28.657758] PM: suspend entry (deep)
11734 01:03:24.553405 <6>[ 28.661625] Filesystems sync: 0.000 seconds
11735 01:03:24.556389 <6>[ 28.666372] Freezing user space processes
11736 01:03:24.567463 <6>[ 28.672034] Freezing user space processes completed (elapsed 0.001 seconds)
11737 01:03:24.570788 <6>[ 28.679262] OOM killer disabled.
11738 01:03:24.574580 <6>[ 28.682748] Freezing remaining freezable tasks
11739 01:03:24.583939 <6>[ 28.688680] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11740 01:03:24.591628 <6>[ 28.696346] printk: Suspending console(s) (use no_console_suspend to debug)
11741 01:03:30.334695 <6>[ 28.770307] Disabling non-boot CPUs ...
11742 01:03:30.338035 <6>[ 28.771288] psci: CPU1 killed (polled 0 ms)
11743 01:03:30.341266 <6>[ 28.773624] psci: CPU2 killed (polled 0 ms)
11744 01:03:30.347833 <6>[ 28.775709] psci: CPU3 killed (polled 0 ms)
11745 01:03:30.350927 <6>[ 28.776370] psci: CPU4 killed (polled 0 ms)
11746 01:03:30.355062 <6>[ 28.777020] psci: CPU5 killed (polled 0 ms)
11747 01:03:30.360826 <6>[ 28.777638] psci: CPU6 killed (polled 0 ms)
11748 01:03:30.364398 <6>[ 28.778267] psci: CPU7 killed (polled 0 ms)
11749 01:03:30.367533 <6>[ 28.778663] Enabling non-boot CPUs ...
11750 01:03:30.374215 <6>[ 28.778907] Detected VIPT I-cache on CPU1
11751 01:03:30.381430 <6>[ 28.779001] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11752 01:03:30.387733 <6>[ 28.779066] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11753 01:03:30.391184 <6>[ 28.779786] CPU1 is up
11754 01:03:30.394736 <6>[ 28.779938] Detected VIPT I-cache on CPU2
11755 01:03:30.400621 <6>[ 28.780001] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11756 01:03:30.407664 <6>[ 28.780044] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11757 01:03:30.411093 <6>[ 28.780656] CPU2 is up
11758 01:03:30.413774 <6>[ 28.780808] Detected VIPT I-cache on CPU3
11759 01:03:30.420789 <6>[ 28.780872] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11760 01:03:30.430777 <6>[ 28.780913] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11761 01:03:30.431336 <6>[ 28.781509] CPU3 is up
11762 01:03:30.436668 <6>[ 28.781642] Detected PIPT I-cache on CPU4
11763 01:03:30.443966 <6>[ 28.781664] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11764 01:03:30.450560 <6>[ 28.781678] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11765 01:03:30.453871 <6>[ 28.781966] CPU4 is up
11766 01:03:30.457173 <6>[ 28.782099] Detected PIPT I-cache on CPU5
11767 01:03:30.464194 <6>[ 28.782122] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11768 01:03:30.470039 <6>[ 28.782136] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11769 01:03:30.474313 <6>[ 28.782373] CPU5 is up
11770 01:03:30.477174 <6>[ 28.782503] Detected PIPT I-cache on CPU6
11771 01:03:30.483440 <6>[ 28.782525] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11772 01:03:30.493473 <6>[ 28.782540] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11773 01:03:30.494038 <6>[ 28.782794] CPU6 is up
11774 01:03:30.500110 <6>[ 28.782922] Detected PIPT I-cache on CPU7
11775 01:03:30.506492 <6>[ 28.782950] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11776 01:03:30.513433 <6>[ 28.782964] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11777 01:03:30.516811 <6>[ 28.783232] CPU7 is up
11778 01:03:30.519750 <6>[ 29.334384] OOM killer enabled.
11779 01:03:30.524149 <6>[ 29.337774] Restarting tasks ... done.
11780 01:03:30.529566 <5>[ 29.342151] random: crng reseeded on system resumption
11781 01:03:30.533421 <6>[ 29.348367] PM: suspend exit
11782 01:03:30.542217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11783 01:03:30.542774 + set +x
11784 01:03:30.543486 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11786 01:03:30.547799 <LAVA_SIGNAL_ENDRUN 0_sleep 12571095_1.5.2.3.1>
11787 01:03:30.548263 <LAVA_TEST_RUNNER EXIT>
11788 01:03:30.548890 Received signal: <ENDRUN> 0_sleep 12571095_1.5.2.3.1
11789 01:03:30.549322 Ending use of test pattern.
11790 01:03:30.549661 Ending test lava.0_sleep (12571095_1.5.2.3.1), duration 59.81
11792 01:03:30.550855 ok: lava_test_shell seems to have completed
11793 01:03:30.551735 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11794 01:03:30.552236 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11795 01:03:30.552701 end: 3 lava-test-retry (duration 00:01:00) [common]
11796 01:03:30.553177 start: 4 finalize (timeout 00:05:04) [common]
11797 01:03:30.553648 start: 4.1 power-off (timeout 00:00:30) [common]
11798 01:03:30.554449 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11799 01:03:30.640638 >> Command sent successfully.
11800 01:03:30.645066 Returned 0 in 0 seconds
11801 01:03:30.746021 end: 4.1 power-off (duration 00:00:00) [common]
11803 01:03:30.747551 start: 4.2 read-feedback (timeout 00:05:03) [common]
11804 01:03:30.748758 Listened to connection for namespace 'common' for up to 1s
11805 01:03:31.749502 Finalising connection for namespace 'common'
11806 01:03:31.750339 Disconnecting from shell: Finalise
11807 01:03:31.750812 / #
11808 01:03:31.851942 end: 4.2 read-feedback (duration 00:00:01) [common]
11809 01:03:31.852824 end: 4 finalize (duration 00:00:01) [common]
11810 01:03:31.853459 Cleaning after the job
11811 01:03:31.854033 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/ramdisk
11812 01:03:31.898797 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/kernel
11813 01:03:31.927515 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/dtb
11814 01:03:31.927748 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571095/tftp-deploy-b12l71ur/modules
11815 01:03:31.935050 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571095
11816 01:03:32.107061 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571095
11817 01:03:32.107243 Job finished correctly