Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 17
- Errors: 2
- Kernel Errors: 34
- Boot result: PASS
1 01:02:02.865557 lava-dispatcher, installed at version: 2023.10
2 01:02:02.865763 start: 0 validate
3 01:02:02.865891 Start time: 2024-01-19 01:02:02.865883+00:00 (UTC)
4 01:02:02.866036 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:02:02.866171 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 01:02:03.158522 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:02:03.159270 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:02:03.429230 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:02:03.430043 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:02:03.690879 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:02:03.691636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 01:02:03.959527 validate duration: 1.09
14 01:02:03.960872 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:02:03.961413 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:02:03.961914 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:02:03.962559 Not decompressing ramdisk as can be used compressed.
18 01:02:03.963035 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 01:02:03.963422 saving as /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/ramdisk/rootfs.cpio.gz
20 01:02:03.963787 total size: 26246609 (25 MB)
21 01:02:03.969048 progress 0 % (0 MB)
22 01:02:03.997668 progress 5 % (1 MB)
23 01:02:04.010157 progress 10 % (2 MB)
24 01:02:04.019401 progress 15 % (3 MB)
25 01:02:04.027062 progress 20 % (5 MB)
26 01:02:04.033783 progress 25 % (6 MB)
27 01:02:04.040316 progress 30 % (7 MB)
28 01:02:04.046793 progress 35 % (8 MB)
29 01:02:04.053399 progress 40 % (10 MB)
30 01:02:04.060059 progress 45 % (11 MB)
31 01:02:04.066634 progress 50 % (12 MB)
32 01:02:04.073283 progress 55 % (13 MB)
33 01:02:04.079834 progress 60 % (15 MB)
34 01:02:04.086465 progress 65 % (16 MB)
35 01:02:04.093025 progress 70 % (17 MB)
36 01:02:04.099564 progress 75 % (18 MB)
37 01:02:04.106087 progress 80 % (20 MB)
38 01:02:04.112565 progress 85 % (21 MB)
39 01:02:04.119133 progress 90 % (22 MB)
40 01:02:04.126360 progress 95 % (23 MB)
41 01:02:04.132813 progress 100 % (25 MB)
42 01:02:04.133053 25 MB downloaded in 0.17 s (147.86 MB/s)
43 01:02:04.133210 end: 1.1.1 http-download (duration 00:00:00) [common]
45 01:02:04.133455 end: 1.1 download-retry (duration 00:00:00) [common]
46 01:02:04.133542 start: 1.2 download-retry (timeout 00:10:00) [common]
47 01:02:04.133627 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 01:02:04.133746 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 01:02:04.133820 saving as /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/kernel/Image
50 01:02:04.133882 total size: 51532288 (49 MB)
51 01:02:04.133953 No compression specified
52 01:02:04.135076 progress 0 % (0 MB)
53 01:02:04.147717 progress 5 % (2 MB)
54 01:02:04.160467 progress 10 % (4 MB)
55 01:02:04.173319 progress 15 % (7 MB)
56 01:02:04.186104 progress 20 % (9 MB)
57 01:02:04.198937 progress 25 % (12 MB)
58 01:02:04.211462 progress 30 % (14 MB)
59 01:02:04.224298 progress 35 % (17 MB)
60 01:02:04.237047 progress 40 % (19 MB)
61 01:02:04.249521 progress 45 % (22 MB)
62 01:02:04.262181 progress 50 % (24 MB)
63 01:02:04.274951 progress 55 % (27 MB)
64 01:02:04.287769 progress 60 % (29 MB)
65 01:02:04.300583 progress 65 % (31 MB)
66 01:02:04.313108 progress 70 % (34 MB)
67 01:02:04.325924 progress 75 % (36 MB)
68 01:02:04.338716 progress 80 % (39 MB)
69 01:02:04.351171 progress 85 % (41 MB)
70 01:02:04.363864 progress 90 % (44 MB)
71 01:02:04.376615 progress 95 % (46 MB)
72 01:02:04.388930 progress 100 % (49 MB)
73 01:02:04.389127 49 MB downloaded in 0.26 s (192.54 MB/s)
74 01:02:04.389278 end: 1.2.1 http-download (duration 00:00:00) [common]
76 01:02:04.389508 end: 1.2 download-retry (duration 00:00:00) [common]
77 01:02:04.389598 start: 1.3 download-retry (timeout 00:10:00) [common]
78 01:02:04.389684 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 01:02:04.389822 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 01:02:04.389892 saving as /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/dtb/mt8192-asurada-spherion-r0.dtb
81 01:02:04.389996 total size: 47278 (0 MB)
82 01:02:04.390063 No compression specified
83 01:02:04.391268 progress 69 % (0 MB)
84 01:02:04.391535 progress 100 % (0 MB)
85 01:02:04.391686 0 MB downloaded in 0.00 s (26.70 MB/s)
86 01:02:04.391809 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:02:04.392032 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:02:04.392117 start: 1.4 download-retry (timeout 00:10:00) [common]
90 01:02:04.392200 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 01:02:04.392310 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 01:02:04.392379 saving as /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/modules/modules.tar
93 01:02:04.392459 total size: 8625444 (8 MB)
94 01:02:04.392533 Using unxz to decompress xz
95 01:02:04.396143 progress 0 % (0 MB)
96 01:02:04.417084 progress 5 % (0 MB)
97 01:02:04.439961 progress 10 % (0 MB)
98 01:02:04.462478 progress 15 % (1 MB)
99 01:02:04.485355 progress 20 % (1 MB)
100 01:02:04.508853 progress 25 % (2 MB)
101 01:02:04.533738 progress 30 % (2 MB)
102 01:02:04.558862 progress 35 % (2 MB)
103 01:02:04.581308 progress 40 % (3 MB)
104 01:02:04.604911 progress 45 % (3 MB)
105 01:02:04.629572 progress 50 % (4 MB)
106 01:02:04.653024 progress 55 % (4 MB)
107 01:02:04.676660 progress 60 % (4 MB)
108 01:02:04.703077 progress 65 % (5 MB)
109 01:02:04.727463 progress 70 % (5 MB)
110 01:02:04.749974 progress 75 % (6 MB)
111 01:02:04.775769 progress 80 % (6 MB)
112 01:02:04.800433 progress 85 % (7 MB)
113 01:02:04.824866 progress 90 % (7 MB)
114 01:02:04.855178 progress 95 % (7 MB)
115 01:02:04.884155 progress 100 % (8 MB)
116 01:02:04.889067 8 MB downloaded in 0.50 s (16.56 MB/s)
117 01:02:04.889304 end: 1.4.1 http-download (duration 00:00:00) [common]
119 01:02:04.889558 end: 1.4 download-retry (duration 00:00:00) [common]
120 01:02:04.889651 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 01:02:04.889746 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 01:02:04.889825 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:02:04.889908 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 01:02:04.890162 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8
125 01:02:04.890289 makedir: /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin
126 01:02:04.890393 makedir: /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/tests
127 01:02:04.890489 makedir: /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/results
128 01:02:04.890604 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-add-keys
129 01:02:04.890752 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-add-sources
130 01:02:04.890887 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-background-process-start
131 01:02:04.891017 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-background-process-stop
132 01:02:04.891140 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-common-functions
133 01:02:04.891262 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-echo-ipv4
134 01:02:04.891383 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-install-packages
135 01:02:04.891505 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-installed-packages
136 01:02:04.891625 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-os-build
137 01:02:04.891747 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-probe-channel
138 01:02:04.891866 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-probe-ip
139 01:02:04.891985 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-target-ip
140 01:02:04.892104 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-target-mac
141 01:02:04.892223 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-target-storage
142 01:02:04.892346 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-case
143 01:02:04.892467 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-event
144 01:02:04.892587 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-feedback
145 01:02:04.892708 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-raise
146 01:02:04.892828 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-reference
147 01:02:04.892947 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-runner
148 01:02:04.893065 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-set
149 01:02:04.893186 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-test-shell
150 01:02:04.893309 Updating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-install-packages (oe)
151 01:02:04.893457 Updating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/bin/lava-installed-packages (oe)
152 01:02:04.893575 Creating /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/environment
153 01:02:04.893673 LAVA metadata
154 01:02:04.893746 - LAVA_JOB_ID=12571123
155 01:02:04.893812 - LAVA_DISPATCHER_IP=192.168.201.1
156 01:02:04.893912 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 01:02:04.894027 skipped lava-vland-overlay
158 01:02:04.894105 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 01:02:04.894184 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 01:02:04.894252 skipped lava-multinode-overlay
161 01:02:04.894328 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 01:02:04.894421 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 01:02:04.894497 Loading test definitions
164 01:02:04.894588 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 01:02:04.894662 Using /lava-12571123 at stage 0
166 01:02:04.894953 uuid=12571123_1.5.2.3.1 testdef=None
167 01:02:04.895041 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 01:02:04.895125 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 01:02:04.895622 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 01:02:04.895846 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 01:02:04.896450 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 01:02:04.896685 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 01:02:04.897297 runner path: /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12571123_1.5.2.3.1
176 01:02:04.897447 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 01:02:04.897657 Creating lava-test-runner.conf files
179 01:02:04.897722 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571123/lava-overlay-26zc7_w8/lava-12571123/0 for stage 0
180 01:02:04.897809 - 0_v4l2-compliance-mtk-vcodec-enc
181 01:02:04.897906 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 01:02:04.898037 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 01:02:04.904452 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 01:02:04.904558 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 01:02:04.904643 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 01:02:04.904727 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 01:02:04.904818 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 01:02:05.559986 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 01:02:05.560356 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 01:02:05.560471 extracting modules file /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571123/extract-overlay-ramdisk-iysu2dxi/ramdisk
191 01:02:05.765919 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 01:02:05.766251 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 01:02:05.766396 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571123/compress-overlay-ym8f3u5k/overlay-1.5.2.4.tar.gz to ramdisk
194 01:02:05.766467 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571123/compress-overlay-ym8f3u5k/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571123/extract-overlay-ramdisk-iysu2dxi/ramdisk
195 01:02:05.772764 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 01:02:05.772879 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 01:02:05.772973 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 01:02:05.773065 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 01:02:05.773142 Building ramdisk /var/lib/lava/dispatcher/tmp/12571123/extract-overlay-ramdisk-iysu2dxi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571123/extract-overlay-ramdisk-iysu2dxi/ramdisk
200 01:02:06.346525 >> 228443 blocks
201 01:02:10.196116 rename /var/lib/lava/dispatcher/tmp/12571123/extract-overlay-ramdisk-iysu2dxi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/ramdisk/ramdisk.cpio.gz
202 01:02:10.196542 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 01:02:10.196668 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 01:02:10.196767 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 01:02:10.196870 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/kernel/Image'
206 01:02:22.266051 Returned 0 in 12 seconds
207 01:02:22.366999 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/kernel/image.itb
208 01:02:22.962289 output: FIT description: Kernel Image image with one or more FDT blobs
209 01:02:22.962642 output: Created: Fri Jan 19 01:02:22 2024
210 01:02:22.962718 output: Image 0 (kernel-1)
211 01:02:22.962785 output: Description:
212 01:02:22.962853 output: Created: Fri Jan 19 01:02:22 2024
213 01:02:22.962916 output: Type: Kernel Image
214 01:02:22.962976 output: Compression: lzma compressed
215 01:02:22.963036 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
216 01:02:22.963093 output: Architecture: AArch64
217 01:02:22.963154 output: OS: Linux
218 01:02:22.963211 output: Load Address: 0x00000000
219 01:02:22.963266 output: Entry Point: 0x00000000
220 01:02:22.963320 output: Hash algo: crc32
221 01:02:22.963376 output: Hash value: a52aa383
222 01:02:22.963433 output: Image 1 (fdt-1)
223 01:02:22.963489 output: Description: mt8192-asurada-spherion-r0
224 01:02:22.963543 output: Created: Fri Jan 19 01:02:22 2024
225 01:02:22.963596 output: Type: Flat Device Tree
226 01:02:22.963649 output: Compression: uncompressed
227 01:02:22.963703 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 01:02:22.963756 output: Architecture: AArch64
229 01:02:22.963810 output: Hash algo: crc32
230 01:02:22.963863 output: Hash value: cc4352de
231 01:02:22.963916 output: Image 2 (ramdisk-1)
232 01:02:22.963970 output: Description: unavailable
233 01:02:22.964022 output: Created: Fri Jan 19 01:02:22 2024
234 01:02:22.964076 output: Type: RAMDisk Image
235 01:02:22.964129 output: Compression: Unknown Compression
236 01:02:22.964182 output: Data Size: 39373745 Bytes = 38450.92 KiB = 37.55 MiB
237 01:02:22.964243 output: Architecture: AArch64
238 01:02:22.964301 output: OS: Linux
239 01:02:22.964355 output: Load Address: unavailable
240 01:02:22.964408 output: Entry Point: unavailable
241 01:02:22.964461 output: Hash algo: crc32
242 01:02:22.964514 output: Hash value: 4f6c6ab3
243 01:02:22.964567 output: Default Configuration: 'conf-1'
244 01:02:22.964620 output: Configuration 0 (conf-1)
245 01:02:22.964674 output: Description: mt8192-asurada-spherion-r0
246 01:02:22.964726 output: Kernel: kernel-1
247 01:02:22.964779 output: Init Ramdisk: ramdisk-1
248 01:02:22.964832 output: FDT: fdt-1
249 01:02:22.964885 output: Loadables: kernel-1
250 01:02:22.964938 output:
251 01:02:22.965122 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 01:02:22.965222 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 01:02:22.965320 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 01:02:22.965413 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 01:02:22.965493 No LXC device requested
256 01:02:22.965573 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 01:02:22.965658 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 01:02:22.965735 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 01:02:22.965806 Checking files for TFTP limit of 4294967296 bytes.
260 01:02:22.966341 end: 1 tftp-deploy (duration 00:00:19) [common]
261 01:02:22.966444 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 01:02:22.966537 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 01:02:22.966658 substitutions:
264 01:02:22.966725 - {DTB}: 12571123/tftp-deploy-vb3mdyvn/dtb/mt8192-asurada-spherion-r0.dtb
265 01:02:22.966791 - {INITRD}: 12571123/tftp-deploy-vb3mdyvn/ramdisk/ramdisk.cpio.gz
266 01:02:22.966851 - {KERNEL}: 12571123/tftp-deploy-vb3mdyvn/kernel/Image
267 01:02:22.966908 - {LAVA_MAC}: None
268 01:02:22.966964 - {PRESEED_CONFIG}: None
269 01:02:22.967020 - {PRESEED_LOCAL}: None
270 01:02:22.967074 - {RAMDISK}: 12571123/tftp-deploy-vb3mdyvn/ramdisk/ramdisk.cpio.gz
271 01:02:22.967130 - {ROOT_PART}: None
272 01:02:22.967185 - {ROOT}: None
273 01:02:22.967240 - {SERVER_IP}: 192.168.201.1
274 01:02:22.967295 - {TEE}: None
275 01:02:22.967349 Parsed boot commands:
276 01:02:22.967406 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 01:02:22.967579 Parsed boot commands: tftpboot 192.168.201.1 12571123/tftp-deploy-vb3mdyvn/kernel/image.itb 12571123/tftp-deploy-vb3mdyvn/kernel/cmdline
278 01:02:22.967668 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 01:02:22.967758 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 01:02:22.967850 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 01:02:22.967934 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 01:02:22.968004 Not connected, no need to disconnect.
283 01:02:22.968078 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 01:02:22.968157 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 01:02:22.968223 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 01:02:22.971483 Setting prompt string to ['lava-test: # ']
287 01:02:22.971805 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 01:02:22.971912 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 01:02:22.972022 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 01:02:22.972174 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 01:02:22.972410 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 01:02:28.105399 >> Command sent successfully.
293 01:02:28.111492 Returned 0 in 5 seconds
294 01:02:28.212242 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 01:02:28.213711 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 01:02:28.214308 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 01:02:28.214795 Setting prompt string to 'Starting depthcharge on Spherion...'
299 01:02:28.215184 Changing prompt to 'Starting depthcharge on Spherion...'
300 01:02:28.215588 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 01:02:28.216868 [Enter `^Ec?' for help]
302 01:02:28.382467
303 01:02:28.383019
304 01:02:28.383382 F0: 102B 0000
305 01:02:28.383731
306 01:02:28.384045 F3: 1001 0000 [0200]
307 01:02:28.385507
308 01:02:28.385976 F3: 1001 0000
309 01:02:28.386337
310 01:02:28.386660 F7: 102D 0000
311 01:02:28.387112
312 01:02:28.388861 F1: 0000 0000
313 01:02:28.389299
314 01:02:28.389643 V0: 0000 0000 [0001]
315 01:02:28.390001
316 01:02:28.392221 00: 0007 8000
317 01:02:28.392719
318 01:02:28.393071 01: 0000 0000
319 01:02:28.393399
320 01:02:28.395777 BP: 0C00 0209 [0000]
321 01:02:28.396318
322 01:02:28.396668 G0: 1182 0000
323 01:02:28.396994
324 01:02:28.399544 EC: 0000 0021 [4000]
325 01:02:28.400086
326 01:02:28.400436 S7: 0000 0000 [0000]
327 01:02:28.400768
328 01:02:28.403083 CC: 0000 0000 [0001]
329 01:02:28.403519
330 01:02:28.403862 T0: 0000 0040 [010F]
331 01:02:28.404250
332 01:02:28.404572 Jump to BL
333 01:02:28.404879
334 01:02:28.429329
335 01:02:28.429859
336 01:02:28.430255
337 01:02:28.436177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 01:02:28.440243 ARM64: Exception handlers installed.
339 01:02:28.443402 ARM64: Testing exception
340 01:02:28.446655 ARM64: Done test exception
341 01:02:28.453531 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 01:02:28.464217 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 01:02:28.470470 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 01:02:28.480463 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 01:02:28.486723 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 01:02:28.497448 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 01:02:28.507977 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 01:02:28.515374 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 01:02:28.532398 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 01:02:28.535290 WDT: Last reset was cold boot
351 01:02:28.539010 SPI1(PAD0) initialized at 2873684 Hz
352 01:02:28.542133 SPI5(PAD0) initialized at 992727 Hz
353 01:02:28.545503 VBOOT: Loading verstage.
354 01:02:28.552161 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 01:02:28.555770 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 01:02:28.558981 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 01:02:28.562540 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 01:02:28.570001 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 01:02:28.576629 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 01:02:28.587058 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 01:02:28.587627
362 01:02:28.588012
363 01:02:28.597660 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 01:02:28.600941 ARM64: Exception handlers installed.
365 01:02:28.603972 ARM64: Testing exception
366 01:02:28.604560 ARM64: Done test exception
367 01:02:28.610354 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 01:02:28.614403 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 01:02:28.628608 Probing TPM: . done!
370 01:02:28.629198 TPM ready after 0 ms
371 01:02:28.635127 Connected to device vid:did:rid of 1ae0:0028:00
372 01:02:28.642252 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 01:02:28.699488 Initialized TPM device CR50 revision 0
374 01:02:28.711663 tlcl_send_startup: Startup return code is 0
375 01:02:28.712249 TPM: setup succeeded
376 01:02:28.722924 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 01:02:28.732122 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 01:02:28.741577 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 01:02:28.750868 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 01:02:28.754029 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 01:02:28.761748 in-header: 03 07 00 00 08 00 00 00
382 01:02:28.765726 in-data: aa e4 47 04 13 02 00 00
383 01:02:28.769640 Chrome EC: UHEPI supported
384 01:02:28.776205 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 01:02:28.779928 in-header: 03 ad 00 00 08 00 00 00
386 01:02:28.783363 in-data: 00 20 20 08 00 00 00 00
387 01:02:28.783978 Phase 1
388 01:02:28.786763 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 01:02:28.794471 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 01:02:28.798076 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 01:02:28.802302 Recovery requested (1009000e)
392 01:02:28.811166 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 01:02:28.816581 tlcl_extend: response is 0
394 01:02:28.825709 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 01:02:28.831141 tlcl_extend: response is 0
396 01:02:28.838340 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 01:02:28.858835 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 01:02:28.865734 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 01:02:28.866382
400 01:02:28.866777
401 01:02:28.875823 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 01:02:28.878950 ARM64: Exception handlers installed.
403 01:02:28.879539 ARM64: Testing exception
404 01:02:28.882294 ARM64: Done test exception
405 01:02:28.903793 pmic_efuse_setting: Set efuses in 11 msecs
406 01:02:28.907396 pmwrap_interface_init: Select PMIF_VLD_RDY
407 01:02:28.914092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 01:02:28.918126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 01:02:28.921044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 01:02:28.927881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 01:02:28.930766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 01:02:28.938432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 01:02:28.941915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 01:02:28.945350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 01:02:28.952791 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 01:02:28.957045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 01:02:28.960652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 01:02:28.964245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 01:02:28.970960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 01:02:28.974791 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 01:02:28.980982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 01:02:28.988099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 01:02:28.991850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 01:02:28.999431 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 01:02:29.003220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 01:02:29.010073 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 01:02:29.017296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 01:02:29.021040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 01:02:29.027157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 01:02:29.030582 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 01:02:29.037775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 01:02:29.043869 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 01:02:29.047261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 01:02:29.054424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 01:02:29.057230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 01:02:29.060342 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 01:02:29.067676 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 01:02:29.074101 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 01:02:29.077504 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 01:02:29.084392 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 01:02:29.087692 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 01:02:29.094584 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 01:02:29.097455 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 01:02:29.101061 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 01:02:29.107353 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 01:02:29.110644 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 01:02:29.114570 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 01:02:29.121861 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 01:02:29.125219 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 01:02:29.128427 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 01:02:29.134622 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 01:02:29.138760 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 01:02:29.142265 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 01:02:29.145530 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 01:02:29.149396 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 01:02:29.152873 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 01:02:29.156773 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 01:02:29.167504 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 01:02:29.175519 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 01:02:29.178369 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 01:02:29.189133 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 01:02:29.196135 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 01:02:29.199842 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 01:02:29.206394 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 01:02:29.209647 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 01:02:29.216456 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x3a
467 01:02:29.223187 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 01:02:29.226234 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 01:02:29.229975 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 01:02:29.241450 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 01:02:29.250466 [RTC]rtc_get_frequency_meter,154: input=23, output=959
472 01:02:29.260189 [RTC]rtc_get_frequency_meter,154: input=19, output=866
473 01:02:29.269550 [RTC]rtc_get_frequency_meter,154: input=17, output=820
474 01:02:29.279159 [RTC]rtc_get_frequency_meter,154: input=16, output=797
475 01:02:29.288297 [RTC]rtc_get_frequency_meter,154: input=15, output=774
476 01:02:29.298316 [RTC]rtc_get_frequency_meter,154: input=16, output=795
477 01:02:29.301185 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 01:02:29.308162 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 01:02:29.311735 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 01:02:29.315120 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 01:02:29.322037 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 01:02:29.325398 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 01:02:29.328971 ADC[4]: Raw value=902507 ID=7
484 01:02:29.329551 ADC[3]: Raw value=213179 ID=1
485 01:02:29.331893 RAM Code: 0x71
486 01:02:29.335396 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 01:02:29.342148 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 01:02:29.348505 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 01:02:29.355115 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 01:02:29.358159 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 01:02:29.361719 in-header: 03 07 00 00 08 00 00 00
492 01:02:29.364934 in-data: aa e4 47 04 13 02 00 00
493 01:02:29.368342 Chrome EC: UHEPI supported
494 01:02:29.374960 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 01:02:29.378216 in-header: 03 ed 00 00 08 00 00 00
496 01:02:29.381978 in-data: 80 20 60 08 00 00 00 00
497 01:02:29.385249 MRC: failed to locate region type 0.
498 01:02:29.392303 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 01:02:29.395319 DRAM-K: Running full calibration
500 01:02:29.401512 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 01:02:29.402045 header.status = 0x0
502 01:02:29.405088 header.version = 0x6 (expected: 0x6)
503 01:02:29.408135 header.size = 0xd00 (expected: 0xd00)
504 01:02:29.411699 header.flags = 0x0
505 01:02:29.418074 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 01:02:29.434720 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 01:02:29.441561 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 01:02:29.444627 dram_init: ddr_geometry: 2
509 01:02:29.448346 [EMI] MDL number = 2
510 01:02:29.448929 [EMI] Get MDL freq = 0
511 01:02:29.451409 dram_init: ddr_type: 0
512 01:02:29.451988 is_discrete_lpddr4: 1
513 01:02:29.454547 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 01:02:29.455127
515 01:02:29.455508
516 01:02:29.458106 [Bian_co] ETT version 0.0.0.1
517 01:02:29.464745 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 01:02:29.465327
519 01:02:29.468074 dramc_set_vcore_voltage set vcore to 650000
520 01:02:29.468650 Read voltage for 800, 4
521 01:02:29.471625 Vio18 = 0
522 01:02:29.472209 Vcore = 650000
523 01:02:29.472594 Vdram = 0
524 01:02:29.474430 Vddq = 0
525 01:02:29.474911 Vmddr = 0
526 01:02:29.478022 dram_init: config_dvfs: 1
527 01:02:29.481148 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 01:02:29.487928 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 01:02:29.491260 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
530 01:02:29.495043 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
531 01:02:29.497808 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 01:02:29.501147 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 01:02:29.504414 MEM_TYPE=3, freq_sel=18
534 01:02:29.507868 sv_algorithm_assistance_LP4_1600
535 01:02:29.511765 ============ PULL DRAM RESETB DOWN ============
536 01:02:29.514609 ========== PULL DRAM RESETB DOWN end =========
537 01:02:29.521401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 01:02:29.524988 ===================================
539 01:02:29.525574 LPDDR4 DRAM CONFIGURATION
540 01:02:29.528232 ===================================
541 01:02:29.531719 EX_ROW_EN[0] = 0x0
542 01:02:29.534815 EX_ROW_EN[1] = 0x0
543 01:02:29.535399 LP4Y_EN = 0x0
544 01:02:29.538141 WORK_FSP = 0x0
545 01:02:29.538719 WL = 0x2
546 01:02:29.541608 RL = 0x2
547 01:02:29.542229 BL = 0x2
548 01:02:29.544785 RPST = 0x0
549 01:02:29.545360 RD_PRE = 0x0
550 01:02:29.548348 WR_PRE = 0x1
551 01:02:29.548931 WR_PST = 0x0
552 01:02:29.551307 DBI_WR = 0x0
553 01:02:29.551807 DBI_RD = 0x0
554 01:02:29.554971 OTF = 0x1
555 01:02:29.558360 ===================================
556 01:02:29.561244 ===================================
557 01:02:29.561757 ANA top config
558 01:02:29.564586 ===================================
559 01:02:29.568363 DLL_ASYNC_EN = 0
560 01:02:29.571125 ALL_SLAVE_EN = 1
561 01:02:29.571628 NEW_RANK_MODE = 1
562 01:02:29.574627 DLL_IDLE_MODE = 1
563 01:02:29.578170 LP45_APHY_COMB_EN = 1
564 01:02:29.581400 TX_ODT_DIS = 1
565 01:02:29.584760 NEW_8X_MODE = 1
566 01:02:29.587921 ===================================
567 01:02:29.588365 ===================================
568 01:02:29.591326 data_rate = 1600
569 01:02:29.594750 CKR = 1
570 01:02:29.597998 DQ_P2S_RATIO = 8
571 01:02:29.601475 ===================================
572 01:02:29.605036 CA_P2S_RATIO = 8
573 01:02:29.608017 DQ_CA_OPEN = 0
574 01:02:29.608482 DQ_SEMI_OPEN = 0
575 01:02:29.611719 CA_SEMI_OPEN = 0
576 01:02:29.614701 CA_FULL_RATE = 0
577 01:02:29.618305 DQ_CKDIV4_EN = 1
578 01:02:29.622015 CA_CKDIV4_EN = 1
579 01:02:29.625866 CA_PREDIV_EN = 0
580 01:02:29.626540 PH8_DLY = 0
581 01:02:29.629317 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 01:02:29.633091 DQ_AAMCK_DIV = 4
583 01:02:29.636396 CA_AAMCK_DIV = 4
584 01:02:29.636844 CA_ADMCK_DIV = 4
585 01:02:29.640605 DQ_TRACK_CA_EN = 0
586 01:02:29.643857 CA_PICK = 800
587 01:02:29.647539 CA_MCKIO = 800
588 01:02:29.648138 MCKIO_SEMI = 0
589 01:02:29.651189 PLL_FREQ = 3068
590 01:02:29.654897 DQ_UI_PI_RATIO = 32
591 01:02:29.658350 CA_UI_PI_RATIO = 0
592 01:02:29.661748 ===================================
593 01:02:29.665891 ===================================
594 01:02:29.666557 memory_type:LPDDR4
595 01:02:29.669641 GP_NUM : 10
596 01:02:29.670318 SRAM_EN : 1
597 01:02:29.673299 MD32_EN : 0
598 01:02:29.677210 ===================================
599 01:02:29.677800 [ANA_INIT] >>>>>>>>>>>>>>
600 01:02:29.680599 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 01:02:29.684070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 01:02:29.687734 ===================================
603 01:02:29.691496 data_rate = 1600,PCW = 0X7600
604 01:02:29.695351 ===================================
605 01:02:29.699272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 01:02:29.702600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 01:02:29.710384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 01:02:29.714006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 01:02:29.717538 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 01:02:29.721876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 01:02:29.722522 [ANA_INIT] flow start
612 01:02:29.725277 [ANA_INIT] PLL >>>>>>>>
613 01:02:29.725761 [ANA_INIT] PLL <<<<<<<<
614 01:02:29.728571 [ANA_INIT] MIDPI >>>>>>>>
615 01:02:29.732789 [ANA_INIT] MIDPI <<<<<<<<
616 01:02:29.733539 [ANA_INIT] DLL >>>>>>>>
617 01:02:29.736540 [ANA_INIT] flow end
618 01:02:29.740494 ============ LP4 DIFF to SE enter ============
619 01:02:29.743819 ============ LP4 DIFF to SE exit ============
620 01:02:29.747580 [ANA_INIT] <<<<<<<<<<<<<
621 01:02:29.751356 [Flow] Enable top DCM control >>>>>
622 01:02:29.752104 [Flow] Enable top DCM control <<<<<
623 01:02:29.755186 Enable DLL master slave shuffle
624 01:02:29.762431 ==============================================================
625 01:02:29.762874 Gating Mode config
626 01:02:29.769630 ==============================================================
627 01:02:29.770389 Config description:
628 01:02:29.780721 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 01:02:29.787974 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 01:02:29.791680 SELPH_MODE 0: By rank 1: By Phase
631 01:02:29.795250 ==============================================================
632 01:02:29.799209 GAT_TRACK_EN = 1
633 01:02:29.803044 RX_GATING_MODE = 2
634 01:02:29.806742 RX_GATING_TRACK_MODE = 2
635 01:02:29.810225 SELPH_MODE = 1
636 01:02:29.810854 PICG_EARLY_EN = 1
637 01:02:29.814097 VALID_LAT_VALUE = 1
638 01:02:29.821825 ==============================================================
639 01:02:29.825449 Enter into Gating configuration >>>>
640 01:02:29.826083 Exit from Gating configuration <<<<
641 01:02:29.829129 Enter into DVFS_PRE_config >>>>>
642 01:02:29.840608 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 01:02:29.844450 Exit from DVFS_PRE_config <<<<<
644 01:02:29.848154 Enter into PICG configuration >>>>
645 01:02:29.851616 Exit from PICG configuration <<<<
646 01:02:29.852211 [RX_INPUT] configuration >>>>>
647 01:02:29.855251 [RX_INPUT] configuration <<<<<
648 01:02:29.862833 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 01:02:29.866600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 01:02:29.874434 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 01:02:29.877824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 01:02:29.885309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 01:02:29.892649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 01:02:29.896311 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 01:02:29.900538 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 01:02:29.903818 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 01:02:29.907537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 01:02:29.911148 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 01:02:29.915062 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 01:02:29.918407 ===================================
661 01:02:29.921895 LPDDR4 DRAM CONFIGURATION
662 01:02:29.925821 ===================================
663 01:02:29.926439 EX_ROW_EN[0] = 0x0
664 01:02:29.929327 EX_ROW_EN[1] = 0x0
665 01:02:29.930103 LP4Y_EN = 0x0
666 01:02:29.932965 WORK_FSP = 0x0
667 01:02:29.933481 WL = 0x2
668 01:02:29.936936 RL = 0x2
669 01:02:29.937414 BL = 0x2
670 01:02:29.940527 RPST = 0x0
671 01:02:29.941112 RD_PRE = 0x0
672 01:02:29.944303 WR_PRE = 0x1
673 01:02:29.944779 WR_PST = 0x0
674 01:02:29.947769 DBI_WR = 0x0
675 01:02:29.948367 DBI_RD = 0x0
676 01:02:29.951646 OTF = 0x1
677 01:02:29.952224 ===================================
678 01:02:29.955477 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 01:02:29.962721 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 01:02:29.966773 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 01:02:29.970151 ===================================
682 01:02:29.970684 LPDDR4 DRAM CONFIGURATION
683 01:02:29.973440 ===================================
684 01:02:29.976904 EX_ROW_EN[0] = 0x10
685 01:02:29.980196 EX_ROW_EN[1] = 0x0
686 01:02:29.980733 LP4Y_EN = 0x0
687 01:02:29.983489 WORK_FSP = 0x0
688 01:02:29.984023 WL = 0x2
689 01:02:29.986598 RL = 0x2
690 01:02:29.987029 BL = 0x2
691 01:02:29.989862 RPST = 0x0
692 01:02:29.990430 RD_PRE = 0x0
693 01:02:29.993468 WR_PRE = 0x1
694 01:02:29.993977 WR_PST = 0x0
695 01:02:29.996604 DBI_WR = 0x0
696 01:02:29.997182 DBI_RD = 0x0
697 01:02:30.000372 OTF = 0x1
698 01:02:30.003364 ===================================
699 01:02:30.009891 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 01:02:30.013184 nWR fixed to 40
701 01:02:30.013665 [ModeRegInit_LP4] CH0 RK0
702 01:02:30.016759 [ModeRegInit_LP4] CH0 RK1
703 01:02:30.020665 [ModeRegInit_LP4] CH1 RK0
704 01:02:30.023316 [ModeRegInit_LP4] CH1 RK1
705 01:02:30.023902 match AC timing 13
706 01:02:30.026495 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 01:02:30.033337 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 01:02:30.036601 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 01:02:30.040130 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 01:02:30.046847 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 01:02:30.047437 [EMI DOE] emi_dcm 0
712 01:02:30.053400 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 01:02:30.054034 ==
714 01:02:30.056841 Dram Type= 6, Freq= 0, CH_0, rank 0
715 01:02:30.060028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 01:02:30.060509 ==
717 01:02:30.066847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 01:02:30.070391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 01:02:30.080443 [CA 0] Center 38 (7~69) winsize 63
720 01:02:30.083810 [CA 1] Center 38 (7~69) winsize 63
721 01:02:30.086989 [CA 2] Center 35 (5~66) winsize 62
722 01:02:30.090574 [CA 3] Center 35 (5~66) winsize 62
723 01:02:30.093862 [CA 4] Center 34 (4~65) winsize 62
724 01:02:30.097471 [CA 5] Center 33 (3~64) winsize 62
725 01:02:30.098105
726 01:02:30.100535 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 01:02:30.101118
728 01:02:30.103751 [CATrainingPosCal] consider 1 rank data
729 01:02:30.106745 u2DelayCellTimex100 = 270/100 ps
730 01:02:30.110066 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 01:02:30.114119 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
732 01:02:30.120473 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 01:02:30.123604 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 01:02:30.127031 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 01:02:30.130223 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 01:02:30.130704
737 01:02:30.133621 CA PerBit enable=1, Macro0, CA PI delay=33
738 01:02:30.134234
739 01:02:30.136975 [CBTSetCACLKResult] CA Dly = 33
740 01:02:30.137456 CS Dly: 6 (0~37)
741 01:02:30.140409 ==
742 01:02:30.140888 Dram Type= 6, Freq= 0, CH_0, rank 1
743 01:02:30.146859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 01:02:30.147465 ==
745 01:02:30.153748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 01:02:30.157178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 01:02:30.167249 [CA 0] Center 38 (7~69) winsize 63
748 01:02:30.170287 [CA 1] Center 38 (8~69) winsize 62
749 01:02:30.173252 [CA 2] Center 36 (6~67) winsize 62
750 01:02:30.177266 [CA 3] Center 35 (5~66) winsize 62
751 01:02:30.180260 [CA 4] Center 35 (4~66) winsize 63
752 01:02:30.183738 [CA 5] Center 34 (4~65) winsize 62
753 01:02:30.184331
754 01:02:30.187285 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 01:02:30.187876
756 01:02:30.190390 [CATrainingPosCal] consider 2 rank data
757 01:02:30.194056 u2DelayCellTimex100 = 270/100 ps
758 01:02:30.196840 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
759 01:02:30.200262 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
760 01:02:30.207007 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
761 01:02:30.210226 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
762 01:02:30.213915 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
763 01:02:30.217182 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 01:02:30.217769
765 01:02:30.221372 CA PerBit enable=1, Macro0, CA PI delay=34
766 01:02:30.222002
767 01:02:30.223932 [CBTSetCACLKResult] CA Dly = 34
768 01:02:30.224518 CS Dly: 6 (0~38)
769 01:02:30.224901
770 01:02:30.226818 ----->DramcWriteLeveling(PI) begin...
771 01:02:30.227325 ==
772 01:02:30.230331 Dram Type= 6, Freq= 0, CH_0, rank 0
773 01:02:30.236790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 01:02:30.237379 ==
775 01:02:30.240440 Write leveling (Byte 0): 30 => 30
776 01:02:30.243713 Write leveling (Byte 1): 29 => 29
777 01:02:30.244198 DramcWriteLeveling(PI) end<-----
778 01:02:30.246803
779 01:02:30.247380 ==
780 01:02:30.250377 Dram Type= 6, Freq= 0, CH_0, rank 0
781 01:02:30.257307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 01:02:30.257896 ==
783 01:02:30.258339 [Gating] SW mode calibration
784 01:02:30.263807 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 01:02:30.267687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 01:02:30.271239 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 01:02:30.278710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 01:02:30.281849 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 01:02:30.285584 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 01:02:30.288864 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 01:02:30.296028 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 01:02:30.299741 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 01:02:30.302977 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 01:02:30.309556 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 01:02:30.312766 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 01:02:30.316202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 01:02:30.319418 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 01:02:30.326294 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 01:02:30.329640 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 01:02:30.333077 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 01:02:30.339495 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 01:02:30.342636 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 01:02:30.346000 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 01:02:30.353236 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 01:02:30.356104 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 01:02:30.359472 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 01:02:30.365932 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 01:02:30.369455 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 01:02:30.372472 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 01:02:30.379466 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 01:02:30.382820 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
812 01:02:30.386606 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
813 01:02:30.392993 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
814 01:02:30.395951 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 01:02:30.399861 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 01:02:30.402680 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 01:02:30.409603 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 01:02:30.412776 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 01:02:30.416519 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
820 01:02:30.422905 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
821 01:02:30.426699 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
822 01:02:30.429516 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 01:02:30.436337 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 01:02:30.439647 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 01:02:30.443063 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:02:30.449328 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:02:30.453135 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
828 01:02:30.456118 0 11 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
829 01:02:30.463868 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
830 01:02:30.466599 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 01:02:30.469733 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 01:02:30.476406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 01:02:30.479342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:02:30.482756 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:02:30.489658 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 01:02:30.492968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 01:02:30.496221 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 01:02:30.499781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 01:02:30.506039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 01:02:30.510158 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 01:02:30.512770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:02:30.519617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:02:30.522731 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:02:30.526633 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:02:30.533050 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:02:30.536716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:02:30.539962 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:02:30.546513 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:02:30.549994 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:02:30.552945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:02:30.559357 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 01:02:30.562934 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 01:02:30.566595 Total UI for P1: 0, mck2ui 16
854 01:02:30.570054 best dqsien dly found for B0: ( 0, 14, 4)
855 01:02:30.573082 Total UI for P1: 0, mck2ui 16
856 01:02:30.576565 best dqsien dly found for B1: ( 0, 14, 6)
857 01:02:30.579996 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 01:02:30.583238 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
859 01:02:30.583725
860 01:02:30.586207 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 01:02:30.590028 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 01:02:30.592965 [Gating] SW calibration Done
863 01:02:30.593448 ==
864 01:02:30.596563 Dram Type= 6, Freq= 0, CH_0, rank 0
865 01:02:30.599658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 01:02:30.600146 ==
867 01:02:30.603224 RX Vref Scan: 0
868 01:02:30.603708
869 01:02:30.604090 RX Vref 0 -> 0, step: 1
870 01:02:30.604445
871 01:02:30.606314 RX Delay -130 -> 252, step: 16
872 01:02:30.613403 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 01:02:30.616368 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 01:02:30.619691 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 01:02:30.623088 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
876 01:02:30.626468 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 01:02:30.630086 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 01:02:30.636684 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
879 01:02:30.640026 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
880 01:02:30.643317 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
881 01:02:30.647027 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
882 01:02:30.650157 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 01:02:30.656527 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 01:02:30.659552 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
885 01:02:30.663030 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
886 01:02:30.666416 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
887 01:02:30.672927 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
888 01:02:30.673414 ==
889 01:02:30.676759 Dram Type= 6, Freq= 0, CH_0, rank 0
890 01:02:30.680111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 01:02:30.680648 ==
892 01:02:30.681004 DQS Delay:
893 01:02:30.683321 DQS0 = 0, DQS1 = 0
894 01:02:30.683801 DQM Delay:
895 01:02:30.686631 DQM0 = 92, DQM1 = 80
896 01:02:30.687233 DQ Delay:
897 01:02:30.689539 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =93
898 01:02:30.693213 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
899 01:02:30.696607 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
900 01:02:30.699606 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
901 01:02:30.700096
902 01:02:30.700481
903 01:02:30.700838 ==
904 01:02:30.702871 Dram Type= 6, Freq= 0, CH_0, rank 0
905 01:02:30.706583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 01:02:30.707071 ==
907 01:02:30.707462
908 01:02:30.707820
909 01:02:30.709504 TX Vref Scan disable
910 01:02:30.713277 == TX Byte 0 ==
911 01:02:30.716898 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
912 01:02:30.719800 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
913 01:02:30.723158 == TX Byte 1 ==
914 01:02:30.726522 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
915 01:02:30.730005 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
916 01:02:30.730539 ==
917 01:02:30.733181 Dram Type= 6, Freq= 0, CH_0, rank 0
918 01:02:30.739715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 01:02:30.740246 ==
920 01:02:30.751734 TX Vref=22, minBit 8, minWin=26, winSum=438
921 01:02:30.754828 TX Vref=24, minBit 1, minWin=27, winSum=445
922 01:02:30.757771 TX Vref=26, minBit 6, minWin=27, winSum=449
923 01:02:30.761804 TX Vref=28, minBit 6, minWin=27, winSum=448
924 01:02:30.764935 TX Vref=30, minBit 6, minWin=27, winSum=450
925 01:02:30.768116 TX Vref=32, minBit 11, minWin=27, winSum=453
926 01:02:30.774539 [TxChooseVref] Worse bit 11, Min win 27, Win sum 453, Final Vref 32
927 01:02:30.775124
928 01:02:30.778210 Final TX Range 1 Vref 32
929 01:02:30.778799
930 01:02:30.779187 ==
931 01:02:30.781326 Dram Type= 6, Freq= 0, CH_0, rank 0
932 01:02:30.784355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 01:02:30.784841 ==
934 01:02:30.787938
935 01:02:30.788517
936 01:02:30.788904 TX Vref Scan disable
937 01:02:30.791403 == TX Byte 0 ==
938 01:02:30.794477 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 01:02:30.797825 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 01:02:30.801117 == TX Byte 1 ==
941 01:02:30.804844 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
942 01:02:30.807912 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
943 01:02:30.811113
944 01:02:30.811724 [DATLAT]
945 01:02:30.812094 Freq=800, CH0 RK0
946 01:02:30.812428
947 01:02:30.814437 DATLAT Default: 0xa
948 01:02:30.814873 0, 0xFFFF, sum = 0
949 01:02:30.818086 1, 0xFFFF, sum = 0
950 01:02:30.818530 2, 0xFFFF, sum = 0
951 01:02:30.821198 3, 0xFFFF, sum = 0
952 01:02:30.821640 4, 0xFFFF, sum = 0
953 01:02:30.824958 5, 0xFFFF, sum = 0
954 01:02:30.825495 6, 0xFFFF, sum = 0
955 01:02:30.828239 7, 0xFFFF, sum = 0
956 01:02:30.828777 8, 0xFFFF, sum = 0
957 01:02:30.832024 9, 0x0, sum = 1
958 01:02:30.832566 10, 0x0, sum = 2
959 01:02:30.834797 11, 0x0, sum = 3
960 01:02:30.835337 12, 0x0, sum = 4
961 01:02:30.838262 best_step = 10
962 01:02:30.838791
963 01:02:30.839145 ==
964 01:02:30.841870 Dram Type= 6, Freq= 0, CH_0, rank 0
965 01:02:30.844876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 01:02:30.845410 ==
967 01:02:30.848422 RX Vref Scan: 1
968 01:02:30.848956
969 01:02:30.849308 Set Vref Range= 32 -> 127
970 01:02:30.849635
971 01:02:30.851958 RX Vref 32 -> 127, step: 1
972 01:02:30.852490
973 01:02:30.854774 RX Delay -95 -> 252, step: 8
974 01:02:30.855282
975 01:02:30.858139 Set Vref, RX VrefLevel [Byte0]: 32
976 01:02:30.861795 [Byte1]: 32
977 01:02:30.862263
978 01:02:30.865184 Set Vref, RX VrefLevel [Byte0]: 33
979 01:02:30.868621 [Byte1]: 33
980 01:02:30.871850
981 01:02:30.872382 Set Vref, RX VrefLevel [Byte0]: 34
982 01:02:30.875011 [Byte1]: 34
983 01:02:30.879035
984 01:02:30.879566 Set Vref, RX VrefLevel [Byte0]: 35
985 01:02:30.882741 [Byte1]: 35
986 01:02:30.887248
987 01:02:30.887816 Set Vref, RX VrefLevel [Byte0]: 36
988 01:02:30.890501 [Byte1]: 36
989 01:02:30.894517
990 01:02:30.895189 Set Vref, RX VrefLevel [Byte0]: 37
991 01:02:30.897691 [Byte1]: 37
992 01:02:30.901933
993 01:02:30.902498 Set Vref, RX VrefLevel [Byte0]: 38
994 01:02:30.905603 [Byte1]: 38
995 01:02:30.909627
996 01:02:30.910197 Set Vref, RX VrefLevel [Byte0]: 39
997 01:02:30.912683 [Byte1]: 39
998 01:02:30.917252
999 01:02:30.917785 Set Vref, RX VrefLevel [Byte0]: 40
1000 01:02:30.920744 [Byte1]: 40
1001 01:02:30.924637
1002 01:02:30.925184 Set Vref, RX VrefLevel [Byte0]: 41
1003 01:02:30.928086 [Byte1]: 41
1004 01:02:30.933088
1005 01:02:30.933667 Set Vref, RX VrefLevel [Byte0]: 42
1006 01:02:30.936268 [Byte1]: 42
1007 01:02:30.940735
1008 01:02:30.941219 Set Vref, RX VrefLevel [Byte0]: 43
1009 01:02:30.943825 [Byte1]: 43
1010 01:02:30.947896
1011 01:02:30.948465 Set Vref, RX VrefLevel [Byte0]: 44
1012 01:02:30.951444 [Byte1]: 44
1013 01:02:30.955558
1014 01:02:30.956036 Set Vref, RX VrefLevel [Byte0]: 45
1015 01:02:30.958455 [Byte1]: 45
1016 01:02:30.962903
1017 01:02:30.963388 Set Vref, RX VrefLevel [Byte0]: 46
1018 01:02:30.966670 [Byte1]: 46
1019 01:02:30.970755
1020 01:02:30.971321 Set Vref, RX VrefLevel [Byte0]: 47
1021 01:02:30.973603 [Byte1]: 47
1022 01:02:30.978316
1023 01:02:30.978885 Set Vref, RX VrefLevel [Byte0]: 48
1024 01:02:30.981804 [Byte1]: 48
1025 01:02:30.985834
1026 01:02:30.986463 Set Vref, RX VrefLevel [Byte0]: 49
1027 01:02:30.989445 [Byte1]: 49
1028 01:02:30.993406
1029 01:02:30.994007 Set Vref, RX VrefLevel [Byte0]: 50
1030 01:02:30.996317 [Byte1]: 50
1031 01:02:31.000643
1032 01:02:31.001113 Set Vref, RX VrefLevel [Byte0]: 51
1033 01:02:31.004369 [Byte1]: 51
1034 01:02:31.008238
1035 01:02:31.008712 Set Vref, RX VrefLevel [Byte0]: 52
1036 01:02:31.011630 [Byte1]: 52
1037 01:02:31.016203
1038 01:02:31.016676 Set Vref, RX VrefLevel [Byte0]: 53
1039 01:02:31.019420 [Byte1]: 53
1040 01:02:31.023418
1041 01:02:31.024053 Set Vref, RX VrefLevel [Byte0]: 54
1042 01:02:31.027361 [Byte1]: 54
1043 01:02:31.031382
1044 01:02:31.032060 Set Vref, RX VrefLevel [Byte0]: 55
1045 01:02:31.034598 [Byte1]: 55
1046 01:02:31.038835
1047 01:02:31.039402 Set Vref, RX VrefLevel [Byte0]: 56
1048 01:02:31.042474 [Byte1]: 56
1049 01:02:31.046555
1050 01:02:31.047120 Set Vref, RX VrefLevel [Byte0]: 57
1051 01:02:31.050063 [Byte1]: 57
1052 01:02:31.054447
1053 01:02:31.055011 Set Vref, RX VrefLevel [Byte0]: 58
1054 01:02:31.057432 [Byte1]: 58
1055 01:02:31.061815
1056 01:02:31.062435 Set Vref, RX VrefLevel [Byte0]: 59
1057 01:02:31.064877 [Byte1]: 59
1058 01:02:31.069554
1059 01:02:31.070152 Set Vref, RX VrefLevel [Byte0]: 60
1060 01:02:31.072780 [Byte1]: 60
1061 01:02:31.077060
1062 01:02:31.077631 Set Vref, RX VrefLevel [Byte0]: 61
1063 01:02:31.080093 [Byte1]: 61
1064 01:02:31.084656
1065 01:02:31.085220 Set Vref, RX VrefLevel [Byte0]: 62
1066 01:02:31.087744 [Byte1]: 62
1067 01:02:31.092105
1068 01:02:31.092673 Set Vref, RX VrefLevel [Byte0]: 63
1069 01:02:31.095419 [Byte1]: 63
1070 01:02:31.099315
1071 01:02:31.099879 Set Vref, RX VrefLevel [Byte0]: 64
1072 01:02:31.102829 [Byte1]: 64
1073 01:02:31.107018
1074 01:02:31.107594 Set Vref, RX VrefLevel [Byte0]: 65
1075 01:02:31.110435 [Byte1]: 65
1076 01:02:31.114423
1077 01:02:31.114896 Set Vref, RX VrefLevel [Byte0]: 66
1078 01:02:31.118099 [Byte1]: 66
1079 01:02:31.122556
1080 01:02:31.123120 Set Vref, RX VrefLevel [Byte0]: 67
1081 01:02:31.125756 [Byte1]: 67
1082 01:02:31.130301
1083 01:02:31.130867 Set Vref, RX VrefLevel [Byte0]: 68
1084 01:02:31.134055 [Byte1]: 68
1085 01:02:31.137598
1086 01:02:31.138297 Set Vref, RX VrefLevel [Byte0]: 69
1087 01:02:31.140923 [Byte1]: 69
1088 01:02:31.145306
1089 01:02:31.145896 Set Vref, RX VrefLevel [Byte0]: 70
1090 01:02:31.148660 [Byte1]: 70
1091 01:02:31.152880
1092 01:02:31.153446 Set Vref, RX VrefLevel [Byte0]: 71
1093 01:02:31.156269 [Byte1]: 71
1094 01:02:31.160266
1095 01:02:31.160833 Set Vref, RX VrefLevel [Byte0]: 72
1096 01:02:31.164260 [Byte1]: 72
1097 01:02:31.168305
1098 01:02:31.168878 Set Vref, RX VrefLevel [Byte0]: 73
1099 01:02:31.171282 [Byte1]: 73
1100 01:02:31.175817
1101 01:02:31.176383 Set Vref, RX VrefLevel [Byte0]: 74
1102 01:02:31.179181 [Byte1]: 74
1103 01:02:31.182926
1104 01:02:31.183492 Set Vref, RX VrefLevel [Byte0]: 75
1105 01:02:31.186496 [Byte1]: 75
1106 01:02:31.191318
1107 01:02:31.191884 Set Vref, RX VrefLevel [Byte0]: 76
1108 01:02:31.194429 [Byte1]: 76
1109 01:02:31.198497
1110 01:02:31.199164 Final RX Vref Byte 0 = 62 to rank0
1111 01:02:31.201927 Final RX Vref Byte 1 = 55 to rank0
1112 01:02:31.205369 Final RX Vref Byte 0 = 62 to rank1
1113 01:02:31.208601 Final RX Vref Byte 1 = 55 to rank1==
1114 01:02:31.211646 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 01:02:31.214871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 01:02:31.218146 ==
1117 01:02:31.218619 DQS Delay:
1118 01:02:31.218991 DQS0 = 0, DQS1 = 0
1119 01:02:31.222063 DQM Delay:
1120 01:02:31.222623 DQM0 = 92, DQM1 = 82
1121 01:02:31.224790 DQ Delay:
1122 01:02:31.228751 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1123 01:02:31.232291 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1124 01:02:31.232864 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1125 01:02:31.234892 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1126 01:02:31.238576
1127 01:02:31.239049
1128 01:02:31.245333 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1129 01:02:31.248736 CH0 RK0: MR19=606, MR18=3D39
1130 01:02:31.255497 CH0_RK0: MR19=0x606, MR18=0x3D39, DQSOSC=394, MR23=63, INC=95, DEC=63
1131 01:02:31.256068
1132 01:02:31.258590 ----->DramcWriteLeveling(PI) begin...
1133 01:02:31.259170 ==
1134 01:02:31.261823 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 01:02:31.265212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 01:02:31.265788 ==
1137 01:02:31.268739 Write leveling (Byte 0): 31 => 31
1138 01:02:31.271918 Write leveling (Byte 1): 28 => 28
1139 01:02:31.275238 DramcWriteLeveling(PI) end<-----
1140 01:02:31.275809
1141 01:02:31.276191 ==
1142 01:02:31.278758 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 01:02:31.281927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 01:02:31.282520 ==
1145 01:02:31.285292 [Gating] SW mode calibration
1146 01:02:31.292113 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 01:02:31.298559 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 01:02:31.301731 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 01:02:31.305287 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 01:02:31.349780 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 01:02:31.350456 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 01:02:31.351197 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:02:31.351583 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:02:31.351927 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:02:31.352280 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:02:31.352687 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:02:31.353026 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 01:02:31.353351 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 01:02:31.353668 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 01:02:31.393490 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 01:02:31.394121 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 01:02:31.394855 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 01:02:31.395239 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 01:02:31.395589 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 01:02:31.395927 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1166 01:02:31.396261 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 01:02:31.396587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 01:02:31.396912 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 01:02:31.397231 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 01:02:31.417705 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 01:02:31.418723 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 01:02:31.419140 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 01:02:31.419501 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 01:02:31.419845 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1175 01:02:31.421654 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 01:02:31.425008 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 01:02:31.428638 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 01:02:31.434719 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 01:02:31.438100 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 01:02:31.441464 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 01:02:31.447906 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
1182 01:02:31.451557 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
1183 01:02:31.454783 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 01:02:31.461453 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 01:02:31.464748 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 01:02:31.468537 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 01:02:31.474729 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 01:02:31.478041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 01:02:31.481568 0 11 4 | B1->B0 | 2a2a 3535 | 0 0 | (0 0) (0 0)
1190 01:02:31.484820 0 11 8 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
1191 01:02:31.491743 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 01:02:31.494763 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 01:02:31.498312 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 01:02:31.505587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 01:02:31.508447 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 01:02:31.512292 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 01:02:31.515614 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1198 01:02:31.522941 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 01:02:31.526334 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 01:02:31.529767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 01:02:31.533079 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 01:02:31.539920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 01:02:31.543893 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 01:02:31.546885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 01:02:31.554198 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 01:02:31.557257 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 01:02:31.560871 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 01:02:31.563898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 01:02:31.570331 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 01:02:31.573683 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 01:02:31.577530 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 01:02:31.584242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 01:02:31.587253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1214 01:02:31.590803 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 01:02:31.597274 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 01:02:31.600660 Total UI for P1: 0, mck2ui 16
1217 01:02:31.603668 best dqsien dly found for B0: ( 0, 14, 6)
1218 01:02:31.604235 Total UI for P1: 0, mck2ui 16
1219 01:02:31.610439 best dqsien dly found for B1: ( 0, 14, 6)
1220 01:02:31.613838 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1221 01:02:31.617695 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1222 01:02:31.618315
1223 01:02:31.620462 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 01:02:31.623516 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 01:02:31.627153 [Gating] SW calibration Done
1226 01:02:31.627720 ==
1227 01:02:31.630366 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 01:02:31.633607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 01:02:31.634117 ==
1230 01:02:31.636861 RX Vref Scan: 0
1231 01:02:31.637490
1232 01:02:31.637917 RX Vref 0 -> 0, step: 1
1233 01:02:31.638427
1234 01:02:31.640518 RX Delay -130 -> 252, step: 16
1235 01:02:31.643596 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 01:02:31.650176 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 01:02:31.653420 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1238 01:02:31.656868 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1239 01:02:31.659845 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 01:02:31.663349 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1241 01:02:31.670272 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 01:02:31.673270 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1243 01:02:31.677279 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1244 01:02:31.680421 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1245 01:02:31.683303 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 01:02:31.690329 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1247 01:02:31.693569 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1248 01:02:31.697225 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1249 01:02:31.700797 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 01:02:31.706697 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1251 01:02:31.707176 ==
1252 01:02:31.710174 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 01:02:31.713518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 01:02:31.714038 ==
1255 01:02:31.714424 DQS Delay:
1256 01:02:31.717035 DQS0 = 0, DQS1 = 0
1257 01:02:31.717601 DQM Delay:
1258 01:02:31.720142 DQM0 = 89, DQM1 = 82
1259 01:02:31.720707 DQ Delay:
1260 01:02:31.723559 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1261 01:02:31.726584 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1262 01:02:31.730371 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1263 01:02:31.733609 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1264 01:02:31.734230
1265 01:02:31.734611
1266 01:02:31.734961 ==
1267 01:02:31.737275 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 01:02:31.740258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 01:02:31.740733 ==
1270 01:02:31.741105
1271 01:02:31.741453
1272 01:02:31.743752 TX Vref Scan disable
1273 01:02:31.747153 == TX Byte 0 ==
1274 01:02:31.750570 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1275 01:02:31.753598 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1276 01:02:31.757175 == TX Byte 1 ==
1277 01:02:31.760252 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1278 01:02:31.763540 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1279 01:02:31.764022 ==
1280 01:02:31.766672 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 01:02:31.770311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 01:02:31.773610 ==
1283 01:02:31.785309 TX Vref=22, minBit 8, minWin=27, winSum=444
1284 01:02:31.788923 TX Vref=24, minBit 8, minWin=27, winSum=448
1285 01:02:31.792132 TX Vref=26, minBit 8, minWin=27, winSum=452
1286 01:02:31.795662 TX Vref=28, minBit 8, minWin=27, winSum=453
1287 01:02:31.798821 TX Vref=30, minBit 8, minWin=28, winSum=457
1288 01:02:31.802149 TX Vref=32, minBit 8, minWin=27, winSum=455
1289 01:02:31.809627 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30
1290 01:02:31.810262
1291 01:02:31.812079 Final TX Range 1 Vref 30
1292 01:02:31.812554
1293 01:02:31.812924 ==
1294 01:02:31.815506 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 01:02:31.818851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 01:02:31.819321 ==
1297 01:02:31.819688
1298 01:02:31.820026
1299 01:02:31.822249 TX Vref Scan disable
1300 01:02:31.825310 == TX Byte 0 ==
1301 01:02:31.828833 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1302 01:02:31.832053 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1303 01:02:31.835307 == TX Byte 1 ==
1304 01:02:31.838509 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1305 01:02:31.842430 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1306 01:02:31.842840
1307 01:02:31.845500 [DATLAT]
1308 01:02:31.845889 Freq=800, CH0 RK1
1309 01:02:31.846167
1310 01:02:31.848589 DATLAT Default: 0xa
1311 01:02:31.848978 0, 0xFFFF, sum = 0
1312 01:02:31.852647 1, 0xFFFF, sum = 0
1313 01:02:31.853043 2, 0xFFFF, sum = 0
1314 01:02:31.855355 3, 0xFFFF, sum = 0
1315 01:02:31.855749 4, 0xFFFF, sum = 0
1316 01:02:31.858960 5, 0xFFFF, sum = 0
1317 01:02:31.859354 6, 0xFFFF, sum = 0
1318 01:02:31.861924 7, 0xFFFF, sum = 0
1319 01:02:31.862343 8, 0xFFFF, sum = 0
1320 01:02:31.865476 9, 0x0, sum = 1
1321 01:02:31.865868 10, 0x0, sum = 2
1322 01:02:31.868572 11, 0x0, sum = 3
1323 01:02:31.868967 12, 0x0, sum = 4
1324 01:02:31.872331 best_step = 10
1325 01:02:31.872751
1326 01:02:31.873116 ==
1327 01:02:31.875360 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 01:02:31.878546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 01:02:31.879098 ==
1330 01:02:31.881878 RX Vref Scan: 0
1331 01:02:31.882329
1332 01:02:31.882666 RX Vref 0 -> 0, step: 1
1333 01:02:31.882977
1334 01:02:31.885527 RX Delay -79 -> 252, step: 8
1335 01:02:31.892089 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 01:02:31.895320 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1337 01:02:31.898969 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1338 01:02:31.901796 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1339 01:02:31.905401 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1340 01:02:31.912083 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1341 01:02:31.915581 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 01:02:31.919352 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 01:02:31.922563 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1344 01:02:31.925749 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1345 01:02:31.929081 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1346 01:02:31.935484 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1347 01:02:31.938787 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1348 01:02:31.942195 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1349 01:02:31.945859 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 01:02:31.952319 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1351 01:02:31.952835 ==
1352 01:02:31.955751 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 01:02:31.959056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 01:02:31.959569 ==
1355 01:02:31.959906 DQS Delay:
1356 01:02:31.962621 DQS0 = 0, DQS1 = 0
1357 01:02:31.963135 DQM Delay:
1358 01:02:31.965663 DQM0 = 91, DQM1 = 83
1359 01:02:31.966209 DQ Delay:
1360 01:02:31.969048 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1361 01:02:31.972118 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1362 01:02:31.975579 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1363 01:02:31.979207 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1364 01:02:31.979725
1365 01:02:31.980063
1366 01:02:31.985718 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
1367 01:02:31.988840 CH0 RK1: MR19=606, MR18=3C17
1368 01:02:31.995441 CH0_RK1: MR19=0x606, MR18=0x3C17, DQSOSC=394, MR23=63, INC=95, DEC=63
1369 01:02:31.998983 [RxdqsGatingPostProcess] freq 800
1370 01:02:32.005624 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 01:02:32.006231 Pre-setting of DQS Precalculation
1372 01:02:32.012490 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 01:02:32.013087 ==
1374 01:02:32.015742 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 01:02:32.018844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 01:02:32.019319 ==
1377 01:02:32.026773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 01:02:32.032487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 01:02:32.040725 [CA 0] Center 36 (6~67) winsize 62
1380 01:02:32.044046 [CA 1] Center 36 (6~67) winsize 62
1381 01:02:32.047203 [CA 2] Center 35 (5~65) winsize 61
1382 01:02:32.050412 [CA 3] Center 34 (3~65) winsize 63
1383 01:02:32.053909 [CA 4] Center 34 (4~64) winsize 61
1384 01:02:32.057009 [CA 5] Center 33 (3~64) winsize 62
1385 01:02:32.057574
1386 01:02:32.060470 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1387 01:02:32.061043
1388 01:02:32.063422 [CATrainingPosCal] consider 1 rank data
1389 01:02:32.066894 u2DelayCellTimex100 = 270/100 ps
1390 01:02:32.070351 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 01:02:32.074233 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 01:02:32.080309 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1393 01:02:32.084183 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 01:02:32.087135 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1395 01:02:32.090414 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 01:02:32.090881
1397 01:02:32.093745 CA PerBit enable=1, Macro0, CA PI delay=33
1398 01:02:32.094352
1399 01:02:32.097064 [CBTSetCACLKResult] CA Dly = 33
1400 01:02:32.097627 CS Dly: 4 (0~35)
1401 01:02:32.098055 ==
1402 01:02:32.100275 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 01:02:32.106837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 01:02:32.107315 ==
1405 01:02:32.110326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 01:02:32.117022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 01:02:32.126584 [CA 0] Center 37 (7~67) winsize 61
1408 01:02:32.129935 [CA 1] Center 37 (6~68) winsize 63
1409 01:02:32.133376 [CA 2] Center 35 (5~66) winsize 62
1410 01:02:32.136999 [CA 3] Center 34 (4~65) winsize 62
1411 01:02:32.139737 [CA 4] Center 34 (4~65) winsize 62
1412 01:02:32.143321 [CA 5] Center 34 (4~64) winsize 61
1413 01:02:32.143892
1414 01:02:32.146795 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 01:02:32.147364
1416 01:02:32.150293 [CATrainingPosCal] consider 2 rank data
1417 01:02:32.153239 u2DelayCellTimex100 = 270/100 ps
1418 01:02:32.156976 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1419 01:02:32.160144 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 01:02:32.166358 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1421 01:02:32.170058 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 01:02:32.173712 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 01:02:32.177872 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 01:02:32.178490
1425 01:02:32.180554 CA PerBit enable=1, Macro0, CA PI delay=34
1426 01:02:32.181026
1427 01:02:32.184796 [CBTSetCACLKResult] CA Dly = 34
1428 01:02:32.185371 CS Dly: 5 (0~37)
1429 01:02:32.185884
1430 01:02:32.188488 ----->DramcWriteLeveling(PI) begin...
1431 01:02:32.189067 ==
1432 01:02:32.192166 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 01:02:32.195787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 01:02:32.196357 ==
1435 01:02:32.199740 Write leveling (Byte 0): 30 => 30
1436 01:02:32.203126 Write leveling (Byte 1): 30 => 30
1437 01:02:32.203805 DramcWriteLeveling(PI) end<-----
1438 01:02:32.207133
1439 01:02:32.207783 ==
1440 01:02:32.208187 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 01:02:32.214067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 01:02:32.214702 ==
1443 01:02:32.215092 [Gating] SW mode calibration
1444 01:02:32.224101 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 01:02:32.227876 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 01:02:32.230687 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1447 01:02:32.237733 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1448 01:02:32.241157 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 01:02:32.244447 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 01:02:32.251173 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 01:02:32.254622 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 01:02:32.257629 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 01:02:32.264439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 01:02:32.267672 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 01:02:32.271048 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 01:02:32.278099 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 01:02:32.280958 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 01:02:32.284908 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 01:02:32.291288 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 01:02:32.294318 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 01:02:32.297657 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 01:02:32.301361 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1463 01:02:32.307444 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1464 01:02:32.310733 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 01:02:32.314543 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 01:02:32.321414 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 01:02:32.324303 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 01:02:32.327828 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 01:02:32.334222 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 01:02:32.337750 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 01:02:32.340790 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1472 01:02:32.347737 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1473 01:02:32.350867 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 01:02:32.354552 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 01:02:32.361015 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 01:02:32.364124 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 01:02:32.367290 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 01:02:32.374589 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 01:02:32.377375 0 10 4 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
1480 01:02:32.381026 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 01:02:32.387939 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 01:02:32.391036 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 01:02:32.394621 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 01:02:32.397741 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 01:02:32.404205 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 01:02:32.407594 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 01:02:32.411159 0 11 4 | B1->B0 | 3131 3434 | 0 0 | (1 1) (0 0)
1488 01:02:32.417480 0 11 8 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
1489 01:02:32.421189 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 01:02:32.424642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 01:02:32.431077 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 01:02:32.434089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 01:02:32.437605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 01:02:32.444664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1495 01:02:32.447784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1496 01:02:32.450834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1497 01:02:32.457841 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 01:02:32.461096 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 01:02:32.464408 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 01:02:32.471143 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 01:02:32.474780 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 01:02:32.478460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 01:02:32.481378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 01:02:32.488642 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 01:02:32.491425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 01:02:32.494621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 01:02:32.501196 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 01:02:32.504225 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 01:02:32.507892 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 01:02:32.514641 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 01:02:32.517814 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 01:02:32.521571 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 01:02:32.524367 Total UI for P1: 0, mck2ui 16
1514 01:02:32.528157 best dqsien dly found for B0: ( 0, 14, 4)
1515 01:02:32.531471 Total UI for P1: 0, mck2ui 16
1516 01:02:32.534603 best dqsien dly found for B1: ( 0, 14, 4)
1517 01:02:32.537578 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 01:02:32.540922 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1519 01:02:32.541511
1520 01:02:32.547827 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 01:02:32.551118 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 01:02:32.551712 [Gating] SW calibration Done
1523 01:02:32.554491 ==
1524 01:02:32.555099 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 01:02:32.560828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 01:02:32.561456 ==
1527 01:02:32.561840 RX Vref Scan: 0
1528 01:02:32.562256
1529 01:02:32.564448 RX Vref 0 -> 0, step: 1
1530 01:02:32.564918
1531 01:02:32.568160 RX Delay -130 -> 252, step: 16
1532 01:02:32.571130 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1533 01:02:32.574800 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1534 01:02:32.577842 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1535 01:02:32.584466 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1536 01:02:32.587790 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1537 01:02:32.591410 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1538 01:02:32.594885 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1539 01:02:32.598066 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1540 01:02:32.604503 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1541 01:02:32.607735 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1542 01:02:32.611500 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1543 01:02:32.614351 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1544 01:02:32.617782 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1545 01:02:32.624681 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1546 01:02:32.627857 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1547 01:02:32.631540 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1548 01:02:32.632118 ==
1549 01:02:32.634611 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 01:02:32.638152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 01:02:32.638733 ==
1552 01:02:32.641452 DQS Delay:
1553 01:02:32.642073 DQS0 = 0, DQS1 = 0
1554 01:02:32.644659 DQM Delay:
1555 01:02:32.645237 DQM0 = 90, DQM1 = 82
1556 01:02:32.645619 DQ Delay:
1557 01:02:32.648536 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1558 01:02:32.651463 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =93
1559 01:02:32.654589 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1560 01:02:32.658035 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1561 01:02:32.658603
1562 01:02:32.658980
1563 01:02:32.659326 ==
1564 01:02:32.661075 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 01:02:32.667606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 01:02:32.668245 ==
1567 01:02:32.668639
1568 01:02:32.668988
1569 01:02:32.669321 TX Vref Scan disable
1570 01:02:32.671465 == TX Byte 0 ==
1571 01:02:32.674794 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1572 01:02:32.678656 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1573 01:02:32.681502 == TX Byte 1 ==
1574 01:02:32.684783 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1575 01:02:32.688479 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1576 01:02:32.691713 ==
1577 01:02:32.695136 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 01:02:32.698800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 01:02:32.699373 ==
1580 01:02:32.710610 TX Vref=22, minBit 15, minWin=26, winSum=445
1581 01:02:32.713999 TX Vref=24, minBit 8, minWin=27, winSum=449
1582 01:02:32.717280 TX Vref=26, minBit 8, minWin=27, winSum=453
1583 01:02:32.721049 TX Vref=28, minBit 15, minWin=27, winSum=458
1584 01:02:32.724091 TX Vref=30, minBit 15, minWin=27, winSum=459
1585 01:02:32.730578 TX Vref=32, minBit 12, minWin=27, winSum=457
1586 01:02:32.734189 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1587 01:02:32.734755
1588 01:02:32.737801 Final TX Range 1 Vref 30
1589 01:02:32.738408
1590 01:02:32.738789 ==
1591 01:02:32.740702 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 01:02:32.744094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 01:02:32.747725 ==
1594 01:02:32.748292
1595 01:02:32.748671
1596 01:02:32.749019 TX Vref Scan disable
1597 01:02:32.750971 == TX Byte 0 ==
1598 01:02:32.754553 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1599 01:02:32.758580 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1600 01:02:32.761213 == TX Byte 1 ==
1601 01:02:32.764463 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1602 01:02:32.768020 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1603 01:02:32.768494
1604 01:02:32.771640 [DATLAT]
1605 01:02:32.772206 Freq=800, CH1 RK0
1606 01:02:32.772587
1607 01:02:32.774703 DATLAT Default: 0xa
1608 01:02:32.775178 0, 0xFFFF, sum = 0
1609 01:02:32.778250 1, 0xFFFF, sum = 0
1610 01:02:32.778830 2, 0xFFFF, sum = 0
1611 01:02:32.781452 3, 0xFFFF, sum = 0
1612 01:02:32.782059 4, 0xFFFF, sum = 0
1613 01:02:32.785220 5, 0xFFFF, sum = 0
1614 01:02:32.785812 6, 0xFFFF, sum = 0
1615 01:02:32.788334 7, 0xFFFF, sum = 0
1616 01:02:32.788911 8, 0xFFFF, sum = 0
1617 01:02:32.791492 9, 0x0, sum = 1
1618 01:02:32.792072 10, 0x0, sum = 2
1619 01:02:32.795023 11, 0x0, sum = 3
1620 01:02:32.795600 12, 0x0, sum = 4
1621 01:02:32.798395 best_step = 10
1622 01:02:32.798965
1623 01:02:32.799347 ==
1624 01:02:32.801517 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 01:02:32.804540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 01:02:32.805015 ==
1627 01:02:32.807930 RX Vref Scan: 1
1628 01:02:32.808407
1629 01:02:32.808784 Set Vref Range= 32 -> 127
1630 01:02:32.809137
1631 01:02:32.811501 RX Vref 32 -> 127, step: 1
1632 01:02:32.812068
1633 01:02:32.814574 RX Delay -95 -> 252, step: 8
1634 01:02:32.815147
1635 01:02:32.817985 Set Vref, RX VrefLevel [Byte0]: 32
1636 01:02:32.821686 [Byte1]: 32
1637 01:02:32.822324
1638 01:02:32.824876 Set Vref, RX VrefLevel [Byte0]: 33
1639 01:02:32.828253 [Byte1]: 33
1640 01:02:32.831557
1641 01:02:32.832121 Set Vref, RX VrefLevel [Byte0]: 34
1642 01:02:32.834639 [Byte1]: 34
1643 01:02:32.839155
1644 01:02:32.839717 Set Vref, RX VrefLevel [Byte0]: 35
1645 01:02:32.842106 [Byte1]: 35
1646 01:02:32.846735
1647 01:02:32.847297 Set Vref, RX VrefLevel [Byte0]: 36
1648 01:02:32.849924 [Byte1]: 36
1649 01:02:32.853886
1650 01:02:32.854386 Set Vref, RX VrefLevel [Byte0]: 37
1651 01:02:32.857659 [Byte1]: 37
1652 01:02:32.861822
1653 01:02:32.862417 Set Vref, RX VrefLevel [Byte0]: 38
1654 01:02:32.865128 [Byte1]: 38
1655 01:02:32.868979
1656 01:02:32.869467 Set Vref, RX VrefLevel [Byte0]: 39
1657 01:02:32.872680 [Byte1]: 39
1658 01:02:32.876871
1659 01:02:32.877432 Set Vref, RX VrefLevel [Byte0]: 40
1660 01:02:32.880084 [Byte1]: 40
1661 01:02:32.884634
1662 01:02:32.885196 Set Vref, RX VrefLevel [Byte0]: 41
1663 01:02:32.887815 [Byte1]: 41
1664 01:02:32.892475
1665 01:02:32.893045 Set Vref, RX VrefLevel [Byte0]: 42
1666 01:02:32.895483 [Byte1]: 42
1667 01:02:32.899783
1668 01:02:32.900401 Set Vref, RX VrefLevel [Byte0]: 43
1669 01:02:32.903762 [Byte1]: 43
1670 01:02:32.907332
1671 01:02:32.907802 Set Vref, RX VrefLevel [Byte0]: 44
1672 01:02:32.910955 [Byte1]: 44
1673 01:02:32.914837
1674 01:02:32.915446 Set Vref, RX VrefLevel [Byte0]: 45
1675 01:02:32.918150 [Byte1]: 45
1676 01:02:32.922831
1677 01:02:32.923396 Set Vref, RX VrefLevel [Byte0]: 46
1678 01:02:32.925782 [Byte1]: 46
1679 01:02:32.930253
1680 01:02:32.930819 Set Vref, RX VrefLevel [Byte0]: 47
1681 01:02:32.933316 [Byte1]: 47
1682 01:02:32.938108
1683 01:02:32.938666 Set Vref, RX VrefLevel [Byte0]: 48
1684 01:02:32.940984 [Byte1]: 48
1685 01:02:32.945143
1686 01:02:32.945705 Set Vref, RX VrefLevel [Byte0]: 49
1687 01:02:32.948858 [Byte1]: 49
1688 01:02:32.953204
1689 01:02:32.953771 Set Vref, RX VrefLevel [Byte0]: 50
1690 01:02:32.956442 [Byte1]: 50
1691 01:02:32.960719
1692 01:02:32.961287 Set Vref, RX VrefLevel [Byte0]: 51
1693 01:02:32.963589 [Byte1]: 51
1694 01:02:32.968438
1695 01:02:32.969003 Set Vref, RX VrefLevel [Byte0]: 52
1696 01:02:32.971411 [Byte1]: 52
1697 01:02:32.975409
1698 01:02:32.975978 Set Vref, RX VrefLevel [Byte0]: 53
1699 01:02:32.978846 [Byte1]: 53
1700 01:02:32.983651
1701 01:02:32.984214 Set Vref, RX VrefLevel [Byte0]: 54
1702 01:02:32.986718 [Byte1]: 54
1703 01:02:32.990879
1704 01:02:32.991450 Set Vref, RX VrefLevel [Byte0]: 55
1705 01:02:32.994393 [Byte1]: 55
1706 01:02:32.998315
1707 01:02:32.998894 Set Vref, RX VrefLevel [Byte0]: 56
1708 01:02:33.002072 [Byte1]: 56
1709 01:02:33.006049
1710 01:02:33.006517 Set Vref, RX VrefLevel [Byte0]: 57
1711 01:02:33.009432 [Byte1]: 57
1712 01:02:33.013834
1713 01:02:33.014456 Set Vref, RX VrefLevel [Byte0]: 58
1714 01:02:33.016909 [Byte1]: 58
1715 01:02:33.021451
1716 01:02:33.022062 Set Vref, RX VrefLevel [Byte0]: 59
1717 01:02:33.024458 [Byte1]: 59
1718 01:02:33.028915
1719 01:02:33.029550 Set Vref, RX VrefLevel [Byte0]: 60
1720 01:02:33.032295 [Byte1]: 60
1721 01:02:33.036691
1722 01:02:33.037267 Set Vref, RX VrefLevel [Byte0]: 61
1723 01:02:33.039929 [Byte1]: 61
1724 01:02:33.044196
1725 01:02:33.044769 Set Vref, RX VrefLevel [Byte0]: 62
1726 01:02:33.047511 [Byte1]: 62
1727 01:02:33.051886
1728 01:02:33.052457 Set Vref, RX VrefLevel [Byte0]: 63
1729 01:02:33.055349 [Byte1]: 63
1730 01:02:33.059563
1731 01:02:33.060141 Set Vref, RX VrefLevel [Byte0]: 64
1732 01:02:33.062822 [Byte1]: 64
1733 01:02:33.066709
1734 01:02:33.067291 Set Vref, RX VrefLevel [Byte0]: 65
1735 01:02:33.070242 [Byte1]: 65
1736 01:02:33.074694
1737 01:02:33.075272 Set Vref, RX VrefLevel [Byte0]: 66
1738 01:02:33.078242 [Byte1]: 66
1739 01:02:33.082118
1740 01:02:33.082692 Set Vref, RX VrefLevel [Byte0]: 67
1741 01:02:33.085290 [Byte1]: 67
1742 01:02:33.089666
1743 01:02:33.090272 Set Vref, RX VrefLevel [Byte0]: 68
1744 01:02:33.092967 [Byte1]: 68
1745 01:02:33.097093
1746 01:02:33.097567 Set Vref, RX VrefLevel [Byte0]: 69
1747 01:02:33.100456 [Byte1]: 69
1748 01:02:33.104745
1749 01:02:33.105325 Set Vref, RX VrefLevel [Byte0]: 70
1750 01:02:33.108028 [Byte1]: 70
1751 01:02:33.112361
1752 01:02:33.112926 Set Vref, RX VrefLevel [Byte0]: 71
1753 01:02:33.115504 [Byte1]: 71
1754 01:02:33.120131
1755 01:02:33.120700 Set Vref, RX VrefLevel [Byte0]: 72
1756 01:02:33.123206 [Byte1]: 72
1757 01:02:33.127515
1758 01:02:33.128081 Set Vref, RX VrefLevel [Byte0]: 73
1759 01:02:33.131069 [Byte1]: 73
1760 01:02:33.135203
1761 01:02:33.138177 Set Vref, RX VrefLevel [Byte0]: 74
1762 01:02:33.138648 [Byte1]: 74
1763 01:02:33.142900
1764 01:02:33.143464 Final RX Vref Byte 0 = 51 to rank0
1765 01:02:33.145793 Final RX Vref Byte 1 = 60 to rank0
1766 01:02:33.149924 Final RX Vref Byte 0 = 51 to rank1
1767 01:02:33.152921 Final RX Vref Byte 1 = 60 to rank1==
1768 01:02:33.156406 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 01:02:33.162773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 01:02:33.163348 ==
1771 01:02:33.163732 DQS Delay:
1772 01:02:33.164148 DQS0 = 0, DQS1 = 0
1773 01:02:33.165819 DQM Delay:
1774 01:02:33.166491 DQM0 = 92, DQM1 = 82
1775 01:02:33.169563 DQ Delay:
1776 01:02:33.172992 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1777 01:02:33.176691 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1778 01:02:33.177188 DQ8 =72, DQ9 =68, DQ10 =88, DQ11 =76
1779 01:02:33.179507 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1780 01:02:33.183187
1781 01:02:33.183756
1782 01:02:33.189476 [DQSOSCAuto] RK0, (LSB)MR18= 0x3250, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
1783 01:02:33.193197 CH1 RK0: MR19=606, MR18=3250
1784 01:02:33.199771 CH1_RK0: MR19=0x606, MR18=0x3250, DQSOSC=389, MR23=63, INC=97, DEC=65
1785 01:02:33.200362
1786 01:02:33.202662 ----->DramcWriteLeveling(PI) begin...
1787 01:02:33.203143 ==
1788 01:02:33.206242 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 01:02:33.209513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 01:02:33.210074 ==
1791 01:02:33.212961 Write leveling (Byte 0): 27 => 27
1792 01:02:33.216195 Write leveling (Byte 1): 30 => 30
1793 01:02:33.219449 DramcWriteLeveling(PI) end<-----
1794 01:02:33.219924
1795 01:02:33.220300 ==
1796 01:02:33.223255 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 01:02:33.226094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 01:02:33.226572 ==
1799 01:02:33.229732 [Gating] SW mode calibration
1800 01:02:33.236625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 01:02:33.243024 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 01:02:33.246551 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1803 01:02:33.249842 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1804 01:02:33.256512 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 01:02:33.259536 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 01:02:33.262897 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 01:02:33.269706 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 01:02:33.273012 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 01:02:33.276550 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 01:02:33.282799 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 01:02:33.286734 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 01:02:33.289736 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 01:02:33.292943 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 01:02:33.299779 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 01:02:33.303543 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 01:02:33.306290 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 01:02:33.313223 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 01:02:33.316146 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1819 01:02:33.319688 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1820 01:02:33.326327 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 01:02:33.329890 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 01:02:33.332946 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 01:02:33.339674 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 01:02:33.342868 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 01:02:33.346437 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 01:02:33.353272 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 01:02:33.356063 0 9 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1828 01:02:33.359703 0 9 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
1829 01:02:33.366660 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 01:02:33.369588 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 01:02:33.373091 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 01:02:33.379811 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 01:02:33.382971 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 01:02:33.386138 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1835 01:02:33.390059 0 10 4 | B1->B0 | 2f2f 3232 | 0 0 | (0 0) (0 0)
1836 01:02:33.396432 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
1837 01:02:33.400137 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 01:02:33.402964 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 01:02:33.409567 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 01:02:33.412682 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 01:02:33.416437 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 01:02:33.422917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 01:02:33.426521 0 11 4 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1844 01:02:33.429434 0 11 8 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
1845 01:02:33.436675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 01:02:33.439846 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 01:02:33.442905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 01:02:33.450044 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 01:02:33.453058 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 01:02:33.456847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1851 01:02:33.463041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1852 01:02:33.466867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1853 01:02:33.469797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 01:02:33.473661 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 01:02:33.480232 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 01:02:33.483383 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 01:02:33.486655 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 01:02:33.494059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 01:02:33.496695 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 01:02:33.499716 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 01:02:33.506597 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 01:02:33.509612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 01:02:33.513141 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 01:02:33.519762 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 01:02:33.523161 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 01:02:33.526985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 01:02:33.533908 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 01:02:33.536452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 01:02:33.540396 Total UI for P1: 0, mck2ui 16
1870 01:02:33.542989 best dqsien dly found for B0: ( 0, 14, 4)
1871 01:02:33.546559 Total UI for P1: 0, mck2ui 16
1872 01:02:33.550069 best dqsien dly found for B1: ( 0, 14, 4)
1873 01:02:33.553480 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1874 01:02:33.556440 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 01:02:33.556916
1876 01:02:33.559972 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1877 01:02:33.563407 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 01:02:33.566709 [Gating] SW calibration Done
1879 01:02:33.567395 ==
1880 01:02:33.570180 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 01:02:33.573839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 01:02:33.574454 ==
1883 01:02:33.576532 RX Vref Scan: 0
1884 01:02:33.577098
1885 01:02:33.577480 RX Vref 0 -> 0, step: 1
1886 01:02:33.580062
1887 01:02:33.580627 RX Delay -130 -> 252, step: 16
1888 01:02:33.586818 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1889 01:02:33.590313 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1890 01:02:33.593200 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1891 01:02:33.596529 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1892 01:02:33.600326 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1893 01:02:33.606797 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1894 01:02:33.609656 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1895 01:02:33.613137 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1896 01:02:33.616529 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1897 01:02:33.620061 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1898 01:02:33.626412 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1899 01:02:33.629989 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1900 01:02:33.633433 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1901 01:02:33.636501 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1902 01:02:33.639953 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1903 01:02:33.646774 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1904 01:02:33.647347 ==
1905 01:02:33.649930 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 01:02:33.653550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 01:02:33.654160 ==
1908 01:02:33.654552 DQS Delay:
1909 01:02:33.656793 DQS0 = 0, DQS1 = 0
1910 01:02:33.657370 DQM Delay:
1911 01:02:33.659712 DQM0 = 89, DQM1 = 84
1912 01:02:33.660193 DQ Delay:
1913 01:02:33.663169 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1914 01:02:33.667139 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1915 01:02:33.670229 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1916 01:02:33.673275 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1917 01:02:33.673850
1918 01:02:33.674275
1919 01:02:33.674630 ==
1920 01:02:33.676784 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 01:02:33.680332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 01:02:33.680903 ==
1923 01:02:33.681286
1924 01:02:33.681635
1925 01:02:33.683254 TX Vref Scan disable
1926 01:02:33.686977 == TX Byte 0 ==
1927 01:02:33.689737 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1928 01:02:33.693213 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1929 01:02:33.696211 == TX Byte 1 ==
1930 01:02:33.699807 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1931 01:02:33.703301 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1932 01:02:33.703775 ==
1933 01:02:33.706365 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 01:02:33.712828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 01:02:33.713304 ==
1936 01:02:33.724997 TX Vref=22, minBit 8, minWin=27, winSum=447
1937 01:02:33.728501 TX Vref=24, minBit 9, minWin=27, winSum=452
1938 01:02:33.731610 TX Vref=26, minBit 13, minWin=27, winSum=458
1939 01:02:33.734711 TX Vref=28, minBit 9, minWin=27, winSum=457
1940 01:02:33.738077 TX Vref=30, minBit 9, minWin=27, winSum=460
1941 01:02:33.741740 TX Vref=32, minBit 9, minWin=27, winSum=458
1942 01:02:33.748555 [TxChooseVref] Worse bit 9, Min win 27, Win sum 460, Final Vref 30
1943 01:02:33.749129
1944 01:02:33.752069 Final TX Range 1 Vref 30
1945 01:02:33.752645
1946 01:02:33.753024 ==
1947 01:02:33.755571 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 01:02:33.758516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 01:02:33.759089 ==
1950 01:02:33.759472
1951 01:02:33.759824
1952 01:02:33.762065 TX Vref Scan disable
1953 01:02:33.765720 == TX Byte 0 ==
1954 01:02:33.769093 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 01:02:33.772098 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 01:02:33.775503 == TX Byte 1 ==
1957 01:02:33.778617 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1958 01:02:33.781977 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1959 01:02:33.782546
1960 01:02:33.785521 [DATLAT]
1961 01:02:33.786134 Freq=800, CH1 RK1
1962 01:02:33.786522
1963 01:02:33.788717 DATLAT Default: 0xa
1964 01:02:33.789288 0, 0xFFFF, sum = 0
1965 01:02:33.792289 1, 0xFFFF, sum = 0
1966 01:02:33.792864 2, 0xFFFF, sum = 0
1967 01:02:33.795501 3, 0xFFFF, sum = 0
1968 01:02:33.796081 4, 0xFFFF, sum = 0
1969 01:02:33.798772 5, 0xFFFF, sum = 0
1970 01:02:33.799347 6, 0xFFFF, sum = 0
1971 01:02:33.802321 7, 0xFFFF, sum = 0
1972 01:02:33.802897 8, 0xFFFF, sum = 0
1973 01:02:33.805536 9, 0x0, sum = 1
1974 01:02:33.806155 10, 0x0, sum = 2
1975 01:02:33.808973 11, 0x0, sum = 3
1976 01:02:33.809553 12, 0x0, sum = 4
1977 01:02:33.812006 best_step = 10
1978 01:02:33.812479
1979 01:02:33.812858 ==
1980 01:02:33.815810 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 01:02:33.818662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 01:02:33.819188 ==
1983 01:02:33.819578 RX Vref Scan: 0
1984 01:02:33.822148
1985 01:02:33.822620 RX Vref 0 -> 0, step: 1
1986 01:02:33.822999
1987 01:02:33.825296 RX Delay -95 -> 252, step: 8
1988 01:02:33.829411 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
1989 01:02:33.835808 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1990 01:02:33.839114 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1991 01:02:33.842586 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1992 01:02:33.845866 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1993 01:02:33.849498 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1994 01:02:33.852409 iDelay=209, Bit 6, Center 100 (1 ~ 200) 200
1995 01:02:33.859107 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
1996 01:02:33.862314 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1997 01:02:33.865635 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1998 01:02:33.868949 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1999 01:02:33.872130 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2000 01:02:33.879371 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2001 01:02:33.882333 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2002 01:02:33.885857 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2003 01:02:33.889165 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2004 01:02:33.889736 ==
2005 01:02:33.892473 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 01:02:33.899596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 01:02:33.900169 ==
2008 01:02:33.900551 DQS Delay:
2009 01:02:33.902270 DQS0 = 0, DQS1 = 0
2010 01:02:33.902744 DQM Delay:
2011 01:02:33.903121 DQM0 = 92, DQM1 = 85
2012 01:02:33.905970 DQ Delay:
2013 01:02:33.909048 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2014 01:02:33.912439 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =88
2015 01:02:33.915736 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2016 01:02:33.919140 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =96
2017 01:02:33.919668
2018 01:02:33.920048
2019 01:02:33.925697 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2020 01:02:33.929430 CH1 RK1: MR19=606, MR18=3D12
2021 01:02:33.935804 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2022 01:02:33.939056 [RxdqsGatingPostProcess] freq 800
2023 01:02:33.942766 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 01:02:33.945529 Pre-setting of DQS Precalculation
2025 01:02:33.952440 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 01:02:33.959450 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 01:02:33.966026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 01:02:33.966646
2029 01:02:33.967030
2030 01:02:33.968834 [Calibration Summary] 1600 Mbps
2031 01:02:33.969310 CH 0, Rank 0
2032 01:02:33.972497 SW Impedance : PASS
2033 01:02:33.975714 DUTY Scan : NO K
2034 01:02:33.976261 ZQ Calibration : PASS
2035 01:02:33.978997 Jitter Meter : NO K
2036 01:02:33.982155 CBT Training : PASS
2037 01:02:33.982630 Write leveling : PASS
2038 01:02:33.985713 RX DQS gating : PASS
2039 01:02:33.989265 RX DQ/DQS(RDDQC) : PASS
2040 01:02:33.989846 TX DQ/DQS : PASS
2041 01:02:33.992325 RX DATLAT : PASS
2042 01:02:33.995772 RX DQ/DQS(Engine): PASS
2043 01:02:33.996341 TX OE : NO K
2044 01:02:33.996726 All Pass.
2045 01:02:33.997079
2046 01:02:33.999383 CH 0, Rank 1
2047 01:02:33.999951 SW Impedance : PASS
2048 01:02:34.002563 DUTY Scan : NO K
2049 01:02:34.006458 ZQ Calibration : PASS
2050 01:02:34.007028 Jitter Meter : NO K
2051 01:02:34.008718 CBT Training : PASS
2052 01:02:34.012234 Write leveling : PASS
2053 01:02:34.012825 RX DQS gating : PASS
2054 01:02:34.015311 RX DQ/DQS(RDDQC) : PASS
2055 01:02:34.018884 TX DQ/DQS : PASS
2056 01:02:34.019363 RX DATLAT : PASS
2057 01:02:34.022292 RX DQ/DQS(Engine): PASS
2058 01:02:34.025609 TX OE : NO K
2059 01:02:34.026245 All Pass.
2060 01:02:34.026634
2061 01:02:34.026986 CH 1, Rank 0
2062 01:02:34.029440 SW Impedance : PASS
2063 01:02:34.032118 DUTY Scan : NO K
2064 01:02:34.032686 ZQ Calibration : PASS
2065 01:02:34.035712 Jitter Meter : NO K
2066 01:02:34.038864 CBT Training : PASS
2067 01:02:34.039433 Write leveling : PASS
2068 01:02:34.042377 RX DQS gating : PASS
2069 01:02:34.045525 RX DQ/DQS(RDDQC) : PASS
2070 01:02:34.046047 TX DQ/DQS : PASS
2071 01:02:34.048966 RX DATLAT : PASS
2072 01:02:34.049537 RX DQ/DQS(Engine): PASS
2073 01:02:34.052379 TX OE : NO K
2074 01:02:34.052949 All Pass.
2075 01:02:34.053328
2076 01:02:34.056043 CH 1, Rank 1
2077 01:02:34.056614 SW Impedance : PASS
2078 01:02:34.059018 DUTY Scan : NO K
2079 01:02:34.062364 ZQ Calibration : PASS
2080 01:02:34.062935 Jitter Meter : NO K
2081 01:02:34.066094 CBT Training : PASS
2082 01:02:34.068923 Write leveling : PASS
2083 01:02:34.069394 RX DQS gating : PASS
2084 01:02:34.072846 RX DQ/DQS(RDDQC) : PASS
2085 01:02:34.075470 TX DQ/DQS : PASS
2086 01:02:34.076052 RX DATLAT : PASS
2087 01:02:34.078744 RX DQ/DQS(Engine): PASS
2088 01:02:34.082308 TX OE : NO K
2089 01:02:34.082878 All Pass.
2090 01:02:34.083254
2091 01:02:34.083603 DramC Write-DBI off
2092 01:02:34.085405 PER_BANK_REFRESH: Hybrid Mode
2093 01:02:34.088583 TX_TRACKING: ON
2094 01:02:34.091990 [GetDramInforAfterCalByMRR] Vendor 6.
2095 01:02:34.095536 [GetDramInforAfterCalByMRR] Revision 606.
2096 01:02:34.098752 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 01:02:34.099320 MR0 0x3b3b
2098 01:02:34.102216 MR8 0x5151
2099 01:02:34.106008 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 01:02:34.106578
2101 01:02:34.106956 MR0 0x3b3b
2102 01:02:34.107301 MR8 0x5151
2103 01:02:34.108646 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 01:02:34.109120
2105 01:02:34.118916 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 01:02:34.122247 [FAST_K] Save calibration result to emmc
2107 01:02:34.125621 [FAST_K] Save calibration result to emmc
2108 01:02:34.129084 dram_init: config_dvfs: 1
2109 01:02:34.132318 dramc_set_vcore_voltage set vcore to 662500
2110 01:02:34.135685 Read voltage for 1200, 2
2111 01:02:34.136270 Vio18 = 0
2112 01:02:34.139302 Vcore = 662500
2113 01:02:34.139874 Vdram = 0
2114 01:02:34.140253 Vddq = 0
2115 01:02:34.140604 Vmddr = 0
2116 01:02:34.145681 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 01:02:34.148900 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 01:02:34.152249 MEM_TYPE=3, freq_sel=15
2119 01:02:34.155540 sv_algorithm_assistance_LP4_1600
2120 01:02:34.159226 ============ PULL DRAM RESETB DOWN ============
2121 01:02:34.165495 ========== PULL DRAM RESETB DOWN end =========
2122 01:02:34.168619 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 01:02:34.172187 ===================================
2124 01:02:34.175475 LPDDR4 DRAM CONFIGURATION
2125 01:02:34.178706 ===================================
2126 01:02:34.179183 EX_ROW_EN[0] = 0x0
2127 01:02:34.182534 EX_ROW_EN[1] = 0x0
2128 01:02:34.183121 LP4Y_EN = 0x0
2129 01:02:34.185482 WORK_FSP = 0x0
2130 01:02:34.185988 WL = 0x4
2131 01:02:34.189191 RL = 0x4
2132 01:02:34.189760 BL = 0x2
2133 01:02:34.192035 RPST = 0x0
2134 01:02:34.192606 RD_PRE = 0x0
2135 01:02:34.195334 WR_PRE = 0x1
2136 01:02:34.195805 WR_PST = 0x0
2137 01:02:34.199009 DBI_WR = 0x0
2138 01:02:34.202198 DBI_RD = 0x0
2139 01:02:34.202670 OTF = 0x1
2140 01:02:34.205304 ===================================
2141 01:02:34.208953 ===================================
2142 01:02:34.209525 ANA top config
2143 01:02:34.212187 ===================================
2144 01:02:34.215359 DLL_ASYNC_EN = 0
2145 01:02:34.218506 ALL_SLAVE_EN = 0
2146 01:02:34.222228 NEW_RANK_MODE = 1
2147 01:02:34.222708 DLL_IDLE_MODE = 1
2148 01:02:34.225566 LP45_APHY_COMB_EN = 1
2149 01:02:34.229231 TX_ODT_DIS = 1
2150 01:02:34.231826 NEW_8X_MODE = 1
2151 01:02:34.235430 ===================================
2152 01:02:34.238828 ===================================
2153 01:02:34.242077 data_rate = 2400
2154 01:02:34.245491 CKR = 1
2155 01:02:34.246001 DQ_P2S_RATIO = 8
2156 01:02:34.249082 ===================================
2157 01:02:34.252264 CA_P2S_RATIO = 8
2158 01:02:34.255308 DQ_CA_OPEN = 0
2159 01:02:34.259049 DQ_SEMI_OPEN = 0
2160 01:02:34.262141 CA_SEMI_OPEN = 0
2161 01:02:34.262614 CA_FULL_RATE = 0
2162 01:02:34.265492 DQ_CKDIV4_EN = 0
2163 01:02:34.268871 CA_CKDIV4_EN = 0
2164 01:02:34.272400 CA_PREDIV_EN = 0
2165 01:02:34.275564 PH8_DLY = 17
2166 01:02:34.278903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 01:02:34.279479 DQ_AAMCK_DIV = 4
2168 01:02:34.282901 CA_AAMCK_DIV = 4
2169 01:02:34.286005 CA_ADMCK_DIV = 4
2170 01:02:34.288610 DQ_TRACK_CA_EN = 0
2171 01:02:34.292143 CA_PICK = 1200
2172 01:02:34.295890 CA_MCKIO = 1200
2173 01:02:34.298824 MCKIO_SEMI = 0
2174 01:02:34.299415 PLL_FREQ = 2366
2175 01:02:34.302389 DQ_UI_PI_RATIO = 32
2176 01:02:34.305243 CA_UI_PI_RATIO = 0
2177 01:02:34.309181 ===================================
2178 01:02:34.312047 ===================================
2179 01:02:34.315620 memory_type:LPDDR4
2180 01:02:34.316092 GP_NUM : 10
2181 01:02:34.318904 SRAM_EN : 1
2182 01:02:34.322345 MD32_EN : 0
2183 01:02:34.326920 ===================================
2184 01:02:34.327491 [ANA_INIT] >>>>>>>>>>>>>>
2185 01:02:34.328620 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 01:02:34.331962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 01:02:34.335757 ===================================
2188 01:02:34.338825 data_rate = 2400,PCW = 0X5b00
2189 01:02:34.342193 ===================================
2190 01:02:34.345555 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 01:02:34.352432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 01:02:34.355495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 01:02:34.362257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 01:02:34.365444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 01:02:34.368859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 01:02:34.369339 [ANA_INIT] flow start
2197 01:02:34.372194 [ANA_INIT] PLL >>>>>>>>
2198 01:02:34.375554 [ANA_INIT] PLL <<<<<<<<
2199 01:02:34.376133 [ANA_INIT] MIDPI >>>>>>>>
2200 01:02:34.379544 [ANA_INIT] MIDPI <<<<<<<<
2201 01:02:34.382678 [ANA_INIT] DLL >>>>>>>>
2202 01:02:34.385615 [ANA_INIT] DLL <<<<<<<<
2203 01:02:34.386114 [ANA_INIT] flow end
2204 01:02:34.388914 ============ LP4 DIFF to SE enter ============
2205 01:02:34.395835 ============ LP4 DIFF to SE exit ============
2206 01:02:34.396418 [ANA_INIT] <<<<<<<<<<<<<
2207 01:02:34.398742 [Flow] Enable top DCM control >>>>>
2208 01:02:34.402490 [Flow] Enable top DCM control <<<<<
2209 01:02:34.405514 Enable DLL master slave shuffle
2210 01:02:34.412418 ==============================================================
2211 01:02:34.413038 Gating Mode config
2212 01:02:34.419102 ==============================================================
2213 01:02:34.422078 Config description:
2214 01:02:34.429016 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 01:02:34.435968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 01:02:34.442414 SELPH_MODE 0: By rank 1: By Phase
2217 01:02:34.449038 ==============================================================
2218 01:02:34.449623 GAT_TRACK_EN = 1
2219 01:02:34.452360 RX_GATING_MODE = 2
2220 01:02:34.455545 RX_GATING_TRACK_MODE = 2
2221 01:02:34.459024 SELPH_MODE = 1
2222 01:02:34.462306 PICG_EARLY_EN = 1
2223 01:02:34.465883 VALID_LAT_VALUE = 1
2224 01:02:34.472518 ==============================================================
2225 01:02:34.475840 Enter into Gating configuration >>>>
2226 01:02:34.478800 Exit from Gating configuration <<<<
2227 01:02:34.482568 Enter into DVFS_PRE_config >>>>>
2228 01:02:34.492248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 01:02:34.495370 Exit from DVFS_PRE_config <<<<<
2230 01:02:34.499181 Enter into PICG configuration >>>>
2231 01:02:34.502288 Exit from PICG configuration <<<<
2232 01:02:34.505978 [RX_INPUT] configuration >>>>>
2233 01:02:34.506570 [RX_INPUT] configuration <<<<<
2234 01:02:34.512515 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 01:02:34.518430 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 01:02:34.521836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 01:02:34.528793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 01:02:34.535430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 01:02:34.542163 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 01:02:34.545810 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 01:02:34.548967 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 01:02:34.555599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 01:02:34.559160 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 01:02:34.562204 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 01:02:34.565751 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 01:02:34.569194 ===================================
2247 01:02:34.572579 LPDDR4 DRAM CONFIGURATION
2248 01:02:34.575691 ===================================
2249 01:02:34.579056 EX_ROW_EN[0] = 0x0
2250 01:02:34.579626 EX_ROW_EN[1] = 0x0
2251 01:02:34.582282 LP4Y_EN = 0x0
2252 01:02:34.582883 WORK_FSP = 0x0
2253 01:02:34.585578 WL = 0x4
2254 01:02:34.586195 RL = 0x4
2255 01:02:34.588568 BL = 0x2
2256 01:02:34.589035 RPST = 0x0
2257 01:02:34.592395 RD_PRE = 0x0
2258 01:02:34.592964 WR_PRE = 0x1
2259 01:02:34.595796 WR_PST = 0x0
2260 01:02:34.596365 DBI_WR = 0x0
2261 01:02:34.599004 DBI_RD = 0x0
2262 01:02:34.599636 OTF = 0x1
2263 01:02:34.602415 ===================================
2264 01:02:34.609168 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 01:02:34.612858 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 01:02:34.615527 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 01:02:34.618899 ===================================
2268 01:02:34.622152 LPDDR4 DRAM CONFIGURATION
2269 01:02:34.625634 ===================================
2270 01:02:34.629126 EX_ROW_EN[0] = 0x10
2271 01:02:34.629690 EX_ROW_EN[1] = 0x0
2272 01:02:34.632386 LP4Y_EN = 0x0
2273 01:02:34.632961 WORK_FSP = 0x0
2274 01:02:34.635406 WL = 0x4
2275 01:02:34.635878 RL = 0x4
2276 01:02:34.639015 BL = 0x2
2277 01:02:34.639606 RPST = 0x0
2278 01:02:34.642336 RD_PRE = 0x0
2279 01:02:34.642807 WR_PRE = 0x1
2280 01:02:34.645648 WR_PST = 0x0
2281 01:02:34.646154 DBI_WR = 0x0
2282 01:02:34.649702 DBI_RD = 0x0
2283 01:02:34.650322 OTF = 0x1
2284 01:02:34.652733 ===================================
2285 01:02:34.659125 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 01:02:34.659694 ==
2287 01:02:34.662613 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 01:02:34.665881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 01:02:34.669114 ==
2290 01:02:34.669591 [Duty_Offset_Calibration]
2291 01:02:34.672331 B0:2 B1:0 CA:1
2292 01:02:34.672899
2293 01:02:34.675751 [DutyScan_Calibration_Flow] k_type=0
2294 01:02:34.682924
2295 01:02:34.683380 ==CLK 0==
2296 01:02:34.686589 Final CLK duty delay cell = -4
2297 01:02:34.689927 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2298 01:02:34.693522 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2299 01:02:34.696566 [-4] AVG Duty = 4953%(X100)
2300 01:02:34.697027
2301 01:02:34.700244 CH0 CLK Duty spec in!! Max-Min= 156%
2302 01:02:34.703724 [DutyScan_Calibration_Flow] ====Done====
2303 01:02:34.704281
2304 01:02:34.706853 [DutyScan_Calibration_Flow] k_type=1
2305 01:02:34.722368
2306 01:02:34.722919 ==DQS 0 ==
2307 01:02:34.725786 Final DQS duty delay cell = 0
2308 01:02:34.728606 [0] MAX Duty = 5187%(X100), DQS PI = 32
2309 01:02:34.731884 [0] MIN Duty = 4938%(X100), DQS PI = 0
2310 01:02:34.732349 [0] AVG Duty = 5062%(X100)
2311 01:02:34.735461
2312 01:02:34.735969 ==DQS 1 ==
2313 01:02:34.738416 Final DQS duty delay cell = -4
2314 01:02:34.742477 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2315 01:02:34.745383 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2316 01:02:34.748740 [-4] AVG Duty = 5031%(X100)
2317 01:02:34.749249
2318 01:02:34.752137 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2319 01:02:34.752649
2320 01:02:34.754995 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2321 01:02:34.758271 [DutyScan_Calibration_Flow] ====Done====
2322 01:02:34.758689
2323 01:02:34.761991 [DutyScan_Calibration_Flow] k_type=3
2324 01:02:34.779351
2325 01:02:34.779904 ==DQM 0 ==
2326 01:02:34.782212 Final DQM duty delay cell = 0
2327 01:02:34.786346 [0] MAX Duty = 5062%(X100), DQS PI = 24
2328 01:02:34.789097 [0] MIN Duty = 4844%(X100), DQS PI = 0
2329 01:02:34.789560 [0] AVG Duty = 4953%(X100)
2330 01:02:34.789929
2331 01:02:34.792812 ==DQM 1 ==
2332 01:02:34.796020 Final DQM duty delay cell = 0
2333 01:02:34.799520 [0] MAX Duty = 5187%(X100), DQS PI = 46
2334 01:02:34.802706 [0] MIN Duty = 5000%(X100), DQS PI = 10
2335 01:02:34.803263 [0] AVG Duty = 5093%(X100)
2336 01:02:34.803637
2337 01:02:34.809337 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2338 01:02:34.809897
2339 01:02:34.812342 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2340 01:02:34.815480 [DutyScan_Calibration_Flow] ====Done====
2341 01:02:34.815942
2342 01:02:34.818582 [DutyScan_Calibration_Flow] k_type=2
2343 01:02:34.834829
2344 01:02:34.835382 ==DQ 0 ==
2345 01:02:34.838118 Final DQ duty delay cell = -4
2346 01:02:34.841923 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2347 01:02:34.845115 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2348 01:02:34.847653 [-4] AVG Duty = 4953%(X100)
2349 01:02:34.848138
2350 01:02:34.848501 ==DQ 1 ==
2351 01:02:34.851632 Final DQ duty delay cell = 0
2352 01:02:34.854845 [0] MAX Duty = 4969%(X100), DQS PI = 56
2353 01:02:34.857853 [0] MIN Duty = 4907%(X100), DQS PI = 0
2354 01:02:34.858372 [0] AVG Duty = 4938%(X100)
2355 01:02:34.861058
2356 01:02:34.864608 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2357 01:02:34.865183
2358 01:02:34.868177 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2359 01:02:34.871081 [DutyScan_Calibration_Flow] ====Done====
2360 01:02:34.871559 ==
2361 01:02:34.874849 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 01:02:34.878009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 01:02:34.878599 ==
2364 01:02:34.881369 [Duty_Offset_Calibration]
2365 01:02:34.881970 B0:0 B1:-1 CA:2
2366 01:02:34.882372
2367 01:02:34.884250 [DutyScan_Calibration_Flow] k_type=0
2368 01:02:34.895162
2369 01:02:34.895728 ==CLK 0==
2370 01:02:34.898171 Final CLK duty delay cell = 0
2371 01:02:34.902063 [0] MAX Duty = 5156%(X100), DQS PI = 16
2372 01:02:34.905584 [0] MIN Duty = 4938%(X100), DQS PI = 44
2373 01:02:34.906196 [0] AVG Duty = 5047%(X100)
2374 01:02:34.908573
2375 01:02:34.909142 CH1 CLK Duty spec in!! Max-Min= 218%
2376 01:02:34.914844 [DutyScan_Calibration_Flow] ====Done====
2377 01:02:34.915424
2378 01:02:34.918239 [DutyScan_Calibration_Flow] k_type=1
2379 01:02:34.934673
2380 01:02:34.935235 ==DQS 0 ==
2381 01:02:34.937642 Final DQS duty delay cell = 0
2382 01:02:34.940857 [0] MAX Duty = 5093%(X100), DQS PI = 24
2383 01:02:34.944715 [0] MIN Duty = 4969%(X100), DQS PI = 0
2384 01:02:34.945292 [0] AVG Duty = 5031%(X100)
2385 01:02:34.947488
2386 01:02:34.947983 ==DQS 1 ==
2387 01:02:34.950793 Final DQS duty delay cell = 0
2388 01:02:34.954070 [0] MAX Duty = 5156%(X100), DQS PI = 0
2389 01:02:34.957732 [0] MIN Duty = 4844%(X100), DQS PI = 36
2390 01:02:34.958392 [0] AVG Duty = 5000%(X100)
2391 01:02:34.961082
2392 01:02:34.964230 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2393 01:02:34.964802
2394 01:02:34.967702 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2395 01:02:34.970911 [DutyScan_Calibration_Flow] ====Done====
2396 01:02:34.971387
2397 01:02:34.974020 [DutyScan_Calibration_Flow] k_type=3
2398 01:02:34.991134
2399 01:02:34.991701 ==DQM 0 ==
2400 01:02:34.994012 Final DQM duty delay cell = 4
2401 01:02:34.997341 [4] MAX Duty = 5124%(X100), DQS PI = 22
2402 01:02:35.001161 [4] MIN Duty = 4969%(X100), DQS PI = 28
2403 01:02:35.001737 [4] AVG Duty = 5046%(X100)
2404 01:02:35.004175
2405 01:02:35.004742 ==DQM 1 ==
2406 01:02:35.007976 Final DQM duty delay cell = -4
2407 01:02:35.010800 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2408 01:02:35.014280 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2409 01:02:35.017441 [-4] AVG Duty = 4875%(X100)
2410 01:02:35.018082
2411 01:02:35.020618 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2412 01:02:35.021122
2413 01:02:35.023861 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2414 01:02:35.027656 [DutyScan_Calibration_Flow] ====Done====
2415 01:02:35.028225
2416 01:02:35.030841 [DutyScan_Calibration_Flow] k_type=2
2417 01:02:35.047924
2418 01:02:35.048493 ==DQ 0 ==
2419 01:02:35.051485 Final DQ duty delay cell = 0
2420 01:02:35.054660 [0] MAX Duty = 5062%(X100), DQS PI = 20
2421 01:02:35.057816 [0] MIN Duty = 4938%(X100), DQS PI = 0
2422 01:02:35.058429 [0] AVG Duty = 5000%(X100)
2423 01:02:35.058815
2424 01:02:35.061385 ==DQ 1 ==
2425 01:02:35.064724 Final DQ duty delay cell = 0
2426 01:02:35.068169 [0] MAX Duty = 5031%(X100), DQS PI = 0
2427 01:02:35.070981 [0] MIN Duty = 4813%(X100), DQS PI = 34
2428 01:02:35.071463 [0] AVG Duty = 4922%(X100)
2429 01:02:35.071925
2430 01:02:35.074478 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2431 01:02:35.075046
2432 01:02:35.077798 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2433 01:02:35.084473 [DutyScan_Calibration_Flow] ====Done====
2434 01:02:35.087507 nWR fixed to 30
2435 01:02:35.087985 [ModeRegInit_LP4] CH0 RK0
2436 01:02:35.090985 [ModeRegInit_LP4] CH0 RK1
2437 01:02:35.094590 [ModeRegInit_LP4] CH1 RK0
2438 01:02:35.095161 [ModeRegInit_LP4] CH1 RK1
2439 01:02:35.097927 match AC timing 7
2440 01:02:35.101289 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 01:02:35.104924 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 01:02:35.111076 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 01:02:35.114772 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 01:02:35.121200 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 01:02:35.121751 ==
2446 01:02:35.124403 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 01:02:35.127620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 01:02:35.128093 ==
2449 01:02:35.134448 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 01:02:35.137761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2451 01:02:35.147322 [CA 0] Center 38 (7~69) winsize 63
2452 01:02:35.150905 [CA 1] Center 38 (7~69) winsize 63
2453 01:02:35.154104 [CA 2] Center 34 (4~65) winsize 62
2454 01:02:35.157383 [CA 3] Center 34 (4~65) winsize 62
2455 01:02:35.160699 [CA 4] Center 34 (4~64) winsize 61
2456 01:02:35.164525 [CA 5] Center 32 (2~63) winsize 62
2457 01:02:35.165100
2458 01:02:35.167597 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2459 01:02:35.168167
2460 01:02:35.171012 [CATrainingPosCal] consider 1 rank data
2461 01:02:35.174310 u2DelayCellTimex100 = 270/100 ps
2462 01:02:35.177452 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2463 01:02:35.180815 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2464 01:02:35.188032 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2465 01:02:35.190870 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 01:02:35.194203 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2467 01:02:35.197195 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2468 01:02:35.197676
2469 01:02:35.201471 CA PerBit enable=1, Macro0, CA PI delay=32
2470 01:02:35.202085
2471 01:02:35.207063 [CBTSetCACLKResult] CA Dly = 32
2472 01:02:35.207637 CS Dly: 6 (0~37)
2473 01:02:35.208017 ==
2474 01:02:35.208374 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 01:02:35.214093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 01:02:35.214660 ==
2477 01:02:35.217632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 01:02:35.224329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2479 01:02:35.233038 [CA 0] Center 38 (8~69) winsize 62
2480 01:02:35.236440 [CA 1] Center 38 (7~69) winsize 63
2481 01:02:35.240166 [CA 2] Center 35 (5~66) winsize 62
2482 01:02:35.242735 [CA 3] Center 35 (5~66) winsize 62
2483 01:02:35.246526 [CA 4] Center 34 (4~65) winsize 62
2484 01:02:35.250008 [CA 5] Center 33 (3~64) winsize 62
2485 01:02:35.250578
2486 01:02:35.253242 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 01:02:35.253823
2488 01:02:35.256384 [CATrainingPosCal] consider 2 rank data
2489 01:02:35.259687 u2DelayCellTimex100 = 270/100 ps
2490 01:02:35.263398 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2491 01:02:35.266320 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2492 01:02:35.272966 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2493 01:02:35.276152 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2494 01:02:35.279657 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2495 01:02:35.283101 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2496 01:02:35.283668
2497 01:02:35.286540 CA PerBit enable=1, Macro0, CA PI delay=33
2498 01:02:35.287117
2499 01:02:35.289550 [CBTSetCACLKResult] CA Dly = 33
2500 01:02:35.290151 CS Dly: 7 (0~39)
2501 01:02:35.290537
2502 01:02:35.293048 ----->DramcWriteLeveling(PI) begin...
2503 01:02:35.296465 ==
2504 01:02:35.299684 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 01:02:35.303299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 01:02:35.303881 ==
2507 01:02:35.306241 Write leveling (Byte 0): 32 => 32
2508 01:02:35.309897 Write leveling (Byte 1): 30 => 30
2509 01:02:35.313045 DramcWriteLeveling(PI) end<-----
2510 01:02:35.313622
2511 01:02:35.314032 ==
2512 01:02:35.316042 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 01:02:35.319379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 01:02:35.319869 ==
2515 01:02:35.322658 [Gating] SW mode calibration
2516 01:02:35.330169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 01:02:35.332950 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 01:02:35.339699 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2519 01:02:35.342669 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2520 01:02:35.346192 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 01:02:35.352805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 01:02:35.356196 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 01:02:35.359662 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 01:02:35.366253 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2525 01:02:35.369883 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2526 01:02:35.373301 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2527 01:02:35.379770 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 01:02:35.383178 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 01:02:35.386412 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 01:02:35.392837 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 01:02:35.396551 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 01:02:35.399456 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
2533 01:02:35.406561 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2534 01:02:35.410115 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2535 01:02:35.412850 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 01:02:35.419840 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 01:02:35.422747 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 01:02:35.426585 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 01:02:35.429557 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 01:02:35.436639 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 01:02:35.440026 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2542 01:02:35.443345 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 01:02:35.449742 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 01:02:35.453022 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 01:02:35.456555 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 01:02:35.462903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 01:02:35.466461 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 01:02:35.470442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 01:02:35.476486 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 01:02:35.479534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 01:02:35.483180 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 01:02:35.489925 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 01:02:35.493186 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 01:02:35.496494 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 01:02:35.503368 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 01:02:35.506607 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 01:02:35.509585 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 01:02:35.513039 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 01:02:35.516307 Total UI for P1: 0, mck2ui 16
2560 01:02:35.519651 best dqsien dly found for B0: ( 1, 3, 28)
2561 01:02:35.527786 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 01:02:35.530375 Total UI for P1: 0, mck2ui 16
2563 01:02:35.533491 best dqsien dly found for B1: ( 1, 4, 0)
2564 01:02:35.536321 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 01:02:35.539763 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 01:02:35.540338
2567 01:02:35.542857 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 01:02:35.546455 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 01:02:35.549669 [Gating] SW calibration Done
2570 01:02:35.550283 ==
2571 01:02:35.553242 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 01:02:35.556747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 01:02:35.557325 ==
2574 01:02:35.559680 RX Vref Scan: 0
2575 01:02:35.560254
2576 01:02:35.560629 RX Vref 0 -> 0, step: 1
2577 01:02:35.560976
2578 01:02:35.562695 RX Delay -40 -> 252, step: 8
2579 01:02:35.566376 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2580 01:02:35.573304 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2581 01:02:35.576971 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 01:02:35.579914 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 01:02:35.583283 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2584 01:02:35.586627 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 01:02:35.593063 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 01:02:35.597112 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 01:02:35.599609 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 01:02:35.603039 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2589 01:02:35.606851 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2590 01:02:35.613092 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 01:02:35.616596 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2592 01:02:35.619487 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2593 01:02:35.623164 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 01:02:35.626278 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2595 01:02:35.629548 ==
2596 01:02:35.630061 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 01:02:35.636848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 01:02:35.637419 ==
2599 01:02:35.637801 DQS Delay:
2600 01:02:35.639750 DQS0 = 0, DQS1 = 0
2601 01:02:35.640218 DQM Delay:
2602 01:02:35.643096 DQM0 = 122, DQM1 = 110
2603 01:02:35.643665 DQ Delay:
2604 01:02:35.646542 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2605 01:02:35.649510 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2606 01:02:35.653093 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2607 01:02:35.656690 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2608 01:02:35.657262
2609 01:02:35.657636
2610 01:02:35.658022 ==
2611 01:02:35.660095 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 01:02:35.663235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 01:02:35.666307 ==
2614 01:02:35.666778
2615 01:02:35.667152
2616 01:02:35.667499 TX Vref Scan disable
2617 01:02:35.669780 == TX Byte 0 ==
2618 01:02:35.673386 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2619 01:02:35.676690 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2620 01:02:35.680012 == TX Byte 1 ==
2621 01:02:35.683265 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2622 01:02:35.686585 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2623 01:02:35.687154 ==
2624 01:02:35.689863 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 01:02:35.696530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 01:02:35.697098 ==
2627 01:02:35.707371 TX Vref=22, minBit 7, minWin=23, winSum=399
2628 01:02:35.710659 TX Vref=24, minBit 4, minWin=24, winSum=405
2629 01:02:35.714016 TX Vref=26, minBit 0, minWin=25, winSum=407
2630 01:02:35.717188 TX Vref=28, minBit 4, minWin=24, winSum=410
2631 01:02:35.720411 TX Vref=30, minBit 1, minWin=25, winSum=418
2632 01:02:35.724121 TX Vref=32, minBit 1, minWin=25, winSum=411
2633 01:02:35.730605 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 30
2634 01:02:35.731161
2635 01:02:35.733886 Final TX Range 1 Vref 30
2636 01:02:35.734388
2637 01:02:35.734763 ==
2638 01:02:35.737468 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 01:02:35.740854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 01:02:35.741439 ==
2641 01:02:35.741822
2642 01:02:35.742226
2643 01:02:35.744314 TX Vref Scan disable
2644 01:02:35.747710 == TX Byte 0 ==
2645 01:02:35.751178 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2646 01:02:35.753820 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2647 01:02:35.757764 == TX Byte 1 ==
2648 01:02:35.760656 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2649 01:02:35.764030 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2650 01:02:35.764497
2651 01:02:35.767420 [DATLAT]
2652 01:02:35.767909 Freq=1200, CH0 RK0
2653 01:02:35.768493
2654 01:02:35.770807 DATLAT Default: 0xd
2655 01:02:35.771236 0, 0xFFFF, sum = 0
2656 01:02:35.774277 1, 0xFFFF, sum = 0
2657 01:02:35.774709 2, 0xFFFF, sum = 0
2658 01:02:35.777746 3, 0xFFFF, sum = 0
2659 01:02:35.778203 4, 0xFFFF, sum = 0
2660 01:02:35.781172 5, 0xFFFF, sum = 0
2661 01:02:35.781701 6, 0xFFFF, sum = 0
2662 01:02:35.784507 7, 0xFFFF, sum = 0
2663 01:02:35.785039 8, 0xFFFF, sum = 0
2664 01:02:35.787693 9, 0xFFFF, sum = 0
2665 01:02:35.788223 10, 0xFFFF, sum = 0
2666 01:02:35.791250 11, 0xFFFF, sum = 0
2667 01:02:35.791780 12, 0x0, sum = 1
2668 01:02:35.794460 13, 0x0, sum = 2
2669 01:02:35.794989 14, 0x0, sum = 3
2670 01:02:35.797575 15, 0x0, sum = 4
2671 01:02:35.798345 best_step = 13
2672 01:02:35.798731
2673 01:02:35.799053 ==
2674 01:02:35.801114 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 01:02:35.807722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 01:02:35.808249 ==
2677 01:02:35.808598 RX Vref Scan: 1
2678 01:02:35.808920
2679 01:02:35.811221 Set Vref Range= 32 -> 127
2680 01:02:35.811743
2681 01:02:35.814606 RX Vref 32 -> 127, step: 1
2682 01:02:35.815134
2683 01:02:35.815477 RX Delay -13 -> 252, step: 4
2684 01:02:35.818187
2685 01:02:35.818710 Set Vref, RX VrefLevel [Byte0]: 32
2686 01:02:35.821060 [Byte1]: 32
2687 01:02:35.825701
2688 01:02:35.826168 Set Vref, RX VrefLevel [Byte0]: 33
2689 01:02:35.828440 [Byte1]: 33
2690 01:02:35.833430
2691 01:02:35.833986 Set Vref, RX VrefLevel [Byte0]: 34
2692 01:02:35.836912 [Byte1]: 34
2693 01:02:35.841258
2694 01:02:35.841783 Set Vref, RX VrefLevel [Byte0]: 35
2695 01:02:35.844709 [Byte1]: 35
2696 01:02:35.849599
2697 01:02:35.850167 Set Vref, RX VrefLevel [Byte0]: 36
2698 01:02:35.852391 [Byte1]: 36
2699 01:02:35.857024
2700 01:02:35.857455 Set Vref, RX VrefLevel [Byte0]: 37
2701 01:02:35.860476 [Byte1]: 37
2702 01:02:35.864950
2703 01:02:35.865481 Set Vref, RX VrefLevel [Byte0]: 38
2704 01:02:35.868121 [Byte1]: 38
2705 01:02:35.873378
2706 01:02:35.873921 Set Vref, RX VrefLevel [Byte0]: 39
2707 01:02:35.876562 [Byte1]: 39
2708 01:02:35.880763
2709 01:02:35.881297 Set Vref, RX VrefLevel [Byte0]: 40
2710 01:02:35.884344 [Byte1]: 40
2711 01:02:35.888998
2712 01:02:35.889523 Set Vref, RX VrefLevel [Byte0]: 41
2713 01:02:35.892119 [Byte1]: 41
2714 01:02:35.896817
2715 01:02:35.897344 Set Vref, RX VrefLevel [Byte0]: 42
2716 01:02:35.899655 [Byte1]: 42
2717 01:02:35.904853
2718 01:02:35.905377 Set Vref, RX VrefLevel [Byte0]: 43
2719 01:02:35.910793 [Byte1]: 43
2720 01:02:35.911319
2721 01:02:35.913985 Set Vref, RX VrefLevel [Byte0]: 44
2722 01:02:35.917455 [Byte1]: 44
2723 01:02:35.918036
2724 01:02:35.920527 Set Vref, RX VrefLevel [Byte0]: 45
2725 01:02:35.923794 [Byte1]: 45
2726 01:02:35.928099
2727 01:02:35.928523 Set Vref, RX VrefLevel [Byte0]: 46
2728 01:02:35.931447 [Byte1]: 46
2729 01:02:35.936038
2730 01:02:35.936559 Set Vref, RX VrefLevel [Byte0]: 47
2731 01:02:35.939683 [Byte1]: 47
2732 01:02:35.943967
2733 01:02:35.944491 Set Vref, RX VrefLevel [Byte0]: 48
2734 01:02:35.947083 [Byte1]: 48
2735 01:02:35.951614
2736 01:02:35.952139 Set Vref, RX VrefLevel [Byte0]: 49
2737 01:02:35.954716 [Byte1]: 49
2738 01:02:35.959417
2739 01:02:35.959842 Set Vref, RX VrefLevel [Byte0]: 50
2740 01:02:35.962885 [Byte1]: 50
2741 01:02:35.967468
2742 01:02:35.967988 Set Vref, RX VrefLevel [Byte0]: 51
2743 01:02:35.970474 [Byte1]: 51
2744 01:02:35.975648
2745 01:02:35.976174 Set Vref, RX VrefLevel [Byte0]: 52
2746 01:02:35.978859 [Byte1]: 52
2747 01:02:35.983344
2748 01:02:35.983866 Set Vref, RX VrefLevel [Byte0]: 53
2749 01:02:35.986662 [Byte1]: 53
2750 01:02:35.991128
2751 01:02:35.991651 Set Vref, RX VrefLevel [Byte0]: 54
2752 01:02:35.994946 [Byte1]: 54
2753 01:02:35.999012
2754 01:02:35.999535 Set Vref, RX VrefLevel [Byte0]: 55
2755 01:02:36.002361 [Byte1]: 55
2756 01:02:36.006837
2757 01:02:36.007461 Set Vref, RX VrefLevel [Byte0]: 56
2758 01:02:36.010189 [Byte1]: 56
2759 01:02:36.015138
2760 01:02:36.015667 Set Vref, RX VrefLevel [Byte0]: 57
2761 01:02:36.018568 [Byte1]: 57
2762 01:02:36.022429
2763 01:02:36.023077 Set Vref, RX VrefLevel [Byte0]: 58
2764 01:02:36.026213 [Byte1]: 58
2765 01:02:36.030565
2766 01:02:36.031087 Set Vref, RX VrefLevel [Byte0]: 59
2767 01:02:36.034580 [Byte1]: 59
2768 01:02:36.038880
2769 01:02:36.039407 Set Vref, RX VrefLevel [Byte0]: 60
2770 01:02:36.041632 [Byte1]: 60
2771 01:02:36.046499
2772 01:02:36.047022 Set Vref, RX VrefLevel [Byte0]: 61
2773 01:02:36.050102 [Byte1]: 61
2774 01:02:36.054312
2775 01:02:36.054846 Set Vref, RX VrefLevel [Byte0]: 62
2776 01:02:36.057679 [Byte1]: 62
2777 01:02:36.061876
2778 01:02:36.062333 Set Vref, RX VrefLevel [Byte0]: 63
2779 01:02:36.065499 [Byte1]: 63
2780 01:02:36.069776
2781 01:02:36.070249 Set Vref, RX VrefLevel [Byte0]: 64
2782 01:02:36.073282 [Byte1]: 64
2783 01:02:36.077766
2784 01:02:36.078326 Set Vref, RX VrefLevel [Byte0]: 65
2785 01:02:36.081081 [Byte1]: 65
2786 01:02:36.085755
2787 01:02:36.086301 Set Vref, RX VrefLevel [Byte0]: 66
2788 01:02:36.089281 [Byte1]: 66
2789 01:02:36.093639
2790 01:02:36.094199 Set Vref, RX VrefLevel [Byte0]: 67
2791 01:02:36.096939 [Byte1]: 67
2792 01:02:36.102035
2793 01:02:36.102561 Set Vref, RX VrefLevel [Byte0]: 68
2794 01:02:36.105038 [Byte1]: 68
2795 01:02:36.109426
2796 01:02:36.110013 Set Vref, RX VrefLevel [Byte0]: 69
2797 01:02:36.112639 [Byte1]: 69
2798 01:02:36.117417
2799 01:02:36.117970 Final RX Vref Byte 0 = 59 to rank0
2800 01:02:36.120884 Final RX Vref Byte 1 = 50 to rank0
2801 01:02:36.124384 Final RX Vref Byte 0 = 59 to rank1
2802 01:02:36.127077 Final RX Vref Byte 1 = 50 to rank1==
2803 01:02:36.130601 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 01:02:36.137363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 01:02:36.137891 ==
2806 01:02:36.138279 DQS Delay:
2807 01:02:36.138601 DQS0 = 0, DQS1 = 0
2808 01:02:36.140869 DQM Delay:
2809 01:02:36.141291 DQM0 = 122, DQM1 = 109
2810 01:02:36.144064 DQ Delay:
2811 01:02:36.147841 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2812 01:02:36.150840 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2813 01:02:36.154036 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2814 01:02:36.157670 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2815 01:02:36.158249
2816 01:02:36.158593
2817 01:02:36.164119 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2818 01:02:36.167431 CH0 RK0: MR19=404, MR18=A07
2819 01:02:36.174066 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2820 01:02:36.174591
2821 01:02:36.177124 ----->DramcWriteLeveling(PI) begin...
2822 01:02:36.177652 ==
2823 01:02:36.180857 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 01:02:36.183641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 01:02:36.184074 ==
2826 01:02:36.187343 Write leveling (Byte 0): 33 => 33
2827 01:02:36.190568 Write leveling (Byte 1): 30 => 30
2828 01:02:36.193886 DramcWriteLeveling(PI) end<-----
2829 01:02:36.194446
2830 01:02:36.194789 ==
2831 01:02:36.197288 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 01:02:36.204382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 01:02:36.204920 ==
2834 01:02:36.205266 [Gating] SW mode calibration
2835 01:02:36.214448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 01:02:36.217615 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 01:02:36.220882 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2838 01:02:36.227317 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 01:02:36.230803 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 01:02:36.233760 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 01:02:36.240715 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 01:02:36.244254 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 01:02:36.247330 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 01:02:36.254340 0 15 28 | B1->B0 | 3030 2b2b | 0 0 | (0 1) (1 0)
2845 01:02:36.257481 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 01:02:36.260952 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 01:02:36.267442 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 01:02:36.270838 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 01:02:36.273917 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 01:02:36.280701 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 01:02:36.283895 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2852 01:02:36.288239 1 0 28 | B1->B0 | 3535 3f3f | 1 0 | (0 0) (0 0)
2853 01:02:36.292529 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 01:02:36.297514 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 01:02:36.300989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 01:02:36.304269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 01:02:36.310755 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 01:02:36.313698 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 01:02:36.317417 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 01:02:36.324170 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2861 01:02:36.327124 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2862 01:02:36.330840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 01:02:36.337935 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 01:02:36.340838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 01:02:36.344232 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 01:02:36.350725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 01:02:36.354396 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 01:02:36.357867 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 01:02:36.364118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 01:02:36.367477 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 01:02:36.370811 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 01:02:36.374387 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 01:02:36.380944 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 01:02:36.384219 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 01:02:36.387471 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2876 01:02:36.394120 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2877 01:02:36.398025 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 01:02:36.401102 Total UI for P1: 0, mck2ui 16
2879 01:02:36.404392 best dqsien dly found for B0: ( 1, 3, 26)
2880 01:02:36.407438 Total UI for P1: 0, mck2ui 16
2881 01:02:36.410937 best dqsien dly found for B1: ( 1, 3, 28)
2882 01:02:36.413918 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2883 01:02:36.417816 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2884 01:02:36.418431
2885 01:02:36.420839 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2886 01:02:36.423891 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2887 01:02:36.427727 [Gating] SW calibration Done
2888 01:02:36.428196 ==
2889 01:02:36.430743 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 01:02:36.434278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 01:02:36.437514 ==
2892 01:02:36.438137 RX Vref Scan: 0
2893 01:02:36.438519
2894 01:02:36.441100 RX Vref 0 -> 0, step: 1
2895 01:02:36.441826
2896 01:02:36.444191 RX Delay -40 -> 252, step: 8
2897 01:02:36.447496 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2898 01:02:36.450688 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2899 01:02:36.454541 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2900 01:02:36.457886 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2901 01:02:36.461302 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2902 01:02:36.467733 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2903 01:02:36.471349 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2904 01:02:36.473988 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2905 01:02:36.477642 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2906 01:02:36.481298 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2907 01:02:36.487672 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2908 01:02:36.490890 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2909 01:02:36.493997 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2910 01:02:36.497686 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2911 01:02:36.500583 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2912 01:02:36.507473 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2913 01:02:36.508051 ==
2914 01:02:36.510609 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 01:02:36.514243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 01:02:36.514843 ==
2917 01:02:36.515225 DQS Delay:
2918 01:02:36.517542 DQS0 = 0, DQS1 = 0
2919 01:02:36.518153 DQM Delay:
2920 01:02:36.520706 DQM0 = 120, DQM1 = 108
2921 01:02:36.521173 DQ Delay:
2922 01:02:36.524273 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2923 01:02:36.527472 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2924 01:02:36.530938 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2925 01:02:36.534747 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2926 01:02:36.535346
2927 01:02:36.535729
2928 01:02:36.537456 ==
2929 01:02:36.541095 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 01:02:36.544352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 01:02:36.544931 ==
2932 01:02:36.545312
2933 01:02:36.545658
2934 01:02:36.547790 TX Vref Scan disable
2935 01:02:36.548364 == TX Byte 0 ==
2936 01:02:36.550965 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2937 01:02:36.557912 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2938 01:02:36.558529 == TX Byte 1 ==
2939 01:02:36.561021 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2940 01:02:36.567961 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2941 01:02:36.568542 ==
2942 01:02:36.571188 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 01:02:36.574110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 01:02:36.574586 ==
2945 01:02:36.586321 TX Vref=22, minBit 1, minWin=24, winSum=403
2946 01:02:36.590108 TX Vref=24, minBit 0, minWin=25, winSum=409
2947 01:02:36.593108 TX Vref=26, minBit 0, minWin=25, winSum=412
2948 01:02:36.596576 TX Vref=28, minBit 0, minWin=25, winSum=415
2949 01:02:36.599777 TX Vref=30, minBit 0, minWin=25, winSum=416
2950 01:02:36.603183 TX Vref=32, minBit 1, minWin=25, winSum=413
2951 01:02:36.609722 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
2952 01:02:36.610356
2953 01:02:36.613151 Final TX Range 1 Vref 30
2954 01:02:36.613790
2955 01:02:36.614222 ==
2956 01:02:36.616244 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 01:02:36.619557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 01:02:36.620035 ==
2959 01:02:36.620409
2960 01:02:36.622882
2961 01:02:36.623354 TX Vref Scan disable
2962 01:02:36.626062 == TX Byte 0 ==
2963 01:02:36.629696 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2964 01:02:36.633435 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2965 01:02:36.636390 == TX Byte 1 ==
2966 01:02:36.639987 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2967 01:02:36.643233 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2968 01:02:36.643819
2969 01:02:36.646636 [DATLAT]
2970 01:02:36.647108 Freq=1200, CH0 RK1
2971 01:02:36.647484
2972 01:02:36.649969 DATLAT Default: 0xd
2973 01:02:36.650439 0, 0xFFFF, sum = 0
2974 01:02:36.653347 1, 0xFFFF, sum = 0
2975 01:02:36.653924 2, 0xFFFF, sum = 0
2976 01:02:36.656532 3, 0xFFFF, sum = 0
2977 01:02:36.657104 4, 0xFFFF, sum = 0
2978 01:02:36.659851 5, 0xFFFF, sum = 0
2979 01:02:36.660425 6, 0xFFFF, sum = 0
2980 01:02:36.663350 7, 0xFFFF, sum = 0
2981 01:02:36.663927 8, 0xFFFF, sum = 0
2982 01:02:36.666161 9, 0xFFFF, sum = 0
2983 01:02:36.669856 10, 0xFFFF, sum = 0
2984 01:02:36.670481 11, 0xFFFF, sum = 0
2985 01:02:36.672996 12, 0x0, sum = 1
2986 01:02:36.673492 13, 0x0, sum = 2
2987 01:02:36.673874 14, 0x0, sum = 3
2988 01:02:36.676490 15, 0x0, sum = 4
2989 01:02:36.677066 best_step = 13
2990 01:02:36.677446
2991 01:02:36.679880 ==
2992 01:02:36.680353 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 01:02:36.686223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 01:02:36.686785 ==
2995 01:02:36.687162 RX Vref Scan: 0
2996 01:02:36.687512
2997 01:02:36.689775 RX Vref 0 -> 0, step: 1
2998 01:02:36.690367
2999 01:02:36.693193 RX Delay -21 -> 252, step: 4
3000 01:02:36.696762 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3001 01:02:36.700024 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3002 01:02:36.706325 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3003 01:02:36.709727 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3004 01:02:36.712988 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3005 01:02:36.716523 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3006 01:02:36.719683 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3007 01:02:36.727827 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3008 01:02:36.729456 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3009 01:02:36.733023 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3010 01:02:36.736139 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3011 01:02:36.739671 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3012 01:02:36.746354 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3013 01:02:36.749767 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3014 01:02:36.752802 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3015 01:02:36.756300 iDelay=195, Bit 15, Center 116 (55 ~ 178) 124
3016 01:02:36.756908 ==
3017 01:02:36.760490 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 01:02:36.766469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 01:02:36.767062 ==
3020 01:02:36.767556 DQS Delay:
3021 01:02:36.768013 DQS0 = 0, DQS1 = 0
3022 01:02:36.770328 DQM Delay:
3023 01:02:36.770917 DQM0 = 119, DQM1 = 108
3024 01:02:36.773703 DQ Delay:
3025 01:02:36.776338 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3026 01:02:36.780136 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3027 01:02:36.783051 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3028 01:02:36.786557 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
3029 01:02:36.787043
3030 01:02:36.787689
3031 01:02:36.793158 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3032 01:02:36.796290 CH0 RK1: MR19=403, MR18=EF5
3033 01:02:36.803098 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3034 01:02:36.806835 [RxdqsGatingPostProcess] freq 1200
3035 01:02:36.813221 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3036 01:02:36.813798 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 01:02:36.816291 best DQS1 dly(2T, 0.5T) = (0, 12)
3038 01:02:36.819646 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 01:02:36.822857 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3040 01:02:36.826121 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 01:02:36.829407 best DQS1 dly(2T, 0.5T) = (0, 11)
3042 01:02:36.834416 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 01:02:36.836527 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3044 01:02:36.840072 Pre-setting of DQS Precalculation
3045 01:02:36.843010 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3046 01:02:36.846098 ==
3047 01:02:36.849745 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 01:02:36.852848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 01:02:36.853374 ==
3050 01:02:36.856245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3051 01:02:36.863211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3052 01:02:36.872378 [CA 0] Center 37 (7~67) winsize 61
3053 01:02:36.875717 [CA 1] Center 37 (7~68) winsize 62
3054 01:02:36.878845 [CA 2] Center 35 (5~65) winsize 61
3055 01:02:36.882106 [CA 3] Center 33 (3~64) winsize 62
3056 01:02:36.885527 [CA 4] Center 33 (3~64) winsize 62
3057 01:02:36.889229 [CA 5] Center 33 (3~63) winsize 61
3058 01:02:36.889799
3059 01:02:36.892167 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3060 01:02:36.892635
3061 01:02:36.895465 [CATrainingPosCal] consider 1 rank data
3062 01:02:36.898831 u2DelayCellTimex100 = 270/100 ps
3063 01:02:36.902281 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3064 01:02:36.905722 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3065 01:02:36.912392 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3066 01:02:36.915661 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3067 01:02:36.918852 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3068 01:02:36.922830 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3069 01:02:36.923461
3070 01:02:36.925440 CA PerBit enable=1, Macro0, CA PI delay=33
3071 01:02:36.926013
3072 01:02:36.928710 [CBTSetCACLKResult] CA Dly = 33
3073 01:02:36.929178 CS Dly: 5 (0~36)
3074 01:02:36.929550 ==
3075 01:02:36.932105 Dram Type= 6, Freq= 0, CH_1, rank 1
3076 01:02:36.939436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 01:02:36.940049 ==
3078 01:02:36.942386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3079 01:02:36.948704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3080 01:02:36.957710 [CA 0] Center 38 (8~68) winsize 61
3081 01:02:36.961263 [CA 1] Center 37 (7~68) winsize 62
3082 01:02:36.964200 [CA 2] Center 35 (5~66) winsize 62
3083 01:02:36.967986 [CA 3] Center 34 (4~65) winsize 62
3084 01:02:36.971040 [CA 4] Center 34 (4~64) winsize 61
3085 01:02:36.974394 [CA 5] Center 33 (3~63) winsize 61
3086 01:02:36.974864
3087 01:02:36.977714 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3088 01:02:36.978335
3089 01:02:36.981031 [CATrainingPosCal] consider 2 rank data
3090 01:02:36.984670 u2DelayCellTimex100 = 270/100 ps
3091 01:02:36.987967 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3092 01:02:36.991256 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3093 01:02:36.997756 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3094 01:02:37.000967 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 01:02:37.004737 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 01:02:37.007908 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3097 01:02:37.008476
3098 01:02:37.011116 CA PerBit enable=1, Macro0, CA PI delay=33
3099 01:02:37.011685
3100 01:02:37.014578 [CBTSetCACLKResult] CA Dly = 33
3101 01:02:37.015146 CS Dly: 6 (0~38)
3102 01:02:37.015524
3103 01:02:37.017840 ----->DramcWriteLeveling(PI) begin...
3104 01:02:37.021293 ==
3105 01:02:37.024420 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 01:02:37.027516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 01:02:37.027991 ==
3108 01:02:37.030839 Write leveling (Byte 0): 23 => 23
3109 01:02:37.034313 Write leveling (Byte 1): 27 => 27
3110 01:02:37.037400 DramcWriteLeveling(PI) end<-----
3111 01:02:37.037872
3112 01:02:37.038328 ==
3113 01:02:37.041133 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 01:02:37.044194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 01:02:37.044695 ==
3116 01:02:37.047457 [Gating] SW mode calibration
3117 01:02:37.054550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3118 01:02:37.057797 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3119 01:02:37.064398 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 01:02:37.067872 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 01:02:37.071206 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 01:02:37.077734 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 01:02:37.081170 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 01:02:37.084582 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3125 01:02:37.091102 0 15 24 | B1->B0 | 2b2b 2929 | 1 0 | (1 0) (1 0)
3126 01:02:37.094259 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 01:02:37.098052 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 01:02:37.104602 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 01:02:37.108614 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 01:02:37.111153 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 01:02:37.118175 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 01:02:37.121341 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 01:02:37.124193 1 0 24 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (1 1)
3134 01:02:37.131230 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 01:02:37.134295 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 01:02:37.138269 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 01:02:37.141480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 01:02:37.147734 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 01:02:37.151182 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 01:02:37.154418 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 01:02:37.161373 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 01:02:37.164549 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3143 01:02:37.168116 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 01:02:37.175006 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 01:02:37.178000 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 01:02:37.181324 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 01:02:37.188199 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 01:02:37.191315 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 01:02:37.194856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 01:02:37.201325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 01:02:37.204781 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 01:02:37.208144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 01:02:37.214805 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 01:02:37.218589 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 01:02:37.221629 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 01:02:37.227665 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3157 01:02:37.231116 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 01:02:37.234410 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3159 01:02:37.238090 Total UI for P1: 0, mck2ui 16
3160 01:02:37.241514 best dqsien dly found for B0: ( 1, 3, 22)
3161 01:02:37.244612 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 01:02:37.247725 Total UI for P1: 0, mck2ui 16
3163 01:02:37.250870 best dqsien dly found for B1: ( 1, 3, 26)
3164 01:02:37.254623 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3165 01:02:37.257972 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 01:02:37.260908
3167 01:02:37.264453 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3168 01:02:37.268279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 01:02:37.271679 [Gating] SW calibration Done
3170 01:02:37.272158 ==
3171 01:02:37.274214 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 01:02:37.277603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 01:02:37.278182 ==
3174 01:02:37.278595 RX Vref Scan: 0
3175 01:02:37.278953
3176 01:02:37.281163 RX Vref 0 -> 0, step: 1
3177 01:02:37.281747
3178 01:02:37.284402 RX Delay -40 -> 252, step: 8
3179 01:02:37.287665 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3180 01:02:37.291102 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3181 01:02:37.298573 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3182 01:02:37.301238 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3183 01:02:37.304800 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3184 01:02:37.308034 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3185 01:02:37.311585 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3186 01:02:37.318519 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3187 01:02:37.321446 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3188 01:02:37.324404 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3189 01:02:37.328219 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3190 01:02:37.331218 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3191 01:02:37.334759 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3192 01:02:37.341632 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3193 01:02:37.344788 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3194 01:02:37.348170 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3195 01:02:37.348739 ==
3196 01:02:37.351385 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 01:02:37.354889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 01:02:37.355464 ==
3199 01:02:37.358494 DQS Delay:
3200 01:02:37.359061 DQS0 = 0, DQS1 = 0
3201 01:02:37.361466 DQM Delay:
3202 01:02:37.362076 DQM0 = 120, DQM1 = 112
3203 01:02:37.362464 DQ Delay:
3204 01:02:37.368163 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3205 01:02:37.371481 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3206 01:02:37.374563 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3207 01:02:37.378654 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3208 01:02:37.379252
3209 01:02:37.379631
3210 01:02:37.379976 ==
3211 01:02:37.381511 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 01:02:37.384939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 01:02:37.385526 ==
3214 01:02:37.385931
3215 01:02:37.386326
3216 01:02:37.387937 TX Vref Scan disable
3217 01:02:37.388412 == TX Byte 0 ==
3218 01:02:37.395052 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3219 01:02:37.398109 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3220 01:02:37.398592 == TX Byte 1 ==
3221 01:02:37.404938 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3222 01:02:37.408409 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3223 01:02:37.408978 ==
3224 01:02:37.411976 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 01:02:37.414855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 01:02:37.415424 ==
3227 01:02:37.427660 TX Vref=22, minBit 11, minWin=23, winSum=396
3228 01:02:37.431097 TX Vref=24, minBit 10, minWin=23, winSum=403
3229 01:02:37.434547 TX Vref=26, minBit 11, minWin=24, winSum=410
3230 01:02:37.437989 TX Vref=28, minBit 8, minWin=25, winSum=412
3231 01:02:37.441210 TX Vref=30, minBit 8, minWin=25, winSum=416
3232 01:02:37.448008 TX Vref=32, minBit 10, minWin=25, winSum=422
3233 01:02:37.451273 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 32
3234 01:02:37.451749
3235 01:02:37.454422 Final TX Range 1 Vref 32
3236 01:02:37.454895
3237 01:02:37.455270 ==
3238 01:02:37.457802 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 01:02:37.461249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 01:02:37.464391 ==
3241 01:02:37.464863
3242 01:02:37.465238
3243 01:02:37.465586 TX Vref Scan disable
3244 01:02:37.467764 == TX Byte 0 ==
3245 01:02:37.471491 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3246 01:02:37.474754 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3247 01:02:37.477816 == TX Byte 1 ==
3248 01:02:37.481020 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 01:02:37.485103 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 01:02:37.488095
3251 01:02:37.488684 [DATLAT]
3252 01:02:37.489068 Freq=1200, CH1 RK0
3253 01:02:37.489420
3254 01:02:37.491826 DATLAT Default: 0xd
3255 01:02:37.492296 0, 0xFFFF, sum = 0
3256 01:02:37.494541 1, 0xFFFF, sum = 0
3257 01:02:37.495019 2, 0xFFFF, sum = 0
3258 01:02:37.498004 3, 0xFFFF, sum = 0
3259 01:02:37.498482 4, 0xFFFF, sum = 0
3260 01:02:37.501141 5, 0xFFFF, sum = 0
3261 01:02:37.504625 6, 0xFFFF, sum = 0
3262 01:02:37.505119 7, 0xFFFF, sum = 0
3263 01:02:37.507998 8, 0xFFFF, sum = 0
3264 01:02:37.508519 9, 0xFFFF, sum = 0
3265 01:02:37.511291 10, 0xFFFF, sum = 0
3266 01:02:37.511788 11, 0xFFFF, sum = 0
3267 01:02:37.514602 12, 0x0, sum = 1
3268 01:02:37.515369 13, 0x0, sum = 2
3269 01:02:37.517992 14, 0x0, sum = 3
3270 01:02:37.518513 15, 0x0, sum = 4
3271 01:02:37.518898 best_step = 13
3272 01:02:37.519246
3273 01:02:37.521158 ==
3274 01:02:37.524996 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 01:02:37.527839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 01:02:37.528334 ==
3277 01:02:37.528709 RX Vref Scan: 1
3278 01:02:37.529058
3279 01:02:37.531085 Set Vref Range= 32 -> 127
3280 01:02:37.531841
3281 01:02:37.534470 RX Vref 32 -> 127, step: 1
3282 01:02:37.534936
3283 01:02:37.537902 RX Delay -13 -> 252, step: 4
3284 01:02:37.538412
3285 01:02:37.541187 Set Vref, RX VrefLevel [Byte0]: 32
3286 01:02:37.544592 [Byte1]: 32
3287 01:02:37.545075
3288 01:02:37.548360 Set Vref, RX VrefLevel [Byte0]: 33
3289 01:02:37.551515 [Byte1]: 33
3290 01:02:37.551981
3291 01:02:37.554531 Set Vref, RX VrefLevel [Byte0]: 34
3292 01:02:37.557703 [Byte1]: 34
3293 01:02:37.561911
3294 01:02:37.562268 Set Vref, RX VrefLevel [Byte0]: 35
3295 01:02:37.564978 [Byte1]: 35
3296 01:02:37.569711
3297 01:02:37.569897 Set Vref, RX VrefLevel [Byte0]: 36
3298 01:02:37.573111 [Byte1]: 36
3299 01:02:37.577469
3300 01:02:37.577626 Set Vref, RX VrefLevel [Byte0]: 37
3301 01:02:37.580807 [Byte1]: 37
3302 01:02:37.585430
3303 01:02:37.585585 Set Vref, RX VrefLevel [Byte0]: 38
3304 01:02:37.588697 [Byte1]: 38
3305 01:02:37.593355
3306 01:02:37.593509 Set Vref, RX VrefLevel [Byte0]: 39
3307 01:02:37.596556 [Byte1]: 39
3308 01:02:37.601168
3309 01:02:37.601326 Set Vref, RX VrefLevel [Byte0]: 40
3310 01:02:37.604455 [Byte1]: 40
3311 01:02:37.609072
3312 01:02:37.609227 Set Vref, RX VrefLevel [Byte0]: 41
3313 01:02:37.612416 [Byte1]: 41
3314 01:02:37.616957
3315 01:02:37.617113 Set Vref, RX VrefLevel [Byte0]: 42
3316 01:02:37.620538 [Byte1]: 42
3317 01:02:37.624813
3318 01:02:37.624992 Set Vref, RX VrefLevel [Byte0]: 43
3319 01:02:37.628294 [Byte1]: 43
3320 01:02:37.633038
3321 01:02:37.633218 Set Vref, RX VrefLevel [Byte0]: 44
3322 01:02:37.635905 [Byte1]: 44
3323 01:02:37.640574
3324 01:02:37.640752 Set Vref, RX VrefLevel [Byte0]: 45
3325 01:02:37.644060 [Byte1]: 45
3326 01:02:37.648409
3327 01:02:37.648587 Set Vref, RX VrefLevel [Byte0]: 46
3328 01:02:37.652018 [Byte1]: 46
3329 01:02:37.656170
3330 01:02:37.659631 Set Vref, RX VrefLevel [Byte0]: 47
3331 01:02:37.662954 [Byte1]: 47
3332 01:02:37.663131
3333 01:02:37.666711 Set Vref, RX VrefLevel [Byte0]: 48
3334 01:02:37.669577 [Byte1]: 48
3335 01:02:37.669844
3336 01:02:37.673524 Set Vref, RX VrefLevel [Byte0]: 49
3337 01:02:37.676304 [Byte1]: 49
3338 01:02:37.680412
3339 01:02:37.680675 Set Vref, RX VrefLevel [Byte0]: 50
3340 01:02:37.684081 [Byte1]: 50
3341 01:02:37.688508
3342 01:02:37.688805 Set Vref, RX VrefLevel [Byte0]: 51
3343 01:02:37.691621 [Byte1]: 51
3344 01:02:37.696210
3345 01:02:37.696655 Set Vref, RX VrefLevel [Byte0]: 52
3346 01:02:37.699624 [Byte1]: 52
3347 01:02:37.704165
3348 01:02:37.704677 Set Vref, RX VrefLevel [Byte0]: 53
3349 01:02:37.707384 [Byte1]: 53
3350 01:02:37.712298
3351 01:02:37.712850 Set Vref, RX VrefLevel [Byte0]: 54
3352 01:02:37.715429 [Byte1]: 54
3353 01:02:37.719938
3354 01:02:37.720474 Set Vref, RX VrefLevel [Byte0]: 55
3355 01:02:37.723294 [Byte1]: 55
3356 01:02:37.727567
3357 01:02:37.728032 Set Vref, RX VrefLevel [Byte0]: 56
3358 01:02:37.730843 [Byte1]: 56
3359 01:02:37.735920
3360 01:02:37.736497 Set Vref, RX VrefLevel [Byte0]: 57
3361 01:02:37.738936 [Byte1]: 57
3362 01:02:37.744349
3363 01:02:37.744916 Set Vref, RX VrefLevel [Byte0]: 58
3364 01:02:37.746732 [Byte1]: 58
3365 01:02:37.751329
3366 01:02:37.751815 Set Vref, RX VrefLevel [Byte0]: 59
3367 01:02:37.755096 [Byte1]: 59
3368 01:02:37.759703
3369 01:02:37.760272 Set Vref, RX VrefLevel [Byte0]: 60
3370 01:02:37.762470 [Byte1]: 60
3371 01:02:37.767306
3372 01:02:37.767877 Set Vref, RX VrefLevel [Byte0]: 61
3373 01:02:37.770838 [Byte1]: 61
3374 01:02:37.775099
3375 01:02:37.775734 Set Vref, RX VrefLevel [Byte0]: 62
3376 01:02:37.778296 [Byte1]: 62
3377 01:02:37.782950
3378 01:02:37.783415 Set Vref, RX VrefLevel [Byte0]: 63
3379 01:02:37.786202 [Byte1]: 63
3380 01:02:37.791138
3381 01:02:37.791704 Set Vref, RX VrefLevel [Byte0]: 64
3382 01:02:37.794051 [Byte1]: 64
3383 01:02:37.798837
3384 01:02:37.799403 Set Vref, RX VrefLevel [Byte0]: 65
3385 01:02:37.802182 [Byte1]: 65
3386 01:02:37.806998
3387 01:02:37.807699 Set Vref, RX VrefLevel [Byte0]: 66
3388 01:02:37.809968 [Byte1]: 66
3389 01:02:37.814536
3390 01:02:37.815087 Set Vref, RX VrefLevel [Byte0]: 67
3391 01:02:37.818764 [Byte1]: 67
3392 01:02:37.822296
3393 01:02:37.822760 Set Vref, RX VrefLevel [Byte0]: 68
3394 01:02:37.825469 [Byte1]: 68
3395 01:02:37.830170
3396 01:02:37.830600 Final RX Vref Byte 0 = 52 to rank0
3397 01:02:37.833538 Final RX Vref Byte 1 = 52 to rank0
3398 01:02:37.836894 Final RX Vref Byte 0 = 52 to rank1
3399 01:02:37.840405 Final RX Vref Byte 1 = 52 to rank1==
3400 01:02:37.844056 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 01:02:37.847222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 01:02:37.850757 ==
3403 01:02:37.851224 DQS Delay:
3404 01:02:37.851595 DQS0 = 0, DQS1 = 0
3405 01:02:37.853549 DQM Delay:
3406 01:02:37.854041 DQM0 = 119, DQM1 = 112
3407 01:02:37.857198 DQ Delay:
3408 01:02:37.860384 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3409 01:02:37.864235 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3410 01:02:37.867413 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3411 01:02:37.871284 DQ12 =122, DQ13 =116, DQ14 =122, DQ15 =116
3412 01:02:37.871850
3413 01:02:37.872222
3414 01:02:37.877590 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3415 01:02:37.880631 CH1 RK0: MR19=404, MR18=417
3416 01:02:37.887662 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3417 01:02:37.888235
3418 01:02:37.890950 ----->DramcWriteLeveling(PI) begin...
3419 01:02:37.891526 ==
3420 01:02:37.893799 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 01:02:37.897590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 01:02:37.898201 ==
3423 01:02:37.901076 Write leveling (Byte 0): 24 => 24
3424 01:02:37.904553 Write leveling (Byte 1): 28 => 28
3425 01:02:37.907675 DramcWriteLeveling(PI) end<-----
3426 01:02:37.908290
3427 01:02:37.908682 ==
3428 01:02:37.910500 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 01:02:37.914190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 01:02:37.917366 ==
3431 01:02:37.917959 [Gating] SW mode calibration
3432 01:02:37.923989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 01:02:37.930549 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 01:02:37.934045 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 01:02:37.941458 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 01:02:37.944010 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 01:02:37.947223 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 01:02:37.954300 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 01:02:37.957874 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 01:02:37.961229 0 15 24 | B1->B0 | 2e2e 3333 | 0 1 | (0 0) (1 0)
3441 01:02:37.964557 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3442 01:02:37.971506 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 01:02:37.974599 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 01:02:37.977621 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 01:02:37.984385 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 01:02:37.987880 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 01:02:37.991063 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 01:02:37.997891 1 0 24 | B1->B0 | 3d3d 2a2a | 0 0 | (0 0) (0 0)
3449 01:02:38.001408 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3450 01:02:38.004846 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 01:02:38.011193 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 01:02:38.014412 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 01:02:38.017877 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 01:02:38.024415 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 01:02:38.028483 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 01:02:38.030938 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3457 01:02:38.037781 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3458 01:02:38.041261 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 01:02:38.044689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 01:02:38.047661 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 01:02:38.054409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 01:02:38.058077 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 01:02:38.061324 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 01:02:38.067874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 01:02:38.071355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 01:02:38.074693 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 01:02:38.081391 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 01:02:38.084481 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 01:02:38.087847 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 01:02:38.094819 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 01:02:38.097663 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 01:02:38.101391 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 01:02:38.107741 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 01:02:38.108312 Total UI for P1: 0, mck2ui 16
3475 01:02:38.114518 best dqsien dly found for B0: ( 1, 3, 24)
3476 01:02:38.115087 Total UI for P1: 0, mck2ui 16
3477 01:02:38.120705 best dqsien dly found for B1: ( 1, 3, 24)
3478 01:02:38.124098 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3479 01:02:38.127426 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3480 01:02:38.128014
3481 01:02:38.130460 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3482 01:02:38.134296 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3483 01:02:38.137886 [Gating] SW calibration Done
3484 01:02:38.138386 ==
3485 01:02:38.140527 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 01:02:38.143870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 01:02:38.144341 ==
3488 01:02:38.147584 RX Vref Scan: 0
3489 01:02:38.148153
3490 01:02:38.148533 RX Vref 0 -> 0, step: 1
3491 01:02:38.148882
3492 01:02:38.150552 RX Delay -40 -> 252, step: 8
3493 01:02:38.153881 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3494 01:02:38.160625 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3495 01:02:38.163833 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3496 01:02:38.167299 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3497 01:02:38.170666 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3498 01:02:38.173686 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3499 01:02:38.180874 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3500 01:02:38.184094 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3501 01:02:38.187251 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3502 01:02:38.190805 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3503 01:02:38.194206 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3504 01:02:38.200643 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3505 01:02:38.204061 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3506 01:02:38.207885 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3507 01:02:38.210689 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3508 01:02:38.213930 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3509 01:02:38.217682 ==
3510 01:02:38.220760 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 01:02:38.224060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 01:02:38.224636 ==
3513 01:02:38.225011 DQS Delay:
3514 01:02:38.226818 DQS0 = 0, DQS1 = 0
3515 01:02:38.227286 DQM Delay:
3516 01:02:38.230351 DQM0 = 120, DQM1 = 113
3517 01:02:38.230818 DQ Delay:
3518 01:02:38.233549 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3519 01:02:38.237031 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3520 01:02:38.240525 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3521 01:02:38.243774 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3522 01:02:38.244403
3523 01:02:38.244784
3524 01:02:38.245126 ==
3525 01:02:38.246967 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 01:02:38.253690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 01:02:38.254379 ==
3528 01:02:38.254762
3529 01:02:38.255107
3530 01:02:38.255436 TX Vref Scan disable
3531 01:02:38.256859 == TX Byte 0 ==
3532 01:02:38.260278 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3533 01:02:38.263970 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3534 01:02:38.266926 == TX Byte 1 ==
3535 01:02:38.270033 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3536 01:02:38.276882 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3537 01:02:38.277442 ==
3538 01:02:38.280063 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 01:02:38.283775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 01:02:38.284351 ==
3541 01:02:38.295100 TX Vref=22, minBit 9, minWin=24, winSum=406
3542 01:02:38.298301 TX Vref=24, minBit 1, minWin=25, winSum=416
3543 01:02:38.301817 TX Vref=26, minBit 3, minWin=25, winSum=417
3544 01:02:38.305480 TX Vref=28, minBit 1, minWin=26, winSum=424
3545 01:02:38.308637 TX Vref=30, minBit 0, minWin=26, winSum=423
3546 01:02:38.311698 TX Vref=32, minBit 9, minWin=25, winSum=424
3547 01:02:38.318374 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 28
3548 01:02:38.318947
3549 01:02:38.321539 Final TX Range 1 Vref 28
3550 01:02:38.322145
3551 01:02:38.322525 ==
3552 01:02:38.325083 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 01:02:38.327982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 01:02:38.328525 ==
3555 01:02:38.331466
3556 01:02:38.331929
3557 01:02:38.332294 TX Vref Scan disable
3558 01:02:38.334487 == TX Byte 0 ==
3559 01:02:38.338040 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3560 01:02:38.341296 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3561 01:02:38.344918 == TX Byte 1 ==
3562 01:02:38.347916 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 01:02:38.351456 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 01:02:38.354951
3565 01:02:38.355511 [DATLAT]
3566 01:02:38.355881 Freq=1200, CH1 RK1
3567 01:02:38.356233
3568 01:02:38.358101 DATLAT Default: 0xd
3569 01:02:38.358618 0, 0xFFFF, sum = 0
3570 01:02:38.361695 1, 0xFFFF, sum = 0
3571 01:02:38.362208 2, 0xFFFF, sum = 0
3572 01:02:38.365161 3, 0xFFFF, sum = 0
3573 01:02:38.365734 4, 0xFFFF, sum = 0
3574 01:02:38.368475 5, 0xFFFF, sum = 0
3575 01:02:38.371912 6, 0xFFFF, sum = 0
3576 01:02:38.372490 7, 0xFFFF, sum = 0
3577 01:02:38.374536 8, 0xFFFF, sum = 0
3578 01:02:38.375016 9, 0xFFFF, sum = 0
3579 01:02:38.378243 10, 0xFFFF, sum = 0
3580 01:02:38.378754 11, 0xFFFF, sum = 0
3581 01:02:38.381172 12, 0x0, sum = 1
3582 01:02:38.381647 13, 0x0, sum = 2
3583 01:02:38.384857 14, 0x0, sum = 3
3584 01:02:38.385432 15, 0x0, sum = 4
3585 01:02:38.385816 best_step = 13
3586 01:02:38.388095
3587 01:02:38.388652 ==
3588 01:02:38.391950 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 01:02:38.394701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 01:02:38.395171 ==
3591 01:02:38.395544 RX Vref Scan: 0
3592 01:02:38.395891
3593 01:02:38.397911 RX Vref 0 -> 0, step: 1
3594 01:02:38.398419
3595 01:02:38.401918 RX Delay -13 -> 252, step: 4
3596 01:02:38.405488 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3597 01:02:38.411334 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3598 01:02:38.414862 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3599 01:02:38.418294 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3600 01:02:38.421428 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3601 01:02:38.424930 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3602 01:02:38.430949 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3603 01:02:38.434681 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3604 01:02:38.437584 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3605 01:02:38.441623 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3606 01:02:38.444922 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3607 01:02:38.451286 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3608 01:02:38.454371 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3609 01:02:38.458379 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3610 01:02:38.461238 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3611 01:02:38.464533 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3612 01:02:38.465104 ==
3613 01:02:38.467734 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 01:02:38.474513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 01:02:38.475089 ==
3616 01:02:38.475465 DQS Delay:
3617 01:02:38.477763 DQS0 = 0, DQS1 = 0
3618 01:02:38.478438 DQM Delay:
3619 01:02:38.481053 DQM0 = 119, DQM1 = 113
3620 01:02:38.481625 DQ Delay:
3621 01:02:38.484537 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3622 01:02:38.487506 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3623 01:02:38.491333 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3624 01:02:38.494391 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3625 01:02:38.494864
3626 01:02:38.495233
3627 01:02:38.504650 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3628 01:02:38.505225 CH1 RK1: MR19=403, MR18=8ED
3629 01:02:38.510947 CH1_RK1: MR19=0x403, MR18=0x8ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3630 01:02:38.514108 [RxdqsGatingPostProcess] freq 1200
3631 01:02:38.521005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3632 01:02:38.524228 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 01:02:38.527467 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 01:02:38.530849 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 01:02:38.534350 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 01:02:38.537443 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 01:02:38.540900 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 01:02:38.541470 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 01:02:38.544151 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 01:02:38.548183 Pre-setting of DQS Precalculation
3641 01:02:38.554397 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3642 01:02:38.560641 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3643 01:02:38.567723 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3644 01:02:38.568291
3645 01:02:38.568667
3646 01:02:38.570903 [Calibration Summary] 2400 Mbps
3647 01:02:38.574372 CH 0, Rank 0
3648 01:02:38.574946 SW Impedance : PASS
3649 01:02:38.577355 DUTY Scan : NO K
3650 01:02:38.577823 ZQ Calibration : PASS
3651 01:02:38.580928 Jitter Meter : NO K
3652 01:02:38.583937 CBT Training : PASS
3653 01:02:38.584549 Write leveling : PASS
3654 01:02:38.587194 RX DQS gating : PASS
3655 01:02:38.590763 RX DQ/DQS(RDDQC) : PASS
3656 01:02:38.591328 TX DQ/DQS : PASS
3657 01:02:38.593629 RX DATLAT : PASS
3658 01:02:38.597305 RX DQ/DQS(Engine): PASS
3659 01:02:38.597871 TX OE : NO K
3660 01:02:38.600776 All Pass.
3661 01:02:38.601496
3662 01:02:38.601886 CH 0, Rank 1
3663 01:02:38.603848 SW Impedance : PASS
3664 01:02:38.604314 DUTY Scan : NO K
3665 01:02:38.607339 ZQ Calibration : PASS
3666 01:02:38.610745 Jitter Meter : NO K
3667 01:02:38.611312 CBT Training : PASS
3668 01:02:38.614221 Write leveling : PASS
3669 01:02:38.617247 RX DQS gating : PASS
3670 01:02:38.617817 RX DQ/DQS(RDDQC) : PASS
3671 01:02:38.620370 TX DQ/DQS : PASS
3672 01:02:38.623744 RX DATLAT : PASS
3673 01:02:38.624316 RX DQ/DQS(Engine): PASS
3674 01:02:38.626862 TX OE : NO K
3675 01:02:38.627330 All Pass.
3676 01:02:38.627703
3677 01:02:38.629919 CH 1, Rank 0
3678 01:02:38.630421 SW Impedance : PASS
3679 01:02:38.633556 DUTY Scan : NO K
3680 01:02:38.636678 ZQ Calibration : PASS
3681 01:02:38.637148 Jitter Meter : NO K
3682 01:02:38.640124 CBT Training : PASS
3683 01:02:38.640697 Write leveling : PASS
3684 01:02:38.643451 RX DQS gating : PASS
3685 01:02:38.646720 RX DQ/DQS(RDDQC) : PASS
3686 01:02:38.647283 TX DQ/DQS : PASS
3687 01:02:38.649971 RX DATLAT : PASS
3688 01:02:38.653753 RX DQ/DQS(Engine): PASS
3689 01:02:38.654368 TX OE : NO K
3690 01:02:38.656841 All Pass.
3691 01:02:38.657410
3692 01:02:38.657783 CH 1, Rank 1
3693 01:02:38.659980 SW Impedance : PASS
3694 01:02:38.660540 DUTY Scan : NO K
3695 01:02:38.663622 ZQ Calibration : PASS
3696 01:02:38.666735 Jitter Meter : NO K
3697 01:02:38.667303 CBT Training : PASS
3698 01:02:38.670314 Write leveling : PASS
3699 01:02:38.673508 RX DQS gating : PASS
3700 01:02:38.674129 RX DQ/DQS(RDDQC) : PASS
3701 01:02:38.676523 TX DQ/DQS : PASS
3702 01:02:38.680091 RX DATLAT : PASS
3703 01:02:38.680667 RX DQ/DQS(Engine): PASS
3704 01:02:38.683456 TX OE : NO K
3705 01:02:38.684032 All Pass.
3706 01:02:38.684407
3707 01:02:38.686592 DramC Write-DBI off
3708 01:02:38.690095 PER_BANK_REFRESH: Hybrid Mode
3709 01:02:38.690668 TX_TRACKING: ON
3710 01:02:38.699965 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3711 01:02:38.703430 [FAST_K] Save calibration result to emmc
3712 01:02:38.706698 dramc_set_vcore_voltage set vcore to 650000
3713 01:02:38.710103 Read voltage for 600, 5
3714 01:02:38.710685 Vio18 = 0
3715 01:02:38.711069 Vcore = 650000
3716 01:02:38.713510 Vdram = 0
3717 01:02:38.714141 Vddq = 0
3718 01:02:38.714537 Vmddr = 0
3719 01:02:38.719880 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3720 01:02:38.723353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3721 01:02:38.726832 MEM_TYPE=3, freq_sel=19
3722 01:02:38.729830 sv_algorithm_assistance_LP4_1600
3723 01:02:38.733572 ============ PULL DRAM RESETB DOWN ============
3724 01:02:38.736685 ========== PULL DRAM RESETB DOWN end =========
3725 01:02:38.743272 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 01:02:38.746457 ===================================
3727 01:02:38.746937 LPDDR4 DRAM CONFIGURATION
3728 01:02:38.750146 ===================================
3729 01:02:38.753124 EX_ROW_EN[0] = 0x0
3730 01:02:38.756507 EX_ROW_EN[1] = 0x0
3731 01:02:38.757088 LP4Y_EN = 0x0
3732 01:02:38.760135 WORK_FSP = 0x0
3733 01:02:38.760714 WL = 0x2
3734 01:02:38.763162 RL = 0x2
3735 01:02:38.763745 BL = 0x2
3736 01:02:38.766864 RPST = 0x0
3737 01:02:38.767443 RD_PRE = 0x0
3738 01:02:38.770111 WR_PRE = 0x1
3739 01:02:38.770687 WR_PST = 0x0
3740 01:02:38.772816 DBI_WR = 0x0
3741 01:02:38.773293 DBI_RD = 0x0
3742 01:02:38.776306 OTF = 0x1
3743 01:02:38.780917 ===================================
3744 01:02:38.782466 ===================================
3745 01:02:38.782979 ANA top config
3746 01:02:38.786270 ===================================
3747 01:02:38.789460 DLL_ASYNC_EN = 0
3748 01:02:38.793178 ALL_SLAVE_EN = 1
3749 01:02:38.795924 NEW_RANK_MODE = 1
3750 01:02:38.796585 DLL_IDLE_MODE = 1
3751 01:02:38.799476 LP45_APHY_COMB_EN = 1
3752 01:02:38.802760 TX_ODT_DIS = 1
3753 01:02:38.806285 NEW_8X_MODE = 1
3754 01:02:38.809401 ===================================
3755 01:02:38.812792 ===================================
3756 01:02:38.816076 data_rate = 1200
3757 01:02:38.816567 CKR = 1
3758 01:02:38.819145 DQ_P2S_RATIO = 8
3759 01:02:38.822544 ===================================
3760 01:02:38.825877 CA_P2S_RATIO = 8
3761 01:02:38.829194 DQ_CA_OPEN = 0
3762 01:02:38.832678 DQ_SEMI_OPEN = 0
3763 01:02:38.836056 CA_SEMI_OPEN = 0
3764 01:02:38.836489 CA_FULL_RATE = 0
3765 01:02:38.839155 DQ_CKDIV4_EN = 1
3766 01:02:38.842413 CA_CKDIV4_EN = 1
3767 01:02:38.845635 CA_PREDIV_EN = 0
3768 01:02:38.849765 PH8_DLY = 0
3769 01:02:38.850233 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3770 01:02:38.852451 DQ_AAMCK_DIV = 4
3771 01:02:38.855805 CA_AAMCK_DIV = 4
3772 01:02:38.859378 CA_ADMCK_DIV = 4
3773 01:02:38.862453 DQ_TRACK_CA_EN = 0
3774 01:02:38.865973 CA_PICK = 600
3775 01:02:38.869292 CA_MCKIO = 600
3776 01:02:38.869866 MCKIO_SEMI = 0
3777 01:02:38.872624 PLL_FREQ = 2288
3778 01:02:38.875908 DQ_UI_PI_RATIO = 32
3779 01:02:38.879057 CA_UI_PI_RATIO = 0
3780 01:02:38.882501 ===================================
3781 01:02:38.885650 ===================================
3782 01:02:38.889242 memory_type:LPDDR4
3783 01:02:38.889812 GP_NUM : 10
3784 01:02:38.892180 SRAM_EN : 1
3785 01:02:38.895492 MD32_EN : 0
3786 01:02:38.899330 ===================================
3787 01:02:38.899906 [ANA_INIT] >>>>>>>>>>>>>>
3788 01:02:38.902179 <<<<<< [CONFIGURE PHASE]: ANA_TX
3789 01:02:38.905694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3790 01:02:38.909367 ===================================
3791 01:02:38.912097 data_rate = 1200,PCW = 0X5800
3792 01:02:38.915659 ===================================
3793 01:02:38.918566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3794 01:02:38.925591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 01:02:38.928677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 01:02:38.935178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3797 01:02:38.938873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3798 01:02:38.942206 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3799 01:02:38.942769 [ANA_INIT] flow start
3800 01:02:38.945435 [ANA_INIT] PLL >>>>>>>>
3801 01:02:38.948719 [ANA_INIT] PLL <<<<<<<<
3802 01:02:38.949288 [ANA_INIT] MIDPI >>>>>>>>
3803 01:02:38.952349 [ANA_INIT] MIDPI <<<<<<<<
3804 01:02:38.955484 [ANA_INIT] DLL >>>>>>>>
3805 01:02:38.955958 [ANA_INIT] flow end
3806 01:02:38.962062 ============ LP4 DIFF to SE enter ============
3807 01:02:38.965293 ============ LP4 DIFF to SE exit ============
3808 01:02:38.968753 [ANA_INIT] <<<<<<<<<<<<<
3809 01:02:38.971913 [Flow] Enable top DCM control >>>>>
3810 01:02:38.975494 [Flow] Enable top DCM control <<<<<
3811 01:02:38.978441 Enable DLL master slave shuffle
3812 01:02:38.981674 ==============================================================
3813 01:02:38.985072 Gating Mode config
3814 01:02:38.988890 ==============================================================
3815 01:02:38.991893 Config description:
3816 01:02:39.002024 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3817 01:02:39.008770 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3818 01:02:39.011840 SELPH_MODE 0: By rank 1: By Phase
3819 01:02:39.018716 ==============================================================
3820 01:02:39.022109 GAT_TRACK_EN = 1
3821 01:02:39.025024 RX_GATING_MODE = 2
3822 01:02:39.028296 RX_GATING_TRACK_MODE = 2
3823 01:02:39.031546 SELPH_MODE = 1
3824 01:02:39.032016 PICG_EARLY_EN = 1
3825 01:02:39.035172 VALID_LAT_VALUE = 1
3826 01:02:39.041936 ==============================================================
3827 01:02:39.044896 Enter into Gating configuration >>>>
3828 01:02:39.048253 Exit from Gating configuration <<<<
3829 01:02:39.051793 Enter into DVFS_PRE_config >>>>>
3830 01:02:39.061723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3831 01:02:39.065460 Exit from DVFS_PRE_config <<<<<
3832 01:02:39.068640 Enter into PICG configuration >>>>
3833 01:02:39.072015 Exit from PICG configuration <<<<
3834 01:02:39.075323 [RX_INPUT] configuration >>>>>
3835 01:02:39.079023 [RX_INPUT] configuration <<<<<
3836 01:02:39.081827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3837 01:02:39.088719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3838 01:02:39.095396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 01:02:39.102331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 01:02:39.108400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 01:02:39.111428 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 01:02:39.119194 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3843 01:02:39.122177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3844 01:02:39.125016 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3845 01:02:39.127891 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3846 01:02:39.134410 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3847 01:02:39.137833 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 01:02:39.141053 ===================================
3849 01:02:39.144790 LPDDR4 DRAM CONFIGURATION
3850 01:02:39.147953 ===================================
3851 01:02:39.148538 EX_ROW_EN[0] = 0x0
3852 01:02:39.151553 EX_ROW_EN[1] = 0x0
3853 01:02:39.152118 LP4Y_EN = 0x0
3854 01:02:39.154494 WORK_FSP = 0x0
3855 01:02:39.154965 WL = 0x2
3856 01:02:39.158146 RL = 0x2
3857 01:02:39.158708 BL = 0x2
3858 01:02:39.161478 RPST = 0x0
3859 01:02:39.164624 RD_PRE = 0x0
3860 01:02:39.165190 WR_PRE = 0x1
3861 01:02:39.167746 WR_PST = 0x0
3862 01:02:39.168312 DBI_WR = 0x0
3863 01:02:39.171197 DBI_RD = 0x0
3864 01:02:39.171761 OTF = 0x1
3865 01:02:39.174549 ===================================
3866 01:02:39.178134 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3867 01:02:39.184712 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3868 01:02:39.187852 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 01:02:39.191253 ===================================
3870 01:02:39.194882 LPDDR4 DRAM CONFIGURATION
3871 01:02:39.197677 ===================================
3872 01:02:39.198274 EX_ROW_EN[0] = 0x10
3873 01:02:39.200774 EX_ROW_EN[1] = 0x0
3874 01:02:39.201242 LP4Y_EN = 0x0
3875 01:02:39.204456 WORK_FSP = 0x0
3876 01:02:39.205026 WL = 0x2
3877 01:02:39.208027 RL = 0x2
3878 01:02:39.208594 BL = 0x2
3879 01:02:39.211023 RPST = 0x0
3880 01:02:39.211494 RD_PRE = 0x0
3881 01:02:39.214311 WR_PRE = 0x1
3882 01:02:39.214878 WR_PST = 0x0
3883 01:02:39.217751 DBI_WR = 0x0
3884 01:02:39.218384 DBI_RD = 0x0
3885 01:02:39.220938 OTF = 0x1
3886 01:02:39.224451 ===================================
3887 01:02:39.230564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3888 01:02:39.234620 nWR fixed to 30
3889 01:02:39.237733 [ModeRegInit_LP4] CH0 RK0
3890 01:02:39.238372 [ModeRegInit_LP4] CH0 RK1
3891 01:02:39.240915 [ModeRegInit_LP4] CH1 RK0
3892 01:02:39.244265 [ModeRegInit_LP4] CH1 RK1
3893 01:02:39.244833 match AC timing 17
3894 01:02:39.250977 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3895 01:02:39.254113 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3896 01:02:39.257524 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3897 01:02:39.264503 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3898 01:02:39.267551 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3899 01:02:39.268125 ==
3900 01:02:39.271260 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 01:02:39.274437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3902 01:02:39.275015 ==
3903 01:02:39.280834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3904 01:02:39.287750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3905 01:02:39.290780 [CA 0] Center 35 (5~66) winsize 62
3906 01:02:39.294370 [CA 1] Center 36 (6~67) winsize 62
3907 01:02:39.297765 [CA 2] Center 34 (4~65) winsize 62
3908 01:02:39.301273 [CA 3] Center 34 (3~65) winsize 63
3909 01:02:39.304481 [CA 4] Center 33 (3~64) winsize 62
3910 01:02:39.307604 [CA 5] Center 33 (3~64) winsize 62
3911 01:02:39.308183
3912 01:02:39.310816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3913 01:02:39.311393
3914 01:02:39.313995 [CATrainingPosCal] consider 1 rank data
3915 01:02:39.317800 u2DelayCellTimex100 = 270/100 ps
3916 01:02:39.320696 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3917 01:02:39.324084 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3918 01:02:39.327370 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3919 01:02:39.330462 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3920 01:02:39.333932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3921 01:02:39.341222 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3922 01:02:39.341789
3923 01:02:39.343835 CA PerBit enable=1, Macro0, CA PI delay=33
3924 01:02:39.344420
3925 01:02:39.347092 [CBTSetCACLKResult] CA Dly = 33
3926 01:02:39.347564 CS Dly: 5 (0~36)
3927 01:02:39.347938 ==
3928 01:02:39.350137 Dram Type= 6, Freq= 0, CH_0, rank 1
3929 01:02:39.353467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 01:02:39.357030 ==
3931 01:02:39.360442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 01:02:39.366965 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 01:02:39.370403 [CA 0] Center 36 (6~67) winsize 62
3934 01:02:39.373775 [CA 1] Center 36 (6~67) winsize 62
3935 01:02:39.377085 [CA 2] Center 34 (4~65) winsize 62
3936 01:02:39.380399 [CA 3] Center 34 (4~65) winsize 62
3937 01:02:39.383831 [CA 4] Center 34 (3~65) winsize 63
3938 01:02:39.386831 [CA 5] Center 33 (3~64) winsize 62
3939 01:02:39.387417
3940 01:02:39.390377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 01:02:39.390855
3942 01:02:39.393872 [CATrainingPosCal] consider 2 rank data
3943 01:02:39.397261 u2DelayCellTimex100 = 270/100 ps
3944 01:02:39.400425 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3945 01:02:39.403645 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 01:02:39.406824 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 01:02:39.413653 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 01:02:39.417100 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 01:02:39.420387 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 01:02:39.420965
3951 01:02:39.423932 CA PerBit enable=1, Macro0, CA PI delay=33
3952 01:02:39.424506
3953 01:02:39.426440 [CBTSetCACLKResult] CA Dly = 33
3954 01:02:39.426975 CS Dly: 5 (0~37)
3955 01:02:39.427359
3956 01:02:39.429918 ----->DramcWriteLeveling(PI) begin...
3957 01:02:39.430440 ==
3958 01:02:39.433184 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 01:02:39.439514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 01:02:39.440149 ==
3961 01:02:39.443248 Write leveling (Byte 0): 32 => 32
3962 01:02:39.446242 Write leveling (Byte 1): 32 => 32
3963 01:02:39.446747 DramcWriteLeveling(PI) end<-----
3964 01:02:39.449529
3965 01:02:39.450034 ==
3966 01:02:39.453211 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 01:02:39.456541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 01:02:39.457058 ==
3969 01:02:39.459825 [Gating] SW mode calibration
3970 01:02:39.466116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 01:02:39.469558 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3972 01:02:39.476453 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 01:02:39.479244 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 01:02:39.482781 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 01:02:39.489499 0 9 12 | B1->B0 | 3333 2b2b | 1 0 | (1 1) (0 0)
3976 01:02:39.493123 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3977 01:02:39.496310 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 01:02:39.502731 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 01:02:39.506087 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 01:02:39.509687 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 01:02:39.515918 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 01:02:39.519510 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 01:02:39.522573 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3984 01:02:39.529187 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3985 01:02:39.532583 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 01:02:39.536198 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 01:02:39.542485 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 01:02:39.545904 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 01:02:39.549648 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 01:02:39.557187 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 01:02:39.558917 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3992 01:02:39.562323 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 01:02:39.568889 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 01:02:39.572049 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 01:02:39.575631 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 01:02:39.582260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 01:02:39.585705 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 01:02:39.588936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 01:02:39.595899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 01:02:39.599264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 01:02:39.602241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 01:02:39.609100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 01:02:39.612479 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 01:02:39.615728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 01:02:39.619068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 01:02:39.625708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4007 01:02:39.629548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4008 01:02:39.632147 Total UI for P1: 0, mck2ui 16
4009 01:02:39.636005 best dqsien dly found for B0: ( 0, 13, 8)
4010 01:02:39.638609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4011 01:02:39.645562 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 01:02:39.649080 Total UI for P1: 0, mck2ui 16
4013 01:02:39.651965 best dqsien dly found for B1: ( 0, 13, 16)
4014 01:02:39.655250 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4015 01:02:39.658607 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4016 01:02:39.659193
4017 01:02:39.662050 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4018 01:02:39.665439 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4019 01:02:39.668668 [Gating] SW calibration Done
4020 01:02:39.669259 ==
4021 01:02:39.672030 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 01:02:39.675454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 01:02:39.676021 ==
4024 01:02:39.678637 RX Vref Scan: 0
4025 01:02:39.679107
4026 01:02:39.679483 RX Vref 0 -> 0, step: 1
4027 01:02:39.679829
4028 01:02:39.682053 RX Delay -230 -> 252, step: 16
4029 01:02:39.688693 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4030 01:02:39.692037 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4031 01:02:39.695538 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4032 01:02:39.698831 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4033 01:02:39.702308 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4034 01:02:39.708965 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4035 01:02:39.712153 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4036 01:02:39.715370 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4037 01:02:39.718848 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4038 01:02:39.725849 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4039 01:02:39.728511 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4040 01:02:39.732085 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4041 01:02:39.736102 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4042 01:02:39.741598 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4043 01:02:39.745479 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4044 01:02:39.748558 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4045 01:02:39.749129 ==
4046 01:02:39.751971 Dram Type= 6, Freq= 0, CH_0, rank 0
4047 01:02:39.755202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4048 01:02:39.755682 ==
4049 01:02:39.758605 DQS Delay:
4050 01:02:39.759075 DQS0 = 0, DQS1 = 0
4051 01:02:39.761671 DQM Delay:
4052 01:02:39.762182 DQM0 = 51, DQM1 = 41
4053 01:02:39.762559 DQ Delay:
4054 01:02:39.765329 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4055 01:02:39.768443 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4056 01:02:39.772051 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4057 01:02:39.774780 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4058 01:02:39.775255
4059 01:02:39.775695
4060 01:02:39.778377 ==
4061 01:02:39.778941 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 01:02:39.785121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 01:02:39.785735 ==
4064 01:02:39.786153
4065 01:02:39.786505
4066 01:02:39.788509 TX Vref Scan disable
4067 01:02:39.788981 == TX Byte 0 ==
4068 01:02:39.791521 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4069 01:02:39.798488 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4070 01:02:39.799017 == TX Byte 1 ==
4071 01:02:39.805124 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4072 01:02:39.808625 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4073 01:02:39.809154 ==
4074 01:02:39.811527 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 01:02:39.815122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 01:02:39.815651 ==
4077 01:02:39.815994
4078 01:02:39.816314
4079 01:02:39.818209 TX Vref Scan disable
4080 01:02:39.821412 == TX Byte 0 ==
4081 01:02:39.824529 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4082 01:02:39.828131 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4083 01:02:39.831047 == TX Byte 1 ==
4084 01:02:39.834541 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4085 01:02:39.838205 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4086 01:02:39.838733
4087 01:02:39.841429 [DATLAT]
4088 01:02:39.841853 Freq=600, CH0 RK0
4089 01:02:39.842246
4090 01:02:39.844366 DATLAT Default: 0x9
4091 01:02:39.844794 0, 0xFFFF, sum = 0
4092 01:02:39.848121 1, 0xFFFF, sum = 0
4093 01:02:39.848647 2, 0xFFFF, sum = 0
4094 01:02:39.851284 3, 0xFFFF, sum = 0
4095 01:02:39.851819 4, 0xFFFF, sum = 0
4096 01:02:39.854337 5, 0xFFFF, sum = 0
4097 01:02:39.854768 6, 0xFFFF, sum = 0
4098 01:02:39.858064 7, 0xFFFF, sum = 0
4099 01:02:39.858635 8, 0x0, sum = 1
4100 01:02:39.861084 9, 0x0, sum = 2
4101 01:02:39.861663 10, 0x0, sum = 3
4102 01:02:39.864264 11, 0x0, sum = 4
4103 01:02:39.864697 best_step = 9
4104 01:02:39.865037
4105 01:02:39.865353 ==
4106 01:02:39.867768 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 01:02:39.871978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 01:02:39.874238 ==
4109 01:02:39.874792 RX Vref Scan: 1
4110 01:02:39.875330
4111 01:02:39.877752 RX Vref 0 -> 0, step: 1
4112 01:02:39.878233
4113 01:02:39.882810 RX Delay -179 -> 252, step: 8
4114 01:02:39.883360
4115 01:02:39.884453 Set Vref, RX VrefLevel [Byte0]: 59
4116 01:02:39.884877 [Byte1]: 50
4117 01:02:39.889615
4118 01:02:39.890222 Final RX Vref Byte 0 = 59 to rank0
4119 01:02:39.893031 Final RX Vref Byte 1 = 50 to rank0
4120 01:02:39.896298 Final RX Vref Byte 0 = 59 to rank1
4121 01:02:39.899783 Final RX Vref Byte 1 = 50 to rank1==
4122 01:02:39.902721 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 01:02:39.909562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 01:02:39.910138 ==
4125 01:02:39.910494 DQS Delay:
4126 01:02:39.910815 DQS0 = 0, DQS1 = 0
4127 01:02:39.912612 DQM Delay:
4128 01:02:39.913037 DQM0 = 48, DQM1 = 37
4129 01:02:39.916329 DQ Delay:
4130 01:02:39.919696 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4131 01:02:39.923080 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4132 01:02:39.923606 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4133 01:02:39.929666 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4134 01:02:39.930235
4135 01:02:39.930585
4136 01:02:39.935949 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4137 01:02:39.939266 CH0 RK0: MR19=808, MR18=5953
4138 01:02:39.946038 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4139 01:02:39.946468
4140 01:02:39.949136 ----->DramcWriteLeveling(PI) begin...
4141 01:02:39.949566 ==
4142 01:02:39.952876 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 01:02:39.956184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 01:02:39.956713 ==
4145 01:02:39.959409 Write leveling (Byte 0): 35 => 35
4146 01:02:39.962529 Write leveling (Byte 1): 31 => 31
4147 01:02:39.965859 DramcWriteLeveling(PI) end<-----
4148 01:02:39.966417
4149 01:02:39.966762 ==
4150 01:02:39.969384 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 01:02:39.972542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 01:02:39.973071 ==
4153 01:02:39.976015 [Gating] SW mode calibration
4154 01:02:39.982333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4155 01:02:39.988951 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4156 01:02:39.992139 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 01:02:39.998859 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 01:02:40.002311 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 01:02:40.005570 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
4160 01:02:40.012054 0 9 16 | B1->B0 | 2626 2424 | 1 1 | (1 0) (1 0)
4161 01:02:40.015346 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 01:02:40.018771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 01:02:40.025417 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 01:02:40.029468 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 01:02:40.032097 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 01:02:40.035314 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 01:02:40.042056 0 10 12 | B1->B0 | 2c2c 3434 | 1 0 | (0 0) (0 0)
4168 01:02:40.045668 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4169 01:02:40.048838 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 01:02:40.055647 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 01:02:40.058631 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 01:02:40.062616 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 01:02:40.069046 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 01:02:40.072038 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 01:02:40.075283 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 01:02:40.081862 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 01:02:40.085337 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 01:02:40.088606 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 01:02:40.095580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 01:02:40.098233 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 01:02:40.101600 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 01:02:40.108272 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 01:02:40.111898 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 01:02:40.115016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 01:02:40.121588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 01:02:40.125193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 01:02:40.128133 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 01:02:40.134889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 01:02:40.138195 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 01:02:40.141419 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 01:02:40.148707 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 01:02:40.151324 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 01:02:40.154960 Total UI for P1: 0, mck2ui 16
4194 01:02:40.158141 best dqsien dly found for B0: ( 0, 13, 14)
4195 01:02:40.161550 Total UI for P1: 0, mck2ui 16
4196 01:02:40.164966 best dqsien dly found for B1: ( 0, 13, 14)
4197 01:02:40.168284 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4198 01:02:40.171480 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4199 01:02:40.172051
4200 01:02:40.174611 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 01:02:40.177726 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4202 01:02:40.181621 [Gating] SW calibration Done
4203 01:02:40.182116 ==
4204 01:02:40.184533 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 01:02:40.188176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 01:02:40.191546 ==
4207 01:02:40.192116 RX Vref Scan: 0
4208 01:02:40.192495
4209 01:02:40.194607 RX Vref 0 -> 0, step: 1
4210 01:02:40.195080
4211 01:02:40.197800 RX Delay -230 -> 252, step: 16
4212 01:02:40.201425 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4213 01:02:40.204782 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4214 01:02:40.208669 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4215 01:02:40.211392 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4216 01:02:40.218105 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4217 01:02:40.222037 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4218 01:02:40.224612 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4219 01:02:40.227896 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4220 01:02:40.234857 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4221 01:02:40.238033 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4222 01:02:40.241365 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4223 01:02:40.244410 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4224 01:02:40.248041 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4225 01:02:40.254454 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4226 01:02:40.258113 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4227 01:02:40.261612 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4228 01:02:40.262210 ==
4229 01:02:40.264768 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 01:02:40.268156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 01:02:40.271305 ==
4232 01:02:40.271873 DQS Delay:
4233 01:02:40.272250 DQS0 = 0, DQS1 = 0
4234 01:02:40.274623 DQM Delay:
4235 01:02:40.275095 DQM0 = 48, DQM1 = 41
4236 01:02:40.278215 DQ Delay:
4237 01:02:40.281435 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4238 01:02:40.281910 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4239 01:02:40.284837 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4240 01:02:40.287920 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4241 01:02:40.291599
4242 01:02:40.292162
4243 01:02:40.292537 ==
4244 01:02:40.294436 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 01:02:40.297797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 01:02:40.298299 ==
4247 01:02:40.298674
4248 01:02:40.299023
4249 01:02:40.301249 TX Vref Scan disable
4250 01:02:40.301819 == TX Byte 0 ==
4251 01:02:40.307997 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4252 01:02:40.310962 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4253 01:02:40.311594 == TX Byte 1 ==
4254 01:02:40.317674 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4255 01:02:40.320892 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4256 01:02:40.321381 ==
4257 01:02:40.324026 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 01:02:40.327519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 01:02:40.328044 ==
4260 01:02:40.328423
4261 01:02:40.328774
4262 01:02:40.330674 TX Vref Scan disable
4263 01:02:40.334391 == TX Byte 0 ==
4264 01:02:40.337314 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4265 01:02:40.344203 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4266 01:02:40.344716 == TX Byte 1 ==
4267 01:02:40.347447 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4268 01:02:40.354335 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4269 01:02:40.354873
4270 01:02:40.355221 [DATLAT]
4271 01:02:40.355538 Freq=600, CH0 RK1
4272 01:02:40.355848
4273 01:02:40.357877 DATLAT Default: 0x9
4274 01:02:40.358343 0, 0xFFFF, sum = 0
4275 01:02:40.360841 1, 0xFFFF, sum = 0
4276 01:02:40.361273 2, 0xFFFF, sum = 0
4277 01:02:40.363861 3, 0xFFFF, sum = 0
4278 01:02:40.367249 4, 0xFFFF, sum = 0
4279 01:02:40.367780 5, 0xFFFF, sum = 0
4280 01:02:40.370865 6, 0xFFFF, sum = 0
4281 01:02:40.371397 7, 0xFFFF, sum = 0
4282 01:02:40.373758 8, 0x0, sum = 1
4283 01:02:40.374324 9, 0x0, sum = 2
4284 01:02:40.377086 10, 0x0, sum = 3
4285 01:02:40.377617 11, 0x0, sum = 4
4286 01:02:40.377991 best_step = 9
4287 01:02:40.378316
4288 01:02:40.380645 ==
4289 01:02:40.381072 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 01:02:40.387233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 01:02:40.387762 ==
4292 01:02:40.388108 RX Vref Scan: 0
4293 01:02:40.388423
4294 01:02:40.390502 RX Vref 0 -> 0, step: 1
4295 01:02:40.390918
4296 01:02:40.393693 RX Delay -179 -> 252, step: 8
4297 01:02:40.396904 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4298 01:02:40.403555 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4299 01:02:40.406914 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4300 01:02:40.410004 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4301 01:02:40.413763 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4302 01:02:40.416848 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4303 01:02:40.423992 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4304 01:02:40.427297 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4305 01:02:40.430310 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4306 01:02:40.433596 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4307 01:02:40.440184 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4308 01:02:40.443640 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4309 01:02:40.447115 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4310 01:02:40.450044 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4311 01:02:40.453485 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4312 01:02:40.460153 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4313 01:02:40.460667 ==
4314 01:02:40.463480 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 01:02:40.466755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 01:02:40.467272 ==
4317 01:02:40.467608 DQS Delay:
4318 01:02:40.470543 DQS0 = 0, DQS1 = 0
4319 01:02:40.471053 DQM Delay:
4320 01:02:40.473590 DQM0 = 48, DQM1 = 41
4321 01:02:40.474143 DQ Delay:
4322 01:02:40.476717 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4323 01:02:40.480696 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4324 01:02:40.483405 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4325 01:02:40.486829 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4326 01:02:40.487343
4327 01:02:40.487675
4328 01:02:40.497183 [DQSOSCAuto] RK1, (LSB)MR18= 0x612f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4329 01:02:40.497706 CH0 RK1: MR19=808, MR18=612F
4330 01:02:40.503367 CH0_RK1: MR19=0x808, MR18=0x612F, DQSOSC=391, MR23=63, INC=171, DEC=114
4331 01:02:40.506762 [RxdqsGatingPostProcess] freq 600
4332 01:02:40.513170 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4333 01:02:40.516853 Pre-setting of DQS Precalculation
4334 01:02:40.519894 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4335 01:02:40.520408 ==
4336 01:02:40.523408 Dram Type= 6, Freq= 0, CH_1, rank 0
4337 01:02:40.526656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 01:02:40.527193 ==
4339 01:02:40.534060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4340 01:02:40.540095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4341 01:02:40.543410 [CA 0] Center 35 (5~66) winsize 62
4342 01:02:40.546142 [CA 1] Center 35 (5~66) winsize 62
4343 01:02:40.549738 [CA 2] Center 34 (4~65) winsize 62
4344 01:02:40.553045 [CA 3] Center 33 (3~64) winsize 62
4345 01:02:40.556447 [CA 4] Center 34 (3~65) winsize 63
4346 01:02:40.559806 [CA 5] Center 33 (3~64) winsize 62
4347 01:02:40.560221
4348 01:02:40.563022 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4349 01:02:40.563552
4350 01:02:40.566449 [CATrainingPosCal] consider 1 rank data
4351 01:02:40.569739 u2DelayCellTimex100 = 270/100 ps
4352 01:02:40.573585 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4353 01:02:40.576090 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4354 01:02:40.579896 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4355 01:02:40.583067 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4356 01:02:40.589707 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4357 01:02:40.593122 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4358 01:02:40.593637
4359 01:02:40.596253 CA PerBit enable=1, Macro0, CA PI delay=33
4360 01:02:40.596769
4361 01:02:40.599653 [CBTSetCACLKResult] CA Dly = 33
4362 01:02:40.600167 CS Dly: 4 (0~35)
4363 01:02:40.600502 ==
4364 01:02:40.603075 Dram Type= 6, Freq= 0, CH_1, rank 1
4365 01:02:40.609737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 01:02:40.610292 ==
4367 01:02:40.613012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 01:02:40.619962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4369 01:02:40.622847 [CA 0] Center 35 (5~66) winsize 62
4370 01:02:40.626498 [CA 1] Center 35 (5~66) winsize 62
4371 01:02:40.629580 [CA 2] Center 34 (4~65) winsize 62
4372 01:02:40.632747 [CA 3] Center 34 (4~65) winsize 62
4373 01:02:40.636497 [CA 4] Center 34 (4~64) winsize 61
4374 01:02:40.639368 [CA 5] Center 33 (3~64) winsize 62
4375 01:02:40.639925
4376 01:02:40.644895 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4377 01:02:40.645407
4378 01:02:40.646825 [CATrainingPosCal] consider 2 rank data
4379 01:02:40.649276 u2DelayCellTimex100 = 270/100 ps
4380 01:02:40.652707 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 01:02:40.655991 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 01:02:40.659195 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 01:02:40.666069 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4384 01:02:40.669451 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4385 01:02:40.672833 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 01:02:40.673355
4387 01:02:40.675942 CA PerBit enable=1, Macro0, CA PI delay=33
4388 01:02:40.676373
4389 01:02:40.679669 [CBTSetCACLKResult] CA Dly = 33
4390 01:02:40.680201 CS Dly: 5 (0~37)
4391 01:02:40.680548
4392 01:02:40.682811 ----->DramcWriteLeveling(PI) begin...
4393 01:02:40.683244 ==
4394 01:02:40.686216 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 01:02:40.692931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 01:02:40.693466 ==
4397 01:02:40.696285 Write leveling (Byte 0): 31 => 31
4398 01:02:40.699674 Write leveling (Byte 1): 30 => 30
4399 01:02:40.700199 DramcWriteLeveling(PI) end<-----
4400 01:02:40.700545
4401 01:02:40.702903 ==
4402 01:02:40.706521 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 01:02:40.709715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 01:02:40.710173 ==
4405 01:02:40.713095 [Gating] SW mode calibration
4406 01:02:40.719451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4407 01:02:40.722914 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4408 01:02:40.729545 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 01:02:40.732388 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 01:02:40.735849 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4411 01:02:40.742740 0 9 12 | B1->B0 | 3030 2929 | 0 1 | (0 1) (1 0)
4412 01:02:40.746273 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 01:02:40.749779 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 01:02:40.755950 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 01:02:40.759335 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 01:02:40.762873 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 01:02:40.769529 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 01:02:40.772632 0 10 8 | B1->B0 | 2626 2828 | 0 0 | (0 0) (1 1)
4419 01:02:40.776207 0 10 12 | B1->B0 | 3c3c 3e3e | 0 0 | (0 0) (0 0)
4420 01:02:40.779145 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 01:02:40.785910 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 01:02:40.789335 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 01:02:40.793138 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 01:02:40.799560 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 01:02:40.802683 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 01:02:40.805783 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 01:02:40.812679 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4428 01:02:40.816160 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 01:02:40.819729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 01:02:40.826094 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 01:02:40.828962 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 01:02:40.832527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 01:02:40.839260 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 01:02:40.842592 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 01:02:40.846422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 01:02:40.852378 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 01:02:40.855594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 01:02:40.859085 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 01:02:40.865500 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 01:02:40.868962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 01:02:40.872345 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 01:02:40.879363 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 01:02:40.882084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4444 01:02:40.885678 Total UI for P1: 0, mck2ui 16
4445 01:02:40.888944 best dqsien dly found for B0: ( 0, 13, 10)
4446 01:02:40.892301 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 01:02:40.895518 Total UI for P1: 0, mck2ui 16
4448 01:02:40.898877 best dqsien dly found for B1: ( 0, 13, 12)
4449 01:02:40.901934 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4450 01:02:40.905934 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4451 01:02:40.906401
4452 01:02:40.908648 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4453 01:02:40.915794 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 01:02:40.916330 [Gating] SW calibration Done
4455 01:02:40.918824 ==
4456 01:02:40.919359 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 01:02:40.925647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 01:02:40.926279 ==
4459 01:02:40.926664 RX Vref Scan: 0
4460 01:02:40.927017
4461 01:02:40.928757 RX Vref 0 -> 0, step: 1
4462 01:02:40.929225
4463 01:02:40.932179 RX Delay -230 -> 252, step: 16
4464 01:02:40.935265 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4465 01:02:40.938597 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4466 01:02:40.946236 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4467 01:02:40.948883 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4468 01:02:40.952108 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4469 01:02:40.955350 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4470 01:02:40.958549 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4471 01:02:40.965481 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4472 01:02:40.968362 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4473 01:02:40.971913 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4474 01:02:40.975341 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4475 01:02:40.981865 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4476 01:02:40.985443 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4477 01:02:40.988661 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4478 01:02:40.991653 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4479 01:02:40.998498 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4480 01:02:40.999075 ==
4481 01:02:41.002030 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 01:02:41.005169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 01:02:41.005739 ==
4484 01:02:41.006180 DQS Delay:
4485 01:02:41.008278 DQS0 = 0, DQS1 = 0
4486 01:02:41.008845 DQM Delay:
4487 01:02:41.011615 DQM0 = 49, DQM1 = 42
4488 01:02:41.012188 DQ Delay:
4489 01:02:41.015223 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4490 01:02:41.018342 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4491 01:02:41.021794 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4492 01:02:41.025022 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4493 01:02:41.025592
4494 01:02:41.026014
4495 01:02:41.026376 ==
4496 01:02:41.028421 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 01:02:41.031404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 01:02:41.031888 ==
4499 01:02:41.034708
4500 01:02:41.035267
4501 01:02:41.035651 TX Vref Scan disable
4502 01:02:41.038114 == TX Byte 0 ==
4503 01:02:41.041648 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4504 01:02:41.045002 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4505 01:02:41.048198 == TX Byte 1 ==
4506 01:02:41.051412 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4507 01:02:41.055273 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4508 01:02:41.055843 ==
4509 01:02:41.058384 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 01:02:41.064834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 01:02:41.065401 ==
4512 01:02:41.065775
4513 01:02:41.066176
4514 01:02:41.066510 TX Vref Scan disable
4515 01:02:41.069449 == TX Byte 0 ==
4516 01:02:41.072881 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4517 01:02:41.079402 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4518 01:02:41.079998 == TX Byte 1 ==
4519 01:02:41.082460 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 01:02:41.089439 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 01:02:41.090078
4522 01:02:41.090568 [DATLAT]
4523 01:02:41.091056 Freq=600, CH1 RK0
4524 01:02:41.091500
4525 01:02:41.092426 DATLAT Default: 0x9
4526 01:02:41.092935 0, 0xFFFF, sum = 0
4527 01:02:41.095836 1, 0xFFFF, sum = 0
4528 01:02:41.096418 2, 0xFFFF, sum = 0
4529 01:02:41.099435 3, 0xFFFF, sum = 0
4530 01:02:41.100022 4, 0xFFFF, sum = 0
4531 01:02:41.102670 5, 0xFFFF, sum = 0
4532 01:02:41.106304 6, 0xFFFF, sum = 0
4533 01:02:41.106947 7, 0xFFFF, sum = 0
4534 01:02:41.107442 8, 0x0, sum = 1
4535 01:02:41.108999 9, 0x0, sum = 2
4536 01:02:41.109489 10, 0x0, sum = 3
4537 01:02:41.112724 11, 0x0, sum = 4
4538 01:02:41.113313 best_step = 9
4539 01:02:41.113800
4540 01:02:41.114293 ==
4541 01:02:41.115681 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 01:02:41.122559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 01:02:41.123141 ==
4544 01:02:41.123630 RX Vref Scan: 1
4545 01:02:41.124084
4546 01:02:41.126304 RX Vref 0 -> 0, step: 1
4547 01:02:41.126883
4548 01:02:41.129214 RX Delay -179 -> 252, step: 8
4549 01:02:41.129793
4550 01:02:41.132056 Set Vref, RX VrefLevel [Byte0]: 52
4551 01:02:41.135689 [Byte1]: 52
4552 01:02:41.136189
4553 01:02:41.138971 Final RX Vref Byte 0 = 52 to rank0
4554 01:02:41.142812 Final RX Vref Byte 1 = 52 to rank0
4555 01:02:41.145698 Final RX Vref Byte 0 = 52 to rank1
4556 01:02:41.148924 Final RX Vref Byte 1 = 52 to rank1==
4557 01:02:41.152546 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 01:02:41.155560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 01:02:41.156145 ==
4560 01:02:41.158851 DQS Delay:
4561 01:02:41.159329 DQS0 = 0, DQS1 = 0
4562 01:02:41.162050 DQM Delay:
4563 01:02:41.162530 DQM0 = 48, DQM1 = 40
4564 01:02:41.163002 DQ Delay:
4565 01:02:41.165558 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4566 01:02:41.168957 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4567 01:02:41.171971 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4568 01:02:41.175645 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4569 01:02:41.176240
4570 01:02:41.176729
4571 01:02:41.185738 [DQSOSCAuto] RK0, (LSB)MR18= 0x466d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4572 01:02:41.188802 CH1 RK0: MR19=808, MR18=466D
4573 01:02:41.192397 CH1_RK0: MR19=0x808, MR18=0x466D, DQSOSC=389, MR23=63, INC=173, DEC=115
4574 01:02:41.192978
4575 01:02:41.195497 ----->DramcWriteLeveling(PI) begin...
4576 01:02:41.198559 ==
4577 01:02:41.202255 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 01:02:41.205327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 01:02:41.205881 ==
4580 01:02:41.209284 Write leveling (Byte 0): 29 => 29
4581 01:02:41.211915 Write leveling (Byte 1): 32 => 32
4582 01:02:41.215601 DramcWriteLeveling(PI) end<-----
4583 01:02:41.216198
4584 01:02:41.216682 ==
4585 01:02:41.218628 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 01:02:41.222017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 01:02:41.222505 ==
4588 01:02:41.225368 [Gating] SW mode calibration
4589 01:02:41.231652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4590 01:02:41.238820 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4591 01:02:41.241853 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 01:02:41.245561 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 01:02:41.251790 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4594 01:02:41.255497 0 9 12 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (1 1)
4595 01:02:41.258670 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 01:02:41.265239 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 01:02:41.269006 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 01:02:41.271957 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 01:02:41.278461 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 01:02:41.281824 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 01:02:41.285160 0 10 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
4602 01:02:41.291656 0 10 12 | B1->B0 | 3838 2d2d | 0 0 | (1 1) (1 1)
4603 01:02:41.294771 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 01:02:41.298179 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 01:02:41.301617 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 01:02:41.308516 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 01:02:41.311583 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 01:02:41.314680 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 01:02:41.321397 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 01:02:41.324782 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4611 01:02:41.328394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 01:02:41.334131 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 01:02:41.337558 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 01:02:41.341161 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 01:02:41.347976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 01:02:41.350831 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 01:02:41.354389 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 01:02:41.361147 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 01:02:41.364363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 01:02:41.367864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 01:02:41.374792 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 01:02:41.377875 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 01:02:41.381143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 01:02:41.387764 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 01:02:41.390803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4626 01:02:41.394272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4627 01:02:41.397774 Total UI for P1: 0, mck2ui 16
4628 01:02:41.401330 best dqsien dly found for B0: ( 0, 13, 8)
4629 01:02:41.407621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 01:02:41.408196 Total UI for P1: 0, mck2ui 16
4631 01:02:41.410759 best dqsien dly found for B1: ( 0, 13, 12)
4632 01:02:41.418080 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4633 01:02:41.421196 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4634 01:02:41.421773
4635 01:02:41.424676 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4636 01:02:41.427856 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 01:02:41.430986 [Gating] SW calibration Done
4638 01:02:41.431601 ==
4639 01:02:41.434551 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 01:02:41.437765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 01:02:41.438267 ==
4642 01:02:41.441170 RX Vref Scan: 0
4643 01:02:41.441736
4644 01:02:41.442166 RX Vref 0 -> 0, step: 1
4645 01:02:41.442525
4646 01:02:41.444256 RX Delay -230 -> 252, step: 16
4647 01:02:41.447576 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4648 01:02:41.453867 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4649 01:02:41.457622 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4650 01:02:41.461023 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4651 01:02:41.464404 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4652 01:02:41.467779 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4653 01:02:41.474526 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4654 01:02:41.477522 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4655 01:02:41.481199 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4656 01:02:41.483870 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4657 01:02:41.490964 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4658 01:02:41.494097 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4659 01:02:41.497223 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4660 01:02:41.501290 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4661 01:02:41.507505 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4662 01:02:41.511812 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4663 01:02:41.512385 ==
4664 01:02:41.514237 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 01:02:41.517348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 01:02:41.517926 ==
4667 01:02:41.520808 DQS Delay:
4668 01:02:41.521376 DQS0 = 0, DQS1 = 0
4669 01:02:41.521754 DQM Delay:
4670 01:02:41.523713 DQM0 = 50, DQM1 = 46
4671 01:02:41.524198 DQ Delay:
4672 01:02:41.527308 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4673 01:02:41.530406 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4674 01:02:41.533667 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4675 01:02:41.537187 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4676 01:02:41.537657
4677 01:02:41.538069
4678 01:02:41.538432 ==
4679 01:02:41.540604 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 01:02:41.547177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 01:02:41.547747 ==
4682 01:02:41.548125
4683 01:02:41.548474
4684 01:02:41.548806 TX Vref Scan disable
4685 01:02:41.550466 == TX Byte 0 ==
4686 01:02:41.553880 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4687 01:02:41.560459 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4688 01:02:41.561012 == TX Byte 1 ==
4689 01:02:41.564092 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4690 01:02:41.570809 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4691 01:02:41.571379 ==
4692 01:02:41.574186 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 01:02:41.577405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 01:02:41.578012 ==
4695 01:02:41.578402
4696 01:02:41.578753
4697 01:02:41.580652 TX Vref Scan disable
4698 01:02:41.583977 == TX Byte 0 ==
4699 01:02:41.587997 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4700 01:02:41.591237 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4701 01:02:41.591809 == TX Byte 1 ==
4702 01:02:41.597401 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4703 01:02:41.601069 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4704 01:02:41.601638
4705 01:02:41.602055 [DATLAT]
4706 01:02:41.603889 Freq=600, CH1 RK1
4707 01:02:41.604465
4708 01:02:41.604941 DATLAT Default: 0x9
4709 01:02:41.607013 0, 0xFFFF, sum = 0
4710 01:02:41.607495 1, 0xFFFF, sum = 0
4711 01:02:41.610630 2, 0xFFFF, sum = 0
4712 01:02:41.613864 3, 0xFFFF, sum = 0
4713 01:02:41.614474 4, 0xFFFF, sum = 0
4714 01:02:41.617314 5, 0xFFFF, sum = 0
4715 01:02:41.617902 6, 0xFFFF, sum = 0
4716 01:02:41.620698 7, 0xFFFF, sum = 0
4717 01:02:41.621275 8, 0x0, sum = 1
4718 01:02:41.621662 9, 0x0, sum = 2
4719 01:02:41.624225 10, 0x0, sum = 3
4720 01:02:41.624704 11, 0x0, sum = 4
4721 01:02:41.627407 best_step = 9
4722 01:02:41.627976
4723 01:02:41.628351 ==
4724 01:02:41.630509 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 01:02:41.633620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 01:02:41.634131 ==
4727 01:02:41.636960 RX Vref Scan: 0
4728 01:02:41.637494
4729 01:02:41.637871 RX Vref 0 -> 0, step: 1
4730 01:02:41.638286
4731 01:02:41.640456 RX Delay -163 -> 252, step: 8
4732 01:02:41.647735 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4733 01:02:41.651185 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4734 01:02:41.654469 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4735 01:02:41.657898 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4736 01:02:41.661244 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4737 01:02:41.667723 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4738 01:02:41.671107 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4739 01:02:41.674367 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4740 01:02:41.677811 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4741 01:02:41.683928 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4742 01:02:41.687628 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4743 01:02:41.690811 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4744 01:02:41.694211 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4745 01:02:41.697837 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4746 01:02:41.704134 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4747 01:02:41.707722 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4748 01:02:41.708290 ==
4749 01:02:41.710664 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 01:02:41.714115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 01:02:41.714681 ==
4752 01:02:41.717463 DQS Delay:
4753 01:02:41.718073 DQS0 = 0, DQS1 = 0
4754 01:02:41.718461 DQM Delay:
4755 01:02:41.720564 DQM0 = 49, DQM1 = 44
4756 01:02:41.721133 DQ Delay:
4757 01:02:41.723887 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4758 01:02:41.727307 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4759 01:02:41.730576 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4760 01:02:41.733580 DQ12 =48, DQ13 =52, DQ14 =48, DQ15 =52
4761 01:02:41.734091
4762 01:02:41.734469
4763 01:02:41.744011 [DQSOSCAuto] RK1, (LSB)MR18= 0x541a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
4764 01:02:41.747064 CH1 RK1: MR19=808, MR18=541A
4765 01:02:41.750396 CH1_RK1: MR19=0x808, MR18=0x541A, DQSOSC=393, MR23=63, INC=169, DEC=113
4766 01:02:41.753795 [RxdqsGatingPostProcess] freq 600
4767 01:02:41.760402 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4768 01:02:41.764481 Pre-setting of DQS Precalculation
4769 01:02:41.766895 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4770 01:02:41.774339 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4771 01:02:41.783605 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4772 01:02:41.784175
4773 01:02:41.784556
4774 01:02:41.787254 [Calibration Summary] 1200 Mbps
4775 01:02:41.787724 CH 0, Rank 0
4776 01:02:41.790396 SW Impedance : PASS
4777 01:02:41.790961 DUTY Scan : NO K
4778 01:02:41.793465 ZQ Calibration : PASS
4779 01:02:41.797154 Jitter Meter : NO K
4780 01:02:41.797727 CBT Training : PASS
4781 01:02:41.800637 Write leveling : PASS
4782 01:02:41.801203 RX DQS gating : PASS
4783 01:02:41.804020 RX DQ/DQS(RDDQC) : PASS
4784 01:02:41.807155 TX DQ/DQS : PASS
4785 01:02:41.807726 RX DATLAT : PASS
4786 01:02:41.810470 RX DQ/DQS(Engine): PASS
4787 01:02:41.813858 TX OE : NO K
4788 01:02:41.814462 All Pass.
4789 01:02:41.814842
4790 01:02:41.815190 CH 0, Rank 1
4791 01:02:41.817122 SW Impedance : PASS
4792 01:02:41.820084 DUTY Scan : NO K
4793 01:02:41.820558 ZQ Calibration : PASS
4794 01:02:41.823983 Jitter Meter : NO K
4795 01:02:41.826724 CBT Training : PASS
4796 01:02:41.827196 Write leveling : PASS
4797 01:02:41.830180 RX DQS gating : PASS
4798 01:02:41.833716 RX DQ/DQS(RDDQC) : PASS
4799 01:02:41.834241 TX DQ/DQS : PASS
4800 01:02:41.837032 RX DATLAT : PASS
4801 01:02:41.840054 RX DQ/DQS(Engine): PASS
4802 01:02:41.840575 TX OE : NO K
4803 01:02:41.841120 All Pass.
4804 01:02:41.843230
4805 01:02:41.843705 CH 1, Rank 0
4806 01:02:41.846832 SW Impedance : PASS
4807 01:02:41.847404 DUTY Scan : NO K
4808 01:02:41.850167 ZQ Calibration : PASS
4809 01:02:41.853317 Jitter Meter : NO K
4810 01:02:41.853793 CBT Training : PASS
4811 01:02:41.856532 Write leveling : PASS
4812 01:02:41.857000 RX DQS gating : PASS
4813 01:02:41.860060 RX DQ/DQS(RDDQC) : PASS
4814 01:02:41.863202 TX DQ/DQS : PASS
4815 01:02:41.863675 RX DATLAT : PASS
4816 01:02:41.866852 RX DQ/DQS(Engine): PASS
4817 01:02:41.870338 TX OE : NO K
4818 01:02:41.870992 All Pass.
4819 01:02:41.871396
4820 01:02:41.871747 CH 1, Rank 1
4821 01:02:41.873218 SW Impedance : PASS
4822 01:02:41.877068 DUTY Scan : NO K
4823 01:02:41.877543 ZQ Calibration : PASS
4824 01:02:41.880212 Jitter Meter : NO K
4825 01:02:41.883458 CBT Training : PASS
4826 01:02:41.883938 Write leveling : PASS
4827 01:02:41.887031 RX DQS gating : PASS
4828 01:02:41.890238 RX DQ/DQS(RDDQC) : PASS
4829 01:02:41.890809 TX DQ/DQS : PASS
4830 01:02:41.893687 RX DATLAT : PASS
4831 01:02:41.896955 RX DQ/DQS(Engine): PASS
4832 01:02:41.897525 TX OE : NO K
4833 01:02:41.897910 All Pass.
4834 01:02:41.900008
4835 01:02:41.900571 DramC Write-DBI off
4836 01:02:41.903437 PER_BANK_REFRESH: Hybrid Mode
4837 01:02:41.903999 TX_TRACKING: ON
4838 01:02:41.913290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4839 01:02:41.916401 [FAST_K] Save calibration result to emmc
4840 01:02:41.919703 dramc_set_vcore_voltage set vcore to 662500
4841 01:02:41.923032 Read voltage for 933, 3
4842 01:02:41.923705 Vio18 = 0
4843 01:02:41.926404 Vcore = 662500
4844 01:02:41.926927 Vdram = 0
4845 01:02:41.927611 Vddq = 0
4846 01:02:41.928270 Vmddr = 0
4847 01:02:41.932921 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4848 01:02:41.939608 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4849 01:02:41.940094 MEM_TYPE=3, freq_sel=17
4850 01:02:41.942680 sv_algorithm_assistance_LP4_1600
4851 01:02:41.946272 ============ PULL DRAM RESETB DOWN ============
4852 01:02:41.952664 ========== PULL DRAM RESETB DOWN end =========
4853 01:02:41.956332 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4854 01:02:41.959623 ===================================
4855 01:02:41.962726 LPDDR4 DRAM CONFIGURATION
4856 01:02:41.966233 ===================================
4857 01:02:41.966662 EX_ROW_EN[0] = 0x0
4858 01:02:41.969416 EX_ROW_EN[1] = 0x0
4859 01:02:41.969842 LP4Y_EN = 0x0
4860 01:02:41.972893 WORK_FSP = 0x0
4861 01:02:41.973329 WL = 0x3
4862 01:02:41.976249 RL = 0x3
4863 01:02:41.976772 BL = 0x2
4864 01:02:41.979727 RPST = 0x0
4865 01:02:41.982985 RD_PRE = 0x0
4866 01:02:41.983509 WR_PRE = 0x1
4867 01:02:41.986634 WR_PST = 0x0
4868 01:02:41.987063 DBI_WR = 0x0
4869 01:02:41.989690 DBI_RD = 0x0
4870 01:02:41.990264 OTF = 0x1
4871 01:02:41.992827 ===================================
4872 01:02:41.996521 ===================================
4873 01:02:41.999866 ANA top config
4874 01:02:42.003024 ===================================
4875 01:02:42.003552 DLL_ASYNC_EN = 0
4876 01:02:42.005861 ALL_SLAVE_EN = 1
4877 01:02:42.009846 NEW_RANK_MODE = 1
4878 01:02:42.012781 DLL_IDLE_MODE = 1
4879 01:02:42.013306 LP45_APHY_COMB_EN = 1
4880 01:02:42.016368 TX_ODT_DIS = 1
4881 01:02:42.019485 NEW_8X_MODE = 1
4882 01:02:42.022814 ===================================
4883 01:02:42.026095 ===================================
4884 01:02:42.029732 data_rate = 1866
4885 01:02:42.032811 CKR = 1
4886 01:02:42.035755 DQ_P2S_RATIO = 8
4887 01:02:42.038925 ===================================
4888 01:02:42.039357 CA_P2S_RATIO = 8
4889 01:02:42.042227 DQ_CA_OPEN = 0
4890 01:02:42.045921 DQ_SEMI_OPEN = 0
4891 01:02:42.049158 CA_SEMI_OPEN = 0
4892 01:02:42.052495 CA_FULL_RATE = 0
4893 01:02:42.056156 DQ_CKDIV4_EN = 1
4894 01:02:42.056581 CA_CKDIV4_EN = 1
4895 01:02:42.059131 CA_PREDIV_EN = 0
4896 01:02:42.062238 PH8_DLY = 0
4897 01:02:42.066066 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4898 01:02:42.068839 DQ_AAMCK_DIV = 4
4899 01:02:42.069333 CA_AAMCK_DIV = 4
4900 01:02:42.072305 CA_ADMCK_DIV = 4
4901 01:02:42.075844 DQ_TRACK_CA_EN = 0
4902 01:02:42.078830 CA_PICK = 933
4903 01:02:42.081986 CA_MCKIO = 933
4904 01:02:42.085442 MCKIO_SEMI = 0
4905 01:02:42.088817 PLL_FREQ = 3732
4906 01:02:42.092529 DQ_UI_PI_RATIO = 32
4907 01:02:42.093063 CA_UI_PI_RATIO = 0
4908 01:02:42.095624 ===================================
4909 01:02:42.098853 ===================================
4910 01:02:42.102836 memory_type:LPDDR4
4911 01:02:42.105160 GP_NUM : 10
4912 01:02:42.105590 SRAM_EN : 1
4913 01:02:42.108914 MD32_EN : 0
4914 01:02:42.112048 ===================================
4915 01:02:42.115430 [ANA_INIT] >>>>>>>>>>>>>>
4916 01:02:42.118685 <<<<<< [CONFIGURE PHASE]: ANA_TX
4917 01:02:42.122018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4918 01:02:42.125558 ===================================
4919 01:02:42.126162 data_rate = 1866,PCW = 0X8f00
4920 01:02:42.128754 ===================================
4921 01:02:42.132109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4922 01:02:42.138417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 01:02:42.145437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 01:02:42.148949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4925 01:02:42.152058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4926 01:02:42.155294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4927 01:02:42.158555 [ANA_INIT] flow start
4928 01:02:42.159028 [ANA_INIT] PLL >>>>>>>>
4929 01:02:42.162416 [ANA_INIT] PLL <<<<<<<<
4930 01:02:42.165527 [ANA_INIT] MIDPI >>>>>>>>
4931 01:02:42.168874 [ANA_INIT] MIDPI <<<<<<<<
4932 01:02:42.169345 [ANA_INIT] DLL >>>>>>>>
4933 01:02:42.172280 [ANA_INIT] flow end
4934 01:02:42.175331 ============ LP4 DIFF to SE enter ============
4935 01:02:42.178575 ============ LP4 DIFF to SE exit ============
4936 01:02:42.182117 [ANA_INIT] <<<<<<<<<<<<<
4937 01:02:42.185367 [Flow] Enable top DCM control >>>>>
4938 01:02:42.188345 [Flow] Enable top DCM control <<<<<
4939 01:02:42.192348 Enable DLL master slave shuffle
4940 01:02:42.198570 ==============================================================
4941 01:02:42.199141 Gating Mode config
4942 01:02:42.205482 ==============================================================
4943 01:02:42.206084 Config description:
4944 01:02:42.215268 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4945 01:02:42.221616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4946 01:02:42.228687 SELPH_MODE 0: By rank 1: By Phase
4947 01:02:42.231855 ==============================================================
4948 01:02:42.234719 GAT_TRACK_EN = 1
4949 01:02:42.238482 RX_GATING_MODE = 2
4950 01:02:42.241736 RX_GATING_TRACK_MODE = 2
4951 01:02:42.245062 SELPH_MODE = 1
4952 01:02:42.248248 PICG_EARLY_EN = 1
4953 01:02:42.251872 VALID_LAT_VALUE = 1
4954 01:02:42.254733 ==============================================================
4955 01:02:42.257972 Enter into Gating configuration >>>>
4956 01:02:42.261414 Exit from Gating configuration <<<<
4957 01:02:42.264579 Enter into DVFS_PRE_config >>>>>
4958 01:02:42.277900 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4959 01:02:42.281231 Exit from DVFS_PRE_config <<<<<
4960 01:02:42.284885 Enter into PICG configuration >>>>
4961 01:02:42.287692 Exit from PICG configuration <<<<
4962 01:02:42.288167 [RX_INPUT] configuration >>>>>
4963 01:02:42.291366 [RX_INPUT] configuration <<<<<
4964 01:02:42.298337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4965 01:02:42.301406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4966 01:02:42.308232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 01:02:42.314702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 01:02:42.321652 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 01:02:42.328686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 01:02:42.331601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4971 01:02:42.334325 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4972 01:02:42.337833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4973 01:02:42.344798 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4974 01:02:42.347824 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4975 01:02:42.351352 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 01:02:42.354652 ===================================
4977 01:02:42.357737 LPDDR4 DRAM CONFIGURATION
4978 01:02:42.360920 ===================================
4979 01:02:42.364421 EX_ROW_EN[0] = 0x0
4980 01:02:42.365073 EX_ROW_EN[1] = 0x0
4981 01:02:42.367365 LP4Y_EN = 0x0
4982 01:02:42.367837 WORK_FSP = 0x0
4983 01:02:42.370682 WL = 0x3
4984 01:02:42.371152 RL = 0x3
4985 01:02:42.374046 BL = 0x2
4986 01:02:42.374544 RPST = 0x0
4987 01:02:42.377619 RD_PRE = 0x0
4988 01:02:42.378162 WR_PRE = 0x1
4989 01:02:42.380947 WR_PST = 0x0
4990 01:02:42.381510 DBI_WR = 0x0
4991 01:02:42.384032 DBI_RD = 0x0
4992 01:02:42.384581 OTF = 0x1
4993 01:02:42.387840 ===================================
4994 01:02:42.394299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4995 01:02:42.397517 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4996 01:02:42.400950 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 01:02:42.403848 ===================================
4998 01:02:42.407471 LPDDR4 DRAM CONFIGURATION
4999 01:02:42.410805 ===================================
5000 01:02:42.414212 EX_ROW_EN[0] = 0x10
5001 01:02:42.414800 EX_ROW_EN[1] = 0x0
5002 01:02:42.417353 LP4Y_EN = 0x0
5003 01:02:42.417918 WORK_FSP = 0x0
5004 01:02:42.420467 WL = 0x3
5005 01:02:42.420937 RL = 0x3
5006 01:02:42.424170 BL = 0x2
5007 01:02:42.424737 RPST = 0x0
5008 01:02:42.427481 RD_PRE = 0x0
5009 01:02:42.428050 WR_PRE = 0x1
5010 01:02:42.431068 WR_PST = 0x0
5011 01:02:42.431636 DBI_WR = 0x0
5012 01:02:42.434069 DBI_RD = 0x0
5013 01:02:42.434688 OTF = 0x1
5014 01:02:42.437271 ===================================
5015 01:02:42.444107 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5016 01:02:42.449596 nWR fixed to 30
5017 01:02:42.451898 [ModeRegInit_LP4] CH0 RK0
5018 01:02:42.452467 [ModeRegInit_LP4] CH0 RK1
5019 01:02:42.455185 [ModeRegInit_LP4] CH1 RK0
5020 01:02:42.458345 [ModeRegInit_LP4] CH1 RK1
5021 01:02:42.458816 match AC timing 9
5022 01:02:42.465126 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5023 01:02:42.468823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5024 01:02:42.472210 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5025 01:02:42.478478 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5026 01:02:42.481533 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5027 01:02:42.482138 ==
5028 01:02:42.485190 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 01:02:42.488832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5030 01:02:42.489337 ==
5031 01:02:42.495284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5032 01:02:42.501702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5033 01:02:42.504964 [CA 0] Center 37 (7~68) winsize 62
5034 01:02:42.508590 [CA 1] Center 37 (7~68) winsize 62
5035 01:02:42.512013 [CA 2] Center 35 (5~66) winsize 62
5036 01:02:42.515223 [CA 3] Center 34 (4~65) winsize 62
5037 01:02:42.518496 [CA 4] Center 34 (4~64) winsize 61
5038 01:02:42.521762 [CA 5] Center 33 (3~64) winsize 62
5039 01:02:42.522411
5040 01:02:42.524977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5041 01:02:42.525450
5042 01:02:42.528194 [CATrainingPosCal] consider 1 rank data
5043 01:02:42.531599 u2DelayCellTimex100 = 270/100 ps
5044 01:02:42.535155 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5045 01:02:42.538123 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5046 01:02:42.541526 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5047 01:02:42.545179 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5048 01:02:42.548334 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5049 01:02:42.554503 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5050 01:02:42.555065
5051 01:02:42.557720 CA PerBit enable=1, Macro0, CA PI delay=33
5052 01:02:42.558246
5053 01:02:42.561052 [CBTSetCACLKResult] CA Dly = 33
5054 01:02:42.561557 CS Dly: 7 (0~38)
5055 01:02:42.561986 ==
5056 01:02:42.564514 Dram Type= 6, Freq= 0, CH_0, rank 1
5057 01:02:42.567953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 01:02:42.571183 ==
5059 01:02:42.574063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 01:02:42.581088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5061 01:02:42.584752 [CA 0] Center 38 (7~69) winsize 63
5062 01:02:42.587537 [CA 1] Center 38 (8~69) winsize 62
5063 01:02:42.590764 [CA 2] Center 36 (6~66) winsize 61
5064 01:02:42.594219 [CA 3] Center 35 (5~66) winsize 62
5065 01:02:42.598945 [CA 4] Center 34 (4~65) winsize 62
5066 01:02:42.601477 [CA 5] Center 34 (4~64) winsize 61
5067 01:02:42.602130
5068 01:02:42.604307 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5069 01:02:42.604884
5070 01:02:42.607328 [CATrainingPosCal] consider 2 rank data
5071 01:02:42.610649 u2DelayCellTimex100 = 270/100 ps
5072 01:02:42.613717 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5073 01:02:42.617156 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5074 01:02:42.623863 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5075 01:02:42.627309 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5076 01:02:42.630437 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5077 01:02:42.633621 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5078 01:02:42.634135
5079 01:02:42.637175 CA PerBit enable=1, Macro0, CA PI delay=34
5080 01:02:42.637651
5081 01:02:42.640079 [CBTSetCACLKResult] CA Dly = 34
5082 01:02:42.640551 CS Dly: 7 (0~39)
5083 01:02:42.640924
5084 01:02:42.643835 ----->DramcWriteLeveling(PI) begin...
5085 01:02:42.647013 ==
5086 01:02:42.650134 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 01:02:42.653719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 01:02:42.654319 ==
5089 01:02:42.656991 Write leveling (Byte 0): 33 => 33
5090 01:02:42.660242 Write leveling (Byte 1): 29 => 29
5091 01:02:42.663504 DramcWriteLeveling(PI) end<-----
5092 01:02:42.664077
5093 01:02:42.664458 ==
5094 01:02:42.666579 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 01:02:42.670354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 01:02:42.670931 ==
5097 01:02:42.673195 [Gating] SW mode calibration
5098 01:02:42.680379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5099 01:02:42.686469 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5100 01:02:42.690047 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5101 01:02:42.693208 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 01:02:42.699809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 01:02:42.702962 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 01:02:42.706085 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 01:02:42.712767 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 01:02:42.716425 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5107 01:02:42.719795 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5108 01:02:42.726499 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5109 01:02:42.729643 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 01:02:42.733309 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 01:02:42.736841 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 01:02:42.743154 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 01:02:42.746737 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 01:02:42.750014 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5115 01:02:42.756084 0 15 28 | B1->B0 | 2727 4343 | 0 1 | (0 0) (0 0)
5116 01:02:42.759592 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5117 01:02:42.763340 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 01:02:42.769868 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 01:02:42.773354 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 01:02:42.776133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 01:02:42.782516 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 01:02:42.786353 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 01:02:42.789400 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 01:02:42.796065 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 01:02:42.799326 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 01:02:42.802647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 01:02:42.808856 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 01:02:42.812443 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 01:02:42.818365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 01:02:42.822029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 01:02:42.825432 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 01:02:42.828722 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 01:02:42.835289 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 01:02:42.838617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 01:02:42.842102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 01:02:42.848797 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 01:02:42.852224 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 01:02:42.855133 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 01:02:42.862364 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 01:02:42.865486 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 01:02:42.868783 Total UI for P1: 0, mck2ui 16
5142 01:02:42.871535 best dqsien dly found for B0: ( 1, 2, 26)
5143 01:02:42.874618 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 01:02:42.878130 Total UI for P1: 0, mck2ui 16
5145 01:02:42.881913 best dqsien dly found for B1: ( 1, 3, 0)
5146 01:02:42.884783 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5147 01:02:42.888233 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5148 01:02:42.888330
5149 01:02:42.894735 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5150 01:02:42.897884 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5151 01:02:42.897989 [Gating] SW calibration Done
5152 01:02:42.901191 ==
5153 01:02:42.904594 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 01:02:42.907953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 01:02:42.908042 ==
5156 01:02:42.908111 RX Vref Scan: 0
5157 01:02:42.908176
5158 01:02:42.911214 RX Vref 0 -> 0, step: 1
5159 01:02:42.911297
5160 01:02:42.914581 RX Delay -80 -> 252, step: 8
5161 01:02:42.917704 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5162 01:02:42.921122 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5163 01:02:42.927793 iDelay=208, Bit 2, Center 107 (24 ~ 191) 168
5164 01:02:42.931137 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5165 01:02:42.934840 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5166 01:02:42.937902 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5167 01:02:42.941048 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5168 01:02:42.944296 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5169 01:02:42.950794 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5170 01:02:42.954215 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5171 01:02:42.957842 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5172 01:02:42.961070 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5173 01:02:42.964126 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5174 01:02:42.967666 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5175 01:02:42.974198 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5176 01:02:42.977602 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5177 01:02:42.977691 ==
5178 01:02:42.980887 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 01:02:42.984299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 01:02:42.984386 ==
5181 01:02:42.984452 DQS Delay:
5182 01:02:42.987419 DQS0 = 0, DQS1 = 0
5183 01:02:42.987507 DQM Delay:
5184 01:02:42.990698 DQM0 = 107, DQM1 = 91
5185 01:02:42.990783 DQ Delay:
5186 01:02:42.994264 DQ0 =111, DQ1 =111, DQ2 =107, DQ3 =99
5187 01:02:42.997488 DQ4 =111, DQ5 =91, DQ6 =115, DQ7 =115
5188 01:02:43.000824 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5189 01:02:43.004099 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5190 01:02:43.004186
5191 01:02:43.004253
5192 01:02:43.004315 ==
5193 01:02:43.007370 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 01:02:43.013921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 01:02:43.014041 ==
5196 01:02:43.014109
5197 01:02:43.014171
5198 01:02:43.014231 TX Vref Scan disable
5199 01:02:43.018269 == TX Byte 0 ==
5200 01:02:43.020954 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5201 01:02:43.027713 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5202 01:02:43.027803 == TX Byte 1 ==
5203 01:02:43.031038 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5204 01:02:43.037658 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5205 01:02:43.037781 ==
5206 01:02:43.040712 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 01:02:43.043954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 01:02:43.044042 ==
5209 01:02:43.044109
5210 01:02:43.044170
5211 01:02:43.047384 TX Vref Scan disable
5212 01:02:43.047469 == TX Byte 0 ==
5213 01:02:43.053875 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5214 01:02:43.057721 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5215 01:02:43.057809 == TX Byte 1 ==
5216 01:02:43.063866 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5217 01:02:43.067255 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5218 01:02:43.067343
5219 01:02:43.067411 [DATLAT]
5220 01:02:43.070490 Freq=933, CH0 RK0
5221 01:02:43.070574
5222 01:02:43.070641 DATLAT Default: 0xd
5223 01:02:43.074118 0, 0xFFFF, sum = 0
5224 01:02:43.074204 1, 0xFFFF, sum = 0
5225 01:02:43.078170 2, 0xFFFF, sum = 0
5226 01:02:43.080754 3, 0xFFFF, sum = 0
5227 01:02:43.080914 4, 0xFFFF, sum = 0
5228 01:02:43.084047 5, 0xFFFF, sum = 0
5229 01:02:43.084216 6, 0xFFFF, sum = 0
5230 01:02:43.088002 7, 0xFFFF, sum = 0
5231 01:02:43.088165 8, 0xFFFF, sum = 0
5232 01:02:43.090729 9, 0xFFFF, sum = 0
5233 01:02:43.090891 10, 0x0, sum = 1
5234 01:02:43.093884 11, 0x0, sum = 2
5235 01:02:43.094054 12, 0x0, sum = 3
5236 01:02:43.094133 13, 0x0, sum = 4
5237 01:02:43.097434 best_step = 11
5238 01:02:43.097596
5239 01:02:43.097671 ==
5240 01:02:43.100646 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 01:02:43.104526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 01:02:43.104701 ==
5243 01:02:43.107201 RX Vref Scan: 1
5244 01:02:43.107376
5245 01:02:43.110668 RX Vref 0 -> 0, step: 1
5246 01:02:43.110850
5247 01:02:43.110941 RX Delay -53 -> 252, step: 4
5248 01:02:43.111027
5249 01:02:43.113894 Set Vref, RX VrefLevel [Byte0]: 59
5250 01:02:43.117307 [Byte1]: 50
5251 01:02:43.121702
5252 01:02:43.121905 Final RX Vref Byte 0 = 59 to rank0
5253 01:02:43.125113 Final RX Vref Byte 1 = 50 to rank0
5254 01:02:43.128366 Final RX Vref Byte 0 = 59 to rank1
5255 01:02:43.131585 Final RX Vref Byte 1 = 50 to rank1==
5256 01:02:43.135119 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 01:02:43.141731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 01:02:43.142047 ==
5259 01:02:43.142230 DQS Delay:
5260 01:02:43.142391 DQS0 = 0, DQS1 = 0
5261 01:02:43.145907 DQM Delay:
5262 01:02:43.146264 DQM0 = 108, DQM1 = 92
5263 01:02:43.148923 DQ Delay:
5264 01:02:43.151846 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5265 01:02:43.155176 DQ4 =106, DQ5 =100, DQ6 =118, DQ7 =114
5266 01:02:43.158459 DQ8 =88, DQ9 =78, DQ10 =92, DQ11 =90
5267 01:02:43.162540 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5268 01:02:43.163016
5269 01:02:43.163390
5270 01:02:43.168537 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5271 01:02:43.171802 CH0 RK0: MR19=505, MR18=2420
5272 01:02:43.178628 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5273 01:02:43.179189
5274 01:02:43.181715 ----->DramcWriteLeveling(PI) begin...
5275 01:02:43.182232 ==
5276 01:02:43.185213 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 01:02:43.188966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 01:02:43.189547 ==
5279 01:02:43.192067 Write leveling (Byte 0): 34 => 34
5280 01:02:43.195067 Write leveling (Byte 1): 31 => 31
5281 01:02:43.198679 DramcWriteLeveling(PI) end<-----
5282 01:02:43.199248
5283 01:02:43.199625 ==
5284 01:02:43.201920 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 01:02:43.208629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 01:02:43.209204 ==
5287 01:02:43.209586 [Gating] SW mode calibration
5288 01:02:43.218192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5289 01:02:43.221844 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5290 01:02:43.224965 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 01:02:43.231613 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 01:02:43.234453 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 01:02:43.237793 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 01:02:43.244666 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 01:02:43.247879 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 01:02:43.251683 0 14 24 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
5297 01:02:43.257634 0 14 28 | B1->B0 | 2e2e 2626 | 0 1 | (1 0) (0 0)
5298 01:02:43.261142 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 01:02:43.264696 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 01:02:43.271257 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 01:02:43.274491 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 01:02:43.277929 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 01:02:43.284568 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 01:02:43.287706 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5305 01:02:43.290887 0 15 28 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5306 01:02:43.298159 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 01:02:43.301044 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 01:02:43.304515 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 01:02:43.311469 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 01:02:43.314843 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 01:02:43.317645 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 01:02:43.324332 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5313 01:02:43.327835 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5314 01:02:43.330915 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 01:02:43.337451 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 01:02:43.340811 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 01:02:43.344666 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 01:02:43.351166 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 01:02:43.354385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 01:02:43.357478 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 01:02:43.360820 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 01:02:43.367588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 01:02:43.370751 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 01:02:43.374272 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 01:02:43.381066 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 01:02:43.384360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 01:02:43.387525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 01:02:43.394387 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 01:02:43.397707 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5330 01:02:43.400887 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 01:02:43.404529 Total UI for P1: 0, mck2ui 16
5332 01:02:43.407721 best dqsien dly found for B0: ( 1, 2, 28)
5333 01:02:43.410866 Total UI for P1: 0, mck2ui 16
5334 01:02:43.414096 best dqsien dly found for B1: ( 1, 2, 28)
5335 01:02:43.418184 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5336 01:02:43.420916 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5337 01:02:43.421472
5338 01:02:43.427484 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5339 01:02:43.430531 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 01:02:43.433926 [Gating] SW calibration Done
5341 01:02:43.434430 ==
5342 01:02:43.437469 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 01:02:43.440723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 01:02:43.441200 ==
5345 01:02:43.441580 RX Vref Scan: 0
5346 01:02:43.441935
5347 01:02:43.443837 RX Vref 0 -> 0, step: 1
5348 01:02:43.444308
5349 01:02:43.447600 RX Delay -80 -> 252, step: 8
5350 01:02:43.450826 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5351 01:02:43.453580 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5352 01:02:43.457461 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5353 01:02:43.463970 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5354 01:02:43.466995 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5355 01:02:43.470600 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5356 01:02:43.473741 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5357 01:02:43.477439 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5358 01:02:43.480270 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5359 01:02:43.487175 iDelay=208, Bit 9, Center 83 (0 ~ 167) 168
5360 01:02:43.490467 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5361 01:02:43.493877 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5362 01:02:43.497227 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5363 01:02:43.500358 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5364 01:02:43.503499 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5365 01:02:43.510833 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5366 01:02:43.511410 ==
5367 01:02:43.514009 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 01:02:43.517273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 01:02:43.517852 ==
5370 01:02:43.518272 DQS Delay:
5371 01:02:43.520464 DQS0 = 0, DQS1 = 0
5372 01:02:43.521041 DQM Delay:
5373 01:02:43.523741 DQM0 = 104, DQM1 = 92
5374 01:02:43.524316 DQ Delay:
5375 01:02:43.526668 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5376 01:02:43.530452 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5377 01:02:43.533367 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =91
5378 01:02:43.536526 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5379 01:02:43.537001
5380 01:02:43.537374
5381 01:02:43.537719 ==
5382 01:02:43.539787 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 01:02:43.546554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 01:02:43.547132 ==
5385 01:02:43.547515
5386 01:02:43.547863
5387 01:02:43.548197 TX Vref Scan disable
5388 01:02:43.550346 == TX Byte 0 ==
5389 01:02:43.553433 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5390 01:02:43.560518 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5391 01:02:43.561142 == TX Byte 1 ==
5392 01:02:43.563452 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5393 01:02:43.569913 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5394 01:02:43.570523 ==
5395 01:02:43.573648 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 01:02:43.576923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 01:02:43.577498 ==
5398 01:02:43.577880
5399 01:02:43.578285
5400 01:02:43.581180 TX Vref Scan disable
5401 01:02:43.581652 == TX Byte 0 ==
5402 01:02:43.586631 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5403 01:02:43.589814 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5404 01:02:43.590321 == TX Byte 1 ==
5405 01:02:43.596721 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5406 01:02:43.600876 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5407 01:02:43.601462
5408 01:02:43.601928 [DATLAT]
5409 01:02:43.603506 Freq=933, CH0 RK1
5410 01:02:43.604030
5411 01:02:43.604458 DATLAT Default: 0xb
5412 01:02:43.606855 0, 0xFFFF, sum = 0
5413 01:02:43.607442 1, 0xFFFF, sum = 0
5414 01:02:43.609855 2, 0xFFFF, sum = 0
5415 01:02:43.610479 3, 0xFFFF, sum = 0
5416 01:02:43.613810 4, 0xFFFF, sum = 0
5417 01:02:43.614440 5, 0xFFFF, sum = 0
5418 01:02:43.616888 6, 0xFFFF, sum = 0
5419 01:02:43.617476 7, 0xFFFF, sum = 0
5420 01:02:43.620143 8, 0xFFFF, sum = 0
5421 01:02:43.623359 9, 0xFFFF, sum = 0
5422 01:02:43.623944 10, 0x0, sum = 1
5423 01:02:43.624340 11, 0x0, sum = 2
5424 01:02:43.626519 12, 0x0, sum = 3
5425 01:02:43.627004 13, 0x0, sum = 4
5426 01:02:43.630074 best_step = 11
5427 01:02:43.630648
5428 01:02:43.631029 ==
5429 01:02:43.633720 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 01:02:43.636654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 01:02:43.637138 ==
5432 01:02:43.640053 RX Vref Scan: 0
5433 01:02:43.640631
5434 01:02:43.641123 RX Vref 0 -> 0, step: 1
5435 01:02:43.643083
5436 01:02:43.643656 RX Delay -45 -> 252, step: 4
5437 01:02:43.650831 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5438 01:02:43.654048 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5439 01:02:43.657141 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5440 01:02:43.661031 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5441 01:02:43.663702 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5442 01:02:43.670784 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5443 01:02:43.674167 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5444 01:02:43.677666 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5445 01:02:43.680311 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5446 01:02:43.684254 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5447 01:02:43.686891 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5448 01:02:43.694030 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5449 01:02:43.696883 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5450 01:02:43.700446 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5451 01:02:43.703564 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5452 01:02:43.707022 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5453 01:02:43.710314 ==
5454 01:02:43.713747 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 01:02:43.717353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 01:02:43.717989 ==
5457 01:02:43.718390 DQS Delay:
5458 01:02:43.720587 DQS0 = 0, DQS1 = 0
5459 01:02:43.721059 DQM Delay:
5460 01:02:43.723813 DQM0 = 103, DQM1 = 92
5461 01:02:43.724395 DQ Delay:
5462 01:02:43.726804 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5463 01:02:43.730432 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5464 01:02:43.733599 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5465 01:02:43.737102 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5466 01:02:43.737686
5467 01:02:43.738117
5468 01:02:43.746981 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5469 01:02:43.747570 CH0 RK1: MR19=505, MR18=2B0C
5470 01:02:43.753403 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5471 01:02:43.757048 [RxdqsGatingPostProcess] freq 933
5472 01:02:43.763199 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5473 01:02:43.766636 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 01:02:43.770050 best DQS1 dly(2T, 0.5T) = (0, 11)
5475 01:02:43.773055 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 01:02:43.776712 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5477 01:02:43.779899 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 01:02:43.780483 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 01:02:43.783063 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 01:02:43.786528 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 01:02:43.789662 Pre-setting of DQS Precalculation
5482 01:02:43.796644 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5483 01:02:43.797228 ==
5484 01:02:43.799968 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 01:02:43.803087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 01:02:43.803674 ==
5487 01:02:43.809695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5488 01:02:43.816491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5489 01:02:43.819851 [CA 0] Center 37 (7~67) winsize 61
5490 01:02:43.822782 [CA 1] Center 37 (7~68) winsize 62
5491 01:02:43.826662 [CA 2] Center 35 (5~65) winsize 61
5492 01:02:43.829936 [CA 3] Center 34 (4~65) winsize 62
5493 01:02:43.832819 [CA 4] Center 34 (4~65) winsize 62
5494 01:02:43.836068 [CA 5] Center 33 (3~64) winsize 62
5495 01:02:43.836648
5496 01:02:43.839302 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5497 01:02:43.839883
5498 01:02:43.842530 [CATrainingPosCal] consider 1 rank data
5499 01:02:43.846107 u2DelayCellTimex100 = 270/100 ps
5500 01:02:43.849605 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5501 01:02:43.852852 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5502 01:02:43.856192 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5503 01:02:43.859276 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 01:02:43.863017 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 01:02:43.866006 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5506 01:02:43.866482
5507 01:02:43.872491 CA PerBit enable=1, Macro0, CA PI delay=33
5508 01:02:43.873017
5509 01:02:43.876051 [CBTSetCACLKResult] CA Dly = 33
5510 01:02:43.876631 CS Dly: 5 (0~36)
5511 01:02:43.877017 ==
5512 01:02:43.879163 Dram Type= 6, Freq= 0, CH_1, rank 1
5513 01:02:43.882414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 01:02:43.882995 ==
5515 01:02:43.889402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 01:02:43.895462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 01:02:43.898845 [CA 0] Center 37 (7~68) winsize 62
5518 01:02:43.902063 [CA 1] Center 37 (6~68) winsize 63
5519 01:02:43.905457 [CA 2] Center 35 (4~66) winsize 63
5520 01:02:43.908827 [CA 3] Center 34 (4~65) winsize 62
5521 01:02:43.911958 [CA 4] Center 34 (4~65) winsize 62
5522 01:02:43.915454 [CA 5] Center 34 (4~64) winsize 61
5523 01:02:43.916072
5524 01:02:43.918768 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 01:02:43.919250
5526 01:02:43.922101 [CATrainingPosCal] consider 2 rank data
5527 01:02:43.925485 u2DelayCellTimex100 = 270/100 ps
5528 01:02:43.928574 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5529 01:02:43.932094 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5530 01:02:43.935207 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5531 01:02:43.938428 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5532 01:02:43.943302 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5533 01:02:43.948700 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5534 01:02:43.949280
5535 01:02:43.952254 CA PerBit enable=1, Macro0, CA PI delay=34
5536 01:02:43.952833
5537 01:02:43.955267 [CBTSetCACLKResult] CA Dly = 34
5538 01:02:43.955850 CS Dly: 6 (0~38)
5539 01:02:43.956235
5540 01:02:43.958793 ----->DramcWriteLeveling(PI) begin...
5541 01:02:43.959379 ==
5542 01:02:43.962295 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 01:02:43.965210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 01:02:43.968382 ==
5545 01:02:43.968862 Write leveling (Byte 0): 29 => 29
5546 01:02:43.971963 Write leveling (Byte 1): 29 => 29
5547 01:02:43.975142 DramcWriteLeveling(PI) end<-----
5548 01:02:43.975621
5549 01:02:43.975996 ==
5550 01:02:43.978731 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 01:02:43.985111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 01:02:43.985596 ==
5553 01:02:43.988353 [Gating] SW mode calibration
5554 01:02:43.995260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5555 01:02:43.998421 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5556 01:02:44.005226 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 01:02:44.008459 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 01:02:44.013413 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 01:02:44.015090 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 01:02:44.021838 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 01:02:44.024964 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5562 01:02:44.028996 0 14 24 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
5563 01:02:44.035191 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5564 01:02:44.038410 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 01:02:44.042382 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 01:02:44.048640 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 01:02:44.051987 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 01:02:44.055091 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 01:02:44.061885 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 01:02:44.064704 0 15 24 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
5571 01:02:44.068360 0 15 28 | B1->B0 | 3b3b 4242 | 1 0 | (0 0) (0 0)
5572 01:02:44.075208 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 01:02:44.078327 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 01:02:44.081788 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 01:02:44.088255 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 01:02:44.091571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 01:02:44.094607 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 01:02:44.101721 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5579 01:02:44.104415 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 01:02:44.108141 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 01:02:44.114762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 01:02:44.117841 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 01:02:44.121335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 01:02:44.127972 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 01:02:44.131250 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 01:02:44.134661 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 01:02:44.141182 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 01:02:44.144667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 01:02:44.147971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 01:02:44.154156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 01:02:44.157741 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 01:02:44.161818 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 01:02:44.164491 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5594 01:02:44.171401 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5595 01:02:44.174267 Total UI for P1: 0, mck2ui 16
5596 01:02:44.177622 best dqsien dly found for B0: ( 1, 2, 20)
5597 01:02:44.181473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 01:02:44.184578 Total UI for P1: 0, mck2ui 16
5599 01:02:44.187750 best dqsien dly found for B1: ( 1, 2, 24)
5600 01:02:44.190885 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5601 01:02:44.194304 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5602 01:02:44.194673
5603 01:02:44.197917 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5604 01:02:44.204611 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5605 01:02:44.205181 [Gating] SW calibration Done
5606 01:02:44.205560 ==
5607 01:02:44.208181 Dram Type= 6, Freq= 0, CH_1, rank 0
5608 01:02:44.214095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 01:02:44.214661 ==
5610 01:02:44.215044 RX Vref Scan: 0
5611 01:02:44.215397
5612 01:02:44.217899 RX Vref 0 -> 0, step: 1
5613 01:02:44.218501
5614 01:02:44.221301 RX Delay -80 -> 252, step: 8
5615 01:02:44.224269 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5616 01:02:44.227427 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5617 01:02:44.231235 iDelay=208, Bit 2, Center 99 (16 ~ 183) 168
5618 01:02:44.234469 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5619 01:02:44.240716 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5620 01:02:44.244156 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5621 01:02:44.247680 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5622 01:02:44.250789 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5623 01:02:44.254283 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5624 01:02:44.260662 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5625 01:02:44.263749 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5626 01:02:44.267375 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5627 01:02:44.270610 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5628 01:02:44.273992 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5629 01:02:44.280377 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5630 01:02:44.284084 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5631 01:02:44.284649 ==
5632 01:02:44.287255 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 01:02:44.290749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 01:02:44.291223 ==
5635 01:02:44.293627 DQS Delay:
5636 01:02:44.294127 DQS0 = 0, DQS1 = 0
5637 01:02:44.294503 DQM Delay:
5638 01:02:44.296863 DQM0 = 105, DQM1 = 99
5639 01:02:44.297331 DQ Delay:
5640 01:02:44.300311 DQ0 =107, DQ1 =99, DQ2 =99, DQ3 =103
5641 01:02:44.304054 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5642 01:02:44.307343 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5643 01:02:44.310559 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5644 01:02:44.311032
5645 01:02:44.314261
5646 01:02:44.314825 ==
5647 01:02:44.317235 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 01:02:44.320680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 01:02:44.321253 ==
5650 01:02:44.321630
5651 01:02:44.322011
5652 01:02:44.323826 TX Vref Scan disable
5653 01:02:44.324389 == TX Byte 0 ==
5654 01:02:44.330303 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5655 01:02:44.333853 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5656 01:02:44.334485 == TX Byte 1 ==
5657 01:02:44.340450 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5658 01:02:44.343885 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5659 01:02:44.344364 ==
5660 01:02:44.347270 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 01:02:44.350600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 01:02:44.351185 ==
5663 01:02:44.351563
5664 01:02:44.352018
5665 01:02:44.353479 TX Vref Scan disable
5666 01:02:44.356719 == TX Byte 0 ==
5667 01:02:44.360512 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5668 01:02:44.363409 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5669 01:02:44.366808 == TX Byte 1 ==
5670 01:02:44.370025 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 01:02:44.373396 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 01:02:44.374093
5673 01:02:44.377331 [DATLAT]
5674 01:02:44.377896 Freq=933, CH1 RK0
5675 01:02:44.378332
5676 01:02:44.380559 DATLAT Default: 0xd
5677 01:02:44.381127 0, 0xFFFF, sum = 0
5678 01:02:44.383694 1, 0xFFFF, sum = 0
5679 01:02:44.384269 2, 0xFFFF, sum = 0
5680 01:02:44.387368 3, 0xFFFF, sum = 0
5681 01:02:44.387941 4, 0xFFFF, sum = 0
5682 01:02:44.389959 5, 0xFFFF, sum = 0
5683 01:02:44.390448 6, 0xFFFF, sum = 0
5684 01:02:44.393249 7, 0xFFFF, sum = 0
5685 01:02:44.393823 8, 0xFFFF, sum = 0
5686 01:02:44.396970 9, 0xFFFF, sum = 0
5687 01:02:44.397529 10, 0x0, sum = 1
5688 01:02:44.399947 11, 0x0, sum = 2
5689 01:02:44.400423 12, 0x0, sum = 3
5690 01:02:44.403389 13, 0x0, sum = 4
5691 01:02:44.403866 best_step = 11
5692 01:02:44.404235
5693 01:02:44.404578 ==
5694 01:02:44.407174 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 01:02:44.413062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 01:02:44.413538 ==
5697 01:02:44.413916 RX Vref Scan: 1
5698 01:02:44.414298
5699 01:02:44.416556 RX Vref 0 -> 0, step: 1
5700 01:02:44.417025
5701 01:02:44.420169 RX Delay -45 -> 252, step: 4
5702 01:02:44.420640
5703 01:02:44.423223 Set Vref, RX VrefLevel [Byte0]: 52
5704 01:02:44.426426 [Byte1]: 52
5705 01:02:44.426895
5706 01:02:44.429843 Final RX Vref Byte 0 = 52 to rank0
5707 01:02:44.433048 Final RX Vref Byte 1 = 52 to rank0
5708 01:02:44.436452 Final RX Vref Byte 0 = 52 to rank1
5709 01:02:44.439509 Final RX Vref Byte 1 = 52 to rank1==
5710 01:02:44.443137 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 01:02:44.446044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 01:02:44.446248 ==
5713 01:02:44.450386 DQS Delay:
5714 01:02:44.450523 DQS0 = 0, DQS1 = 0
5715 01:02:44.450633 DQM Delay:
5716 01:02:44.452948 DQM0 = 108, DQM1 = 101
5717 01:02:44.453086 DQ Delay:
5718 01:02:44.455969 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =108
5719 01:02:44.459309 DQ4 =108, DQ5 =116, DQ6 =116, DQ7 =104
5720 01:02:44.462430 DQ8 =90, DQ9 =90, DQ10 =104, DQ11 =94
5721 01:02:44.469076 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108
5722 01:02:44.469168
5723 01:02:44.469238
5724 01:02:44.475833 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5725 01:02:44.479131 CH1 RK0: MR19=505, MR18=1C35
5726 01:02:44.486115 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5727 01:02:44.486202
5728 01:02:44.489309 ----->DramcWriteLeveling(PI) begin...
5729 01:02:44.489395 ==
5730 01:02:44.492562 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 01:02:44.495801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 01:02:44.495890 ==
5733 01:02:44.498991 Write leveling (Byte 0): 29 => 29
5734 01:02:44.502435 Write leveling (Byte 1): 28 => 28
5735 01:02:44.505793 DramcWriteLeveling(PI) end<-----
5736 01:02:44.505876
5737 01:02:44.505947 ==
5738 01:02:44.509228 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 01:02:44.512188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 01:02:44.512272 ==
5741 01:02:44.516169 [Gating] SW mode calibration
5742 01:02:44.522505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5743 01:02:44.528918 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5744 01:02:44.532087 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5745 01:02:44.539019 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 01:02:44.542124 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 01:02:44.545506 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 01:02:44.549043 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 01:02:44.555460 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 01:02:44.558830 0 14 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 0)
5751 01:02:44.562664 0 14 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 0)
5752 01:02:44.568661 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 01:02:44.572231 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 01:02:44.575871 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 01:02:44.582280 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 01:02:44.585506 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 01:02:44.588872 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 01:02:44.595594 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5759 01:02:44.598940 0 15 28 | B1->B0 | 3c3c 3232 | 0 0 | (0 0) (0 0)
5760 01:02:44.601880 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 01:02:44.608616 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 01:02:44.612008 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 01:02:44.615262 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 01:02:44.621817 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 01:02:44.624992 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 01:02:44.628587 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5767 01:02:44.635477 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5768 01:02:44.638471 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 01:02:44.641887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 01:02:44.648427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 01:02:44.651705 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 01:02:44.654874 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 01:02:44.661460 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 01:02:44.664929 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 01:02:44.668148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 01:02:44.674684 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 01:02:44.677942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 01:02:44.681648 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 01:02:44.688169 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 01:02:44.691177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 01:02:44.694658 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 01:02:44.701278 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 01:02:44.704392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5784 01:02:44.707964 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 01:02:44.711044 Total UI for P1: 0, mck2ui 16
5786 01:02:44.714417 best dqsien dly found for B0: ( 1, 2, 28)
5787 01:02:44.718111 Total UI for P1: 0, mck2ui 16
5788 01:02:44.721151 best dqsien dly found for B1: ( 1, 2, 28)
5789 01:02:44.724427 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5790 01:02:44.727630 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5791 01:02:44.727715
5792 01:02:44.731159 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5793 01:02:44.737634 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5794 01:02:44.737731 [Gating] SW calibration Done
5795 01:02:44.737799 ==
5796 01:02:44.741208 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 01:02:44.747654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 01:02:44.747751 ==
5799 01:02:44.747819 RX Vref Scan: 0
5800 01:02:44.747880
5801 01:02:44.751242 RX Vref 0 -> 0, step: 1
5802 01:02:44.751327
5803 01:02:44.754085 RX Delay -80 -> 252, step: 8
5804 01:02:44.757508 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5805 01:02:44.760998 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5806 01:02:44.764036 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5807 01:02:44.770781 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5808 01:02:44.774116 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5809 01:02:44.777407 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5810 01:02:44.781134 iDelay=200, Bit 6, Center 115 (32 ~ 199) 168
5811 01:02:44.784017 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5812 01:02:44.787261 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5813 01:02:44.794229 iDelay=200, Bit 9, Center 91 (8 ~ 175) 168
5814 01:02:44.797308 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5815 01:02:44.800817 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5816 01:02:44.804279 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5817 01:02:44.807239 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5818 01:02:44.814115 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5819 01:02:44.817190 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5820 01:02:44.817276 ==
5821 01:02:44.820581 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 01:02:44.824074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 01:02:44.824159 ==
5824 01:02:44.824225 DQS Delay:
5825 01:02:44.827242 DQS0 = 0, DQS1 = 0
5826 01:02:44.827326 DQM Delay:
5827 01:02:44.830616 DQM0 = 105, DQM1 = 97
5828 01:02:44.830701 DQ Delay:
5829 01:02:44.833868 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =103
5830 01:02:44.837513 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =103
5831 01:02:44.840696 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =95
5832 01:02:44.843980 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =107
5833 01:02:44.844065
5834 01:02:44.844131
5835 01:02:44.844191 ==
5836 01:02:44.847339 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 01:02:44.854129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 01:02:44.854214 ==
5839 01:02:44.854281
5840 01:02:44.854342
5841 01:02:44.857058 TX Vref Scan disable
5842 01:02:44.857142 == TX Byte 0 ==
5843 01:02:44.860524 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5844 01:02:44.866995 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5845 01:02:44.867081 == TX Byte 1 ==
5846 01:02:44.870369 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5847 01:02:44.876933 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5848 01:02:44.877025 ==
5849 01:02:44.880237 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 01:02:44.884086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 01:02:44.884171 ==
5852 01:02:44.884238
5853 01:02:44.884299
5854 01:02:44.886844 TX Vref Scan disable
5855 01:02:44.890585 == TX Byte 0 ==
5856 01:02:44.893478 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5857 01:02:44.897168 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5858 01:02:44.900108 == TX Byte 1 ==
5859 01:02:44.903525 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 01:02:44.906823 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 01:02:44.906908
5862 01:02:44.906975 [DATLAT]
5863 01:02:44.910168 Freq=933, CH1 RK1
5864 01:02:44.910253
5865 01:02:44.913304 DATLAT Default: 0xb
5866 01:02:44.913388 0, 0xFFFF, sum = 0
5867 01:02:44.917082 1, 0xFFFF, sum = 0
5868 01:02:44.917168 2, 0xFFFF, sum = 0
5869 01:02:44.920198 3, 0xFFFF, sum = 0
5870 01:02:44.920284 4, 0xFFFF, sum = 0
5871 01:02:44.923339 5, 0xFFFF, sum = 0
5872 01:02:44.923424 6, 0xFFFF, sum = 0
5873 01:02:44.926534 7, 0xFFFF, sum = 0
5874 01:02:44.926619 8, 0xFFFF, sum = 0
5875 01:02:44.929980 9, 0xFFFF, sum = 0
5876 01:02:44.930065 10, 0x0, sum = 1
5877 01:02:44.933436 11, 0x0, sum = 2
5878 01:02:44.933522 12, 0x0, sum = 3
5879 01:02:44.936841 13, 0x0, sum = 4
5880 01:02:44.936927 best_step = 11
5881 01:02:44.936993
5882 01:02:44.937054 ==
5883 01:02:44.939851 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 01:02:44.943363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 01:02:44.946864 ==
5886 01:02:44.946949 RX Vref Scan: 0
5887 01:02:44.947016
5888 01:02:44.949822 RX Vref 0 -> 0, step: 1
5889 01:02:44.949906
5890 01:02:44.949981 RX Delay -53 -> 252, step: 4
5891 01:02:44.958338 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5892 01:02:44.961675 iDelay=199, Bit 1, Center 102 (27 ~ 178) 152
5893 01:02:44.964768 iDelay=199, Bit 2, Center 98 (23 ~ 174) 152
5894 01:02:44.967961 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5895 01:02:44.971220 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5896 01:02:44.977872 iDelay=199, Bit 5, Center 120 (43 ~ 198) 156
5897 01:02:44.981223 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5898 01:02:44.984931 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5899 01:02:44.987752 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5900 01:02:44.991192 iDelay=199, Bit 9, Center 92 (15 ~ 170) 156
5901 01:02:44.997908 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5902 01:02:45.001523 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5903 01:02:45.004397 iDelay=199, Bit 12, Center 110 (31 ~ 190) 160
5904 01:02:45.007856 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5905 01:02:45.011052 iDelay=199, Bit 14, Center 108 (23 ~ 194) 172
5906 01:02:45.017722 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5907 01:02:45.017810 ==
5908 01:02:45.021060 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 01:02:45.024274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 01:02:45.024360 ==
5911 01:02:45.024428 DQS Delay:
5912 01:02:45.027805 DQS0 = 0, DQS1 = 0
5913 01:02:45.027890 DQM Delay:
5914 01:02:45.031011 DQM0 = 108, DQM1 = 101
5915 01:02:45.031096 DQ Delay:
5916 01:02:45.034595 DQ0 =112, DQ1 =102, DQ2 =98, DQ3 =106
5917 01:02:45.037699 DQ4 =108, DQ5 =120, DQ6 =114, DQ7 =106
5918 01:02:45.041399 DQ8 =88, DQ9 =92, DQ10 =100, DQ11 =96
5919 01:02:45.044160 DQ12 =110, DQ13 =106, DQ14 =108, DQ15 =110
5920 01:02:45.044245
5921 01:02:45.044312
5922 01:02:45.053977 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5923 01:02:45.057460 CH1 RK1: MR19=504, MR18=20FC
5924 01:02:45.060654 CH1_RK1: MR19=0x504, MR18=0x20FC, DQSOSC=411, MR23=63, INC=64, DEC=42
5925 01:02:45.064023 [RxdqsGatingPostProcess] freq 933
5926 01:02:45.071243 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5927 01:02:45.074131 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 01:02:45.077522 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 01:02:45.080539 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 01:02:45.084111 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 01:02:45.087289 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 01:02:45.090574 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 01:02:45.094181 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 01:02:45.097295 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 01:02:45.100833 Pre-setting of DQS Precalculation
5936 01:02:45.104691 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5937 01:02:45.110622 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5938 01:02:45.117005 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5939 01:02:45.117093
5940 01:02:45.120361
5941 01:02:45.120446 [Calibration Summary] 1866 Mbps
5942 01:02:45.123672 CH 0, Rank 0
5943 01:02:45.123757 SW Impedance : PASS
5944 01:02:45.127018 DUTY Scan : NO K
5945 01:02:45.130624 ZQ Calibration : PASS
5946 01:02:45.130709 Jitter Meter : NO K
5947 01:02:45.134071 CBT Training : PASS
5948 01:02:45.136972 Write leveling : PASS
5949 01:02:45.137056 RX DQS gating : PASS
5950 01:02:45.140242 RX DQ/DQS(RDDQC) : PASS
5951 01:02:45.143680 TX DQ/DQS : PASS
5952 01:02:45.143766 RX DATLAT : PASS
5953 01:02:45.147009 RX DQ/DQS(Engine): PASS
5954 01:02:45.150836 TX OE : NO K
5955 01:02:45.150921 All Pass.
5956 01:02:45.150987
5957 01:02:45.151071 CH 0, Rank 1
5958 01:02:45.153603 SW Impedance : PASS
5959 01:02:45.156947 DUTY Scan : NO K
5960 01:02:45.157030 ZQ Calibration : PASS
5961 01:02:45.160877 Jitter Meter : NO K
5962 01:02:45.160959 CBT Training : PASS
5963 01:02:45.163649 Write leveling : PASS
5964 01:02:45.166984 RX DQS gating : PASS
5965 01:02:45.167066 RX DQ/DQS(RDDQC) : PASS
5966 01:02:45.170217 TX DQ/DQS : PASS
5967 01:02:45.173465 RX DATLAT : PASS
5968 01:02:45.173547 RX DQ/DQS(Engine): PASS
5969 01:02:45.176961 TX OE : NO K
5970 01:02:45.177044 All Pass.
5971 01:02:45.177110
5972 01:02:45.180177 CH 1, Rank 0
5973 01:02:45.180259 SW Impedance : PASS
5974 01:02:45.183209 DUTY Scan : NO K
5975 01:02:45.186620 ZQ Calibration : PASS
5976 01:02:45.186703 Jitter Meter : NO K
5977 01:02:45.190140 CBT Training : PASS
5978 01:02:45.193409 Write leveling : PASS
5979 01:02:45.193492 RX DQS gating : PASS
5980 01:02:45.196865 RX DQ/DQS(RDDQC) : PASS
5981 01:02:45.200196 TX DQ/DQS : PASS
5982 01:02:45.200280 RX DATLAT : PASS
5983 01:02:45.203371 RX DQ/DQS(Engine): PASS
5984 01:02:45.206801 TX OE : NO K
5985 01:02:45.206884 All Pass.
5986 01:02:45.206950
5987 01:02:45.207010 CH 1, Rank 1
5988 01:02:45.209793 SW Impedance : PASS
5989 01:02:45.213251 DUTY Scan : NO K
5990 01:02:45.213334 ZQ Calibration : PASS
5991 01:02:45.216910 Jitter Meter : NO K
5992 01:02:45.220175 CBT Training : PASS
5993 01:02:45.220258 Write leveling : PASS
5994 01:02:45.223089 RX DQS gating : PASS
5995 01:02:45.223172 RX DQ/DQS(RDDQC) : PASS
5996 01:02:45.226382 TX DQ/DQS : PASS
5997 01:02:45.229782 RX DATLAT : PASS
5998 01:02:45.229895 RX DQ/DQS(Engine): PASS
5999 01:02:45.233299 TX OE : NO K
6000 01:02:45.233382 All Pass.
6001 01:02:45.233447
6002 01:02:45.236951 DramC Write-DBI off
6003 01:02:45.239731 PER_BANK_REFRESH: Hybrid Mode
6004 01:02:45.239819 TX_TRACKING: ON
6005 01:02:45.250045 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6006 01:02:45.253035 [FAST_K] Save calibration result to emmc
6007 01:02:45.256509 dramc_set_vcore_voltage set vcore to 650000
6008 01:02:45.260049 Read voltage for 400, 6
6009 01:02:45.260133 Vio18 = 0
6010 01:02:45.260199 Vcore = 650000
6011 01:02:45.263092 Vdram = 0
6012 01:02:45.263175 Vddq = 0
6013 01:02:45.263241 Vmddr = 0
6014 01:02:45.269604 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6015 01:02:45.273068 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6016 01:02:45.276262 MEM_TYPE=3, freq_sel=20
6017 01:02:45.279885 sv_algorithm_assistance_LP4_800
6018 01:02:45.283039 ============ PULL DRAM RESETB DOWN ============
6019 01:02:45.286222 ========== PULL DRAM RESETB DOWN end =========
6020 01:02:45.292712 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6021 01:02:45.296131 ===================================
6022 01:02:45.299603 LPDDR4 DRAM CONFIGURATION
6023 01:02:45.302665 ===================================
6024 01:02:45.302750 EX_ROW_EN[0] = 0x0
6025 01:02:45.305969 EX_ROW_EN[1] = 0x0
6026 01:02:45.306053 LP4Y_EN = 0x0
6027 01:02:45.309440 WORK_FSP = 0x0
6028 01:02:45.309523 WL = 0x2
6029 01:02:45.312561 RL = 0x2
6030 01:02:45.312643 BL = 0x2
6031 01:02:45.316184 RPST = 0x0
6032 01:02:45.316267 RD_PRE = 0x0
6033 01:02:45.319318 WR_PRE = 0x1
6034 01:02:45.319400 WR_PST = 0x0
6035 01:02:45.322578 DBI_WR = 0x0
6036 01:02:45.322661 DBI_RD = 0x0
6037 01:02:45.325916 OTF = 0x1
6038 01:02:45.329182 ===================================
6039 01:02:45.332776 ===================================
6040 01:02:45.332860 ANA top config
6041 01:02:45.335939 ===================================
6042 01:02:45.339446 DLL_ASYNC_EN = 0
6043 01:02:45.342618 ALL_SLAVE_EN = 1
6044 01:02:45.346100 NEW_RANK_MODE = 1
6045 01:02:45.349307 DLL_IDLE_MODE = 1
6046 01:02:45.349399 LP45_APHY_COMB_EN = 1
6047 01:02:45.352481 TX_ODT_DIS = 1
6048 01:02:45.355865 NEW_8X_MODE = 1
6049 01:02:45.359205 ===================================
6050 01:02:45.362492 ===================================
6051 01:02:45.365580 data_rate = 800
6052 01:02:45.368845 CKR = 1
6053 01:02:45.368929 DQ_P2S_RATIO = 4
6054 01:02:45.372393 ===================================
6055 01:02:45.375561 CA_P2S_RATIO = 4
6056 01:02:45.378832 DQ_CA_OPEN = 0
6057 01:02:45.382079 DQ_SEMI_OPEN = 1
6058 01:02:45.385584 CA_SEMI_OPEN = 1
6059 01:02:45.389718 CA_FULL_RATE = 0
6060 01:02:45.389802 DQ_CKDIV4_EN = 0
6061 01:02:45.392022 CA_CKDIV4_EN = 1
6062 01:02:45.395372 CA_PREDIV_EN = 0
6063 01:02:45.398721 PH8_DLY = 0
6064 01:02:45.402213 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6065 01:02:45.405336 DQ_AAMCK_DIV = 0
6066 01:02:45.405420 CA_AAMCK_DIV = 0
6067 01:02:45.408793 CA_ADMCK_DIV = 4
6068 01:02:45.411926 DQ_TRACK_CA_EN = 0
6069 01:02:45.415643 CA_PICK = 800
6070 01:02:45.418954 CA_MCKIO = 400
6071 01:02:45.421927 MCKIO_SEMI = 400
6072 01:02:45.425157 PLL_FREQ = 3016
6073 01:02:45.425241 DQ_UI_PI_RATIO = 32
6074 01:02:45.428497 CA_UI_PI_RATIO = 32
6075 01:02:45.431987 ===================================
6076 01:02:45.435262 ===================================
6077 01:02:45.438499 memory_type:LPDDR4
6078 01:02:45.441924 GP_NUM : 10
6079 01:02:45.442040 SRAM_EN : 1
6080 01:02:45.445001 MD32_EN : 0
6081 01:02:45.448510 ===================================
6082 01:02:45.451679 [ANA_INIT] >>>>>>>>>>>>>>
6083 01:02:45.455497 <<<<<< [CONFIGURE PHASE]: ANA_TX
6084 01:02:45.458322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6085 01:02:45.462157 ===================================
6086 01:02:45.462241 data_rate = 800,PCW = 0X7400
6087 01:02:45.465247 ===================================
6088 01:02:45.468401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6089 01:02:45.475075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 01:02:45.485392 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 01:02:45.491912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6092 01:02:45.495183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6093 01:02:45.498153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6094 01:02:45.501866 [ANA_INIT] flow start
6095 01:02:45.501979 [ANA_INIT] PLL >>>>>>>>
6096 01:02:45.505038 [ANA_INIT] PLL <<<<<<<<
6097 01:02:45.508497 [ANA_INIT] MIDPI >>>>>>>>
6098 01:02:45.508581 [ANA_INIT] MIDPI <<<<<<<<
6099 01:02:45.511892 [ANA_INIT] DLL >>>>>>>>
6100 01:02:45.514882 [ANA_INIT] flow end
6101 01:02:45.518476 ============ LP4 DIFF to SE enter ============
6102 01:02:45.521527 ============ LP4 DIFF to SE exit ============
6103 01:02:45.525266 [ANA_INIT] <<<<<<<<<<<<<
6104 01:02:45.528180 [Flow] Enable top DCM control >>>>>
6105 01:02:45.531559 [Flow] Enable top DCM control <<<<<
6106 01:02:45.535134 Enable DLL master slave shuffle
6107 01:02:45.538116 ==============================================================
6108 01:02:45.541386 Gating Mode config
6109 01:02:45.545055 ==============================================================
6110 01:02:45.548241 Config description:
6111 01:02:45.558152 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6112 01:02:45.564687 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6113 01:02:45.568061 SELPH_MODE 0: By rank 1: By Phase
6114 01:02:45.574513 ==============================================================
6115 01:02:45.577868 GAT_TRACK_EN = 0
6116 01:02:45.581552 RX_GATING_MODE = 2
6117 01:02:45.584436 RX_GATING_TRACK_MODE = 2
6118 01:02:45.587993 SELPH_MODE = 1
6119 01:02:45.591208 PICG_EARLY_EN = 1
6120 01:02:45.595057 VALID_LAT_VALUE = 1
6121 01:02:45.597850 ==============================================================
6122 01:02:45.601055 Enter into Gating configuration >>>>
6123 01:02:45.604478 Exit from Gating configuration <<<<
6124 01:02:45.607935 Enter into DVFS_PRE_config >>>>>
6125 01:02:45.617973 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6126 01:02:45.621216 Exit from DVFS_PRE_config <<<<<
6127 01:02:45.624684 Enter into PICG configuration >>>>
6128 01:02:45.627535 Exit from PICG configuration <<<<
6129 01:02:45.631241 [RX_INPUT] configuration >>>>>
6130 01:02:45.634451 [RX_INPUT] configuration <<<<<
6131 01:02:45.641009 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6132 01:02:45.644008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6133 01:02:45.650770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6134 01:02:45.657646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6135 01:02:45.664009 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 01:02:45.670454 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 01:02:45.674115 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6138 01:02:45.677326 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6139 01:02:45.680424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6140 01:02:45.687566 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6141 01:02:45.690679 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6142 01:02:45.694119 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6143 01:02:45.697334 ===================================
6144 01:02:45.700484 LPDDR4 DRAM CONFIGURATION
6145 01:02:45.703948 ===================================
6146 01:02:45.704032 EX_ROW_EN[0] = 0x0
6147 01:02:45.706967 EX_ROW_EN[1] = 0x0
6148 01:02:45.710421 LP4Y_EN = 0x0
6149 01:02:45.710504 WORK_FSP = 0x0
6150 01:02:45.713628 WL = 0x2
6151 01:02:45.713711 RL = 0x2
6152 01:02:45.717392 BL = 0x2
6153 01:02:45.717476 RPST = 0x0
6154 01:02:45.720364 RD_PRE = 0x0
6155 01:02:45.720447 WR_PRE = 0x1
6156 01:02:45.723639 WR_PST = 0x0
6157 01:02:45.723722 DBI_WR = 0x0
6158 01:02:45.726864 DBI_RD = 0x0
6159 01:02:45.726946 OTF = 0x1
6160 01:02:45.730318 ===================================
6161 01:02:45.733936 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6162 01:02:45.740045 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6163 01:02:45.743846 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 01:02:45.746720 ===================================
6165 01:02:45.749976 LPDDR4 DRAM CONFIGURATION
6166 01:02:45.753424 ===================================
6167 01:02:45.753509 EX_ROW_EN[0] = 0x10
6168 01:02:45.756841 EX_ROW_EN[1] = 0x0
6169 01:02:45.760021 LP4Y_EN = 0x0
6170 01:02:45.760105 WORK_FSP = 0x0
6171 01:02:45.763666 WL = 0x2
6172 01:02:45.763749 RL = 0x2
6173 01:02:45.766670 BL = 0x2
6174 01:02:45.766754 RPST = 0x0
6175 01:02:45.770274 RD_PRE = 0x0
6176 01:02:45.770360 WR_PRE = 0x1
6177 01:02:45.773537 WR_PST = 0x0
6178 01:02:45.773621 DBI_WR = 0x0
6179 01:02:45.776904 DBI_RD = 0x0
6180 01:02:45.776988 OTF = 0x1
6181 01:02:45.780198 ===================================
6182 01:02:45.786651 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6183 01:02:45.790781 nWR fixed to 30
6184 01:02:45.794235 [ModeRegInit_LP4] CH0 RK0
6185 01:02:45.794319 [ModeRegInit_LP4] CH0 RK1
6186 01:02:45.797491 [ModeRegInit_LP4] CH1 RK0
6187 01:02:45.801060 [ModeRegInit_LP4] CH1 RK1
6188 01:02:45.801145 match AC timing 19
6189 01:02:45.807386 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6190 01:02:45.810852 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6191 01:02:45.814053 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6192 01:02:45.820704 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6193 01:02:45.823848 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6194 01:02:45.823933 ==
6195 01:02:45.827268 Dram Type= 6, Freq= 0, CH_0, rank 0
6196 01:02:45.830747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6197 01:02:45.830832 ==
6198 01:02:45.837282 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6199 01:02:45.844019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6200 01:02:45.847126 [CA 0] Center 36 (8~64) winsize 57
6201 01:02:45.850550 [CA 1] Center 36 (8~64) winsize 57
6202 01:02:45.853832 [CA 2] Center 36 (8~64) winsize 57
6203 01:02:45.857127 [CA 3] Center 36 (8~64) winsize 57
6204 01:02:45.857212 [CA 4] Center 36 (8~64) winsize 57
6205 01:02:45.860567 [CA 5] Center 36 (8~64) winsize 57
6206 01:02:45.860651
6207 01:02:45.867205 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6208 01:02:45.867293
6209 01:02:45.870691 [CATrainingPosCal] consider 1 rank data
6210 01:02:45.873971 u2DelayCellTimex100 = 270/100 ps
6211 01:02:45.877237 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 01:02:45.880651 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 01:02:45.884002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 01:02:45.887074 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 01:02:45.890384 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 01:02:45.893919 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 01:02:45.894040
6218 01:02:45.897458 CA PerBit enable=1, Macro0, CA PI delay=36
6219 01:02:45.897542
6220 01:02:45.900515 [CBTSetCACLKResult] CA Dly = 36
6221 01:02:45.904161 CS Dly: 1 (0~32)
6222 01:02:45.904245 ==
6223 01:02:45.907143 Dram Type= 6, Freq= 0, CH_0, rank 1
6224 01:02:45.910266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6225 01:02:45.910351 ==
6226 01:02:45.917085 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6227 01:02:45.920625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6228 01:02:45.923716 [CA 0] Center 36 (8~64) winsize 57
6229 01:02:45.927187 [CA 1] Center 36 (8~64) winsize 57
6230 01:02:45.930425 [CA 2] Center 36 (8~64) winsize 57
6231 01:02:45.933764 [CA 3] Center 36 (8~64) winsize 57
6232 01:02:45.936762 [CA 4] Center 36 (8~64) winsize 57
6233 01:02:45.940112 [CA 5] Center 36 (8~64) winsize 57
6234 01:02:45.940201
6235 01:02:45.943751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6236 01:02:45.943834
6237 01:02:45.946924 [CATrainingPosCal] consider 2 rank data
6238 01:02:45.950307 u2DelayCellTimex100 = 270/100 ps
6239 01:02:45.953715 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 01:02:45.957062 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 01:02:45.963336 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 01:02:45.966820 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 01:02:45.970224 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 01:02:45.973546 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 01:02:45.973633
6246 01:02:45.976875 CA PerBit enable=1, Macro0, CA PI delay=36
6247 01:02:45.976958
6248 01:02:45.980421 [CBTSetCACLKResult] CA Dly = 36
6249 01:02:45.980505 CS Dly: 1 (0~32)
6250 01:02:45.980573
6251 01:02:45.983510 ----->DramcWriteLeveling(PI) begin...
6252 01:02:45.986618 ==
6253 01:02:45.986702 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 01:02:45.993348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 01:02:45.993435 ==
6256 01:02:45.996788 Write leveling (Byte 0): 40 => 8
6257 01:02:45.999960 Write leveling (Byte 1): 32 => 0
6258 01:02:46.000046 DramcWriteLeveling(PI) end<-----
6259 01:02:46.003452
6260 01:02:46.003535 ==
6261 01:02:46.006551 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 01:02:46.010079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 01:02:46.010163 ==
6264 01:02:46.013182 [Gating] SW mode calibration
6265 01:02:46.020055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6266 01:02:46.023591 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6267 01:02:46.029756 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 01:02:46.033614 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 01:02:46.036682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 01:02:46.043194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 01:02:46.046810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 01:02:46.049968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 01:02:46.056570 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 01:02:46.060248 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 01:02:46.063255 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 01:02:46.066329 Total UI for P1: 0, mck2ui 16
6277 01:02:46.069646 best dqsien dly found for B0: ( 0, 14, 24)
6278 01:02:46.073313 Total UI for P1: 0, mck2ui 16
6279 01:02:46.076422 best dqsien dly found for B1: ( 0, 14, 24)
6280 01:02:46.079712 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6281 01:02:46.083297 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6282 01:02:46.083384
6283 01:02:46.089904 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 01:02:46.093003 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 01:02:46.096580 [Gating] SW calibration Done
6286 01:02:46.096664 ==
6287 01:02:46.099668 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 01:02:46.102781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 01:02:46.102867 ==
6290 01:02:46.102934 RX Vref Scan: 0
6291 01:02:46.102995
6292 01:02:46.106095 RX Vref 0 -> 0, step: 1
6293 01:02:46.106177
6294 01:02:46.109687 RX Delay -410 -> 252, step: 16
6295 01:02:46.112729 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6296 01:02:46.119441 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6297 01:02:46.122505 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6298 01:02:46.125872 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6299 01:02:46.129119 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6300 01:02:46.135969 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6301 01:02:46.139561 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6302 01:02:46.142622 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6303 01:02:46.146098 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6304 01:02:46.152501 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6305 01:02:46.155909 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6306 01:02:46.159282 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6307 01:02:46.162635 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6308 01:02:46.168946 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6309 01:02:46.172367 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6310 01:02:46.175523 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6311 01:02:46.175608 ==
6312 01:02:46.179073 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 01:02:46.185415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 01:02:46.185500 ==
6315 01:02:46.185567 DQS Delay:
6316 01:02:46.188774 DQS0 = 27, DQS1 = 35
6317 01:02:46.188857 DQM Delay:
6318 01:02:46.188922 DQM0 = 12, DQM1 = 6
6319 01:02:46.192117 DQ Delay:
6320 01:02:46.195358 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6321 01:02:46.195441 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6322 01:02:46.198880 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6323 01:02:46.202229 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6324 01:02:46.202310
6325 01:02:46.202375
6326 01:02:46.202435 ==
6327 01:02:46.205469 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 01:02:46.211854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 01:02:46.211938 ==
6330 01:02:46.212003
6331 01:02:46.212063
6332 01:02:46.215526 TX Vref Scan disable
6333 01:02:46.215609 == TX Byte 0 ==
6334 01:02:46.219092 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 01:02:46.225351 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 01:02:46.225433 == TX Byte 1 ==
6337 01:02:46.228750 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6338 01:02:46.235038 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6339 01:02:46.235120 ==
6340 01:02:46.238688 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 01:02:46.242093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 01:02:46.242176 ==
6343 01:02:46.242242
6344 01:02:46.242301
6345 01:02:46.245008 TX Vref Scan disable
6346 01:02:46.245115 == TX Byte 0 ==
6347 01:02:46.248477 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 01:02:46.254999 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 01:02:46.255083 == TX Byte 1 ==
6350 01:02:46.258442 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6351 01:02:46.265095 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6352 01:02:46.265178
6353 01:02:46.265243 [DATLAT]
6354 01:02:46.265302 Freq=400, CH0 RK0
6355 01:02:46.265362
6356 01:02:46.268796 DATLAT Default: 0xf
6357 01:02:46.271772 0, 0xFFFF, sum = 0
6358 01:02:46.271857 1, 0xFFFF, sum = 0
6359 01:02:46.275117 2, 0xFFFF, sum = 0
6360 01:02:46.275200 3, 0xFFFF, sum = 0
6361 01:02:46.278771 4, 0xFFFF, sum = 0
6362 01:02:46.278854 5, 0xFFFF, sum = 0
6363 01:02:46.281698 6, 0xFFFF, sum = 0
6364 01:02:46.281781 7, 0xFFFF, sum = 0
6365 01:02:46.285023 8, 0xFFFF, sum = 0
6366 01:02:46.285107 9, 0xFFFF, sum = 0
6367 01:02:46.288266 10, 0xFFFF, sum = 0
6368 01:02:46.288349 11, 0xFFFF, sum = 0
6369 01:02:46.291677 12, 0xFFFF, sum = 0
6370 01:02:46.291761 13, 0x0, sum = 1
6371 01:02:46.295366 14, 0x0, sum = 2
6372 01:02:46.295450 15, 0x0, sum = 3
6373 01:02:46.298250 16, 0x0, sum = 4
6374 01:02:46.298334 best_step = 14
6375 01:02:46.298399
6376 01:02:46.298459 ==
6377 01:02:46.301472 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 01:02:46.308432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 01:02:46.308516 ==
6380 01:02:46.308582 RX Vref Scan: 1
6381 01:02:46.308643
6382 01:02:46.311323 RX Vref 0 -> 0, step: 1
6383 01:02:46.311406
6384 01:02:46.314738 RX Delay -311 -> 252, step: 8
6385 01:02:46.314821
6386 01:02:46.318121 Set Vref, RX VrefLevel [Byte0]: 59
6387 01:02:46.321434 [Byte1]: 50
6388 01:02:46.321516
6389 01:02:46.324838 Final RX Vref Byte 0 = 59 to rank0
6390 01:02:46.327899 Final RX Vref Byte 1 = 50 to rank0
6391 01:02:46.331513 Final RX Vref Byte 0 = 59 to rank1
6392 01:02:46.334960 Final RX Vref Byte 1 = 50 to rank1==
6393 01:02:46.337864 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 01:02:46.341574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 01:02:46.341657 ==
6396 01:02:46.344733 DQS Delay:
6397 01:02:46.344816 DQS0 = 28, DQS1 = 48
6398 01:02:46.347725 DQM Delay:
6399 01:02:46.347808 DQM0 = 13, DQM1 = 15
6400 01:02:46.351340 DQ Delay:
6401 01:02:46.351422 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6402 01:02:46.354617 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6403 01:02:46.357767 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6404 01:02:46.361477 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6405 01:02:46.361563
6406 01:02:46.361630
6407 01:02:46.371053 [DQSOSCAuto] RK0, (LSB)MR18= 0xa49b, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6408 01:02:46.374511 CH0 RK0: MR19=C0C, MR18=A49B
6409 01:02:46.381416 CH0_RK0: MR19=0xC0C, MR18=0xA49B, DQSOSC=389, MR23=63, INC=390, DEC=260
6410 01:02:46.381507 ==
6411 01:02:46.384481 Dram Type= 6, Freq= 0, CH_0, rank 1
6412 01:02:46.387764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 01:02:46.387851 ==
6414 01:02:46.391101 [Gating] SW mode calibration
6415 01:02:46.397832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6416 01:02:46.400861 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6417 01:02:46.407843 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 01:02:46.410840 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 01:02:46.414620 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 01:02:46.420927 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 01:02:46.424716 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 01:02:46.427514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 01:02:46.434549 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 01:02:46.437512 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 01:02:46.441164 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 01:02:46.444330 Total UI for P1: 0, mck2ui 16
6427 01:02:46.447488 best dqsien dly found for B0: ( 0, 14, 24)
6428 01:02:46.450952 Total UI for P1: 0, mck2ui 16
6429 01:02:46.454406 best dqsien dly found for B1: ( 0, 14, 24)
6430 01:02:46.457850 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6431 01:02:46.460972 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6432 01:02:46.461057
6433 01:02:46.467624 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 01:02:46.471311 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 01:02:46.471399 [Gating] SW calibration Done
6436 01:02:46.474790 ==
6437 01:02:46.474876 Dram Type= 6, Freq= 0, CH_0, rank 1
6438 01:02:46.480934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 01:02:46.481021 ==
6440 01:02:46.481087 RX Vref Scan: 0
6441 01:02:46.481150
6442 01:02:46.484731 RX Vref 0 -> 0, step: 1
6443 01:02:46.484819
6444 01:02:46.487558 RX Delay -410 -> 252, step: 16
6445 01:02:46.490924 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6446 01:02:46.494329 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6447 01:02:46.501228 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6448 01:02:46.504433 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6449 01:02:46.507651 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6450 01:02:46.511055 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6451 01:02:46.517539 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6452 01:02:46.520998 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6453 01:02:46.524152 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6454 01:02:46.527394 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6455 01:02:46.534265 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6456 01:02:46.537724 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6457 01:02:46.540676 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6458 01:02:46.547506 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6459 01:02:46.550863 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6460 01:02:46.553958 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6461 01:02:46.554044 ==
6462 01:02:46.557406 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 01:02:46.560667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 01:02:46.560752 ==
6465 01:02:46.564129 DQS Delay:
6466 01:02:46.564213 DQS0 = 19, DQS1 = 43
6467 01:02:46.567398 DQM Delay:
6468 01:02:46.567482 DQM0 = 2, DQM1 = 17
6469 01:02:46.567550 DQ Delay:
6470 01:02:46.570537 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6471 01:02:46.573745 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6472 01:02:46.577413 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6473 01:02:46.580682 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6474 01:02:46.580767
6475 01:02:46.580835
6476 01:02:46.580898 ==
6477 01:02:46.583958 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 01:02:46.591272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 01:02:46.591374 ==
6480 01:02:46.591442
6481 01:02:46.591503
6482 01:02:46.591564 TX Vref Scan disable
6483 01:02:46.593651 == TX Byte 0 ==
6484 01:02:46.597059 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6485 01:02:46.600456 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6486 01:02:46.603989 == TX Byte 1 ==
6487 01:02:46.607239 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6488 01:02:46.610512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6489 01:02:46.610598 ==
6490 01:02:46.613648 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 01:02:46.620280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 01:02:46.620369 ==
6493 01:02:46.620437
6494 01:02:46.620498
6495 01:02:46.620559 TX Vref Scan disable
6496 01:02:46.623471 == TX Byte 0 ==
6497 01:02:46.627106 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6498 01:02:46.630516 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6499 01:02:46.633394 == TX Byte 1 ==
6500 01:02:46.636604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6501 01:02:46.640445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6502 01:02:46.640531
6503 01:02:46.643414 [DATLAT]
6504 01:02:46.643499 Freq=400, CH0 RK1
6505 01:02:46.643567
6506 01:02:46.646900 DATLAT Default: 0xe
6507 01:02:46.646985 0, 0xFFFF, sum = 0
6508 01:02:46.650181 1, 0xFFFF, sum = 0
6509 01:02:46.650268 2, 0xFFFF, sum = 0
6510 01:02:46.653545 3, 0xFFFF, sum = 0
6511 01:02:46.653631 4, 0xFFFF, sum = 0
6512 01:02:46.657250 5, 0xFFFF, sum = 0
6513 01:02:46.657335 6, 0xFFFF, sum = 0
6514 01:02:46.660159 7, 0xFFFF, sum = 0
6515 01:02:46.660244 8, 0xFFFF, sum = 0
6516 01:02:46.663631 9, 0xFFFF, sum = 0
6517 01:02:46.663717 10, 0xFFFF, sum = 0
6518 01:02:46.666976 11, 0xFFFF, sum = 0
6519 01:02:46.667061 12, 0xFFFF, sum = 0
6520 01:02:46.670073 13, 0x0, sum = 1
6521 01:02:46.670159 14, 0x0, sum = 2
6522 01:02:46.673703 15, 0x0, sum = 3
6523 01:02:46.673789 16, 0x0, sum = 4
6524 01:02:46.677398 best_step = 14
6525 01:02:46.677482
6526 01:02:46.677550 ==
6527 01:02:46.680152 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 01:02:46.683545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 01:02:46.683631 ==
6530 01:02:46.686893 RX Vref Scan: 0
6531 01:02:46.686977
6532 01:02:46.687044 RX Vref 0 -> 0, step: 1
6533 01:02:46.687106
6534 01:02:46.690269 RX Delay -327 -> 252, step: 8
6535 01:02:46.698126 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6536 01:02:46.701447 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6537 01:02:46.705262 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6538 01:02:46.708228 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6539 01:02:46.714566 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6540 01:02:46.718469 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6541 01:02:46.721859 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6542 01:02:46.724802 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6543 01:02:46.731317 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6544 01:02:46.734710 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6545 01:02:46.737816 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6546 01:02:46.744691 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6547 01:02:46.747873 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6548 01:02:46.751555 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6549 01:02:46.754916 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6550 01:02:46.761187 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6551 01:02:46.761272 ==
6552 01:02:46.764676 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 01:02:46.767860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 01:02:46.767945 ==
6555 01:02:46.768014 DQS Delay:
6556 01:02:46.771073 DQS0 = 28, DQS1 = 40
6557 01:02:46.771159 DQM Delay:
6558 01:02:46.774976 DQM0 = 10, DQM1 = 12
6559 01:02:46.775061 DQ Delay:
6560 01:02:46.777911 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6561 01:02:46.781237 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6562 01:02:46.784330 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6563 01:02:46.787660 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6564 01:02:46.787744
6565 01:02:46.787811
6566 01:02:46.794423 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6567 01:02:46.797655 CH0 RK1: MR19=C0C, MR18=B86C
6568 01:02:46.804591 CH0_RK1: MR19=0xC0C, MR18=0xB86C, DQSOSC=386, MR23=63, INC=396, DEC=264
6569 01:02:46.807735 [RxdqsGatingPostProcess] freq 400
6570 01:02:46.814900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6571 01:02:46.814989 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 01:02:46.817584 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 01:02:46.821097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 01:02:46.824247 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 01:02:46.827729 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 01:02:46.831032 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 01:02:46.834909 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 01:02:46.837554 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 01:02:46.840789 Pre-setting of DQS Precalculation
6580 01:02:46.847474 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6581 01:02:46.847560 ==
6582 01:02:46.850571 Dram Type= 6, Freq= 0, CH_1, rank 0
6583 01:02:46.853952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 01:02:46.854037 ==
6585 01:02:46.860685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6586 01:02:46.864176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6587 01:02:46.867180 [CA 0] Center 36 (8~64) winsize 57
6588 01:02:46.870806 [CA 1] Center 36 (8~64) winsize 57
6589 01:02:46.874121 [CA 2] Center 36 (8~64) winsize 57
6590 01:02:46.877318 [CA 3] Center 36 (8~64) winsize 57
6591 01:02:46.880572 [CA 4] Center 36 (8~64) winsize 57
6592 01:02:46.884094 [CA 5] Center 36 (8~64) winsize 57
6593 01:02:46.884179
6594 01:02:46.887349 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6595 01:02:46.887433
6596 01:02:46.890725 [CATrainingPosCal] consider 1 rank data
6597 01:02:46.894506 u2DelayCellTimex100 = 270/100 ps
6598 01:02:46.897025 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 01:02:46.900348 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 01:02:46.903702 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 01:02:46.910265 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 01:02:46.913907 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 01:02:46.916967 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 01:02:46.917051
6605 01:02:46.920491 CA PerBit enable=1, Macro0, CA PI delay=36
6606 01:02:46.920575
6607 01:02:46.923840 [CBTSetCACLKResult] CA Dly = 36
6608 01:02:46.923925 CS Dly: 1 (0~32)
6609 01:02:46.923993 ==
6610 01:02:46.927195 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 01:02:46.933996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 01:02:46.934082 ==
6613 01:02:46.937176 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6614 01:02:46.943790 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6615 01:02:46.947246 [CA 0] Center 36 (8~64) winsize 57
6616 01:02:46.950402 [CA 1] Center 36 (8~64) winsize 57
6617 01:02:46.953464 [CA 2] Center 36 (8~64) winsize 57
6618 01:02:46.957006 [CA 3] Center 36 (8~64) winsize 57
6619 01:02:46.960340 [CA 4] Center 36 (8~64) winsize 57
6620 01:02:46.963636 [CA 5] Center 36 (8~64) winsize 57
6621 01:02:46.963720
6622 01:02:46.966957 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6623 01:02:46.967041
6624 01:02:46.970373 [CATrainingPosCal] consider 2 rank data
6625 01:02:46.973659 u2DelayCellTimex100 = 270/100 ps
6626 01:02:46.977112 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 01:02:46.980201 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 01:02:46.983813 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 01:02:46.986800 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 01:02:46.990405 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 01:02:46.993400 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 01:02:46.993484
6633 01:02:47.000041 CA PerBit enable=1, Macro0, CA PI delay=36
6634 01:02:47.000126
6635 01:02:47.003388 [CBTSetCACLKResult] CA Dly = 36
6636 01:02:47.003473 CS Dly: 1 (0~32)
6637 01:02:47.003541
6638 01:02:47.006959 ----->DramcWriteLeveling(PI) begin...
6639 01:02:47.007045 ==
6640 01:02:47.009957 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 01:02:47.013856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 01:02:47.013945 ==
6643 01:02:47.016574 Write leveling (Byte 0): 40 => 8
6644 01:02:47.019958 Write leveling (Byte 1): 32 => 0
6645 01:02:47.023366 DramcWriteLeveling(PI) end<-----
6646 01:02:47.023449
6647 01:02:47.023515 ==
6648 01:02:47.026759 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 01:02:47.033021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 01:02:47.033105 ==
6651 01:02:47.033171 [Gating] SW mode calibration
6652 01:02:47.043203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6653 01:02:47.046280 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6654 01:02:47.049670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 01:02:47.056346 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 01:02:47.059627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 01:02:47.063038 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 01:02:47.069707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 01:02:47.073013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 01:02:47.076734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 01:02:47.082885 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 01:02:47.086264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 01:02:47.089633 Total UI for P1: 0, mck2ui 16
6664 01:02:47.092779 best dqsien dly found for B0: ( 0, 14, 24)
6665 01:02:47.096386 Total UI for P1: 0, mck2ui 16
6666 01:02:47.099368 best dqsien dly found for B1: ( 0, 14, 24)
6667 01:02:47.103210 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6668 01:02:47.106162 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6669 01:02:47.106248
6670 01:02:47.109544 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 01:02:47.112765 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 01:02:47.116026 [Gating] SW calibration Done
6673 01:02:47.116108 ==
6674 01:02:47.119388 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 01:02:47.126778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 01:02:47.126863 ==
6677 01:02:47.126929 RX Vref Scan: 0
6678 01:02:47.126991
6679 01:02:47.129647 RX Vref 0 -> 0, step: 1
6680 01:02:47.129731
6681 01:02:47.133103 RX Delay -410 -> 252, step: 16
6682 01:02:47.136423 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6683 01:02:47.139794 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6684 01:02:47.142946 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6685 01:02:47.149380 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6686 01:02:47.153105 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6687 01:02:47.156677 iDelay=230, Bit 5, Center -11 (-234 ~ 213) 448
6688 01:02:47.159614 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6689 01:02:47.166220 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6690 01:02:47.169577 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6691 01:02:47.172692 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6692 01:02:47.176294 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6693 01:02:47.182664 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6694 01:02:47.185894 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6695 01:02:47.189452 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6696 01:02:47.196058 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6697 01:02:47.199266 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6698 01:02:47.199350 ==
6699 01:02:47.202975 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 01:02:47.205964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 01:02:47.206048 ==
6702 01:02:47.206114 DQS Delay:
6703 01:02:47.209384 DQS0 = 27, DQS1 = 43
6704 01:02:47.209466 DQM Delay:
6705 01:02:47.212446 DQM0 = 9, DQM1 = 18
6706 01:02:47.212528 DQ Delay:
6707 01:02:47.215669 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6708 01:02:47.219591 DQ4 =8, DQ5 =16, DQ6 =24, DQ7 =0
6709 01:02:47.222554 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6710 01:02:47.226201 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6711 01:02:47.226286
6712 01:02:47.226352
6713 01:02:47.226412 ==
6714 01:02:47.229136 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 01:02:47.232354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 01:02:47.232438 ==
6717 01:02:47.232506
6718 01:02:47.236087
6719 01:02:47.236170 TX Vref Scan disable
6720 01:02:47.239023 == TX Byte 0 ==
6721 01:02:47.242321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 01:02:47.245623 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 01:02:47.249037 == TX Byte 1 ==
6724 01:02:47.252286 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6725 01:02:47.255796 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6726 01:02:47.255880 ==
6727 01:02:47.259297 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 01:02:47.262255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 01:02:47.265727 ==
6730 01:02:47.265811
6731 01:02:47.265877
6732 01:02:47.265945 TX Vref Scan disable
6733 01:02:47.269256 == TX Byte 0 ==
6734 01:02:47.272448 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 01:02:47.275671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 01:02:47.279411 == TX Byte 1 ==
6737 01:02:47.282360 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6738 01:02:47.286202 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6739 01:02:47.286286
6740 01:02:47.288983 [DATLAT]
6741 01:02:47.289066 Freq=400, CH1 RK0
6742 01:02:47.289134
6743 01:02:47.292968 DATLAT Default: 0xf
6744 01:02:47.293053 0, 0xFFFF, sum = 0
6745 01:02:47.295464 1, 0xFFFF, sum = 0
6746 01:02:47.295549 2, 0xFFFF, sum = 0
6747 01:02:47.298853 3, 0xFFFF, sum = 0
6748 01:02:47.298938 4, 0xFFFF, sum = 0
6749 01:02:47.302283 5, 0xFFFF, sum = 0
6750 01:02:47.302368 6, 0xFFFF, sum = 0
6751 01:02:47.305511 7, 0xFFFF, sum = 0
6752 01:02:47.305595 8, 0xFFFF, sum = 0
6753 01:02:47.308857 9, 0xFFFF, sum = 0
6754 01:02:47.308941 10, 0xFFFF, sum = 0
6755 01:02:47.312058 11, 0xFFFF, sum = 0
6756 01:02:47.312142 12, 0xFFFF, sum = 0
6757 01:02:47.315350 13, 0x0, sum = 1
6758 01:02:47.315434 14, 0x0, sum = 2
6759 01:02:47.318887 15, 0x0, sum = 3
6760 01:02:47.318972 16, 0x0, sum = 4
6761 01:02:47.321902 best_step = 14
6762 01:02:47.321991
6763 01:02:47.322057 ==
6764 01:02:47.325847 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 01:02:47.328654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 01:02:47.328739 ==
6767 01:02:47.331993 RX Vref Scan: 1
6768 01:02:47.332077
6769 01:02:47.332142 RX Vref 0 -> 0, step: 1
6770 01:02:47.332203
6771 01:02:47.335373 RX Delay -327 -> 252, step: 8
6772 01:02:47.335457
6773 01:02:47.338943 Set Vref, RX VrefLevel [Byte0]: 52
6774 01:02:47.342027 [Byte1]: 52
6775 01:02:47.346688
6776 01:02:47.346799 Final RX Vref Byte 0 = 52 to rank0
6777 01:02:47.350192 Final RX Vref Byte 1 = 52 to rank0
6778 01:02:47.353466 Final RX Vref Byte 0 = 52 to rank1
6779 01:02:47.356635 Final RX Vref Byte 1 = 52 to rank1==
6780 01:02:47.360161 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 01:02:47.366599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 01:02:47.366684 ==
6783 01:02:47.366752 DQS Delay:
6784 01:02:47.369905 DQS0 = 32, DQS1 = 40
6785 01:02:47.370024 DQM Delay:
6786 01:02:47.370092 DQM0 = 11, DQM1 = 13
6787 01:02:47.372995 DQ Delay:
6788 01:02:47.376356 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6789 01:02:47.376440 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6790 01:02:47.380031 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =8
6791 01:02:47.383350 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6792 01:02:47.383433
6793 01:02:47.383499
6794 01:02:47.392859 [DQSOSCAuto] RK0, (LSB)MR18= 0x8bc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6795 01:02:47.396428 CH1 RK0: MR19=C0C, MR18=8BC6
6796 01:02:47.402936 CH1_RK0: MR19=0xC0C, MR18=0x8BC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6797 01:02:47.403021 ==
6798 01:02:47.406486 Dram Type= 6, Freq= 0, CH_1, rank 1
6799 01:02:47.409523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 01:02:47.409608 ==
6801 01:02:47.412823 [Gating] SW mode calibration
6802 01:02:47.419485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6803 01:02:47.425853 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6804 01:02:47.429897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 01:02:47.432577 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 01:02:47.439291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 01:02:47.442593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 01:02:47.446320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 01:02:47.452832 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 01:02:47.456354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 01:02:47.459094 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 01:02:47.465790 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 01:02:47.465875 Total UI for P1: 0, mck2ui 16
6814 01:02:47.469080 best dqsien dly found for B0: ( 0, 14, 24)
6815 01:02:47.472465 Total UI for P1: 0, mck2ui 16
6816 01:02:47.475956 best dqsien dly found for B1: ( 0, 14, 24)
6817 01:02:47.479353 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6818 01:02:47.485983 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6819 01:02:47.486067
6820 01:02:47.489055 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 01:02:47.492717 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 01:02:47.495592 [Gating] SW calibration Done
6823 01:02:47.495676 ==
6824 01:02:47.498820 Dram Type= 6, Freq= 0, CH_1, rank 1
6825 01:02:47.502316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 01:02:47.502401 ==
6827 01:02:47.505876 RX Vref Scan: 0
6828 01:02:47.505995
6829 01:02:47.506063 RX Vref 0 -> 0, step: 1
6830 01:02:47.506125
6831 01:02:47.508976 RX Delay -410 -> 252, step: 16
6832 01:02:47.515766 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6833 01:02:47.518966 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6834 01:02:47.522104 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6835 01:02:47.525608 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6836 01:02:47.528722 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6837 01:02:47.535555 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6838 01:02:47.539207 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6839 01:02:47.542647 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6840 01:02:47.545304 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6841 01:02:47.551948 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6842 01:02:47.555228 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6843 01:02:47.558638 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6844 01:02:47.565551 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6845 01:02:47.568681 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6846 01:02:47.571993 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6847 01:02:47.575348 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6848 01:02:47.575433 ==
6849 01:02:47.578637 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 01:02:47.585362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 01:02:47.585448 ==
6852 01:02:47.585515 DQS Delay:
6853 01:02:47.588718 DQS0 = 27, DQS1 = 43
6854 01:02:47.588802 DQM Delay:
6855 01:02:47.588868 DQM0 = 11, DQM1 = 20
6856 01:02:47.591947 DQ Delay:
6857 01:02:47.595598 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6858 01:02:47.595683 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6859 01:02:47.598849 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6860 01:02:47.601856 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6861 01:02:47.605288
6862 01:02:47.605372
6863 01:02:47.605438 ==
6864 01:02:47.608816 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 01:02:47.612068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 01:02:47.612152 ==
6867 01:02:47.612219
6868 01:02:47.612280
6869 01:02:47.615186 TX Vref Scan disable
6870 01:02:47.615269 == TX Byte 0 ==
6871 01:02:47.618546 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6872 01:02:47.625302 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6873 01:02:47.625386 == TX Byte 1 ==
6874 01:02:47.628890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6875 01:02:47.635110 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6876 01:02:47.635193 ==
6877 01:02:47.638280 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 01:02:47.641998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 01:02:47.642108 ==
6880 01:02:47.642202
6881 01:02:47.642347
6882 01:02:47.644999 TX Vref Scan disable
6883 01:02:47.645082 == TX Byte 0 ==
6884 01:02:47.648722 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6885 01:02:47.655182 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6886 01:02:47.655266 == TX Byte 1 ==
6887 01:02:47.658292 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6888 01:02:47.665116 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6889 01:02:47.665199
6890 01:02:47.665266 [DATLAT]
6891 01:02:47.665326 Freq=400, CH1 RK1
6892 01:02:47.665386
6893 01:02:47.668516 DATLAT Default: 0xe
6894 01:02:47.671520 0, 0xFFFF, sum = 0
6895 01:02:47.671606 1, 0xFFFF, sum = 0
6896 01:02:47.675072 2, 0xFFFF, sum = 0
6897 01:02:47.675157 3, 0xFFFF, sum = 0
6898 01:02:47.678324 4, 0xFFFF, sum = 0
6899 01:02:47.678410 5, 0xFFFF, sum = 0
6900 01:02:47.681454 6, 0xFFFF, sum = 0
6901 01:02:47.681540 7, 0xFFFF, sum = 0
6902 01:02:47.684887 8, 0xFFFF, sum = 0
6903 01:02:47.684971 9, 0xFFFF, sum = 0
6904 01:02:47.688494 10, 0xFFFF, sum = 0
6905 01:02:47.688579 11, 0xFFFF, sum = 0
6906 01:02:47.691599 12, 0xFFFF, sum = 0
6907 01:02:47.691685 13, 0x0, sum = 1
6908 01:02:47.694934 14, 0x0, sum = 2
6909 01:02:47.695019 15, 0x0, sum = 3
6910 01:02:47.698367 16, 0x0, sum = 4
6911 01:02:47.698452 best_step = 14
6912 01:02:47.698519
6913 01:02:47.698581 ==
6914 01:02:47.701844 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 01:02:47.708601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 01:02:47.708687 ==
6917 01:02:47.708753 RX Vref Scan: 0
6918 01:02:47.708816
6919 01:02:47.712193 RX Vref 0 -> 0, step: 1
6920 01:02:47.712277
6921 01:02:47.715027 RX Delay -327 -> 252, step: 8
6922 01:02:47.721504 iDelay=217, Bit 0, Center -20 (-239 ~ 200) 440
6923 01:02:47.724827 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6924 01:02:47.727971 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6925 01:02:47.731488 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6926 01:02:47.738062 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6927 01:02:47.741466 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6928 01:02:47.744779 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6929 01:02:47.748164 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6930 01:02:47.751430 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6931 01:02:47.757878 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6932 01:02:47.761559 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6933 01:02:47.764462 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6934 01:02:47.771242 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6935 01:02:47.774557 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6936 01:02:47.777680 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6937 01:02:47.781853 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6938 01:02:47.782000 ==
6939 01:02:47.784721 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 01:02:47.791205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 01:02:47.791290 ==
6942 01:02:47.791357 DQS Delay:
6943 01:02:47.794686 DQS0 = 28, DQS1 = 36
6944 01:02:47.794770 DQM Delay:
6945 01:02:47.797977 DQM0 = 9, DQM1 = 11
6946 01:02:47.798061 DQ Delay:
6947 01:02:47.801343 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =12
6948 01:02:47.804283 DQ4 =12, DQ5 =20, DQ6 =12, DQ7 =4
6949 01:02:47.804366 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6950 01:02:47.811028 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6951 01:02:47.811112
6952 01:02:47.811178
6953 01:02:47.817775 [DQSOSCAuto] RK1, (LSB)MR18= 0xa54c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6954 01:02:47.821250 CH1 RK1: MR19=C0C, MR18=A54C
6955 01:02:47.827989 CH1_RK1: MR19=0xC0C, MR18=0xA54C, DQSOSC=389, MR23=63, INC=390, DEC=260
6956 01:02:47.830936 [RxdqsGatingPostProcess] freq 400
6957 01:02:47.834370 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6958 01:02:47.837744 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 01:02:47.840791 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 01:02:47.844461 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 01:02:47.847534 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 01:02:47.850871 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 01:02:47.854444 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 01:02:47.857512 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 01:02:47.861287 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 01:02:47.864170 Pre-setting of DQS Precalculation
6967 01:02:47.869684 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6968 01:02:47.877817 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6969 01:02:47.884097 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6970 01:02:47.884185
6971 01:02:47.884252
6972 01:02:47.887259 [Calibration Summary] 800 Mbps
6973 01:02:47.887344 CH 0, Rank 0
6974 01:02:47.890658 SW Impedance : PASS
6975 01:02:47.890743 DUTY Scan : NO K
6976 01:02:47.894054 ZQ Calibration : PASS
6977 01:02:47.897316 Jitter Meter : NO K
6978 01:02:47.897400 CBT Training : PASS
6979 01:02:47.900991 Write leveling : PASS
6980 01:02:47.901076 RX DQS gating : PASS
6981 01:02:47.903923 RX DQ/DQS(RDDQC) : PASS
6982 01:02:47.907523 TX DQ/DQS : PASS
6983 01:02:47.907607 RX DATLAT : PASS
6984 01:02:47.910709 RX DQ/DQS(Engine): PASS
6985 01:02:47.914022 TX OE : NO K
6986 01:02:47.914106 All Pass.
6987 01:02:47.914172
6988 01:02:47.914231 CH 0, Rank 1
6989 01:02:47.917589 SW Impedance : PASS
6990 01:02:47.920707 DUTY Scan : NO K
6991 01:02:47.920796 ZQ Calibration : PASS
6992 01:02:47.923883 Jitter Meter : NO K
6993 01:02:47.927355 CBT Training : PASS
6994 01:02:47.927438 Write leveling : NO K
6995 01:02:47.930897 RX DQS gating : PASS
6996 01:02:47.933635 RX DQ/DQS(RDDQC) : PASS
6997 01:02:47.933713 TX DQ/DQS : PASS
6998 01:02:47.937449 RX DATLAT : PASS
6999 01:02:47.940264 RX DQ/DQS(Engine): PASS
7000 01:02:47.940378 TX OE : NO K
7001 01:02:47.943968 All Pass.
7002 01:02:47.944052
7003 01:02:47.944153 CH 1, Rank 0
7004 01:02:47.947046 SW Impedance : PASS
7005 01:02:47.947121 DUTY Scan : NO K
7006 01:02:47.950333 ZQ Calibration : PASS
7007 01:02:47.953654 Jitter Meter : NO K
7008 01:02:47.953730 CBT Training : PASS
7009 01:02:47.957049 Write leveling : PASS
7010 01:02:47.957133 RX DQS gating : PASS
7011 01:02:47.960302 RX DQ/DQS(RDDQC) : PASS
7012 01:02:47.963628 TX DQ/DQS : PASS
7013 01:02:47.963715 RX DATLAT : PASS
7014 01:02:47.967588 RX DQ/DQS(Engine): PASS
7015 01:02:47.970295 TX OE : NO K
7016 01:02:47.970380 All Pass.
7017 01:02:47.970446
7018 01:02:47.970517 CH 1, Rank 1
7019 01:02:47.974116 SW Impedance : PASS
7020 01:02:47.976790 DUTY Scan : NO K
7021 01:02:47.976874 ZQ Calibration : PASS
7022 01:02:47.980238 Jitter Meter : NO K
7023 01:02:47.983531 CBT Training : PASS
7024 01:02:47.983614 Write leveling : NO K
7025 01:02:47.987135 RX DQS gating : PASS
7026 01:02:47.990432 RX DQ/DQS(RDDQC) : PASS
7027 01:02:47.990514 TX DQ/DQS : PASS
7028 01:02:47.993459 RX DATLAT : PASS
7029 01:02:47.997044 RX DQ/DQS(Engine): PASS
7030 01:02:47.997131 TX OE : NO K
7031 01:02:48.000321 All Pass.
7032 01:02:48.000404
7033 01:02:48.000470 DramC Write-DBI off
7034 01:02:48.003753 PER_BANK_REFRESH: Hybrid Mode
7035 01:02:48.003835 TX_TRACKING: ON
7036 01:02:48.013367 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7037 01:02:48.016774 [FAST_K] Save calibration result to emmc
7038 01:02:48.020222 dramc_set_vcore_voltage set vcore to 725000
7039 01:02:48.023359 Read voltage for 1600, 0
7040 01:02:48.023442 Vio18 = 0
7041 01:02:48.026937 Vcore = 725000
7042 01:02:48.027020 Vdram = 0
7043 01:02:48.027086 Vddq = 0
7044 01:02:48.029804 Vmddr = 0
7045 01:02:48.033291 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7046 01:02:48.040363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7047 01:02:48.040446 MEM_TYPE=3, freq_sel=13
7048 01:02:48.043249 sv_algorithm_assistance_LP4_3733
7049 01:02:48.046882 ============ PULL DRAM RESETB DOWN ============
7050 01:02:48.053367 ========== PULL DRAM RESETB DOWN end =========
7051 01:02:48.056726 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7052 01:02:48.059867 ===================================
7053 01:02:48.062996 LPDDR4 DRAM CONFIGURATION
7054 01:02:48.066427 ===================================
7055 01:02:48.066511 EX_ROW_EN[0] = 0x0
7056 01:02:48.069671 EX_ROW_EN[1] = 0x0
7057 01:02:48.073052 LP4Y_EN = 0x0
7058 01:02:48.073137 WORK_FSP = 0x1
7059 01:02:48.076491 WL = 0x5
7060 01:02:48.076574 RL = 0x5
7061 01:02:48.080023 BL = 0x2
7062 01:02:48.080106 RPST = 0x0
7063 01:02:48.083009 RD_PRE = 0x0
7064 01:02:48.083092 WR_PRE = 0x1
7065 01:02:48.086284 WR_PST = 0x1
7066 01:02:48.086367 DBI_WR = 0x0
7067 01:02:48.089680 DBI_RD = 0x0
7068 01:02:48.089785 OTF = 0x1
7069 01:02:48.093041 ===================================
7070 01:02:48.096172 ===================================
7071 01:02:48.099669 ANA top config
7072 01:02:48.102690 ===================================
7073 01:02:48.102774 DLL_ASYNC_EN = 0
7074 01:02:48.106211 ALL_SLAVE_EN = 0
7075 01:02:48.109672 NEW_RANK_MODE = 1
7076 01:02:48.112843 DLL_IDLE_MODE = 1
7077 01:02:48.112927 LP45_APHY_COMB_EN = 1
7078 01:02:48.116167 TX_ODT_DIS = 0
7079 01:02:48.120048 NEW_8X_MODE = 1
7080 01:02:48.122953 ===================================
7081 01:02:48.125987 ===================================
7082 01:02:48.129440 data_rate = 3200
7083 01:02:48.133056 CKR = 1
7084 01:02:48.136151 DQ_P2S_RATIO = 8
7085 01:02:48.139492 ===================================
7086 01:02:48.139576 CA_P2S_RATIO = 8
7087 01:02:48.142673 DQ_CA_OPEN = 0
7088 01:02:48.146058 DQ_SEMI_OPEN = 0
7089 01:02:48.150351 CA_SEMI_OPEN = 0
7090 01:02:48.152955 CA_FULL_RATE = 0
7091 01:02:48.156238 DQ_CKDIV4_EN = 0
7092 01:02:48.156323 CA_CKDIV4_EN = 0
7093 01:02:48.159713 CA_PREDIV_EN = 0
7094 01:02:48.162932 PH8_DLY = 12
7095 01:02:48.166147 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7096 01:02:48.169231 DQ_AAMCK_DIV = 4
7097 01:02:48.172640 CA_AAMCK_DIV = 4
7098 01:02:48.172725 CA_ADMCK_DIV = 4
7099 01:02:48.176184 DQ_TRACK_CA_EN = 0
7100 01:02:48.179746 CA_PICK = 1600
7101 01:02:48.182648 CA_MCKIO = 1600
7102 01:02:48.185869 MCKIO_SEMI = 0
7103 01:02:48.189488 PLL_FREQ = 3068
7104 01:02:48.192656 DQ_UI_PI_RATIO = 32
7105 01:02:48.192741 CA_UI_PI_RATIO = 0
7106 01:02:48.196278 ===================================
7107 01:02:48.199681 ===================================
7108 01:02:48.202858 memory_type:LPDDR4
7109 01:02:48.206214 GP_NUM : 10
7110 01:02:48.206300 SRAM_EN : 1
7111 01:02:48.209425 MD32_EN : 0
7112 01:02:48.212550 ===================================
7113 01:02:48.215885 [ANA_INIT] >>>>>>>>>>>>>>
7114 01:02:48.219579 <<<<<< [CONFIGURE PHASE]: ANA_TX
7115 01:02:48.222417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7116 01:02:48.225786 ===================================
7117 01:02:48.225870 data_rate = 3200,PCW = 0X7600
7118 01:02:48.229130 ===================================
7119 01:02:48.232422 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7120 01:02:48.239304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 01:02:48.245806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 01:02:48.248940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7123 01:02:48.252314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7124 01:02:48.255462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7125 01:02:48.258963 [ANA_INIT] flow start
7126 01:02:48.262318 [ANA_INIT] PLL >>>>>>>>
7127 01:02:48.262403 [ANA_INIT] PLL <<<<<<<<
7128 01:02:48.265298 [ANA_INIT] MIDPI >>>>>>>>
7129 01:02:48.268731 [ANA_INIT] MIDPI <<<<<<<<
7130 01:02:48.268816 [ANA_INIT] DLL >>>>>>>>
7131 01:02:48.272592 [ANA_INIT] DLL <<<<<<<<
7132 01:02:48.276139 [ANA_INIT] flow end
7133 01:02:48.278991 ============ LP4 DIFF to SE enter ============
7134 01:02:48.281978 ============ LP4 DIFF to SE exit ============
7135 01:02:48.285331 [ANA_INIT] <<<<<<<<<<<<<
7136 01:02:48.288600 [Flow] Enable top DCM control >>>>>
7137 01:02:48.291851 [Flow] Enable top DCM control <<<<<
7138 01:02:48.295416 Enable DLL master slave shuffle
7139 01:02:48.298785 ==============================================================
7140 01:02:48.301975 Gating Mode config
7141 01:02:48.308601 ==============================================================
7142 01:02:48.308687 Config description:
7143 01:02:48.318643 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7144 01:02:48.325596 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7145 01:02:48.328654 SELPH_MODE 0: By rank 1: By Phase
7146 01:02:48.335144 ==============================================================
7147 01:02:48.338754 GAT_TRACK_EN = 1
7148 01:02:48.341873 RX_GATING_MODE = 2
7149 01:02:48.345011 RX_GATING_TRACK_MODE = 2
7150 01:02:48.348730 SELPH_MODE = 1
7151 01:02:48.351967 PICG_EARLY_EN = 1
7152 01:02:48.355314 VALID_LAT_VALUE = 1
7153 01:02:48.358337 ==============================================================
7154 01:02:48.361861 Enter into Gating configuration >>>>
7155 01:02:48.364985 Exit from Gating configuration <<<<
7156 01:02:48.368381 Enter into DVFS_PRE_config >>>>>
7157 01:02:48.381603 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7158 01:02:48.381712 Exit from DVFS_PRE_config <<<<<
7159 01:02:48.385156 Enter into PICG configuration >>>>
7160 01:02:48.388344 Exit from PICG configuration <<<<
7161 01:02:48.391497 [RX_INPUT] configuration >>>>>
7162 01:02:48.395249 [RX_INPUT] configuration <<<<<
7163 01:02:48.401912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7164 01:02:48.404959 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7165 01:02:48.411758 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7166 01:02:48.418361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7167 01:02:48.425089 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 01:02:48.431700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 01:02:48.434858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7170 01:02:48.438421 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7171 01:02:48.441685 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7172 01:02:48.448258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7173 01:02:48.451412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7174 01:02:48.454777 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7175 01:02:48.458206 ===================================
7176 01:02:48.462161 LPDDR4 DRAM CONFIGURATION
7177 01:02:48.465328 ===================================
7178 01:02:48.465412 EX_ROW_EN[0] = 0x0
7179 01:02:48.467997 EX_ROW_EN[1] = 0x0
7180 01:02:48.471337 LP4Y_EN = 0x0
7181 01:02:48.471420 WORK_FSP = 0x1
7182 01:02:48.474999 WL = 0x5
7183 01:02:48.475083 RL = 0x5
7184 01:02:48.478119 BL = 0x2
7185 01:02:48.478202 RPST = 0x0
7186 01:02:48.481573 RD_PRE = 0x0
7187 01:02:48.481656 WR_PRE = 0x1
7188 01:02:48.484625 WR_PST = 0x1
7189 01:02:48.484707 DBI_WR = 0x0
7190 01:02:48.488351 DBI_RD = 0x0
7191 01:02:48.488434 OTF = 0x1
7192 01:02:48.491102 ===================================
7193 01:02:48.494476 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7194 01:02:48.501364 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7195 01:02:48.504444 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 01:02:48.508224 ===================================
7197 01:02:48.511298 LPDDR4 DRAM CONFIGURATION
7198 01:02:48.514491 ===================================
7199 01:02:48.514574 EX_ROW_EN[0] = 0x10
7200 01:02:48.517888 EX_ROW_EN[1] = 0x0
7201 01:02:48.520938 LP4Y_EN = 0x0
7202 01:02:48.521021 WORK_FSP = 0x1
7203 01:02:48.524446 WL = 0x5
7204 01:02:48.524529 RL = 0x5
7205 01:02:48.527753 BL = 0x2
7206 01:02:48.527835 RPST = 0x0
7207 01:02:48.530967 RD_PRE = 0x0
7208 01:02:48.531050 WR_PRE = 0x1
7209 01:02:48.534412 WR_PST = 0x1
7210 01:02:48.534495 DBI_WR = 0x0
7211 01:02:48.537832 DBI_RD = 0x0
7212 01:02:48.537934 OTF = 0x1
7213 01:02:48.541196 ===================================
7214 01:02:48.548064 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7215 01:02:48.548150 ==
7216 01:02:48.551007 Dram Type= 6, Freq= 0, CH_0, rank 0
7217 01:02:48.554635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7218 01:02:48.554721 ==
7219 01:02:48.557891 [Duty_Offset_Calibration]
7220 01:02:48.561052 B0:2 B1:0 CA:1
7221 01:02:48.561136
7222 01:02:48.564081 [DutyScan_Calibration_Flow] k_type=0
7223 01:02:48.572043
7224 01:02:48.572127 ==CLK 0==
7225 01:02:48.575330 Final CLK duty delay cell = -4
7226 01:02:48.578492 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7227 01:02:48.582229 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7228 01:02:48.585240 [-4] AVG Duty = 4937%(X100)
7229 01:02:48.585323
7230 01:02:48.588610 CH0 CLK Duty spec in!! Max-Min= 187%
7231 01:02:48.592066 [DutyScan_Calibration_Flow] ====Done====
7232 01:02:48.592151
7233 01:02:48.595387 [DutyScan_Calibration_Flow] k_type=1
7234 01:02:48.611480
7235 01:02:48.611567 ==DQS 0 ==
7236 01:02:48.614621 Final DQS duty delay cell = 0
7237 01:02:48.617936 [0] MAX Duty = 5249%(X100), DQS PI = 32
7238 01:02:48.621595 [0] MIN Duty = 4938%(X100), DQS PI = 62
7239 01:02:48.624764 [0] AVG Duty = 5093%(X100)
7240 01:02:48.624849
7241 01:02:48.624915 ==DQS 1 ==
7242 01:02:48.628303 Final DQS duty delay cell = -4
7243 01:02:48.631487 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7244 01:02:48.634546 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7245 01:02:48.637904 [-4] AVG Duty = 5000%(X100)
7246 01:02:48.638010
7247 01:02:48.641292 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7248 01:02:48.641377
7249 01:02:48.644500 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7250 01:02:48.648047 [DutyScan_Calibration_Flow] ====Done====
7251 01:02:48.648132
7252 01:02:48.650948 [DutyScan_Calibration_Flow] k_type=3
7253 01:02:48.668735
7254 01:02:48.668819 ==DQM 0 ==
7255 01:02:48.672349 Final DQM duty delay cell = 0
7256 01:02:48.675664 [0] MAX Duty = 5093%(X100), DQS PI = 26
7257 01:02:48.678740 [0] MIN Duty = 4813%(X100), DQS PI = 50
7258 01:02:48.682200 [0] AVG Duty = 4953%(X100)
7259 01:02:48.682284
7260 01:02:48.682351 ==DQM 1 ==
7261 01:02:48.685691 Final DQM duty delay cell = 0
7262 01:02:48.688834 [0] MAX Duty = 5249%(X100), DQS PI = 30
7263 01:02:48.692055 [0] MIN Duty = 5031%(X100), DQS PI = 8
7264 01:02:48.695262 [0] AVG Duty = 5140%(X100)
7265 01:02:48.695346
7266 01:02:48.698810 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7267 01:02:48.698894
7268 01:02:48.701945 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7269 01:02:48.705328 [DutyScan_Calibration_Flow] ====Done====
7270 01:02:48.705412
7271 01:02:48.708876 [DutyScan_Calibration_Flow] k_type=2
7272 01:02:48.725869
7273 01:02:48.725984 ==DQ 0 ==
7274 01:02:48.729120 Final DQ duty delay cell = 0
7275 01:02:48.732683 [0] MAX Duty = 5124%(X100), DQS PI = 34
7276 01:02:48.735891 [0] MIN Duty = 5000%(X100), DQS PI = 16
7277 01:02:48.735975 [0] AVG Duty = 5062%(X100)
7278 01:02:48.739262
7279 01:02:48.739345 ==DQ 1 ==
7280 01:02:48.742566 Final DQ duty delay cell = 0
7281 01:02:48.745915 [0] MAX Duty = 4969%(X100), DQS PI = 44
7282 01:02:48.749330 [0] MIN Duty = 4875%(X100), DQS PI = 10
7283 01:02:48.749460 [0] AVG Duty = 4922%(X100)
7284 01:02:48.749562
7285 01:02:48.752473 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7286 01:02:48.755950
7287 01:02:48.759494 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7288 01:02:48.762478 [DutyScan_Calibration_Flow] ====Done====
7289 01:02:48.762588 ==
7290 01:02:48.765854 Dram Type= 6, Freq= 0, CH_1, rank 0
7291 01:02:48.769192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 01:02:48.769305 ==
7293 01:02:48.772923 [Duty_Offset_Calibration]
7294 01:02:48.773031 B0:0 B1:-1 CA:2
7295 01:02:48.773136
7296 01:02:48.775588 [DutyScan_Calibration_Flow] k_type=0
7297 01:02:48.786350
7298 01:02:48.786462 ==CLK 0==
7299 01:02:48.789590 Final CLK duty delay cell = 0
7300 01:02:48.792767 [0] MAX Duty = 5156%(X100), DQS PI = 10
7301 01:02:48.796138 [0] MIN Duty = 4906%(X100), DQS PI = 46
7302 01:02:48.799232 [0] AVG Duty = 5031%(X100)
7303 01:02:48.799343
7304 01:02:48.802809 CH1 CLK Duty spec in!! Max-Min= 250%
7305 01:02:48.806155 [DutyScan_Calibration_Flow] ====Done====
7306 01:02:48.806266
7307 01:02:48.809703 [DutyScan_Calibration_Flow] k_type=1
7308 01:02:48.825898
7309 01:02:48.826017 ==DQS 0 ==
7310 01:02:48.829445 Final DQS duty delay cell = 0
7311 01:02:48.832571 [0] MAX Duty = 5093%(X100), DQS PI = 24
7312 01:02:48.835869 [0] MIN Duty = 4969%(X100), DQS PI = 2
7313 01:02:48.835979 [0] AVG Duty = 5031%(X100)
7314 01:02:48.839760
7315 01:02:48.839872 ==DQS 1 ==
7316 01:02:48.842523 Final DQS duty delay cell = 0
7317 01:02:48.845869 [0] MAX Duty = 5187%(X100), DQS PI = 0
7318 01:02:48.849055 [0] MIN Duty = 4844%(X100), DQS PI = 32
7319 01:02:48.849167 [0] AVG Duty = 5015%(X100)
7320 01:02:48.852646
7321 01:02:48.855880 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7322 01:02:48.855988
7323 01:02:48.859114 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7324 01:02:48.862491 [DutyScan_Calibration_Flow] ====Done====
7325 01:02:48.862603
7326 01:02:48.865647 [DutyScan_Calibration_Flow] k_type=3
7327 01:02:48.883740
7328 01:02:48.883855 ==DQM 0 ==
7329 01:02:48.886792 Final DQM duty delay cell = 4
7330 01:02:48.890534 [4] MAX Duty = 5125%(X100), DQS PI = 22
7331 01:02:48.893533 [4] MIN Duty = 5000%(X100), DQS PI = 30
7332 01:02:48.896684 [4] AVG Duty = 5062%(X100)
7333 01:02:48.896788
7334 01:02:48.896880 ==DQM 1 ==
7335 01:02:48.900429 Final DQM duty delay cell = 0
7336 01:02:48.903325 [0] MAX Duty = 5281%(X100), DQS PI = 58
7337 01:02:48.907062 [0] MIN Duty = 4907%(X100), DQS PI = 34
7338 01:02:48.909999 [0] AVG Duty = 5094%(X100)
7339 01:02:48.910105
7340 01:02:48.913352 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7341 01:02:48.913458
7342 01:02:48.916449 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7343 01:02:48.919683 [DutyScan_Calibration_Flow] ====Done====
7344 01:02:48.919800
7345 01:02:48.923066 [DutyScan_Calibration_Flow] k_type=2
7346 01:02:48.940621
7347 01:02:48.940746 ==DQ 0 ==
7348 01:02:48.943587 Final DQ duty delay cell = 0
7349 01:02:48.946836 [0] MAX Duty = 5062%(X100), DQS PI = 18
7350 01:02:48.950413 [0] MIN Duty = 4969%(X100), DQS PI = 2
7351 01:02:48.950522 [0] AVG Duty = 5015%(X100)
7352 01:02:48.953630
7353 01:02:48.953737 ==DQ 1 ==
7354 01:02:48.957013 Final DQ duty delay cell = 0
7355 01:02:48.960172 [0] MAX Duty = 5062%(X100), DQS PI = 4
7356 01:02:48.963408 [0] MIN Duty = 4844%(X100), DQS PI = 32
7357 01:02:48.963520 [0] AVG Duty = 4953%(X100)
7358 01:02:48.963620
7359 01:02:48.966855 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7360 01:02:48.970189
7361 01:02:48.973350 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7362 01:02:48.976634 [DutyScan_Calibration_Flow] ====Done====
7363 01:02:48.980049 nWR fixed to 30
7364 01:02:48.980164 [ModeRegInit_LP4] CH0 RK0
7365 01:02:48.983361 [ModeRegInit_LP4] CH0 RK1
7366 01:02:48.986721 [ModeRegInit_LP4] CH1 RK0
7367 01:02:48.990060 [ModeRegInit_LP4] CH1 RK1
7368 01:02:48.990171 match AC timing 5
7369 01:02:48.993262 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7370 01:02:49.000034 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7371 01:02:49.003246 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7372 01:02:49.009814 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7373 01:02:49.013094 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7374 01:02:49.013207 [MiockJmeterHQA]
7375 01:02:49.013305
7376 01:02:49.016180 [DramcMiockJmeter] u1RxGatingPI = 0
7377 01:02:49.019777 0 : 4257, 4030
7378 01:02:49.019888 4 : 4252, 4027
7379 01:02:49.022849 8 : 4253, 4027
7380 01:02:49.022960 12 : 4257, 4029
7381 01:02:49.023064 16 : 4252, 4027
7382 01:02:49.026256 20 : 4252, 4027
7383 01:02:49.026365 24 : 4252, 4027
7384 01:02:49.029719 28 : 4365, 4140
7385 01:02:49.029829 32 : 4365, 4140
7386 01:02:49.032810 36 : 4255, 4029
7387 01:02:49.032920 40 : 4252, 4027
7388 01:02:49.036437 44 : 4363, 4138
7389 01:02:49.036551 48 : 4253, 4027
7390 01:02:49.036653 52 : 4365, 4140
7391 01:02:49.039658 56 : 4255, 4029
7392 01:02:49.039770 60 : 4365, 4140
7393 01:02:49.042657 64 : 4253, 4026
7394 01:02:49.042772 68 : 4250, 4027
7395 01:02:49.046006 72 : 4249, 4027
7396 01:02:49.046120 76 : 4250, 4027
7397 01:02:49.049301 80 : 4363, 4140
7398 01:02:49.049414 84 : 4363, 4140
7399 01:02:49.049516 88 : 4253, 3641
7400 01:02:49.052632 92 : 4252, 0
7401 01:02:49.052747 96 : 4252, 0
7402 01:02:49.055994 100 : 4360, 0
7403 01:02:49.056107 104 : 4252, 0
7404 01:02:49.056205 108 : 4252, 0
7405 01:02:49.059311 112 : 4254, 0
7406 01:02:49.059427 116 : 4363, 0
7407 01:02:49.059527 120 : 4360, 0
7408 01:02:49.062555 124 : 4250, 0
7409 01:02:49.062666 128 : 4247, 0
7410 01:02:49.066093 132 : 4252, 0
7411 01:02:49.066206 136 : 4364, 0
7412 01:02:49.066307 140 : 4255, 0
7413 01:02:49.069297 144 : 4250, 0
7414 01:02:49.069408 148 : 4361, 0
7415 01:02:49.072559 152 : 4253, 0
7416 01:02:49.072670 156 : 4250, 0
7417 01:02:49.072772 160 : 4250, 0
7418 01:02:49.076155 164 : 4252, 0
7419 01:02:49.076270 168 : 4360, 0
7420 01:02:49.079900 172 : 4250, 0
7421 01:02:49.080012 176 : 4250, 0
7422 01:02:49.080116 180 : 4255, 0
7423 01:02:49.082670 184 : 4361, 0
7424 01:02:49.082784 188 : 4250, 0
7425 01:02:49.082884 192 : 4250, 0
7426 01:02:49.086249 196 : 4250, 0
7427 01:02:49.086363 200 : 4361, 0
7428 01:02:49.089692 204 : 4250, 2282
7429 01:02:49.089804 208 : 4363, 4140
7430 01:02:49.092449 212 : 4363, 4140
7431 01:02:49.092561 216 : 4361, 4137
7432 01:02:49.095978 220 : 4250, 4027
7433 01:02:49.096093 224 : 4363, 4140
7434 01:02:49.099418 228 : 4252, 4029
7435 01:02:49.099528 232 : 4250, 4027
7436 01:02:49.099629 236 : 4255, 4029
7437 01:02:49.103012 240 : 4252, 4030
7438 01:02:49.103124 244 : 4250, 4027
7439 01:02:49.105989 248 : 4363, 4140
7440 01:02:49.106101 252 : 4250, 4027
7441 01:02:49.109286 256 : 4250, 4027
7442 01:02:49.109400 260 : 4361, 4137
7443 01:02:49.112510 264 : 4361, 4138
7444 01:02:49.112623 268 : 4361, 4137
7445 01:02:49.115790 272 : 4250, 4027
7446 01:02:49.115905 276 : 4250, 4027
7447 01:02:49.118959 280 : 4250, 4027
7448 01:02:49.119073 284 : 4250, 4026
7449 01:02:49.122207 288 : 4250, 4026
7450 01:02:49.122320 292 : 4252, 4030
7451 01:02:49.125726 296 : 4250, 4026
7452 01:02:49.125842 300 : 4361, 4138
7453 01:02:49.125948 304 : 4250, 4027
7454 01:02:49.128927 308 : 4250, 4027
7455 01:02:49.129039 312 : 4249, 3989
7456 01:02:49.132441 316 : 4361, 2300
7457 01:02:49.132556 320 : 4250, 5
7458 01:02:49.132656
7459 01:02:49.135824 MIOCK jitter meter ch=0
7460 01:02:49.135932
7461 01:02:49.139372 1T = (320-92) = 228 dly cells
7462 01:02:49.142749 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7463 01:02:49.145932 ==
7464 01:02:49.148999 Dram Type= 6, Freq= 0, CH_0, rank 0
7465 01:02:49.152371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7466 01:02:49.152486 ==
7467 01:02:49.155694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7468 01:02:49.162309 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7469 01:02:49.165872 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7470 01:02:49.172175 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7471 01:02:49.180895 [CA 0] Center 43 (13~73) winsize 61
7472 01:02:49.183875 [CA 1] Center 43 (13~73) winsize 61
7473 01:02:49.186973 [CA 2] Center 38 (8~68) winsize 61
7474 01:02:49.190508 [CA 3] Center 37 (8~67) winsize 60
7475 01:02:49.193864 [CA 4] Center 36 (6~66) winsize 61
7476 01:02:49.197035 [CA 5] Center 35 (5~65) winsize 61
7477 01:02:49.197149
7478 01:02:49.200627 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7479 01:02:49.200738
7480 01:02:49.203894 [CATrainingPosCal] consider 1 rank data
7481 01:02:49.207126 u2DelayCellTimex100 = 285/100 ps
7482 01:02:49.210180 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7483 01:02:49.217066 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7484 01:02:49.220714 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7485 01:02:49.224128 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7486 01:02:49.226895 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7487 01:02:49.230285 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7488 01:02:49.230396
7489 01:02:49.233514 CA PerBit enable=1, Macro0, CA PI delay=35
7490 01:02:49.233627
7491 01:02:49.237156 [CBTSetCACLKResult] CA Dly = 35
7492 01:02:49.240426 CS Dly: 9 (0~40)
7493 01:02:49.243836 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7494 01:02:49.246992 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7495 01:02:49.247103 ==
7496 01:02:49.250161 Dram Type= 6, Freq= 0, CH_0, rank 1
7497 01:02:49.254124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7498 01:02:49.254237 ==
7499 01:02:49.260284 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7500 01:02:49.263699 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7501 01:02:49.270193 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7502 01:02:49.273679 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7503 01:02:49.283895 [CA 0] Center 43 (14~73) winsize 60
7504 01:02:49.287067 [CA 1] Center 43 (13~73) winsize 61
7505 01:02:49.290411 [CA 2] Center 38 (9~67) winsize 59
7506 01:02:49.293808 [CA 3] Center 38 (8~68) winsize 61
7507 01:02:49.296776 [CA 4] Center 37 (7~67) winsize 61
7508 01:02:49.300215 [CA 5] Center 36 (6~66) winsize 61
7509 01:02:49.300329
7510 01:02:49.303536 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7511 01:02:49.303647
7512 01:02:49.306936 [CATrainingPosCal] consider 2 rank data
7513 01:02:49.309916 u2DelayCellTimex100 = 285/100 ps
7514 01:02:49.313482 CA0 delay=43 (14~73),Diff = 8 PI (27 cell)
7515 01:02:49.320582 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7516 01:02:49.323377 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7517 01:02:49.326602 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7518 01:02:49.330288 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7519 01:02:49.333392 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7520 01:02:49.333502
7521 01:02:49.336626 CA PerBit enable=1, Macro0, CA PI delay=35
7522 01:02:49.336738
7523 01:02:49.340026 [CBTSetCACLKResult] CA Dly = 35
7524 01:02:49.343341 CS Dly: 10 (0~43)
7525 01:02:49.346775 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7526 01:02:49.349860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7527 01:02:49.349992
7528 01:02:49.353395 ----->DramcWriteLeveling(PI) begin...
7529 01:02:49.353508 ==
7530 01:02:49.356501 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 01:02:49.363376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 01:02:49.363494 ==
7533 01:02:49.366572 Write leveling (Byte 0): 36 => 36
7534 01:02:49.366684 Write leveling (Byte 1): 30 => 30
7535 01:02:49.369931 DramcWriteLeveling(PI) end<-----
7536 01:02:49.370077
7537 01:02:49.370177 ==
7538 01:02:49.373232 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 01:02:49.379823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 01:02:49.379940 ==
7541 01:02:49.382979 [Gating] SW mode calibration
7542 01:02:49.390106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7543 01:02:49.393114 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7544 01:02:49.399761 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 01:02:49.403318 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 01:02:49.406552 1 4 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7547 01:02:49.413283 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7548 01:02:49.416388 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7549 01:02:49.419775 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
7550 01:02:49.426427 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 01:02:49.430093 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 01:02:49.433170 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 01:02:49.436442 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 01:02:49.443045 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7555 01:02:49.446774 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7556 01:02:49.449880 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7557 01:02:49.456523 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7558 01:02:49.459771 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 01:02:49.462915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 01:02:49.469927 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 01:02:49.473070 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 01:02:49.476374 1 6 8 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7563 01:02:49.482834 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7564 01:02:49.485999 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7565 01:02:49.489453 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7566 01:02:49.496241 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 01:02:49.499452 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 01:02:49.502697 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 01:02:49.509620 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 01:02:49.512725 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 01:02:49.516122 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 01:02:49.522937 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7573 01:02:49.526466 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7574 01:02:49.529397 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 01:02:49.536334 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 01:02:49.539485 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 01:02:49.542936 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 01:02:49.549201 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 01:02:49.552646 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 01:02:49.556238 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 01:02:49.562869 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 01:02:49.566461 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 01:02:49.569380 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 01:02:49.575707 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 01:02:49.579139 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 01:02:49.582713 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 01:02:49.586336 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 01:02:49.592464 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7589 01:02:49.595676 Total UI for P1: 0, mck2ui 16
7590 01:02:49.599349 best dqsien dly found for B0: ( 1, 9, 10)
7591 01:02:49.602302 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 01:02:49.605804 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 01:02:49.612649 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 01:02:49.615918 Total UI for P1: 0, mck2ui 16
7595 01:02:49.619019 best dqsien dly found for B1: ( 1, 9, 22)
7596 01:02:49.622222 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7597 01:02:49.626319 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7598 01:02:49.626428
7599 01:02:49.629052 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7600 01:02:49.632410 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7601 01:02:49.636057 [Gating] SW calibration Done
7602 01:02:49.636166 ==
7603 01:02:49.639275 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 01:02:49.642140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 01:02:49.642253 ==
7606 01:02:49.645744 RX Vref Scan: 0
7607 01:02:49.645854
7608 01:02:49.649003 RX Vref 0 -> 0, step: 1
7609 01:02:49.649112
7610 01:02:49.649212 RX Delay 0 -> 252, step: 8
7611 01:02:49.655433 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7612 01:02:49.659263 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7613 01:02:49.662470 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7614 01:02:49.665551 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7615 01:02:49.668804 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7616 01:02:49.672710 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7617 01:02:49.678613 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7618 01:02:49.682205 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7619 01:02:49.685114 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7620 01:02:49.688721 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7621 01:02:49.695315 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7622 01:02:49.698591 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7623 01:02:49.701925 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7624 01:02:49.705256 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7625 01:02:49.708609 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7626 01:02:49.715171 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7627 01:02:49.715287 ==
7628 01:02:49.718409 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 01:02:49.721586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 01:02:49.721697 ==
7631 01:02:49.721798 DQS Delay:
7632 01:02:49.725509 DQS0 = 0, DQS1 = 0
7633 01:02:49.725619 DQM Delay:
7634 01:02:49.728561 DQM0 = 138, DQM1 = 127
7635 01:02:49.728670 DQ Delay:
7636 01:02:49.732089 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7637 01:02:49.735341 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7638 01:02:49.738529 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7639 01:02:49.742009 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7640 01:02:49.742118
7641 01:02:49.742220
7642 01:02:49.742314 ==
7643 01:02:49.745176 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 01:02:49.751951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 01:02:49.752063 ==
7646 01:02:49.752159
7647 01:02:49.752255
7648 01:02:49.752347 TX Vref Scan disable
7649 01:02:49.755561 == TX Byte 0 ==
7650 01:02:49.758952 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7651 01:02:49.765898 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7652 01:02:49.766017 == TX Byte 1 ==
7653 01:02:49.768854 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7654 01:02:49.775488 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7655 01:02:49.775598 ==
7656 01:02:49.778978 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 01:02:49.782087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 01:02:49.782197 ==
7659 01:02:49.794751
7660 01:02:49.798140 TX Vref early break, caculate TX vref
7661 01:02:49.801252 TX Vref=16, minBit 2, minWin=23, winSum=377
7662 01:02:49.804623 TX Vref=18, minBit 4, minWin=23, winSum=394
7663 01:02:49.808134 TX Vref=20, minBit 0, minWin=24, winSum=396
7664 01:02:49.811358 TX Vref=22, minBit 0, minWin=25, winSum=409
7665 01:02:49.814852 TX Vref=24, minBit 0, minWin=25, winSum=419
7666 01:02:49.821656 TX Vref=26, minBit 6, minWin=25, winSum=420
7667 01:02:49.825226 TX Vref=28, minBit 0, minWin=25, winSum=426
7668 01:02:49.828121 TX Vref=30, minBit 0, minWin=25, winSum=421
7669 01:02:49.831346 TX Vref=32, minBit 0, minWin=25, winSum=410
7670 01:02:49.834920 TX Vref=34, minBit 1, minWin=24, winSum=398
7671 01:02:49.841338 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
7672 01:02:49.841448
7673 01:02:49.844684 Final TX Range 0 Vref 28
7674 01:02:49.844798
7675 01:02:49.844896 ==
7676 01:02:49.847953 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 01:02:49.851122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 01:02:49.851231 ==
7679 01:02:49.851331
7680 01:02:49.851425
7681 01:02:49.854692 TX Vref Scan disable
7682 01:02:49.861282 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7683 01:02:49.861395 == TX Byte 0 ==
7684 01:02:49.864840 u2DelayCellOfst[0]=13 cells (4 PI)
7685 01:02:49.868060 u2DelayCellOfst[1]=17 cells (5 PI)
7686 01:02:49.871249 u2DelayCellOfst[2]=10 cells (3 PI)
7687 01:02:49.874572 u2DelayCellOfst[3]=10 cells (3 PI)
7688 01:02:49.877684 u2DelayCellOfst[4]=6 cells (2 PI)
7689 01:02:49.881282 u2DelayCellOfst[5]=0 cells (0 PI)
7690 01:02:49.884869 u2DelayCellOfst[6]=17 cells (5 PI)
7691 01:02:49.887721 u2DelayCellOfst[7]=13 cells (4 PI)
7692 01:02:49.890979 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7693 01:02:49.894580 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 01:02:49.897781 == TX Byte 1 ==
7695 01:02:49.897893 u2DelayCellOfst[8]=0 cells (0 PI)
7696 01:02:49.901121 u2DelayCellOfst[9]=0 cells (0 PI)
7697 01:02:49.904464 u2DelayCellOfst[10]=10 cells (3 PI)
7698 01:02:49.907775 u2DelayCellOfst[11]=3 cells (1 PI)
7699 01:02:49.910874 u2DelayCellOfst[12]=13 cells (4 PI)
7700 01:02:49.914334 u2DelayCellOfst[13]=10 cells (3 PI)
7701 01:02:49.917508 u2DelayCellOfst[14]=17 cells (5 PI)
7702 01:02:49.920947 u2DelayCellOfst[15]=10 cells (3 PI)
7703 01:02:49.924457 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7704 01:02:49.930667 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7705 01:02:49.930777 DramC Write-DBI on
7706 01:02:49.930877 ==
7707 01:02:49.934197 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 01:02:49.937602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 01:02:49.940644 ==
7710 01:02:49.940753
7711 01:02:49.940852
7712 01:02:49.940948 TX Vref Scan disable
7713 01:02:49.944323 == TX Byte 0 ==
7714 01:02:49.948175 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7715 01:02:49.951275 == TX Byte 1 ==
7716 01:02:49.954203 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7717 01:02:49.957596 DramC Write-DBI off
7718 01:02:49.957708
7719 01:02:49.957807 [DATLAT]
7720 01:02:49.957905 Freq=1600, CH0 RK0
7721 01:02:49.958007
7722 01:02:49.961167 DATLAT Default: 0xf
7723 01:02:49.961275 0, 0xFFFF, sum = 0
7724 01:02:49.964155 1, 0xFFFF, sum = 0
7725 01:02:49.967534 2, 0xFFFF, sum = 0
7726 01:02:49.967643 3, 0xFFFF, sum = 0
7727 01:02:49.970885 4, 0xFFFF, sum = 0
7728 01:02:49.971000 5, 0xFFFF, sum = 0
7729 01:02:49.974432 6, 0xFFFF, sum = 0
7730 01:02:49.974543 7, 0xFFFF, sum = 0
7731 01:02:49.977708 8, 0xFFFF, sum = 0
7732 01:02:49.977818 9, 0xFFFF, sum = 0
7733 01:02:49.981117 10, 0xFFFF, sum = 0
7734 01:02:49.981230 11, 0xFFFF, sum = 0
7735 01:02:49.984159 12, 0xFFFF, sum = 0
7736 01:02:49.984269 13, 0xFFFF, sum = 0
7737 01:02:49.987707 14, 0x0, sum = 1
7738 01:02:49.987820 15, 0x0, sum = 2
7739 01:02:49.991188 16, 0x0, sum = 3
7740 01:02:49.991302 17, 0x0, sum = 4
7741 01:02:49.994353 best_step = 15
7742 01:02:49.994464
7743 01:02:49.994560 ==
7744 01:02:49.997696 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 01:02:50.000928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 01:02:50.001038 ==
7747 01:02:50.001139 RX Vref Scan: 1
7748 01:02:50.001235
7749 01:02:50.004380 Set Vref Range= 24 -> 127
7750 01:02:50.004491
7751 01:02:50.007918 RX Vref 24 -> 127, step: 1
7752 01:02:50.008029
7753 01:02:50.011098 RX Delay 19 -> 252, step: 4
7754 01:02:50.011211
7755 01:02:50.014516 Set Vref, RX VrefLevel [Byte0]: 24
7756 01:02:50.017599 [Byte1]: 24
7757 01:02:50.017709
7758 01:02:50.020935 Set Vref, RX VrefLevel [Byte0]: 25
7759 01:02:50.024334 [Byte1]: 25
7760 01:02:50.024443
7761 01:02:50.027598 Set Vref, RX VrefLevel [Byte0]: 26
7762 01:02:50.030796 [Byte1]: 26
7763 01:02:50.034696
7764 01:02:50.034804 Set Vref, RX VrefLevel [Byte0]: 27
7765 01:02:50.038063 [Byte1]: 27
7766 01:02:50.042214
7767 01:02:50.042323 Set Vref, RX VrefLevel [Byte0]: 28
7768 01:02:50.045860 [Byte1]: 28
7769 01:02:50.049692
7770 01:02:50.049803 Set Vref, RX VrefLevel [Byte0]: 29
7771 01:02:50.052998 [Byte1]: 29
7772 01:02:50.057318
7773 01:02:50.057428 Set Vref, RX VrefLevel [Byte0]: 30
7774 01:02:50.060756 [Byte1]: 30
7775 01:02:50.064945
7776 01:02:50.065053 Set Vref, RX VrefLevel [Byte0]: 31
7777 01:02:50.068334 [Byte1]: 31
7778 01:02:50.072637
7779 01:02:50.072749 Set Vref, RX VrefLevel [Byte0]: 32
7780 01:02:50.075961 [Byte1]: 32
7781 01:02:50.080236
7782 01:02:50.080348 Set Vref, RX VrefLevel [Byte0]: 33
7783 01:02:50.083312 [Byte1]: 33
7784 01:02:50.087786
7785 01:02:50.087899 Set Vref, RX VrefLevel [Byte0]: 34
7786 01:02:50.090945 [Byte1]: 34
7787 01:02:50.095399
7788 01:02:50.095511 Set Vref, RX VrefLevel [Byte0]: 35
7789 01:02:50.098598 [Byte1]: 35
7790 01:02:50.102915
7791 01:02:50.103027 Set Vref, RX VrefLevel [Byte0]: 36
7792 01:02:50.106186 [Byte1]: 36
7793 01:02:50.110434
7794 01:02:50.110544 Set Vref, RX VrefLevel [Byte0]: 37
7795 01:02:50.113677 [Byte1]: 37
7796 01:02:50.118067
7797 01:02:50.118176 Set Vref, RX VrefLevel [Byte0]: 38
7798 01:02:50.121543 [Byte1]: 38
7799 01:02:50.125601
7800 01:02:50.125713 Set Vref, RX VrefLevel [Byte0]: 39
7801 01:02:50.128973 [Byte1]: 39
7802 01:02:50.133193
7803 01:02:50.133305 Set Vref, RX VrefLevel [Byte0]: 40
7804 01:02:50.136758 [Byte1]: 40
7805 01:02:50.140874
7806 01:02:50.140982 Set Vref, RX VrefLevel [Byte0]: 41
7807 01:02:50.143874 [Byte1]: 41
7808 01:02:50.148089
7809 01:02:50.148197 Set Vref, RX VrefLevel [Byte0]: 42
7810 01:02:50.151588 [Byte1]: 42
7811 01:02:50.155884
7812 01:02:50.155995 Set Vref, RX VrefLevel [Byte0]: 43
7813 01:02:50.158915 [Byte1]: 43
7814 01:02:50.163498
7815 01:02:50.163606 Set Vref, RX VrefLevel [Byte0]: 44
7816 01:02:50.166643 [Byte1]: 44
7817 01:02:50.171162
7818 01:02:50.171274 Set Vref, RX VrefLevel [Byte0]: 45
7819 01:02:50.174133 [Byte1]: 45
7820 01:02:50.178576
7821 01:02:50.178688 Set Vref, RX VrefLevel [Byte0]: 46
7822 01:02:50.181842 [Byte1]: 46
7823 01:02:50.186185
7824 01:02:50.186294 Set Vref, RX VrefLevel [Byte0]: 47
7825 01:02:50.189441 [Byte1]: 47
7826 01:02:50.193597
7827 01:02:50.193707 Set Vref, RX VrefLevel [Byte0]: 48
7828 01:02:50.197420 [Byte1]: 48
7829 01:02:50.201200
7830 01:02:50.201309 Set Vref, RX VrefLevel [Byte0]: 49
7831 01:02:50.204701 [Byte1]: 49
7832 01:02:50.208659
7833 01:02:50.208772 Set Vref, RX VrefLevel [Byte0]: 50
7834 01:02:50.211878 [Byte1]: 50
7835 01:02:50.216506
7836 01:02:50.216615 Set Vref, RX VrefLevel [Byte0]: 51
7837 01:02:50.219485 [Byte1]: 51
7838 01:02:50.224194
7839 01:02:50.224304 Set Vref, RX VrefLevel [Byte0]: 52
7840 01:02:50.227713 [Byte1]: 52
7841 01:02:50.231598
7842 01:02:50.231708 Set Vref, RX VrefLevel [Byte0]: 53
7843 01:02:50.234757 [Byte1]: 53
7844 01:02:50.239227
7845 01:02:50.239336 Set Vref, RX VrefLevel [Byte0]: 54
7846 01:02:50.242479 [Byte1]: 54
7847 01:02:50.246588
7848 01:02:50.246699 Set Vref, RX VrefLevel [Byte0]: 55
7849 01:02:50.250204 [Byte1]: 55
7850 01:02:50.254212
7851 01:02:50.254323 Set Vref, RX VrefLevel [Byte0]: 56
7852 01:02:50.257606 [Byte1]: 56
7853 01:02:50.261807
7854 01:02:50.261918 Set Vref, RX VrefLevel [Byte0]: 57
7855 01:02:50.265078 [Byte1]: 57
7856 01:02:50.269384
7857 01:02:50.269493 Set Vref, RX VrefLevel [Byte0]: 58
7858 01:02:50.273531 [Byte1]: 58
7859 01:02:50.277035
7860 01:02:50.277144 Set Vref, RX VrefLevel [Byte0]: 59
7861 01:02:50.280059 [Byte1]: 59
7862 01:02:50.284618
7863 01:02:50.284728 Set Vref, RX VrefLevel [Byte0]: 60
7864 01:02:50.288235 [Byte1]: 60
7865 01:02:50.292171
7866 01:02:50.292284 Set Vref, RX VrefLevel [Byte0]: 61
7867 01:02:50.295265 [Byte1]: 61
7868 01:02:50.299587
7869 01:02:50.299699 Set Vref, RX VrefLevel [Byte0]: 62
7870 01:02:50.303179 [Byte1]: 62
7871 01:02:50.307278
7872 01:02:50.307386 Set Vref, RX VrefLevel [Byte0]: 63
7873 01:02:50.310757 [Byte1]: 63
7874 01:02:50.314939
7875 01:02:50.315049 Set Vref, RX VrefLevel [Byte0]: 64
7876 01:02:50.318284 [Byte1]: 64
7877 01:02:50.322409
7878 01:02:50.322522 Set Vref, RX VrefLevel [Byte0]: 65
7879 01:02:50.325956 [Byte1]: 65
7880 01:02:50.329912
7881 01:02:50.330054 Set Vref, RX VrefLevel [Byte0]: 66
7882 01:02:50.333140 [Byte1]: 66
7883 01:02:50.337727
7884 01:02:50.337835 Set Vref, RX VrefLevel [Byte0]: 67
7885 01:02:50.340952 [Byte1]: 67
7886 01:02:50.345089
7887 01:02:50.345202 Set Vref, RX VrefLevel [Byte0]: 68
7888 01:02:50.348480 [Byte1]: 68
7889 01:02:50.352700
7890 01:02:50.352812 Set Vref, RX VrefLevel [Byte0]: 69
7891 01:02:50.355982 [Byte1]: 69
7892 01:02:50.360476
7893 01:02:50.360585 Set Vref, RX VrefLevel [Byte0]: 70
7894 01:02:50.363439 [Byte1]: 70
7895 01:02:50.368003
7896 01:02:50.368115 Set Vref, RX VrefLevel [Byte0]: 71
7897 01:02:50.371514 [Byte1]: 71
7898 01:02:50.375810
7899 01:02:50.375917 Set Vref, RX VrefLevel [Byte0]: 72
7900 01:02:50.378819 [Byte1]: 72
7901 01:02:50.383008
7902 01:02:50.383120 Set Vref, RX VrefLevel [Byte0]: 73
7903 01:02:50.386345 [Byte1]: 73
7904 01:02:50.390332
7905 01:02:50.390440 Set Vref, RX VrefLevel [Byte0]: 74
7906 01:02:50.393791 [Byte1]: 74
7907 01:02:50.398237
7908 01:02:50.398346 Set Vref, RX VrefLevel [Byte0]: 75
7909 01:02:50.401621 [Byte1]: 75
7910 01:02:50.405585
7911 01:02:50.405694 Set Vref, RX VrefLevel [Byte0]: 76
7912 01:02:50.408928 [Byte1]: 76
7913 01:02:50.413265
7914 01:02:50.413374 Set Vref, RX VrefLevel [Byte0]: 77
7915 01:02:50.416610 [Byte1]: 77
7916 01:02:50.420727
7917 01:02:50.420838 Set Vref, RX VrefLevel [Byte0]: 78
7918 01:02:50.423977 [Byte1]: 78
7919 01:02:50.428270
7920 01:02:50.428384 Set Vref, RX VrefLevel [Byte0]: 79
7921 01:02:50.432009 [Byte1]: 79
7922 01:02:50.436044
7923 01:02:50.436156 Set Vref, RX VrefLevel [Byte0]: 80
7924 01:02:50.439494 [Byte1]: 80
7925 01:02:50.443528
7926 01:02:50.443641 Set Vref, RX VrefLevel [Byte0]: 81
7927 01:02:50.446982 [Byte1]: 81
7928 01:02:50.451097
7929 01:02:50.451214 Final RX Vref Byte 0 = 58 to rank0
7930 01:02:50.454957 Final RX Vref Byte 1 = 61 to rank0
7931 01:02:50.457612 Final RX Vref Byte 0 = 58 to rank1
7932 01:02:50.461135 Final RX Vref Byte 1 = 61 to rank1==
7933 01:02:50.464301 Dram Type= 6, Freq= 0, CH_0, rank 0
7934 01:02:50.471013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7935 01:02:50.471127 ==
7936 01:02:50.471226 DQS Delay:
7937 01:02:50.474458 DQS0 = 0, DQS1 = 0
7938 01:02:50.474570 DQM Delay:
7939 01:02:50.474666 DQM0 = 135, DQM1 = 124
7940 01:02:50.477457 DQ Delay:
7941 01:02:50.481060 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =132
7942 01:02:50.484210 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7943 01:02:50.487592 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7944 01:02:50.490754 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7945 01:02:50.490866
7946 01:02:50.490962
7947 01:02:50.491059
7948 01:02:50.494313 [DramC_TX_OE_Calibration] TA2
7949 01:02:50.497486 Original DQ_B0 (3 6) =30, OEN = 27
7950 01:02:50.500829 Original DQ_B1 (3 6) =30, OEN = 27
7951 01:02:50.504318 24, 0x0, End_B0=24 End_B1=24
7952 01:02:50.504431 25, 0x0, End_B0=25 End_B1=25
7953 01:02:50.507780 26, 0x0, End_B0=26 End_B1=26
7954 01:02:50.510761 27, 0x0, End_B0=27 End_B1=27
7955 01:02:50.514217 28, 0x0, End_B0=28 End_B1=28
7956 01:02:50.517431 29, 0x0, End_B0=29 End_B1=29
7957 01:02:50.517541 30, 0x0, End_B0=30 End_B1=30
7958 01:02:50.520617 31, 0x4141, End_B0=30 End_B1=30
7959 01:02:50.525057 Byte0 end_step=30 best_step=27
7960 01:02:50.527386 Byte1 end_step=30 best_step=27
7961 01:02:50.530700 Byte0 TX OE(2T, 0.5T) = (3, 3)
7962 01:02:50.534199 Byte1 TX OE(2T, 0.5T) = (3, 3)
7963 01:02:50.534307
7964 01:02:50.534406
7965 01:02:50.541035 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7966 01:02:50.543934 CH0 RK0: MR19=303, MR18=1C1A
7967 01:02:50.550596 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7968 01:02:50.550710
7969 01:02:50.554006 ----->DramcWriteLeveling(PI) begin...
7970 01:02:50.554118 ==
7971 01:02:50.557509 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 01:02:50.560621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 01:02:50.560732 ==
7974 01:02:50.564155 Write leveling (Byte 0): 37 => 37
7975 01:02:50.567138 Write leveling (Byte 1): 30 => 30
7976 01:02:50.570883 DramcWriteLeveling(PI) end<-----
7977 01:02:50.570990
7978 01:02:50.571084 ==
7979 01:02:50.573714 Dram Type= 6, Freq= 0, CH_0, rank 1
7980 01:02:50.577516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 01:02:50.577639 ==
7982 01:02:50.580768 [Gating] SW mode calibration
7983 01:02:50.587285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7984 01:02:50.593633 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7985 01:02:50.596970 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 01:02:50.603837 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 01:02:50.606775 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7988 01:02:50.610088 1 4 12 | B1->B0 | 2524 3333 | 1 1 | (1 1) (0 0)
7989 01:02:50.616606 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 01:02:50.620094 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 01:02:50.623673 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 01:02:50.630317 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 01:02:50.633400 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 01:02:50.636516 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 01:02:50.643091 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7996 01:02:50.646425 1 5 12 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 0)
7997 01:02:50.649686 1 5 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7998 01:02:50.656446 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 01:02:50.659498 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 01:02:50.662856 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 01:02:50.669506 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 01:02:50.673053 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 01:02:50.676058 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
8004 01:02:50.679637 1 6 12 | B1->B0 | 3030 4141 | 0 1 | (0 0) (0 0)
8005 01:02:50.686127 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 01:02:50.689648 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 01:02:50.696464 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 01:02:50.699260 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 01:02:50.702989 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 01:02:50.706172 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 01:02:50.712531 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 01:02:50.715705 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8013 01:02:50.719127 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8014 01:02:50.725468 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 01:02:50.728892 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 01:02:50.735335 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 01:02:50.738736 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 01:02:50.742234 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 01:02:50.745357 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 01:02:50.751875 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 01:02:50.755531 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 01:02:50.758627 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 01:02:50.765137 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 01:02:50.768446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 01:02:50.772002 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 01:02:50.778464 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 01:02:50.781726 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8028 01:02:50.785155 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8029 01:02:50.791982 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8030 01:02:50.795636 Total UI for P1: 0, mck2ui 16
8031 01:02:50.799111 best dqsien dly found for B0: ( 1, 9, 10)
8032 01:02:50.802084 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8033 01:02:50.805243 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 01:02:50.808785 Total UI for P1: 0, mck2ui 16
8035 01:02:50.811870 best dqsien dly found for B1: ( 1, 9, 18)
8036 01:02:50.815387 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8037 01:02:50.818733 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8038 01:02:50.818844
8039 01:02:50.825245 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8040 01:02:50.828444 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8041 01:02:50.832052 [Gating] SW calibration Done
8042 01:02:50.832163 ==
8043 01:02:50.835081 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 01:02:50.838811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 01:02:50.838924 ==
8046 01:02:50.839025 RX Vref Scan: 0
8047 01:02:50.839123
8048 01:02:50.841886 RX Vref 0 -> 0, step: 1
8049 01:02:50.842003
8050 01:02:50.845156 RX Delay 0 -> 252, step: 8
8051 01:02:50.848642 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8052 01:02:50.851937 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8053 01:02:50.855389 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8054 01:02:50.861565 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8055 01:02:50.864860 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8056 01:02:50.868299 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8057 01:02:50.871630 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8058 01:02:50.874874 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8059 01:02:50.881618 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8060 01:02:50.884979 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8061 01:02:50.888134 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8062 01:02:50.891476 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8063 01:02:50.894884 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8064 01:02:50.901571 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8065 01:02:50.905142 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8066 01:02:50.908438 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8067 01:02:50.908550 ==
8068 01:02:50.911576 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 01:02:50.914779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 01:02:50.918084 ==
8071 01:02:50.918195 DQS Delay:
8072 01:02:50.918296 DQS0 = 0, DQS1 = 0
8073 01:02:50.921457 DQM Delay:
8074 01:02:50.921568 DQM0 = 135, DQM1 = 126
8075 01:02:50.924766 DQ Delay:
8076 01:02:50.928664 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8077 01:02:50.931451 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8078 01:02:50.934692 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8079 01:02:50.938298 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8080 01:02:50.938406
8081 01:02:50.938508
8082 01:02:50.938604 ==
8083 01:02:50.941537 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 01:02:50.944691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 01:02:50.944803 ==
8086 01:02:50.944899
8087 01:02:50.947976
8088 01:02:50.948086 TX Vref Scan disable
8089 01:02:50.951386 == TX Byte 0 ==
8090 01:02:50.954592 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8091 01:02:50.958621 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8092 01:02:50.961670 == TX Byte 1 ==
8093 01:02:50.964997 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8094 01:02:50.968280 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8095 01:02:50.968388 ==
8096 01:02:50.971334 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 01:02:50.977880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 01:02:50.978061 ==
8099 01:02:50.991665
8100 01:02:50.994773 TX Vref early break, caculate TX vref
8101 01:02:50.998093 TX Vref=16, minBit 0, minWin=23, winSum=387
8102 01:02:51.001189 TX Vref=18, minBit 0, minWin=23, winSum=400
8103 01:02:51.004640 TX Vref=20, minBit 0, minWin=24, winSum=402
8104 01:02:51.007774 TX Vref=22, minBit 8, minWin=24, winSum=417
8105 01:02:51.011205 TX Vref=24, minBit 0, minWin=25, winSum=424
8106 01:02:51.018055 TX Vref=26, minBit 0, minWin=26, winSum=428
8107 01:02:51.021211 TX Vref=28, minBit 0, minWin=25, winSum=428
8108 01:02:51.024655 TX Vref=30, minBit 0, minWin=25, winSum=423
8109 01:02:51.028432 TX Vref=32, minBit 2, minWin=24, winSum=412
8110 01:02:51.031912 TX Vref=34, minBit 2, minWin=24, winSum=406
8111 01:02:51.034712 TX Vref=36, minBit 4, minWin=23, winSum=394
8112 01:02:51.041246 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8113 01:02:51.041360
8114 01:02:51.044923 Final TX Range 0 Vref 26
8115 01:02:51.045032
8116 01:02:51.045130 ==
8117 01:02:51.048298 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 01:02:51.051024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 01:02:51.051134 ==
8120 01:02:51.051234
8121 01:02:51.051332
8122 01:02:51.054542 TX Vref Scan disable
8123 01:02:51.061559 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8124 01:02:51.061672 == TX Byte 0 ==
8125 01:02:51.064410 u2DelayCellOfst[0]=10 cells (3 PI)
8126 01:02:51.067608 u2DelayCellOfst[1]=13 cells (4 PI)
8127 01:02:51.071082 u2DelayCellOfst[2]=10 cells (3 PI)
8128 01:02:51.074318 u2DelayCellOfst[3]=13 cells (4 PI)
8129 01:02:51.077627 u2DelayCellOfst[4]=6 cells (2 PI)
8130 01:02:51.081352 u2DelayCellOfst[5]=0 cells (0 PI)
8131 01:02:51.084493 u2DelayCellOfst[6]=17 cells (5 PI)
8132 01:02:51.087940 u2DelayCellOfst[7]=13 cells (4 PI)
8133 01:02:51.091362 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8134 01:02:51.094634 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8135 01:02:51.098230 == TX Byte 1 ==
8136 01:02:51.098342 u2DelayCellOfst[8]=0 cells (0 PI)
8137 01:02:51.101097 u2DelayCellOfst[9]=0 cells (0 PI)
8138 01:02:51.104747 u2DelayCellOfst[10]=6 cells (2 PI)
8139 01:02:51.107953 u2DelayCellOfst[11]=3 cells (1 PI)
8140 01:02:51.111316 u2DelayCellOfst[12]=13 cells (4 PI)
8141 01:02:51.115078 u2DelayCellOfst[13]=13 cells (4 PI)
8142 01:02:51.117731 u2DelayCellOfst[14]=17 cells (5 PI)
8143 01:02:51.121075 u2DelayCellOfst[15]=10 cells (3 PI)
8144 01:02:51.124431 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8145 01:02:51.131410 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8146 01:02:51.131520 DramC Write-DBI on
8147 01:02:51.131617 ==
8148 01:02:51.134579 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 01:02:51.141109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 01:02:51.141222 ==
8151 01:02:51.141321
8152 01:02:51.141415
8153 01:02:51.141507 TX Vref Scan disable
8154 01:02:51.144644 == TX Byte 0 ==
8155 01:02:51.148354 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8156 01:02:51.151724 == TX Byte 1 ==
8157 01:02:51.154795 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8158 01:02:51.157900 DramC Write-DBI off
8159 01:02:51.158047
8160 01:02:51.158146 [DATLAT]
8161 01:02:51.158240 Freq=1600, CH0 RK1
8162 01:02:51.158335
8163 01:02:51.161314 DATLAT Default: 0xf
8164 01:02:51.161421 0, 0xFFFF, sum = 0
8165 01:02:51.164470 1, 0xFFFF, sum = 0
8166 01:02:51.168110 2, 0xFFFF, sum = 0
8167 01:02:51.168220 3, 0xFFFF, sum = 0
8168 01:02:51.171831 4, 0xFFFF, sum = 0
8169 01:02:51.171944 5, 0xFFFF, sum = 0
8170 01:02:51.174468 6, 0xFFFF, sum = 0
8171 01:02:51.174579 7, 0xFFFF, sum = 0
8172 01:02:51.177778 8, 0xFFFF, sum = 0
8173 01:02:51.177895 9, 0xFFFF, sum = 0
8174 01:02:51.181289 10, 0xFFFF, sum = 0
8175 01:02:51.181401 11, 0xFFFF, sum = 0
8176 01:02:51.184572 12, 0xFFFF, sum = 0
8177 01:02:51.184684 13, 0xFFFF, sum = 0
8178 01:02:51.187812 14, 0x0, sum = 1
8179 01:02:51.187923 15, 0x0, sum = 2
8180 01:02:51.191313 16, 0x0, sum = 3
8181 01:02:51.191424 17, 0x0, sum = 4
8182 01:02:51.194358 best_step = 15
8183 01:02:51.194468
8184 01:02:51.194567 ==
8185 01:02:51.197599 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 01:02:51.201128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 01:02:51.201240 ==
8188 01:02:51.204989 RX Vref Scan: 0
8189 01:02:51.205097
8190 01:02:51.205196 RX Vref 0 -> 0, step: 1
8191 01:02:51.205293
8192 01:02:51.207526 RX Delay 11 -> 252, step: 4
8193 01:02:51.211030 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8194 01:02:51.217703 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8195 01:02:51.220799 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8196 01:02:51.224758 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8197 01:02:51.227752 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8198 01:02:51.230987 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8199 01:02:51.237600 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8200 01:02:51.240805 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8201 01:02:51.244107 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8202 01:02:51.247202 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8203 01:02:51.250752 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8204 01:02:51.257531 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8205 01:02:51.260781 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8206 01:02:51.264120 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8207 01:02:51.267197 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8208 01:02:51.273826 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8209 01:02:51.273910 ==
8210 01:02:51.277101 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 01:02:51.280466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 01:02:51.280552 ==
8213 01:02:51.280618 DQS Delay:
8214 01:02:51.284091 DQS0 = 0, DQS1 = 0
8215 01:02:51.284175 DQM Delay:
8216 01:02:51.287057 DQM0 = 133, DQM1 = 123
8217 01:02:51.287141 DQ Delay:
8218 01:02:51.291032 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8219 01:02:51.293695 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8220 01:02:51.297205 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8221 01:02:51.300293 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8222 01:02:51.300377
8223 01:02:51.300443
8224 01:02:51.303893
8225 01:02:51.303976 [DramC_TX_OE_Calibration] TA2
8226 01:02:51.307341 Original DQ_B0 (3 6) =30, OEN = 27
8227 01:02:51.310236 Original DQ_B1 (3 6) =30, OEN = 27
8228 01:02:51.313595 24, 0x0, End_B0=24 End_B1=24
8229 01:02:51.316971 25, 0x0, End_B0=25 End_B1=25
8230 01:02:51.320343 26, 0x0, End_B0=26 End_B1=26
8231 01:02:51.320428 27, 0x0, End_B0=27 End_B1=27
8232 01:02:51.323725 28, 0x0, End_B0=28 End_B1=28
8233 01:02:51.326908 29, 0x0, End_B0=29 End_B1=29
8234 01:02:51.330342 30, 0x0, End_B0=30 End_B1=30
8235 01:02:51.330432 31, 0x4141, End_B0=30 End_B1=30
8236 01:02:51.333647 Byte0 end_step=30 best_step=27
8237 01:02:51.337051 Byte1 end_step=30 best_step=27
8238 01:02:51.340224 Byte0 TX OE(2T, 0.5T) = (3, 3)
8239 01:02:51.343664 Byte1 TX OE(2T, 0.5T) = (3, 3)
8240 01:02:51.343751
8241 01:02:51.343818
8242 01:02:51.350617 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8243 01:02:51.353592 CH0 RK1: MR19=303, MR18=210E
8244 01:02:51.360464 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8245 01:02:51.363552 [RxdqsGatingPostProcess] freq 1600
8246 01:02:51.370341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8247 01:02:51.370426 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 01:02:51.373841 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 01:02:51.377553 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 01:02:51.380357 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 01:02:51.383777 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 01:02:51.387105 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 01:02:51.390158 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 01:02:51.393621 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 01:02:51.396661 Pre-setting of DQS Precalculation
8256 01:02:51.400329 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8257 01:02:51.400414 ==
8258 01:02:51.403854 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 01:02:51.410049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 01:02:51.410134 ==
8261 01:02:51.413646 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 01:02:51.420539 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 01:02:51.423679 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 01:02:51.429815 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 01:02:51.437613 [CA 0] Center 40 (11~70) winsize 60
8266 01:02:51.441995 [CA 1] Center 41 (11~71) winsize 61
8267 01:02:51.444313 [CA 2] Center 37 (8~67) winsize 60
8268 01:02:51.447521 [CA 3] Center 36 (7~66) winsize 60
8269 01:02:51.451475 [CA 4] Center 37 (7~67) winsize 61
8270 01:02:51.454486 [CA 5] Center 36 (6~66) winsize 61
8271 01:02:51.454571
8272 01:02:51.457693 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8273 01:02:51.457777
8274 01:02:51.461175 [CATrainingPosCal] consider 1 rank data
8275 01:02:51.464925 u2DelayCellTimex100 = 285/100 ps
8276 01:02:51.467750 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8277 01:02:51.474427 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8278 01:02:51.477905 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8279 01:02:51.481333 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8280 01:02:51.484437 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8281 01:02:51.487528 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8282 01:02:51.487617
8283 01:02:51.491087 CA PerBit enable=1, Macro0, CA PI delay=36
8284 01:02:51.491175
8285 01:02:51.494303 [CBTSetCACLKResult] CA Dly = 36
8286 01:02:51.497607 CS Dly: 8 (0~39)
8287 01:02:51.500954 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 01:02:51.504332 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 01:02:51.504417 ==
8290 01:02:51.507462 Dram Type= 6, Freq= 0, CH_1, rank 1
8291 01:02:51.510777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 01:02:51.510861 ==
8293 01:02:51.517381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 01:02:51.520602 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 01:02:51.527554 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 01:02:51.531093 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 01:02:51.540934 [CA 0] Center 41 (12~71) winsize 60
8298 01:02:51.544497 [CA 1] Center 41 (12~71) winsize 60
8299 01:02:51.548025 [CA 2] Center 38 (9~68) winsize 60
8300 01:02:51.551329 [CA 3] Center 37 (8~67) winsize 60
8301 01:02:51.554178 [CA 4] Center 37 (8~67) winsize 60
8302 01:02:51.557631 [CA 5] Center 37 (7~67) winsize 61
8303 01:02:51.557712
8304 01:02:51.560661 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8305 01:02:51.560743
8306 01:02:51.564627 [CATrainingPosCal] consider 2 rank data
8307 01:02:51.567379 u2DelayCellTimex100 = 285/100 ps
8308 01:02:51.570899 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8309 01:02:51.577260 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8310 01:02:51.580736 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8311 01:02:51.583855 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8312 01:02:51.587258 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 01:02:51.590738 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 01:02:51.590821
8315 01:02:51.594087 CA PerBit enable=1, Macro0, CA PI delay=36
8316 01:02:51.594170
8317 01:02:51.597151 [CBTSetCACLKResult] CA Dly = 36
8318 01:02:51.600544 CS Dly: 9 (0~41)
8319 01:02:51.603843 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 01:02:51.607025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 01:02:51.607124
8322 01:02:51.610410 ----->DramcWriteLeveling(PI) begin...
8323 01:02:51.610495 ==
8324 01:02:51.613834 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 01:02:51.617174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 01:02:51.620503 ==
8327 01:02:51.620586 Write leveling (Byte 0): 26 => 26
8328 01:02:51.624157 Write leveling (Byte 1): 28 => 28
8329 01:02:51.627224 DramcWriteLeveling(PI) end<-----
8330 01:02:51.627307
8331 01:02:51.627381 ==
8332 01:02:51.630357 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 01:02:51.637076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 01:02:51.637160 ==
8335 01:02:51.640182 [Gating] SW mode calibration
8336 01:02:51.647041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8337 01:02:51.650551 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8338 01:02:51.657210 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 01:02:51.660263 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 01:02:51.663614 1 4 8 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
8341 01:02:51.670582 1 4 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8342 01:02:51.673401 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 01:02:51.677039 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 01:02:51.680601 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 01:02:51.686862 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 01:02:51.690272 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 01:02:51.693830 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8348 01:02:51.700263 1 5 8 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 0)
8349 01:02:51.703395 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8350 01:02:51.706997 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 01:02:51.713585 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 01:02:51.716784 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 01:02:51.720264 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 01:02:51.727024 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 01:02:51.730054 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 01:02:51.733266 1 6 8 | B1->B0 | 3030 3d3d | 1 0 | (0 0) (0 0)
8357 01:02:51.739953 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 01:02:51.743203 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 01:02:51.746642 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 01:02:51.753246 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 01:02:51.756776 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 01:02:51.759707 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 01:02:51.766671 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 01:02:51.769804 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8365 01:02:51.773352 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8366 01:02:51.779979 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 01:02:51.783198 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 01:02:51.786440 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 01:02:51.793727 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 01:02:51.796486 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 01:02:51.799597 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 01:02:51.806289 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 01:02:51.810620 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 01:02:51.813312 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 01:02:51.819600 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 01:02:51.822800 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 01:02:51.826061 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 01:02:51.832676 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 01:02:51.836335 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8380 01:02:51.840075 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 01:02:51.846190 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8382 01:02:51.846276 Total UI for P1: 0, mck2ui 16
8383 01:02:51.849421 best dqsien dly found for B0: ( 1, 9, 6)
8384 01:02:51.856032 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 01:02:51.860025 Total UI for P1: 0, mck2ui 16
8386 01:02:51.862697 best dqsien dly found for B1: ( 1, 9, 10)
8387 01:02:51.865930 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8388 01:02:51.869478 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8389 01:02:51.869563
8390 01:02:51.873360 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8391 01:02:51.875673 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 01:02:51.879532 [Gating] SW calibration Done
8393 01:02:51.879644 ==
8394 01:02:51.882393 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 01:02:51.885556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 01:02:51.885645 ==
8397 01:02:51.888977 RX Vref Scan: 0
8398 01:02:51.889061
8399 01:02:51.892555 RX Vref 0 -> 0, step: 1
8400 01:02:51.892639
8401 01:02:51.892706 RX Delay 0 -> 252, step: 8
8402 01:02:51.898932 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8403 01:02:51.902412 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8404 01:02:51.905540 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8405 01:02:51.909263 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8406 01:02:51.912273 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8407 01:02:51.919173 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8408 01:02:51.922414 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8409 01:02:51.925907 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8410 01:02:51.929284 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8411 01:02:51.932343 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8412 01:02:51.935992 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8413 01:02:51.942282 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8414 01:02:51.945845 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8415 01:02:51.948851 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8416 01:02:51.952529 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8417 01:02:51.959166 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8418 01:02:51.959252 ==
8419 01:02:51.962200 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 01:02:51.965315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 01:02:51.965400 ==
8422 01:02:51.965468 DQS Delay:
8423 01:02:51.968668 DQS0 = 0, DQS1 = 0
8424 01:02:51.968753 DQM Delay:
8425 01:02:51.972194 DQM0 = 136, DQM1 = 130
8426 01:02:51.972278 DQ Delay:
8427 01:02:51.975283 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8428 01:02:51.978668 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8429 01:02:51.981895 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8430 01:02:51.985802 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8431 01:02:51.985914
8432 01:02:51.986026
8433 01:02:51.988568 ==
8434 01:02:51.992108 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 01:02:51.995133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 01:02:51.995218 ==
8437 01:02:51.995285
8438 01:02:51.995348
8439 01:02:51.998820 TX Vref Scan disable
8440 01:02:51.998930 == TX Byte 0 ==
8441 01:02:52.002309 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8442 01:02:52.008574 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8443 01:02:52.008657 == TX Byte 1 ==
8444 01:02:52.012306 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8445 01:02:52.018563 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8446 01:02:52.018645 ==
8447 01:02:52.022588 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 01:02:52.025046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 01:02:52.025129 ==
8450 01:02:52.036772
8451 01:02:52.040209 TX Vref early break, caculate TX vref
8452 01:02:52.043896 TX Vref=16, minBit 15, minWin=21, winSum=369
8453 01:02:52.046630 TX Vref=18, minBit 10, minWin=21, winSum=379
8454 01:02:52.050383 TX Vref=20, minBit 9, minWin=23, winSum=390
8455 01:02:52.053607 TX Vref=22, minBit 10, minWin=23, winSum=397
8456 01:02:52.060108 TX Vref=24, minBit 10, minWin=24, winSum=410
8457 01:02:52.063591 TX Vref=26, minBit 0, minWin=25, winSum=421
8458 01:02:52.066618 TX Vref=28, minBit 9, minWin=25, winSum=419
8459 01:02:52.069816 TX Vref=30, minBit 10, minWin=24, winSum=409
8460 01:02:52.073180 TX Vref=32, minBit 12, minWin=23, winSum=397
8461 01:02:52.079985 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8462 01:02:52.080071
8463 01:02:52.083177 Final TX Range 0 Vref 26
8464 01:02:52.083261
8465 01:02:52.083326 ==
8466 01:02:52.086901 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 01:02:52.090234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 01:02:52.090318 ==
8469 01:02:52.090384
8470 01:02:52.090444
8471 01:02:52.093406 TX Vref Scan disable
8472 01:02:52.099851 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8473 01:02:52.099935 == TX Byte 0 ==
8474 01:02:52.103653 u2DelayCellOfst[0]=13 cells (4 PI)
8475 01:02:52.106626 u2DelayCellOfst[1]=6 cells (2 PI)
8476 01:02:52.109745 u2DelayCellOfst[2]=0 cells (0 PI)
8477 01:02:52.113483 u2DelayCellOfst[3]=3 cells (1 PI)
8478 01:02:52.116755 u2DelayCellOfst[4]=6 cells (2 PI)
8479 01:02:52.119753 u2DelayCellOfst[5]=17 cells (5 PI)
8480 01:02:52.123233 u2DelayCellOfst[6]=17 cells (5 PI)
8481 01:02:52.123315 u2DelayCellOfst[7]=3 cells (1 PI)
8482 01:02:52.129784 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8483 01:02:52.133282 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8484 01:02:52.133364 == TX Byte 1 ==
8485 01:02:52.136348 u2DelayCellOfst[8]=0 cells (0 PI)
8486 01:02:52.139682 u2DelayCellOfst[9]=3 cells (1 PI)
8487 01:02:52.143053 u2DelayCellOfst[10]=13 cells (4 PI)
8488 01:02:52.146430 u2DelayCellOfst[11]=3 cells (1 PI)
8489 01:02:52.149848 u2DelayCellOfst[12]=17 cells (5 PI)
8490 01:02:52.153124 u2DelayCellOfst[13]=17 cells (5 PI)
8491 01:02:52.156626 u2DelayCellOfst[14]=20 cells (6 PI)
8492 01:02:52.159697 u2DelayCellOfst[15]=17 cells (5 PI)
8493 01:02:52.163077 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8494 01:02:52.166323 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8495 01:02:52.169769 DramC Write-DBI on
8496 01:02:52.169868 ==
8497 01:02:52.172810 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 01:02:52.176485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 01:02:52.176567 ==
8500 01:02:52.176632
8501 01:02:52.179445
8502 01:02:52.179553 TX Vref Scan disable
8503 01:02:52.182980 == TX Byte 0 ==
8504 01:02:52.186335 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8505 01:02:52.189446 == TX Byte 1 ==
8506 01:02:52.193010 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8507 01:02:52.193093 DramC Write-DBI off
8508 01:02:52.193158
8509 01:02:52.196910 [DATLAT]
8510 01:02:52.196991 Freq=1600, CH1 RK0
8511 01:02:52.197055
8512 01:02:52.199382 DATLAT Default: 0xf
8513 01:02:52.199463 0, 0xFFFF, sum = 0
8514 01:02:52.202635 1, 0xFFFF, sum = 0
8515 01:02:52.202717 2, 0xFFFF, sum = 0
8516 01:02:52.206070 3, 0xFFFF, sum = 0
8517 01:02:52.206158 4, 0xFFFF, sum = 0
8518 01:02:52.209292 5, 0xFFFF, sum = 0
8519 01:02:52.209375 6, 0xFFFF, sum = 0
8520 01:02:52.213414 7, 0xFFFF, sum = 0
8521 01:02:52.216245 8, 0xFFFF, sum = 0
8522 01:02:52.216328 9, 0xFFFF, sum = 0
8523 01:02:52.219642 10, 0xFFFF, sum = 0
8524 01:02:52.219725 11, 0xFFFF, sum = 0
8525 01:02:52.223064 12, 0xFFFF, sum = 0
8526 01:02:52.223147 13, 0xFFFF, sum = 0
8527 01:02:52.226199 14, 0x0, sum = 1
8528 01:02:52.226282 15, 0x0, sum = 2
8529 01:02:52.229124 16, 0x0, sum = 3
8530 01:02:52.229206 17, 0x0, sum = 4
8531 01:02:52.232629 best_step = 15
8532 01:02:52.232711
8533 01:02:52.232776 ==
8534 01:02:52.235724 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 01:02:52.239091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 01:02:52.239174 ==
8537 01:02:52.239240 RX Vref Scan: 1
8538 01:02:52.242810
8539 01:02:52.242893 Set Vref Range= 24 -> 127
8540 01:02:52.242959
8541 01:02:52.245987 RX Vref 24 -> 127, step: 1
8542 01:02:52.246070
8543 01:02:52.248943 RX Delay 19 -> 252, step: 4
8544 01:02:52.249026
8545 01:02:52.252751 Set Vref, RX VrefLevel [Byte0]: 24
8546 01:02:52.256216 [Byte1]: 24
8547 01:02:52.256299
8548 01:02:52.259339 Set Vref, RX VrefLevel [Byte0]: 25
8549 01:02:52.262409 [Byte1]: 25
8550 01:02:52.262492
8551 01:02:52.265548 Set Vref, RX VrefLevel [Byte0]: 26
8552 01:02:52.268984 [Byte1]: 26
8553 01:02:52.272878
8554 01:02:52.272960 Set Vref, RX VrefLevel [Byte0]: 27
8555 01:02:52.276071 [Byte1]: 27
8556 01:02:52.280391
8557 01:02:52.280473 Set Vref, RX VrefLevel [Byte0]: 28
8558 01:02:52.283844 [Byte1]: 28
8559 01:02:52.288145
8560 01:02:52.288231 Set Vref, RX VrefLevel [Byte0]: 29
8561 01:02:52.291270 [Byte1]: 29
8562 01:02:52.295779
8563 01:02:52.295861 Set Vref, RX VrefLevel [Byte0]: 30
8564 01:02:52.298624 [Byte1]: 30
8565 01:02:52.303165
8566 01:02:52.303248 Set Vref, RX VrefLevel [Byte0]: 31
8567 01:02:52.306601 [Byte1]: 31
8568 01:02:52.310699
8569 01:02:52.310781 Set Vref, RX VrefLevel [Byte0]: 32
8570 01:02:52.314247 [Byte1]: 32
8571 01:02:52.318277
8572 01:02:52.318361 Set Vref, RX VrefLevel [Byte0]: 33
8573 01:02:52.321666 [Byte1]: 33
8574 01:02:52.325911
8575 01:02:52.326000 Set Vref, RX VrefLevel [Byte0]: 34
8576 01:02:52.329066 [Byte1]: 34
8577 01:02:52.333433
8578 01:02:52.333516 Set Vref, RX VrefLevel [Byte0]: 35
8579 01:02:52.336883 [Byte1]: 35
8580 01:02:52.341036
8581 01:02:52.341119 Set Vref, RX VrefLevel [Byte0]: 36
8582 01:02:52.344630 [Byte1]: 36
8583 01:02:52.348800
8584 01:02:52.348883 Set Vref, RX VrefLevel [Byte0]: 37
8585 01:02:52.351833 [Byte1]: 37
8586 01:02:52.356253
8587 01:02:52.356337 Set Vref, RX VrefLevel [Byte0]: 38
8588 01:02:52.359387 [Byte1]: 38
8589 01:02:52.363590
8590 01:02:52.363673 Set Vref, RX VrefLevel [Byte0]: 39
8591 01:02:52.367042 [Byte1]: 39
8592 01:02:52.371133
8593 01:02:52.371216 Set Vref, RX VrefLevel [Byte0]: 40
8594 01:02:52.374502 [Byte1]: 40
8595 01:02:52.378703
8596 01:02:52.378786 Set Vref, RX VrefLevel [Byte0]: 41
8597 01:02:52.381923 [Byte1]: 41
8598 01:02:52.386539
8599 01:02:52.386622 Set Vref, RX VrefLevel [Byte0]: 42
8600 01:02:52.390144 [Byte1]: 42
8601 01:02:52.393958
8602 01:02:52.394055 Set Vref, RX VrefLevel [Byte0]: 43
8603 01:02:52.397294 [Byte1]: 43
8604 01:02:52.401766
8605 01:02:52.401850 Set Vref, RX VrefLevel [Byte0]: 44
8606 01:02:52.404954 [Byte1]: 44
8607 01:02:52.409002
8608 01:02:52.409085 Set Vref, RX VrefLevel [Byte0]: 45
8609 01:02:52.412491 [Byte1]: 45
8610 01:02:52.417331
8611 01:02:52.417415 Set Vref, RX VrefLevel [Byte0]: 46
8612 01:02:52.419971 [Byte1]: 46
8613 01:02:52.424360
8614 01:02:52.424443 Set Vref, RX VrefLevel [Byte0]: 47
8615 01:02:52.427684 [Byte1]: 47
8616 01:02:52.431999
8617 01:02:52.432081 Set Vref, RX VrefLevel [Byte0]: 48
8618 01:02:52.435352 [Byte1]: 48
8619 01:02:52.439417
8620 01:02:52.439498 Set Vref, RX VrefLevel [Byte0]: 49
8621 01:02:52.443346 [Byte1]: 49
8622 01:02:52.446972
8623 01:02:52.447054 Set Vref, RX VrefLevel [Byte0]: 50
8624 01:02:52.450254 [Byte1]: 50
8625 01:02:52.454421
8626 01:02:52.454515 Set Vref, RX VrefLevel [Byte0]: 51
8627 01:02:52.457990 [Byte1]: 51
8628 01:02:52.462449
8629 01:02:52.462530 Set Vref, RX VrefLevel [Byte0]: 52
8630 01:02:52.465556 [Byte1]: 52
8631 01:02:52.469852
8632 01:02:52.469934 Set Vref, RX VrefLevel [Byte0]: 53
8633 01:02:52.472959 [Byte1]: 53
8634 01:02:52.477431
8635 01:02:52.477511 Set Vref, RX VrefLevel [Byte0]: 54
8636 01:02:52.480869 [Byte1]: 54
8637 01:02:52.485091
8638 01:02:52.485172 Set Vref, RX VrefLevel [Byte0]: 55
8639 01:02:52.488316 [Byte1]: 55
8640 01:02:52.492631
8641 01:02:52.492712 Set Vref, RX VrefLevel [Byte0]: 56
8642 01:02:52.495748 [Byte1]: 56
8643 01:02:52.500008
8644 01:02:52.500089 Set Vref, RX VrefLevel [Byte0]: 57
8645 01:02:52.503302 [Byte1]: 57
8646 01:02:52.507645
8647 01:02:52.507725 Set Vref, RX VrefLevel [Byte0]: 58
8648 01:02:52.510852 [Byte1]: 58
8649 01:02:52.515251
8650 01:02:52.515332 Set Vref, RX VrefLevel [Byte0]: 59
8651 01:02:52.518548 [Byte1]: 59
8652 01:02:52.523285
8653 01:02:52.523366 Set Vref, RX VrefLevel [Byte0]: 60
8654 01:02:52.526067 [Byte1]: 60
8655 01:02:52.530204
8656 01:02:52.530284 Set Vref, RX VrefLevel [Byte0]: 61
8657 01:02:52.533530 [Byte1]: 61
8658 01:02:52.537960
8659 01:02:52.538069 Set Vref, RX VrefLevel [Byte0]: 62
8660 01:02:52.540920 [Byte1]: 62
8661 01:02:52.545484
8662 01:02:52.545565 Set Vref, RX VrefLevel [Byte0]: 63
8663 01:02:52.548744 [Byte1]: 63
8664 01:02:52.552920
8665 01:02:52.553001 Set Vref, RX VrefLevel [Byte0]: 64
8666 01:02:52.556365 [Byte1]: 64
8667 01:02:52.560685
8668 01:02:52.560766 Set Vref, RX VrefLevel [Byte0]: 65
8669 01:02:52.564030 [Byte1]: 65
8670 01:02:52.568221
8671 01:02:52.568301 Set Vref, RX VrefLevel [Byte0]: 66
8672 01:02:52.571463 [Byte1]: 66
8673 01:02:52.575691
8674 01:02:52.575772 Set Vref, RX VrefLevel [Byte0]: 67
8675 01:02:52.579374 [Byte1]: 67
8676 01:02:52.583250
8677 01:02:52.583332 Set Vref, RX VrefLevel [Byte0]: 68
8678 01:02:52.586539 [Byte1]: 68
8679 01:02:52.591065
8680 01:02:52.591145 Set Vref, RX VrefLevel [Byte0]: 69
8681 01:02:52.594426 [Byte1]: 69
8682 01:02:52.598267
8683 01:02:52.598348 Set Vref, RX VrefLevel [Byte0]: 70
8684 01:02:52.601903 [Byte1]: 70
8685 01:02:52.605958
8686 01:02:52.606053 Set Vref, RX VrefLevel [Byte0]: 71
8687 01:02:52.609091 [Byte1]: 71
8688 01:02:52.613460
8689 01:02:52.613541 Set Vref, RX VrefLevel [Byte0]: 72
8690 01:02:52.617466 [Byte1]: 72
8691 01:02:52.621201
8692 01:02:52.621281 Set Vref, RX VrefLevel [Byte0]: 73
8693 01:02:52.624329 [Byte1]: 73
8694 01:02:52.628788
8695 01:02:52.628869 Set Vref, RX VrefLevel [Byte0]: 74
8696 01:02:52.633210 [Byte1]: 74
8697 01:02:52.636168
8698 01:02:52.636249 Set Vref, RX VrefLevel [Byte0]: 75
8699 01:02:52.639627 [Byte1]: 75
8700 01:02:52.643825
8701 01:02:52.643905 Final RX Vref Byte 0 = 59 to rank0
8702 01:02:52.647151 Final RX Vref Byte 1 = 63 to rank0
8703 01:02:52.650606 Final RX Vref Byte 0 = 59 to rank1
8704 01:02:52.653661 Final RX Vref Byte 1 = 63 to rank1==
8705 01:02:52.657228 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 01:02:52.663644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 01:02:52.663725 ==
8708 01:02:52.663790 DQS Delay:
8709 01:02:52.663849 DQS0 = 0, DQS1 = 0
8710 01:02:52.667316 DQM Delay:
8711 01:02:52.667396 DQM0 = 133, DQM1 = 130
8712 01:02:52.670799 DQ Delay:
8713 01:02:52.673995 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8714 01:02:52.676911 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8715 01:02:52.680352 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8716 01:02:52.683834 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =136
8717 01:02:52.683916
8718 01:02:52.683981
8719 01:02:52.684039
8720 01:02:52.687036 [DramC_TX_OE_Calibration] TA2
8721 01:02:52.690732 Original DQ_B0 (3 6) =30, OEN = 27
8722 01:02:52.693663 Original DQ_B1 (3 6) =30, OEN = 27
8723 01:02:52.697282 24, 0x0, End_B0=24 End_B1=24
8724 01:02:52.697368 25, 0x0, End_B0=25 End_B1=25
8725 01:02:52.700524 26, 0x0, End_B0=26 End_B1=26
8726 01:02:52.703532 27, 0x0, End_B0=27 End_B1=27
8727 01:02:52.706747 28, 0x0, End_B0=28 End_B1=28
8728 01:02:52.710236 29, 0x0, End_B0=29 End_B1=29
8729 01:02:52.710321 30, 0x0, End_B0=30 End_B1=30
8730 01:02:52.713473 31, 0x4141, End_B0=30 End_B1=30
8731 01:02:52.717158 Byte0 end_step=30 best_step=27
8732 01:02:52.720078 Byte1 end_step=30 best_step=27
8733 01:02:52.723439 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 01:02:52.726702 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 01:02:52.726802
8736 01:02:52.726900
8737 01:02:52.733285 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8738 01:02:52.736548 CH1 RK0: MR19=303, MR18=1826
8739 01:02:52.743339 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8740 01:02:52.743426
8741 01:02:52.746529 ----->DramcWriteLeveling(PI) begin...
8742 01:02:52.746617 ==
8743 01:02:52.749887 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 01:02:52.753220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 01:02:52.753306 ==
8746 01:02:52.756730 Write leveling (Byte 0): 23 => 23
8747 01:02:52.760010 Write leveling (Byte 1): 29 => 29
8748 01:02:52.763774 DramcWriteLeveling(PI) end<-----
8749 01:02:52.763860
8750 01:02:52.763946 ==
8751 01:02:52.766670 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 01:02:52.770102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 01:02:52.770188 ==
8754 01:02:52.773260 [Gating] SW mode calibration
8755 01:02:52.780361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 01:02:52.786506 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 01:02:52.789914 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 01:02:52.793357 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 01:02:52.799684 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8760 01:02:52.803427 1 4 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8761 01:02:52.806392 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 01:02:52.813768 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 01:02:52.816303 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 01:02:52.820038 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 01:02:52.826256 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 01:02:52.829558 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 01:02:52.833355 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8768 01:02:52.839680 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 0)
8769 01:02:52.843016 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 01:02:52.846304 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 01:02:52.852947 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 01:02:52.856125 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 01:02:52.859604 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 01:02:52.866133 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8775 01:02:52.869654 1 6 8 | B1->B0 | 4343 2525 | 0 0 | (0 0) (0 0)
8776 01:02:52.873095 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8777 01:02:52.879650 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 01:02:52.882839 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 01:02:52.886295 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 01:02:52.892797 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 01:02:52.896377 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 01:02:52.899631 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 01:02:52.906121 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8784 01:02:52.909593 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8785 01:02:52.913372 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 01:02:52.916404 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 01:02:52.922785 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 01:02:52.926364 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 01:02:52.929731 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 01:02:52.936204 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 01:02:52.939436 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 01:02:52.942480 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 01:02:52.949716 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 01:02:52.952595 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 01:02:52.955860 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 01:02:52.962565 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 01:02:52.966301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 01:02:52.969210 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 01:02:52.975987 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8800 01:02:52.979412 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8801 01:02:52.982508 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 01:02:52.985879 Total UI for P1: 0, mck2ui 16
8803 01:02:52.989203 best dqsien dly found for B0: ( 1, 9, 10)
8804 01:02:52.992492 Total UI for P1: 0, mck2ui 16
8805 01:02:52.995967 best dqsien dly found for B1: ( 1, 9, 10)
8806 01:02:52.999148 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8807 01:02:53.002359 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8808 01:02:53.002440
8809 01:02:53.009391 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8810 01:02:53.012545 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8811 01:02:53.015666 [Gating] SW calibration Done
8812 01:02:53.015747 ==
8813 01:02:53.019480 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 01:02:53.022623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 01:02:53.022705 ==
8816 01:02:53.022769 RX Vref Scan: 0
8817 01:02:53.022828
8818 01:02:53.025947 RX Vref 0 -> 0, step: 1
8819 01:02:53.026053
8820 01:02:53.029230 RX Delay 0 -> 252, step: 8
8821 01:02:53.032562 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8822 01:02:53.036153 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8823 01:02:53.039220 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8824 01:02:53.045918 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8825 01:02:53.049114 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8826 01:02:53.052507 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8827 01:02:53.055573 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8828 01:02:53.059044 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8829 01:02:53.065676 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8830 01:02:53.069077 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8831 01:02:53.072434 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8832 01:02:53.075628 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8833 01:02:53.078998 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8834 01:02:53.085734 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8835 01:02:53.088741 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8836 01:02:53.092094 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8837 01:02:53.092179 ==
8838 01:02:53.095460 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 01:02:53.098922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 01:02:53.102432 ==
8841 01:02:53.102517 DQS Delay:
8842 01:02:53.102601 DQS0 = 0, DQS1 = 0
8843 01:02:53.105351 DQM Delay:
8844 01:02:53.105435 DQM0 = 136, DQM1 = 132
8845 01:02:53.108793 DQ Delay:
8846 01:02:53.112361 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8847 01:02:53.115597 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8848 01:02:53.118983 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8849 01:02:53.122539 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8850 01:02:53.122624
8851 01:02:53.122709
8852 01:02:53.122789 ==
8853 01:02:53.125560 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 01:02:53.128895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 01:02:53.128981 ==
8856 01:02:53.129066
8857 01:02:53.129146
8858 01:02:53.132082 TX Vref Scan disable
8859 01:02:53.135391 == TX Byte 0 ==
8860 01:02:53.138840 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8861 01:02:53.142389 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8862 01:02:53.145494 == TX Byte 1 ==
8863 01:02:53.148777 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8864 01:02:53.152116 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8865 01:02:53.152201 ==
8866 01:02:53.155378 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 01:02:53.162241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 01:02:53.162331 ==
8869 01:02:53.173776
8870 01:02:53.177358 TX Vref early break, caculate TX vref
8871 01:02:53.180262 TX Vref=16, minBit 9, minWin=22, winSum=377
8872 01:02:53.183702 TX Vref=18, minBit 9, minWin=22, winSum=388
8873 01:02:53.187118 TX Vref=20, minBit 9, minWin=23, winSum=400
8874 01:02:53.190962 TX Vref=22, minBit 9, minWin=24, winSum=408
8875 01:02:53.193748 TX Vref=24, minBit 9, minWin=24, winSum=411
8876 01:02:53.200180 TX Vref=26, minBit 8, minWin=25, winSum=418
8877 01:02:53.203815 TX Vref=28, minBit 8, minWin=25, winSum=414
8878 01:02:53.207150 TX Vref=30, minBit 8, minWin=24, winSum=408
8879 01:02:53.210331 TX Vref=32, minBit 0, minWin=24, winSum=398
8880 01:02:53.213569 TX Vref=34, minBit 0, minWin=23, winSum=391
8881 01:02:53.220566 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 26
8882 01:02:53.220654
8883 01:02:53.223842 Final TX Range 0 Vref 26
8884 01:02:53.223928
8885 01:02:53.223995 ==
8886 01:02:53.227167 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 01:02:53.230300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 01:02:53.230385 ==
8889 01:02:53.230452
8890 01:02:53.230515
8891 01:02:53.233457 TX Vref Scan disable
8892 01:02:53.240418 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8893 01:02:53.240504 == TX Byte 0 ==
8894 01:02:53.243807 u2DelayCellOfst[0]=17 cells (5 PI)
8895 01:02:53.247156 u2DelayCellOfst[1]=10 cells (3 PI)
8896 01:02:53.250521 u2DelayCellOfst[2]=0 cells (0 PI)
8897 01:02:53.253996 u2DelayCellOfst[3]=6 cells (2 PI)
8898 01:02:53.257081 u2DelayCellOfst[4]=6 cells (2 PI)
8899 01:02:53.257164 u2DelayCellOfst[5]=17 cells (5 PI)
8900 01:02:53.260406 u2DelayCellOfst[6]=13 cells (4 PI)
8901 01:02:53.263691 u2DelayCellOfst[7]=3 cells (1 PI)
8902 01:02:53.270135 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8903 01:02:53.273655 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8904 01:02:53.273738 == TX Byte 1 ==
8905 01:02:53.276958 u2DelayCellOfst[8]=0 cells (0 PI)
8906 01:02:53.280219 u2DelayCellOfst[9]=3 cells (1 PI)
8907 01:02:53.283722 u2DelayCellOfst[10]=10 cells (3 PI)
8908 01:02:53.287215 u2DelayCellOfst[11]=3 cells (1 PI)
8909 01:02:53.290301 u2DelayCellOfst[12]=13 cells (4 PI)
8910 01:02:53.293516 u2DelayCellOfst[13]=17 cells (5 PI)
8911 01:02:53.297003 u2DelayCellOfst[14]=17 cells (5 PI)
8912 01:02:53.300342 u2DelayCellOfst[15]=17 cells (5 PI)
8913 01:02:53.303613 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8914 01:02:53.306841 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8915 01:02:53.310499 DramC Write-DBI on
8916 01:02:53.310588 ==
8917 01:02:53.313752 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 01:02:53.317039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 01:02:53.317127 ==
8920 01:02:53.317195
8921 01:02:53.317256
8922 01:02:53.320448 TX Vref Scan disable
8923 01:02:53.323600 == TX Byte 0 ==
8924 01:02:53.326818 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8925 01:02:53.330120 == TX Byte 1 ==
8926 01:02:53.333842 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8927 01:02:53.333933 DramC Write-DBI off
8928 01:02:53.334025
8929 01:02:53.336880 [DATLAT]
8930 01:02:53.336965 Freq=1600, CH1 RK1
8931 01:02:53.337032
8932 01:02:53.340295 DATLAT Default: 0xf
8933 01:02:53.340381 0, 0xFFFF, sum = 0
8934 01:02:53.343407 1, 0xFFFF, sum = 0
8935 01:02:53.343538 2, 0xFFFF, sum = 0
8936 01:02:53.346952 3, 0xFFFF, sum = 0
8937 01:02:53.347040 4, 0xFFFF, sum = 0
8938 01:02:53.349914 5, 0xFFFF, sum = 0
8939 01:02:53.350046 6, 0xFFFF, sum = 0
8940 01:02:53.353835 7, 0xFFFF, sum = 0
8941 01:02:53.353926 8, 0xFFFF, sum = 0
8942 01:02:53.357019 9, 0xFFFF, sum = 0
8943 01:02:53.360196 10, 0xFFFF, sum = 0
8944 01:02:53.360286 11, 0xFFFF, sum = 0
8945 01:02:53.363504 12, 0xFFFF, sum = 0
8946 01:02:53.363606 13, 0xFFFF, sum = 0
8947 01:02:53.366831 14, 0x0, sum = 1
8948 01:02:53.366919 15, 0x0, sum = 2
8949 01:02:53.370336 16, 0x0, sum = 3
8950 01:02:53.370421 17, 0x0, sum = 4
8951 01:02:53.370489 best_step = 15
8952 01:02:53.370551
8953 01:02:53.373488 ==
8954 01:02:53.376798 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 01:02:53.380088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 01:02:53.380175 ==
8957 01:02:53.380242 RX Vref Scan: 0
8958 01:02:53.380302
8959 01:02:53.383700 RX Vref 0 -> 0, step: 1
8960 01:02:53.383784
8961 01:02:53.386698 RX Delay 19 -> 252, step: 4
8962 01:02:53.389867 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8963 01:02:53.393662 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8964 01:02:53.400123 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8965 01:02:53.403331 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8966 01:02:53.406623 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8967 01:02:53.409733 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8968 01:02:53.413383 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8969 01:02:53.416675 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8970 01:02:53.423208 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8971 01:02:53.426723 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8972 01:02:53.429967 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8973 01:02:53.433251 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8974 01:02:53.439895 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8975 01:02:53.443213 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8976 01:02:53.446524 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8977 01:02:53.450118 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8978 01:02:53.450213 ==
8979 01:02:53.453322 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 01:02:53.456681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 01:02:53.459574 ==
8982 01:02:53.459666 DQS Delay:
8983 01:02:53.459734 DQS0 = 0, DQS1 = 0
8984 01:02:53.463271 DQM Delay:
8985 01:02:53.463358 DQM0 = 134, DQM1 = 129
8986 01:02:53.466386 DQ Delay:
8987 01:02:53.469597 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8988 01:02:53.473164 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8989 01:02:53.476162 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8990 01:02:53.479628 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =140
8991 01:02:53.479733
8992 01:02:53.479801
8993 01:02:53.479862
8994 01:02:53.482954 [DramC_TX_OE_Calibration] TA2
8995 01:02:53.485970 Original DQ_B0 (3 6) =30, OEN = 27
8996 01:02:53.489566 Original DQ_B1 (3 6) =30, OEN = 27
8997 01:02:53.492938 24, 0x0, End_B0=24 End_B1=24
8998 01:02:53.493035 25, 0x0, End_B0=25 End_B1=25
8999 01:02:53.496250 26, 0x0, End_B0=26 End_B1=26
9000 01:02:53.499307 27, 0x0, End_B0=27 End_B1=27
9001 01:02:53.502946 28, 0x0, End_B0=28 End_B1=28
9002 01:02:53.503041 29, 0x0, End_B0=29 End_B1=29
9003 01:02:53.506219 30, 0x0, End_B0=30 End_B1=30
9004 01:02:53.509250 31, 0x5151, End_B0=30 End_B1=30
9005 01:02:53.512707 Byte0 end_step=30 best_step=27
9006 01:02:53.515746 Byte1 end_step=30 best_step=27
9007 01:02:53.519383 Byte0 TX OE(2T, 0.5T) = (3, 3)
9008 01:02:53.522334 Byte1 TX OE(2T, 0.5T) = (3, 3)
9009 01:02:53.522426
9010 01:02:53.522494
9011 01:02:53.529126 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9012 01:02:53.532600 CH1 RK1: MR19=303, MR18=1C07
9013 01:02:53.538954 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9014 01:02:53.542296 [RxdqsGatingPostProcess] freq 1600
9015 01:02:53.545834 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9016 01:02:53.549178 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 01:02:53.552470 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 01:02:53.556146 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 01:02:53.559117 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 01:02:53.562432 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 01:02:53.565814 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 01:02:53.569265 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 01:02:53.572186 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 01:02:53.575516 Pre-setting of DQS Precalculation
9025 01:02:53.579274 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9026 01:02:53.585713 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9027 01:02:53.592617 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9028 01:02:53.592742
9029 01:02:53.595756
9030 01:02:53.595842 [Calibration Summary] 3200 Mbps
9031 01:02:53.598898 CH 0, Rank 0
9032 01:02:53.599000 SW Impedance : PASS
9033 01:02:53.602267 DUTY Scan : NO K
9034 01:02:53.605337 ZQ Calibration : PASS
9035 01:02:53.605428 Jitter Meter : NO K
9036 01:02:53.608973 CBT Training : PASS
9037 01:02:53.612113 Write leveling : PASS
9038 01:02:53.612204 RX DQS gating : PASS
9039 01:02:53.615324 RX DQ/DQS(RDDQC) : PASS
9040 01:02:53.619062 TX DQ/DQS : PASS
9041 01:02:53.619152 RX DATLAT : PASS
9042 01:02:53.622349 RX DQ/DQS(Engine): PASS
9043 01:02:53.625406 TX OE : PASS
9044 01:02:53.625496 All Pass.
9045 01:02:53.625564
9046 01:02:53.625626 CH 0, Rank 1
9047 01:02:53.628822 SW Impedance : PASS
9048 01:02:53.631957 DUTY Scan : NO K
9049 01:02:53.632044 ZQ Calibration : PASS
9050 01:02:53.635553 Jitter Meter : NO K
9051 01:02:53.635640 CBT Training : PASS
9052 01:02:53.638757 Write leveling : PASS
9053 01:02:53.642077 RX DQS gating : PASS
9054 01:02:53.642165 RX DQ/DQS(RDDQC) : PASS
9055 01:02:53.645558 TX DQ/DQS : PASS
9056 01:02:53.649004 RX DATLAT : PASS
9057 01:02:53.649092 RX DQ/DQS(Engine): PASS
9058 01:02:53.651941 TX OE : PASS
9059 01:02:53.652027 All Pass.
9060 01:02:53.652095
9061 01:02:53.655510 CH 1, Rank 0
9062 01:02:53.655641 SW Impedance : PASS
9063 01:02:53.658700 DUTY Scan : NO K
9064 01:02:53.661931 ZQ Calibration : PASS
9065 01:02:53.662058 Jitter Meter : NO K
9066 01:02:53.665404 CBT Training : PASS
9067 01:02:53.668474 Write leveling : PASS
9068 01:02:53.668563 RX DQS gating : PASS
9069 01:02:53.672063 RX DQ/DQS(RDDQC) : PASS
9070 01:02:53.675130 TX DQ/DQS : PASS
9071 01:02:53.675219 RX DATLAT : PASS
9072 01:02:53.678544 RX DQ/DQS(Engine): PASS
9073 01:02:53.682153 TX OE : PASS
9074 01:02:53.682268 All Pass.
9075 01:02:53.682396
9076 01:02:53.682479 CH 1, Rank 1
9077 01:02:53.685273 SW Impedance : PASS
9078 01:02:53.688440 DUTY Scan : NO K
9079 01:02:53.688539 ZQ Calibration : PASS
9080 01:02:53.691684 Jitter Meter : NO K
9081 01:02:53.691769 CBT Training : PASS
9082 01:02:53.695971 Write leveling : PASS
9083 01:02:53.698059 RX DQS gating : PASS
9084 01:02:53.698182 RX DQ/DQS(RDDQC) : PASS
9085 01:02:53.701634 TX DQ/DQS : PASS
9086 01:02:53.704793 RX DATLAT : PASS
9087 01:02:53.704876 RX DQ/DQS(Engine): PASS
9088 01:02:53.708405 TX OE : PASS
9089 01:02:53.708488 All Pass.
9090 01:02:53.708553
9091 01:02:53.711531 DramC Write-DBI on
9092 01:02:53.714751 PER_BANK_REFRESH: Hybrid Mode
9093 01:02:53.714834 TX_TRACKING: ON
9094 01:02:53.725021 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9095 01:02:53.731356 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9096 01:02:53.741276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 01:02:53.744324 [FAST_K] Save calibration result to emmc
9098 01:02:53.744410 sync common calibartion params.
9099 01:02:53.747920 sync cbt_mode0:1, 1:1
9100 01:02:53.751344 dram_init: ddr_geometry: 2
9101 01:02:53.755063 dram_init: ddr_geometry: 2
9102 01:02:53.755147 dram_init: ddr_geometry: 2
9103 01:02:53.758215 0:dram_rank_size:100000000
9104 01:02:53.761012 1:dram_rank_size:100000000
9105 01:02:53.764269 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9106 01:02:53.768023 DFS_SHUFFLE_HW_MODE: ON
9107 01:02:53.770966 dramc_set_vcore_voltage set vcore to 725000
9108 01:02:53.774357 Read voltage for 1600, 0
9109 01:02:53.774440 Vio18 = 0
9110 01:02:53.777722 Vcore = 725000
9111 01:02:53.777806 Vdram = 0
9112 01:02:53.777873 Vddq = 0
9113 01:02:53.777935 Vmddr = 0
9114 01:02:53.780965 switch to 3200 Mbps bootup
9115 01:02:53.784701 [DramcRunTimeConfig]
9116 01:02:53.784786 PHYPLL
9117 01:02:53.787676 DPM_CONTROL_AFTERK: ON
9118 01:02:53.787759 PER_BANK_REFRESH: ON
9119 01:02:53.790896 REFRESH_OVERHEAD_REDUCTION: ON
9120 01:02:53.794297 CMD_PICG_NEW_MODE: OFF
9121 01:02:53.794381 XRTWTW_NEW_MODE: ON
9122 01:02:53.797835 XRTRTR_NEW_MODE: ON
9123 01:02:53.798004 TX_TRACKING: ON
9124 01:02:53.800871 RDSEL_TRACKING: OFF
9125 01:02:53.804195 DQS Precalculation for DVFS: ON
9126 01:02:53.804280 RX_TRACKING: OFF
9127 01:02:53.804347 HW_GATING DBG: ON
9128 01:02:53.807434 ZQCS_ENABLE_LP4: ON
9129 01:02:53.810795 RX_PICG_NEW_MODE: ON
9130 01:02:53.810879 TX_PICG_NEW_MODE: ON
9131 01:02:53.813994 ENABLE_RX_DCM_DPHY: ON
9132 01:02:53.817544 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9133 01:02:53.820883 DUMMY_READ_FOR_TRACKING: OFF
9134 01:02:53.820967 !!! SPM_CONTROL_AFTERK: OFF
9135 01:02:53.824005 !!! SPM could not control APHY
9136 01:02:53.827537 IMPEDANCE_TRACKING: ON
9137 01:02:53.827624 TEMP_SENSOR: ON
9138 01:02:53.830930 HW_SAVE_FOR_SR: OFF
9139 01:02:53.833802 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9140 01:02:53.837117 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9141 01:02:53.837203 Read ODT Tracking: ON
9142 01:02:53.840508 Refresh Rate DeBounce: ON
9143 01:02:53.844027 DFS_NO_QUEUE_FLUSH: ON
9144 01:02:53.847519 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9145 01:02:53.847603 ENABLE_DFS_RUNTIME_MRW: OFF
9146 01:02:53.850371 DDR_RESERVE_NEW_MODE: ON
9147 01:02:53.853838 MR_CBT_SWITCH_FREQ: ON
9148 01:02:53.853922 =========================
9149 01:02:53.873874 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9150 01:02:53.877364 dram_init: ddr_geometry: 2
9151 01:02:53.895374 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9152 01:02:53.899147 dram_init: dram init end (result: 0)
9153 01:02:53.905268 DRAM-K: Full calibration passed in 24500 msecs
9154 01:02:53.908704 MRC: failed to locate region type 0.
9155 01:02:53.908792 DRAM rank0 size:0x100000000,
9156 01:02:53.912100 DRAM rank1 size=0x100000000
9157 01:02:53.922188 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9158 01:02:53.929275 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9159 01:02:53.935464 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9160 01:02:53.941882 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9161 01:02:53.945324 DRAM rank0 size:0x100000000,
9162 01:02:53.948604 DRAM rank1 size=0x100000000
9163 01:02:53.948688 CBMEM:
9164 01:02:53.951930 IMD: root @ 0xfffff000 254 entries.
9165 01:02:53.955538 IMD: root @ 0xffffec00 62 entries.
9166 01:02:53.958730 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9167 01:02:53.961909 WARNING: RO_VPD is uninitialized or empty.
9168 01:02:53.968653 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9169 01:02:53.975670 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9170 01:02:53.988273 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9171 01:02:53.999504 BS: romstage times (exec / console): total (unknown) / 24016 ms
9172 01:02:53.999592
9173 01:02:53.999659
9174 01:02:54.009515 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9175 01:02:54.012849 ARM64: Exception handlers installed.
9176 01:02:54.016416 ARM64: Testing exception
9177 01:02:54.019559 ARM64: Done test exception
9178 01:02:54.019644 Enumerating buses...
9179 01:02:54.023061 Show all devs... Before device enumeration.
9180 01:02:54.026368 Root Device: enabled 1
9181 01:02:54.029467 CPU_CLUSTER: 0: enabled 1
9182 01:02:54.029550 CPU: 00: enabled 1
9183 01:02:54.032938 Compare with tree...
9184 01:02:54.033020 Root Device: enabled 1
9185 01:02:54.036261 CPU_CLUSTER: 0: enabled 1
9186 01:02:54.039519 CPU: 00: enabled 1
9187 01:02:54.039601 Root Device scanning...
9188 01:02:54.042586 scan_static_bus for Root Device
9189 01:02:54.045912 CPU_CLUSTER: 0 enabled
9190 01:02:54.049409 scan_static_bus for Root Device done
9191 01:02:54.052944 scan_bus: bus Root Device finished in 8 msecs
9192 01:02:54.053026 done
9193 01:02:54.059682 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9194 01:02:54.062731 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9195 01:02:54.069790 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9196 01:02:54.072657 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9197 01:02:54.076350 Allocating resources...
9198 01:02:54.079814 Reading resources...
9199 01:02:54.083070 Root Device read_resources bus 0 link: 0
9200 01:02:54.083212 DRAM rank0 size:0x100000000,
9201 01:02:54.086394 DRAM rank1 size=0x100000000
9202 01:02:54.089307 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9203 01:02:54.093183 CPU: 00 missing read_resources
9204 01:02:54.096057 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9205 01:02:54.102604 Root Device read_resources bus 0 link: 0 done
9206 01:02:54.102696 Done reading resources.
9207 01:02:54.109472 Show resources in subtree (Root Device)...After reading.
9208 01:02:54.112584 Root Device child on link 0 CPU_CLUSTER: 0
9209 01:02:54.116156 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 01:02:54.125880 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 01:02:54.126014 CPU: 00
9212 01:02:54.129341 Root Device assign_resources, bus 0 link: 0
9213 01:02:54.132573 CPU_CLUSTER: 0 missing set_resources
9214 01:02:54.135953 Root Device assign_resources, bus 0 link: 0 done
9215 01:02:54.139291 Done setting resources.
9216 01:02:54.146614 Show resources in subtree (Root Device)...After assigning values.
9217 01:02:54.149627 Root Device child on link 0 CPU_CLUSTER: 0
9218 01:02:54.152566 CPU_CLUSTER: 0 child on link 0 CPU: 00
9219 01:02:54.162578 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9220 01:02:54.162675 CPU: 00
9221 01:02:54.165899 Done allocating resources.
9222 01:02:54.169203 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9223 01:02:54.172490 Enabling resources...
9224 01:02:54.172575 done.
9225 01:02:54.179409 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9226 01:02:54.179497 Initializing devices...
9227 01:02:54.182615 Root Device init
9228 01:02:54.182714 init hardware done!
9229 01:02:54.185878 0x00000018: ctrlr->caps
9230 01:02:54.189033 52.000 MHz: ctrlr->f_max
9231 01:02:54.189119 0.400 MHz: ctrlr->f_min
9232 01:02:54.192427 0x40ff8080: ctrlr->voltages
9233 01:02:54.192514 sclk: 390625
9234 01:02:54.196136 Bus Width = 1
9235 01:02:54.196225 sclk: 390625
9236 01:02:54.196293 Bus Width = 1
9237 01:02:54.199730 Early init status = 3
9238 01:02:54.205723 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9239 01:02:54.209082 in-header: 03 fc 00 00 01 00 00 00
9240 01:02:54.209175 in-data: 00
9241 01:02:54.215722 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9242 01:02:54.218844 in-header: 03 fd 00 00 00 00 00 00
9243 01:02:54.222483 in-data:
9244 01:02:54.225958 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9245 01:02:54.229277 in-header: 03 fc 00 00 01 00 00 00
9246 01:02:54.232334 in-data: 00
9247 01:02:54.235883 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9248 01:02:54.240049 in-header: 03 fd 00 00 00 00 00 00
9249 01:02:54.243083 in-data:
9250 01:02:54.246740 [SSUSB] Setting up USB HOST controller...
9251 01:02:54.249677 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9252 01:02:54.253058 [SSUSB] phy power-on done.
9253 01:02:54.256374 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9254 01:02:54.262852 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9255 01:02:54.266286 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9256 01:02:54.273116 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9257 01:02:54.280224 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9258 01:02:54.286380 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9259 01:02:54.293096 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9260 01:02:54.299634 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9261 01:02:54.303048 SPM: binary array size = 0x9dc
9262 01:02:54.306588 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9263 01:02:54.312921 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9264 01:02:54.319557 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9265 01:02:54.322809 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9266 01:02:54.326412 configure_display: Starting display init
9267 01:02:54.362969 anx7625_power_on_init: Init interface.
9268 01:02:54.366410 anx7625_disable_pd_protocol: Disabled PD feature.
9269 01:02:54.369864 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9270 01:02:54.397548 anx7625_start_dp_work: Secure OCM version=00
9271 01:02:54.400464 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9272 01:02:54.415526 sp_tx_get_edid_block: EDID Block = 1
9273 01:02:54.518297 Extracted contents:
9274 01:02:54.521524 header: 00 ff ff ff ff ff ff 00
9275 01:02:54.524571 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9276 01:02:54.528122 version: 01 04
9277 01:02:54.531298 basic params: 95 1f 11 78 0a
9278 01:02:54.534689 chroma info: 76 90 94 55 54 90 27 21 50 54
9279 01:02:54.538083 established: 00 00 00
9280 01:02:54.544678 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9281 01:02:54.548029 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9282 01:02:54.554373 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9283 01:02:54.560893 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9284 01:02:54.567921 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9285 01:02:54.571391 extensions: 00
9286 01:02:54.571516 checksum: fb
9287 01:02:54.571616
9288 01:02:54.574496 Manufacturer: IVO Model 57d Serial Number 0
9289 01:02:54.578076 Made week 0 of 2020
9290 01:02:54.578160 EDID version: 1.4
9291 01:02:54.580983 Digital display
9292 01:02:54.584217 6 bits per primary color channel
9293 01:02:54.584347 DisplayPort interface
9294 01:02:54.587545 Maximum image size: 31 cm x 17 cm
9295 01:02:54.590965 Gamma: 220%
9296 01:02:54.591045 Check DPMS levels
9297 01:02:54.594332 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9298 01:02:54.597567 First detailed timing is preferred timing
9299 01:02:54.601172 Established timings supported:
9300 01:02:54.604303 Standard timings supported:
9301 01:02:54.607927 Detailed timings
9302 01:02:54.611391 Hex of detail: 383680a07038204018303c0035ae10000019
9303 01:02:54.614337 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9304 01:02:54.620798 0780 0798 07c8 0820 hborder 0
9305 01:02:54.624864 0438 043b 0447 0458 vborder 0
9306 01:02:54.628443 -hsync -vsync
9307 01:02:54.628598 Did detailed timing
9308 01:02:54.634464 Hex of detail: 000000000000000000000000000000000000
9309 01:02:54.634619 Manufacturer-specified data, tag 0
9310 01:02:54.640615 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9311 01:02:54.644435 ASCII string: InfoVision
9312 01:02:54.647421 Hex of detail: 000000fe00523134304e574635205248200a
9313 01:02:54.651212 ASCII string: R140NWF5 RH
9314 01:02:54.651295 Checksum
9315 01:02:54.654121 Checksum: 0xfb (valid)
9316 01:02:54.657133 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9317 01:02:54.660891 DSI data_rate: 832800000 bps
9318 01:02:54.667755 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9319 01:02:54.670837 anx7625_parse_edid: pixelclock(138800).
9320 01:02:54.674326 hactive(1920), hsync(48), hfp(24), hbp(88)
9321 01:02:54.677336 vactive(1080), vsync(12), vfp(3), vbp(17)
9322 01:02:54.680776 anx7625_dsi_config: config dsi.
9323 01:02:54.687574 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9324 01:02:54.700285 anx7625_dsi_config: success to config DSI
9325 01:02:54.703858 anx7625_dp_start: MIPI phy setup OK.
9326 01:02:54.706993 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9327 01:02:54.710606 mtk_ddp_mode_set invalid vrefresh 60
9328 01:02:54.713717 main_disp_path_setup
9329 01:02:54.713927 ovl_layer_smi_id_en
9330 01:02:54.717699 ovl_layer_smi_id_en
9331 01:02:54.717912 ccorr_config
9332 01:02:54.718072 aal_config
9333 01:02:54.720501 gamma_config
9334 01:02:54.720660 postmask_config
9335 01:02:54.723551 dither_config
9336 01:02:54.727038 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9337 01:02:54.733738 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9338 01:02:54.737429 Root Device init finished in 551 msecs
9339 01:02:54.737766 CPU_CLUSTER: 0 init
9340 01:02:54.746997 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9341 01:02:54.750462 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9342 01:02:54.753724 APU_MBOX 0x190000b0 = 0x10001
9343 01:02:54.757292 APU_MBOX 0x190001b0 = 0x10001
9344 01:02:54.760736 APU_MBOX 0x190005b0 = 0x10001
9345 01:02:54.763876 APU_MBOX 0x190006b0 = 0x10001
9346 01:02:54.767277 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9347 01:02:54.779392 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9348 01:02:54.791888 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9349 01:02:54.798808 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9350 01:02:54.810741 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9351 01:02:54.819853 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9352 01:02:54.822893 CPU_CLUSTER: 0 init finished in 81 msecs
9353 01:02:54.826069 Devices initialized
9354 01:02:54.829448 Show all devs... After init.
9355 01:02:54.830018 Root Device: enabled 1
9356 01:02:54.832779 CPU_CLUSTER: 0: enabled 1
9357 01:02:54.836199 CPU: 00: enabled 1
9358 01:02:54.839354 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9359 01:02:54.842795 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9360 01:02:54.846203 ELOG: NV offset 0x57f000 size 0x1000
9361 01:02:54.852422 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9362 01:02:54.859187 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9363 01:02:54.862798 ELOG: Event(17) added with size 13 at 2024-01-19 01:02:14 UTC
9364 01:02:54.866356 out: cmd=0x121: 03 db 21 01 00 00 00 00
9365 01:02:54.870864 in-header: 03 1a 00 00 2c 00 00 00
9366 01:02:54.883983 in-data: 45 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 01:02:54.890557 ELOG: Event(A1) added with size 10 at 2024-01-19 01:02:14 UTC
9368 01:02:54.897592 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9369 01:02:54.904005 ELOG: Event(A0) added with size 9 at 2024-01-19 01:02:14 UTC
9370 01:02:54.907621 elog_add_boot_reason: Logged dev mode boot
9371 01:02:54.910450 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9372 01:02:54.913988 Finalize devices...
9373 01:02:54.914525 Devices finalized
9374 01:02:54.920859 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9375 01:02:54.924357 Writing coreboot table at 0xffe64000
9376 01:02:54.927263 0. 000000000010a000-0000000000113fff: RAMSTAGE
9377 01:02:54.930775 1. 0000000040000000-00000000400fffff: RAM
9378 01:02:54.934131 2. 0000000040100000-000000004032afff: RAMSTAGE
9379 01:02:54.940777 3. 000000004032b000-00000000545fffff: RAM
9380 01:02:54.944338 4. 0000000054600000-000000005465ffff: BL31
9381 01:02:54.947182 5. 0000000054660000-00000000ffe63fff: RAM
9382 01:02:54.950451 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9383 01:02:54.957355 7. 0000000100000000-000000023fffffff: RAM
9384 01:02:54.957890 Passing 5 GPIOs to payload:
9385 01:02:54.963666 NAME | PORT | POLARITY | VALUE
9386 01:02:54.966874 EC in RW | 0x000000aa | low | undefined
9387 01:02:54.973705 EC interrupt | 0x00000005 | low | undefined
9388 01:02:54.977332 TPM interrupt | 0x000000ab | high | undefined
9389 01:02:54.980286 SD card detect | 0x00000011 | high | undefined
9390 01:02:54.986848 speaker enable | 0x00000093 | high | undefined
9391 01:02:54.990437 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9392 01:02:54.993439 in-header: 03 f9 00 00 02 00 00 00
9393 01:02:54.993866 in-data: 02 00
9394 01:02:54.996722 ADC[4]: Raw value=901032 ID=7
9395 01:02:54.999637 ADC[3]: Raw value=213179 ID=1
9396 01:02:54.999720 RAM Code: 0x71
9397 01:02:55.002982 ADC[6]: Raw value=74502 ID=0
9398 01:02:55.006240 ADC[5]: Raw value=212441 ID=1
9399 01:02:55.006328 SKU Code: 0x1
9400 01:02:55.013204 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bcf0
9401 01:02:55.016456 coreboot table: 964 bytes.
9402 01:02:55.019767 IMD ROOT 0. 0xfffff000 0x00001000
9403 01:02:55.023139 IMD SMALL 1. 0xffffe000 0x00001000
9404 01:02:55.026241 RO MCACHE 2. 0xffffc000 0x00001104
9405 01:02:55.029802 CONSOLE 3. 0xfff7c000 0x00080000
9406 01:02:55.033348 FMAP 4. 0xfff7b000 0x00000452
9407 01:02:55.036658 TIME STAMP 5. 0xfff7a000 0x00000910
9408 01:02:55.039791 VBOOT WORK 6. 0xfff66000 0x00014000
9409 01:02:55.043316 RAMOOPS 7. 0xffe66000 0x00100000
9410 01:02:55.046751 COREBOOT 8. 0xffe64000 0x00002000
9411 01:02:55.047161 IMD small region:
9412 01:02:55.049715 IMD ROOT 0. 0xffffec00 0x00000400
9413 01:02:55.053593 VPD 1. 0xffffeb80 0x0000006c
9414 01:02:55.056168 MMC STATUS 2. 0xffffeb60 0x00000004
9415 01:02:55.063475 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9416 01:02:55.066288 Probing TPM: done!
9417 01:02:55.070149 Connected to device vid:did:rid of 1ae0:0028:00
9418 01:02:55.080258 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9419 01:02:55.083108 Initialized TPM device CR50 revision 0
9420 01:02:55.086678 Checking cr50 for pending updates
9421 01:02:55.090266 Reading cr50 TPM mode
9422 01:02:55.098745 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9423 01:02:55.105204 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9424 01:02:55.145789 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9425 01:02:55.148604 Checking segment from ROM address 0x40100000
9426 01:02:55.151755 Checking segment from ROM address 0x4010001c
9427 01:02:55.158654 Loading segment from ROM address 0x40100000
9428 01:02:55.159106 code (compression=0)
9429 01:02:55.168445 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9430 01:02:55.175213 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9431 01:02:55.175645 it's not compressed!
9432 01:02:55.182275 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9433 01:02:55.185349 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9434 01:02:55.205523 Loading segment from ROM address 0x4010001c
9435 01:02:55.206065 Entry Point 0x80000000
9436 01:02:55.208767 Loaded segments
9437 01:02:55.212112 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9438 01:02:55.219042 Jumping to boot code at 0x80000000(0xffe64000)
9439 01:02:55.225623 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9440 01:02:55.232138 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9441 01:02:55.239941 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9442 01:02:55.243359 Checking segment from ROM address 0x40100000
9443 01:02:55.246590 Checking segment from ROM address 0x4010001c
9444 01:02:55.253364 Loading segment from ROM address 0x40100000
9445 01:02:55.253575 code (compression=1)
9446 01:02:55.259877 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9447 01:02:55.269895 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9448 01:02:55.270021 using LZMA
9449 01:02:55.278083 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9450 01:02:55.284583 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9451 01:02:55.287948 Loading segment from ROM address 0x4010001c
9452 01:02:55.288091 Entry Point 0x54601000
9453 01:02:55.291838 Loaded segments
9454 01:02:55.294819 NOTICE: MT8192 bl31_setup
9455 01:02:55.301697 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9456 01:02:55.305303 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9457 01:02:55.308682 WARNING: region 0:
9458 01:02:55.311469 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 01:02:55.311552 WARNING: region 1:
9460 01:02:55.318190 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9461 01:02:55.321639 WARNING: region 2:
9462 01:02:55.324926 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9463 01:02:55.328671 WARNING: region 3:
9464 01:02:55.331486 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 01:02:55.334988 WARNING: region 4:
9466 01:02:55.341835 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 01:02:55.341949 WARNING: region 5:
9468 01:02:55.345147 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 01:02:55.348527 WARNING: region 6:
9470 01:02:55.351835 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 01:02:55.351912 WARNING: region 7:
9472 01:02:55.358616 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 01:02:55.365627 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9474 01:02:55.368632 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9475 01:02:55.372153 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9476 01:02:55.378841 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9477 01:02:55.382263 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9478 01:02:55.385312 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9479 01:02:55.391998 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9480 01:02:55.395312 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9481 01:02:55.398407 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9482 01:02:55.405063 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9483 01:02:55.408566 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9484 01:02:55.415507 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9485 01:02:55.418388 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9486 01:02:55.421850 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9487 01:02:55.428451 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9488 01:02:55.431971 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9489 01:02:55.435262 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9490 01:02:55.442155 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9491 01:02:55.445279 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9492 01:02:55.448438 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9493 01:02:55.455512 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9494 01:02:55.458478 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9495 01:02:55.465635 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9496 01:02:55.468813 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9497 01:02:55.472111 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9498 01:02:55.478814 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9499 01:02:55.482048 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9500 01:02:55.488756 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9501 01:02:55.492011 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9502 01:02:55.495351 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9503 01:02:55.502171 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9504 01:02:55.505257 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9505 01:02:55.508800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9506 01:02:55.515157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9507 01:02:55.518818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9508 01:02:55.522445 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9509 01:02:55.525351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9510 01:02:55.531879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9511 01:02:55.535262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9512 01:02:55.538718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9513 01:02:55.541899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9514 01:02:55.548853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9515 01:02:55.551972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9516 01:02:55.555754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9517 01:02:55.558665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9518 01:02:55.565616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9519 01:02:55.569166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9520 01:02:55.572589 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9521 01:02:55.578981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9522 01:02:55.582482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9523 01:02:55.585727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9524 01:02:55.592014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9525 01:02:55.595468 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9526 01:02:55.601973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9527 01:02:55.605307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9528 01:02:55.611898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9529 01:02:55.615503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9530 01:02:55.618510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9531 01:02:55.625266 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9532 01:02:55.628572 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9533 01:02:55.635421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9534 01:02:55.638543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9535 01:02:55.645207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9536 01:02:55.648687 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9537 01:02:55.652152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9538 01:02:55.658747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9539 01:02:55.662209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9540 01:02:55.668887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9541 01:02:55.672128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9542 01:02:55.678914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9543 01:02:55.682090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9544 01:02:55.685744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9545 01:02:55.692307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9546 01:02:55.695571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9547 01:02:55.702918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9548 01:02:55.705762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9549 01:02:55.712440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9550 01:02:55.715694 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9551 01:02:55.718904 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9552 01:02:55.725634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9553 01:02:55.728973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9554 01:02:55.735553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9555 01:02:55.738844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9556 01:02:55.745781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9557 01:02:55.748946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9558 01:02:55.752565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9559 01:02:55.759043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9560 01:02:55.762097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9561 01:02:55.769203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9562 01:02:55.772539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9563 01:02:55.778989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9564 01:02:55.782801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9565 01:02:55.785752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9566 01:02:55.792390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9567 01:02:55.795591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9568 01:02:55.802736 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9569 01:02:55.805809 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9570 01:02:55.809147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9571 01:02:55.812486 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9572 01:02:55.819469 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9573 01:02:55.822430 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9574 01:02:55.825808 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9575 01:02:55.832666 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9576 01:02:55.835855 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9577 01:02:55.842506 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9578 01:02:55.845806 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9579 01:02:55.849315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9580 01:02:55.856358 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9581 01:02:55.859702 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9582 01:02:55.866351 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9583 01:02:55.869309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9584 01:02:55.872505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9585 01:02:55.879321 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9586 01:02:55.882561 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9587 01:02:55.889375 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9588 01:02:55.892555 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9589 01:02:55.896020 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9590 01:02:55.899015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9591 01:02:55.906120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9592 01:02:55.909511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9593 01:02:55.912790 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9594 01:02:55.916021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9595 01:02:55.922517 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9596 01:02:55.926050 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9597 01:02:55.929086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9598 01:02:55.935828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9599 01:02:55.939129 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9600 01:02:55.945793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9601 01:02:55.949192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9602 01:02:55.952506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9603 01:02:55.959237 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9604 01:02:55.963148 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9605 01:02:55.965945 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9606 01:02:55.972775 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9607 01:02:55.976036 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9608 01:02:55.982436 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9609 01:02:55.985928 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9610 01:02:55.989683 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9611 01:02:55.996084 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9612 01:02:55.999252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9613 01:02:56.006267 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9614 01:02:56.009690 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9615 01:02:56.013135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9616 01:02:56.019699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9617 01:02:56.022717 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9618 01:02:56.026058 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9619 01:02:56.032696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9620 01:02:56.036107 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9621 01:02:56.043119 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9622 01:02:56.046077 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9623 01:02:56.049693 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9624 01:02:56.056290 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9625 01:02:56.059476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9626 01:02:56.062843 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9627 01:02:56.069683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9628 01:02:56.072682 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9629 01:02:56.079679 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9630 01:02:56.082918 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9631 01:02:56.086521 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9632 01:02:56.093131 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9633 01:02:56.096239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9634 01:02:56.102710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9635 01:02:56.106203 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9636 01:02:56.109658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9637 01:02:56.116177 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9638 01:02:56.119144 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9639 01:02:56.125867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9640 01:02:56.128933 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9641 01:02:56.132400 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9642 01:02:56.139191 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9643 01:02:56.142656 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9644 01:02:56.148821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9645 01:02:56.151775 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9646 01:02:56.155206 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9647 01:02:56.161752 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9648 01:02:56.165028 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9649 01:02:56.171577 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9650 01:02:56.175088 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9651 01:02:56.178876 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9652 01:02:56.185021 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9653 01:02:56.188672 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9654 01:02:56.194895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9655 01:02:56.198699 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9656 01:02:56.201870 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9657 01:02:56.208424 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9658 01:02:56.211603 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9659 01:02:56.214967 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9660 01:02:56.221763 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9661 01:02:56.224898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9662 01:02:56.231790 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9663 01:02:56.234515 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9664 01:02:56.241225 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9665 01:02:56.244973 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9666 01:02:56.251215 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9667 01:02:56.254672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9668 01:02:56.257601 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9669 01:02:56.264411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9670 01:02:56.268010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9671 01:02:56.274499 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9672 01:02:56.277582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9673 01:02:56.280779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9674 01:02:56.287685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9675 01:02:56.290744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9676 01:02:56.298051 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9677 01:02:56.300872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9678 01:02:56.307302 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9679 01:02:56.310650 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9680 01:02:56.314190 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9681 01:02:56.320682 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9682 01:02:56.324080 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9683 01:02:56.330735 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9684 01:02:56.333904 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9685 01:02:56.340814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9686 01:02:56.344055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9687 01:02:56.347459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9688 01:02:56.354338 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9689 01:02:56.357576 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9690 01:02:56.363767 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9691 01:02:56.367099 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9692 01:02:56.370476 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9693 01:02:56.376973 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9694 01:02:56.380421 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9695 01:02:56.387227 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9696 01:02:56.390633 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9697 01:02:56.396845 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9698 01:02:56.400566 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9699 01:02:56.403638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9700 01:02:56.410548 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9701 01:02:56.413681 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9702 01:02:56.417069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9703 01:02:56.423612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9704 01:02:56.426805 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9705 01:02:56.430449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9706 01:02:56.433477 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9707 01:02:56.440458 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9708 01:02:56.443530 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9709 01:02:56.447018 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9710 01:02:56.453516 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9711 01:02:56.456843 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9712 01:02:56.460451 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9713 01:02:56.466584 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9714 01:02:56.470151 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9715 01:02:56.476551 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9716 01:02:56.479805 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9717 01:02:56.483329 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9718 01:02:56.489743 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9719 01:02:56.493521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9720 01:02:56.500008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9721 01:02:56.503440 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9722 01:02:56.506527 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9723 01:02:56.512996 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9724 01:02:56.516376 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9725 01:02:56.520154 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9726 01:02:56.526356 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9727 01:02:56.529677 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9728 01:02:56.532834 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9729 01:02:56.539557 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9730 01:02:56.542987 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9731 01:02:56.545932 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9732 01:02:56.552603 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9733 01:02:56.556294 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9734 01:02:56.562644 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9735 01:02:56.566757 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9736 01:02:56.569402 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9737 01:02:56.575834 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9738 01:02:56.579517 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9739 01:02:56.582866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9740 01:02:56.589347 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9741 01:02:56.592688 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9742 01:02:56.596055 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9743 01:02:56.602634 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9744 01:02:56.606274 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9745 01:02:56.609664 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9746 01:02:56.612525 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9747 01:02:56.619359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9748 01:02:56.622436 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9749 01:02:56.625801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9750 01:02:56.630114 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9751 01:02:56.632702 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9752 01:02:56.639501 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9753 01:02:56.642914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9754 01:02:56.645804 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9755 01:02:56.652517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9756 01:02:56.655627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9757 01:02:56.662181 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9758 01:02:56.665756 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9759 01:02:56.669177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9760 01:02:56.675991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9761 01:02:56.678999 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9762 01:02:56.685456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9763 01:02:56.689180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9764 01:02:56.692726 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9765 01:02:56.698967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9766 01:02:56.702623 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9767 01:02:56.708685 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9768 01:02:56.712142 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9769 01:02:56.719221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9770 01:02:56.722226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9771 01:02:56.725411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9772 01:02:56.732134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9773 01:02:56.735276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9774 01:02:56.742232 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9775 01:02:56.745622 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9776 01:02:56.748565 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9777 01:02:56.755330 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9778 01:02:56.758597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9779 01:02:56.765139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9780 01:02:56.768569 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9781 01:02:56.771935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9782 01:02:56.779128 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9783 01:02:56.782271 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9784 01:02:56.788507 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9785 01:02:56.792095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9786 01:02:56.795080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9787 01:02:56.801496 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9788 01:02:56.805041 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9789 01:02:56.811906 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9790 01:02:56.815372 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9791 01:02:56.821774 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9792 01:02:56.824781 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9793 01:02:56.828044 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9794 01:02:56.834568 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9795 01:02:56.837954 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9796 01:02:56.844597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9797 01:02:56.847638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9798 01:02:56.851265 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9799 01:02:56.857943 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9800 01:02:56.860862 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9801 01:02:56.867776 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9802 01:02:56.870816 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9803 01:02:56.874196 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9804 01:02:56.881038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9805 01:02:56.884568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9806 01:02:56.890790 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9807 01:02:56.893927 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9808 01:02:56.900446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9809 01:02:56.903836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9810 01:02:56.907344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9811 01:02:56.913822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9812 01:02:56.916909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9813 01:02:56.923853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9814 01:02:56.927240 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9815 01:02:56.933658 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9816 01:02:56.937436 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9817 01:02:56.940785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9818 01:02:56.947056 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9819 01:02:56.951317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9820 01:02:56.957240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9821 01:02:56.960631 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9822 01:02:56.964260 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9823 01:02:56.971057 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9824 01:02:56.973854 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9825 01:02:56.980740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9826 01:02:56.983949 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9827 01:02:56.987211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9828 01:02:56.994021 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9829 01:02:56.997288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9830 01:02:57.003788 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9831 01:02:57.007079 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9832 01:02:57.013904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9833 01:02:57.017027 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9834 01:02:57.020195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9835 01:02:57.027005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9836 01:02:57.029912 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9837 01:02:57.036739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9838 01:02:57.039941 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9839 01:02:57.046965 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9840 01:02:57.049730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9841 01:02:57.056739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9842 01:02:57.059849 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9843 01:02:57.063282 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9844 01:02:57.069905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9845 01:02:57.073125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9846 01:02:57.080106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9847 01:02:57.083065 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9848 01:02:57.090139 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9849 01:02:57.093154 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9850 01:02:57.096383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9851 01:02:57.103030 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9852 01:02:57.106501 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9853 01:02:57.113085 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9854 01:02:57.116314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9855 01:02:57.122926 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9856 01:02:57.126416 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9857 01:02:57.133110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9858 01:02:57.136414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9859 01:02:57.139799 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9860 01:02:57.146293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9861 01:02:57.149814 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9862 01:02:57.156153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9863 01:02:57.159638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9864 01:02:57.166448 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9865 01:02:57.169681 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9866 01:02:57.173163 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9867 01:02:57.179698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9868 01:02:57.182752 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9869 01:02:57.189246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9870 01:02:57.192669 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9871 01:02:57.199279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9872 01:02:57.202705 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9873 01:02:57.209505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9874 01:02:57.212575 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9875 01:02:57.216039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9876 01:02:57.222650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9877 01:02:57.225731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9878 01:02:57.232377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9879 01:02:57.236016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9880 01:02:57.239289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9881 01:02:57.245657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9882 01:02:57.249175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9883 01:02:57.255597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9884 01:02:57.259059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9885 01:02:57.265852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9886 01:02:57.269107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9887 01:02:57.275415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9888 01:02:57.279140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9889 01:02:57.285885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9890 01:02:57.289219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9891 01:02:57.295803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9892 01:02:57.299134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9893 01:02:57.305768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9894 01:02:57.309095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9895 01:02:57.315892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9896 01:02:57.318880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9897 01:02:57.325628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9898 01:02:57.329000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9899 01:02:57.335790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9900 01:02:57.338767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9901 01:02:57.345773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9902 01:02:57.348697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9903 01:02:57.355075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9904 01:02:57.358355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9905 01:02:57.365114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9906 01:02:57.368186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9907 01:02:57.374837 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9908 01:02:57.374920 INFO: [APUAPC] vio 0
9909 01:02:57.381644 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9910 01:02:57.385292 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9911 01:02:57.388570 INFO: [APUAPC] D0_APC_0: 0x400510
9912 01:02:57.391650 INFO: [APUAPC] D0_APC_1: 0x0
9913 01:02:57.395129 INFO: [APUAPC] D0_APC_2: 0x1540
9914 01:02:57.398587 INFO: [APUAPC] D0_APC_3: 0x0
9915 01:02:57.401672 INFO: [APUAPC] D1_APC_0: 0xffffffff
9916 01:02:57.404901 INFO: [APUAPC] D1_APC_1: 0xffffffff
9917 01:02:57.408471 INFO: [APUAPC] D1_APC_2: 0x3fffff
9918 01:02:57.411944 INFO: [APUAPC] D1_APC_3: 0x0
9919 01:02:57.414843 INFO: [APUAPC] D2_APC_0: 0xffffffff
9920 01:02:57.418563 INFO: [APUAPC] D2_APC_1: 0xffffffff
9921 01:02:57.421518 INFO: [APUAPC] D2_APC_2: 0x3fffff
9922 01:02:57.425214 INFO: [APUAPC] D2_APC_3: 0x0
9923 01:02:57.428377 INFO: [APUAPC] D3_APC_0: 0xffffffff
9924 01:02:57.431617 INFO: [APUAPC] D3_APC_1: 0xffffffff
9925 01:02:57.435091 INFO: [APUAPC] D3_APC_2: 0x3fffff
9926 01:02:57.435175 INFO: [APUAPC] D3_APC_3: 0x0
9927 01:02:57.441687 INFO: [APUAPC] D4_APC_0: 0xffffffff
9928 01:02:57.445116 INFO: [APUAPC] D4_APC_1: 0xffffffff
9929 01:02:57.448289 INFO: [APUAPC] D4_APC_2: 0x3fffff
9930 01:02:57.448373 INFO: [APUAPC] D4_APC_3: 0x0
9931 01:02:57.451413 INFO: [APUAPC] D5_APC_0: 0xffffffff
9932 01:02:57.455190 INFO: [APUAPC] D5_APC_1: 0xffffffff
9933 01:02:57.458211 INFO: [APUAPC] D5_APC_2: 0x3fffff
9934 01:02:57.461344 INFO: [APUAPC] D5_APC_3: 0x0
9935 01:02:57.464617 INFO: [APUAPC] D6_APC_0: 0xffffffff
9936 01:02:57.468264 INFO: [APUAPC] D6_APC_1: 0xffffffff
9937 01:02:57.471269 INFO: [APUAPC] D6_APC_2: 0x3fffff
9938 01:02:57.474586 INFO: [APUAPC] D6_APC_3: 0x0
9939 01:02:57.478096 INFO: [APUAPC] D7_APC_0: 0xffffffff
9940 01:02:57.481487 INFO: [APUAPC] D7_APC_1: 0xffffffff
9941 01:02:57.484783 INFO: [APUAPC] D7_APC_2: 0x3fffff
9942 01:02:57.488097 INFO: [APUAPC] D7_APC_3: 0x0
9943 01:02:57.491137 INFO: [APUAPC] D8_APC_0: 0xffffffff
9944 01:02:57.494712 INFO: [APUAPC] D8_APC_1: 0xffffffff
9945 01:02:57.498300 INFO: [APUAPC] D8_APC_2: 0x3fffff
9946 01:02:57.501472 INFO: [APUAPC] D8_APC_3: 0x0
9947 01:02:57.504645 INFO: [APUAPC] D9_APC_0: 0xffffffff
9948 01:02:57.508546 INFO: [APUAPC] D9_APC_1: 0xffffffff
9949 01:02:57.511228 INFO: [APUAPC] D9_APC_2: 0x3fffff
9950 01:02:57.514537 INFO: [APUAPC] D9_APC_3: 0x0
9951 01:02:57.517616 INFO: [APUAPC] D10_APC_0: 0xffffffff
9952 01:02:57.521221 INFO: [APUAPC] D10_APC_1: 0xffffffff
9953 01:02:57.524447 INFO: [APUAPC] D10_APC_2: 0x3fffff
9954 01:02:57.527841 INFO: [APUAPC] D10_APC_3: 0x0
9955 01:02:57.530922 INFO: [APUAPC] D11_APC_0: 0xffffffff
9956 01:02:57.534693 INFO: [APUAPC] D11_APC_1: 0xffffffff
9957 01:02:57.537737 INFO: [APUAPC] D11_APC_2: 0x3fffff
9958 01:02:57.540720 INFO: [APUAPC] D11_APC_3: 0x0
9959 01:02:57.544328 INFO: [APUAPC] D12_APC_0: 0xffffffff
9960 01:02:57.547624 INFO: [APUAPC] D12_APC_1: 0xffffffff
9961 01:02:57.550795 INFO: [APUAPC] D12_APC_2: 0x3fffff
9962 01:02:57.554303 INFO: [APUAPC] D12_APC_3: 0x0
9963 01:02:57.557515 INFO: [APUAPC] D13_APC_0: 0xffffffff
9964 01:02:57.560942 INFO: [APUAPC] D13_APC_1: 0xffffffff
9965 01:02:57.563867 INFO: [APUAPC] D13_APC_2: 0x3fffff
9966 01:02:57.567633 INFO: [APUAPC] D13_APC_3: 0x0
9967 01:02:57.570487 INFO: [APUAPC] D14_APC_0: 0xffffffff
9968 01:02:57.573976 INFO: [APUAPC] D14_APC_1: 0xffffffff
9969 01:02:57.577357 INFO: [APUAPC] D14_APC_2: 0x3fffff
9970 01:02:57.580607 INFO: [APUAPC] D14_APC_3: 0x0
9971 01:02:57.583925 INFO: [APUAPC] D15_APC_0: 0xffffffff
9972 01:02:57.587251 INFO: [APUAPC] D15_APC_1: 0xffffffff
9973 01:02:57.590772 INFO: [APUAPC] D15_APC_2: 0x3fffff
9974 01:02:57.594010 INFO: [APUAPC] D15_APC_3: 0x0
9975 01:02:57.597046 INFO: [APUAPC] APC_CON: 0x4
9976 01:02:57.600700 INFO: [NOCDAPC] D0_APC_0: 0x0
9977 01:02:57.604189 INFO: [NOCDAPC] D0_APC_1: 0x0
9978 01:02:57.607097 INFO: [NOCDAPC] D1_APC_0: 0x0
9979 01:02:57.610579 INFO: [NOCDAPC] D1_APC_1: 0xfff
9980 01:02:57.614313 INFO: [NOCDAPC] D2_APC_0: 0x0
9981 01:02:57.614396 INFO: [NOCDAPC] D2_APC_1: 0xfff
9982 01:02:57.617268 INFO: [NOCDAPC] D3_APC_0: 0x0
9983 01:02:57.620364 INFO: [NOCDAPC] D3_APC_1: 0xfff
9984 01:02:57.623724 INFO: [NOCDAPC] D4_APC_0: 0x0
9985 01:02:57.627073 INFO: [NOCDAPC] D4_APC_1: 0xfff
9986 01:02:57.630687 INFO: [NOCDAPC] D5_APC_0: 0x0
9987 01:02:57.633701 INFO: [NOCDAPC] D5_APC_1: 0xfff
9988 01:02:57.636985 INFO: [NOCDAPC] D6_APC_0: 0x0
9989 01:02:57.640298 INFO: [NOCDAPC] D6_APC_1: 0xfff
9990 01:02:57.643792 INFO: [NOCDAPC] D7_APC_0: 0x0
9991 01:02:57.646945 INFO: [NOCDAPC] D7_APC_1: 0xfff
9992 01:02:57.647027 INFO: [NOCDAPC] D8_APC_0: 0x0
9993 01:02:57.650652 INFO: [NOCDAPC] D8_APC_1: 0xfff
9994 01:02:57.653440 INFO: [NOCDAPC] D9_APC_0: 0x0
9995 01:02:57.656832 INFO: [NOCDAPC] D9_APC_1: 0xfff
9996 01:02:57.660216 INFO: [NOCDAPC] D10_APC_0: 0x0
9997 01:02:57.663493 INFO: [NOCDAPC] D10_APC_1: 0xfff
9998 01:02:57.666931 INFO: [NOCDAPC] D11_APC_0: 0x0
9999 01:02:57.670343 INFO: [NOCDAPC] D11_APC_1: 0xfff
10000 01:02:57.673833 INFO: [NOCDAPC] D12_APC_0: 0x0
10001 01:02:57.676852 INFO: [NOCDAPC] D12_APC_1: 0xfff
10002 01:02:57.680350 INFO: [NOCDAPC] D13_APC_0: 0x0
10003 01:02:57.683632 INFO: [NOCDAPC] D13_APC_1: 0xfff
10004 01:02:57.687072 INFO: [NOCDAPC] D14_APC_0: 0x0
10005 01:02:57.690186 INFO: [NOCDAPC] D14_APC_1: 0xfff
10006 01:02:57.690269 INFO: [NOCDAPC] D15_APC_0: 0x0
10007 01:02:57.693703 INFO: [NOCDAPC] D15_APC_1: 0xfff
10008 01:02:57.696914 INFO: [NOCDAPC] APC_CON: 0x4
10009 01:02:57.700165 INFO: [APUAPC] set_apusys_apc done
10010 01:02:57.703635 INFO: [DEVAPC] devapc_init done
10011 01:02:57.706649 INFO: GICv3 without legacy support detected.
10012 01:02:57.713313 INFO: ARM GICv3 driver initialized in EL3
10013 01:02:57.716953 INFO: Maximum SPI INTID supported: 639
10014 01:02:57.720312 INFO: BL31: Initializing runtime services
10015 01:02:57.726999 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10016 01:02:57.729916 INFO: SPM: enable CPC mode
10017 01:02:57.733138 INFO: mcdi ready for mcusys-off-idle and system suspend
10018 01:02:57.736598 INFO: BL31: Preparing for EL3 exit to normal world
10019 01:02:57.743322 INFO: Entry point address = 0x80000000
10020 01:02:57.743405 INFO: SPSR = 0x8
10021 01:02:57.749562
10022 01:02:57.749644
10023 01:02:57.749709
10024 01:02:57.753089 Starting depthcharge on Spherion...
10025 01:02:57.753171
10026 01:02:57.753236 Wipe memory regions:
10027 01:02:57.753296
10028 01:02:57.753909 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10029 01:02:57.754086 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10030 01:02:57.754181 Setting prompt string to ['asurada:']
10031 01:02:57.754280 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10032 01:02:57.756395 [0x00000040000000, 0x00000054600000)
10033 01:02:57.878814
10034 01:02:57.878947 [0x00000054660000, 0x00000080000000)
10035 01:02:58.139459
10036 01:02:58.139616 [0x000000821a7280, 0x000000ffe64000)
10037 01:02:58.884283
10038 01:02:58.884435 [0x00000100000000, 0x00000240000000)
10039 01:03:00.774421
10040 01:03:00.777837 Initializing XHCI USB controller at 0x11200000.
10041 01:03:01.815419
10042 01:03:01.818680 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10043 01:03:01.818766
10044 01:03:01.818832
10045 01:03:01.818895
10046 01:03:01.819171 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 01:03:01.919560 asurada: tftpboot 192.168.201.1 12571123/tftp-deploy-vb3mdyvn/kernel/image.itb 12571123/tftp-deploy-vb3mdyvn/kernel/cmdline
10049 01:03:01.919672 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 01:03:01.919810 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10051 01:03:01.924323 tftpboot 192.168.201.1 12571123/tftp-deploy-vb3mdyvn/kernel/image.itp-deploy-vb3mdyvn/kernel/cmdline
10052 01:03:01.924408
10053 01:03:01.924473 Waiting for link
10054 01:03:02.084231
10055 01:03:02.084340 R8152: Initializing
10056 01:03:02.084407
10057 01:03:02.087574 Version 9 (ocp_data = 6010)
10058 01:03:02.087657
10059 01:03:02.090963 R8152: Done initializing
10060 01:03:02.091046
10061 01:03:02.091112 Adding net device
10062 01:03:03.963422
10063 01:03:03.963576 done.
10064 01:03:03.963646
10065 01:03:03.963708 MAC: 00:e0:4c:72:2d:d6
10066 01:03:03.963768
10067 01:03:03.966781 Sending DHCP discover... done.
10068 01:03:03.966866
10069 01:03:03.970211 Waiting for reply... done.
10070 01:03:03.970309
10071 01:03:03.973668 Sending DHCP request... done.
10072 01:03:03.973752
10073 01:03:03.976818 Waiting for reply... done.
10074 01:03:03.976901
10075 01:03:03.976968 My ip is 192.168.201.21
10076 01:03:03.977028
10077 01:03:03.980544 The DHCP server ip is 192.168.201.1
10078 01:03:03.980627
10079 01:03:03.986574 TFTP server IP predefined by user: 192.168.201.1
10080 01:03:03.986657
10081 01:03:03.993259 Bootfile predefined by user: 12571123/tftp-deploy-vb3mdyvn/kernel/image.itb
10082 01:03:03.993343
10083 01:03:03.993408 Sending tftp read request... done.
10084 01:03:03.996370
10085 01:03:03.996452 Waiting for the transfer...
10086 01:03:03.996519
10087 01:03:04.288069 00000000 ################################################################
10088 01:03:04.288212
10089 01:03:04.554560 00080000 ################################################################
10090 01:03:04.554705
10091 01:03:04.802983 00100000 ################################################################
10092 01:03:04.803138
10093 01:03:05.088217 00180000 ################################################################
10094 01:03:05.088355
10095 01:03:05.383130 00200000 ################################################################
10096 01:03:05.383276
10097 01:03:05.668836 00280000 ################################################################
10098 01:03:05.668987
10099 01:03:05.967561 00300000 ################################################################
10100 01:03:05.967739
10101 01:03:06.267734 00380000 ################################################################
10102 01:03:06.267892
10103 01:03:06.565055 00400000 ################################################################
10104 01:03:06.565206
10105 01:03:06.856761 00480000 ################################################################
10106 01:03:06.856906
10107 01:03:07.152013 00500000 ################################################################
10108 01:03:07.152155
10109 01:03:07.451503 00580000 ################################################################
10110 01:03:07.451643
10111 01:03:07.747553 00600000 ################################################################
10112 01:03:07.747702
10113 01:03:08.046374 00680000 ################################################################
10114 01:03:08.046519
10115 01:03:08.321321 00700000 ################################################################
10116 01:03:08.321466
10117 01:03:08.590549 00780000 ################################################################
10118 01:03:08.590707
10119 01:03:08.879416 00800000 ################################################################
10120 01:03:08.879566
10121 01:03:09.173687 00880000 ################################################################
10122 01:03:09.173867
10123 01:03:09.452960 00900000 ################################################################
10124 01:03:09.453118
10125 01:03:09.738739 00980000 ################################################################
10126 01:03:09.738899
10127 01:03:10.038252 00a00000 ################################################################
10128 01:03:10.038447
10129 01:03:10.338235 00a80000 ################################################################
10130 01:03:10.338394
10131 01:03:10.626196 00b00000 ################################################################
10132 01:03:10.626351
10133 01:03:10.927393 00b80000 ################################################################
10134 01:03:10.927552
10135 01:03:11.221482 00c00000 ################################################################
10136 01:03:11.221639
10137 01:03:11.517608 00c80000 ################################################################
10138 01:03:11.517769
10139 01:03:11.808538 00d00000 ################################################################
10140 01:03:11.808699
10141 01:03:12.101759 00d80000 ################################################################
10142 01:03:12.101922
10143 01:03:12.387887 00e00000 ################################################################
10144 01:03:12.388042
10145 01:03:12.672038 00e80000 ################################################################
10146 01:03:12.672196
10147 01:03:12.957058 00f00000 ################################################################
10148 01:03:12.957208
10149 01:03:13.239251 00f80000 ################################################################
10150 01:03:13.239408
10151 01:03:13.524539 01000000 ################################################################
10152 01:03:13.524700
10153 01:03:13.798728 01080000 ################################################################
10154 01:03:13.798880
10155 01:03:14.055597 01100000 ################################################################
10156 01:03:14.055752
10157 01:03:14.351975 01180000 ################################################################
10158 01:03:14.352133
10159 01:03:14.619751 01200000 ################################################################
10160 01:03:14.619950
10161 01:03:14.882316 01280000 ################################################################
10162 01:03:14.882477
10163 01:03:15.173175 01300000 ################################################################
10164 01:03:15.173324
10165 01:03:15.473017 01380000 ################################################################
10166 01:03:15.473174
10167 01:03:15.750504 01400000 ################################################################
10168 01:03:15.750663
10169 01:03:16.046024 01480000 ################################################################
10170 01:03:16.046181
10171 01:03:16.346771 01500000 ################################################################
10172 01:03:16.346926
10173 01:03:16.645065 01580000 ################################################################
10174 01:03:16.645220
10175 01:03:16.942443 01600000 ################################################################
10176 01:03:16.942603
10177 01:03:17.234957 01680000 ################################################################
10178 01:03:17.235111
10179 01:03:17.527849 01700000 ################################################################
10180 01:03:17.528010
10181 01:03:17.826699 01780000 ################################################################
10182 01:03:17.826859
10183 01:03:18.123883 01800000 ################################################################
10184 01:03:18.124038
10185 01:03:18.427296 01880000 ################################################################
10186 01:03:18.427447
10187 01:03:18.724719 01900000 ################################################################
10188 01:03:18.724898
10189 01:03:18.964074 01980000 ################################################################
10190 01:03:18.964234
10191 01:03:19.205863 01a00000 ################################################################
10192 01:03:19.206044
10193 01:03:19.451904 01a80000 ################################################################
10194 01:03:19.452062
10195 01:03:19.747402 01b00000 ################################################################
10196 01:03:19.747558
10197 01:03:20.041457 01b80000 ################################################################
10198 01:03:20.041614
10199 01:03:20.335723 01c00000 ################################################################
10200 01:03:20.335882
10201 01:03:20.629523 01c80000 ################################################################
10202 01:03:20.629679
10203 01:03:20.921856 01d00000 ################################################################
10204 01:03:20.922028
10205 01:03:21.211958 01d80000 ################################################################
10206 01:03:21.212137
10207 01:03:21.509767 01e00000 ################################################################
10208 01:03:21.509913
10209 01:03:21.793498 01e80000 ################################################################
10210 01:03:21.793648
10211 01:03:22.090342 01f00000 ################################################################
10212 01:03:22.090473
10213 01:03:22.385598 01f80000 ################################################################
10214 01:03:22.385723
10215 01:03:22.685216 02000000 ################################################################
10216 01:03:22.685350
10217 01:03:22.984017 02080000 ################################################################
10218 01:03:22.984167
10219 01:03:23.277908 02100000 ################################################################
10220 01:03:23.278053
10221 01:03:23.579469 02180000 ################################################################
10222 01:03:23.579614
10223 01:03:23.879952 02200000 ################################################################
10224 01:03:23.880083
10225 01:03:24.176713 02280000 ################################################################
10226 01:03:24.176863
10227 01:03:24.457865 02300000 ################################################################
10228 01:03:24.458066
10229 01:03:24.714708 02380000 ################################################################
10230 01:03:24.714864
10231 01:03:24.952132 02400000 ################################################################
10232 01:03:24.952316
10233 01:03:25.223211 02480000 ################################################################
10234 01:03:25.223364
10235 01:03:25.487387 02500000 ################################################################
10236 01:03:25.487519
10237 01:03:25.774854 02580000 ################################################################
10238 01:03:25.774981
10239 01:03:26.073541 02600000 ################################################################
10240 01:03:26.073674
10241 01:03:26.374054 02680000 ################################################################
10242 01:03:26.374183
10243 01:03:26.642331 02700000 ################################################################
10244 01:03:26.642476
10245 01:03:26.906635 02780000 ################################################################
10246 01:03:26.906770
10247 01:03:27.164305 02800000 ################################################################
10248 01:03:27.164440
10249 01:03:27.413602 02880000 ################################################################
10250 01:03:27.413729
10251 01:03:27.664354 02900000 ################################################################
10252 01:03:27.664540
10253 01:03:27.914896 02980000 ################################################################
10254 01:03:27.915028
10255 01:03:28.180912 02a00000 ################################################################
10256 01:03:28.181041
10257 01:03:28.431452 02a80000 ################################################################
10258 01:03:28.431606
10259 01:03:28.695355 02b00000 ################################################################
10260 01:03:28.695482
10261 01:03:28.990419 02b80000 ################################################################
10262 01:03:28.990557
10263 01:03:29.274475 02c00000 ################################################################
10264 01:03:29.274615
10265 01:03:29.568509 02c80000 ################################################################
10266 01:03:29.568639
10267 01:03:29.959011 02d00000 ################################################################
10268 01:03:29.959542
10269 01:03:30.326431 02d80000 ################################################################
10270 01:03:30.326581
10271 01:03:30.617634 02e00000 ################################################################
10272 01:03:30.617795
10273 01:03:30.907523 02e80000 ################################################################
10274 01:03:30.907679
10275 01:03:31.182566 02f00000 ################################################################
10276 01:03:31.182698
10277 01:03:31.442108 02f80000 ################################################################
10278 01:03:31.442238
10279 01:03:31.698838 03000000 ################################################################
10280 01:03:31.699016
10281 01:03:31.949109 03080000 ################################################################
10282 01:03:31.949245
10283 01:03:31.992309 03100000 ############ done.
10284 01:03:31.992403
10285 01:03:31.995740 The bootfile was 51471682 bytes long.
10286 01:03:31.995824
10287 01:03:31.998962 Sending tftp read request... done.
10288 01:03:31.999045
10289 01:03:32.002579 Waiting for the transfer...
10290 01:03:32.002671
10291 01:03:32.002738 00000000 # done.
10292 01:03:32.002802
10293 01:03:32.012294 Command line loaded dynamically from TFTP file: 12571123/tftp-deploy-vb3mdyvn/kernel/cmdline
10294 01:03:32.012380
10295 01:03:32.025693 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10296 01:03:32.025778
10297 01:03:32.025845 Loading FIT.
10298 01:03:32.025908
10299 01:03:32.028767 Image ramdisk-1 has 39373745 bytes.
10300 01:03:32.028850
10301 01:03:32.032306 Image fdt-1 has 47278 bytes.
10302 01:03:32.032388
10303 01:03:32.035487 Image kernel-1 has 12048624 bytes.
10304 01:03:32.035570
10305 01:03:32.042096 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10306 01:03:32.042179
10307 01:03:32.062232 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10308 01:03:32.062321
10309 01:03:32.065549 Choosing best match conf-1 for compat google,spherion-rev2.
10310 01:03:32.070183
10311 01:03:32.075000 Connected to device vid:did:rid of 1ae0:0028:00
10312 01:03:32.081697
10313 01:03:32.085045 tpm_get_response: command 0x17b, return code 0x0
10314 01:03:32.085129
10315 01:03:32.091693 ec_init: CrosEC protocol v3 supported (256, 248)
10316 01:03:32.091776
10317 01:03:32.095516 tpm_cleanup: add release locality here.
10318 01:03:32.095599
10319 01:03:32.098352 Shutting down all USB controllers.
10320 01:03:32.098435
10321 01:03:32.101899 Removing current net device
10322 01:03:32.102021
10323 01:03:32.105130 Exiting depthcharge with code 4 at timestamp: 63675091
10324 01:03:32.105213
10325 01:03:32.111649 LZMA decompressing kernel-1 to 0x821a6718
10326 01:03:32.111733
10327 01:03:32.114980 LZMA decompressing kernel-1 to 0x40000000
10328 01:03:33.612860
10329 01:03:33.612999 jumping to kernel
10330 01:03:33.613508 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10331 01:03:33.613606 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10332 01:03:33.613685 Setting prompt string to ['Linux version [0-9]']
10333 01:03:33.613758 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10334 01:03:33.613828 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10335 01:03:33.694753
10336 01:03:33.697917 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10337 01:03:33.701681 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10338 01:03:33.701773 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10339 01:03:33.701850 Setting prompt string to []
10340 01:03:33.701928 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10341 01:03:33.702044 Using line separator: #'\n'#
10342 01:03:33.702105 No login prompt set.
10343 01:03:33.702169 Parsing kernel messages
10344 01:03:33.702226 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10345 01:03:33.702328 [login-action] Waiting for messages, (timeout 00:03:49)
10346 01:03:33.721510 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10347 01:03:33.724433 [ 0.000000] random: crng init done
10348 01:03:33.731172 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10349 01:03:33.734381 [ 0.000000] efi: UEFI not found.
10350 01:03:33.741607 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10351 01:03:33.747934 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10352 01:03:33.757755 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10353 01:03:33.767704 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10354 01:03:33.774238 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10355 01:03:33.781019 [ 0.000000] printk: bootconsole [mtk8250] enabled
10356 01:03:33.787766 [ 0.000000] NUMA: No NUMA configuration found
10357 01:03:33.793890 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10358 01:03:33.797840 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10359 01:03:33.800670 [ 0.000000] Zone ranges:
10360 01:03:33.807602 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10361 01:03:33.810610 [ 0.000000] DMA32 empty
10362 01:03:33.817578 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10363 01:03:33.820467 [ 0.000000] Movable zone start for each node
10364 01:03:33.824075 [ 0.000000] Early memory node ranges
10365 01:03:33.830532 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10366 01:03:33.837394 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10367 01:03:33.843667 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10368 01:03:33.850344 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10369 01:03:33.853866 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10370 01:03:33.863349 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10371 01:03:33.919468 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10372 01:03:33.925894 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10373 01:03:33.932700 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10374 01:03:33.936322 [ 0.000000] psci: probing for conduit method from DT.
10375 01:03:33.942528 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10376 01:03:33.945896 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10377 01:03:33.952931 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10378 01:03:33.955991 [ 0.000000] psci: SMC Calling Convention v1.2
10379 01:03:33.962661 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10380 01:03:33.966065 [ 0.000000] Detected VIPT I-cache on CPU0
10381 01:03:33.972601 [ 0.000000] CPU features: detected: GIC system register CPU interface
10382 01:03:33.979603 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10383 01:03:33.985665 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10384 01:03:33.992146 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10385 01:03:33.998874 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10386 01:03:34.009030 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10387 01:03:34.012412 [ 0.000000] alternatives: applying boot alternatives
10388 01:03:34.018814 [ 0.000000] Fallback order for Node 0: 0
10389 01:03:34.025697 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10390 01:03:34.029271 [ 0.000000] Policy zone: Normal
10391 01:03:34.042523 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10392 01:03:34.051713 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10393 01:03:34.063953 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10394 01:03:34.073794 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10395 01:03:34.080514 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10396 01:03:34.083602 <6>[ 0.000000] software IO TLB: area num 8.
10397 01:03:34.140373 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10398 01:03:34.289504 <6>[ 0.000000] Memory: 7928804K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 423964K reserved, 32768K cma-reserved)
10399 01:03:34.296343 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10400 01:03:34.302873 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10401 01:03:34.306154 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10402 01:03:34.312634 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10403 01:03:34.319472 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10404 01:03:34.323384 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10405 01:03:34.332939 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10406 01:03:34.339492 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10407 01:03:34.342913 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10408 01:03:34.350541 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10409 01:03:34.354056 <6>[ 0.000000] GICv3: 608 SPIs implemented
10410 01:03:34.360442 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10411 01:03:34.364012 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10412 01:03:34.367403 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10413 01:03:34.377121 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10414 01:03:34.387056 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10415 01:03:34.400188 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10416 01:03:34.406942 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10417 01:03:34.416470 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10418 01:03:34.429757 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10419 01:03:34.435889 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10420 01:03:34.442741 <6>[ 0.009183] Console: colour dummy device 80x25
10421 01:03:34.452815 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10422 01:03:34.459237 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10423 01:03:34.462649 <6>[ 0.029253] LSM: Security Framework initializing
10424 01:03:34.469699 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 01:03:34.479048 <6>[ 0.042006] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 01:03:34.485784 <6>[ 0.051473] cblist_init_generic: Setting adjustable number of callback queues.
10427 01:03:34.492615 <6>[ 0.058915] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 01:03:34.502660 <6>[ 0.065253] cblist_init_generic: Setting adjustable number of callback queues.
10429 01:03:34.509117 <6>[ 0.072680] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 01:03:34.512475 <6>[ 0.079120] rcu: Hierarchical SRCU implementation.
10431 01:03:34.519226 <6>[ 0.084137] rcu: Max phase no-delay instances is 1000.
10432 01:03:34.525629 <6>[ 0.091162] EFI services will not be available.
10433 01:03:34.528715 <6>[ 0.096111] smp: Bringing up secondary CPUs ...
10434 01:03:34.537099 <6>[ 0.101160] Detected VIPT I-cache on CPU1
10435 01:03:34.543604 <6>[ 0.101230] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10436 01:03:34.550740 <6>[ 0.101262] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10437 01:03:34.553897 <6>[ 0.101596] Detected VIPT I-cache on CPU2
10438 01:03:34.560791 <6>[ 0.101645] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10439 01:03:34.567226 <6>[ 0.101662] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10440 01:03:34.573582 <6>[ 0.101919] Detected VIPT I-cache on CPU3
10441 01:03:34.580141 <6>[ 0.101966] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10442 01:03:34.587009 <6>[ 0.101980] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10443 01:03:34.590283 <6>[ 0.102286] CPU features: detected: Spectre-v4
10444 01:03:34.597182 <6>[ 0.102293] CPU features: detected: Spectre-BHB
10445 01:03:34.600208 <6>[ 0.102297] Detected PIPT I-cache on CPU4
10446 01:03:34.606622 <6>[ 0.102356] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10447 01:03:34.613193 <6>[ 0.102372] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10448 01:03:34.620229 <6>[ 0.102663] Detected PIPT I-cache on CPU5
10449 01:03:34.626663 <6>[ 0.102725] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10450 01:03:34.633324 <6>[ 0.102743] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10451 01:03:34.636674 <6>[ 0.103024] Detected PIPT I-cache on CPU6
10452 01:03:34.643447 <6>[ 0.103089] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10453 01:03:34.649848 <6>[ 0.103106] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10454 01:03:34.656620 <6>[ 0.103398] Detected PIPT I-cache on CPU7
10455 01:03:34.663005 <6>[ 0.103463] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10456 01:03:34.669672 <6>[ 0.103479] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10457 01:03:34.673214 <6>[ 0.103526] smp: Brought up 1 node, 8 CPUs
10458 01:03:34.679802 <6>[ 0.244922] SMP: Total of 8 processors activated.
10459 01:03:34.682631 <6>[ 0.249873] CPU features: detected: 32-bit EL0 Support
10460 01:03:34.692646 <6>[ 0.255269] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10461 01:03:34.699552 <6>[ 0.264069] CPU features: detected: Common not Private translations
10462 01:03:34.706060 <6>[ 0.270545] CPU features: detected: CRC32 instructions
10463 01:03:34.709273 <6>[ 0.275896] CPU features: detected: RCpc load-acquire (LDAPR)
10464 01:03:34.715960 <6>[ 0.281856] CPU features: detected: LSE atomic instructions
10465 01:03:34.722662 <6>[ 0.287638] CPU features: detected: Privileged Access Never
10466 01:03:34.728987 <6>[ 0.293417] CPU features: detected: RAS Extension Support
10467 01:03:34.735641 <6>[ 0.299061] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10468 01:03:34.738817 <6>[ 0.306324] CPU: All CPU(s) started at EL2
10469 01:03:34.745638 <6>[ 0.310641] alternatives: applying system-wide alternatives
10470 01:03:34.754832 <6>[ 0.321367] devtmpfs: initialized
10471 01:03:34.767437 <6>[ 0.330336] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10472 01:03:34.777031 <6>[ 0.340297] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10473 01:03:34.780557 <6>[ 0.348012] pinctrl core: initialized pinctrl subsystem
10474 01:03:34.788488 <6>[ 0.354657] DMI not present or invalid.
10475 01:03:34.794887 <6>[ 0.359072] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10476 01:03:34.801514 <6>[ 0.365948] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10477 01:03:34.811469 <6>[ 0.373534] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10478 01:03:34.818010 <6>[ 0.381750] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10479 01:03:34.824731 <6>[ 0.389992] audit: initializing netlink subsys (disabled)
10480 01:03:34.831340 <5>[ 0.395686] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10481 01:03:34.837933 <6>[ 0.396383] thermal_sys: Registered thermal governor 'step_wise'
10482 01:03:34.844915 <6>[ 0.403655] thermal_sys: Registered thermal governor 'power_allocator'
10483 01:03:34.848566 <6>[ 0.409908] cpuidle: using governor menu
10484 01:03:34.854339 <6>[ 0.420870] NET: Registered PF_QIPCRTR protocol family
10485 01:03:34.861081 <6>[ 0.426346] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10486 01:03:34.867812 <6>[ 0.433451] ASID allocator initialised with 32768 entries
10487 01:03:34.874550 <6>[ 0.440009] Serial: AMBA PL011 UART driver
10488 01:03:34.882196 <4>[ 0.448800] Trying to register duplicate clock ID: 134
10489 01:03:34.938372 <6>[ 0.508239] KASLR enabled
10490 01:03:34.952891 <6>[ 0.515936] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10491 01:03:34.959485 <6>[ 0.522948] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10492 01:03:34.965908 <6>[ 0.529436] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10493 01:03:34.972358 <6>[ 0.536441] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10494 01:03:34.978904 <6>[ 0.542928] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10495 01:03:34.985617 <6>[ 0.549934] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10496 01:03:34.992053 <6>[ 0.556422] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10497 01:03:34.999149 <6>[ 0.563425] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10498 01:03:35.002112 <6>[ 0.570889] ACPI: Interpreter disabled.
10499 01:03:35.010905 <6>[ 0.577308] iommu: Default domain type: Translated
10500 01:03:35.017493 <6>[ 0.582442] iommu: DMA domain TLB invalidation policy: strict mode
10501 01:03:35.020906 <5>[ 0.589098] SCSI subsystem initialized
10502 01:03:35.027362 <6>[ 0.593349] usbcore: registered new interface driver usbfs
10503 01:03:35.034096 <6>[ 0.599079] usbcore: registered new interface driver hub
10504 01:03:35.037392 <6>[ 0.604632] usbcore: registered new device driver usb
10505 01:03:35.044204 <6>[ 0.610755] pps_core: LinuxPPS API ver. 1 registered
10506 01:03:35.054477 <6>[ 0.615949] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10507 01:03:35.057337 <6>[ 0.625296] PTP clock support registered
10508 01:03:35.060908 <6>[ 0.629536] EDAC MC: Ver: 3.0.0
10509 01:03:35.068270 <6>[ 0.634715] FPGA manager framework
10510 01:03:35.074572 <6>[ 0.638389] Advanced Linux Sound Architecture Driver Initialized.
10511 01:03:35.078278 <6>[ 0.645165] vgaarb: loaded
10512 01:03:35.084623 <6>[ 0.648313] clocksource: Switched to clocksource arch_sys_counter
10513 01:03:35.087874 <5>[ 0.654759] VFS: Disk quotas dquot_6.6.0
10514 01:03:35.094533 <6>[ 0.658943] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10515 01:03:35.097555 <6>[ 0.666131] pnp: PnP ACPI: disabled
10516 01:03:35.106508 <6>[ 0.672859] NET: Registered PF_INET protocol family
10517 01:03:35.116260 <6>[ 0.678442] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10518 01:03:35.127359 <6>[ 0.690739] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10519 01:03:35.137448 <6>[ 0.699551] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10520 01:03:35.144065 <6>[ 0.707522] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10521 01:03:35.150591 <6>[ 0.716221] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10522 01:03:35.162741 <6>[ 0.725968] TCP: Hash tables configured (established 65536 bind 65536)
10523 01:03:35.169404 <6>[ 0.732832] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 01:03:35.175988 <6>[ 0.740031] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 01:03:35.182473 <6>[ 0.747735] NET: Registered PF_UNIX/PF_LOCAL protocol family
10526 01:03:35.189178 <6>[ 0.753898] RPC: Registered named UNIX socket transport module.
10527 01:03:35.192257 <6>[ 0.760052] RPC: Registered udp transport module.
10528 01:03:35.198997 <6>[ 0.764985] RPC: Registered tcp transport module.
10529 01:03:35.205591 <6>[ 0.769916] RPC: Registered tcp NFSv4.1 backchannel transport module.
10530 01:03:35.209057 <6>[ 0.776583] PCI: CLS 0 bytes, default 64
10531 01:03:35.212289 <6>[ 0.781040] Unpacking initramfs...
10532 01:03:35.222099 <6>[ 0.784772] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10533 01:03:35.228757 <6>[ 0.793430] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10534 01:03:35.235648 <6>[ 0.802284] kvm [1]: IPA Size Limit: 40 bits
10535 01:03:35.239139 <6>[ 0.806812] kvm [1]: GICv3: no GICV resource entry
10536 01:03:35.246087 <6>[ 0.811834] kvm [1]: disabling GICv2 emulation
10537 01:03:35.252373 <6>[ 0.816521] kvm [1]: GIC system register CPU interface enabled
10538 01:03:35.255848 <6>[ 0.822691] kvm [1]: vgic interrupt IRQ18
10539 01:03:35.262842 <6>[ 0.828372] kvm [1]: VHE mode initialized successfully
10540 01:03:35.268878 <5>[ 0.834632] Initialise system trusted keyrings
10541 01:03:35.275834 <6>[ 0.839454] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10542 01:03:35.283195 <6>[ 0.849486] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10543 01:03:35.289533 <5>[ 0.855870] NFS: Registering the id_resolver key type
10544 01:03:35.292686 <5>[ 0.861168] Key type id_resolver registered
10545 01:03:35.299429 <5>[ 0.865585] Key type id_legacy registered
10546 01:03:35.306077 <6>[ 0.869881] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10547 01:03:35.312760 <6>[ 0.876802] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10548 01:03:35.319427 <6>[ 0.884554] 9p: Installing v9fs 9p2000 file system support
10549 01:03:35.356634 <5>[ 0.922806] Key type asymmetric registered
10550 01:03:35.359433 <5>[ 0.927136] Asymmetric key parser 'x509' registered
10551 01:03:35.369886 <6>[ 0.932278] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10552 01:03:35.372663 <6>[ 0.939892] io scheduler mq-deadline registered
10553 01:03:35.375801 <6>[ 0.944655] io scheduler kyber registered
10554 01:03:35.395489 <6>[ 0.961660] EINJ: ACPI disabled.
10555 01:03:35.427327 <4>[ 0.987228] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 01:03:35.437294 <4>[ 0.997896] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 01:03:35.452065 <6>[ 1.018621] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10558 01:03:35.460037 <6>[ 1.026677] printk: console [ttyS0] disabled
10559 01:03:35.488376 <6>[ 1.051358] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10560 01:03:35.494639 <6>[ 1.060842] printk: console [ttyS0] enabled
10561 01:03:35.498304 <6>[ 1.060842] printk: console [ttyS0] enabled
10562 01:03:35.504789 <6>[ 1.069754] printk: bootconsole [mtk8250] disabled
10563 01:03:35.507843 <6>[ 1.069754] printk: bootconsole [mtk8250] disabled
10564 01:03:35.514641 <6>[ 1.081086] SuperH (H)SCI(F) driver initialized
10565 01:03:35.517703 <6>[ 1.086375] msm_serial: driver initialized
10566 01:03:35.532248 <6>[ 1.095391] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10567 01:03:35.541860 <6>[ 1.103940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10568 01:03:35.548794 <6>[ 1.112483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10569 01:03:35.558592 <6>[ 1.121112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10570 01:03:35.565424 <6>[ 1.129821] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10571 01:03:35.575292 <6>[ 1.138538] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10572 01:03:35.585132 <6>[ 1.147082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10573 01:03:35.591804 <6>[ 1.155894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10574 01:03:35.601853 <6>[ 1.164439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10575 01:03:35.613539 <6>[ 1.180177] loop: module loaded
10576 01:03:35.620327 <6>[ 1.186162] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10577 01:03:35.642831 <4>[ 1.209529] mtk-pmic-keys: Failed to locate of_node [id: -1]
10578 01:03:35.649614 <6>[ 1.216425] megasas: 07.719.03.00-rc1
10579 01:03:35.659309 <6>[ 1.225961] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10580 01:03:35.673347 <6>[ 1.239687] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10581 01:03:35.689090 <6>[ 1.255646] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10582 01:03:35.745160 <6>[ 1.304868] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10583 01:03:36.817970 <6>[ 2.384510] Freeing initrd memory: 38448K
10584 01:03:36.828266 <6>[ 2.394840] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10585 01:03:36.838917 <6>[ 2.405786] tun: Universal TUN/TAP device driver, 1.6
10586 01:03:36.842119 <6>[ 2.411841] thunder_xcv, ver 1.0
10587 01:03:36.845657 <6>[ 2.415343] thunder_bgx, ver 1.0
10588 01:03:36.848812 <6>[ 2.418841] nicpf, ver 1.0
10589 01:03:36.859582 <6>[ 2.422853] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10590 01:03:36.862643 <6>[ 2.430329] hns3: Copyright (c) 2017 Huawei Corporation.
10591 01:03:36.869212 <6>[ 2.435919] hclge is initializing
10592 01:03:36.872652 <6>[ 2.439498] e1000: Intel(R) PRO/1000 Network Driver
10593 01:03:36.879565 <6>[ 2.444628] e1000: Copyright (c) 1999-2006 Intel Corporation.
10594 01:03:36.882835 <6>[ 2.450641] e1000e: Intel(R) PRO/1000 Network Driver
10595 01:03:36.889529 <6>[ 2.455857] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10596 01:03:36.896261 <6>[ 2.462043] igb: Intel(R) Gigabit Ethernet Network Driver
10597 01:03:36.902424 <6>[ 2.467693] igb: Copyright (c) 2007-2014 Intel Corporation.
10598 01:03:36.909352 <6>[ 2.473529] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10599 01:03:36.915708 <6>[ 2.480047] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10600 01:03:36.918977 <6>[ 2.486510] sky2: driver version 1.30
10601 01:03:36.925740 <6>[ 2.491502] VFIO - User Level meta-driver version: 0.3
10602 01:03:36.933083 <6>[ 2.499734] usbcore: registered new interface driver usb-storage
10603 01:03:36.939716 <6>[ 2.506188] usbcore: registered new device driver onboard-usb-hub
10604 01:03:36.948356 <6>[ 2.515326] mt6397-rtc mt6359-rtc: registered as rtc0
10605 01:03:36.958358 <6>[ 2.520794] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T01:02:56 UTC (1705626176)
10606 01:03:36.961987 <6>[ 2.530361] i2c_dev: i2c /dev entries driver
10607 01:03:36.978706 <6>[ 2.542107] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10608 01:03:36.999614 <6>[ 2.566116] cpu cpu0: EM: created perf domain
10609 01:03:37.002593 <6>[ 2.571049] cpu cpu4: EM: created perf domain
10610 01:03:37.010048 <6>[ 2.576622] sdhci: Secure Digital Host Controller Interface driver
10611 01:03:37.016846 <6>[ 2.583051] sdhci: Copyright(c) Pierre Ossman
10612 01:03:37.023117 <6>[ 2.588010] Synopsys Designware Multimedia Card Interface Driver
10613 01:03:37.029860 <6>[ 2.594654] sdhci-pltfm: SDHCI platform and OF driver helper
10614 01:03:37.033160 <6>[ 2.594775] mmc0: CQHCI version 5.10
10615 01:03:37.039793 <6>[ 2.604647] ledtrig-cpu: registered to indicate activity on CPUs
10616 01:03:37.046272 <6>[ 2.611600] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10617 01:03:37.052996 <6>[ 2.618655] usbcore: registered new interface driver usbhid
10618 01:03:37.056405 <6>[ 2.624478] usbhid: USB HID core driver
10619 01:03:37.062650 <6>[ 2.628675] spi_master spi0: will run message pump with realtime priority
10620 01:03:37.108401 <6>[ 2.668410] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10621 01:03:37.127547 <6>[ 2.684466] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10622 01:03:37.131243 <6>[ 2.699889] mmc0: Command Queue Engine enabled
10623 01:03:37.137735 <6>[ 2.704629] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10624 01:03:37.144723 <6>[ 2.711491] cros-ec-spi spi0.0: Chrome EC device registered
10625 01:03:37.151618 <6>[ 2.711956] mmcblk0: mmc0:0001 DA4128 116 GiB
10626 01:03:37.160513 <6>[ 2.727373] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10627 01:03:37.168156 <6>[ 2.734955] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10628 01:03:37.174831 <6>[ 2.740974] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10629 01:03:37.181533 <6>[ 2.746982] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10630 01:03:37.191575 <6>[ 2.751199] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10631 01:03:37.198114 <6>[ 2.764250] NET: Registered PF_PACKET protocol family
10632 01:03:37.201290 <6>[ 2.769699] 9pnet: Installing 9P2000 support
10633 01:03:37.208047 <5>[ 2.774279] Key type dns_resolver registered
10634 01:03:37.211553 <6>[ 2.779394] registered taskstats version 1
10635 01:03:37.217994 <5>[ 2.783814] Loading compiled-in X.509 certificates
10636 01:03:37.246360 <4>[ 2.806367] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 01:03:37.256701 <4>[ 2.817192] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 01:03:37.262680 <3>[ 2.827819] debugfs: File 'uA_load' in directory '/' already present!
10639 01:03:37.269795 <3>[ 2.834530] debugfs: File 'min_uV' in directory '/' already present!
10640 01:03:37.276184 <3>[ 2.841144] debugfs: File 'max_uV' in directory '/' already present!
10641 01:03:37.282716 <3>[ 2.847755] debugfs: File 'constraint_flags' in directory '/' already present!
10642 01:03:37.295451 <3>[ 2.859013] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10643 01:03:37.308309 <6>[ 2.875115] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 01:03:37.315216 <6>[ 2.881914] xhci-mtk 11200000.usb: xHCI Host Controller
10645 01:03:37.321811 <6>[ 2.887419] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 01:03:37.332014 <6>[ 2.895268] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 01:03:37.338617 <6>[ 2.904807] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 01:03:37.345176 <6>[ 2.910918] xhci-mtk 11200000.usb: xHCI Host Controller
10649 01:03:37.351680 <6>[ 2.916405] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 01:03:37.358088 <6>[ 2.924059] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 01:03:37.365056 <6>[ 2.931853] hub 1-0:1.0: USB hub found
10652 01:03:37.368658 <6>[ 2.935889] hub 1-0:1.0: 1 port detected
10653 01:03:37.378127 <6>[ 2.940188] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 01:03:37.381620 <6>[ 2.948903] hub 2-0:1.0: USB hub found
10655 01:03:37.384695 <6>[ 2.952927] hub 2-0:1.0: 1 port detected
10656 01:03:37.393161 <6>[ 2.959761] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 01:03:37.406062 <6>[ 2.969567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10658 01:03:37.412686 <6>[ 2.977682] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10659 01:03:37.422477 <4>[ 2.985579] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10660 01:03:37.432424 <6>[ 2.995118] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10661 01:03:37.439142 <6>[ 3.003199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10662 01:03:37.445631 <6>[ 3.011217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10663 01:03:37.455593 <6>[ 3.019129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10664 01:03:37.462341 <6>[ 3.026966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10665 01:03:37.472007 <6>[ 3.034784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10666 01:03:37.482034 <6>[ 3.045226] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10667 01:03:37.488751 <6>[ 3.053581] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10668 01:03:37.498609 <6>[ 3.061948] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10669 01:03:37.505710 <6>[ 3.070292] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10670 01:03:37.515474 <6>[ 3.078642] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10671 01:03:37.522319 <6>[ 3.086981] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10672 01:03:37.532038 <6>[ 3.095331] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10673 01:03:37.542006 <6>[ 3.103670] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10674 01:03:37.548402 <6>[ 3.112019] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10675 01:03:37.558166 <6>[ 3.120357] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10676 01:03:37.564724 <6>[ 3.128705] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10677 01:03:37.574657 <6>[ 3.137044] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10678 01:03:37.581366 <6>[ 3.145382] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10679 01:03:37.591457 <6>[ 3.153721] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10680 01:03:37.598172 <6>[ 3.162059] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10681 01:03:37.604239 <6>[ 3.170814] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10682 01:03:37.611396 <6>[ 3.177975] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10683 01:03:37.618291 <6>[ 3.184748] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10684 01:03:37.628193 <6>[ 3.191507] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10685 01:03:37.634623 <6>[ 3.198442] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10686 01:03:37.641188 <6>[ 3.205298] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10687 01:03:37.651214 <6>[ 3.214426] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10688 01:03:37.661314 <6>[ 3.223544] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10689 01:03:37.670798 <6>[ 3.232837] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10690 01:03:37.681211 <6>[ 3.242340] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10691 01:03:37.690637 <6>[ 3.251913] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10692 01:03:37.697955 <6>[ 3.261034] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10693 01:03:37.707367 <6>[ 3.270500] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10694 01:03:37.717537 <6>[ 3.279618] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10695 01:03:37.727351 <6>[ 3.288914] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10696 01:03:37.737076 <6>[ 3.299074] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10697 01:03:37.746936 <6>[ 3.310615] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10698 01:03:37.812975 <6>[ 3.376591] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10699 01:03:37.967574 <6>[ 3.534445] hub 1-1:1.0: USB hub found
10700 01:03:37.971011 <6>[ 3.538972] hub 1-1:1.0: 4 ports detected
10701 01:03:37.980321 <6>[ 3.547353] hub 1-1:1.0: USB hub found
10702 01:03:37.983591 <6>[ 3.551709] hub 1-1:1.0: 4 ports detected
10703 01:03:38.093329 <6>[ 3.656868] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10704 01:03:38.119658 <6>[ 3.686455] hub 2-1:1.0: USB hub found
10705 01:03:38.123195 <6>[ 3.690943] hub 2-1:1.0: 3 ports detected
10706 01:03:38.132115 <6>[ 3.699130] hub 2-1:1.0: USB hub found
10707 01:03:38.135764 <6>[ 3.703569] hub 2-1:1.0: 3 ports detected
10708 01:03:38.309158 <6>[ 3.872612] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10709 01:03:38.441585 <6>[ 4.008616] hub 1-1.4:1.0: USB hub found
10710 01:03:38.444912 <6>[ 4.013288] hub 1-1.4:1.0: 2 ports detected
10711 01:03:38.455210 <6>[ 4.021928] hub 1-1.4:1.0: USB hub found
10712 01:03:38.458531 <6>[ 4.026563] hub 1-1.4:1.0: 2 ports detected
10713 01:03:38.524992 <6>[ 4.088840] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10714 01:03:38.757015 <6>[ 4.320631] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10715 01:03:38.948964 <6>[ 4.512613] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10716 01:03:50.034498 <6>[ 15.605617] ALSA device list:
10717 01:03:50.041275 <6>[ 15.608904] No soundcards found.
10718 01:03:50.049206 <6>[ 15.616890] Freeing unused kernel memory: 8448K
10719 01:03:50.052499 <6>[ 15.621911] Run /init as init process
10720 01:03:50.098803 <6>[ 15.666393] NET: Registered PF_INET6 protocol family
10721 01:03:50.105297 <6>[ 15.672719] Segment Routing with IPv6
10722 01:03:50.108217 <6>[ 15.676671] In-situ OAM (IOAM) with IPv6
10723 01:03:50.139105 <30>[ 15.690629] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10724 01:03:50.146512 <30>[ 15.714524] systemd[1]: Detected architecture arm64.
10725 01:03:50.146848
10726 01:03:50.152933 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10727 01:03:50.153240
10728 01:03:50.164852 <30>[ 15.732692] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10729 01:03:50.317422 <30>[ 15.882025] systemd[1]: Queued start job for default target Graphical Interface.
10730 01:03:50.349359 <30>[ 15.917240] systemd[1]: Created slice system-getty.slice.
10731 01:03:50.355631 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10732 01:03:50.373319 <30>[ 15.940956] systemd[1]: Created slice system-modprobe.slice.
10733 01:03:50.379162 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10734 01:03:50.396586 <30>[ 15.965107] systemd[1]: Created slice system-serial\x2dgetty.slice.
10735 01:03:50.406954 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10736 01:03:50.421433 <30>[ 15.989700] systemd[1]: Created slice User and Session Slice.
10737 01:03:50.427919 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10738 01:03:50.448352 <30>[ 16.013182] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10739 01:03:50.457888 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10740 01:03:50.476761 <30>[ 16.041238] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10741 01:03:50.482756 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10742 01:03:50.507170 <30>[ 16.069054] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10743 01:03:50.514052 <30>[ 16.081293] systemd[1]: Reached target Local Encrypted Volumes.
10744 01:03:50.520561 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10745 01:03:50.536760 <30>[ 16.105137] systemd[1]: Reached target Paths.
10746 01:03:50.540289 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10747 01:03:50.556655 <30>[ 16.124609] systemd[1]: Reached target Remote File Systems.
10748 01:03:50.562884 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10749 01:03:50.576327 <30>[ 16.144581] systemd[1]: Reached target Slices.
10750 01:03:50.579646 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10751 01:03:50.596888 <30>[ 16.164586] systemd[1]: Reached target Swap.
10752 01:03:50.599956 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10753 01:03:50.621253 <30>[ 16.185517] systemd[1]: Listening on initctl Compatibility Named Pipe.
10754 01:03:50.627784 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10755 01:03:50.641502 <30>[ 16.209469] systemd[1]: Listening on Journal Audit Socket.
10756 01:03:50.648176 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10757 01:03:50.666063 <30>[ 16.233797] systemd[1]: Listening on Journal Socket (/dev/log).
10758 01:03:50.672531 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10759 01:03:50.689867 <30>[ 16.257817] systemd[1]: Listening on Journal Socket.
10760 01:03:50.696221 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10761 01:03:50.712425 <30>[ 16.277292] systemd[1]: Listening on Network Service Netlink Socket.
10762 01:03:50.719004 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10763 01:03:50.733734 <30>[ 16.301864] systemd[1]: Listening on udev Control Socket.
10764 01:03:50.740242 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10765 01:03:50.757271 <30>[ 16.325664] systemd[1]: Listening on udev Kernel Socket.
10766 01:03:50.763904 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10767 01:03:50.804482 <30>[ 16.372687] systemd[1]: Mounting Huge Pages File System...
10768 01:03:50.811151 Mounting [0;1;39mHuge Pages File System[0m...
10769 01:03:50.826648 <30>[ 16.394965] systemd[1]: Mounting POSIX Message Queue File System...
10770 01:03:50.833211 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10771 01:03:50.872946 <30>[ 16.440686] systemd[1]: Mounting Kernel Debug File System...
10772 01:03:50.879458 Mounting [0;1;39mKernel Debug File System[0m...
10773 01:03:50.896001 <30>[ 16.460771] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10774 01:03:50.907332 <30>[ 16.471963] systemd[1]: Starting Create list of static device nodes for the current kernel...
10775 01:03:50.913850 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10776 01:03:50.937568 <30>[ 16.505045] systemd[1]: Starting Load Kernel Module configfs...
10777 01:03:50.943605 Starting [0;1;39mLoad Kernel Module configfs[0m...
10778 01:03:50.964827 <30>[ 16.532864] systemd[1]: Starting Load Kernel Module drm...
10779 01:03:50.971589 Starting [0;1;39mLoad Kernel Module drm[0m...
10780 01:03:50.992151 <30>[ 16.556921] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10781 01:03:51.006602 <30>[ 16.574571] systemd[1]: Starting Journal Service...
10782 01:03:51.009997 Starting [0;1;39mJournal Service[0m...
10783 01:03:51.031428 <30>[ 16.599238] systemd[1]: Starting Load Kernel Modules...
10784 01:03:51.038312 Starting [0;1;39mLoad Kernel Modules[0m...
10785 01:03:51.060718 <30>[ 16.625564] systemd[1]: Starting Remount Root and Kernel File Systems...
10786 01:03:51.067318 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10787 01:03:51.085025 <30>[ 16.652432] systemd[1]: Starting Coldplug All udev Devices...
10788 01:03:51.091404 Starting [0;1;39mColdplug All udev Devices[0m...
10789 01:03:51.107788 <30>[ 16.675569] systemd[1]: Started Journal Service.
10790 01:03:51.114333 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10791 01:03:51.131887 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10792 01:03:51.150706 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10793 01:03:51.166107 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10794 01:03:51.185446 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10795 01:03:51.202643 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10796 01:03:51.224112 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10797 01:03:51.246534 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10798 01:03:51.270908 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10799 01:03:51.289215 See 'systemctl status systemd-remount-fs.service' for details.
10800 01:03:51.341316 Mounting [0;1;39mKernel Configuration File System[0m...
10801 01:03:51.361918 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10802 01:03:51.375497 <46>[ 16.939848] systemd-journald[184]: Received client request to flush runtime journal.
10803 01:03:51.417877 Starting [0;1;39mLoad/Save Random Seed[0m...
10804 01:03:51.436877 Starting [0;1;39mApply Kernel Variables[0m...
10805 01:03:51.457248 Starting [0;1;39mCreate System Users[0m...
10806 01:03:51.476508 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10807 01:03:51.493799 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10808 01:03:51.514136 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10809 01:03:51.526871 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10810 01:03:51.542631 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10811 01:03:51.558850 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10812 01:03:51.606203 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10813 01:03:51.628702 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10814 01:03:51.641166 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10815 01:03:51.660817 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10816 01:03:51.705251 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10817 01:03:51.729887 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10818 01:03:51.758523 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10819 01:03:51.778562 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10820 01:03:51.815227 Starting [0;1;39mNetwork Service[0m...
10821 01:03:51.835069 Starting [0;1;39mNetwork Time Synchronization[0m...
10822 01:03:51.856922 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10823 01:03:51.911024 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m<6>[ 17.475702] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10824 01:03:51.911593 .
10825 01:03:51.921030 <6>[ 17.484286] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10826 01:03:51.930759 <6>[ 17.495018] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10827 01:03:51.937686 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10828 01:03:51.953928 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10829 01:03:51.985015 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10830 01:03:51.997285 <3>[ 17.561663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 01:03:52.003670 <6>[ 17.566532] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10832 01:03:52.013766 <3>[ 17.572547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 01:03:52.020285 <3>[ 17.585426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 01:03:52.027008 <6>[ 17.593799] remoteproc remoteproc0: scp is available
10835 01:03:52.033342 [[0;32m OK [<6>[ 17.599206] remoteproc remoteproc0: powering up scp
10836 01:03:52.043448 0m] Created slic<6>[ 17.605753] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10837 01:03:52.053347 e [0;1;39msyste<3>[ 17.607914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 01:03:52.056973 <6>[ 17.615448] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10839 01:03:52.066686 <6>[ 17.625829] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10840 01:03:52.073104 <3>[ 17.630636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 01:03:52.082940 m-systemd\x2dbac<6>[ 17.640733] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10842 01:03:52.089451 <3>[ 17.646371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 01:03:52.096353 klight.slice[0m<6>[ 17.655036] pci_bus 0000:00: root bus resource [bus 00-ff]
10844 01:03:52.102876 <4>[ 17.658420] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10845 01:03:52.103430 .
10846 01:03:52.112470 <3>[ 17.662669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 01:03:52.119840 <3>[ 17.662681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 01:03:52.130107 <4>[ 17.664399] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10849 01:03:52.137002 <6>[ 17.669949] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10850 01:03:52.143634 <4>[ 17.670691] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10851 01:03:52.150464 <4>[ 17.670691] Fallback method does not support PEC.
10852 01:03:52.153659 <6>[ 17.677704] mc: Linux media interface: v0.10
10853 01:03:52.163718 <3>[ 17.678785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 01:03:52.173163 <6>[ 17.685460] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10855 01:03:52.176739 <6>[ 17.685552] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10856 01:03:52.186747 <6>[ 17.685585] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10857 01:03:52.190383 <6>[ 17.685769] pci 0000:00:00.0: supports D1 D2
10858 01:03:52.197358 <6>[ 17.687432] usbcore: registered new device driver r8152-cfgselector
10859 01:03:52.203719 <3>[ 17.703115] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 01:03:52.214170 <3>[ 17.703992] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 01:03:52.220341 <3>[ 17.704005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 01:03:52.230541 <3>[ 17.704009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 01:03:52.236828 <3>[ 17.706599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 01:03:52.247086 <3>[ 17.706630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10865 01:03:52.253417 <3>[ 17.706636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 01:03:52.264089 <3>[ 17.706647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10867 01:03:52.270604 <3>[ 17.706653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10868 01:03:52.277335 <3>[ 17.707288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 01:03:52.284097 <6>[ 17.708331] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10870 01:03:52.294150 <6>[ 17.710364] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10871 01:03:52.304195 <6>[ 17.730602] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10872 01:03:52.310555 <6>[ 17.734965] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10873 01:03:52.317604 <6>[ 17.741164] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10874 01:03:52.323976 <6>[ 17.744717] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10875 01:03:52.331002 <6>[ 17.744739] remoteproc remoteproc0: remote processor scp is now up
10876 01:03:52.342335 <6>[ 17.751027] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10877 01:03:52.347063 <6>[ 17.758797] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10878 01:03:52.354608 <6>[ 17.763001] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10879 01:03:52.364763 <6>[ 17.763016] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10880 01:03:52.372214 <3>[ 17.770884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 01:03:52.375001 <6>[ 17.778406] pci 0000:01:00.0: supports D1 D2
10882 01:03:52.385136 <3>[ 17.786902] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10883 01:03:52.392214 <6>[ 17.794459] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10884 01:03:52.399097 <6>[ 17.816610] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10885 01:03:52.405774 <6>[ 17.819006] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10886 01:03:52.416166 <6>[ 17.822700] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10887 01:03:52.422867 <6>[ 17.827332] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10888 01:03:52.432859 <6>[ 17.839579] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10889 01:03:52.440202 <6>[ 17.843267] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10890 01:03:52.450662 <6>[ 17.843282] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10891 01:03:52.457509 <6>[ 17.843296] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10892 01:03:52.464466 <6>[ 17.843316] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10893 01:03:52.470656 <6>[ 17.844081] videodev: Linux video capture interface: v2.00
10894 01:03:52.473812 <6>[ 17.852610] Bluetooth: Core ver 2.22
10895 01:03:52.481754 <6>[ 17.855098] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10896 01:03:52.491315 <4>[ 17.855954] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10897 01:03:52.501442 <4>[ 17.855965] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10898 01:03:52.505311 <6>[ 17.858586] pci 0000:00:00.0: PCI bridge to [bus 01]
10899 01:03:52.511886 <6>[ 17.866730] NET: Registered PF_BLUETOOTH protocol family
10900 01:03:52.518364 <6>[ 17.876724] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10901 01:03:52.524766 <6>[ 17.882971] Bluetooth: HCI device and connection manager initialized
10902 01:03:52.532218 <6>[ 17.890326] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10903 01:03:52.535509 <6>[ 17.898704] Bluetooth: HCI socket layer initialized
10904 01:03:52.546003 <3>[ 17.900232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 01:03:52.552028 <6>[ 17.905699] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10906 01:03:52.555904 <6>[ 17.912419] Bluetooth: L2CAP socket layer initialized
10907 01:03:52.562523 <6>[ 17.912440] Bluetooth: SCO socket layer initialized
10908 01:03:52.565131 <6>[ 17.912569] r8152 2-1.3:1.0 eth0: v1.12.13
10909 01:03:52.571931 <6>[ 17.912673] usbcore: registered new interface driver r8152
10910 01:03:52.578671 <6>[ 17.913890] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10911 01:03:52.591708 <6>[ 17.915023] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10912 01:03:52.598366 <6>[ 17.915115] usbcore: registered new interface driver uvcvideo
10913 01:03:52.601712 <6>[ 17.922089] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10914 01:03:52.611900 <3>[ 17.938746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 01:03:52.621602 <3>[ 17.939380] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10916 01:03:52.625156 <6>[ 17.945953] usbcore: registered new interface driver cdc_ether
10917 01:03:52.631442 <6>[ 17.946461] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10918 01:03:52.641001 <3>[ 17.946543] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 01:03:52.648400 <5>[ 17.967255] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10920 01:03:52.658174 <3>[ 17.969986] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 01:03:52.664390 <6>[ 17.972641] usbcore: registered new interface driver btusb
10922 01:03:52.674067 <4>[ 17.973231] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10923 01:03:52.680738 <3>[ 17.973239] Bluetooth: hci0: Failed to load firmware file (-2)
10924 01:03:52.687751 <3>[ 17.973240] Bluetooth: hci0: Failed to set up firmware (-2)
10925 01:03:52.697610 <4>[ 17.973244] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10926 01:03:52.703960 <6>[ 17.980202] usbcore: registered new interface driver r8153_ecm
10927 01:03:52.710857 <5>[ 17.992369] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10928 01:03:52.717351 <3>[ 17.992392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 01:03:52.724152 <6>[ 18.009930] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10930 01:03:52.733883 <5>[ 18.013856] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10931 01:03:52.740368 <3>[ 18.014071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 01:03:52.746887 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10933 01:03:52.765254 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10934 01:03:52.780605 <4>[ 18.345453] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10935 01:03:52.787264 <6>[ 18.354376] cfg80211: failed to load regulatory.db
10936 01:03:52.827218 <6>[ 18.391705] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10937 01:03:52.833799 <6>[ 18.399245] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10938 01:03:52.840498 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10939 01:03:52.857857 <6>[ 18.425983] mt7921e 0000:01:00.0: ASIC revision: 79610010
10940 01:03:52.866924 Starting [0;1;39mNetwork Name Resolution[0m...
10941 01:03:52.886855 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10942 01:03:52.930379 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10943 01:03:52.959329 <6>[ 18.524353] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10944 01:03:52.962585 <6>[ 18.524353]
10945 01:03:53.064312 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10946 01:03:53.080815 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10947 01:03:53.099980 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10948 01:03:53.112892 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10949 01:03:53.132686 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10950 01:03:53.147899 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10951 01:03:53.160737 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10952 01:03:53.180841 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10953 01:03:53.193041 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10954 01:03:53.208945 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10955 01:03:53.226806 <6>[ 18.791697] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10956 01:03:53.236968 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10957 01:03:53.269165 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10958 01:03:53.296193 Starting [0;1;39mUser Login Management[0m...
10959 01:03:53.316044 Starting [0;1;39mPermit User Sessions[0m...
10960 01:03:53.338981 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10961 01:03:53.351795 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10962 01:03:53.369555 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10963 01:03:53.387209 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10964 01:03:53.430611 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10965 01:03:53.450756 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10966 01:03:53.469631 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10967 01:03:53.485432 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10968 01:03:53.501208 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10969 01:03:53.545269 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10970 01:03:53.580735 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10971 01:03:53.609025
10972 01:03:53.609592
10973 01:03:53.611937 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10974 01:03:53.612408
10975 01:03:53.615521 debian-bullseye-arm64 login: root (automatic login)
10976 01:03:53.615994
10977 01:03:53.616365
10978 01:03:53.632774 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
10979 01:03:53.633340
10980 01:03:53.639641 The programs included with the Debian GNU/Linux system are free software;
10981 01:03:53.646170 the exact distribution terms for each program are described in the
10982 01:03:53.649518 individual files in /usr/share/doc/*/copyright.
10983 01:03:53.650121
10984 01:03:53.656351 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 01:03:53.659612 permitted by applicable law.
10986 01:03:53.661122 Matched prompt #10: / #
10988 01:03:53.662288 Setting prompt string to ['/ #']
10989 01:03:53.662772 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10991 01:03:53.663840 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10992 01:03:53.664328 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
10993 01:03:53.664714 Setting prompt string to ['/ #']
10994 01:03:53.665066 Forcing a shell prompt, looking for ['/ #']
10996 01:03:53.715952 / #
10997 01:03:53.716612 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 01:03:53.717088 Waiting using forced prompt support (timeout 00:02:30)
10999 01:03:53.722302
11000 01:03:53.723219 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 01:03:53.723750 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
11002 01:03:53.724252 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11003 01:03:53.724945 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
11004 01:03:53.725446 end: 2 depthcharge-action (duration 00:01:31) [common]
11005 01:03:53.725988 start: 3 lava-test-retry (timeout 00:08:10) [common]
11006 01:03:53.726499 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
11007 01:03:53.726911 Using namespace: common
11009 01:03:53.828186 / # #
11010 01:03:53.828918 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11011 01:03:53.834833 #
11012 01:03:53.835718 Using /lava-12571123
11014 01:03:53.937084 / # export SHELL=/bin/sh
11015 01:03:53.943514 export SHELL=/bin/sh
11017 01:03:54.045232 / # . /lava-12571123/environment
11018 01:03:54.046040 <6>[ 19.528772] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11019 01:03:54.046478 <6>[ 19.536852] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11020 01:03:54.051581 . /lava-12571123/environment
11022 01:03:54.153262 / # /lava-12571123/bin/lava-test-runner /lava-12571123/0
11023 01:03:54.153879 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 01:03:54.155570 <6>[ 19.641796] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11025 01:03:54.159715 /lava-12571123/bin/lava-test-runner /lava-12571123/0
11026 01:03:54.206616 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11027 01:03:54.207307 + cd /lava-12571123/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11028 01:03:54.207718 + cat uuid
11029 01:03:54.208367 + UUID=12571123_1.5.2.3.1
11030 01:03:54.208746 + set +x
11031 01:03:54.209096 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12571123_1.5.2.3.1>
11032 01:03:54.209437 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11033 01:03:54.210095 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12571123_1.5.2.3.1
11034 01:03:54.210486 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12571123_1.5.2.3.1)
11035 01:03:54.210922 Skipping test definition patterns.
11036 01:03:54.211420 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
11037 01:03:54.211880 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
11038 01:03:54.214382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 19.777515] use of bytesused == 0 is deprecated and will be removed in the future,
11039 01:03:54.217441 <4>[ 19.786469] use the actual size instead.
11040 01:03:54.217915 RESULT=pass>
11041 01:03:54.221117 device: /dev/video2
11042 01:03:54.234500 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11043 01:03:54.246117 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11044 01:03:54.253115
11045 01:03:54.265369 Compliance test for mtk-vcodec-enc device /dev/video2:
11046 01:03:54.274448
11047 01:03:54.284607 Driver Info:
11048 01:03:54.295561 Driver name : mtk-vcodec-enc
11049 01:03:54.310588 Card type : MT8192 video encoder
11050 01:03:54.321579 Bus info : platform:17020000.vcodec
11051 01:03:54.327205 Driver version : 6.1.72
11052 01:03:54.343747 Capabilities : 0x84204000
11053 01:03:54.355131 Video Memory-to-Memory Multiplanar
11054 01:03:54.364306 Streaming
11055 01:03:54.374501 Extended Pix Format
11056 01:03:54.386873 Device Capabilities
11057 01:03:54.396570 Device Caps : 0x04204000
11058 01:03:54.408065 Video Memory-to-Memory Multiplanar
11059 01:03:54.423346 Streaming
11060 01:03:54.435880 Extended Pix Format
11061 01:03:54.449607 Detected Stateful Encoder
11062 01:03:54.458596
11063 01:03:54.470801 Required ioctls:
11064 01:03:54.487017 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11065 01:03:54.487579 test VIDIOC_QUERYCAP: OK
11066 01:03:54.488220 Received signal: <TESTSET> START Required-ioctls
11067 01:03:54.488612 Starting test_set Required-ioctls
11068 01:03:54.509881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11069 01:03:54.510779 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11071 01:03:54.513248 test invalid ioctls: OK
11072 01:03:54.533828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11073 01:03:54.534456
11074 01:03:54.535096 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11076 01:03:54.548328 Allow for multiple opens:
11077 01:03:54.555523 <LAVA_SIGNAL_TESTSET STOP>
11078 01:03:54.556369 Received signal: <TESTSET> STOP
11079 01:03:54.556798 Closing test_set Required-ioctls
11080 01:03:54.565393 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11081 01:03:54.566267 Received signal: <TESTSET> START Allow-for-multiple-opens
11082 01:03:54.566667 Starting test_set Allow-for-multiple-opens
11083 01:03:54.568793 test second /dev/video2 open: OK
11084 01:03:54.590284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11085 01:03:54.591158 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11087 01:03:54.593230 test VIDIOC_QUERYCAP: OK
11088 01:03:54.615125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11089 01:03:54.615957 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11091 01:03:54.618441 test VIDIOC_G/S_PRIORITY: OK
11092 01:03:54.641391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11093 01:03:54.642288 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11095 01:03:54.644218 test for unlimited opens: OK
11096 01:03:54.664643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11097 01:03:54.665229
11098 01:03:54.665891 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11100 01:03:54.674888 Debug ioctls:
11101 01:03:54.682825 <LAVA_SIGNAL_TESTSET STOP>
11102 01:03:54.683679 Received signal: <TESTSET> STOP
11103 01:03:54.684080 Closing test_set Allow-for-multiple-opens
11104 01:03:54.694910 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11105 01:03:54.695764 Received signal: <TESTSET> START Debug-ioctls
11106 01:03:54.696166 Starting test_set Debug-ioctls
11107 01:03:54.698066 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11108 01:03:54.720742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11109 01:03:54.721604 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11111 01:03:54.727374 test VIDIOC_LOG_STATUS: OK (Not Supported)
11112 01:03:54.747099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11113 01:03:54.747688
11114 01:03:54.748338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11116 01:03:54.761291 Input ioctls:
11117 01:03:54.767771 <LAVA_SIGNAL_TESTSET STOP>
11118 01:03:54.768625 Received signal: <TESTSET> STOP
11119 01:03:54.769025 Closing test_set Debug-ioctls
11120 01:03:54.777464 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11121 01:03:54.778351 Received signal: <TESTSET> START Input-ioctls
11122 01:03:54.778760 Starting test_set Input-ioctls
11123 01:03:54.780448 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11124 01:03:54.804792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11125 01:03:54.805621 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11127 01:03:54.808386 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11128 01:03:54.826030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11129 01:03:54.826779 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11131 01:03:54.833122 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11132 01:03:54.852031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11133 01:03:54.852880 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11135 01:03:54.858279 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11136 01:03:54.878114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11137 01:03:54.878954 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11139 01:03:54.881028 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11140 01:03:54.902326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11141 01:03:54.903162 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11143 01:03:54.905639 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11144 01:03:54.929497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11145 01:03:54.930403 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11147 01:03:54.933074 Inputs: 0 Audio Inputs: 0 Tuners: 0
11148 01:03:54.939997
11149 01:03:54.957492 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11150 01:03:54.979215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11151 01:03:54.980064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11153 01:03:54.985864 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11154 01:03:55.009612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11155 01:03:55.010484 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11157 01:03:55.016081 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11158 01:03:55.033690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11159 01:03:55.034547 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11161 01:03:55.040284 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11162 01:03:55.059034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11163 01:03:55.059875 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11165 01:03:55.065839 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11166 01:03:55.092798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11167 01:03:55.093357
11168 01:03:55.094027 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11170 01:03:55.111000 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11171 01:03:55.134055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11172 01:03:55.134940 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11174 01:03:55.140771 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11175 01:03:55.160838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11176 01:03:55.161671 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11178 01:03:55.164454 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11179 01:03:55.181869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11180 01:03:55.182733 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11182 01:03:55.185624 test VIDIOC_G/S_EDID: OK (Not Supported)
11183 01:03:55.212215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11184 01:03:55.212817
11185 01:03:55.213458 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11187 01:03:55.224406 Control ioctls:
11188 01:03:55.231890 <LAVA_SIGNAL_TESTSET STOP>
11189 01:03:55.232733 Received signal: <TESTSET> STOP
11190 01:03:55.233134 Closing test_set Input-ioctls
11191 01:03:55.241159 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11192 01:03:55.242049 Received signal: <TESTSET> START Control-ioctls
11193 01:03:55.242468 Starting test_set Control-ioctls
11194 01:03:55.244643 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11195 01:03:55.269908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11196 01:03:55.270519 test VIDIOC_QUERYCTRL: OK
11197 01:03:55.271161 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11199 01:03:55.290890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11200 01:03:55.291758 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11202 01:03:55.294090 test VIDIOC_G/S_CTRL: OK
11203 01:03:55.315691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11204 01:03:55.316518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11206 01:03:55.319124 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11207 01:03:55.346288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11208 01:03:55.347124 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11210 01:03:55.356259 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11211 01:03:55.364828 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11212 01:03:55.393829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11213 01:03:55.394713 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11215 01:03:55.397034 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11216 01:03:55.419681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11217 01:03:55.420676 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11219 01:03:55.422689 Standard Controls: 16 Private Controls: 0
11220 01:03:55.430265
11221 01:03:55.446477 Format ioctls:
11222 01:03:55.453634 <LAVA_SIGNAL_TESTSET STOP>
11223 01:03:55.454526 Received signal: <TESTSET> STOP
11224 01:03:55.454935 Closing test_set Control-ioctls
11225 01:03:55.463281 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11226 01:03:55.464133 Received signal: <TESTSET> START Format-ioctls
11227 01:03:55.464545 Starting test_set Format-ioctls
11228 01:03:55.466478 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11229 01:03:55.494820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11230 01:03:55.495686 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11232 01:03:55.497847 test VIDIOC_G/S_PARM: OK
11233 01:03:55.515143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11234 01:03:55.515970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11236 01:03:55.518085 test VIDIOC_G_FBUF: OK (Not Supported)
11237 01:03:55.546355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11238 01:03:55.547190 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11240 01:03:55.549717 test VIDIOC_G_FMT: OK
11241 01:03:55.574784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11242 01:03:55.575641 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11244 01:03:55.578067 test VIDIOC_TRY_FMT: OK
11245 01:03:55.599239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11246 01:03:55.600269 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11248 01:03:55.609314 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11249 01:03:55.614213 test VIDIOC_S_FMT: FAIL
11250 01:03:55.640114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11251 01:03:55.640955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11253 01:03:55.643649 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11254 01:03:55.667426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11255 01:03:55.668300 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11257 01:03:55.670011 test Cropping: OK
11258 01:03:55.692198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11259 01:03:55.693021 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11261 01:03:55.695517 test Composing: OK (Not Supported)
11262 01:03:55.722692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11263 01:03:55.723527 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11265 01:03:55.725297 test Scaling: OK (Not Supported)
11266 01:03:55.750597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11267 01:03:55.751167
11268 01:03:55.751800 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11270 01:03:55.760119 Codec ioctls:
11271 01:03:55.768082 <LAVA_SIGNAL_TESTSET STOP>
11272 01:03:55.768916 Received signal: <TESTSET> STOP
11273 01:03:55.769309 Closing test_set Format-ioctls
11274 01:03:55.777696 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11275 01:03:55.778568 Received signal: <TESTSET> START Codec-ioctls
11276 01:03:55.778967 Starting test_set Codec-ioctls
11277 01:03:55.780715 test VIDIOC_(TRY_)ENCODER_CMD: OK
11278 01:03:55.806373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11279 01:03:55.807353 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11281 01:03:55.821096 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11282 01:03:55.850274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11283 01:03:55.851132 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11285 01:03:55.857445 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11286 01:03:55.874308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11287 01:03:55.874882
11288 01:03:55.875527 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11290 01:03:55.892223 Buffer ioctls:
11291 01:03:55.899877 <LAVA_SIGNAL_TESTSET STOP>
11292 01:03:55.900714 Received signal: <TESTSET> STOP
11293 01:03:55.901109 Closing test_set Codec-ioctls
11294 01:03:55.908494 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11295 01:03:55.909390 Received signal: <TESTSET> START Buffer-ioctls
11296 01:03:55.909815 Starting test_set Buffer-ioctls
11297 01:03:55.912148 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11298 01:03:55.937455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11299 01:03:55.938077 test VIDIOC_EXPBUF: OK
11300 01:03:55.938734 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11302 01:03:55.958240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11303 01:03:55.959074 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11305 01:03:55.961348 test Requests: OK (Not Supported)
11306 01:03:55.986103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11307 01:03:55.986665
11308 01:03:55.987311 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11310 01:03:55.997991 Test input 0:
11311 01:03:56.007171
11312 01:03:56.020204 Streaming ioctls:
11313 01:03:56.029324 <LAVA_SIGNAL_TESTSET STOP>
11314 01:03:56.030065 Received signal: <TESTSET> STOP
11315 01:03:56.030504 Closing test_set Buffer-ioctls
11316 01:03:56.039632 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11317 01:03:56.040542 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11318 01:03:56.040957 Starting test_set Streaming-ioctls_Test-input-0
11319 01:03:56.042656 test read/write: OK (Not Supported)
11320 01:03:56.066761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11321 01:03:56.067600 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11323 01:03:56.073271 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11324 01:03:56.083990 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11325 01:03:56.094106 test blocking wait: FAIL
11326 01:03:56.119305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11327 01:03:56.120225 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11329 01:03:56.129076 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11330 01:03:56.132362 test MMAP (select): FAIL
11331 01:03:56.162810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11332 01:03:56.163659 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11334 01:03:56.169480 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11335 01:03:56.173326 test MMAP (epoll): FAIL
11336 01:03:56.198797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11337 01:03:56.199633 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11339 01:03:56.208772 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11340 01:03:56.221158 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11341 01:03:56.226293 test USERPTR (select): FAIL
11342 01:03:56.251827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11343 01:03:56.252676 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11345 01:03:56.258275 test DMABUF: Cannot test, specify --expbuf-device
11346 01:03:56.263628
11347 01:03:56.281680 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11348 01:03:56.285207 <LAVA_TEST_RUNNER EXIT>
11349 01:03:56.286066 ok: lava_test_shell seems to have completed
11350 01:03:56.286480 Marking unfinished test run as failed
11352 01:03:56.291553 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11353 01:03:56.292203 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11354 01:03:56.292690 end: 3 lava-test-retry (duration 00:00:03) [common]
11355 01:03:56.293186 start: 4 finalize (timeout 00:08:08) [common]
11356 01:03:56.293692 start: 4.1 power-off (timeout 00:00:30) [common]
11357 01:03:56.294541 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11358 01:03:56.415847 >> Command sent successfully.
11359 01:03:56.419638 Returned 0 in 0 seconds
11360 01:03:56.520526 end: 4.1 power-off (duration 00:00:00) [common]
11362 01:03:56.522074 start: 4.2 read-feedback (timeout 00:08:07) [common]
11363 01:03:56.523312 Listened to connection for namespace 'common' for up to 1s
11364 01:03:57.524003 Finalising connection for namespace 'common'
11365 01:03:57.524716 Disconnecting from shell: Finalise
11366 01:03:57.525136 / #
11367 01:03:57.626169 end: 4.2 read-feedback (duration 00:00:01) [common]
11368 01:03:57.626886 end: 4 finalize (duration 00:00:01) [common]
11369 01:03:57.627512 Cleaning after the job
11370 01:03:57.628022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/ramdisk
11371 01:03:57.648416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/kernel
11372 01:03:57.670177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/dtb
11373 01:03:57.670568 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571123/tftp-deploy-vb3mdyvn/modules
11374 01:03:57.679835 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571123
11375 01:03:57.738328 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571123
11376 01:03:57.738515 Job finished correctly