Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 16
- Errors: 1
- Kernel Errors: 35
- Boot result: PASS
1 00:55:21.728557 lava-dispatcher, installed at version: 2023.10
2 00:55:21.728781 start: 0 validate
3 00:55:21.728920 Start time: 2024-01-19 00:55:21.728912+00:00 (UTC)
4 00:55:21.729044 Using caching service: 'http://localhost/cache/?uri=%s'
5 00:55:21.729178 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 00:55:21.999926 Using caching service: 'http://localhost/cache/?uri=%s'
7 00:55:22.000615 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 00:55:53.525724 Using caching service: 'http://localhost/cache/?uri=%s'
9 00:55:53.526399 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 00:55:53.799174 Using caching service: 'http://localhost/cache/?uri=%s'
11 00:55:53.799859 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.72-cip13-30-g79e2886a5da69%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 00:56:04.344965 validate duration: 42.62
14 00:56:04.345319 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:56:04.345448 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:56:04.345581 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:56:04.345739 Not decompressing ramdisk as can be used compressed.
18 00:56:04.345856 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 00:56:04.345951 saving as /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/ramdisk/rootfs.cpio.gz
20 00:56:04.346046 total size: 26246609 (25 MB)
21 00:56:04.613641 progress 0 % (0 MB)
22 00:56:04.621070 progress 5 % (1 MB)
23 00:56:04.628046 progress 10 % (2 MB)
24 00:56:04.635104 progress 15 % (3 MB)
25 00:56:04.642153 progress 20 % (5 MB)
26 00:56:04.649279 progress 25 % (6 MB)
27 00:56:04.656581 progress 30 % (7 MB)
28 00:56:04.663647 progress 35 % (8 MB)
29 00:56:04.670772 progress 40 % (10 MB)
30 00:56:04.677821 progress 45 % (11 MB)
31 00:56:04.684887 progress 50 % (12 MB)
32 00:56:04.692264 progress 55 % (13 MB)
33 00:56:04.699584 progress 60 % (15 MB)
34 00:56:04.706922 progress 65 % (16 MB)
35 00:56:04.714094 progress 70 % (17 MB)
36 00:56:04.720998 progress 75 % (18 MB)
37 00:56:04.727897 progress 80 % (20 MB)
38 00:56:04.735088 progress 85 % (21 MB)
39 00:56:04.742266 progress 90 % (22 MB)
40 00:56:04.749052 progress 95 % (23 MB)
41 00:56:04.755876 progress 100 % (25 MB)
42 00:56:04.756142 25 MB downloaded in 0.41 s (61.04 MB/s)
43 00:56:04.756300 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:56:04.756548 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:56:04.756637 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:56:04.756724 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:56:04.756863 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 00:56:04.756935 saving as /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/kernel/Image
50 00:56:04.756998 total size: 51532288 (49 MB)
51 00:56:04.757061 No compression specified
52 00:56:04.758297 progress 0 % (0 MB)
53 00:56:04.772451 progress 5 % (2 MB)
54 00:56:04.786874 progress 10 % (4 MB)
55 00:56:04.800773 progress 15 % (7 MB)
56 00:56:04.814600 progress 20 % (9 MB)
57 00:56:04.828976 progress 25 % (12 MB)
58 00:56:04.842766 progress 30 % (14 MB)
59 00:56:04.856388 progress 35 % (17 MB)
60 00:56:04.870547 progress 40 % (19 MB)
61 00:56:04.884290 progress 45 % (22 MB)
62 00:56:04.897842 progress 50 % (24 MB)
63 00:56:04.911586 progress 55 % (27 MB)
64 00:56:04.925535 progress 60 % (29 MB)
65 00:56:04.939090 progress 65 % (31 MB)
66 00:56:04.952473 progress 70 % (34 MB)
67 00:56:04.966458 progress 75 % (36 MB)
68 00:56:04.979790 progress 80 % (39 MB)
69 00:56:04.993147 progress 85 % (41 MB)
70 00:56:05.007174 progress 90 % (44 MB)
71 00:56:05.020699 progress 95 % (46 MB)
72 00:56:05.033577 progress 100 % (49 MB)
73 00:56:05.033781 49 MB downloaded in 0.28 s (177.56 MB/s)
74 00:56:05.033928 end: 1.2.1 http-download (duration 00:00:00) [common]
76 00:56:05.034159 end: 1.2 download-retry (duration 00:00:00) [common]
77 00:56:05.034247 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:56:05.034341 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:56:05.034482 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 00:56:05.034554 saving as /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/dtb/mt8192-asurada-spherion-r0.dtb
81 00:56:05.034620 total size: 47278 (0 MB)
82 00:56:05.034682 No compression specified
83 00:56:05.299924 progress 69 % (0 MB)
84 00:56:05.300256 progress 100 % (0 MB)
85 00:56:05.300419 0 MB downloaded in 0.27 s (0.17 MB/s)
86 00:56:05.300564 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:56:05.300793 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:56:05.300884 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:56:05.300970 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:56:05.301105 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.72-cip13-30-g79e2886a5da69/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 00:56:05.301177 saving as /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/modules/modules.tar
93 00:56:05.301238 total size: 8625444 (8 MB)
94 00:56:05.301322 Using unxz to decompress xz
95 00:56:05.305662 progress 0 % (0 MB)
96 00:56:05.326644 progress 5 % (0 MB)
97 00:56:05.350034 progress 10 % (0 MB)
98 00:56:05.373627 progress 15 % (1 MB)
99 00:56:05.397190 progress 20 % (1 MB)
100 00:56:05.421244 progress 25 % (2 MB)
101 00:56:05.446912 progress 30 % (2 MB)
102 00:56:05.473069 progress 35 % (2 MB)
103 00:56:05.496557 progress 40 % (3 MB)
104 00:56:05.520875 progress 45 % (3 MB)
105 00:56:05.546026 progress 50 % (4 MB)
106 00:56:05.570594 progress 55 % (4 MB)
107 00:56:05.595622 progress 60 % (4 MB)
108 00:56:05.623391 progress 65 % (5 MB)
109 00:56:05.648133 progress 70 % (5 MB)
110 00:56:05.672056 progress 75 % (6 MB)
111 00:56:05.699109 progress 80 % (6 MB)
112 00:56:05.725040 progress 85 % (7 MB)
113 00:56:05.750123 progress 90 % (7 MB)
114 00:56:05.781454 progress 95 % (7 MB)
115 00:56:05.809062 progress 100 % (8 MB)
116 00:56:05.814041 8 MB downloaded in 0.51 s (16.04 MB/s)
117 00:56:05.814295 end: 1.4.1 http-download (duration 00:00:01) [common]
119 00:56:05.814560 end: 1.4 download-retry (duration 00:00:01) [common]
120 00:56:05.814655 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 00:56:05.814749 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 00:56:05.814831 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:56:05.814922 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 00:56:05.815154 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_
125 00:56:05.815292 makedir: /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin
126 00:56:05.815399 makedir: /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/tests
127 00:56:05.815500 makedir: /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/results
128 00:56:05.815618 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-add-keys
129 00:56:05.815770 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-add-sources
130 00:56:05.815904 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-background-process-start
131 00:56:05.816038 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-background-process-stop
132 00:56:05.816168 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-common-functions
133 00:56:05.816297 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-echo-ipv4
134 00:56:05.816426 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-install-packages
135 00:56:05.816558 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-installed-packages
136 00:56:05.816686 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-os-build
137 00:56:05.816814 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-probe-channel
138 00:56:05.816945 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-probe-ip
139 00:56:05.817074 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-target-ip
140 00:56:05.817203 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-target-mac
141 00:56:05.817331 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-target-storage
142 00:56:05.817464 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-case
143 00:56:05.817639 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-event
144 00:56:05.817767 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-feedback
145 00:56:05.817896 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-raise
146 00:56:05.818031 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-reference
147 00:56:05.818163 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-runner
148 00:56:05.818292 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-set
149 00:56:05.818428 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-test-shell
150 00:56:05.818561 Updating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-install-packages (oe)
151 00:56:05.818718 Updating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/bin/lava-installed-packages (oe)
152 00:56:05.818843 Creating /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/environment
153 00:56:05.818946 LAVA metadata
154 00:56:05.819022 - LAVA_JOB_ID=12571064
155 00:56:05.819089 - LAVA_DISPATCHER_IP=192.168.201.1
156 00:56:05.819191 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 00:56:05.819258 skipped lava-vland-overlay
158 00:56:05.819333 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 00:56:05.819415 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 00:56:05.819483 skipped lava-multinode-overlay
161 00:56:05.819556 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 00:56:05.819640 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 00:56:05.819717 Loading test definitions
164 00:56:05.819809 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 00:56:05.819886 Using /lava-12571064 at stage 0
166 00:56:05.820199 uuid=12571064_1.5.2.3.1 testdef=None
167 00:56:05.820289 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 00:56:05.820375 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 00:56:05.820898 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 00:56:05.821121 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 00:56:05.821821 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 00:56:05.822060 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 00:56:05.822657 runner path: /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/0/tests/0_v4l2-compliance-uvc test_uuid 12571064_1.5.2.3.1
176 00:56:05.822816 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 00:56:05.823028 Creating lava-test-runner.conf files
179 00:56:05.823093 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12571064/lava-overlay-c0gr4c9_/lava-12571064/0 for stage 0
180 00:56:05.823183 - 0_v4l2-compliance-uvc
181 00:56:05.823284 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 00:56:05.823367 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 00:56:05.830215 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 00:56:05.830320 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 00:56:05.830407 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 00:56:05.830492 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 00:56:05.830584 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 00:56:06.555965 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 00:56:06.556395 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 00:56:06.556532 extracting modules file /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12571064/extract-overlay-ramdisk-605ccz70/ramdisk
191 00:56:06.794733 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 00:56:06.794903 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 00:56:06.795002 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571064/compress-overlay-zws69u5p/overlay-1.5.2.4.tar.gz to ramdisk
194 00:56:06.795079 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12571064/compress-overlay-zws69u5p/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12571064/extract-overlay-ramdisk-605ccz70/ramdisk
195 00:56:06.801676 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 00:56:06.801790 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 00:56:06.801884 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 00:56:06.801973 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 00:56:06.802052 Building ramdisk /var/lib/lava/dispatcher/tmp/12571064/extract-overlay-ramdisk-605ccz70/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12571064/extract-overlay-ramdisk-605ccz70/ramdisk
200 00:56:07.441512 >> 228442 blocks
201 00:56:11.438260 rename /var/lib/lava/dispatcher/tmp/12571064/extract-overlay-ramdisk-605ccz70/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/ramdisk/ramdisk.cpio.gz
202 00:56:11.438717 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 00:56:11.438844 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 00:56:11.438948 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 00:56:11.439058 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/kernel/Image'
206 00:56:23.848343 Returned 0 in 12 seconds
207 00:56:23.949013 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/kernel/image.itb
208 00:56:24.586513 output: FIT description: Kernel Image image with one or more FDT blobs
209 00:56:24.586914 output: Created: Fri Jan 19 00:56:24 2024
210 00:56:24.586991 output: Image 0 (kernel-1)
211 00:56:24.587061 output: Description:
212 00:56:24.587128 output: Created: Fri Jan 19 00:56:24 2024
213 00:56:24.587191 output: Type: Kernel Image
214 00:56:24.587251 output: Compression: lzma compressed
215 00:56:24.587310 output: Data Size: 12048624 Bytes = 11766.23 KiB = 11.49 MiB
216 00:56:24.587368 output: Architecture: AArch64
217 00:56:24.587426 output: OS: Linux
218 00:56:24.587481 output: Load Address: 0x00000000
219 00:56:24.587537 output: Entry Point: 0x00000000
220 00:56:24.587593 output: Hash algo: crc32
221 00:56:24.587649 output: Hash value: a52aa383
222 00:56:24.587705 output: Image 1 (fdt-1)
223 00:56:24.587762 output: Description: mt8192-asurada-spherion-r0
224 00:56:24.587816 output: Created: Fri Jan 19 00:56:24 2024
225 00:56:24.587870 output: Type: Flat Device Tree
226 00:56:24.587924 output: Compression: uncompressed
227 00:56:24.587978 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 00:56:24.588032 output: Architecture: AArch64
229 00:56:24.588086 output: Hash algo: crc32
230 00:56:24.588140 output: Hash value: cc4352de
231 00:56:24.588194 output: Image 2 (ramdisk-1)
232 00:56:24.588247 output: Description: unavailable
233 00:56:24.588300 output: Created: Fri Jan 19 00:56:24 2024
234 00:56:24.588359 output: Type: RAMDisk Image
235 00:56:24.588431 output: Compression: Unknown Compression
236 00:56:24.588487 output: Data Size: 39355230 Bytes = 38432.84 KiB = 37.53 MiB
237 00:56:24.588541 output: Architecture: AArch64
238 00:56:24.588640 output: OS: Linux
239 00:56:24.588701 output: Load Address: unavailable
240 00:56:24.588771 output: Entry Point: unavailable
241 00:56:24.588833 output: Hash algo: crc32
242 00:56:24.588888 output: Hash value: d9c5d904
243 00:56:24.588946 output: Default Configuration: 'conf-1'
244 00:56:24.589018 output: Configuration 0 (conf-1)
245 00:56:24.589074 output: Description: mt8192-asurada-spherion-r0
246 00:56:24.589129 output: Kernel: kernel-1
247 00:56:24.589183 output: Init Ramdisk: ramdisk-1
248 00:56:24.589238 output: FDT: fdt-1
249 00:56:24.589291 output: Loadables: kernel-1
250 00:56:24.589345 output:
251 00:56:24.589562 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 00:56:24.589660 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 00:56:24.589776 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 00:56:24.589890 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 00:56:24.589984 No LXC device requested
256 00:56:24.590073 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 00:56:24.590160 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 00:56:24.590244 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 00:56:24.590324 Checking files for TFTP limit of 4294967296 bytes.
260 00:56:24.590964 end: 1 tftp-deploy (duration 00:00:20) [common]
261 00:56:24.591204 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 00:56:24.591304 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 00:56:24.591438 substitutions:
264 00:56:24.591509 - {DTB}: 12571064/tftp-deploy-w3kw8ada/dtb/mt8192-asurada-spherion-r0.dtb
265 00:56:24.591575 - {INITRD}: 12571064/tftp-deploy-w3kw8ada/ramdisk/ramdisk.cpio.gz
266 00:56:24.591636 - {KERNEL}: 12571064/tftp-deploy-w3kw8ada/kernel/Image
267 00:56:24.591694 - {LAVA_MAC}: None
268 00:56:24.591752 - {PRESEED_CONFIG}: None
269 00:56:24.591808 - {PRESEED_LOCAL}: None
270 00:56:24.591864 - {RAMDISK}: 12571064/tftp-deploy-w3kw8ada/ramdisk/ramdisk.cpio.gz
271 00:56:24.591920 - {ROOT_PART}: None
272 00:56:24.591976 - {ROOT}: None
273 00:56:24.592031 - {SERVER_IP}: 192.168.201.1
274 00:56:24.592086 - {TEE}: None
275 00:56:24.592141 Parsed boot commands:
276 00:56:24.592197 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 00:56:24.592380 Parsed boot commands: tftpboot 192.168.201.1 12571064/tftp-deploy-w3kw8ada/kernel/image.itb 12571064/tftp-deploy-w3kw8ada/kernel/cmdline
278 00:56:24.592470 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 00:56:24.592561 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 00:56:24.592665 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 00:56:24.592749 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 00:56:24.592823 Not connected, no need to disconnect.
283 00:56:24.592899 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 00:56:24.592982 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 00:56:24.593048 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 00:56:24.596972 Setting prompt string to ['lava-test: # ']
287 00:56:24.597382 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 00:56:24.597506 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 00:56:24.597606 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 00:56:24.597700 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 00:56:24.597933 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 00:56:29.727244 >> Command sent successfully.
293 00:56:29.729959 Returned 0 in 5 seconds
294 00:56:29.830369 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 00:56:29.830713 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 00:56:29.830815 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 00:56:29.830905 Setting prompt string to 'Starting depthcharge on Spherion...'
299 00:56:29.830973 Changing prompt to 'Starting depthcharge on Spherion...'
300 00:56:29.831041 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 00:56:29.831368 [Enter `^Ec?' for help]
302 00:56:30.002306
303 00:56:30.002472
304 00:56:30.002544 F0: 102B 0000
305 00:56:30.002610
306 00:56:30.002670 F3: 1001 0000 [0200]
307 00:56:30.002730
308 00:56:30.005444 F3: 1001 0000
309 00:56:30.005590
310 00:56:30.005657 F7: 102D 0000
311 00:56:30.005721
312 00:56:30.009071 F1: 0000 0000
313 00:56:30.009160
314 00:56:30.009231 V0: 0000 0000 [0001]
315 00:56:30.009296
316 00:56:30.012135 00: 0007 8000
317 00:56:30.012242
318 00:56:30.012344 01: 0000 0000
319 00:56:30.012423
320 00:56:30.015676 BP: 0C00 0209 [0000]
321 00:56:30.015763
322 00:56:30.015829 G0: 1182 0000
323 00:56:30.015892
324 00:56:30.019196 EC: 0000 0021 [4000]
325 00:56:30.019283
326 00:56:30.019350 S7: 0000 0000 [0000]
327 00:56:30.019412
328 00:56:30.022736 CC: 0000 0000 [0001]
329 00:56:30.022825
330 00:56:30.022892 T0: 0000 0040 [010F]
331 00:56:30.022956
332 00:56:30.023036 Jump to BL
333 00:56:30.023109
334 00:56:30.049193
335 00:56:30.049373
336 00:56:30.049501
337 00:56:30.055998 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 00:56:30.059382 ARM64: Exception handlers installed.
339 00:56:30.062999 ARM64: Testing exception
340 00:56:30.066236 ARM64: Done test exception
341 00:56:30.073068 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 00:56:30.082929 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 00:56:30.089843 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 00:56:30.099820 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 00:56:30.106649 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 00:56:30.116604 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 00:56:30.127578 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 00:56:30.134047 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 00:56:30.152235 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 00:56:30.155005 WDT: Last reset was cold boot
351 00:56:30.158425 SPI1(PAD0) initialized at 2873684 Hz
352 00:56:30.161997 SPI5(PAD0) initialized at 992727 Hz
353 00:56:30.165084 VBOOT: Loading verstage.
354 00:56:30.171833 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 00:56:30.175228 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 00:56:30.178502 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 00:56:30.181791 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 00:56:30.189419 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 00:56:30.196203 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 00:56:30.206980 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 00:56:30.207131
362 00:56:30.207207
363 00:56:30.216997 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 00:56:30.220375 ARM64: Exception handlers installed.
365 00:56:30.223700 ARM64: Testing exception
366 00:56:30.223803 ARM64: Done test exception
367 00:56:30.230681 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 00:56:30.234022 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 00:56:30.247833 Probing TPM: . done!
370 00:56:30.247990 TPM ready after 0 ms
371 00:56:30.254787 Connected to device vid:did:rid of 1ae0:0028:00
372 00:56:30.261862 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 00:56:30.302393 Initialized TPM device CR50 revision 0
374 00:56:30.313702 tlcl_send_startup: Startup return code is 0
375 00:56:30.313856 TPM: setup succeeded
376 00:56:30.325148 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 00:56:30.333830 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 00:56:30.345530 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 00:56:30.355050 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 00:56:30.358277 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 00:56:30.362109 in-header: 03 07 00 00 08 00 00 00
382 00:56:30.365975 in-data: aa e4 47 04 13 02 00 00
383 00:56:30.369739 Chrome EC: UHEPI supported
384 00:56:30.376479 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 00:56:30.380022 in-header: 03 9d 00 00 08 00 00 00
386 00:56:30.384093 in-data: 10 20 20 08 00 00 00 00
387 00:56:30.384202 Phase 1
388 00:56:30.387608 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 00:56:30.394681 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 00:56:30.402009 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 00:56:30.402140 Recovery requested (1009000e)
392 00:56:30.411250 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 00:56:30.416490 tlcl_extend: response is 0
394 00:56:30.424683 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 00:56:30.430055 tlcl_extend: response is 0
396 00:56:30.436616 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 00:56:30.457647 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 00:56:30.465062 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 00:56:30.465196
400 00:56:30.465269
401 00:56:30.472331 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 00:56:30.476499 ARM64: Exception handlers installed.
403 00:56:30.480368 ARM64: Testing exception
404 00:56:30.483175 ARM64: Done test exception
405 00:56:30.499828 pmic_efuse_setting: Set efuses in 11 msecs
406 00:56:30.505337 pmwrap_interface_init: Select PMIF_VLD_RDY
407 00:56:30.512699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 00:56:30.516095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 00:56:30.519896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 00:56:30.527194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 00:56:30.531072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 00:56:30.534712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 00:56:30.542078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 00:56:30.545768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 00:56:30.548992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 00:56:30.555613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 00:56:30.558886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 00:56:30.565452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 00:56:30.568822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 00:56:30.575726 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 00:56:30.579029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 00:56:30.585416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 00:56:30.592206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 00:56:30.598683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 00:56:30.602340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 00:56:30.609951 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 00:56:30.613718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 00:56:30.620939 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 00:56:30.624017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 00:56:30.631328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 00:56:30.635004 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 00:56:30.641282 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 00:56:30.648769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 00:56:30.652460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 00:56:30.656160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 00:56:30.662572 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 00:56:30.666332 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 00:56:30.673639 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 00:56:30.677298 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 00:56:30.680940 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 00:56:30.688351 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 00:56:30.691799 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 00:56:30.695298 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 00:56:30.701925 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 00:56:30.705337 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 00:56:30.711908 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 00:56:30.715140 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 00:56:30.718549 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 00:56:30.721879 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 00:56:30.728613 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 00:56:30.731894 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 00:56:30.735198 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 00:56:30.741779 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 00:56:30.745401 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 00:56:30.748508 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 00:56:30.751894 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 00:56:30.758560 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 00:56:30.765090 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 00:56:30.774992 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 00:56:30.778324 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 00:56:30.785275 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 00:56:30.795281 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 00:56:30.798709 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 00:56:30.805248 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 00:56:30.808628 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 00:56:30.815401 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1b
467 00:56:30.821933 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 00:56:30.825433 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 00:56:30.828795 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 00:56:30.839836 [RTC]rtc_get_frequency_meter,154: input=15, output=795
471 00:56:30.843141 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 00:56:30.850055 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 00:56:30.853329 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 00:56:30.856552 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 00:56:30.859598 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 00:56:30.863335 ADC[4]: Raw value=899260 ID=7
477 00:56:30.866553 ADC[3]: Raw value=212700 ID=1
478 00:56:30.869797 RAM Code: 0x71
479 00:56:30.873235 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 00:56:30.876447 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 00:56:30.886976 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 00:56:30.893968 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 00:56:30.897257 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 00:56:30.900616 in-header: 03 07 00 00 08 00 00 00
485 00:56:30.904062 in-data: aa e4 47 04 13 02 00 00
486 00:56:30.904157 Chrome EC: UHEPI supported
487 00:56:30.910768 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 00:56:30.914918 in-header: 03 d5 00 00 08 00 00 00
489 00:56:30.918508 in-data: 98 20 60 08 00 00 00 00
490 00:56:30.922261 MRC: failed to locate region type 0.
491 00:56:30.929281 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 00:56:30.932817 DRAM-K: Running full calibration
493 00:56:30.939618 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 00:56:30.939738 header.status = 0x0
495 00:56:30.943284 header.version = 0x6 (expected: 0x6)
496 00:56:30.946721 header.size = 0xd00 (expected: 0xd00)
497 00:56:30.946819 header.flags = 0x0
498 00:56:30.953359 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 00:56:30.972118 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 00:56:30.978639 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 00:56:30.981956 dram_init: ddr_geometry: 2
502 00:56:30.985432 [EMI] MDL number = 2
503 00:56:30.985546 [EMI] Get MDL freq = 0
504 00:56:30.988711 dram_init: ddr_type: 0
505 00:56:30.988800 is_discrete_lpddr4: 1
506 00:56:30.991919 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 00:56:30.992008
508 00:56:30.992076
509 00:56:30.995243 [Bian_co] ETT version 0.0.0.1
510 00:56:31.002020 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 00:56:31.002132
512 00:56:31.005195 dramc_set_vcore_voltage set vcore to 650000
513 00:56:31.005282 Read voltage for 800, 4
514 00:56:31.008827 Vio18 = 0
515 00:56:31.008916 Vcore = 650000
516 00:56:31.008984 Vdram = 0
517 00:56:31.011806 Vddq = 0
518 00:56:31.011893 Vmddr = 0
519 00:56:31.015298 dram_init: config_dvfs: 1
520 00:56:31.018839 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 00:56:31.025333 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 00:56:31.028515 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 00:56:31.031965 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 00:56:31.035393 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 00:56:31.038679 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 00:56:31.042074 MEM_TYPE=3, freq_sel=18
527 00:56:31.045301 sv_algorithm_assistance_LP4_1600
528 00:56:31.048717 ============ PULL DRAM RESETB DOWN ============
529 00:56:31.052067 ========== PULL DRAM RESETB DOWN end =========
530 00:56:31.058660 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 00:56:31.061859 ===================================
532 00:56:31.065223 LPDDR4 DRAM CONFIGURATION
533 00:56:31.065342 ===================================
534 00:56:31.068643 EX_ROW_EN[0] = 0x0
535 00:56:31.072173 EX_ROW_EN[1] = 0x0
536 00:56:31.072263 LP4Y_EN = 0x0
537 00:56:31.075283 WORK_FSP = 0x0
538 00:56:31.075369 WL = 0x2
539 00:56:31.078778 RL = 0x2
540 00:56:31.078864 BL = 0x2
541 00:56:31.082130 RPST = 0x0
542 00:56:31.082215 RD_PRE = 0x0
543 00:56:31.085305 WR_PRE = 0x1
544 00:56:31.085417 WR_PST = 0x0
545 00:56:31.088724 DBI_WR = 0x0
546 00:56:31.088811 DBI_RD = 0x0
547 00:56:31.092082 OTF = 0x1
548 00:56:31.095320 ===================================
549 00:56:31.098890 ===================================
550 00:56:31.099006 ANA top config
551 00:56:31.102293 ===================================
552 00:56:31.105375 DLL_ASYNC_EN = 0
553 00:56:31.108987 ALL_SLAVE_EN = 1
554 00:56:31.112059 NEW_RANK_MODE = 1
555 00:56:31.112148 DLL_IDLE_MODE = 1
556 00:56:31.115658 LP45_APHY_COMB_EN = 1
557 00:56:31.119107 TX_ODT_DIS = 1
558 00:56:31.122347 NEW_8X_MODE = 1
559 00:56:31.125435 ===================================
560 00:56:31.128718 ===================================
561 00:56:31.128806 data_rate = 1600
562 00:56:31.132375 CKR = 1
563 00:56:31.135631 DQ_P2S_RATIO = 8
564 00:56:31.139073 ===================================
565 00:56:31.142089 CA_P2S_RATIO = 8
566 00:56:31.145297 DQ_CA_OPEN = 0
567 00:56:31.148760 DQ_SEMI_OPEN = 0
568 00:56:31.148853 CA_SEMI_OPEN = 0
569 00:56:31.152198 CA_FULL_RATE = 0
570 00:56:31.155294 DQ_CKDIV4_EN = 1
571 00:56:31.158866 CA_CKDIV4_EN = 1
572 00:56:31.162142 CA_PREDIV_EN = 0
573 00:56:31.165845 PH8_DLY = 0
574 00:56:31.165945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 00:56:31.169572 DQ_AAMCK_DIV = 4
576 00:56:31.173294 CA_AAMCK_DIV = 4
577 00:56:31.176831 CA_ADMCK_DIV = 4
578 00:56:31.176935 DQ_TRACK_CA_EN = 0
579 00:56:31.180522 CA_PICK = 800
580 00:56:31.184400 CA_MCKIO = 800
581 00:56:31.188210 MCKIO_SEMI = 0
582 00:56:31.188308 PLL_FREQ = 3068
583 00:56:31.191970 DQ_UI_PI_RATIO = 32
584 00:56:31.195971 CA_UI_PI_RATIO = 0
585 00:56:31.199601 ===================================
586 00:56:31.203360 ===================================
587 00:56:31.203465 memory_type:LPDDR4
588 00:56:31.207227 GP_NUM : 10
589 00:56:31.207322 SRAM_EN : 1
590 00:56:31.210951 MD32_EN : 0
591 00:56:31.214463 ===================================
592 00:56:31.214558 [ANA_INIT] >>>>>>>>>>>>>>
593 00:56:31.218214 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 00:56:31.222016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 00:56:31.225642 ===================================
596 00:56:31.229430 data_rate = 1600,PCW = 0X7600
597 00:56:31.233104 ===================================
598 00:56:31.237021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 00:56:31.240756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 00:56:31.247981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 00:56:31.251672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 00:56:31.255438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 00:56:31.258982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 00:56:31.259078 [ANA_INIT] flow start
605 00:56:31.262849 [ANA_INIT] PLL >>>>>>>>
606 00:56:31.262939 [ANA_INIT] PLL <<<<<<<<
607 00:56:31.266802 [ANA_INIT] MIDPI >>>>>>>>
608 00:56:31.270421 [ANA_INIT] MIDPI <<<<<<<<
609 00:56:31.270544 [ANA_INIT] DLL >>>>>>>>
610 00:56:31.273967 [ANA_INIT] flow end
611 00:56:31.277640 ============ LP4 DIFF to SE enter ============
612 00:56:31.281176 ============ LP4 DIFF to SE exit ============
613 00:56:31.284974 [ANA_INIT] <<<<<<<<<<<<<
614 00:56:31.288648 [Flow] Enable top DCM control >>>>>
615 00:56:31.288747 [Flow] Enable top DCM control <<<<<
616 00:56:31.292383 Enable DLL master slave shuffle
617 00:56:31.300173 ==============================================================
618 00:56:31.300300 Gating Mode config
619 00:56:31.306605 ==============================================================
620 00:56:31.306716 Config description:
621 00:56:31.316346 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 00:56:31.323364 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 00:56:31.329967 SELPH_MODE 0: By rank 1: By Phase
624 00:56:31.333419 ==============================================================
625 00:56:31.336541 GAT_TRACK_EN = 1
626 00:56:31.340025 RX_GATING_MODE = 2
627 00:56:31.343122 RX_GATING_TRACK_MODE = 2
628 00:56:31.346355 SELPH_MODE = 1
629 00:56:31.349758 PICG_EARLY_EN = 1
630 00:56:31.353332 VALID_LAT_VALUE = 1
631 00:56:31.356728 ==============================================================
632 00:56:31.360179 Enter into Gating configuration >>>>
633 00:56:31.363329 Exit from Gating configuration <<<<
634 00:56:31.366850 Enter into DVFS_PRE_config >>>>>
635 00:56:31.380029 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 00:56:31.383188 Exit from DVFS_PRE_config <<<<<
637 00:56:31.383288 Enter into PICG configuration >>>>
638 00:56:31.386659 Exit from PICG configuration <<<<
639 00:56:31.390046 [RX_INPUT] configuration >>>>>
640 00:56:31.393489 [RX_INPUT] configuration <<<<<
641 00:56:31.399961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 00:56:31.403309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 00:56:31.409931 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 00:56:31.416649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 00:56:31.423355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 00:56:31.430039 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 00:56:31.433395 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 00:56:31.436941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 00:56:31.440492 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 00:56:31.446893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 00:56:31.450206 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 00:56:31.453680 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 00:56:31.456842 ===================================
654 00:56:31.460329 LPDDR4 DRAM CONFIGURATION
655 00:56:31.463433 ===================================
656 00:56:31.463525 EX_ROW_EN[0] = 0x0
657 00:56:31.466973 EX_ROW_EN[1] = 0x0
658 00:56:31.470164 LP4Y_EN = 0x0
659 00:56:31.470252 WORK_FSP = 0x0
660 00:56:31.473665 WL = 0x2
661 00:56:31.473750 RL = 0x2
662 00:56:31.476743 BL = 0x2
663 00:56:31.476830 RPST = 0x0
664 00:56:31.480187 RD_PRE = 0x0
665 00:56:31.480274 WR_PRE = 0x1
666 00:56:31.483516 WR_PST = 0x0
667 00:56:31.483603 DBI_WR = 0x0
668 00:56:31.486934 DBI_RD = 0x0
669 00:56:31.487021 OTF = 0x1
670 00:56:31.490080 ===================================
671 00:56:31.493316 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 00:56:31.500112 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 00:56:31.503504 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 00:56:31.506714 ===================================
675 00:56:31.510101 LPDDR4 DRAM CONFIGURATION
676 00:56:31.513427 ===================================
677 00:56:31.513555 EX_ROW_EN[0] = 0x10
678 00:56:31.516636 EX_ROW_EN[1] = 0x0
679 00:56:31.516722 LP4Y_EN = 0x0
680 00:56:31.520043 WORK_FSP = 0x0
681 00:56:31.520132 WL = 0x2
682 00:56:31.523329 RL = 0x2
683 00:56:31.523415 BL = 0x2
684 00:56:31.527059 RPST = 0x0
685 00:56:31.527146 RD_PRE = 0x0
686 00:56:31.530087 WR_PRE = 0x1
687 00:56:31.530175 WR_PST = 0x0
688 00:56:31.533376 DBI_WR = 0x0
689 00:56:31.536936 DBI_RD = 0x0
690 00:56:31.537025 OTF = 0x1
691 00:56:31.540311 ===================================
692 00:56:31.547666 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 00:56:31.551374 nWR fixed to 40
694 00:56:31.551488 [ModeRegInit_LP4] CH0 RK0
695 00:56:31.554813 [ModeRegInit_LP4] CH0 RK1
696 00:56:31.558227 [ModeRegInit_LP4] CH1 RK0
697 00:56:31.558319 [ModeRegInit_LP4] CH1 RK1
698 00:56:31.561998 match AC timing 13
699 00:56:31.565532 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 00:56:31.569276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 00:56:31.573135 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 00:56:31.580477 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 00:56:31.584386 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 00:56:31.584487 [EMI DOE] emi_dcm 0
705 00:56:31.591361 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 00:56:31.591472 ==
707 00:56:31.595088 Dram Type= 6, Freq= 0, CH_0, rank 0
708 00:56:31.598902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 00:56:31.599001 ==
710 00:56:31.602802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 00:56:31.609374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 00:56:31.618169 [CA 0] Center 37 (7~68) winsize 62
713 00:56:31.622059 [CA 1] Center 37 (7~68) winsize 62
714 00:56:31.626097 [CA 2] Center 35 (5~66) winsize 62
715 00:56:31.629813 [CA 3] Center 35 (5~66) winsize 62
716 00:56:31.633367 [CA 4] Center 34 (4~65) winsize 62
717 00:56:31.633499 [CA 5] Center 34 (4~64) winsize 61
718 00:56:31.633571
719 00:56:31.637057 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 00:56:31.640764
721 00:56:31.640859 [CATrainingPosCal] consider 1 rank data
722 00:56:31.644328 u2DelayCellTimex100 = 270/100 ps
723 00:56:31.648188 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
724 00:56:31.652028 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 00:56:31.656077 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 00:56:31.660248 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 00:56:31.663954 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 00:56:31.667125 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 00:56:31.667222
730 00:56:31.671004 CA PerBit enable=1, Macro0, CA PI delay=34
731 00:56:31.671099
732 00:56:31.674739 [CBTSetCACLKResult] CA Dly = 34
733 00:56:31.674832 CS Dly: 6 (0~37)
734 00:56:31.674901 ==
735 00:56:31.678291 Dram Type= 6, Freq= 0, CH_0, rank 1
736 00:56:31.682037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 00:56:31.685882 ==
738 00:56:31.689301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 00:56:31.693383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 00:56:31.704165 [CA 0] Center 38 (7~69) winsize 63
741 00:56:31.707793 [CA 1] Center 38 (7~69) winsize 63
742 00:56:31.711688 [CA 2] Center 35 (5~66) winsize 62
743 00:56:31.715181 [CA 3] Center 35 (5~66) winsize 62
744 00:56:31.718890 [CA 4] Center 34 (4~65) winsize 62
745 00:56:31.722352 [CA 5] Center 34 (3~65) winsize 63
746 00:56:31.722452
747 00:56:31.726434 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 00:56:31.726529
749 00:56:31.729972 [CATrainingPosCal] consider 2 rank data
750 00:56:31.730062 u2DelayCellTimex100 = 270/100 ps
751 00:56:31.737116 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
752 00:56:31.741108 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 00:56:31.741212 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 00:56:31.744536 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 00:56:31.748431 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 00:56:31.751722 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 00:56:31.755724
758 00:56:31.759467 CA PerBit enable=1, Macro0, CA PI delay=34
759 00:56:31.759581
760 00:56:31.759655 [CBTSetCACLKResult] CA Dly = 34
761 00:56:31.763430 CS Dly: 6 (0~37)
762 00:56:31.763533
763 00:56:31.767101 ----->DramcWriteLeveling(PI) begin...
764 00:56:31.767198 ==
765 00:56:31.770621 Dram Type= 6, Freq= 0, CH_0, rank 0
766 00:56:31.774501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 00:56:31.774600 ==
768 00:56:31.777969 Write leveling (Byte 0): 31 => 31
769 00:56:31.778063 Write leveling (Byte 1): 30 => 30
770 00:56:31.781433 DramcWriteLeveling(PI) end<-----
771 00:56:31.781581
772 00:56:31.781650 ==
773 00:56:31.785385 Dram Type= 6, Freq= 0, CH_0, rank 0
774 00:56:31.789606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 00:56:31.789704 ==
776 00:56:31.793011 [Gating] SW mode calibration
777 00:56:31.800778 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 00:56:31.804420 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 00:56:31.811815 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 00:56:31.815334 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 00:56:31.819288 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 00:56:31.823045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
783 00:56:31.826543 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 00:56:31.830592 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 00:56:31.837942 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 00:56:31.841375 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 00:56:31.845011 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 00:56:31.849061 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 00:56:31.852292 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 00:56:31.859827 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 00:56:31.863127 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 00:56:31.866737 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 00:56:31.870430 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 00:56:31.877525 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 00:56:31.880678 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 00:56:31.884268 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 00:56:31.887427 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
798 00:56:31.894232 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 00:56:31.897358 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 00:56:31.900799 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 00:56:31.907463 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 00:56:31.910759 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 00:56:31.914065 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 00:56:31.920592 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 00:56:31.924071 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
806 00:56:31.927117 0 9 12 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
807 00:56:31.934019 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 00:56:31.937155 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 00:56:31.940734 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 00:56:31.947196 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 00:56:31.950582 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 00:56:31.953706 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 00:56:31.960574 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
814 00:56:31.963750 0 10 12 | B1->B0 | 2e2e 2525 | 0 0 | (0 1) (0 0)
815 00:56:31.967249 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 00:56:31.974063 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 00:56:31.977366 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 00:56:31.980422 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 00:56:31.987012 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 00:56:31.990590 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 00:56:31.993910 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
822 00:56:32.000375 0 11 12 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
823 00:56:32.003762 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 00:56:32.007158 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 00:56:32.010296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 00:56:32.017085 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 00:56:32.020463 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 00:56:32.023689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 00:56:32.030306 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 00:56:32.033730 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 00:56:32.037064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
832 00:56:32.043897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 00:56:32.047078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 00:56:32.050572 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 00:56:32.057388 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 00:56:32.060623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 00:56:32.063864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 00:56:32.070930 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 00:56:32.073995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 00:56:32.077427 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 00:56:32.084033 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 00:56:32.087224 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 00:56:32.090732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 00:56:32.093968 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 00:56:32.100320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 00:56:32.103750 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 00:56:32.107032 Total UI for P1: 0, mck2ui 16
848 00:56:32.110554 best dqsien dly found for B0: ( 0, 14, 8)
849 00:56:32.114029 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 00:56:32.117136 Total UI for P1: 0, mck2ui 16
851 00:56:32.120533 best dqsien dly found for B1: ( 0, 14, 12)
852 00:56:32.123838 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 00:56:32.127225 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 00:56:32.130351
855 00:56:32.133907 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 00:56:32.136955 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 00:56:32.140659 [Gating] SW calibration Done
858 00:56:32.140744 ==
859 00:56:32.143738 Dram Type= 6, Freq= 0, CH_0, rank 0
860 00:56:32.146970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 00:56:32.147056 ==
862 00:56:32.147125 RX Vref Scan: 0
863 00:56:32.147188
864 00:56:32.150275 RX Vref 0 -> 0, step: 1
865 00:56:32.150387
866 00:56:32.153957 RX Delay -130 -> 252, step: 16
867 00:56:32.157014 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 00:56:32.160473 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 00:56:32.167204 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 00:56:32.170523 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 00:56:32.173741 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 00:56:32.177186 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 00:56:32.180357 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 00:56:32.187174 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 00:56:32.190340 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
876 00:56:32.193932 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 00:56:32.197030 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 00:56:32.200388 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 00:56:32.207090 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 00:56:32.210464 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 00:56:32.213891 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
882 00:56:32.216989 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 00:56:32.217075 ==
884 00:56:32.220131 Dram Type= 6, Freq= 0, CH_0, rank 0
885 00:56:32.227113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 00:56:32.227207 ==
887 00:56:32.227278 DQS Delay:
888 00:56:32.227342 DQS0 = 0, DQS1 = 0
889 00:56:32.230160 DQM Delay:
890 00:56:32.230246 DQM0 = 82, DQM1 = 71
891 00:56:32.233386 DQ Delay:
892 00:56:32.236931 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 00:56:32.240323 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 00:56:32.240413 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
895 00:56:32.246775 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
896 00:56:32.246870
897 00:56:32.246938
898 00:56:32.247002 ==
899 00:56:32.251078 Dram Type= 6, Freq= 0, CH_0, rank 0
900 00:56:32.254298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 00:56:32.254386 ==
902 00:56:32.254455
903 00:56:32.254539
904 00:56:32.257721 TX Vref Scan disable
905 00:56:32.257807 == TX Byte 0 ==
906 00:56:32.260930 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
907 00:56:32.267702 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
908 00:56:32.267789 == TX Byte 1 ==
909 00:56:32.270972 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 00:56:32.277507 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 00:56:32.277609 ==
912 00:56:32.280919 Dram Type= 6, Freq= 0, CH_0, rank 0
913 00:56:32.284268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 00:56:32.284355 ==
915 00:56:32.297135 TX Vref=22, minBit 10, minWin=26, winSum=432
916 00:56:32.300439 TX Vref=24, minBit 1, minWin=27, winSum=436
917 00:56:32.303939 TX Vref=26, minBit 1, minWin=27, winSum=442
918 00:56:32.307412 TX Vref=28, minBit 0, minWin=27, winSum=440
919 00:56:32.310544 TX Vref=30, minBit 1, minWin=27, winSum=443
920 00:56:32.317078 TX Vref=32, minBit 10, minWin=26, winSum=437
921 00:56:32.320403 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
922 00:56:32.320489
923 00:56:32.323811 Final TX Range 1 Vref 30
924 00:56:32.323897
925 00:56:32.323965 ==
926 00:56:32.327053 Dram Type= 6, Freq= 0, CH_0, rank 0
927 00:56:32.330506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 00:56:32.330601 ==
929 00:56:32.333766
930 00:56:32.333852
931 00:56:32.333920 TX Vref Scan disable
932 00:56:32.337323 == TX Byte 0 ==
933 00:56:32.340610 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
934 00:56:32.347690 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
935 00:56:32.347776 == TX Byte 1 ==
936 00:56:32.350401 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 00:56:32.357388 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 00:56:32.357503
939 00:56:32.357590 [DATLAT]
940 00:56:32.357655 Freq=800, CH0 RK0
941 00:56:32.357718
942 00:56:32.360760 DATLAT Default: 0xa
943 00:56:32.360848 0, 0xFFFF, sum = 0
944 00:56:32.363748 1, 0xFFFF, sum = 0
945 00:56:32.363837 2, 0xFFFF, sum = 0
946 00:56:32.367118 3, 0xFFFF, sum = 0
947 00:56:32.370502 4, 0xFFFF, sum = 0
948 00:56:32.370589 5, 0xFFFF, sum = 0
949 00:56:32.373729 6, 0xFFFF, sum = 0
950 00:56:32.373815 7, 0xFFFF, sum = 0
951 00:56:32.377214 8, 0xFFFF, sum = 0
952 00:56:32.377299 9, 0x0, sum = 1
953 00:56:32.377368 10, 0x0, sum = 2
954 00:56:32.380378 11, 0x0, sum = 3
955 00:56:32.380463 12, 0x0, sum = 4
956 00:56:32.383697 best_step = 10
957 00:56:32.383781
958 00:56:32.383848 ==
959 00:56:32.387147 Dram Type= 6, Freq= 0, CH_0, rank 0
960 00:56:32.390591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 00:56:32.390676 ==
962 00:56:32.394048 RX Vref Scan: 1
963 00:56:32.394133
964 00:56:32.394201 Set Vref Range= 32 -> 127
965 00:56:32.394264
966 00:56:32.397407 RX Vref 32 -> 127, step: 1
967 00:56:32.397504
968 00:56:32.400585 RX Delay -111 -> 252, step: 8
969 00:56:32.400670
970 00:56:32.403716 Set Vref, RX VrefLevel [Byte0]: 32
971 00:56:32.407112 [Byte1]: 32
972 00:56:32.407197
973 00:56:32.410292 Set Vref, RX VrefLevel [Byte0]: 33
974 00:56:32.413760 [Byte1]: 33
975 00:56:32.417777
976 00:56:32.417864 Set Vref, RX VrefLevel [Byte0]: 34
977 00:56:32.421011 [Byte1]: 34
978 00:56:32.425575
979 00:56:32.425660 Set Vref, RX VrefLevel [Byte0]: 35
980 00:56:32.428725 [Byte1]: 35
981 00:56:32.433021
982 00:56:32.433105 Set Vref, RX VrefLevel [Byte0]: 36
983 00:56:32.436527 [Byte1]: 36
984 00:56:32.440730
985 00:56:32.440814 Set Vref, RX VrefLevel [Byte0]: 37
986 00:56:32.443855 [Byte1]: 37
987 00:56:32.448408
988 00:56:32.448492 Set Vref, RX VrefLevel [Byte0]: 38
989 00:56:32.451504 [Byte1]: 38
990 00:56:32.456110
991 00:56:32.456193 Set Vref, RX VrefLevel [Byte0]: 39
992 00:56:32.459314 [Byte1]: 39
993 00:56:32.464002
994 00:56:32.464084 Set Vref, RX VrefLevel [Byte0]: 40
995 00:56:32.467071 [Byte1]: 40
996 00:56:32.471421
997 00:56:32.471505 Set Vref, RX VrefLevel [Byte0]: 41
998 00:56:32.474603 [Byte1]: 41
999 00:56:32.479137
1000 00:56:32.479233 Set Vref, RX VrefLevel [Byte0]: 42
1001 00:56:32.482448 [Byte1]: 42
1002 00:56:32.486565
1003 00:56:32.489841 Set Vref, RX VrefLevel [Byte0]: 43
1004 00:56:32.489926 [Byte1]: 43
1005 00:56:32.494142
1006 00:56:32.494245 Set Vref, RX VrefLevel [Byte0]: 44
1007 00:56:32.497661 [Byte1]: 44
1008 00:56:32.501918
1009 00:56:32.502002 Set Vref, RX VrefLevel [Byte0]: 45
1010 00:56:32.505422 [Byte1]: 45
1011 00:56:32.509947
1012 00:56:32.510030 Set Vref, RX VrefLevel [Byte0]: 46
1013 00:56:32.513350 [Byte1]: 46
1014 00:56:32.517655
1015 00:56:32.517737 Set Vref, RX VrefLevel [Byte0]: 47
1016 00:56:32.520805 [Byte1]: 47
1017 00:56:32.525279
1018 00:56:32.525363 Set Vref, RX VrefLevel [Byte0]: 48
1019 00:56:32.528821 [Byte1]: 48
1020 00:56:32.532951
1021 00:56:32.533034 Set Vref, RX VrefLevel [Byte0]: 49
1022 00:56:32.536489 [Byte1]: 49
1023 00:56:32.540652
1024 00:56:32.540735 Set Vref, RX VrefLevel [Byte0]: 50
1025 00:56:32.543682 [Byte1]: 50
1026 00:56:32.547686
1027 00:56:32.547797 Set Vref, RX VrefLevel [Byte0]: 51
1028 00:56:32.551086 [Byte1]: 51
1029 00:56:32.555355
1030 00:56:32.555441 Set Vref, RX VrefLevel [Byte0]: 52
1031 00:56:32.558900 [Byte1]: 52
1032 00:56:32.562963
1033 00:56:32.563046 Set Vref, RX VrefLevel [Byte0]: 53
1034 00:56:32.566601 [Byte1]: 53
1035 00:56:32.570744
1036 00:56:32.570827 Set Vref, RX VrefLevel [Byte0]: 54
1037 00:56:32.574140 [Byte1]: 54
1038 00:56:32.578414
1039 00:56:32.578498 Set Vref, RX VrefLevel [Byte0]: 55
1040 00:56:32.581762 [Byte1]: 55
1041 00:56:32.586031
1042 00:56:32.586113 Set Vref, RX VrefLevel [Byte0]: 56
1043 00:56:32.589445 [Byte1]: 56
1044 00:56:32.593853
1045 00:56:32.593942 Set Vref, RX VrefLevel [Byte0]: 57
1046 00:56:32.596896 [Byte1]: 57
1047 00:56:32.601221
1048 00:56:32.601305 Set Vref, RX VrefLevel [Byte0]: 58
1049 00:56:32.604512 [Byte1]: 58
1050 00:56:32.608821
1051 00:56:32.608904 Set Vref, RX VrefLevel [Byte0]: 59
1052 00:56:32.612192 [Byte1]: 59
1053 00:56:32.616498
1054 00:56:32.616645 Set Vref, RX VrefLevel [Byte0]: 60
1055 00:56:32.619968 [Byte1]: 60
1056 00:56:32.624056
1057 00:56:32.624166 Set Vref, RX VrefLevel [Byte0]: 61
1058 00:56:32.627401 [Byte1]: 61
1059 00:56:32.631836
1060 00:56:32.631946 Set Vref, RX VrefLevel [Byte0]: 62
1061 00:56:32.635131 [Byte1]: 62
1062 00:56:32.639380
1063 00:56:32.639463 Set Vref, RX VrefLevel [Byte0]: 63
1064 00:56:32.642671 [Byte1]: 63
1065 00:56:32.647011
1066 00:56:32.647095 Set Vref, RX VrefLevel [Byte0]: 64
1067 00:56:32.650550 [Byte1]: 64
1068 00:56:32.654740
1069 00:56:32.654824 Set Vref, RX VrefLevel [Byte0]: 65
1070 00:56:32.658114 [Byte1]: 65
1071 00:56:32.662368
1072 00:56:32.662451 Set Vref, RX VrefLevel [Byte0]: 66
1073 00:56:32.665634 [Byte1]: 66
1074 00:56:32.670125
1075 00:56:32.670208 Set Vref, RX VrefLevel [Byte0]: 67
1076 00:56:32.673302 [Byte1]: 67
1077 00:56:32.677610
1078 00:56:32.677693 Set Vref, RX VrefLevel [Byte0]: 68
1079 00:56:32.681147 [Byte1]: 68
1080 00:56:32.685379
1081 00:56:32.685463 Set Vref, RX VrefLevel [Byte0]: 69
1082 00:56:32.688616 [Byte1]: 69
1083 00:56:32.693183
1084 00:56:32.693267 Set Vref, RX VrefLevel [Byte0]: 70
1085 00:56:32.696428 [Byte1]: 70
1086 00:56:32.700567
1087 00:56:32.700649 Set Vref, RX VrefLevel [Byte0]: 71
1088 00:56:32.704221 [Byte1]: 71
1089 00:56:32.708489
1090 00:56:32.708572 Set Vref, RX VrefLevel [Byte0]: 72
1091 00:56:32.711710 [Byte1]: 72
1092 00:56:32.715876
1093 00:56:32.715959 Set Vref, RX VrefLevel [Byte0]: 73
1094 00:56:32.719199 [Byte1]: 73
1095 00:56:32.723529
1096 00:56:32.723617 Set Vref, RX VrefLevel [Byte0]: 74
1097 00:56:32.726906 [Byte1]: 74
1098 00:56:32.731086
1099 00:56:32.731170 Set Vref, RX VrefLevel [Byte0]: 75
1100 00:56:32.734372 [Byte1]: 75
1101 00:56:32.738870
1102 00:56:32.738954 Set Vref, RX VrefLevel [Byte0]: 76
1103 00:56:32.742282 [Byte1]: 76
1104 00:56:32.746377
1105 00:56:32.746462 Set Vref, RX VrefLevel [Byte0]: 77
1106 00:56:32.749970 [Byte1]: 77
1107 00:56:32.754136
1108 00:56:32.754225 Set Vref, RX VrefLevel [Byte0]: 78
1109 00:56:32.757404 [Byte1]: 78
1110 00:56:32.761812
1111 00:56:32.761899 Set Vref, RX VrefLevel [Byte0]: 79
1112 00:56:32.765014 [Byte1]: 79
1113 00:56:32.769407
1114 00:56:32.769535 Final RX Vref Byte 0 = 62 to rank0
1115 00:56:32.772702 Final RX Vref Byte 1 = 58 to rank0
1116 00:56:32.776187 Final RX Vref Byte 0 = 62 to rank1
1117 00:56:32.779419 Final RX Vref Byte 1 = 58 to rank1==
1118 00:56:32.782810 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 00:56:32.789487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 00:56:32.789574 ==
1121 00:56:32.789641 DQS Delay:
1122 00:56:32.789703 DQS0 = 0, DQS1 = 0
1123 00:56:32.792710 DQM Delay:
1124 00:56:32.792793 DQM0 = 82, DQM1 = 68
1125 00:56:32.796187 DQ Delay:
1126 00:56:32.799560 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1127 00:56:32.799644 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1128 00:56:32.802672 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1129 00:56:32.809426 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =76
1130 00:56:32.809553
1131 00:56:32.809620
1132 00:56:32.816167 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1133 00:56:32.819686 CH0 RK0: MR19=606, MR18=2424
1134 00:56:32.826103 CH0_RK0: MR19=0x606, MR18=0x2424, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 00:56:32.826195
1136 00:56:32.829717 ----->DramcWriteLeveling(PI) begin...
1137 00:56:32.829802 ==
1138 00:56:32.832924 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 00:56:32.836196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 00:56:32.836282 ==
1141 00:56:32.839693 Write leveling (Byte 0): 32 => 32
1142 00:56:32.843059 Write leveling (Byte 1): 32 => 32
1143 00:56:32.846241 DramcWriteLeveling(PI) end<-----
1144 00:56:32.846325
1145 00:56:32.846392 ==
1146 00:56:32.849438 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 00:56:32.852784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 00:56:32.852870 ==
1149 00:56:32.855938 [Gating] SW mode calibration
1150 00:56:32.862685 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 00:56:32.869593 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 00:56:32.872779 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 00:56:32.876174 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 00:56:32.882956 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 00:56:32.885992 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 00:56:32.889283 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 00:56:32.895999 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 00:56:32.899598 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 00:56:32.902873 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 00:56:32.909437 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 00:56:32.913007 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 00:56:32.916149 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 00:56:32.919347 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 00:56:32.926361 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 00:56:32.970149 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 00:56:32.970307 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 00:56:32.970387 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 00:56:32.970655 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 00:56:32.970750 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 00:56:32.970841 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1171 00:56:32.970931 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 00:56:32.971018 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 00:56:32.971104 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 00:56:32.971190 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 00:56:33.014483 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 00:56:33.014640 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 00:56:33.014718 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 00:56:33.014975 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1179 00:56:33.015061 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 00:56:33.015142 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 00:56:33.015629 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 00:56:33.015746 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 00:56:33.016040 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 00:56:33.016138 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 00:56:33.019046 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1186 00:56:33.022317 0 10 8 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (1 0)
1187 00:56:33.025750 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1188 00:56:33.032332 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 00:56:33.035682 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 00:56:33.038836 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 00:56:33.045766 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 00:56:33.048961 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 00:56:33.052315 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1194 00:56:33.059119 0 11 8 | B1->B0 | 3434 3939 | 0 0 | (0 0) (0 0)
1195 00:56:33.062281 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
1196 00:56:33.065690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 00:56:33.068911 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 00:56:33.075744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 00:56:33.079203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 00:56:33.082462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 00:56:33.089806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 00:56:33.093228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 00:56:33.096899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 00:56:33.100789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 00:56:33.104124 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 00:56:33.111135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 00:56:33.114499 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 00:56:33.117641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 00:56:33.124419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 00:56:33.127676 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 00:56:33.131132 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 00:56:33.137975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 00:56:33.141132 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 00:56:33.144253 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 00:56:33.151179 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 00:56:33.154584 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 00:56:33.157618 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 00:56:33.164338 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1219 00:56:33.164427 Total UI for P1: 0, mck2ui 16
1220 00:56:33.167929 best dqsien dly found for B0: ( 0, 14, 4)
1221 00:56:33.174318 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 00:56:33.177513 Total UI for P1: 0, mck2ui 16
1223 00:56:33.181037 best dqsien dly found for B1: ( 0, 14, 8)
1224 00:56:33.184475 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1225 00:56:33.187596 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1226 00:56:33.187681
1227 00:56:33.191110 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1228 00:56:33.194515 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1229 00:56:33.197836 [Gating] SW calibration Done
1230 00:56:33.197937 ==
1231 00:56:33.200894 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 00:56:33.204537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 00:56:33.204623 ==
1234 00:56:33.207617 RX Vref Scan: 0
1235 00:56:33.207701
1236 00:56:33.207769 RX Vref 0 -> 0, step: 1
1237 00:56:33.207831
1238 00:56:33.210995 RX Delay -130 -> 252, step: 16
1239 00:56:33.217662 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1240 00:56:33.221200 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 00:56:33.224219 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1242 00:56:33.227635 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1243 00:56:33.230951 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1244 00:56:33.234503 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1245 00:56:33.241022 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1246 00:56:33.244375 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1247 00:56:33.247593 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1248 00:56:33.250884 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1249 00:56:33.254452 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 00:56:33.261077 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1251 00:56:33.264203 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1252 00:56:33.267669 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1253 00:56:33.271086 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1254 00:56:33.277753 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1255 00:56:33.277857 ==
1256 00:56:33.281006 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 00:56:33.284323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 00:56:33.284422 ==
1259 00:56:33.284489 DQS Delay:
1260 00:56:33.287486 DQS0 = 0, DQS1 = 0
1261 00:56:33.287571 DQM Delay:
1262 00:56:33.291034 DQM0 = 78, DQM1 = 69
1263 00:56:33.291130 DQ Delay:
1264 00:56:33.294156 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1265 00:56:33.297653 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1266 00:56:33.300840 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1267 00:56:33.304410 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1268 00:56:33.304495
1269 00:56:33.304562
1270 00:56:33.304623 ==
1271 00:56:33.307658 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 00:56:33.310927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 00:56:33.311011 ==
1274 00:56:33.311078
1275 00:56:33.311139
1276 00:56:33.314401 TX Vref Scan disable
1277 00:56:33.317756 == TX Byte 0 ==
1278 00:56:33.320825 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 00:56:33.324412 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 00:56:33.327548 == TX Byte 1 ==
1281 00:56:33.331039 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1282 00:56:33.334361 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1283 00:56:33.334446 ==
1284 00:56:33.337430 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 00:56:33.340905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 00:56:33.344352 ==
1287 00:56:33.355348 TX Vref=22, minBit 9, minWin=26, winSum=433
1288 00:56:33.358740 TX Vref=24, minBit 9, minWin=26, winSum=439
1289 00:56:33.362019 TX Vref=26, minBit 1, minWin=27, winSum=444
1290 00:56:33.365242 TX Vref=28, minBit 3, minWin=27, winSum=444
1291 00:56:33.368549 TX Vref=30, minBit 7, minWin=27, winSum=443
1292 00:56:33.372057 TX Vref=32, minBit 1, minWin=27, winSum=443
1293 00:56:33.379023 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 26
1294 00:56:33.379116
1295 00:56:33.382004 Final TX Range 1 Vref 26
1296 00:56:33.382090
1297 00:56:33.382156 ==
1298 00:56:33.385377 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 00:56:33.388570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 00:56:33.388655 ==
1301 00:56:33.388722
1302 00:56:33.392113
1303 00:56:33.392195 TX Vref Scan disable
1304 00:56:33.395317 == TX Byte 0 ==
1305 00:56:33.398796 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 00:56:33.401885 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 00:56:33.405188 == TX Byte 1 ==
1308 00:56:33.408659 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1309 00:56:33.415304 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1310 00:56:33.415388
1311 00:56:33.415453 [DATLAT]
1312 00:56:33.415515 Freq=800, CH0 RK1
1313 00:56:33.415574
1314 00:56:33.418730 DATLAT Default: 0xa
1315 00:56:33.418814 0, 0xFFFF, sum = 0
1316 00:56:33.421868 1, 0xFFFF, sum = 0
1317 00:56:33.421953 2, 0xFFFF, sum = 0
1318 00:56:33.425246 3, 0xFFFF, sum = 0
1319 00:56:33.425331 4, 0xFFFF, sum = 0
1320 00:56:33.428776 5, 0xFFFF, sum = 0
1321 00:56:33.431959 6, 0xFFFF, sum = 0
1322 00:56:33.432043 7, 0xFFFF, sum = 0
1323 00:56:33.435126 8, 0xFFFF, sum = 0
1324 00:56:33.435211 9, 0x0, sum = 1
1325 00:56:33.435278 10, 0x0, sum = 2
1326 00:56:33.438637 11, 0x0, sum = 3
1327 00:56:33.438721 12, 0x0, sum = 4
1328 00:56:33.441973 best_step = 10
1329 00:56:33.442056
1330 00:56:33.442121 ==
1331 00:56:33.445182 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 00:56:33.448539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 00:56:33.448623 ==
1334 00:56:33.451916 RX Vref Scan: 0
1335 00:56:33.451999
1336 00:56:33.452064 RX Vref 0 -> 0, step: 1
1337 00:56:33.452128
1338 00:56:33.455065 RX Delay -111 -> 252, step: 8
1339 00:56:33.462243 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1340 00:56:33.465388 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1341 00:56:33.468759 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1342 00:56:33.472026 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
1343 00:56:33.475266 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1344 00:56:33.482027 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1345 00:56:33.485300 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1346 00:56:33.488584 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1347 00:56:33.491784 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1348 00:56:33.495193 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1349 00:56:33.501863 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1350 00:56:33.505321 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1351 00:56:33.508884 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1352 00:56:33.512036 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1353 00:56:33.515189 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1354 00:56:33.521893 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1355 00:56:33.521975 ==
1356 00:56:33.525298 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 00:56:33.528627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 00:56:33.528716 ==
1359 00:56:33.528780 DQS Delay:
1360 00:56:33.531883 DQS0 = 0, DQS1 = 0
1361 00:56:33.531966 DQM Delay:
1362 00:56:33.535132 DQM0 = 79, DQM1 = 70
1363 00:56:33.535214 DQ Delay:
1364 00:56:33.538697 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =76
1365 00:56:33.541837 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1366 00:56:33.545120 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1367 00:56:33.548589 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1368 00:56:33.548672
1369 00:56:33.548738
1370 00:56:33.558397 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1371 00:56:33.558488 CH0 RK1: MR19=606, MR18=4B26
1372 00:56:33.565058 CH0_RK1: MR19=0x606, MR18=0x4B26, DQSOSC=391, MR23=63, INC=96, DEC=64
1373 00:56:33.568579 [RxdqsGatingPostProcess] freq 800
1374 00:56:33.575160 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 00:56:33.578540 Pre-setting of DQS Precalculation
1376 00:56:33.581827 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 00:56:33.581911 ==
1378 00:56:33.585448 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 00:56:33.588542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 00:56:33.588626 ==
1381 00:56:33.595482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 00:56:33.602003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 00:56:33.610338 [CA 0] Center 37 (7~67) winsize 61
1384 00:56:33.613789 [CA 1] Center 37 (7~67) winsize 61
1385 00:56:33.617051 [CA 2] Center 34 (5~64) winsize 60
1386 00:56:33.620348 [CA 3] Center 34 (4~64) winsize 61
1387 00:56:33.623898 [CA 4] Center 34 (4~64) winsize 61
1388 00:56:33.627042 [CA 5] Center 34 (4~64) winsize 61
1389 00:56:33.627126
1390 00:56:33.630448 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1391 00:56:33.630533
1392 00:56:33.633829 [CATrainingPosCal] consider 1 rank data
1393 00:56:33.637053 u2DelayCellTimex100 = 270/100 ps
1394 00:56:33.640546 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1395 00:56:33.643812 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1396 00:56:33.650475 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1397 00:56:33.653644 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1398 00:56:33.656916 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 00:56:33.660192 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 00:56:33.660278
1401 00:56:33.663678 CA PerBit enable=1, Macro0, CA PI delay=34
1402 00:56:33.663761
1403 00:56:33.666898 [CBTSetCACLKResult] CA Dly = 34
1404 00:56:33.666981 CS Dly: 5 (0~36)
1405 00:56:33.667048 ==
1406 00:56:33.670385 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 00:56:33.676902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 00:56:33.676986 ==
1409 00:56:33.680347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 00:56:33.686889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 00:56:33.696549 [CA 0] Center 37 (7~67) winsize 61
1412 00:56:33.699671 [CA 1] Center 36 (6~67) winsize 62
1413 00:56:33.703261 [CA 2] Center 35 (5~65) winsize 61
1414 00:56:33.706448 [CA 3] Center 34 (4~64) winsize 61
1415 00:56:33.710002 [CA 4] Center 34 (4~65) winsize 62
1416 00:56:33.713171 [CA 5] Center 33 (3~64) winsize 62
1417 00:56:33.713255
1418 00:56:33.716548 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 00:56:33.716632
1420 00:56:33.719952 [CATrainingPosCal] consider 2 rank data
1421 00:56:33.723077 u2DelayCellTimex100 = 270/100 ps
1422 00:56:33.726443 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1423 00:56:33.729880 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1424 00:56:33.736508 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1425 00:56:33.739785 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 00:56:33.743068 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 00:56:33.746558 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 00:56:33.746643
1429 00:56:33.750045 CA PerBit enable=1, Macro0, CA PI delay=34
1430 00:56:33.750132
1431 00:56:33.754118 [CBTSetCACLKResult] CA Dly = 34
1432 00:56:33.754207 CS Dly: 6 (0~38)
1433 00:56:33.754275
1434 00:56:33.758008 ----->DramcWriteLeveling(PI) begin...
1435 00:56:33.758095 ==
1436 00:56:33.761706 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 00:56:33.765423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 00:56:33.765546 ==
1439 00:56:33.768961 Write leveling (Byte 0): 30 => 30
1440 00:56:33.772752 Write leveling (Byte 1): 30 => 30
1441 00:56:33.776654 DramcWriteLeveling(PI) end<-----
1442 00:56:33.776739
1443 00:56:33.776806 ==
1444 00:56:33.780379 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 00:56:33.783723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 00:56:33.783808 ==
1447 00:56:33.786938 [Gating] SW mode calibration
1448 00:56:33.793877 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 00:56:33.797018 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 00:56:33.803384 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 00:56:33.806749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 00:56:33.810404 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 00:56:33.816637 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 00:56:33.820043 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 00:56:33.823353 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 00:56:33.830164 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 00:56:33.833357 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 00:56:33.836617 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 00:56:33.843490 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 00:56:33.846677 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 00:56:33.850056 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 00:56:33.853539 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 00:56:33.860055 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 00:56:33.863296 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 00:56:33.866580 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 00:56:33.873509 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 00:56:33.876633 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 00:56:33.880144 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1469 00:56:33.886734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 00:56:33.889921 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 00:56:33.893433 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 00:56:33.900131 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 00:56:33.903591 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 00:56:33.907001 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 00:56:33.913626 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 00:56:33.916747 0 9 8 | B1->B0 | 2929 2b2b | 1 0 | (0 0) (0 0)
1477 00:56:33.920154 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 00:56:33.926873 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 00:56:33.929986 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 00:56:33.933192 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 00:56:33.940033 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 00:56:33.943338 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 00:56:33.946815 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
1484 00:56:33.950346 0 10 8 | B1->B0 | 2f2f 2d2d | 1 1 | (1 0) (1 0)
1485 00:56:33.956777 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 00:56:33.960223 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 00:56:33.963572 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 00:56:33.969960 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 00:56:33.973481 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 00:56:33.976734 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 00:56:33.983364 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 00:56:33.986496 0 11 8 | B1->B0 | 3636 3636 | 0 1 | (0 0) (0 0)
1493 00:56:33.990088 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 00:56:33.996667 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 00:56:33.999949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 00:56:34.003329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 00:56:34.009879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 00:56:34.013174 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 00:56:34.016556 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 00:56:34.023347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 00:56:34.026730 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 00:56:34.029915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 00:56:34.036603 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 00:56:34.039874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 00:56:34.043180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 00:56:34.049865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 00:56:34.053375 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 00:56:34.056105 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 00:56:34.062888 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 00:56:34.066219 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 00:56:34.069484 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 00:56:34.076190 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 00:56:34.079759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 00:56:34.082808 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 00:56:34.086355 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 00:56:34.092996 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 00:56:34.096086 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 00:56:34.099607 Total UI for P1: 0, mck2ui 16
1519 00:56:34.102710 best dqsien dly found for B0: ( 0, 14, 8)
1520 00:56:34.106064 Total UI for P1: 0, mck2ui 16
1521 00:56:34.109468 best dqsien dly found for B1: ( 0, 14, 8)
1522 00:56:34.112858 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1523 00:56:34.116340 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 00:56:34.116451
1525 00:56:34.119506 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 00:56:34.122687 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 00:56:34.126047 [Gating] SW calibration Done
1528 00:56:34.126165 ==
1529 00:56:34.129736 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 00:56:34.132883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 00:56:34.136328 ==
1532 00:56:34.136415 RX Vref Scan: 0
1533 00:56:34.136481
1534 00:56:34.139607 RX Vref 0 -> 0, step: 1
1535 00:56:34.139692
1536 00:56:34.142823 RX Delay -130 -> 252, step: 16
1537 00:56:34.146320 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1538 00:56:34.149629 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1539 00:56:34.153091 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1540 00:56:34.156413 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1541 00:56:34.163164 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1542 00:56:34.166219 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1543 00:56:34.169179 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1544 00:56:34.172571 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1545 00:56:34.176036 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1546 00:56:34.182683 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1547 00:56:34.186097 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1548 00:56:34.189337 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1549 00:56:34.192583 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1550 00:56:34.195901 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1551 00:56:34.202610 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1552 00:56:34.205696 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1553 00:56:34.205782 ==
1554 00:56:34.209120 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 00:56:34.212353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 00:56:34.212437 ==
1557 00:56:34.215855 DQS Delay:
1558 00:56:34.215938 DQS0 = 0, DQS1 = 0
1559 00:56:34.216005 DQM Delay:
1560 00:56:34.219076 DQM0 = 81, DQM1 = 70
1561 00:56:34.219191 DQ Delay:
1562 00:56:34.222469 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1563 00:56:34.225713 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1564 00:56:34.229168 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1565 00:56:34.232412 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1566 00:56:34.232496
1567 00:56:34.232563
1568 00:56:34.232625 ==
1569 00:56:34.235962 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 00:56:34.242385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 00:56:34.242481 ==
1572 00:56:34.242548
1573 00:56:34.242609
1574 00:56:34.242669 TX Vref Scan disable
1575 00:56:34.246119 == TX Byte 0 ==
1576 00:56:34.249301 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1577 00:56:34.252843 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1578 00:56:34.256188 == TX Byte 1 ==
1579 00:56:34.259623 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 00:56:34.266031 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 00:56:34.266121 ==
1582 00:56:34.269678 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 00:56:34.272796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 00:56:34.272881 ==
1585 00:56:34.285174 TX Vref=22, minBit 0, minWin=27, winSum=438
1586 00:56:34.288453 TX Vref=24, minBit 1, minWin=26, winSum=439
1587 00:56:34.291738 TX Vref=26, minBit 1, minWin=27, winSum=442
1588 00:56:34.295272 TX Vref=28, minBit 7, minWin=27, winSum=445
1589 00:56:34.298388 TX Vref=30, minBit 9, minWin=27, winSum=450
1590 00:56:34.302025 TX Vref=32, minBit 0, minWin=27, winSum=445
1591 00:56:34.308463 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 30
1592 00:56:34.308554
1593 00:56:34.311951 Final TX Range 1 Vref 30
1594 00:56:34.312035
1595 00:56:34.312101 ==
1596 00:56:34.315339 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 00:56:34.318425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 00:56:34.318536 ==
1599 00:56:34.318631
1600 00:56:34.318721
1601 00:56:34.322055 TX Vref Scan disable
1602 00:56:34.325813 == TX Byte 0 ==
1603 00:56:34.329252 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1604 00:56:34.332594 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1605 00:56:34.336082 == TX Byte 1 ==
1606 00:56:34.339163 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 00:56:34.342616 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 00:56:34.342788
1609 00:56:34.345902 [DATLAT]
1610 00:56:34.345986 Freq=800, CH1 RK0
1611 00:56:34.346052
1612 00:56:34.349133 DATLAT Default: 0xa
1613 00:56:34.349244 0, 0xFFFF, sum = 0
1614 00:56:34.352510 1, 0xFFFF, sum = 0
1615 00:56:34.352615 2, 0xFFFF, sum = 0
1616 00:56:34.356016 3, 0xFFFF, sum = 0
1617 00:56:34.356129 4, 0xFFFF, sum = 0
1618 00:56:34.359186 5, 0xFFFF, sum = 0
1619 00:56:34.359267 6, 0xFFFF, sum = 0
1620 00:56:34.362534 7, 0xFFFF, sum = 0
1621 00:56:34.362611 8, 0xFFFF, sum = 0
1622 00:56:34.365993 9, 0x0, sum = 1
1623 00:56:34.366079 10, 0x0, sum = 2
1624 00:56:34.369104 11, 0x0, sum = 3
1625 00:56:34.369188 12, 0x0, sum = 4
1626 00:56:34.372466 best_step = 10
1627 00:56:34.372576
1628 00:56:34.372671 ==
1629 00:56:34.375751 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 00:56:34.379072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 00:56:34.379157 ==
1632 00:56:34.379223 RX Vref Scan: 1
1633 00:56:34.379285
1634 00:56:34.382598 Set Vref Range= 32 -> 127
1635 00:56:34.382682
1636 00:56:34.385758 RX Vref 32 -> 127, step: 1
1637 00:56:34.385887
1638 00:56:34.389022 RX Delay -111 -> 252, step: 8
1639 00:56:34.389132
1640 00:56:34.392808 Set Vref, RX VrefLevel [Byte0]: 32
1641 00:56:34.395790 [Byte1]: 32
1642 00:56:34.395876
1643 00:56:34.399337 Set Vref, RX VrefLevel [Byte0]: 33
1644 00:56:34.402438 [Byte1]: 33
1645 00:56:34.402526
1646 00:56:34.405753 Set Vref, RX VrefLevel [Byte0]: 34
1647 00:56:34.409031 [Byte1]: 34
1648 00:56:34.412966
1649 00:56:34.413051 Set Vref, RX VrefLevel [Byte0]: 35
1650 00:56:34.416662 [Byte1]: 35
1651 00:56:34.420807
1652 00:56:34.420892 Set Vref, RX VrefLevel [Byte0]: 36
1653 00:56:34.423905 [Byte1]: 36
1654 00:56:34.428484
1655 00:56:34.428570 Set Vref, RX VrefLevel [Byte0]: 37
1656 00:56:34.431851 [Byte1]: 37
1657 00:56:34.435950
1658 00:56:34.436034 Set Vref, RX VrefLevel [Byte0]: 38
1659 00:56:34.439188 [Byte1]: 38
1660 00:56:34.443748
1661 00:56:34.443831 Set Vref, RX VrefLevel [Byte0]: 39
1662 00:56:34.446935 [Byte1]: 39
1663 00:56:34.451233
1664 00:56:34.451317 Set Vref, RX VrefLevel [Byte0]: 40
1665 00:56:34.454704 [Byte1]: 40
1666 00:56:34.458969
1667 00:56:34.459064 Set Vref, RX VrefLevel [Byte0]: 41
1668 00:56:34.462136 [Byte1]: 41
1669 00:56:34.466505
1670 00:56:34.466615 Set Vref, RX VrefLevel [Byte0]: 42
1671 00:56:34.469921 [Byte1]: 42
1672 00:56:34.474332
1673 00:56:34.474416 Set Vref, RX VrefLevel [Byte0]: 43
1674 00:56:34.477433 [Byte1]: 43
1675 00:56:34.482062
1676 00:56:34.482145 Set Vref, RX VrefLevel [Byte0]: 44
1677 00:56:34.485277 [Byte1]: 44
1678 00:56:34.489357
1679 00:56:34.489442 Set Vref, RX VrefLevel [Byte0]: 45
1680 00:56:34.492850 [Byte1]: 45
1681 00:56:34.497094
1682 00:56:34.497181 Set Vref, RX VrefLevel [Byte0]: 46
1683 00:56:34.500373 [Byte1]: 46
1684 00:56:34.504828
1685 00:56:34.504913 Set Vref, RX VrefLevel [Byte0]: 47
1686 00:56:34.508321 [Byte1]: 47
1687 00:56:34.512322
1688 00:56:34.512407 Set Vref, RX VrefLevel [Byte0]: 48
1689 00:56:34.515809 [Byte1]: 48
1690 00:56:34.520117
1691 00:56:34.520201 Set Vref, RX VrefLevel [Byte0]: 49
1692 00:56:34.523380 [Byte1]: 49
1693 00:56:34.527782
1694 00:56:34.527875 Set Vref, RX VrefLevel [Byte0]: 50
1695 00:56:34.531069 [Byte1]: 50
1696 00:56:34.535611
1697 00:56:34.535705 Set Vref, RX VrefLevel [Byte0]: 51
1698 00:56:34.538790 [Byte1]: 51
1699 00:56:34.543037
1700 00:56:34.543120 Set Vref, RX VrefLevel [Byte0]: 52
1701 00:56:34.546180 [Byte1]: 52
1702 00:56:34.550757
1703 00:56:34.550847 Set Vref, RX VrefLevel [Byte0]: 53
1704 00:56:34.554174 [Byte1]: 53
1705 00:56:34.558343
1706 00:56:34.558427 Set Vref, RX VrefLevel [Byte0]: 54
1707 00:56:34.561761 [Byte1]: 54
1708 00:56:34.565859
1709 00:56:34.565947 Set Vref, RX VrefLevel [Byte0]: 55
1710 00:56:34.569173 [Byte1]: 55
1711 00:56:34.573590
1712 00:56:34.573676 Set Vref, RX VrefLevel [Byte0]: 56
1713 00:56:34.577232 [Byte1]: 56
1714 00:56:34.581221
1715 00:56:34.581308 Set Vref, RX VrefLevel [Byte0]: 57
1716 00:56:34.584558 [Byte1]: 57
1717 00:56:34.589092
1718 00:56:34.589203 Set Vref, RX VrefLevel [Byte0]: 58
1719 00:56:34.592219 [Byte1]: 58
1720 00:56:34.596573
1721 00:56:34.596659 Set Vref, RX VrefLevel [Byte0]: 59
1722 00:56:34.600091 [Byte1]: 59
1723 00:56:34.604065
1724 00:56:34.604153 Set Vref, RX VrefLevel [Byte0]: 60
1725 00:56:34.607505 [Byte1]: 60
1726 00:56:34.611952
1727 00:56:34.612052 Set Vref, RX VrefLevel [Byte0]: 61
1728 00:56:34.615299 [Byte1]: 61
1729 00:56:34.619357
1730 00:56:34.619471 Set Vref, RX VrefLevel [Byte0]: 62
1731 00:56:34.622829 [Byte1]: 62
1732 00:56:34.627258
1733 00:56:34.627344 Set Vref, RX VrefLevel [Byte0]: 63
1734 00:56:34.630648 [Byte1]: 63
1735 00:56:34.634731
1736 00:56:34.634816 Set Vref, RX VrefLevel [Byte0]: 64
1737 00:56:34.638201 [Byte1]: 64
1738 00:56:34.642523
1739 00:56:34.642608 Set Vref, RX VrefLevel [Byte0]: 65
1740 00:56:34.645745 [Byte1]: 65
1741 00:56:34.649980
1742 00:56:34.650065 Set Vref, RX VrefLevel [Byte0]: 66
1743 00:56:34.653310 [Byte1]: 66
1744 00:56:34.657650
1745 00:56:34.657750 Set Vref, RX VrefLevel [Byte0]: 67
1746 00:56:34.661035 [Byte1]: 67
1747 00:56:34.665371
1748 00:56:34.665483 Set Vref, RX VrefLevel [Byte0]: 68
1749 00:56:34.668548 [Byte1]: 68
1750 00:56:34.672857
1751 00:56:34.672945 Set Vref, RX VrefLevel [Byte0]: 69
1752 00:56:34.676339 [Byte1]: 69
1753 00:56:34.680570
1754 00:56:34.680656 Set Vref, RX VrefLevel [Byte0]: 70
1755 00:56:34.683891 [Byte1]: 70
1756 00:56:34.688396
1757 00:56:34.688482 Set Vref, RX VrefLevel [Byte0]: 71
1758 00:56:34.691574 [Byte1]: 71
1759 00:56:34.696170
1760 00:56:34.696254 Set Vref, RX VrefLevel [Byte0]: 72
1761 00:56:34.699342 [Byte1]: 72
1762 00:56:34.703620
1763 00:56:34.703758 Set Vref, RX VrefLevel [Byte0]: 73
1764 00:56:34.706945 [Byte1]: 73
1765 00:56:34.711353
1766 00:56:34.711441 Set Vref, RX VrefLevel [Byte0]: 74
1767 00:56:34.714683 [Byte1]: 74
1768 00:56:34.718930
1769 00:56:34.719018 Final RX Vref Byte 0 = 63 to rank0
1770 00:56:34.722373 Final RX Vref Byte 1 = 60 to rank0
1771 00:56:34.725682 Final RX Vref Byte 0 = 63 to rank1
1772 00:56:34.728894 Final RX Vref Byte 1 = 60 to rank1==
1773 00:56:34.732313 Dram Type= 6, Freq= 0, CH_1, rank 0
1774 00:56:34.738897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1775 00:56:34.738990 ==
1776 00:56:34.739058 DQS Delay:
1777 00:56:34.739120 DQS0 = 0, DQS1 = 0
1778 00:56:34.742324 DQM Delay:
1779 00:56:34.742410 DQM0 = 80, DQM1 = 70
1780 00:56:34.745731 DQ Delay:
1781 00:56:34.748909 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1782 00:56:34.748995 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1783 00:56:34.752465 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1784 00:56:34.755581 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1785 00:56:34.758974
1786 00:56:34.759063
1787 00:56:34.765624 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1788 00:56:34.768839 CH1 RK0: MR19=606, MR18=1721
1789 00:56:34.775648 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1790 00:56:34.775743
1791 00:56:34.778752 ----->DramcWriteLeveling(PI) begin...
1792 00:56:34.778842 ==
1793 00:56:34.782268 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 00:56:34.785619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 00:56:34.785707 ==
1796 00:56:34.788856 Write leveling (Byte 0): 27 => 27
1797 00:56:34.792566 Write leveling (Byte 1): 30 => 30
1798 00:56:34.795707 DramcWriteLeveling(PI) end<-----
1799 00:56:34.795795
1800 00:56:34.795861 ==
1801 00:56:34.798835 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 00:56:34.802423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 00:56:34.802513 ==
1804 00:56:34.805752 [Gating] SW mode calibration
1805 00:56:34.812244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1806 00:56:34.818988 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1807 00:56:34.822386 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1808 00:56:34.825460 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 00:56:34.832353 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1810 00:56:34.835483 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 00:56:34.839018 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 00:56:34.845595 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 00:56:34.848915 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 00:56:34.852047 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 00:56:34.859067 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 00:56:34.862087 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 00:56:34.865615 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 00:56:34.872381 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 00:56:34.875362 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 00:56:34.878930 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 00:56:34.882001 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 00:56:34.888946 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 00:56:34.892031 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 00:56:34.895501 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1825 00:56:34.902108 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1826 00:56:34.905305 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 00:56:34.908764 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 00:56:34.915378 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 00:56:34.918991 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 00:56:34.922172 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 00:56:34.928528 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 00:56:34.932402 0 9 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1833 00:56:34.935352 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1834 00:56:34.941786 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 00:56:34.945345 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 00:56:34.948819 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 00:56:34.955347 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 00:56:34.958622 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 00:56:34.962003 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1840 00:56:34.968695 0 10 4 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (1 1)
1841 00:56:34.971919 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1842 00:56:34.975315 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 00:56:34.982066 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 00:56:34.985198 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 00:56:34.988564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 00:56:34.992008 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 00:56:34.998818 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1848 00:56:35.002189 0 11 4 | B1->B0 | 2a2a 3d3d | 0 0 | (0 0) (0 0)
1849 00:56:35.005354 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1850 00:56:35.012132 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 00:56:35.015419 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 00:56:35.018828 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 00:56:35.025380 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 00:56:35.028699 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 00:56:35.031981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 00:56:35.038734 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1857 00:56:35.041848 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 00:56:35.045409 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 00:56:35.051896 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 00:56:35.055382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 00:56:35.058432 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 00:56:35.065276 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 00:56:35.068579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 00:56:35.071875 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 00:56:35.078571 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 00:56:35.082154 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 00:56:35.085385 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 00:56:35.088548 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 00:56:35.095142 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 00:56:35.098465 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 00:56:35.101862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 00:56:35.108837 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1873 00:56:35.111985 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1874 00:56:35.115411 Total UI for P1: 0, mck2ui 16
1875 00:56:35.118623 best dqsien dly found for B0: ( 0, 14, 4)
1876 00:56:35.122104 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1877 00:56:35.125309 Total UI for P1: 0, mck2ui 16
1878 00:56:35.128717 best dqsien dly found for B1: ( 0, 14, 6)
1879 00:56:35.131918 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1880 00:56:35.135405 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1881 00:56:35.135517
1882 00:56:35.141957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1883 00:56:35.145193 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 00:56:35.145303 [Gating] SW calibration Done
1885 00:56:35.148623 ==
1886 00:56:35.148735 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 00:56:35.155330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 00:56:35.155442 ==
1889 00:56:35.155539 RX Vref Scan: 0
1890 00:56:35.155632
1891 00:56:35.158666 RX Vref 0 -> 0, step: 1
1892 00:56:35.158775
1893 00:56:35.162041 RX Delay -130 -> 252, step: 16
1894 00:56:35.165193 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1895 00:56:35.168824 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1896 00:56:35.171785 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1897 00:56:35.178413 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1898 00:56:35.181859 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1899 00:56:35.185181 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1900 00:56:35.188498 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1901 00:56:35.192158 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1902 00:56:35.198497 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1903 00:56:35.202152 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1904 00:56:35.205419 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1905 00:56:35.208535 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1906 00:56:35.211879 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1907 00:56:35.218486 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1908 00:56:35.221849 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1909 00:56:35.225341 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1910 00:56:35.225452 ==
1911 00:56:35.228405 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 00:56:35.232018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 00:56:35.235090 ==
1914 00:56:35.235199 DQS Delay:
1915 00:56:35.235293 DQS0 = 0, DQS1 = 0
1916 00:56:35.238338 DQM Delay:
1917 00:56:35.238446 DQM0 = 76, DQM1 = 71
1918 00:56:35.241968 DQ Delay:
1919 00:56:35.242074 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =69
1920 00:56:35.245301 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1921 00:56:35.248354 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1922 00:56:35.251668 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1923 00:56:35.251775
1924 00:56:35.255172
1925 00:56:35.255279 ==
1926 00:56:35.258382 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 00:56:35.261783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 00:56:35.261891 ==
1929 00:56:35.261985
1930 00:56:35.262077
1931 00:56:35.264933 TX Vref Scan disable
1932 00:56:35.265040 == TX Byte 0 ==
1933 00:56:35.271645 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1934 00:56:35.275016 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1935 00:56:35.275125 == TX Byte 1 ==
1936 00:56:35.281675 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1937 00:56:35.284990 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1938 00:56:35.285098 ==
1939 00:56:35.288278 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 00:56:35.291717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 00:56:35.291826 ==
1942 00:56:35.305330 TX Vref=22, minBit 4, minWin=27, winSum=449
1943 00:56:35.308777 TX Vref=24, minBit 1, minWin=28, winSum=457
1944 00:56:35.311944 TX Vref=26, minBit 0, minWin=28, winSum=456
1945 00:56:35.315342 TX Vref=28, minBit 1, minWin=28, winSum=461
1946 00:56:35.318773 TX Vref=30, minBit 1, minWin=27, winSum=461
1947 00:56:35.321983 TX Vref=32, minBit 0, minWin=28, winSum=462
1948 00:56:35.328648 [TxChooseVref] Worse bit 0, Min win 28, Win sum 462, Final Vref 32
1949 00:56:35.328758
1950 00:56:35.331769 Final TX Range 1 Vref 32
1951 00:56:35.331878
1952 00:56:35.331972 ==
1953 00:56:35.335345 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 00:56:35.338824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 00:56:35.338932 ==
1956 00:56:35.339026
1957 00:56:35.341926
1958 00:56:35.342032 TX Vref Scan disable
1959 00:56:35.345277 == TX Byte 0 ==
1960 00:56:35.348437 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1961 00:56:35.355342 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1962 00:56:35.355450 == TX Byte 1 ==
1963 00:56:35.358501 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 00:56:35.365179 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 00:56:35.365286
1966 00:56:35.365378 [DATLAT]
1967 00:56:35.365469 Freq=800, CH1 RK1
1968 00:56:35.365606
1969 00:56:35.368603 DATLAT Default: 0xa
1970 00:56:35.368708 0, 0xFFFF, sum = 0
1971 00:56:35.371722 1, 0xFFFF, sum = 0
1972 00:56:35.371828 2, 0xFFFF, sum = 0
1973 00:56:35.375099 3, 0xFFFF, sum = 0
1974 00:56:35.375209 4, 0xFFFF, sum = 0
1975 00:56:35.378603 5, 0xFFFF, sum = 0
1976 00:56:35.381828 6, 0xFFFF, sum = 0
1977 00:56:35.381940 7, 0xFFFF, sum = 0
1978 00:56:35.385086 8, 0xFFFF, sum = 0
1979 00:56:35.385196 9, 0x0, sum = 1
1980 00:56:35.385292 10, 0x0, sum = 2
1981 00:56:35.388687 11, 0x0, sum = 3
1982 00:56:35.388797 12, 0x0, sum = 4
1983 00:56:35.391745 best_step = 10
1984 00:56:35.391853
1985 00:56:35.391947 ==
1986 00:56:35.395075 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 00:56:35.398257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 00:56:35.398366 ==
1989 00:56:35.401766 RX Vref Scan: 0
1990 00:56:35.401872
1991 00:56:35.401968 RX Vref 0 -> 0, step: 1
1992 00:56:35.402062
1993 00:56:35.404883 RX Delay -111 -> 252, step: 8
1994 00:56:35.411991 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1995 00:56:35.415466 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1996 00:56:35.418555 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1997 00:56:35.422067 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1998 00:56:35.425134 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
1999 00:56:35.431942 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2000 00:56:35.435116 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2001 00:56:35.438600 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2002 00:56:35.441875 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2003 00:56:35.445232 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2004 00:56:35.451852 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2005 00:56:35.455251 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2006 00:56:35.458714 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2007 00:56:35.461842 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2008 00:56:35.468357 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2009 00:56:35.471680 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2010 00:56:35.471790 ==
2011 00:56:35.475045 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 00:56:35.478286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 00:56:35.478397 ==
2014 00:56:35.478493 DQS Delay:
2015 00:56:35.481709 DQS0 = 0, DQS1 = 0
2016 00:56:35.481816 DQM Delay:
2017 00:56:35.485297 DQM0 = 77, DQM1 = 74
2018 00:56:35.485404 DQ Delay:
2019 00:56:35.488404 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =72
2020 00:56:35.491660 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2021 00:56:35.495131 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2022 00:56:35.498398 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2023 00:56:35.498506
2024 00:56:35.498601
2025 00:56:35.508496 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2026 00:56:35.508607 CH1 RK1: MR19=606, MR18=1F37
2027 00:56:35.514950 CH1_RK1: MR19=0x606, MR18=0x1F37, DQSOSC=395, MR23=63, INC=94, DEC=63
2028 00:56:35.518623 [RxdqsGatingPostProcess] freq 800
2029 00:56:35.525081 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 00:56:35.528354 Pre-setting of DQS Precalculation
2031 00:56:35.531896 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 00:56:35.538465 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 00:56:35.545131 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 00:56:35.548484
2035 00:56:35.548592
2036 00:56:35.548686 [Calibration Summary] 1600 Mbps
2037 00:56:35.551827 CH 0, Rank 0
2038 00:56:35.551936 SW Impedance : PASS
2039 00:56:35.554977 DUTY Scan : NO K
2040 00:56:35.558502 ZQ Calibration : PASS
2041 00:56:35.558612 Jitter Meter : NO K
2042 00:56:35.561832 CBT Training : PASS
2043 00:56:35.564930 Write leveling : PASS
2044 00:56:35.565040 RX DQS gating : PASS
2045 00:56:35.568499 RX DQ/DQS(RDDQC) : PASS
2046 00:56:35.571884 TX DQ/DQS : PASS
2047 00:56:35.571995 RX DATLAT : PASS
2048 00:56:35.575176 RX DQ/DQS(Engine): PASS
2049 00:56:35.578463 TX OE : NO K
2050 00:56:35.578572 All Pass.
2051 00:56:35.578667
2052 00:56:35.578758 CH 0, Rank 1
2053 00:56:35.581670 SW Impedance : PASS
2054 00:56:35.585157 DUTY Scan : NO K
2055 00:56:35.585264 ZQ Calibration : PASS
2056 00:56:35.588336 Jitter Meter : NO K
2057 00:56:35.588444 CBT Training : PASS
2058 00:56:35.591952 Write leveling : PASS
2059 00:56:35.595064 RX DQS gating : PASS
2060 00:56:35.595171 RX DQ/DQS(RDDQC) : PASS
2061 00:56:35.598528 TX DQ/DQS : PASS
2062 00:56:35.601791 RX DATLAT : PASS
2063 00:56:35.601899 RX DQ/DQS(Engine): PASS
2064 00:56:35.605215 TX OE : NO K
2065 00:56:35.605324 All Pass.
2066 00:56:35.605418
2067 00:56:35.608658 CH 1, Rank 0
2068 00:56:35.608769 SW Impedance : PASS
2069 00:56:35.612140 DUTY Scan : NO K
2070 00:56:35.615372 ZQ Calibration : PASS
2071 00:56:35.615480 Jitter Meter : NO K
2072 00:56:35.618740 CBT Training : PASS
2073 00:56:35.621651 Write leveling : PASS
2074 00:56:35.621760 RX DQS gating : PASS
2075 00:56:35.625000 RX DQ/DQS(RDDQC) : PASS
2076 00:56:35.628549 TX DQ/DQS : PASS
2077 00:56:35.628658 RX DATLAT : PASS
2078 00:56:35.631646 RX DQ/DQS(Engine): PASS
2079 00:56:35.631754 TX OE : NO K
2080 00:56:35.635049 All Pass.
2081 00:56:35.635157
2082 00:56:35.635250 CH 1, Rank 1
2083 00:56:35.638496 SW Impedance : PASS
2084 00:56:35.638604 DUTY Scan : NO K
2085 00:56:35.641599 ZQ Calibration : PASS
2086 00:56:35.644827 Jitter Meter : NO K
2087 00:56:35.644934 CBT Training : PASS
2088 00:56:35.648359 Write leveling : PASS
2089 00:56:35.651541 RX DQS gating : PASS
2090 00:56:35.651649 RX DQ/DQS(RDDQC) : PASS
2091 00:56:35.654990 TX DQ/DQS : PASS
2092 00:56:35.658363 RX DATLAT : PASS
2093 00:56:35.658473 RX DQ/DQS(Engine): PASS
2094 00:56:35.661436 TX OE : NO K
2095 00:56:35.661585 All Pass.
2096 00:56:35.661680
2097 00:56:35.665030 DramC Write-DBI off
2098 00:56:35.668340 PER_BANK_REFRESH: Hybrid Mode
2099 00:56:35.668449 TX_TRACKING: ON
2100 00:56:35.671494 [GetDramInforAfterCalByMRR] Vendor 6.
2101 00:56:35.674945 [GetDramInforAfterCalByMRR] Revision 606.
2102 00:56:35.678109 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 00:56:35.681514 MR0 0x3b3b
2104 00:56:35.681639 MR8 0x5151
2105 00:56:35.685114 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 00:56:35.685223
2107 00:56:35.685317 MR0 0x3b3b
2108 00:56:35.687926 MR8 0x5151
2109 00:56:35.691378 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 00:56:35.691486
2111 00:56:35.701272 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 00:56:35.704724 [FAST_K] Save calibration result to emmc
2113 00:56:35.708107 [FAST_K] Save calibration result to emmc
2114 00:56:35.708217 dram_init: config_dvfs: 1
2115 00:56:35.714640 dramc_set_vcore_voltage set vcore to 662500
2116 00:56:35.714750 Read voltage for 1200, 2
2117 00:56:35.718026 Vio18 = 0
2118 00:56:35.718140 Vcore = 662500
2119 00:56:35.718235 Vdram = 0
2120 00:56:35.718327 Vddq = 0
2121 00:56:35.721427 Vmddr = 0
2122 00:56:35.725052 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 00:56:35.731442 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 00:56:35.734609 MEM_TYPE=3, freq_sel=15
2125 00:56:35.734718 sv_algorithm_assistance_LP4_1600
2126 00:56:35.741270 ============ PULL DRAM RESETB DOWN ============
2127 00:56:35.744784 ========== PULL DRAM RESETB DOWN end =========
2128 00:56:35.748077 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 00:56:35.751510 ===================================
2130 00:56:35.754605 LPDDR4 DRAM CONFIGURATION
2131 00:56:35.758159 ===================================
2132 00:56:35.761406 EX_ROW_EN[0] = 0x0
2133 00:56:35.761556 EX_ROW_EN[1] = 0x0
2134 00:56:35.764848 LP4Y_EN = 0x0
2135 00:56:35.764956 WORK_FSP = 0x0
2136 00:56:35.768105 WL = 0x4
2137 00:56:35.768213 RL = 0x4
2138 00:56:35.771322 BL = 0x2
2139 00:56:35.771431 RPST = 0x0
2140 00:56:35.774671 RD_PRE = 0x0
2141 00:56:35.774778 WR_PRE = 0x1
2142 00:56:35.778113 WR_PST = 0x0
2143 00:56:35.778221 DBI_WR = 0x0
2144 00:56:35.781249 DBI_RD = 0x0
2145 00:56:35.781356 OTF = 0x1
2146 00:56:35.784693 ===================================
2147 00:56:35.787816 ===================================
2148 00:56:35.791189 ANA top config
2149 00:56:35.794800 ===================================
2150 00:56:35.797986 DLL_ASYNC_EN = 0
2151 00:56:35.798096 ALL_SLAVE_EN = 0
2152 00:56:35.801290 NEW_RANK_MODE = 1
2153 00:56:35.804599 DLL_IDLE_MODE = 1
2154 00:56:35.808110 LP45_APHY_COMB_EN = 1
2155 00:56:35.808219 TX_ODT_DIS = 1
2156 00:56:35.811202 NEW_8X_MODE = 1
2157 00:56:35.814763 ===================================
2158 00:56:35.818050 ===================================
2159 00:56:35.821282 data_rate = 2400
2160 00:56:35.824770 CKR = 1
2161 00:56:35.828216 DQ_P2S_RATIO = 8
2162 00:56:35.831483 ===================================
2163 00:56:35.834693 CA_P2S_RATIO = 8
2164 00:56:35.834802 DQ_CA_OPEN = 0
2165 00:56:35.838248 DQ_SEMI_OPEN = 0
2166 00:56:35.841412 CA_SEMI_OPEN = 0
2167 00:56:35.844852 CA_FULL_RATE = 0
2168 00:56:35.848246 DQ_CKDIV4_EN = 0
2169 00:56:35.848355 CA_CKDIV4_EN = 0
2170 00:56:35.851472 CA_PREDIV_EN = 0
2171 00:56:35.854942 PH8_DLY = 17
2172 00:56:35.858261 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 00:56:35.861415 DQ_AAMCK_DIV = 4
2174 00:56:35.864702 CA_AAMCK_DIV = 4
2175 00:56:35.864813 CA_ADMCK_DIV = 4
2176 00:56:35.868297 DQ_TRACK_CA_EN = 0
2177 00:56:35.871294 CA_PICK = 1200
2178 00:56:35.874702 CA_MCKIO = 1200
2179 00:56:35.878136 MCKIO_SEMI = 0
2180 00:56:35.881685 PLL_FREQ = 2366
2181 00:56:35.884677 DQ_UI_PI_RATIO = 32
2182 00:56:35.888109 CA_UI_PI_RATIO = 0
2183 00:56:35.891413 ===================================
2184 00:56:35.891523 ===================================
2185 00:56:35.894915 memory_type:LPDDR4
2186 00:56:35.898116 GP_NUM : 10
2187 00:56:35.898224 SRAM_EN : 1
2188 00:56:35.901454 MD32_EN : 0
2189 00:56:35.904612 ===================================
2190 00:56:35.908173 [ANA_INIT] >>>>>>>>>>>>>>
2191 00:56:35.911470 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 00:56:35.914670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 00:56:35.918310 ===================================
2194 00:56:35.918392 data_rate = 2400,PCW = 0X5b00
2195 00:56:35.921356 ===================================
2196 00:56:35.924894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 00:56:35.931393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 00:56:35.938403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 00:56:35.941696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 00:56:35.944735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 00:56:35.948375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 00:56:35.951335 [ANA_INIT] flow start
2203 00:56:35.954721 [ANA_INIT] PLL >>>>>>>>
2204 00:56:35.954806 [ANA_INIT] PLL <<<<<<<<
2205 00:56:35.957983 [ANA_INIT] MIDPI >>>>>>>>
2206 00:56:35.961639 [ANA_INIT] MIDPI <<<<<<<<
2207 00:56:35.961724 [ANA_INIT] DLL >>>>>>>>
2208 00:56:35.964802 [ANA_INIT] DLL <<<<<<<<
2209 00:56:35.967952 [ANA_INIT] flow end
2210 00:56:35.971490 ============ LP4 DIFF to SE enter ============
2211 00:56:35.974802 ============ LP4 DIFF to SE exit ============
2212 00:56:35.978041 [ANA_INIT] <<<<<<<<<<<<<
2213 00:56:35.981198 [Flow] Enable top DCM control >>>>>
2214 00:56:35.984752 [Flow] Enable top DCM control <<<<<
2215 00:56:35.988163 Enable DLL master slave shuffle
2216 00:56:35.991397 ==============================================================
2217 00:56:35.994878 Gating Mode config
2218 00:56:35.998085 ==============================================================
2219 00:56:36.001359 Config description:
2220 00:56:36.011308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 00:56:36.018081 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 00:56:36.021456 SELPH_MODE 0: By rank 1: By Phase
2223 00:56:36.028047 ==============================================================
2224 00:56:36.031278 GAT_TRACK_EN = 1
2225 00:56:36.034679 RX_GATING_MODE = 2
2226 00:56:36.038136 RX_GATING_TRACK_MODE = 2
2227 00:56:36.041308 SELPH_MODE = 1
2228 00:56:36.044795 PICG_EARLY_EN = 1
2229 00:56:36.044880 VALID_LAT_VALUE = 1
2230 00:56:36.051287 ==============================================================
2231 00:56:36.054562 Enter into Gating configuration >>>>
2232 00:56:36.058198 Exit from Gating configuration <<<<
2233 00:56:36.061278 Enter into DVFS_PRE_config >>>>>
2234 00:56:36.071553 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 00:56:36.074828 Exit from DVFS_PRE_config <<<<<
2236 00:56:36.077893 Enter into PICG configuration >>>>
2237 00:56:36.081343 Exit from PICG configuration <<<<
2238 00:56:36.084814 [RX_INPUT] configuration >>>>>
2239 00:56:36.087894 [RX_INPUT] configuration <<<<<
2240 00:56:36.091159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 00:56:36.097763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 00:56:36.104586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 00:56:36.111049 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 00:56:36.117758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 00:56:36.121145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 00:56:36.127752 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 00:56:36.131123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 00:56:36.134357 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 00:56:36.137890 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 00:56:36.144550 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 00:56:36.147828 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 00:56:36.151248 ===================================
2253 00:56:36.154372 LPDDR4 DRAM CONFIGURATION
2254 00:56:36.157774 ===================================
2255 00:56:36.157860 EX_ROW_EN[0] = 0x0
2256 00:56:36.161294 EX_ROW_EN[1] = 0x0
2257 00:56:36.161406 LP4Y_EN = 0x0
2258 00:56:36.164395 WORK_FSP = 0x0
2259 00:56:36.164503 WL = 0x4
2260 00:56:36.167643 RL = 0x4
2261 00:56:36.167751 BL = 0x2
2262 00:56:36.171263 RPST = 0x0
2263 00:56:36.171372 RD_PRE = 0x0
2264 00:56:36.174350 WR_PRE = 0x1
2265 00:56:36.174457 WR_PST = 0x0
2266 00:56:36.177571 DBI_WR = 0x0
2267 00:56:36.180865 DBI_RD = 0x0
2268 00:56:36.180974 OTF = 0x1
2269 00:56:36.184472 ===================================
2270 00:56:36.187724 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 00:56:36.190960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 00:56:36.197716 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 00:56:36.200931 ===================================
2274 00:56:36.201041 LPDDR4 DRAM CONFIGURATION
2275 00:56:36.204450 ===================================
2276 00:56:36.207584 EX_ROW_EN[0] = 0x10
2277 00:56:36.210961 EX_ROW_EN[1] = 0x0
2278 00:56:36.211072 LP4Y_EN = 0x0
2279 00:56:36.214283 WORK_FSP = 0x0
2280 00:56:36.214393 WL = 0x4
2281 00:56:36.217697 RL = 0x4
2282 00:56:36.217806 BL = 0x2
2283 00:56:36.220943 RPST = 0x0
2284 00:56:36.221050 RD_PRE = 0x0
2285 00:56:36.224513 WR_PRE = 0x1
2286 00:56:36.224622 WR_PST = 0x0
2287 00:56:36.227677 DBI_WR = 0x0
2288 00:56:36.227786 DBI_RD = 0x0
2289 00:56:36.231035 OTF = 0x1
2290 00:56:36.234384 ===================================
2291 00:56:36.240931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 00:56:36.241042 ==
2293 00:56:36.244287 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 00:56:36.247799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 00:56:36.247911 ==
2296 00:56:36.251048 [Duty_Offset_Calibration]
2297 00:56:36.251156 B0:2 B1:0 CA:3
2298 00:56:36.251250
2299 00:56:36.254353 [DutyScan_Calibration_Flow] k_type=0
2300 00:56:36.264557
2301 00:56:36.264675 ==CLK 0==
2302 00:56:36.268050 Final CLK duty delay cell = 0
2303 00:56:36.271396 [0] MAX Duty = 5031%(X100), DQS PI = 12
2304 00:56:36.274562 [0] MIN Duty = 4906%(X100), DQS PI = 54
2305 00:56:36.274671 [0] AVG Duty = 4968%(X100)
2306 00:56:36.277985
2307 00:56:36.281299 CH0 CLK Duty spec in!! Max-Min= 125%
2308 00:56:36.284469 [DutyScan_Calibration_Flow] ====Done====
2309 00:56:36.284578
2310 00:56:36.288021 [DutyScan_Calibration_Flow] k_type=1
2311 00:56:36.303067
2312 00:56:36.303188 ==DQS 0 ==
2313 00:56:36.306491 Final DQS duty delay cell = 0
2314 00:56:36.309737 [0] MAX Duty = 5062%(X100), DQS PI = 14
2315 00:56:36.313149 [0] MIN Duty = 4907%(X100), DQS PI = 2
2316 00:56:36.313256 [0] AVG Duty = 4984%(X100)
2317 00:56:36.316479
2318 00:56:36.316587 ==DQS 1 ==
2319 00:56:36.319937 Final DQS duty delay cell = -4
2320 00:56:36.323317 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2321 00:56:36.326515 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2322 00:56:36.329995 [-4] AVG Duty = 4937%(X100)
2323 00:56:36.330103
2324 00:56:36.333100 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2325 00:56:36.333208
2326 00:56:36.336305 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2327 00:56:36.339773 [DutyScan_Calibration_Flow] ====Done====
2328 00:56:36.339881
2329 00:56:36.342949 [DutyScan_Calibration_Flow] k_type=3
2330 00:56:36.360851
2331 00:56:36.360981 ==DQM 0 ==
2332 00:56:36.364018 Final DQM duty delay cell = 0
2333 00:56:36.367612 [0] MAX Duty = 5124%(X100), DQS PI = 28
2334 00:56:36.370738 [0] MIN Duty = 4907%(X100), DQS PI = 0
2335 00:56:36.370846 [0] AVG Duty = 5015%(X100)
2336 00:56:36.374104
2337 00:56:36.374210 ==DQM 1 ==
2338 00:56:36.377253 Final DQM duty delay cell = 4
2339 00:56:36.380715 [4] MAX Duty = 5124%(X100), DQS PI = 50
2340 00:56:36.384281 [4] MIN Duty = 5000%(X100), DQS PI = 14
2341 00:56:36.384389 [4] AVG Duty = 5062%(X100)
2342 00:56:36.387488
2343 00:56:36.390962 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2344 00:56:36.391071
2345 00:56:36.394190 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2346 00:56:36.397439 [DutyScan_Calibration_Flow] ====Done====
2347 00:56:36.397591
2348 00:56:36.400790 [DutyScan_Calibration_Flow] k_type=2
2349 00:56:36.415597
2350 00:56:36.415714 ==DQ 0 ==
2351 00:56:36.418841 Final DQ duty delay cell = -4
2352 00:56:36.422145 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2353 00:56:36.425702 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2354 00:56:36.428975 [-4] AVG Duty = 4969%(X100)
2355 00:56:36.429082
2356 00:56:36.429175 ==DQ 1 ==
2357 00:56:36.432156 Final DQ duty delay cell = -4
2358 00:56:36.435413 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2359 00:56:36.438940 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2360 00:56:36.442207 [-4] AVG Duty = 4922%(X100)
2361 00:56:36.442314
2362 00:56:36.445649 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2363 00:56:36.445757
2364 00:56:36.448822 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2365 00:56:36.452313 [DutyScan_Calibration_Flow] ====Done====
2366 00:56:36.452421 ==
2367 00:56:36.455566 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 00:56:36.458762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 00:56:36.458882 ==
2370 00:56:36.462413 [Duty_Offset_Calibration]
2371 00:56:36.462521 B0:1 B1:-2 CA:0
2372 00:56:36.462615
2373 00:56:36.465545 [DutyScan_Calibration_Flow] k_type=0
2374 00:56:36.476167
2375 00:56:36.476279 ==CLK 0==
2376 00:56:36.479343 Final CLK duty delay cell = 0
2377 00:56:36.482669 [0] MAX Duty = 5031%(X100), DQS PI = 18
2378 00:56:36.486190 [0] MIN Duty = 4876%(X100), DQS PI = 58
2379 00:56:36.486299 [0] AVG Duty = 4953%(X100)
2380 00:56:36.489378
2381 00:56:36.492643 CH1 CLK Duty spec in!! Max-Min= 155%
2382 00:56:36.496124 [DutyScan_Calibration_Flow] ====Done====
2383 00:56:36.496231
2384 00:56:36.499341 [DutyScan_Calibration_Flow] k_type=1
2385 00:56:36.514552
2386 00:56:36.514697 ==DQS 0 ==
2387 00:56:36.517893 Final DQS duty delay cell = -4
2388 00:56:36.521342 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2389 00:56:36.524657 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2390 00:56:36.527936 [-4] AVG Duty = 4953%(X100)
2391 00:56:36.528049
2392 00:56:36.528142 ==DQS 1 ==
2393 00:56:36.531232 Final DQS duty delay cell = 0
2394 00:56:36.534647 [0] MAX Duty = 5093%(X100), DQS PI = 0
2395 00:56:36.538070 [0] MIN Duty = 4875%(X100), DQS PI = 26
2396 00:56:36.541620 [0] AVG Duty = 4984%(X100)
2397 00:56:36.541728
2398 00:56:36.544670 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2399 00:56:36.544777
2400 00:56:36.547817 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2401 00:56:36.551373 [DutyScan_Calibration_Flow] ====Done====
2402 00:56:36.551478
2403 00:56:36.554547 [DutyScan_Calibration_Flow] k_type=3
2404 00:56:36.571313
2405 00:56:36.571444 ==DQM 0 ==
2406 00:56:36.574733 Final DQM duty delay cell = 0
2407 00:56:36.578317 [0] MAX Duty = 5000%(X100), DQS PI = 24
2408 00:56:36.581408 [0] MIN Duty = 4876%(X100), DQS PI = 0
2409 00:56:36.581561 [0] AVG Duty = 4938%(X100)
2410 00:56:36.584944
2411 00:56:36.585051 ==DQM 1 ==
2412 00:56:36.588162 Final DQM duty delay cell = 0
2413 00:56:36.591333 [0] MAX Duty = 5031%(X100), DQS PI = 36
2414 00:56:36.594765 [0] MIN Duty = 4907%(X100), DQS PI = 0
2415 00:56:36.594874 [0] AVG Duty = 4969%(X100)
2416 00:56:36.598187
2417 00:56:36.601344 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2418 00:56:36.601453
2419 00:56:36.604892 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2420 00:56:36.608126 [DutyScan_Calibration_Flow] ====Done====
2421 00:56:36.608236
2422 00:56:36.611685 [DutyScan_Calibration_Flow] k_type=2
2423 00:56:36.627861
2424 00:56:36.627979 ==DQ 0 ==
2425 00:56:36.631013 Final DQ duty delay cell = 0
2426 00:56:36.634390 [0] MAX Duty = 5062%(X100), DQS PI = 12
2427 00:56:36.637749 [0] MIN Duty = 4938%(X100), DQS PI = 54
2428 00:56:36.637832 [0] AVG Duty = 5000%(X100)
2429 00:56:36.637898
2430 00:56:36.641068 ==DQ 1 ==
2431 00:56:36.644476 Final DQ duty delay cell = 0
2432 00:56:36.647823 [0] MAX Duty = 5093%(X100), DQS PI = 20
2433 00:56:36.651240 [0] MIN Duty = 4969%(X100), DQS PI = 26
2434 00:56:36.651323 [0] AVG Duty = 5031%(X100)
2435 00:56:36.651388
2436 00:56:36.654695 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2437 00:56:36.654778
2438 00:56:36.657860 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2439 00:56:36.664440 [DutyScan_Calibration_Flow] ====Done====
2440 00:56:36.668009 nWR fixed to 30
2441 00:56:36.668093 [ModeRegInit_LP4] CH0 RK0
2442 00:56:36.671125 [ModeRegInit_LP4] CH0 RK1
2443 00:56:36.674473 [ModeRegInit_LP4] CH1 RK0
2444 00:56:36.674554 [ModeRegInit_LP4] CH1 RK1
2445 00:56:36.677880 match AC timing 7
2446 00:56:36.681358 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 00:56:36.684485 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 00:56:36.691512 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 00:56:36.694674 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 00:56:36.701162 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 00:56:36.701249 ==
2452 00:56:36.704718 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 00:56:36.707860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 00:56:36.707970 ==
2455 00:56:36.714629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 00:56:36.718066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 00:56:36.727827 [CA 0] Center 40 (10~71) winsize 62
2458 00:56:36.731162 [CA 1] Center 39 (9~70) winsize 62
2459 00:56:36.734543 [CA 2] Center 36 (6~66) winsize 61
2460 00:56:36.737616 [CA 3] Center 35 (5~66) winsize 62
2461 00:56:36.741075 [CA 4] Center 34 (4~65) winsize 62
2462 00:56:36.744266 [CA 5] Center 33 (3~63) winsize 61
2463 00:56:36.744351
2464 00:56:36.747901 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2465 00:56:36.747984
2466 00:56:36.751343 [CATrainingPosCal] consider 1 rank data
2467 00:56:36.754475 u2DelayCellTimex100 = 270/100 ps
2468 00:56:36.757800 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2469 00:56:36.764335 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2470 00:56:36.767659 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2471 00:56:36.771252 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 00:56:36.774468 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2473 00:56:36.777733 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2474 00:56:36.777843
2475 00:56:36.781186 CA PerBit enable=1, Macro0, CA PI delay=33
2476 00:56:36.781294
2477 00:56:36.784601 [CBTSetCACLKResult] CA Dly = 33
2478 00:56:36.784712 CS Dly: 7 (0~38)
2479 00:56:36.787917 ==
2480 00:56:36.788026 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 00:56:36.794507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 00:56:36.794619 ==
2483 00:56:36.797627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 00:56:36.804250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2485 00:56:36.813682 [CA 0] Center 40 (10~70) winsize 61
2486 00:56:36.816944 [CA 1] Center 39 (9~70) winsize 62
2487 00:56:36.820260 [CA 2] Center 35 (5~66) winsize 62
2488 00:56:36.823585 [CA 3] Center 35 (5~66) winsize 62
2489 00:56:36.827009 [CA 4] Center 34 (4~65) winsize 62
2490 00:56:36.830284 [CA 5] Center 33 (3~64) winsize 62
2491 00:56:36.830392
2492 00:56:36.833755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2493 00:56:36.833865
2494 00:56:36.837169 [CATrainingPosCal] consider 2 rank data
2495 00:56:36.840250 u2DelayCellTimex100 = 270/100 ps
2496 00:56:36.843673 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2497 00:56:36.850458 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2498 00:56:36.853715 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2499 00:56:36.857149 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 00:56:36.860380 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2501 00:56:36.863845 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2502 00:56:36.863955
2503 00:56:36.866998 CA PerBit enable=1, Macro0, CA PI delay=33
2504 00:56:36.867105
2505 00:56:36.870690 [CBTSetCACLKResult] CA Dly = 33
2506 00:56:36.870798 CS Dly: 8 (0~40)
2507 00:56:36.873903
2508 00:56:36.877281 ----->DramcWriteLeveling(PI) begin...
2509 00:56:36.877389 ==
2510 00:56:36.880555 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 00:56:36.883915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 00:56:36.884023 ==
2513 00:56:36.887458 Write leveling (Byte 0): 33 => 33
2514 00:56:36.890626 Write leveling (Byte 1): 29 => 29
2515 00:56:36.893705 DramcWriteLeveling(PI) end<-----
2516 00:56:36.893811
2517 00:56:36.893904 ==
2518 00:56:36.897202 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 00:56:36.900811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 00:56:36.900918 ==
2521 00:56:36.903943 [Gating] SW mode calibration
2522 00:56:36.910672 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 00:56:36.913944 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 00:56:36.920449 0 15 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
2525 00:56:36.923948 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2526 00:56:36.927329 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 00:56:36.933970 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 00:56:36.937572 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 00:56:36.940545 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 00:56:36.947297 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 00:56:36.950461 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2532 00:56:36.954005 1 0 0 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 1)
2533 00:56:36.960483 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2534 00:56:36.963736 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 00:56:36.967160 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 00:56:36.974011 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 00:56:36.977046 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 00:56:36.980531 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 00:56:36.987163 1 0 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2540 00:56:36.990740 1 1 0 | B1->B0 | 2929 3838 | 1 0 | (0 0) (0 0)
2541 00:56:36.993909 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2542 00:56:37.000413 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 00:56:37.003900 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 00:56:37.007170 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 00:56:37.013812 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 00:56:37.017060 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 00:56:37.020493 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2548 00:56:37.024084 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2549 00:56:37.030407 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 00:56:37.033983 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 00:56:37.037102 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 00:56:37.043815 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 00:56:37.047252 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 00:56:37.050418 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 00:56:37.057286 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 00:56:37.060654 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 00:56:37.063769 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 00:56:37.070735 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 00:56:37.073864 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 00:56:37.076885 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 00:56:37.083686 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 00:56:37.086914 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 00:56:37.090465 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 00:56:37.096890 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 00:56:37.100338 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 00:56:37.103540 Total UI for P1: 0, mck2ui 16
2567 00:56:37.106836 best dqsien dly found for B0: ( 1, 3, 30)
2568 00:56:37.110188 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 00:56:37.113799 Total UI for P1: 0, mck2ui 16
2570 00:56:37.116804 best dqsien dly found for B1: ( 1, 4, 4)
2571 00:56:37.120387 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2572 00:56:37.123581 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2573 00:56:37.123688
2574 00:56:37.126941 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2575 00:56:37.133724 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2576 00:56:37.133807 [Gating] SW calibration Done
2577 00:56:37.133873 ==
2578 00:56:37.137224 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 00:56:37.143820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 00:56:37.143903 ==
2581 00:56:37.143968 RX Vref Scan: 0
2582 00:56:37.144029
2583 00:56:37.147137 RX Vref 0 -> 0, step: 1
2584 00:56:37.147217
2585 00:56:37.150476 RX Delay -40 -> 252, step: 8
2586 00:56:37.153721 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2587 00:56:37.157099 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2588 00:56:37.160414 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2589 00:56:37.163705 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2590 00:56:37.170540 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2591 00:56:37.173639 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2592 00:56:37.176985 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2593 00:56:37.180354 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2594 00:56:37.183941 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2595 00:56:37.190211 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2596 00:56:37.193436 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2597 00:56:37.197050 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2598 00:56:37.200429 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2599 00:56:37.203619 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2600 00:56:37.210301 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2601 00:56:37.213672 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2602 00:56:37.213782 ==
2603 00:56:37.217272 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 00:56:37.220301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 00:56:37.220411 ==
2606 00:56:37.220507 DQS Delay:
2607 00:56:37.223707 DQS0 = 0, DQS1 = 0
2608 00:56:37.223816 DQM Delay:
2609 00:56:37.226993 DQM0 = 113, DQM1 = 102
2610 00:56:37.227107 DQ Delay:
2611 00:56:37.230146 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2612 00:56:37.233419 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2613 00:56:37.237298 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2614 00:56:37.240461 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2615 00:56:37.240571
2616 00:56:37.243791
2617 00:56:37.243898 ==
2618 00:56:37.247181 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 00:56:37.250293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 00:56:37.250405 ==
2621 00:56:37.250502
2622 00:56:37.250594
2623 00:56:37.253653 TX Vref Scan disable
2624 00:56:37.253762 == TX Byte 0 ==
2625 00:56:37.256967 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2626 00:56:37.263695 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2627 00:56:37.263812 == TX Byte 1 ==
2628 00:56:37.270404 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2629 00:56:37.273650 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2630 00:56:37.273759 ==
2631 00:56:37.277128 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 00:56:37.280281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 00:56:37.280391 ==
2634 00:56:37.292749 TX Vref=22, minBit 1, minWin=25, winSum=416
2635 00:56:37.296054 TX Vref=24, minBit 1, minWin=26, winSum=423
2636 00:56:37.299530 TX Vref=26, minBit 1, minWin=26, winSum=427
2637 00:56:37.302556 TX Vref=28, minBit 4, minWin=26, winSum=435
2638 00:56:37.306044 TX Vref=30, minBit 1, minWin=27, winSum=436
2639 00:56:37.309348 TX Vref=32, minBit 2, minWin=26, winSum=425
2640 00:56:37.316142 [TxChooseVref] Worse bit 1, Min win 27, Win sum 436, Final Vref 30
2641 00:56:37.316256
2642 00:56:37.319284 Final TX Range 1 Vref 30
2643 00:56:37.319392
2644 00:56:37.319487 ==
2645 00:56:37.322401 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 00:56:37.325823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 00:56:37.325933 ==
2648 00:56:37.326028
2649 00:56:37.329264
2650 00:56:37.329371 TX Vref Scan disable
2651 00:56:37.332439 == TX Byte 0 ==
2652 00:56:37.335859 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2653 00:56:37.339354 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2654 00:56:37.342628 == TX Byte 1 ==
2655 00:56:37.345796 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2656 00:56:37.349348 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2657 00:56:37.352447
2658 00:56:37.352556 [DATLAT]
2659 00:56:37.352651 Freq=1200, CH0 RK0
2660 00:56:37.352745
2661 00:56:37.355910 DATLAT Default: 0xd
2662 00:56:37.356020 0, 0xFFFF, sum = 0
2663 00:56:37.359226 1, 0xFFFF, sum = 0
2664 00:56:37.359337 2, 0xFFFF, sum = 0
2665 00:56:37.362395 3, 0xFFFF, sum = 0
2666 00:56:37.362507 4, 0xFFFF, sum = 0
2667 00:56:37.365866 5, 0xFFFF, sum = 0
2668 00:56:37.365994 6, 0xFFFF, sum = 0
2669 00:56:37.369036 7, 0xFFFF, sum = 0
2670 00:56:37.372744 8, 0xFFFF, sum = 0
2671 00:56:37.372854 9, 0xFFFF, sum = 0
2672 00:56:37.375870 10, 0xFFFF, sum = 0
2673 00:56:37.375980 11, 0xFFFF, sum = 0
2674 00:56:37.379079 12, 0x0, sum = 1
2675 00:56:37.379189 13, 0x0, sum = 2
2676 00:56:37.382554 14, 0x0, sum = 3
2677 00:56:37.382663 15, 0x0, sum = 4
2678 00:56:37.382760 best_step = 13
2679 00:56:37.382852
2680 00:56:37.385694 ==
2681 00:56:37.389284 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 00:56:37.392420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 00:56:37.392529 ==
2684 00:56:37.392624 RX Vref Scan: 1
2685 00:56:37.392716
2686 00:56:37.395902 Set Vref Range= 32 -> 127
2687 00:56:37.396010
2688 00:56:37.399047 RX Vref 32 -> 127, step: 1
2689 00:56:37.399155
2690 00:56:37.402619 RX Delay -37 -> 252, step: 4
2691 00:56:37.402727
2692 00:56:37.406002 Set Vref, RX VrefLevel [Byte0]: 32
2693 00:56:37.409091 [Byte1]: 32
2694 00:56:37.409200
2695 00:56:37.412556 Set Vref, RX VrefLevel [Byte0]: 33
2696 00:56:37.415673 [Byte1]: 33
2697 00:56:37.419121
2698 00:56:37.419228 Set Vref, RX VrefLevel [Byte0]: 34
2699 00:56:37.422313 [Byte1]: 34
2700 00:56:37.427240
2701 00:56:37.427348 Set Vref, RX VrefLevel [Byte0]: 35
2702 00:56:37.430529 [Byte1]: 35
2703 00:56:37.435007
2704 00:56:37.435116 Set Vref, RX VrefLevel [Byte0]: 36
2705 00:56:37.438417 [Byte1]: 36
2706 00:56:37.443072
2707 00:56:37.443179 Set Vref, RX VrefLevel [Byte0]: 37
2708 00:56:37.446457 [Byte1]: 37
2709 00:56:37.450935
2710 00:56:37.451042 Set Vref, RX VrefLevel [Byte0]: 38
2711 00:56:37.454285 [Byte1]: 38
2712 00:56:37.458959
2713 00:56:37.459068 Set Vref, RX VrefLevel [Byte0]: 39
2714 00:56:37.462150 [Byte1]: 39
2715 00:56:37.466922
2716 00:56:37.467033 Set Vref, RX VrefLevel [Byte0]: 40
2717 00:56:37.470456 [Byte1]: 40
2718 00:56:37.475214
2719 00:56:37.475323 Set Vref, RX VrefLevel [Byte0]: 41
2720 00:56:37.478301 [Byte1]: 41
2721 00:56:37.483255
2722 00:56:37.483365 Set Vref, RX VrefLevel [Byte0]: 42
2723 00:56:37.486323 [Byte1]: 42
2724 00:56:37.491306
2725 00:56:37.491415 Set Vref, RX VrefLevel [Byte0]: 43
2726 00:56:37.494460 [Byte1]: 43
2727 00:56:37.498836
2728 00:56:37.498946 Set Vref, RX VrefLevel [Byte0]: 44
2729 00:56:37.502183 [Byte1]: 44
2730 00:56:37.506916
2731 00:56:37.507086 Set Vref, RX VrefLevel [Byte0]: 45
2732 00:56:37.510337 [Byte1]: 45
2733 00:56:37.514979
2734 00:56:37.515089 Set Vref, RX VrefLevel [Byte0]: 46
2735 00:56:37.518398 [Byte1]: 46
2736 00:56:37.523029
2737 00:56:37.523134 Set Vref, RX VrefLevel [Byte0]: 47
2738 00:56:37.526250 [Byte1]: 47
2739 00:56:37.530885
2740 00:56:37.530992 Set Vref, RX VrefLevel [Byte0]: 48
2741 00:56:37.534272 [Byte1]: 48
2742 00:56:37.538920
2743 00:56:37.539026 Set Vref, RX VrefLevel [Byte0]: 49
2744 00:56:37.542412 [Byte1]: 49
2745 00:56:37.546953
2746 00:56:37.547058 Set Vref, RX VrefLevel [Byte0]: 50
2747 00:56:37.550510 [Byte1]: 50
2748 00:56:37.554861
2749 00:56:37.554964 Set Vref, RX VrefLevel [Byte0]: 51
2750 00:56:37.558492 [Byte1]: 51
2751 00:56:37.562939
2752 00:56:37.563043 Set Vref, RX VrefLevel [Byte0]: 52
2753 00:56:37.566318 [Byte1]: 52
2754 00:56:37.571204
2755 00:56:37.571305 Set Vref, RX VrefLevel [Byte0]: 53
2756 00:56:37.574575 [Byte1]: 53
2757 00:56:37.579001
2758 00:56:37.579105 Set Vref, RX VrefLevel [Byte0]: 54
2759 00:56:37.582255 [Byte1]: 54
2760 00:56:37.586811
2761 00:56:37.586917 Set Vref, RX VrefLevel [Byte0]: 55
2762 00:56:37.590341 [Byte1]: 55
2763 00:56:37.595113
2764 00:56:37.595220 Set Vref, RX VrefLevel [Byte0]: 56
2765 00:56:37.598259 [Byte1]: 56
2766 00:56:37.602893
2767 00:56:37.603000 Set Vref, RX VrefLevel [Byte0]: 57
2768 00:56:37.606287 [Byte1]: 57
2769 00:56:37.610921
2770 00:56:37.611027 Set Vref, RX VrefLevel [Byte0]: 58
2771 00:56:37.614208 [Byte1]: 58
2772 00:56:37.618923
2773 00:56:37.619026 Set Vref, RX VrefLevel [Byte0]: 59
2774 00:56:37.622424 [Byte1]: 59
2775 00:56:37.627028
2776 00:56:37.627131 Set Vref, RX VrefLevel [Byte0]: 60
2777 00:56:37.630370 [Byte1]: 60
2778 00:56:37.634932
2779 00:56:37.635036 Set Vref, RX VrefLevel [Byte0]: 61
2780 00:56:37.638359 [Byte1]: 61
2781 00:56:37.643223
2782 00:56:37.643328 Set Vref, RX VrefLevel [Byte0]: 62
2783 00:56:37.646306 [Byte1]: 62
2784 00:56:37.650910
2785 00:56:37.651013 Set Vref, RX VrefLevel [Byte0]: 63
2786 00:56:37.654531 [Byte1]: 63
2787 00:56:37.659057
2788 00:56:37.659163 Set Vref, RX VrefLevel [Byte0]: 64
2789 00:56:37.662166 [Byte1]: 64
2790 00:56:37.667251
2791 00:56:37.667355 Set Vref, RX VrefLevel [Byte0]: 65
2792 00:56:37.670364 [Byte1]: 65
2793 00:56:37.675102
2794 00:56:37.675207 Set Vref, RX VrefLevel [Byte0]: 66
2795 00:56:37.678217 [Byte1]: 66
2796 00:56:37.682940
2797 00:56:37.683043 Set Vref, RX VrefLevel [Byte0]: 67
2798 00:56:37.686454 [Byte1]: 67
2799 00:56:37.691190
2800 00:56:37.691293 Set Vref, RX VrefLevel [Byte0]: 68
2801 00:56:37.694348 [Byte1]: 68
2802 00:56:37.698972
2803 00:56:37.699077 Set Vref, RX VrefLevel [Byte0]: 69
2804 00:56:37.702431 [Byte1]: 69
2805 00:56:37.707176
2806 00:56:37.707305 Set Vref, RX VrefLevel [Byte0]: 70
2807 00:56:37.710239 [Byte1]: 70
2808 00:56:37.715056
2809 00:56:37.715162 Set Vref, RX VrefLevel [Byte0]: 71
2810 00:56:37.718263 [Byte1]: 71
2811 00:56:37.722964
2812 00:56:37.723068 Set Vref, RX VrefLevel [Byte0]: 72
2813 00:56:37.726323 [Byte1]: 72
2814 00:56:37.731178
2815 00:56:37.731284 Set Vref, RX VrefLevel [Byte0]: 73
2816 00:56:37.734476 [Byte1]: 73
2817 00:56:37.739312
2818 00:56:37.739416 Set Vref, RX VrefLevel [Byte0]: 74
2819 00:56:37.742259 [Byte1]: 74
2820 00:56:37.747164
2821 00:56:37.747269 Final RX Vref Byte 0 = 60 to rank0
2822 00:56:37.750337 Final RX Vref Byte 1 = 52 to rank0
2823 00:56:37.753819 Final RX Vref Byte 0 = 60 to rank1
2824 00:56:37.756956 Final RX Vref Byte 1 = 52 to rank1==
2825 00:56:37.760562 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 00:56:37.767024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 00:56:37.767132 ==
2828 00:56:37.767224 DQS Delay:
2829 00:56:37.770044 DQS0 = 0, DQS1 = 0
2830 00:56:37.770148 DQM Delay:
2831 00:56:37.770241 DQM0 = 112, DQM1 = 100
2832 00:56:37.773608 DQ Delay:
2833 00:56:37.777028 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2834 00:56:37.780160 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =122
2835 00:56:37.783478 DQ8 =92, DQ9 =84, DQ10 =102, DQ11 =92
2836 00:56:37.787061 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2837 00:56:37.787165
2838 00:56:37.787255
2839 00:56:37.793569 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2840 00:56:37.797067 CH0 RK0: MR19=303, MR18=FEFD
2841 00:56:37.803326 CH0_RK0: MR19=0x303, MR18=0xFEFD, DQSOSC=410, MR23=63, INC=39, DEC=26
2842 00:56:37.803434
2843 00:56:37.806592 ----->DramcWriteLeveling(PI) begin...
2844 00:56:37.806702 ==
2845 00:56:37.809964 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 00:56:37.813311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 00:56:37.816644 ==
2848 00:56:37.816747 Write leveling (Byte 0): 32 => 32
2849 00:56:37.819893 Write leveling (Byte 1): 30 => 30
2850 00:56:37.823476 DramcWriteLeveling(PI) end<-----
2851 00:56:37.823581
2852 00:56:37.823670 ==
2853 00:56:37.826564 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 00:56:37.833519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 00:56:37.833641 ==
2856 00:56:37.836778 [Gating] SW mode calibration
2857 00:56:37.843427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 00:56:37.846704 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 00:56:37.853317 0 15 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2860 00:56:37.856820 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 00:56:37.859961 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 00:56:37.863642 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 00:56:37.870271 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 00:56:37.873438 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 00:56:37.876721 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2866 00:56:37.883363 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 1)
2867 00:56:37.886609 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 00:56:37.889937 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 00:56:37.896534 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 00:56:37.899883 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 00:56:37.903415 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 00:56:37.909988 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 00:56:37.913369 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2874 00:56:37.916608 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2875 00:56:37.923501 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2876 00:56:37.926727 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 00:56:37.930172 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 00:56:37.936513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 00:56:37.940094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 00:56:37.943267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 00:56:37.950093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 00:56:37.953427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 00:56:37.956982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 00:56:37.964015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 00:56:37.967088 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 00:56:37.970474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 00:56:37.973542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 00:56:37.980524 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 00:56:37.983526 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 00:56:37.986941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 00:56:37.993490 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 00:56:37.997133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 00:56:38.000578 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 00:56:38.006854 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 00:56:38.010294 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 00:56:38.013619 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 00:56:38.020260 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 00:56:38.023610 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 00:56:38.026829 Total UI for P1: 0, mck2ui 16
2900 00:56:38.030219 best dqsien dly found for B0: ( 1, 3, 24)
2901 00:56:38.033495 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 00:56:38.036860 Total UI for P1: 0, mck2ui 16
2903 00:56:38.040102 best dqsien dly found for B1: ( 1, 3, 28)
2904 00:56:38.043575 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2905 00:56:38.047085 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2906 00:56:38.047443
2907 00:56:38.053750 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2908 00:56:38.056713 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2909 00:56:38.057107 [Gating] SW calibration Done
2910 00:56:38.060258 ==
2911 00:56:38.063225 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 00:56:38.066709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 00:56:38.066906 ==
2914 00:56:38.066997 RX Vref Scan: 0
2915 00:56:38.067062
2916 00:56:38.069951 RX Vref 0 -> 0, step: 1
2917 00:56:38.070138
2918 00:56:38.073148 RX Delay -40 -> 252, step: 8
2919 00:56:38.076383 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2920 00:56:38.079958 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2921 00:56:38.083056 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2922 00:56:38.089673 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2923 00:56:38.093103 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 00:56:38.096485 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2925 00:56:38.099811 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2926 00:56:38.103005 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 00:56:38.109869 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2928 00:56:38.112910 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2929 00:56:38.116333 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2930 00:56:38.119632 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2931 00:56:38.123081 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2932 00:56:38.129702 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2933 00:56:38.133419 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2934 00:56:38.136587 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2935 00:56:38.136690 ==
2936 00:56:38.140019 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 00:56:38.143328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 00:56:38.143450 ==
2939 00:56:38.146433 DQS Delay:
2940 00:56:38.146519 DQS0 = 0, DQS1 = 0
2941 00:56:38.146585 DQM Delay:
2942 00:56:38.149853 DQM0 = 112, DQM1 = 101
2943 00:56:38.149941 DQ Delay:
2944 00:56:38.153401 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2945 00:56:38.156627 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2946 00:56:38.160172 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2947 00:56:38.166704 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2948 00:56:38.166794
2949 00:56:38.166860
2950 00:56:38.166921 ==
2951 00:56:38.170010 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 00:56:38.173059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 00:56:38.173143 ==
2954 00:56:38.173209
2955 00:56:38.173271
2956 00:56:38.176424 TX Vref Scan disable
2957 00:56:38.176508 == TX Byte 0 ==
2958 00:56:38.182991 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2959 00:56:38.186547 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2960 00:56:38.186654 == TX Byte 1 ==
2961 00:56:38.193117 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2962 00:56:38.196361 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2963 00:56:38.196471 ==
2964 00:56:38.199596 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 00:56:38.203052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 00:56:38.203180 ==
2967 00:56:38.216101 TX Vref=22, minBit 2, minWin=26, winSum=426
2968 00:56:38.219153 TX Vref=24, minBit 1, minWin=26, winSum=431
2969 00:56:38.222505 TX Vref=26, minBit 1, minWin=26, winSum=432
2970 00:56:38.225940 TX Vref=28, minBit 1, minWin=27, winSum=439
2971 00:56:38.228826 TX Vref=30, minBit 1, minWin=27, winSum=442
2972 00:56:38.235405 TX Vref=32, minBit 8, minWin=26, winSum=435
2973 00:56:38.238952 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
2974 00:56:38.239048
2975 00:56:38.242310 Final TX Range 1 Vref 30
2976 00:56:38.242394
2977 00:56:38.242460 ==
2978 00:56:38.245399 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 00:56:38.248632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 00:56:38.251994 ==
2981 00:56:38.252077
2982 00:56:38.252142
2983 00:56:38.252204 TX Vref Scan disable
2984 00:56:38.255734 == TX Byte 0 ==
2985 00:56:38.258834 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2986 00:56:38.262214 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2987 00:56:38.265511 == TX Byte 1 ==
2988 00:56:38.269139 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2989 00:56:38.272735 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2990 00:56:38.275740
2991 00:56:38.276132 [DATLAT]
2992 00:56:38.276447 Freq=1200, CH0 RK1
2993 00:56:38.276743
2994 00:56:38.279314 DATLAT Default: 0xd
2995 00:56:38.279708 0, 0xFFFF, sum = 0
2996 00:56:38.282560 1, 0xFFFF, sum = 0
2997 00:56:38.282959 2, 0xFFFF, sum = 0
2998 00:56:38.285745 3, 0xFFFF, sum = 0
2999 00:56:38.289381 4, 0xFFFF, sum = 0
3000 00:56:38.289822 5, 0xFFFF, sum = 0
3001 00:56:38.292332 6, 0xFFFF, sum = 0
3002 00:56:38.292735 7, 0xFFFF, sum = 0
3003 00:56:38.295548 8, 0xFFFF, sum = 0
3004 00:56:38.295834 9, 0xFFFF, sum = 0
3005 00:56:38.298904 10, 0xFFFF, sum = 0
3006 00:56:38.299124 11, 0xFFFF, sum = 0
3007 00:56:38.302397 12, 0x0, sum = 1
3008 00:56:38.302691 13, 0x0, sum = 2
3009 00:56:38.305650 14, 0x0, sum = 3
3010 00:56:38.305869 15, 0x0, sum = 4
3011 00:56:38.306045 best_step = 13
3012 00:56:38.309071
3013 00:56:38.309286 ==
3014 00:56:38.312447 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 00:56:38.315599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 00:56:38.315818 ==
3017 00:56:38.315992 RX Vref Scan: 0
3018 00:56:38.316154
3019 00:56:38.318778 RX Vref 0 -> 0, step: 1
3020 00:56:38.319005
3021 00:56:38.322483 RX Delay -37 -> 252, step: 4
3022 00:56:38.325457 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3023 00:56:38.332226 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3024 00:56:38.335454 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3025 00:56:38.338838 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3026 00:56:38.342132 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 00:56:38.345504 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3028 00:56:38.352209 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3029 00:56:38.355307 iDelay=195, Bit 7, Center 116 (43 ~ 190) 148
3030 00:56:38.358786 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3031 00:56:38.362142 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3032 00:56:38.365455 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3033 00:56:38.372134 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3034 00:56:38.375179 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3035 00:56:38.378473 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3036 00:56:38.381986 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3037 00:56:38.385384 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3038 00:56:38.385462 ==
3039 00:56:38.388902 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 00:56:38.395156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 00:56:38.395243 ==
3042 00:56:38.395310 DQS Delay:
3043 00:56:38.398760 DQS0 = 0, DQS1 = 0
3044 00:56:38.398844 DQM Delay:
3045 00:56:38.401851 DQM0 = 110, DQM1 = 101
3046 00:56:38.401933 DQ Delay:
3047 00:56:38.405072 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3048 00:56:38.408717 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =116
3049 00:56:38.411881 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3050 00:56:38.415376 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3051 00:56:38.415460
3052 00:56:38.415526
3053 00:56:38.425279 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3054 00:56:38.425366 CH0 RK1: MR19=403, MR18=12F9
3055 00:56:38.431809 CH0_RK1: MR19=0x403, MR18=0x12F9, DQSOSC=403, MR23=63, INC=40, DEC=26
3056 00:56:38.435119 [RxdqsGatingPostProcess] freq 1200
3057 00:56:38.442007 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 00:56:38.445384 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 00:56:38.448713 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 00:56:38.451881 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 00:56:38.455172 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 00:56:38.455256 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 00:56:38.458604 best DQS1 dly(2T, 0.5T) = (0, 11)
3064 00:56:38.461826 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 00:56:38.465314 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3066 00:56:38.468521 Pre-setting of DQS Precalculation
3067 00:56:38.475307 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 00:56:38.475393 ==
3069 00:56:38.478774 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 00:56:38.481881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 00:56:38.481966 ==
3072 00:56:38.488716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 00:56:38.495088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3074 00:56:38.501885 [CA 0] Center 37 (7~67) winsize 61
3075 00:56:38.505127 [CA 1] Center 38 (8~68) winsize 61
3076 00:56:38.508424 [CA 2] Center 34 (4~64) winsize 61
3077 00:56:38.512027 [CA 3] Center 33 (3~64) winsize 62
3078 00:56:38.515109 [CA 4] Center 34 (4~64) winsize 61
3079 00:56:38.518632 [CA 5] Center 33 (3~63) winsize 61
3080 00:56:38.518715
3081 00:56:38.521766 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 00:56:38.521849
3083 00:56:38.525304 [CATrainingPosCal] consider 1 rank data
3084 00:56:38.528575 u2DelayCellTimex100 = 270/100 ps
3085 00:56:38.531837 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3086 00:56:38.535433 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3087 00:56:38.542083 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 00:56:38.545619 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 00:56:38.548731 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 00:56:38.552288 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3091 00:56:38.552372
3092 00:56:38.555541 CA PerBit enable=1, Macro0, CA PI delay=33
3093 00:56:38.555625
3094 00:56:38.558725 [CBTSetCACLKResult] CA Dly = 33
3095 00:56:38.558808 CS Dly: 5 (0~36)
3096 00:56:38.558874 ==
3097 00:56:38.562312 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 00:56:38.568985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 00:56:38.569071 ==
3100 00:56:38.572199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 00:56:38.578630 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3102 00:56:38.587455 [CA 0] Center 37 (7~67) winsize 61
3103 00:56:38.591049 [CA 1] Center 37 (7~68) winsize 62
3104 00:56:38.594227 [CA 2] Center 34 (4~65) winsize 62
3105 00:56:38.597586 [CA 3] Center 33 (3~64) winsize 62
3106 00:56:38.600678 [CA 4] Center 34 (4~65) winsize 62
3107 00:56:38.604220 [CA 5] Center 32 (2~63) winsize 62
3108 00:56:38.604304
3109 00:56:38.607530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3110 00:56:38.607614
3111 00:56:38.610816 [CATrainingPosCal] consider 2 rank data
3112 00:56:38.614261 u2DelayCellTimex100 = 270/100 ps
3113 00:56:38.617326 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3114 00:56:38.620737 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 00:56:38.627498 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 00:56:38.630676 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3117 00:56:38.634162 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 00:56:38.637435 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3119 00:56:38.637541
3120 00:56:38.640634 CA PerBit enable=1, Macro0, CA PI delay=33
3121 00:56:38.640718
3122 00:56:38.644164 [CBTSetCACLKResult] CA Dly = 33
3123 00:56:38.644248 CS Dly: 6 (0~39)
3124 00:56:38.644315
3125 00:56:38.647616 ----->DramcWriteLeveling(PI) begin...
3126 00:56:38.650637 ==
3127 00:56:38.654138 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 00:56:38.657371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 00:56:38.657458 ==
3130 00:56:38.660855 Write leveling (Byte 0): 26 => 26
3131 00:56:38.664178 Write leveling (Byte 1): 26 => 26
3132 00:56:38.667541 DramcWriteLeveling(PI) end<-----
3133 00:56:38.667624
3134 00:56:38.667690 ==
3135 00:56:38.670882 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 00:56:38.674118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 00:56:38.674202 ==
3138 00:56:38.677364 [Gating] SW mode calibration
3139 00:56:38.684067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 00:56:38.687408 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 00:56:38.694328 0 15 0 | B1->B0 | 3030 3030 | 1 1 | (1 1) (0 0)
3142 00:56:38.697448 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 00:56:38.700997 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 00:56:38.707738 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 00:56:38.710777 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 00:56:38.714058 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 00:56:38.720749 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 00:56:38.724005 0 15 28 | B1->B0 | 2c2c 2d2d | 1 0 | (1 0) (0 0)
3149 00:56:38.727639 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3150 00:56:38.733826 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 00:56:38.737337 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 00:56:38.740475 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 00:56:38.747368 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 00:56:38.750532 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 00:56:38.753806 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3156 00:56:38.760574 1 0 28 | B1->B0 | 4040 3f3f | 0 0 | (0 0) (0 0)
3157 00:56:38.763755 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3158 00:56:38.767303 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 00:56:38.773849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 00:56:38.777316 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 00:56:38.780414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 00:56:38.787082 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 00:56:38.790547 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 00:56:38.793865 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 00:56:38.797357 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 00:56:38.803941 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 00:56:38.807200 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 00:56:38.810646 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 00:56:38.817310 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 00:56:38.820471 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 00:56:38.823862 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 00:56:38.830405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 00:56:38.833817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 00:56:38.837287 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 00:56:38.843794 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 00:56:38.847142 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 00:56:38.850705 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 00:56:38.857082 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 00:56:38.860477 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 00:56:38.863692 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 00:56:38.870882 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 00:56:38.870995 Total UI for P1: 0, mck2ui 16
3183 00:56:38.877024 best dqsien dly found for B0: ( 1, 3, 28)
3184 00:56:38.877111 Total UI for P1: 0, mck2ui 16
3185 00:56:38.880598 best dqsien dly found for B1: ( 1, 3, 28)
3186 00:56:38.887162 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3187 00:56:38.890657 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3188 00:56:38.890743
3189 00:56:38.893768 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3190 00:56:38.897336 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 00:56:38.900773 [Gating] SW calibration Done
3192 00:56:38.900870 ==
3193 00:56:38.903785 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 00:56:38.907336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 00:56:38.907423 ==
3196 00:56:38.907511 RX Vref Scan: 0
3197 00:56:38.910714
3198 00:56:38.910799 RX Vref 0 -> 0, step: 1
3199 00:56:38.910888
3200 00:56:38.913990 RX Delay -40 -> 252, step: 8
3201 00:56:38.917245 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3202 00:56:38.920784 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3203 00:56:38.927466 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3204 00:56:38.930599 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3205 00:56:38.933939 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 00:56:38.937402 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3207 00:56:38.940789 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3208 00:56:38.947335 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3209 00:56:38.950821 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3210 00:56:38.953880 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3211 00:56:38.957251 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3212 00:56:38.960682 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3213 00:56:38.967526 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3214 00:56:38.970613 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3215 00:56:38.974124 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3216 00:56:38.977423 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3217 00:56:38.977562 ==
3218 00:56:38.980586 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 00:56:38.984019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 00:56:38.987196 ==
3221 00:56:38.987283 DQS Delay:
3222 00:56:38.987370 DQS0 = 0, DQS1 = 0
3223 00:56:38.990736 DQM Delay:
3224 00:56:38.990822 DQM0 = 112, DQM1 = 106
3225 00:56:38.993968 DQ Delay:
3226 00:56:38.997446 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3227 00:56:39.000515 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3228 00:56:39.003839 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3229 00:56:39.007101 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3230 00:56:39.007187
3231 00:56:39.007274
3232 00:56:39.007357 ==
3233 00:56:39.010687 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 00:56:39.013998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 00:56:39.014085 ==
3236 00:56:39.014173
3237 00:56:39.014255
3238 00:56:39.017321 TX Vref Scan disable
3239 00:56:39.020488 == TX Byte 0 ==
3240 00:56:39.023906 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3241 00:56:39.027532 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3242 00:56:39.030661 == TX Byte 1 ==
3243 00:56:39.034062 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3244 00:56:39.037428 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3245 00:56:39.037525 ==
3246 00:56:39.040753 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 00:56:39.044128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 00:56:39.047290 ==
3249 00:56:39.057316 TX Vref=22, minBit 9, minWin=24, winSum=406
3250 00:56:39.060864 TX Vref=24, minBit 9, minWin=24, winSum=406
3251 00:56:39.063991 TX Vref=26, minBit 10, minWin=24, winSum=415
3252 00:56:39.067385 TX Vref=28, minBit 10, minWin=24, winSum=421
3253 00:56:39.070840 TX Vref=30, minBit 9, minWin=24, winSum=421
3254 00:56:39.077596 TX Vref=32, minBit 9, minWin=24, winSum=416
3255 00:56:39.080968 [TxChooseVref] Worse bit 10, Min win 24, Win sum 421, Final Vref 28
3256 00:56:39.081056
3257 00:56:39.083952 Final TX Range 1 Vref 28
3258 00:56:39.084039
3259 00:56:39.084126 ==
3260 00:56:39.087378 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 00:56:39.090934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 00:56:39.091021 ==
3263 00:56:39.094109
3264 00:56:39.094195
3265 00:56:39.094282 TX Vref Scan disable
3266 00:56:39.097466 == TX Byte 0 ==
3267 00:56:39.100587 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3268 00:56:39.103984 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3269 00:56:39.107278 == TX Byte 1 ==
3270 00:56:39.110708 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 00:56:39.113905 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 00:56:39.117336
3273 00:56:39.117427 [DATLAT]
3274 00:56:39.117527 Freq=1200, CH1 RK0
3275 00:56:39.117611
3276 00:56:39.120582 DATLAT Default: 0xd
3277 00:56:39.120668 0, 0xFFFF, sum = 0
3278 00:56:39.123994 1, 0xFFFF, sum = 0
3279 00:56:39.124081 2, 0xFFFF, sum = 0
3280 00:56:39.127553 3, 0xFFFF, sum = 0
3281 00:56:39.127640 4, 0xFFFF, sum = 0
3282 00:56:39.130675 5, 0xFFFF, sum = 0
3283 00:56:39.133985 6, 0xFFFF, sum = 0
3284 00:56:39.134098 7, 0xFFFF, sum = 0
3285 00:56:39.137281 8, 0xFFFF, sum = 0
3286 00:56:39.137368 9, 0xFFFF, sum = 0
3287 00:56:39.140815 10, 0xFFFF, sum = 0
3288 00:56:39.140901 11, 0xFFFF, sum = 0
3289 00:56:39.144090 12, 0x0, sum = 1
3290 00:56:39.144181 13, 0x0, sum = 2
3291 00:56:39.147473 14, 0x0, sum = 3
3292 00:56:39.147560 15, 0x0, sum = 4
3293 00:56:39.147662 best_step = 13
3294 00:56:39.147761
3295 00:56:39.150803 ==
3296 00:56:39.154024 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 00:56:39.157306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 00:56:39.157389 ==
3299 00:56:39.157455 RX Vref Scan: 1
3300 00:56:39.157528
3301 00:56:39.160835 Set Vref Range= 32 -> 127
3302 00:56:39.160921
3303 00:56:39.163957 RX Vref 32 -> 127, step: 1
3304 00:56:39.164079
3305 00:56:39.167392 RX Delay -21 -> 252, step: 4
3306 00:56:39.167505
3307 00:56:39.170523 Set Vref, RX VrefLevel [Byte0]: 32
3308 00:56:39.173836 [Byte1]: 32
3309 00:56:39.173918
3310 00:56:39.177270 Set Vref, RX VrefLevel [Byte0]: 33
3311 00:56:39.180737 [Byte1]: 33
3312 00:56:39.180845
3313 00:56:39.183844 Set Vref, RX VrefLevel [Byte0]: 34
3314 00:56:39.187387 [Byte1]: 34
3315 00:56:39.191910
3316 00:56:39.191991 Set Vref, RX VrefLevel [Byte0]: 35
3317 00:56:39.195167 [Byte1]: 35
3318 00:56:39.199709
3319 00:56:39.199791 Set Vref, RX VrefLevel [Byte0]: 36
3320 00:56:39.203020 [Byte1]: 36
3321 00:56:39.207598
3322 00:56:39.207679 Set Vref, RX VrefLevel [Byte0]: 37
3323 00:56:39.210978 [Byte1]: 37
3324 00:56:39.215602
3325 00:56:39.215684 Set Vref, RX VrefLevel [Byte0]: 38
3326 00:56:39.218650 [Byte1]: 38
3327 00:56:39.223294
3328 00:56:39.223376 Set Vref, RX VrefLevel [Byte0]: 39
3329 00:56:39.226573 [Byte1]: 39
3330 00:56:39.231430
3331 00:56:39.231512 Set Vref, RX VrefLevel [Byte0]: 40
3332 00:56:39.234543 [Byte1]: 40
3333 00:56:39.239309
3334 00:56:39.239391 Set Vref, RX VrefLevel [Byte0]: 41
3335 00:56:39.242445 [Byte1]: 41
3336 00:56:39.247235
3337 00:56:39.247319 Set Vref, RX VrefLevel [Byte0]: 42
3338 00:56:39.250343 [Byte1]: 42
3339 00:56:39.254962
3340 00:56:39.255044 Set Vref, RX VrefLevel [Byte0]: 43
3341 00:56:39.258547 [Byte1]: 43
3342 00:56:39.263049
3343 00:56:39.263131 Set Vref, RX VrefLevel [Byte0]: 44
3344 00:56:39.266124 [Byte1]: 44
3345 00:56:39.270736
3346 00:56:39.270818 Set Vref, RX VrefLevel [Byte0]: 45
3347 00:56:39.274253 [Byte1]: 45
3348 00:56:39.278925
3349 00:56:39.279006 Set Vref, RX VrefLevel [Byte0]: 46
3350 00:56:39.281956 [Byte1]: 46
3351 00:56:39.286764
3352 00:56:39.286862 Set Vref, RX VrefLevel [Byte0]: 47
3353 00:56:39.290039 [Byte1]: 47
3354 00:56:39.294573
3355 00:56:39.294654 Set Vref, RX VrefLevel [Byte0]: 48
3356 00:56:39.297821 [Byte1]: 48
3357 00:56:39.302597
3358 00:56:39.302679 Set Vref, RX VrefLevel [Byte0]: 49
3359 00:56:39.305761 [Byte1]: 49
3360 00:56:39.310593
3361 00:56:39.310676 Set Vref, RX VrefLevel [Byte0]: 50
3362 00:56:39.313771 [Byte1]: 50
3363 00:56:39.318525
3364 00:56:39.318606 Set Vref, RX VrefLevel [Byte0]: 51
3365 00:56:39.321857 [Byte1]: 51
3366 00:56:39.326309
3367 00:56:39.326392 Set Vref, RX VrefLevel [Byte0]: 52
3368 00:56:39.329664 [Byte1]: 52
3369 00:56:39.334288
3370 00:56:39.334374 Set Vref, RX VrefLevel [Byte0]: 53
3371 00:56:39.337697 [Byte1]: 53
3372 00:56:39.342314
3373 00:56:39.342426 Set Vref, RX VrefLevel [Byte0]: 54
3374 00:56:39.345445 [Byte1]: 54
3375 00:56:39.350239
3376 00:56:39.350326 Set Vref, RX VrefLevel [Byte0]: 55
3377 00:56:39.353420 [Byte1]: 55
3378 00:56:39.357970
3379 00:56:39.358071 Set Vref, RX VrefLevel [Byte0]: 56
3380 00:56:39.361382 [Byte1]: 56
3381 00:56:39.365893
3382 00:56:39.365976 Set Vref, RX VrefLevel [Byte0]: 57
3383 00:56:39.369405 [Byte1]: 57
3384 00:56:39.374051
3385 00:56:39.374133 Set Vref, RX VrefLevel [Byte0]: 58
3386 00:56:39.377605 [Byte1]: 58
3387 00:56:39.382383
3388 00:56:39.382958 Set Vref, RX VrefLevel [Byte0]: 59
3389 00:56:39.385545 [Byte1]: 59
3390 00:56:39.390290
3391 00:56:39.390995 Set Vref, RX VrefLevel [Byte0]: 60
3392 00:56:39.393317 [Byte1]: 60
3393 00:56:39.398307
3394 00:56:39.398769 Set Vref, RX VrefLevel [Byte0]: 61
3395 00:56:39.401250 [Byte1]: 61
3396 00:56:39.406108
3397 00:56:39.406514 Set Vref, RX VrefLevel [Byte0]: 62
3398 00:56:39.409407 [Byte1]: 62
3399 00:56:39.414485
3400 00:56:39.415018 Set Vref, RX VrefLevel [Byte0]: 63
3401 00:56:39.417578 [Byte1]: 63
3402 00:56:39.421905
3403 00:56:39.422443 Set Vref, RX VrefLevel [Byte0]: 64
3404 00:56:39.425708 [Byte1]: 64
3405 00:56:39.429856
3406 00:56:39.430395 Set Vref, RX VrefLevel [Byte0]: 65
3407 00:56:39.432975 [Byte1]: 65
3408 00:56:39.437718
3409 00:56:39.438245 Final RX Vref Byte 0 = 57 to rank0
3410 00:56:39.441328 Final RX Vref Byte 1 = 49 to rank0
3411 00:56:39.444619 Final RX Vref Byte 0 = 57 to rank1
3412 00:56:39.448172 Final RX Vref Byte 1 = 49 to rank1==
3413 00:56:39.451006 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 00:56:39.457692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 00:56:39.458228 ==
3416 00:56:39.458682 DQS Delay:
3417 00:56:39.459110 DQS0 = 0, DQS1 = 0
3418 00:56:39.460988 DQM Delay:
3419 00:56:39.461466 DQM0 = 114, DQM1 = 105
3420 00:56:39.464105 DQ Delay:
3421 00:56:39.467805 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3422 00:56:39.471063 DQ4 =112, DQ5 =120, DQ6 =126, DQ7 =112
3423 00:56:39.474360 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3424 00:56:39.477591 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3425 00:56:39.478032
3426 00:56:39.478474
3427 00:56:39.487873 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3428 00:56:39.488415 CH1 RK0: MR19=303, MR18=EDF4
3429 00:56:39.494376 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3430 00:56:39.494920
3431 00:56:39.497623 ----->DramcWriteLeveling(PI) begin...
3432 00:56:39.498158 ==
3433 00:56:39.500920 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 00:56:39.507401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 00:56:39.507925 ==
3436 00:56:39.510658 Write leveling (Byte 0): 26 => 26
3437 00:56:39.511104 Write leveling (Byte 1): 27 => 27
3438 00:56:39.514139 DramcWriteLeveling(PI) end<-----
3439 00:56:39.514581
3440 00:56:39.515092 ==
3441 00:56:39.517528 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 00:56:39.524181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 00:56:39.524736 ==
3444 00:56:39.527244 [Gating] SW mode calibration
3445 00:56:39.534149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 00:56:39.537572 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 00:56:39.544281 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 00:56:39.547818 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 00:56:39.551256 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 00:56:39.554422 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 00:56:39.561074 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 00:56:39.564087 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 00:56:39.567447 0 15 24 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 0)
3454 00:56:39.574153 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3455 00:56:39.577268 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 00:56:39.580717 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 00:56:39.587753 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 00:56:39.590795 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 00:56:39.594283 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 00:56:39.601107 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3461 00:56:39.604456 1 0 24 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
3462 00:56:39.607414 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3463 00:56:39.614017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 00:56:39.617225 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 00:56:39.621144 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 00:56:39.627630 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 00:56:39.630659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 00:56:39.633919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 00:56:39.640952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3470 00:56:39.644234 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3471 00:56:39.647566 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 00:56:39.654063 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 00:56:39.657264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 00:56:39.660849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 00:56:39.667142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 00:56:39.670654 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 00:56:39.673569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 00:56:39.681048 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 00:56:39.683735 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 00:56:39.686958 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 00:56:39.693631 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 00:56:39.697056 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 00:56:39.700265 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 00:56:39.703720 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 00:56:39.709926 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3486 00:56:39.713365 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3487 00:56:39.716532 Total UI for P1: 0, mck2ui 16
3488 00:56:39.720084 best dqsien dly found for B0: ( 1, 3, 24)
3489 00:56:39.723388 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 00:56:39.726511 Total UI for P1: 0, mck2ui 16
3491 00:56:39.729878 best dqsien dly found for B1: ( 1, 3, 26)
3492 00:56:39.733166 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3493 00:56:39.740143 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3494 00:56:39.740668
3495 00:56:39.743536 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3496 00:56:39.746838 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3497 00:56:39.749798 [Gating] SW calibration Done
3498 00:56:39.750244 ==
3499 00:56:39.753874 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 00:56:39.756692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 00:56:39.757222 ==
3502 00:56:39.757629 RX Vref Scan: 0
3503 00:56:39.759888
3504 00:56:39.760304 RX Vref 0 -> 0, step: 1
3505 00:56:39.760637
3506 00:56:39.763407 RX Delay -40 -> 252, step: 8
3507 00:56:39.766415 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3508 00:56:39.769615 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3509 00:56:39.776749 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3510 00:56:39.780272 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3511 00:56:39.783171 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3512 00:56:39.786619 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3513 00:56:39.789680 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3514 00:56:39.796622 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3515 00:56:39.799770 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3516 00:56:39.803302 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3517 00:56:39.806441 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3518 00:56:39.809805 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3519 00:56:39.815929 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3520 00:56:39.819968 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3521 00:56:39.823274 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3522 00:56:39.826417 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3523 00:56:39.827134 ==
3524 00:56:39.829234 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 00:56:39.836364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 00:56:39.836890 ==
3527 00:56:39.837234 DQS Delay:
3528 00:56:39.839399 DQS0 = 0, DQS1 = 0
3529 00:56:39.839916 DQM Delay:
3530 00:56:39.842754 DQM0 = 109, DQM1 = 107
3531 00:56:39.843302 DQ Delay:
3532 00:56:39.845935 DQ0 =111, DQ1 =107, DQ2 =99, DQ3 =107
3533 00:56:39.849027 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3534 00:56:39.852442 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3535 00:56:39.856010 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3536 00:56:39.856536
3537 00:56:39.856878
3538 00:56:39.857200 ==
3539 00:56:39.859200 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 00:56:39.862236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 00:56:39.865848 ==
3542 00:56:39.866386
3543 00:56:39.866739
3544 00:56:39.867056 TX Vref Scan disable
3545 00:56:39.868763 == TX Byte 0 ==
3546 00:56:39.872313 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3547 00:56:39.875792 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3548 00:56:39.878978 == TX Byte 1 ==
3549 00:56:39.882038 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3550 00:56:39.885985 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3551 00:56:39.889081 ==
3552 00:56:39.892343 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 00:56:39.895581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 00:56:39.896113 ==
3555 00:56:39.906650 TX Vref=22, minBit 9, minWin=25, winSum=417
3556 00:56:39.909999 TX Vref=24, minBit 0, minWin=26, winSum=427
3557 00:56:39.913088 TX Vref=26, minBit 8, minWin=26, winSum=429
3558 00:56:39.916945 TX Vref=28, minBit 8, minWin=26, winSum=430
3559 00:56:39.920063 TX Vref=30, minBit 9, minWin=26, winSum=434
3560 00:56:39.923066 TX Vref=32, minBit 1, minWin=26, winSum=427
3561 00:56:39.929812 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3562 00:56:39.930373
3563 00:56:39.933197 Final TX Range 1 Vref 30
3564 00:56:39.933655
3565 00:56:39.933998 ==
3566 00:56:39.936499 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 00:56:39.939698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 00:56:39.940240 ==
3569 00:56:39.943428
3570 00:56:39.943947
3571 00:56:39.944291 TX Vref Scan disable
3572 00:56:39.946386 == TX Byte 0 ==
3573 00:56:39.950096 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3574 00:56:39.953320 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3575 00:56:39.956430 == TX Byte 1 ==
3576 00:56:39.960045 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3577 00:56:39.966250 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3578 00:56:39.966684
3579 00:56:39.967024 [DATLAT]
3580 00:56:39.967342 Freq=1200, CH1 RK1
3581 00:56:39.967653
3582 00:56:39.969550 DATLAT Default: 0xd
3583 00:56:39.969981 0, 0xFFFF, sum = 0
3584 00:56:39.972832 1, 0xFFFF, sum = 0
3585 00:56:39.976111 2, 0xFFFF, sum = 0
3586 00:56:39.976543 3, 0xFFFF, sum = 0
3587 00:56:39.979506 4, 0xFFFF, sum = 0
3588 00:56:39.979964 5, 0xFFFF, sum = 0
3589 00:56:39.982727 6, 0xFFFF, sum = 0
3590 00:56:39.983298 7, 0xFFFF, sum = 0
3591 00:56:39.985844 8, 0xFFFF, sum = 0
3592 00:56:39.986276 9, 0xFFFF, sum = 0
3593 00:56:39.989545 10, 0xFFFF, sum = 0
3594 00:56:39.989982 11, 0xFFFF, sum = 0
3595 00:56:39.993139 12, 0x0, sum = 1
3596 00:56:39.993707 13, 0x0, sum = 2
3597 00:56:39.996299 14, 0x0, sum = 3
3598 00:56:39.996822 15, 0x0, sum = 4
3599 00:56:39.999544 best_step = 13
3600 00:56:40.000072
3601 00:56:40.000415 ==
3602 00:56:40.003024 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 00:56:40.006080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 00:56:40.006619 ==
3605 00:56:40.006965 RX Vref Scan: 0
3606 00:56:40.009140
3607 00:56:40.009603 RX Vref 0 -> 0, step: 1
3608 00:56:40.009952
3609 00:56:40.012370 RX Delay -21 -> 252, step: 4
3610 00:56:40.019351 iDelay=195, Bit 0, Center 112 (39 ~ 186) 148
3611 00:56:40.022660 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3612 00:56:40.025659 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3613 00:56:40.029255 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3614 00:56:40.032262 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3615 00:56:40.039058 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3616 00:56:40.042226 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3617 00:56:40.045593 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3618 00:56:40.048567 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3619 00:56:40.052008 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3620 00:56:40.058836 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3621 00:56:40.062023 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3622 00:56:40.065177 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3623 00:56:40.068765 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3624 00:56:40.071926 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3625 00:56:40.078600 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3626 00:56:40.079028 ==
3627 00:56:40.082051 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 00:56:40.085363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 00:56:40.085952 ==
3630 00:56:40.086304 DQS Delay:
3631 00:56:40.088513 DQS0 = 0, DQS1 = 0
3632 00:56:40.088938 DQM Delay:
3633 00:56:40.092004 DQM0 = 111, DQM1 = 109
3634 00:56:40.092524 DQ Delay:
3635 00:56:40.095242 DQ0 =112, DQ1 =110, DQ2 =102, DQ3 =108
3636 00:56:40.098800 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =110
3637 00:56:40.102129 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3638 00:56:40.105189 DQ12 =116, DQ13 =116, DQ14 =118, DQ15 =116
3639 00:56:40.105749
3640 00:56:40.108482
3641 00:56:40.114993 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa09, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3642 00:56:40.118038 CH1 RK1: MR19=304, MR18=FA09
3643 00:56:40.125131 CH1_RK1: MR19=0x304, MR18=0xFA09, DQSOSC=406, MR23=63, INC=39, DEC=26
3644 00:56:40.128622 [RxdqsGatingPostProcess] freq 1200
3645 00:56:40.131871 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 00:56:40.134773 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 00:56:40.138346 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 00:56:40.141751 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 00:56:40.144857 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 00:56:40.148462 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 00:56:40.151648 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 00:56:40.155113 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 00:56:40.158328 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 00:56:40.161578 Pre-setting of DQS Precalculation
3655 00:56:40.164960 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 00:56:40.171514 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 00:56:40.181161 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 00:56:40.181706
3659 00:56:40.182054
3660 00:56:40.184516 [Calibration Summary] 2400 Mbps
3661 00:56:40.184944 CH 0, Rank 0
3662 00:56:40.187855 SW Impedance : PASS
3663 00:56:40.188284 DUTY Scan : NO K
3664 00:56:40.191111 ZQ Calibration : PASS
3665 00:56:40.194259 Jitter Meter : NO K
3666 00:56:40.194960 CBT Training : PASS
3667 00:56:40.197813 Write leveling : PASS
3668 00:56:40.198240 RX DQS gating : PASS
3669 00:56:40.201430 RX DQ/DQS(RDDQC) : PASS
3670 00:56:40.204597 TX DQ/DQS : PASS
3671 00:56:40.205119 RX DATLAT : PASS
3672 00:56:40.207381 RX DQ/DQS(Engine): PASS
3673 00:56:40.211090 TX OE : NO K
3674 00:56:40.211567 All Pass.
3675 00:56:40.212000
3676 00:56:40.212330 CH 0, Rank 1
3677 00:56:40.214167 SW Impedance : PASS
3678 00:56:40.218103 DUTY Scan : NO K
3679 00:56:40.218629 ZQ Calibration : PASS
3680 00:56:40.221131 Jitter Meter : NO K
3681 00:56:40.224097 CBT Training : PASS
3682 00:56:40.224524 Write leveling : PASS
3683 00:56:40.227858 RX DQS gating : PASS
3684 00:56:40.230950 RX DQ/DQS(RDDQC) : PASS
3685 00:56:40.231380 TX DQ/DQS : PASS
3686 00:56:40.234388 RX DATLAT : PASS
3687 00:56:40.237739 RX DQ/DQS(Engine): PASS
3688 00:56:40.238260 TX OE : NO K
3689 00:56:40.241003 All Pass.
3690 00:56:40.241424
3691 00:56:40.241792 CH 1, Rank 0
3692 00:56:40.244370 SW Impedance : PASS
3693 00:56:40.244894 DUTY Scan : NO K
3694 00:56:40.247156 ZQ Calibration : PASS
3695 00:56:40.250669 Jitter Meter : NO K
3696 00:56:40.251093 CBT Training : PASS
3697 00:56:40.254403 Write leveling : PASS
3698 00:56:40.257230 RX DQS gating : PASS
3699 00:56:40.257687 RX DQ/DQS(RDDQC) : PASS
3700 00:56:40.260836 TX DQ/DQS : PASS
3701 00:56:40.261362 RX DATLAT : PASS
3702 00:56:40.263967 RX DQ/DQS(Engine): PASS
3703 00:56:40.267423 TX OE : NO K
3704 00:56:40.267945 All Pass.
3705 00:56:40.268286
3706 00:56:40.268601 CH 1, Rank 1
3707 00:56:40.270662 SW Impedance : PASS
3708 00:56:40.273923 DUTY Scan : NO K
3709 00:56:40.274348 ZQ Calibration : PASS
3710 00:56:40.277141 Jitter Meter : NO K
3711 00:56:40.280556 CBT Training : PASS
3712 00:56:40.280984 Write leveling : PASS
3713 00:56:40.284263 RX DQS gating : PASS
3714 00:56:40.287370 RX DQ/DQS(RDDQC) : PASS
3715 00:56:40.287895 TX DQ/DQS : PASS
3716 00:56:40.290460 RX DATLAT : PASS
3717 00:56:40.293816 RX DQ/DQS(Engine): PASS
3718 00:56:40.294245 TX OE : NO K
3719 00:56:40.296959 All Pass.
3720 00:56:40.297520
3721 00:56:40.298045 DramC Write-DBI off
3722 00:56:40.300163 PER_BANK_REFRESH: Hybrid Mode
3723 00:56:40.300591 TX_TRACKING: ON
3724 00:56:40.310341 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 00:56:40.313908 [FAST_K] Save calibration result to emmc
3726 00:56:40.317046 dramc_set_vcore_voltage set vcore to 650000
3727 00:56:40.320318 Read voltage for 600, 5
3728 00:56:40.320839 Vio18 = 0
3729 00:56:40.324128 Vcore = 650000
3730 00:56:40.324649 Vdram = 0
3731 00:56:40.324990 Vddq = 0
3732 00:56:40.325307 Vmddr = 0
3733 00:56:40.330423 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 00:56:40.337385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 00:56:40.338099 MEM_TYPE=3, freq_sel=19
3736 00:56:40.340031 sv_algorithm_assistance_LP4_1600
3737 00:56:40.343707 ============ PULL DRAM RESETB DOWN ============
3738 00:56:40.350272 ========== PULL DRAM RESETB DOWN end =========
3739 00:56:40.353930 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 00:56:40.356917 ===================================
3741 00:56:40.360351 LPDDR4 DRAM CONFIGURATION
3742 00:56:40.363455 ===================================
3743 00:56:40.363885 EX_ROW_EN[0] = 0x0
3744 00:56:40.367260 EX_ROW_EN[1] = 0x0
3745 00:56:40.367781 LP4Y_EN = 0x0
3746 00:56:40.370129 WORK_FSP = 0x0
3747 00:56:40.373846 WL = 0x2
3748 00:56:40.374366 RL = 0x2
3749 00:56:40.377083 BL = 0x2
3750 00:56:40.377641 RPST = 0x0
3751 00:56:40.380039 RD_PRE = 0x0
3752 00:56:40.380618 WR_PRE = 0x1
3753 00:56:40.383472 WR_PST = 0x0
3754 00:56:40.383896 DBI_WR = 0x0
3755 00:56:40.386940 DBI_RD = 0x0
3756 00:56:40.387461 OTF = 0x1
3757 00:56:40.390172 ===================================
3758 00:56:40.393834 ===================================
3759 00:56:40.397030 ANA top config
3760 00:56:40.399962 ===================================
3761 00:56:40.400392 DLL_ASYNC_EN = 0
3762 00:56:40.403526 ALL_SLAVE_EN = 1
3763 00:56:40.406948 NEW_RANK_MODE = 1
3764 00:56:40.410083 DLL_IDLE_MODE = 1
3765 00:56:40.412935 LP45_APHY_COMB_EN = 1
3766 00:56:40.413360 TX_ODT_DIS = 1
3767 00:56:40.416472 NEW_8X_MODE = 1
3768 00:56:40.420255 ===================================
3769 00:56:40.423435 ===================================
3770 00:56:40.426665 data_rate = 1200
3771 00:56:40.429848 CKR = 1
3772 00:56:40.432704 DQ_P2S_RATIO = 8
3773 00:56:40.436157 ===================================
3774 00:56:40.436658 CA_P2S_RATIO = 8
3775 00:56:40.439742 DQ_CA_OPEN = 0
3776 00:56:40.443004 DQ_SEMI_OPEN = 0
3777 00:56:40.446025 CA_SEMI_OPEN = 0
3778 00:56:40.449621 CA_FULL_RATE = 0
3779 00:56:40.452776 DQ_CKDIV4_EN = 1
3780 00:56:40.456064 CA_CKDIV4_EN = 1
3781 00:56:40.456517 CA_PREDIV_EN = 0
3782 00:56:40.459700 PH8_DLY = 0
3783 00:56:40.462408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 00:56:40.466056 DQ_AAMCK_DIV = 4
3785 00:56:40.469170 CA_AAMCK_DIV = 4
3786 00:56:40.472496 CA_ADMCK_DIV = 4
3787 00:56:40.473004 DQ_TRACK_CA_EN = 0
3788 00:56:40.475792 CA_PICK = 600
3789 00:56:40.479286 CA_MCKIO = 600
3790 00:56:40.482887 MCKIO_SEMI = 0
3791 00:56:40.485971 PLL_FREQ = 2288
3792 00:56:40.489142 DQ_UI_PI_RATIO = 32
3793 00:56:40.492643 CA_UI_PI_RATIO = 0
3794 00:56:40.495593 ===================================
3795 00:56:40.498964 ===================================
3796 00:56:40.499491 memory_type:LPDDR4
3797 00:56:40.502155 GP_NUM : 10
3798 00:56:40.505314 SRAM_EN : 1
3799 00:56:40.505739 MD32_EN : 0
3800 00:56:40.509007 ===================================
3801 00:56:40.512256 [ANA_INIT] >>>>>>>>>>>>>>
3802 00:56:40.515670 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 00:56:40.518806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 00:56:40.522248 ===================================
3805 00:56:40.525683 data_rate = 1200,PCW = 0X5800
3806 00:56:40.528656 ===================================
3807 00:56:40.532190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 00:56:40.535437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 00:56:40.542063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 00:56:40.545930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 00:56:40.549274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 00:56:40.552485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 00:56:40.555137 [ANA_INIT] flow start
3814 00:56:40.558976 [ANA_INIT] PLL >>>>>>>>
3815 00:56:40.559496 [ANA_INIT] PLL <<<<<<<<
3816 00:56:40.562036 [ANA_INIT] MIDPI >>>>>>>>
3817 00:56:40.565123 [ANA_INIT] MIDPI <<<<<<<<
3818 00:56:40.565593 [ANA_INIT] DLL >>>>>>>>
3819 00:56:40.568564 [ANA_INIT] flow end
3820 00:56:40.571685 ============ LP4 DIFF to SE enter ============
3821 00:56:40.578646 ============ LP4 DIFF to SE exit ============
3822 00:56:40.579189 [ANA_INIT] <<<<<<<<<<<<<
3823 00:56:40.581843 [Flow] Enable top DCM control >>>>>
3824 00:56:40.584909 [Flow] Enable top DCM control <<<<<
3825 00:56:40.588787 Enable DLL master slave shuffle
3826 00:56:40.595373 ==============================================================
3827 00:56:40.595906 Gating Mode config
3828 00:56:40.601997 ==============================================================
3829 00:56:40.605146 Config description:
3830 00:56:40.614606 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 00:56:40.621907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 00:56:40.624846 SELPH_MODE 0: By rank 1: By Phase
3833 00:56:40.631344 ==============================================================
3834 00:56:40.634561 GAT_TRACK_EN = 1
3835 00:56:40.635001 RX_GATING_MODE = 2
3836 00:56:40.637864 RX_GATING_TRACK_MODE = 2
3837 00:56:40.641209 SELPH_MODE = 1
3838 00:56:40.644395 PICG_EARLY_EN = 1
3839 00:56:40.648107 VALID_LAT_VALUE = 1
3840 00:56:40.654390 ==============================================================
3841 00:56:40.657816 Enter into Gating configuration >>>>
3842 00:56:40.661252 Exit from Gating configuration <<<<
3843 00:56:40.664369 Enter into DVFS_PRE_config >>>>>
3844 00:56:40.674312 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 00:56:40.677603 Exit from DVFS_PRE_config <<<<<
3846 00:56:40.681105 Enter into PICG configuration >>>>
3847 00:56:40.684291 Exit from PICG configuration <<<<
3848 00:56:40.687849 [RX_INPUT] configuration >>>>>
3849 00:56:40.691146 [RX_INPUT] configuration <<<<<
3850 00:56:40.694105 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 00:56:40.700944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 00:56:40.707646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 00:56:40.713830 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 00:56:40.717376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 00:56:40.723710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 00:56:40.727235 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 00:56:40.733996 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 00:56:40.737520 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 00:56:40.740626 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 00:56:40.743687 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 00:56:40.750192 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 00:56:40.753905 ===================================
3863 00:56:40.756916 LPDDR4 DRAM CONFIGURATION
3864 00:56:40.760046 ===================================
3865 00:56:40.760471 EX_ROW_EN[0] = 0x0
3866 00:56:40.763427 EX_ROW_EN[1] = 0x0
3867 00:56:40.763848 LP4Y_EN = 0x0
3868 00:56:40.767292 WORK_FSP = 0x0
3869 00:56:40.767821 WL = 0x2
3870 00:56:40.770141 RL = 0x2
3871 00:56:40.770701 BL = 0x2
3872 00:56:40.773157 RPST = 0x0
3873 00:56:40.773935 RD_PRE = 0x0
3874 00:56:40.776940 WR_PRE = 0x1
3875 00:56:40.777581 WR_PST = 0x0
3876 00:56:40.779890 DBI_WR = 0x0
3877 00:56:40.780591 DBI_RD = 0x0
3878 00:56:40.783205 OTF = 0x1
3879 00:56:40.786580 ===================================
3880 00:56:40.789933 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 00:56:40.793166 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 00:56:40.799715 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 00:56:40.802845 ===================================
3884 00:56:40.806769 LPDDR4 DRAM CONFIGURATION
3885 00:56:40.809732 ===================================
3886 00:56:40.810166 EX_ROW_EN[0] = 0x10
3887 00:56:40.812913 EX_ROW_EN[1] = 0x0
3888 00:56:40.813346 LP4Y_EN = 0x0
3889 00:56:40.816608 WORK_FSP = 0x0
3890 00:56:40.817132 WL = 0x2
3891 00:56:40.820162 RL = 0x2
3892 00:56:40.820695 BL = 0x2
3893 00:56:40.823176 RPST = 0x0
3894 00:56:40.823600 RD_PRE = 0x0
3895 00:56:40.826423 WR_PRE = 0x1
3896 00:56:40.826956 WR_PST = 0x0
3897 00:56:40.829691 DBI_WR = 0x0
3898 00:56:40.830120 DBI_RD = 0x0
3899 00:56:40.832812 OTF = 0x1
3900 00:56:40.836192 ===================================
3901 00:56:40.843000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 00:56:40.846414 nWR fixed to 30
3903 00:56:40.849668 [ModeRegInit_LP4] CH0 RK0
3904 00:56:40.850213 [ModeRegInit_LP4] CH0 RK1
3905 00:56:40.853280 [ModeRegInit_LP4] CH1 RK0
3906 00:56:40.856167 [ModeRegInit_LP4] CH1 RK1
3907 00:56:40.856592 match AC timing 17
3908 00:56:40.862788 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 00:56:40.865959 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 00:56:40.869358 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 00:56:40.876118 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 00:56:40.879448 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 00:56:40.879978 ==
3914 00:56:40.882927 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 00:56:40.885889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 00:56:40.886316 ==
3917 00:56:40.892720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 00:56:40.899617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3919 00:56:40.902554 [CA 0] Center 37 (7~67) winsize 61
3920 00:56:40.905866 [CA 1] Center 36 (6~67) winsize 62
3921 00:56:40.909164 [CA 2] Center 35 (5~65) winsize 61
3922 00:56:40.912352 [CA 3] Center 34 (4~65) winsize 62
3923 00:56:40.916257 [CA 4] Center 34 (4~65) winsize 62
3924 00:56:40.919404 [CA 5] Center 33 (3~64) winsize 62
3925 00:56:40.919925
3926 00:56:40.922929 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3927 00:56:40.923451
3928 00:56:40.926146 [CATrainingPosCal] consider 1 rank data
3929 00:56:40.929349 u2DelayCellTimex100 = 270/100 ps
3930 00:56:40.932652 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3931 00:56:40.935590 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 00:56:40.939236 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3933 00:56:40.942402 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 00:56:40.946222 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 00:56:40.952896 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 00:56:40.953422
3937 00:56:40.955911 CA PerBit enable=1, Macro0, CA PI delay=33
3938 00:56:40.956436
3939 00:56:40.959334 [CBTSetCACLKResult] CA Dly = 33
3940 00:56:40.959858 CS Dly: 5 (0~36)
3941 00:56:40.960199 ==
3942 00:56:40.962058 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 00:56:40.965506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 00:56:40.968843 ==
3945 00:56:40.972504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 00:56:40.978644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 00:56:40.982260 [CA 0] Center 37 (7~67) winsize 61
3948 00:56:40.985628 [CA 1] Center 37 (7~67) winsize 61
3949 00:56:40.988502 [CA 2] Center 35 (5~65) winsize 61
3950 00:56:40.992039 [CA 3] Center 34 (4~65) winsize 62
3951 00:56:40.995278 [CA 4] Center 34 (4~65) winsize 62
3952 00:56:40.998462 [CA 5] Center 33 (3~64) winsize 62
3953 00:56:40.998886
3954 00:56:41.002267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 00:56:41.002792
3956 00:56:41.005315 [CATrainingPosCal] consider 2 rank data
3957 00:56:41.008834 u2DelayCellTimex100 = 270/100 ps
3958 00:56:41.011892 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3959 00:56:41.015076 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3960 00:56:41.018866 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3961 00:56:41.025259 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 00:56:41.029096 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 00:56:41.032083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 00:56:41.032505
3965 00:56:41.035211 CA PerBit enable=1, Macro0, CA PI delay=33
3966 00:56:41.035634
3967 00:56:41.038476 [CBTSetCACLKResult] CA Dly = 33
3968 00:56:41.038995 CS Dly: 6 (0~38)
3969 00:56:41.039337
3970 00:56:41.041791 ----->DramcWriteLeveling(PI) begin...
3971 00:56:41.045252 ==
3972 00:56:41.045814 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 00:56:41.052375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 00:56:41.053047 ==
3975 00:56:41.055047 Write leveling (Byte 0): 33 => 33
3976 00:56:41.058448 Write leveling (Byte 1): 32 => 32
3977 00:56:41.061607 DramcWriteLeveling(PI) end<-----
3978 00:56:41.062124
3979 00:56:41.062461 ==
3980 00:56:41.065123 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 00:56:41.068693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 00:56:41.069216 ==
3983 00:56:41.072197 [Gating] SW mode calibration
3984 00:56:41.078410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 00:56:41.081791 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 00:56:41.088543 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 00:56:41.091747 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 00:56:41.094766 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 00:56:41.102034 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3990 00:56:41.105243 0 9 16 | B1->B0 | 2f2f 2b2b | 1 1 | (1 1) (1 0)
3991 00:56:41.108174 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 00:56:41.114890 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 00:56:41.118114 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 00:56:41.121583 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 00:56:41.127838 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 00:56:41.131465 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 00:56:41.134639 0 10 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
3998 00:56:41.141168 0 10 16 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
3999 00:56:41.144868 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4000 00:56:41.148099 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 00:56:41.154740 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 00:56:41.157950 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 00:56:41.161126 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 00:56:41.168119 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 00:56:41.171209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 00:56:41.174605 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4007 00:56:41.181388 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 00:56:41.184903 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 00:56:41.187776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 00:56:41.194177 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 00:56:41.197943 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 00:56:41.201030 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 00:56:41.207668 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 00:56:41.211288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 00:56:41.214170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 00:56:41.220848 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 00:56:41.224171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 00:56:41.227021 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 00:56:41.233946 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 00:56:41.237351 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 00:56:41.240827 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4022 00:56:41.247252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 00:56:41.247777 Total UI for P1: 0, mck2ui 16
4024 00:56:41.254080 best dqsien dly found for B0: ( 0, 13, 12)
4025 00:56:41.254600 Total UI for P1: 0, mck2ui 16
4026 00:56:41.257155 best dqsien dly found for B1: ( 0, 13, 14)
4027 00:56:41.263788 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4028 00:56:41.267260 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4029 00:56:41.267785
4030 00:56:41.270690 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4031 00:56:41.273765 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4032 00:56:41.276917 [Gating] SW calibration Done
4033 00:56:41.277337 ==
4034 00:56:41.280349 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 00:56:41.283926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 00:56:41.284451 ==
4037 00:56:41.287138 RX Vref Scan: 0
4038 00:56:41.287655
4039 00:56:41.287996 RX Vref 0 -> 0, step: 1
4040 00:56:41.288311
4041 00:56:41.290155 RX Delay -230 -> 252, step: 16
4042 00:56:41.297190 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4043 00:56:41.300458 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4044 00:56:41.303628 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4045 00:56:41.306827 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4046 00:56:41.310206 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4047 00:56:41.316898 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4048 00:56:41.319887 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4049 00:56:41.323408 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4050 00:56:41.326796 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4051 00:56:41.333139 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4052 00:56:41.336358 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4053 00:56:41.339687 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4054 00:56:41.343069 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4055 00:56:41.349574 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4056 00:56:41.352936 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4057 00:56:41.356199 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4058 00:56:41.356636 ==
4059 00:56:41.359494 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 00:56:41.362722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 00:56:41.363158 ==
4062 00:56:41.366153 DQS Delay:
4063 00:56:41.366585 DQS0 = 0, DQS1 = 0
4064 00:56:41.369321 DQM Delay:
4065 00:56:41.369807 DQM0 = 40, DQM1 = 33
4066 00:56:41.370245 DQ Delay:
4067 00:56:41.373010 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4068 00:56:41.376163 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4069 00:56:41.379851 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4070 00:56:41.382691 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4071 00:56:41.383127
4072 00:56:41.383562
4073 00:56:41.386022 ==
4074 00:56:41.389258 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 00:56:41.392932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 00:56:41.393463 ==
4077 00:56:41.393966
4078 00:56:41.394380
4079 00:56:41.395717 TX Vref Scan disable
4080 00:56:41.396104 == TX Byte 0 ==
4081 00:56:41.402659 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4082 00:56:41.406060 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4083 00:56:41.406593 == TX Byte 1 ==
4084 00:56:41.412505 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4085 00:56:41.415596 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4086 00:56:41.416031 ==
4087 00:56:41.419377 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 00:56:41.422781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 00:56:41.423310 ==
4090 00:56:41.423647
4091 00:56:41.423960
4092 00:56:41.425844 TX Vref Scan disable
4093 00:56:41.429210 == TX Byte 0 ==
4094 00:56:41.432506 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4095 00:56:41.435465 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4096 00:56:41.439348 == TX Byte 1 ==
4097 00:56:41.442323 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4098 00:56:41.446129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4099 00:56:41.446655
4100 00:56:41.449326 [DATLAT]
4101 00:56:41.449884 Freq=600, CH0 RK0
4102 00:56:41.450226
4103 00:56:41.452510 DATLAT Default: 0x9
4104 00:56:41.453029 0, 0xFFFF, sum = 0
4105 00:56:41.455570 1, 0xFFFF, sum = 0
4106 00:56:41.455998 2, 0xFFFF, sum = 0
4107 00:56:41.459027 3, 0xFFFF, sum = 0
4108 00:56:41.459561 4, 0xFFFF, sum = 0
4109 00:56:41.462359 5, 0xFFFF, sum = 0
4110 00:56:41.462885 6, 0xFFFF, sum = 0
4111 00:56:41.465596 7, 0xFFFF, sum = 0
4112 00:56:41.466029 8, 0x0, sum = 1
4113 00:56:41.469266 9, 0x0, sum = 2
4114 00:56:41.469844 10, 0x0, sum = 3
4115 00:56:41.472446 11, 0x0, sum = 4
4116 00:56:41.472989 best_step = 9
4117 00:56:41.473333
4118 00:56:41.473692 ==
4119 00:56:41.475572 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 00:56:41.482004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 00:56:41.482429 ==
4122 00:56:41.482767 RX Vref Scan: 1
4123 00:56:41.483084
4124 00:56:41.485342 RX Vref 0 -> 0, step: 1
4125 00:56:41.485802
4126 00:56:41.488713 RX Delay -195 -> 252, step: 8
4127 00:56:41.489135
4128 00:56:41.492120 Set Vref, RX VrefLevel [Byte0]: 60
4129 00:56:41.495688 [Byte1]: 52
4130 00:56:41.496208
4131 00:56:41.498743 Final RX Vref Byte 0 = 60 to rank0
4132 00:56:41.501927 Final RX Vref Byte 1 = 52 to rank0
4133 00:56:41.505081 Final RX Vref Byte 0 = 60 to rank1
4134 00:56:41.508893 Final RX Vref Byte 1 = 52 to rank1==
4135 00:56:41.512089 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 00:56:41.515177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 00:56:41.515650 ==
4138 00:56:41.518393 DQS Delay:
4139 00:56:41.518821 DQS0 = 0, DQS1 = 0
4140 00:56:41.519164 DQM Delay:
4141 00:56:41.521758 DQM0 = 34, DQM1 = 29
4142 00:56:41.522184 DQ Delay:
4143 00:56:41.525030 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4144 00:56:41.528155 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4145 00:56:41.531699 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4146 00:56:41.535230 DQ12 =32, DQ13 =36, DQ14 =44, DQ15 =36
4147 00:56:41.535655
4148 00:56:41.536002
4149 00:56:41.545012 [DQSOSCAuto] RK0, (LSB)MR18= 0x403f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4150 00:56:41.548421 CH0 RK0: MR19=808, MR18=403F
4151 00:56:41.551510 CH0_RK0: MR19=0x808, MR18=0x403F, DQSOSC=397, MR23=63, INC=166, DEC=110
4152 00:56:41.555165
4153 00:56:41.558383 ----->DramcWriteLeveling(PI) begin...
4154 00:56:41.558923 ==
4155 00:56:41.561870 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 00:56:41.564666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 00:56:41.565096 ==
4158 00:56:41.567925 Write leveling (Byte 0): 34 => 34
4159 00:56:41.571375 Write leveling (Byte 1): 30 => 30
4160 00:56:41.575267 DramcWriteLeveling(PI) end<-----
4161 00:56:41.575801
4162 00:56:41.576146 ==
4163 00:56:41.578050 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 00:56:41.581255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 00:56:41.581728 ==
4166 00:56:41.584752 [Gating] SW mode calibration
4167 00:56:41.591163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 00:56:41.598157 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 00:56:41.601323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 00:56:41.605110 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 00:56:41.611483 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 00:56:41.614712 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4173 00:56:41.618401 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4174 00:56:41.624724 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 00:56:41.628148 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 00:56:41.631263 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 00:56:41.638107 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 00:56:41.641296 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 00:56:41.644594 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 00:56:41.651076 0 10 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
4181 00:56:41.654558 0 10 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
4182 00:56:41.657585 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 00:56:41.664290 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 00:56:41.667307 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 00:56:41.671099 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 00:56:41.677535 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 00:56:41.680608 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 00:56:41.684328 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4189 00:56:41.690237 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4190 00:56:41.693871 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 00:56:41.697248 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 00:56:41.700657 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 00:56:41.707180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 00:56:41.710659 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 00:56:41.713572 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 00:56:41.720235 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 00:56:41.724036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 00:56:41.726623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 00:56:41.733207 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 00:56:41.736853 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 00:56:41.740471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 00:56:41.746758 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 00:56:41.750391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 00:56:41.753462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 00:56:41.760046 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 00:56:41.763338 Total UI for P1: 0, mck2ui 16
4207 00:56:41.766451 best dqsien dly found for B0: ( 0, 13, 14)
4208 00:56:41.770187 Total UI for P1: 0, mck2ui 16
4209 00:56:41.773387 best dqsien dly found for B1: ( 0, 13, 14)
4210 00:56:41.776613 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4211 00:56:41.780281 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4212 00:56:41.780809
4213 00:56:41.783162 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4214 00:56:41.786378 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4215 00:56:41.789529 [Gating] SW calibration Done
4216 00:56:41.789964 ==
4217 00:56:41.793353 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 00:56:41.796255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 00:56:41.796777 ==
4220 00:56:41.800100 RX Vref Scan: 0
4221 00:56:41.800650
4222 00:56:41.802766 RX Vref 0 -> 0, step: 1
4223 00:56:41.803262
4224 00:56:41.803608 RX Delay -230 -> 252, step: 16
4225 00:56:41.809691 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4226 00:56:41.812710 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4227 00:56:41.816414 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4228 00:56:41.819921 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4229 00:56:41.826557 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4230 00:56:41.829271 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4231 00:56:41.832677 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4232 00:56:41.836254 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4233 00:56:41.842466 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4234 00:56:41.845943 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4235 00:56:41.849023 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4236 00:56:41.852234 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4237 00:56:41.855677 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4238 00:56:41.862128 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4239 00:56:41.865536 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4240 00:56:41.868753 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4241 00:56:41.869195 ==
4242 00:56:41.872035 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 00:56:41.878722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 00:56:41.879163 ==
4245 00:56:41.879506 DQS Delay:
4246 00:56:41.882228 DQS0 = 0, DQS1 = 0
4247 00:56:41.882649 DQM Delay:
4248 00:56:41.882985 DQM0 = 35, DQM1 = 28
4249 00:56:41.885507 DQ Delay:
4250 00:56:41.889046 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4251 00:56:41.892246 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4252 00:56:41.895792 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4253 00:56:41.899088 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4254 00:56:41.899617
4255 00:56:41.899956
4256 00:56:41.900271 ==
4257 00:56:41.901883 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 00:56:41.905595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 00:56:41.906256 ==
4260 00:56:41.906682
4261 00:56:41.907006
4262 00:56:41.908523 TX Vref Scan disable
4263 00:56:41.911907 == TX Byte 0 ==
4264 00:56:41.914940 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4265 00:56:41.918678 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4266 00:56:41.922378 == TX Byte 1 ==
4267 00:56:41.925128 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4268 00:56:41.928672 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4269 00:56:41.929205 ==
4270 00:56:41.931594 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 00:56:41.935331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 00:56:41.938686 ==
4273 00:56:41.939136
4274 00:56:41.939472
4275 00:56:41.939788 TX Vref Scan disable
4276 00:56:41.942300 == TX Byte 0 ==
4277 00:56:41.945698 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4278 00:56:41.952630 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4279 00:56:41.953172 == TX Byte 1 ==
4280 00:56:41.955580 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4281 00:56:41.962282 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4282 00:56:41.962806
4283 00:56:41.963152 [DATLAT]
4284 00:56:41.963470 Freq=600, CH0 RK1
4285 00:56:41.963781
4286 00:56:41.965453 DATLAT Default: 0x9
4287 00:56:41.965911 0, 0xFFFF, sum = 0
4288 00:56:41.968755 1, 0xFFFF, sum = 0
4289 00:56:41.969187 2, 0xFFFF, sum = 0
4290 00:56:41.972354 3, 0xFFFF, sum = 0
4291 00:56:41.975649 4, 0xFFFF, sum = 0
4292 00:56:41.976197 5, 0xFFFF, sum = 0
4293 00:56:41.978863 6, 0xFFFF, sum = 0
4294 00:56:41.979515 7, 0xFFFF, sum = 0
4295 00:56:41.982034 8, 0x0, sum = 1
4296 00:56:41.982462 9, 0x0, sum = 2
4297 00:56:41.982805 10, 0x0, sum = 3
4298 00:56:41.985279 11, 0x0, sum = 4
4299 00:56:41.985802 best_step = 9
4300 00:56:41.986143
4301 00:56:41.986458 ==
4302 00:56:41.988460 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 00:56:41.995266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 00:56:41.995695 ==
4305 00:56:41.996036 RX Vref Scan: 0
4306 00:56:41.996353
4307 00:56:41.998612 RX Vref 0 -> 0, step: 1
4308 00:56:41.999035
4309 00:56:42.002225 RX Delay -195 -> 252, step: 8
4310 00:56:42.005544 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4311 00:56:42.012321 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4312 00:56:42.015070 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4313 00:56:42.019026 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4314 00:56:42.022057 iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320
4315 00:56:42.028689 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4316 00:56:42.031821 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4317 00:56:42.035609 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4318 00:56:42.038621 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4319 00:56:42.042239 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4320 00:56:42.048226 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4321 00:56:42.051928 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4322 00:56:42.055433 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4323 00:56:42.058442 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4324 00:56:42.065116 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4325 00:56:42.068340 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4326 00:56:42.068765 ==
4327 00:56:42.071767 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 00:56:42.074931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 00:56:42.075450 ==
4330 00:56:42.078502 DQS Delay:
4331 00:56:42.078937 DQS0 = 0, DQS1 = 0
4332 00:56:42.079346 DQM Delay:
4333 00:56:42.081869 DQM0 = 33, DQM1 = 27
4334 00:56:42.082298 DQ Delay:
4335 00:56:42.084831 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4336 00:56:42.088247 DQ4 =28, DQ5 =20, DQ6 =44, DQ7 =44
4337 00:56:42.091502 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4338 00:56:42.095053 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4339 00:56:42.095468
4340 00:56:42.095798
4341 00:56:42.104555 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4342 00:56:42.108029 CH0 RK1: MR19=808, MR18=6C3A
4343 00:56:42.111154 CH0_RK1: MR19=0x808, MR18=0x6C3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4344 00:56:42.114422 [RxdqsGatingPostProcess] freq 600
4345 00:56:42.121102 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 00:56:42.124437 Pre-setting of DQS Precalculation
4347 00:56:42.127942 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 00:56:42.128108 ==
4349 00:56:42.130901 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 00:56:42.137558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 00:56:42.137683 ==
4352 00:56:42.140721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 00:56:42.147635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4354 00:56:42.150835 [CA 0] Center 35 (5~66) winsize 62
4355 00:56:42.154730 [CA 1] Center 35 (5~66) winsize 62
4356 00:56:42.157820 [CA 2] Center 34 (4~64) winsize 61
4357 00:56:42.161172 [CA 3] Center 34 (3~65) winsize 63
4358 00:56:42.164699 [CA 4] Center 34 (4~65) winsize 62
4359 00:56:42.167897 [CA 5] Center 33 (3~64) winsize 62
4360 00:56:42.168058
4361 00:56:42.171404 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4362 00:56:42.171565
4363 00:56:42.174430 [CATrainingPosCal] consider 1 rank data
4364 00:56:42.177809 u2DelayCellTimex100 = 270/100 ps
4365 00:56:42.180823 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 00:56:42.187861 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4367 00:56:42.191009 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4368 00:56:42.194330 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4369 00:56:42.197560 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4370 00:56:42.200804 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4371 00:56:42.200991
4372 00:56:42.204552 CA PerBit enable=1, Macro0, CA PI delay=33
4373 00:56:42.204736
4374 00:56:42.207740 [CBTSetCACLKResult] CA Dly = 33
4375 00:56:42.207934 CS Dly: 5 (0~36)
4376 00:56:42.210925 ==
4377 00:56:42.214069 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 00:56:42.217660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 00:56:42.217881 ==
4380 00:56:42.221003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 00:56:42.227761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4382 00:56:42.231550 [CA 0] Center 36 (6~66) winsize 61
4383 00:56:42.234516 [CA 1] Center 36 (6~67) winsize 62
4384 00:56:42.237955 [CA 2] Center 34 (4~65) winsize 62
4385 00:56:42.241587 [CA 3] Center 34 (3~65) winsize 63
4386 00:56:42.244794 [CA 4] Center 34 (4~65) winsize 62
4387 00:56:42.247987 [CA 5] Center 34 (3~65) winsize 63
4388 00:56:42.248604
4389 00:56:42.251486 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4390 00:56:42.252011
4391 00:56:42.254952 [CATrainingPosCal] consider 2 rank data
4392 00:56:42.258470 u2DelayCellTimex100 = 270/100 ps
4393 00:56:42.261689 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4394 00:56:42.264913 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4395 00:56:42.271376 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4396 00:56:42.274973 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4397 00:56:42.277733 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 00:56:42.281269 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4399 00:56:42.281742
4400 00:56:42.284466 CA PerBit enable=1, Macro0, CA PI delay=33
4401 00:56:42.284891
4402 00:56:42.288258 [CBTSetCACLKResult] CA Dly = 33
4403 00:56:42.288784 CS Dly: 5 (0~36)
4404 00:56:42.289191
4405 00:56:42.294693 ----->DramcWriteLeveling(PI) begin...
4406 00:56:42.295213 ==
4407 00:56:42.298110 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 00:56:42.301455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 00:56:42.302020 ==
4410 00:56:42.304699 Write leveling (Byte 0): 30 => 30
4411 00:56:42.307994 Write leveling (Byte 1): 30 => 30
4412 00:56:42.311242 DramcWriteLeveling(PI) end<-----
4413 00:56:42.311777
4414 00:56:42.312119 ==
4415 00:56:42.314810 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 00:56:42.317627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 00:56:42.318058 ==
4418 00:56:42.321533 [Gating] SW mode calibration
4419 00:56:42.328354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 00:56:42.334423 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 00:56:42.337708 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 00:56:42.341271 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 00:56:42.347789 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 00:56:42.350886 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
4425 00:56:42.354376 0 9 16 | B1->B0 | 2525 2525 | 0 0 | (1 1) (1 1)
4426 00:56:42.360879 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 00:56:42.364280 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 00:56:42.367475 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 00:56:42.374066 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 00:56:42.377669 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 00:56:42.381025 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 00:56:42.384133 0 10 12 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
4433 00:56:42.390459 0 10 16 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
4434 00:56:42.394164 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 00:56:42.397499 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 00:56:42.404186 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 00:56:42.407325 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 00:56:42.410108 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 00:56:42.417041 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 00:56:42.420175 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 00:56:42.423880 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4442 00:56:42.430099 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 00:56:42.433445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 00:56:42.436623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 00:56:42.443258 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 00:56:42.446334 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 00:56:42.449790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 00:56:42.456076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 00:56:42.459439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 00:56:42.463011 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 00:56:42.469344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 00:56:42.472965 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 00:56:42.476086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 00:56:42.482571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 00:56:42.485981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 00:56:42.489110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4457 00:56:42.495941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4458 00:56:42.499071 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 00:56:42.502549 Total UI for P1: 0, mck2ui 16
4460 00:56:42.505986 best dqsien dly found for B0: ( 0, 13, 14)
4461 00:56:42.509148 Total UI for P1: 0, mck2ui 16
4462 00:56:42.512387 best dqsien dly found for B1: ( 0, 13, 16)
4463 00:56:42.515911 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4464 00:56:42.519098 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4465 00:56:42.519204
4466 00:56:42.522362 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4467 00:56:42.525735 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4468 00:56:42.529050 [Gating] SW calibration Done
4469 00:56:42.529151 ==
4470 00:56:42.532352 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 00:56:42.538924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 00:56:42.539030 ==
4473 00:56:42.539126 RX Vref Scan: 0
4474 00:56:42.539222
4475 00:56:42.542252 RX Vref 0 -> 0, step: 1
4476 00:56:42.542367
4477 00:56:42.545589 RX Delay -230 -> 252, step: 16
4478 00:56:42.548902 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4479 00:56:42.552348 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4480 00:56:42.555720 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4481 00:56:42.562359 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4482 00:56:42.565557 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4483 00:56:42.568839 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4484 00:56:42.572470 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4485 00:56:42.575511 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4486 00:56:42.582270 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4487 00:56:42.585398 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4488 00:56:42.588921 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4489 00:56:42.592016 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4490 00:56:42.598846 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4491 00:56:42.602016 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4492 00:56:42.605487 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4493 00:56:42.608987 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4494 00:56:42.612049 ==
4495 00:56:42.612153 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 00:56:42.618726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 00:56:42.618817 ==
4498 00:56:42.618884 DQS Delay:
4499 00:56:42.621915 DQS0 = 0, DQS1 = 0
4500 00:56:42.621998 DQM Delay:
4501 00:56:42.625285 DQM0 = 38, DQM1 = 29
4502 00:56:42.625368 DQ Delay:
4503 00:56:42.628525 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4504 00:56:42.631941 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4505 00:56:42.635166 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4506 00:56:42.638641 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4507 00:56:42.638726
4508 00:56:42.638792
4509 00:56:42.638853 ==
4510 00:56:42.641787 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 00:56:42.645200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 00:56:42.645283 ==
4513 00:56:42.645350
4514 00:56:42.645410
4515 00:56:42.648467 TX Vref Scan disable
4516 00:56:42.651867 == TX Byte 0 ==
4517 00:56:42.654989 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4518 00:56:42.658324 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4519 00:56:42.661588 == TX Byte 1 ==
4520 00:56:42.664879 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4521 00:56:42.668284 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4522 00:56:42.668368 ==
4523 00:56:42.671650 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 00:56:42.677985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 00:56:42.678074 ==
4526 00:56:42.678161
4527 00:56:42.678244
4528 00:56:42.678342 TX Vref Scan disable
4529 00:56:42.682331 == TX Byte 0 ==
4530 00:56:42.685441 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4531 00:56:42.692350 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4532 00:56:42.692435 == TX Byte 1 ==
4533 00:56:42.695430 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4534 00:56:42.702113 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4535 00:56:42.702197
4536 00:56:42.702264 [DATLAT]
4537 00:56:42.702326 Freq=600, CH1 RK0
4538 00:56:42.702387
4539 00:56:42.705350 DATLAT Default: 0x9
4540 00:56:42.705433 0, 0xFFFF, sum = 0
4541 00:56:42.708627 1, 0xFFFF, sum = 0
4542 00:56:42.712236 2, 0xFFFF, sum = 0
4543 00:56:42.712320 3, 0xFFFF, sum = 0
4544 00:56:42.715463 4, 0xFFFF, sum = 0
4545 00:56:42.715548 5, 0xFFFF, sum = 0
4546 00:56:42.718895 6, 0xFFFF, sum = 0
4547 00:56:42.718980 7, 0xFFFF, sum = 0
4548 00:56:42.722185 8, 0x0, sum = 1
4549 00:56:42.722270 9, 0x0, sum = 2
4550 00:56:42.722337 10, 0x0, sum = 3
4551 00:56:42.725360 11, 0x0, sum = 4
4552 00:56:42.725444 best_step = 9
4553 00:56:42.725551
4554 00:56:42.725616 ==
4555 00:56:42.728636 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 00:56:42.735547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 00:56:42.735631 ==
4558 00:56:42.735698 RX Vref Scan: 1
4559 00:56:42.735760
4560 00:56:42.738745 RX Vref 0 -> 0, step: 1
4561 00:56:42.738828
4562 00:56:42.741809 RX Delay -195 -> 252, step: 8
4563 00:56:42.741892
4564 00:56:42.745783 Set Vref, RX VrefLevel [Byte0]: 57
4565 00:56:42.748983 [Byte1]: 49
4566 00:56:42.749371
4567 00:56:42.752882 Final RX Vref Byte 0 = 57 to rank0
4568 00:56:42.756021 Final RX Vref Byte 1 = 49 to rank0
4569 00:56:42.759328 Final RX Vref Byte 0 = 57 to rank1
4570 00:56:42.762413 Final RX Vref Byte 1 = 49 to rank1==
4571 00:56:42.765814 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 00:56:42.768935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 00:56:42.769333 ==
4574 00:56:42.772363 DQS Delay:
4575 00:56:42.772789 DQS0 = 0, DQS1 = 0
4576 00:56:42.775714 DQM Delay:
4577 00:56:42.776249 DQM0 = 39, DQM1 = 29
4578 00:56:42.776597 DQ Delay:
4579 00:56:42.778939 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4580 00:56:42.782149 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4581 00:56:42.785665 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4582 00:56:42.788532 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4583 00:56:42.788964
4584 00:56:42.789305
4585 00:56:42.798483 [DQSOSCAuto] RK0, (LSB)MR18= 0x2634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4586 00:56:42.802051 CH1 RK0: MR19=808, MR18=2634
4587 00:56:42.809053 CH1_RK0: MR19=0x808, MR18=0x2634, DQSOSC=400, MR23=63, INC=163, DEC=109
4588 00:56:42.809636
4589 00:56:42.812181 ----->DramcWriteLeveling(PI) begin...
4590 00:56:42.812719 ==
4591 00:56:42.815098 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 00:56:42.818343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 00:56:42.818836 ==
4594 00:56:42.822049 Write leveling (Byte 0): 28 => 28
4595 00:56:42.825282 Write leveling (Byte 1): 28 => 28
4596 00:56:42.828712 DramcWriteLeveling(PI) end<-----
4597 00:56:42.829248
4598 00:56:42.829639 ==
4599 00:56:42.832022 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 00:56:42.835024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 00:56:42.835458 ==
4602 00:56:42.838265 [Gating] SW mode calibration
4603 00:56:42.845150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 00:56:42.851829 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 00:56:42.855153 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 00:56:42.858672 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 00:56:42.865335 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4608 00:56:42.868744 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4609 00:56:42.872047 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
4610 00:56:42.878327 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 00:56:42.881892 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 00:56:42.884736 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 00:56:42.891516 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 00:56:42.894785 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 00:56:42.898133 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4616 00:56:42.904588 0 10 12 | B1->B0 | 3232 3a3a | 0 0 | (1 1) (0 0)
4617 00:56:42.908052 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 00:56:42.911325 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 00:56:42.917765 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 00:56:42.920969 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 00:56:42.924369 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 00:56:42.931181 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 00:56:42.934469 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4624 00:56:42.937624 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4625 00:56:42.944716 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 00:56:42.947585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 00:56:42.951113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 00:56:42.957819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 00:56:42.960865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 00:56:42.964034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 00:56:42.970393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 00:56:42.974156 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 00:56:42.977592 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 00:56:42.983699 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 00:56:42.987523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 00:56:42.990627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 00:56:42.996953 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 00:56:43.000078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 00:56:43.003554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4640 00:56:43.006997 Total UI for P1: 0, mck2ui 16
4641 00:56:43.010093 best dqsien dly found for B0: ( 0, 13, 6)
4642 00:56:43.016709 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4643 00:56:43.020188 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 00:56:43.023728 Total UI for P1: 0, mck2ui 16
4645 00:56:43.026867 best dqsien dly found for B1: ( 0, 13, 12)
4646 00:56:43.029992 best DQS0 dly(MCK, UI, PI) = (0, 13, 6)
4647 00:56:43.033560 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4648 00:56:43.034096
4649 00:56:43.036526 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 6)
4650 00:56:43.039822 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4651 00:56:43.043452 [Gating] SW calibration Done
4652 00:56:43.043985 ==
4653 00:56:43.046355 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 00:56:43.049606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 00:56:43.053429 ==
4656 00:56:43.053995 RX Vref Scan: 0
4657 00:56:43.054343
4658 00:56:43.056282 RX Vref 0 -> 0, step: 1
4659 00:56:43.056709
4660 00:56:43.059725 RX Delay -230 -> 252, step: 16
4661 00:56:43.063478 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4662 00:56:43.066448 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4663 00:56:43.069648 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4664 00:56:43.076510 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4665 00:56:43.079696 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4666 00:56:43.082978 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4667 00:56:43.086280 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4668 00:56:43.090116 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4669 00:56:43.096655 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4670 00:56:43.099892 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4671 00:56:43.103131 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4672 00:56:43.106486 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4673 00:56:43.113138 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4674 00:56:43.116034 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4675 00:56:43.119884 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4676 00:56:43.123239 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4677 00:56:43.123775 ==
4678 00:56:43.126443 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 00:56:43.133002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 00:56:43.133573 ==
4681 00:56:43.133925 DQS Delay:
4682 00:56:43.136368 DQS0 = 0, DQS1 = 0
4683 00:56:43.136896 DQM Delay:
4684 00:56:43.137241 DQM0 = 35, DQM1 = 29
4685 00:56:43.139405 DQ Delay:
4686 00:56:43.142936 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4687 00:56:43.146270 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4688 00:56:43.149219 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4689 00:56:43.152710 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4690 00:56:43.153240
4691 00:56:43.153617
4692 00:56:43.153940 ==
4693 00:56:43.155906 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 00:56:43.159383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 00:56:43.159918 ==
4696 00:56:43.160266
4697 00:56:43.160584
4698 00:56:43.162651 TX Vref Scan disable
4699 00:56:43.165613 == TX Byte 0 ==
4700 00:56:43.168999 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 00:56:43.172747 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 00:56:43.176144 == TX Byte 1 ==
4703 00:56:43.178915 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4704 00:56:43.182449 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4705 00:56:43.182993 ==
4706 00:56:43.185450 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 00:56:43.188885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 00:56:43.191953 ==
4709 00:56:43.192383
4710 00:56:43.192723
4711 00:56:43.193036 TX Vref Scan disable
4712 00:56:43.196150 == TX Byte 0 ==
4713 00:56:43.199364 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4714 00:56:43.205947 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4715 00:56:43.206481 == TX Byte 1 ==
4716 00:56:43.209348 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4717 00:56:43.215828 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4718 00:56:43.216257
4719 00:56:43.216597 [DATLAT]
4720 00:56:43.217039 Freq=600, CH1 RK1
4721 00:56:43.217365
4722 00:56:43.219025 DATLAT Default: 0x9
4723 00:56:43.219484 0, 0xFFFF, sum = 0
4724 00:56:43.222854 1, 0xFFFF, sum = 0
4725 00:56:43.225878 2, 0xFFFF, sum = 0
4726 00:56:43.226314 3, 0xFFFF, sum = 0
4727 00:56:43.228880 4, 0xFFFF, sum = 0
4728 00:56:43.229312 5, 0xFFFF, sum = 0
4729 00:56:43.232788 6, 0xFFFF, sum = 0
4730 00:56:43.233320 7, 0xFFFF, sum = 0
4731 00:56:43.235628 8, 0x0, sum = 1
4732 00:56:43.236085 9, 0x0, sum = 2
4733 00:56:43.236434 10, 0x0, sum = 3
4734 00:56:43.238893 11, 0x0, sum = 4
4735 00:56:43.239375 best_step = 9
4736 00:56:43.239773
4737 00:56:43.240101 ==
4738 00:56:43.242047 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 00:56:43.248944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 00:56:43.249510 ==
4741 00:56:43.249864 RX Vref Scan: 0
4742 00:56:43.250189
4743 00:56:43.252356 RX Vref 0 -> 0, step: 1
4744 00:56:43.252889
4745 00:56:43.255682 RX Delay -195 -> 252, step: 8
4746 00:56:43.259166 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4747 00:56:43.265698 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4748 00:56:43.269431 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4749 00:56:43.272572 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4750 00:56:43.275754 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4751 00:56:43.282359 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4752 00:56:43.285150 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4753 00:56:43.288619 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4754 00:56:43.292311 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4755 00:56:43.295834 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4756 00:56:43.301868 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4757 00:56:43.305450 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4758 00:56:43.308721 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4759 00:56:43.311780 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4760 00:56:43.318374 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4761 00:56:43.322096 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4762 00:56:43.322634 ==
4763 00:56:43.325277 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 00:56:43.328359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 00:56:43.328806 ==
4766 00:56:43.331617 DQS Delay:
4767 00:56:43.332049 DQS0 = 0, DQS1 = 0
4768 00:56:43.335069 DQM Delay:
4769 00:56:43.335495 DQM0 = 35, DQM1 = 29
4770 00:56:43.335910 DQ Delay:
4771 00:56:43.338478 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4772 00:56:43.341632 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =32
4773 00:56:43.345374 DQ8 =16, DQ9 =16, DQ10 =36, DQ11 =24
4774 00:56:43.348415 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4775 00:56:43.348947
4776 00:56:43.349290
4777 00:56:43.358451 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4778 00:56:43.361516 CH1 RK1: MR19=808, MR18=3E5E
4779 00:56:43.368668 CH1_RK1: MR19=0x808, MR18=0x3E5E, DQSOSC=392, MR23=63, INC=170, DEC=113
4780 00:56:43.369202 [RxdqsGatingPostProcess] freq 600
4781 00:56:43.375067 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4782 00:56:43.378438 Pre-setting of DQS Precalculation
4783 00:56:43.381516 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4784 00:56:43.391582 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4785 00:56:43.397731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4786 00:56:43.398242
4787 00:56:43.398587
4788 00:56:43.400978 [Calibration Summary] 1200 Mbps
4789 00:56:43.401407 CH 0, Rank 0
4790 00:56:43.404540 SW Impedance : PASS
4791 00:56:43.405073 DUTY Scan : NO K
4792 00:56:43.407841 ZQ Calibration : PASS
4793 00:56:43.411391 Jitter Meter : NO K
4794 00:56:43.411921 CBT Training : PASS
4795 00:56:43.414246 Write leveling : PASS
4796 00:56:43.417522 RX DQS gating : PASS
4797 00:56:43.417952 RX DQ/DQS(RDDQC) : PASS
4798 00:56:43.420840 TX DQ/DQS : PASS
4799 00:56:43.424366 RX DATLAT : PASS
4800 00:56:43.424902 RX DQ/DQS(Engine): PASS
4801 00:56:43.427564 TX OE : NO K
4802 00:56:43.427995 All Pass.
4803 00:56:43.428336
4804 00:56:43.431010 CH 0, Rank 1
4805 00:56:43.431574 SW Impedance : PASS
4806 00:56:43.434105 DUTY Scan : NO K
4807 00:56:43.437454 ZQ Calibration : PASS
4808 00:56:43.437921 Jitter Meter : NO K
4809 00:56:43.440386 CBT Training : PASS
4810 00:56:43.443765 Write leveling : PASS
4811 00:56:43.444192 RX DQS gating : PASS
4812 00:56:43.447078 RX DQ/DQS(RDDQC) : PASS
4813 00:56:43.450812 TX DQ/DQS : PASS
4814 00:56:43.451347 RX DATLAT : PASS
4815 00:56:43.453932 RX DQ/DQS(Engine): PASS
4816 00:56:43.457398 TX OE : NO K
4817 00:56:43.457979 All Pass.
4818 00:56:43.458326
4819 00:56:43.458651 CH 1, Rank 0
4820 00:56:43.460578 SW Impedance : PASS
4821 00:56:43.464470 DUTY Scan : NO K
4822 00:56:43.465007 ZQ Calibration : PASS
4823 00:56:43.467064 Jitter Meter : NO K
4824 00:56:43.467587 CBT Training : PASS
4825 00:56:43.470683 Write leveling : PASS
4826 00:56:43.474416 RX DQS gating : PASS
4827 00:56:43.474957 RX DQ/DQS(RDDQC) : PASS
4828 00:56:43.477125 TX DQ/DQS : PASS
4829 00:56:43.480643 RX DATLAT : PASS
4830 00:56:43.481174 RX DQ/DQS(Engine): PASS
4831 00:56:43.483954 TX OE : NO K
4832 00:56:43.484491 All Pass.
4833 00:56:43.484840
4834 00:56:43.487073 CH 1, Rank 1
4835 00:56:43.487502 SW Impedance : PASS
4836 00:56:43.490772 DUTY Scan : NO K
4837 00:56:43.494049 ZQ Calibration : PASS
4838 00:56:43.494586 Jitter Meter : NO K
4839 00:56:43.497112 CBT Training : PASS
4840 00:56:43.500660 Write leveling : PASS
4841 00:56:43.501194 RX DQS gating : PASS
4842 00:56:43.504092 RX DQ/DQS(RDDQC) : PASS
4843 00:56:43.507283 TX DQ/DQS : PASS
4844 00:56:43.507818 RX DATLAT : PASS
4845 00:56:43.510306 RX DQ/DQS(Engine): PASS
4846 00:56:43.513831 TX OE : NO K
4847 00:56:43.514361 All Pass.
4848 00:56:43.514707
4849 00:56:43.515025 DramC Write-DBI off
4850 00:56:43.516791 PER_BANK_REFRESH: Hybrid Mode
4851 00:56:43.520074 TX_TRACKING: ON
4852 00:56:43.527178 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4853 00:56:43.530345 [FAST_K] Save calibration result to emmc
4854 00:56:43.536793 dramc_set_vcore_voltage set vcore to 662500
4855 00:56:43.537312 Read voltage for 933, 3
4856 00:56:43.540046 Vio18 = 0
4857 00:56:43.540479 Vcore = 662500
4858 00:56:43.540823 Vdram = 0
4859 00:56:43.541142 Vddq = 0
4860 00:56:43.543790 Vmddr = 0
4861 00:56:43.546807 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4862 00:56:43.553242 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4863 00:56:43.556861 MEM_TYPE=3, freq_sel=17
4864 00:56:43.557391 sv_algorithm_assistance_LP4_1600
4865 00:56:43.562873 ============ PULL DRAM RESETB DOWN ============
4866 00:56:43.566003 ========== PULL DRAM RESETB DOWN end =========
4867 00:56:43.569484 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4868 00:56:43.572635 ===================================
4869 00:56:43.576024 LPDDR4 DRAM CONFIGURATION
4870 00:56:43.579260 ===================================
4871 00:56:43.582652 EX_ROW_EN[0] = 0x0
4872 00:56:43.582737 EX_ROW_EN[1] = 0x0
4873 00:56:43.585762 LP4Y_EN = 0x0
4874 00:56:43.585847 WORK_FSP = 0x0
4875 00:56:43.589393 WL = 0x3
4876 00:56:43.589503 RL = 0x3
4877 00:56:43.592521 BL = 0x2
4878 00:56:43.592605 RPST = 0x0
4879 00:56:43.596007 RD_PRE = 0x0
4880 00:56:43.596091 WR_PRE = 0x1
4881 00:56:43.599122 WR_PST = 0x0
4882 00:56:43.599205 DBI_WR = 0x0
4883 00:56:43.602462 DBI_RD = 0x0
4884 00:56:43.602548 OTF = 0x1
4885 00:56:43.606002 ===================================
4886 00:56:43.609210 ===================================
4887 00:56:43.612446 ANA top config
4888 00:56:43.615990 ===================================
4889 00:56:43.619119 DLL_ASYNC_EN = 0
4890 00:56:43.619203 ALL_SLAVE_EN = 1
4891 00:56:43.622641 NEW_RANK_MODE = 1
4892 00:56:43.625972 DLL_IDLE_MODE = 1
4893 00:56:43.629171 LP45_APHY_COMB_EN = 1
4894 00:56:43.632444 TX_ODT_DIS = 1
4895 00:56:43.632528 NEW_8X_MODE = 1
4896 00:56:43.635946 ===================================
4897 00:56:43.638989 ===================================
4898 00:56:43.642316 data_rate = 1866
4899 00:56:43.645601 CKR = 1
4900 00:56:43.648888 DQ_P2S_RATIO = 8
4901 00:56:43.652162 ===================================
4902 00:56:43.655651 CA_P2S_RATIO = 8
4903 00:56:43.658858 DQ_CA_OPEN = 0
4904 00:56:43.658941 DQ_SEMI_OPEN = 0
4905 00:56:43.662217 CA_SEMI_OPEN = 0
4906 00:56:43.665361 CA_FULL_RATE = 0
4907 00:56:43.668723 DQ_CKDIV4_EN = 1
4908 00:56:43.672115 CA_CKDIV4_EN = 1
4909 00:56:43.675556 CA_PREDIV_EN = 0
4910 00:56:43.675639 PH8_DLY = 0
4911 00:56:43.678603 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4912 00:56:43.681931 DQ_AAMCK_DIV = 4
4913 00:56:43.685437 CA_AAMCK_DIV = 4
4914 00:56:43.688574 CA_ADMCK_DIV = 4
4915 00:56:43.691850 DQ_TRACK_CA_EN = 0
4916 00:56:43.691933 CA_PICK = 933
4917 00:56:43.695274 CA_MCKIO = 933
4918 00:56:43.698766 MCKIO_SEMI = 0
4919 00:56:43.701972 PLL_FREQ = 3732
4920 00:56:43.705302 DQ_UI_PI_RATIO = 32
4921 00:56:43.708600 CA_UI_PI_RATIO = 0
4922 00:56:43.711847 ===================================
4923 00:56:43.715269 ===================================
4924 00:56:43.715352 memory_type:LPDDR4
4925 00:56:43.718568 GP_NUM : 10
4926 00:56:43.721812 SRAM_EN : 1
4927 00:56:43.721895 MD32_EN : 0
4928 00:56:43.725029 ===================================
4929 00:56:43.728406 [ANA_INIT] >>>>>>>>>>>>>>
4930 00:56:43.731629 <<<<<< [CONFIGURE PHASE]: ANA_TX
4931 00:56:43.735122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4932 00:56:43.738373 ===================================
4933 00:56:43.741585 data_rate = 1866,PCW = 0X8f00
4934 00:56:43.744947 ===================================
4935 00:56:43.748189 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4936 00:56:43.751515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 00:56:43.758302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 00:56:43.761618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4939 00:56:43.767971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4940 00:56:43.771276 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4941 00:56:43.771360 [ANA_INIT] flow start
4942 00:56:43.774822 [ANA_INIT] PLL >>>>>>>>
4943 00:56:43.778053 [ANA_INIT] PLL <<<<<<<<
4944 00:56:43.778136 [ANA_INIT] MIDPI >>>>>>>>
4945 00:56:43.781432 [ANA_INIT] MIDPI <<<<<<<<
4946 00:56:43.784734 [ANA_INIT] DLL >>>>>>>>
4947 00:56:43.784817 [ANA_INIT] flow end
4948 00:56:43.788091 ============ LP4 DIFF to SE enter ============
4949 00:56:43.794705 ============ LP4 DIFF to SE exit ============
4950 00:56:43.794790 [ANA_INIT] <<<<<<<<<<<<<
4951 00:56:43.797987 [Flow] Enable top DCM control >>>>>
4952 00:56:43.801271 [Flow] Enable top DCM control <<<<<
4953 00:56:43.804872 Enable DLL master slave shuffle
4954 00:56:43.811173 ==============================================================
4955 00:56:43.811257 Gating Mode config
4956 00:56:43.818089 ==============================================================
4957 00:56:43.821329 Config description:
4958 00:56:43.831318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4959 00:56:43.837839 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4960 00:56:43.840960 SELPH_MODE 0: By rank 1: By Phase
4961 00:56:43.847695 ==============================================================
4962 00:56:43.851338 GAT_TRACK_EN = 1
4963 00:56:43.854599 RX_GATING_MODE = 2
4964 00:56:43.854680 RX_GATING_TRACK_MODE = 2
4965 00:56:43.858031 SELPH_MODE = 1
4966 00:56:43.861355 PICG_EARLY_EN = 1
4967 00:56:43.864437 VALID_LAT_VALUE = 1
4968 00:56:43.870944 ==============================================================
4969 00:56:43.874560 Enter into Gating configuration >>>>
4970 00:56:43.877694 Exit from Gating configuration <<<<
4971 00:56:43.880918 Enter into DVFS_PRE_config >>>>>
4972 00:56:43.891019 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4973 00:56:43.894095 Exit from DVFS_PRE_config <<<<<
4974 00:56:43.897662 Enter into PICG configuration >>>>
4975 00:56:43.901036 Exit from PICG configuration <<<<
4976 00:56:43.904430 [RX_INPUT] configuration >>>>>
4977 00:56:43.907640 [RX_INPUT] configuration <<<<<
4978 00:56:43.911056 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4979 00:56:43.917451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4980 00:56:43.924050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 00:56:43.930948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 00:56:43.934351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 00:56:43.940844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 00:56:43.943975 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4985 00:56:43.950717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4986 00:56:43.953861 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4987 00:56:43.957305 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4988 00:56:43.960590 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4989 00:56:43.967117 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 00:56:43.970363 ===================================
4991 00:56:43.973710 LPDDR4 DRAM CONFIGURATION
4992 00:56:43.977256 ===================================
4993 00:56:43.977339 EX_ROW_EN[0] = 0x0
4994 00:56:43.980417 EX_ROW_EN[1] = 0x0
4995 00:56:43.980501 LP4Y_EN = 0x0
4996 00:56:43.983569 WORK_FSP = 0x0
4997 00:56:43.983652 WL = 0x3
4998 00:56:43.986884 RL = 0x3
4999 00:56:43.986993 BL = 0x2
5000 00:56:43.990279 RPST = 0x0
5001 00:56:43.990381 RD_PRE = 0x0
5002 00:56:43.993601 WR_PRE = 0x1
5003 00:56:43.993685 WR_PST = 0x0
5004 00:56:43.996776 DBI_WR = 0x0
5005 00:56:43.996860 DBI_RD = 0x0
5006 00:56:44.000342 OTF = 0x1
5007 00:56:44.003609 ===================================
5008 00:56:44.007077 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5009 00:56:44.010296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5010 00:56:44.016867 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 00:56:44.020144 ===================================
5012 00:56:44.020231 LPDDR4 DRAM CONFIGURATION
5013 00:56:44.023557 ===================================
5014 00:56:44.026958 EX_ROW_EN[0] = 0x10
5015 00:56:44.030259 EX_ROW_EN[1] = 0x0
5016 00:56:44.030342 LP4Y_EN = 0x0
5017 00:56:44.033334 WORK_FSP = 0x0
5018 00:56:44.033437 WL = 0x3
5019 00:56:44.036658 RL = 0x3
5020 00:56:44.036754 BL = 0x2
5021 00:56:44.039921 RPST = 0x0
5022 00:56:44.040006 RD_PRE = 0x0
5023 00:56:44.043246 WR_PRE = 0x1
5024 00:56:44.043331 WR_PST = 0x0
5025 00:56:44.046885 DBI_WR = 0x0
5026 00:56:44.046982 DBI_RD = 0x0
5027 00:56:44.050045 OTF = 0x1
5028 00:56:44.053298 ===================================
5029 00:56:44.059905 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5030 00:56:44.063131 nWR fixed to 30
5031 00:56:44.066555 [ModeRegInit_LP4] CH0 RK0
5032 00:56:44.066705 [ModeRegInit_LP4] CH0 RK1
5033 00:56:44.069911 [ModeRegInit_LP4] CH1 RK0
5034 00:56:44.073286 [ModeRegInit_LP4] CH1 RK1
5035 00:56:44.073371 match AC timing 9
5036 00:56:44.079743 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5037 00:56:44.083256 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5038 00:56:44.086435 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5039 00:56:44.093269 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5040 00:56:44.096275 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5041 00:56:44.096359 ==
5042 00:56:44.099606 Dram Type= 6, Freq= 0, CH_0, rank 0
5043 00:56:44.103081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5044 00:56:44.103165 ==
5045 00:56:44.109471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5046 00:56:44.116332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5047 00:56:44.119731 [CA 0] Center 38 (8~69) winsize 62
5048 00:56:44.123074 [CA 1] Center 38 (7~69) winsize 63
5049 00:56:44.126416 [CA 2] Center 35 (5~66) winsize 62
5050 00:56:44.129690 [CA 3] Center 35 (5~65) winsize 61
5051 00:56:44.133120 [CA 4] Center 34 (4~65) winsize 62
5052 00:56:44.136390 [CA 5] Center 33 (3~64) winsize 62
5053 00:56:44.136473
5054 00:56:44.139476 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5055 00:56:44.139584
5056 00:56:44.143124 [CATrainingPosCal] consider 1 rank data
5057 00:56:44.146424 u2DelayCellTimex100 = 270/100 ps
5058 00:56:44.149467 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5059 00:56:44.152724 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5060 00:56:44.156225 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5061 00:56:44.159325 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5062 00:56:44.162801 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5063 00:56:44.166013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5064 00:56:44.169338
5065 00:56:44.172684 CA PerBit enable=1, Macro0, CA PI delay=33
5066 00:56:44.172767
5067 00:56:44.175847 [CBTSetCACLKResult] CA Dly = 33
5068 00:56:44.175930 CS Dly: 7 (0~38)
5069 00:56:44.175997 ==
5070 00:56:44.179575 Dram Type= 6, Freq= 0, CH_0, rank 1
5071 00:56:44.182745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 00:56:44.182829 ==
5073 00:56:44.189108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 00:56:44.195953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5075 00:56:44.199200 [CA 0] Center 38 (8~69) winsize 62
5076 00:56:44.202398 [CA 1] Center 38 (7~69) winsize 63
5077 00:56:44.205649 [CA 2] Center 35 (5~66) winsize 62
5078 00:56:44.209265 [CA 3] Center 35 (5~65) winsize 61
5079 00:56:44.212282 [CA 4] Center 34 (4~65) winsize 62
5080 00:56:44.215848 [CA 5] Center 34 (4~64) winsize 61
5081 00:56:44.215932
5082 00:56:44.219010 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5083 00:56:44.219094
5084 00:56:44.222367 [CATrainingPosCal] consider 2 rank data
5085 00:56:44.225771 u2DelayCellTimex100 = 270/100 ps
5086 00:56:44.228940 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5087 00:56:44.232367 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5088 00:56:44.235586 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5089 00:56:44.238945 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5090 00:56:44.245438 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5091 00:56:44.248710 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5092 00:56:44.248794
5093 00:56:44.252221 CA PerBit enable=1, Macro0, CA PI delay=34
5094 00:56:44.252305
5095 00:56:44.255503 [CBTSetCACLKResult] CA Dly = 34
5096 00:56:44.255586 CS Dly: 7 (0~39)
5097 00:56:44.255658
5098 00:56:44.258631 ----->DramcWriteLeveling(PI) begin...
5099 00:56:44.258717 ==
5100 00:56:44.262013 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 00:56:44.268579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 00:56:44.268664 ==
5103 00:56:44.272134 Write leveling (Byte 0): 32 => 32
5104 00:56:44.275428 Write leveling (Byte 1): 30 => 30
5105 00:56:44.275511 DramcWriteLeveling(PI) end<-----
5106 00:56:44.275577
5107 00:56:44.278624 ==
5108 00:56:44.281728 Dram Type= 6, Freq= 0, CH_0, rank 0
5109 00:56:44.285204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5110 00:56:44.285287 ==
5111 00:56:44.288668 [Gating] SW mode calibration
5112 00:56:44.294950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5113 00:56:44.298584 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5114 00:56:44.305071 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5115 00:56:44.308315 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5116 00:56:44.311381 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 00:56:44.318179 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 00:56:44.321601 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 00:56:44.325013 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 00:56:44.331617 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 00:56:44.334817 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5122 00:56:44.338097 0 15 0 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (1 0)
5123 00:56:44.344862 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5124 00:56:44.348152 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 00:56:44.351206 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 00:56:44.358038 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 00:56:44.361224 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 00:56:44.364412 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 00:56:44.371295 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5130 00:56:44.374454 1 0 0 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
5131 00:56:44.377909 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5132 00:56:44.384318 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 00:56:44.387707 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 00:56:44.390870 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 00:56:44.398134 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 00:56:44.400774 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 00:56:44.404225 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 00:56:44.410883 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 00:56:44.414207 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 00:56:44.417358 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 00:56:44.424222 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 00:56:44.427417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 00:56:44.430895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 00:56:44.437353 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 00:56:44.440419 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 00:56:44.443948 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 00:56:44.450584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 00:56:44.453703 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 00:56:44.456838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 00:56:44.463672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 00:56:44.466987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 00:56:44.470154 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 00:56:44.477225 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 00:56:44.480095 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5155 00:56:44.483661 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 00:56:44.486900 Total UI for P1: 0, mck2ui 16
5157 00:56:44.490131 best dqsien dly found for B0: ( 1, 3, 0)
5158 00:56:44.493441 Total UI for P1: 0, mck2ui 16
5159 00:56:44.496857 best dqsien dly found for B1: ( 1, 3, 2)
5160 00:56:44.499940 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5161 00:56:44.503456 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5162 00:56:44.503539
5163 00:56:44.506814 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5164 00:56:44.510034 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5165 00:56:44.513360 [Gating] SW calibration Done
5166 00:56:44.513482 ==
5167 00:56:44.516849 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 00:56:44.523546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 00:56:44.523631 ==
5170 00:56:44.523697 RX Vref Scan: 0
5171 00:56:44.523759
5172 00:56:44.526637 RX Vref 0 -> 0, step: 1
5173 00:56:44.526744
5174 00:56:44.530143 RX Delay -80 -> 252, step: 8
5175 00:56:44.533301 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5176 00:56:44.536510 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5177 00:56:44.540106 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5178 00:56:44.543235 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5179 00:56:44.546572 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5180 00:56:44.553277 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5181 00:56:44.556411 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5182 00:56:44.559927 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5183 00:56:44.563045 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5184 00:56:44.566451 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5185 00:56:44.573000 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5186 00:56:44.576238 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5187 00:56:44.579589 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5188 00:56:44.582809 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5189 00:56:44.586155 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5190 00:56:44.592913 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5191 00:56:44.593007 ==
5192 00:56:44.596172 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 00:56:44.599741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 00:56:44.599827 ==
5195 00:56:44.599896 DQS Delay:
5196 00:56:44.602891 DQS0 = 0, DQS1 = 0
5197 00:56:44.602977 DQM Delay:
5198 00:56:44.606067 DQM0 = 94, DQM1 = 83
5199 00:56:44.606152 DQ Delay:
5200 00:56:44.609689 DQ0 =95, DQ1 =95, DQ2 =91, DQ3 =91
5201 00:56:44.612857 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5202 00:56:44.615978 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5203 00:56:44.619565 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =91
5204 00:56:44.619657
5205 00:56:44.619728
5206 00:56:44.619791 ==
5207 00:56:44.622921 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 00:56:44.626028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 00:56:44.629440 ==
5210 00:56:44.629534
5211 00:56:44.629602
5212 00:56:44.629664 TX Vref Scan disable
5213 00:56:44.632700 == TX Byte 0 ==
5214 00:56:44.636018 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5215 00:56:44.639356 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5216 00:56:44.642951 == TX Byte 1 ==
5217 00:56:44.645910 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5218 00:56:44.649138 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5219 00:56:44.652560 ==
5220 00:56:44.652644 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 00:56:44.659282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 00:56:44.659367 ==
5223 00:56:44.659434
5224 00:56:44.659495
5225 00:56:44.662516 TX Vref Scan disable
5226 00:56:44.662603 == TX Byte 0 ==
5227 00:56:44.669322 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5228 00:56:44.672293 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5229 00:56:44.672376 == TX Byte 1 ==
5230 00:56:44.679110 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5231 00:56:44.682318 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5232 00:56:44.682401
5233 00:56:44.682468 [DATLAT]
5234 00:56:44.685859 Freq=933, CH0 RK0
5235 00:56:44.685945
5236 00:56:44.686012 DATLAT Default: 0xd
5237 00:56:44.688803 0, 0xFFFF, sum = 0
5238 00:56:44.688934 1, 0xFFFF, sum = 0
5239 00:56:44.692077 2, 0xFFFF, sum = 0
5240 00:56:44.692161 3, 0xFFFF, sum = 0
5241 00:56:44.695564 4, 0xFFFF, sum = 0
5242 00:56:44.695678 5, 0xFFFF, sum = 0
5243 00:56:44.698851 6, 0xFFFF, sum = 0
5244 00:56:44.698939 7, 0xFFFF, sum = 0
5245 00:56:44.702377 8, 0xFFFF, sum = 0
5246 00:56:44.705515 9, 0xFFFF, sum = 0
5247 00:56:44.705600 10, 0x0, sum = 1
5248 00:56:44.705668 11, 0x0, sum = 2
5249 00:56:44.709108 12, 0x0, sum = 3
5250 00:56:44.709193 13, 0x0, sum = 4
5251 00:56:44.712287 best_step = 11
5252 00:56:44.712371
5253 00:56:44.712438 ==
5254 00:56:44.715597 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 00:56:44.718716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 00:56:44.718844 ==
5257 00:56:44.722133 RX Vref Scan: 1
5258 00:56:44.722217
5259 00:56:44.722284 RX Vref 0 -> 0, step: 1
5260 00:56:44.722349
5261 00:56:44.725457 RX Delay -69 -> 252, step: 4
5262 00:56:44.725564
5263 00:56:44.728765 Set Vref, RX VrefLevel [Byte0]: 60
5264 00:56:44.732179 [Byte1]: 52
5265 00:56:44.736406
5266 00:56:44.736488 Final RX Vref Byte 0 = 60 to rank0
5267 00:56:44.739650 Final RX Vref Byte 1 = 52 to rank0
5268 00:56:44.743065 Final RX Vref Byte 0 = 60 to rank1
5269 00:56:44.746223 Final RX Vref Byte 1 = 52 to rank1==
5270 00:56:44.749758 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 00:56:44.756346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 00:56:44.756431 ==
5273 00:56:44.756498 DQS Delay:
5274 00:56:44.759731 DQS0 = 0, DQS1 = 0
5275 00:56:44.759814 DQM Delay:
5276 00:56:44.759881 DQM0 = 95, DQM1 = 83
5277 00:56:44.762969 DQ Delay:
5278 00:56:44.766003 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =92
5279 00:56:44.769514 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5280 00:56:44.772893 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =78
5281 00:56:44.775958 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5282 00:56:44.776061
5283 00:56:44.776179
5284 00:56:44.782895 [DQSOSCAuto] RK0, (LSB)MR18= 0x1413, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5285 00:56:44.785941 CH0 RK0: MR19=505, MR18=1413
5286 00:56:44.792759 CH0_RK0: MR19=0x505, MR18=0x1413, DQSOSC=415, MR23=63, INC=62, DEC=41
5287 00:56:44.792861
5288 00:56:44.795833 ----->DramcWriteLeveling(PI) begin...
5289 00:56:44.795918 ==
5290 00:56:44.799056 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 00:56:44.802599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 00:56:44.802684 ==
5293 00:56:44.805728 Write leveling (Byte 0): 31 => 31
5294 00:56:44.809199 Write leveling (Byte 1): 30 => 30
5295 00:56:44.812474 DramcWriteLeveling(PI) end<-----
5296 00:56:44.812556
5297 00:56:44.812622 ==
5298 00:56:44.816052 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 00:56:44.819312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 00:56:44.819395 ==
5301 00:56:44.822400 [Gating] SW mode calibration
5302 00:56:44.829082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5303 00:56:44.835867 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5304 00:56:44.839198 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5305 00:56:44.845613 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5306 00:56:44.848716 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 00:56:44.852464 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 00:56:44.858626 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 00:56:44.862277 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 00:56:44.865522 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 00:56:44.871998 0 14 28 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
5312 00:56:44.875337 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5313 00:56:44.878508 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 00:56:44.884975 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 00:56:44.888468 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 00:56:44.891968 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 00:56:44.898626 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 00:56:44.901776 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 00:56:44.904951 0 15 28 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
5320 00:56:44.911625 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5321 00:56:44.914877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 00:56:44.918400 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 00:56:44.924900 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 00:56:44.928177 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 00:56:44.931335 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 00:56:44.938052 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 00:56:44.941438 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5328 00:56:44.944513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5329 00:56:44.951160 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 00:56:44.954601 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 00:56:44.957970 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 00:56:44.964649 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 00:56:44.967849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 00:56:44.971091 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 00:56:44.974566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 00:56:44.981120 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 00:56:44.984629 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 00:56:44.987691 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 00:56:44.994358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 00:56:44.997671 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 00:56:45.000907 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 00:56:45.007514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 00:56:45.010804 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5344 00:56:45.014379 Total UI for P1: 0, mck2ui 16
5345 00:56:45.017454 best dqsien dly found for B0: ( 1, 2, 26)
5346 00:56:45.020552 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 00:56:45.024048 Total UI for P1: 0, mck2ui 16
5348 00:56:45.027394 best dqsien dly found for B1: ( 1, 2, 30)
5349 00:56:45.030733 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5350 00:56:45.037145 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5351 00:56:45.037254
5352 00:56:45.040814 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5353 00:56:45.044101 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5354 00:56:45.047387 [Gating] SW calibration Done
5355 00:56:45.047471 ==
5356 00:56:45.050564 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 00:56:45.053977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 00:56:45.054061 ==
5359 00:56:45.054128 RX Vref Scan: 0
5360 00:56:45.057296
5361 00:56:45.057378 RX Vref 0 -> 0, step: 1
5362 00:56:45.057445
5363 00:56:45.060769 RX Delay -80 -> 252, step: 8
5364 00:56:45.064069 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5365 00:56:45.067536 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5366 00:56:45.073887 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5367 00:56:45.077242 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5368 00:56:45.080425 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5369 00:56:45.083623 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5370 00:56:45.086960 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5371 00:56:45.093806 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5372 00:56:45.097053 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5373 00:56:45.100183 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5374 00:56:45.103554 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5375 00:56:45.106932 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5376 00:56:45.113440 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5377 00:56:45.117069 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5378 00:56:45.120285 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5379 00:56:45.123535 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5380 00:56:45.123619 ==
5381 00:56:45.126858 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 00:56:45.130166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 00:56:45.133430 ==
5384 00:56:45.133553 DQS Delay:
5385 00:56:45.133621 DQS0 = 0, DQS1 = 0
5386 00:56:45.136707 DQM Delay:
5387 00:56:45.136790 DQM0 = 91, DQM1 = 82
5388 00:56:45.140158 DQ Delay:
5389 00:56:45.143284 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5390 00:56:45.146507 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5391 00:56:45.150047 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5392 00:56:45.153317 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5393 00:56:45.153401
5394 00:56:45.153468
5395 00:56:45.153575 ==
5396 00:56:45.156617 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 00:56:45.160058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 00:56:45.160142 ==
5399 00:56:45.160208
5400 00:56:45.160270
5401 00:56:45.163142 TX Vref Scan disable
5402 00:56:45.163229 == TX Byte 0 ==
5403 00:56:45.169831 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5404 00:56:45.173128 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5405 00:56:45.173211 == TX Byte 1 ==
5406 00:56:45.179507 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5407 00:56:45.182814 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5408 00:56:45.182896 ==
5409 00:56:45.186072 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 00:56:45.189604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 00:56:45.189724 ==
5412 00:56:45.189831
5413 00:56:45.192981
5414 00:56:45.193063 TX Vref Scan disable
5415 00:56:45.196188 == TX Byte 0 ==
5416 00:56:45.199700 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5417 00:56:45.202698 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5418 00:56:45.206206 == TX Byte 1 ==
5419 00:56:45.209422 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5420 00:56:45.212838 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5421 00:56:45.215994
5422 00:56:45.216091 [DATLAT]
5423 00:56:45.216187 Freq=933, CH0 RK1
5424 00:56:45.216280
5425 00:56:45.219552 DATLAT Default: 0xb
5426 00:56:45.219663 0, 0xFFFF, sum = 0
5427 00:56:45.222527 1, 0xFFFF, sum = 0
5428 00:56:45.222639 2, 0xFFFF, sum = 0
5429 00:56:45.225718 3, 0xFFFF, sum = 0
5430 00:56:45.229353 4, 0xFFFF, sum = 0
5431 00:56:45.229487 5, 0xFFFF, sum = 0
5432 00:56:45.232467 6, 0xFFFF, sum = 0
5433 00:56:45.232551 7, 0xFFFF, sum = 0
5434 00:56:45.235901 8, 0xFFFF, sum = 0
5435 00:56:45.235985 9, 0xFFFF, sum = 0
5436 00:56:45.239115 10, 0x0, sum = 1
5437 00:56:45.239199 11, 0x0, sum = 2
5438 00:56:45.242512 12, 0x0, sum = 3
5439 00:56:45.242623 13, 0x0, sum = 4
5440 00:56:45.242724 best_step = 11
5441 00:56:45.242816
5442 00:56:45.245896 ==
5443 00:56:45.249087 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 00:56:45.252343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 00:56:45.252454 ==
5446 00:56:45.252522 RX Vref Scan: 0
5447 00:56:45.252584
5448 00:56:45.255563 RX Vref 0 -> 0, step: 1
5449 00:56:45.255646
5450 00:56:45.258785 RX Delay -77 -> 252, step: 4
5451 00:56:45.265387 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5452 00:56:45.268809 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5453 00:56:45.272051 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5454 00:56:45.275549 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5455 00:56:45.278959 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5456 00:56:45.282218 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5457 00:56:45.288569 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5458 00:56:45.292107 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5459 00:56:45.295346 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5460 00:56:45.298569 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5461 00:56:45.301791 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5462 00:56:45.308418 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5463 00:56:45.311905 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5464 00:56:45.314919 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5465 00:56:45.318554 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5466 00:56:45.321612 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5467 00:56:45.321696 ==
5468 00:56:45.325023 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 00:56:45.331687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 00:56:45.331797 ==
5471 00:56:45.331867 DQS Delay:
5472 00:56:45.334883 DQS0 = 0, DQS1 = 0
5473 00:56:45.334966 DQM Delay:
5474 00:56:45.338389 DQM0 = 91, DQM1 = 84
5475 00:56:45.338497 DQ Delay:
5476 00:56:45.341593 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5477 00:56:45.345025 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =102
5478 00:56:45.348251 DQ8 =80, DQ9 =70, DQ10 =86, DQ11 =76
5479 00:56:45.351404 DQ12 =92, DQ13 =90, DQ14 =94, DQ15 =90
5480 00:56:45.351487
5481 00:56:45.351552
5482 00:56:45.358187 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5483 00:56:45.361343 CH0 RK1: MR19=505, MR18=2D0F
5484 00:56:45.367947 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5485 00:56:45.371362 [RxdqsGatingPostProcess] freq 933
5486 00:56:45.378011 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5487 00:56:45.378119 best DQS0 dly(2T, 0.5T) = (0, 11)
5488 00:56:45.381451 best DQS1 dly(2T, 0.5T) = (0, 11)
5489 00:56:45.384592 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5490 00:56:45.387974 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5491 00:56:45.391326 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 00:56:45.394399 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 00:56:45.397842 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 00:56:45.400863 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 00:56:45.404289 Pre-setting of DQS Precalculation
5496 00:56:45.410847 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5497 00:56:45.410932 ==
5498 00:56:45.414349 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 00:56:45.417414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 00:56:45.417531 ==
5501 00:56:45.424045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5502 00:56:45.427550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5503 00:56:45.431519 [CA 0] Center 37 (7~67) winsize 61
5504 00:56:45.434787 [CA 1] Center 37 (7~68) winsize 62
5505 00:56:45.438401 [CA 2] Center 34 (5~64) winsize 60
5506 00:56:45.441619 [CA 3] Center 34 (4~64) winsize 61
5507 00:56:45.444843 [CA 4] Center 34 (5~64) winsize 60
5508 00:56:45.448445 [CA 5] Center 34 (4~64) winsize 61
5509 00:56:45.448557
5510 00:56:45.451274 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5511 00:56:45.451350
5512 00:56:45.455006 [CATrainingPosCal] consider 1 rank data
5513 00:56:45.458045 u2DelayCellTimex100 = 270/100 ps
5514 00:56:45.461373 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5515 00:56:45.465044 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5516 00:56:45.471594 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5517 00:56:45.474810 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5518 00:56:45.478279 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5519 00:56:45.481255 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5520 00:56:45.481364
5521 00:56:45.484645 CA PerBit enable=1, Macro0, CA PI delay=34
5522 00:56:45.484747
5523 00:56:45.488036 [CBTSetCACLKResult] CA Dly = 34
5524 00:56:45.488136 CS Dly: 6 (0~37)
5525 00:56:45.491333 ==
5526 00:56:45.494679 Dram Type= 6, Freq= 0, CH_1, rank 1
5527 00:56:45.497786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 00:56:45.497871 ==
5529 00:56:45.501400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5530 00:56:45.507884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5531 00:56:45.511700 [CA 0] Center 37 (7~67) winsize 61
5532 00:56:45.514820 [CA 1] Center 37 (7~68) winsize 62
5533 00:56:45.517932 [CA 2] Center 35 (5~65) winsize 61
5534 00:56:45.521208 [CA 3] Center 34 (4~64) winsize 61
5535 00:56:45.524642 [CA 4] Center 35 (5~65) winsize 61
5536 00:56:45.527876 [CA 5] Center 33 (3~64) winsize 62
5537 00:56:45.527955
5538 00:56:45.531275 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5539 00:56:45.531414
5540 00:56:45.534635 [CATrainingPosCal] consider 2 rank data
5541 00:56:45.537768 u2DelayCellTimex100 = 270/100 ps
5542 00:56:45.540945 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5543 00:56:45.547827 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5544 00:56:45.550998 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5545 00:56:45.554401 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5546 00:56:45.557559 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5547 00:56:45.560772 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5548 00:56:45.560856
5549 00:56:45.564097 CA PerBit enable=1, Macro0, CA PI delay=34
5550 00:56:45.564198
5551 00:56:45.567427 [CBTSetCACLKResult] CA Dly = 34
5552 00:56:45.570850 CS Dly: 7 (0~39)
5553 00:56:45.570956
5554 00:56:45.574176 ----->DramcWriteLeveling(PI) begin...
5555 00:56:45.574283 ==
5556 00:56:45.577345 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 00:56:45.580873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 00:56:45.580969 ==
5559 00:56:45.583932 Write leveling (Byte 0): 27 => 27
5560 00:56:45.587528 Write leveling (Byte 1): 28 => 28
5561 00:56:45.590815 DramcWriteLeveling(PI) end<-----
5562 00:56:45.590907
5563 00:56:45.590992 ==
5564 00:56:45.593906 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 00:56:45.597281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 00:56:45.597381 ==
5567 00:56:45.600559 [Gating] SW mode calibration
5568 00:56:45.607079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5569 00:56:45.613892 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5570 00:56:45.616934 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5571 00:56:45.620316 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 00:56:45.627125 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 00:56:45.630574 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 00:56:45.633621 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 00:56:45.640305 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 00:56:45.643632 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 00:56:45.647037 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5578 00:56:45.653446 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 00:56:45.657013 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 00:56:45.660165 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 00:56:45.666835 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 00:56:45.670148 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 00:56:45.673435 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 00:56:45.680164 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 00:56:45.683324 0 15 28 | B1->B0 | 3333 3333 | 0 1 | (0 0) (0 0)
5586 00:56:45.686744 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5587 00:56:45.693362 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 00:56:45.696465 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 00:56:45.699638 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 00:56:45.706509 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 00:56:45.709809 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 00:56:45.712927 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 00:56:45.719824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5594 00:56:45.723265 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 00:56:45.726410 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 00:56:45.732998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 00:56:45.736167 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 00:56:45.739469 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 00:56:45.746199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 00:56:45.749515 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 00:56:45.752796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 00:56:45.759272 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 00:56:45.762605 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 00:56:45.766077 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 00:56:45.772623 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 00:56:45.775771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 00:56:45.779069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 00:56:45.785869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5609 00:56:45.788947 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5610 00:56:45.792378 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 00:56:45.795543 Total UI for P1: 0, mck2ui 16
5612 00:56:45.799226 best dqsien dly found for B0: ( 1, 2, 28)
5613 00:56:45.802377 Total UI for P1: 0, mck2ui 16
5614 00:56:45.805632 best dqsien dly found for B1: ( 1, 2, 26)
5615 00:56:45.809077 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5616 00:56:45.812307 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5617 00:56:45.812384
5618 00:56:45.815507 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5619 00:56:45.822191 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5620 00:56:45.822302 [Gating] SW calibration Done
5621 00:56:45.825591 ==
5622 00:56:45.825669 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 00:56:45.832288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 00:56:45.832366 ==
5625 00:56:45.832436 RX Vref Scan: 0
5626 00:56:45.832497
5627 00:56:45.835415 RX Vref 0 -> 0, step: 1
5628 00:56:45.835512
5629 00:56:45.838542 RX Delay -80 -> 252, step: 8
5630 00:56:45.842182 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5631 00:56:45.845500 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5632 00:56:45.848664 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5633 00:56:45.855329 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5634 00:56:45.858928 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5635 00:56:45.861816 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5636 00:56:45.865296 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5637 00:56:45.868465 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5638 00:56:45.872033 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5639 00:56:45.878512 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5640 00:56:45.881606 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5641 00:56:45.885281 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5642 00:56:45.888271 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5643 00:56:45.891785 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5644 00:56:45.898526 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5645 00:56:45.901687 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5646 00:56:45.901763 ==
5647 00:56:45.905130 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 00:56:45.908537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 00:56:45.908621 ==
5650 00:56:45.911555 DQS Delay:
5651 00:56:45.911637 DQS0 = 0, DQS1 = 0
5652 00:56:45.911703 DQM Delay:
5653 00:56:45.914868 DQM0 = 94, DQM1 = 87
5654 00:56:45.914949 DQ Delay:
5655 00:56:45.918406 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5656 00:56:45.921673 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5657 00:56:45.925026 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5658 00:56:45.928213 DQ12 =99, DQ13 =91, DQ14 =91, DQ15 =91
5659 00:56:45.928295
5660 00:56:45.928378
5661 00:56:45.928440 ==
5662 00:56:45.931410 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 00:56:45.938092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 00:56:45.938175 ==
5665 00:56:45.938241
5666 00:56:45.938301
5667 00:56:45.938358 TX Vref Scan disable
5668 00:56:45.941718 == TX Byte 0 ==
5669 00:56:45.945043 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5670 00:56:45.948360 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5671 00:56:45.951605 == TX Byte 1 ==
5672 00:56:45.954699 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 00:56:45.961515 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 00:56:45.961598 ==
5675 00:56:45.964610 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 00:56:45.968185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 00:56:45.968290 ==
5678 00:56:45.968384
5679 00:56:45.968479
5680 00:56:45.971207 TX Vref Scan disable
5681 00:56:45.971310 == TX Byte 0 ==
5682 00:56:45.977911 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5683 00:56:45.981158 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5684 00:56:45.981260 == TX Byte 1 ==
5685 00:56:45.987756 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5686 00:56:45.991149 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5687 00:56:45.991254
5688 00:56:45.991361 [DATLAT]
5689 00:56:45.994398 Freq=933, CH1 RK0
5690 00:56:45.994499
5691 00:56:45.994591 DATLAT Default: 0xd
5692 00:56:45.997913 0, 0xFFFF, sum = 0
5693 00:56:45.998017 1, 0xFFFF, sum = 0
5694 00:56:46.001116 2, 0xFFFF, sum = 0
5695 00:56:46.004262 3, 0xFFFF, sum = 0
5696 00:56:46.004366 4, 0xFFFF, sum = 0
5697 00:56:46.007751 5, 0xFFFF, sum = 0
5698 00:56:46.007859 6, 0xFFFF, sum = 0
5699 00:56:46.011192 7, 0xFFFF, sum = 0
5700 00:56:46.011299 8, 0xFFFF, sum = 0
5701 00:56:46.014558 9, 0xFFFF, sum = 0
5702 00:56:46.014634 10, 0x0, sum = 1
5703 00:56:46.017662 11, 0x0, sum = 2
5704 00:56:46.017775 12, 0x0, sum = 3
5705 00:56:46.017871 13, 0x0, sum = 4
5706 00:56:46.020988 best_step = 11
5707 00:56:46.021090
5708 00:56:46.021190 ==
5709 00:56:46.024319 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 00:56:46.027633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 00:56:46.027709 ==
5712 00:56:46.031172 RX Vref Scan: 1
5713 00:56:46.031273
5714 00:56:46.034173 RX Vref 0 -> 0, step: 1
5715 00:56:46.034274
5716 00:56:46.034365 RX Delay -61 -> 252, step: 4
5717 00:56:46.034462
5718 00:56:46.037470 Set Vref, RX VrefLevel [Byte0]: 57
5719 00:56:46.040766 [Byte1]: 49
5720 00:56:46.045352
5721 00:56:46.045466 Final RX Vref Byte 0 = 57 to rank0
5722 00:56:46.049009 Final RX Vref Byte 1 = 49 to rank0
5723 00:56:46.052191 Final RX Vref Byte 0 = 57 to rank1
5724 00:56:46.055682 Final RX Vref Byte 1 = 49 to rank1==
5725 00:56:46.058994 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 00:56:46.065413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 00:56:46.065552 ==
5728 00:56:46.065675 DQS Delay:
5729 00:56:46.065783 DQS0 = 0, DQS1 = 0
5730 00:56:46.068636 DQM Delay:
5731 00:56:46.068732 DQM0 = 97, DQM1 = 88
5732 00:56:46.072252 DQ Delay:
5733 00:56:46.075453 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5734 00:56:46.078761 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5735 00:56:46.082032 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5736 00:56:46.085246 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5737 00:56:46.085329
5738 00:56:46.085395
5739 00:56:46.091891 [DQSOSCAuto] RK0, (LSB)MR18= 0x30c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5740 00:56:46.095196 CH1 RK0: MR19=505, MR18=30C
5741 00:56:46.101925 CH1_RK0: MR19=0x505, MR18=0x30C, DQSOSC=418, MR23=63, INC=62, DEC=41
5742 00:56:46.102035
5743 00:56:46.105114 ----->DramcWriteLeveling(PI) begin...
5744 00:56:46.105217 ==
5745 00:56:46.108539 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 00:56:46.111653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 00:56:46.111729 ==
5748 00:56:46.114896 Write leveling (Byte 0): 26 => 26
5749 00:56:46.118395 Write leveling (Byte 1): 26 => 26
5750 00:56:46.121575 DramcWriteLeveling(PI) end<-----
5751 00:56:46.121684
5752 00:56:46.121795 ==
5753 00:56:46.125020 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 00:56:46.128176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 00:56:46.128259 ==
5756 00:56:46.131509 [Gating] SW mode calibration
5757 00:56:46.138447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5758 00:56:46.144761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5759 00:56:46.148199 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5760 00:56:46.154931 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 00:56:46.158215 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 00:56:46.161363 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 00:56:46.167765 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 00:56:46.171410 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 00:56:46.174724 0 14 24 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
5766 00:56:46.181268 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5767 00:56:46.184510 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5768 00:56:46.187854 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 00:56:46.194391 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 00:56:46.197663 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 00:56:46.201060 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 00:56:46.204439 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 00:56:46.210999 0 15 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
5774 00:56:46.214245 0 15 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5775 00:56:46.217576 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 00:56:46.224321 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 00:56:46.227474 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 00:56:46.230710 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 00:56:46.237361 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 00:56:46.240575 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5781 00:56:46.244151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5782 00:56:46.250530 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5783 00:56:46.254126 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 00:56:46.257296 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 00:56:46.264059 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 00:56:46.267229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 00:56:46.270735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 00:56:46.277276 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 00:56:46.280843 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 00:56:46.283870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 00:56:46.290517 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 00:56:46.293944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 00:56:46.297342 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 00:56:46.303899 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 00:56:46.307154 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 00:56:46.310711 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5797 00:56:46.317113 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5798 00:56:46.320366 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5799 00:56:46.323742 Total UI for P1: 0, mck2ui 16
5800 00:56:46.327080 best dqsien dly found for B0: ( 1, 2, 22)
5801 00:56:46.330420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 00:56:46.333563 Total UI for P1: 0, mck2ui 16
5803 00:56:46.337189 best dqsien dly found for B1: ( 1, 2, 28)
5804 00:56:46.340213 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5805 00:56:46.343627 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5806 00:56:46.343742
5807 00:56:46.350228 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5808 00:56:46.353735 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5809 00:56:46.353851 [Gating] SW calibration Done
5810 00:56:46.356951 ==
5811 00:56:46.360053 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 00:56:46.363707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 00:56:46.363795 ==
5814 00:56:46.363862 RX Vref Scan: 0
5815 00:56:46.363925
5816 00:56:46.366758 RX Vref 0 -> 0, step: 1
5817 00:56:46.366842
5818 00:56:46.370261 RX Delay -80 -> 252, step: 8
5819 00:56:46.373260 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5820 00:56:46.376613 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5821 00:56:46.380074 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5822 00:56:46.386505 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5823 00:56:46.390165 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5824 00:56:46.393316 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5825 00:56:46.396527 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5826 00:56:46.399922 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5827 00:56:46.403486 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5828 00:56:46.409845 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5829 00:56:46.413090 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5830 00:56:46.416410 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5831 00:56:46.419998 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5832 00:56:46.423049 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5833 00:56:46.429513 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5834 00:56:46.432886 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5835 00:56:46.433001 ==
5836 00:56:46.436149 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 00:56:46.439672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 00:56:46.439758 ==
5839 00:56:46.439826 DQS Delay:
5840 00:56:46.442898 DQS0 = 0, DQS1 = 0
5841 00:56:46.442982 DQM Delay:
5842 00:56:46.446238 DQM0 = 94, DQM1 = 89
5843 00:56:46.446322 DQ Delay:
5844 00:56:46.449799 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5845 00:56:46.452870 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5846 00:56:46.456125 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5847 00:56:46.459525 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5848 00:56:46.459621
5849 00:56:46.459702
5850 00:56:46.459794 ==
5851 00:56:46.462917 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 00:56:46.469471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 00:56:46.469605 ==
5854 00:56:46.469714
5855 00:56:46.469816
5856 00:56:46.469883 TX Vref Scan disable
5857 00:56:46.472760 == TX Byte 0 ==
5858 00:56:46.476119 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5859 00:56:46.479599 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5860 00:56:46.482803 == TX Byte 1 ==
5861 00:56:46.486021 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5862 00:56:46.489636 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5863 00:56:46.492947 ==
5864 00:56:46.495893 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 00:56:46.499326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 00:56:46.499432 ==
5867 00:56:46.499530
5868 00:56:46.499622
5869 00:56:46.503070 TX Vref Scan disable
5870 00:56:46.503181 == TX Byte 0 ==
5871 00:56:46.509212 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5872 00:56:46.512593 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5873 00:56:46.512667 == TX Byte 1 ==
5874 00:56:46.519310 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5875 00:56:46.522441 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5876 00:56:46.522550
5877 00:56:46.522644 [DATLAT]
5878 00:56:46.525823 Freq=933, CH1 RK1
5879 00:56:46.525907
5880 00:56:46.525973 DATLAT Default: 0xb
5881 00:56:46.529248 0, 0xFFFF, sum = 0
5882 00:56:46.529347 1, 0xFFFF, sum = 0
5883 00:56:46.532378 2, 0xFFFF, sum = 0
5884 00:56:46.532490 3, 0xFFFF, sum = 0
5885 00:56:46.535957 4, 0xFFFF, sum = 0
5886 00:56:46.539184 5, 0xFFFF, sum = 0
5887 00:56:46.539272 6, 0xFFFF, sum = 0
5888 00:56:46.542429 7, 0xFFFF, sum = 0
5889 00:56:46.542530 8, 0xFFFF, sum = 0
5890 00:56:46.545747 9, 0xFFFF, sum = 0
5891 00:56:46.545836 10, 0x0, sum = 1
5892 00:56:46.548901 11, 0x0, sum = 2
5893 00:56:46.548988 12, 0x0, sum = 3
5894 00:56:46.549093 13, 0x0, sum = 4
5895 00:56:46.552405 best_step = 11
5896 00:56:46.552491
5897 00:56:46.552577 ==
5898 00:56:46.555616 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 00:56:46.559101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 00:56:46.559189 ==
5901 00:56:46.562234 RX Vref Scan: 0
5902 00:56:46.562320
5903 00:56:46.562409 RX Vref 0 -> 0, step: 1
5904 00:56:46.565635
5905 00:56:46.565722 RX Delay -69 -> 252, step: 4
5906 00:56:46.573123 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5907 00:56:46.576368 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5908 00:56:46.579958 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5909 00:56:46.583266 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5910 00:56:46.586310 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5911 00:56:46.592955 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5912 00:56:46.596445 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5913 00:56:46.599600 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5914 00:56:46.603105 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5915 00:56:46.606591 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5916 00:56:46.609763 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5917 00:56:46.616263 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5918 00:56:46.619474 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5919 00:56:46.622713 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5920 00:56:46.626318 iDelay=203, Bit 14, Center 102 (15 ~ 190) 176
5921 00:56:46.632918 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5922 00:56:46.633003 ==
5923 00:56:46.635904 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 00:56:46.639281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 00:56:46.639369 ==
5926 00:56:46.639457 DQS Delay:
5927 00:56:46.642550 DQS0 = 0, DQS1 = 0
5928 00:56:46.642637 DQM Delay:
5929 00:56:46.645902 DQM0 = 91, DQM1 = 91
5930 00:56:46.645988 DQ Delay:
5931 00:56:46.649135 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
5932 00:56:46.652489 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
5933 00:56:46.656037 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =82
5934 00:56:46.659200 DQ12 =100, DQ13 =96, DQ14 =102, DQ15 =96
5935 00:56:46.659285
5936 00:56:46.659401
5937 00:56:46.665865 [DQSOSCAuto] RK1, (LSB)MR18= 0x1326, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5938 00:56:46.669210 CH1 RK1: MR19=505, MR18=1326
5939 00:56:46.675903 CH1_RK1: MR19=0x505, MR18=0x1326, DQSOSC=409, MR23=63, INC=64, DEC=43
5940 00:56:46.679297 [RxdqsGatingPostProcess] freq 933
5941 00:56:46.686124 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5942 00:56:46.689439 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 00:56:46.689566 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 00:56:46.692514 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 00:56:46.695840 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 00:56:46.699289 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 00:56:46.702539 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 00:56:46.705805 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 00:56:46.708955 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 00:56:46.712287 Pre-setting of DQS Precalculation
5951 00:56:46.719065 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5952 00:56:46.725417 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5953 00:56:46.732369 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5954 00:56:46.732459
5955 00:56:46.732547
5956 00:56:46.735700 [Calibration Summary] 1866 Mbps
5957 00:56:46.735786 CH 0, Rank 0
5958 00:56:46.738949 SW Impedance : PASS
5959 00:56:46.742116 DUTY Scan : NO K
5960 00:56:46.742202 ZQ Calibration : PASS
5961 00:56:46.745343 Jitter Meter : NO K
5962 00:56:46.748821 CBT Training : PASS
5963 00:56:46.748906 Write leveling : PASS
5964 00:56:46.752015 RX DQS gating : PASS
5965 00:56:46.755545 RX DQ/DQS(RDDQC) : PASS
5966 00:56:46.755630 TX DQ/DQS : PASS
5967 00:56:46.758722 RX DATLAT : PASS
5968 00:56:46.761982 RX DQ/DQS(Engine): PASS
5969 00:56:46.762067 TX OE : NO K
5970 00:56:46.762154 All Pass.
5971 00:56:46.765428
5972 00:56:46.765523 CH 0, Rank 1
5973 00:56:46.768564 SW Impedance : PASS
5974 00:56:46.768649 DUTY Scan : NO K
5975 00:56:46.771949 ZQ Calibration : PASS
5976 00:56:46.775225 Jitter Meter : NO K
5977 00:56:46.775311 CBT Training : PASS
5978 00:56:46.778555 Write leveling : PASS
5979 00:56:46.778643 RX DQS gating : PASS
5980 00:56:46.781939 RX DQ/DQS(RDDQC) : PASS
5981 00:56:46.785101 TX DQ/DQS : PASS
5982 00:56:46.785187 RX DATLAT : PASS
5983 00:56:46.788405 RX DQ/DQS(Engine): PASS
5984 00:56:46.791792 TX OE : NO K
5985 00:56:46.791879 All Pass.
5986 00:56:46.791966
5987 00:56:46.792048 CH 1, Rank 0
5988 00:56:46.794965 SW Impedance : PASS
5989 00:56:46.798213 DUTY Scan : NO K
5990 00:56:46.798298 ZQ Calibration : PASS
5991 00:56:46.801467 Jitter Meter : NO K
5992 00:56:46.804933 CBT Training : PASS
5993 00:56:46.805018 Write leveling : PASS
5994 00:56:46.808102 RX DQS gating : PASS
5995 00:56:46.811611 RX DQ/DQS(RDDQC) : PASS
5996 00:56:46.811696 TX DQ/DQS : PASS
5997 00:56:46.814823 RX DATLAT : PASS
5998 00:56:46.818029 RX DQ/DQS(Engine): PASS
5999 00:56:46.818113 TX OE : NO K
6000 00:56:46.821226 All Pass.
6001 00:56:46.821358
6002 00:56:46.821468 CH 1, Rank 1
6003 00:56:46.824740 SW Impedance : PASS
6004 00:56:46.824824 DUTY Scan : NO K
6005 00:56:46.827974 ZQ Calibration : PASS
6006 00:56:46.831594 Jitter Meter : NO K
6007 00:56:46.831679 CBT Training : PASS
6008 00:56:46.834720 Write leveling : PASS
6009 00:56:46.837939 RX DQS gating : PASS
6010 00:56:46.838023 RX DQ/DQS(RDDQC) : PASS
6011 00:56:46.841211 TX DQ/DQS : PASS
6012 00:56:46.841296 RX DATLAT : PASS
6013 00:56:46.844718 RX DQ/DQS(Engine): PASS
6014 00:56:46.847968 TX OE : NO K
6015 00:56:46.848049 All Pass.
6016 00:56:46.848114
6017 00:56:46.851222 DramC Write-DBI off
6018 00:56:46.854483 PER_BANK_REFRESH: Hybrid Mode
6019 00:56:46.854564 TX_TRACKING: ON
6020 00:56:46.864433 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6021 00:56:46.867667 [FAST_K] Save calibration result to emmc
6022 00:56:46.870904 dramc_set_vcore_voltage set vcore to 650000
6023 00:56:46.874255 Read voltage for 400, 6
6024 00:56:46.874335 Vio18 = 0
6025 00:56:46.874400 Vcore = 650000
6026 00:56:46.877730 Vdram = 0
6027 00:56:46.877811 Vddq = 0
6028 00:56:46.877877 Vmddr = 0
6029 00:56:46.884326 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6030 00:56:46.887697 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6031 00:56:46.891058 MEM_TYPE=3, freq_sel=20
6032 00:56:46.894140 sv_algorithm_assistance_LP4_800
6033 00:56:46.897720 ============ PULL DRAM RESETB DOWN ============
6034 00:56:46.900983 ========== PULL DRAM RESETB DOWN end =========
6035 00:56:46.907448 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6036 00:56:46.910685 ===================================
6037 00:56:46.910767 LPDDR4 DRAM CONFIGURATION
6038 00:56:46.913937 ===================================
6039 00:56:46.917328 EX_ROW_EN[0] = 0x0
6040 00:56:46.920556 EX_ROW_EN[1] = 0x0
6041 00:56:46.920638 LP4Y_EN = 0x0
6042 00:56:46.923842 WORK_FSP = 0x0
6043 00:56:46.923924 WL = 0x2
6044 00:56:46.927363 RL = 0x2
6045 00:56:46.927445 BL = 0x2
6046 00:56:46.930612 RPST = 0x0
6047 00:56:46.930693 RD_PRE = 0x0
6048 00:56:46.934047 WR_PRE = 0x1
6049 00:56:46.934128 WR_PST = 0x0
6050 00:56:46.937352 DBI_WR = 0x0
6051 00:56:46.937459 DBI_RD = 0x0
6052 00:56:46.940639 OTF = 0x1
6053 00:56:46.943890 ===================================
6054 00:56:46.947419 ===================================
6055 00:56:46.947501 ANA top config
6056 00:56:46.950670 ===================================
6057 00:56:46.953952 DLL_ASYNC_EN = 0
6058 00:56:46.957042 ALL_SLAVE_EN = 1
6059 00:56:46.960543 NEW_RANK_MODE = 1
6060 00:56:46.960634 DLL_IDLE_MODE = 1
6061 00:56:46.963764 LP45_APHY_COMB_EN = 1
6062 00:56:46.967134 TX_ODT_DIS = 1
6063 00:56:46.970483 NEW_8X_MODE = 1
6064 00:56:46.973666 ===================================
6065 00:56:46.976886 ===================================
6066 00:56:46.980406 data_rate = 800
6067 00:56:46.980488 CKR = 1
6068 00:56:46.983671 DQ_P2S_RATIO = 4
6069 00:56:46.987233 ===================================
6070 00:56:46.990493 CA_P2S_RATIO = 4
6071 00:56:46.993656 DQ_CA_OPEN = 0
6072 00:56:46.997010 DQ_SEMI_OPEN = 1
6073 00:56:47.000024 CA_SEMI_OPEN = 1
6074 00:56:47.000133 CA_FULL_RATE = 0
6075 00:56:47.003596 DQ_CKDIV4_EN = 0
6076 00:56:47.006615 CA_CKDIV4_EN = 1
6077 00:56:47.009988 CA_PREDIV_EN = 0
6078 00:56:47.013628 PH8_DLY = 0
6079 00:56:47.013710 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6080 00:56:47.016770 DQ_AAMCK_DIV = 0
6081 00:56:47.019961 CA_AAMCK_DIV = 0
6082 00:56:47.023360 CA_ADMCK_DIV = 4
6083 00:56:47.026692 DQ_TRACK_CA_EN = 0
6084 00:56:47.029877 CA_PICK = 800
6085 00:56:47.033512 CA_MCKIO = 400
6086 00:56:47.033608 MCKIO_SEMI = 400
6087 00:56:47.036801 PLL_FREQ = 3016
6088 00:56:47.039953 DQ_UI_PI_RATIO = 32
6089 00:56:47.043139 CA_UI_PI_RATIO = 32
6090 00:56:47.046630 ===================================
6091 00:56:47.049921 ===================================
6092 00:56:47.053381 memory_type:LPDDR4
6093 00:56:47.053462 GP_NUM : 10
6094 00:56:47.056391 SRAM_EN : 1
6095 00:56:47.059903 MD32_EN : 0
6096 00:56:47.063123 ===================================
6097 00:56:47.063204 [ANA_INIT] >>>>>>>>>>>>>>
6098 00:56:47.066539 <<<<<< [CONFIGURE PHASE]: ANA_TX
6099 00:56:47.069750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6100 00:56:47.073340 ===================================
6101 00:56:47.076297 data_rate = 800,PCW = 0X7400
6102 00:56:47.079879 ===================================
6103 00:56:47.083069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6104 00:56:47.089751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6105 00:56:47.099696 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 00:56:47.106056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6107 00:56:47.109629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6108 00:56:47.112867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6109 00:56:47.112949 [ANA_INIT] flow start
6110 00:56:47.115995 [ANA_INIT] PLL >>>>>>>>
6111 00:56:47.119242 [ANA_INIT] PLL <<<<<<<<
6112 00:56:47.119323 [ANA_INIT] MIDPI >>>>>>>>
6113 00:56:47.122644 [ANA_INIT] MIDPI <<<<<<<<
6114 00:56:47.125871 [ANA_INIT] DLL >>>>>>>>
6115 00:56:47.125952 [ANA_INIT] flow end
6116 00:56:47.132640 ============ LP4 DIFF to SE enter ============
6117 00:56:47.135973 ============ LP4 DIFF to SE exit ============
6118 00:56:47.139152 [ANA_INIT] <<<<<<<<<<<<<
6119 00:56:47.142561 [Flow] Enable top DCM control >>>>>
6120 00:56:47.145922 [Flow] Enable top DCM control <<<<<
6121 00:56:47.146004 Enable DLL master slave shuffle
6122 00:56:47.152549 ==============================================================
6123 00:56:47.155769 Gating Mode config
6124 00:56:47.158927 ==============================================================
6125 00:56:47.162458 Config description:
6126 00:56:47.172285 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6127 00:56:47.179117 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6128 00:56:47.182346 SELPH_MODE 0: By rank 1: By Phase
6129 00:56:47.188966 ==============================================================
6130 00:56:47.192294 GAT_TRACK_EN = 0
6131 00:56:47.195745 RX_GATING_MODE = 2
6132 00:56:47.198954 RX_GATING_TRACK_MODE = 2
6133 00:56:47.202306 SELPH_MODE = 1
6134 00:56:47.205588 PICG_EARLY_EN = 1
6135 00:56:47.205670 VALID_LAT_VALUE = 1
6136 00:56:47.212076 ==============================================================
6137 00:56:47.215262 Enter into Gating configuration >>>>
6138 00:56:47.218608 Exit from Gating configuration <<<<
6139 00:56:47.222060 Enter into DVFS_PRE_config >>>>>
6140 00:56:47.232095 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6141 00:56:47.235337 Exit from DVFS_PRE_config <<<<<
6142 00:56:47.238716 Enter into PICG configuration >>>>
6143 00:56:47.241776 Exit from PICG configuration <<<<
6144 00:56:47.245100 [RX_INPUT] configuration >>>>>
6145 00:56:47.248523 [RX_INPUT] configuration <<<<<
6146 00:56:47.251830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6147 00:56:47.258270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6148 00:56:47.265096 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 00:56:47.271679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 00:56:47.278343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 00:56:47.285075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 00:56:47.288358 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6153 00:56:47.291533 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6154 00:56:47.295031 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6155 00:56:47.301619 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6156 00:56:47.304726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6157 00:56:47.308002 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6158 00:56:47.311249 ===================================
6159 00:56:47.314636 LPDDR4 DRAM CONFIGURATION
6160 00:56:47.318065 ===================================
6161 00:56:47.318150 EX_ROW_EN[0] = 0x0
6162 00:56:47.321297 EX_ROW_EN[1] = 0x0
6163 00:56:47.321406 LP4Y_EN = 0x0
6164 00:56:47.324590 WORK_FSP = 0x0
6165 00:56:47.324675 WL = 0x2
6166 00:56:47.328249 RL = 0x2
6167 00:56:47.331506 BL = 0x2
6168 00:56:47.331590 RPST = 0x0
6169 00:56:47.334737 RD_PRE = 0x0
6170 00:56:47.334821 WR_PRE = 0x1
6171 00:56:47.338102 WR_PST = 0x0
6172 00:56:47.338187 DBI_WR = 0x0
6173 00:56:47.341298 DBI_RD = 0x0
6174 00:56:47.341379 OTF = 0x1
6175 00:56:47.344669 ===================================
6176 00:56:47.347951 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6177 00:56:47.354724 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6178 00:56:47.357883 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 00:56:47.361297 ===================================
6180 00:56:47.364735 LPDDR4 DRAM CONFIGURATION
6181 00:56:47.367975 ===================================
6182 00:56:47.368057 EX_ROW_EN[0] = 0x10
6183 00:56:47.371305 EX_ROW_EN[1] = 0x0
6184 00:56:47.371385 LP4Y_EN = 0x0
6185 00:56:47.374408 WORK_FSP = 0x0
6186 00:56:47.374491 WL = 0x2
6187 00:56:47.377935 RL = 0x2
6188 00:56:47.378016 BL = 0x2
6189 00:56:47.381204 RPST = 0x0
6190 00:56:47.384290 RD_PRE = 0x0
6191 00:56:47.384370 WR_PRE = 0x1
6192 00:56:47.387789 WR_PST = 0x0
6193 00:56:47.387870 DBI_WR = 0x0
6194 00:56:47.391113 DBI_RD = 0x0
6195 00:56:47.391194 OTF = 0x1
6196 00:56:47.394531 ===================================
6197 00:56:47.400959 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6198 00:56:47.404634 nWR fixed to 30
6199 00:56:47.407903 [ModeRegInit_LP4] CH0 RK0
6200 00:56:47.407984 [ModeRegInit_LP4] CH0 RK1
6201 00:56:47.411484 [ModeRegInit_LP4] CH1 RK0
6202 00:56:47.414729 [ModeRegInit_LP4] CH1 RK1
6203 00:56:47.414810 match AC timing 19
6204 00:56:47.421423 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6205 00:56:47.424710 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6206 00:56:47.427923 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6207 00:56:47.434755 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6208 00:56:47.437938 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6209 00:56:47.438019 ==
6210 00:56:47.441092 Dram Type= 6, Freq= 0, CH_0, rank 0
6211 00:56:47.444686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6212 00:56:47.444768 ==
6213 00:56:47.451411 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6214 00:56:47.457895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6215 00:56:47.461359 [CA 0] Center 36 (8~64) winsize 57
6216 00:56:47.464584 [CA 1] Center 36 (8~64) winsize 57
6217 00:56:47.467931 [CA 2] Center 36 (8~64) winsize 57
6218 00:56:47.468014 [CA 3] Center 36 (8~64) winsize 57
6219 00:56:47.471535 [CA 4] Center 36 (8~64) winsize 57
6220 00:56:47.474778 [CA 5] Center 36 (8~64) winsize 57
6221 00:56:47.474861
6222 00:56:47.477878 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6223 00:56:47.481139
6224 00:56:47.484615 [CATrainingPosCal] consider 1 rank data
6225 00:56:47.484732 u2DelayCellTimex100 = 270/100 ps
6226 00:56:47.491204 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 00:56:47.494482 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 00:56:47.497880 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 00:56:47.501195 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 00:56:47.504409 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 00:56:47.507669 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 00:56:47.507752
6233 00:56:47.510943 CA PerBit enable=1, Macro0, CA PI delay=36
6234 00:56:47.511036
6235 00:56:47.514389 [CBTSetCACLKResult] CA Dly = 36
6236 00:56:47.517608 CS Dly: 1 (0~32)
6237 00:56:47.517693 ==
6238 00:56:47.521111 Dram Type= 6, Freq= 0, CH_0, rank 1
6239 00:56:47.524182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6240 00:56:47.524274 ==
6241 00:56:47.531017 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6242 00:56:47.533937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6243 00:56:47.537522 [CA 0] Center 36 (8~64) winsize 57
6244 00:56:47.540606 [CA 1] Center 36 (8~64) winsize 57
6245 00:56:47.543928 [CA 2] Center 36 (8~64) winsize 57
6246 00:56:47.547527 [CA 3] Center 36 (8~64) winsize 57
6247 00:56:47.550654 [CA 4] Center 36 (8~64) winsize 57
6248 00:56:47.554055 [CA 5] Center 36 (8~64) winsize 57
6249 00:56:47.554141
6250 00:56:47.557377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6251 00:56:47.557463
6252 00:56:47.560748 [CATrainingPosCal] consider 2 rank data
6253 00:56:47.563939 u2DelayCellTimex100 = 270/100 ps
6254 00:56:47.567050 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 00:56:47.574003 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 00:56:47.577042 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 00:56:47.580268 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 00:56:47.583617 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 00:56:47.586915 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 00:56:47.587000
6261 00:56:47.590310 CA PerBit enable=1, Macro0, CA PI delay=36
6262 00:56:47.590394
6263 00:56:47.593644 [CBTSetCACLKResult] CA Dly = 36
6264 00:56:47.593727 CS Dly: 1 (0~32)
6265 00:56:47.596748
6266 00:56:47.600161 ----->DramcWriteLeveling(PI) begin...
6267 00:56:47.600248 ==
6268 00:56:47.603268 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 00:56:47.606546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 00:56:47.606630 ==
6271 00:56:47.610255 Write leveling (Byte 0): 40 => 8
6272 00:56:47.613192 Write leveling (Byte 1): 40 => 8
6273 00:56:47.616599 DramcWriteLeveling(PI) end<-----
6274 00:56:47.616683
6275 00:56:47.616749 ==
6276 00:56:47.620087 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 00:56:47.623073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 00:56:47.623180 ==
6279 00:56:47.626645 [Gating] SW mode calibration
6280 00:56:47.633332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6281 00:56:47.639708 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6282 00:56:47.642976 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6283 00:56:47.646294 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 00:56:47.653118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 00:56:47.656324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 00:56:47.659595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 00:56:47.666005 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 00:56:47.669315 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 00:56:47.672489 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 00:56:47.679399 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 00:56:47.679483 Total UI for P1: 0, mck2ui 16
6292 00:56:47.685794 best dqsien dly found for B0: ( 0, 14, 24)
6293 00:56:47.685881 Total UI for P1: 0, mck2ui 16
6294 00:56:47.692407 best dqsien dly found for B1: ( 0, 14, 24)
6295 00:56:47.695735 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6296 00:56:47.698827 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6297 00:56:47.698910
6298 00:56:47.702141 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6299 00:56:47.705533 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 00:56:47.708723 [Gating] SW calibration Done
6301 00:56:47.708806 ==
6302 00:56:47.712200 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 00:56:47.715428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 00:56:47.715512 ==
6305 00:56:47.718688 RX Vref Scan: 0
6306 00:56:47.718770
6307 00:56:47.718837 RX Vref 0 -> 0, step: 1
6308 00:56:47.722166
6309 00:56:47.722249 RX Delay -410 -> 252, step: 16
6310 00:56:47.728738 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6311 00:56:47.732020 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6312 00:56:47.735555 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6313 00:56:47.738680 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6314 00:56:47.745401 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6315 00:56:47.748638 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6316 00:56:47.751911 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6317 00:56:47.755172 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6318 00:56:47.761831 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6319 00:56:47.765333 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6320 00:56:47.768482 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6321 00:56:47.774911 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6322 00:56:47.778508 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6323 00:56:47.781779 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6324 00:56:47.784915 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6325 00:56:47.791412 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6326 00:56:47.791546 ==
6327 00:56:47.794976 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 00:56:47.798238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 00:56:47.798369 ==
6330 00:56:47.798492 DQS Delay:
6331 00:56:47.801295 DQS0 = 59, DQS1 = 59
6332 00:56:47.801428 DQM Delay:
6333 00:56:47.804595 DQM0 = 18, DQM1 = 10
6334 00:56:47.804727 DQ Delay:
6335 00:56:47.807828 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6336 00:56:47.811200 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6337 00:56:47.814450 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6338 00:56:47.817726 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6339 00:56:47.817857
6340 00:56:47.817981
6341 00:56:47.818107 ==
6342 00:56:47.821216 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 00:56:47.824328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 00:56:47.824464 ==
6345 00:56:47.827774
6346 00:56:47.827908
6347 00:56:47.828063 TX Vref Scan disable
6348 00:56:47.831080 == TX Byte 0 ==
6349 00:56:47.834307 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 00:56:47.837651 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 00:56:47.841045 == TX Byte 1 ==
6352 00:56:47.844083 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 00:56:47.847588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 00:56:47.847722 ==
6355 00:56:47.851036 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 00:56:47.854326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 00:56:47.857501 ==
6358 00:56:47.857586
6359 00:56:47.857673
6360 00:56:47.857753 TX Vref Scan disable
6361 00:56:47.860897 == TX Byte 0 ==
6362 00:56:47.864021 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 00:56:47.867257 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 00:56:47.870708 == TX Byte 1 ==
6365 00:56:47.873979 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 00:56:47.877270 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 00:56:47.877357
6368 00:56:47.880856 [DATLAT]
6369 00:56:47.880940 Freq=400, CH0 RK0
6370 00:56:47.881028
6371 00:56:47.883978 DATLAT Default: 0xf
6372 00:56:47.884064 0, 0xFFFF, sum = 0
6373 00:56:47.887180 1, 0xFFFF, sum = 0
6374 00:56:47.887267 2, 0xFFFF, sum = 0
6375 00:56:47.890403 3, 0xFFFF, sum = 0
6376 00:56:47.890490 4, 0xFFFF, sum = 0
6377 00:56:47.894004 5, 0xFFFF, sum = 0
6378 00:56:47.894091 6, 0xFFFF, sum = 0
6379 00:56:47.896941 7, 0xFFFF, sum = 0
6380 00:56:47.897030 8, 0xFFFF, sum = 0
6381 00:56:47.900415 9, 0xFFFF, sum = 0
6382 00:56:47.900501 10, 0xFFFF, sum = 0
6383 00:56:47.903599 11, 0xFFFF, sum = 0
6384 00:56:47.907152 12, 0xFFFF, sum = 0
6385 00:56:47.907239 13, 0x0, sum = 1
6386 00:56:47.907327 14, 0x0, sum = 2
6387 00:56:47.910422 15, 0x0, sum = 3
6388 00:56:47.910508 16, 0x0, sum = 4
6389 00:56:47.913668 best_step = 14
6390 00:56:47.913753
6391 00:56:47.913840 ==
6392 00:56:47.916846 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 00:56:47.920324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 00:56:47.920411 ==
6395 00:56:47.923933 RX Vref Scan: 1
6396 00:56:47.924042
6397 00:56:47.924145 RX Vref 0 -> 0, step: 1
6398 00:56:47.924244
6399 00:56:47.927079 RX Delay -359 -> 252, step: 8
6400 00:56:47.927164
6401 00:56:47.930027 Set Vref, RX VrefLevel [Byte0]: 60
6402 00:56:47.933300 [Byte1]: 52
6403 00:56:47.938391
6404 00:56:47.938476 Final RX Vref Byte 0 = 60 to rank0
6405 00:56:47.941804 Final RX Vref Byte 1 = 52 to rank0
6406 00:56:47.944919 Final RX Vref Byte 0 = 60 to rank1
6407 00:56:47.948263 Final RX Vref Byte 1 = 52 to rank1==
6408 00:56:47.951758 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 00:56:47.958436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 00:56:47.958534 ==
6411 00:56:47.958622 DQS Delay:
6412 00:56:47.961805 DQS0 = 60, DQS1 = 68
6413 00:56:47.961890 DQM Delay:
6414 00:56:47.961976 DQM0 = 14, DQM1 = 14
6415 00:56:47.964877 DQ Delay:
6416 00:56:47.968347 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6417 00:56:47.971635 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6418 00:56:47.971727 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6419 00:56:47.975108 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6420 00:56:47.978362
6421 00:56:47.978445
6422 00:56:47.984841 [DQSOSCAuto] RK0, (LSB)MR18= 0x8885, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6423 00:56:47.988055 CH0 RK0: MR19=C0C, MR18=8885
6424 00:56:47.994872 CH0_RK0: MR19=0xC0C, MR18=0x8885, DQSOSC=392, MR23=63, INC=384, DEC=256
6425 00:56:47.995012 ==
6426 00:56:47.998261 Dram Type= 6, Freq= 0, CH_0, rank 1
6427 00:56:48.001424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 00:56:48.001576 ==
6429 00:56:48.004664 [Gating] SW mode calibration
6430 00:56:48.011297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6431 00:56:48.017788 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6432 00:56:48.021353 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6433 00:56:48.024474 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 00:56:48.031427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 00:56:48.034664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 00:56:48.037694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 00:56:48.044619 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 00:56:48.047885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 00:56:48.051068 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 00:56:48.057434 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 00:56:48.057549 Total UI for P1: 0, mck2ui 16
6442 00:56:48.064337 best dqsien dly found for B0: ( 0, 14, 24)
6443 00:56:48.064437 Total UI for P1: 0, mck2ui 16
6444 00:56:48.070660 best dqsien dly found for B1: ( 0, 14, 24)
6445 00:56:48.074212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6446 00:56:48.077393 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6447 00:56:48.077491
6448 00:56:48.080594 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6449 00:56:48.084138 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 00:56:48.087282 [Gating] SW calibration Done
6451 00:56:48.087373 ==
6452 00:56:48.090559 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 00:56:48.094308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 00:56:48.094398 ==
6455 00:56:48.097394 RX Vref Scan: 0
6456 00:56:48.097550
6457 00:56:48.097638 RX Vref 0 -> 0, step: 1
6458 00:56:48.097720
6459 00:56:48.100553 RX Delay -410 -> 252, step: 16
6460 00:56:48.107375 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6461 00:56:48.110604 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6462 00:56:48.114031 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6463 00:56:48.117256 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6464 00:56:48.123813 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6465 00:56:48.127139 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6466 00:56:48.130453 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6467 00:56:48.133662 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6468 00:56:48.140346 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6469 00:56:48.143905 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6470 00:56:48.147145 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6471 00:56:48.150263 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6472 00:56:48.156951 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6473 00:56:48.160392 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6474 00:56:48.163550 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6475 00:56:48.166710 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6476 00:56:48.170205 ==
6477 00:56:48.173421 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 00:56:48.176860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 00:56:48.176950 ==
6480 00:56:48.177038 DQS Delay:
6481 00:56:48.180261 DQS0 = 59, DQS1 = 59
6482 00:56:48.180347 DQM Delay:
6483 00:56:48.183727 DQM0 = 16, DQM1 = 10
6484 00:56:48.183813 DQ Delay:
6485 00:56:48.186871 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6486 00:56:48.190260 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6487 00:56:48.193320 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6488 00:56:48.196743 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6489 00:56:48.196830
6490 00:56:48.196917
6491 00:56:48.196998 ==
6492 00:56:48.200059 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 00:56:48.203414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 00:56:48.203501 ==
6495 00:56:48.203587
6496 00:56:48.203668
6497 00:56:48.206588 TX Vref Scan disable
6498 00:56:48.206673 == TX Byte 0 ==
6499 00:56:48.213349 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6500 00:56:48.216643 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6501 00:56:48.216729 == TX Byte 1 ==
6502 00:56:48.223022 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6503 00:56:48.226843 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6504 00:56:48.226935 ==
6505 00:56:48.229941 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 00:56:48.233256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 00:56:48.233343 ==
6508 00:56:48.233446
6509 00:56:48.233537
6510 00:56:48.236346 TX Vref Scan disable
6511 00:56:48.239514 == TX Byte 0 ==
6512 00:56:48.243108 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6513 00:56:48.246343 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6514 00:56:48.246457 == TX Byte 1 ==
6515 00:56:48.253052 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6516 00:56:48.256146 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6517 00:56:48.256238
6518 00:56:48.256305 [DATLAT]
6519 00:56:48.259677 Freq=400, CH0 RK1
6520 00:56:48.259762
6521 00:56:48.259828 DATLAT Default: 0xe
6522 00:56:48.263009 0, 0xFFFF, sum = 0
6523 00:56:48.263097 1, 0xFFFF, sum = 0
6524 00:56:48.266274 2, 0xFFFF, sum = 0
6525 00:56:48.266364 3, 0xFFFF, sum = 0
6526 00:56:48.269553 4, 0xFFFF, sum = 0
6527 00:56:48.269646 5, 0xFFFF, sum = 0
6528 00:56:48.273130 6, 0xFFFF, sum = 0
6529 00:56:48.273218 7, 0xFFFF, sum = 0
6530 00:56:48.276279 8, 0xFFFF, sum = 0
6531 00:56:48.279716 9, 0xFFFF, sum = 0
6532 00:56:48.279803 10, 0xFFFF, sum = 0
6533 00:56:48.282938 11, 0xFFFF, sum = 0
6534 00:56:48.283024 12, 0xFFFF, sum = 0
6535 00:56:48.286239 13, 0x0, sum = 1
6536 00:56:48.286325 14, 0x0, sum = 2
6537 00:56:48.289486 15, 0x0, sum = 3
6538 00:56:48.289610 16, 0x0, sum = 4
6539 00:56:48.289706 best_step = 14
6540 00:56:48.292989
6541 00:56:48.293060 ==
6542 00:56:48.296194 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 00:56:48.299635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 00:56:48.299726 ==
6545 00:56:48.299814 RX Vref Scan: 0
6546 00:56:48.299896
6547 00:56:48.302878 RX Vref 0 -> 0, step: 1
6548 00:56:48.302968
6549 00:56:48.306370 RX Delay -359 -> 252, step: 8
6550 00:56:48.313278 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6551 00:56:48.316571 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6552 00:56:48.319881 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6553 00:56:48.323365 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6554 00:56:48.329935 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6555 00:56:48.333227 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6556 00:56:48.336234 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6557 00:56:48.343029 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6558 00:56:48.346247 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6559 00:56:48.349603 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6560 00:56:48.353010 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6561 00:56:48.359308 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6562 00:56:48.362590 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6563 00:56:48.366162 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6564 00:56:48.369352 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6565 00:56:48.376099 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6566 00:56:48.376185 ==
6567 00:56:48.379162 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 00:56:48.382406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 00:56:48.382492 ==
6570 00:56:48.382579 DQS Delay:
6571 00:56:48.385895 DQS0 = 60, DQS1 = 72
6572 00:56:48.385981 DQM Delay:
6573 00:56:48.389471 DQM0 = 11, DQM1 = 17
6574 00:56:48.389594 DQ Delay:
6575 00:56:48.392391 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6576 00:56:48.395703 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6577 00:56:48.399152 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6578 00:56:48.402686 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6579 00:56:48.402801
6580 00:56:48.402867
6581 00:56:48.409028 [DQSOSCAuto] RK1, (LSB)MR18= 0xce85, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6582 00:56:48.412413 CH0 RK1: MR19=C0C, MR18=CE85
6583 00:56:48.419186 CH0_RK1: MR19=0xC0C, MR18=0xCE85, DQSOSC=384, MR23=63, INC=400, DEC=267
6584 00:56:48.422444 [RxdqsGatingPostProcess] freq 400
6585 00:56:48.428957 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6586 00:56:48.432236 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 00:56:48.435512 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 00:56:48.438942 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 00:56:48.442329 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 00:56:48.442411 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 00:56:48.445611 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 00:56:48.448887 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 00:56:48.452133 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 00:56:48.455359 Pre-setting of DQS Precalculation
6595 00:56:48.461857 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6596 00:56:48.461939 ==
6597 00:56:48.465189 Dram Type= 6, Freq= 0, CH_1, rank 0
6598 00:56:48.468620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 00:56:48.468704 ==
6600 00:56:48.475258 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6601 00:56:48.481961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6602 00:56:48.485164 [CA 0] Center 36 (8~64) winsize 57
6603 00:56:48.485250 [CA 1] Center 36 (8~64) winsize 57
6604 00:56:48.488575 [CA 2] Center 36 (8~64) winsize 57
6605 00:56:48.491929 [CA 3] Center 36 (8~64) winsize 57
6606 00:56:48.495147 [CA 4] Center 36 (8~64) winsize 57
6607 00:56:48.498549 [CA 5] Center 36 (8~64) winsize 57
6608 00:56:48.498635
6609 00:56:48.501722 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6610 00:56:48.501807
6611 00:56:48.505136 [CATrainingPosCal] consider 1 rank data
6612 00:56:48.508229 u2DelayCellTimex100 = 270/100 ps
6613 00:56:48.511484 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 00:56:48.518243 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 00:56:48.521792 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 00:56:48.524930 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 00:56:48.528502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 00:56:48.531771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 00:56:48.531854
6620 00:56:48.534903 CA PerBit enable=1, Macro0, CA PI delay=36
6621 00:56:48.534987
6622 00:56:48.538249 [CBTSetCACLKResult] CA Dly = 36
6623 00:56:48.538335 CS Dly: 1 (0~32)
6624 00:56:48.541535 ==
6625 00:56:48.544980 Dram Type= 6, Freq= 0, CH_1, rank 1
6626 00:56:48.548288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 00:56:48.548372 ==
6628 00:56:48.551503 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6629 00:56:48.558205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6630 00:56:48.561439 [CA 0] Center 36 (8~64) winsize 57
6631 00:56:48.564543 [CA 1] Center 36 (8~64) winsize 57
6632 00:56:48.567844 [CA 2] Center 36 (8~64) winsize 57
6633 00:56:48.571079 [CA 3] Center 36 (8~64) winsize 57
6634 00:56:48.574509 [CA 4] Center 36 (8~64) winsize 57
6635 00:56:48.577912 [CA 5] Center 36 (8~64) winsize 57
6636 00:56:48.577995
6637 00:56:48.581145 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6638 00:56:48.581229
6639 00:56:48.584620 [CATrainingPosCal] consider 2 rank data
6640 00:56:48.587639 u2DelayCellTimex100 = 270/100 ps
6641 00:56:48.591342 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 00:56:48.594524 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 00:56:48.597823 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 00:56:48.604354 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 00:56:48.607642 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 00:56:48.610817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 00:56:48.610901
6648 00:56:48.614329 CA PerBit enable=1, Macro0, CA PI delay=36
6649 00:56:48.614413
6650 00:56:48.617547 [CBTSetCACLKResult] CA Dly = 36
6651 00:56:48.617631 CS Dly: 1 (0~32)
6652 00:56:48.617698
6653 00:56:48.621041 ----->DramcWriteLeveling(PI) begin...
6654 00:56:48.621126 ==
6655 00:56:48.624235 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 00:56:48.630778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 00:56:48.630868 ==
6658 00:56:48.634050 Write leveling (Byte 0): 40 => 8
6659 00:56:48.637613 Write leveling (Byte 1): 40 => 8
6660 00:56:48.637696 DramcWriteLeveling(PI) end<-----
6661 00:56:48.637763
6662 00:56:48.640699 ==
6663 00:56:48.643899 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 00:56:48.647135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 00:56:48.647234 ==
6666 00:56:48.650563 [Gating] SW mode calibration
6667 00:56:48.656998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6668 00:56:48.660571 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6669 00:56:48.667071 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6670 00:56:48.670535 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 00:56:48.674008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 00:56:48.680478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 00:56:48.683681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 00:56:48.686849 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 00:56:48.693710 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 00:56:48.696908 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 00:56:48.700208 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 00:56:48.703669 Total UI for P1: 0, mck2ui 16
6679 00:56:48.706764 best dqsien dly found for B0: ( 0, 14, 24)
6680 00:56:48.710205 Total UI for P1: 0, mck2ui 16
6681 00:56:48.713337 best dqsien dly found for B1: ( 0, 14, 24)
6682 00:56:48.716623 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6683 00:56:48.720136 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6684 00:56:48.723305
6685 00:56:48.726704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6686 00:56:48.729717 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 00:56:48.733133 [Gating] SW calibration Done
6688 00:56:48.733232 ==
6689 00:56:48.736455 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 00:56:48.739782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 00:56:48.739867 ==
6692 00:56:48.739935 RX Vref Scan: 0
6693 00:56:48.743436
6694 00:56:48.743522 RX Vref 0 -> 0, step: 1
6695 00:56:48.743609
6696 00:56:48.746497 RX Delay -410 -> 252, step: 16
6697 00:56:48.749794 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6698 00:56:48.756516 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6699 00:56:48.759778 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6700 00:56:48.762883 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6701 00:56:48.766208 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6702 00:56:48.772878 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6703 00:56:48.776233 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6704 00:56:48.779431 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6705 00:56:48.782871 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6706 00:56:48.789265 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6707 00:56:48.792856 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6708 00:56:48.795994 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6709 00:56:48.802869 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6710 00:56:48.805852 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6711 00:56:48.809290 iDelay=230, Bit 14, Center -51 (-314 ~ 213) 528
6712 00:56:48.812462 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6713 00:56:48.812550 ==
6714 00:56:48.815776 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 00:56:48.822566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 00:56:48.822665 ==
6717 00:56:48.822734 DQS Delay:
6718 00:56:48.825701 DQS0 = 51, DQS1 = 67
6719 00:56:48.825791 DQM Delay:
6720 00:56:48.829174 DQM0 = 12, DQM1 = 18
6721 00:56:48.829260 DQ Delay:
6722 00:56:48.832486 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6723 00:56:48.835713 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6724 00:56:48.835802 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6725 00:56:48.842481 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =32
6726 00:56:48.842572
6727 00:56:48.842659
6728 00:56:48.842741 ==
6729 00:56:48.845724 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 00:56:48.849219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 00:56:48.849311 ==
6732 00:56:48.849413
6733 00:56:48.849518
6734 00:56:48.852353 TX Vref Scan disable
6735 00:56:48.852439 == TX Byte 0 ==
6736 00:56:48.858867 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 00:56:48.862113 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 00:56:48.862202 == TX Byte 1 ==
6739 00:56:48.865431 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 00:56:48.872346 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 00:56:48.872433 ==
6742 00:56:48.875485 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 00:56:48.878964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 00:56:48.879050 ==
6745 00:56:48.879153
6746 00:56:48.879253
6747 00:56:48.881991 TX Vref Scan disable
6748 00:56:48.882076 == TX Byte 0 ==
6749 00:56:48.888636 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 00:56:48.892259 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 00:56:48.892345 == TX Byte 1 ==
6752 00:56:48.898508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 00:56:48.902016 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 00:56:48.902102
6755 00:56:48.902188 [DATLAT]
6756 00:56:48.905263 Freq=400, CH1 RK0
6757 00:56:48.905348
6758 00:56:48.905450 DATLAT Default: 0xf
6759 00:56:48.908559 0, 0xFFFF, sum = 0
6760 00:56:48.908646 1, 0xFFFF, sum = 0
6761 00:56:48.912160 2, 0xFFFF, sum = 0
6762 00:56:48.912246 3, 0xFFFF, sum = 0
6763 00:56:48.915277 4, 0xFFFF, sum = 0
6764 00:56:48.915363 5, 0xFFFF, sum = 0
6765 00:56:48.918722 6, 0xFFFF, sum = 0
6766 00:56:48.918808 7, 0xFFFF, sum = 0
6767 00:56:48.922110 8, 0xFFFF, sum = 0
6768 00:56:48.922196 9, 0xFFFF, sum = 0
6769 00:56:48.925141 10, 0xFFFF, sum = 0
6770 00:56:48.925228 11, 0xFFFF, sum = 0
6771 00:56:48.928677 12, 0xFFFF, sum = 0
6772 00:56:48.928763 13, 0x0, sum = 1
6773 00:56:48.931688 14, 0x0, sum = 2
6774 00:56:48.931774 15, 0x0, sum = 3
6775 00:56:48.935231 16, 0x0, sum = 4
6776 00:56:48.935317 best_step = 14
6777 00:56:48.935403
6778 00:56:48.935485 ==
6779 00:56:48.938370 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 00:56:48.945066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 00:56:48.945152 ==
6782 00:56:48.945239 RX Vref Scan: 1
6783 00:56:48.945320
6784 00:56:48.948428 RX Vref 0 -> 0, step: 1
6785 00:56:48.948513
6786 00:56:48.951683 RX Delay -375 -> 252, step: 8
6787 00:56:48.951768
6788 00:56:48.954913 Set Vref, RX VrefLevel [Byte0]: 57
6789 00:56:48.958181 [Byte1]: 49
6790 00:56:48.961641
6791 00:56:48.961726 Final RX Vref Byte 0 = 57 to rank0
6792 00:56:48.964984 Final RX Vref Byte 1 = 49 to rank0
6793 00:56:48.968254 Final RX Vref Byte 0 = 57 to rank1
6794 00:56:48.971849 Final RX Vref Byte 1 = 49 to rank1==
6795 00:56:48.975171 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 00:56:48.981693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 00:56:48.981788 ==
6798 00:56:48.981877 DQS Delay:
6799 00:56:48.984859 DQS0 = 56, DQS1 = 68
6800 00:56:48.984945 DQM Delay:
6801 00:56:48.985048 DQM0 = 13, DQM1 = 14
6802 00:56:48.988175 DQ Delay:
6803 00:56:48.991558 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6804 00:56:48.991647 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6805 00:56:48.994804 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6806 00:56:48.998170 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6807 00:56:48.998259
6808 00:56:49.001516
6809 00:56:49.008107 [DQSOSCAuto] RK0, (LSB)MR18= 0x5468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6810 00:56:49.011660 CH1 RK0: MR19=C0C, MR18=5468
6811 00:56:49.018160 CH1_RK0: MR19=0xC0C, MR18=0x5468, DQSOSC=396, MR23=63, INC=376, DEC=251
6812 00:56:49.018260 ==
6813 00:56:49.021598 Dram Type= 6, Freq= 0, CH_1, rank 1
6814 00:56:49.024835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 00:56:49.024923 ==
6816 00:56:49.028206 [Gating] SW mode calibration
6817 00:56:49.034621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6818 00:56:49.041380 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6819 00:56:49.044693 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6820 00:56:49.047951 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 00:56:49.054519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 00:56:49.057919 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 00:56:49.061379 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 00:56:49.064741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 00:56:49.071220 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 00:56:49.074435 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 00:56:49.077760 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 00:56:49.080983 Total UI for P1: 0, mck2ui 16
6829 00:56:49.084248 best dqsien dly found for B0: ( 0, 14, 24)
6830 00:56:49.087723 Total UI for P1: 0, mck2ui 16
6831 00:56:49.090896 best dqsien dly found for B1: ( 0, 14, 24)
6832 00:56:49.094509 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6833 00:56:49.101156 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6834 00:56:49.101244
6835 00:56:49.104447 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6836 00:56:49.107670 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 00:56:49.111057 [Gating] SW calibration Done
6838 00:56:49.111144 ==
6839 00:56:49.114301 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 00:56:49.117780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 00:56:49.117865 ==
6842 00:56:49.117932 RX Vref Scan: 0
6843 00:56:49.121262
6844 00:56:49.121348 RX Vref 0 -> 0, step: 1
6845 00:56:49.121415
6846 00:56:49.124500 RX Delay -410 -> 252, step: 16
6847 00:56:49.127730 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6848 00:56:49.134353 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6849 00:56:49.137697 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6850 00:56:49.140991 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6851 00:56:49.144140 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6852 00:56:49.150914 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6853 00:56:49.154259 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6854 00:56:49.157532 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6855 00:56:49.160599 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6856 00:56:49.167214 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6857 00:56:49.170855 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6858 00:56:49.173954 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6859 00:56:49.177218 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6860 00:56:49.183858 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6861 00:56:49.187446 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6862 00:56:49.190702 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6863 00:56:49.190786 ==
6864 00:56:49.194004 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 00:56:49.200538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 00:56:49.200627 ==
6867 00:56:49.200715 DQS Delay:
6868 00:56:49.203710 DQS0 = 59, DQS1 = 59
6869 00:56:49.203795 DQM Delay:
6870 00:56:49.203882 DQM0 = 19, DQM1 = 13
6871 00:56:49.207024 DQ Delay:
6872 00:56:49.210522 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6873 00:56:49.213704 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6874 00:56:49.216880 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6875 00:56:49.220461 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6876 00:56:49.220546
6877 00:56:49.220633
6878 00:56:49.220714 ==
6879 00:56:49.223740 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 00:56:49.226795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 00:56:49.226881 ==
6882 00:56:49.226968
6883 00:56:49.227049
6884 00:56:49.230332 TX Vref Scan disable
6885 00:56:49.230418 == TX Byte 0 ==
6886 00:56:49.236620 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6887 00:56:49.239946 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6888 00:56:49.240032 == TX Byte 1 ==
6889 00:56:49.246816 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6890 00:56:49.249877 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6891 00:56:49.249962 ==
6892 00:56:49.253272 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 00:56:49.256579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 00:56:49.256663 ==
6895 00:56:49.256730
6896 00:56:49.256792
6897 00:56:49.259984 TX Vref Scan disable
6898 00:56:49.260067 == TX Byte 0 ==
6899 00:56:49.266692 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6900 00:56:49.269833 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6901 00:56:49.269917 == TX Byte 1 ==
6902 00:56:49.276636 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6903 00:56:49.279823 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6904 00:56:49.279907
6905 00:56:49.279973 [DATLAT]
6906 00:56:49.283144 Freq=400, CH1 RK1
6907 00:56:49.283228
6908 00:56:49.283294 DATLAT Default: 0xe
6909 00:56:49.286462 0, 0xFFFF, sum = 0
6910 00:56:49.286547 1, 0xFFFF, sum = 0
6911 00:56:49.289673 2, 0xFFFF, sum = 0
6912 00:56:49.289757 3, 0xFFFF, sum = 0
6913 00:56:49.293184 4, 0xFFFF, sum = 0
6914 00:56:49.293269 5, 0xFFFF, sum = 0
6915 00:56:49.296738 6, 0xFFFF, sum = 0
6916 00:56:49.296822 7, 0xFFFF, sum = 0
6917 00:56:49.299703 8, 0xFFFF, sum = 0
6918 00:56:49.299788 9, 0xFFFF, sum = 0
6919 00:56:49.303134 10, 0xFFFF, sum = 0
6920 00:56:49.306389 11, 0xFFFF, sum = 0
6921 00:56:49.306476 12, 0xFFFF, sum = 0
6922 00:56:49.309453 13, 0x0, sum = 1
6923 00:56:49.309563 14, 0x0, sum = 2
6924 00:56:49.313059 15, 0x0, sum = 3
6925 00:56:49.313146 16, 0x0, sum = 4
6926 00:56:49.313251 best_step = 14
6927 00:56:49.313351
6928 00:56:49.316221 ==
6929 00:56:49.316323 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 00:56:49.322887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 00:56:49.322972 ==
6932 00:56:49.323039 RX Vref Scan: 0
6933 00:56:49.323101
6934 00:56:49.326444 RX Vref 0 -> 0, step: 1
6935 00:56:49.326527
6936 00:56:49.329683 RX Delay -359 -> 252, step: 8
6937 00:56:49.336436 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6938 00:56:49.339638 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6939 00:56:49.343249 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6940 00:56:49.346452 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6941 00:56:49.353160 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6942 00:56:49.356355 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6943 00:56:49.359625 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6944 00:56:49.363069 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6945 00:56:49.369744 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6946 00:56:49.372993 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6947 00:56:49.376201 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6948 00:56:49.379584 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6949 00:56:49.386263 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6950 00:56:49.389376 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6951 00:56:49.392692 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6952 00:56:49.399365 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6953 00:56:49.399457 ==
6954 00:56:49.402743 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 00:56:49.405846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 00:56:49.405918 ==
6957 00:56:49.405982 DQS Delay:
6958 00:56:49.409333 DQS0 = 60, DQS1 = 64
6959 00:56:49.409431 DQM Delay:
6960 00:56:49.412597 DQM0 = 13, DQM1 = 10
6961 00:56:49.412671 DQ Delay:
6962 00:56:49.416129 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6963 00:56:49.419251 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6964 00:56:49.422840 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6965 00:56:49.426045 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6966 00:56:49.426161
6967 00:56:49.426260
6968 00:56:49.432308 [DQSOSCAuto] RK1, (LSB)MR18= 0x80b0, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6969 00:56:49.435763 CH1 RK1: MR19=C0C, MR18=80B0
6970 00:56:49.442252 CH1_RK1: MR19=0xC0C, MR18=0x80B0, DQSOSC=387, MR23=63, INC=394, DEC=262
6971 00:56:49.445610 [RxdqsGatingPostProcess] freq 400
6972 00:56:49.452406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6973 00:56:49.455611 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 00:56:49.459148 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 00:56:49.459221 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 00:56:49.462375 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 00:56:49.465504 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 00:56:49.469039 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 00:56:49.472251 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 00:56:49.475665 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 00:56:49.478848 Pre-setting of DQS Precalculation
6982 00:56:49.485608 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6983 00:56:49.492221 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6984 00:56:49.498544 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6985 00:56:49.498631
6986 00:56:49.498718
6987 00:56:49.502007 [Calibration Summary] 800 Mbps
6988 00:56:49.502078 CH 0, Rank 0
6989 00:56:49.505293 SW Impedance : PASS
6990 00:56:49.508635 DUTY Scan : NO K
6991 00:56:49.508708 ZQ Calibration : PASS
6992 00:56:49.512153 Jitter Meter : NO K
6993 00:56:49.515342 CBT Training : PASS
6994 00:56:49.515424 Write leveling : PASS
6995 00:56:49.518675 RX DQS gating : PASS
6996 00:56:49.518758 RX DQ/DQS(RDDQC) : PASS
6997 00:56:49.522077 TX DQ/DQS : PASS
6998 00:56:49.525433 RX DATLAT : PASS
6999 00:56:49.525565 RX DQ/DQS(Engine): PASS
7000 00:56:49.528863 TX OE : NO K
7001 00:56:49.528947 All Pass.
7002 00:56:49.529012
7003 00:56:49.531858 CH 0, Rank 1
7004 00:56:49.531939 SW Impedance : PASS
7005 00:56:49.535447 DUTY Scan : NO K
7006 00:56:49.538709 ZQ Calibration : PASS
7007 00:56:49.538800 Jitter Meter : NO K
7008 00:56:49.542055 CBT Training : PASS
7009 00:56:49.545313 Write leveling : NO K
7010 00:56:49.545394 RX DQS gating : PASS
7011 00:56:49.548573 RX DQ/DQS(RDDQC) : PASS
7012 00:56:49.551814 TX DQ/DQS : PASS
7013 00:56:49.551896 RX DATLAT : PASS
7014 00:56:49.555068 RX DQ/DQS(Engine): PASS
7015 00:56:49.558299 TX OE : NO K
7016 00:56:49.558380 All Pass.
7017 00:56:49.558444
7018 00:56:49.558505 CH 1, Rank 0
7019 00:56:49.561615 SW Impedance : PASS
7020 00:56:49.565200 DUTY Scan : NO K
7021 00:56:49.565282 ZQ Calibration : PASS
7022 00:56:49.568330 Jitter Meter : NO K
7023 00:56:49.571496 CBT Training : PASS
7024 00:56:49.571575 Write leveling : PASS
7025 00:56:49.575049 RX DQS gating : PASS
7026 00:56:49.575130 RX DQ/DQS(RDDQC) : PASS
7027 00:56:49.578439 TX DQ/DQS : PASS
7028 00:56:49.581472 RX DATLAT : PASS
7029 00:56:49.581591 RX DQ/DQS(Engine): PASS
7030 00:56:49.584903 TX OE : NO K
7031 00:56:49.584987 All Pass.
7032 00:56:49.585060
7033 00:56:49.588383 CH 1, Rank 1
7034 00:56:49.588464 SW Impedance : PASS
7035 00:56:49.591637 DUTY Scan : NO K
7036 00:56:49.594762 ZQ Calibration : PASS
7037 00:56:49.594844 Jitter Meter : NO K
7038 00:56:49.598286 CBT Training : PASS
7039 00:56:49.601623 Write leveling : NO K
7040 00:56:49.601704 RX DQS gating : PASS
7041 00:56:49.604783 RX DQ/DQS(RDDQC) : PASS
7042 00:56:49.608076 TX DQ/DQS : PASS
7043 00:56:49.608158 RX DATLAT : PASS
7044 00:56:49.611476 RX DQ/DQS(Engine): PASS
7045 00:56:49.614783 TX OE : NO K
7046 00:56:49.614865 All Pass.
7047 00:56:49.614930
7048 00:56:49.614990 DramC Write-DBI off
7049 00:56:49.618306 PER_BANK_REFRESH: Hybrid Mode
7050 00:56:49.621385 TX_TRACKING: ON
7051 00:56:49.628079 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7052 00:56:49.631284 [FAST_K] Save calibration result to emmc
7053 00:56:49.638064 dramc_set_vcore_voltage set vcore to 725000
7054 00:56:49.638147 Read voltage for 1600, 0
7055 00:56:49.641276 Vio18 = 0
7056 00:56:49.641356 Vcore = 725000
7057 00:56:49.641422 Vdram = 0
7058 00:56:49.644838 Vddq = 0
7059 00:56:49.644919 Vmddr = 0
7060 00:56:49.648068 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7061 00:56:49.654571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7062 00:56:49.658151 MEM_TYPE=3, freq_sel=13
7063 00:56:49.661265 sv_algorithm_assistance_LP4_3733
7064 00:56:49.664565 ============ PULL DRAM RESETB DOWN ============
7065 00:56:49.667832 ========== PULL DRAM RESETB DOWN end =========
7066 00:56:49.674498 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7067 00:56:49.677678 ===================================
7068 00:56:49.677760 LPDDR4 DRAM CONFIGURATION
7069 00:56:49.680893 ===================================
7070 00:56:49.684473 EX_ROW_EN[0] = 0x0
7071 00:56:49.684554 EX_ROW_EN[1] = 0x0
7072 00:56:49.687662 LP4Y_EN = 0x0
7073 00:56:49.687743 WORK_FSP = 0x1
7074 00:56:49.690900 WL = 0x5
7075 00:56:49.690982 RL = 0x5
7076 00:56:49.694422 BL = 0x2
7077 00:56:49.697637 RPST = 0x0
7078 00:56:49.697734 RD_PRE = 0x0
7079 00:56:49.700835 WR_PRE = 0x1
7080 00:56:49.700916 WR_PST = 0x1
7081 00:56:49.704075 DBI_WR = 0x0
7082 00:56:49.704157 DBI_RD = 0x0
7083 00:56:49.707475 OTF = 0x1
7084 00:56:49.710897 ===================================
7085 00:56:49.713964 ===================================
7086 00:56:49.714046 ANA top config
7087 00:56:49.717295 ===================================
7088 00:56:49.720691 DLL_ASYNC_EN = 0
7089 00:56:49.723881 ALL_SLAVE_EN = 0
7090 00:56:49.723963 NEW_RANK_MODE = 1
7091 00:56:49.727191 DLL_IDLE_MODE = 1
7092 00:56:49.730776 LP45_APHY_COMB_EN = 1
7093 00:56:49.733992 TX_ODT_DIS = 0
7094 00:56:49.734101 NEW_8X_MODE = 1
7095 00:56:49.737472 ===================================
7096 00:56:49.740651 ===================================
7097 00:56:49.744141 data_rate = 3200
7098 00:56:49.747440 CKR = 1
7099 00:56:49.750675 DQ_P2S_RATIO = 8
7100 00:56:49.753938 ===================================
7101 00:56:49.757211 CA_P2S_RATIO = 8
7102 00:56:49.760803 DQ_CA_OPEN = 0
7103 00:56:49.760884 DQ_SEMI_OPEN = 0
7104 00:56:49.763788 CA_SEMI_OPEN = 0
7105 00:56:49.767368 CA_FULL_RATE = 0
7106 00:56:49.770637 DQ_CKDIV4_EN = 0
7107 00:56:49.773731 CA_CKDIV4_EN = 0
7108 00:56:49.777235 CA_PREDIV_EN = 0
7109 00:56:49.777316 PH8_DLY = 12
7110 00:56:49.780538 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7111 00:56:49.783812 DQ_AAMCK_DIV = 4
7112 00:56:49.787392 CA_AAMCK_DIV = 4
7113 00:56:49.790425 CA_ADMCK_DIV = 4
7114 00:56:49.793941 DQ_TRACK_CA_EN = 0
7115 00:56:49.797174 CA_PICK = 1600
7116 00:56:49.797256 CA_MCKIO = 1600
7117 00:56:49.800401 MCKIO_SEMI = 0
7118 00:56:49.803803 PLL_FREQ = 3068
7119 00:56:49.807156 DQ_UI_PI_RATIO = 32
7120 00:56:49.810614 CA_UI_PI_RATIO = 0
7121 00:56:49.813732 ===================================
7122 00:56:49.817045 ===================================
7123 00:56:49.820579 memory_type:LPDDR4
7124 00:56:49.820653 GP_NUM : 10
7125 00:56:49.823662 SRAM_EN : 1
7126 00:56:49.823742 MD32_EN : 0
7127 00:56:49.826919 ===================================
7128 00:56:49.830391 [ANA_INIT] >>>>>>>>>>>>>>
7129 00:56:49.833776 <<<<<< [CONFIGURE PHASE]: ANA_TX
7130 00:56:49.836973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7131 00:56:49.840324 ===================================
7132 00:56:49.843755 data_rate = 3200,PCW = 0X7600
7133 00:56:49.847147 ===================================
7134 00:56:49.850453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7135 00:56:49.853640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7136 00:56:49.860459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 00:56:49.867084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7138 00:56:49.870339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7139 00:56:49.873505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7140 00:56:49.873579 [ANA_INIT] flow start
7141 00:56:49.876776 [ANA_INIT] PLL >>>>>>>>
7142 00:56:49.880289 [ANA_INIT] PLL <<<<<<<<
7143 00:56:49.880360 [ANA_INIT] MIDPI >>>>>>>>
7144 00:56:49.883562 [ANA_INIT] MIDPI <<<<<<<<
7145 00:56:49.887002 [ANA_INIT] DLL >>>>>>>>
7146 00:56:49.887074 [ANA_INIT] DLL <<<<<<<<
7147 00:56:49.890148 [ANA_INIT] flow end
7148 00:56:49.893425 ============ LP4 DIFF to SE enter ============
7149 00:56:49.896992 ============ LP4 DIFF to SE exit ============
7150 00:56:49.900256 [ANA_INIT] <<<<<<<<<<<<<
7151 00:56:49.903421 [Flow] Enable top DCM control >>>>>
7152 00:56:49.906933 [Flow] Enable top DCM control <<<<<
7153 00:56:49.909908 Enable DLL master slave shuffle
7154 00:56:49.916334 ==============================================================
7155 00:56:49.916412 Gating Mode config
7156 00:56:49.923380 ==============================================================
7157 00:56:49.926456 Config description:
7158 00:56:49.932978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7159 00:56:49.939903 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7160 00:56:49.946210 SELPH_MODE 0: By rank 1: By Phase
7161 00:56:49.952862 ==============================================================
7162 00:56:49.952947 GAT_TRACK_EN = 1
7163 00:56:49.956391 RX_GATING_MODE = 2
7164 00:56:49.959443 RX_GATING_TRACK_MODE = 2
7165 00:56:49.962834 SELPH_MODE = 1
7166 00:56:49.966348 PICG_EARLY_EN = 1
7167 00:56:49.969380 VALID_LAT_VALUE = 1
7168 00:56:49.975893 ==============================================================
7169 00:56:49.979456 Enter into Gating configuration >>>>
7170 00:56:49.982600 Exit from Gating configuration <<<<
7171 00:56:49.985892 Enter into DVFS_PRE_config >>>>>
7172 00:56:49.996020 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7173 00:56:49.999328 Exit from DVFS_PRE_config <<<<<
7174 00:56:50.002664 Enter into PICG configuration >>>>
7175 00:56:50.005843 Exit from PICG configuration <<<<
7176 00:56:50.008930 [RX_INPUT] configuration >>>>>
7177 00:56:50.012169 [RX_INPUT] configuration <<<<<
7178 00:56:50.015504 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7179 00:56:50.022212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7180 00:56:50.029003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 00:56:50.035492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 00:56:50.038745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 00:56:50.045315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 00:56:50.048462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7185 00:56:50.055321 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7186 00:56:50.058742 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7187 00:56:50.061687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7188 00:56:50.065299 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7189 00:56:50.071786 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7190 00:56:50.075171 ===================================
7191 00:56:50.078302 LPDDR4 DRAM CONFIGURATION
7192 00:56:50.081803 ===================================
7193 00:56:50.081877 EX_ROW_EN[0] = 0x0
7194 00:56:50.085085 EX_ROW_EN[1] = 0x0
7195 00:56:50.085155 LP4Y_EN = 0x0
7196 00:56:50.088420 WORK_FSP = 0x1
7197 00:56:50.088490 WL = 0x5
7198 00:56:50.091592 RL = 0x5
7199 00:56:50.091661 BL = 0x2
7200 00:56:50.094950 RPST = 0x0
7201 00:56:50.095020 RD_PRE = 0x0
7202 00:56:50.098096 WR_PRE = 0x1
7203 00:56:50.098194 WR_PST = 0x1
7204 00:56:50.101696 DBI_WR = 0x0
7205 00:56:50.101777 DBI_RD = 0x0
7206 00:56:50.104939 OTF = 0x1
7207 00:56:50.108180 ===================================
7208 00:56:50.111456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7209 00:56:50.114698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7210 00:56:50.121322 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 00:56:50.124651 ===================================
7212 00:56:50.127832 LPDDR4 DRAM CONFIGURATION
7213 00:56:50.127917 ===================================
7214 00:56:50.131087 EX_ROW_EN[0] = 0x10
7215 00:56:50.134563 EX_ROW_EN[1] = 0x0
7216 00:56:50.134635 LP4Y_EN = 0x0
7217 00:56:50.137829 WORK_FSP = 0x1
7218 00:56:50.137912 WL = 0x5
7219 00:56:50.140994 RL = 0x5
7220 00:56:50.141077 BL = 0x2
7221 00:56:50.144237 RPST = 0x0
7222 00:56:50.144320 RD_PRE = 0x0
7223 00:56:50.147683 WR_PRE = 0x1
7224 00:56:50.147766 WR_PST = 0x1
7225 00:56:50.151051 DBI_WR = 0x0
7226 00:56:50.151134 DBI_RD = 0x0
7227 00:56:50.154368 OTF = 0x1
7228 00:56:50.157681 ===================================
7229 00:56:50.164180 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7230 00:56:50.164263 ==
7231 00:56:50.167600 Dram Type= 6, Freq= 0, CH_0, rank 0
7232 00:56:50.170800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7233 00:56:50.170884 ==
7234 00:56:50.174267 [Duty_Offset_Calibration]
7235 00:56:50.174351 B0:2 B1:0 CA:3
7236 00:56:50.174417
7237 00:56:50.177647 [DutyScan_Calibration_Flow] k_type=0
7238 00:56:50.188576
7239 00:56:50.188659 ==CLK 0==
7240 00:56:50.192071 Final CLK duty delay cell = 0
7241 00:56:50.195295 [0] MAX Duty = 5031%(X100), DQS PI = 12
7242 00:56:50.198738 [0] MIN Duty = 4875%(X100), DQS PI = 8
7243 00:56:50.198822 [0] AVG Duty = 4953%(X100)
7244 00:56:50.201909
7245 00:56:50.205427 CH0 CLK Duty spec in!! Max-Min= 156%
7246 00:56:50.208749 [DutyScan_Calibration_Flow] ====Done====
7247 00:56:50.208833
7248 00:56:50.211656 [DutyScan_Calibration_Flow] k_type=1
7249 00:56:50.228606
7250 00:56:50.228687 ==DQS 0 ==
7251 00:56:50.231996 Final DQS duty delay cell = 0
7252 00:56:50.235120 [0] MAX Duty = 5094%(X100), DQS PI = 30
7253 00:56:50.238525 [0] MIN Duty = 4875%(X100), DQS PI = 48
7254 00:56:50.241867 [0] AVG Duty = 4984%(X100)
7255 00:56:50.242016
7256 00:56:50.242103 ==DQS 1 ==
7257 00:56:50.245353 Final DQS duty delay cell = 0
7258 00:56:50.248626 [0] MAX Duty = 5156%(X100), DQS PI = 32
7259 00:56:50.251857 [0] MIN Duty = 5062%(X100), DQS PI = 8
7260 00:56:50.255072 [0] AVG Duty = 5109%(X100)
7261 00:56:50.255155
7262 00:56:50.258319 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7263 00:56:50.258403
7264 00:56:50.261814 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7265 00:56:50.264975 [DutyScan_Calibration_Flow] ====Done====
7266 00:56:50.265058
7267 00:56:50.268175 [DutyScan_Calibration_Flow] k_type=3
7268 00:56:50.286562
7269 00:56:50.286645 ==DQM 0 ==
7270 00:56:50.289870 Final DQM duty delay cell = 0
7271 00:56:50.293073 [0] MAX Duty = 5156%(X100), DQS PI = 28
7272 00:56:50.296341 [0] MIN Duty = 4875%(X100), DQS PI = 0
7273 00:56:50.296425 [0] AVG Duty = 5015%(X100)
7274 00:56:50.299929
7275 00:56:50.300013 ==DQM 1 ==
7276 00:56:50.303140 Final DQM duty delay cell = 4
7277 00:56:50.306399 [4] MAX Duty = 5187%(X100), DQS PI = 60
7278 00:56:50.309434 [4] MIN Duty = 5000%(X100), DQS PI = 12
7279 00:56:50.312682 [4] AVG Duty = 5093%(X100)
7280 00:56:50.312764
7281 00:56:50.316309 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7282 00:56:50.316392
7283 00:56:50.319448 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7284 00:56:50.322681 [DutyScan_Calibration_Flow] ====Done====
7285 00:56:50.322764
7286 00:56:50.325947 [DutyScan_Calibration_Flow] k_type=2
7287 00:56:50.342731
7288 00:56:50.342814 ==DQ 0 ==
7289 00:56:50.346257 Final DQ duty delay cell = -4
7290 00:56:50.349285 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7291 00:56:50.352725 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7292 00:56:50.355832 [-4] AVG Duty = 4938%(X100)
7293 00:56:50.355914
7294 00:56:50.355980 ==DQ 1 ==
7295 00:56:50.359446 Final DQ duty delay cell = 0
7296 00:56:50.362583 [0] MAX Duty = 5156%(X100), DQS PI = 58
7297 00:56:50.365729 [0] MIN Duty = 5000%(X100), DQS PI = 16
7298 00:56:50.369262 [0] AVG Duty = 5078%(X100)
7299 00:56:50.369361
7300 00:56:50.372582 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7301 00:56:50.372665
7302 00:56:50.375705 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7303 00:56:50.379001 [DutyScan_Calibration_Flow] ====Done====
7304 00:56:50.379083 ==
7305 00:56:50.382525 Dram Type= 6, Freq= 0, CH_1, rank 0
7306 00:56:50.385749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 00:56:50.385832 ==
7308 00:56:50.389178 [Duty_Offset_Calibration]
7309 00:56:50.389260 B0:1 B1:-2 CA:0
7310 00:56:50.389325
7311 00:56:50.392312 [DutyScan_Calibration_Flow] k_type=0
7312 00:56:50.403367
7313 00:56:50.403478 ==CLK 0==
7314 00:56:50.406511 Final CLK duty delay cell = 0
7315 00:56:50.409848 [0] MAX Duty = 5093%(X100), DQS PI = 22
7316 00:56:50.413401 [0] MIN Duty = 4844%(X100), DQS PI = 0
7317 00:56:50.413497 [0] AVG Duty = 4968%(X100)
7318 00:56:50.416518
7319 00:56:50.419697 CH1 CLK Duty spec in!! Max-Min= 249%
7320 00:56:50.423320 [DutyScan_Calibration_Flow] ====Done====
7321 00:56:50.423406
7322 00:56:50.426624 [DutyScan_Calibration_Flow] k_type=1
7323 00:56:50.442290
7324 00:56:50.442401 ==DQS 0 ==
7325 00:56:50.445455 Final DQS duty delay cell = -4
7326 00:56:50.448800 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7327 00:56:50.451924 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7328 00:56:50.455606 [-4] AVG Duty = 4906%(X100)
7329 00:56:50.455688
7330 00:56:50.455753 ==DQS 1 ==
7331 00:56:50.458612 Final DQS duty delay cell = 0
7332 00:56:50.461973 [0] MAX Duty = 5124%(X100), DQS PI = 62
7333 00:56:50.465264 [0] MIN Duty = 4844%(X100), DQS PI = 24
7334 00:56:50.468514 [0] AVG Duty = 4984%(X100)
7335 00:56:50.468596
7336 00:56:50.472118 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7337 00:56:50.472201
7338 00:56:50.475133 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7339 00:56:50.478624 [DutyScan_Calibration_Flow] ====Done====
7340 00:56:50.478706
7341 00:56:50.481868 [DutyScan_Calibration_Flow] k_type=3
7342 00:56:50.499561
7343 00:56:50.499648 ==DQM 0 ==
7344 00:56:50.502682 Final DQM duty delay cell = 0
7345 00:56:50.506248 [0] MAX Duty = 5031%(X100), DQS PI = 24
7346 00:56:50.509437 [0] MIN Duty = 4813%(X100), DQS PI = 56
7347 00:56:50.512954 [0] AVG Duty = 4922%(X100)
7348 00:56:50.513029
7349 00:56:50.513092 ==DQM 1 ==
7350 00:56:50.516132 Final DQM duty delay cell = 0
7351 00:56:50.519688 [0] MAX Duty = 5094%(X100), DQS PI = 36
7352 00:56:50.522763 [0] MIN Duty = 4875%(X100), DQS PI = 24
7353 00:56:50.525920 [0] AVG Duty = 4984%(X100)
7354 00:56:50.526005
7355 00:56:50.529586 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7356 00:56:50.529670
7357 00:56:50.532864 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7358 00:56:50.536053 [DutyScan_Calibration_Flow] ====Done====
7359 00:56:50.536137
7360 00:56:50.539346 [DutyScan_Calibration_Flow] k_type=2
7361 00:56:50.556390
7362 00:56:50.556473 ==DQ 0 ==
7363 00:56:50.559551 Final DQ duty delay cell = 0
7364 00:56:50.563019 [0] MAX Duty = 5093%(X100), DQS PI = 20
7365 00:56:50.566392 [0] MIN Duty = 4907%(X100), DQS PI = 46
7366 00:56:50.566476 [0] AVG Duty = 5000%(X100)
7367 00:56:50.569912
7368 00:56:50.569995 ==DQ 1 ==
7369 00:56:50.573191 Final DQ duty delay cell = 0
7370 00:56:50.576354 [0] MAX Duty = 5125%(X100), DQS PI = 34
7371 00:56:50.579643 [0] MIN Duty = 4969%(X100), DQS PI = 24
7372 00:56:50.579726 [0] AVG Duty = 5047%(X100)
7373 00:56:50.579792
7374 00:56:50.583260 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7375 00:56:50.586490
7376 00:56:50.589449 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7377 00:56:50.592874 [DutyScan_Calibration_Flow] ====Done====
7378 00:56:50.596112 nWR fixed to 30
7379 00:56:50.596196 [ModeRegInit_LP4] CH0 RK0
7380 00:56:50.599575 [ModeRegInit_LP4] CH0 RK1
7381 00:56:50.602854 [ModeRegInit_LP4] CH1 RK0
7382 00:56:50.606422 [ModeRegInit_LP4] CH1 RK1
7383 00:56:50.606505 match AC timing 5
7384 00:56:50.609679 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7385 00:56:50.616211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7386 00:56:50.619311 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7387 00:56:50.626035 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7388 00:56:50.629385 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7389 00:56:50.629468 [MiockJmeterHQA]
7390 00:56:50.629571
7391 00:56:50.632574 [DramcMiockJmeter] u1RxGatingPI = 0
7392 00:56:50.635717 0 : 4363, 4138
7393 00:56:50.635801 4 : 4252, 4027
7394 00:56:50.639250 8 : 4252, 4027
7395 00:56:50.639334 12 : 4255, 4029
7396 00:56:50.639401 16 : 4252, 4027
7397 00:56:50.642469 20 : 4253, 4026
7398 00:56:50.642553 24 : 4363, 4138
7399 00:56:50.645919 28 : 4363, 4138
7400 00:56:50.646003 32 : 4252, 4027
7401 00:56:50.648987 36 : 4252, 4027
7402 00:56:50.649071 40 : 4253, 4027
7403 00:56:50.652437 44 : 4363, 4138
7404 00:56:50.652521 48 : 4252, 4027
7405 00:56:50.652589 52 : 4361, 4137
7406 00:56:50.655566 56 : 4253, 4026
7407 00:56:50.655650 60 : 4250, 4027
7408 00:56:50.659134 64 : 4250, 4027
7409 00:56:50.659218 68 : 4253, 4029
7410 00:56:50.662435 72 : 4361, 4138
7411 00:56:50.662519 76 : 4250, 4027
7412 00:56:50.665733 80 : 4361, 4137
7413 00:56:50.665817 84 : 4250, 4027
7414 00:56:50.665885 88 : 4250, 4026
7415 00:56:50.668867 92 : 4250, 4027
7416 00:56:50.668950 96 : 4363, 4138
7417 00:56:50.672150 100 : 4250, 4026
7418 00:56:50.672234 104 : 4250, 3564
7419 00:56:50.675522 108 : 4250, 0
7420 00:56:50.675605 112 : 4250, 0
7421 00:56:50.675672 116 : 4253, 0
7422 00:56:50.678739 120 : 4250, 0
7423 00:56:50.678823 124 : 4250, 0
7424 00:56:50.681983 128 : 4252, 0
7425 00:56:50.682067 132 : 4361, 0
7426 00:56:50.682134 136 : 4361, 0
7427 00:56:50.685267 140 : 4248, 0
7428 00:56:50.685351 144 : 4250, 0
7429 00:56:50.688562 148 : 4361, 0
7430 00:56:50.688646 152 : 4360, 0
7431 00:56:50.688713 156 : 4250, 0
7432 00:56:50.692034 160 : 4360, 0
7433 00:56:50.692118 164 : 4250, 0
7434 00:56:50.695318 168 : 4250, 0
7435 00:56:50.695402 172 : 4250, 0
7436 00:56:50.695469 176 : 4250, 0
7437 00:56:50.698314 180 : 4253, 0
7438 00:56:50.698398 184 : 4361, 0
7439 00:56:50.698465 188 : 4250, 0
7440 00:56:50.701681 192 : 4250, 0
7441 00:56:50.701766 196 : 4360, 0
7442 00:56:50.705295 200 : 4361, 0
7443 00:56:50.705378 204 : 4363, 0
7444 00:56:50.705445 208 : 4250, 0
7445 00:56:50.708349 212 : 4361, 0
7446 00:56:50.708433 216 : 4361, 0
7447 00:56:50.711971 220 : 4248, 0
7448 00:56:50.712055 224 : 4250, 0
7449 00:56:50.712122 228 : 4250, 0
7450 00:56:50.715049 232 : 4253, 0
7451 00:56:50.715133 236 : 4361, 1174
7452 00:56:50.718473 240 : 4250, 4027
7453 00:56:50.718558 244 : 4360, 4137
7454 00:56:50.721637 248 : 4252, 4029
7455 00:56:50.721721 252 : 4250, 4027
7456 00:56:50.724910 256 : 4250, 4027
7457 00:56:50.724994 260 : 4252, 4029
7458 00:56:50.728255 264 : 4250, 4027
7459 00:56:50.728357 268 : 4250, 4027
7460 00:56:50.728426 272 : 4250, 4027
7461 00:56:50.731591 276 : 4252, 4029
7462 00:56:50.731675 280 : 4250, 4027
7463 00:56:50.734809 284 : 4360, 4138
7464 00:56:50.734893 288 : 4361, 4137
7465 00:56:50.738069 292 : 4250, 4027
7466 00:56:50.738153 296 : 4363, 4140
7467 00:56:50.741486 300 : 4361, 4138
7468 00:56:50.741584 304 : 4250, 4027
7469 00:56:50.744882 308 : 4250, 4027
7470 00:56:50.744966 312 : 4252, 4029
7471 00:56:50.748304 316 : 4250, 4027
7472 00:56:50.748388 320 : 4250, 4027
7473 00:56:50.751527 324 : 4250, 4027
7474 00:56:50.751611 328 : 4252, 4029
7475 00:56:50.755022 332 : 4250, 4027
7476 00:56:50.755106 336 : 4361, 4137
7477 00:56:50.755174 340 : 4361, 4138
7478 00:56:50.758225 344 : 4250, 4027
7479 00:56:50.758309 348 : 4363, 4140
7480 00:56:50.761512 352 : 4360, 4130
7481 00:56:50.761597 356 : 4250, 2589
7482 00:56:50.764655 360 : 4250, 1
7483 00:56:50.764739
7484 00:56:50.764805 MIOCK jitter meter ch=0
7485 00:56:50.767945
7486 00:56:50.768027 1T = (360-108) = 252 dly cells
7487 00:56:50.774567 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7488 00:56:50.774651 ==
7489 00:56:50.778096 Dram Type= 6, Freq= 0, CH_0, rank 0
7490 00:56:50.781151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7491 00:56:50.781235 ==
7492 00:56:50.787732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7493 00:56:50.791298 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7494 00:56:50.797701 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7495 00:56:50.800987 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7496 00:56:50.811541 [CA 0] Center 44 (14~75) winsize 62
7497 00:56:50.814634 [CA 1] Center 43 (13~74) winsize 62
7498 00:56:50.818226 [CA 2] Center 40 (11~69) winsize 59
7499 00:56:50.821217 [CA 3] Center 39 (10~68) winsize 59
7500 00:56:50.824732 [CA 4] Center 37 (8~67) winsize 60
7501 00:56:50.827999 [CA 5] Center 37 (7~67) winsize 61
7502 00:56:50.828083
7503 00:56:50.831197 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7504 00:56:50.831279
7505 00:56:50.838036 [CATrainingPosCal] consider 1 rank data
7506 00:56:50.838118 u2DelayCellTimex100 = 258/100 ps
7507 00:56:50.844388 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7508 00:56:50.847791 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7509 00:56:50.851050 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7510 00:56:50.854417 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7511 00:56:50.857788 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7512 00:56:50.861239 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7513 00:56:50.861321
7514 00:56:50.864503 CA PerBit enable=1, Macro0, CA PI delay=37
7515 00:56:50.864585
7516 00:56:50.867786 [CBTSetCACLKResult] CA Dly = 37
7517 00:56:50.870976 CS Dly: 11 (0~42)
7518 00:56:50.874386 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7519 00:56:50.877669 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7520 00:56:50.877750 ==
7521 00:56:50.880787 Dram Type= 6, Freq= 0, CH_0, rank 1
7522 00:56:50.887638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 00:56:50.887720 ==
7524 00:56:50.890860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 00:56:50.897345 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 00:56:50.900898 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 00:56:50.907311 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 00:56:50.915258 [CA 0] Center 43 (13~74) winsize 62
7529 00:56:50.918564 [CA 1] Center 43 (13~74) winsize 62
7530 00:56:50.922025 [CA 2] Center 39 (10~68) winsize 59
7531 00:56:50.925053 [CA 3] Center 39 (10~68) winsize 59
7532 00:56:50.928453 [CA 4] Center 36 (6~66) winsize 61
7533 00:56:50.931649 [CA 5] Center 36 (6~66) winsize 61
7534 00:56:50.931733
7535 00:56:50.935265 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 00:56:50.935348
7537 00:56:50.941842 [CATrainingPosCal] consider 2 rank data
7538 00:56:50.941925 u2DelayCellTimex100 = 258/100 ps
7539 00:56:50.948412 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7540 00:56:50.951886 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7541 00:56:50.955018 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7542 00:56:50.958565 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7543 00:56:50.961899 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7544 00:56:50.965047 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7545 00:56:50.965130
7546 00:56:50.968483 CA PerBit enable=1, Macro0, CA PI delay=36
7547 00:56:50.968566
7548 00:56:50.971695 [CBTSetCACLKResult] CA Dly = 36
7549 00:56:50.975099 CS Dly: 11 (0~43)
7550 00:56:50.978546 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 00:56:50.981526 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 00:56:50.981610
7553 00:56:50.985124 ----->DramcWriteLeveling(PI) begin...
7554 00:56:50.985207 ==
7555 00:56:50.988364 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 00:56:50.994754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 00:56:50.994837 ==
7558 00:56:50.998361 Write leveling (Byte 0): 36 => 36
7559 00:56:51.001626 Write leveling (Byte 1): 28 => 28
7560 00:56:51.001709 DramcWriteLeveling(PI) end<-----
7561 00:56:51.004835
7562 00:56:51.004915 ==
7563 00:56:51.008247 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 00:56:51.011350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 00:56:51.011432 ==
7566 00:56:51.014690 [Gating] SW mode calibration
7567 00:56:51.021258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7568 00:56:51.024661 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7569 00:56:51.031095 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 00:56:51.034608 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 00:56:51.037946 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 00:56:51.044582 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 00:56:51.047834 1 4 16 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7574 00:56:51.050814 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7575 00:56:51.057469 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7576 00:56:51.061000 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7577 00:56:51.064253 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7578 00:56:51.070815 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7579 00:56:51.074158 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 00:56:51.077511 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7581 00:56:51.083853 1 5 16 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
7582 00:56:51.087154 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7583 00:56:51.090737 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7584 00:56:51.097281 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 00:56:51.100697 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 00:56:51.104047 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 00:56:51.110606 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 00:56:51.113870 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 00:56:51.117167 1 6 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7590 00:56:51.123673 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7591 00:56:51.127213 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7592 00:56:51.130405 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7593 00:56:51.137096 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 00:56:51.140323 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 00:56:51.143931 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 00:56:51.150451 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7597 00:56:51.153703 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7598 00:56:51.156947 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7599 00:56:51.163733 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7600 00:56:51.166926 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 00:56:51.170049 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 00:56:51.176850 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 00:56:51.180083 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 00:56:51.183558 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 00:56:51.190064 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 00:56:51.193631 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 00:56:51.196809 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 00:56:51.203228 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 00:56:51.206569 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 00:56:51.209886 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 00:56:51.216528 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 00:56:51.220026 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7613 00:56:51.223287 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7614 00:56:51.226534 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7615 00:56:51.229983 Total UI for P1: 0, mck2ui 16
7616 00:56:51.233249 best dqsien dly found for B0: ( 1, 9, 14)
7617 00:56:51.239868 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7618 00:56:51.243238 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7619 00:56:51.246701 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 00:56:51.249815 Total UI for P1: 0, mck2ui 16
7621 00:56:51.252931 best dqsien dly found for B1: ( 1, 9, 26)
7622 00:56:51.256498 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7623 00:56:51.262870 best DQS1 dly(MCK, UI, PI) = (1, 9, 26)
7624 00:56:51.262953
7625 00:56:51.266266 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7626 00:56:51.269537 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)
7627 00:56:51.272826 [Gating] SW calibration Done
7628 00:56:51.272909 ==
7629 00:56:51.276294 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 00:56:51.279614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 00:56:51.279698 ==
7632 00:56:51.282999 RX Vref Scan: 0
7633 00:56:51.283082
7634 00:56:51.283147 RX Vref 0 -> 0, step: 1
7635 00:56:51.283209
7636 00:56:51.286250 RX Delay 0 -> 252, step: 8
7637 00:56:51.289333 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7638 00:56:51.296056 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7639 00:56:51.299276 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7640 00:56:51.302621 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7641 00:56:51.305741 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7642 00:56:51.309236 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7643 00:56:51.315625 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7644 00:56:51.319195 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7645 00:56:51.322290 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7646 00:56:51.325760 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
7647 00:56:51.328972 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7648 00:56:51.335714 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7649 00:56:51.338957 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7650 00:56:51.342243 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7651 00:56:51.345560 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7652 00:56:51.348977 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7653 00:56:51.352204 ==
7654 00:56:51.355707 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 00:56:51.358797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 00:56:51.358878 ==
7657 00:56:51.358944 DQS Delay:
7658 00:56:51.362097 DQS0 = 0, DQS1 = 0
7659 00:56:51.362178 DQM Delay:
7660 00:56:51.365431 DQM0 = 127, DQM1 = 123
7661 00:56:51.365531 DQ Delay:
7662 00:56:51.368681 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7663 00:56:51.372427 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7664 00:56:51.375606 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7665 00:56:51.378899 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7666 00:56:51.378980
7667 00:56:51.379045
7668 00:56:51.379105 ==
7669 00:56:51.382209 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 00:56:51.388642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 00:56:51.388724 ==
7672 00:56:51.388790
7673 00:56:51.388849
7674 00:56:51.388908 TX Vref Scan disable
7675 00:56:51.392221 == TX Byte 0 ==
7676 00:56:51.395739 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7677 00:56:51.402301 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7678 00:56:51.402383 == TX Byte 1 ==
7679 00:56:51.405349 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7680 00:56:51.412027 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7681 00:56:51.412131 ==
7682 00:56:51.415461 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 00:56:51.418614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 00:56:51.418698 ==
7685 00:56:51.433216
7686 00:56:51.436694 TX Vref early break, caculate TX vref
7687 00:56:51.439827 TX Vref=16, minBit 9, minWin=21, winSum=366
7688 00:56:51.443314 TX Vref=18, minBit 11, minWin=21, winSum=369
7689 00:56:51.446525 TX Vref=20, minBit 8, minWin=22, winSum=377
7690 00:56:51.449903 TX Vref=22, minBit 8, minWin=23, winSum=388
7691 00:56:51.453238 TX Vref=24, minBit 4, minWin=24, winSum=400
7692 00:56:51.459822 TX Vref=26, minBit 8, minWin=24, winSum=411
7693 00:56:51.463000 TX Vref=28, minBit 8, minWin=23, winSum=408
7694 00:56:51.466481 TX Vref=30, minBit 8, minWin=23, winSum=401
7695 00:56:51.469694 TX Vref=32, minBit 9, minWin=22, winSum=393
7696 00:56:51.472870 TX Vref=34, minBit 8, minWin=22, winSum=390
7697 00:56:51.476441 TX Vref=36, minBit 8, minWin=21, winSum=373
7698 00:56:51.482934 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 26
7699 00:56:51.483017
7700 00:56:51.486300 Final TX Range 0 Vref 26
7701 00:56:51.486382
7702 00:56:51.486446 ==
7703 00:56:51.489495 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 00:56:51.492915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 00:56:51.492997 ==
7706 00:56:51.493072
7707 00:56:51.496091
7708 00:56:51.496171 TX Vref Scan disable
7709 00:56:51.502973 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7710 00:56:51.503058 == TX Byte 0 ==
7711 00:56:51.506150 u2DelayCellOfst[0]=15 cells (4 PI)
7712 00:56:51.509561 u2DelayCellOfst[1]=18 cells (5 PI)
7713 00:56:51.512809 u2DelayCellOfst[2]=11 cells (3 PI)
7714 00:56:51.515992 u2DelayCellOfst[3]=11 cells (3 PI)
7715 00:56:51.519448 u2DelayCellOfst[4]=7 cells (2 PI)
7716 00:56:51.522596 u2DelayCellOfst[5]=0 cells (0 PI)
7717 00:56:51.526240 u2DelayCellOfst[6]=18 cells (5 PI)
7718 00:56:51.529442 u2DelayCellOfst[7]=18 cells (5 PI)
7719 00:56:51.532715 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7720 00:56:51.536101 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7721 00:56:51.539202 == TX Byte 1 ==
7722 00:56:51.542821 u2DelayCellOfst[8]=0 cells (0 PI)
7723 00:56:51.545960 u2DelayCellOfst[9]=3 cells (1 PI)
7724 00:56:51.549154 u2DelayCellOfst[10]=7 cells (2 PI)
7725 00:56:51.549235 u2DelayCellOfst[11]=7 cells (2 PI)
7726 00:56:51.552651 u2DelayCellOfst[12]=11 cells (3 PI)
7727 00:56:51.555867 u2DelayCellOfst[13]=11 cells (3 PI)
7728 00:56:51.558956 u2DelayCellOfst[14]=15 cells (4 PI)
7729 00:56:51.562494 u2DelayCellOfst[15]=11 cells (3 PI)
7730 00:56:51.568998 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7731 00:56:51.572151 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7732 00:56:51.572233 DramC Write-DBI on
7733 00:56:51.575472 ==
7734 00:56:51.578972 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 00:56:51.582247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 00:56:51.582330 ==
7737 00:56:51.582396
7738 00:56:51.582458
7739 00:56:51.585601 TX Vref Scan disable
7740 00:56:51.585683 == TX Byte 0 ==
7741 00:56:51.592178 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7742 00:56:51.592262 == TX Byte 1 ==
7743 00:56:51.595424 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7744 00:56:51.598873 DramC Write-DBI off
7745 00:56:51.598961
7746 00:56:51.599027 [DATLAT]
7747 00:56:51.602163 Freq=1600, CH0 RK0
7748 00:56:51.602262
7749 00:56:51.602332 DATLAT Default: 0xf
7750 00:56:51.605647 0, 0xFFFF, sum = 0
7751 00:56:51.605745 1, 0xFFFF, sum = 0
7752 00:56:51.608989 2, 0xFFFF, sum = 0
7753 00:56:51.609077 3, 0xFFFF, sum = 0
7754 00:56:51.612217 4, 0xFFFF, sum = 0
7755 00:56:51.612306 5, 0xFFFF, sum = 0
7756 00:56:51.615590 6, 0xFFFF, sum = 0
7757 00:56:51.615677 7, 0xFFFF, sum = 0
7758 00:56:51.618967 8, 0xFFFF, sum = 0
7759 00:56:51.622079 9, 0xFFFF, sum = 0
7760 00:56:51.622165 10, 0xFFFF, sum = 0
7761 00:56:51.625190 11, 0xFFFF, sum = 0
7762 00:56:51.625275 12, 0xFFFF, sum = 0
7763 00:56:51.628662 13, 0xEFFF, sum = 0
7764 00:56:51.628747 14, 0x0, sum = 1
7765 00:56:51.631867 15, 0x0, sum = 2
7766 00:56:51.631951 16, 0x0, sum = 3
7767 00:56:51.635238 17, 0x0, sum = 4
7768 00:56:51.635323 best_step = 15
7769 00:56:51.635389
7770 00:56:51.635451 ==
7771 00:56:51.638557 Dram Type= 6, Freq= 0, CH_0, rank 0
7772 00:56:51.641972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7773 00:56:51.642056 ==
7774 00:56:51.645207 RX Vref Scan: 1
7775 00:56:51.645291
7776 00:56:51.648727 Set Vref Range= 24 -> 127
7777 00:56:51.648811
7778 00:56:51.648877 RX Vref 24 -> 127, step: 1
7779 00:56:51.648939
7780 00:56:51.651849 RX Delay 3 -> 252, step: 4
7781 00:56:51.651932
7782 00:56:51.655288 Set Vref, RX VrefLevel [Byte0]: 24
7783 00:56:51.658250 [Byte1]: 24
7784 00:56:51.661815
7785 00:56:51.661899 Set Vref, RX VrefLevel [Byte0]: 25
7786 00:56:51.665298 [Byte1]: 25
7787 00:56:51.669673
7788 00:56:51.669765 Set Vref, RX VrefLevel [Byte0]: 26
7789 00:56:51.672885 [Byte1]: 26
7790 00:56:51.677198
7791 00:56:51.677281 Set Vref, RX VrefLevel [Byte0]: 27
7792 00:56:51.680691 [Byte1]: 27
7793 00:56:51.684991
7794 00:56:51.685074 Set Vref, RX VrefLevel [Byte0]: 28
7795 00:56:51.688275 [Byte1]: 28
7796 00:56:51.692619
7797 00:56:51.692704 Set Vref, RX VrefLevel [Byte0]: 29
7798 00:56:51.695794 [Byte1]: 29
7799 00:56:51.700282
7800 00:56:51.700371 Set Vref, RX VrefLevel [Byte0]: 30
7801 00:56:51.703483 [Byte1]: 30
7802 00:56:51.707731
7803 00:56:51.707818 Set Vref, RX VrefLevel [Byte0]: 31
7804 00:56:51.711329 [Byte1]: 31
7805 00:56:51.715365
7806 00:56:51.715452 Set Vref, RX VrefLevel [Byte0]: 32
7807 00:56:51.718914 [Byte1]: 32
7808 00:56:51.723078
7809 00:56:51.723170 Set Vref, RX VrefLevel [Byte0]: 33
7810 00:56:51.726452 [Byte1]: 33
7811 00:56:51.730696
7812 00:56:51.730788 Set Vref, RX VrefLevel [Byte0]: 34
7813 00:56:51.734251 [Byte1]: 34
7814 00:56:51.738527
7815 00:56:51.738612 Set Vref, RX VrefLevel [Byte0]: 35
7816 00:56:51.741663 [Byte1]: 35
7817 00:56:51.746057
7818 00:56:51.746142 Set Vref, RX VrefLevel [Byte0]: 36
7819 00:56:51.749479 [Byte1]: 36
7820 00:56:51.753890
7821 00:56:51.753977 Set Vref, RX VrefLevel [Byte0]: 37
7822 00:56:51.757192 [Byte1]: 37
7823 00:56:51.761359
7824 00:56:51.761447 Set Vref, RX VrefLevel [Byte0]: 38
7825 00:56:51.764637 [Byte1]: 38
7826 00:56:51.768904
7827 00:56:51.768990 Set Vref, RX VrefLevel [Byte0]: 39
7828 00:56:51.772535 [Byte1]: 39
7829 00:56:51.776867
7830 00:56:51.776956 Set Vref, RX VrefLevel [Byte0]: 40
7831 00:56:51.779934 [Byte1]: 40
7832 00:56:51.784248
7833 00:56:51.784339 Set Vref, RX VrefLevel [Byte0]: 41
7834 00:56:51.787816 [Byte1]: 41
7835 00:56:51.791971
7836 00:56:51.792058 Set Vref, RX VrefLevel [Byte0]: 42
7837 00:56:51.795226 [Byte1]: 42
7838 00:56:51.799645
7839 00:56:51.799735 Set Vref, RX VrefLevel [Byte0]: 43
7840 00:56:51.802958 [Byte1]: 43
7841 00:56:51.807435
7842 00:56:51.807523 Set Vref, RX VrefLevel [Byte0]: 44
7843 00:56:51.810524 [Byte1]: 44
7844 00:56:51.814971
7845 00:56:51.815059 Set Vref, RX VrefLevel [Byte0]: 45
7846 00:56:51.818148 [Byte1]: 45
7847 00:56:51.822525
7848 00:56:51.822613 Set Vref, RX VrefLevel [Byte0]: 46
7849 00:56:51.825825 [Byte1]: 46
7850 00:56:51.830311
7851 00:56:51.830403 Set Vref, RX VrefLevel [Byte0]: 47
7852 00:56:51.833586 [Byte1]: 47
7853 00:56:51.837836
7854 00:56:51.837925 Set Vref, RX VrefLevel [Byte0]: 48
7855 00:56:51.841428 [Byte1]: 48
7856 00:56:51.845703
7857 00:56:51.845799 Set Vref, RX VrefLevel [Byte0]: 49
7858 00:56:51.848779 [Byte1]: 49
7859 00:56:51.853101
7860 00:56:51.853194 Set Vref, RX VrefLevel [Byte0]: 50
7861 00:56:51.859550 [Byte1]: 50
7862 00:56:51.859643
7863 00:56:51.862862 Set Vref, RX VrefLevel [Byte0]: 51
7864 00:56:51.866348 [Byte1]: 51
7865 00:56:51.866437
7866 00:56:51.869573 Set Vref, RX VrefLevel [Byte0]: 52
7867 00:56:51.872850 [Byte1]: 52
7868 00:56:51.876396
7869 00:56:51.876480 Set Vref, RX VrefLevel [Byte0]: 53
7870 00:56:51.879573 [Byte1]: 53
7871 00:56:51.883907
7872 00:56:51.883995 Set Vref, RX VrefLevel [Byte0]: 54
7873 00:56:51.887024 [Byte1]: 54
7874 00:56:51.891625
7875 00:56:51.891713 Set Vref, RX VrefLevel [Byte0]: 55
7876 00:56:51.894989 [Byte1]: 55
7877 00:56:51.899224
7878 00:56:51.899310 Set Vref, RX VrefLevel [Byte0]: 56
7879 00:56:51.902494 [Byte1]: 56
7880 00:56:51.906656
7881 00:56:51.906751 Set Vref, RX VrefLevel [Byte0]: 57
7882 00:56:51.910269 [Byte1]: 57
7883 00:56:51.914513
7884 00:56:51.914602 Set Vref, RX VrefLevel [Byte0]: 58
7885 00:56:51.917713 [Byte1]: 58
7886 00:56:51.921980
7887 00:56:51.925333 Set Vref, RX VrefLevel [Byte0]: 59
7888 00:56:51.925420 [Byte1]: 59
7889 00:56:51.929832
7890 00:56:51.929948 Set Vref, RX VrefLevel [Byte0]: 60
7891 00:56:51.933001 [Byte1]: 60
7892 00:56:51.937422
7893 00:56:51.937562 Set Vref, RX VrefLevel [Byte0]: 61
7894 00:56:51.940654 [Byte1]: 61
7895 00:56:51.945080
7896 00:56:51.945175 Set Vref, RX VrefLevel [Byte0]: 62
7897 00:56:51.948342 [Byte1]: 62
7898 00:56:51.952647
7899 00:56:51.952739 Set Vref, RX VrefLevel [Byte0]: 63
7900 00:56:51.956227 [Byte1]: 63
7901 00:56:51.960372
7902 00:56:51.960448 Set Vref, RX VrefLevel [Byte0]: 64
7903 00:56:51.963526 [Byte1]: 64
7904 00:56:51.967988
7905 00:56:51.968113 Set Vref, RX VrefLevel [Byte0]: 65
7906 00:56:51.971431 [Byte1]: 65
7907 00:56:51.975722
7908 00:56:51.975803 Set Vref, RX VrefLevel [Byte0]: 66
7909 00:56:51.978835 [Byte1]: 66
7910 00:56:51.983446
7911 00:56:51.983521 Set Vref, RX VrefLevel [Byte0]: 67
7912 00:56:51.986598 [Byte1]: 67
7913 00:56:51.990900
7914 00:56:51.991005 Set Vref, RX VrefLevel [Byte0]: 68
7915 00:56:51.994340 [Byte1]: 68
7916 00:56:51.998622
7917 00:56:51.998699 Set Vref, RX VrefLevel [Byte0]: 69
7918 00:56:52.001921 [Byte1]: 69
7919 00:56:52.006219
7920 00:56:52.006312 Set Vref, RX VrefLevel [Byte0]: 70
7921 00:56:52.009469 [Byte1]: 70
7922 00:56:52.013971
7923 00:56:52.014068 Set Vref, RX VrefLevel [Byte0]: 71
7924 00:56:52.017213 [Byte1]: 71
7925 00:56:52.021446
7926 00:56:52.021567 Set Vref, RX VrefLevel [Byte0]: 72
7927 00:56:52.024819 [Byte1]: 72
7928 00:56:52.029137
7929 00:56:52.029219 Set Vref, RX VrefLevel [Byte0]: 73
7930 00:56:52.032365 [Byte1]: 73
7931 00:56:52.036741
7932 00:56:52.036826 Set Vref, RX VrefLevel [Byte0]: 74
7933 00:56:52.040086 [Byte1]: 74
7934 00:56:52.044390
7935 00:56:52.044478 Final RX Vref Byte 0 = 64 to rank0
7936 00:56:52.047725 Final RX Vref Byte 1 = 60 to rank0
7937 00:56:52.051240 Final RX Vref Byte 0 = 64 to rank1
7938 00:56:52.054663 Final RX Vref Byte 1 = 60 to rank1==
7939 00:56:52.057858 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 00:56:52.064247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 00:56:52.064353 ==
7942 00:56:52.064421 DQS Delay:
7943 00:56:52.067532 DQS0 = 0, DQS1 = 0
7944 00:56:52.067615 DQM Delay:
7945 00:56:52.067695 DQM0 = 126, DQM1 = 119
7946 00:56:52.071000 DQ Delay:
7947 00:56:52.074732 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7948 00:56:52.077658 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7949 00:56:52.080989 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7950 00:56:52.084257 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7951 00:56:52.084346
7952 00:56:52.084413
7953 00:56:52.084474
7954 00:56:52.087833 [DramC_TX_OE_Calibration] TA2
7955 00:56:52.091045 Original DQ_B0 (3 6) =30, OEN = 27
7956 00:56:52.094310 Original DQ_B1 (3 6) =30, OEN = 27
7957 00:56:52.097748 24, 0x0, End_B0=24 End_B1=24
7958 00:56:52.097835 25, 0x0, End_B0=25 End_B1=25
7959 00:56:52.100933 26, 0x0, End_B0=26 End_B1=26
7960 00:56:52.104210 27, 0x0, End_B0=27 End_B1=27
7961 00:56:52.107574 28, 0x0, End_B0=28 End_B1=28
7962 00:56:52.110936 29, 0x0, End_B0=29 End_B1=29
7963 00:56:52.111026 30, 0x0, End_B0=30 End_B1=30
7964 00:56:52.114249 31, 0x4141, End_B0=30 End_B1=30
7965 00:56:52.117257 Byte0 end_step=30 best_step=27
7966 00:56:52.120843 Byte1 end_step=30 best_step=27
7967 00:56:52.124095 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 00:56:52.127414 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 00:56:52.127529
7970 00:56:52.127622
7971 00:56:52.133965 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7972 00:56:52.137222 CH0 RK0: MR19=303, MR18=1515
7973 00:56:52.144049 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
7974 00:56:52.144166
7975 00:56:52.147105 ----->DramcWriteLeveling(PI) begin...
7976 00:56:52.147194 ==
7977 00:56:52.150426 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 00:56:52.153927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 00:56:52.154042 ==
7980 00:56:52.156963 Write leveling (Byte 0): 36 => 36
7981 00:56:52.160504 Write leveling (Byte 1): 28 => 28
7982 00:56:52.163837 DramcWriteLeveling(PI) end<-----
7983 00:56:52.163925
7984 00:56:52.163991 ==
7985 00:56:52.166945 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 00:56:52.170423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 00:56:52.170511 ==
7988 00:56:52.173582 [Gating] SW mode calibration
7989 00:56:52.180280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 00:56:52.186916 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 00:56:52.190212 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 00:56:52.196577 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 00:56:52.200101 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 00:56:52.203212 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7995 00:56:52.210057 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7996 00:56:52.213203 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 00:56:52.216817 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 00:56:52.223125 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 00:56:52.226693 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 00:56:52.229813 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 00:56:52.236568 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8002 00:56:52.239841 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
8003 00:56:52.243188 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8004 00:56:52.246363 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8005 00:56:52.253143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 00:56:52.256626 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 00:56:52.259927 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 00:56:52.266346 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 00:56:52.269602 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8010 00:56:52.273262 1 6 12 | B1->B0 | 2424 4343 | 0 1 | (0 0) (0 0)
8011 00:56:52.279624 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8012 00:56:52.282804 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 00:56:52.286050 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 00:56:52.292918 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 00:56:52.295998 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 00:56:52.299559 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 00:56:52.306044 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 00:56:52.309335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8019 00:56:52.312865 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8020 00:56:52.319327 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 00:56:52.322544 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 00:56:52.325895 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 00:56:52.332551 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 00:56:52.335810 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 00:56:52.338924 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 00:56:52.345649 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 00:56:52.348910 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 00:56:52.352446 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 00:56:52.358859 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 00:56:52.362246 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 00:56:52.365719 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 00:56:52.371983 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 00:56:52.375704 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 00:56:52.378805 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8035 00:56:52.382257 Total UI for P1: 0, mck2ui 16
8036 00:56:52.385356 best dqsien dly found for B0: ( 1, 9, 8)
8037 00:56:52.392185 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8038 00:56:52.395410 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8039 00:56:52.398608 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 00:56:52.401990 Total UI for P1: 0, mck2ui 16
8041 00:56:52.405431 best dqsien dly found for B1: ( 1, 9, 16)
8042 00:56:52.408534 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8043 00:56:52.412180 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8044 00:56:52.412290
8045 00:56:52.418667 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8046 00:56:52.421823 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8047 00:56:52.421907 [Gating] SW calibration Done
8048 00:56:52.425364 ==
8049 00:56:52.428602 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 00:56:52.431994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 00:56:52.432086 ==
8052 00:56:52.432154 RX Vref Scan: 0
8053 00:56:52.432215
8054 00:56:52.435182 RX Vref 0 -> 0, step: 1
8055 00:56:52.435266
8056 00:56:52.438683 RX Delay 0 -> 252, step: 8
8057 00:56:52.441773 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8058 00:56:52.445184 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8059 00:56:52.448511 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8060 00:56:52.455120 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8061 00:56:52.458374 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8062 00:56:52.461607 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8063 00:56:52.464917 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8064 00:56:52.468218 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8065 00:56:52.474933 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8066 00:56:52.478116 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8067 00:56:52.481289 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8068 00:56:52.484741 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8069 00:56:52.491208 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8070 00:56:52.494765 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8071 00:56:52.497992 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8072 00:56:52.501281 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8073 00:56:52.501368 ==
8074 00:56:52.504470 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 00:56:52.511088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 00:56:52.511200 ==
8077 00:56:52.511272 DQS Delay:
8078 00:56:52.511334 DQS0 = 0, DQS1 = 0
8079 00:56:52.514454 DQM Delay:
8080 00:56:52.514538 DQM0 = 128, DQM1 = 122
8081 00:56:52.517881 DQ Delay:
8082 00:56:52.521182 DQ0 =127, DQ1 =127, DQ2 =127, DQ3 =123
8083 00:56:52.524309 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8084 00:56:52.527946 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8085 00:56:52.531433 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8086 00:56:52.531527
8087 00:56:52.531596
8088 00:56:52.531658 ==
8089 00:56:52.534401 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 00:56:52.537691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 00:56:52.540933 ==
8092 00:56:52.541022
8093 00:56:52.541108
8094 00:56:52.541189 TX Vref Scan disable
8095 00:56:52.544240 == TX Byte 0 ==
8096 00:56:52.547809 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8097 00:56:52.550754 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8098 00:56:52.554416 == TX Byte 1 ==
8099 00:56:52.557602 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8100 00:56:52.560833 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8101 00:56:52.564308 ==
8102 00:56:52.564426 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 00:56:52.570668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 00:56:52.570784 ==
8105 00:56:52.583592
8106 00:56:52.587189 TX Vref early break, caculate TX vref
8107 00:56:52.590192 TX Vref=16, minBit 8, minWin=21, winSum=369
8108 00:56:52.593597 TX Vref=18, minBit 8, minWin=22, winSum=377
8109 00:56:52.597071 TX Vref=20, minBit 8, minWin=22, winSum=384
8110 00:56:52.600106 TX Vref=22, minBit 8, minWin=24, winSum=400
8111 00:56:52.603645 TX Vref=24, minBit 8, minWin=23, winSum=400
8112 00:56:52.610135 TX Vref=26, minBit 8, minWin=24, winSum=413
8113 00:56:52.613320 TX Vref=28, minBit 8, minWin=24, winSum=414
8114 00:56:52.616605 TX Vref=30, minBit 8, minWin=24, winSum=410
8115 00:56:52.620094 TX Vref=32, minBit 8, minWin=23, winSum=404
8116 00:56:52.623499 TX Vref=34, minBit 8, minWin=22, winSum=391
8117 00:56:52.630284 [TxChooseVref] Worse bit 8, Min win 24, Win sum 414, Final Vref 28
8118 00:56:52.630397
8119 00:56:52.633468 Final TX Range 0 Vref 28
8120 00:56:52.633581
8121 00:56:52.633667 ==
8122 00:56:52.636610 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 00:56:52.639990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 00:56:52.640082 ==
8125 00:56:52.640169
8126 00:56:52.640249
8127 00:56:52.643197 TX Vref Scan disable
8128 00:56:52.650078 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8129 00:56:52.650182 == TX Byte 0 ==
8130 00:56:52.653319 u2DelayCellOfst[0]=15 cells (4 PI)
8131 00:56:52.656677 u2DelayCellOfst[1]=15 cells (4 PI)
8132 00:56:52.659928 u2DelayCellOfst[2]=11 cells (3 PI)
8133 00:56:52.663287 u2DelayCellOfst[3]=11 cells (3 PI)
8134 00:56:52.666631 u2DelayCellOfst[4]=7 cells (2 PI)
8135 00:56:52.670057 u2DelayCellOfst[5]=0 cells (0 PI)
8136 00:56:52.673120 u2DelayCellOfst[6]=18 cells (5 PI)
8137 00:56:52.676611 u2DelayCellOfst[7]=15 cells (4 PI)
8138 00:56:52.679856 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8139 00:56:52.683104 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8140 00:56:52.686348 == TX Byte 1 ==
8141 00:56:52.686443 u2DelayCellOfst[8]=0 cells (0 PI)
8142 00:56:52.689914 u2DelayCellOfst[9]=3 cells (1 PI)
8143 00:56:52.693099 u2DelayCellOfst[10]=11 cells (3 PI)
8144 00:56:52.696281 u2DelayCellOfst[11]=7 cells (2 PI)
8145 00:56:52.699846 u2DelayCellOfst[12]=15 cells (4 PI)
8146 00:56:52.703077 u2DelayCellOfst[13]=15 cells (4 PI)
8147 00:56:52.706396 u2DelayCellOfst[14]=15 cells (4 PI)
8148 00:56:52.709424 u2DelayCellOfst[15]=11 cells (3 PI)
8149 00:56:52.713188 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8150 00:56:52.719633 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8151 00:56:52.719744 DramC Write-DBI on
8152 00:56:52.719836 ==
8153 00:56:52.722970 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 00:56:52.729431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 00:56:52.729588 ==
8156 00:56:52.729691
8157 00:56:52.729789
8158 00:56:52.729887 TX Vref Scan disable
8159 00:56:52.733239 == TX Byte 0 ==
8160 00:56:52.736585 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8161 00:56:52.740258 == TX Byte 1 ==
8162 00:56:52.743565 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8163 00:56:52.743666 DramC Write-DBI off
8164 00:56:52.746838
8165 00:56:52.746925 [DATLAT]
8166 00:56:52.747010 Freq=1600, CH0 RK1
8167 00:56:52.747091
8168 00:56:52.749998 DATLAT Default: 0xf
8169 00:56:52.750085 0, 0xFFFF, sum = 0
8170 00:56:52.753584 1, 0xFFFF, sum = 0
8171 00:56:52.753699 2, 0xFFFF, sum = 0
8172 00:56:52.756676 3, 0xFFFF, sum = 0
8173 00:56:52.756764 4, 0xFFFF, sum = 0
8174 00:56:52.759940 5, 0xFFFF, sum = 0
8175 00:56:52.763273 6, 0xFFFF, sum = 0
8176 00:56:52.763368 7, 0xFFFF, sum = 0
8177 00:56:52.766746 8, 0xFFFF, sum = 0
8178 00:56:52.766837 9, 0xFFFF, sum = 0
8179 00:56:52.769975 10, 0xFFFF, sum = 0
8180 00:56:52.770064 11, 0xFFFF, sum = 0
8181 00:56:52.773201 12, 0xFFFF, sum = 0
8182 00:56:52.773315 13, 0xCFFF, sum = 0
8183 00:56:52.776764 14, 0x0, sum = 1
8184 00:56:52.776853 15, 0x0, sum = 2
8185 00:56:52.780326 16, 0x0, sum = 3
8186 00:56:52.780416 17, 0x0, sum = 4
8187 00:56:52.780514 best_step = 15
8188 00:56:52.783588
8189 00:56:52.783670 ==
8190 00:56:52.786741 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 00:56:52.789951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 00:56:52.790036 ==
8193 00:56:52.790102 RX Vref Scan: 0
8194 00:56:52.790163
8195 00:56:52.793224 RX Vref 0 -> 0, step: 1
8196 00:56:52.793307
8197 00:56:52.796686 RX Delay 3 -> 252, step: 4
8198 00:56:52.799935 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8199 00:56:52.806549 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8200 00:56:52.809797 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8201 00:56:52.813163 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8202 00:56:52.816352 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8203 00:56:52.819774 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8204 00:56:52.826344 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8205 00:56:52.830002 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8206 00:56:52.833215 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8207 00:56:52.836557 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8208 00:56:52.839879 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8209 00:56:52.846165 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8210 00:56:52.849625 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8211 00:56:52.852858 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8212 00:56:52.856014 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8213 00:56:52.859273 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8214 00:56:52.862860 ==
8215 00:56:52.866019 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 00:56:52.869375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 00:56:52.869459 ==
8218 00:56:52.869584 DQS Delay:
8219 00:56:52.872535 DQS0 = 0, DQS1 = 0
8220 00:56:52.872637 DQM Delay:
8221 00:56:52.876054 DQM0 = 124, DQM1 = 118
8222 00:56:52.876162 DQ Delay:
8223 00:56:52.879310 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8224 00:56:52.882400 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8225 00:56:52.885605 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8226 00:56:52.889220 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8227 00:56:52.889308
8228 00:56:52.889408
8229 00:56:52.892195
8230 00:56:52.892272 [DramC_TX_OE_Calibration] TA2
8231 00:56:52.895640 Original DQ_B0 (3 6) =30, OEN = 27
8232 00:56:52.898834 Original DQ_B1 (3 6) =30, OEN = 27
8233 00:56:52.902213 24, 0x0, End_B0=24 End_B1=24
8234 00:56:52.905742 25, 0x0, End_B0=25 End_B1=25
8235 00:56:52.909089 26, 0x0, End_B0=26 End_B1=26
8236 00:56:52.909183 27, 0x0, End_B0=27 End_B1=27
8237 00:56:52.912221 28, 0x0, End_B0=28 End_B1=28
8238 00:56:52.915499 29, 0x0, End_B0=29 End_B1=29
8239 00:56:52.918682 30, 0x0, End_B0=30 End_B1=30
8240 00:56:52.921869 31, 0x4141, End_B0=30 End_B1=30
8241 00:56:52.921953 Byte0 end_step=30 best_step=27
8242 00:56:52.925245 Byte1 end_step=30 best_step=27
8243 00:56:52.928734 Byte0 TX OE(2T, 0.5T) = (3, 3)
8244 00:56:52.932058 Byte1 TX OE(2T, 0.5T) = (3, 3)
8245 00:56:52.932157
8246 00:56:52.932224
8247 00:56:52.938462 [DQSOSCAuto] RK1, (LSB)MR18= 0x2713, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
8248 00:56:52.941823 CH0 RK1: MR19=303, MR18=2713
8249 00:56:52.948538 CH0_RK1: MR19=0x303, MR18=0x2713, DQSOSC=390, MR23=63, INC=24, DEC=16
8250 00:56:52.951911 [RxdqsGatingPostProcess] freq 1600
8251 00:56:52.958569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8252 00:56:52.961808 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 00:56:52.961907 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 00:56:52.965003 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 00:56:52.968591 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 00:56:52.971746 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 00:56:52.975020 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 00:56:52.978471 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 00:56:52.981597 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 00:56:52.985011 Pre-setting of DQS Precalculation
8261 00:56:52.988235 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8262 00:56:52.991708 ==
8263 00:56:52.994909 Dram Type= 6, Freq= 0, CH_1, rank 0
8264 00:56:52.998446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 00:56:52.998534 ==
8266 00:56:53.001555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8267 00:56:53.008211 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8268 00:56:53.011396 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8269 00:56:53.018007 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8270 00:56:53.026592 [CA 0] Center 41 (12~71) winsize 60
8271 00:56:53.029635 [CA 1] Center 42 (13~72) winsize 60
8272 00:56:53.033106 [CA 2] Center 37 (9~66) winsize 58
8273 00:56:53.036439 [CA 3] Center 36 (7~66) winsize 60
8274 00:56:53.039584 [CA 4] Center 37 (8~66) winsize 59
8275 00:56:53.043047 [CA 5] Center 36 (7~66) winsize 60
8276 00:56:53.043143
8277 00:56:53.046290 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8278 00:56:53.046377
8279 00:56:53.052663 [CATrainingPosCal] consider 1 rank data
8280 00:56:53.052761 u2DelayCellTimex100 = 258/100 ps
8281 00:56:53.059283 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8282 00:56:53.062503 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8283 00:56:53.066019 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8284 00:56:53.069230 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8285 00:56:53.072536 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8286 00:56:53.076065 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8287 00:56:53.076159
8288 00:56:53.079195 CA PerBit enable=1, Macro0, CA PI delay=36
8289 00:56:53.079287
8290 00:56:53.082446 [CBTSetCACLKResult] CA Dly = 36
8291 00:56:53.085870 CS Dly: 9 (0~40)
8292 00:56:53.089061 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8293 00:56:53.092624 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8294 00:56:53.092723 ==
8295 00:56:53.095803 Dram Type= 6, Freq= 0, CH_1, rank 1
8296 00:56:53.099264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 00:56:53.102383 ==
8298 00:56:53.105962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 00:56:53.109121 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 00:56:53.115839 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 00:56:53.122241 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 00:56:53.129512 [CA 0] Center 42 (13~71) winsize 59
8303 00:56:53.132716 [CA 1] Center 42 (12~72) winsize 61
8304 00:56:53.136232 [CA 2] Center 37 (8~67) winsize 60
8305 00:56:53.139454 [CA 3] Center 36 (6~66) winsize 61
8306 00:56:53.143131 [CA 4] Center 37 (8~67) winsize 60
8307 00:56:53.146286 [CA 5] Center 36 (6~66) winsize 61
8308 00:56:53.146377
8309 00:56:53.149462 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8310 00:56:53.149586
8311 00:56:53.153045 [CATrainingPosCal] consider 2 rank data
8312 00:56:53.156202 u2DelayCellTimex100 = 258/100 ps
8313 00:56:53.159486 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8314 00:56:53.166047 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8315 00:56:53.169583 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8316 00:56:53.172624 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 00:56:53.176234 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8318 00:56:53.179520 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8319 00:56:53.179610
8320 00:56:53.182673 CA PerBit enable=1, Macro0, CA PI delay=36
8321 00:56:53.182757
8322 00:56:53.185844 [CBTSetCACLKResult] CA Dly = 36
8323 00:56:53.189375 CS Dly: 11 (0~44)
8324 00:56:53.192443 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 00:56:53.195697 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 00:56:53.195784
8327 00:56:53.199246 ----->DramcWriteLeveling(PI) begin...
8328 00:56:53.199331 ==
8329 00:56:53.202484 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 00:56:53.209071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 00:56:53.209188 ==
8332 00:56:53.212523 Write leveling (Byte 0): 24 => 24
8333 00:56:53.212614 Write leveling (Byte 1): 27 => 27
8334 00:56:53.215741 DramcWriteLeveling(PI) end<-----
8335 00:56:53.215826
8336 00:56:53.215890 ==
8337 00:56:53.218991 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 00:56:53.225645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 00:56:53.225749 ==
8340 00:56:53.229132 [Gating] SW mode calibration
8341 00:56:53.235583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8342 00:56:53.238807 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8343 00:56:53.245327 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 00:56:53.248862 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 00:56:53.251934 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 00:56:53.258745 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 00:56:53.262081 1 4 16 | B1->B0 | 3434 3433 | 0 1 | (0 0) (0 0)
8348 00:56:53.265252 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8349 00:56:53.271787 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 00:56:53.275371 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 00:56:53.278540 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 00:56:53.285095 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 00:56:53.288430 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 00:56:53.291594 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8355 00:56:53.298146 1 5 16 | B1->B0 | 2c2c 2e2e | 0 0 | (1 0) (1 0)
8356 00:56:53.301642 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 00:56:53.304875 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 00:56:53.311594 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 00:56:53.315079 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 00:56:53.318393 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 00:56:53.324955 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 00:56:53.328150 1 6 12 | B1->B0 | 2a2a 2626 | 1 1 | (0 0) (0 0)
8363 00:56:53.331347 1 6 16 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
8364 00:56:53.338146 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 00:56:53.341259 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 00:56:53.344506 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 00:56:53.350997 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 00:56:53.354378 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 00:56:53.357659 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 00:56:53.364384 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 00:56:53.367725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 00:56:53.370913 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8373 00:56:53.377373 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 00:56:53.380884 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 00:56:53.384355 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 00:56:53.390793 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 00:56:53.393993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 00:56:53.397620 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 00:56:53.403942 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 00:56:53.407364 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 00:56:53.410657 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 00:56:53.417099 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 00:56:53.420310 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 00:56:53.423977 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 00:56:53.430556 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 00:56:53.433803 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 00:56:53.437000 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8388 00:56:53.440240 Total UI for P1: 0, mck2ui 16
8389 00:56:53.443530 best dqsien dly found for B1: ( 1, 9, 12)
8390 00:56:53.446919 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 00:56:53.450191 Total UI for P1: 0, mck2ui 16
8392 00:56:53.453547 best dqsien dly found for B0: ( 1, 9, 14)
8393 00:56:53.460321 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8394 00:56:53.463610 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8395 00:56:53.463703
8396 00:56:53.466697 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8397 00:56:53.470192 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8398 00:56:53.473206 [Gating] SW calibration Done
8399 00:56:53.473294 ==
8400 00:56:53.476671 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 00:56:53.480046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 00:56:53.480142 ==
8403 00:56:53.483198 RX Vref Scan: 0
8404 00:56:53.483283
8405 00:56:53.483348 RX Vref 0 -> 0, step: 1
8406 00:56:53.483410
8407 00:56:53.486512 RX Delay 0 -> 252, step: 8
8408 00:56:53.489889 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8409 00:56:53.493307 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8410 00:56:53.499892 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8411 00:56:53.503194 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8412 00:56:53.506549 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8413 00:56:53.510160 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8414 00:56:53.516656 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8415 00:56:53.519861 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8416 00:56:53.523041 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8417 00:56:53.526161 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8418 00:56:53.529733 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8419 00:56:53.536230 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8420 00:56:53.539844 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8421 00:56:53.543131 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8422 00:56:53.546303 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8423 00:56:53.549616 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8424 00:56:53.553232 ==
8425 00:56:53.553327 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 00:56:53.559637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 00:56:53.559741 ==
8428 00:56:53.559810 DQS Delay:
8429 00:56:53.562866 DQS0 = 0, DQS1 = 0
8430 00:56:53.562951 DQM Delay:
8431 00:56:53.566222 DQM0 = 132, DQM1 = 125
8432 00:56:53.566308 DQ Delay:
8433 00:56:53.569681 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8434 00:56:53.572697 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8435 00:56:53.576268 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8436 00:56:53.579475 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8437 00:56:53.579566
8438 00:56:53.579632
8439 00:56:53.579693 ==
8440 00:56:53.582745 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 00:56:53.589117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 00:56:53.589228 ==
8443 00:56:53.589299
8444 00:56:53.589359
8445 00:56:53.589418 TX Vref Scan disable
8446 00:56:53.592919 == TX Byte 0 ==
8447 00:56:53.596305 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8448 00:56:53.602848 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8449 00:56:53.602958 == TX Byte 1 ==
8450 00:56:53.606231 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8451 00:56:53.612813 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8452 00:56:53.612926 ==
8453 00:56:53.616069 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 00:56:53.619304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 00:56:53.619396 ==
8456 00:56:53.631715
8457 00:56:53.635275 TX Vref early break, caculate TX vref
8458 00:56:53.638338 TX Vref=16, minBit 1, minWin=22, winSum=362
8459 00:56:53.641564 TX Vref=18, minBit 1, minWin=22, winSum=371
8460 00:56:53.644747 TX Vref=20, minBit 0, minWin=23, winSum=379
8461 00:56:53.648223 TX Vref=22, minBit 1, minWin=24, winSum=393
8462 00:56:53.651565 TX Vref=24, minBit 1, minWin=24, winSum=401
8463 00:56:53.658194 TX Vref=26, minBit 0, minWin=23, winSum=410
8464 00:56:53.661321 TX Vref=28, minBit 0, minWin=25, winSum=420
8465 00:56:53.664638 TX Vref=30, minBit 0, minWin=24, winSum=413
8466 00:56:53.667919 TX Vref=32, minBit 1, minWin=24, winSum=406
8467 00:56:53.671392 TX Vref=34, minBit 6, minWin=23, winSum=397
8468 00:56:53.677855 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8469 00:56:53.677967
8470 00:56:53.681434 Final TX Range 0 Vref 28
8471 00:56:53.681569
8472 00:56:53.681636 ==
8473 00:56:53.684697 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 00:56:53.687830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 00:56:53.687924 ==
8476 00:56:53.687991
8477 00:56:53.688052
8478 00:56:53.691148 TX Vref Scan disable
8479 00:56:53.697712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8480 00:56:53.697830 == TX Byte 0 ==
8481 00:56:53.701439 u2DelayCellOfst[0]=22 cells (6 PI)
8482 00:56:53.704290 u2DelayCellOfst[1]=18 cells (5 PI)
8483 00:56:53.707648 u2DelayCellOfst[2]=0 cells (0 PI)
8484 00:56:53.711072 u2DelayCellOfst[3]=7 cells (2 PI)
8485 00:56:53.714447 u2DelayCellOfst[4]=11 cells (3 PI)
8486 00:56:53.717698 u2DelayCellOfst[5]=22 cells (6 PI)
8487 00:56:53.720776 u2DelayCellOfst[6]=22 cells (6 PI)
8488 00:56:53.724274 u2DelayCellOfst[7]=7 cells (2 PI)
8489 00:56:53.727551 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8490 00:56:53.730812 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8491 00:56:53.734357 == TX Byte 1 ==
8492 00:56:53.737205 u2DelayCellOfst[8]=0 cells (0 PI)
8493 00:56:53.737302 u2DelayCellOfst[9]=7 cells (2 PI)
8494 00:56:53.740579 u2DelayCellOfst[10]=15 cells (4 PI)
8495 00:56:53.743978 u2DelayCellOfst[11]=11 cells (3 PI)
8496 00:56:53.747308 u2DelayCellOfst[12]=15 cells (4 PI)
8497 00:56:53.750561 u2DelayCellOfst[13]=22 cells (6 PI)
8498 00:56:53.754046 u2DelayCellOfst[14]=22 cells (6 PI)
8499 00:56:53.757116 u2DelayCellOfst[15]=22 cells (6 PI)
8500 00:56:53.763790 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8501 00:56:53.767243 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8502 00:56:53.767347 DramC Write-DBI on
8503 00:56:53.767433 ==
8504 00:56:53.770477 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 00:56:53.777042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 00:56:53.777148 ==
8507 00:56:53.777240
8508 00:56:53.777322
8509 00:56:53.777419 TX Vref Scan disable
8510 00:56:53.781189 == TX Byte 0 ==
8511 00:56:53.784731 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8512 00:56:53.788039 == TX Byte 1 ==
8513 00:56:53.791345 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8514 00:56:53.794564 DramC Write-DBI off
8515 00:56:53.794657
8516 00:56:53.794745 [DATLAT]
8517 00:56:53.794826 Freq=1600, CH1 RK0
8518 00:56:53.794905
8519 00:56:53.797644 DATLAT Default: 0xf
8520 00:56:53.797731 0, 0xFFFF, sum = 0
8521 00:56:53.801045 1, 0xFFFF, sum = 0
8522 00:56:53.804311 2, 0xFFFF, sum = 0
8523 00:56:53.804433 3, 0xFFFF, sum = 0
8524 00:56:53.807578 4, 0xFFFF, sum = 0
8525 00:56:53.807677 5, 0xFFFF, sum = 0
8526 00:56:53.810876 6, 0xFFFF, sum = 0
8527 00:56:53.810983 7, 0xFFFF, sum = 0
8528 00:56:53.814510 8, 0xFFFF, sum = 0
8529 00:56:53.814603 9, 0xFFFF, sum = 0
8530 00:56:53.817613 10, 0xFFFF, sum = 0
8531 00:56:53.817710 11, 0xFFFF, sum = 0
8532 00:56:53.820705 12, 0xFFFF, sum = 0
8533 00:56:53.820829 13, 0x8FFF, sum = 0
8534 00:56:53.824007 14, 0x0, sum = 1
8535 00:56:53.824097 15, 0x0, sum = 2
8536 00:56:53.827252 16, 0x0, sum = 3
8537 00:56:53.827342 17, 0x0, sum = 4
8538 00:56:53.830807 best_step = 15
8539 00:56:53.830898
8540 00:56:53.830985 ==
8541 00:56:53.833909 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 00:56:53.837348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 00:56:53.837447 ==
8544 00:56:53.840725 RX Vref Scan: 1
8545 00:56:53.840815
8546 00:56:53.840929 Set Vref Range= 24 -> 127
8547 00:56:53.841010
8548 00:56:53.844012 RX Vref 24 -> 127, step: 1
8549 00:56:53.844099
8550 00:56:53.847046 RX Delay 11 -> 252, step: 4
8551 00:56:53.847147
8552 00:56:53.850368 Set Vref, RX VrefLevel [Byte0]: 24
8553 00:56:53.853806 [Byte1]: 24
8554 00:56:53.853905
8555 00:56:53.856916 Set Vref, RX VrefLevel [Byte0]: 25
8556 00:56:53.860194 [Byte1]: 25
8557 00:56:53.864018
8558 00:56:53.864117 Set Vref, RX VrefLevel [Byte0]: 26
8559 00:56:53.867249 [Byte1]: 26
8560 00:56:53.871683
8561 00:56:53.871778 Set Vref, RX VrefLevel [Byte0]: 27
8562 00:56:53.874824 [Byte1]: 27
8563 00:56:53.879057
8564 00:56:53.879149 Set Vref, RX VrefLevel [Byte0]: 28
8565 00:56:53.882517 [Byte1]: 28
8566 00:56:53.886634
8567 00:56:53.886728 Set Vref, RX VrefLevel [Byte0]: 29
8568 00:56:53.889862 [Byte1]: 29
8569 00:56:53.894279
8570 00:56:53.894369 Set Vref, RX VrefLevel [Byte0]: 30
8571 00:56:53.897822 [Byte1]: 30
8572 00:56:53.902066
8573 00:56:53.902157 Set Vref, RX VrefLevel [Byte0]: 31
8574 00:56:53.905182 [Byte1]: 31
8575 00:56:53.909565
8576 00:56:53.909668 Set Vref, RX VrefLevel [Byte0]: 32
8577 00:56:53.913002 [Byte1]: 32
8578 00:56:53.917227
8579 00:56:53.917341 Set Vref, RX VrefLevel [Byte0]: 33
8580 00:56:53.920432 [Byte1]: 33
8581 00:56:53.924781
8582 00:56:53.924867 Set Vref, RX VrefLevel [Byte0]: 34
8583 00:56:53.928195 [Byte1]: 34
8584 00:56:53.932507
8585 00:56:53.932624 Set Vref, RX VrefLevel [Byte0]: 35
8586 00:56:53.935815 [Byte1]: 35
8587 00:56:53.939987
8588 00:56:53.940081 Set Vref, RX VrefLevel [Byte0]: 36
8589 00:56:53.943211 [Byte1]: 36
8590 00:56:53.947698
8591 00:56:53.947792 Set Vref, RX VrefLevel [Byte0]: 37
8592 00:56:53.950768 [Byte1]: 37
8593 00:56:53.955107
8594 00:56:53.955198 Set Vref, RX VrefLevel [Byte0]: 38
8595 00:56:53.958523 [Byte1]: 38
8596 00:56:53.962807
8597 00:56:53.962901 Set Vref, RX VrefLevel [Byte0]: 39
8598 00:56:53.966167 [Byte1]: 39
8599 00:56:53.970442
8600 00:56:53.970536 Set Vref, RX VrefLevel [Byte0]: 40
8601 00:56:53.973872 [Byte1]: 40
8602 00:56:53.977926
8603 00:56:53.978022 Set Vref, RX VrefLevel [Byte0]: 41
8604 00:56:53.981419 [Byte1]: 41
8605 00:56:53.985747
8606 00:56:53.985839 Set Vref, RX VrefLevel [Byte0]: 42
8607 00:56:53.989169 [Byte1]: 42
8608 00:56:53.993138
8609 00:56:53.993228 Set Vref, RX VrefLevel [Byte0]: 43
8610 00:56:53.996783 [Byte1]: 43
8611 00:56:54.001047
8612 00:56:54.001148 Set Vref, RX VrefLevel [Byte0]: 44
8613 00:56:54.004340 [Byte1]: 44
8614 00:56:54.008627
8615 00:56:54.008730 Set Vref, RX VrefLevel [Byte0]: 45
8616 00:56:54.011749 [Byte1]: 45
8617 00:56:54.016224
8618 00:56:54.016325 Set Vref, RX VrefLevel [Byte0]: 46
8619 00:56:54.019679 [Byte1]: 46
8620 00:56:54.023829
8621 00:56:54.023925 Set Vref, RX VrefLevel [Byte0]: 47
8622 00:56:54.027164 [Byte1]: 47
8623 00:56:54.031398
8624 00:56:54.031497 Set Vref, RX VrefLevel [Byte0]: 48
8625 00:56:54.034863 [Byte1]: 48
8626 00:56:54.039110
8627 00:56:54.039209 Set Vref, RX VrefLevel [Byte0]: 49
8628 00:56:54.042474 [Byte1]: 49
8629 00:56:54.046474
8630 00:56:54.046568 Set Vref, RX VrefLevel [Byte0]: 50
8631 00:56:54.049756 [Byte1]: 50
8632 00:56:54.054114
8633 00:56:54.054216 Set Vref, RX VrefLevel [Byte0]: 51
8634 00:56:54.057318 [Byte1]: 51
8635 00:56:54.061824
8636 00:56:54.061925 Set Vref, RX VrefLevel [Byte0]: 52
8637 00:56:54.065255 [Byte1]: 52
8638 00:56:54.069433
8639 00:56:54.069565 Set Vref, RX VrefLevel [Byte0]: 53
8640 00:56:54.072783 [Byte1]: 53
8641 00:56:54.077098
8642 00:56:54.077198 Set Vref, RX VrefLevel [Byte0]: 54
8643 00:56:54.080315 [Byte1]: 54
8644 00:56:54.084766
8645 00:56:54.084926 Set Vref, RX VrefLevel [Byte0]: 55
8646 00:56:54.087885 [Byte1]: 55
8647 00:56:54.092176
8648 00:56:54.092271 Set Vref, RX VrefLevel [Byte0]: 56
8649 00:56:54.095626 [Byte1]: 56
8650 00:56:54.099956
8651 00:56:54.100059 Set Vref, RX VrefLevel [Byte0]: 57
8652 00:56:54.103180 [Byte1]: 57
8653 00:56:54.107444
8654 00:56:54.107545 Set Vref, RX VrefLevel [Byte0]: 58
8655 00:56:54.110728 [Byte1]: 58
8656 00:56:54.115267
8657 00:56:54.115362 Set Vref, RX VrefLevel [Byte0]: 59
8658 00:56:54.118388 [Byte1]: 59
8659 00:56:54.122671
8660 00:56:54.122767 Set Vref, RX VrefLevel [Byte0]: 60
8661 00:56:54.126043 [Byte1]: 60
8662 00:56:54.130437
8663 00:56:54.130551 Set Vref, RX VrefLevel [Byte0]: 61
8664 00:56:54.133602 [Byte1]: 61
8665 00:56:54.138098
8666 00:56:54.138201 Set Vref, RX VrefLevel [Byte0]: 62
8667 00:56:54.141180 [Byte1]: 62
8668 00:56:54.145594
8669 00:56:54.145692 Set Vref, RX VrefLevel [Byte0]: 63
8670 00:56:54.148810 [Byte1]: 63
8671 00:56:54.153370
8672 00:56:54.153470 Set Vref, RX VrefLevel [Byte0]: 64
8673 00:56:54.156628 [Byte1]: 64
8674 00:56:54.160918
8675 00:56:54.161012 Set Vref, RX VrefLevel [Byte0]: 65
8676 00:56:54.164127 [Byte1]: 65
8677 00:56:54.168448
8678 00:56:54.168543 Set Vref, RX VrefLevel [Byte0]: 66
8679 00:56:54.171936 [Byte1]: 66
8680 00:56:54.175934
8681 00:56:54.176029 Set Vref, RX VrefLevel [Byte0]: 67
8682 00:56:54.179197 [Byte1]: 67
8683 00:56:54.183658
8684 00:56:54.183757 Set Vref, RX VrefLevel [Byte0]: 68
8685 00:56:54.187145 [Byte1]: 68
8686 00:56:54.191374
8687 00:56:54.191473 Final RX Vref Byte 0 = 55 to rank0
8688 00:56:54.194653 Final RX Vref Byte 1 = 51 to rank0
8689 00:56:54.197939 Final RX Vref Byte 0 = 55 to rank1
8690 00:56:54.201170 Final RX Vref Byte 1 = 51 to rank1==
8691 00:56:54.204582 Dram Type= 6, Freq= 0, CH_1, rank 0
8692 00:56:54.211253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8693 00:56:54.211382 ==
8694 00:56:54.211480 DQS Delay:
8695 00:56:54.211563 DQS0 = 0, DQS1 = 0
8696 00:56:54.214377 DQM Delay:
8697 00:56:54.214470 DQM0 = 131, DQM1 = 123
8698 00:56:54.217990 DQ Delay:
8699 00:56:54.220990 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8700 00:56:54.224275 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8701 00:56:54.227916 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8702 00:56:54.231078 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8703 00:56:54.231174
8704 00:56:54.231269
8705 00:56:54.231350
8706 00:56:54.234234 [DramC_TX_OE_Calibration] TA2
8707 00:56:54.237687 Original DQ_B0 (3 6) =30, OEN = 27
8708 00:56:54.240951 Original DQ_B1 (3 6) =30, OEN = 27
8709 00:56:54.244275 24, 0x0, End_B0=24 End_B1=24
8710 00:56:54.244372 25, 0x0, End_B0=25 End_B1=25
8711 00:56:54.247647 26, 0x0, End_B0=26 End_B1=26
8712 00:56:54.250850 27, 0x0, End_B0=27 End_B1=27
8713 00:56:54.254181 28, 0x0, End_B0=28 End_B1=28
8714 00:56:54.257614 29, 0x0, End_B0=29 End_B1=29
8715 00:56:54.257713 30, 0x0, End_B0=30 End_B1=30
8716 00:56:54.260898 31, 0x4141, End_B0=30 End_B1=30
8717 00:56:54.264066 Byte0 end_step=30 best_step=27
8718 00:56:54.267425 Byte1 end_step=30 best_step=27
8719 00:56:54.270549 Byte0 TX OE(2T, 0.5T) = (3, 3)
8720 00:56:54.274201 Byte1 TX OE(2T, 0.5T) = (3, 3)
8721 00:56:54.274295
8722 00:56:54.274382
8723 00:56:54.280722 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8724 00:56:54.283806 CH1 RK0: MR19=303, MR18=80D
8725 00:56:54.290461 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8726 00:56:54.290574
8727 00:56:54.293633 ----->DramcWriteLeveling(PI) begin...
8728 00:56:54.293724 ==
8729 00:56:54.297086 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 00:56:54.300427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 00:56:54.300518 ==
8732 00:56:54.303637 Write leveling (Byte 0): 24 => 24
8733 00:56:54.307333 Write leveling (Byte 1): 28 => 28
8734 00:56:54.310228 DramcWriteLeveling(PI) end<-----
8735 00:56:54.310324
8736 00:56:54.310409 ==
8737 00:56:54.313578 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 00:56:54.316759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 00:56:54.316857 ==
8740 00:56:54.320243 [Gating] SW mode calibration
8741 00:56:54.326850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8742 00:56:54.333321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8743 00:56:54.336520 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 00:56:54.343184 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 00:56:54.346601 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8746 00:56:54.349840 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8747 00:56:54.356433 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 00:56:54.359770 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 00:56:54.363257 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 00:56:54.369814 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 00:56:54.373093 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 00:56:54.376354 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 00:56:54.379944 1 5 8 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
8754 00:56:54.386576 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8755 00:56:54.389803 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 00:56:54.393085 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 00:56:54.399800 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 00:56:54.402956 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 00:56:54.406422 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 00:56:54.412812 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8761 00:56:54.416259 1 6 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8762 00:56:54.419556 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8763 00:56:54.426215 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 00:56:54.429309 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 00:56:54.432529 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 00:56:54.439463 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 00:56:54.442683 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 00:56:54.445921 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 00:56:54.452786 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8770 00:56:54.455826 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8771 00:56:54.458947 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8772 00:56:54.465720 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 00:56:54.469085 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 00:56:54.472215 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 00:56:54.479013 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 00:56:54.482279 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 00:56:54.485503 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 00:56:54.492111 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 00:56:54.495607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 00:56:54.498883 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 00:56:54.505472 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 00:56:54.509112 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 00:56:54.512559 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 00:56:54.519092 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 00:56:54.522263 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8786 00:56:54.525746 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8787 00:56:54.528797 Total UI for P1: 0, mck2ui 16
8788 00:56:54.531944 best dqsien dly found for B0: ( 1, 9, 8)
8789 00:56:54.538666 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 00:56:54.538779 Total UI for P1: 0, mck2ui 16
8791 00:56:54.545350 best dqsien dly found for B1: ( 1, 9, 12)
8792 00:56:54.548599 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8793 00:56:54.551923 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8794 00:56:54.552007
8795 00:56:54.555270 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8796 00:56:54.558546 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8797 00:56:54.561992 [Gating] SW calibration Done
8798 00:56:54.562088 ==
8799 00:56:54.565062 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 00:56:54.568597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 00:56:54.568685 ==
8802 00:56:54.571583 RX Vref Scan: 0
8803 00:56:54.571671
8804 00:56:54.571767 RX Vref 0 -> 0, step: 1
8805 00:56:54.571861
8806 00:56:54.574967 RX Delay 0 -> 252, step: 8
8807 00:56:54.578375 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8808 00:56:54.584885 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8809 00:56:54.588467 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8810 00:56:54.591709 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8811 00:56:54.594763 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8812 00:56:54.597968 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8813 00:56:54.604577 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8814 00:56:54.607870 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8815 00:56:54.611493 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8816 00:56:54.614776 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8817 00:56:54.618027 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8818 00:56:54.624569 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8819 00:56:54.627907 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8820 00:56:54.631131 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8821 00:56:54.634500 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8822 00:56:54.641256 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8823 00:56:54.641380 ==
8824 00:56:54.644238 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 00:56:54.647862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 00:56:54.647982 ==
8827 00:56:54.648081 DQS Delay:
8828 00:56:54.650936 DQS0 = 0, DQS1 = 0
8829 00:56:54.651047 DQM Delay:
8830 00:56:54.654131 DQM0 = 132, DQM1 = 128
8831 00:56:54.654218 DQ Delay:
8832 00:56:54.657595 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8833 00:56:54.660824 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8834 00:56:54.664400 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8835 00:56:54.667573 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8836 00:56:54.667664
8837 00:56:54.667731
8838 00:56:54.670788 ==
8839 00:56:54.674187 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 00:56:54.677267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 00:56:54.677356 ==
8842 00:56:54.677422
8843 00:56:54.677489
8844 00:56:54.680622 TX Vref Scan disable
8845 00:56:54.680707 == TX Byte 0 ==
8846 00:56:54.687094 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8847 00:56:54.690413 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8848 00:56:54.690512 == TX Byte 1 ==
8849 00:56:54.696983 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8850 00:56:54.700576 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8851 00:56:54.700689 ==
8852 00:56:54.703926 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 00:56:54.706937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 00:56:54.707035 ==
8855 00:56:54.721704
8856 00:56:54.724914 TX Vref early break, caculate TX vref
8857 00:56:54.728528 TX Vref=16, minBit 0, minWin=23, winSum=386
8858 00:56:54.731802 TX Vref=18, minBit 0, minWin=22, winSum=392
8859 00:56:54.735026 TX Vref=20, minBit 0, minWin=24, winSum=397
8860 00:56:54.738343 TX Vref=22, minBit 0, minWin=24, winSum=407
8861 00:56:54.741436 TX Vref=24, minBit 0, minWin=25, winSum=419
8862 00:56:54.747986 TX Vref=26, minBit 0, minWin=25, winSum=423
8863 00:56:54.751274 TX Vref=28, minBit 0, minWin=26, winSum=425
8864 00:56:54.754625 TX Vref=30, minBit 1, minWin=24, winSum=422
8865 00:56:54.758163 TX Vref=32, minBit 5, minWin=24, winSum=409
8866 00:56:54.761427 TX Vref=34, minBit 0, minWin=24, winSum=404
8867 00:56:54.764666 TX Vref=36, minBit 5, minWin=23, winSum=396
8868 00:56:54.771119 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8869 00:56:54.771220
8870 00:56:54.774474 Final TX Range 0 Vref 28
8871 00:56:54.774560
8872 00:56:54.774626 ==
8873 00:56:54.777749 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 00:56:54.781272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 00:56:54.781372 ==
8876 00:56:54.784295
8877 00:56:54.784381
8878 00:56:54.784446 TX Vref Scan disable
8879 00:56:54.791017 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8880 00:56:54.791120 == TX Byte 0 ==
8881 00:56:54.794275 u2DelayCellOfst[0]=18 cells (5 PI)
8882 00:56:54.797673 u2DelayCellOfst[1]=18 cells (5 PI)
8883 00:56:54.800860 u2DelayCellOfst[2]=0 cells (0 PI)
8884 00:56:54.804320 u2DelayCellOfst[3]=7 cells (2 PI)
8885 00:56:54.807579 u2DelayCellOfst[4]=11 cells (3 PI)
8886 00:56:54.810870 u2DelayCellOfst[5]=26 cells (7 PI)
8887 00:56:54.814406 u2DelayCellOfst[6]=22 cells (6 PI)
8888 00:56:54.817603 u2DelayCellOfst[7]=7 cells (2 PI)
8889 00:56:54.820844 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8890 00:56:54.824321 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8891 00:56:54.827492 == TX Byte 1 ==
8892 00:56:54.830807 u2DelayCellOfst[8]=0 cells (0 PI)
8893 00:56:54.834328 u2DelayCellOfst[9]=11 cells (3 PI)
8894 00:56:54.837400 u2DelayCellOfst[10]=15 cells (4 PI)
8895 00:56:54.840817 u2DelayCellOfst[11]=7 cells (2 PI)
8896 00:56:54.844135 u2DelayCellOfst[12]=18 cells (5 PI)
8897 00:56:54.844220 u2DelayCellOfst[13]=18 cells (5 PI)
8898 00:56:54.847307 u2DelayCellOfst[14]=18 cells (5 PI)
8899 00:56:54.850545 u2DelayCellOfst[15]=18 cells (5 PI)
8900 00:56:54.857263 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8901 00:56:54.860668 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8902 00:56:54.863699 DramC Write-DBI on
8903 00:56:54.863792 ==
8904 00:56:54.866945 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 00:56:54.870364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 00:56:54.870484 ==
8907 00:56:54.870578
8908 00:56:54.870643
8909 00:56:54.873631 TX Vref Scan disable
8910 00:56:54.873715 == TX Byte 0 ==
8911 00:56:54.880294 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8912 00:56:54.880395 == TX Byte 1 ==
8913 00:56:54.883628 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8914 00:56:54.886739 DramC Write-DBI off
8915 00:56:54.886857
8916 00:56:54.886951 [DATLAT]
8917 00:56:54.890245 Freq=1600, CH1 RK1
8918 00:56:54.890331
8919 00:56:54.890396 DATLAT Default: 0xf
8920 00:56:54.893647 0, 0xFFFF, sum = 0
8921 00:56:54.893734 1, 0xFFFF, sum = 0
8922 00:56:54.896899 2, 0xFFFF, sum = 0
8923 00:56:54.896985 3, 0xFFFF, sum = 0
8924 00:56:54.899995 4, 0xFFFF, sum = 0
8925 00:56:54.903334 5, 0xFFFF, sum = 0
8926 00:56:54.903431 6, 0xFFFF, sum = 0
8927 00:56:54.906706 7, 0xFFFF, sum = 0
8928 00:56:54.906796 8, 0xFFFF, sum = 0
8929 00:56:54.910285 9, 0xFFFF, sum = 0
8930 00:56:54.910382 10, 0xFFFF, sum = 0
8931 00:56:54.913345 11, 0xFFFF, sum = 0
8932 00:56:54.913432 12, 0xFFFF, sum = 0
8933 00:56:54.916720 13, 0x8FFF, sum = 0
8934 00:56:54.916808 14, 0x0, sum = 1
8935 00:56:54.919922 15, 0x0, sum = 2
8936 00:56:54.920010 16, 0x0, sum = 3
8937 00:56:54.923237 17, 0x0, sum = 4
8938 00:56:54.923325 best_step = 15
8939 00:56:54.923392
8940 00:56:54.923454 ==
8941 00:56:54.926750 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 00:56:54.929981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 00:56:54.933450 ==
8944 00:56:54.933568 RX Vref Scan: 0
8945 00:56:54.933641
8946 00:56:54.936672 RX Vref 0 -> 0, step: 1
8947 00:56:54.936756
8948 00:56:54.936821 RX Delay 11 -> 252, step: 4
8949 00:56:54.944023 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8950 00:56:54.947286 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8951 00:56:54.950563 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8952 00:56:54.953729 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8953 00:56:54.957290 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8954 00:56:54.963754 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8955 00:56:54.966981 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8956 00:56:54.970534 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8957 00:56:54.973920 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8958 00:56:54.977106 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8959 00:56:54.983826 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8960 00:56:54.987015 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8961 00:56:54.990166 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8962 00:56:54.993656 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8963 00:56:55.000247 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8964 00:56:55.003410 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8965 00:56:55.003506 ==
8966 00:56:55.006730 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 00:56:55.010212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 00:56:55.010311 ==
8969 00:56:55.013423 DQS Delay:
8970 00:56:55.013547 DQS0 = 0, DQS1 = 0
8971 00:56:55.013623 DQM Delay:
8972 00:56:55.016855 DQM0 = 129, DQM1 = 125
8973 00:56:55.016940 DQ Delay:
8974 00:56:55.020096 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =126
8975 00:56:55.023337 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
8976 00:56:55.026854 DQ8 =110, DQ9 =116, DQ10 =128, DQ11 =120
8977 00:56:55.033359 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
8978 00:56:55.033508
8979 00:56:55.033594
8980 00:56:55.033656
8981 00:56:55.036878 [DramC_TX_OE_Calibration] TA2
8982 00:56:55.036964 Original DQ_B0 (3 6) =30, OEN = 27
8983 00:56:55.040156 Original DQ_B1 (3 6) =30, OEN = 27
8984 00:56:55.043200 24, 0x0, End_B0=24 End_B1=24
8985 00:56:55.046566 25, 0x0, End_B0=25 End_B1=25
8986 00:56:55.049954 26, 0x0, End_B0=26 End_B1=26
8987 00:56:55.053272 27, 0x0, End_B0=27 End_B1=27
8988 00:56:55.053366 28, 0x0, End_B0=28 End_B1=28
8989 00:56:55.056697 29, 0x0, End_B0=29 End_B1=29
8990 00:56:55.059986 30, 0x0, End_B0=30 End_B1=30
8991 00:56:55.063544 31, 0x4141, End_B0=30 End_B1=30
8992 00:56:55.066693 Byte0 end_step=30 best_step=27
8993 00:56:55.066780 Byte1 end_step=30 best_step=27
8994 00:56:55.070269 Byte0 TX OE(2T, 0.5T) = (3, 3)
8995 00:56:55.073245 Byte1 TX OE(2T, 0.5T) = (3, 3)
8996 00:56:55.073332
8997 00:56:55.073399
8998 00:56:55.083267 [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
8999 00:56:55.083394 CH1 RK1: MR19=303, MR18=121E
9000 00:56:55.089831 CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15
9001 00:56:55.093083 [RxdqsGatingPostProcess] freq 1600
9002 00:56:55.099581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9003 00:56:55.102972 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 00:56:55.106222 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 00:56:55.109629 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 00:56:55.113022 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 00:56:55.113119 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 00:56:55.116387 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 00:56:55.119716 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 00:56:55.122820 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 00:56:55.126193 Pre-setting of DQS Precalculation
9012 00:56:55.132972 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9013 00:56:55.139318 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9014 00:56:55.146172 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9015 00:56:55.146292
9016 00:56:55.146361
9017 00:56:55.149248 [Calibration Summary] 3200 Mbps
9018 00:56:55.149337 CH 0, Rank 0
9019 00:56:55.152798 SW Impedance : PASS
9020 00:56:55.155878 DUTY Scan : NO K
9021 00:56:55.155985 ZQ Calibration : PASS
9022 00:56:55.159340 Jitter Meter : NO K
9023 00:56:55.162664 CBT Training : PASS
9024 00:56:55.162753 Write leveling : PASS
9025 00:56:55.165894 RX DQS gating : PASS
9026 00:56:55.169389 RX DQ/DQS(RDDQC) : PASS
9027 00:56:55.169501 TX DQ/DQS : PASS
9028 00:56:55.172499 RX DATLAT : PASS
9029 00:56:55.175730 RX DQ/DQS(Engine): PASS
9030 00:56:55.175818 TX OE : PASS
9031 00:56:55.179216 All Pass.
9032 00:56:55.179302
9033 00:56:55.179368 CH 0, Rank 1
9034 00:56:55.182375 SW Impedance : PASS
9035 00:56:55.182460 DUTY Scan : NO K
9036 00:56:55.185914 ZQ Calibration : PASS
9037 00:56:55.189042 Jitter Meter : NO K
9038 00:56:55.189128 CBT Training : PASS
9039 00:56:55.192218 Write leveling : PASS
9040 00:56:55.195596 RX DQS gating : PASS
9041 00:56:55.195685 RX DQ/DQS(RDDQC) : PASS
9042 00:56:55.199029 TX DQ/DQS : PASS
9043 00:56:55.199113 RX DATLAT : PASS
9044 00:56:55.202236 RX DQ/DQS(Engine): PASS
9045 00:56:55.205447 TX OE : PASS
9046 00:56:55.205560 All Pass.
9047 00:56:55.205626
9048 00:56:55.205688 CH 1, Rank 0
9049 00:56:55.208839 SW Impedance : PASS
9050 00:56:55.212106 DUTY Scan : NO K
9051 00:56:55.212198 ZQ Calibration : PASS
9052 00:56:55.215710 Jitter Meter : NO K
9053 00:56:55.218914 CBT Training : PASS
9054 00:56:55.219002 Write leveling : PASS
9055 00:56:55.222334 RX DQS gating : PASS
9056 00:56:55.225410 RX DQ/DQS(RDDQC) : PASS
9057 00:56:55.225552 TX DQ/DQS : PASS
9058 00:56:55.228875 RX DATLAT : PASS
9059 00:56:55.232002 RX DQ/DQS(Engine): PASS
9060 00:56:55.232098 TX OE : PASS
9061 00:56:55.235527 All Pass.
9062 00:56:55.235614
9063 00:56:55.235716 CH 1, Rank 1
9064 00:56:55.238702 SW Impedance : PASS
9065 00:56:55.238787 DUTY Scan : NO K
9066 00:56:55.242241 ZQ Calibration : PASS
9067 00:56:55.245439 Jitter Meter : NO K
9068 00:56:55.245564 CBT Training : PASS
9069 00:56:55.248655 Write leveling : PASS
9070 00:56:55.251991 RX DQS gating : PASS
9071 00:56:55.252085 RX DQ/DQS(RDDQC) : PASS
9072 00:56:55.255266 TX DQ/DQS : PASS
9073 00:56:55.258290 RX DATLAT : PASS
9074 00:56:55.258380 RX DQ/DQS(Engine): PASS
9075 00:56:55.261873 TX OE : PASS
9076 00:56:55.261962 All Pass.
9077 00:56:55.262048
9078 00:56:55.265033 DramC Write-DBI on
9079 00:56:55.265119 PER_BANK_REFRESH: Hybrid Mode
9080 00:56:55.268594 TX_TRACKING: ON
9081 00:56:55.278595 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9082 00:56:55.285215 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9083 00:56:55.291806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 00:56:55.295050 [FAST_K] Save calibration result to emmc
9085 00:56:55.298300 sync common calibartion params.
9086 00:56:55.301567 sync cbt_mode0:1, 1:1
9087 00:56:55.301660 dram_init: ddr_geometry: 2
9088 00:56:55.304972 dram_init: ddr_geometry: 2
9089 00:56:55.308250 dram_init: ddr_geometry: 2
9090 00:56:55.311558 0:dram_rank_size:100000000
9091 00:56:55.311656 1:dram_rank_size:100000000
9092 00:56:55.318221 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9093 00:56:55.321528 DFS_SHUFFLE_HW_MODE: ON
9094 00:56:55.324772 dramc_set_vcore_voltage set vcore to 725000
9095 00:56:55.328094 Read voltage for 1600, 0
9096 00:56:55.328206 Vio18 = 0
9097 00:56:55.328308 Vcore = 725000
9098 00:56:55.331348 Vdram = 0
9099 00:56:55.331472 Vddq = 0
9100 00:56:55.331635 Vmddr = 0
9101 00:56:55.334780 switch to 3200 Mbps bootup
9102 00:56:55.334869 [DramcRunTimeConfig]
9103 00:56:55.338217 PHYPLL
9104 00:56:55.338307 DPM_CONTROL_AFTERK: ON
9105 00:56:55.341553 PER_BANK_REFRESH: ON
9106 00:56:55.344704 REFRESH_OVERHEAD_REDUCTION: ON
9107 00:56:55.344792 CMD_PICG_NEW_MODE: OFF
9108 00:56:55.348049 XRTWTW_NEW_MODE: ON
9109 00:56:55.348137 XRTRTR_NEW_MODE: ON
9110 00:56:55.351288 TX_TRACKING: ON
9111 00:56:55.351410 RDSEL_TRACKING: OFF
9112 00:56:55.354898 DQS Precalculation for DVFS: ON
9113 00:56:55.358232 RX_TRACKING: OFF
9114 00:56:55.358325 HW_GATING DBG: ON
9115 00:56:55.361511 ZQCS_ENABLE_LP4: ON
9116 00:56:55.361612 RX_PICG_NEW_MODE: ON
9117 00:56:55.364458 TX_PICG_NEW_MODE: ON
9118 00:56:55.364556 ENABLE_RX_DCM_DPHY: ON
9119 00:56:55.367958 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9120 00:56:55.371308 DUMMY_READ_FOR_TRACKING: OFF
9121 00:56:55.374519 !!! SPM_CONTROL_AFTERK: OFF
9122 00:56:55.378102 !!! SPM could not control APHY
9123 00:56:55.378194 IMPEDANCE_TRACKING: ON
9124 00:56:55.381319 TEMP_SENSOR: ON
9125 00:56:55.381406 HW_SAVE_FOR_SR: OFF
9126 00:56:55.384609 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9127 00:56:55.387829 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9128 00:56:55.391065 Read ODT Tracking: ON
9129 00:56:55.394333 Refresh Rate DeBounce: ON
9130 00:56:55.394425 DFS_NO_QUEUE_FLUSH: ON
9131 00:56:55.397827 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9132 00:56:55.401257 ENABLE_DFS_RUNTIME_MRW: OFF
9133 00:56:55.404243 DDR_RESERVE_NEW_MODE: ON
9134 00:56:55.404337 MR_CBT_SWITCH_FREQ: ON
9135 00:56:55.407595 =========================
9136 00:56:55.426690 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9137 00:56:55.429944 dram_init: ddr_geometry: 2
9138 00:56:55.448250 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9139 00:56:55.451427 dram_init: dram init end (result: 0)
9140 00:56:55.458122 DRAM-K: Full calibration passed in 24514 msecs
9141 00:56:55.461270 MRC: failed to locate region type 0.
9142 00:56:55.461375 DRAM rank0 size:0x100000000,
9143 00:56:55.464848 DRAM rank1 size=0x100000000
9144 00:56:55.474626 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9145 00:56:55.481279 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9146 00:56:55.487616 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9147 00:56:55.494265 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9148 00:56:55.497505 DRAM rank0 size:0x100000000,
9149 00:56:55.501085 DRAM rank1 size=0x100000000
9150 00:56:55.501179 CBMEM:
9151 00:56:55.504217 IMD: root @ 0xfffff000 254 entries.
9152 00:56:55.507684 IMD: root @ 0xffffec00 62 entries.
9153 00:56:55.510819 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9154 00:56:55.517614 WARNING: RO_VPD is uninitialized or empty.
9155 00:56:55.520856 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9156 00:56:55.528287 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9157 00:56:55.541136 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9158 00:56:55.552216 BS: romstage times (exec / console): total (unknown) / 23986 ms
9159 00:56:55.552380
9160 00:56:55.552489
9161 00:56:55.562236 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9162 00:56:55.565446 ARM64: Exception handlers installed.
9163 00:56:55.568969 ARM64: Testing exception
9164 00:56:55.572483 ARM64: Done test exception
9165 00:56:55.572578 Enumerating buses...
9166 00:56:55.575564 Show all devs... Before device enumeration.
9167 00:56:55.578912 Root Device: enabled 1
9168 00:56:55.582267 CPU_CLUSTER: 0: enabled 1
9169 00:56:55.582358 CPU: 00: enabled 1
9170 00:56:55.585459 Compare with tree...
9171 00:56:55.585587 Root Device: enabled 1
9172 00:56:55.588713 CPU_CLUSTER: 0: enabled 1
9173 00:56:55.592047 CPU: 00: enabled 1
9174 00:56:55.592134 Root Device scanning...
9175 00:56:55.595570 scan_static_bus for Root Device
9176 00:56:55.598723 CPU_CLUSTER: 0 enabled
9177 00:56:55.601974 scan_static_bus for Root Device done
9178 00:56:55.605419 scan_bus: bus Root Device finished in 8 msecs
9179 00:56:55.605547 done
9180 00:56:55.612031 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9181 00:56:55.615151 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9182 00:56:55.621978 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9183 00:56:55.625202 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9184 00:56:55.628517 Allocating resources...
9185 00:56:55.631620 Reading resources...
9186 00:56:55.635225 Root Device read_resources bus 0 link: 0
9187 00:56:55.638388 DRAM rank0 size:0x100000000,
9188 00:56:55.638483 DRAM rank1 size=0x100000000
9189 00:56:55.641702 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9190 00:56:55.644859 CPU: 00 missing read_resources
9191 00:56:55.651537 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9192 00:56:55.655117 Root Device read_resources bus 0 link: 0 done
9193 00:56:55.655214 Done reading resources.
9194 00:56:55.661496 Show resources in subtree (Root Device)...After reading.
9195 00:56:55.664832 Root Device child on link 0 CPU_CLUSTER: 0
9196 00:56:55.668152 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 00:56:55.678009 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 00:56:55.678140 CPU: 00
9199 00:56:55.681304 Root Device assign_resources, bus 0 link: 0
9200 00:56:55.684988 CPU_CLUSTER: 0 missing set_resources
9201 00:56:55.691379 Root Device assign_resources, bus 0 link: 0 done
9202 00:56:55.691506 Done setting resources.
9203 00:56:55.697866 Show resources in subtree (Root Device)...After assigning values.
9204 00:56:55.701417 Root Device child on link 0 CPU_CLUSTER: 0
9205 00:56:55.704547 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 00:56:55.714636 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 00:56:55.714787 CPU: 00
9208 00:56:55.717963 Done allocating resources.
9209 00:56:55.724301 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9210 00:56:55.724411 Enabling resources...
9211 00:56:55.724514 done.
9212 00:56:55.731123 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9213 00:56:55.731234 Initializing devices...
9214 00:56:55.734211 Root Device init
9215 00:56:55.734326 init hardware done!
9216 00:56:55.737512 0x00000018: ctrlr->caps
9217 00:56:55.741125 52.000 MHz: ctrlr->f_max
9218 00:56:55.741220 0.400 MHz: ctrlr->f_min
9219 00:56:55.744461 0x40ff8080: ctrlr->voltages
9220 00:56:55.747588 sclk: 390625
9221 00:56:55.747678 Bus Width = 1
9222 00:56:55.747765 sclk: 390625
9223 00:56:55.750863 Bus Width = 1
9224 00:56:55.750974 Early init status = 3
9225 00:56:55.757271 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9226 00:56:55.760769 in-header: 03 fc 00 00 01 00 00 00
9227 00:56:55.764003 in-data: 00
9228 00:56:55.767245 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9229 00:56:55.771692 in-header: 03 fd 00 00 00 00 00 00
9230 00:56:55.774808 in-data:
9231 00:56:55.778360 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9232 00:56:55.782582 in-header: 03 fc 00 00 01 00 00 00
9233 00:56:55.785869 in-data: 00
9234 00:56:55.789226 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9235 00:56:55.794776 in-header: 03 fd 00 00 00 00 00 00
9236 00:56:55.797913 in-data:
9237 00:56:55.801207 [SSUSB] Setting up USB HOST controller...
9238 00:56:55.804429 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9239 00:56:55.807855 [SSUSB] phy power-on done.
9240 00:56:55.811083 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9241 00:56:55.817674 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9242 00:56:55.820989 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9243 00:56:55.827808 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9244 00:56:55.834213 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9245 00:56:55.840866 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9246 00:56:55.847619 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9247 00:56:55.854419 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9248 00:56:55.857689 SPM: binary array size = 0x9dc
9249 00:56:55.860835 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9250 00:56:55.867519 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9251 00:56:55.874031 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9252 00:56:55.880579 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9253 00:56:55.883975 configure_display: Starting display init
9254 00:56:55.917916 anx7625_power_on_init: Init interface.
9255 00:56:55.921279 anx7625_disable_pd_protocol: Disabled PD feature.
9256 00:56:55.924684 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9257 00:56:55.952282 anx7625_start_dp_work: Secure OCM version=00
9258 00:56:55.955644 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9259 00:56:55.970324 sp_tx_get_edid_block: EDID Block = 1
9260 00:56:56.072979 Extracted contents:
9261 00:56:56.076542 header: 00 ff ff ff ff ff ff 00
9262 00:56:56.079723 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9263 00:56:56.083007 version: 01 04
9264 00:56:56.086099 basic params: 95 1f 11 78 0a
9265 00:56:56.089329 chroma info: 76 90 94 55 54 90 27 21 50 54
9266 00:56:56.092623 established: 00 00 00
9267 00:56:56.099305 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9268 00:56:56.105847 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9269 00:56:56.109272 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9270 00:56:56.115759 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9271 00:56:56.122394 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9272 00:56:56.125576 extensions: 00
9273 00:56:56.125682 checksum: fb
9274 00:56:56.125775
9275 00:56:56.132163 Manufacturer: IVO Model 57d Serial Number 0
9276 00:56:56.132294 Made week 0 of 2020
9277 00:56:56.135440 EDID version: 1.4
9278 00:56:56.135557 Digital display
9279 00:56:56.138885 6 bits per primary color channel
9280 00:56:56.142173 DisplayPort interface
9281 00:56:56.142263 Maximum image size: 31 cm x 17 cm
9282 00:56:56.145380 Gamma: 220%
9283 00:56:56.145468 Check DPMS levels
9284 00:56:56.152028 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9285 00:56:56.155224 First detailed timing is preferred timing
9286 00:56:56.155323 Established timings supported:
9287 00:56:56.158497 Standard timings supported:
9288 00:56:56.161871 Detailed timings
9289 00:56:56.165070 Hex of detail: 383680a07038204018303c0035ae10000019
9290 00:56:56.171886 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9291 00:56:56.175121 0780 0798 07c8 0820 hborder 0
9292 00:56:56.178390 0438 043b 0447 0458 vborder 0
9293 00:56:56.181817 -hsync -vsync
9294 00:56:56.181918 Did detailed timing
9295 00:56:56.188448 Hex of detail: 000000000000000000000000000000000000
9296 00:56:56.191670 Manufacturer-specified data, tag 0
9297 00:56:56.195067 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9298 00:56:56.198211 ASCII string: InfoVision
9299 00:56:56.201563 Hex of detail: 000000fe00523134304e574635205248200a
9300 00:56:56.204805 ASCII string: R140NWF5 RH
9301 00:56:56.204896 Checksum
9302 00:56:56.208383 Checksum: 0xfb (valid)
9303 00:56:56.211570 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9304 00:56:56.214792 DSI data_rate: 832800000 bps
9305 00:56:56.221314 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9306 00:56:56.224967 anx7625_parse_edid: pixelclock(138800).
9307 00:56:56.228169 hactive(1920), hsync(48), hfp(24), hbp(88)
9308 00:56:56.231351 vactive(1080), vsync(12), vfp(3), vbp(17)
9309 00:56:56.234624 anx7625_dsi_config: config dsi.
9310 00:56:56.241323 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9311 00:56:56.254938 anx7625_dsi_config: success to config DSI
9312 00:56:56.258219 anx7625_dp_start: MIPI phy setup OK.
9313 00:56:56.261436 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9314 00:56:56.265173 mtk_ddp_mode_set invalid vrefresh 60
9315 00:56:56.268298 main_disp_path_setup
9316 00:56:56.268396 ovl_layer_smi_id_en
9317 00:56:56.271611 ovl_layer_smi_id_en
9318 00:56:56.271701 ccorr_config
9319 00:56:56.271766 aal_config
9320 00:56:56.274766 gamma_config
9321 00:56:56.274849 postmask_config
9322 00:56:56.278240 dither_config
9323 00:56:56.281324 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9324 00:56:56.288165 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9325 00:56:56.291534 Root Device init finished in 553 msecs
9326 00:56:56.294732 CPU_CLUSTER: 0 init
9327 00:56:56.301542 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9328 00:56:56.304677 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9329 00:56:56.308077 APU_MBOX 0x190000b0 = 0x10001
9330 00:56:56.311498 APU_MBOX 0x190001b0 = 0x10001
9331 00:56:56.314758 APU_MBOX 0x190005b0 = 0x10001
9332 00:56:56.318077 APU_MBOX 0x190006b0 = 0x10001
9333 00:56:56.321237 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9334 00:56:56.334151 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9335 00:56:56.346679 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9336 00:56:56.353269 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9337 00:56:56.364456 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9338 00:56:56.373845 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9339 00:56:56.377346 CPU_CLUSTER: 0 init finished in 81 msecs
9340 00:56:56.380698 Devices initialized
9341 00:56:56.384006 Show all devs... After init.
9342 00:56:56.384101 Root Device: enabled 1
9343 00:56:56.387245 CPU_CLUSTER: 0: enabled 1
9344 00:56:56.390643 CPU: 00: enabled 1
9345 00:56:56.393911 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9346 00:56:56.397101 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9347 00:56:56.400365 ELOG: NV offset 0x57f000 size 0x1000
9348 00:56:56.406879 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9349 00:56:56.413618 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9350 00:56:56.416902 ELOG: Event(17) added with size 13 at 2024-01-19 00:56:56 UTC
9351 00:56:56.423418 out: cmd=0x121: 03 db 21 01 00 00 00 00
9352 00:56:56.426743 in-header: 03 97 00 00 2c 00 00 00
9353 00:56:56.436840 in-data: c8 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 00:56:56.443396 ELOG: Event(A1) added with size 10 at 2024-01-19 00:56:56 UTC
9355 00:56:56.450219 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9356 00:56:56.456709 ELOG: Event(A0) added with size 9 at 2024-01-19 00:56:56 UTC
9357 00:56:56.460049 elog_add_boot_reason: Logged dev mode boot
9358 00:56:56.463259 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9359 00:56:56.466874 Finalize devices...
9360 00:56:56.466975 Devices finalized
9361 00:56:56.473250 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9362 00:56:56.476689 Writing coreboot table at 0xffe64000
9363 00:56:56.479944 0. 000000000010a000-0000000000113fff: RAMSTAGE
9364 00:56:56.483393 1. 0000000040000000-00000000400fffff: RAM
9365 00:56:56.489984 2. 0000000040100000-000000004032afff: RAMSTAGE
9366 00:56:56.493148 3. 000000004032b000-00000000545fffff: RAM
9367 00:56:56.496458 4. 0000000054600000-000000005465ffff: BL31
9368 00:56:56.499964 5. 0000000054660000-00000000ffe63fff: RAM
9369 00:56:56.506291 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9370 00:56:56.509543 7. 0000000100000000-000000023fffffff: RAM
9371 00:56:56.512930 Passing 5 GPIOs to payload:
9372 00:56:56.516498 NAME | PORT | POLARITY | VALUE
9373 00:56:56.519690 EC in RW | 0x000000aa | low | undefined
9374 00:56:56.526254 EC interrupt | 0x00000005 | low | undefined
9375 00:56:56.529686 TPM interrupt | 0x000000ab | high | undefined
9376 00:56:56.536257 SD card detect | 0x00000011 | high | undefined
9377 00:56:56.539597 speaker enable | 0x00000093 | high | undefined
9378 00:56:56.542824 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9379 00:56:56.546004 in-header: 03 f9 00 00 02 00 00 00
9380 00:56:56.549235 in-data: 02 00
9381 00:56:56.549328 ADC[4]: Raw value=894821 ID=7
9382 00:56:56.552672 ADC[3]: Raw value=213070 ID=1
9383 00:56:56.556026 RAM Code: 0x71
9384 00:56:56.559177 ADC[6]: Raw value=74722 ID=0
9385 00:56:56.559269 ADC[5]: Raw value=212700 ID=1
9386 00:56:56.562607 SKU Code: 0x1
9387 00:56:56.566071 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1418
9388 00:56:56.569407 coreboot table: 964 bytes.
9389 00:56:56.572593 IMD ROOT 0. 0xfffff000 0x00001000
9390 00:56:56.575755 IMD SMALL 1. 0xffffe000 0x00001000
9391 00:56:56.579029 RO MCACHE 2. 0xffffc000 0x00001104
9392 00:56:56.582546 CONSOLE 3. 0xfff7c000 0x00080000
9393 00:56:56.585752 FMAP 4. 0xfff7b000 0x00000452
9394 00:56:56.588978 TIME STAMP 5. 0xfff7a000 0x00000910
9395 00:56:56.592282 VBOOT WORK 6. 0xfff66000 0x00014000
9396 00:56:56.595642 RAMOOPS 7. 0xffe66000 0x00100000
9397 00:56:56.599113 COREBOOT 8. 0xffe64000 0x00002000
9398 00:56:56.602258 IMD small region:
9399 00:56:56.605429 IMD ROOT 0. 0xffffec00 0x00000400
9400 00:56:56.608858 VPD 1. 0xffffeb80 0x0000006c
9401 00:56:56.612249 MMC STATUS 2. 0xffffeb60 0x00000004
9402 00:56:56.615489 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9403 00:56:56.618936 Probing TPM: done!
9404 00:56:56.622455 Connected to device vid:did:rid of 1ae0:0028:00
9405 00:56:56.632781 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9406 00:56:56.636020 Initialized TPM device CR50 revision 0
9407 00:56:56.639562 Checking cr50 for pending updates
9408 00:56:56.643486 Reading cr50 TPM mode
9409 00:56:56.652195 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9410 00:56:56.658950 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9411 00:56:56.698861 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9412 00:56:56.702165 Checking segment from ROM address 0x40100000
9413 00:56:56.705282 Checking segment from ROM address 0x4010001c
9414 00:56:56.712199 Loading segment from ROM address 0x40100000
9415 00:56:56.712331 code (compression=0)
9416 00:56:56.718983 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9417 00:56:56.729055 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9418 00:56:56.729193 it's not compressed!
9419 00:56:56.735570 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9420 00:56:56.738856 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9421 00:56:56.759348 Loading segment from ROM address 0x4010001c
9422 00:56:56.759503 Entry Point 0x80000000
9423 00:56:56.762552 Loaded segments
9424 00:56:56.765844 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9425 00:56:56.772388 Jumping to boot code at 0x80000000(0xffe64000)
9426 00:56:56.779321 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9427 00:56:56.785990 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9428 00:56:56.793667 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9429 00:56:56.797081 Checking segment from ROM address 0x40100000
9430 00:56:56.800209 Checking segment from ROM address 0x4010001c
9431 00:56:56.806860 Loading segment from ROM address 0x40100000
9432 00:56:56.806971 code (compression=1)
9433 00:56:56.813497 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9434 00:56:56.823722 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9435 00:56:56.823859 using LZMA
9436 00:56:56.831994 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9437 00:56:56.839034 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9438 00:56:56.842260 Loading segment from ROM address 0x4010001c
9439 00:56:56.842376 Entry Point 0x54601000
9440 00:56:56.845420 Loaded segments
9441 00:56:56.848617 NOTICE: MT8192 bl31_setup
9442 00:56:56.855758 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9443 00:56:56.859136 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9444 00:56:56.862471 WARNING: region 0:
9445 00:56:56.865527 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 00:56:56.865620 WARNING: region 1:
9447 00:56:56.872518 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9448 00:56:56.875804 WARNING: region 2:
9449 00:56:56.878872 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9450 00:56:56.882291 WARNING: region 3:
9451 00:56:56.885501 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9452 00:56:56.888780 WARNING: region 4:
9453 00:56:56.895512 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9454 00:56:56.895623 WARNING: region 5:
9455 00:56:56.898795 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 00:56:56.902102 WARNING: region 6:
9457 00:56:56.905432 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 00:56:56.908680 WARNING: region 7:
9459 00:56:56.912179 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 00:56:56.918646 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9461 00:56:56.921953 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9462 00:56:56.925472 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9463 00:56:56.932143 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9464 00:56:56.935349 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9465 00:56:56.938666 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9466 00:56:56.945427 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9467 00:56:56.948851 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9468 00:56:56.955208 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9469 00:56:56.958762 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9470 00:56:56.962003 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9471 00:56:56.968573 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9472 00:56:56.972084 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9473 00:56:56.975235 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9474 00:56:56.981859 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9475 00:56:56.985272 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9476 00:56:56.992031 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9477 00:56:56.995234 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9478 00:56:56.998444 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9479 00:56:57.005215 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9480 00:56:57.008702 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9481 00:56:57.011998 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9482 00:56:57.018626 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9483 00:56:57.022018 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9484 00:56:57.028673 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9485 00:56:57.031892 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9486 00:56:57.035210 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9487 00:56:57.041807 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9488 00:56:57.045235 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9489 00:56:57.051818 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9490 00:56:57.055114 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9491 00:56:57.058489 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9492 00:56:57.065288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9493 00:56:57.068485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9494 00:56:57.071874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9495 00:56:57.075263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9496 00:56:57.082041 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9497 00:56:57.085382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9498 00:56:57.088772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9499 00:56:57.091929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9500 00:56:57.098773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9501 00:56:57.102151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9502 00:56:57.105436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9503 00:56:57.108737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9504 00:56:57.115607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9505 00:56:57.118661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9506 00:56:57.122209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9507 00:56:57.125427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9508 00:56:57.132309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9509 00:56:57.135506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9510 00:56:57.141848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9511 00:56:57.145375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9512 00:56:57.148545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9513 00:56:57.155519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9514 00:56:57.158581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9515 00:56:57.165243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9516 00:56:57.168484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9517 00:56:57.175194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9518 00:56:57.178685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9519 00:56:57.185240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9520 00:56:57.188447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9521 00:56:57.192054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9522 00:56:57.198799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9523 00:56:57.202067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9524 00:56:57.208514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9525 00:56:57.212130 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9526 00:56:57.218502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9527 00:56:57.221995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9528 00:56:57.225173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9529 00:56:57.231856 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9530 00:56:57.235149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9531 00:56:57.241734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9532 00:56:57.244985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9533 00:56:57.251612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9534 00:56:57.254962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9535 00:56:57.261778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9536 00:56:57.265021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9537 00:56:57.268334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9538 00:56:57.274880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9539 00:56:57.278351 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9540 00:56:57.284970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9541 00:56:57.288214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9542 00:56:57.295028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9543 00:56:57.298138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9544 00:56:57.301368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9545 00:56:57.308100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9546 00:56:57.311456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9547 00:56:57.318135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9548 00:56:57.321213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9549 00:56:57.328140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9550 00:56:57.331416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9551 00:56:57.337744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9552 00:56:57.341325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9553 00:56:57.344482 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9554 00:56:57.351479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9555 00:56:57.354634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9556 00:56:57.361248 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9557 00:56:57.364505 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9558 00:56:57.367975 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9559 00:56:57.371165 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9560 00:56:57.377855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9561 00:56:57.381437 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9562 00:56:57.384742 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9563 00:56:57.391365 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9564 00:56:57.394822 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9565 00:56:57.397974 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9566 00:56:57.404761 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9567 00:56:57.408220 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9568 00:56:57.414860 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9569 00:56:57.418044 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9570 00:56:57.421468 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9571 00:56:57.428147 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9572 00:56:57.431445 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9573 00:56:57.438267 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9574 00:56:57.441618 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9575 00:56:57.444642 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9576 00:56:57.451621 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9577 00:56:57.454735 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9578 00:56:57.457992 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9579 00:56:57.464564 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9580 00:56:57.467886 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9581 00:56:57.471478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9582 00:56:57.474724 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9583 00:56:57.477978 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9584 00:56:57.484714 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9585 00:56:57.488319 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9586 00:56:57.494690 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9587 00:56:57.498072 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9588 00:56:57.501604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9589 00:56:57.508162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9590 00:56:57.511474 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9591 00:56:57.518048 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9592 00:56:57.521431 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9593 00:56:57.524673 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9594 00:56:57.531566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9595 00:56:57.534811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9596 00:56:57.541581 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9597 00:56:57.544874 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9598 00:56:57.548048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9599 00:56:57.554879 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9600 00:56:57.558161 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9601 00:56:57.561470 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9602 00:56:57.568099 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9603 00:56:57.571427 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9604 00:56:57.578479 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9605 00:56:57.581632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9606 00:56:57.584810 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9607 00:56:57.591678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9608 00:56:57.594948 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9609 00:56:57.601602 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9610 00:56:57.604843 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9611 00:56:57.608309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9612 00:56:57.615162 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9613 00:56:57.618273 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9614 00:56:57.621468 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9615 00:56:57.628523 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9616 00:56:57.631759 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9617 00:56:57.638691 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9618 00:56:57.641463 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9619 00:56:57.645015 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9620 00:56:57.651408 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9621 00:56:57.654971 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9622 00:56:57.661379 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9623 00:56:57.664956 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9624 00:56:57.667965 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9625 00:56:57.674668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9626 00:56:57.678132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9627 00:56:57.681528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9628 00:56:57.688004 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9629 00:56:57.691285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9630 00:56:57.698007 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9631 00:56:57.701142 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9632 00:56:57.704437 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9633 00:56:57.711007 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9634 00:56:57.714634 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9635 00:56:57.721305 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9636 00:56:57.724248 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9637 00:56:57.727741 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9638 00:56:57.734291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9639 00:56:57.737401 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9640 00:56:57.744060 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9641 00:56:57.747553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9642 00:56:57.750867 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9643 00:56:57.757429 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9644 00:56:57.760721 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9645 00:56:57.767239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9646 00:56:57.770714 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9647 00:56:57.773746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9648 00:56:57.780691 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9649 00:56:57.783854 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9650 00:56:57.790532 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9651 00:56:57.794056 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9652 00:56:57.800398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9653 00:56:57.803827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9654 00:56:57.807167 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9655 00:56:57.813846 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9656 00:56:57.817186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9657 00:56:57.823772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9658 00:56:57.826853 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9659 00:56:57.833500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9660 00:56:57.836862 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9661 00:56:57.840017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9662 00:56:57.847023 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9663 00:56:57.849934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9664 00:56:57.856669 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9665 00:56:57.859887 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9666 00:56:57.863482 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9667 00:56:57.870068 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9668 00:56:57.873639 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9669 00:56:57.880247 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9670 00:56:57.883491 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9671 00:56:57.886822 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9672 00:56:57.893582 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9673 00:56:57.896764 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9674 00:56:57.903180 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9675 00:56:57.906703 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9676 00:56:57.913056 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9677 00:56:57.916590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9678 00:56:57.919835 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9679 00:56:57.926449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9680 00:56:57.929559 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9681 00:56:57.936430 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9682 00:56:57.939641 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9683 00:56:57.943148 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9684 00:56:57.949633 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9685 00:56:57.952780 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9686 00:56:57.959584 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9687 00:56:57.962772 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9688 00:56:57.969374 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9689 00:56:57.972913 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9690 00:56:57.976143 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9691 00:56:57.979582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9692 00:56:57.982752 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9693 00:56:57.989438 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9694 00:56:57.992661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9695 00:56:57.996276 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9696 00:56:58.002717 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9697 00:56:58.006165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9698 00:56:58.009665 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9699 00:56:58.016164 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9700 00:56:58.019603 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9701 00:56:58.026022 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9702 00:56:58.029244 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9703 00:56:58.032877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9704 00:56:58.039226 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9705 00:56:58.042851 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9706 00:56:58.045957 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9707 00:56:58.052611 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9708 00:56:58.055929 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9709 00:56:58.062493 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9710 00:56:58.065649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9711 00:56:58.069054 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9712 00:56:58.075728 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9713 00:56:58.079055 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9714 00:56:58.082371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9715 00:56:58.088857 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9716 00:56:58.092154 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9717 00:56:58.098590 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9718 00:56:58.101915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9719 00:56:58.105190 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9720 00:56:58.112138 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9721 00:56:58.115361 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9722 00:56:58.122048 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9723 00:56:58.125344 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9724 00:56:58.128705 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9725 00:56:58.135392 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9726 00:56:58.138479 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9727 00:56:58.141897 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9728 00:56:58.148603 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9729 00:56:58.151691 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9730 00:56:58.154874 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9731 00:56:58.158379 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9732 00:56:58.161648 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9733 00:56:58.168190 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9734 00:56:58.171594 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9735 00:56:58.174735 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9736 00:56:58.178277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9737 00:56:58.184813 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9738 00:56:58.188163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9739 00:56:58.191320 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9740 00:56:58.197854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9741 00:56:58.201375 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9742 00:56:58.204706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9743 00:56:58.211215 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9744 00:56:58.214645 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9745 00:56:58.221303 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9746 00:56:58.224633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9747 00:56:58.227896 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9748 00:56:58.234641 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9749 00:56:58.237775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9750 00:56:58.244524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9751 00:56:58.247869 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9752 00:56:58.251078 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9753 00:56:58.257816 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9754 00:56:58.260958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9755 00:56:58.267659 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9756 00:56:58.270835 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9757 00:56:58.274204 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9758 00:56:58.281036 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9759 00:56:58.284191 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9760 00:56:58.290842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9761 00:56:58.294279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9762 00:56:58.300608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9763 00:56:58.303971 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9764 00:56:58.307254 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9765 00:56:58.314034 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9766 00:56:58.317375 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9767 00:56:58.324095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9768 00:56:58.327360 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9769 00:56:58.330675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9770 00:56:58.337349 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9771 00:56:58.340598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9772 00:56:58.347216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9773 00:56:58.350529 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9774 00:56:58.354158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9775 00:56:58.360648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9776 00:56:58.363871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9777 00:56:58.370490 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9778 00:56:58.373841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9779 00:56:58.377136 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9780 00:56:58.383794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9781 00:56:58.387197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9782 00:56:58.393759 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9783 00:56:58.397114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9784 00:56:58.400206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9785 00:56:58.407002 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9786 00:56:58.410472 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9787 00:56:58.416890 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9788 00:56:58.420204 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9789 00:56:58.423581 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9790 00:56:58.430360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9791 00:56:58.433464 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9792 00:56:58.440282 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9793 00:56:58.443606 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9794 00:56:58.450235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9795 00:56:58.453413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9796 00:56:58.456687 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9797 00:56:58.463420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9798 00:56:58.466670 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9799 00:56:58.473226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9800 00:56:58.476689 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9801 00:56:58.480235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9802 00:56:58.486594 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9803 00:56:58.489834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9804 00:56:58.496160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9805 00:56:58.499707 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9806 00:56:58.506296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9807 00:56:58.509560 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9808 00:56:58.512732 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9809 00:56:58.519433 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9810 00:56:58.522686 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9811 00:56:58.529677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9812 00:56:58.532854 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9813 00:56:58.536310 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9814 00:56:58.542765 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9815 00:56:58.546006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9816 00:56:58.552854 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9817 00:56:58.555882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9818 00:56:58.562898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9819 00:56:58.566151 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9820 00:56:58.572631 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9821 00:56:58.575900 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9822 00:56:58.579217 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9823 00:56:58.586019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9824 00:56:58.589159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9825 00:56:58.595845 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9826 00:56:58.598963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9827 00:56:58.605756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9828 00:56:58.608921 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9829 00:56:58.612289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9830 00:56:58.619242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9831 00:56:58.622401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9832 00:56:58.628672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9833 00:56:58.632141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9834 00:56:58.638733 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9835 00:56:58.641907 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9836 00:56:58.648782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9837 00:56:58.652064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9838 00:56:58.655364 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9839 00:56:58.661867 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9840 00:56:58.665373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9841 00:56:58.671886 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9842 00:56:58.675149 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9843 00:56:58.681835 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9844 00:56:58.685024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9845 00:56:58.688497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9846 00:56:58.695270 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9847 00:56:58.698402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9848 00:56:58.705235 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9849 00:56:58.708350 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9850 00:56:58.714890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9851 00:56:58.718362 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9852 00:56:58.724840 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9853 00:56:58.728301 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9854 00:56:58.731520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9855 00:56:58.738221 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9856 00:56:58.741485 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9857 00:56:58.748097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9858 00:56:58.751481 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9859 00:56:58.758075 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9860 00:56:58.761344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9861 00:56:58.764503 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9862 00:56:58.771148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9863 00:56:58.774691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9864 00:56:58.781055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9865 00:56:58.784575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9866 00:56:58.791127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9867 00:56:58.794302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9868 00:56:58.801017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9869 00:56:58.804230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9870 00:56:58.811061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9871 00:56:58.814312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9872 00:56:58.817686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9873 00:56:58.824316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9874 00:56:58.827430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9875 00:56:58.834036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9876 00:56:58.837507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9877 00:56:58.843987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9878 00:56:58.847114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9879 00:56:58.854083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9880 00:56:58.857247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9881 00:56:58.863864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9882 00:56:58.867051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9883 00:56:58.873757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9884 00:56:58.876990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9885 00:56:58.883735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9886 00:56:58.886974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9887 00:56:58.893518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9888 00:56:58.897003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9889 00:56:58.903588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9890 00:56:58.907005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9891 00:56:58.913467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9892 00:56:58.916744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9893 00:56:58.923414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9894 00:56:58.926624 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9895 00:56:58.930071 INFO: [APUAPC] vio 0
9896 00:56:58.933362 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9897 00:56:58.939946 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9898 00:56:58.943200 INFO: [APUAPC] D0_APC_0: 0x400510
9899 00:56:58.946576 INFO: [APUAPC] D0_APC_1: 0x0
9900 00:56:58.949797 INFO: [APUAPC] D0_APC_2: 0x1540
9901 00:56:58.949873 INFO: [APUAPC] D0_APC_3: 0x0
9902 00:56:58.953194 INFO: [APUAPC] D1_APC_0: 0xffffffff
9903 00:56:58.956595 INFO: [APUAPC] D1_APC_1: 0xffffffff
9904 00:56:58.960084 INFO: [APUAPC] D1_APC_2: 0x3fffff
9905 00:56:58.963207 INFO: [APUAPC] D1_APC_3: 0x0
9906 00:56:58.966238 INFO: [APUAPC] D2_APC_0: 0xffffffff
9907 00:56:58.969785 INFO: [APUAPC] D2_APC_1: 0xffffffff
9908 00:56:58.973029 INFO: [APUAPC] D2_APC_2: 0x3fffff
9909 00:56:58.976423 INFO: [APUAPC] D2_APC_3: 0x0
9910 00:56:58.979664 INFO: [APUAPC] D3_APC_0: 0xffffffff
9911 00:56:58.982718 INFO: [APUAPC] D3_APC_1: 0xffffffff
9912 00:56:58.986294 INFO: [APUAPC] D3_APC_2: 0x3fffff
9913 00:56:58.989631 INFO: [APUAPC] D3_APC_3: 0x0
9914 00:56:58.992848 INFO: [APUAPC] D4_APC_0: 0xffffffff
9915 00:56:58.996209 INFO: [APUAPC] D4_APC_1: 0xffffffff
9916 00:56:58.999378 INFO: [APUAPC] D4_APC_2: 0x3fffff
9917 00:56:59.002878 INFO: [APUAPC] D4_APC_3: 0x0
9918 00:56:59.006105 INFO: [APUAPC] D5_APC_0: 0xffffffff
9919 00:56:59.009305 INFO: [APUAPC] D5_APC_1: 0xffffffff
9920 00:56:59.012624 INFO: [APUAPC] D5_APC_2: 0x3fffff
9921 00:56:59.016088 INFO: [APUAPC] D5_APC_3: 0x0
9922 00:56:59.019414 INFO: [APUAPC] D6_APC_0: 0xffffffff
9923 00:56:59.022483 INFO: [APUAPC] D6_APC_1: 0xffffffff
9924 00:56:59.026193 INFO: [APUAPC] D6_APC_2: 0x3fffff
9925 00:56:59.029280 INFO: [APUAPC] D6_APC_3: 0x0
9926 00:56:59.032596 INFO: [APUAPC] D7_APC_0: 0xffffffff
9927 00:56:59.035873 INFO: [APUAPC] D7_APC_1: 0xffffffff
9928 00:56:59.039208 INFO: [APUAPC] D7_APC_2: 0x3fffff
9929 00:56:59.042661 INFO: [APUAPC] D7_APC_3: 0x0
9930 00:56:59.046007 INFO: [APUAPC] D8_APC_0: 0xffffffff
9931 00:56:59.049303 INFO: [APUAPC] D8_APC_1: 0xffffffff
9932 00:56:59.052387 INFO: [APUAPC] D8_APC_2: 0x3fffff
9933 00:56:59.055848 INFO: [APUAPC] D8_APC_3: 0x0
9934 00:56:59.059320 INFO: [APUAPC] D9_APC_0: 0xffffffff
9935 00:56:59.062728 INFO: [APUAPC] D9_APC_1: 0xffffffff
9936 00:56:59.065838 INFO: [APUAPC] D9_APC_2: 0x3fffff
9937 00:56:59.069275 INFO: [APUAPC] D9_APC_3: 0x0
9938 00:56:59.072547 INFO: [APUAPC] D10_APC_0: 0xffffffff
9939 00:56:59.075804 INFO: [APUAPC] D10_APC_1: 0xffffffff
9940 00:56:59.079169 INFO: [APUAPC] D10_APC_2: 0x3fffff
9941 00:56:59.082479 INFO: [APUAPC] D10_APC_3: 0x0
9942 00:56:59.085705 INFO: [APUAPC] D11_APC_0: 0xffffffff
9943 00:56:59.089238 INFO: [APUAPC] D11_APC_1: 0xffffffff
9944 00:56:59.092350 INFO: [APUAPC] D11_APC_2: 0x3fffff
9945 00:56:59.095584 INFO: [APUAPC] D11_APC_3: 0x0
9946 00:56:59.099173 INFO: [APUAPC] D12_APC_0: 0xffffffff
9947 00:56:59.102312 INFO: [APUAPC] D12_APC_1: 0xffffffff
9948 00:56:59.105622 INFO: [APUAPC] D12_APC_2: 0x3fffff
9949 00:56:59.108758 INFO: [APUAPC] D12_APC_3: 0x0
9950 00:56:59.112341 INFO: [APUAPC] D13_APC_0: 0xffffffff
9951 00:56:59.115550 INFO: [APUAPC] D13_APC_1: 0xffffffff
9952 00:56:59.118910 INFO: [APUAPC] D13_APC_2: 0x3fffff
9953 00:56:59.122056 INFO: [APUAPC] D13_APC_3: 0x0
9954 00:56:59.125651 INFO: [APUAPC] D14_APC_0: 0xffffffff
9955 00:56:59.128736 INFO: [APUAPC] D14_APC_1: 0xffffffff
9956 00:56:59.131943 INFO: [APUAPC] D14_APC_2: 0x3fffff
9957 00:56:59.135445 INFO: [APUAPC] D14_APC_3: 0x0
9958 00:56:59.139026 INFO: [APUAPC] D15_APC_0: 0xffffffff
9959 00:56:59.142270 INFO: [APUAPC] D15_APC_1: 0xffffffff
9960 00:56:59.145372 INFO: [APUAPC] D15_APC_2: 0x3fffff
9961 00:56:59.148594 INFO: [APUAPC] D15_APC_3: 0x0
9962 00:56:59.152339 INFO: [APUAPC] APC_CON: 0x4
9963 00:56:59.155212 INFO: [NOCDAPC] D0_APC_0: 0x0
9964 00:56:59.158675 INFO: [NOCDAPC] D0_APC_1: 0x0
9965 00:56:59.158751 INFO: [NOCDAPC] D1_APC_0: 0x0
9966 00:56:59.161856 INFO: [NOCDAPC] D1_APC_1: 0xfff
9967 00:56:59.165322 INFO: [NOCDAPC] D2_APC_0: 0x0
9968 00:56:59.168508 INFO: [NOCDAPC] D2_APC_1: 0xfff
9969 00:56:59.171738 INFO: [NOCDAPC] D3_APC_0: 0x0
9970 00:56:59.175133 INFO: [NOCDAPC] D3_APC_1: 0xfff
9971 00:56:59.178559 INFO: [NOCDAPC] D4_APC_0: 0x0
9972 00:56:59.181643 INFO: [NOCDAPC] D4_APC_1: 0xfff
9973 00:56:59.185183 INFO: [NOCDAPC] D5_APC_0: 0x0
9974 00:56:59.188532 INFO: [NOCDAPC] D5_APC_1: 0xfff
9975 00:56:59.188609 INFO: [NOCDAPC] D6_APC_0: 0x0
9976 00:56:59.191795 INFO: [NOCDAPC] D6_APC_1: 0xfff
9977 00:56:59.195070 INFO: [NOCDAPC] D7_APC_0: 0x0
9978 00:56:59.198554 INFO: [NOCDAPC] D7_APC_1: 0xfff
9979 00:56:59.201828 INFO: [NOCDAPC] D8_APC_0: 0x0
9980 00:56:59.205069 INFO: [NOCDAPC] D8_APC_1: 0xfff
9981 00:56:59.208345 INFO: [NOCDAPC] D9_APC_0: 0x0
9982 00:56:59.211861 INFO: [NOCDAPC] D9_APC_1: 0xfff
9983 00:56:59.215254 INFO: [NOCDAPC] D10_APC_0: 0x0
9984 00:56:59.218393 INFO: [NOCDAPC] D10_APC_1: 0xfff
9985 00:56:59.221910 INFO: [NOCDAPC] D11_APC_0: 0x0
9986 00:56:59.225252 INFO: [NOCDAPC] D11_APC_1: 0xfff
9987 00:56:59.228430 INFO: [NOCDAPC] D12_APC_0: 0x0
9988 00:56:59.228505 INFO: [NOCDAPC] D12_APC_1: 0xfff
9989 00:56:59.231864 INFO: [NOCDAPC] D13_APC_0: 0x0
9990 00:56:59.235368 INFO: [NOCDAPC] D13_APC_1: 0xfff
9991 00:56:59.238489 INFO: [NOCDAPC] D14_APC_0: 0x0
9992 00:56:59.241773 INFO: [NOCDAPC] D14_APC_1: 0xfff
9993 00:56:59.245199 INFO: [NOCDAPC] D15_APC_0: 0x0
9994 00:56:59.248278 INFO: [NOCDAPC] D15_APC_1: 0xfff
9995 00:56:59.251606 INFO: [NOCDAPC] APC_CON: 0x4
9996 00:56:59.255235 INFO: [APUAPC] set_apusys_apc done
9997 00:56:59.258490 INFO: [DEVAPC] devapc_init done
9998 00:56:59.261658 INFO: GICv3 without legacy support detected.
9999 00:56:59.264869 INFO: ARM GICv3 driver initialized in EL3
10000 00:56:59.268354 INFO: Maximum SPI INTID supported: 639
10001 00:56:59.275066 INFO: BL31: Initializing runtime services
10002 00:56:59.278234 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10003 00:56:59.281361 INFO: SPM: enable CPC mode
10004 00:56:59.288046 INFO: mcdi ready for mcusys-off-idle and system suspend
10005 00:56:59.291281 INFO: BL31: Preparing for EL3 exit to normal world
10006 00:56:59.294581 INFO: Entry point address = 0x80000000
10007 00:56:59.297786 INFO: SPSR = 0x8
10008 00:56:59.303721
10009 00:56:59.303840
10010 00:56:59.303933
10011 00:56:59.304693 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10012 00:56:59.304814 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10013 00:56:59.304906 Setting prompt string to ['asurada:']
10014 00:56:59.305001 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10015 00:56:59.306820 Starting depthcharge on Spherion...
10016 00:56:59.306907
10017 00:56:59.306993 Wipe memory regions:
10018 00:56:59.307074
10019 00:56:59.310063 [0x00000040000000, 0x00000054600000)
10020 00:56:59.432418
10021 00:56:59.432586 [0x00000054660000, 0x00000080000000)
10022 00:56:59.693025
10023 00:56:59.693177 [0x000000821a7280, 0x000000ffe64000)
10024 00:57:00.438214
10025 00:57:00.438372 [0x00000100000000, 0x00000240000000)
10026 00:57:02.328558
10027 00:57:02.331606 Initializing XHCI USB controller at 0x11200000.
10028 00:57:03.369496
10029 00:57:03.372765 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10030 00:57:03.372858
10031 00:57:03.372924
10032 00:57:03.372984
10033 00:57:03.373265 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10035 00:57:03.473584 asurada: tftpboot 192.168.201.1 12571064/tftp-deploy-w3kw8ada/kernel/image.itb 12571064/tftp-deploy-w3kw8ada/kernel/cmdline
10036 00:57:03.473755 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10037 00:57:03.473856 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10038 00:57:03.477894 tftpboot 192.168.201.1 12571064/tftp-deploy-w3kw8ada/kernel/image.itbtp-deploy-w3kw8ada/kernel/cmdline
10039 00:57:03.477977
10040 00:57:03.478042 Waiting for link
10041 00:57:03.638125
10042 00:57:03.638312 R8152: Initializing
10043 00:57:03.638386
10044 00:57:03.641865 Version 6 (ocp_data = 5c30)
10045 00:57:03.641957
10046 00:57:03.644910 R8152: Done initializing
10047 00:57:03.644996
10048 00:57:03.645098 Adding net device
10049 00:57:05.548835
10050 00:57:05.548980 done.
10051 00:57:05.549077
10052 00:57:05.549157 MAC: 00:24:32:30:78:ff
10053 00:57:05.549255
10054 00:57:05.552273 Sending DHCP discover... done.
10055 00:57:05.552358
10056 00:57:05.555589 Waiting for reply... done.
10057 00:57:05.555680
10058 00:57:05.558734 Sending DHCP request... done.
10059 00:57:05.558818
10060 00:57:05.563237 Waiting for reply... done.
10061 00:57:05.563330
10062 00:57:05.563414 My ip is 192.168.201.21
10063 00:57:05.563494
10064 00:57:05.566807 The DHCP server ip is 192.168.201.1
10065 00:57:05.566899
10066 00:57:05.573112 TFTP server IP predefined by user: 192.168.201.1
10067 00:57:05.573191
10068 00:57:05.579736 Bootfile predefined by user: 12571064/tftp-deploy-w3kw8ada/kernel/image.itb
10069 00:57:05.579811
10070 00:57:05.579874 Sending tftp read request... done.
10071 00:57:05.582993
10072 00:57:05.586819 Waiting for the transfer...
10073 00:57:05.586893
10074 00:57:06.151692 00000000 ################################################################
10075 00:57:06.151838
10076 00:57:06.755579 00080000 ################################################################
10077 00:57:06.755745
10078 00:57:07.427750 00100000 ################################################################
10079 00:57:07.428300
10080 00:57:08.115664 00180000 ################################################################
10081 00:57:08.116187
10082 00:57:08.804148 00200000 ################################################################
10083 00:57:08.804828
10084 00:57:09.475177 00280000 ################################################################
10085 00:57:09.475790
10086 00:57:10.122675 00300000 ################################################################
10087 00:57:10.122856
10088 00:57:10.665627 00380000 ################################################################
10089 00:57:10.665783
10090 00:57:11.199927 00400000 ################################################################
10091 00:57:11.200076
10092 00:57:11.748254 00480000 ################################################################
10093 00:57:11.748416
10094 00:57:12.287350 00500000 ################################################################
10095 00:57:12.287493
10096 00:57:12.838497 00580000 ################################################################
10097 00:57:12.838646
10098 00:57:13.392108 00600000 ################################################################
10099 00:57:13.392252
10100 00:57:14.062339 00680000 ################################################################
10101 00:57:14.062862
10102 00:57:14.587958 00700000 ################################################################
10103 00:57:14.588174
10104 00:57:15.113090 00780000 ################################################################
10105 00:57:15.113250
10106 00:57:15.645617 00800000 ################################################################
10107 00:57:15.645758
10108 00:57:16.240131 00880000 ################################################################
10109 00:57:16.240737
10110 00:57:16.802920 00900000 ################################################################
10111 00:57:16.803064
10112 00:57:17.337137 00980000 ################################################################
10113 00:57:17.337306
10114 00:57:17.878526 00a00000 ################################################################
10115 00:57:17.878692
10116 00:57:18.414006 00a80000 ################################################################
10117 00:57:18.414146
10118 00:57:18.957209 00b00000 ################################################################
10119 00:57:18.957342
10120 00:57:19.494251 00b80000 ################################################################
10121 00:57:19.494395
10122 00:57:20.021509 00c00000 ################################################################
10123 00:57:20.021660
10124 00:57:20.549878 00c80000 ################################################################
10125 00:57:20.550017
10126 00:57:21.106745 00d00000 ################################################################
10127 00:57:21.106889
10128 00:57:21.662165 00d80000 ################################################################
10129 00:57:21.662336
10130 00:57:22.193647 00e00000 ################################################################
10131 00:57:22.193797
10132 00:57:22.727517 00e80000 ################################################################
10133 00:57:22.727663
10134 00:57:23.256609 00f00000 ################################################################
10135 00:57:23.256747
10136 00:57:23.789694 00f80000 ################################################################
10137 00:57:23.789831
10138 00:57:24.317907 01000000 ################################################################
10139 00:57:24.318078
10140 00:57:24.845933 01080000 ################################################################
10141 00:57:24.846080
10142 00:57:25.372761 01100000 ################################################################
10143 00:57:25.372899
10144 00:57:25.898548 01180000 ################################################################
10145 00:57:25.898690
10146 00:57:26.436589 01200000 ################################################################
10147 00:57:26.436724
10148 00:57:26.972073 01280000 ################################################################
10149 00:57:26.972212
10150 00:57:27.500493 01300000 ################################################################
10151 00:57:27.500655
10152 00:57:28.025053 01380000 ################################################################
10153 00:57:28.025200
10154 00:57:28.549105 01400000 ################################################################
10155 00:57:28.549277
10156 00:57:29.086156 01480000 ################################################################
10157 00:57:29.086295
10158 00:57:29.617668 01500000 ################################################################
10159 00:57:29.617831
10160 00:57:30.169691 01580000 ################################################################
10161 00:57:30.169832
10162 00:57:30.818953 01600000 ################################################################
10163 00:57:30.819468
10164 00:57:31.501743 01680000 ################################################################
10165 00:57:31.502474
10166 00:57:32.181006 01700000 ################################################################
10167 00:57:32.181692
10168 00:57:32.715521 01780000 ################################################################
10169 00:57:32.715691
10170 00:57:33.243187 01800000 ################################################################
10171 00:57:33.243327
10172 00:57:33.805388 01880000 ################################################################
10173 00:57:33.805573
10174 00:57:34.372806 01900000 ################################################################
10175 00:57:34.372945
10176 00:57:34.939929 01980000 ################################################################
10177 00:57:34.940072
10178 00:57:35.485043 01a00000 ################################################################
10179 00:57:35.485197
10180 00:57:36.086722 01a80000 ################################################################
10181 00:57:36.086871
10182 00:57:36.653365 01b00000 ################################################################
10183 00:57:36.653543
10184 00:57:37.302445 01b80000 ################################################################
10185 00:57:37.302972
10186 00:57:38.004260 01c00000 ################################################################
10187 00:57:38.004944
10188 00:57:38.704886 01c80000 ################################################################
10189 00:57:38.705473
10190 00:57:39.380652 01d00000 ################################################################
10191 00:57:39.381186
10192 00:57:40.060471 01d80000 ################################################################
10193 00:57:40.060991
10194 00:57:40.661018 01e00000 ################################################################
10195 00:57:40.661155
10196 00:57:41.253278 01e80000 ################################################################
10197 00:57:41.253952
10198 00:57:41.928687 01f00000 ################################################################
10199 00:57:41.929216
10200 00:57:42.610741 01f80000 ################################################################
10201 00:57:42.611397
10202 00:57:43.292330 02000000 ################################################################
10203 00:57:43.292882
10204 00:57:43.964870 02080000 ################################################################
10205 00:57:43.965562
10206 00:57:44.637653 02100000 ################################################################
10207 00:57:44.638199
10208 00:57:45.258267 02180000 ################################################################
10209 00:57:45.258407
10210 00:57:45.894298 02200000 ################################################################
10211 00:57:45.894896
10212 00:57:46.597461 02280000 ################################################################
10213 00:57:46.598057
10214 00:57:47.296466 02300000 ################################################################
10215 00:57:47.297014
10216 00:57:47.990461 02380000 ################################################################
10217 00:57:47.991072
10218 00:57:48.677783 02400000 ################################################################
10219 00:57:48.678296
10220 00:57:49.374771 02480000 ################################################################
10221 00:57:49.375320
10222 00:57:49.919418 02500000 ################################################################
10223 00:57:49.919559
10224 00:57:50.510652 02580000 ################################################################
10225 00:57:50.511222
10226 00:57:51.197008 02600000 ################################################################
10227 00:57:51.197568
10228 00:57:51.842362 02680000 ################################################################
10229 00:57:51.842500
10230 00:57:52.460638 02700000 ################################################################
10231 00:57:52.460784
10232 00:57:53.029768 02780000 ################################################################
10233 00:57:53.029910
10234 00:57:53.595548 02800000 ################################################################
10235 00:57:53.595727
10236 00:57:54.220104 02880000 ################################################################
10237 00:57:54.220622
10238 00:57:54.900646 02900000 ################################################################
10239 00:57:54.901255
10240 00:57:55.663116 02980000 ################################################################
10241 00:57:55.663703
10242 00:57:56.395806 02a00000 ################################################################
10243 00:57:56.396327
10244 00:57:57.115870 02a80000 ################################################################
10245 00:57:57.116009
10246 00:57:57.712824 02b00000 ################################################################
10247 00:57:57.713838
10248 00:57:58.270682 02b80000 ################################################################
10249 00:57:58.270903
10250 00:57:58.840687 02c00000 ################################################################
10251 00:57:58.840822
10252 00:57:59.530981 02c80000 ################################################################
10253 00:57:59.531514
10254 00:58:00.289623 02d00000 ################################################################
10255 00:58:00.290148
10256 00:58:00.888167 02d80000 ################################################################
10257 00:58:00.888304
10258 00:58:01.503412 02e00000 ################################################################
10259 00:58:01.503571
10260 00:58:02.248046 02e80000 ################################################################
10261 00:58:02.248590
10262 00:58:02.997683 02f00000 ################################################################
10263 00:58:02.998214
10264 00:58:03.772378 02f80000 ################################################################
10265 00:58:03.773191
10266 00:58:04.521948 03000000 ################################################################
10267 00:58:04.522474
10268 00:58:05.272207 03080000 ################################################################
10269 00:58:05.272919
10270 00:58:05.378332 03100000 ######### done.
10271 00:58:05.378876
10272 00:58:05.381653 The bootfile was 51453166 bytes long.
10273 00:58:05.382080
10274 00:58:05.384603 Sending tftp read request... done.
10275 00:58:05.385022
10276 00:58:05.388847 Waiting for the transfer...
10277 00:58:05.389270
10278 00:58:05.389642 00000000 # done.
10279 00:58:05.389973
10280 00:58:05.395353 Command line loaded dynamically from TFTP file: 12571064/tftp-deploy-w3kw8ada/kernel/cmdline
10281 00:58:05.395886
10282 00:58:05.411891 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10283 00:58:05.412421
10284 00:58:05.412847 Loading FIT.
10285 00:58:05.413175
10286 00:58:05.415126 Image ramdisk-1 has 39355230 bytes.
10287 00:58:05.415550
10288 00:58:05.418690 Image fdt-1 has 47278 bytes.
10289 00:58:05.419224
10290 00:58:05.421662 Image kernel-1 has 12048624 bytes.
10291 00:58:05.422088
10292 00:58:05.428586 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 00:58:05.429171
10294 00:58:05.448158 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 00:58:05.448716
10296 00:58:05.451512 Choosing best match conf-1 for compat google,spherion-rev2.
10297 00:58:05.456407
10298 00:58:05.461045 Connected to device vid:did:rid of 1ae0:0028:00
10299 00:58:05.467954
10300 00:58:05.470887 tpm_get_response: command 0x17b, return code 0x0
10301 00:58:05.471321
10302 00:58:05.474302 ec_init: CrosEC protocol v3 supported (256, 248)
10303 00:58:05.480027
10304 00:58:05.483327 tpm_cleanup: add release locality here.
10305 00:58:05.483755
10306 00:58:05.484090 Shutting down all USB controllers.
10307 00:58:05.486641
10308 00:58:05.487063 Removing current net device
10309 00:58:05.487435
10310 00:58:05.493703 Exiting depthcharge with code 4 at timestamp: 95439890
10311 00:58:05.494236
10312 00:58:05.496503 LZMA decompressing kernel-1 to 0x821a6718
10313 00:58:05.496929
10314 00:58:05.500076 LZMA decompressing kernel-1 to 0x40000000
10315 00:58:06.998221
10316 00:58:06.998752 jumping to kernel
10317 00:58:07.000634 end: 2.2.4 bootloader-commands (duration 00:01:08) [common]
10318 00:58:07.001116 start: 2.2.5 auto-login-action (timeout 00:03:18) [common]
10319 00:58:07.001514 Setting prompt string to ['Linux version [0-9]']
10320 00:58:07.001868 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 00:58:07.002218 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 00:58:07.080915
10323 00:58:07.084243 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 00:58:07.088034 start: 2.2.5.1 login-action (timeout 00:03:18) [common]
10325 00:58:07.088726 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 00:58:07.089111 Setting prompt string to []
10327 00:58:07.089549 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10328 00:58:07.089937 Using line separator: #'\n'#
10329 00:58:07.090250 No login prompt set.
10330 00:58:07.090572 Parsing kernel messages
10331 00:58:07.090862 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10332 00:58:07.091367 [login-action] Waiting for messages, (timeout 00:03:17)
10333 00:58:07.107350 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j81675-arm64-gcc-10-defconfig-arm64-chromebook-jxb7j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024
10334 00:58:07.110982 [ 0.000000] random: crng init done
10335 00:58:07.117266 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10336 00:58:07.121268 [ 0.000000] efi: UEFI not found.
10337 00:58:07.127107 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10338 00:58:07.134379 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10339 00:58:07.143770 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10340 00:58:07.153591 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10341 00:58:07.160771 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10342 00:58:07.167357 [ 0.000000] printk: bootconsole [mtk8250] enabled
10343 00:58:07.173882 [ 0.000000] NUMA: No NUMA configuration found
10344 00:58:07.180420 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10345 00:58:07.183788 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10346 00:58:07.186790 [ 0.000000] Zone ranges:
10347 00:58:07.193623 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10348 00:58:07.196778 [ 0.000000] DMA32 empty
10349 00:58:07.203567 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10350 00:58:07.206980 [ 0.000000] Movable zone start for each node
10351 00:58:07.210131 [ 0.000000] Early memory node ranges
10352 00:58:07.216401 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10353 00:58:07.223066 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10354 00:58:07.229943 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10355 00:58:07.236192 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10356 00:58:07.242874 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10357 00:58:07.249762 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10358 00:58:07.305610 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10359 00:58:07.312029 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10360 00:58:07.318936 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10361 00:58:07.322075 [ 0.000000] psci: probing for conduit method from DT.
10362 00:58:07.328495 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10363 00:58:07.331959 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10364 00:58:07.338372 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10365 00:58:07.341768 [ 0.000000] psci: SMC Calling Convention v1.2
10366 00:58:07.348666 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10367 00:58:07.352320 [ 0.000000] Detected VIPT I-cache on CPU0
10368 00:58:07.358448 [ 0.000000] CPU features: detected: GIC system register CPU interface
10369 00:58:07.364742 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10370 00:58:07.371913 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10371 00:58:07.378162 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10372 00:58:07.388191 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10373 00:58:07.394363 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10374 00:58:07.397606 [ 0.000000] alternatives: applying boot alternatives
10375 00:58:07.404792 [ 0.000000] Fallback order for Node 0: 0
10376 00:58:07.411198 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10377 00:58:07.414396 [ 0.000000] Policy zone: Normal
10378 00:58:07.427686 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10379 00:58:07.437745 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10380 00:58:07.449947 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10381 00:58:07.459724 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10382 00:58:07.466327 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10383 00:58:07.469728 <6>[ 0.000000] software IO TLB: area num 8.
10384 00:58:07.525912 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10385 00:58:07.675687 <6>[ 0.000000] Memory: 7928824K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 423944K reserved, 32768K cma-reserved)
10386 00:58:07.682240 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10387 00:58:07.688767 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10388 00:58:07.692183 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10389 00:58:07.698912 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10390 00:58:07.705532 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10391 00:58:07.708792 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10392 00:58:07.718594 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10393 00:58:07.725069 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10394 00:58:07.731782 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10395 00:58:07.738433 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10396 00:58:07.741834 <6>[ 0.000000] GICv3: 608 SPIs implemented
10397 00:58:07.744971 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10398 00:58:07.751507 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10399 00:58:07.754506 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10400 00:58:07.761630 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10401 00:58:07.774889 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10402 00:58:07.788369 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10403 00:58:07.794802 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10404 00:58:07.802131 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10405 00:58:07.815424 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10406 00:58:07.822416 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10407 00:58:07.829031 <6>[ 0.009238] Console: colour dummy device 80x25
10408 00:58:07.838834 <6>[ 0.013964] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10409 00:58:07.845525 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10410 00:58:07.848789 <6>[ 0.029307] LSM: Security Framework initializing
10411 00:58:07.855125 <6>[ 0.034245] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 00:58:07.865139 <6>[ 0.042060] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 00:58:07.872106 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10414 00:58:07.878559 <6>[ 0.058908] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 00:58:07.888449 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10416 00:58:07.894969 <6>[ 0.072720] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 00:58:07.898028 <6>[ 0.079122] rcu: Hierarchical SRCU implementation.
10418 00:58:07.904668 <6>[ 0.084139] rcu: Max phase no-delay instances is 1000.
10419 00:58:07.911807 <6>[ 0.091196] EFI services will not be available.
10420 00:58:07.915068 <6>[ 0.096148] smp: Bringing up secondary CPUs ...
10421 00:58:07.922915 <6>[ 0.101195] Detected VIPT I-cache on CPU1
10422 00:58:07.929435 <6>[ 0.101265] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10423 00:58:07.936203 <6>[ 0.101297] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10424 00:58:07.939648 <6>[ 0.101637] Detected VIPT I-cache on CPU2
10425 00:58:07.945918 <6>[ 0.101689] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10426 00:58:07.955972 <6>[ 0.101708] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10427 00:58:07.959164 <6>[ 0.101966] Detected VIPT I-cache on CPU3
10428 00:58:07.965724 <6>[ 0.102012] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10429 00:58:07.972835 <6>[ 0.102027] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10430 00:58:07.976111 <6>[ 0.102329] CPU features: detected: Spectre-v4
10431 00:58:07.982438 <6>[ 0.102336] CPU features: detected: Spectre-BHB
10432 00:58:07.985917 <6>[ 0.102341] Detected PIPT I-cache on CPU4
10433 00:58:07.992340 <6>[ 0.102397] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10434 00:58:07.999017 <6>[ 0.102413] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10435 00:58:08.005647 <6>[ 0.102703] Detected PIPT I-cache on CPU5
10436 00:58:08.012376 <6>[ 0.102765] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10437 00:58:08.018974 <6>[ 0.102782] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10438 00:58:08.022105 <6>[ 0.103062] Detected PIPT I-cache on CPU6
10439 00:58:08.028467 <6>[ 0.103126] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10440 00:58:08.035055 <6>[ 0.103142] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10441 00:58:08.041575 <6>[ 0.103434] Detected PIPT I-cache on CPU7
10442 00:58:08.048489 <6>[ 0.103498] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10443 00:58:08.054908 <6>[ 0.103514] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10444 00:58:08.058593 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10445 00:58:08.065123 <6>[ 0.244823] SMP: Total of 8 processors activated.
10446 00:58:08.067957 <6>[ 0.249744] CPU features: detected: 32-bit EL0 Support
10447 00:58:08.077905 <6>[ 0.255106] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10448 00:58:08.085213 <6>[ 0.263906] CPU features: detected: Common not Private translations
10449 00:58:08.091463 <6>[ 0.270421] CPU features: detected: CRC32 instructions
10450 00:58:08.094525 <6>[ 0.275806] CPU features: detected: RCpc load-acquire (LDAPR)
10451 00:58:08.101435 <6>[ 0.281766] CPU features: detected: LSE atomic instructions
10452 00:58:08.108054 <6>[ 0.287547] CPU features: detected: Privileged Access Never
10453 00:58:08.114748 <6>[ 0.293326] CPU features: detected: RAS Extension Support
10454 00:58:08.121536 <6>[ 0.298955] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10455 00:58:08.124738 <6>[ 0.306217] CPU: All CPU(s) started at EL2
10456 00:58:08.131307 <6>[ 0.310534] alternatives: applying system-wide alternatives
10457 00:58:08.140483 <6>[ 0.321300] devtmpfs: initialized
10458 00:58:08.152507 <6>[ 0.330134] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10459 00:58:08.162641 <6>[ 0.340095] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10460 00:58:08.169539 <6>[ 0.348301] pinctrl core: initialized pinctrl subsystem
10461 00:58:08.172844 <6>[ 0.354969] DMI not present or invalid.
10462 00:58:08.179052 <6>[ 0.359381] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10463 00:58:08.189184 <6>[ 0.366236] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10464 00:58:08.195615 <6>[ 0.373815] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10465 00:58:08.206073 <6>[ 0.382041] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10466 00:58:08.208814 <6>[ 0.390281] audit: initializing netlink subsys (disabled)
10467 00:58:08.218821 <5>[ 0.395973] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10468 00:58:08.225507 <6>[ 0.396674] thermal_sys: Registered thermal governor 'step_wise'
10469 00:58:08.232117 <6>[ 0.403939] thermal_sys: Registered thermal governor 'power_allocator'
10470 00:58:08.235448 <6>[ 0.410193] cpuidle: using governor menu
10471 00:58:08.242213 <6>[ 0.421151] NET: Registered PF_QIPCRTR protocol family
10472 00:58:08.248784 <6>[ 0.426624] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10473 00:58:08.255077 <6>[ 0.433729] ASID allocator initialised with 32768 entries
10474 00:58:08.258138 <6>[ 0.440284] Serial: AMBA PL011 UART driver
10475 00:58:08.268265 <4>[ 0.449106] Trying to register duplicate clock ID: 134
10476 00:58:08.322407 <6>[ 0.506389] KASLR enabled
10477 00:58:08.336912 <6>[ 0.514125] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10478 00:58:08.343043 <6>[ 0.521141] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10479 00:58:08.349680 <6>[ 0.527632] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10480 00:58:08.356646 <6>[ 0.534640] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10481 00:58:08.363082 <6>[ 0.541128] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10482 00:58:08.369597 <6>[ 0.548134] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10483 00:58:08.376615 <6>[ 0.554624] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10484 00:58:08.383201 <6>[ 0.561628] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10485 00:58:08.386074 <6>[ 0.569132] ACPI: Interpreter disabled.
10486 00:58:08.395163 <6>[ 0.575545] iommu: Default domain type: Translated
10487 00:58:08.401685 <6>[ 0.580657] iommu: DMA domain TLB invalidation policy: strict mode
10488 00:58:08.404908 <5>[ 0.587311] SCSI subsystem initialized
10489 00:58:08.411352 <6>[ 0.591474] usbcore: registered new interface driver usbfs
10490 00:58:08.418156 <6>[ 0.597208] usbcore: registered new interface driver hub
10491 00:58:08.421516 <6>[ 0.602760] usbcore: registered new device driver usb
10492 00:58:08.428442 <6>[ 0.608861] pps_core: LinuxPPS API ver. 1 registered
10493 00:58:08.438029 <6>[ 0.614055] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10494 00:58:08.441179 <6>[ 0.623405] PTP clock support registered
10495 00:58:08.444862 <6>[ 0.627650] EDAC MC: Ver: 3.0.0
10496 00:58:08.452422 <6>[ 0.632805] FPGA manager framework
10497 00:58:08.458688 <6>[ 0.636485] Advanced Linux Sound Architecture Driver Initialized.
10498 00:58:08.461986 <6>[ 0.643257] vgaarb: loaded
10499 00:58:08.468863 <6>[ 0.646408] clocksource: Switched to clocksource arch_sys_counter
10500 00:58:08.472149 <5>[ 0.652850] VFS: Disk quotas dquot_6.6.0
10501 00:58:08.478455 <6>[ 0.657036] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10502 00:58:08.482175 <6>[ 0.664225] pnp: PnP ACPI: disabled
10503 00:58:08.490581 <6>[ 0.670931] NET: Registered PF_INET protocol family
10504 00:58:08.500318 <6>[ 0.676517] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10505 00:58:08.511782 <6>[ 0.688799] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10506 00:58:08.521173 <6>[ 0.697611] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10507 00:58:08.527877 <6>[ 0.705582] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10508 00:58:08.537615 <6>[ 0.714282] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10509 00:58:08.544691 <6>[ 0.724030] TCP: Hash tables configured (established 65536 bind 65536)
10510 00:58:08.551203 <6>[ 0.730887] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10511 00:58:08.561248 <6>[ 0.738088] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 00:58:08.567275 <6>[ 0.745792] NET: Registered PF_UNIX/PF_LOCAL protocol family
10513 00:58:08.570963 <6>[ 0.751962] RPC: Registered named UNIX socket transport module.
10514 00:58:08.577627 <6>[ 0.758114] RPC: Registered udp transport module.
10515 00:58:08.580759 <6>[ 0.763047] RPC: Registered tcp transport module.
10516 00:58:08.590645 <6>[ 0.767980] RPC: Registered tcp NFSv4.1 backchannel transport module.
10517 00:58:08.594052 <6>[ 0.774645] PCI: CLS 0 bytes, default 64
10518 00:58:08.597222 <6>[ 0.779039] Unpacking initramfs...
10519 00:58:08.621311 <6>[ 0.798539] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10520 00:58:08.630824 <6>[ 0.807234] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10521 00:58:08.634498 <6>[ 0.816128] kvm [1]: IPA Size Limit: 40 bits
10522 00:58:08.641155 <6>[ 0.820653] kvm [1]: GICv3: no GICV resource entry
10523 00:58:08.644502 <6>[ 0.825675] kvm [1]: disabling GICv2 emulation
10524 00:58:08.651067 <6>[ 0.830365] kvm [1]: GIC system register CPU interface enabled
10525 00:58:08.654280 <6>[ 0.836531] kvm [1]: vgic interrupt IRQ18
10526 00:58:08.660962 <6>[ 0.840887] kvm [1]: VHE mode initialized successfully
10527 00:58:08.667430 <5>[ 0.847296] Initialise system trusted keyrings
10528 00:58:08.674067 <6>[ 0.852098] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10529 00:58:08.681703 <6>[ 0.862183] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10530 00:58:08.688219 <5>[ 0.868575] NFS: Registering the id_resolver key type
10531 00:58:08.691473 <5>[ 0.873872] Key type id_resolver registered
10532 00:58:08.698262 <5>[ 0.878288] Key type id_legacy registered
10533 00:58:08.704924 <6>[ 0.882567] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10534 00:58:08.711428 <6>[ 0.889486] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10535 00:58:08.717994 <6>[ 0.897201] 9p: Installing v9fs 9p2000 file system support
10536 00:58:08.754114 <5>[ 0.934686] Key type asymmetric registered
10537 00:58:08.757045 <5>[ 0.939018] Asymmetric key parser 'x509' registered
10538 00:58:08.767254 <6>[ 0.944162] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10539 00:58:08.770492 <6>[ 0.951778] io scheduler mq-deadline registered
10540 00:58:08.773705 <6>[ 0.956539] io scheduler kyber registered
10541 00:58:08.793308 <6>[ 0.973817] EINJ: ACPI disabled.
10542 00:58:08.825573 <4>[ 0.999578] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 00:58:08.835239 <4>[ 1.010209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 00:58:08.850397 <6>[ 1.030950] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10545 00:58:08.857951 <6>[ 1.039023] printk: console [ttyS0] disabled
10546 00:58:08.886120 <6>[ 1.063673] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10547 00:58:08.893137 <6>[ 1.073149] printk: console [ttyS0] enabled
10548 00:58:08.896128 <6>[ 1.073149] printk: console [ttyS0] enabled
10549 00:58:08.902847 <6>[ 1.082045] printk: bootconsole [mtk8250] disabled
10550 00:58:08.906454 <6>[ 1.082045] printk: bootconsole [mtk8250] disabled
10551 00:58:08.912914 <6>[ 1.093319] SuperH (H)SCI(F) driver initialized
10552 00:58:08.916166 <6>[ 1.098617] msm_serial: driver initialized
10553 00:58:08.930189 <6>[ 1.107626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10554 00:58:08.940595 <6>[ 1.116189] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10555 00:58:08.947014 <6>[ 1.124732] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10556 00:58:08.956930 <6>[ 1.133361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10557 00:58:08.963640 <6>[ 1.142069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10558 00:58:08.973363 <6>[ 1.150784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10559 00:58:08.983254 <6>[ 1.159337] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10560 00:58:08.990189 <6>[ 1.168139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10561 00:58:08.999691 <6>[ 1.176684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10562 00:58:09.011879 <6>[ 1.192442] loop: module loaded
10563 00:58:09.018378 <6>[ 1.198387] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10564 00:58:09.041377 <4>[ 1.221817] mtk-pmic-keys: Failed to locate of_node [id: -1]
10565 00:58:09.047717 <6>[ 1.228702] megasas: 07.719.03.00-rc1
10566 00:58:09.057347 <6>[ 1.238301] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10567 00:58:09.065128 <6>[ 1.245793] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10568 00:58:09.081908 <6>[ 1.262247] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10569 00:58:09.137782 <6>[ 1.311953] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10570 00:58:10.229699 <6>[ 2.410313] Freeing initrd memory: 38428K
10571 00:58:10.239665 <6>[ 2.420640] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10572 00:58:10.250529 <6>[ 2.431530] tun: Universal TUN/TAP device driver, 1.6
10573 00:58:10.253784 <6>[ 2.437586] thunder_xcv, ver 1.0
10574 00:58:10.257292 <6>[ 2.441090] thunder_bgx, ver 1.0
10575 00:58:10.260297 <6>[ 2.444586] nicpf, ver 1.0
10576 00:58:10.271048 <6>[ 2.448585] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10577 00:58:10.273996 <6>[ 2.456061] hns3: Copyright (c) 2017 Huawei Corporation.
10578 00:58:10.277808 <6>[ 2.461647] hclge is initializing
10579 00:58:10.284084 <6>[ 2.465228] e1000: Intel(R) PRO/1000 Network Driver
10580 00:58:10.291371 <6>[ 2.470357] e1000: Copyright (c) 1999-2006 Intel Corporation.
10581 00:58:10.294555 <6>[ 2.476388] e1000e: Intel(R) PRO/1000 Network Driver
10582 00:58:10.300983 <6>[ 2.481604] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10583 00:58:10.307681 <6>[ 2.487789] igb: Intel(R) Gigabit Ethernet Network Driver
10584 00:58:10.314131 <6>[ 2.493439] igb: Copyright (c) 2007-2014 Intel Corporation.
10585 00:58:10.321188 <6>[ 2.499274] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10586 00:58:10.327138 <6>[ 2.505791] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10587 00:58:10.330668 <6>[ 2.512252] sky2: driver version 1.30
10588 00:58:10.337286 <6>[ 2.517233] VFIO - User Level meta-driver version: 0.3
10589 00:58:10.344560 <6>[ 2.525451] usbcore: registered new interface driver usb-storage
10590 00:58:10.351097 <6>[ 2.531897] usbcore: registered new device driver onboard-usb-hub
10591 00:58:10.360138 <6>[ 2.541037] mt6397-rtc mt6359-rtc: registered as rtc0
10592 00:58:10.369897 <6>[ 2.546505] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-19T00:58:10 UTC (1705625890)
10593 00:58:10.373176 <6>[ 2.556061] i2c_dev: i2c /dev entries driver
10594 00:58:10.389708 <6>[ 2.567709] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10595 00:58:10.409961 <6>[ 2.590701] cpu cpu0: EM: created perf domain
10596 00:58:10.413079 <6>[ 2.595626] cpu cpu4: EM: created perf domain
10597 00:58:10.420429 <6>[ 2.601191] sdhci: Secure Digital Host Controller Interface driver
10598 00:58:10.427288 <6>[ 2.607624] sdhci: Copyright(c) Pierre Ossman
10599 00:58:10.433886 <6>[ 2.612587] Synopsys Designware Multimedia Card Interface Driver
10600 00:58:10.440257 <6>[ 2.619214] sdhci-pltfm: SDHCI platform and OF driver helper
10601 00:58:10.443269 <6>[ 2.619308] mmc0: CQHCI version 5.10
10602 00:58:10.450442 <6>[ 2.629174] ledtrig-cpu: registered to indicate activity on CPUs
10603 00:58:10.457009 <6>[ 2.636145] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10604 00:58:10.463165 <6>[ 2.643190] usbcore: registered new interface driver usbhid
10605 00:58:10.466658 <6>[ 2.649012] usbhid: USB HID core driver
10606 00:58:10.473309 <6>[ 2.653212] spi_master spi0: will run message pump with realtime priority
10607 00:58:10.517122 <6>[ 2.691409] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10608 00:58:10.536258 <6>[ 2.707329] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10609 00:58:10.540106 <6>[ 2.721694] mmc0: Command Queue Engine enabled
10610 00:58:10.546496 <6>[ 2.726452] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10611 00:58:10.553151 <6>[ 2.733219] cros-ec-spi spi0.0: Chrome EC device registered
10612 00:58:10.556716 <6>[ 2.733704] mmcblk0: mmc0:0001 DA4128 116 GiB
10613 00:58:10.568299 <6>[ 2.749195] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10614 00:58:10.575731 <6>[ 2.756503] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10615 00:58:10.582001 <6>[ 2.762383] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10616 00:58:10.589112 <6>[ 2.768286] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10617 00:58:10.602911 <6>[ 2.780539] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10618 00:58:10.610420 <6>[ 2.791157] NET: Registered PF_PACKET protocol family
10619 00:58:10.613453 <6>[ 2.796550] 9pnet: Installing 9P2000 support
10620 00:58:10.620364 <5>[ 2.801122] Key type dns_resolver registered
10621 00:58:10.623547 <6>[ 2.806117] registered taskstats version 1
10622 00:58:10.630258 <5>[ 2.810504] Loading compiled-in X.509 certificates
10623 00:58:10.659958 <4>[ 2.834140] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10624 00:58:10.670125 <4>[ 2.844944] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 00:58:10.676775 <3>[ 2.855531] debugfs: File 'uA_load' in directory '/' already present!
10626 00:58:10.683388 <3>[ 2.862244] debugfs: File 'min_uV' in directory '/' already present!
10627 00:58:10.689647 <3>[ 2.868853] debugfs: File 'max_uV' in directory '/' already present!
10628 00:58:10.696255 <3>[ 2.875460] debugfs: File 'constraint_flags' in directory '/' already present!
10629 00:58:10.707519 <3>[ 2.885121] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10630 00:58:10.721159 <6>[ 2.901590] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10631 00:58:10.727880 <6>[ 2.908349] xhci-mtk 11200000.usb: xHCI Host Controller
10632 00:58:10.733706 <6>[ 2.913849] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10633 00:58:10.744369 <6>[ 2.921713] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10634 00:58:10.750835 <6>[ 2.931143] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10635 00:58:10.757335 <6>[ 2.937327] xhci-mtk 11200000.usb: xHCI Host Controller
10636 00:58:10.763604 <6>[ 2.942830] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10637 00:58:10.770351 <6>[ 2.950484] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10638 00:58:10.777828 <6>[ 2.958438] hub 1-0:1.0: USB hub found
10639 00:58:10.781060 <6>[ 2.962459] hub 1-0:1.0: 1 port detected
10640 00:58:10.790829 <6>[ 2.966762] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10641 00:58:10.794324 <6>[ 2.975579] hub 2-0:1.0: USB hub found
10642 00:58:10.797511 <6>[ 2.979606] hub 2-0:1.0: 1 port detected
10643 00:58:10.806426 <6>[ 2.987349] mtk-msdc 11f70000.mmc: Got CD GPIO
10644 00:58:10.819901 <6>[ 2.997429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10645 00:58:10.826348 <6>[ 3.005460] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10646 00:58:10.836474 <4>[ 3.013370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10647 00:58:10.846188 <6>[ 3.022941] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10648 00:58:10.853200 <6>[ 3.031018] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10649 00:58:10.859658 <6>[ 3.039031] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10650 00:58:10.869466 <6>[ 3.046954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10651 00:58:10.876519 <6>[ 3.054771] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10652 00:58:10.886123 <6>[ 3.062589] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10653 00:58:10.895994 <6>[ 3.072980] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10654 00:58:10.902855 <6>[ 3.081344] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10655 00:58:10.912535 <6>[ 3.089693] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10656 00:58:10.919308 <6>[ 3.098031] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10657 00:58:10.928810 <6>[ 3.106370] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10658 00:58:10.935505 <6>[ 3.114709] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10659 00:58:10.945229 <6>[ 3.123046] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10660 00:58:10.955591 <6>[ 3.131385] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10661 00:58:10.961755 <6>[ 3.139723] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10662 00:58:10.971843 <6>[ 3.148061] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10663 00:58:10.978340 <6>[ 3.156400] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10664 00:58:10.988657 <6>[ 3.164739] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10665 00:58:10.995239 <6>[ 3.173077] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10666 00:58:11.005109 <6>[ 3.181417] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10667 00:58:11.011521 <6>[ 3.189756] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10668 00:58:11.018356 <6>[ 3.198497] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10669 00:58:11.024638 <6>[ 3.205643] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10670 00:58:11.031589 <6>[ 3.212394] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10671 00:58:11.041872 <6>[ 3.219163] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10672 00:58:11.047784 <6>[ 3.226091] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10673 00:58:11.055007 <6>[ 3.232947] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10674 00:58:11.064528 <6>[ 3.242083] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10675 00:58:11.074788 <6>[ 3.251205] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10676 00:58:11.084718 <6>[ 3.260500] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10677 00:58:11.094778 <6>[ 3.269966] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10678 00:58:11.104113 <6>[ 3.279433] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10679 00:58:11.110810 <6>[ 3.288553] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10680 00:58:11.120887 <6>[ 3.298020] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10681 00:58:11.130876 <6>[ 3.307138] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10682 00:58:11.140624 <6>[ 3.316432] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10683 00:58:11.150295 <6>[ 3.326592] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10684 00:58:11.160975 <6>[ 3.338419] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10685 00:58:11.213175 <6>[ 3.390683] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10686 00:58:11.367608 <6>[ 3.548757] hub 1-1:1.0: USB hub found
10687 00:58:11.371120 <6>[ 3.553298] hub 1-1:1.0: 4 ports detected
10688 00:58:11.380310 <6>[ 3.561629] hub 1-1:1.0: USB hub found
10689 00:58:11.383762 <6>[ 3.565969] hub 1-1:1.0: 4 ports detected
10690 00:58:11.493214 <6>[ 3.671027] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10691 00:58:11.519334 <6>[ 3.700367] hub 2-1:1.0: USB hub found
10692 00:58:11.522821 <6>[ 3.704896] hub 2-1:1.0: 3 ports detected
10693 00:58:11.532207 <6>[ 3.712950] hub 2-1:1.0: USB hub found
10694 00:58:11.535148 <6>[ 3.717435] hub 2-1:1.0: 3 ports detected
10695 00:58:11.708853 <6>[ 3.886727] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10696 00:58:11.841636 <6>[ 4.022601] hub 1-1.4:1.0: USB hub found
10697 00:58:11.845266 <6>[ 4.027258] hub 1-1.4:1.0: 2 ports detected
10698 00:58:11.854194 <6>[ 4.035095] hub 1-1.4:1.0: USB hub found
10699 00:58:11.857055 <6>[ 4.039690] hub 1-1.4:1.0: 2 ports detected
10700 00:58:11.921107 <6>[ 4.098908] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10701 00:58:12.152604 <6>[ 4.330726] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10702 00:58:12.345313 <6>[ 4.522722] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10703 00:58:23.446068 <6>[ 15.631685] ALSA device list:
10704 00:58:23.452842 <6>[ 15.634981] No soundcards found.
10705 00:58:23.460886 <6>[ 15.642946] Freeing unused kernel memory: 8448K
10706 00:58:23.463873 <6>[ 15.647963] Run /init as init process
10707 00:58:23.512467 <6>[ 15.694643] NET: Registered PF_INET6 protocol family
10708 00:58:23.518986 <6>[ 15.700925] Segment Routing with IPv6
10709 00:58:23.522418 <6>[ 15.704875] In-situ OAM (IOAM) with IPv6
10710 00:58:23.557222 <30>[ 15.719311] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10711 00:58:23.560246 <30>[ 15.743066] systemd[1]: Detected architecture arm64.
10712 00:58:23.560824
10713 00:58:23.566714 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10714 00:58:23.567239
10715 00:58:23.580569 <30>[ 15.762619] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10716 00:58:23.766094 <30>[ 15.945187] systemd[1]: Queued start job for default target Graphical Interface.
10717 00:58:23.785117 <30>[ 15.967586] systemd[1]: Created slice system-getty.slice.
10718 00:58:23.792059 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10719 00:58:23.812928 <30>[ 15.995239] systemd[1]: Created slice system-modprobe.slice.
10720 00:58:23.819454 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10721 00:58:23.837562 <30>[ 16.019675] systemd[1]: Created slice system-serial\x2dgetty.slice.
10722 00:58:23.847590 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10723 00:58:23.861667 <30>[ 16.044133] systemd[1]: Created slice User and Session Slice.
10724 00:58:23.868152 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10725 00:58:23.887725 <30>[ 16.066757] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10726 00:58:23.897602 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10727 00:58:23.911855 <30>[ 16.090698] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10728 00:58:23.918318 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10729 00:58:23.939113 <30>[ 16.114780] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10730 00:58:23.945345 <30>[ 16.126894] systemd[1]: Reached target Local Encrypted Volumes.
10731 00:58:23.952393 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10732 00:58:23.968970 <30>[ 16.151101] systemd[1]: Reached target Paths.
10733 00:58:23.975273 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10734 00:58:23.988398 <30>[ 16.170727] systemd[1]: Reached target Remote File Systems.
10735 00:58:23.995227 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10736 00:58:24.012863 <30>[ 16.195061] systemd[1]: Reached target Slices.
10737 00:58:24.019229 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10738 00:58:24.032625 <30>[ 16.214740] systemd[1]: Reached target Swap.
10739 00:58:24.035661 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10740 00:58:24.055995 <30>[ 16.235206] systemd[1]: Listening on initctl Compatibility Named Pipe.
10741 00:58:24.062865 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10742 00:58:24.069417 <30>[ 16.250518] systemd[1]: Listening on Journal Audit Socket.
10743 00:58:24.076039 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10744 00:58:24.089096 <30>[ 16.271196] systemd[1]: Listening on Journal Socket (/dev/log).
10745 00:58:24.095467 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10746 00:58:24.113626 <30>[ 16.295934] systemd[1]: Listening on Journal Socket.
10747 00:58:24.120216 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10748 00:58:24.136636 <30>[ 16.315433] systemd[1]: Listening on Network Service Netlink Socket.
10749 00:58:24.142732 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10750 00:58:24.157093 <30>[ 16.339296] systemd[1]: Listening on udev Control Socket.
10751 00:58:24.163316 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10752 00:58:24.181057 <30>[ 16.363793] systemd[1]: Listening on udev Kernel Socket.
10753 00:58:24.188400 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10754 00:58:24.244799 <30>[ 16.426951] systemd[1]: Mounting Huge Pages File System...
10755 00:58:24.251507 Mounting [0;1;39mHuge Pages File System[0m...
10756 00:58:24.266309 <30>[ 16.448748] systemd[1]: Mounting POSIX Message Queue File System...
10757 00:58:24.272864 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10758 00:58:24.290063 <30>[ 16.472626] systemd[1]: Mounting Kernel Debug File System...
10759 00:58:24.296996 Mounting [0;1;39mKernel Debug File System[0m...
10760 00:58:24.315850 <30>[ 16.494940] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10761 00:58:24.328142 <30>[ 16.507614] systemd[1]: Starting Create list of static device nodes for the current kernel...
10762 00:58:24.334974 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10763 00:58:24.356387 <30>[ 16.538891] systemd[1]: Starting Load Kernel Module configfs...
10764 00:58:24.362673 Starting [0;1;39mLoad Kernel Module configfs[0m...
10765 00:58:24.380824 <30>[ 16.563181] systemd[1]: Starting Load Kernel Module drm...
10766 00:58:24.387360 Starting [0;1;39mLoad Kernel Module drm[0m...
10767 00:58:24.404058 <30>[ 16.583185] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10768 00:58:24.418442 <30>[ 16.601052] systemd[1]: Starting Journal Service...
10769 00:58:24.421542 Starting [0;1;39mJournal Service[0m...
10770 00:58:24.445285 <30>[ 16.627840] systemd[1]: Starting Load Kernel Modules...
10771 00:58:24.451891 Starting [0;1;39mLoad Kernel Modules[0m...
10772 00:58:24.476081 <30>[ 16.655106] systemd[1]: Starting Remount Root and Kernel File Systems...
10773 00:58:24.482437 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10774 00:58:24.500600 <30>[ 16.683179] systemd[1]: Starting Coldplug All udev Devices...
10775 00:58:24.507196 Starting [0;1;39mColdplug All udev Devices[0m...
10776 00:58:24.523538 <30>[ 16.706277] systemd[1]: Started Journal Service.
10777 00:58:24.530338 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10778 00:58:24.550469 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10779 00:58:24.573245 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10780 00:58:24.589273 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10781 00:58:24.610065 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10782 00:58:24.626031 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10783 00:58:24.643261 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10784 00:58:24.662255 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10785 00:58:24.681998 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10786 00:58:24.695919 See 'systemctl status systemd-remount-fs.service' for details.
10787 00:58:24.748438 Mounting [0;1;39mKernel Configuration File System[0m...
10788 00:58:24.768590 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10789 00:58:24.789571 <46>[ 16.969015] systemd-journald[178]: Received client request to flush runtime journal.
10790 00:58:24.796142 Starting [0;1;39mLoad/Save Random Seed[0m...
10791 00:58:24.810902 Starting [0;1;39mApply Kernel Variables[0m...
10792 00:58:24.828734 Starting [0;1;39mCreate System Users[0m...
10793 00:58:24.847431 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10794 00:58:24.865104 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10795 00:58:24.884677 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10796 00:58:24.897685 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10797 00:58:24.913510 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10798 00:58:24.929647 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10799 00:58:24.976497 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10800 00:58:25.005787 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10801 00:58:25.020413 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10802 00:58:25.035931 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10803 00:58:25.092998 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10804 00:58:25.117268 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10805 00:58:25.137991 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10806 00:58:25.159117 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10807 00:58:25.210397 Starting [0;1;39mNetwork Service[0m...
10808 00:58:25.234420 Starting [0;1;39mNetwork Time Synchronization[0m...
10809 00:58:25.256416 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10810 00:58:25.306427 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10811 00:58:25.321611 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10812 00:58:25.337435 <6>[ 17.516431] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10813 00:58:25.344302 <6>[ 17.524060] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10814 00:58:25.353847 <6>[ 17.532942] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10815 00:58:25.367524 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbac<6>[ 17.547593] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10816 00:58:25.370184 klight.slice[0m.
10817 00:58:25.384356 <4>[ 17.563390] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10818 00:58:25.390987 <3>[ 17.565802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 00:58:25.397070 <6>[ 17.570778] remoteproc remoteproc0: scp is available
10820 00:58:25.403987 <3>[ 17.579004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 00:58:25.410317 <6>[ 17.584368] remoteproc remoteproc0: powering up scp
10822 00:58:25.416745 <3>[ 17.592240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10823 00:58:25.423333 <4>[ 17.595414] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10824 00:58:25.433224 <6>[ 17.597423] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10825 00:58:25.440028 <3>[ 17.607243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 00:58:25.446406 <6>[ 17.610772] mc: Linux media interface: v0.10
10827 00:58:25.453113 <6>[ 17.612893] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10828 00:58:25.459586 <3>[ 17.621383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 00:58:25.465944 <6>[ 17.635131] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10830 00:58:25.475885 <3>[ 17.639611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 00:58:25.482747 <3>[ 17.639622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 00:58:25.492353 <3>[ 17.639627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10833 00:58:25.498901 <3>[ 17.641213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10834 00:58:25.505354 <6>[ 17.651266] usbcore: registered new device driver r8152-cfgselector
10835 00:58:25.512140 <6>[ 17.651542] videodev: Linux video capture interface: v2.00
10836 00:58:25.522175 <6>[ 17.656635] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10837 00:58:25.531979 <3>[ 17.659736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 00:58:25.538796 <3>[ 17.659751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 00:58:25.545349 <3>[ 17.659756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 00:58:25.552315 <6>[ 17.673301] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10841 00:58:25.563120 <3>[ 17.673525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 00:58:25.569758 <3>[ 17.673541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 00:58:25.579406 <3>[ 17.673545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 00:58:25.585969 <3>[ 17.673549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 00:58:25.592768 <3>[ 17.673552] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 00:58:25.603062 <3>[ 17.674065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 00:58:25.609653 <6>[ 17.680422] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10848 00:58:25.620251 <4>[ 17.689174] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10849 00:58:25.626578 <4>[ 17.689174] Fallback method does not support PEC.
10850 00:58:25.629862 <6>[ 17.689201] pci_bus 0000:00: root bus resource [bus 00-ff]
10851 00:58:25.636459 <6>[ 17.689210] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10852 00:58:25.646651 <6>[ 17.689215] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10853 00:58:25.653584 <6>[ 17.689289] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10854 00:58:25.660776 <6>[ 17.689338] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10855 00:58:25.667400 <6>[ 17.689462] pci 0000:00:00.0: supports D1 D2
10856 00:58:25.674078 <6>[ 17.689467] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10857 00:58:25.680697 <6>[ 17.692413] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10858 00:58:25.687883 <6>[ 17.695267] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10859 00:58:25.697998 <6>[ 17.713462] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10860 00:58:25.704604 <6>[ 17.719275] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10861 00:58:25.711834 <3>[ 17.750102] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10862 00:58:25.721940 <3>[ 17.750887] power_supply sbs-5-000b: driver failed to report `status' property: -6
10863 00:58:25.728969 <6>[ 17.754874] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10864 00:58:25.735747 <6>[ 17.758190] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10865 00:58:25.742201 <6>[ 17.766178] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10866 00:58:25.748730 <6>[ 17.767101] Bluetooth: Core ver 2.22
10867 00:58:25.751940 <6>[ 17.767179] NET: Registered PF_BLUETOOTH protocol family
10868 00:58:25.758519 <6>[ 17.767182] Bluetooth: HCI device and connection manager initialized
10869 00:58:25.766151 <6>[ 17.767209] Bluetooth: HCI socket layer initialized
10870 00:58:25.769433 <6>[ 17.767215] Bluetooth: L2CAP socket layer initialized
10871 00:58:25.776361 <6>[ 17.767227] Bluetooth: SCO socket layer initialized
10872 00:58:25.782657 <6>[ 17.774694] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10873 00:58:25.793027 <6>[ 17.777359] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10874 00:58:25.799852 <6>[ 17.779154] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10875 00:58:25.806747 <6>[ 17.782636] remoteproc remoteproc0: remote processor scp is now up
10876 00:58:25.813613 <6>[ 17.782926] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10877 00:58:25.820299 <6>[ 17.783533] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10878 00:58:25.834300 <6>[ 17.784834] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10879 00:58:25.841241 <6>[ 17.785000] usbcore: registered new interface driver uvcvideo
10880 00:58:25.844329 <6>[ 17.791222] pci 0000:01:00.0: supports D1 D2
10881 00:58:25.851180 <3>[ 17.805088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 00:58:25.861540 <4>[ 17.805743] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10883 00:58:25.871425 <4>[ 17.805752] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10884 00:58:25.878049 <3>[ 17.805903] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10885 00:58:25.884520 <6>[ 17.813299] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10886 00:58:25.891168 <6>[ 17.827077] usbcore: registered new interface driver btusb
10887 00:58:25.897996 <6>[ 17.827238] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10888 00:58:25.907724 <4>[ 17.827871] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10889 00:58:25.914122 <3>[ 17.827882] Bluetooth: hci0: Failed to load firmware file (-2)
10890 00:58:25.920914 <3>[ 17.827891] Bluetooth: hci0: Failed to set up firmware (-2)
10891 00:58:25.930735 <4>[ 17.827897] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10892 00:58:25.937665 <6>[ 17.846557] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10893 00:58:25.947120 <3>[ 17.850641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 00:58:25.950514 <6>[ 17.850733] r8152 2-1.3:1.0 eth0: v1.12.13
10895 00:58:25.957254 <6>[ 17.850897] usbcore: registered new interface driver r8152
10896 00:58:25.964026 <3>[ 17.851393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10897 00:58:25.973897 <6>[ 17.854344] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10898 00:58:25.976994 <6>[ 17.869698] usbcore: registered new interface driver cdc_ether
10899 00:58:25.987004 <6>[ 17.875656] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10900 00:58:25.993662 <6>[ 17.875667] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10901 00:58:26.003749 <3>[ 17.876618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 00:58:26.010334 <6>[ 17.892673] usbcore: registered new interface driver r8153_ecm
10903 00:58:26.016954 <3>[ 17.897883] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 00:58:26.026797 <6>[ 17.901230] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10905 00:58:26.036556 <3>[ 17.918030] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 00:58:26.043894 <6>[ 17.923546] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10907 00:58:26.050003 <6>[ 17.925621] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10908 00:58:26.056751 <3>[ 17.953502] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 00:58:26.063530 <6>[ 17.958469] pci 0000:00:00.0: PCI bridge to [bus 01]
10910 00:58:26.070058 <6>[ 18.251358] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10911 00:58:26.076632 <6>[ 18.251517] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10912 00:58:26.086696 [[0;32m OK [<6>[ 18.266345] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10913 00:58:26.093293 0m] Reached targ<6>[ 18.274058] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10914 00:58:26.096600 et [0;1;39mSystem Time Set[0m.
10915 00:58:26.113657 <5>[ 18.293150] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10916 00:58:26.120611 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10917 00:58:26.133960 <5>[ 18.312990] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10918 00:58:26.140340 <5>[ 18.320436] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10919 00:58:26.150167 <4>[ 18.328943] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10920 00:58:26.156772 <6>[ 18.337940] cfg80211: failed to load regulatory.db
10921 00:58:26.200849 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd<6>[ 18.381866] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10922 00:58:26.210672 _backlight[0m..<6>[ 18.389979] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10923 00:58:26.211196 .
10924 00:58:26.235353 Starting [0;1;39mNetwork Name Resoluti<6>[ 18.418044] mt7921e 0000:01:00.0: ASIC revision: 79610010
10925 00:58:26.238615 on[0m...
10926 00:58:26.258751 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10927 00:58:26.279679 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10928 00:58:26.297110 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10929 00:58:26.340187 <6>[ 18.519385] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10930 00:58:26.343546 <6>[ 18.519385]
10931 00:58:26.349939 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10932 00:58:26.496592 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10933 00:58:26.512083 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10934 00:58:26.531149 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10935 00:58:26.547963 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10936 00:58:26.568082 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10937 00:58:26.583313 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10938 00:58:26.596075 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10939 00:58:26.608492 <6>[ 18.787819] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10940 00:58:26.615081 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10941 00:58:26.632347 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10942 00:58:26.648372 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10943 00:58:26.668071 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10944 00:58:26.700895 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10945 00:58:26.733509 Starting [0;1;39mUser Login Management[0m...
10946 00:58:26.752250 Starting [0;1;39mPermit User Sessions[0m...
10947 00:58:26.774955 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10948 00:58:26.793676 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10949 00:58:26.813904 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10950 00:58:26.830117 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10951 00:58:26.889688 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10952 00:58:26.907091 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10953 00:58:26.924670 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10954 00:58:26.940251 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10955 00:58:26.955994 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10956 00:58:27.002058 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10957 00:58:27.041301 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10958 00:58:27.093535
10959 00:58:27.094059
10960 00:58:27.096495 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10961 00:58:27.096914
10962 00:58:27.099765 debian-bullseye-arm64 login: root (automatic login)
10963 00:58:27.100189
10964 00:58:27.100525
10965 00:58:27.115798 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Fri Jan 19 00:37:44 UTC 2024 aarch64
10966 00:58:27.116333
10967 00:58:27.122420 The programs included with the Debian GNU/Linux system are free software;
10968 00:58:27.129145 the exact distribution terms for each program are described in the
10969 00:58:27.132367 individual files in /usr/share/doc/*/copyright.
10970 00:58:27.132892
10971 00:58:27.138453 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10972 00:58:27.142017 permitted by applicable law.
10973 00:58:27.143353 Matched prompt #10: / #
10975 00:58:27.144344 Setting prompt string to ['/ #']
10976 00:58:27.144777 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10978 00:58:27.145795 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10979 00:58:27.146237 start: 2.2.6 expect-shell-connection (timeout 00:02:57) [common]
10980 00:58:27.146596 Setting prompt string to ['/ #']
10981 00:58:27.146908 Forcing a shell prompt, looking for ['/ #']
10983 00:58:27.197796 / #
10984 00:58:27.198395 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10985 00:58:27.198818 Waiting using forced prompt support (timeout 00:02:30)
10986 00:58:27.203851
10987 00:58:27.204736 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10988 00:58:27.205226 start: 2.2.7 export-device-env (timeout 00:02:57) [common]
10989 00:58:27.205725 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10990 00:58:27.206161 end: 2.2 depthcharge-retry (duration 00:02:03) [common]
10991 00:58:27.206590 end: 2 depthcharge-action (duration 00:02:03) [common]
10992 00:58:27.207016 start: 3 lava-test-retry (timeout 00:07:37) [common]
10993 00:58:27.207427 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
10994 00:58:27.207792 Using namespace: common
10996 00:58:27.308962 / # #
10997 00:58:27.309753 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10998 00:58:27.310345 <6>[ 19.425391] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
10999 00:58:27.310696 <6>[ 19.433437] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11000 00:58:27.315198 #
11001 00:58:27.316037 Using /lava-12571064
11003 00:58:27.417295 / # export SHELL=/bin/sh
11004 00:58:27.424010 export SHELL=/bin/sh
11006 00:58:27.525728 / # . /lava-12571064/environment
11007 00:58:27.526503 <6>[ 19.643179] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11008 00:58:27.531873 . /lava-12571064/environment
11010 00:58:27.633559 / # /lava-12571064/bin/lava-test-runner /lava-12571064/0
11011 00:58:27.634246 Test shell timeout: 10s (minimum of the action and connection timeout)
11012 00:58:27.640283 /lava-12571064/bin/lava-test-runner /lava-12571064/0
11013 00:58:27.662767 + export TESTRUN_ID=0_v4l2-compliance-uvc
11014 00:58:27.665978 + cd /lava-12571064/0/tests/0_v4l2-compliance-uvc
11015 00:58:27.666508 + cat uuid
11016 00:58:27.669371 + UUID=12571064_1.5.2.3.1
11017 00:58:27.669928 + set +x
11018 00:58:27.675978 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12571064_1.5.2.3.1>
11019 00:58:27.676789 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12571064_1.5.2.3.1
11020 00:58:27.677166 Starting test lava.0_v4l2-compliance-uvc (12571064_1.5.2.3.1)
11021 00:58:27.677648 Skipping test definition patterns.
11022 00:58:27.679046 + /usr/bin/v4l2-parser.sh -d uvcvideo
11023 00:58:27.685454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11024 00:58:27.686090 device: /dev/video0
11025 00:58:27.686700 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11027 00:58:34.175103 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11028 00:58:34.187596 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11029 00:58:34.196042
11030 00:58:34.214071 Compliance test for uvcvideo device /dev/video0:
11031 00:58:34.222369
11032 00:58:34.235107 Driver Info:
11033 00:58:34.246251 Driver name : uvcvideo
11034 00:58:34.263613 Card type : HD User Facing: HD User Facing
11035 00:58:34.278880 Bus info : usb-11200000.usb-1.4.1
11036 00:58:34.285961 Driver version : 6.1.72
11037 00:58:34.300188 Capabilities : 0x84a00001
11038 00:58:34.315482 Metadata Capture
11039 00:58:34.328526 Streaming
11040 00:58:34.339354 Extended Pix Format
11041 00:58:34.349524 Device Capabilities
11042 00:58:34.358943 Device Caps : 0x04200001
11043 00:58:34.376169 Streaming
11044 00:58:34.385619 Extended Pix Format
11045 00:58:34.400943 Media Driver Info:
11046 00:58:34.412092 Driver name : uvcvideo
11047 00:58:34.426134 Model : HD User Facing: HD User Facing
11048 00:58:34.433724 Serial : 200901010001
11049 00:58:34.446670 Bus info : usb-11200000.usb-1.4.1
11050 00:58:34.454368 Media version : 6.1.72
11051 00:58:34.467279 Hardware revision: 0x00009758 (38744)
11052 00:58:34.475654 Driver version : 6.1.72
11053 00:58:34.488542 Interface Info:
11054 00:58:34.504728 <LAVA_SIGNAL_TESTSET START Interface-Info>
11055 00:58:34.505261 ID : 0x03000002
11056 00:58:34.505937 Received signal: <TESTSET> START Interface-Info
11057 00:58:34.506332 Starting test_set Interface-Info
11058 00:58:34.515151 Type : V4L Video
11059 00:58:34.526690 Entity Info:
11060 00:58:34.534380 <LAVA_SIGNAL_TESTSET STOP>
11061 00:58:34.535161 Received signal: <TESTSET> STOP
11062 00:58:34.535533 Closing test_set Interface-Info
11063 00:58:34.544067 <LAVA_SIGNAL_TESTSET START Entity-Info>
11064 00:58:34.544845 Received signal: <TESTSET> START Entity-Info
11065 00:58:34.545205 Starting test_set Entity-Info
11066 00:58:34.547390 ID : 0x00000001 (1)
11067 00:58:34.557173 Name : HD User Facing: HD User Facing
11068 00:58:34.566347 Function : V4L2 I/O
11069 00:58:34.577406 Flags : default
11070 00:58:34.589225 Pad 0x01000007 : 0: Sink
11071 00:58:34.613526 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11072 00:58:34.614071
11073 00:58:34.626614 Required ioctls:
11074 00:58:34.634072 <LAVA_SIGNAL_TESTSET STOP>
11075 00:58:34.634871 Received signal: <TESTSET> STOP
11076 00:58:34.635228 Closing test_set Entity-Info
11077 00:58:34.643789 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11078 00:58:34.644584 Received signal: <TESTSET> START Required-ioctls
11079 00:58:34.644961 Starting test_set Required-ioctls
11080 00:58:34.647377 test MC information (see 'Media Driver Info' above): OK
11081 00:58:34.674032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11082 00:58:34.674836 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11084 00:58:34.676878 test VIDIOC_QUERYCAP: OK
11085 00:58:34.694964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11086 00:58:34.695764 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11088 00:58:34.697858 test invalid ioctls: OK
11089 00:58:34.724770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11090 00:58:34.725305
11091 00:58:34.725970 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11093 00:58:34.737133 Allow for multiple opens:
11094 00:58:34.749210 <LAVA_SIGNAL_TESTSET STOP>
11095 00:58:34.750058 Received signal: <TESTSET> STOP
11096 00:58:34.750421 Closing test_set Required-ioctls
11097 00:58:34.758389 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11098 00:58:34.759185 Received signal: <TESTSET> START Allow-for-multiple-opens
11099 00:58:34.759545 Starting test_set Allow-for-multiple-opens
11100 00:58:34.761616 test second /dev/video0 open: OK
11101 00:58:34.784633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11102 00:58:34.785425 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11104 00:58:34.788035 test VIDIOC_QUERYCAP: OK
11105 00:58:34.813665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11106 00:58:34.814516 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11108 00:58:34.816816 test VIDIOC_G/S_PRIORITY: OK
11109 00:58:34.844799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11110 00:58:34.845607 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11112 00:58:34.848195 test for unlimited opens: OK
11113 00:58:34.870431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11114 00:58:34.870966
11115 00:58:34.871568 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11117 00:58:34.882165 Debug ioctls:
11118 00:58:34.889638 <LAVA_SIGNAL_TESTSET STOP>
11119 00:58:34.890431 Received signal: <TESTSET> STOP
11120 00:58:34.890796 Closing test_set Allow-for-multiple-opens
11121 00:58:34.900194 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11122 00:58:34.901014 Received signal: <TESTSET> START Debug-ioctls
11123 00:58:34.901381 Starting test_set Debug-ioctls
11124 00:58:34.903226 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11125 00:58:34.931822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11126 00:58:34.932623 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11128 00:58:34.938467 test VIDIOC_LOG_STATUS: OK (Not Supported)
11129 00:58:34.958006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11130 00:58:34.958506
11131 00:58:34.959097 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11133 00:58:34.972918 Input ioctls:
11134 00:58:34.979744 <LAVA_SIGNAL_TESTSET STOP>
11135 00:58:34.980421 Received signal: <TESTSET> STOP
11136 00:58:34.980774 Closing test_set Debug-ioctls
11137 00:58:34.990076 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11138 00:58:34.990856 Received signal: <TESTSET> START Input-ioctls
11139 00:58:34.991216 Starting test_set Input-ioctls
11140 00:58:34.992792 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11141 00:58:35.018216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11142 00:58:35.019071 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11144 00:58:35.021574 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11145 00:58:35.042062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11146 00:58:35.042845 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11148 00:58:35.048514 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11149 00:58:35.067407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11150 00:58:35.068189 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11152 00:58:35.070437 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11153 00:58:35.092984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11154 00:58:35.093835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11156 00:58:35.096173 test VIDIOC_G/S/ENUMINPUT: OK
11157 00:58:35.119042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11158 00:58:35.119844 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11160 00:58:35.122141 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11161 00:58:35.149177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11162 00:58:35.149986 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11164 00:58:35.152604 Inputs: 1 Audio Inputs: 0 Tuners: 0
11165 00:58:35.158970
11166 00:58:35.176289 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11167 00:58:35.203512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11168 00:58:35.204358 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11170 00:58:35.210159 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11171 00:58:35.229648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11172 00:58:35.230347 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11174 00:58:35.235898 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11175 00:58:35.255391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11176 00:58:35.256217 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11178 00:58:35.261764 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11179 00:58:35.284957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11180 00:58:35.285792 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11182 00:58:35.291322 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11183 00:58:35.307865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11184 00:58:35.308394
11185 00:58:35.309053 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11187 00:58:35.331457 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11188 00:58:35.353568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11189 00:58:35.354356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11191 00:58:35.359817 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11192 00:58:35.381632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11193 00:58:35.382551 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11195 00:58:35.384759 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11196 00:58:35.402968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11197 00:58:35.403820 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11199 00:58:35.406212 test VIDIOC_G/S_EDID: OK (Not Supported)
11200 00:58:35.429672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11201 00:58:35.430209
11202 00:58:35.430820 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11204 00:58:35.440888 Control ioctls (Input 0):
11205 00:58:35.448123 <LAVA_SIGNAL_TESTSET STOP>
11206 00:58:35.448953 Received signal: <TESTSET> STOP
11207 00:58:35.449321 Closing test_set Input-ioctls
11208 00:58:35.457873 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11209 00:58:35.458673 Received signal: <TESTSET> START Control-ioctls-Input-0
11210 00:58:35.459034 Starting test_set Control-ioctls-Input-0
11211 00:58:35.460963 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11212 00:58:35.486863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11213 00:58:35.487397 test VIDIOC_QUERYCTRL: OK
11214 00:58:35.488003 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11216 00:58:35.508633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11217 00:58:35.509426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11219 00:58:35.511596 test VIDIOC_G/S_CTRL: OK
11220 00:58:35.537174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11221 00:58:35.538004 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11223 00:58:35.540356 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11224 00:58:35.562276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11225 00:58:35.563064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11227 00:58:35.568849 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11228 00:58:35.590803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11229 00:58:35.591583 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11231 00:58:35.593859 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11232 00:58:35.619696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11233 00:58:35.620518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11235 00:58:35.622638 Standard Controls: 16 Private Controls: 0
11236 00:58:35.631134
11237 00:58:35.642236 Format ioctls (Input 0):
11238 00:58:35.654161 <LAVA_SIGNAL_TESTSET STOP>
11239 00:58:35.654950 Received signal: <TESTSET> STOP
11240 00:58:35.655304 Closing test_set Control-ioctls-Input-0
11241 00:58:35.664244 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11242 00:58:35.665051 Received signal: <TESTSET> START Format-ioctls-Input-0
11243 00:58:35.665435 Starting test_set Format-ioctls-Input-0
11244 00:58:35.667339 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11245 00:58:35.693019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11246 00:58:35.693970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11248 00:58:35.695883 test VIDIOC_G/S_PARM: OK
11249 00:58:35.716109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11250 00:58:35.716903 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11252 00:58:35.719652 test VIDIOC_G_FBUF: OK (Not Supported)
11253 00:58:35.742187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11254 00:58:35.742982 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11256 00:58:35.745383 test VIDIOC_G_FMT: OK
11257 00:58:35.767067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11258 00:58:35.767855 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11260 00:58:35.770150 test VIDIOC_TRY_FMT: OK
11261 00:58:35.792835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11262 00:58:35.793657 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11264 00:58:35.799709 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11265 00:58:35.803644 test VIDIOC_S_FMT: OK
11266 00:58:35.828891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11267 00:58:35.829682 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11269 00:58:35.832080 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11270 00:58:35.859079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11271 00:58:35.859922 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11273 00:58:35.862241 test Cropping: OK (Not Supported)
11274 00:58:35.885402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11275 00:58:35.886293 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11277 00:58:35.888657 test Composing: OK (Not Supported)
11278 00:58:35.913215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11279 00:58:35.914093 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11281 00:58:35.916327 test Scaling: OK (Not Supported)
11282 00:58:35.939385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11283 00:58:35.939908
11284 00:58:35.940509 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11286 00:58:35.950236 Codec ioctls (Input 0):
11287 00:58:35.957336 <LAVA_SIGNAL_TESTSET STOP>
11288 00:58:35.958159 Received signal: <TESTSET> STOP
11289 00:58:35.958512 Closing test_set Format-ioctls-Input-0
11290 00:58:35.967369 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11291 00:58:35.968155 Received signal: <TESTSET> START Codec-ioctls-Input-0
11292 00:58:35.968519 Starting test_set Codec-ioctls-Input-0
11293 00:58:35.970185 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11294 00:58:35.992639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11295 00:58:35.993426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11297 00:58:35.998829 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11298 00:58:36.016910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11299 00:58:36.017700 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11301 00:58:36.023251 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11302 00:58:36.043853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11303 00:58:36.044383
11304 00:58:36.045010 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11306 00:58:36.055332 Buffer ioctls (Input 0):
11307 00:58:36.062253 <LAVA_SIGNAL_TESTSET STOP>
11308 00:58:36.063040 Received signal: <TESTSET> STOP
11309 00:58:36.063410 Closing test_set Codec-ioctls-Input-0
11310 00:58:36.071535 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11311 00:58:36.072325 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11312 00:58:36.072691 Starting test_set Buffer-ioctls-Input-0
11313 00:58:36.074780 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11314 00:58:36.101065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11315 00:58:36.101620 test VIDIOC_EXPBUF: OK
11316 00:58:36.102225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11318 00:58:36.123701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11319 00:58:36.124499 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11321 00:58:36.126873 test Requests: OK (Not Supported)
11322 00:58:36.155404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11323 00:58:36.155929
11324 00:58:36.156531 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11326 00:58:36.166880 Test input 0:
11327 00:58:36.176776
11328 00:58:36.188193 Streaming ioctls:
11329 00:58:36.194342 <LAVA_SIGNAL_TESTSET STOP>
11330 00:58:36.195135 Received signal: <TESTSET> STOP
11331 00:58:36.195493 Closing test_set Buffer-ioctls-Input-0
11332 00:58:36.203634 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11333 00:58:36.204433 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11334 00:58:36.204807 Starting test_set Streaming-ioctls_Test-input-0
11335 00:58:36.207158 test read/write: OK (Not Supported)
11336 00:58:36.228822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11337 00:58:36.229603 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11339 00:58:36.232084 test blocking wait: OK
11340 00:58:36.253897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11341 00:58:36.254664 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11343 00:58:36.264013 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11344 00:58:36.267237 test MMAP (no poll): FAIL
11345 00:58:36.291677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11346 00:58:36.292367 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11348 00:58:36.301768 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11349 00:58:36.302320 test MMAP (select): FAIL
11350 00:58:36.328965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11351 00:58:36.329653 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11353 00:58:36.338905 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11354 00:58:36.339440 test MMAP (epoll): FAIL
11355 00:58:36.364766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11356 00:58:36.365304
11357 00:58:36.365955 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11359 00:58:36.377099
11360 00:58:36.565120
11361 00:58:36.576899 test USERPTR (no poll): OK
11362 00:58:36.603512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11363 00:58:36.604044
11364 00:58:36.604646 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11366 00:58:36.617989
11367 00:58:36.808950
11368 00:58:36.822049 test USERPTR (select): OK
11369 00:58:36.853180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11370 00:58:36.854024 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11372 00:58:36.859590 test DMABUF: Cannot test, specify --expbuf-device
11373 00:58:36.863965
11374 00:58:36.880369 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11375 00:58:36.883903 <LAVA_TEST_RUNNER EXIT>
11376 00:58:36.884711 ok: lava_test_shell seems to have completed
11377 00:58:36.885095 Marking unfinished test run as failed
11379 00:58:36.890209 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11380 00:58:36.890831 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11381 00:58:36.891266 end: 3 lava-test-retry (duration 00:00:10) [common]
11382 00:58:36.891713 start: 4 finalize (timeout 00:07:27) [common]
11383 00:58:36.892164 start: 4.1 power-off (timeout 00:00:30) [common]
11384 00:58:36.892887 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11385 00:58:36.978335 >> Command sent successfully.
11386 00:58:36.982943 Returned 0 in 0 seconds
11387 00:58:37.083896 end: 4.1 power-off (duration 00:00:00) [common]
11389 00:58:37.085268 start: 4.2 read-feedback (timeout 00:07:27) [common]
11390 00:58:37.086575 Listened to connection for namespace 'common' for up to 1s
11391 00:58:38.087239 Finalising connection for namespace 'common'
11392 00:58:38.087858 Disconnecting from shell: Finalise
11393 00:58:38.088260 / #
11394 00:58:38.189251 end: 4.2 read-feedback (duration 00:00:01) [common]
11395 00:58:38.189975 end: 4 finalize (duration 00:00:01) [common]
11396 00:58:38.190518 Cleaning after the job
11397 00:58:38.190997 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/ramdisk
11398 00:58:38.216026 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/kernel
11399 00:58:38.250408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/dtb
11400 00:58:38.250666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12571064/tftp-deploy-w3kw8ada/modules
11401 00:58:38.259480 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12571064
11402 00:58:38.325799 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12571064
11403 00:58:38.325978 Job finished correctly