[Enter `^Ec?' for help] coreboot-v1.9308_26_0.0.22-27049-gc173a2e938 Wed Sep 6 23:44:51 UTC 2023 bootblock starting (log level: 8)... CPU: Intel(R) Celeron(R) 7305 CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423 CPU: AES supported, TXT NOT supported, VT supported Cache: Level 3: Associativity = 8 Partitions = 1 Line Size = 64 Sets = 16384 Cache size = 8 MiB MCH: device id 4619 (rev 04) is Alderlake-P PCH: device id 5182 (rev 01) is Raptorlake-P SKU IGD: device id 46b3 (rev 0c) is Alderlake P GT2 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 37 FMAP: area COREBOOT found @ 1875000 (7909376 bytes) CBFS: mcache @0xfef85600 built for 73 files, used 0x1000 of 0x2000 bytes CBFS: Found 'fallback/verstage' @0x18bf40 size 0x164a8 in mcache @0xfef85908 coreboot-v1.9308_26_0.0.22-27049-gc173a2e938 Wed Sep 6 23:44:51 UTC 2023 verstage starting (log level: 8)... Probing TPM I2C: I2C bus 1 version 0x3230302a DW I2C bus 1 at 0xfe022000 (400 KHz) I2C TX abort detected (00000001) cr50_i2c_read: Address write failed .done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.141/cr50_v2.9 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Reading cr50 boot mode Cr50 says boot_mode is VERIFIED_RW(0x00). Phase 1 FMAP: area GBB found @ 1805000 (458752 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 1805000 (458752 bytes) FMAP: area VBLOCK_B found @ 1000000 (65536 bytes) FMAP: area VBLOCK_B found @ 1000000 (65536 bytes) VB2:vb2_verify_keyblock() Checking keyblock signature... VB2:vb2_verify_data() HW crypto for hash_alg 3 not supported, using SW VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported, using SW FMAP: area VBLOCK_B found @ 1000000 (65536 bytes) FMAP: area VBLOCK_B found @ 1000000 (65536 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_verify_data() Using HW crypto engine for hash_alg 2 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW Phase 4 FMAP: area FW_MAIN_B found @ 1010000 (5242816 bytes) VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW Saving vboot hash. TPM: Extending digest for `VBOOT: boot mode` into PCR 0 tlcl_extend: response is 0 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1 tlcl_extend: response is 0 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured tlcl_lock_nv_write: response is 0 tlcl_lock_nv_write: response is 0 Slot B is selected FMAP: area FW_MAIN_B found @ 1010000 (5242816 bytes) CBFS: mcache @0xfef87600 built for 23 files, used 0x464 of 0x2000 bytes CBFS: Found 'fallback/romstage' @0x0 size 0x1e2e0 in mcache @0xfef87600 BS: verstage times (exec / console): total (unknown) / 267 ms coreboot-v1.9308_26_0.0.22-27049-gc173a2e938 Wed Sep 6 23:44:51 UTC 2023 romstage starting (log level: 8)... Google Chrome EC: version: ro: moli_v2.0.19454-8a70cbdcf0 rw: moli_v2.0.22464-d4ba27cabb running image: 2 FMAP: area FW_MAIN_B found @ 1010000 (5242816 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'ecrw.hash' @0x1e0200 size 0x20 in mcache @0xfef879bc VB2:check_ec_hash() Hexp RW(active): 4b5e9cf392d67cb44ef3fdfc435e56e521eb3b13299fd09abf8f0e82d1d7976d VB2:check_ec_hash() Hmir: 4b5e9cf392d67cb44ef3fdfc435e56e521eb3b13299fd09abf8f0e82d1d7976d EC took 943us to calculate image hash VB2:check_ec_hash() Heff RW(active): 4b5e9cf392d67cb44ef3fdfc435e56e521eb3b13299fd09abf8f0e82d1d7976d VB2:sync_ec() select_rw=RW(active) EC returned error result code 1 PARAM_LIMIT_POWER not supported by EC. Waited 7383us to clear limit power flag. pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00040000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00082000 TCO_STS: 0000 0000 GEN_PMCON: d0015038 00002200 GBLRST_CAUSE: 00000000 00000000 HPR_CAUSE0: 00000000 prev_sleep_state 5 Abort disabling TXT, as CPU is not TXT capable. cse_lite: Number of partitions = 3 cse_lite: Current partition = RO cse_lite: Next partition = RO cse_lite: Flags = 0x7 cse_lite: RO version = 16.1.25.2049 (Status=0x0, Start=0x2000, End=0x19bfff) cse_lite: RW version = 16.1.25.2049 (Status=0x0, Start=0x205000, End=0x439fff) FMAP: area SI_ME found @ 1000 (5238784 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 cse_lite: CSE RW partition: offset = 0x205000, size = 0x235000 CBFS: Found 'me_rw.version' @0x7eec0 size 0xd in mcache @0xfef877f4 cse_lite: CSE CBFS RW version : 16.1.25.2049 CSE Sub-partition update not required cse_lite: Set Boot Partition Info Command (RW) HECI: Global Reset(Type:1) Command