Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 01:14:12.871394 lava-dispatcher, installed at version: 2024.01
2 01:14:12.871596 start: 0 validate
3 01:14:12.871723 Start time: 2024-04-23 01:14:12.871714+00:00 (UTC)
4 01:14:12.871841 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:14:12.871962 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:14:13.129641 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:14:13.130385 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:14:13.388366 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:14:13.389067 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:14:13.646582 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:14:13.647430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:14:14.151723 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:14:14.152467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:14:14.418998 validate duration: 1.55
16 01:14:14.420262 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:14:14.420775 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:14:14.421255 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:14:14.421865 Not decompressing ramdisk as can be used compressed.
20 01:14:14.422368 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 01:14:14.422725 saving as /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/ramdisk/initrd.cpio.gz
22 01:14:14.423078 total size: 5628182 (5 MB)
23 01:14:14.428274 progress 0 % (0 MB)
24 01:14:14.437628 progress 5 % (0 MB)
25 01:14:14.444407 progress 10 % (0 MB)
26 01:14:14.448434 progress 15 % (0 MB)
27 01:14:14.452226 progress 20 % (1 MB)
28 01:14:14.455295 progress 25 % (1 MB)
29 01:14:14.458265 progress 30 % (1 MB)
30 01:14:14.460955 progress 35 % (1 MB)
31 01:14:14.463202 progress 40 % (2 MB)
32 01:14:14.465607 progress 45 % (2 MB)
33 01:14:14.467557 progress 50 % (2 MB)
34 01:14:14.469688 progress 55 % (2 MB)
35 01:14:14.471608 progress 60 % (3 MB)
36 01:14:14.473327 progress 65 % (3 MB)
37 01:14:14.475203 progress 70 % (3 MB)
38 01:14:14.476751 progress 75 % (4 MB)
39 01:14:14.478486 progress 80 % (4 MB)
40 01:14:14.479992 progress 85 % (4 MB)
41 01:14:14.481576 progress 90 % (4 MB)
42 01:14:14.483155 progress 95 % (5 MB)
43 01:14:14.484579 progress 100 % (5 MB)
44 01:14:14.484777 5 MB downloaded in 0.06 s (86.96 MB/s)
45 01:14:14.484924 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:14:14.485151 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:14:14.485233 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:14:14.485313 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:14:14.485440 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:14:14.485509 saving as /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/kernel/Image
52 01:14:14.485567 total size: 54352384 (51 MB)
53 01:14:14.485628 No compression specified
54 01:14:14.486749 progress 0 % (0 MB)
55 01:14:14.499984 progress 5 % (2 MB)
56 01:14:14.513989 progress 10 % (5 MB)
57 01:14:14.527712 progress 15 % (7 MB)
58 01:14:14.541410 progress 20 % (10 MB)
59 01:14:14.555184 progress 25 % (12 MB)
60 01:14:14.568777 progress 30 % (15 MB)
61 01:14:14.582286 progress 35 % (18 MB)
62 01:14:14.595890 progress 40 % (20 MB)
63 01:14:14.609399 progress 45 % (23 MB)
64 01:14:14.623137 progress 50 % (25 MB)
65 01:14:14.636688 progress 55 % (28 MB)
66 01:14:14.650169 progress 60 % (31 MB)
67 01:14:14.663666 progress 65 % (33 MB)
68 01:14:14.677720 progress 70 % (36 MB)
69 01:14:14.691608 progress 75 % (38 MB)
70 01:14:14.704928 progress 80 % (41 MB)
71 01:14:14.718656 progress 85 % (44 MB)
72 01:14:14.732751 progress 90 % (46 MB)
73 01:14:14.746328 progress 95 % (49 MB)
74 01:14:14.759751 progress 100 % (51 MB)
75 01:14:14.759967 51 MB downloaded in 0.27 s (188.90 MB/s)
76 01:14:14.760115 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:14:14.760339 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:14:14.760423 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:14:14.760511 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:14:14.760643 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:14:14.760717 saving as /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/dtb/mt8192-asurada-spherion-r0.dtb
83 01:14:14.760782 total size: 47230 (0 MB)
84 01:14:14.760842 No compression specified
85 01:14:14.761928 progress 69 % (0 MB)
86 01:14:14.762262 progress 100 % (0 MB)
87 01:14:14.762416 0 MB downloaded in 0.00 s (27.61 MB/s)
88 01:14:14.762536 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:14:14.762748 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:14:14.762831 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:14:14.762910 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:14:14.763023 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 01:14:14.763091 saving as /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/nfsrootfs/full.rootfs.tar
95 01:14:14.763151 total size: 107552908 (102 MB)
96 01:14:14.763211 Using unxz to decompress xz
97 01:14:14.767170 progress 0 % (0 MB)
98 01:14:15.039390 progress 5 % (5 MB)
99 01:14:15.347927 progress 10 % (10 MB)
100 01:14:15.652528 progress 15 % (15 MB)
101 01:14:15.967848 progress 20 % (20 MB)
102 01:14:16.224245 progress 25 % (25 MB)
103 01:14:16.508003 progress 30 % (30 MB)
104 01:14:16.812960 progress 35 % (35 MB)
105 01:14:16.976632 progress 40 % (41 MB)
106 01:14:17.168902 progress 45 % (46 MB)
107 01:14:17.468024 progress 50 % (51 MB)
108 01:14:17.758371 progress 55 % (56 MB)
109 01:14:18.082242 progress 60 % (61 MB)
110 01:14:18.403443 progress 65 % (66 MB)
111 01:14:18.716175 progress 70 % (71 MB)
112 01:14:19.037011 progress 75 % (76 MB)
113 01:14:19.334524 progress 80 % (82 MB)
114 01:14:19.638797 progress 85 % (87 MB)
115 01:14:19.934286 progress 90 % (92 MB)
116 01:14:20.229394 progress 95 % (97 MB)
117 01:14:20.542084 progress 100 % (102 MB)
118 01:14:20.547207 102 MB downloaded in 5.78 s (17.73 MB/s)
119 01:14:20.547478 end: 1.4.1 http-download (duration 00:00:06) [common]
121 01:14:20.547772 end: 1.4 download-retry (duration 00:00:06) [common]
122 01:14:20.547876 start: 1.5 download-retry (timeout 00:09:54) [common]
123 01:14:20.547979 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 01:14:20.548144 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:14:20.548221 saving as /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/modules/modules.tar
126 01:14:20.548302 total size: 8638160 (8 MB)
127 01:14:20.548403 Using unxz to decompress xz
128 01:14:20.552584 progress 0 % (0 MB)
129 01:14:20.571507 progress 5 % (0 MB)
130 01:14:20.596929 progress 10 % (0 MB)
131 01:14:20.621714 progress 15 % (1 MB)
132 01:14:20.645583 progress 20 % (1 MB)
133 01:14:20.671308 progress 25 % (2 MB)
134 01:14:20.697629 progress 30 % (2 MB)
135 01:14:20.723261 progress 35 % (2 MB)
136 01:14:20.748671 progress 40 % (3 MB)
137 01:14:20.773537 progress 45 % (3 MB)
138 01:14:20.797713 progress 50 % (4 MB)
139 01:14:20.821809 progress 55 % (4 MB)
140 01:14:20.849500 progress 60 % (4 MB)
141 01:14:20.874080 progress 65 % (5 MB)
142 01:14:20.898294 progress 70 % (5 MB)
143 01:14:20.922159 progress 75 % (6 MB)
144 01:14:20.946875 progress 80 % (6 MB)
145 01:14:20.974363 progress 85 % (7 MB)
146 01:14:20.999861 progress 90 % (7 MB)
147 01:14:21.028246 progress 95 % (7 MB)
148 01:14:21.054120 progress 100 % (8 MB)
149 01:14:21.059814 8 MB downloaded in 0.51 s (16.11 MB/s)
150 01:14:21.060063 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:14:21.060324 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:14:21.060418 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 01:14:21.060513 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 01:14:23.120425 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj
156 01:14:23.120626 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 01:14:23.120727 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 01:14:23.120878 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje
159 01:14:23.121000 makedir: /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin
160 01:14:23.121096 makedir: /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/tests
161 01:14:23.121188 makedir: /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/results
162 01:14:23.121284 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-add-keys
163 01:14:23.121420 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-add-sources
164 01:14:23.121541 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-background-process-start
165 01:14:23.121662 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-background-process-stop
166 01:14:23.121782 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-common-functions
167 01:14:23.121899 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-echo-ipv4
168 01:14:23.122017 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-install-packages
169 01:14:23.122171 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-installed-packages
170 01:14:23.122287 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-os-build
171 01:14:23.122404 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-probe-channel
172 01:14:23.122520 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-probe-ip
173 01:14:23.122637 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-target-ip
174 01:14:23.122753 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-target-mac
175 01:14:23.122869 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-target-storage
176 01:14:23.122987 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-case
177 01:14:23.123105 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-event
178 01:14:23.123232 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-feedback
179 01:14:23.123349 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-raise
180 01:14:23.123465 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-reference
181 01:14:23.123581 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-runner
182 01:14:23.123696 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-set
183 01:14:23.123811 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-test-shell
184 01:14:23.123927 Updating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-install-packages (oe)
185 01:14:23.124068 Updating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/bin/lava-installed-packages (oe)
186 01:14:23.124181 Creating /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/environment
187 01:14:23.124272 LAVA metadata
188 01:14:23.124338 - LAVA_JOB_ID=13468779
189 01:14:23.124398 - LAVA_DISPATCHER_IP=192.168.201.1
190 01:14:23.124492 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 01:14:23.124555 skipped lava-vland-overlay
192 01:14:23.124624 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 01:14:23.124699 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 01:14:23.124756 skipped lava-multinode-overlay
195 01:14:23.124823 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 01:14:23.124895 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 01:14:23.124963 Loading test definitions
198 01:14:23.125045 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 01:14:23.125113 Using /lava-13468779 at stage 0
200 01:14:23.125456 uuid=13468779_1.6.2.3.1 testdef=None
201 01:14:23.125539 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 01:14:23.125619 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 01:14:23.126264 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 01:14:23.126472 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 01:14:23.127063 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 01:14:23.127296 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 01:14:23.128260 runner path: /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/0/tests/0_dmesg test_uuid 13468779_1.6.2.3.1
210 01:14:23.128411 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 01:14:23.128604 Creating lava-test-runner.conf files
213 01:14:23.128664 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468779/lava-overlay-k5msfkje/lava-13468779/0 for stage 0
214 01:14:23.128748 - 0_dmesg
215 01:14:23.128841 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 01:14:23.128921 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
217 01:14:23.134691 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 01:14:23.134788 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
219 01:14:23.134869 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 01:14:23.134947 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 01:14:23.135027 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
222 01:14:23.295910 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 01:14:23.296281 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 01:14:23.296402 extracting modules file /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj
225 01:14:23.503447 extracting modules file /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468779/extract-overlay-ramdisk-d8tf2dd_/ramdisk
226 01:14:23.715850 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 01:14:23.716016 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 01:14:23.716108 [common] Applying overlay to NFS
229 01:14:23.716176 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468779/compress-overlay-_t8obgo2/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj
230 01:14:23.722668 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 01:14:23.722778 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 01:14:23.722864 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 01:14:23.722946 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 01:14:23.723022 Building ramdisk /var/lib/lava/dispatcher/tmp/13468779/extract-overlay-ramdisk-d8tf2dd_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468779/extract-overlay-ramdisk-d8tf2dd_/ramdisk
235 01:14:24.072456 >> 130624 blocks
236 01:14:26.085934 rename /var/lib/lava/dispatcher/tmp/13468779/extract-overlay-ramdisk-d8tf2dd_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/ramdisk/ramdisk.cpio.gz
237 01:14:26.086446 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 01:14:26.086592 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
239 01:14:26.086720 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
240 01:14:26.086858 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/kernel/Image'
241 01:14:38.896413 Returned 0 in 12 seconds
242 01:14:38.997065 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/kernel/image.itb
243 01:14:39.367871 output: FIT description: Kernel Image image with one or more FDT blobs
244 01:14:39.368258 output: Created: Tue Apr 23 02:14:39 2024
245 01:14:39.368339 output: Image 0 (kernel-1)
246 01:14:39.368404 output: Description:
247 01:14:39.368466 output: Created: Tue Apr 23 02:14:39 2024
248 01:14:39.368525 output: Type: Kernel Image
249 01:14:39.368585 output: Compression: lzma compressed
250 01:14:39.368640 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
251 01:14:39.368697 output: Architecture: AArch64
252 01:14:39.368752 output: OS: Linux
253 01:14:39.368804 output: Load Address: 0x00000000
254 01:14:39.368861 output: Entry Point: 0x00000000
255 01:14:39.368918 output: Hash algo: crc32
256 01:14:39.368974 output: Hash value: 1126c3f9
257 01:14:39.369028 output: Image 1 (fdt-1)
258 01:14:39.369082 output: Description: mt8192-asurada-spherion-r0
259 01:14:39.369136 output: Created: Tue Apr 23 02:14:39 2024
260 01:14:39.369189 output: Type: Flat Device Tree
261 01:14:39.369241 output: Compression: uncompressed
262 01:14:39.369292 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
263 01:14:39.369345 output: Architecture: AArch64
264 01:14:39.369396 output: Hash algo: crc32
265 01:14:39.369448 output: Hash value: 4bf0d1ac
266 01:14:39.369499 output: Image 2 (ramdisk-1)
267 01:14:39.369550 output: Description: unavailable
268 01:14:39.369602 output: Created: Tue Apr 23 02:14:39 2024
269 01:14:39.369653 output: Type: RAMDisk Image
270 01:14:39.369705 output: Compression: Unknown Compression
271 01:14:39.369757 output: Data Size: 18775635 Bytes = 18335.58 KiB = 17.91 MiB
272 01:14:39.369809 output: Architecture: AArch64
273 01:14:39.369860 output: OS: Linux
274 01:14:39.369912 output: Load Address: unavailable
275 01:14:39.369963 output: Entry Point: unavailable
276 01:14:39.370014 output: Hash algo: crc32
277 01:14:39.370108 output: Hash value: 7908f380
278 01:14:39.370160 output: Default Configuration: 'conf-1'
279 01:14:39.370215 output: Configuration 0 (conf-1)
280 01:14:39.370315 output: Description: mt8192-asurada-spherion-r0
281 01:14:39.370421 output: Kernel: kernel-1
282 01:14:39.370473 output: Init Ramdisk: ramdisk-1
283 01:14:39.370525 output: FDT: fdt-1
284 01:14:39.370576 output: Loadables: kernel-1
285 01:14:39.370627 output:
286 01:14:39.370823 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 01:14:39.370917 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 01:14:39.371019 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 01:14:39.371116 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 01:14:39.371192 No LXC device requested
291 01:14:39.371269 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 01:14:39.371359 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 01:14:39.371437 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 01:14:39.371504 Checking files for TFTP limit of 4294967296 bytes.
295 01:14:39.371990 end: 1 tftp-deploy (duration 00:00:25) [common]
296 01:14:39.372088 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 01:14:39.372175 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 01:14:39.372305 substitutions:
299 01:14:39.372378 - {DTB}: 13468779/tftp-deploy-xr4cs4k4/dtb/mt8192-asurada-spherion-r0.dtb
300 01:14:39.372441 - {INITRD}: 13468779/tftp-deploy-xr4cs4k4/ramdisk/ramdisk.cpio.gz
301 01:14:39.372499 - {KERNEL}: 13468779/tftp-deploy-xr4cs4k4/kernel/Image
302 01:14:39.372555 - {LAVA_MAC}: None
303 01:14:39.372609 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj
304 01:14:39.372664 - {NFS_SERVER_IP}: 192.168.201.1
305 01:14:39.372717 - {PRESEED_CONFIG}: None
306 01:14:39.372770 - {PRESEED_LOCAL}: None
307 01:14:39.372823 - {RAMDISK}: 13468779/tftp-deploy-xr4cs4k4/ramdisk/ramdisk.cpio.gz
308 01:14:39.372875 - {ROOT_PART}: None
309 01:14:39.372928 - {ROOT}: None
310 01:14:39.372980 - {SERVER_IP}: 192.168.201.1
311 01:14:39.373031 - {TEE}: None
312 01:14:39.373083 Parsed boot commands:
313 01:14:39.373134 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 01:14:39.373312 Parsed boot commands: tftpboot 192.168.201.1 13468779/tftp-deploy-xr4cs4k4/kernel/image.itb 13468779/tftp-deploy-xr4cs4k4/kernel/cmdline
315 01:14:39.373397 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 01:14:39.373481 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 01:14:39.373575 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 01:14:39.373660 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 01:14:39.373734 Not connected, no need to disconnect.
320 01:14:39.373807 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 01:14:39.373888 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 01:14:39.373957 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 01:14:39.377993 Setting prompt string to ['lava-test: # ']
324 01:14:39.378478 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 01:14:39.378669 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 01:14:39.378769 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 01:14:39.378880 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 01:14:39.379101 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
329 01:14:44.512639 >> Command sent successfully.
330 01:14:44.514978 Returned 0 in 5 seconds
331 01:14:44.615408 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 01:14:44.615744 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 01:14:44.615845 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 01:14:44.615933 Setting prompt string to 'Starting depthcharge on Spherion...'
336 01:14:44.616000 Changing prompt to 'Starting depthcharge on Spherion...'
337 01:14:44.616064 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 01:14:44.616331 [Enter `^Ec?' for help]
339 01:14:45.023608
340 01:14:45.023774
341 01:14:45.023874 F0: 102B 0000
342 01:14:45.023957
343 01:14:45.024034 F3: 1001 0000 [0200]
344 01:14:45.026816
345 01:14:45.026900 F3: 1001 0000
346 01:14:45.026985
347 01:14:45.027064 F7: 102D 0000
348 01:14:45.027141
349 01:14:45.029949 F1: 0000 0000
350 01:14:45.030082
351 01:14:45.030183 V0: 0000 0000 [0001]
352 01:14:45.030281
353 01:14:45.033673 00: 0007 8000
354 01:14:45.033761
355 01:14:45.033845 01: 0000 0000
356 01:14:45.033927
357 01:14:45.036379 BP: 0C00 0209 [0000]
358 01:14:45.036462
359 01:14:45.036544 G0: 1182 0000
360 01:14:45.036623
361 01:14:45.040045 EC: 0000 0021 [4000]
362 01:14:45.040128
363 01:14:45.040211 S7: 0000 0000 [0000]
364 01:14:45.040289
365 01:14:45.043248 CC: 0000 0000 [0001]
366 01:14:45.043331
367 01:14:45.043414 T0: 0000 0040 [010F]
368 01:14:45.043496
369 01:14:45.046254 Jump to BL
370 01:14:45.046336
371 01:14:45.070501
372 01:14:45.070609
373 01:14:45.070698
374 01:14:45.079951 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 01:14:45.083703 ARM64: Exception handlers installed.
376 01:14:45.083790 ARM64: Testing exception
377 01:14:45.086575 ARM64: Done test exception
378 01:14:45.093515 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 01:14:45.103816 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 01:14:45.110245 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 01:14:45.120843 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 01:14:45.127491 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 01:14:45.137891 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 01:14:45.147973 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 01:14:45.154988 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 01:14:45.173210 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 01:14:45.176875 WDT: Last reset was cold boot
388 01:14:45.180178 SPI1(PAD0) initialized at 2873684 Hz
389 01:14:45.183597 SPI5(PAD0) initialized at 992727 Hz
390 01:14:45.186544 VBOOT: Loading verstage.
391 01:14:45.193014 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 01:14:45.196339 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 01:14:45.199609 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 01:14:45.202904 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 01:14:45.210540 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 01:14:45.217064 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 01:14:45.228044 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
398 01:14:45.228140
399 01:14:45.228206
400 01:14:45.237868 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 01:14:45.241484 ARM64: Exception handlers installed.
402 01:14:45.244856 ARM64: Testing exception
403 01:14:45.244939 ARM64: Done test exception
404 01:14:45.251192 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 01:14:45.254710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 01:14:45.269405 Probing TPM: . done!
407 01:14:45.269519 TPM ready after 0 ms
408 01:14:45.275990 Connected to device vid:did:rid of 1ae0:0028:00
409 01:14:45.282420 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
410 01:14:45.286441 Initialized TPM device CR50 revision 0
411 01:14:45.385978 tlcl_send_startup: Startup return code is 0
412 01:14:45.386148 TPM: setup succeeded
413 01:14:45.400095 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 01:14:45.409380 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 01:14:45.421272 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 01:14:45.430838 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 01:14:45.434510 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 01:14:45.438636 in-header: 03 07 00 00 08 00 00 00
419 01:14:45.441703 in-data: aa e4 47 04 13 02 00 00
420 01:14:45.445215 Chrome EC: UHEPI supported
421 01:14:45.448715 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 01:14:45.453339 in-header: 03 ad 00 00 08 00 00 00
423 01:14:45.456120 in-data: 00 20 20 08 00 00 00 00
424 01:14:45.459795 Phase 1
425 01:14:45.462969 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 01:14:45.469610 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 01:14:45.472694 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 01:14:45.476146 Recovery requested (1009000e)
429 01:14:45.484639 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 01:14:45.489781 tlcl_extend: response is 0
431 01:14:45.497780 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 01:14:45.503844 tlcl_extend: response is 0
433 01:14:45.510362 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 01:14:45.530472 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
435 01:14:45.536803 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 01:14:45.536991
437 01:14:45.537147
438 01:14:45.546720 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 01:14:45.550064 ARM64: Exception handlers installed.
440 01:14:45.553683 ARM64: Testing exception
441 01:14:45.553770 ARM64: Done test exception
442 01:14:45.575888 pmic_efuse_setting: Set efuses in 11 msecs
443 01:14:45.579135 pmwrap_interface_init: Select PMIF_VLD_RDY
444 01:14:45.585779 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 01:14:45.589479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 01:14:45.596005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 01:14:45.599188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 01:14:45.606332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 01:14:45.609262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 01:14:45.612713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 01:14:45.619356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 01:14:45.622353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 01:14:45.628979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 01:14:45.632622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 01:14:45.636199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 01:14:45.642410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 01:14:45.649306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 01:14:45.652617 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 01:14:45.659137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 01:14:45.666369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 01:14:45.672201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 01:14:45.675644 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 01:14:45.682258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 01:14:45.688712 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 01:14:45.692090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 01:14:45.698817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 01:14:45.705311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 01:14:45.708485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 01:14:45.715436 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 01:14:45.721663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 01:14:45.725062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 01:14:45.731860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 01:14:45.734888 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 01:14:45.738258 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 01:14:45.744914 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 01:14:45.751605 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 01:14:45.755464 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 01:14:45.758373 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 01:14:45.764903 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 01:14:45.771556 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 01:14:45.775039 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 01:14:45.778737 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 01:14:45.784706 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 01:14:45.788273 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 01:14:45.791713 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 01:14:45.798209 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 01:14:45.801319 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 01:14:45.804651 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 01:14:45.811570 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 01:14:45.814870 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 01:14:45.818329 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 01:14:45.821161 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 01:14:45.828311 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 01:14:45.831463 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 01:14:45.838416 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 01:14:45.847961 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 01:14:45.851928 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 01:14:45.861261 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 01:14:45.868015 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 01:14:45.874481 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 01:14:45.877998 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 01:14:45.881127 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 01:14:45.888756 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x13
504 01:14:45.895584 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
505 01:14:45.898693 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 01:14:45.905112 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 01:14:45.913081 [RTC]rtc_get_frequency_meter,154: input=15, output=764
508 01:14:45.922826 [RTC]rtc_get_frequency_meter,154: input=23, output=949
509 01:14:45.932196 [RTC]rtc_get_frequency_meter,154: input=19, output=856
510 01:14:45.941896 [RTC]rtc_get_frequency_meter,154: input=17, output=810
511 01:14:45.951382 [RTC]rtc_get_frequency_meter,154: input=16, output=788
512 01:14:45.960790 [RTC]rtc_get_frequency_meter,154: input=16, output=786
513 01:14:45.970359 [RTC]rtc_get_frequency_meter,154: input=17, output=811
514 01:14:45.973530 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 01:14:45.980580 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 01:14:45.983941 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 01:14:45.987524 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
518 01:14:45.994402 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 01:14:45.997352 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
520 01:14:46.001044 ADC[4]: Raw value=670063 ID=5
521 01:14:46.001162 ADC[3]: Raw value=212917 ID=1
522 01:14:46.003954 RAM Code: 0x51
523 01:14:46.007249 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 01:14:46.013973 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 01:14:46.021008 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
526 01:14:46.027239 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
527 01:14:46.030524 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 01:14:46.034234 in-header: 03 07 00 00 08 00 00 00
529 01:14:46.037506 in-data: aa e4 47 04 13 02 00 00
530 01:14:46.040767 Chrome EC: UHEPI supported
531 01:14:46.047219 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 01:14:46.051015 in-header: 03 ed 00 00 08 00 00 00
533 01:14:46.053922 in-data: 80 20 60 08 00 00 00 00
534 01:14:46.057039 MRC: failed to locate region type 0.
535 01:14:46.064395 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 01:14:46.064502 DRAM-K: Running full calibration
537 01:14:46.071595 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
538 01:14:46.071705 header.status = 0x0
539 01:14:46.075611 header.version = 0x6 (expected: 0x6)
540 01:14:46.078734 header.size = 0xd00 (expected: 0xd00)
541 01:14:46.082583 header.flags = 0x0
542 01:14:46.085910 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 01:14:46.105776 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
544 01:14:46.112493 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 01:14:46.115798 dram_init: ddr_geometry: 0
546 01:14:46.115901 [EMI] MDL number = 0
547 01:14:46.119089 [EMI] Get MDL freq = 0
548 01:14:46.122190 dram_init: ddr_type: 0
549 01:14:46.122276 is_discrete_lpddr4: 1
550 01:14:46.125877 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 01:14:46.125963
552 01:14:46.126067
553 01:14:46.128899 [Bian_co] ETT version 0.0.0.1
554 01:14:46.132168 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
555 01:14:46.136041
556 01:14:46.138961 dramc_set_vcore_voltage set vcore to 650000
557 01:14:46.139049 Read voltage for 800, 4
558 01:14:46.142741 Vio18 = 0
559 01:14:46.142828 Vcore = 650000
560 01:14:46.142914 Vdram = 0
561 01:14:46.146294 Vddq = 0
562 01:14:46.146380 Vmddr = 0
563 01:14:46.149075 dram_init: config_dvfs: 1
564 01:14:46.152672 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 01:14:46.158823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 01:14:46.162204 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 01:14:46.165480 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 01:14:46.168782 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 01:14:46.172186 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 01:14:46.175502 MEM_TYPE=3, freq_sel=18
571 01:14:46.178967 sv_algorithm_assistance_LP4_1600
572 01:14:46.182020 ============ PULL DRAM RESETB DOWN ============
573 01:14:46.185670 ========== PULL DRAM RESETB DOWN end =========
574 01:14:46.192040 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 01:14:46.195480 ===================================
576 01:14:46.195577 LPDDR4 DRAM CONFIGURATION
577 01:14:46.198603 ===================================
578 01:14:46.202259 EX_ROW_EN[0] = 0x0
579 01:14:46.205328 EX_ROW_EN[1] = 0x0
580 01:14:46.205413 LP4Y_EN = 0x0
581 01:14:46.209043 WORK_FSP = 0x0
582 01:14:46.209133 WL = 0x2
583 01:14:46.212023 RL = 0x2
584 01:14:46.212109 BL = 0x2
585 01:14:46.215274 RPST = 0x0
586 01:14:46.215361 RD_PRE = 0x0
587 01:14:46.218657 WR_PRE = 0x1
588 01:14:46.218743 WR_PST = 0x0
589 01:14:46.222319 DBI_WR = 0x0
590 01:14:46.222408 DBI_RD = 0x0
591 01:14:46.225671 OTF = 0x1
592 01:14:46.228881 ===================================
593 01:14:46.232382 ===================================
594 01:14:46.232476 ANA top config
595 01:14:46.235665 ===================================
596 01:14:46.238744 DLL_ASYNC_EN = 0
597 01:14:46.242289 ALL_SLAVE_EN = 1
598 01:14:46.245386 NEW_RANK_MODE = 1
599 01:14:46.245478 DLL_IDLE_MODE = 1
600 01:14:46.248450 LP45_APHY_COMB_EN = 1
601 01:14:46.251980 TX_ODT_DIS = 1
602 01:14:46.255067 NEW_8X_MODE = 1
603 01:14:46.258697 ===================================
604 01:14:46.261905 ===================================
605 01:14:46.261991 data_rate = 1600
606 01:14:46.265263 CKR = 1
607 01:14:46.268649 DQ_P2S_RATIO = 8
608 01:14:46.271991 ===================================
609 01:14:46.275239 CA_P2S_RATIO = 8
610 01:14:46.278688 DQ_CA_OPEN = 0
611 01:14:46.281637 DQ_SEMI_OPEN = 0
612 01:14:46.281724 CA_SEMI_OPEN = 0
613 01:14:46.285282 CA_FULL_RATE = 0
614 01:14:46.288914 DQ_CKDIV4_EN = 1
615 01:14:46.291832 CA_CKDIV4_EN = 1
616 01:14:46.295292 CA_PREDIV_EN = 0
617 01:14:46.298425 PH8_DLY = 0
618 01:14:46.298511 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 01:14:46.301945 DQ_AAMCK_DIV = 4
620 01:14:46.305168 CA_AAMCK_DIV = 4
621 01:14:46.308650 CA_ADMCK_DIV = 4
622 01:14:46.311903 DQ_TRACK_CA_EN = 0
623 01:14:46.315186 CA_PICK = 800
624 01:14:46.318364 CA_MCKIO = 800
625 01:14:46.318450 MCKIO_SEMI = 0
626 01:14:46.321615 PLL_FREQ = 3068
627 01:14:46.325067 DQ_UI_PI_RATIO = 32
628 01:14:46.328217 CA_UI_PI_RATIO = 0
629 01:14:46.331553 ===================================
630 01:14:46.334973 ===================================
631 01:14:46.338340 memory_type:LPDDR4
632 01:14:46.338423 GP_NUM : 10
633 01:14:46.342003 SRAM_EN : 1
634 01:14:46.345013 MD32_EN : 0
635 01:14:46.345095 ===================================
636 01:14:46.348537 [ANA_INIT] >>>>>>>>>>>>>>
637 01:14:46.351601 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 01:14:46.355027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 01:14:46.358193 ===================================
640 01:14:46.361739 data_rate = 1600,PCW = 0X7600
641 01:14:46.364857 ===================================
642 01:14:46.368249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 01:14:46.375245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 01:14:46.378325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 01:14:46.385101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 01:14:46.388179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 01:14:46.391781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 01:14:46.391866 [ANA_INIT] flow start
649 01:14:46.394854 [ANA_INIT] PLL >>>>>>>>
650 01:14:46.398204 [ANA_INIT] PLL <<<<<<<<
651 01:14:46.398286 [ANA_INIT] MIDPI >>>>>>>>
652 01:14:46.401484 [ANA_INIT] MIDPI <<<<<<<<
653 01:14:46.405085 [ANA_INIT] DLL >>>>>>>>
654 01:14:46.405168 [ANA_INIT] flow end
655 01:14:46.411902 ============ LP4 DIFF to SE enter ============
656 01:14:46.415622 ============ LP4 DIFF to SE exit ============
657 01:14:46.415706 [ANA_INIT] <<<<<<<<<<<<<
658 01:14:46.419746 [Flow] Enable top DCM control >>>>>
659 01:14:46.423147 [Flow] Enable top DCM control <<<<<
660 01:14:46.426322 Enable DLL master slave shuffle
661 01:14:46.430196 ==============================================================
662 01:14:46.433727 Gating Mode config
663 01:14:46.437403 ==============================================================
664 01:14:46.441380 Config description:
665 01:14:46.452302 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 01:14:46.455999 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 01:14:46.462579 SELPH_MODE 0: By rank 1: By Phase
668 01:14:46.465828 ==============================================================
669 01:14:46.469117 GAT_TRACK_EN = 1
670 01:14:46.472847 RX_GATING_MODE = 2
671 01:14:46.475884 RX_GATING_TRACK_MODE = 2
672 01:14:46.479424 SELPH_MODE = 1
673 01:14:46.482549 PICG_EARLY_EN = 1
674 01:14:46.485735 VALID_LAT_VALUE = 1
675 01:14:46.492737 ==============================================================
676 01:14:46.496055 Enter into Gating configuration >>>>
677 01:14:46.499641 Exit from Gating configuration <<<<
678 01:14:46.499724 Enter into DVFS_PRE_config >>>>>
679 01:14:46.510392 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 01:14:46.514100 Exit from DVFS_PRE_config <<<<<
681 01:14:46.517715 Enter into PICG configuration >>>>
682 01:14:46.521215 Exit from PICG configuration <<<<
683 01:14:46.525278 [RX_INPUT] configuration >>>>>
684 01:14:46.528714 [RX_INPUT] configuration <<<<<
685 01:14:46.532617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 01:14:46.536294 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 01:14:46.543169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 01:14:46.550900 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 01:14:46.558256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 01:14:46.561818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 01:14:46.565588 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 01:14:46.569104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 01:14:46.573240 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 01:14:46.580777 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 01:14:46.584290 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 01:14:46.587957 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 01:14:46.591345 ===================================
698 01:14:46.591438 LPDDR4 DRAM CONFIGURATION
699 01:14:46.595175 ===================================
700 01:14:46.599101 EX_ROW_EN[0] = 0x0
701 01:14:46.599187 EX_ROW_EN[1] = 0x0
702 01:14:46.602754 LP4Y_EN = 0x0
703 01:14:46.602839 WORK_FSP = 0x0
704 01:14:46.606528 WL = 0x2
705 01:14:46.606613 RL = 0x2
706 01:14:46.610334 BL = 0x2
707 01:14:46.610419 RPST = 0x0
708 01:14:46.613865 RD_PRE = 0x0
709 01:14:46.613949 WR_PRE = 0x1
710 01:14:46.614015 WR_PST = 0x0
711 01:14:46.617822 DBI_WR = 0x0
712 01:14:46.617908 DBI_RD = 0x0
713 01:14:46.621300 OTF = 0x1
714 01:14:46.624304 ===================================
715 01:14:46.627635 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 01:14:46.630857 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 01:14:46.637675 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 01:14:46.640916 ===================================
719 01:14:46.641005 LPDDR4 DRAM CONFIGURATION
720 01:14:46.644690 ===================================
721 01:14:46.648444 EX_ROW_EN[0] = 0x10
722 01:14:46.648530 EX_ROW_EN[1] = 0x0
723 01:14:46.652010 LP4Y_EN = 0x0
724 01:14:46.652094 WORK_FSP = 0x0
725 01:14:46.655483 WL = 0x2
726 01:14:46.655570 RL = 0x2
727 01:14:46.658981 BL = 0x2
728 01:14:46.659066 RPST = 0x0
729 01:14:46.662482 RD_PRE = 0x0
730 01:14:46.662567 WR_PRE = 0x1
731 01:14:46.665760 WR_PST = 0x0
732 01:14:46.665845 DBI_WR = 0x0
733 01:14:46.669342 DBI_RD = 0x0
734 01:14:46.669428 OTF = 0x1
735 01:14:46.673033 ===================================
736 01:14:46.679912 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 01:14:46.683400 nWR fixed to 40
738 01:14:46.686836 [ModeRegInit_LP4] CH0 RK0
739 01:14:46.686922 [ModeRegInit_LP4] CH0 RK1
740 01:14:46.690232 [ModeRegInit_LP4] CH1 RK0
741 01:14:46.693516 [ModeRegInit_LP4] CH1 RK1
742 01:14:46.693600 match AC timing 12
743 01:14:46.700401 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
744 01:14:46.703433 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 01:14:46.707077 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 01:14:46.713775 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 01:14:46.717383 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 01:14:46.717471 [EMI DOE] emi_dcm 0
749 01:14:46.724125 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 01:14:46.724216 ==
751 01:14:46.727488 Dram Type= 6, Freq= 0, CH_0, rank 0
752 01:14:46.731723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
753 01:14:46.731809 ==
754 01:14:46.734926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 01:14:46.742282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 01:14:46.751126 [CA 0] Center 37 (7~68) winsize 62
757 01:14:46.754887 [CA 1] Center 37 (7~68) winsize 62
758 01:14:46.758477 [CA 2] Center 35 (5~66) winsize 62
759 01:14:46.762110 [CA 3] Center 35 (4~66) winsize 63
760 01:14:46.765588 [CA 4] Center 34 (4~65) winsize 62
761 01:14:46.769236 [CA 5] Center 34 (4~64) winsize 61
762 01:14:46.769321
763 01:14:46.773215 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 01:14:46.773299
765 01:14:46.776850 [CATrainingPosCal] consider 1 rank data
766 01:14:46.776935 u2DelayCellTimex100 = 270/100 ps
767 01:14:46.780614 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
768 01:14:46.784550 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
769 01:14:46.788122 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
770 01:14:46.792190 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
771 01:14:46.795082 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
772 01:14:46.798871 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
773 01:14:46.798957
774 01:14:46.802930 CA PerBit enable=1, Macro0, CA PI delay=34
775 01:14:46.805925
776 01:14:46.806079 [CBTSetCACLKResult] CA Dly = 34
777 01:14:46.809697 CS Dly: 5 (0~36)
778 01:14:46.809780 ==
779 01:14:46.813357 Dram Type= 6, Freq= 0, CH_0, rank 1
780 01:14:46.817492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 01:14:46.817578 ==
782 01:14:46.820308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 01:14:46.827236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 01:14:46.837240 [CA 0] Center 37 (7~68) winsize 62
785 01:14:46.840794 [CA 1] Center 37 (6~68) winsize 63
786 01:14:46.844160 [CA 2] Center 35 (5~66) winsize 62
787 01:14:46.848096 [CA 3] Center 35 (5~66) winsize 62
788 01:14:46.851781 [CA 4] Center 34 (3~65) winsize 63
789 01:14:46.855312 [CA 5] Center 34 (3~65) winsize 63
790 01:14:46.855399
791 01:14:46.858797 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 01:14:46.858883
793 01:14:46.862461 [CATrainingPosCal] consider 2 rank data
794 01:14:46.865803 u2DelayCellTimex100 = 270/100 ps
795 01:14:46.869857 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
796 01:14:46.873089 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
797 01:14:46.876553 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
798 01:14:46.880361 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
799 01:14:46.884311 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
800 01:14:46.887418 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
801 01:14:46.887505
802 01:14:46.891250 CA PerBit enable=1, Macro0, CA PI delay=34
803 01:14:46.891339
804 01:14:46.894827 [CBTSetCACLKResult] CA Dly = 34
805 01:14:46.894913 CS Dly: 6 (0~38)
806 01:14:46.894980
807 01:14:46.898439 ----->DramcWriteLeveling(PI) begin...
808 01:14:46.898528 ==
809 01:14:46.902189 Dram Type= 6, Freq= 0, CH_0, rank 0
810 01:14:46.905647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 01:14:46.905734 ==
812 01:14:46.909352 Write leveling (Byte 0): 27 => 27
813 01:14:46.912796 Write leveling (Byte 1): 26 => 26
814 01:14:46.916785 DramcWriteLeveling(PI) end<-----
815 01:14:46.916870
816 01:14:46.916937 ==
817 01:14:46.920504 Dram Type= 6, Freq= 0, CH_0, rank 0
818 01:14:46.924037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
819 01:14:46.924129 ==
820 01:14:46.927256 [Gating] SW mode calibration
821 01:14:46.934851 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 01:14:46.938343 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 01:14:46.942728 0 6 0 | B1->B0 | 3434 3333 | 0 1 | (0 1) (1 0)
824 01:14:46.946200 0 6 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
825 01:14:46.949866 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 01:14:46.957134 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 01:14:46.960892 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 01:14:46.964346 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 01:14:46.968017 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 01:14:46.971702 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 01:14:46.979350 0 7 0 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
832 01:14:46.982839 0 7 4 | B1->B0 | 3838 4141 | 1 0 | (0 0) (0 0)
833 01:14:46.986570 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 01:14:46.990008 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 01:14:46.993835 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 01:14:47.001004 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 01:14:47.004743 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 01:14:47.008337 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
839 01:14:47.011929 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 01:14:47.015617 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
841 01:14:47.023149 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 01:14:47.026864 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 01:14:47.030601 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 01:14:47.034348 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 01:14:47.037651 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 01:14:47.045715 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 01:14:47.048882 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 01:14:47.052516 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 01:14:47.056539 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 01:14:47.060326 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 01:14:47.067117 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 01:14:47.070895 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 01:14:47.075086 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 01:14:47.078426 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 01:14:47.081877 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
856 01:14:47.089838 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
857 01:14:47.089926 Total UI for P1: 0, mck2ui 16
858 01:14:47.093423 best dqsien dly found for B0: ( 0, 10, 0)
859 01:14:47.096827 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 01:14:47.100374 Total UI for P1: 0, mck2ui 16
861 01:14:47.104080 best dqsien dly found for B1: ( 0, 10, 2)
862 01:14:47.108199 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
863 01:14:47.111653 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
864 01:14:47.111740
865 01:14:47.115103 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
866 01:14:47.118950 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
867 01:14:47.122890 [Gating] SW calibration Done
868 01:14:47.122979 ==
869 01:14:47.126296 Dram Type= 6, Freq= 0, CH_0, rank 0
870 01:14:47.130132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
871 01:14:47.130220 ==
872 01:14:47.133594 RX Vref Scan: 0
873 01:14:47.133678
874 01:14:47.133744 RX Vref 0 -> 0, step: 1
875 01:14:47.133806
876 01:14:47.137270 RX Delay -130 -> 252, step: 16
877 01:14:47.141186 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
878 01:14:47.144685 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
879 01:14:47.148190 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
880 01:14:47.151705 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
881 01:14:47.155806 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
882 01:14:47.159070 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
883 01:14:47.166736 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
884 01:14:47.170256 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
885 01:14:47.174042 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
886 01:14:47.177576 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
887 01:14:47.181199 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
888 01:14:47.184806 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
889 01:14:47.188356 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
890 01:14:47.192316 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
891 01:14:47.195486 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
892 01:14:47.202712 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
893 01:14:47.202802 ==
894 01:14:47.206803 Dram Type= 6, Freq= 0, CH_0, rank 0
895 01:14:47.210310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
896 01:14:47.210396 ==
897 01:14:47.210462 DQS Delay:
898 01:14:47.213872 DQS0 = 0, DQS1 = 0
899 01:14:47.213955 DQM Delay:
900 01:14:47.214028 DQM0 = 83, DQM1 = 74
901 01:14:47.217398 DQ Delay:
902 01:14:47.217481 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
903 01:14:47.220981 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
904 01:14:47.224910 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
905 01:14:47.228387 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
906 01:14:47.228473
907 01:14:47.228539
908 01:14:47.228600 ==
909 01:14:47.232194 Dram Type= 6, Freq= 0, CH_0, rank 0
910 01:14:47.235643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
911 01:14:47.235728 ==
912 01:14:47.235795
913 01:14:47.235855
914 01:14:47.239171 TX Vref Scan disable
915 01:14:47.242955 == TX Byte 0 ==
916 01:14:47.246362 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
917 01:14:47.250064 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
918 01:14:47.250149 == TX Byte 1 ==
919 01:14:47.257242 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
920 01:14:47.260901 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
921 01:14:47.260987 ==
922 01:14:47.264526 Dram Type= 6, Freq= 0, CH_0, rank 0
923 01:14:47.267809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 01:14:47.267895 ==
925 01:14:47.281242 TX Vref=22, minBit 0, minWin=27, winSum=439
926 01:14:47.284761 TX Vref=24, minBit 0, minWin=27, winSum=443
927 01:14:47.288116 TX Vref=26, minBit 4, minWin=27, winSum=448
928 01:14:47.291603 TX Vref=28, minBit 11, minWin=27, winSum=449
929 01:14:47.294731 TX Vref=30, minBit 2, minWin=28, winSum=452
930 01:14:47.298436 TX Vref=32, minBit 0, minWin=28, winSum=449
931 01:14:47.304869 [TxChooseVref] Worse bit 2, Min win 28, Win sum 452, Final Vref 30
932 01:14:47.304957
933 01:14:47.308468 Final TX Range 1 Vref 30
934 01:14:47.308552
935 01:14:47.308617 ==
936 01:14:47.312235 Dram Type= 6, Freq= 0, CH_0, rank 0
937 01:14:47.315801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
938 01:14:47.315887 ==
939 01:14:47.315957
940 01:14:47.316017
941 01:14:47.316074 TX Vref Scan disable
942 01:14:47.320715 == TX Byte 0 ==
943 01:14:47.324646 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
944 01:14:47.328248 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
945 01:14:47.332092 == TX Byte 1 ==
946 01:14:47.335403 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
947 01:14:47.339323 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
948 01:14:47.339406
949 01:14:47.339472 [DATLAT]
950 01:14:47.342813 Freq=800, CH0 RK0
951 01:14:47.342896
952 01:14:47.342962 DATLAT Default: 0xa
953 01:14:47.346453 0, 0xFFFF, sum = 0
954 01:14:47.346538 1, 0xFFFF, sum = 0
955 01:14:47.349608 2, 0xFFFF, sum = 0
956 01:14:47.349691 3, 0xFFFF, sum = 0
957 01:14:47.352906 4, 0xFFFF, sum = 0
958 01:14:47.352990 5, 0xFFFF, sum = 0
959 01:14:47.356491 6, 0xFFFF, sum = 0
960 01:14:47.356576 7, 0xFFFF, sum = 0
961 01:14:47.359727 8, 0x0, sum = 1
962 01:14:47.359812 9, 0x0, sum = 2
963 01:14:47.362811 10, 0x0, sum = 3
964 01:14:47.362895 11, 0x0, sum = 4
965 01:14:47.362962 best_step = 9
966 01:14:47.366302
967 01:14:47.366385 ==
968 01:14:47.369330 Dram Type= 6, Freq= 0, CH_0, rank 0
969 01:14:47.372958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
970 01:14:47.373043 ==
971 01:14:47.373108 RX Vref Scan: 1
972 01:14:47.373170
973 01:14:47.376066 Set Vref Range= 32 -> 127
974 01:14:47.376149
975 01:14:47.379619 RX Vref 32 -> 127, step: 1
976 01:14:47.379702
977 01:14:47.382930 RX Delay -111 -> 252, step: 8
978 01:14:47.383013
979 01:14:47.386061 Set Vref, RX VrefLevel [Byte0]: 32
980 01:14:47.389651 [Byte1]: 32
981 01:14:47.389733
982 01:14:47.392843 Set Vref, RX VrefLevel [Byte0]: 33
983 01:14:47.396049 [Byte1]: 33
984 01:14:47.396133
985 01:14:47.399452 Set Vref, RX VrefLevel [Byte0]: 34
986 01:14:47.402590 [Byte1]: 34
987 01:14:47.406614
988 01:14:47.406697 Set Vref, RX VrefLevel [Byte0]: 35
989 01:14:47.409694 [Byte1]: 35
990 01:14:47.414366
991 01:14:47.414448 Set Vref, RX VrefLevel [Byte0]: 36
992 01:14:47.417295 [Byte1]: 36
993 01:14:47.421623
994 01:14:47.421705 Set Vref, RX VrefLevel [Byte0]: 37
995 01:14:47.425351 [Byte1]: 37
996 01:14:47.429391
997 01:14:47.429473 Set Vref, RX VrefLevel [Byte0]: 38
998 01:14:47.432895 [Byte1]: 38
999 01:14:47.437254
1000 01:14:47.437336 Set Vref, RX VrefLevel [Byte0]: 39
1001 01:14:47.440335 [Byte1]: 39
1002 01:14:47.444850
1003 01:14:47.444934 Set Vref, RX VrefLevel [Byte0]: 40
1004 01:14:47.448001 [Byte1]: 40
1005 01:14:47.452321
1006 01:14:47.452405 Set Vref, RX VrefLevel [Byte0]: 41
1007 01:14:47.455679 [Byte1]: 41
1008 01:14:47.460244
1009 01:14:47.460328 Set Vref, RX VrefLevel [Byte0]: 42
1010 01:14:47.463510 [Byte1]: 42
1011 01:14:47.467982
1012 01:14:47.468067 Set Vref, RX VrefLevel [Byte0]: 43
1013 01:14:47.471015 [Byte1]: 43
1014 01:14:47.475328
1015 01:14:47.475413 Set Vref, RX VrefLevel [Byte0]: 44
1016 01:14:47.478516 [Byte1]: 44
1017 01:14:47.482939
1018 01:14:47.483024 Set Vref, RX VrefLevel [Byte0]: 45
1019 01:14:47.486565 [Byte1]: 45
1020 01:14:47.490651
1021 01:14:47.490735 Set Vref, RX VrefLevel [Byte0]: 46
1022 01:14:47.494261 [Byte1]: 46
1023 01:14:47.498389
1024 01:14:47.498476 Set Vref, RX VrefLevel [Byte0]: 47
1025 01:14:47.502176 [Byte1]: 47
1026 01:14:47.506136
1027 01:14:47.506217 Set Vref, RX VrefLevel [Byte0]: 48
1028 01:14:47.509380 [Byte1]: 48
1029 01:14:47.513796
1030 01:14:47.513879 Set Vref, RX VrefLevel [Byte0]: 49
1031 01:14:47.517091 [Byte1]: 49
1032 01:14:47.521253
1033 01:14:47.521337 Set Vref, RX VrefLevel [Byte0]: 50
1034 01:14:47.524318 [Byte1]: 50
1035 01:14:47.528886
1036 01:14:47.528969 Set Vref, RX VrefLevel [Byte0]: 51
1037 01:14:47.532302 [Byte1]: 51
1038 01:14:47.536994
1039 01:14:47.537077 Set Vref, RX VrefLevel [Byte0]: 52
1040 01:14:47.539723 [Byte1]: 52
1041 01:14:47.544422
1042 01:14:47.544505 Set Vref, RX VrefLevel [Byte0]: 53
1043 01:14:47.547441 [Byte1]: 53
1044 01:14:47.551586
1045 01:14:47.551669 Set Vref, RX VrefLevel [Byte0]: 54
1046 01:14:47.554960 [Byte1]: 54
1047 01:14:47.559305
1048 01:14:47.559389 Set Vref, RX VrefLevel [Byte0]: 55
1049 01:14:47.562813 [Byte1]: 55
1050 01:14:47.567354
1051 01:14:47.567437 Set Vref, RX VrefLevel [Byte0]: 56
1052 01:14:47.570420 [Byte1]: 56
1053 01:14:47.575055
1054 01:14:47.575142 Set Vref, RX VrefLevel [Byte0]: 57
1055 01:14:47.578150 [Byte1]: 57
1056 01:14:47.582751
1057 01:14:47.582833 Set Vref, RX VrefLevel [Byte0]: 58
1058 01:14:47.585510 [Byte1]: 58
1059 01:14:47.590021
1060 01:14:47.590146 Set Vref, RX VrefLevel [Byte0]: 59
1061 01:14:47.593260 [Byte1]: 59
1062 01:14:47.597878
1063 01:14:47.597963 Set Vref, RX VrefLevel [Byte0]: 60
1064 01:14:47.600884 [Byte1]: 60
1065 01:14:47.605651
1066 01:14:47.605735 Set Vref, RX VrefLevel [Byte0]: 61
1067 01:14:47.608905 [Byte1]: 61
1068 01:14:47.613170
1069 01:14:47.613252 Set Vref, RX VrefLevel [Byte0]: 62
1070 01:14:47.616253 [Byte1]: 62
1071 01:14:47.620690
1072 01:14:47.620799 Set Vref, RX VrefLevel [Byte0]: 63
1073 01:14:47.624016 [Byte1]: 63
1074 01:14:47.628166
1075 01:14:47.628249 Set Vref, RX VrefLevel [Byte0]: 64
1076 01:14:47.631910 [Byte1]: 64
1077 01:14:47.636015
1078 01:14:47.636098 Set Vref, RX VrefLevel [Byte0]: 65
1079 01:14:47.639236 [Byte1]: 65
1080 01:14:47.643652
1081 01:14:47.643734 Set Vref, RX VrefLevel [Byte0]: 66
1082 01:14:47.646815 [Byte1]: 66
1083 01:14:47.651489
1084 01:14:47.651573 Set Vref, RX VrefLevel [Byte0]: 67
1085 01:14:47.654318 [Byte1]: 67
1086 01:14:47.658626
1087 01:14:47.658710 Set Vref, RX VrefLevel [Byte0]: 68
1088 01:14:47.662249 [Byte1]: 68
1089 01:14:47.666816
1090 01:14:47.666901 Set Vref, RX VrefLevel [Byte0]: 69
1091 01:14:47.669989 [Byte1]: 69
1092 01:14:47.674503
1093 01:14:47.674587 Set Vref, RX VrefLevel [Byte0]: 70
1094 01:14:47.677327 [Byte1]: 70
1095 01:14:47.681768
1096 01:14:47.681853 Set Vref, RX VrefLevel [Byte0]: 71
1097 01:14:47.685121 [Byte1]: 71
1098 01:14:47.689299
1099 01:14:47.689382 Set Vref, RX VrefLevel [Byte0]: 72
1100 01:14:47.693013 [Byte1]: 72
1101 01:14:47.697175
1102 01:14:47.697261 Set Vref, RX VrefLevel [Byte0]: 73
1103 01:14:47.700396 [Byte1]: 73
1104 01:14:47.704537
1105 01:14:47.704621 Set Vref, RX VrefLevel [Byte0]: 74
1106 01:14:47.707804 [Byte1]: 74
1107 01:14:47.712631
1108 01:14:47.712714 Set Vref, RX VrefLevel [Byte0]: 75
1109 01:14:47.715503 [Byte1]: 75
1110 01:14:47.720147
1111 01:14:47.720230 Final RX Vref Byte 0 = 50 to rank0
1112 01:14:47.723553 Final RX Vref Byte 1 = 56 to rank0
1113 01:14:47.726744 Final RX Vref Byte 0 = 50 to rank1
1114 01:14:47.729950 Final RX Vref Byte 1 = 56 to rank1==
1115 01:14:47.733446 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 01:14:47.740381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1117 01:14:47.740475 ==
1118 01:14:47.740541 DQS Delay:
1119 01:14:47.740600 DQS0 = 0, DQS1 = 0
1120 01:14:47.743120 DQM Delay:
1121 01:14:47.743200 DQM0 = 83, DQM1 = 73
1122 01:14:47.746591 DQ Delay:
1123 01:14:47.749875 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1124 01:14:47.753271 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1125 01:14:47.756526 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1126 01:14:47.759641 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1127 01:14:47.759723
1128 01:14:47.759788
1129 01:14:47.766530 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1130 01:14:47.769795 CH0 RK0: MR19=606, MR18=3838
1131 01:14:47.776319 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1132 01:14:47.776409
1133 01:14:47.779936 ----->DramcWriteLeveling(PI) begin...
1134 01:14:47.780020 ==
1135 01:14:47.783237 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 01:14:47.786552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1137 01:14:47.786637 ==
1138 01:14:47.789873 Write leveling (Byte 0): 28 => 28
1139 01:14:47.793241 Write leveling (Byte 1): 29 => 29
1140 01:14:47.796449 DramcWriteLeveling(PI) end<-----
1141 01:14:47.796534
1142 01:14:47.796599 ==
1143 01:14:47.799526 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 01:14:47.803085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1145 01:14:47.803172 ==
1146 01:14:47.806201 [Gating] SW mode calibration
1147 01:14:47.812811 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 01:14:47.819667 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 01:14:47.822971 0 6 0 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (1 1)
1150 01:14:47.826596 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 01:14:47.833120 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 01:14:47.836292 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 01:14:47.839816 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 01:14:47.846376 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 01:14:47.849729 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 01:14:47.853084 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 01:14:47.860035 0 7 0 | B1->B0 | 2c2c 2e2e | 1 0 | (0 0) (0 0)
1158 01:14:47.863087 0 7 4 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
1159 01:14:47.866331 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1160 01:14:47.872662 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1161 01:14:47.876543 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1162 01:14:47.879411 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1163 01:14:47.885961 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1164 01:14:47.890158 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1165 01:14:47.894036 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1166 01:14:47.897538 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 01:14:47.901256 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 01:14:47.907959 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 01:14:47.911677 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 01:14:47.915030 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1171 01:14:47.918403 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1172 01:14:47.925382 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1173 01:14:47.928605 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1174 01:14:47.932021 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1175 01:14:47.939017 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1176 01:14:47.942041 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1177 01:14:47.945228 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1178 01:14:47.952182 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1179 01:14:47.955358 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1180 01:14:47.958818 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1181 01:14:47.965420 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1182 01:14:47.968628 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1183 01:14:47.971968 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 01:14:47.975356 Total UI for P1: 0, mck2ui 16
1185 01:14:47.978741 best dqsien dly found for B0: ( 0, 10, 4)
1186 01:14:47.981790 Total UI for P1: 0, mck2ui 16
1187 01:14:47.985361 best dqsien dly found for B1: ( 0, 10, 2)
1188 01:14:47.989104 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
1189 01:14:47.991963 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1190 01:14:47.992044
1191 01:14:47.995545 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
1192 01:14:48.002163 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1193 01:14:48.002247 [Gating] SW calibration Done
1194 01:14:48.002312 ==
1195 01:14:48.005350 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 01:14:48.012028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1197 01:14:48.012112 ==
1198 01:14:48.012178 RX Vref Scan: 0
1199 01:14:48.012238
1200 01:14:48.015331 RX Vref 0 -> 0, step: 1
1201 01:14:48.015412
1202 01:14:48.018611 RX Delay -130 -> 252, step: 16
1203 01:14:48.022378 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1204 01:14:48.025355 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1205 01:14:48.028473 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1206 01:14:48.035478 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1207 01:14:48.038684 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1208 01:14:48.041786 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1209 01:14:48.044987 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1210 01:14:48.048395 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1211 01:14:48.054950 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1212 01:14:48.058232 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1213 01:14:48.061556 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1214 01:14:48.065000 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1215 01:14:48.068211 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1216 01:14:48.075185 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1217 01:14:48.078302 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1218 01:14:48.081566 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1219 01:14:48.081646 ==
1220 01:14:48.085177 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 01:14:48.088354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 01:14:48.088434 ==
1223 01:14:48.091892 DQS Delay:
1224 01:14:48.091971 DQS0 = 0, DQS1 = 0
1225 01:14:48.095191 DQM Delay:
1226 01:14:48.095273 DQM0 = 81, DQM1 = 74
1227 01:14:48.095336 DQ Delay:
1228 01:14:48.098336 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1229 01:14:48.101778 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1230 01:14:48.105167 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1231 01:14:48.108381 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1232 01:14:48.108461
1233 01:14:48.108524
1234 01:14:48.111685 ==
1235 01:14:48.111764 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 01:14:48.118474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1237 01:14:48.118554 ==
1238 01:14:48.118617
1239 01:14:48.118674
1240 01:14:48.121692 TX Vref Scan disable
1241 01:14:48.121770 == TX Byte 0 ==
1242 01:14:48.124930 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1243 01:14:48.131485 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1244 01:14:48.131568 == TX Byte 1 ==
1245 01:14:48.134849 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1246 01:14:48.141523 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1247 01:14:48.141610 ==
1248 01:14:48.145211 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 01:14:48.148153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1250 01:14:48.148233 ==
1251 01:14:48.161351 TX Vref=22, minBit 0, minWin=27, winSum=448
1252 01:14:48.164610 TX Vref=24, minBit 2, minWin=28, winSum=453
1253 01:14:48.167824 TX Vref=26, minBit 2, minWin=28, winSum=454
1254 01:14:48.171225 TX Vref=28, minBit 2, minWin=28, winSum=459
1255 01:14:48.174839 TX Vref=30, minBit 2, minWin=28, winSum=458
1256 01:14:48.177631 TX Vref=32, minBit 0, minWin=28, winSum=460
1257 01:14:48.184409 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 32
1258 01:14:48.184490
1259 01:14:48.187629 Final TX Range 1 Vref 32
1260 01:14:48.187709
1261 01:14:48.187772 ==
1262 01:14:48.190995 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 01:14:48.194706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1264 01:14:48.194787 ==
1265 01:14:48.194850
1266 01:14:48.197487
1267 01:14:48.197565 TX Vref Scan disable
1268 01:14:48.201342 == TX Byte 0 ==
1269 01:14:48.204206 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1270 01:14:48.207961 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1271 01:14:48.210798 == TX Byte 1 ==
1272 01:14:48.214586 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1273 01:14:48.220931 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1274 01:14:48.221012
1275 01:14:48.221075 [DATLAT]
1276 01:14:48.221134 Freq=800, CH0 RK1
1277 01:14:48.221192
1278 01:14:48.224472 DATLAT Default: 0x9
1279 01:14:48.224552 0, 0xFFFF, sum = 0
1280 01:14:48.228535 1, 0xFFFF, sum = 0
1281 01:14:48.228619 2, 0xFFFF, sum = 0
1282 01:14:48.231232 3, 0xFFFF, sum = 0
1283 01:14:48.231312 4, 0xFFFF, sum = 0
1284 01:14:48.234320 5, 0xFFFF, sum = 0
1285 01:14:48.237708 6, 0xFFFF, sum = 0
1286 01:14:48.237793 7, 0xFFFF, sum = 0
1287 01:14:48.237858 8, 0x0, sum = 1
1288 01:14:48.241227 9, 0x0, sum = 2
1289 01:14:48.241308 10, 0x0, sum = 3
1290 01:14:48.244092 11, 0x0, sum = 4
1291 01:14:48.244173 best_step = 9
1292 01:14:48.244236
1293 01:14:48.244294 ==
1294 01:14:48.247580 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 01:14:48.253975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1296 01:14:48.254102 ==
1297 01:14:48.254166 RX Vref Scan: 0
1298 01:14:48.254228
1299 01:14:48.257319 RX Vref 0 -> 0, step: 1
1300 01:14:48.257400
1301 01:14:48.260865 RX Delay -111 -> 252, step: 8
1302 01:14:48.263915 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1303 01:14:48.267530 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1304 01:14:48.274402 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1305 01:14:48.277598 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1306 01:14:48.280836 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1307 01:14:48.284310 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1308 01:14:48.287730 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1309 01:14:48.294358 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1310 01:14:48.297453 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1311 01:14:48.300793 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1312 01:14:48.304115 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1313 01:14:48.307647 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1314 01:14:48.314188 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1315 01:14:48.317674 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1316 01:14:48.321577 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1317 01:14:48.324225 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1318 01:14:48.324318 ==
1319 01:14:48.327602 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 01:14:48.331025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1321 01:14:48.334296 ==
1322 01:14:48.334377 DQS Delay:
1323 01:14:48.334441 DQS0 = 0, DQS1 = 0
1324 01:14:48.337686 DQM Delay:
1325 01:14:48.337766 DQM0 = 84, DQM1 = 74
1326 01:14:48.341104 DQ Delay:
1327 01:14:48.341185 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1328 01:14:48.344593 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1329 01:14:48.347593 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1330 01:14:48.351093 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1331 01:14:48.351175
1332 01:14:48.354304
1333 01:14:48.361007 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1334 01:14:48.363982 CH0 RK1: MR19=606, MR18=3F3F
1335 01:14:48.371103 CH0_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1336 01:14:48.371185 [RxdqsGatingPostProcess] freq 800
1337 01:14:48.377570 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1338 01:14:48.380854 Pre-setting of DQS Precalculation
1339 01:14:48.384366 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1340 01:14:48.387812 ==
1341 01:14:48.390685 Dram Type= 6, Freq= 0, CH_1, rank 0
1342 01:14:48.394163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1343 01:14:48.394247 ==
1344 01:14:48.397371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1345 01:14:48.404075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1346 01:14:48.413632 [CA 0] Center 37 (6~68) winsize 63
1347 01:14:48.417152 [CA 1] Center 37 (6~68) winsize 63
1348 01:14:48.420477 [CA 2] Center 34 (4~65) winsize 62
1349 01:14:48.423714 [CA 3] Center 34 (4~65) winsize 62
1350 01:14:48.427019 [CA 4] Center 33 (3~64) winsize 62
1351 01:14:48.430369 [CA 5] Center 33 (3~64) winsize 62
1352 01:14:48.430451
1353 01:14:48.433864 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1354 01:14:48.433944
1355 01:14:48.436978 [CATrainingPosCal] consider 1 rank data
1356 01:14:48.440773 u2DelayCellTimex100 = 270/100 ps
1357 01:14:48.443704 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1358 01:14:48.450471 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1359 01:14:48.453550 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1360 01:14:48.457062 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1361 01:14:48.460454 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1362 01:14:48.463619 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1363 01:14:48.463703
1364 01:14:48.466873 CA PerBit enable=1, Macro0, CA PI delay=33
1365 01:14:48.466953
1366 01:14:48.470078 [CBTSetCACLKResult] CA Dly = 33
1367 01:14:48.470159 CS Dly: 4 (0~35)
1368 01:14:48.473395 ==
1369 01:14:48.476838 Dram Type= 6, Freq= 0, CH_1, rank 1
1370 01:14:48.480327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1371 01:14:48.480408 ==
1372 01:14:48.483464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 01:14:48.490620 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 01:14:48.499687 [CA 0] Center 36 (6~67) winsize 62
1375 01:14:48.503006 [CA 1] Center 37 (6~68) winsize 63
1376 01:14:48.506498 [CA 2] Center 34 (4~65) winsize 62
1377 01:14:48.509965 [CA 3] Center 34 (4~65) winsize 62
1378 01:14:48.512846 [CA 4] Center 33 (3~64) winsize 62
1379 01:14:48.516240 [CA 5] Center 33 (3~64) winsize 62
1380 01:14:48.516318
1381 01:14:48.519421 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1382 01:14:48.519499
1383 01:14:48.522769 [CATrainingPosCal] consider 2 rank data
1384 01:14:48.526282 u2DelayCellTimex100 = 270/100 ps
1385 01:14:48.529476 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1386 01:14:48.533434 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1387 01:14:48.539395 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 01:14:48.542667 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 01:14:48.545992 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 01:14:48.549350 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1391 01:14:48.549444
1392 01:14:48.552832 CA PerBit enable=1, Macro0, CA PI delay=33
1393 01:14:48.552911
1394 01:14:48.556659 [CBTSetCACLKResult] CA Dly = 33
1395 01:14:48.556738 CS Dly: 4 (0~36)
1396 01:14:48.556801
1397 01:14:48.560156 ----->DramcWriteLeveling(PI) begin...
1398 01:14:48.560236 ==
1399 01:14:48.563741 Dram Type= 6, Freq= 0, CH_1, rank 0
1400 01:14:48.567538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1401 01:14:48.567617 ==
1402 01:14:48.571203 Write leveling (Byte 0): 28 => 28
1403 01:14:48.575060 Write leveling (Byte 1): 24 => 24
1404 01:14:48.578808 DramcWriteLeveling(PI) end<-----
1405 01:14:48.578888
1406 01:14:48.578952 ==
1407 01:14:48.582262 Dram Type= 6, Freq= 0, CH_1, rank 0
1408 01:14:48.585973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1409 01:14:48.586093 ==
1410 01:14:48.589567 [Gating] SW mode calibration
1411 01:14:48.596592 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1412 01:14:48.599635 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1413 01:14:48.606302 0 6 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
1414 01:14:48.609758 0 6 4 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1415 01:14:48.613175 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1416 01:14:48.619621 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1417 01:14:48.622881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1418 01:14:48.626519 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1419 01:14:48.633001 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1420 01:14:48.636231 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1421 01:14:48.639288 0 7 0 | B1->B0 | 2f2f 3d3d | 1 0 | (0 0) (0 0)
1422 01:14:48.646136 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1423 01:14:48.649385 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1424 01:14:48.652827 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1425 01:14:48.659607 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1426 01:14:48.662528 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1427 01:14:48.665928 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1428 01:14:48.673153 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1429 01:14:48.675811 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1430 01:14:48.679165 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 01:14:48.685916 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 01:14:48.689112 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1433 01:14:48.692371 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1434 01:14:48.698971 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1435 01:14:48.702380 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1436 01:14:48.705591 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1437 01:14:48.712241 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1438 01:14:48.715725 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1439 01:14:48.718869 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1440 01:14:48.725488 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1441 01:14:48.728903 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1442 01:14:48.732679 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1443 01:14:48.738825 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1444 01:14:48.742072 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1445 01:14:48.745362 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1446 01:14:48.749099 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 01:14:48.752029 Total UI for P1: 0, mck2ui 16
1448 01:14:48.755843 best dqsien dly found for B0: ( 0, 9, 30)
1449 01:14:48.758803 Total UI for P1: 0, mck2ui 16
1450 01:14:48.762392 best dqsien dly found for B1: ( 0, 9, 30)
1451 01:14:48.765530 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1452 01:14:48.769234 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1453 01:14:48.772351
1454 01:14:48.775578 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1455 01:14:48.778828 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1456 01:14:48.782020 [Gating] SW calibration Done
1457 01:14:48.782152 ==
1458 01:14:48.785578 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 01:14:48.788886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1460 01:14:48.788967 ==
1461 01:14:48.789030 RX Vref Scan: 0
1462 01:14:48.789089
1463 01:14:48.792254 RX Vref 0 -> 0, step: 1
1464 01:14:48.792332
1465 01:14:48.795713 RX Delay -130 -> 252, step: 16
1466 01:14:48.799294 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1467 01:14:48.802335 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1468 01:14:48.808841 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1469 01:14:48.812247 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1470 01:14:48.815330 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1471 01:14:48.818791 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1472 01:14:48.822333 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1473 01:14:48.828728 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1474 01:14:48.831955 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1475 01:14:48.835482 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1476 01:14:48.838756 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1477 01:14:48.841800 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1478 01:14:48.848689 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1479 01:14:48.851993 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1480 01:14:48.855244 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1481 01:14:48.858386 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1482 01:14:48.858466 ==
1483 01:14:48.862484 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 01:14:48.868439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 01:14:48.868520 ==
1486 01:14:48.868584 DQS Delay:
1487 01:14:48.871976 DQS0 = 0, DQS1 = 0
1488 01:14:48.872060 DQM Delay:
1489 01:14:48.872122 DQM0 = 83, DQM1 = 74
1490 01:14:48.875242 DQ Delay:
1491 01:14:48.878269 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1492 01:14:48.881498 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =85
1493 01:14:48.884855 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1494 01:14:48.888240 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1495 01:14:48.888319
1496 01:14:48.888382
1497 01:14:48.888440 ==
1498 01:14:48.891751 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 01:14:48.895258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1500 01:14:48.895343 ==
1501 01:14:48.895405
1502 01:14:48.895464
1503 01:14:48.898303 TX Vref Scan disable
1504 01:14:48.901785 == TX Byte 0 ==
1505 01:14:48.904774 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1506 01:14:48.908503 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1507 01:14:48.911699 == TX Byte 1 ==
1508 01:14:48.914950 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1509 01:14:48.918008 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1510 01:14:48.918125 ==
1511 01:14:48.921821 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 01:14:48.924899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1513 01:14:48.924980 ==
1514 01:14:48.939414 TX Vref=22, minBit 3, minWin=27, winSum=448
1515 01:14:48.943006 TX Vref=24, minBit 11, minWin=27, winSum=450
1516 01:14:48.946281 TX Vref=26, minBit 0, minWin=28, winSum=456
1517 01:14:48.949605 TX Vref=28, minBit 0, minWin=28, winSum=458
1518 01:14:48.952779 TX Vref=30, minBit 0, minWin=28, winSum=457
1519 01:14:48.959626 TX Vref=32, minBit 0, minWin=28, winSum=457
1520 01:14:48.962848 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1521 01:14:48.962929
1522 01:14:48.966166 Final TX Range 1 Vref 28
1523 01:14:48.966247
1524 01:14:48.966309 ==
1525 01:14:48.969276 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 01:14:48.972853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1527 01:14:48.972935 ==
1528 01:14:48.976098
1529 01:14:48.976177
1530 01:14:48.976240 TX Vref Scan disable
1531 01:14:48.979678 == TX Byte 0 ==
1532 01:14:48.982850 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1533 01:14:48.989483 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1534 01:14:48.989565 == TX Byte 1 ==
1535 01:14:48.992792 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1536 01:14:48.999354 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1537 01:14:48.999440
1538 01:14:48.999504 [DATLAT]
1539 01:14:48.999574 Freq=800, CH1 RK0
1540 01:14:48.999635
1541 01:14:49.002690 DATLAT Default: 0xa
1542 01:14:49.002769 0, 0xFFFF, sum = 0
1543 01:14:49.006140 1, 0xFFFF, sum = 0
1544 01:14:49.006221 2, 0xFFFF, sum = 0
1545 01:14:49.009840 3, 0xFFFF, sum = 0
1546 01:14:49.009948 4, 0xFFFF, sum = 0
1547 01:14:49.012675 5, 0xFFFF, sum = 0
1548 01:14:49.016312 6, 0xFFFF, sum = 0
1549 01:14:49.016394 7, 0xFFFF, sum = 0
1550 01:14:49.016457 8, 0x0, sum = 1
1551 01:14:49.019420 9, 0x0, sum = 2
1552 01:14:49.019527 10, 0x0, sum = 3
1553 01:14:49.022676 11, 0x0, sum = 4
1554 01:14:49.022760 best_step = 9
1555 01:14:49.022822
1556 01:14:49.022880 ==
1557 01:14:49.026341 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 01:14:49.033111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1559 01:14:49.033193 ==
1560 01:14:49.033255 RX Vref Scan: 1
1561 01:14:49.033314
1562 01:14:49.036242 Set Vref Range= 32 -> 127
1563 01:14:49.036322
1564 01:14:49.039492 RX Vref 32 -> 127, step: 1
1565 01:14:49.039572
1566 01:14:49.039634 RX Delay -111 -> 252, step: 8
1567 01:14:49.042866
1568 01:14:49.042946 Set Vref, RX VrefLevel [Byte0]: 32
1569 01:14:49.046209 [Byte1]: 32
1570 01:14:49.050477
1571 01:14:49.050556 Set Vref, RX VrefLevel [Byte0]: 33
1572 01:14:49.054193 [Byte1]: 33
1573 01:14:49.058316
1574 01:14:49.058396 Set Vref, RX VrefLevel [Byte0]: 34
1575 01:14:49.061400 [Byte1]: 34
1576 01:14:49.065868
1577 01:14:49.065948 Set Vref, RX VrefLevel [Byte0]: 35
1578 01:14:49.069686 [Byte1]: 35
1579 01:14:49.073497
1580 01:14:49.073577 Set Vref, RX VrefLevel [Byte0]: 36
1581 01:14:49.076601 [Byte1]: 36
1582 01:14:49.081519
1583 01:14:49.081600 Set Vref, RX VrefLevel [Byte0]: 37
1584 01:14:49.084519 [Byte1]: 37
1585 01:14:49.088913
1586 01:14:49.088993 Set Vref, RX VrefLevel [Byte0]: 38
1587 01:14:49.092159 [Byte1]: 38
1588 01:14:49.096354
1589 01:14:49.096436 Set Vref, RX VrefLevel [Byte0]: 39
1590 01:14:49.100169 [Byte1]: 39
1591 01:14:49.104024
1592 01:14:49.104104 Set Vref, RX VrefLevel [Byte0]: 40
1593 01:14:49.107475 [Byte1]: 40
1594 01:14:49.111988
1595 01:14:49.112068 Set Vref, RX VrefLevel [Byte0]: 41
1596 01:14:49.114927 [Byte1]: 41
1597 01:14:49.119566
1598 01:14:49.119655 Set Vref, RX VrefLevel [Byte0]: 42
1599 01:14:49.122524 [Byte1]: 42
1600 01:14:49.126920
1601 01:14:49.130323 Set Vref, RX VrefLevel [Byte0]: 43
1602 01:14:49.133725 [Byte1]: 43
1603 01:14:49.133806
1604 01:14:49.137777 Set Vref, RX VrefLevel [Byte0]: 44
1605 01:14:49.140653 [Byte1]: 44
1606 01:14:49.140729
1607 01:14:49.143899 Set Vref, RX VrefLevel [Byte0]: 45
1608 01:14:49.147793 [Byte1]: 45
1609 01:14:49.147865
1610 01:14:49.150616 Set Vref, RX VrefLevel [Byte0]: 46
1611 01:14:49.153954 [Byte1]: 46
1612 01:14:49.157391
1613 01:14:49.157471 Set Vref, RX VrefLevel [Byte0]: 47
1614 01:14:49.160959 [Byte1]: 47
1615 01:14:49.165222
1616 01:14:49.165303 Set Vref, RX VrefLevel [Byte0]: 48
1617 01:14:49.168357 [Byte1]: 48
1618 01:14:49.173168
1619 01:14:49.173255 Set Vref, RX VrefLevel [Byte0]: 49
1620 01:14:49.176119 [Byte1]: 49
1621 01:14:49.180986
1622 01:14:49.181067 Set Vref, RX VrefLevel [Byte0]: 50
1623 01:14:49.183873 [Byte1]: 50
1624 01:14:49.188097
1625 01:14:49.188179 Set Vref, RX VrefLevel [Byte0]: 51
1626 01:14:49.191694 [Byte1]: 51
1627 01:14:49.195646
1628 01:14:49.195729 Set Vref, RX VrefLevel [Byte0]: 52
1629 01:14:49.199129 [Byte1]: 52
1630 01:14:49.203717
1631 01:14:49.203799 Set Vref, RX VrefLevel [Byte0]: 53
1632 01:14:49.207007 [Byte1]: 53
1633 01:14:49.211059
1634 01:14:49.211140 Set Vref, RX VrefLevel [Byte0]: 54
1635 01:14:49.214877 [Byte1]: 54
1636 01:14:49.218672
1637 01:14:49.218758 Set Vref, RX VrefLevel [Byte0]: 55
1638 01:14:49.222112 [Byte1]: 55
1639 01:14:49.226458
1640 01:14:49.226544 Set Vref, RX VrefLevel [Byte0]: 56
1641 01:14:49.229890 [Byte1]: 56
1642 01:14:49.234486
1643 01:14:49.234586 Set Vref, RX VrefLevel [Byte0]: 57
1644 01:14:49.237798 [Byte1]: 57
1645 01:14:49.241698
1646 01:14:49.241807 Set Vref, RX VrefLevel [Byte0]: 58
1647 01:14:49.244960 [Byte1]: 58
1648 01:14:49.249209
1649 01:14:49.249284 Set Vref, RX VrefLevel [Byte0]: 59
1650 01:14:49.252587 [Byte1]: 59
1651 01:14:49.256828
1652 01:14:49.256927 Set Vref, RX VrefLevel [Byte0]: 60
1653 01:14:49.260251 [Byte1]: 60
1654 01:14:49.264612
1655 01:14:49.264719 Set Vref, RX VrefLevel [Byte0]: 61
1656 01:14:49.268002 [Byte1]: 61
1657 01:14:49.272514
1658 01:14:49.272614 Set Vref, RX VrefLevel [Byte0]: 62
1659 01:14:49.275414 [Byte1]: 62
1660 01:14:49.279863
1661 01:14:49.279965 Set Vref, RX VrefLevel [Byte0]: 63
1662 01:14:49.283260 [Byte1]: 63
1663 01:14:49.287781
1664 01:14:49.287887 Set Vref, RX VrefLevel [Byte0]: 64
1665 01:14:49.290783 [Byte1]: 64
1666 01:14:49.295192
1667 01:14:49.295311 Set Vref, RX VrefLevel [Byte0]: 65
1668 01:14:49.298450 [Byte1]: 65
1669 01:14:49.302644
1670 01:14:49.302718 Set Vref, RX VrefLevel [Byte0]: 66
1671 01:14:49.306241 [Byte1]: 66
1672 01:14:49.310638
1673 01:14:49.310706 Set Vref, RX VrefLevel [Byte0]: 67
1674 01:14:49.313940 [Byte1]: 67
1675 01:14:49.317918
1676 01:14:49.318014 Set Vref, RX VrefLevel [Byte0]: 68
1677 01:14:49.321659 [Byte1]: 68
1678 01:14:49.325730
1679 01:14:49.325849 Set Vref, RX VrefLevel [Byte0]: 69
1680 01:14:49.329206 [Byte1]: 69
1681 01:14:49.333305
1682 01:14:49.333377 Set Vref, RX VrefLevel [Byte0]: 70
1683 01:14:49.336755 [Byte1]: 70
1684 01:14:49.341527
1685 01:14:49.341601 Set Vref, RX VrefLevel [Byte0]: 71
1686 01:14:49.344384 [Byte1]: 71
1687 01:14:49.348772
1688 01:14:49.348850 Set Vref, RX VrefLevel [Byte0]: 72
1689 01:14:49.352047 [Byte1]: 72
1690 01:14:49.356656
1691 01:14:49.356728 Set Vref, RX VrefLevel [Byte0]: 73
1692 01:14:49.359506 [Byte1]: 73
1693 01:14:49.363869
1694 01:14:49.363942 Set Vref, RX VrefLevel [Byte0]: 74
1695 01:14:49.367183 [Byte1]: 74
1696 01:14:49.371765
1697 01:14:49.371840 Set Vref, RX VrefLevel [Byte0]: 75
1698 01:14:49.375037 [Byte1]: 75
1699 01:14:49.379640
1700 01:14:49.379721 Set Vref, RX VrefLevel [Byte0]: 76
1701 01:14:49.382802 [Byte1]: 76
1702 01:14:49.387268
1703 01:14:49.387344 Final RX Vref Byte 0 = 58 to rank0
1704 01:14:49.390089 Final RX Vref Byte 1 = 52 to rank0
1705 01:14:49.393475 Final RX Vref Byte 0 = 58 to rank1
1706 01:14:49.397043 Final RX Vref Byte 1 = 52 to rank1==
1707 01:14:49.400191 Dram Type= 6, Freq= 0, CH_1, rank 0
1708 01:14:49.407198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1709 01:14:49.407286 ==
1710 01:14:49.407360 DQS Delay:
1711 01:14:49.407420 DQS0 = 0, DQS1 = 0
1712 01:14:49.410147 DQM Delay:
1713 01:14:49.410247 DQM0 = 80, DQM1 = 75
1714 01:14:49.413551 DQ Delay:
1715 01:14:49.416767 DQ0 =88, DQ1 =72, DQ2 =72, DQ3 =76
1716 01:14:49.420102 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1717 01:14:49.423712 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1718 01:14:49.426653 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1719 01:14:49.426724
1720 01:14:49.426785
1721 01:14:49.433186 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1722 01:14:49.436561 CH1 RK0: MR19=606, MR18=4E4E
1723 01:14:49.443230 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1724 01:14:49.443332
1725 01:14:49.446499 ----->DramcWriteLeveling(PI) begin...
1726 01:14:49.446581 ==
1727 01:14:49.450009 Dram Type= 6, Freq= 0, CH_1, rank 1
1728 01:14:49.453472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1729 01:14:49.453548 ==
1730 01:14:49.456745 Write leveling (Byte 0): 24 => 24
1731 01:14:49.460393 Write leveling (Byte 1): 23 => 23
1732 01:14:49.463279 DramcWriteLeveling(PI) end<-----
1733 01:14:49.463349
1734 01:14:49.463409 ==
1735 01:14:49.466607 Dram Type= 6, Freq= 0, CH_1, rank 1
1736 01:14:49.470054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1737 01:14:49.470139 ==
1738 01:14:49.473490 [Gating] SW mode calibration
1739 01:14:49.480081 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1740 01:14:49.486538 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1741 01:14:49.489635 0 6 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1742 01:14:49.493047 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1743 01:14:49.499706 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1744 01:14:49.503007 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1745 01:14:49.506171 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1746 01:14:49.512967 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1747 01:14:49.516762 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1748 01:14:49.519753 0 6 28 | B1->B0 | 2323 2a2a | 1 0 | (0 0) (0 0)
1749 01:14:49.526109 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1750 01:14:49.529383 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1751 01:14:49.532613 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1752 01:14:49.539278 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1753 01:14:49.542521 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1754 01:14:49.546102 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1755 01:14:49.552487 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1756 01:14:49.556045 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1757 01:14:49.559327 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1758 01:14:49.566019 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1759 01:14:49.569150 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1760 01:14:49.572762 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1761 01:14:49.579050 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1762 01:14:49.582361 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1763 01:14:49.585643 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1764 01:14:49.592217 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1765 01:14:49.595786 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1766 01:14:49.599328 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1767 01:14:49.605728 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1768 01:14:49.608806 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1769 01:14:49.612153 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1770 01:14:49.619019 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1771 01:14:49.622208 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1772 01:14:49.625607 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1773 01:14:49.632390 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1774 01:14:49.632470 Total UI for P1: 0, mck2ui 16
1775 01:14:49.638895 best dqsien dly found for B0: ( 0, 9, 26)
1776 01:14:49.642241 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 01:14:49.645504 Total UI for P1: 0, mck2ui 16
1778 01:14:49.648868 best dqsien dly found for B1: ( 0, 9, 30)
1779 01:14:49.652177 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1780 01:14:49.655485 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1781 01:14:49.655587
1782 01:14:49.659751 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1783 01:14:49.662112 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1784 01:14:49.665708 [Gating] SW calibration Done
1785 01:14:49.665812 ==
1786 01:14:49.669147 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 01:14:49.672868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1788 01:14:49.672941 ==
1789 01:14:49.675446 RX Vref Scan: 0
1790 01:14:49.675517
1791 01:14:49.678732 RX Vref 0 -> 0, step: 1
1792 01:14:49.678803
1793 01:14:49.681977 RX Delay -130 -> 252, step: 16
1794 01:14:49.685645 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1795 01:14:49.688674 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1796 01:14:49.692288 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1797 01:14:49.695317 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1798 01:14:49.702287 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1799 01:14:49.705603 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1800 01:14:49.708801 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1801 01:14:49.711989 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1802 01:14:49.715441 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1803 01:14:49.721861 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1804 01:14:49.725302 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1805 01:14:49.728369 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1806 01:14:49.731965 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1807 01:14:49.735247 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1808 01:14:49.741956 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1809 01:14:49.745881 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1810 01:14:49.745986 ==
1811 01:14:49.748616 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 01:14:49.751898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1813 01:14:49.751996 ==
1814 01:14:49.755263 DQS Delay:
1815 01:14:49.755374 DQS0 = 0, DQS1 = 0
1816 01:14:49.755463 DQM Delay:
1817 01:14:49.758913 DQM0 = 85, DQM1 = 73
1818 01:14:49.758987 DQ Delay:
1819 01:14:49.761653 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1820 01:14:49.765150 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1821 01:14:49.768257 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1822 01:14:49.772029 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1823 01:14:49.772133
1824 01:14:49.772224
1825 01:14:49.772311 ==
1826 01:14:49.775126 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 01:14:49.781703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1828 01:14:49.781811 ==
1829 01:14:49.781902
1830 01:14:49.781989
1831 01:14:49.782082 TX Vref Scan disable
1832 01:14:49.785481 == TX Byte 0 ==
1833 01:14:49.788690 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1834 01:14:49.792161 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1835 01:14:49.795627 == TX Byte 1 ==
1836 01:14:49.798715 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1837 01:14:49.801908 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1838 01:14:49.805082 ==
1839 01:14:49.809007 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 01:14:49.811766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 01:14:49.811847 ==
1842 01:14:49.824255 TX Vref=22, minBit 0, minWin=28, winSum=452
1843 01:14:49.827659 TX Vref=24, minBit 0, minWin=28, winSum=453
1844 01:14:49.831006 TX Vref=26, minBit 0, minWin=28, winSum=458
1845 01:14:49.834000 TX Vref=28, minBit 9, minWin=27, winSum=458
1846 01:14:49.837487 TX Vref=30, minBit 9, minWin=27, winSum=455
1847 01:14:49.841030 TX Vref=32, minBit 0, minWin=28, winSum=456
1848 01:14:49.847517 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 26
1849 01:14:49.847603
1850 01:14:49.851046 Final TX Range 1 Vref 26
1851 01:14:49.851121
1852 01:14:49.851183 ==
1853 01:14:49.854104 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 01:14:49.857306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1855 01:14:49.857384 ==
1856 01:14:49.857445
1857 01:14:49.860522
1858 01:14:49.860628 TX Vref Scan disable
1859 01:14:49.864270 == TX Byte 0 ==
1860 01:14:49.867261 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1861 01:14:49.874347 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1862 01:14:49.874431 == TX Byte 1 ==
1863 01:14:49.877710 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1864 01:14:49.883744 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1865 01:14:49.883821
1866 01:14:49.883893 [DATLAT]
1867 01:14:49.883957 Freq=800, CH1 RK1
1868 01:14:49.884015
1869 01:14:49.887296 DATLAT Default: 0x9
1870 01:14:49.887375 0, 0xFFFF, sum = 0
1871 01:14:49.890846 1, 0xFFFF, sum = 0
1872 01:14:49.890927 2, 0xFFFF, sum = 0
1873 01:14:49.894158 3, 0xFFFF, sum = 0
1874 01:14:49.897574 4, 0xFFFF, sum = 0
1875 01:14:49.897686 5, 0xFFFF, sum = 0
1876 01:14:49.900467 6, 0xFFFF, sum = 0
1877 01:14:49.900586 7, 0xFFFF, sum = 0
1878 01:14:49.903699 8, 0x0, sum = 1
1879 01:14:49.903775 9, 0x0, sum = 2
1880 01:14:49.903847 10, 0x0, sum = 3
1881 01:14:49.907297 11, 0x0, sum = 4
1882 01:14:49.907378 best_step = 9
1883 01:14:49.907440
1884 01:14:49.907498 ==
1885 01:14:49.910417 Dram Type= 6, Freq= 0, CH_1, rank 1
1886 01:14:49.917566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1887 01:14:49.917675 ==
1888 01:14:49.917769 RX Vref Scan: 0
1889 01:14:49.917877
1890 01:14:49.920591 RX Vref 0 -> 0, step: 1
1891 01:14:49.920688
1892 01:14:49.924009 RX Delay -111 -> 252, step: 8
1893 01:14:49.927912 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1894 01:14:49.930526 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1895 01:14:49.937350 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1896 01:14:49.940477 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1897 01:14:49.943960 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1898 01:14:49.947712 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1899 01:14:49.950361 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1900 01:14:49.957241 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1901 01:14:49.960327 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1902 01:14:49.963615 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1903 01:14:49.967251 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1904 01:14:49.970612 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1905 01:14:49.977001 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1906 01:14:49.980528 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1907 01:14:49.983985 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1908 01:14:49.987113 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1909 01:14:49.987196 ==
1910 01:14:49.990367 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 01:14:49.997014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1912 01:14:49.997127 ==
1913 01:14:49.997218 DQS Delay:
1914 01:14:50.000582 DQS0 = 0, DQS1 = 0
1915 01:14:50.000663 DQM Delay:
1916 01:14:50.000725 DQM0 = 83, DQM1 = 75
1917 01:14:50.004094 DQ Delay:
1918 01:14:50.006802 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =80
1919 01:14:50.010414 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1920 01:14:50.013766 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1921 01:14:50.016827 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1922 01:14:50.016907
1923 01:14:50.016970
1924 01:14:50.023589 [DQSOSCAuto] RK1, (LSB)MR18= 0x3434, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1925 01:14:50.026805 CH1 RK1: MR19=606, MR18=3434
1926 01:14:50.033253 CH1_RK1: MR19=0x606, MR18=0x3434, DQSOSC=396, MR23=63, INC=94, DEC=62
1927 01:14:50.036531 [RxdqsGatingPostProcess] freq 800
1928 01:14:50.040003 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1929 01:14:50.043224 Pre-setting of DQS Precalculation
1930 01:14:50.050270 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1931 01:14:50.056641 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1932 01:14:50.063562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1933 01:14:50.063649
1934 01:14:50.063713
1935 01:14:50.066760 [Calibration Summary] 1600 Mbps
1936 01:14:50.066841 CH 0, Rank 0
1937 01:14:50.069894 SW Impedance : PASS
1938 01:14:50.073438 DUTY Scan : NO K
1939 01:14:50.073520 ZQ Calibration : PASS
1940 01:14:50.077192 Jitter Meter : NO K
1941 01:14:50.080068 CBT Training : PASS
1942 01:14:50.080149 Write leveling : PASS
1943 01:14:50.083254 RX DQS gating : PASS
1944 01:14:50.083336 RX DQ/DQS(RDDQC) : PASS
1945 01:14:50.086825 TX DQ/DQS : PASS
1946 01:14:50.090314 RX DATLAT : PASS
1947 01:14:50.090395 RX DQ/DQS(Engine): PASS
1948 01:14:50.093783 TX OE : NO K
1949 01:14:50.093865 All Pass.
1950 01:14:50.093928
1951 01:14:50.096537 CH 0, Rank 1
1952 01:14:50.096656 SW Impedance : PASS
1953 01:14:50.099940 DUTY Scan : NO K
1954 01:14:50.103492 ZQ Calibration : PASS
1955 01:14:50.103572 Jitter Meter : NO K
1956 01:14:50.106633 CBT Training : PASS
1957 01:14:50.110124 Write leveling : PASS
1958 01:14:50.110204 RX DQS gating : PASS
1959 01:14:50.113639 RX DQ/DQS(RDDQC) : PASS
1960 01:14:50.116959 TX DQ/DQS : PASS
1961 01:14:50.117042 RX DATLAT : PASS
1962 01:14:50.119785 RX DQ/DQS(Engine): PASS
1963 01:14:50.123545 TX OE : NO K
1964 01:14:50.123626 All Pass.
1965 01:14:50.123776
1966 01:14:50.123837 CH 1, Rank 0
1967 01:14:50.126405 SW Impedance : PASS
1968 01:14:50.129737 DUTY Scan : NO K
1969 01:14:50.129843 ZQ Calibration : PASS
1970 01:14:50.133229 Jitter Meter : NO K
1971 01:14:50.136399 CBT Training : PASS
1972 01:14:50.136480 Write leveling : PASS
1973 01:14:50.139552 RX DQS gating : PASS
1974 01:14:50.139633 RX DQ/DQS(RDDQC) : PASS
1975 01:14:50.143429 TX DQ/DQS : PASS
1976 01:14:50.146225 RX DATLAT : PASS
1977 01:14:50.146305 RX DQ/DQS(Engine): PASS
1978 01:14:50.149700 TX OE : NO K
1979 01:14:50.149780 All Pass.
1980 01:14:50.149843
1981 01:14:50.152864 CH 1, Rank 1
1982 01:14:50.152943 SW Impedance : PASS
1983 01:14:50.156486 DUTY Scan : NO K
1984 01:14:50.159751 ZQ Calibration : PASS
1985 01:14:50.159832 Jitter Meter : NO K
1986 01:14:50.163051 CBT Training : PASS
1987 01:14:50.166271 Write leveling : PASS
1988 01:14:50.166352 RX DQS gating : PASS
1989 01:14:50.169463 RX DQ/DQS(RDDQC) : PASS
1990 01:14:50.172801 TX DQ/DQS : PASS
1991 01:14:50.172882 RX DATLAT : PASS
1992 01:14:50.176203 RX DQ/DQS(Engine): PASS
1993 01:14:50.179747 TX OE : NO K
1994 01:14:50.179840 All Pass.
1995 01:14:50.179914
1996 01:14:50.179978 DramC Write-DBI off
1997 01:14:50.182902 PER_BANK_REFRESH: Hybrid Mode
1998 01:14:50.186696 TX_TRACKING: ON
1999 01:14:50.189928 [GetDramInforAfterCalByMRR] Vendor 6.
2000 01:14:50.193135 [GetDramInforAfterCalByMRR] Revision 606.
2001 01:14:50.196373 [GetDramInforAfterCalByMRR] Revision 2 0.
2002 01:14:50.196457 MR0 0x3939
2003 01:14:50.199591 MR8 0x1111
2004 01:14:50.203267 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2005 01:14:50.203350
2006 01:14:50.203414 MR0 0x3939
2007 01:14:50.203473 MR8 0x1111
2008 01:14:50.206717 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2009 01:14:50.206801
2010 01:14:50.216236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2011 01:14:50.219419 [FAST_K] Save calibration result to emmc
2012 01:14:50.223290 [FAST_K] Save calibration result to emmc
2013 01:14:50.226408 dram_init: config_dvfs: 1
2014 01:14:50.229490 dramc_set_vcore_voltage set vcore to 662500
2015 01:14:50.232984 Read voltage for 1200, 2
2016 01:14:50.233068 Vio18 = 0
2017 01:14:50.236173 Vcore = 662500
2018 01:14:50.236254 Vdram = 0
2019 01:14:50.236318 Vddq = 0
2020 01:14:50.236377 Vmddr = 0
2021 01:14:50.242866 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2022 01:14:50.249689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2023 01:14:50.249801 MEM_TYPE=3, freq_sel=15
2024 01:14:50.252830 sv_algorithm_assistance_LP4_1600
2025 01:14:50.256242 ============ PULL DRAM RESETB DOWN ============
2026 01:14:50.262767 ========== PULL DRAM RESETB DOWN end =========
2027 01:14:50.266202 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2028 01:14:50.269598 ===================================
2029 01:14:50.272616 LPDDR4 DRAM CONFIGURATION
2030 01:14:50.276109 ===================================
2031 01:14:50.276195 EX_ROW_EN[0] = 0x0
2032 01:14:50.279189 EX_ROW_EN[1] = 0x0
2033 01:14:50.279271 LP4Y_EN = 0x0
2034 01:14:50.282733 WORK_FSP = 0x0
2035 01:14:50.282815 WL = 0x4
2036 01:14:50.285972 RL = 0x4
2037 01:14:50.286102 BL = 0x2
2038 01:14:50.289589 RPST = 0x0
2039 01:14:50.292869 RD_PRE = 0x0
2040 01:14:50.292996 WR_PRE = 0x1
2041 01:14:50.295662 WR_PST = 0x0
2042 01:14:50.295743 DBI_WR = 0x0
2043 01:14:50.299212 DBI_RD = 0x0
2044 01:14:50.299296 OTF = 0x1
2045 01:14:50.302573 ===================================
2046 01:14:50.305748 ===================================
2047 01:14:50.309726 ANA top config
2048 01:14:50.309809 ===================================
2049 01:14:50.312339 DLL_ASYNC_EN = 0
2050 01:14:50.316179 ALL_SLAVE_EN = 0
2051 01:14:50.319526 NEW_RANK_MODE = 1
2052 01:14:50.323005 DLL_IDLE_MODE = 1
2053 01:14:50.323087 LP45_APHY_COMB_EN = 1
2054 01:14:50.325850 TX_ODT_DIS = 1
2055 01:14:50.328978 NEW_8X_MODE = 1
2056 01:14:50.332696 ===================================
2057 01:14:50.336120 ===================================
2058 01:14:50.338994 data_rate = 2400
2059 01:14:50.342574 CKR = 1
2060 01:14:50.342670 DQ_P2S_RATIO = 8
2061 01:14:50.346000 ===================================
2062 01:14:50.349117 CA_P2S_RATIO = 8
2063 01:14:50.352522 DQ_CA_OPEN = 0
2064 01:14:50.355774 DQ_SEMI_OPEN = 0
2065 01:14:50.359477 CA_SEMI_OPEN = 0
2066 01:14:50.362168 CA_FULL_RATE = 0
2067 01:14:50.362250 DQ_CKDIV4_EN = 0
2068 01:14:50.365695 CA_CKDIV4_EN = 0
2069 01:14:50.368790 CA_PREDIV_EN = 0
2070 01:14:50.372470 PH8_DLY = 17
2071 01:14:50.375632 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2072 01:14:50.378904 DQ_AAMCK_DIV = 4
2073 01:14:50.378986 CA_AAMCK_DIV = 4
2074 01:14:50.382371 CA_ADMCK_DIV = 4
2075 01:14:50.385446 DQ_TRACK_CA_EN = 0
2076 01:14:50.389184 CA_PICK = 1200
2077 01:14:50.392471 CA_MCKIO = 1200
2078 01:14:50.395372 MCKIO_SEMI = 0
2079 01:14:50.399028 PLL_FREQ = 2366
2080 01:14:50.402181 DQ_UI_PI_RATIO = 32
2081 01:14:50.402261 CA_UI_PI_RATIO = 0
2082 01:14:50.405442 ===================================
2083 01:14:50.408833 ===================================
2084 01:14:50.412092 memory_type:LPDDR4
2085 01:14:50.415232 GP_NUM : 10
2086 01:14:50.415313 SRAM_EN : 1
2087 01:14:50.418602 MD32_EN : 0
2088 01:14:50.421868 ===================================
2089 01:14:50.425546 [ANA_INIT] >>>>>>>>>>>>>>
2090 01:14:50.425626 <<<<<< [CONFIGURE PHASE]: ANA_TX
2091 01:14:50.432168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2092 01:14:50.435719 ===================================
2093 01:14:50.435799 data_rate = 2400,PCW = 0X5b00
2094 01:14:50.438584 ===================================
2095 01:14:50.441983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2096 01:14:50.448572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2097 01:14:50.455118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2098 01:14:50.458653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2099 01:14:50.461938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2100 01:14:50.465385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2101 01:14:50.468661 [ANA_INIT] flow start
2102 01:14:50.468740 [ANA_INIT] PLL >>>>>>>>
2103 01:14:50.471856 [ANA_INIT] PLL <<<<<<<<
2104 01:14:50.475195 [ANA_INIT] MIDPI >>>>>>>>
2105 01:14:50.475275 [ANA_INIT] MIDPI <<<<<<<<
2106 01:14:50.478651 [ANA_INIT] DLL >>>>>>>>
2107 01:14:50.481759 [ANA_INIT] DLL <<<<<<<<
2108 01:14:50.481872 [ANA_INIT] flow end
2109 01:14:50.488764 ============ LP4 DIFF to SE enter ============
2110 01:14:50.492014 ============ LP4 DIFF to SE exit ============
2111 01:14:50.495755 [ANA_INIT] <<<<<<<<<<<<<
2112 01:14:50.498518 [Flow] Enable top DCM control >>>>>
2113 01:14:50.501753 [Flow] Enable top DCM control <<<<<
2114 01:14:50.501832 Enable DLL master slave shuffle
2115 01:14:50.508573 ==============================================================
2116 01:14:50.511708 Gating Mode config
2117 01:14:50.515606 ==============================================================
2118 01:14:50.518523 Config description:
2119 01:14:50.528481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2120 01:14:50.535149 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2121 01:14:50.538696 SELPH_MODE 0: By rank 1: By Phase
2122 01:14:50.544996 ==============================================================
2123 01:14:50.548854 GAT_TRACK_EN = 1
2124 01:14:50.551611 RX_GATING_MODE = 2
2125 01:14:50.555217 RX_GATING_TRACK_MODE = 2
2126 01:14:50.558431 SELPH_MODE = 1
2127 01:14:50.558511 PICG_EARLY_EN = 1
2128 01:14:50.562324 VALID_LAT_VALUE = 1
2129 01:14:50.568500 ==============================================================
2130 01:14:50.571933 Enter into Gating configuration >>>>
2131 01:14:50.575156 Exit from Gating configuration <<<<
2132 01:14:50.578383 Enter into DVFS_PRE_config >>>>>
2133 01:14:50.588436 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2134 01:14:50.591593 Exit from DVFS_PRE_config <<<<<
2135 01:14:50.595029 Enter into PICG configuration >>>>
2136 01:14:50.598397 Exit from PICG configuration <<<<
2137 01:14:50.601939 [RX_INPUT] configuration >>>>>
2138 01:14:50.604976 [RX_INPUT] configuration <<<<<
2139 01:14:50.608642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2140 01:14:50.615042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2141 01:14:50.621729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2142 01:14:50.628265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2143 01:14:50.635292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2144 01:14:50.638074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2145 01:14:50.644765 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2146 01:14:50.648123 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2147 01:14:50.651665 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2148 01:14:50.655099 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2149 01:14:50.658615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2150 01:14:50.665264 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2151 01:14:50.668386 ===================================
2152 01:14:50.671573 LPDDR4 DRAM CONFIGURATION
2153 01:14:50.675164 ===================================
2154 01:14:50.675245 EX_ROW_EN[0] = 0x0
2155 01:14:50.678050 EX_ROW_EN[1] = 0x0
2156 01:14:50.678145 LP4Y_EN = 0x0
2157 01:14:50.681612 WORK_FSP = 0x0
2158 01:14:50.681692 WL = 0x4
2159 01:14:50.685020 RL = 0x4
2160 01:14:50.685100 BL = 0x2
2161 01:14:50.688229 RPST = 0x0
2162 01:14:50.688310 RD_PRE = 0x0
2163 01:14:50.692000 WR_PRE = 0x1
2164 01:14:50.692080 WR_PST = 0x0
2165 01:14:50.694516 DBI_WR = 0x0
2166 01:14:50.694597 DBI_RD = 0x0
2167 01:14:50.697839 OTF = 0x1
2168 01:14:50.701127 ===================================
2169 01:14:50.704732 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2170 01:14:50.707807 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2171 01:14:50.714347 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2172 01:14:50.717754 ===================================
2173 01:14:50.717837 LPDDR4 DRAM CONFIGURATION
2174 01:14:50.721315 ===================================
2175 01:14:50.724458 EX_ROW_EN[0] = 0x10
2176 01:14:50.727908 EX_ROW_EN[1] = 0x0
2177 01:14:50.728045 LP4Y_EN = 0x0
2178 01:14:50.731182 WORK_FSP = 0x0
2179 01:14:50.731263 WL = 0x4
2180 01:14:50.734472 RL = 0x4
2181 01:14:50.734552 BL = 0x2
2182 01:14:50.737690 RPST = 0x0
2183 01:14:50.737771 RD_PRE = 0x0
2184 01:14:50.741293 WR_PRE = 0x1
2185 01:14:50.741374 WR_PST = 0x0
2186 01:14:50.744792 DBI_WR = 0x0
2187 01:14:50.744872 DBI_RD = 0x0
2188 01:14:50.747704 OTF = 0x1
2189 01:14:50.751109 ===================================
2190 01:14:50.757836 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2191 01:14:50.757918 ==
2192 01:14:50.760934 Dram Type= 6, Freq= 0, CH_0, rank 0
2193 01:14:50.764209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2194 01:14:50.764291 ==
2195 01:14:50.767581 [Duty_Offset_Calibration]
2196 01:14:50.767662 B0:0 B1:2 CA:1
2197 01:14:50.767725
2198 01:14:50.771384 [DutyScan_Calibration_Flow] k_type=0
2199 01:14:50.781401
2200 01:14:50.781482 ==CLK 0==
2201 01:14:50.785122 Final CLK duty delay cell = 0
2202 01:14:50.788045 [0] MAX Duty = 5093%(X100), DQS PI = 12
2203 01:14:50.791354 [0] MIN Duty = 4938%(X100), DQS PI = 54
2204 01:14:50.791436 [0] AVG Duty = 5015%(X100)
2205 01:14:50.794809
2206 01:14:50.798505 CH0 CLK Duty spec in!! Max-Min= 155%
2207 01:14:50.801438 [DutyScan_Calibration_Flow] ====Done====
2208 01:14:50.801522
2209 01:14:50.804658 [DutyScan_Calibration_Flow] k_type=1
2210 01:14:50.820869
2211 01:14:50.820981 ==DQS 0 ==
2212 01:14:50.824288 Final DQS duty delay cell = 0
2213 01:14:50.827419 [0] MAX Duty = 5125%(X100), DQS PI = 30
2214 01:14:50.830998 [0] MIN Duty = 5031%(X100), DQS PI = 4
2215 01:14:50.831079 [0] AVG Duty = 5078%(X100)
2216 01:14:50.834253
2217 01:14:50.834333 ==DQS 1 ==
2218 01:14:50.837285 Final DQS duty delay cell = 0
2219 01:14:50.841001 [0] MAX Duty = 5062%(X100), DQS PI = 58
2220 01:14:50.843909 [0] MIN Duty = 4906%(X100), DQS PI = 16
2221 01:14:50.847347 [0] AVG Duty = 4984%(X100)
2222 01:14:50.847429
2223 01:14:50.850587 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2224 01:14:50.850668
2225 01:14:50.854289 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2226 01:14:50.857291 [DutyScan_Calibration_Flow] ====Done====
2227 01:14:50.857377
2228 01:14:50.860447 [DutyScan_Calibration_Flow] k_type=3
2229 01:14:50.877995
2230 01:14:50.878086 ==DQM 0 ==
2231 01:14:50.881506 Final DQM duty delay cell = 0
2232 01:14:50.884488 [0] MAX Duty = 5124%(X100), DQS PI = 20
2233 01:14:50.887973 [0] MIN Duty = 4969%(X100), DQS PI = 40
2234 01:14:50.891769 [0] AVG Duty = 5046%(X100)
2235 01:14:50.891869
2236 01:14:50.891948 ==DQM 1 ==
2237 01:14:50.894768 Final DQM duty delay cell = 4
2238 01:14:50.898267 [4] MAX Duty = 5187%(X100), DQS PI = 54
2239 01:14:50.901367 [4] MIN Duty = 5000%(X100), DQS PI = 18
2240 01:14:50.904684 [4] AVG Duty = 5093%(X100)
2241 01:14:50.904817
2242 01:14:50.908212 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2243 01:14:50.908346
2244 01:14:50.911340 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2245 01:14:50.914538 [DutyScan_Calibration_Flow] ====Done====
2246 01:14:50.914709
2247 01:14:50.917948 [DutyScan_Calibration_Flow] k_type=2
2248 01:14:50.933106
2249 01:14:50.933283 ==DQ 0 ==
2250 01:14:50.936307 Final DQ duty delay cell = -4
2251 01:14:50.939546 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2252 01:14:50.942829 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2253 01:14:50.946804 [-4] AVG Duty = 4937%(X100)
2254 01:14:50.946930
2255 01:14:50.947005 ==DQ 1 ==
2256 01:14:50.949855 Final DQ duty delay cell = -4
2257 01:14:50.952943 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2258 01:14:50.956261 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2259 01:14:50.959939 [-4] AVG Duty = 4969%(X100)
2260 01:14:50.960023
2261 01:14:50.963267 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2262 01:14:50.963370
2263 01:14:50.966251 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2264 01:14:50.969569 [DutyScan_Calibration_Flow] ====Done====
2265 01:14:50.969680 ==
2266 01:14:50.972962 Dram Type= 6, Freq= 0, CH_1, rank 0
2267 01:14:50.976515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2268 01:14:50.976620 ==
2269 01:14:50.980325 [Duty_Offset_Calibration]
2270 01:14:50.980406 B0:0 B1:4 CA:-5
2271 01:14:50.980470
2272 01:14:50.983158 [DutyScan_Calibration_Flow] k_type=0
2273 01:14:50.993414
2274 01:14:50.993495 ==CLK 0==
2275 01:14:50.996823 Final CLK duty delay cell = 0
2276 01:14:51.000316 [0] MAX Duty = 5094%(X100), DQS PI = 24
2277 01:14:51.003641 [0] MIN Duty = 4907%(X100), DQS PI = 44
2278 01:14:51.003722 [0] AVG Duty = 5000%(X100)
2279 01:14:51.007150
2280 01:14:51.010268 CH1 CLK Duty spec in!! Max-Min= 187%
2281 01:14:51.013598 [DutyScan_Calibration_Flow] ====Done====
2282 01:14:51.013679
2283 01:14:51.016784 [DutyScan_Calibration_Flow] k_type=1
2284 01:14:51.031843
2285 01:14:51.031934 ==DQS 0 ==
2286 01:14:51.035383 Final DQS duty delay cell = 0
2287 01:14:51.039089 [0] MAX Duty = 5125%(X100), DQS PI = 16
2288 01:14:51.041987 [0] MIN Duty = 4875%(X100), DQS PI = 40
2289 01:14:51.045182 [0] AVG Duty = 5000%(X100)
2290 01:14:51.045263
2291 01:14:51.045326 ==DQS 1 ==
2292 01:14:51.048853 Final DQS duty delay cell = -4
2293 01:14:51.051941 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2294 01:14:51.055251 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2295 01:14:51.058638 [-4] AVG Duty = 4953%(X100)
2296 01:14:51.058719
2297 01:14:51.061934 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2298 01:14:51.062016
2299 01:14:51.065054 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2300 01:14:51.068548 [DutyScan_Calibration_Flow] ====Done====
2301 01:14:51.068629
2302 01:14:51.071620 [DutyScan_Calibration_Flow] k_type=3
2303 01:14:51.087123
2304 01:14:51.087212 ==DQM 0 ==
2305 01:14:51.090495 Final DQM duty delay cell = -4
2306 01:14:51.094557 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2307 01:14:51.097286 [-4] MIN Duty = 4844%(X100), DQS PI = 42
2308 01:14:51.100262 [-4] AVG Duty = 4968%(X100)
2309 01:14:51.100345
2310 01:14:51.100409 ==DQM 1 ==
2311 01:14:51.103988 Final DQM duty delay cell = -4
2312 01:14:51.107091 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2313 01:14:51.110603 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2314 01:14:51.113911 [-4] AVG Duty = 4968%(X100)
2315 01:14:51.113992
2316 01:14:51.116964 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2317 01:14:51.117045
2318 01:14:51.120426 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2319 01:14:51.123652 [DutyScan_Calibration_Flow] ====Done====
2320 01:14:51.123733
2321 01:14:51.127136 [DutyScan_Calibration_Flow] k_type=2
2322 01:14:51.144482
2323 01:14:51.144638 ==DQ 0 ==
2324 01:14:51.147544 Final DQ duty delay cell = 0
2325 01:14:51.150943 [0] MAX Duty = 5062%(X100), DQS PI = 0
2326 01:14:51.154297 [0] MIN Duty = 4938%(X100), DQS PI = 44
2327 01:14:51.154378 [0] AVG Duty = 5000%(X100)
2328 01:14:51.157520
2329 01:14:51.157617 ==DQ 1 ==
2330 01:14:51.160699 Final DQ duty delay cell = 0
2331 01:14:51.164120 [0] MAX Duty = 5000%(X100), DQS PI = 8
2332 01:14:51.167369 [0] MIN Duty = 4875%(X100), DQS PI = 0
2333 01:14:51.167450 [0] AVG Duty = 4937%(X100)
2334 01:14:51.167514
2335 01:14:51.170776 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2336 01:14:51.170944
2337 01:14:51.173988 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2338 01:14:51.180771 [DutyScan_Calibration_Flow] ====Done====
2339 01:14:51.184311 nWR fixed to 30
2340 01:14:51.184470 [ModeRegInit_LP4] CH0 RK0
2341 01:14:51.187619 [ModeRegInit_LP4] CH0 RK1
2342 01:14:51.190698 [ModeRegInit_LP4] CH1 RK0
2343 01:14:51.190778 [ModeRegInit_LP4] CH1 RK1
2344 01:14:51.194173 match AC timing 6
2345 01:14:51.197344 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2346 01:14:51.201015 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2347 01:14:51.207737 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2348 01:14:51.210813 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2349 01:14:51.217365 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2350 01:14:51.217446 ==
2351 01:14:51.220941 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 01:14:51.224123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2353 01:14:51.224204 ==
2354 01:14:51.230895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2355 01:14:51.234026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2356 01:14:51.243848 [CA 0] Center 39 (9~70) winsize 62
2357 01:14:51.247102 [CA 1] Center 39 (9~70) winsize 62
2358 01:14:51.250360 [CA 2] Center 36 (5~67) winsize 63
2359 01:14:51.253791 [CA 3] Center 35 (4~66) winsize 63
2360 01:14:51.256921 [CA 4] Center 34 (3~65) winsize 63
2361 01:14:51.260435 [CA 5] Center 33 (3~64) winsize 62
2362 01:14:51.260515
2363 01:14:51.264203 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2364 01:14:51.264284
2365 01:14:51.267451 [CATrainingPosCal] consider 1 rank data
2366 01:14:51.270455 u2DelayCellTimex100 = 270/100 ps
2367 01:14:51.273764 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2368 01:14:51.277173 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2369 01:14:51.283647 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2370 01:14:51.286947 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2371 01:14:51.290516 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2372 01:14:51.294170 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2373 01:14:51.294251
2374 01:14:51.297084 CA PerBit enable=1, Macro0, CA PI delay=33
2375 01:14:51.297164
2376 01:14:51.300494 [CBTSetCACLKResult] CA Dly = 33
2377 01:14:51.300575 CS Dly: 7 (0~38)
2378 01:14:51.303658 ==
2379 01:14:51.303739 Dram Type= 6, Freq= 0, CH_0, rank 1
2380 01:14:51.310475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2381 01:14:51.310556 ==
2382 01:14:51.313681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2383 01:14:51.320113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2384 01:14:51.329711 [CA 0] Center 39 (8~70) winsize 63
2385 01:14:51.333024 [CA 1] Center 39 (8~70) winsize 63
2386 01:14:51.336216 [CA 2] Center 36 (5~67) winsize 63
2387 01:14:51.339010 [CA 3] Center 35 (4~66) winsize 63
2388 01:14:51.342674 [CA 4] Center 33 (3~64) winsize 62
2389 01:14:51.345675 [CA 5] Center 34 (3~65) winsize 63
2390 01:14:51.345768
2391 01:14:51.349218 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2392 01:14:51.349300
2393 01:14:51.352418 [CATrainingPosCal] consider 2 rank data
2394 01:14:51.356215 u2DelayCellTimex100 = 270/100 ps
2395 01:14:51.359284 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2396 01:14:51.362738 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2397 01:14:51.369259 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2398 01:14:51.372725 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2399 01:14:51.375908 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2400 01:14:51.379121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2401 01:14:51.379215
2402 01:14:51.382924 CA PerBit enable=1, Macro0, CA PI delay=33
2403 01:14:51.383077
2404 01:14:51.386105 [CBTSetCACLKResult] CA Dly = 33
2405 01:14:51.386247 CS Dly: 8 (0~40)
2406 01:14:51.386374
2407 01:14:51.389355 ----->DramcWriteLeveling(PI) begin...
2408 01:14:51.392749 ==
2409 01:14:51.395750 Dram Type= 6, Freq= 0, CH_0, rank 0
2410 01:14:51.399337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2411 01:14:51.399484 ==
2412 01:14:51.402948 Write leveling (Byte 0): 26 => 26
2413 01:14:51.406073 Write leveling (Byte 1): 25 => 25
2414 01:14:51.409462 DramcWriteLeveling(PI) end<-----
2415 01:14:51.409636
2416 01:14:51.409785 ==
2417 01:14:51.412958 Dram Type= 6, Freq= 0, CH_0, rank 0
2418 01:14:51.416231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2419 01:14:51.416447 ==
2420 01:14:51.419527 [Gating] SW mode calibration
2421 01:14:51.426172 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2422 01:14:51.429637 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2423 01:14:51.436558 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2424 01:14:51.439929 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2425 01:14:51.443039 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2426 01:14:51.449812 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2427 01:14:51.453109 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2428 01:14:51.456448 0 11 20 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
2429 01:14:51.463318 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2430 01:14:51.466954 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2431 01:14:51.469709 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2432 01:14:51.476404 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2433 01:14:51.480052 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2434 01:14:51.483165 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2435 01:14:51.489947 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2436 01:14:51.493087 0 12 20 | B1->B0 | 3535 3e3e | 0 1 | (1 1) (0 0)
2437 01:14:51.496476 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2438 01:14:51.502946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2439 01:14:51.506549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2440 01:14:51.509693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2441 01:14:51.516660 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2442 01:14:51.519270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2443 01:14:51.522876 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2444 01:14:51.529682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2445 01:14:51.532971 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2446 01:14:51.536855 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2447 01:14:51.542958 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2448 01:14:51.546090 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2449 01:14:51.549534 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2450 01:14:51.555943 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2451 01:14:51.559852 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2452 01:14:51.562825 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2453 01:14:51.566189 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2454 01:14:51.573137 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2455 01:14:51.575927 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2456 01:14:51.579607 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2457 01:14:51.585562 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2458 01:14:51.589699 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2459 01:14:51.593206 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 01:14:51.599028 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2461 01:14:51.601864 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 01:14:51.605472 Total UI for P1: 0, mck2ui 16
2463 01:14:51.608623 best dqsien dly found for B0: ( 0, 15, 20)
2464 01:14:51.611869 Total UI for P1: 0, mck2ui 16
2465 01:14:51.615456 best dqsien dly found for B1: ( 0, 15, 20)
2466 01:14:51.619002 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2467 01:14:51.621763 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2468 01:14:51.621872
2469 01:14:51.625498 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2470 01:14:51.629266 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2471 01:14:51.632533 [Gating] SW calibration Done
2472 01:14:51.633040 ==
2473 01:14:51.635754 Dram Type= 6, Freq= 0, CH_0, rank 0
2474 01:14:51.642529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2475 01:14:51.643026 ==
2476 01:14:51.643352 RX Vref Scan: 0
2477 01:14:51.643655
2478 01:14:51.645751 RX Vref 0 -> 0, step: 1
2479 01:14:51.646231
2480 01:14:51.649276 RX Delay -40 -> 252, step: 8
2481 01:14:51.652641 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2482 01:14:51.655664 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2483 01:14:51.659171 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2484 01:14:51.662199 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2485 01:14:51.669327 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2486 01:14:51.672842 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2487 01:14:51.675693 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2488 01:14:51.678508 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2489 01:14:51.682159 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2490 01:14:51.688897 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2491 01:14:51.691977 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2492 01:14:51.695194 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2493 01:14:51.699175 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2494 01:14:51.702244 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2495 01:14:51.708891 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2496 01:14:51.711822 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2497 01:14:51.711909 ==
2498 01:14:51.715436 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 01:14:51.718619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2500 01:14:51.718713 ==
2501 01:14:51.721963 DQS Delay:
2502 01:14:51.722071 DQS0 = 0, DQS1 = 0
2503 01:14:51.722151 DQM Delay:
2504 01:14:51.725419 DQM0 = 115, DQM1 = 106
2505 01:14:51.725834 DQ Delay:
2506 01:14:51.729126 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2507 01:14:51.732727 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2508 01:14:51.735848 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2509 01:14:51.742479 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2510 01:14:51.743006
2511 01:14:51.743337
2512 01:14:51.743641 ==
2513 01:14:51.745769 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 01:14:51.749242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2515 01:14:51.749662 ==
2516 01:14:51.749991
2517 01:14:51.750355
2518 01:14:51.752323 TX Vref Scan disable
2519 01:14:51.752737 == TX Byte 0 ==
2520 01:14:51.758716 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2521 01:14:51.761970 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2522 01:14:51.762429 == TX Byte 1 ==
2523 01:14:51.769027 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2524 01:14:51.771904 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2525 01:14:51.772322 ==
2526 01:14:51.775162 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 01:14:51.778677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2528 01:14:51.779262 ==
2529 01:14:51.791309 TX Vref=22, minBit 12, minWin=24, winSum=409
2530 01:14:51.794746 TX Vref=24, minBit 10, minWin=25, winSum=418
2531 01:14:51.798257 TX Vref=26, minBit 10, minWin=25, winSum=425
2532 01:14:51.801134 TX Vref=28, minBit 1, minWin=26, winSum=430
2533 01:14:51.804360 TX Vref=30, minBit 5, minWin=26, winSum=429
2534 01:14:51.811683 TX Vref=32, minBit 8, minWin=25, winSum=428
2535 01:14:51.814487 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
2536 01:14:51.814905
2537 01:14:51.817795 Final TX Range 1 Vref 28
2538 01:14:51.818251
2539 01:14:51.818574 ==
2540 01:14:51.821153 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 01:14:51.824398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 01:14:51.827617 ==
2543 01:14:51.828024
2544 01:14:51.828345
2545 01:14:51.828641 TX Vref Scan disable
2546 01:14:51.831660 == TX Byte 0 ==
2547 01:14:51.834658 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2548 01:14:51.837520 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2549 01:14:51.841053 == TX Byte 1 ==
2550 01:14:51.844316 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2551 01:14:51.850911 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2552 01:14:51.851346
2553 01:14:51.851667 [DATLAT]
2554 01:14:51.851964 Freq=1200, CH0 RK0
2555 01:14:51.852257
2556 01:14:51.854361 DATLAT Default: 0xd
2557 01:14:51.854768 0, 0xFFFF, sum = 0
2558 01:14:51.857547 1, 0xFFFF, sum = 0
2559 01:14:51.861128 2, 0xFFFF, sum = 0
2560 01:14:51.861741 3, 0xFFFF, sum = 0
2561 01:14:51.864092 4, 0xFFFF, sum = 0
2562 01:14:51.864511 5, 0xFFFF, sum = 0
2563 01:14:51.867502 6, 0xFFFF, sum = 0
2564 01:14:51.867922 7, 0xFFFF, sum = 0
2565 01:14:51.870781 8, 0xFFFF, sum = 0
2566 01:14:51.871203 9, 0xFFFF, sum = 0
2567 01:14:51.874108 10, 0xFFFF, sum = 0
2568 01:14:51.874530 11, 0x0, sum = 1
2569 01:14:51.877486 12, 0x0, sum = 2
2570 01:14:51.877905 13, 0x0, sum = 3
2571 01:14:51.880924 14, 0x0, sum = 4
2572 01:14:51.881344 best_step = 12
2573 01:14:51.881672
2574 01:14:51.881980 ==
2575 01:14:51.884006 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 01:14:51.887545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2577 01:14:51.887955 ==
2578 01:14:51.890577 RX Vref Scan: 1
2579 01:14:51.890982
2580 01:14:51.894448 Set Vref Range= 32 -> 127
2581 01:14:51.894855
2582 01:14:51.895197 RX Vref 32 -> 127, step: 1
2583 01:14:51.895501
2584 01:14:51.897598 RX Delay -21 -> 252, step: 4
2585 01:14:51.898003
2586 01:14:51.901046 Set Vref, RX VrefLevel [Byte0]: 32
2587 01:14:51.904268 [Byte1]: 32
2588 01:14:51.907847
2589 01:14:51.908381 Set Vref, RX VrefLevel [Byte0]: 33
2590 01:14:51.911186 [Byte1]: 33
2591 01:14:51.915572
2592 01:14:51.916111 Set Vref, RX VrefLevel [Byte0]: 34
2593 01:14:51.918998 [Byte1]: 34
2594 01:14:51.923516
2595 01:14:51.923613 Set Vref, RX VrefLevel [Byte0]: 35
2596 01:14:51.926800 [Byte1]: 35
2597 01:14:51.931114
2598 01:14:51.931211 Set Vref, RX VrefLevel [Byte0]: 36
2599 01:14:51.934706 [Byte1]: 36
2600 01:14:51.939586
2601 01:14:51.939685 Set Vref, RX VrefLevel [Byte0]: 37
2602 01:14:51.942526 [Byte1]: 37
2603 01:14:51.947141
2604 01:14:51.947235 Set Vref, RX VrefLevel [Byte0]: 38
2605 01:14:51.950402 [Byte1]: 38
2606 01:14:51.955163
2607 01:14:51.955231 Set Vref, RX VrefLevel [Byte0]: 39
2608 01:14:51.958276 [Byte1]: 39
2609 01:14:51.963228
2610 01:14:51.963316 Set Vref, RX VrefLevel [Byte0]: 40
2611 01:14:51.966609 [Byte1]: 40
2612 01:14:51.970966
2613 01:14:51.971034 Set Vref, RX VrefLevel [Byte0]: 41
2614 01:14:51.973909 [Byte1]: 41
2615 01:14:51.978702
2616 01:14:51.978798 Set Vref, RX VrefLevel [Byte0]: 42
2617 01:14:51.981913 [Byte1]: 42
2618 01:14:51.986702
2619 01:14:51.986772 Set Vref, RX VrefLevel [Byte0]: 43
2620 01:14:51.990261 [Byte1]: 43
2621 01:14:51.994667
2622 01:14:51.994753 Set Vref, RX VrefLevel [Byte0]: 44
2623 01:14:51.998006 [Byte1]: 44
2624 01:14:52.002532
2625 01:14:52.002606 Set Vref, RX VrefLevel [Byte0]: 45
2626 01:14:52.005913 [Byte1]: 45
2627 01:14:52.010342
2628 01:14:52.010413 Set Vref, RX VrefLevel [Byte0]: 46
2629 01:14:52.013578 [Byte1]: 46
2630 01:14:52.018661
2631 01:14:52.018740 Set Vref, RX VrefLevel [Byte0]: 47
2632 01:14:52.021560 [Byte1]: 47
2633 01:14:52.026150
2634 01:14:52.026229 Set Vref, RX VrefLevel [Byte0]: 48
2635 01:14:52.029484 [Byte1]: 48
2636 01:14:52.034138
2637 01:14:52.034225 Set Vref, RX VrefLevel [Byte0]: 49
2638 01:14:52.037685 [Byte1]: 49
2639 01:14:52.042200
2640 01:14:52.042278 Set Vref, RX VrefLevel [Byte0]: 50
2641 01:14:52.045503 [Byte1]: 50
2642 01:14:52.050148
2643 01:14:52.050227 Set Vref, RX VrefLevel [Byte0]: 51
2644 01:14:52.053697 [Byte1]: 51
2645 01:14:52.057858
2646 01:14:52.057936 Set Vref, RX VrefLevel [Byte0]: 52
2647 01:14:52.061966 [Byte1]: 52
2648 01:14:52.065951
2649 01:14:52.066085 Set Vref, RX VrefLevel [Byte0]: 53
2650 01:14:52.069219 [Byte1]: 53
2651 01:14:52.073905
2652 01:14:52.073983 Set Vref, RX VrefLevel [Byte0]: 54
2653 01:14:52.077419 [Byte1]: 54
2654 01:14:52.081555
2655 01:14:52.081634 Set Vref, RX VrefLevel [Byte0]: 55
2656 01:14:52.085382 [Byte1]: 55
2657 01:14:52.089886
2658 01:14:52.089965 Set Vref, RX VrefLevel [Byte0]: 56
2659 01:14:52.092973 [Byte1]: 56
2660 01:14:52.097548
2661 01:14:52.097632 Set Vref, RX VrefLevel [Byte0]: 57
2662 01:14:52.100991 [Byte1]: 57
2663 01:14:52.106014
2664 01:14:52.106201 Set Vref, RX VrefLevel [Byte0]: 58
2665 01:14:52.109252 [Byte1]: 58
2666 01:14:52.113923
2667 01:14:52.114133 Set Vref, RX VrefLevel [Byte0]: 59
2668 01:14:52.116971 [Byte1]: 59
2669 01:14:52.121509
2670 01:14:52.121719 Set Vref, RX VrefLevel [Byte0]: 60
2671 01:14:52.124897 [Byte1]: 60
2672 01:14:52.129653
2673 01:14:52.129881 Set Vref, RX VrefLevel [Byte0]: 61
2674 01:14:52.132879 [Byte1]: 61
2675 01:14:52.137436
2676 01:14:52.137677 Set Vref, RX VrefLevel [Byte0]: 62
2677 01:14:52.140625 [Byte1]: 62
2678 01:14:52.145399
2679 01:14:52.145791 Set Vref, RX VrefLevel [Byte0]: 63
2680 01:14:52.148481 [Byte1]: 63
2681 01:14:52.153688
2682 01:14:52.154193 Set Vref, RX VrefLevel [Byte0]: 64
2683 01:14:52.157056 [Byte1]: 64
2684 01:14:52.161895
2685 01:14:52.162458 Set Vref, RX VrefLevel [Byte0]: 65
2686 01:14:52.164836 [Byte1]: 65
2687 01:14:52.169818
2688 01:14:52.170374 Final RX Vref Byte 0 = 53 to rank0
2689 01:14:52.172852 Final RX Vref Byte 1 = 46 to rank0
2690 01:14:52.176131 Final RX Vref Byte 0 = 53 to rank1
2691 01:14:52.179495 Final RX Vref Byte 1 = 46 to rank1==
2692 01:14:52.182949 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 01:14:52.189607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2694 01:14:52.190156 ==
2695 01:14:52.190487 DQS Delay:
2696 01:14:52.190784 DQS0 = 0, DQS1 = 0
2697 01:14:52.192872 DQM Delay:
2698 01:14:52.193393 DQM0 = 114, DQM1 = 104
2699 01:14:52.196299 DQ Delay:
2700 01:14:52.199422 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2701 01:14:52.202428 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2702 01:14:52.205967 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2703 01:14:52.209267 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2704 01:14:52.209776
2705 01:14:52.210143
2706 01:14:52.215760 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2707 01:14:52.218927 CH0 RK0: MR19=404, MR18=808
2708 01:14:52.225632 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2709 01:14:52.226187
2710 01:14:52.228855 ----->DramcWriteLeveling(PI) begin...
2711 01:14:52.229268 ==
2712 01:14:52.232417 Dram Type= 6, Freq= 0, CH_0, rank 1
2713 01:14:52.235468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2714 01:14:52.239038 ==
2715 01:14:52.239546 Write leveling (Byte 0): 28 => 28
2716 01:14:52.242496 Write leveling (Byte 1): 25 => 25
2717 01:14:52.245727 DramcWriteLeveling(PI) end<-----
2718 01:14:52.246295
2719 01:14:52.246657 ==
2720 01:14:52.249139 Dram Type= 6, Freq= 0, CH_0, rank 1
2721 01:14:52.255745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2722 01:14:52.256258 ==
2723 01:14:52.256618 [Gating] SW mode calibration
2724 01:14:52.265632 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2725 01:14:52.268953 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2726 01:14:52.272373 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2727 01:14:52.278896 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2728 01:14:52.282172 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2729 01:14:52.285437 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2730 01:14:52.292040 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2731 01:14:52.295664 0 11 20 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
2732 01:14:52.298697 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2733 01:14:52.305516 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2734 01:14:52.309256 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2735 01:14:52.312468 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2736 01:14:52.318862 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2737 01:14:52.321988 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2738 01:14:52.325784 0 12 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
2739 01:14:52.332453 0 12 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2740 01:14:52.335530 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2741 01:14:52.339262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2742 01:14:52.345659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2743 01:14:52.349092 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2744 01:14:52.352359 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2745 01:14:52.358944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2746 01:14:52.362391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2747 01:14:52.365844 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2748 01:14:52.372611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2749 01:14:52.375330 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2750 01:14:52.378794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2751 01:14:52.385530 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2752 01:14:52.388399 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2753 01:14:52.392098 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2754 01:14:52.395320 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2755 01:14:52.401898 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2756 01:14:52.405109 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2757 01:14:52.408822 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2758 01:14:52.415095 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2759 01:14:52.418922 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2760 01:14:52.422221 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2761 01:14:52.428704 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2762 01:14:52.431666 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2763 01:14:52.435133 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2764 01:14:52.441642 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 01:14:52.445396 Total UI for P1: 0, mck2ui 16
2766 01:14:52.448235 best dqsien dly found for B0: ( 0, 15, 18)
2767 01:14:52.448644 Total UI for P1: 0, mck2ui 16
2768 01:14:52.455198 best dqsien dly found for B1: ( 0, 15, 20)
2769 01:14:52.458355 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2770 01:14:52.461951 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2771 01:14:52.462402
2772 01:14:52.464882 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2773 01:14:52.468643 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2774 01:14:52.471529 [Gating] SW calibration Done
2775 01:14:52.472065 ==
2776 01:14:52.475120 Dram Type= 6, Freq= 0, CH_0, rank 1
2777 01:14:52.478351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2778 01:14:52.478761 ==
2779 01:14:52.481661 RX Vref Scan: 0
2780 01:14:52.482105
2781 01:14:52.482437 RX Vref 0 -> 0, step: 1
2782 01:14:52.482742
2783 01:14:52.485179 RX Delay -40 -> 252, step: 8
2784 01:14:52.488302 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2785 01:14:52.494943 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2786 01:14:52.498094 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2787 01:14:52.501592 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2788 01:14:52.504847 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2789 01:14:52.508698 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2790 01:14:52.515000 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2791 01:14:52.518547 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2792 01:14:52.521767 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2793 01:14:52.524909 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2794 01:14:52.528064 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2795 01:14:52.534804 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2796 01:14:52.537999 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2797 01:14:52.541489 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2798 01:14:52.544699 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2799 01:14:52.548544 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2800 01:14:52.552075 ==
2801 01:14:52.555256 Dram Type= 6, Freq= 0, CH_0, rank 1
2802 01:14:52.558018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2803 01:14:52.558476 ==
2804 01:14:52.558806 DQS Delay:
2805 01:14:52.561385 DQS0 = 0, DQS1 = 0
2806 01:14:52.561796 DQM Delay:
2807 01:14:52.564643 DQM0 = 115, DQM1 = 107
2808 01:14:52.565060 DQ Delay:
2809 01:14:52.568611 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2810 01:14:52.571531 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2811 01:14:52.575251 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2812 01:14:52.578159 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2813 01:14:52.578683
2814 01:14:52.579007
2815 01:14:52.579307 ==
2816 01:14:52.581859 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 01:14:52.588527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2818 01:14:52.589042 ==
2819 01:14:52.589368
2820 01:14:52.589665
2821 01:14:52.589948 TX Vref Scan disable
2822 01:14:52.591795 == TX Byte 0 ==
2823 01:14:52.595017 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2824 01:14:52.601717 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2825 01:14:52.602265 == TX Byte 1 ==
2826 01:14:52.604758 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2827 01:14:52.611183 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2828 01:14:52.611682 ==
2829 01:14:52.614590 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 01:14:52.617955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2831 01:14:52.618394 ==
2832 01:14:52.629217 TX Vref=22, minBit 8, minWin=25, winSum=419
2833 01:14:52.632799 TX Vref=24, minBit 8, minWin=25, winSum=422
2834 01:14:52.636101 TX Vref=26, minBit 8, minWin=26, winSum=430
2835 01:14:52.639423 TX Vref=28, minBit 9, minWin=26, winSum=430
2836 01:14:52.642702 TX Vref=30, minBit 8, minWin=26, winSum=432
2837 01:14:52.649211 TX Vref=32, minBit 8, minWin=26, winSum=434
2838 01:14:52.652992 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 32
2839 01:14:52.653501
2840 01:14:52.655973 Final TX Range 1 Vref 32
2841 01:14:52.656482
2842 01:14:52.656807 ==
2843 01:14:52.659013 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 01:14:52.663123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2845 01:14:52.663634 ==
2846 01:14:52.666158
2847 01:14:52.666663
2848 01:14:52.666989 TX Vref Scan disable
2849 01:14:52.669389 == TX Byte 0 ==
2850 01:14:52.672593 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2851 01:14:52.676142 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2852 01:14:52.679322 == TX Byte 1 ==
2853 01:14:52.683059 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2854 01:14:52.685979 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2855 01:14:52.686530
2856 01:14:52.689634 [DATLAT]
2857 01:14:52.690183 Freq=1200, CH0 RK1
2858 01:14:52.690515
2859 01:14:52.693072 DATLAT Default: 0xc
2860 01:14:52.693580 0, 0xFFFF, sum = 0
2861 01:14:52.696247 1, 0xFFFF, sum = 0
2862 01:14:52.696761 2, 0xFFFF, sum = 0
2863 01:14:52.699475 3, 0xFFFF, sum = 0
2864 01:14:52.699993 4, 0xFFFF, sum = 0
2865 01:14:52.702751 5, 0xFFFF, sum = 0
2866 01:14:52.703164 6, 0xFFFF, sum = 0
2867 01:14:52.705882 7, 0xFFFF, sum = 0
2868 01:14:52.706331 8, 0xFFFF, sum = 0
2869 01:14:52.709703 9, 0xFFFF, sum = 0
2870 01:14:52.712868 10, 0xFFFF, sum = 0
2871 01:14:52.713383 11, 0x0, sum = 1
2872 01:14:52.713711 12, 0x0, sum = 2
2873 01:14:52.715949 13, 0x0, sum = 3
2874 01:14:52.716461 14, 0x0, sum = 4
2875 01:14:52.719452 best_step = 12
2876 01:14:52.719962
2877 01:14:52.720285 ==
2878 01:14:52.722391 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 01:14:52.725881 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2880 01:14:52.726320 ==
2881 01:14:52.728989 RX Vref Scan: 0
2882 01:14:52.729398
2883 01:14:52.729721 RX Vref 0 -> 0, step: 1
2884 01:14:52.732400
2885 01:14:52.732808 RX Delay -21 -> 252, step: 4
2886 01:14:52.739754 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2887 01:14:52.742893 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2888 01:14:52.746712 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2889 01:14:52.749675 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2890 01:14:52.753110 iDelay=199, Bit 4, Center 118 (43 ~ 194) 152
2891 01:14:52.759922 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2892 01:14:52.762833 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2893 01:14:52.766250 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2894 01:14:52.769538 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2895 01:14:52.772768 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2896 01:14:52.779616 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2897 01:14:52.782740 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2898 01:14:52.786331 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2899 01:14:52.789642 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2900 01:14:52.793007 iDelay=199, Bit 14, Center 114 (51 ~ 178) 128
2901 01:14:52.799511 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2902 01:14:52.800017 ==
2903 01:14:52.803137 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 01:14:52.806145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2905 01:14:52.806600 ==
2906 01:14:52.806957 DQS Delay:
2907 01:14:52.810083 DQS0 = 0, DQS1 = 0
2908 01:14:52.810595 DQM Delay:
2909 01:14:52.813334 DQM0 = 115, DQM1 = 104
2910 01:14:52.813848 DQ Delay:
2911 01:14:52.815791 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2912 01:14:52.819169 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2913 01:14:52.822543 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2914 01:14:52.825943 DQ12 =110, DQ13 =112, DQ14 =114, DQ15 =114
2915 01:14:52.826372
2916 01:14:52.826695
2917 01:14:52.835909 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2918 01:14:52.839420 CH0 RK1: MR19=404, MR18=D0D
2919 01:14:52.842603 CH0_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
2920 01:14:52.846056 [RxdqsGatingPostProcess] freq 1200
2921 01:14:52.852790 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2922 01:14:52.855893 Pre-setting of DQS Precalculation
2923 01:14:52.858921 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2924 01:14:52.859333 ==
2925 01:14:52.862541 Dram Type= 6, Freq= 0, CH_1, rank 0
2926 01:14:52.869311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2927 01:14:52.869835 ==
2928 01:14:52.872713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2929 01:14:52.878931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2930 01:14:52.888310 [CA 0] Center 37 (7~68) winsize 62
2931 01:14:52.891405 [CA 1] Center 37 (7~68) winsize 62
2932 01:14:52.894817 [CA 2] Center 34 (4~65) winsize 62
2933 01:14:52.898258 [CA 3] Center 33 (3~64) winsize 62
2934 01:14:52.901374 [CA 4] Center 32 (2~63) winsize 62
2935 01:14:52.904448 [CA 5] Center 32 (2~63) winsize 62
2936 01:14:52.904855
2937 01:14:52.907486 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2938 01:14:52.907895
2939 01:14:52.911639 [CATrainingPosCal] consider 1 rank data
2940 01:14:52.914406 u2DelayCellTimex100 = 270/100 ps
2941 01:14:52.917995 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2942 01:14:52.921174 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2943 01:14:52.928350 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2944 01:14:52.931190 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2945 01:14:52.935095 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2946 01:14:52.938176 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2947 01:14:52.938676
2948 01:14:52.941538 CA PerBit enable=1, Macro0, CA PI delay=32
2949 01:14:52.942241
2950 01:14:52.944497 [CBTSetCACLKResult] CA Dly = 32
2951 01:14:52.945017 CS Dly: 5 (0~36)
2952 01:14:52.948235 ==
2953 01:14:52.948758 Dram Type= 6, Freq= 0, CH_1, rank 1
2954 01:14:52.954532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2955 01:14:52.955239 ==
2956 01:14:52.957834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2957 01:14:52.964838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2958 01:14:52.973371 [CA 0] Center 37 (7~68) winsize 62
2959 01:14:52.976926 [CA 1] Center 37 (7~68) winsize 62
2960 01:14:52.979843 [CA 2] Center 34 (3~65) winsize 63
2961 01:14:52.983215 [CA 3] Center 33 (3~64) winsize 62
2962 01:14:52.986933 [CA 4] Center 32 (2~63) winsize 62
2963 01:14:52.989753 [CA 5] Center 31 (1~62) winsize 62
2964 01:14:52.990201
2965 01:14:52.993481 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2966 01:14:52.993998
2967 01:14:52.996608 [CATrainingPosCal] consider 2 rank data
2968 01:14:52.999966 u2DelayCellTimex100 = 270/100 ps
2969 01:14:53.003003 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2970 01:14:53.006356 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2971 01:14:53.013442 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2972 01:14:53.016735 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2973 01:14:53.020042 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2974 01:14:53.022907 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2975 01:14:53.023325
2976 01:14:53.026305 CA PerBit enable=1, Macro0, CA PI delay=32
2977 01:14:53.026725
2978 01:14:53.029842 [CBTSetCACLKResult] CA Dly = 32
2979 01:14:53.030304 CS Dly: 6 (0~38)
2980 01:14:53.030631
2981 01:14:53.032978 ----->DramcWriteLeveling(PI) begin...
2982 01:14:53.036701 ==
2983 01:14:53.039780 Dram Type= 6, Freq= 0, CH_1, rank 0
2984 01:14:53.042993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2985 01:14:53.043544 ==
2986 01:14:53.046483 Write leveling (Byte 0): 20 => 20
2987 01:14:53.050600 Write leveling (Byte 1): 22 => 22
2988 01:14:53.053073 DramcWriteLeveling(PI) end<-----
2989 01:14:53.053623
2990 01:14:53.053983 ==
2991 01:14:53.056264 Dram Type= 6, Freq= 0, CH_1, rank 0
2992 01:14:53.059863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2993 01:14:53.060317 ==
2994 01:14:53.062999 [Gating] SW mode calibration
2995 01:14:53.069541 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2996 01:14:53.076332 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2997 01:14:53.079635 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2998 01:14:53.082782 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2999 01:14:53.089632 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3000 01:14:53.093397 0 11 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
3001 01:14:53.096506 0 11 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
3002 01:14:53.099457 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3003 01:14:53.106192 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3004 01:14:53.109432 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3005 01:14:53.113065 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3006 01:14:53.119224 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3007 01:14:53.123006 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3008 01:14:53.126347 0 12 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3009 01:14:53.132756 0 12 16 | B1->B0 | 3333 4343 | 1 0 | (0 0) (0 0)
3010 01:14:53.136456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3011 01:14:53.139448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3012 01:14:53.146378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3013 01:14:53.149422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3014 01:14:53.152862 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3015 01:14:53.159495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3016 01:14:53.162634 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3017 01:14:53.165832 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3018 01:14:53.172464 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3019 01:14:53.175707 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3020 01:14:53.178968 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3021 01:14:53.185955 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3022 01:14:53.189236 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3023 01:14:53.192560 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3024 01:14:53.199412 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3025 01:14:53.202320 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3026 01:14:53.205667 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3027 01:14:53.212532 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3028 01:14:53.215731 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3029 01:14:53.218905 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3030 01:14:53.225760 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3031 01:14:53.229335 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3032 01:14:53.232675 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3033 01:14:53.238670 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3034 01:14:53.242353 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3035 01:14:53.246121 Total UI for P1: 0, mck2ui 16
3036 01:14:53.249136 best dqsien dly found for B0: ( 0, 15, 14)
3037 01:14:53.252801 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 01:14:53.255966 Total UI for P1: 0, mck2ui 16
3039 01:14:53.259247 best dqsien dly found for B1: ( 0, 15, 18)
3040 01:14:53.262867 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3041 01:14:53.265646 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3042 01:14:53.266249
3043 01:14:53.269184 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3044 01:14:53.273002 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3045 01:14:53.275799 [Gating] SW calibration Done
3046 01:14:53.276257 ==
3047 01:14:53.278855 Dram Type= 6, Freq= 0, CH_1, rank 0
3048 01:14:53.285902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3049 01:14:53.286493 ==
3050 01:14:53.286865 RX Vref Scan: 0
3051 01:14:53.287365
3052 01:14:53.288732 RX Vref 0 -> 0, step: 1
3053 01:14:53.289350
3054 01:14:53.292041 RX Delay -40 -> 252, step: 8
3055 01:14:53.295916 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3056 01:14:53.299172 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3057 01:14:53.302366 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3058 01:14:53.305723 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3059 01:14:53.312296 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3060 01:14:53.315925 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3061 01:14:53.318821 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3062 01:14:53.322599 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3063 01:14:53.326122 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3064 01:14:53.332263 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3065 01:14:53.352313 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3066 01:14:53.352853 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3067 01:14:53.353292 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3068 01:14:53.353703 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3069 01:14:53.354232 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3070 01:14:53.355362 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3071 01:14:53.355794 ==
3072 01:14:53.358825 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 01:14:53.362139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 01:14:53.362562 ==
3075 01:14:53.365827 DQS Delay:
3076 01:14:53.366413 DQS0 = 0, DQS1 = 0
3077 01:14:53.366752 DQM Delay:
3078 01:14:53.368933 DQM0 = 116, DQM1 = 109
3079 01:14:53.369456 DQ Delay:
3080 01:14:53.371918 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3081 01:14:53.375689 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3082 01:14:53.378602 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3083 01:14:53.385553 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3084 01:14:53.386111
3085 01:14:53.386449
3086 01:14:53.386755 ==
3087 01:14:53.389014 Dram Type= 6, Freq= 0, CH_1, rank 0
3088 01:14:53.392332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3089 01:14:53.392857 ==
3090 01:14:53.393231
3091 01:14:53.393721
3092 01:14:53.395823 TX Vref Scan disable
3093 01:14:53.396342 == TX Byte 0 ==
3094 01:14:53.402198 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3095 01:14:53.405259 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3096 01:14:53.405783 == TX Byte 1 ==
3097 01:14:53.412071 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3098 01:14:53.415516 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3099 01:14:53.416042 ==
3100 01:14:53.418895 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 01:14:53.421899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3102 01:14:53.422373 ==
3103 01:14:53.434461 TX Vref=22, minBit 1, minWin=25, winSum=413
3104 01:14:53.437618 TX Vref=24, minBit 3, minWin=25, winSum=419
3105 01:14:53.441415 TX Vref=26, minBit 9, minWin=25, winSum=421
3106 01:14:53.444694 TX Vref=28, minBit 0, minWin=26, winSum=425
3107 01:14:53.448085 TX Vref=30, minBit 0, minWin=26, winSum=431
3108 01:14:53.451005 TX Vref=32, minBit 3, minWin=26, winSum=429
3109 01:14:53.458270 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
3110 01:14:53.458996
3111 01:14:53.461097 Final TX Range 1 Vref 30
3112 01:14:53.461666
3113 01:14:53.462275 ==
3114 01:14:53.464492 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 01:14:53.467540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3116 01:14:53.467970 ==
3117 01:14:53.468401
3118 01:14:53.471302
3119 01:14:53.471779 TX Vref Scan disable
3120 01:14:53.474537 == TX Byte 0 ==
3121 01:14:53.478380 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3122 01:14:53.480753 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3123 01:14:53.484747 == TX Byte 1 ==
3124 01:14:53.487744 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3125 01:14:53.490708 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3126 01:14:53.494453
3127 01:14:53.494977 [DATLAT]
3128 01:14:53.495419 Freq=1200, CH1 RK0
3129 01:14:53.495832
3130 01:14:53.497732 DATLAT Default: 0xd
3131 01:14:53.498328 0, 0xFFFF, sum = 0
3132 01:14:53.501518 1, 0xFFFF, sum = 0
3133 01:14:53.502083 2, 0xFFFF, sum = 0
3134 01:14:53.503881 3, 0xFFFF, sum = 0
3135 01:14:53.504395 4, 0xFFFF, sum = 0
3136 01:14:53.507628 5, 0xFFFF, sum = 0
3137 01:14:53.511362 6, 0xFFFF, sum = 0
3138 01:14:53.511797 7, 0xFFFF, sum = 0
3139 01:14:53.514162 8, 0xFFFF, sum = 0
3140 01:14:53.514598 9, 0xFFFF, sum = 0
3141 01:14:53.517562 10, 0xFFFF, sum = 0
3142 01:14:53.518141 11, 0x0, sum = 1
3143 01:14:53.520985 12, 0x0, sum = 2
3144 01:14:53.521528 13, 0x0, sum = 3
3145 01:14:53.524423 14, 0x0, sum = 4
3146 01:14:53.524950 best_step = 12
3147 01:14:53.525389
3148 01:14:53.525795 ==
3149 01:14:53.527334 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 01:14:53.530720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3151 01:14:53.531156 ==
3152 01:14:53.534017 RX Vref Scan: 1
3153 01:14:53.534476
3154 01:14:53.538115 Set Vref Range= 32 -> 127
3155 01:14:53.538654
3156 01:14:53.539101 RX Vref 32 -> 127, step: 1
3157 01:14:53.539516
3158 01:14:53.540721 RX Delay -21 -> 252, step: 4
3159 01:14:53.541151
3160 01:14:53.544114 Set Vref, RX VrefLevel [Byte0]: 32
3161 01:14:53.546951 [Byte1]: 32
3162 01:14:53.551471
3163 01:14:53.551991 Set Vref, RX VrefLevel [Byte0]: 33
3164 01:14:53.554251 [Byte1]: 33
3165 01:14:53.559293
3166 01:14:53.559828 Set Vref, RX VrefLevel [Byte0]: 34
3167 01:14:53.562274 [Byte1]: 34
3168 01:14:53.566969
3169 01:14:53.567516 Set Vref, RX VrefLevel [Byte0]: 35
3170 01:14:53.570191 [Byte1]: 35
3171 01:14:53.574845
3172 01:14:53.575373 Set Vref, RX VrefLevel [Byte0]: 36
3173 01:14:53.577992 [Byte1]: 36
3174 01:14:53.582605
3175 01:14:53.583150 Set Vref, RX VrefLevel [Byte0]: 37
3176 01:14:53.585758 [Byte1]: 37
3177 01:14:53.590855
3178 01:14:53.591302 Set Vref, RX VrefLevel [Byte0]: 38
3179 01:14:53.593587 [Byte1]: 38
3180 01:14:53.598125
3181 01:14:53.598558 Set Vref, RX VrefLevel [Byte0]: 39
3182 01:14:53.601880 [Byte1]: 39
3183 01:14:53.606480
3184 01:14:53.607002 Set Vref, RX VrefLevel [Byte0]: 40
3185 01:14:53.609515 [Byte1]: 40
3186 01:14:53.614315
3187 01:14:53.614743 Set Vref, RX VrefLevel [Byte0]: 41
3188 01:14:53.617332 [Byte1]: 41
3189 01:14:53.622054
3190 01:14:53.622471 Set Vref, RX VrefLevel [Byte0]: 42
3191 01:14:53.625489 [Byte1]: 42
3192 01:14:53.630980
3193 01:14:53.631511 Set Vref, RX VrefLevel [Byte0]: 43
3194 01:14:53.633074 [Byte1]: 43
3195 01:14:53.638477
3196 01:14:53.638907 Set Vref, RX VrefLevel [Byte0]: 44
3197 01:14:53.641487 [Byte1]: 44
3198 01:14:53.646020
3199 01:14:53.646493 Set Vref, RX VrefLevel [Byte0]: 45
3200 01:14:53.649344 [Byte1]: 45
3201 01:14:53.653667
3202 01:14:53.654129 Set Vref, RX VrefLevel [Byte0]: 46
3203 01:14:53.657054 [Byte1]: 46
3204 01:14:53.661477
3205 01:14:53.661942 Set Vref, RX VrefLevel [Byte0]: 47
3206 01:14:53.665169 [Byte1]: 47
3207 01:14:53.669747
3208 01:14:53.670220 Set Vref, RX VrefLevel [Byte0]: 48
3209 01:14:53.672759 [Byte1]: 48
3210 01:14:53.677407
3211 01:14:53.677835 Set Vref, RX VrefLevel [Byte0]: 49
3212 01:14:53.680850 [Byte1]: 49
3213 01:14:53.685335
3214 01:14:53.685800 Set Vref, RX VrefLevel [Byte0]: 50
3215 01:14:53.688981 [Byte1]: 50
3216 01:14:53.693076
3217 01:14:53.693505 Set Vref, RX VrefLevel [Byte0]: 51
3218 01:14:53.696821 [Byte1]: 51
3219 01:14:53.701359
3220 01:14:53.701917 Set Vref, RX VrefLevel [Byte0]: 52
3221 01:14:53.704806 [Byte1]: 52
3222 01:14:53.709242
3223 01:14:53.709862 Set Vref, RX VrefLevel [Byte0]: 53
3224 01:14:53.713030 [Byte1]: 53
3225 01:14:53.717907
3226 01:14:53.718461 Set Vref, RX VrefLevel [Byte0]: 54
3227 01:14:53.720517 [Byte1]: 54
3228 01:14:53.725603
3229 01:14:53.726395 Set Vref, RX VrefLevel [Byte0]: 55
3230 01:14:53.728562 [Byte1]: 55
3231 01:14:53.732990
3232 01:14:53.733537 Set Vref, RX VrefLevel [Byte0]: 56
3233 01:14:53.736521 [Byte1]: 56
3234 01:14:53.740921
3235 01:14:53.741465 Set Vref, RX VrefLevel [Byte0]: 57
3236 01:14:53.744500 [Byte1]: 57
3237 01:14:53.748751
3238 01:14:53.749305 Set Vref, RX VrefLevel [Byte0]: 58
3239 01:14:53.752817 [Byte1]: 58
3240 01:14:53.756828
3241 01:14:53.757382 Set Vref, RX VrefLevel [Byte0]: 59
3242 01:14:53.759917 [Byte1]: 59
3243 01:14:53.764770
3244 01:14:53.765417 Set Vref, RX VrefLevel [Byte0]: 60
3245 01:14:53.767719 [Byte1]: 60
3246 01:14:53.772874
3247 01:14:53.773421 Set Vref, RX VrefLevel [Byte0]: 61
3248 01:14:53.775936 [Byte1]: 61
3249 01:14:53.780548
3250 01:14:53.781100 Set Vref, RX VrefLevel [Byte0]: 62
3251 01:14:53.783858 [Byte1]: 62
3252 01:14:53.788821
3253 01:14:53.789370 Set Vref, RX VrefLevel [Byte0]: 63
3254 01:14:53.792055 [Byte1]: 63
3255 01:14:53.796349
3256 01:14:53.796908 Set Vref, RX VrefLevel [Byte0]: 64
3257 01:14:53.799583 [Byte1]: 64
3258 01:14:53.804386
3259 01:14:53.804936 Set Vref, RX VrefLevel [Byte0]: 65
3260 01:14:53.808043 [Byte1]: 65
3261 01:14:53.812255
3262 01:14:53.812801 Set Vref, RX VrefLevel [Byte0]: 66
3263 01:14:53.815674 [Byte1]: 66
3264 01:14:53.820087
3265 01:14:53.820539 Final RX Vref Byte 0 = 56 to rank0
3266 01:14:53.823552 Final RX Vref Byte 1 = 50 to rank0
3267 01:14:53.827159 Final RX Vref Byte 0 = 56 to rank1
3268 01:14:53.830435 Final RX Vref Byte 1 = 50 to rank1==
3269 01:14:53.833505 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 01:14:53.839949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3271 01:14:53.840490 ==
3272 01:14:53.840854 DQS Delay:
3273 01:14:53.841188 DQS0 = 0, DQS1 = 0
3274 01:14:53.844049 DQM Delay:
3275 01:14:53.844603 DQM0 = 115, DQM1 = 105
3276 01:14:53.846627 DQ Delay:
3277 01:14:53.850742 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3278 01:14:53.853707 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3279 01:14:53.857220 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3280 01:14:53.860310 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3281 01:14:53.860767
3282 01:14:53.861126
3283 01:14:53.866717 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3284 01:14:53.869993 CH1 RK0: MR19=404, MR18=1919
3285 01:14:53.876867 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3286 01:14:53.877376
3287 01:14:53.880203 ----->DramcWriteLeveling(PI) begin...
3288 01:14:53.880780 ==
3289 01:14:53.883362 Dram Type= 6, Freq= 0, CH_1, rank 1
3290 01:14:53.886973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3291 01:14:53.890147 ==
3292 01:14:53.890666 Write leveling (Byte 0): 21 => 21
3293 01:14:53.893462 Write leveling (Byte 1): 22 => 22
3294 01:14:53.897021 DramcWriteLeveling(PI) end<-----
3295 01:14:53.897529
3296 01:14:53.897856 ==
3297 01:14:53.899982 Dram Type= 6, Freq= 0, CH_1, rank 1
3298 01:14:53.906587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3299 01:14:53.907097 ==
3300 01:14:53.907428 [Gating] SW mode calibration
3301 01:14:53.916908 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3302 01:14:53.919852 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3303 01:14:53.926776 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3304 01:14:53.929917 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3305 01:14:53.933642 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3306 01:14:53.936460 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3307 01:14:53.942972 0 11 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 1) (0 0)
3308 01:14:53.946348 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3309 01:14:53.953289 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3310 01:14:53.956339 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3311 01:14:53.959630 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3312 01:14:53.962771 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3313 01:14:53.969286 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3314 01:14:53.973041 0 12 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
3315 01:14:53.976283 0 12 16 | B1->B0 | 3332 4646 | 1 0 | (0 0) (0 0)
3316 01:14:53.982785 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3317 01:14:53.986231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3318 01:14:53.989317 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3319 01:14:53.995811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3320 01:14:53.999617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3321 01:14:54.002335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3322 01:14:54.009555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3323 01:14:54.012461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3324 01:14:54.016468 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3325 01:14:54.023151 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3326 01:14:54.025731 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3327 01:14:54.029422 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3328 01:14:54.036133 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 01:14:54.039172 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3330 01:14:54.042762 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 01:14:54.048927 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3332 01:14:54.052520 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3333 01:14:54.055782 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3334 01:14:54.062641 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3335 01:14:54.066334 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3336 01:14:54.069604 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3337 01:14:54.075998 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3338 01:14:54.079460 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3339 01:14:54.083032 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3340 01:14:54.085793 Total UI for P1: 0, mck2ui 16
3341 01:14:54.089343 best dqsien dly found for B0: ( 0, 15, 12)
3342 01:14:54.092314 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 01:14:54.095566 Total UI for P1: 0, mck2ui 16
3344 01:14:54.099278 best dqsien dly found for B1: ( 0, 15, 16)
3345 01:14:54.103018 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3346 01:14:54.109324 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3347 01:14:54.109828
3348 01:14:54.112400 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3349 01:14:54.115954 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3350 01:14:54.119196 [Gating] SW calibration Done
3351 01:14:54.119602 ==
3352 01:14:54.122467 Dram Type= 6, Freq= 0, CH_1, rank 1
3353 01:14:54.126121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3354 01:14:54.126627 ==
3355 01:14:54.129120 RX Vref Scan: 0
3356 01:14:54.129624
3357 01:14:54.129948 RX Vref 0 -> 0, step: 1
3358 01:14:54.130315
3359 01:14:54.132537 RX Delay -40 -> 252, step: 8
3360 01:14:54.135699 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3361 01:14:54.139008 iDelay=208, Bit 1, Center 111 (32 ~ 191) 160
3362 01:14:54.145716 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3363 01:14:54.149066 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3364 01:14:54.152545 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3365 01:14:54.156133 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3366 01:14:54.160012 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3367 01:14:54.165651 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3368 01:14:54.168942 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3369 01:14:54.172551 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3370 01:14:54.175240 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3371 01:14:54.178696 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3372 01:14:54.185405 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3373 01:14:54.188862 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3374 01:14:54.192301 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3375 01:14:54.195436 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3376 01:14:54.195843 ==
3377 01:14:54.199386 Dram Type= 6, Freq= 0, CH_1, rank 1
3378 01:14:54.205839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3379 01:14:54.206365 ==
3380 01:14:54.206688 DQS Delay:
3381 01:14:54.208504 DQS0 = 0, DQS1 = 0
3382 01:14:54.208958 DQM Delay:
3383 01:14:54.209283 DQM0 = 116, DQM1 = 106
3384 01:14:54.212132 DQ Delay:
3385 01:14:54.215481 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3386 01:14:54.218545 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3387 01:14:54.222379 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3388 01:14:54.225790 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =111
3389 01:14:54.226344
3390 01:14:54.226676
3391 01:14:54.226978 ==
3392 01:14:54.228852 Dram Type= 6, Freq= 0, CH_1, rank 1
3393 01:14:54.231689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3394 01:14:54.235379 ==
3395 01:14:54.235885
3396 01:14:54.236211
3397 01:14:54.236509 TX Vref Scan disable
3398 01:14:54.238813 == TX Byte 0 ==
3399 01:14:54.242584 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3400 01:14:54.245488 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3401 01:14:54.248891 == TX Byte 1 ==
3402 01:14:54.251881 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3403 01:14:54.255375 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3404 01:14:54.255883 ==
3405 01:14:54.258722 Dram Type= 6, Freq= 0, CH_1, rank 1
3406 01:14:54.265119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3407 01:14:54.265636 ==
3408 01:14:54.275614 TX Vref=22, minBit 0, minWin=26, winSum=426
3409 01:14:54.279451 TX Vref=24, minBit 3, minWin=26, winSum=426
3410 01:14:54.282218 TX Vref=26, minBit 0, minWin=26, winSum=426
3411 01:14:54.285816 TX Vref=28, minBit 9, minWin=26, winSum=431
3412 01:14:54.289322 TX Vref=30, minBit 8, minWin=26, winSum=434
3413 01:14:54.292182 TX Vref=32, minBit 0, minWin=26, winSum=431
3414 01:14:54.298819 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3415 01:14:54.299230
3416 01:14:54.302341 Final TX Range 1 Vref 30
3417 01:14:54.302752
3418 01:14:54.303080 ==
3419 01:14:54.305828 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 01:14:54.309000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 01:14:54.309589 ==
3422 01:14:54.310118
3423 01:14:54.312443
3424 01:14:54.312855 TX Vref Scan disable
3425 01:14:54.315880 == TX Byte 0 ==
3426 01:14:54.318973 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3427 01:14:54.322222 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3428 01:14:54.325730 == TX Byte 1 ==
3429 01:14:54.329007 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3430 01:14:54.331987 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3431 01:14:54.332404
3432 01:14:54.335718 [DATLAT]
3433 01:14:54.336126 Freq=1200, CH1 RK1
3434 01:14:54.336485
3435 01:14:54.339137 DATLAT Default: 0xc
3436 01:14:54.339549 0, 0xFFFF, sum = 0
3437 01:14:54.342271 1, 0xFFFF, sum = 0
3438 01:14:54.342785 2, 0xFFFF, sum = 0
3439 01:14:54.346171 3, 0xFFFF, sum = 0
3440 01:14:54.346686 4, 0xFFFF, sum = 0
3441 01:14:54.349237 5, 0xFFFF, sum = 0
3442 01:14:54.352329 6, 0xFFFF, sum = 0
3443 01:14:54.352749 7, 0xFFFF, sum = 0
3444 01:14:54.356028 8, 0xFFFF, sum = 0
3445 01:14:54.356545 9, 0xFFFF, sum = 0
3446 01:14:54.359244 10, 0xFFFF, sum = 0
3447 01:14:54.359759 11, 0x0, sum = 1
3448 01:14:54.362218 12, 0x0, sum = 2
3449 01:14:54.362637 13, 0x0, sum = 3
3450 01:14:54.362969 14, 0x0, sum = 4
3451 01:14:54.365644 best_step = 12
3452 01:14:54.366194
3453 01:14:54.366528 ==
3454 01:14:54.369150 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 01:14:54.372616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3456 01:14:54.373127 ==
3457 01:14:54.375335 RX Vref Scan: 0
3458 01:14:54.375746
3459 01:14:54.376073 RX Vref 0 -> 0, step: 1
3460 01:14:54.378802
3461 01:14:54.379211 RX Delay -29 -> 252, step: 4
3462 01:14:54.386365 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3463 01:14:54.389747 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3464 01:14:54.392467 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3465 01:14:54.396373 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3466 01:14:54.399807 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3467 01:14:54.406328 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3468 01:14:54.409678 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3469 01:14:54.412866 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3470 01:14:54.416408 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3471 01:14:54.419243 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3472 01:14:54.426189 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3473 01:14:54.429167 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3474 01:14:54.432579 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3475 01:14:54.435422 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3476 01:14:54.439310 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3477 01:14:54.445624 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3478 01:14:54.446265 ==
3479 01:14:54.449389 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 01:14:54.452006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3481 01:14:54.452433 ==
3482 01:14:54.452857 DQS Delay:
3483 01:14:54.455284 DQS0 = 0, DQS1 = 0
3484 01:14:54.455690 DQM Delay:
3485 01:14:54.458698 DQM0 = 114, DQM1 = 105
3486 01:14:54.459106 DQ Delay:
3487 01:14:54.461843 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3488 01:14:54.466258 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3489 01:14:54.469199 DQ8 =88, DQ9 =94, DQ10 =106, DQ11 =98
3490 01:14:54.472453 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =110
3491 01:14:54.472960
3492 01:14:54.475225
3493 01:14:54.482638 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3494 01:14:54.485276 CH1 RK1: MR19=404, MR18=808
3495 01:14:54.492843 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3496 01:14:54.495420 [RxdqsGatingPostProcess] freq 1200
3497 01:14:54.498598 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3498 01:14:54.501780 Pre-setting of DQS Precalculation
3499 01:14:54.508814 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3500 01:14:54.515309 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3501 01:14:54.521855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3502 01:14:54.522522
3503 01:14:54.523003
3504 01:14:54.524611 [Calibration Summary] 2400 Mbps
3505 01:14:54.525152 CH 0, Rank 0
3506 01:14:54.528009 SW Impedance : PASS
3507 01:14:54.531736 DUTY Scan : NO K
3508 01:14:54.532189 ZQ Calibration : PASS
3509 01:14:54.534410 Jitter Meter : NO K
3510 01:14:54.538385 CBT Training : PASS
3511 01:14:54.538907 Write leveling : PASS
3512 01:14:54.541433 RX DQS gating : PASS
3513 01:14:54.545006 RX DQ/DQS(RDDQC) : PASS
3514 01:14:54.545528 TX DQ/DQS : PASS
3515 01:14:54.547881 RX DATLAT : PASS
3516 01:14:54.548434 RX DQ/DQS(Engine): PASS
3517 01:14:54.551104 TX OE : NO K
3518 01:14:54.551529 All Pass.
3519 01:14:54.551965
3520 01:14:54.554502 CH 0, Rank 1
3521 01:14:54.557944 SW Impedance : PASS
3522 01:14:54.558403 DUTY Scan : NO K
3523 01:14:54.561176 ZQ Calibration : PASS
3524 01:14:54.561598 Jitter Meter : NO K
3525 01:14:54.564453 CBT Training : PASS
3526 01:14:54.567645 Write leveling : PASS
3527 01:14:54.568069 RX DQS gating : PASS
3528 01:14:54.571124 RX DQ/DQS(RDDQC) : PASS
3529 01:14:54.574421 TX DQ/DQS : PASS
3530 01:14:54.574854 RX DATLAT : PASS
3531 01:14:54.577354 RX DQ/DQS(Engine): PASS
3532 01:14:54.580771 TX OE : NO K
3533 01:14:54.581194 All Pass.
3534 01:14:54.581623
3535 01:14:54.582059 CH 1, Rank 0
3536 01:14:54.584568 SW Impedance : PASS
3537 01:14:54.588330 DUTY Scan : NO K
3538 01:14:54.588855 ZQ Calibration : PASS
3539 01:14:54.590691 Jitter Meter : NO K
3540 01:14:54.594629 CBT Training : PASS
3541 01:14:54.595153 Write leveling : PASS
3542 01:14:54.597575 RX DQS gating : PASS
3543 01:14:54.600849 RX DQ/DQS(RDDQC) : PASS
3544 01:14:54.601373 TX DQ/DQS : PASS
3545 01:14:54.604478 RX DATLAT : PASS
3546 01:14:54.607345 RX DQ/DQS(Engine): PASS
3547 01:14:54.607768 TX OE : NO K
3548 01:14:54.611114 All Pass.
3549 01:14:54.611635
3550 01:14:54.612067 CH 1, Rank 1
3551 01:14:54.613855 SW Impedance : PASS
3552 01:14:54.614334 DUTY Scan : NO K
3553 01:14:54.617005 ZQ Calibration : PASS
3554 01:14:54.620983 Jitter Meter : NO K
3555 01:14:54.621506 CBT Training : PASS
3556 01:14:54.624371 Write leveling : PASS
3557 01:14:54.624891 RX DQS gating : PASS
3558 01:14:54.627216 RX DQ/DQS(RDDQC) : PASS
3559 01:14:54.630616 TX DQ/DQS : PASS
3560 01:14:54.631033 RX DATLAT : PASS
3561 01:14:54.633834 RX DQ/DQS(Engine): PASS
3562 01:14:54.636986 TX OE : NO K
3563 01:14:54.637496 All Pass.
3564 01:14:54.637826
3565 01:14:54.640310 DramC Write-DBI off
3566 01:14:54.640819 PER_BANK_REFRESH: Hybrid Mode
3567 01:14:54.643976 TX_TRACKING: ON
3568 01:14:54.653606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3569 01:14:54.657018 [FAST_K] Save calibration result to emmc
3570 01:14:54.660312 dramc_set_vcore_voltage set vcore to 650000
3571 01:14:54.663283 Read voltage for 600, 5
3572 01:14:54.663700 Vio18 = 0
3573 01:14:54.664026 Vcore = 650000
3574 01:14:54.666530 Vdram = 0
3575 01:14:54.666942 Vddq = 0
3576 01:14:54.667267 Vmddr = 0
3577 01:14:54.673325 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3578 01:14:54.676494 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3579 01:14:54.680082 MEM_TYPE=3, freq_sel=19
3580 01:14:54.683186 sv_algorithm_assistance_LP4_1600
3581 01:14:54.686479 ============ PULL DRAM RESETB DOWN ============
3582 01:14:54.689866 ========== PULL DRAM RESETB DOWN end =========
3583 01:14:54.696730 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3584 01:14:54.699523 ===================================
3585 01:14:54.699944 LPDDR4 DRAM CONFIGURATION
3586 01:14:54.702953 ===================================
3587 01:14:54.706489 EX_ROW_EN[0] = 0x0
3588 01:14:54.709683 EX_ROW_EN[1] = 0x0
3589 01:14:54.710231 LP4Y_EN = 0x0
3590 01:14:54.712639 WORK_FSP = 0x0
3591 01:14:54.713288 WL = 0x2
3592 01:14:54.716006 RL = 0x2
3593 01:14:54.716417 BL = 0x2
3594 01:14:54.719905 RPST = 0x0
3595 01:14:54.720416 RD_PRE = 0x0
3596 01:14:54.722840 WR_PRE = 0x1
3597 01:14:54.723249 WR_PST = 0x0
3598 01:14:54.726267 DBI_WR = 0x0
3599 01:14:54.726679 DBI_RD = 0x0
3600 01:14:54.729724 OTF = 0x1
3601 01:14:54.732782 ===================================
3602 01:14:54.736246 ===================================
3603 01:14:54.736659 ANA top config
3604 01:14:54.739647 ===================================
3605 01:14:54.742633 DLL_ASYNC_EN = 0
3606 01:14:54.745746 ALL_SLAVE_EN = 1
3607 01:14:54.749556 NEW_RANK_MODE = 1
3608 01:14:54.750102 DLL_IDLE_MODE = 1
3609 01:14:54.752484 LP45_APHY_COMB_EN = 1
3610 01:14:54.755851 TX_ODT_DIS = 1
3611 01:14:54.759335 NEW_8X_MODE = 1
3612 01:14:54.762786 ===================================
3613 01:14:54.765986 ===================================
3614 01:14:54.769244 data_rate = 1200
3615 01:14:54.769757 CKR = 1
3616 01:14:54.772538 DQ_P2S_RATIO = 8
3617 01:14:54.775837 ===================================
3618 01:14:54.779419 CA_P2S_RATIO = 8
3619 01:14:54.782268 DQ_CA_OPEN = 0
3620 01:14:54.785999 DQ_SEMI_OPEN = 0
3621 01:14:54.789276 CA_SEMI_OPEN = 0
3622 01:14:54.789713 CA_FULL_RATE = 0
3623 01:14:54.792617 DQ_CKDIV4_EN = 1
3624 01:14:54.795595 CA_CKDIV4_EN = 1
3625 01:14:54.799140 CA_PREDIV_EN = 0
3626 01:14:54.802803 PH8_DLY = 0
3627 01:14:54.805656 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3628 01:14:54.806106 DQ_AAMCK_DIV = 4
3629 01:14:54.808997 CA_AAMCK_DIV = 4
3630 01:14:54.812517 CA_ADMCK_DIV = 4
3631 01:14:54.815833 DQ_TRACK_CA_EN = 0
3632 01:14:54.819453 CA_PICK = 600
3633 01:14:54.822996 CA_MCKIO = 600
3634 01:14:54.823500 MCKIO_SEMI = 0
3635 01:14:54.825625 PLL_FREQ = 2288
3636 01:14:54.828629 DQ_UI_PI_RATIO = 32
3637 01:14:54.832677 CA_UI_PI_RATIO = 0
3638 01:14:54.835791 ===================================
3639 01:14:54.839027 ===================================
3640 01:14:54.842229 memory_type:LPDDR4
3641 01:14:54.842738 GP_NUM : 10
3642 01:14:54.845903 SRAM_EN : 1
3643 01:14:54.848970 MD32_EN : 0
3644 01:14:54.852447 ===================================
3645 01:14:54.852962 [ANA_INIT] >>>>>>>>>>>>>>
3646 01:14:54.855747 <<<<<< [CONFIGURE PHASE]: ANA_TX
3647 01:14:54.858861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3648 01:14:54.862130 ===================================
3649 01:14:54.865487 data_rate = 1200,PCW = 0X5800
3650 01:14:54.869219 ===================================
3651 01:14:54.872419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3652 01:14:54.878564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3653 01:14:54.881831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3654 01:14:54.888707 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3655 01:14:54.892191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3656 01:14:54.895337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3657 01:14:54.898525 [ANA_INIT] flow start
3658 01:14:54.899002 [ANA_INIT] PLL >>>>>>>>
3659 01:14:54.901776 [ANA_INIT] PLL <<<<<<<<
3660 01:14:54.905160 [ANA_INIT] MIDPI >>>>>>>>
3661 01:14:54.905669 [ANA_INIT] MIDPI <<<<<<<<
3662 01:14:54.908362 [ANA_INIT] DLL >>>>>>>>
3663 01:14:54.911941 [ANA_INIT] flow end
3664 01:14:54.914734 ============ LP4 DIFF to SE enter ============
3665 01:14:54.918353 ============ LP4 DIFF to SE exit ============
3666 01:14:54.921495 [ANA_INIT] <<<<<<<<<<<<<
3667 01:14:54.924951 [Flow] Enable top DCM control >>>>>
3668 01:14:54.928128 [Flow] Enable top DCM control <<<<<
3669 01:14:54.931475 Enable DLL master slave shuffle
3670 01:14:54.934621 ==============================================================
3671 01:14:54.937921 Gating Mode config
3672 01:14:54.944821 ==============================================================
3673 01:14:54.945333 Config description:
3674 01:14:54.954687 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3675 01:14:54.961509 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3676 01:14:54.964719 SELPH_MODE 0: By rank 1: By Phase
3677 01:14:54.971292 ==============================================================
3678 01:14:54.974585 GAT_TRACK_EN = 1
3679 01:14:54.977963 RX_GATING_MODE = 2
3680 01:14:54.981231 RX_GATING_TRACK_MODE = 2
3681 01:14:54.984583 SELPH_MODE = 1
3682 01:14:54.987975 PICG_EARLY_EN = 1
3683 01:14:54.990800 VALID_LAT_VALUE = 1
3684 01:14:54.994465 ==============================================================
3685 01:14:54.997812 Enter into Gating configuration >>>>
3686 01:14:55.001386 Exit from Gating configuration <<<<
3687 01:14:55.004203 Enter into DVFS_PRE_config >>>>>
3688 01:14:55.017443 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3689 01:14:55.020678 Exit from DVFS_PRE_config <<<<<
3690 01:14:55.023879 Enter into PICG configuration >>>>
3691 01:14:55.024339 Exit from PICG configuration <<<<
3692 01:14:55.027327 [RX_INPUT] configuration >>>>>
3693 01:14:55.030896 [RX_INPUT] configuration <<<<<
3694 01:14:55.037135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3695 01:14:55.040657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3696 01:14:55.047334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3697 01:14:55.053399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3698 01:14:55.060429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3699 01:14:55.066954 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3700 01:14:55.070665 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3701 01:14:55.073843 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3702 01:14:55.080452 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3703 01:14:55.083687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3704 01:14:55.087100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3705 01:14:55.090358 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3706 01:14:55.093550 ===================================
3707 01:14:55.097102 LPDDR4 DRAM CONFIGURATION
3708 01:14:55.100597 ===================================
3709 01:14:55.103531 EX_ROW_EN[0] = 0x0
3710 01:14:55.104007 EX_ROW_EN[1] = 0x0
3711 01:14:55.107035 LP4Y_EN = 0x0
3712 01:14:55.107601 WORK_FSP = 0x0
3713 01:14:55.109999 WL = 0x2
3714 01:14:55.110618 RL = 0x2
3715 01:14:55.113383 BL = 0x2
3716 01:14:55.113948 RPST = 0x0
3717 01:14:55.116557 RD_PRE = 0x0
3718 01:14:55.117252 WR_PRE = 0x1
3719 01:14:55.119792 WR_PST = 0x0
3720 01:14:55.123076 DBI_WR = 0x0
3721 01:14:55.123533 DBI_RD = 0x0
3722 01:14:55.126475 OTF = 0x1
3723 01:14:55.129583 ===================================
3724 01:14:55.133253 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3725 01:14:55.135950 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3726 01:14:55.139498 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 01:14:55.143052 ===================================
3728 01:14:55.146150 LPDDR4 DRAM CONFIGURATION
3729 01:14:55.149488 ===================================
3730 01:14:55.152866 EX_ROW_EN[0] = 0x10
3731 01:14:55.153395 EX_ROW_EN[1] = 0x0
3732 01:14:55.156555 LP4Y_EN = 0x0
3733 01:14:55.157066 WORK_FSP = 0x0
3734 01:14:55.159268 WL = 0x2
3735 01:14:55.159678 RL = 0x2
3736 01:14:55.162617 BL = 0x2
3737 01:14:55.163027 RPST = 0x0
3738 01:14:55.165772 RD_PRE = 0x0
3739 01:14:55.166218 WR_PRE = 0x1
3740 01:14:55.169084 WR_PST = 0x0
3741 01:14:55.172326 DBI_WR = 0x0
3742 01:14:55.172736 DBI_RD = 0x0
3743 01:14:55.175606 OTF = 0x1
3744 01:14:55.179192 ===================================
3745 01:14:55.182617 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3746 01:14:55.188164 nWR fixed to 30
3747 01:14:55.191154 [ModeRegInit_LP4] CH0 RK0
3748 01:14:55.191568 [ModeRegInit_LP4] CH0 RK1
3749 01:14:55.194935 [ModeRegInit_LP4] CH1 RK0
3750 01:14:55.197966 [ModeRegInit_LP4] CH1 RK1
3751 01:14:55.198514 match AC timing 16
3752 01:14:55.205213 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3753 01:14:55.207814 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3754 01:14:55.210746 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3755 01:14:55.217299 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3756 01:14:55.220960 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3757 01:14:55.221526 ==
3758 01:14:55.224947 Dram Type= 6, Freq= 0, CH_0, rank 0
3759 01:14:55.227629 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3760 01:14:55.228193 ==
3761 01:14:55.234202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3762 01:14:55.240579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3763 01:14:55.244301 [CA 0] Center 35 (5~66) winsize 62
3764 01:14:55.248053 [CA 1] Center 35 (5~66) winsize 62
3765 01:14:55.250615 [CA 2] Center 34 (4~65) winsize 62
3766 01:14:55.254442 [CA 3] Center 34 (4~65) winsize 62
3767 01:14:55.257307 [CA 4] Center 33 (3~64) winsize 62
3768 01:14:55.260491 [CA 5] Center 33 (3~64) winsize 62
3769 01:14:55.260950
3770 01:14:55.264037 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3771 01:14:55.264555
3772 01:14:55.267095 [CATrainingPosCal] consider 1 rank data
3773 01:14:55.270592 u2DelayCellTimex100 = 270/100 ps
3774 01:14:55.273777 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3775 01:14:55.277213 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3776 01:14:55.280447 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3777 01:14:55.283415 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3778 01:14:55.290255 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3779 01:14:55.293786 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3780 01:14:55.294395
3781 01:14:55.297055 CA PerBit enable=1, Macro0, CA PI delay=33
3782 01:14:55.297670
3783 01:14:55.300267 [CBTSetCACLKResult] CA Dly = 33
3784 01:14:55.300833 CS Dly: 5 (0~36)
3785 01:14:55.301204 ==
3786 01:14:55.303495 Dram Type= 6, Freq= 0, CH_0, rank 1
3787 01:14:55.310191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3788 01:14:55.310750 ==
3789 01:14:55.313670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3790 01:14:55.320511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3791 01:14:55.323840 [CA 0] Center 35 (5~66) winsize 62
3792 01:14:55.326978 [CA 1] Center 36 (6~66) winsize 61
3793 01:14:55.330439 [CA 2] Center 34 (4~65) winsize 62
3794 01:14:55.333318 [CA 3] Center 34 (4~65) winsize 62
3795 01:14:55.337017 [CA 4] Center 33 (3~64) winsize 62
3796 01:14:55.340245 [CA 5] Center 33 (3~64) winsize 62
3797 01:14:55.340814
3798 01:14:55.343018 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3799 01:14:55.343479
3800 01:14:55.346854 [CATrainingPosCal] consider 2 rank data
3801 01:14:55.349629 u2DelayCellTimex100 = 270/100 ps
3802 01:14:55.353301 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3803 01:14:55.356889 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3804 01:14:55.363239 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3805 01:14:55.366579 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3806 01:14:55.369786 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3807 01:14:55.373157 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3808 01:14:55.373576
3809 01:14:55.376209 CA PerBit enable=1, Macro0, CA PI delay=33
3810 01:14:55.376629
3811 01:14:55.379719 [CBTSetCACLKResult] CA Dly = 33
3812 01:14:55.380135 CS Dly: 5 (0~36)
3813 01:14:55.380464
3814 01:14:55.382985 ----->DramcWriteLeveling(PI) begin...
3815 01:14:55.386391 ==
3816 01:14:55.389662 Dram Type= 6, Freq= 0, CH_0, rank 0
3817 01:14:55.392817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3818 01:14:55.393345 ==
3819 01:14:55.396010 Write leveling (Byte 0): 29 => 29
3820 01:14:55.399417 Write leveling (Byte 1): 29 => 29
3821 01:14:55.402795 DramcWriteLeveling(PI) end<-----
3822 01:14:55.403343
3823 01:14:55.403708 ==
3824 01:14:55.405782 Dram Type= 6, Freq= 0, CH_0, rank 0
3825 01:14:55.409373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3826 01:14:55.409944 ==
3827 01:14:55.412444 [Gating] SW mode calibration
3828 01:14:55.419258 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3829 01:14:55.426113 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3830 01:14:55.429767 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3831 01:14:55.432633 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3832 01:14:55.439067 0 5 8 | B1->B0 | 3232 3030 | 0 1 | (0 1) (1 0)
3833 01:14:55.442716 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3834 01:14:55.445713 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3835 01:14:55.452761 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3836 01:14:55.455642 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3837 01:14:55.459172 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3838 01:14:55.462461 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3839 01:14:55.468773 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3840 01:14:55.472442 0 6 8 | B1->B0 | 2c2c 3535 | 0 1 | (0 0) (0 0)
3841 01:14:55.475625 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3842 01:14:55.482018 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3843 01:14:55.485242 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3844 01:14:55.488614 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3845 01:14:55.495364 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3846 01:14:55.499176 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3847 01:14:55.502126 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3848 01:14:55.508471 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3849 01:14:55.512331 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3850 01:14:55.515385 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3851 01:14:55.521750 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3852 01:14:55.525125 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3853 01:14:55.528485 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3854 01:14:55.535123 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3855 01:14:55.538211 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3856 01:14:55.541809 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3857 01:14:55.548279 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3858 01:14:55.551489 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3859 01:14:55.555131 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3860 01:14:55.561319 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3861 01:14:55.564878 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3862 01:14:55.568151 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3863 01:14:55.574685 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3864 01:14:55.577625 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3865 01:14:55.581359 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3866 01:14:55.584202 Total UI for P1: 0, mck2ui 16
3867 01:14:55.587873 best dqsien dly found for B0: ( 0, 9, 10)
3868 01:14:55.590734 Total UI for P1: 0, mck2ui 16
3869 01:14:55.594596 best dqsien dly found for B1: ( 0, 9, 8)
3870 01:14:55.597616 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3871 01:14:55.601210 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3872 01:14:55.604238
3873 01:14:55.607775 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3874 01:14:55.611021 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3875 01:14:55.614386 [Gating] SW calibration Done
3876 01:14:55.614932 ==
3877 01:14:55.617478 Dram Type= 6, Freq= 0, CH_0, rank 0
3878 01:14:55.620680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3879 01:14:55.621140 ==
3880 01:14:55.621500 RX Vref Scan: 0
3881 01:14:55.624187
3882 01:14:55.624735 RX Vref 0 -> 0, step: 1
3883 01:14:55.625101
3884 01:14:55.627445 RX Delay -230 -> 252, step: 16
3885 01:14:55.630528 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
3886 01:14:55.637213 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3887 01:14:55.640490 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3888 01:14:55.644460 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
3889 01:14:55.647608 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3890 01:14:55.650600 iDelay=218, Bit 5, Center 33 (-118 ~ 185) 304
3891 01:14:55.657111 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3892 01:14:55.660460 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3893 01:14:55.663431 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3894 01:14:55.667420 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
3895 01:14:55.673966 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
3896 01:14:55.677628 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3897 01:14:55.680051 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3898 01:14:55.683578 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3899 01:14:55.690332 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3900 01:14:55.693559 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3901 01:14:55.694132 ==
3902 01:14:55.696825 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 01:14:55.700074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3904 01:14:55.700632 ==
3905 01:14:55.703432 DQS Delay:
3906 01:14:55.703981 DQS0 = 0, DQS1 = 0
3907 01:14:55.704343 DQM Delay:
3908 01:14:55.706612 DQM0 = 43, DQM1 = 35
3909 01:14:55.707159 DQ Delay:
3910 01:14:55.710086 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
3911 01:14:55.713651 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3912 01:14:55.716924 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
3913 01:14:55.719744 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3914 01:14:55.720447
3915 01:14:55.721056
3916 01:14:55.721417 ==
3917 01:14:55.722939 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 01:14:55.729718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3919 01:14:55.730324 ==
3920 01:14:55.730700
3921 01:14:55.731036
3922 01:14:55.732625 TX Vref Scan disable
3923 01:14:55.733080 == TX Byte 0 ==
3924 01:14:55.736408 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3925 01:14:55.742926 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3926 01:14:55.743481 == TX Byte 1 ==
3927 01:14:55.746480 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3928 01:14:55.753171 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3929 01:14:55.753695 ==
3930 01:14:55.755861 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 01:14:55.759311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3932 01:14:55.759817 ==
3933 01:14:55.760149
3934 01:14:55.760455
3935 01:14:55.762562 TX Vref Scan disable
3936 01:14:55.766071 == TX Byte 0 ==
3937 01:14:55.769445 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3938 01:14:55.772497 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3939 01:14:55.775977 == TX Byte 1 ==
3940 01:14:55.779591 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3941 01:14:55.782612 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3942 01:14:55.783120
3943 01:14:55.785860 [DATLAT]
3944 01:14:55.786326 Freq=600, CH0 RK0
3945 01:14:55.786662
3946 01:14:55.789472 DATLAT Default: 0x9
3947 01:14:55.790004 0, 0xFFFF, sum = 0
3948 01:14:55.792248 1, 0xFFFF, sum = 0
3949 01:14:55.792667 2, 0xFFFF, sum = 0
3950 01:14:55.795679 3, 0xFFFF, sum = 0
3951 01:14:55.796098 4, 0xFFFF, sum = 0
3952 01:14:55.799093 5, 0xFFFF, sum = 0
3953 01:14:55.799598 6, 0xFFFF, sum = 0
3954 01:14:55.802489 7, 0x0, sum = 1
3955 01:14:55.802997 8, 0x0, sum = 2
3956 01:14:55.805577 9, 0x0, sum = 3
3957 01:14:55.806124 10, 0x0, sum = 4
3958 01:14:55.809561 best_step = 8
3959 01:14:55.810102
3960 01:14:55.810442 ==
3961 01:14:55.812686 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 01:14:55.815627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3963 01:14:55.816132 ==
3964 01:14:55.816462 RX Vref Scan: 1
3965 01:14:55.819085
3966 01:14:55.819585 RX Vref 0 -> 0, step: 1
3967 01:14:55.819918
3968 01:14:55.822148 RX Delay -179 -> 252, step: 8
3969 01:14:55.822564
3970 01:14:55.825864 Set Vref, RX VrefLevel [Byte0]: 53
3971 01:14:55.828934 [Byte1]: 46
3972 01:14:55.832106
3973 01:14:55.832521 Final RX Vref Byte 0 = 53 to rank0
3974 01:14:55.835268 Final RX Vref Byte 1 = 46 to rank0
3975 01:14:55.838838 Final RX Vref Byte 0 = 53 to rank1
3976 01:14:55.842184 Final RX Vref Byte 1 = 46 to rank1==
3977 01:14:55.845441 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 01:14:55.852157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3979 01:14:55.852675 ==
3980 01:14:55.853056 DQS Delay:
3981 01:14:55.855356 DQS0 = 0, DQS1 = 0
3982 01:14:55.855768 DQM Delay:
3983 01:14:55.856092 DQM0 = 39, DQM1 = 30
3984 01:14:55.858216 DQ Delay:
3985 01:14:55.862106 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3986 01:14:55.864788 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3987 01:14:55.868353 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3988 01:14:55.871731 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3989 01:14:55.872246
3990 01:14:55.872676
3991 01:14:55.878163 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3992 01:14:55.881576 CH0 RK0: MR19=808, MR18=4D4D
3993 01:14:55.887747 CH0_RK0: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
3994 01:14:55.888161
3995 01:14:55.891509 ----->DramcWriteLeveling(PI) begin...
3996 01:14:55.892023 ==
3997 01:14:55.895470 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 01:14:55.897939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 01:14:55.898530 ==
4000 01:14:55.901247 Write leveling (Byte 0): 29 => 29
4001 01:14:55.904426 Write leveling (Byte 1): 30 => 30
4002 01:14:55.908018 DramcWriteLeveling(PI) end<-----
4003 01:14:55.908431
4004 01:14:55.908759 ==
4005 01:14:55.911025 Dram Type= 6, Freq= 0, CH_0, rank 1
4006 01:14:55.914441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4007 01:14:55.918169 ==
4008 01:14:55.918694 [Gating] SW mode calibration
4009 01:14:55.927528 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4010 01:14:55.931112 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4011 01:14:55.934118 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4012 01:14:55.940786 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4013 01:14:55.944569 0 5 8 | B1->B0 | 3232 3232 | 1 0 | (1 0) (0 1)
4014 01:14:55.947154 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4015 01:14:55.954085 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 01:14:55.957252 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 01:14:55.960691 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 01:14:55.967010 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 01:14:55.970478 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 01:14:55.973644 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4021 01:14:55.980511 0 6 8 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
4022 01:14:55.983768 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4023 01:14:55.987214 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 01:14:55.993949 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 01:14:55.997292 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 01:14:56.000429 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 01:14:56.007094 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 01:14:56.010158 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4029 01:14:56.013645 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4030 01:14:56.019857 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4031 01:14:56.023503 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 01:14:56.026740 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 01:14:56.033239 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 01:14:56.036388 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 01:14:56.039959 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 01:14:56.046466 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 01:14:56.049828 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 01:14:56.053128 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 01:14:56.059627 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 01:14:56.063154 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 01:14:56.066460 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 01:14:56.073128 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 01:14:56.076045 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 01:14:56.079429 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 01:14:56.086117 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4046 01:14:56.089035 Total UI for P1: 0, mck2ui 16
4047 01:14:56.092995 best dqsien dly found for B1: ( 0, 9, 6)
4048 01:14:56.095992 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 01:14:56.099760 Total UI for P1: 0, mck2ui 16
4050 01:14:56.102614 best dqsien dly found for B0: ( 0, 9, 8)
4051 01:14:56.105662 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4052 01:14:56.109116 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4053 01:14:56.109659
4054 01:14:56.112314 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4055 01:14:56.115857 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4056 01:14:56.119436 [Gating] SW calibration Done
4057 01:14:56.119995 ==
4058 01:14:56.122091 Dram Type= 6, Freq= 0, CH_0, rank 1
4059 01:14:56.128817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4060 01:14:56.129323 ==
4061 01:14:56.129653 RX Vref Scan: 0
4062 01:14:56.129961
4063 01:14:56.131895 RX Vref 0 -> 0, step: 1
4064 01:14:56.132307
4065 01:14:56.135392 RX Delay -230 -> 252, step: 16
4066 01:14:56.138834 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4067 01:14:56.142354 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4068 01:14:56.145324 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4069 01:14:56.152055 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4070 01:14:56.155445 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4071 01:14:56.159004 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4072 01:14:56.161623 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4073 01:14:56.168805 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4074 01:14:56.171784 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4075 01:14:56.175323 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4076 01:14:56.178541 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4077 01:14:56.181574 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4078 01:14:56.188224 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4079 01:14:56.191719 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4080 01:14:56.194612 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4081 01:14:56.198126 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4082 01:14:56.201609 ==
4083 01:14:56.204637 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 01:14:56.208381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 01:14:56.208891 ==
4086 01:14:56.209223 DQS Delay:
4087 01:14:56.211289 DQS0 = 0, DQS1 = 0
4088 01:14:56.211700 DQM Delay:
4089 01:14:56.214596 DQM0 = 45, DQM1 = 34
4090 01:14:56.215106 DQ Delay:
4091 01:14:56.218123 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4092 01:14:56.221278 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4093 01:14:56.224558 DQ8 =25, DQ9 =9, DQ10 =41, DQ11 =33
4094 01:14:56.228522 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4095 01:14:56.229036
4096 01:14:56.229365
4097 01:14:56.229669 ==
4098 01:14:56.231022 Dram Type= 6, Freq= 0, CH_0, rank 1
4099 01:14:56.234607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4100 01:14:56.235124 ==
4101 01:14:56.235458
4102 01:14:56.235760
4103 01:14:56.237528 TX Vref Scan disable
4104 01:14:56.241025 == TX Byte 0 ==
4105 01:14:56.244790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4106 01:14:56.247863 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4107 01:14:56.250738 == TX Byte 1 ==
4108 01:14:56.254267 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4109 01:14:56.257248 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4110 01:14:56.257660 ==
4111 01:14:56.261127 Dram Type= 6, Freq= 0, CH_0, rank 1
4112 01:14:56.267090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4113 01:14:56.267586 ==
4114 01:14:56.267915
4115 01:14:56.268217
4116 01:14:56.268508 TX Vref Scan disable
4117 01:14:56.272019 == TX Byte 0 ==
4118 01:14:56.275564 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4119 01:14:56.281981 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4120 01:14:56.282506 == TX Byte 1 ==
4121 01:14:56.285185 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4122 01:14:56.291505 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4123 01:14:56.292015
4124 01:14:56.292345 [DATLAT]
4125 01:14:56.292648 Freq=600, CH0 RK1
4126 01:14:56.292948
4127 01:14:56.295386 DATLAT Default: 0x8
4128 01:14:56.295908 0, 0xFFFF, sum = 0
4129 01:14:56.298678 1, 0xFFFF, sum = 0
4130 01:14:56.301766 2, 0xFFFF, sum = 0
4131 01:14:56.302433 3, 0xFFFF, sum = 0
4132 01:14:56.304887 4, 0xFFFF, sum = 0
4133 01:14:56.305305 5, 0xFFFF, sum = 0
4134 01:14:56.307998 6, 0xFFFF, sum = 0
4135 01:14:56.308749 7, 0x0, sum = 1
4136 01:14:56.309199 8, 0x0, sum = 2
4137 01:14:56.311204 9, 0x0, sum = 3
4138 01:14:56.311578 10, 0x0, sum = 4
4139 01:14:56.314730 best_step = 8
4140 01:14:56.315328
4141 01:14:56.315853 ==
4142 01:14:56.317737 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 01:14:56.321481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4144 01:14:56.321918 ==
4145 01:14:56.324697 RX Vref Scan: 0
4146 01:14:56.325128
4147 01:14:56.325463 RX Vref 0 -> 0, step: 1
4148 01:14:56.325776
4149 01:14:56.327927 RX Delay -195 -> 252, step: 8
4150 01:14:56.335454 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4151 01:14:56.339079 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4152 01:14:56.342142 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4153 01:14:56.345207 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4154 01:14:56.351933 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4155 01:14:56.355304 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4156 01:14:56.358433 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4157 01:14:56.361617 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4158 01:14:56.368072 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4159 01:14:56.371465 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4160 01:14:56.374743 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4161 01:14:56.377883 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4162 01:14:56.381237 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4163 01:14:56.388150 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4164 01:14:56.391245 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4165 01:14:56.394758 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4166 01:14:56.394938 ==
4167 01:14:56.397861 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 01:14:56.404677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 01:14:56.404806 ==
4170 01:14:56.404908 DQS Delay:
4171 01:14:56.405002 DQS0 = 0, DQS1 = 0
4172 01:14:56.407912 DQM Delay:
4173 01:14:56.408023 DQM0 = 42, DQM1 = 32
4174 01:14:56.411279 DQ Delay:
4175 01:14:56.414289 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =36
4176 01:14:56.417818 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =48
4177 01:14:56.420870 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4178 01:14:56.424035 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4179 01:14:56.424160
4180 01:14:56.424247
4181 01:14:56.430733 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4182 01:14:56.433975 CH0 RK1: MR19=808, MR18=6B6B
4183 01:14:56.440563 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4184 01:14:56.443996 [RxdqsGatingPostProcess] freq 600
4185 01:14:56.447291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4186 01:14:56.450453 Pre-setting of DQS Precalculation
4187 01:14:56.457454 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4188 01:14:56.457864 ==
4189 01:14:56.461045 Dram Type= 6, Freq= 0, CH_1, rank 0
4190 01:14:56.463973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4191 01:14:56.464517 ==
4192 01:14:56.470588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4193 01:14:56.477153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4194 01:14:56.480496 [CA 0] Center 35 (5~66) winsize 62
4195 01:14:56.484259 [CA 1] Center 35 (5~66) winsize 62
4196 01:14:56.486980 [CA 2] Center 33 (3~64) winsize 62
4197 01:14:56.490566 [CA 3] Center 33 (3~64) winsize 62
4198 01:14:56.493746 [CA 4] Center 33 (2~64) winsize 63
4199 01:14:56.496859 [CA 5] Center 33 (2~64) winsize 63
4200 01:14:56.497435
4201 01:14:56.500420 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4202 01:14:56.500919
4203 01:14:56.504077 [CATrainingPosCal] consider 1 rank data
4204 01:14:56.507095 u2DelayCellTimex100 = 270/100 ps
4205 01:14:56.510338 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4206 01:14:56.513269 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4207 01:14:56.516621 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4208 01:14:56.520103 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4209 01:14:56.523341 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4210 01:14:56.526767 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4211 01:14:56.527005
4212 01:14:56.533067 CA PerBit enable=1, Macro0, CA PI delay=33
4213 01:14:56.533266
4214 01:14:56.536431 [CBTSetCACLKResult] CA Dly = 33
4215 01:14:56.536593 CS Dly: 4 (0~35)
4216 01:14:56.536715 ==
4217 01:14:56.539875 Dram Type= 6, Freq= 0, CH_1, rank 1
4218 01:14:56.543085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4219 01:14:56.543216 ==
4220 01:14:56.549569 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4221 01:14:56.556414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4222 01:14:56.559595 [CA 0] Center 35 (5~66) winsize 62
4223 01:14:56.563303 [CA 1] Center 34 (4~65) winsize 62
4224 01:14:56.565889 [CA 2] Center 33 (3~64) winsize 62
4225 01:14:56.569446 [CA 3] Center 33 (3~64) winsize 62
4226 01:14:56.572961 [CA 4] Center 32 (2~63) winsize 62
4227 01:14:56.576089 [CA 5] Center 32 (2~63) winsize 62
4228 01:14:56.576236
4229 01:14:56.579748 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4230 01:14:56.579898
4231 01:14:56.582659 [CATrainingPosCal] consider 2 rank data
4232 01:14:56.586224 u2DelayCellTimex100 = 270/100 ps
4233 01:14:56.589612 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4234 01:14:56.592729 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4235 01:14:56.596276 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4236 01:14:56.599412 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4237 01:14:56.606069 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4238 01:14:56.609318 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4239 01:14:56.609476
4240 01:14:56.612366 CA PerBit enable=1, Macro0, CA PI delay=32
4241 01:14:56.612572
4242 01:14:56.615863 [CBTSetCACLKResult] CA Dly = 32
4243 01:14:56.616038 CS Dly: 4 (0~36)
4244 01:14:56.616191
4245 01:14:56.619320 ----->DramcWriteLeveling(PI) begin...
4246 01:14:56.619484 ==
4247 01:14:56.622454 Dram Type= 6, Freq= 0, CH_1, rank 0
4248 01:14:56.628910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4249 01:14:56.629082 ==
4250 01:14:56.632286 Write leveling (Byte 0): 26 => 26
4251 01:14:56.635493 Write leveling (Byte 1): 29 => 29
4252 01:14:56.635671 DramcWriteLeveling(PI) end<-----
4253 01:14:56.635798
4254 01:14:56.639065 ==
4255 01:14:56.642354 Dram Type= 6, Freq= 0, CH_1, rank 0
4256 01:14:56.645519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4257 01:14:56.645657 ==
4258 01:14:56.648780 [Gating] SW mode calibration
4259 01:14:56.655833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4260 01:14:56.658669 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4261 01:14:56.665436 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 01:14:56.669386 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4263 01:14:56.672174 0 5 8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
4264 01:14:56.678768 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 01:14:56.682033 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 01:14:56.685610 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 01:14:56.692865 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 01:14:56.695603 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 01:14:56.699027 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 01:14:56.705166 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4271 01:14:56.709027 0 6 8 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
4272 01:14:56.712012 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 01:14:56.718503 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 01:14:56.721706 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 01:14:56.725083 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 01:14:56.731840 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 01:14:56.735241 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 01:14:56.738379 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4279 01:14:56.745258 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4280 01:14:56.749004 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 01:14:56.752101 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 01:14:56.758690 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 01:14:56.761952 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 01:14:56.765407 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 01:14:56.768630 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 01:14:56.775114 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 01:14:56.778351 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 01:14:56.781981 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 01:14:56.787964 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 01:14:56.791886 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 01:14:56.794770 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 01:14:56.801498 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 01:14:56.804430 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 01:14:56.807888 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 01:14:56.814134 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 01:14:56.817362 Total UI for P1: 0, mck2ui 16
4297 01:14:56.820847 best dqsien dly found for B0: ( 0, 9, 6)
4298 01:14:56.824526 Total UI for P1: 0, mck2ui 16
4299 01:14:56.827225 best dqsien dly found for B1: ( 0, 9, 6)
4300 01:14:56.830618 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4301 01:14:56.834249 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4302 01:14:56.834352
4303 01:14:56.837740 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4304 01:14:56.840463 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4305 01:14:56.843740 [Gating] SW calibration Done
4306 01:14:56.843836 ==
4307 01:14:56.847219 Dram Type= 6, Freq= 0, CH_1, rank 0
4308 01:14:56.850455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4309 01:14:56.850574 ==
4310 01:14:56.853519 RX Vref Scan: 0
4311 01:14:56.853610
4312 01:14:56.856990 RX Vref 0 -> 0, step: 1
4313 01:14:56.857080
4314 01:14:56.857151 RX Delay -230 -> 252, step: 16
4315 01:14:56.863811 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4316 01:14:56.867154 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4317 01:14:56.870659 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4318 01:14:56.874033 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4319 01:14:56.880272 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4320 01:14:56.883762 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4321 01:14:56.887024 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4322 01:14:56.890667 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4323 01:14:56.893631 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4324 01:14:56.900384 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4325 01:14:56.903571 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4326 01:14:56.907177 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4327 01:14:56.913407 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4328 01:14:56.916653 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4329 01:14:56.919879 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4330 01:14:56.923437 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4331 01:14:56.923535 ==
4332 01:14:56.926460 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 01:14:56.933349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4334 01:14:56.933448 ==
4335 01:14:56.933526 DQS Delay:
4336 01:14:56.936799 DQS0 = 0, DQS1 = 0
4337 01:14:56.936897 DQM Delay:
4338 01:14:56.936975 DQM0 = 38, DQM1 = 30
4339 01:14:56.940025 DQ Delay:
4340 01:14:56.943133 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4341 01:14:56.946243 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4342 01:14:56.949815 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4343 01:14:56.952936 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4344 01:14:56.953039
4345 01:14:56.953116
4346 01:14:56.953188 ==
4347 01:14:56.956218 Dram Type= 6, Freq= 0, CH_1, rank 0
4348 01:14:56.959464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4349 01:14:56.959550 ==
4350 01:14:56.959616
4351 01:14:56.959676
4352 01:14:56.962900 TX Vref Scan disable
4353 01:14:56.966516 == TX Byte 0 ==
4354 01:14:56.969326 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4355 01:14:56.972634 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4356 01:14:56.976410 == TX Byte 1 ==
4357 01:14:56.979187 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4358 01:14:56.982351 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4359 01:14:56.982433 ==
4360 01:14:56.985515 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 01:14:56.988989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 01:14:56.992259 ==
4363 01:14:56.992340
4364 01:14:56.992403
4365 01:14:56.992463 TX Vref Scan disable
4366 01:14:56.996343 == TX Byte 0 ==
4367 01:14:56.999662 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4368 01:14:57.006381 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4369 01:14:57.006467 == TX Byte 1 ==
4370 01:14:57.009677 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4371 01:14:57.016321 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4372 01:14:57.016426
4373 01:14:57.016505 [DATLAT]
4374 01:14:57.016578 Freq=600, CH1 RK0
4375 01:14:57.016651
4376 01:14:57.019705 DATLAT Default: 0x9
4377 01:14:57.019805 0, 0xFFFF, sum = 0
4378 01:14:57.022848 1, 0xFFFF, sum = 0
4379 01:14:57.025899 2, 0xFFFF, sum = 0
4380 01:14:57.026004 3, 0xFFFF, sum = 0
4381 01:14:57.029524 4, 0xFFFF, sum = 0
4382 01:14:57.029628 5, 0xFFFF, sum = 0
4383 01:14:57.032724 6, 0xFFFF, sum = 0
4384 01:14:57.032826 7, 0x0, sum = 1
4385 01:14:57.032908 8, 0x0, sum = 2
4386 01:14:57.035950 9, 0x0, sum = 3
4387 01:14:57.036052 10, 0x0, sum = 4
4388 01:14:57.039425 best_step = 8
4389 01:14:57.039525
4390 01:14:57.039605 ==
4391 01:14:57.042884 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 01:14:57.046029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4393 01:14:57.046127 ==
4394 01:14:57.049408 RX Vref Scan: 1
4395 01:14:57.049516
4396 01:14:57.049610 RX Vref 0 -> 0, step: 1
4397 01:14:57.049699
4398 01:14:57.052783 RX Delay -195 -> 252, step: 8
4399 01:14:57.052864
4400 01:14:57.055896 Set Vref, RX VrefLevel [Byte0]: 56
4401 01:14:57.059730 [Byte1]: 50
4402 01:14:57.063675
4403 01:14:57.063782 Final RX Vref Byte 0 = 56 to rank0
4404 01:14:57.066782 Final RX Vref Byte 1 = 50 to rank0
4405 01:14:57.070364 Final RX Vref Byte 0 = 56 to rank1
4406 01:14:57.073377 Final RX Vref Byte 1 = 50 to rank1==
4407 01:14:57.077172 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 01:14:57.083804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4409 01:14:57.084219 ==
4410 01:14:57.084543 DQS Delay:
4411 01:14:57.084862 DQS0 = 0, DQS1 = 0
4412 01:14:57.086979 DQM Delay:
4413 01:14:57.087393 DQM0 = 37, DQM1 = 30
4414 01:14:57.090394 DQ Delay:
4415 01:14:57.093512 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4416 01:14:57.097141 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4417 01:14:57.097589 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =24
4418 01:14:57.103777 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4419 01:14:57.104195
4420 01:14:57.104563
4421 01:14:57.110176 [DQSOSCAuto] RK0, (LSB)MR18= 0x7b7b, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4422 01:14:57.113596 CH1 RK0: MR19=808, MR18=7B7B
4423 01:14:57.120396 CH1_RK0: MR19=0x808, MR18=0x7B7B, DQSOSC=386, MR23=63, INC=176, DEC=117
4424 01:14:57.120803
4425 01:14:57.123229 ----->DramcWriteLeveling(PI) begin...
4426 01:14:57.123675 ==
4427 01:14:57.126646 Dram Type= 6, Freq= 0, CH_1, rank 1
4428 01:14:57.130183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4429 01:14:57.130596 ==
4430 01:14:57.133203 Write leveling (Byte 0): 29 => 29
4431 01:14:57.136725 Write leveling (Byte 1): 28 => 28
4432 01:14:57.139905 DramcWriteLeveling(PI) end<-----
4433 01:14:57.140321
4434 01:14:57.140646 ==
4435 01:14:57.143462 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 01:14:57.146464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4437 01:14:57.146881 ==
4438 01:14:57.150148 [Gating] SW mode calibration
4439 01:14:57.156333 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4440 01:14:57.163186 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4441 01:14:57.166334 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 01:14:57.172938 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4443 01:14:57.176500 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (1 1)
4444 01:14:57.179196 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 01:14:57.185963 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 01:14:57.189357 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 01:14:57.237280 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 01:14:57.239373 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 01:14:57.239870 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 01:14:57.240216 0 6 4 | B1->B0 | 2828 3030 | 1 0 | (0 0) (0 0)
4451 01:14:57.240532 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
4452 01:14:57.240831 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 01:14:57.241127 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 01:14:57.241413 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 01:14:57.241724 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 01:14:57.242005 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 01:14:57.242352 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 01:14:57.242965 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4459 01:14:57.245774 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4460 01:14:57.252286 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 01:14:57.255936 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 01:14:57.258962 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 01:14:57.262395 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 01:14:57.269040 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 01:14:57.272448 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 01:14:57.276119 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 01:14:57.281753 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 01:14:57.285457 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 01:14:57.288967 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 01:14:57.295255 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 01:14:57.298837 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 01:14:57.301945 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 01:14:57.308883 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 01:14:57.311981 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4475 01:14:57.315062 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4476 01:14:57.322138 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 01:14:57.325297 Total UI for P1: 0, mck2ui 16
4478 01:14:57.328671 best dqsien dly found for B0: ( 0, 9, 6)
4479 01:14:57.331999 Total UI for P1: 0, mck2ui 16
4480 01:14:57.335171 best dqsien dly found for B1: ( 0, 9, 8)
4481 01:14:57.338754 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4482 01:14:57.342210 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4483 01:14:57.342669
4484 01:14:57.345437 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4485 01:14:57.348647 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4486 01:14:57.351673 [Gating] SW calibration Done
4487 01:14:57.352150 ==
4488 01:14:57.355123 Dram Type= 6, Freq= 0, CH_1, rank 1
4489 01:14:57.358784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4490 01:14:57.359203 ==
4491 01:14:57.361705 RX Vref Scan: 0
4492 01:14:57.362151
4493 01:14:57.362490 RX Vref 0 -> 0, step: 1
4494 01:14:57.362800
4495 01:14:57.364858 RX Delay -230 -> 252, step: 16
4496 01:14:57.371526 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4497 01:14:57.374946 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4498 01:14:57.378297 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4499 01:14:57.382059 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4500 01:14:57.388100 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4501 01:14:57.391454 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4502 01:14:57.394599 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4503 01:14:57.398383 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4504 01:14:57.401363 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4505 01:14:57.407979 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4506 01:14:57.411347 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4507 01:14:57.414491 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4508 01:14:57.417669 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4509 01:14:57.424679 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4510 01:14:57.427761 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4511 01:14:57.430877 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4512 01:14:57.431294 ==
4513 01:14:57.434337 Dram Type= 6, Freq= 0, CH_1, rank 1
4514 01:14:57.437700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4515 01:14:57.440883 ==
4516 01:14:57.441293 DQS Delay:
4517 01:14:57.441621 DQS0 = 0, DQS1 = 0
4518 01:14:57.444117 DQM Delay:
4519 01:14:57.444525 DQM0 = 40, DQM1 = 33
4520 01:14:57.447881 DQ Delay:
4521 01:14:57.451169 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4522 01:14:57.451673 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4523 01:14:57.454542 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4524 01:14:57.457661 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4525 01:14:57.461094
4526 01:14:57.461602
4527 01:14:57.461930 ==
4528 01:14:57.464334 Dram Type= 6, Freq= 0, CH_1, rank 1
4529 01:14:57.467107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4530 01:14:57.467522 ==
4531 01:14:57.467859
4532 01:14:57.468163
4533 01:14:57.470671 TX Vref Scan disable
4534 01:14:57.471081 == TX Byte 0 ==
4535 01:14:57.477261 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 01:14:57.480539 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 01:14:57.481022 == TX Byte 1 ==
4538 01:14:57.487392 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4539 01:14:57.490375 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4540 01:14:57.490787 ==
4541 01:14:57.493957 Dram Type= 6, Freq= 0, CH_1, rank 1
4542 01:14:57.497043 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4543 01:14:57.497456 ==
4544 01:14:57.497784
4545 01:14:57.500094
4546 01:14:57.500506 TX Vref Scan disable
4547 01:14:57.503528 == TX Byte 0 ==
4548 01:14:57.507105 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4549 01:14:57.513414 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4550 01:14:57.513833 == TX Byte 1 ==
4551 01:14:57.516588 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4552 01:14:57.523369 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4553 01:14:57.523863
4554 01:14:57.524188 [DATLAT]
4555 01:14:57.524492 Freq=600, CH1 RK1
4556 01:14:57.524790
4557 01:14:57.526852 DATLAT Default: 0x8
4558 01:14:57.529724 0, 0xFFFF, sum = 0
4559 01:14:57.530193 1, 0xFFFF, sum = 0
4560 01:14:57.533483 2, 0xFFFF, sum = 0
4561 01:14:57.533907 3, 0xFFFF, sum = 0
4562 01:14:57.536704 4, 0xFFFF, sum = 0
4563 01:14:57.537171 5, 0xFFFF, sum = 0
4564 01:14:57.539994 6, 0xFFFF, sum = 0
4565 01:14:57.540417 7, 0x0, sum = 1
4566 01:14:57.543435 8, 0x0, sum = 2
4567 01:14:57.543861 9, 0x0, sum = 3
4568 01:14:57.544197 10, 0x0, sum = 4
4569 01:14:57.546841 best_step = 8
4570 01:14:57.547293
4571 01:14:57.547629 ==
4572 01:14:57.549754 Dram Type= 6, Freq= 0, CH_1, rank 1
4573 01:14:57.552943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4574 01:14:57.553423 ==
4575 01:14:57.556915 RX Vref Scan: 0
4576 01:14:57.557423
4577 01:14:57.559962 RX Vref 0 -> 0, step: 1
4578 01:14:57.560468
4579 01:14:57.560800 RX Delay -195 -> 252, step: 8
4580 01:14:57.567185 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4581 01:14:57.570567 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4582 01:14:57.574397 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4583 01:14:57.577286 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4584 01:14:57.583640 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4585 01:14:57.587173 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4586 01:14:57.590268 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4587 01:14:57.594008 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4588 01:14:57.600645 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4589 01:14:57.604259 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4590 01:14:57.607078 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4591 01:14:57.610775 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4592 01:14:57.616904 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4593 01:14:57.620932 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4594 01:14:57.624109 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4595 01:14:57.626701 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4596 01:14:57.627139 ==
4597 01:14:57.630628 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 01:14:57.636667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4599 01:14:57.637268 ==
4600 01:14:57.637618 DQS Delay:
4601 01:14:57.637931 DQS0 = 0, DQS1 = 0
4602 01:14:57.640442 DQM Delay:
4603 01:14:57.640950 DQM0 = 37, DQM1 = 29
4604 01:14:57.643211 DQ Delay:
4605 01:14:57.647158 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4606 01:14:57.650062 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4607 01:14:57.653409 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4608 01:14:57.656645 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4609 01:14:57.657062
4610 01:14:57.657391
4611 01:14:57.663743 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4612 01:14:57.666539 CH1 RK1: MR19=808, MR18=5858
4613 01:14:57.673009 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4614 01:14:57.676643 [RxdqsGatingPostProcess] freq 600
4615 01:14:57.680146 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4616 01:14:57.683300 Pre-setting of DQS Precalculation
4617 01:14:57.689718 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4618 01:14:57.696183 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4619 01:14:57.703056 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4620 01:14:57.703571
4621 01:14:57.703900
4622 01:14:57.706699 [Calibration Summary] 1200 Mbps
4623 01:14:57.707211 CH 0, Rank 0
4624 01:14:57.709888 SW Impedance : PASS
4625 01:14:57.712785 DUTY Scan : NO K
4626 01:14:57.713217 ZQ Calibration : PASS
4627 01:14:57.716508 Jitter Meter : NO K
4628 01:14:57.719638 CBT Training : PASS
4629 01:14:57.720057 Write leveling : PASS
4630 01:14:57.723240 RX DQS gating : PASS
4631 01:14:57.726202 RX DQ/DQS(RDDQC) : PASS
4632 01:14:57.726618 TX DQ/DQS : PASS
4633 01:14:57.729093 RX DATLAT : PASS
4634 01:14:57.732495 RX DQ/DQS(Engine): PASS
4635 01:14:57.732949 TX OE : NO K
4636 01:14:57.735902 All Pass.
4637 01:14:57.736356
4638 01:14:57.736719 CH 0, Rank 1
4639 01:14:57.739238 SW Impedance : PASS
4640 01:14:57.739695 DUTY Scan : NO K
4641 01:14:57.742217 ZQ Calibration : PASS
4642 01:14:57.745485 Jitter Meter : NO K
4643 01:14:57.745893 CBT Training : PASS
4644 01:14:57.748791 Write leveling : PASS
4645 01:14:57.752539 RX DQS gating : PASS
4646 01:14:57.752961 RX DQ/DQS(RDDQC) : PASS
4647 01:14:57.755813 TX DQ/DQS : PASS
4648 01:14:57.759005 RX DATLAT : PASS
4649 01:14:57.759426 RX DQ/DQS(Engine): PASS
4650 01:14:57.762556 TX OE : NO K
4651 01:14:57.762977 All Pass.
4652 01:14:57.763308
4653 01:14:57.765620 CH 1, Rank 0
4654 01:14:57.766063 SW Impedance : PASS
4655 01:14:57.768838 DUTY Scan : NO K
4656 01:14:57.769253 ZQ Calibration : PASS
4657 01:14:57.772139 Jitter Meter : NO K
4658 01:14:57.775398 CBT Training : PASS
4659 01:14:57.775813 Write leveling : PASS
4660 01:14:57.778639 RX DQS gating : PASS
4661 01:14:57.781801 RX DQ/DQS(RDDQC) : PASS
4662 01:14:57.782335 TX DQ/DQS : PASS
4663 01:14:57.785132 RX DATLAT : PASS
4664 01:14:57.788591 RX DQ/DQS(Engine): PASS
4665 01:14:57.789008 TX OE : NO K
4666 01:14:57.791730 All Pass.
4667 01:14:57.792145
4668 01:14:57.792474 CH 1, Rank 1
4669 01:14:57.795185 SW Impedance : PASS
4670 01:14:57.795602 DUTY Scan : NO K
4671 01:14:57.798616 ZQ Calibration : PASS
4672 01:14:57.802138 Jitter Meter : NO K
4673 01:14:57.802649 CBT Training : PASS
4674 01:14:57.805233 Write leveling : PASS
4675 01:14:57.808536 RX DQS gating : PASS
4676 01:14:57.809046 RX DQ/DQS(RDDQC) : PASS
4677 01:14:57.811758 TX DQ/DQS : PASS
4678 01:14:57.815417 RX DATLAT : PASS
4679 01:14:57.815927 RX DQ/DQS(Engine): PASS
4680 01:14:57.818631 TX OE : NO K
4681 01:14:57.819204 All Pass.
4682 01:14:57.819555
4683 01:14:57.821703 DramC Write-DBI off
4684 01:14:57.825255 PER_BANK_REFRESH: Hybrid Mode
4685 01:14:57.825670 TX_TRACKING: ON
4686 01:14:57.835410 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4687 01:14:57.838193 [FAST_K] Save calibration result to emmc
4688 01:14:57.841557 dramc_set_vcore_voltage set vcore to 662500
4689 01:14:57.844528 Read voltage for 933, 3
4690 01:14:57.844944 Vio18 = 0
4691 01:14:57.845403 Vcore = 662500
4692 01:14:57.847873 Vdram = 0
4693 01:14:57.848288 Vddq = 0
4694 01:14:57.848617 Vmddr = 0
4695 01:14:57.854601 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4696 01:14:57.857820 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4697 01:14:57.861580 MEM_TYPE=3, freq_sel=17
4698 01:14:57.864917 sv_algorithm_assistance_LP4_1600
4699 01:14:57.868025 ============ PULL DRAM RESETB DOWN ============
4700 01:14:57.870993 ========== PULL DRAM RESETB DOWN end =========
4701 01:14:57.877871 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4702 01:14:57.882004 ===================================
4703 01:14:57.884261 LPDDR4 DRAM CONFIGURATION
4704 01:14:57.888264 ===================================
4705 01:14:57.888788 EX_ROW_EN[0] = 0x0
4706 01:14:57.890996 EX_ROW_EN[1] = 0x0
4707 01:14:57.891454 LP4Y_EN = 0x0
4708 01:14:57.894486 WORK_FSP = 0x0
4709 01:14:57.894964 WL = 0x3
4710 01:14:57.897542 RL = 0x3
4711 01:14:57.898000 BL = 0x2
4712 01:14:57.900691 RPST = 0x0
4713 01:14:57.901193 RD_PRE = 0x0
4714 01:14:57.904078 WR_PRE = 0x1
4715 01:14:57.904526 WR_PST = 0x0
4716 01:14:57.907845 DBI_WR = 0x0
4717 01:14:57.908263 DBI_RD = 0x0
4718 01:14:57.910663 OTF = 0x1
4719 01:14:57.914327 ===================================
4720 01:14:57.917961 ===================================
4721 01:14:57.918506 ANA top config
4722 01:14:57.920856 ===================================
4723 01:14:57.924246 DLL_ASYNC_EN = 0
4724 01:14:57.927236 ALL_SLAVE_EN = 1
4725 01:14:57.930488 NEW_RANK_MODE = 1
4726 01:14:57.930910 DLL_IDLE_MODE = 1
4727 01:14:57.934250 LP45_APHY_COMB_EN = 1
4728 01:14:57.937332 TX_ODT_DIS = 1
4729 01:14:57.940397 NEW_8X_MODE = 1
4730 01:14:57.943760 ===================================
4731 01:14:57.946934 ===================================
4732 01:14:57.950362 data_rate = 1866
4733 01:14:57.954005 CKR = 1
4734 01:14:57.954565 DQ_P2S_RATIO = 8
4735 01:14:57.956827 ===================================
4736 01:14:57.960298 CA_P2S_RATIO = 8
4737 01:14:57.963704 DQ_CA_OPEN = 0
4738 01:14:57.967692 DQ_SEMI_OPEN = 0
4739 01:14:57.970465 CA_SEMI_OPEN = 0
4740 01:14:57.973212 CA_FULL_RATE = 0
4741 01:14:57.973670 DQ_CKDIV4_EN = 1
4742 01:14:57.976850 CA_CKDIV4_EN = 1
4743 01:14:57.980287 CA_PREDIV_EN = 0
4744 01:14:57.983627 PH8_DLY = 0
4745 01:14:57.987474 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4746 01:14:57.990225 DQ_AAMCK_DIV = 4
4747 01:14:57.990688 CA_AAMCK_DIV = 4
4748 01:14:57.993971 CA_ADMCK_DIV = 4
4749 01:14:57.996632 DQ_TRACK_CA_EN = 0
4750 01:14:58.000047 CA_PICK = 933
4751 01:14:58.003602 CA_MCKIO = 933
4752 01:14:58.006500 MCKIO_SEMI = 0
4753 01:14:58.010130 PLL_FREQ = 3732
4754 01:14:58.010681 DQ_UI_PI_RATIO = 32
4755 01:14:58.013095 CA_UI_PI_RATIO = 0
4756 01:14:58.016351 ===================================
4757 01:14:58.019593 ===================================
4758 01:14:58.023090 memory_type:LPDDR4
4759 01:14:58.026184 GP_NUM : 10
4760 01:14:58.026677 SRAM_EN : 1
4761 01:14:58.029315 MD32_EN : 0
4762 01:14:58.032923 ===================================
4763 01:14:58.036081 [ANA_INIT] >>>>>>>>>>>>>>
4764 01:14:58.039064 <<<<<< [CONFIGURE PHASE]: ANA_TX
4765 01:14:58.042476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4766 01:14:58.046669 ===================================
4767 01:14:58.047183 data_rate = 1866,PCW = 0X8f00
4768 01:14:58.049492 ===================================
4769 01:14:58.053063 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4770 01:14:58.059473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4771 01:14:58.066069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4772 01:14:58.069356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4773 01:14:58.072551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4774 01:14:58.076057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4775 01:14:58.079533 [ANA_INIT] flow start
4776 01:14:58.082475 [ANA_INIT] PLL >>>>>>>>
4777 01:14:58.082998 [ANA_INIT] PLL <<<<<<<<
4778 01:14:58.085814 [ANA_INIT] MIDPI >>>>>>>>
4779 01:14:58.089382 [ANA_INIT] MIDPI <<<<<<<<
4780 01:14:58.089896 [ANA_INIT] DLL >>>>>>>>
4781 01:14:58.092454 [ANA_INIT] flow end
4782 01:14:58.095921 ============ LP4 DIFF to SE enter ============
4783 01:14:58.099036 ============ LP4 DIFF to SE exit ============
4784 01:14:58.102461 [ANA_INIT] <<<<<<<<<<<<<
4785 01:14:58.105670 [Flow] Enable top DCM control >>>>>
4786 01:14:58.108806 [Flow] Enable top DCM control <<<<<
4787 01:14:58.112098 Enable DLL master slave shuffle
4788 01:14:58.118969 ==============================================================
4789 01:14:58.119483 Gating Mode config
4790 01:14:58.125071 ==============================================================
4791 01:14:58.128416 Config description:
4792 01:14:58.135136 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4793 01:14:58.142415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4794 01:14:58.148174 SELPH_MODE 0: By rank 1: By Phase
4795 01:14:58.155177 ==============================================================
4796 01:14:58.155714 GAT_TRACK_EN = 1
4797 01:14:58.158651 RX_GATING_MODE = 2
4798 01:14:58.161684 RX_GATING_TRACK_MODE = 2
4799 01:14:58.165352 SELPH_MODE = 1
4800 01:14:58.168552 PICG_EARLY_EN = 1
4801 01:14:58.171448 VALID_LAT_VALUE = 1
4802 01:14:58.178122 ==============================================================
4803 01:14:58.181647 Enter into Gating configuration >>>>
4804 01:14:58.184909 Exit from Gating configuration <<<<
4805 01:14:58.188166 Enter into DVFS_PRE_config >>>>>
4806 01:14:58.198230 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4807 01:14:58.201368 Exit from DVFS_PRE_config <<<<<
4808 01:14:58.205043 Enter into PICG configuration >>>>
4809 01:14:58.208334 Exit from PICG configuration <<<<
4810 01:14:58.211577 [RX_INPUT] configuration >>>>>
4811 01:14:58.214545 [RX_INPUT] configuration <<<<<
4812 01:14:58.217880 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4813 01:14:58.224064 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4814 01:14:58.230584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4815 01:14:58.234146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4816 01:14:58.240970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4817 01:14:58.247300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4818 01:14:58.250835 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4819 01:14:58.256991 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4820 01:14:58.260995 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4821 01:14:58.263897 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4822 01:14:58.267174 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4823 01:14:58.274133 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4824 01:14:58.276990 ===================================
4825 01:14:58.277395 LPDDR4 DRAM CONFIGURATION
4826 01:14:58.280196 ===================================
4827 01:14:58.283611 EX_ROW_EN[0] = 0x0
4828 01:14:58.286718 EX_ROW_EN[1] = 0x0
4829 01:14:58.287131 LP4Y_EN = 0x0
4830 01:14:58.290263 WORK_FSP = 0x0
4831 01:14:58.290672 WL = 0x3
4832 01:14:58.293696 RL = 0x3
4833 01:14:58.294161 BL = 0x2
4834 01:14:58.296737 RPST = 0x0
4835 01:14:58.297180 RD_PRE = 0x0
4836 01:14:58.299826 WR_PRE = 0x1
4837 01:14:58.300241 WR_PST = 0x0
4838 01:14:58.303481 DBI_WR = 0x0
4839 01:14:58.303895 DBI_RD = 0x0
4840 01:14:58.306771 OTF = 0x1
4841 01:14:58.310137 ===================================
4842 01:14:58.313085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4843 01:14:58.316369 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4844 01:14:58.322957 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 01:14:58.326435 ===================================
4846 01:14:58.329747 LPDDR4 DRAM CONFIGURATION
4847 01:14:58.330261 ===================================
4848 01:14:58.332812 EX_ROW_EN[0] = 0x10
4849 01:14:58.336201 EX_ROW_EN[1] = 0x0
4850 01:14:58.336496 LP4Y_EN = 0x0
4851 01:14:58.339521 WORK_FSP = 0x0
4852 01:14:58.339748 WL = 0x3
4853 01:14:58.342681 RL = 0x3
4854 01:14:58.342903 BL = 0x2
4855 01:14:58.345984 RPST = 0x0
4856 01:14:58.346222 RD_PRE = 0x0
4857 01:14:58.349404 WR_PRE = 0x1
4858 01:14:58.349624 WR_PST = 0x0
4859 01:14:58.352496 DBI_WR = 0x0
4860 01:14:58.352718 DBI_RD = 0x0
4861 01:14:58.355778 OTF = 0x1
4862 01:14:58.359210 ===================================
4863 01:14:58.366013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4864 01:14:58.369070 nWR fixed to 30
4865 01:14:58.372479 [ModeRegInit_LP4] CH0 RK0
4866 01:14:58.372640 [ModeRegInit_LP4] CH0 RK1
4867 01:14:58.375818 [ModeRegInit_LP4] CH1 RK0
4868 01:14:58.379148 [ModeRegInit_LP4] CH1 RK1
4869 01:14:58.379387 match AC timing 8
4870 01:14:58.385372 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4871 01:14:58.388637 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4872 01:14:58.392354 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4873 01:14:58.398831 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4874 01:14:58.401852 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4875 01:14:58.402051 ==
4876 01:14:58.405413 Dram Type= 6, Freq= 0, CH_0, rank 0
4877 01:14:58.408904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4878 01:14:58.409127 ==
4879 01:14:58.415277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4880 01:14:58.421868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4881 01:14:58.425164 [CA 0] Center 38 (8~69) winsize 62
4882 01:14:58.428533 [CA 1] Center 38 (8~69) winsize 62
4883 01:14:58.431633 [CA 2] Center 36 (6~67) winsize 62
4884 01:14:58.435141 [CA 3] Center 36 (6~67) winsize 62
4885 01:14:58.438407 [CA 4] Center 34 (4~65) winsize 62
4886 01:14:58.441791 [CA 5] Center 34 (4~65) winsize 62
4887 01:14:58.442093
4888 01:14:58.445236 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4889 01:14:58.445602
4890 01:14:58.448627 [CATrainingPosCal] consider 1 rank data
4891 01:14:58.452027 u2DelayCellTimex100 = 270/100 ps
4892 01:14:58.455399 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4893 01:14:58.458550 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4894 01:14:58.461730 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4895 01:14:58.468125 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4896 01:14:58.471590 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4897 01:14:58.475084 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4898 01:14:58.475541
4899 01:14:58.477899 CA PerBit enable=1, Macro0, CA PI delay=34
4900 01:14:58.478431
4901 01:14:58.481518 [CBTSetCACLKResult] CA Dly = 34
4902 01:14:58.482229 CS Dly: 7 (0~38)
4903 01:14:58.482743 ==
4904 01:14:58.484556 Dram Type= 6, Freq= 0, CH_0, rank 1
4905 01:14:58.491213 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4906 01:14:58.491736 ==
4907 01:14:58.494510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4908 01:14:58.501211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4909 01:14:58.504891 [CA 0] Center 38 (8~69) winsize 62
4910 01:14:58.507809 [CA 1] Center 38 (7~69) winsize 63
4911 01:14:58.510957 [CA 2] Center 36 (5~67) winsize 63
4912 01:14:58.514523 [CA 3] Center 35 (5~66) winsize 62
4913 01:14:58.517419 [CA 4] Center 34 (4~65) winsize 62
4914 01:14:58.520771 [CA 5] Center 34 (4~65) winsize 62
4915 01:14:58.521187
4916 01:14:58.523973 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4917 01:14:58.524388
4918 01:14:58.527502 [CATrainingPosCal] consider 2 rank data
4919 01:14:58.530640 u2DelayCellTimex100 = 270/100 ps
4920 01:14:58.534180 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4921 01:14:58.541145 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4922 01:14:58.544032 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4923 01:14:58.547522 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4924 01:14:58.550631 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4925 01:14:58.554138 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4926 01:14:58.554558
4927 01:14:58.557421 CA PerBit enable=1, Macro0, CA PI delay=34
4928 01:14:58.557931
4929 01:14:58.560784 [CBTSetCACLKResult] CA Dly = 34
4930 01:14:58.563796 CS Dly: 7 (0~38)
4931 01:14:58.564211
4932 01:14:58.567471 ----->DramcWriteLeveling(PI) begin...
4933 01:14:58.567893 ==
4934 01:14:58.570743 Dram Type= 6, Freq= 0, CH_0, rank 0
4935 01:14:58.573912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4936 01:14:58.574431 ==
4937 01:14:58.576987 Write leveling (Byte 0): 29 => 29
4938 01:14:58.580283 Write leveling (Byte 1): 27 => 27
4939 01:14:58.583788 DramcWriteLeveling(PI) end<-----
4940 01:14:58.584358
4941 01:14:58.584697 ==
4942 01:14:58.586982 Dram Type= 6, Freq= 0, CH_0, rank 0
4943 01:14:58.590307 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4944 01:14:58.590869 ==
4945 01:14:58.593636 [Gating] SW mode calibration
4946 01:14:58.600008 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4947 01:14:58.606729 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4948 01:14:58.610208 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4949 01:14:58.613458 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4950 01:14:58.620521 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4951 01:14:58.623415 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4952 01:14:58.626811 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4953 01:14:58.633171 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4954 01:14:58.636647 0 10 24 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
4955 01:14:58.639953 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4956 01:14:58.646376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4957 01:14:58.649761 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4958 01:14:58.653290 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4959 01:14:58.659809 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4960 01:14:58.663680 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4961 01:14:58.666631 0 11 20 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
4962 01:14:58.673245 0 11 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4963 01:14:58.676113 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4964 01:14:58.680017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4965 01:14:58.686181 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4966 01:14:58.689289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4967 01:14:58.692656 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4968 01:14:58.699242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4969 01:14:58.702727 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4970 01:14:58.706609 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4971 01:14:58.712846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4972 01:14:58.715996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4973 01:14:58.719090 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4974 01:14:58.726219 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4975 01:14:58.729012 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4976 01:14:58.732284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4977 01:14:58.739036 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4978 01:14:58.741995 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4979 01:14:58.745523 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4980 01:14:58.751926 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4981 01:14:58.755252 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4982 01:14:58.758693 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4983 01:14:58.765867 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4984 01:14:58.768645 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4985 01:14:58.771965 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4986 01:14:58.779067 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4987 01:14:58.779583 Total UI for P1: 0, mck2ui 16
4988 01:14:58.784999 best dqsien dly found for B0: ( 0, 14, 18)
4989 01:14:58.785417 Total UI for P1: 0, mck2ui 16
4990 01:14:58.791763 best dqsien dly found for B1: ( 0, 14, 20)
4991 01:14:58.794954 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
4992 01:14:58.798656 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4993 01:14:58.799189
4994 01:14:58.802342 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
4995 01:14:58.805717 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4996 01:14:58.808484 [Gating] SW calibration Done
4997 01:14:58.808899 ==
4998 01:14:58.811954 Dram Type= 6, Freq= 0, CH_0, rank 0
4999 01:14:58.815189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5000 01:14:58.815614 ==
5001 01:14:58.818465 RX Vref Scan: 0
5002 01:14:58.818884
5003 01:14:58.819215 RX Vref 0 -> 0, step: 1
5004 01:14:58.821276
5005 01:14:58.821694 RX Delay -80 -> 252, step: 8
5006 01:14:58.827866 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5007 01:14:58.831429 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5008 01:14:58.834622 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5009 01:14:58.838007 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5010 01:14:58.841395 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5011 01:14:58.844925 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5012 01:14:58.851082 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5013 01:14:58.854825 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5014 01:14:58.857736 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5015 01:14:58.861633 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5016 01:14:58.864865 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5017 01:14:58.870687 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5018 01:14:58.874097 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5019 01:14:58.877594 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5020 01:14:58.881466 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5021 01:14:58.884053 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5022 01:14:58.884474 ==
5023 01:14:58.887638 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 01:14:58.894129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5025 01:14:58.894550 ==
5026 01:14:58.894879 DQS Delay:
5027 01:14:58.897583 DQS0 = 0, DQS1 = 0
5028 01:14:58.898010 DQM Delay:
5029 01:14:58.900828 DQM0 = 96, DQM1 = 82
5030 01:14:58.901244 DQ Delay:
5031 01:14:58.904290 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5032 01:14:58.907578 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5033 01:14:58.910884 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5034 01:14:58.914165 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5035 01:14:58.914670
5036 01:14:58.915005
5037 01:14:58.915314 ==
5038 01:14:58.917667 Dram Type= 6, Freq= 0, CH_0, rank 0
5039 01:14:58.920750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5040 01:14:58.921307 ==
5041 01:14:58.921673
5042 01:14:58.922010
5043 01:14:58.924414 TX Vref Scan disable
5044 01:14:58.927115 == TX Byte 0 ==
5045 01:14:58.930455 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5046 01:14:58.934013 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5047 01:14:58.937008 == TX Byte 1 ==
5048 01:14:58.940625 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5049 01:14:58.943763 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5050 01:14:58.944198 ==
5051 01:14:58.946748 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 01:14:58.954192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5053 01:14:58.954699 ==
5054 01:14:58.955034
5055 01:14:58.955341
5056 01:14:58.955633 TX Vref Scan disable
5057 01:14:58.957539 == TX Byte 0 ==
5058 01:14:58.960677 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5059 01:14:58.967824 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5060 01:14:58.968334 == TX Byte 1 ==
5061 01:14:58.970825 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5062 01:14:58.977242 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5063 01:14:58.977661
5064 01:14:58.977990 [DATLAT]
5065 01:14:58.978394 Freq=933, CH0 RK0
5066 01:14:58.978716
5067 01:14:58.980283 DATLAT Default: 0xd
5068 01:14:58.984128 0, 0xFFFF, sum = 0
5069 01:14:58.984551 1, 0xFFFF, sum = 0
5070 01:14:58.987277 2, 0xFFFF, sum = 0
5071 01:14:58.987702 3, 0xFFFF, sum = 0
5072 01:14:58.990162 4, 0xFFFF, sum = 0
5073 01:14:58.990588 5, 0xFFFF, sum = 0
5074 01:14:58.993735 6, 0xFFFF, sum = 0
5075 01:14:58.994225 7, 0xFFFF, sum = 0
5076 01:14:58.997079 8, 0xFFFF, sum = 0
5077 01:14:58.997499 9, 0xFFFF, sum = 0
5078 01:14:59.000209 10, 0x0, sum = 1
5079 01:14:59.000662 11, 0x0, sum = 2
5080 01:14:59.003499 12, 0x0, sum = 3
5081 01:14:59.003920 13, 0x0, sum = 4
5082 01:14:59.004252 best_step = 11
5083 01:14:59.006874
5084 01:14:59.007371 ==
5085 01:14:59.010293 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 01:14:59.013628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5087 01:14:59.014080 ==
5088 01:14:59.014443 RX Vref Scan: 1
5089 01:14:59.014753
5090 01:14:59.016998 RX Vref 0 -> 0, step: 1
5091 01:14:59.017431
5092 01:14:59.020630 RX Delay -77 -> 252, step: 4
5093 01:14:59.021169
5094 01:14:59.023788 Set Vref, RX VrefLevel [Byte0]: 53
5095 01:14:59.027419 [Byte1]: 46
5096 01:14:59.027952
5097 01:14:59.030708 Final RX Vref Byte 0 = 53 to rank0
5098 01:14:59.033868 Final RX Vref Byte 1 = 46 to rank0
5099 01:14:59.037335 Final RX Vref Byte 0 = 53 to rank1
5100 01:14:59.040107 Final RX Vref Byte 1 = 46 to rank1==
5101 01:14:59.043316 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 01:14:59.046829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5103 01:14:59.050145 ==
5104 01:14:59.050644 DQS Delay:
5105 01:14:59.050975 DQS0 = 0, DQS1 = 0
5106 01:14:59.053360 DQM Delay:
5107 01:14:59.053843 DQM0 = 97, DQM1 = 86
5108 01:14:59.056672 DQ Delay:
5109 01:14:59.060150 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5110 01:14:59.063330 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =104
5111 01:14:59.066724 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5112 01:14:59.070001 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5113 01:14:59.070541
5114 01:14:59.070880
5115 01:14:59.076907 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5116 01:14:59.079777 CH0 RK0: MR19=505, MR18=1B1B
5117 01:14:59.086580 CH0_RK0: MR19=0x505, MR18=0x1B1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5118 01:14:59.087061
5119 01:14:59.089706 ----->DramcWriteLeveling(PI) begin...
5120 01:14:59.090167 ==
5121 01:14:59.093410 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 01:14:59.096874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5123 01:14:59.097389 ==
5124 01:14:59.099707 Write leveling (Byte 0): 30 => 30
5125 01:14:59.103323 Write leveling (Byte 1): 30 => 30
5126 01:14:59.106500 DramcWriteLeveling(PI) end<-----
5127 01:14:59.106918
5128 01:14:59.107245 ==
5129 01:14:59.110050 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 01:14:59.113610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5131 01:14:59.114174 ==
5132 01:14:59.116547 [Gating] SW mode calibration
5133 01:14:59.123261 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 01:14:59.129870 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5135 01:14:59.133207 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 01:14:59.139521 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 01:14:59.142731 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 01:14:59.146167 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 01:14:59.153157 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 01:14:59.156535 0 10 20 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
5141 01:14:59.159824 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5142 01:14:59.166291 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 01:14:59.169663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 01:14:59.172862 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 01:14:59.179006 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 01:14:59.182365 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 01:14:59.186354 0 11 16 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
5148 01:14:59.192367 0 11 20 | B1->B0 | 2b2b 3434 | 1 0 | (0 0) (0 0)
5149 01:14:59.195898 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5150 01:14:59.198992 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 01:14:59.205751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 01:14:59.209126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 01:14:59.212148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 01:14:59.215902 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 01:14:59.222356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 01:14:59.225673 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5157 01:14:59.228883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5158 01:14:59.235541 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 01:14:59.238779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 01:14:59.241982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 01:14:59.248754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 01:14:59.252224 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 01:14:59.255058 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 01:14:59.261455 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 01:14:59.265226 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 01:14:59.268573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 01:14:59.275007 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 01:14:59.278245 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 01:14:59.282063 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 01:14:59.288479 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 01:14:59.291401 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 01:14:59.294775 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5173 01:14:59.301699 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 01:14:59.305279 Total UI for P1: 0, mck2ui 16
5175 01:14:59.308151 best dqsien dly found for B0: ( 0, 14, 20)
5176 01:14:59.311647 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 01:14:59.314714 Total UI for P1: 0, mck2ui 16
5178 01:14:59.318204 best dqsien dly found for B1: ( 0, 14, 22)
5179 01:14:59.321293 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5180 01:14:59.324593 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5181 01:14:59.325051
5182 01:14:59.327871 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5183 01:14:59.334412 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5184 01:14:59.334830 [Gating] SW calibration Done
5185 01:14:59.335163 ==
5186 01:14:59.338000 Dram Type= 6, Freq= 0, CH_0, rank 1
5187 01:14:59.344301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5188 01:14:59.344718 ==
5189 01:14:59.345050 RX Vref Scan: 0
5190 01:14:59.345362
5191 01:14:59.347993 RX Vref 0 -> 0, step: 1
5192 01:14:59.348435
5193 01:14:59.351316 RX Delay -80 -> 252, step: 8
5194 01:14:59.354734 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5195 01:14:59.357771 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5196 01:14:59.361068 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5197 01:14:59.364599 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5198 01:14:59.370788 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5199 01:14:59.374217 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5200 01:14:59.377449 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5201 01:14:59.380813 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5202 01:14:59.384157 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5203 01:14:59.390757 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5204 01:14:59.394077 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5205 01:14:59.397646 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5206 01:14:59.400766 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5207 01:14:59.403947 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5208 01:14:59.410622 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5209 01:14:59.413800 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5210 01:14:59.414268 ==
5211 01:14:59.417381 Dram Type= 6, Freq= 0, CH_0, rank 1
5212 01:14:59.420478 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5213 01:14:59.420901 ==
5214 01:14:59.421233 DQS Delay:
5215 01:14:59.423787 DQS0 = 0, DQS1 = 0
5216 01:14:59.424480 DQM Delay:
5217 01:14:59.427259 DQM0 = 95, DQM1 = 85
5218 01:14:59.427768 DQ Delay:
5219 01:14:59.430202 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5220 01:14:59.433795 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5221 01:14:59.436832 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5222 01:14:59.440469 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5223 01:14:59.440894
5224 01:14:59.441322
5225 01:14:59.441726 ==
5226 01:14:59.443926 Dram Type= 6, Freq= 0, CH_0, rank 1
5227 01:14:59.450206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5228 01:14:59.450706 ==
5229 01:14:59.451135
5230 01:14:59.451539
5231 01:14:59.451932 TX Vref Scan disable
5232 01:14:59.453559 == TX Byte 0 ==
5233 01:14:59.456776 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5234 01:14:59.463417 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5235 01:14:59.463904 == TX Byte 1 ==
5236 01:14:59.466833 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5237 01:14:59.473350 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5238 01:14:59.473895 ==
5239 01:14:59.476306 Dram Type= 6, Freq= 0, CH_0, rank 1
5240 01:14:59.480354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5241 01:14:59.480786 ==
5242 01:14:59.481218
5243 01:14:59.481621
5244 01:14:59.483101 TX Vref Scan disable
5245 01:14:59.483532 == TX Byte 0 ==
5246 01:14:59.490077 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5247 01:14:59.493286 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5248 01:14:59.493717 == TX Byte 1 ==
5249 01:14:59.499726 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5250 01:14:59.503297 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5251 01:14:59.503819
5252 01:14:59.504267 [DATLAT]
5253 01:14:59.506584 Freq=933, CH0 RK1
5254 01:14:59.507112
5255 01:14:59.507551 DATLAT Default: 0xb
5256 01:14:59.509603 0, 0xFFFF, sum = 0
5257 01:14:59.510065 1, 0xFFFF, sum = 0
5258 01:14:59.513210 2, 0xFFFF, sum = 0
5259 01:14:59.516279 3, 0xFFFF, sum = 0
5260 01:14:59.516713 4, 0xFFFF, sum = 0
5261 01:14:59.519621 5, 0xFFFF, sum = 0
5262 01:14:59.520070 6, 0xFFFF, sum = 0
5263 01:14:59.523080 7, 0xFFFF, sum = 0
5264 01:14:59.523611 8, 0xFFFF, sum = 0
5265 01:14:59.526632 9, 0xFFFF, sum = 0
5266 01:14:59.527160 10, 0x0, sum = 1
5267 01:14:59.529304 11, 0x0, sum = 2
5268 01:14:59.529739 12, 0x0, sum = 3
5269 01:14:59.532935 13, 0x0, sum = 4
5270 01:14:59.533369 best_step = 11
5271 01:14:59.533801
5272 01:14:59.534276 ==
5273 01:14:59.535917 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 01:14:59.539333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5275 01:14:59.539762 ==
5276 01:14:59.542434 RX Vref Scan: 0
5277 01:14:59.542861
5278 01:14:59.545914 RX Vref 0 -> 0, step: 1
5279 01:14:59.546380
5280 01:14:59.546809 RX Delay -69 -> 252, step: 4
5281 01:14:59.553779 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5282 01:14:59.557030 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5283 01:14:59.560830 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5284 01:14:59.563860 iDelay=203, Bit 3, Center 90 (-1 ~ 182) 184
5285 01:14:59.567192 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5286 01:14:59.573575 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5287 01:14:59.577168 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5288 01:14:59.580380 iDelay=203, Bit 7, Center 106 (11 ~ 202) 192
5289 01:14:59.583590 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5290 01:14:59.586736 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5291 01:14:59.593069 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5292 01:14:59.596796 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5293 01:14:59.600220 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5294 01:14:59.603238 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5295 01:14:59.606372 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5296 01:14:59.613291 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5297 01:14:59.613812 ==
5298 01:14:59.616287 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 01:14:59.619642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5300 01:14:59.620169 ==
5301 01:14:59.620615 DQS Delay:
5302 01:14:59.622999 DQS0 = 0, DQS1 = 0
5303 01:14:59.623523 DQM Delay:
5304 01:14:59.626722 DQM0 = 97, DQM1 = 86
5305 01:14:59.627244 DQ Delay:
5306 01:14:59.629753 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5307 01:14:59.633151 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =106
5308 01:14:59.636204 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5309 01:14:59.639601 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5310 01:14:59.640028
5311 01:14:59.640456
5312 01:14:59.646209 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5313 01:14:59.649361 CH0 RK1: MR19=505, MR18=2929
5314 01:14:59.656071 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5315 01:14:59.659370 [RxdqsGatingPostProcess] freq 933
5316 01:14:59.665901 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5317 01:14:59.668992 Pre-setting of DQS Precalculation
5318 01:14:59.672360 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5319 01:14:59.672656 ==
5320 01:14:59.675427 Dram Type= 6, Freq= 0, CH_1, rank 0
5321 01:14:59.678822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5322 01:14:59.681993 ==
5323 01:14:59.685595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5324 01:14:59.691999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5325 01:14:59.695243 [CA 0] Center 37 (7~68) winsize 62
5326 01:14:59.698480 [CA 1] Center 37 (6~68) winsize 63
5327 01:14:59.702236 [CA 2] Center 35 (5~65) winsize 61
5328 01:14:59.705486 [CA 3] Center 34 (4~65) winsize 62
5329 01:14:59.708398 [CA 4] Center 33 (2~64) winsize 63
5330 01:14:59.712102 [CA 5] Center 33 (3~64) winsize 62
5331 01:14:59.712187
5332 01:14:59.715003 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5333 01:14:59.715083
5334 01:14:59.718755 [CATrainingPosCal] consider 1 rank data
5335 01:14:59.722304 u2DelayCellTimex100 = 270/100 ps
5336 01:14:59.725202 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5337 01:14:59.728650 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5338 01:14:59.731703 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5339 01:14:59.738532 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5340 01:14:59.741449 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5341 01:14:59.744787 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5342 01:14:59.744869
5343 01:14:59.748094 CA PerBit enable=1, Macro0, CA PI delay=33
5344 01:14:59.748175
5345 01:14:59.751502 [CBTSetCACLKResult] CA Dly = 33
5346 01:14:59.751582 CS Dly: 5 (0~36)
5347 01:14:59.751646 ==
5348 01:14:59.754763 Dram Type= 6, Freq= 0, CH_1, rank 1
5349 01:14:59.761390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5350 01:14:59.761472 ==
5351 01:14:59.764607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5352 01:14:59.771154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5353 01:14:59.774587 [CA 0] Center 37 (6~68) winsize 63
5354 01:14:59.777906 [CA 1] Center 37 (6~68) winsize 63
5355 01:14:59.781091 [CA 2] Center 34 (4~65) winsize 62
5356 01:14:59.784723 [CA 3] Center 34 (4~64) winsize 61
5357 01:14:59.788258 [CA 4] Center 33 (3~64) winsize 62
5358 01:14:59.791090 [CA 5] Center 33 (3~63) winsize 61
5359 01:14:59.791170
5360 01:14:59.794338 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5361 01:14:59.794419
5362 01:14:59.797749 [CATrainingPosCal] consider 2 rank data
5363 01:14:59.801312 u2DelayCellTimex100 = 270/100 ps
5364 01:14:59.804315 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5365 01:14:59.807716 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5366 01:14:59.814386 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5367 01:14:59.817621 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5368 01:14:59.820815 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5369 01:14:59.824537 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5370 01:14:59.824617
5371 01:14:59.827320 CA PerBit enable=1, Macro0, CA PI delay=33
5372 01:14:59.827401
5373 01:14:59.831073 [CBTSetCACLKResult] CA Dly = 33
5374 01:14:59.831153 CS Dly: 5 (0~37)
5375 01:14:59.833948
5376 01:14:59.837632 ----->DramcWriteLeveling(PI) begin...
5377 01:14:59.837715 ==
5378 01:14:59.840726 Dram Type= 6, Freq= 0, CH_1, rank 0
5379 01:14:59.844117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5380 01:14:59.844198 ==
5381 01:14:59.847180 Write leveling (Byte 0): 24 => 24
5382 01:14:59.850550 Write leveling (Byte 1): 24 => 24
5383 01:14:59.853919 DramcWriteLeveling(PI) end<-----
5384 01:14:59.853999
5385 01:14:59.854102 ==
5386 01:14:59.857355 Dram Type= 6, Freq= 0, CH_1, rank 0
5387 01:14:59.860495 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5388 01:14:59.860575 ==
5389 01:14:59.863906 [Gating] SW mode calibration
5390 01:14:59.870802 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5391 01:14:59.877139 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5392 01:14:59.880265 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 01:14:59.883702 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 01:14:59.890242 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 01:14:59.893697 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 01:14:59.897005 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (0 0)
5397 01:14:59.903429 0 10 20 | B1->B0 | 3131 2424 | 0 0 | (0 0) (0 0)
5398 01:14:59.906852 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5399 01:14:59.910190 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 01:14:59.917048 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 01:14:59.920103 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 01:14:59.923605 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 01:14:59.929880 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 01:14:59.933505 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5405 01:14:59.937027 0 11 20 | B1->B0 | 2a2a 4545 | 0 1 | (0 0) (0 0)
5406 01:14:59.943050 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5407 01:14:59.946456 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 01:14:59.949838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 01:14:59.956591 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 01:14:59.959663 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 01:14:59.963350 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 01:14:59.969576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5413 01:14:59.972996 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5414 01:14:59.976381 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 01:14:59.982852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 01:14:59.986041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 01:14:59.989608 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 01:14:59.995996 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 01:14:59.999666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 01:15:00.002600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 01:15:00.009167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 01:15:00.012611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 01:15:00.015898 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 01:15:00.022370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 01:15:00.025617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 01:15:00.029003 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 01:15:00.035589 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 01:15:00.038982 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5429 01:15:00.042559 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5430 01:15:00.045675 Total UI for P1: 0, mck2ui 16
5431 01:15:00.049091 best dqsien dly found for B0: ( 0, 14, 16)
5432 01:15:00.052669 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5433 01:15:00.055493 Total UI for P1: 0, mck2ui 16
5434 01:15:00.058887 best dqsien dly found for B1: ( 0, 14, 18)
5435 01:15:00.065362 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5436 01:15:00.068723 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5437 01:15:00.068805
5438 01:15:00.072094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5439 01:15:00.075597 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5440 01:15:00.078584 [Gating] SW calibration Done
5441 01:15:00.078665 ==
5442 01:15:00.081976 Dram Type= 6, Freq= 0, CH_1, rank 0
5443 01:15:00.085280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5444 01:15:00.085362 ==
5445 01:15:00.088610 RX Vref Scan: 0
5446 01:15:00.088690
5447 01:15:00.088754 RX Vref 0 -> 0, step: 1
5448 01:15:00.088814
5449 01:15:00.091962 RX Delay -80 -> 252, step: 8
5450 01:15:00.095089 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5451 01:15:00.101656 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5452 01:15:00.105027 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5453 01:15:00.108813 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5454 01:15:00.111580 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5455 01:15:00.115233 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5456 01:15:00.118551 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5457 01:15:00.124903 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5458 01:15:00.128487 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5459 01:15:00.131630 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5460 01:15:00.134936 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5461 01:15:00.137991 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5462 01:15:00.144697 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5463 01:15:00.147991 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5464 01:15:00.151243 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5465 01:15:00.154917 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5466 01:15:00.154999 ==
5467 01:15:00.157853 Dram Type= 6, Freq= 0, CH_1, rank 0
5468 01:15:00.164551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5469 01:15:00.164634 ==
5470 01:15:00.164698 DQS Delay:
5471 01:15:00.164756 DQS0 = 0, DQS1 = 0
5472 01:15:00.167633 DQM Delay:
5473 01:15:00.167746 DQM0 = 94, DQM1 = 87
5474 01:15:00.170912 DQ Delay:
5475 01:15:00.174270 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5476 01:15:00.177487 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5477 01:15:00.180876 DQ8 =71, DQ9 =75, DQ10 =91, DQ11 =79
5478 01:15:00.184015 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5479 01:15:00.184096
5480 01:15:00.184160
5481 01:15:00.184219 ==
5482 01:15:00.187919 Dram Type= 6, Freq= 0, CH_1, rank 0
5483 01:15:00.190863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5484 01:15:00.190944 ==
5485 01:15:00.191008
5486 01:15:00.191067
5487 01:15:00.194430 TX Vref Scan disable
5488 01:15:00.194510 == TX Byte 0 ==
5489 01:15:00.200622 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5490 01:15:00.204093 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5491 01:15:00.204174 == TX Byte 1 ==
5492 01:15:00.210795 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5493 01:15:00.213983 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5494 01:15:00.214074 ==
5495 01:15:00.217304 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 01:15:00.220515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5497 01:15:00.220596 ==
5498 01:15:00.224129
5499 01:15:00.224211
5500 01:15:00.224275 TX Vref Scan disable
5501 01:15:00.227162 == TX Byte 0 ==
5502 01:15:00.230549 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5503 01:15:00.236920 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5504 01:15:00.237003 == TX Byte 1 ==
5505 01:15:00.240396 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5506 01:15:00.247049 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5507 01:15:00.247137
5508 01:15:00.247201 [DATLAT]
5509 01:15:00.247259 Freq=933, CH1 RK0
5510 01:15:00.247318
5511 01:15:00.250244 DATLAT Default: 0xd
5512 01:15:00.250326 0, 0xFFFF, sum = 0
5513 01:15:00.253633 1, 0xFFFF, sum = 0
5514 01:15:00.256955 2, 0xFFFF, sum = 0
5515 01:15:00.257038 3, 0xFFFF, sum = 0
5516 01:15:00.260501 4, 0xFFFF, sum = 0
5517 01:15:00.260583 5, 0xFFFF, sum = 0
5518 01:15:00.263362 6, 0xFFFF, sum = 0
5519 01:15:00.263445 7, 0xFFFF, sum = 0
5520 01:15:00.266811 8, 0xFFFF, sum = 0
5521 01:15:00.266894 9, 0xFFFF, sum = 0
5522 01:15:00.269946 10, 0x0, sum = 1
5523 01:15:00.270073 11, 0x0, sum = 2
5524 01:15:00.273505 12, 0x0, sum = 3
5525 01:15:00.273586 13, 0x0, sum = 4
5526 01:15:00.273650 best_step = 11
5527 01:15:00.276568
5528 01:15:00.276649 ==
5529 01:15:00.280106 Dram Type= 6, Freq= 0, CH_1, rank 0
5530 01:15:00.283551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 01:15:00.283632 ==
5532 01:15:00.283696 RX Vref Scan: 1
5533 01:15:00.283755
5534 01:15:00.286566 RX Vref 0 -> 0, step: 1
5535 01:15:00.286647
5536 01:15:00.289982 RX Delay -69 -> 252, step: 4
5537 01:15:00.290082
5538 01:15:00.293406 Set Vref, RX VrefLevel [Byte0]: 56
5539 01:15:00.296822 [Byte1]: 50
5540 01:15:00.300276
5541 01:15:00.300355 Final RX Vref Byte 0 = 56 to rank0
5542 01:15:00.303115 Final RX Vref Byte 1 = 50 to rank0
5543 01:15:00.306660 Final RX Vref Byte 0 = 56 to rank1
5544 01:15:00.309829 Final RX Vref Byte 1 = 50 to rank1==
5545 01:15:00.312997 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 01:15:00.319744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 01:15:00.319825 ==
5548 01:15:00.319889 DQS Delay:
5549 01:15:00.319948 DQS0 = 0, DQS1 = 0
5550 01:15:00.323149 DQM Delay:
5551 01:15:00.323229 DQM0 = 94, DQM1 = 87
5552 01:15:00.326333 DQ Delay:
5553 01:15:00.329618 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =92
5554 01:15:00.332701 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =92
5555 01:15:00.336081 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5556 01:15:00.339250 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5557 01:15:00.339331
5558 01:15:00.339395
5559 01:15:00.345918 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d2d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5560 01:15:00.349100 CH1 RK0: MR19=505, MR18=2D2D
5561 01:15:00.356017 CH1_RK0: MR19=0x505, MR18=0x2D2D, DQSOSC=407, MR23=63, INC=65, DEC=43
5562 01:15:00.356100
5563 01:15:00.359570 ----->DramcWriteLeveling(PI) begin...
5564 01:15:00.359653 ==
5565 01:15:00.362638 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 01:15:00.365833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5567 01:15:00.365940 ==
5568 01:15:00.369397 Write leveling (Byte 0): 26 => 26
5569 01:15:00.372412 Write leveling (Byte 1): 22 => 22
5570 01:15:00.376028 DramcWriteLeveling(PI) end<-----
5571 01:15:00.376110
5572 01:15:00.376173 ==
5573 01:15:00.379468 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 01:15:00.382496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5575 01:15:00.382578 ==
5576 01:15:00.385688 [Gating] SW mode calibration
5577 01:15:00.392596 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 01:15:00.399092 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5579 01:15:00.402191 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 01:15:00.408815 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 01:15:00.412094 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 01:15:00.415586 0 10 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5583 01:15:00.421915 0 10 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5584 01:15:00.425489 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5585 01:15:00.428732 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 01:15:00.435517 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 01:15:00.438711 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 01:15:00.441765 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 01:15:00.448452 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 01:15:00.451763 0 11 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5591 01:15:00.455129 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5592 01:15:00.462167 0 11 20 | B1->B0 | 3332 4646 | 1 0 | (0 0) (0 0)
5593 01:15:00.464995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 01:15:00.468349 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 01:15:00.475098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 01:15:00.478303 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 01:15:00.481469 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 01:15:00.488258 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 01:15:00.491671 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5600 01:15:00.494939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5601 01:15:00.501489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 01:15:00.504960 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 01:15:00.508485 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 01:15:00.511615 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 01:15:00.518115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 01:15:00.521984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 01:15:00.524665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 01:15:00.531583 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 01:15:00.534531 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 01:15:00.537967 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 01:15:00.544440 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 01:15:00.547789 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 01:15:00.551367 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 01:15:00.557583 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 01:15:00.560859 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5616 01:15:00.564534 Total UI for P1: 0, mck2ui 16
5617 01:15:00.567849 best dqsien dly found for B0: ( 0, 14, 14)
5618 01:15:00.570942 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 01:15:00.574292 Total UI for P1: 0, mck2ui 16
5620 01:15:00.577612 best dqsien dly found for B1: ( 0, 14, 16)
5621 01:15:00.581168 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5622 01:15:00.587515 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5623 01:15:00.587596
5624 01:15:00.590684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5625 01:15:00.593918 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5626 01:15:00.597418 [Gating] SW calibration Done
5627 01:15:00.597503 ==
5628 01:15:00.600547 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 01:15:00.603901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5630 01:15:00.603986 ==
5631 01:15:00.607259 RX Vref Scan: 0
5632 01:15:00.607340
5633 01:15:00.607403 RX Vref 0 -> 0, step: 1
5634 01:15:00.607461
5635 01:15:00.610710 RX Delay -80 -> 252, step: 8
5636 01:15:00.613751 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5637 01:15:00.617138 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5638 01:15:00.623864 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5639 01:15:00.627124 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5640 01:15:00.630579 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5641 01:15:00.633853 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5642 01:15:00.636780 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5643 01:15:00.640312 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5644 01:15:00.646902 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5645 01:15:00.650396 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5646 01:15:00.653625 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5647 01:15:00.657283 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5648 01:15:00.660082 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5649 01:15:00.666737 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5650 01:15:00.669995 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5651 01:15:00.673454 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5652 01:15:00.673535 ==
5653 01:15:00.676628 Dram Type= 6, Freq= 0, CH_1, rank 1
5654 01:15:00.679920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5655 01:15:00.680001 ==
5656 01:15:00.683086 DQS Delay:
5657 01:15:00.683167 DQS0 = 0, DQS1 = 0
5658 01:15:00.686381 DQM Delay:
5659 01:15:00.686461 DQM0 = 98, DQM1 = 90
5660 01:15:00.686525 DQ Delay:
5661 01:15:00.689654 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5662 01:15:00.693114 DQ4 =99, DQ5 =107, DQ6 =103, DQ7 =95
5663 01:15:00.696363 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5664 01:15:00.702910 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =99
5665 01:15:00.702993
5666 01:15:00.703056
5667 01:15:00.703114 ==
5668 01:15:00.706422 Dram Type= 6, Freq= 0, CH_1, rank 1
5669 01:15:00.709577 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5670 01:15:00.709657 ==
5671 01:15:00.709721
5672 01:15:00.709778
5673 01:15:00.713056 TX Vref Scan disable
5674 01:15:00.713135 == TX Byte 0 ==
5675 01:15:00.719449 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 01:15:00.722831 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 01:15:00.722911 == TX Byte 1 ==
5678 01:15:00.729651 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5679 01:15:00.732982 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5680 01:15:00.733063 ==
5681 01:15:00.736165 Dram Type= 6, Freq= 0, CH_1, rank 1
5682 01:15:00.739265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5683 01:15:00.739349 ==
5684 01:15:00.739413
5685 01:15:00.739471
5686 01:15:00.742632 TX Vref Scan disable
5687 01:15:00.745880 == TX Byte 0 ==
5688 01:15:00.749932 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 01:15:00.752597 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 01:15:00.755978 == TX Byte 1 ==
5691 01:15:00.759037 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5692 01:15:00.762404 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5693 01:15:00.765870
5694 01:15:00.765949 [DATLAT]
5695 01:15:00.766012 Freq=933, CH1 RK1
5696 01:15:00.766111
5697 01:15:00.768980 DATLAT Default: 0xb
5698 01:15:00.769059 0, 0xFFFF, sum = 0
5699 01:15:00.772384 1, 0xFFFF, sum = 0
5700 01:15:00.772465 2, 0xFFFF, sum = 0
5701 01:15:00.775627 3, 0xFFFF, sum = 0
5702 01:15:00.778932 4, 0xFFFF, sum = 0
5703 01:15:00.779014 5, 0xFFFF, sum = 0
5704 01:15:00.782148 6, 0xFFFF, sum = 0
5705 01:15:00.782229 7, 0xFFFF, sum = 0
5706 01:15:00.785444 8, 0xFFFF, sum = 0
5707 01:15:00.785526 9, 0xFFFF, sum = 0
5708 01:15:00.788669 10, 0x0, sum = 1
5709 01:15:00.788750 11, 0x0, sum = 2
5710 01:15:00.791969 12, 0x0, sum = 3
5711 01:15:00.792050 13, 0x0, sum = 4
5712 01:15:00.792115 best_step = 11
5713 01:15:00.792175
5714 01:15:00.795222 ==
5715 01:15:00.798650 Dram Type= 6, Freq= 0, CH_1, rank 1
5716 01:15:00.801842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5717 01:15:00.801923 ==
5718 01:15:00.801985 RX Vref Scan: 0
5719 01:15:00.802086
5720 01:15:00.805506 RX Vref 0 -> 0, step: 1
5721 01:15:00.805586
5722 01:15:00.808405 RX Delay -69 -> 252, step: 4
5723 01:15:00.811828 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5724 01:15:00.818489 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5725 01:15:00.821849 iDelay=203, Bit 2, Center 86 (-9 ~ 182) 192
5726 01:15:00.825444 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5727 01:15:00.828453 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5728 01:15:00.832000 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5729 01:15:00.838060 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5730 01:15:00.841376 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5731 01:15:00.845205 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5732 01:15:00.848198 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5733 01:15:00.851950 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5734 01:15:00.858281 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5735 01:15:00.861805 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5736 01:15:00.864637 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5737 01:15:00.868035 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5738 01:15:00.871188 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5739 01:15:00.871268 ==
5740 01:15:00.874549 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 01:15:00.881091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5742 01:15:00.881172 ==
5743 01:15:00.881235 DQS Delay:
5744 01:15:00.884530 DQS0 = 0, DQS1 = 0
5745 01:15:00.884610 DQM Delay:
5746 01:15:00.884673 DQM0 = 95, DQM1 = 87
5747 01:15:00.887774 DQ Delay:
5748 01:15:00.891380 DQ0 =96, DQ1 =92, DQ2 =86, DQ3 =92
5749 01:15:00.894360 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5750 01:15:00.897544 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5751 01:15:00.901158 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5752 01:15:00.901239
5753 01:15:00.901302
5754 01:15:00.907563 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5755 01:15:00.910806 CH1 RK1: MR19=505, MR18=2020
5756 01:15:00.917876 CH1_RK1: MR19=0x505, MR18=0x2020, DQSOSC=411, MR23=63, INC=64, DEC=42
5757 01:15:00.920906 [RxdqsGatingPostProcess] freq 933
5758 01:15:00.924439 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5759 01:15:00.927297 Pre-setting of DQS Precalculation
5760 01:15:00.934048 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5761 01:15:00.940873 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5762 01:15:00.947382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5763 01:15:00.947469
5764 01:15:00.947533
5765 01:15:00.950675 [Calibration Summary] 1866 Mbps
5766 01:15:00.953994 CH 0, Rank 0
5767 01:15:00.954114 SW Impedance : PASS
5768 01:15:00.957456 DUTY Scan : NO K
5769 01:15:00.960548 ZQ Calibration : PASS
5770 01:15:00.960629 Jitter Meter : NO K
5771 01:15:00.963990 CBT Training : PASS
5772 01:15:00.964071 Write leveling : PASS
5773 01:15:00.967224 RX DQS gating : PASS
5774 01:15:00.970401 RX DQ/DQS(RDDQC) : PASS
5775 01:15:00.970481 TX DQ/DQS : PASS
5776 01:15:00.973875 RX DATLAT : PASS
5777 01:15:00.977163 RX DQ/DQS(Engine): PASS
5778 01:15:00.977243 TX OE : NO K
5779 01:15:00.980289 All Pass.
5780 01:15:00.980369
5781 01:15:00.980432 CH 0, Rank 1
5782 01:15:00.983910 SW Impedance : PASS
5783 01:15:00.983991 DUTY Scan : NO K
5784 01:15:00.986865 ZQ Calibration : PASS
5785 01:15:00.990348 Jitter Meter : NO K
5786 01:15:00.990428 CBT Training : PASS
5787 01:15:00.993588 Write leveling : PASS
5788 01:15:00.997000 RX DQS gating : PASS
5789 01:15:00.997081 RX DQ/DQS(RDDQC) : PASS
5790 01:15:01.000214 TX DQ/DQS : PASS
5791 01:15:01.003658 RX DATLAT : PASS
5792 01:15:01.003738 RX DQ/DQS(Engine): PASS
5793 01:15:01.006637 TX OE : NO K
5794 01:15:01.006717 All Pass.
5795 01:15:01.006780
5796 01:15:01.010151 CH 1, Rank 0
5797 01:15:01.010231 SW Impedance : PASS
5798 01:15:01.013269 DUTY Scan : NO K
5799 01:15:01.016732 ZQ Calibration : PASS
5800 01:15:01.016816 Jitter Meter : NO K
5801 01:15:01.019807 CBT Training : PASS
5802 01:15:01.023319 Write leveling : PASS
5803 01:15:01.023400 RX DQS gating : PASS
5804 01:15:01.026495 RX DQ/DQS(RDDQC) : PASS
5805 01:15:01.029828 TX DQ/DQS : PASS
5806 01:15:01.029908 RX DATLAT : PASS
5807 01:15:01.032959 RX DQ/DQS(Engine): PASS
5808 01:15:01.033052 TX OE : NO K
5809 01:15:01.036421 All Pass.
5810 01:15:01.036501
5811 01:15:01.036565 CH 1, Rank 1
5812 01:15:01.039733 SW Impedance : PASS
5813 01:15:01.039883 DUTY Scan : NO K
5814 01:15:01.042995 ZQ Calibration : PASS
5815 01:15:01.046464 Jitter Meter : NO K
5816 01:15:01.046545 CBT Training : PASS
5817 01:15:01.049834 Write leveling : PASS
5818 01:15:01.053017 RX DQS gating : PASS
5819 01:15:01.053098 RX DQ/DQS(RDDQC) : PASS
5820 01:15:01.056088 TX DQ/DQS : PASS
5821 01:15:01.059739 RX DATLAT : PASS
5822 01:15:01.059820 RX DQ/DQS(Engine): PASS
5823 01:15:01.062701 TX OE : NO K
5824 01:15:01.062783 All Pass.
5825 01:15:01.062846
5826 01:15:01.065986 DramC Write-DBI off
5827 01:15:01.069230 PER_BANK_REFRESH: Hybrid Mode
5828 01:15:01.069310 TX_TRACKING: ON
5829 01:15:01.079073 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5830 01:15:01.082665 [FAST_K] Save calibration result to emmc
5831 01:15:01.085735 dramc_set_vcore_voltage set vcore to 650000
5832 01:15:01.089315 Read voltage for 400, 6
5833 01:15:01.089396 Vio18 = 0
5834 01:15:01.089460 Vcore = 650000
5835 01:15:01.092639 Vdram = 0
5836 01:15:01.092719 Vddq = 0
5837 01:15:01.092784 Vmddr = 0
5838 01:15:01.098954 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5839 01:15:01.102558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5840 01:15:01.105725 MEM_TYPE=3, freq_sel=20
5841 01:15:01.109332 sv_algorithm_assistance_LP4_800
5842 01:15:01.112163 ============ PULL DRAM RESETB DOWN ============
5843 01:15:01.118840 ========== PULL DRAM RESETB DOWN end =========
5844 01:15:01.122072 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5845 01:15:01.125775 ===================================
5846 01:15:01.128712 LPDDR4 DRAM CONFIGURATION
5847 01:15:01.132173 ===================================
5848 01:15:01.132256 EX_ROW_EN[0] = 0x0
5849 01:15:01.135219 EX_ROW_EN[1] = 0x0
5850 01:15:01.135300 LP4Y_EN = 0x0
5851 01:15:01.138574 WORK_FSP = 0x0
5852 01:15:01.138656 WL = 0x2
5853 01:15:01.141837 RL = 0x2
5854 01:15:01.141921 BL = 0x2
5855 01:15:01.145278 RPST = 0x0
5856 01:15:01.145360 RD_PRE = 0x0
5857 01:15:01.148605 WR_PRE = 0x1
5858 01:15:01.151830 WR_PST = 0x0
5859 01:15:01.151912 DBI_WR = 0x0
5860 01:15:01.155350 DBI_RD = 0x0
5861 01:15:01.155431 OTF = 0x1
5862 01:15:01.158756 ===================================
5863 01:15:01.161683 ===================================
5864 01:15:01.161766 ANA top config
5865 01:15:01.165031 ===================================
5866 01:15:01.168396 DLL_ASYNC_EN = 0
5867 01:15:01.171832 ALL_SLAVE_EN = 1
5868 01:15:01.174998 NEW_RANK_MODE = 1
5869 01:15:01.178542 DLL_IDLE_MODE = 1
5870 01:15:01.178625 LP45_APHY_COMB_EN = 1
5871 01:15:01.181828 TX_ODT_DIS = 1
5872 01:15:01.185091 NEW_8X_MODE = 1
5873 01:15:01.188177 ===================================
5874 01:15:01.191929 ===================================
5875 01:15:01.194862 data_rate = 800
5876 01:15:01.198302 CKR = 1
5877 01:15:01.201454 DQ_P2S_RATIO = 4
5878 01:15:01.204783 ===================================
5879 01:15:01.204865 CA_P2S_RATIO = 4
5880 01:15:01.207896 DQ_CA_OPEN = 0
5881 01:15:01.211292 DQ_SEMI_OPEN = 1
5882 01:15:01.214430 CA_SEMI_OPEN = 1
5883 01:15:01.217827 CA_FULL_RATE = 0
5884 01:15:01.221250 DQ_CKDIV4_EN = 0
5885 01:15:01.221332 CA_CKDIV4_EN = 1
5886 01:15:01.224993 CA_PREDIV_EN = 0
5887 01:15:01.227685 PH8_DLY = 0
5888 01:15:01.231252 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5889 01:15:01.234228 DQ_AAMCK_DIV = 0
5890 01:15:01.237461 CA_AAMCK_DIV = 0
5891 01:15:01.237543 CA_ADMCK_DIV = 4
5892 01:15:01.241021 DQ_TRACK_CA_EN = 0
5893 01:15:01.244445 CA_PICK = 800
5894 01:15:01.247673 CA_MCKIO = 400
5895 01:15:01.250855 MCKIO_SEMI = 400
5896 01:15:01.254197 PLL_FREQ = 3016
5897 01:15:01.257485 DQ_UI_PI_RATIO = 32
5898 01:15:01.261026 CA_UI_PI_RATIO = 32
5899 01:15:01.264018 ===================================
5900 01:15:01.267681 ===================================
5901 01:15:01.267763 memory_type:LPDDR4
5902 01:15:01.270686 GP_NUM : 10
5903 01:15:01.273963 SRAM_EN : 1
5904 01:15:01.274104 MD32_EN : 0
5905 01:15:01.277195 ===================================
5906 01:15:01.280664 [ANA_INIT] >>>>>>>>>>>>>>
5907 01:15:01.283916 <<<<<< [CONFIGURE PHASE]: ANA_TX
5908 01:15:01.287057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5909 01:15:01.290662 ===================================
5910 01:15:01.293784 data_rate = 800,PCW = 0X7400
5911 01:15:01.296846 ===================================
5912 01:15:01.300100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5913 01:15:01.303644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5914 01:15:01.316772 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5915 01:15:01.320143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5916 01:15:01.323340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5917 01:15:01.326455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5918 01:15:01.329815 [ANA_INIT] flow start
5919 01:15:01.333106 [ANA_INIT] PLL >>>>>>>>
5920 01:15:01.333211 [ANA_INIT] PLL <<<<<<<<
5921 01:15:01.336300 [ANA_INIT] MIDPI >>>>>>>>
5922 01:15:01.339936 [ANA_INIT] MIDPI <<<<<<<<
5923 01:15:01.340039 [ANA_INIT] DLL >>>>>>>>
5924 01:15:01.343089 [ANA_INIT] flow end
5925 01:15:01.346277 ============ LP4 DIFF to SE enter ============
5926 01:15:01.349796 ============ LP4 DIFF to SE exit ============
5927 01:15:01.352891 [ANA_INIT] <<<<<<<<<<<<<
5928 01:15:01.356290 [Flow] Enable top DCM control >>>>>
5929 01:15:01.359459 [Flow] Enable top DCM control <<<<<
5930 01:15:01.363007 Enable DLL master slave shuffle
5931 01:15:01.369694 ==============================================================
5932 01:15:01.369778 Gating Mode config
5933 01:15:01.375994 ==============================================================
5934 01:15:01.376077 Config description:
5935 01:15:01.385956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5936 01:15:01.392590 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5937 01:15:01.399306 SELPH_MODE 0: By rank 1: By Phase
5938 01:15:01.405945 ==============================================================
5939 01:15:01.406057 GAT_TRACK_EN = 0
5940 01:15:01.409281 RX_GATING_MODE = 2
5941 01:15:01.412656 RX_GATING_TRACK_MODE = 2
5942 01:15:01.416029 SELPH_MODE = 1
5943 01:15:01.419156 PICG_EARLY_EN = 1
5944 01:15:01.422855 VALID_LAT_VALUE = 1
5945 01:15:01.429215 ==============================================================
5946 01:15:01.432256 Enter into Gating configuration >>>>
5947 01:15:01.435766 Exit from Gating configuration <<<<
5948 01:15:01.439003 Enter into DVFS_PRE_config >>>>>
5949 01:15:01.448714 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5950 01:15:01.452318 Exit from DVFS_PRE_config <<<<<
5951 01:15:01.455662 Enter into PICG configuration >>>>
5952 01:15:01.458842 Exit from PICG configuration <<<<
5953 01:15:01.461919 [RX_INPUT] configuration >>>>>
5954 01:15:01.465194 [RX_INPUT] configuration <<<<<
5955 01:15:01.468570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5956 01:15:01.475441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5957 01:15:01.481602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5958 01:15:01.485157 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5959 01:15:01.491823 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5960 01:15:01.498154 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5961 01:15:01.501604 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5962 01:15:01.507936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5963 01:15:01.511421 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5964 01:15:01.514531 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5965 01:15:01.517927 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5966 01:15:01.524532 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5967 01:15:01.527722 ===================================
5968 01:15:01.531116 LPDDR4 DRAM CONFIGURATION
5969 01:15:01.534358 ===================================
5970 01:15:01.534434 EX_ROW_EN[0] = 0x0
5971 01:15:01.538264 EX_ROW_EN[1] = 0x0
5972 01:15:01.538336 LP4Y_EN = 0x0
5973 01:15:01.541019 WORK_FSP = 0x0
5974 01:15:01.541117 WL = 0x2
5975 01:15:01.544321 RL = 0x2
5976 01:15:01.544420 BL = 0x2
5977 01:15:01.547567 RPST = 0x0
5978 01:15:01.547665 RD_PRE = 0x0
5979 01:15:01.550684 WR_PRE = 0x1
5980 01:15:01.550778 WR_PST = 0x0
5981 01:15:01.554324 DBI_WR = 0x0
5982 01:15:01.554396 DBI_RD = 0x0
5983 01:15:01.557417 OTF = 0x1
5984 01:15:01.560824 ===================================
5985 01:15:01.564373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5986 01:15:01.567721 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5987 01:15:01.574505 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5988 01:15:01.577541 ===================================
5989 01:15:01.577619 LPDDR4 DRAM CONFIGURATION
5990 01:15:01.580735 ===================================
5991 01:15:01.584204 EX_ROW_EN[0] = 0x10
5992 01:15:01.587302 EX_ROW_EN[1] = 0x0
5993 01:15:01.587392 LP4Y_EN = 0x0
5994 01:15:01.590580 WORK_FSP = 0x0
5995 01:15:01.590673 WL = 0x2
5996 01:15:01.593953 RL = 0x2
5997 01:15:01.594051 BL = 0x2
5998 01:15:01.596972 RPST = 0x0
5999 01:15:01.597067 RD_PRE = 0x0
6000 01:15:01.600567 WR_PRE = 0x1
6001 01:15:01.600661 WR_PST = 0x0
6002 01:15:01.603677 DBI_WR = 0x0
6003 01:15:01.603753 DBI_RD = 0x0
6004 01:15:01.607095 OTF = 0x1
6005 01:15:01.610441 ===================================
6006 01:15:01.616633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6007 01:15:01.620385 nWR fixed to 30
6008 01:15:01.624069 [ModeRegInit_LP4] CH0 RK0
6009 01:15:01.624149 [ModeRegInit_LP4] CH0 RK1
6010 01:15:01.627003 [ModeRegInit_LP4] CH1 RK0
6011 01:15:01.630187 [ModeRegInit_LP4] CH1 RK1
6012 01:15:01.630267 match AC timing 18
6013 01:15:01.636876 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6014 01:15:01.640228 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6015 01:15:01.643525 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6016 01:15:01.649905 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6017 01:15:01.653493 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6018 01:15:01.653574 ==
6019 01:15:01.656744 Dram Type= 6, Freq= 0, CH_0, rank 0
6020 01:15:01.660157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6021 01:15:01.660238 ==
6022 01:15:01.666687 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6023 01:15:01.673193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6024 01:15:01.676269 [CA 0] Center 36 (8~64) winsize 57
6025 01:15:01.679542 [CA 1] Center 36 (8~64) winsize 57
6026 01:15:01.682820 [CA 2] Center 36 (8~64) winsize 57
6027 01:15:01.686201 [CA 3] Center 36 (8~64) winsize 57
6028 01:15:01.689909 [CA 4] Center 36 (8~64) winsize 57
6029 01:15:01.692609 [CA 5] Center 36 (8~64) winsize 57
6030 01:15:01.692714
6031 01:15:01.696386 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6032 01:15:01.696468
6033 01:15:01.699395 [CATrainingPosCal] consider 1 rank data
6034 01:15:01.702888 u2DelayCellTimex100 = 270/100 ps
6035 01:15:01.706201 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 01:15:01.709279 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 01:15:01.712754 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 01:15:01.715960 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 01:15:01.719183 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 01:15:01.722704 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 01:15:01.722775
6042 01:15:01.728976 CA PerBit enable=1, Macro0, CA PI delay=36
6043 01:15:01.729056
6044 01:15:01.729118 [CBTSetCACLKResult] CA Dly = 36
6045 01:15:01.732362 CS Dly: 1 (0~32)
6046 01:15:01.732441 ==
6047 01:15:01.735698 Dram Type= 6, Freq= 0, CH_0, rank 1
6048 01:15:01.738849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6049 01:15:01.738929 ==
6050 01:15:01.745468 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6051 01:15:01.752240 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6052 01:15:01.755344 [CA 0] Center 36 (8~64) winsize 57
6053 01:15:01.758916 [CA 1] Center 36 (8~64) winsize 57
6054 01:15:01.762017 [CA 2] Center 36 (8~64) winsize 57
6055 01:15:01.765233 [CA 3] Center 36 (8~64) winsize 57
6056 01:15:01.765309 [CA 4] Center 36 (8~64) winsize 57
6057 01:15:01.768483 [CA 5] Center 36 (8~64) winsize 57
6058 01:15:01.768561
6059 01:15:01.775741 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6060 01:15:01.775823
6061 01:15:01.778752 [CATrainingPosCal] consider 2 rank data
6062 01:15:01.781924 u2DelayCellTimex100 = 270/100 ps
6063 01:15:01.785028 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 01:15:01.788367 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 01:15:01.791733 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 01:15:01.795235 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 01:15:01.798621 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 01:15:01.801559 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 01:15:01.801641
6070 01:15:01.804902 CA PerBit enable=1, Macro0, CA PI delay=36
6071 01:15:01.804984
6072 01:15:01.808201 [CBTSetCACLKResult] CA Dly = 36
6073 01:15:01.811377 CS Dly: 1 (0~32)
6074 01:15:01.811458
6075 01:15:01.815026 ----->DramcWriteLeveling(PI) begin...
6076 01:15:01.815109 ==
6077 01:15:01.817823 Dram Type= 6, Freq= 0, CH_0, rank 0
6078 01:15:01.821316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6079 01:15:01.821399 ==
6080 01:15:01.824741 Write leveling (Byte 0): 32 => 0
6081 01:15:01.827963 Write leveling (Byte 1): 32 => 0
6082 01:15:01.831263 DramcWriteLeveling(PI) end<-----
6083 01:15:01.831345
6084 01:15:01.831427 ==
6085 01:15:01.834675 Dram Type= 6, Freq= 0, CH_0, rank 0
6086 01:15:01.837920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6087 01:15:01.838004 ==
6088 01:15:01.841048 [Gating] SW mode calibration
6089 01:15:01.848006 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6090 01:15:01.854731 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6091 01:15:01.857671 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6092 01:15:01.864499 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6093 01:15:01.867471 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6094 01:15:01.871045 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6095 01:15:01.877593 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6096 01:15:01.880755 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6097 01:15:01.884211 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6098 01:15:01.890862 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6099 01:15:01.894078 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6100 01:15:01.897467 Total UI for P1: 0, mck2ui 16
6101 01:15:01.900825 best dqsien dly found for B0: ( 0, 10, 16)
6102 01:15:01.904004 Total UI for P1: 0, mck2ui 16
6103 01:15:01.907429 best dqsien dly found for B1: ( 0, 10, 16)
6104 01:15:01.910439 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6105 01:15:01.914001 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6106 01:15:01.914099
6107 01:15:01.917230 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6108 01:15:01.920431 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6109 01:15:01.923928 [Gating] SW calibration Done
6110 01:15:01.924010 ==
6111 01:15:01.927180 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 01:15:01.930591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 01:15:01.933631 ==
6114 01:15:01.933712 RX Vref Scan: 0
6115 01:15:01.933795
6116 01:15:01.936871 RX Vref 0 -> 0, step: 1
6117 01:15:01.936952
6118 01:15:01.940065 RX Delay -410 -> 252, step: 16
6119 01:15:01.943475 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6120 01:15:01.946562 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6121 01:15:01.953186 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6122 01:15:01.956698 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6123 01:15:01.960277 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6124 01:15:01.963435 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6125 01:15:01.966536 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6126 01:15:01.973511 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6127 01:15:01.976584 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6128 01:15:01.979910 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6129 01:15:01.986357 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6130 01:15:01.989979 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6131 01:15:01.992917 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6132 01:15:01.996500 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6133 01:15:02.002905 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6134 01:15:02.006548 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6135 01:15:02.006630 ==
6136 01:15:02.009679 Dram Type= 6, Freq= 0, CH_0, rank 0
6137 01:15:02.013243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6138 01:15:02.013325 ==
6139 01:15:02.016265 DQS Delay:
6140 01:15:02.016347 DQS0 = 51, DQS1 = 59
6141 01:15:02.019392 DQM Delay:
6142 01:15:02.019474 DQM0 = 12, DQM1 = 14
6143 01:15:02.019556 DQ Delay:
6144 01:15:02.022542 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6145 01:15:02.025888 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6146 01:15:02.029376 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6147 01:15:02.032572 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6148 01:15:02.032654
6149 01:15:02.032736
6150 01:15:02.032813 ==
6151 01:15:02.036041 Dram Type= 6, Freq= 0, CH_0, rank 0
6152 01:15:02.042596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6153 01:15:02.042680 ==
6154 01:15:02.042762
6155 01:15:02.042840
6156 01:15:02.042915 TX Vref Scan disable
6157 01:15:02.045773 == TX Byte 0 ==
6158 01:15:02.049060 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6159 01:15:02.052458 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6160 01:15:02.055580 == TX Byte 1 ==
6161 01:15:02.058902 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6162 01:15:02.062145 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6163 01:15:02.065552 ==
6164 01:15:02.068723 Dram Type= 6, Freq= 0, CH_0, rank 0
6165 01:15:02.072171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6166 01:15:02.072254 ==
6167 01:15:02.072336
6168 01:15:02.072413
6169 01:15:02.075592 TX Vref Scan disable
6170 01:15:02.075690 == TX Byte 0 ==
6171 01:15:02.079165 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6172 01:15:02.085507 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6173 01:15:02.085590 == TX Byte 1 ==
6174 01:15:02.088592 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6175 01:15:02.095056 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6176 01:15:02.095138
6177 01:15:02.095220 [DATLAT]
6178 01:15:02.095297 Freq=400, CH0 RK0
6179 01:15:02.098283
6180 01:15:02.098388 DATLAT Default: 0xf
6181 01:15:02.101998 0, 0xFFFF, sum = 0
6182 01:15:02.102105 1, 0xFFFF, sum = 0
6183 01:15:02.104945 2, 0xFFFF, sum = 0
6184 01:15:02.105052 3, 0xFFFF, sum = 0
6185 01:15:02.108311 4, 0xFFFF, sum = 0
6186 01:15:02.108394 5, 0xFFFF, sum = 0
6187 01:15:02.111515 6, 0xFFFF, sum = 0
6188 01:15:02.111598 7, 0xFFFF, sum = 0
6189 01:15:02.115012 8, 0xFFFF, sum = 0
6190 01:15:02.115096 9, 0xFFFF, sum = 0
6191 01:15:02.118036 10, 0xFFFF, sum = 0
6192 01:15:02.118160 11, 0xFFFF, sum = 0
6193 01:15:02.121442 12, 0x0, sum = 1
6194 01:15:02.121525 13, 0x0, sum = 2
6195 01:15:02.124791 14, 0x0, sum = 3
6196 01:15:02.124873 15, 0x0, sum = 4
6197 01:15:02.128007 best_step = 13
6198 01:15:02.128089
6199 01:15:02.128176 ==
6200 01:15:02.131860 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 01:15:02.134793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6202 01:15:02.134870 ==
6203 01:15:02.138111 RX Vref Scan: 1
6204 01:15:02.138180
6205 01:15:02.138240 RX Vref 0 -> 0, step: 1
6206 01:15:02.138297
6207 01:15:02.141166 RX Delay -359 -> 252, step: 8
6208 01:15:02.141272
6209 01:15:02.144622 Set Vref, RX VrefLevel [Byte0]: 53
6210 01:15:02.147770 [Byte1]: 46
6211 01:15:02.152626
6212 01:15:02.152708 Final RX Vref Byte 0 = 53 to rank0
6213 01:15:02.155912 Final RX Vref Byte 1 = 46 to rank0
6214 01:15:02.159217 Final RX Vref Byte 0 = 53 to rank1
6215 01:15:02.162777 Final RX Vref Byte 1 = 46 to rank1==
6216 01:15:02.165976 Dram Type= 6, Freq= 0, CH_0, rank 0
6217 01:15:02.172833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6218 01:15:02.172915 ==
6219 01:15:02.172998 DQS Delay:
6220 01:15:02.175896 DQS0 = 56, DQS1 = 68
6221 01:15:02.175978 DQM Delay:
6222 01:15:02.176064 DQM0 = 13, DQM1 = 17
6223 01:15:02.179338 DQ Delay:
6224 01:15:02.182445 DQ0 =8, DQ1 =12, DQ2 =12, DQ3 =8
6225 01:15:02.185889 DQ4 =20, DQ5 =0, DQ6 =20, DQ7 =24
6226 01:15:02.185971 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6227 01:15:02.188968 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6228 01:15:02.192276
6229 01:15:02.192368
6230 01:15:02.199118 [DQSOSCAuto] RK0, (LSB)MR18= 0x9494, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
6231 01:15:02.202281 CH0 RK0: MR19=C0C, MR18=9494
6232 01:15:02.209061 CH0_RK0: MR19=0xC0C, MR18=0x9494, DQSOSC=391, MR23=63, INC=386, DEC=257
6233 01:15:02.209143 ==
6234 01:15:02.212071 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 01:15:02.215339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6236 01:15:02.215421 ==
6237 01:15:02.218681 [Gating] SW mode calibration
6238 01:15:02.225363 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6239 01:15:02.232217 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6240 01:15:02.235570 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6241 01:15:02.239014 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6242 01:15:02.245185 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6243 01:15:02.248460 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6244 01:15:02.252130 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6245 01:15:02.258562 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6246 01:15:02.261847 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6247 01:15:02.264917 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6248 01:15:02.271467 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6249 01:15:02.271542 Total UI for P1: 0, mck2ui 16
6250 01:15:02.278229 best dqsien dly found for B0: ( 0, 10, 16)
6251 01:15:02.278303 Total UI for P1: 0, mck2ui 16
6252 01:15:02.284755 best dqsien dly found for B1: ( 0, 10, 24)
6253 01:15:02.288219 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6254 01:15:02.291437 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6255 01:15:02.291509
6256 01:15:02.294856 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6257 01:15:02.298144 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6258 01:15:02.301616 [Gating] SW calibration Done
6259 01:15:02.301689 ==
6260 01:15:02.304461 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 01:15:02.307993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6262 01:15:02.308064 ==
6263 01:15:02.311297 RX Vref Scan: 0
6264 01:15:02.311365
6265 01:15:02.311426 RX Vref 0 -> 0, step: 1
6266 01:15:02.314411
6267 01:15:02.314480 RX Delay -410 -> 252, step: 16
6268 01:15:02.321332 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6269 01:15:02.324326 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6270 01:15:02.327651 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6271 01:15:02.331308 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6272 01:15:02.337460 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6273 01:15:02.340895 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6274 01:15:02.344417 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6275 01:15:02.350732 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6276 01:15:02.353998 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6277 01:15:02.357471 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6278 01:15:02.360666 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6279 01:15:02.367508 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6280 01:15:02.370679 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6281 01:15:02.373994 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6282 01:15:02.377392 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6283 01:15:02.383847 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6284 01:15:02.383929 ==
6285 01:15:02.387196 Dram Type= 6, Freq= 0, CH_0, rank 1
6286 01:15:02.390304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6287 01:15:02.390410 ==
6288 01:15:02.390509 DQS Delay:
6289 01:15:02.393700 DQS0 = 43, DQS1 = 59
6290 01:15:02.393796 DQM Delay:
6291 01:15:02.397101 DQM0 = 6, DQM1 = 15
6292 01:15:02.397184 DQ Delay:
6293 01:15:02.400251 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6294 01:15:02.403513 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6295 01:15:02.407146 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6296 01:15:02.410373 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6297 01:15:02.410454
6298 01:15:02.410541
6299 01:15:02.410637 ==
6300 01:15:02.413524 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 01:15:02.416825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6302 01:15:02.416908 ==
6303 01:15:02.417005
6304 01:15:02.417101
6305 01:15:02.420189 TX Vref Scan disable
6306 01:15:02.423471 == TX Byte 0 ==
6307 01:15:02.426669 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6308 01:15:02.429783 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6309 01:15:02.433334 == TX Byte 1 ==
6310 01:15:02.436434 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6311 01:15:02.439895 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6312 01:15:02.439977 ==
6313 01:15:02.443107 Dram Type= 6, Freq= 0, CH_0, rank 1
6314 01:15:02.446317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6315 01:15:02.446399 ==
6316 01:15:02.449520
6317 01:15:02.449601
6318 01:15:02.449682 TX Vref Scan disable
6319 01:15:02.452861 == TX Byte 0 ==
6320 01:15:02.456170 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6321 01:15:02.459511 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6322 01:15:02.462789 == TX Byte 1 ==
6323 01:15:02.466378 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6324 01:15:02.469586 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6325 01:15:02.469668
6326 01:15:02.469750 [DATLAT]
6327 01:15:02.472871 Freq=400, CH0 RK1
6328 01:15:02.472977
6329 01:15:02.476114 DATLAT Default: 0xd
6330 01:15:02.476219 0, 0xFFFF, sum = 0
6331 01:15:02.479402 1, 0xFFFF, sum = 0
6332 01:15:02.479483 2, 0xFFFF, sum = 0
6333 01:15:02.482739 3, 0xFFFF, sum = 0
6334 01:15:02.482820 4, 0xFFFF, sum = 0
6335 01:15:02.486117 5, 0xFFFF, sum = 0
6336 01:15:02.486223 6, 0xFFFF, sum = 0
6337 01:15:02.489243 7, 0xFFFF, sum = 0
6338 01:15:02.489331 8, 0xFFFF, sum = 0
6339 01:15:02.492656 9, 0xFFFF, sum = 0
6340 01:15:02.492736 10, 0xFFFF, sum = 0
6341 01:15:02.495896 11, 0xFFFF, sum = 0
6342 01:15:02.495976 12, 0x0, sum = 1
6343 01:15:02.499379 13, 0x0, sum = 2
6344 01:15:02.499465 14, 0x0, sum = 3
6345 01:15:02.502625 15, 0x0, sum = 4
6346 01:15:02.502704 best_step = 13
6347 01:15:02.502766
6348 01:15:02.502823 ==
6349 01:15:02.505751 Dram Type= 6, Freq= 0, CH_0, rank 1
6350 01:15:02.512309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6351 01:15:02.512388 ==
6352 01:15:02.512450 RX Vref Scan: 0
6353 01:15:02.512508
6354 01:15:02.515724 RX Vref 0 -> 0, step: 1
6355 01:15:02.515790
6356 01:15:02.519007 RX Delay -359 -> 252, step: 8
6357 01:15:02.525595 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6358 01:15:02.528824 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6359 01:15:02.532213 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6360 01:15:02.535598 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6361 01:15:02.542231 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6362 01:15:02.545470 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6363 01:15:02.548620 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6364 01:15:02.552078 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6365 01:15:02.558516 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6366 01:15:02.561769 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6367 01:15:02.565226 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6368 01:15:02.569141 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6369 01:15:02.575114 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6370 01:15:02.578542 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6371 01:15:02.581781 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6372 01:15:02.588562 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6373 01:15:02.588644 ==
6374 01:15:02.592279 Dram Type= 6, Freq= 0, CH_0, rank 1
6375 01:15:02.595463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6376 01:15:02.595533 ==
6377 01:15:02.595594 DQS Delay:
6378 01:15:02.598441 DQS0 = 52, DQS1 = 60
6379 01:15:02.598508 DQM Delay:
6380 01:15:02.601722 DQM0 = 9, DQM1 = 10
6381 01:15:02.601825 DQ Delay:
6382 01:15:02.605003 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6383 01:15:02.608467 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6384 01:15:02.611950 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6385 01:15:02.615005 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6386 01:15:02.615084
6387 01:15:02.615146
6388 01:15:02.621778 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6389 01:15:02.624811 CH0 RK1: MR19=C0C, MR18=B6B6
6390 01:15:02.631446 CH0_RK1: MR19=0xC0C, MR18=0xB6B6, DQSOSC=387, MR23=63, INC=394, DEC=262
6391 01:15:02.634899 [RxdqsGatingPostProcess] freq 400
6392 01:15:02.638343 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6393 01:15:02.641630 Pre-setting of DQS Precalculation
6394 01:15:02.648171 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6395 01:15:02.648275 ==
6396 01:15:02.651390 Dram Type= 6, Freq= 0, CH_1, rank 0
6397 01:15:02.654875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6398 01:15:02.654988 ==
6399 01:15:02.661327 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6400 01:15:02.668091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6401 01:15:02.671274 [CA 0] Center 36 (8~64) winsize 57
6402 01:15:02.674699 [CA 1] Center 36 (8~64) winsize 57
6403 01:15:02.677939 [CA 2] Center 36 (8~64) winsize 57
6404 01:15:02.678018 [CA 3] Center 36 (8~64) winsize 57
6405 01:15:02.681106 [CA 4] Center 36 (8~64) winsize 57
6406 01:15:02.684399 [CA 5] Center 36 (8~64) winsize 57
6407 01:15:02.684478
6408 01:15:02.691133 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6409 01:15:02.691211
6410 01:15:02.694739 [CATrainingPosCal] consider 1 rank data
6411 01:15:02.697814 u2DelayCellTimex100 = 270/100 ps
6412 01:15:02.701116 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 01:15:02.704392 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 01:15:02.707716 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 01:15:02.711031 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 01:15:02.714336 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 01:15:02.717475 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 01:15:02.717548
6419 01:15:02.720987 CA PerBit enable=1, Macro0, CA PI delay=36
6420 01:15:02.721065
6421 01:15:02.724115 [CBTSetCACLKResult] CA Dly = 36
6422 01:15:02.727489 CS Dly: 1 (0~32)
6423 01:15:02.727567 ==
6424 01:15:02.731048 Dram Type= 6, Freq= 0, CH_1, rank 1
6425 01:15:02.734264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6426 01:15:02.734343 ==
6427 01:15:02.740769 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6428 01:15:02.744207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6429 01:15:02.747783 [CA 0] Center 36 (8~64) winsize 57
6430 01:15:02.751225 [CA 1] Center 36 (8~64) winsize 57
6431 01:15:02.754050 [CA 2] Center 36 (8~64) winsize 57
6432 01:15:02.757233 [CA 3] Center 36 (8~64) winsize 57
6433 01:15:02.760404 [CA 4] Center 36 (8~64) winsize 57
6434 01:15:02.763775 [CA 5] Center 36 (8~64) winsize 57
6435 01:15:02.763858
6436 01:15:02.767027 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6437 01:15:02.767117
6438 01:15:02.770499 [CATrainingPosCal] consider 2 rank data
6439 01:15:02.773836 u2DelayCellTimex100 = 270/100 ps
6440 01:15:02.776953 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 01:15:02.783737 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 01:15:02.787066 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 01:15:02.790360 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 01:15:02.793619 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 01:15:02.796783 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 01:15:02.796853
6447 01:15:02.800436 CA PerBit enable=1, Macro0, CA PI delay=36
6448 01:15:02.800507
6449 01:15:02.803525 [CBTSetCACLKResult] CA Dly = 36
6450 01:15:02.803598 CS Dly: 1 (0~32)
6451 01:15:02.806736
6452 01:15:02.810057 ----->DramcWriteLeveling(PI) begin...
6453 01:15:02.810154 ==
6454 01:15:02.813507 Dram Type= 6, Freq= 0, CH_1, rank 0
6455 01:15:02.816821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6456 01:15:02.816902 ==
6457 01:15:02.819920 Write leveling (Byte 0): 32 => 0
6458 01:15:02.823441 Write leveling (Byte 1): 32 => 0
6459 01:15:02.826561 DramcWriteLeveling(PI) end<-----
6460 01:15:02.826641
6461 01:15:02.826704 ==
6462 01:15:02.829822 Dram Type= 6, Freq= 0, CH_1, rank 0
6463 01:15:02.833536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6464 01:15:02.833617 ==
6465 01:15:02.836637 [Gating] SW mode calibration
6466 01:15:02.843842 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 01:15:02.846763 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6468 01:15:02.853566 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 01:15:02.856581 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 01:15:02.859911 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 01:15:02.866953 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
6472 01:15:02.869984 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 01:15:02.873405 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 01:15:02.880269 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 01:15:02.883289 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6476 01:15:02.886385 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 01:15:02.889628 Total UI for P1: 0, mck2ui 16
6478 01:15:02.893030 best dqsien dly found for B0: ( 0, 10, 16)
6479 01:15:02.896190 Total UI for P1: 0, mck2ui 16
6480 01:15:02.899464 best dqsien dly found for B1: ( 0, 10, 16)
6481 01:15:02.902749 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6482 01:15:02.909285 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6483 01:15:02.909366
6484 01:15:02.912949 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6485 01:15:02.916420 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6486 01:15:02.919649 [Gating] SW calibration Done
6487 01:15:02.919730 ==
6488 01:15:02.922439 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 01:15:02.925748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 01:15:02.925828 ==
6491 01:15:02.929198 RX Vref Scan: 0
6492 01:15:02.929282
6493 01:15:02.929346 RX Vref 0 -> 0, step: 1
6494 01:15:02.929406
6495 01:15:02.932461 RX Delay -410 -> 252, step: 16
6496 01:15:02.939297 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6497 01:15:02.942339 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6498 01:15:02.946111 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6499 01:15:02.949253 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6500 01:15:02.955840 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6501 01:15:02.959582 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6502 01:15:02.962117 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6503 01:15:02.965592 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6504 01:15:02.972308 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6505 01:15:02.975430 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 01:15:02.978888 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 01:15:02.982012 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 01:15:02.988951 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 01:15:02.991959 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 01:15:02.995481 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 01:15:03.001815 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6512 01:15:03.001915 ==
6513 01:15:03.005229 Dram Type= 6, Freq= 0, CH_1, rank 0
6514 01:15:03.008543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6515 01:15:03.008620 ==
6516 01:15:03.008684 DQS Delay:
6517 01:15:03.011777 DQS0 = 43, DQS1 = 59
6518 01:15:03.011846 DQM Delay:
6519 01:15:03.015161 DQM0 = 7, DQM1 = 16
6520 01:15:03.015230 DQ Delay:
6521 01:15:03.018553 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6522 01:15:03.021671 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6523 01:15:03.025154 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6524 01:15:03.028334 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6525 01:15:03.028403
6526 01:15:03.028467
6527 01:15:03.028525 ==
6528 01:15:03.031594 Dram Type= 6, Freq= 0, CH_1, rank 0
6529 01:15:03.035551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6530 01:15:03.035621 ==
6531 01:15:03.035681
6532 01:15:03.035736
6533 01:15:03.038117 TX Vref Scan disable
6534 01:15:03.038209 == TX Byte 0 ==
6535 01:15:03.044980 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6536 01:15:03.048323 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6537 01:15:03.048420 == TX Byte 1 ==
6538 01:15:03.054696 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6539 01:15:03.058033 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6540 01:15:03.058136 ==
6541 01:15:03.061298 Dram Type= 6, Freq= 0, CH_1, rank 0
6542 01:15:03.064595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6543 01:15:03.064688 ==
6544 01:15:03.064776
6545 01:15:03.068017
6546 01:15:03.068107 TX Vref Scan disable
6547 01:15:03.071354 == TX Byte 0 ==
6548 01:15:03.074539 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6549 01:15:03.077952 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6550 01:15:03.080979 == TX Byte 1 ==
6551 01:15:03.084341 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6552 01:15:03.087727 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6553 01:15:03.087802
6554 01:15:03.091234 [DATLAT]
6555 01:15:03.091300 Freq=400, CH1 RK0
6556 01:15:03.091359
6557 01:15:03.094241 DATLAT Default: 0xf
6558 01:15:03.094331 0, 0xFFFF, sum = 0
6559 01:15:03.097802 1, 0xFFFF, sum = 0
6560 01:15:03.097872 2, 0xFFFF, sum = 0
6561 01:15:03.101103 3, 0xFFFF, sum = 0
6562 01:15:03.101169 4, 0xFFFF, sum = 0
6563 01:15:03.104204 5, 0xFFFF, sum = 0
6564 01:15:03.104272 6, 0xFFFF, sum = 0
6565 01:15:03.107656 7, 0xFFFF, sum = 0
6566 01:15:03.107727 8, 0xFFFF, sum = 0
6567 01:15:03.110753 9, 0xFFFF, sum = 0
6568 01:15:03.110824 10, 0xFFFF, sum = 0
6569 01:15:03.113966 11, 0xFFFF, sum = 0
6570 01:15:03.114060 12, 0x0, sum = 1
6571 01:15:03.117320 13, 0x0, sum = 2
6572 01:15:03.117412 14, 0x0, sum = 3
6573 01:15:03.120672 15, 0x0, sum = 4
6574 01:15:03.120739 best_step = 13
6575 01:15:03.120796
6576 01:15:03.120857 ==
6577 01:15:03.124186 Dram Type= 6, Freq= 0, CH_1, rank 0
6578 01:15:03.130566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6579 01:15:03.130635 ==
6580 01:15:03.130698 RX Vref Scan: 1
6581 01:15:03.130755
6582 01:15:03.133878 RX Vref 0 -> 0, step: 1
6583 01:15:03.133953
6584 01:15:03.137552 RX Delay -359 -> 252, step: 8
6585 01:15:03.137641
6586 01:15:03.140693 Set Vref, RX VrefLevel [Byte0]: 56
6587 01:15:03.143730 [Byte1]: 50
6588 01:15:03.147149
6589 01:15:03.147221 Final RX Vref Byte 0 = 56 to rank0
6590 01:15:03.150352 Final RX Vref Byte 1 = 50 to rank0
6591 01:15:03.153525 Final RX Vref Byte 0 = 56 to rank1
6592 01:15:03.156911 Final RX Vref Byte 1 = 50 to rank1==
6593 01:15:03.160164 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 01:15:03.166879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6595 01:15:03.166986 ==
6596 01:15:03.167055 DQS Delay:
6597 01:15:03.170056 DQS0 = 48, DQS1 = 64
6598 01:15:03.170134 DQM Delay:
6599 01:15:03.170193 DQM0 = 7, DQM1 = 16
6600 01:15:03.173478 DQ Delay:
6601 01:15:03.177052 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6602 01:15:03.177126 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6603 01:15:03.179969 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6604 01:15:03.183307 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6605 01:15:03.183380
6606 01:15:03.186726
6607 01:15:03.193117 [DQSOSCAuto] RK0, (LSB)MR18= 0xcccc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6608 01:15:03.196479 CH1 RK0: MR19=C0C, MR18=CCCC
6609 01:15:03.203043 CH1_RK0: MR19=0xC0C, MR18=0xCCCC, DQSOSC=384, MR23=63, INC=400, DEC=267
6610 01:15:03.203122 ==
6611 01:15:03.206308 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 01:15:03.209528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6613 01:15:03.209622 ==
6614 01:15:03.212822 [Gating] SW mode calibration
6615 01:15:03.219535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6616 01:15:03.226101 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6617 01:15:03.229372 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6618 01:15:03.233117 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6619 01:15:03.239299 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6620 01:15:03.242814 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6621 01:15:03.245964 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6622 01:15:03.252474 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6623 01:15:03.256009 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6624 01:15:03.259563 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6625 01:15:03.265879 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6626 01:15:03.265959 Total UI for P1: 0, mck2ui 16
6627 01:15:03.269357 best dqsien dly found for B0: ( 0, 10, 16)
6628 01:15:03.272773 Total UI for P1: 0, mck2ui 16
6629 01:15:03.275734 best dqsien dly found for B1: ( 0, 10, 16)
6630 01:15:03.282820 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6631 01:15:03.285643 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6632 01:15:03.285735
6633 01:15:03.289223 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6634 01:15:03.292175 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6635 01:15:03.295547 [Gating] SW calibration Done
6636 01:15:03.295618 ==
6637 01:15:03.298837 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 01:15:03.302263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6639 01:15:03.302335 ==
6640 01:15:03.305516 RX Vref Scan: 0
6641 01:15:03.305593
6642 01:15:03.305652 RX Vref 0 -> 0, step: 1
6643 01:15:03.305708
6644 01:15:03.308707 RX Delay -410 -> 252, step: 16
6645 01:15:03.315424 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6646 01:15:03.318656 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6647 01:15:03.321913 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6648 01:15:03.325207 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6649 01:15:03.332003 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6650 01:15:03.334986 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6651 01:15:03.338383 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6652 01:15:03.341504 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6653 01:15:03.348143 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6654 01:15:03.351527 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6655 01:15:03.354685 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6656 01:15:03.361292 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6657 01:15:03.364547 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6658 01:15:03.367889 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6659 01:15:03.371505 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6660 01:15:03.377924 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6661 01:15:03.378021 ==
6662 01:15:03.381277 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 01:15:03.384370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6664 01:15:03.384465 ==
6665 01:15:03.384551 DQS Delay:
6666 01:15:03.387847 DQS0 = 43, DQS1 = 59
6667 01:15:03.387921 DQM Delay:
6668 01:15:03.390954 DQM0 = 10, DQM1 = 18
6669 01:15:03.391032 DQ Delay:
6670 01:15:03.394641 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6671 01:15:03.397822 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6672 01:15:03.400844 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6673 01:15:03.404367 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6674 01:15:03.404462
6675 01:15:03.404547
6676 01:15:03.404650 ==
6677 01:15:03.407615 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 01:15:03.410937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6679 01:15:03.411016 ==
6680 01:15:03.411076
6681 01:15:03.411131
6682 01:15:03.414223 TX Vref Scan disable
6683 01:15:03.417520 == TX Byte 0 ==
6684 01:15:03.420557 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6685 01:15:03.423825 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6686 01:15:03.427320 == TX Byte 1 ==
6687 01:15:03.430942 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6688 01:15:03.434026 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6689 01:15:03.434126 ==
6690 01:15:03.437464 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 01:15:03.440571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6692 01:15:03.440665 ==
6693 01:15:03.444225
6694 01:15:03.444309
6695 01:15:03.444370 TX Vref Scan disable
6696 01:15:03.447339 == TX Byte 0 ==
6697 01:15:03.450463 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6698 01:15:03.453721 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6699 01:15:03.456875 == TX Byte 1 ==
6700 01:15:03.460515 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6701 01:15:03.463683 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6702 01:15:03.463762
6703 01:15:03.463824 [DATLAT]
6704 01:15:03.467069 Freq=400, CH1 RK1
6705 01:15:03.467148
6706 01:15:03.470223 DATLAT Default: 0xd
6707 01:15:03.470302 0, 0xFFFF, sum = 0
6708 01:15:03.473284 1, 0xFFFF, sum = 0
6709 01:15:03.473364 2, 0xFFFF, sum = 0
6710 01:15:03.476802 3, 0xFFFF, sum = 0
6711 01:15:03.476884 4, 0xFFFF, sum = 0
6712 01:15:03.479918 5, 0xFFFF, sum = 0
6713 01:15:03.479998 6, 0xFFFF, sum = 0
6714 01:15:03.483360 7, 0xFFFF, sum = 0
6715 01:15:03.483440 8, 0xFFFF, sum = 0
6716 01:15:03.486559 9, 0xFFFF, sum = 0
6717 01:15:03.486639 10, 0xFFFF, sum = 0
6718 01:15:03.489907 11, 0xFFFF, sum = 0
6719 01:15:03.489988 12, 0x0, sum = 1
6720 01:15:03.493065 13, 0x0, sum = 2
6721 01:15:03.493145 14, 0x0, sum = 3
6722 01:15:03.496531 15, 0x0, sum = 4
6723 01:15:03.496631 best_step = 13
6724 01:15:03.496718
6725 01:15:03.496811 ==
6726 01:15:03.499857 Dram Type= 6, Freq= 0, CH_1, rank 1
6727 01:15:03.506906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6728 01:15:03.506984 ==
6729 01:15:03.507080 RX Vref Scan: 0
6730 01:15:03.507169
6731 01:15:03.509733 RX Vref 0 -> 0, step: 1
6732 01:15:03.509801
6733 01:15:03.513144 RX Delay -359 -> 252, step: 8
6734 01:15:03.519554 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6735 01:15:03.523065 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6736 01:15:03.526260 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6737 01:15:03.529388 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6738 01:15:03.536304 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6739 01:15:03.539515 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6740 01:15:03.542561 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6741 01:15:03.546337 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6742 01:15:03.552488 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6743 01:15:03.555685 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6744 01:15:03.560012 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6745 01:15:03.565693 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6746 01:15:03.568983 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6747 01:15:03.572352 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6748 01:15:03.575629 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6749 01:15:03.582177 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6750 01:15:03.582252 ==
6751 01:15:03.585690 Dram Type= 6, Freq= 0, CH_1, rank 1
6752 01:15:03.589218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6753 01:15:03.589314 ==
6754 01:15:03.589410 DQS Delay:
6755 01:15:03.592218 DQS0 = 48, DQS1 = 64
6756 01:15:03.592292 DQM Delay:
6757 01:15:03.595617 DQM0 = 9, DQM1 = 15
6758 01:15:03.595685 DQ Delay:
6759 01:15:03.598885 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6760 01:15:03.602020 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6761 01:15:03.605677 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6762 01:15:03.609076 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6763 01:15:03.609155
6764 01:15:03.609217
6765 01:15:03.615251 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6766 01:15:03.618688 CH1 RK1: MR19=C0C, MR18=A8A8
6767 01:15:03.625060 CH1_RK1: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6768 01:15:03.628557 [RxdqsGatingPostProcess] freq 400
6769 01:15:03.634970 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6770 01:15:03.638517 Pre-setting of DQS Precalculation
6771 01:15:03.641828 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6772 01:15:03.648551 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6773 01:15:03.655466 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6774 01:15:03.655564
6775 01:15:03.658337
6776 01:15:03.658407 [Calibration Summary] 800 Mbps
6777 01:15:03.661501 CH 0, Rank 0
6778 01:15:03.661600 SW Impedance : PASS
6779 01:15:03.665013 DUTY Scan : NO K
6780 01:15:03.668341 ZQ Calibration : PASS
6781 01:15:03.668411 Jitter Meter : NO K
6782 01:15:03.671433 CBT Training : PASS
6783 01:15:03.674774 Write leveling : PASS
6784 01:15:03.674842 RX DQS gating : PASS
6785 01:15:03.678222 RX DQ/DQS(RDDQC) : PASS
6786 01:15:03.681499 TX DQ/DQS : PASS
6787 01:15:03.681602 RX DATLAT : PASS
6788 01:15:03.685040 RX DQ/DQS(Engine): PASS
6789 01:15:03.688456 TX OE : NO K
6790 01:15:03.688529 All Pass.
6791 01:15:03.688619
6792 01:15:03.688705 CH 0, Rank 1
6793 01:15:03.691226 SW Impedance : PASS
6794 01:15:03.694675 DUTY Scan : NO K
6795 01:15:03.694745 ZQ Calibration : PASS
6796 01:15:03.697967 Jitter Meter : NO K
6797 01:15:03.698105 CBT Training : PASS
6798 01:15:03.701205 Write leveling : NO K
6799 01:15:03.704976 RX DQS gating : PASS
6800 01:15:03.705058 RX DQ/DQS(RDDQC) : PASS
6801 01:15:03.707959 TX DQ/DQS : PASS
6802 01:15:03.711538 RX DATLAT : PASS
6803 01:15:03.711631 RX DQ/DQS(Engine): PASS
6804 01:15:03.714722 TX OE : NO K
6805 01:15:03.714791 All Pass.
6806 01:15:03.714850
6807 01:15:03.718033 CH 1, Rank 0
6808 01:15:03.718127 SW Impedance : PASS
6809 01:15:03.721126 DUTY Scan : NO K
6810 01:15:03.724284 ZQ Calibration : PASS
6811 01:15:03.724354 Jitter Meter : NO K
6812 01:15:03.727542 CBT Training : PASS
6813 01:15:03.731016 Write leveling : PASS
6814 01:15:03.731085 RX DQS gating : PASS
6815 01:15:03.734251 RX DQ/DQS(RDDQC) : PASS
6816 01:15:03.737512 TX DQ/DQS : PASS
6817 01:15:03.737595 RX DATLAT : PASS
6818 01:15:03.740846 RX DQ/DQS(Engine): PASS
6819 01:15:03.744028 TX OE : NO K
6820 01:15:03.744100 All Pass.
6821 01:15:03.744163
6822 01:15:03.744230 CH 1, Rank 1
6823 01:15:03.747444 SW Impedance : PASS
6824 01:15:03.750895 DUTY Scan : NO K
6825 01:15:03.750992 ZQ Calibration : PASS
6826 01:15:03.754142 Jitter Meter : NO K
6827 01:15:03.757464 CBT Training : PASS
6828 01:15:03.757533 Write leveling : NO K
6829 01:15:03.760590 RX DQS gating : PASS
6830 01:15:03.760685 RX DQ/DQS(RDDQC) : PASS
6831 01:15:03.764079 TX DQ/DQS : PASS
6832 01:15:03.767457 RX DATLAT : PASS
6833 01:15:03.767526 RX DQ/DQS(Engine): PASS
6834 01:15:03.771081 TX OE : NO K
6835 01:15:03.771175 All Pass.
6836 01:15:03.771261
6837 01:15:03.773697 DramC Write-DBI off
6838 01:15:03.777123 PER_BANK_REFRESH: Hybrid Mode
6839 01:15:03.777196 TX_TRACKING: ON
6840 01:15:03.787109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6841 01:15:03.790574 [FAST_K] Save calibration result to emmc
6842 01:15:03.793470 dramc_set_vcore_voltage set vcore to 725000
6843 01:15:03.796702 Read voltage for 1600, 0
6844 01:15:03.796799 Vio18 = 0
6845 01:15:03.800282 Vcore = 725000
6846 01:15:03.800353 Vdram = 0
6847 01:15:03.800412 Vddq = 0
6848 01:15:03.800468 Vmddr = 0
6849 01:15:03.806849 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6850 01:15:03.813435 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6851 01:15:03.813510 MEM_TYPE=3, freq_sel=13
6852 01:15:03.817047 sv_algorithm_assistance_LP4_3733
6853 01:15:03.820148 ============ PULL DRAM RESETB DOWN ============
6854 01:15:03.826910 ========== PULL DRAM RESETB DOWN end =========
6855 01:15:03.829950 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6856 01:15:03.833487 ===================================
6857 01:15:03.836649 LPDDR4 DRAM CONFIGURATION
6858 01:15:03.840267 ===================================
6859 01:15:03.840336 EX_ROW_EN[0] = 0x0
6860 01:15:03.843241 EX_ROW_EN[1] = 0x0
6861 01:15:03.843305 LP4Y_EN = 0x0
6862 01:15:03.846638 WORK_FSP = 0x1
6863 01:15:03.850004 WL = 0x5
6864 01:15:03.850119 RL = 0x5
6865 01:15:03.853283 BL = 0x2
6866 01:15:03.853365 RPST = 0x0
6867 01:15:03.856369 RD_PRE = 0x0
6868 01:15:03.856464 WR_PRE = 0x1
6869 01:15:03.859980 WR_PST = 0x1
6870 01:15:03.860074 DBI_WR = 0x0
6871 01:15:03.862932 DBI_RD = 0x0
6872 01:15:03.862999 OTF = 0x1
6873 01:15:03.866140 ===================================
6874 01:15:03.869343 ===================================
6875 01:15:03.872735 ANA top config
6876 01:15:03.876045 ===================================
6877 01:15:03.876144 DLL_ASYNC_EN = 0
6878 01:15:03.879439 ALL_SLAVE_EN = 0
6879 01:15:03.882720 NEW_RANK_MODE = 1
6880 01:15:03.885877 DLL_IDLE_MODE = 1
6881 01:15:03.889377 LP45_APHY_COMB_EN = 1
6882 01:15:03.889447 TX_ODT_DIS = 0
6883 01:15:03.892538 NEW_8X_MODE = 1
6884 01:15:03.895757 ===================================
6885 01:15:03.898998 ===================================
6886 01:15:03.902493 data_rate = 3200
6887 01:15:03.906002 CKR = 1
6888 01:15:03.909005 DQ_P2S_RATIO = 8
6889 01:15:03.912298 ===================================
6890 01:15:03.915709 CA_P2S_RATIO = 8
6891 01:15:03.915807 DQ_CA_OPEN = 0
6892 01:15:03.919037 DQ_SEMI_OPEN = 0
6893 01:15:03.922189 CA_SEMI_OPEN = 0
6894 01:15:03.925484 CA_FULL_RATE = 0
6895 01:15:03.928934 DQ_CKDIV4_EN = 0
6896 01:15:03.932188 CA_CKDIV4_EN = 0
6897 01:15:03.932294 CA_PREDIV_EN = 0
6898 01:15:03.935681 PH8_DLY = 12
6899 01:15:03.938677 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6900 01:15:03.942468 DQ_AAMCK_DIV = 4
6901 01:15:03.945582 CA_AAMCK_DIV = 4
6902 01:15:03.948874 CA_ADMCK_DIV = 4
6903 01:15:03.948974 DQ_TRACK_CA_EN = 0
6904 01:15:03.952029 CA_PICK = 1600
6905 01:15:03.955276 CA_MCKIO = 1600
6906 01:15:03.958817 MCKIO_SEMI = 0
6907 01:15:03.962244 PLL_FREQ = 3068
6908 01:15:03.965100 DQ_UI_PI_RATIO = 32
6909 01:15:03.968408 CA_UI_PI_RATIO = 0
6910 01:15:03.971591 ===================================
6911 01:15:03.975075 ===================================
6912 01:15:03.975207 memory_type:LPDDR4
6913 01:15:03.978353 GP_NUM : 10
6914 01:15:03.981558 SRAM_EN : 1
6915 01:15:03.981683 MD32_EN : 0
6916 01:15:03.984902 ===================================
6917 01:15:03.988307 [ANA_INIT] >>>>>>>>>>>>>>
6918 01:15:03.991652 <<<<<< [CONFIGURE PHASE]: ANA_TX
6919 01:15:03.995110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6920 01:15:03.998107 ===================================
6921 01:15:04.001422 data_rate = 3200,PCW = 0X7600
6922 01:15:04.004727 ===================================
6923 01:15:04.008356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6924 01:15:04.011364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6925 01:15:04.018178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6926 01:15:04.024670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6927 01:15:04.028009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6928 01:15:04.031173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6929 01:15:04.031246 [ANA_INIT] flow start
6930 01:15:04.034309 [ANA_INIT] PLL >>>>>>>>
6931 01:15:04.038093 [ANA_INIT] PLL <<<<<<<<
6932 01:15:04.038177 [ANA_INIT] MIDPI >>>>>>>>
6933 01:15:04.041021 [ANA_INIT] MIDPI <<<<<<<<
6934 01:15:04.044269 [ANA_INIT] DLL >>>>>>>>
6935 01:15:04.044373 [ANA_INIT] DLL <<<<<<<<
6936 01:15:04.047921 [ANA_INIT] flow end
6937 01:15:04.051097 ============ LP4 DIFF to SE enter ============
6938 01:15:04.054687 ============ LP4 DIFF to SE exit ============
6939 01:15:04.057664 [ANA_INIT] <<<<<<<<<<<<<
6940 01:15:04.061086 [Flow] Enable top DCM control >>>>>
6941 01:15:04.064372 [Flow] Enable top DCM control <<<<<
6942 01:15:04.067775 Enable DLL master slave shuffle
6943 01:15:04.073941 ==============================================================
6944 01:15:04.074074 Gating Mode config
6945 01:15:04.080807 ==============================================================
6946 01:15:04.084127 Config description:
6947 01:15:04.090559 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6948 01:15:04.097204 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6949 01:15:04.103661 SELPH_MODE 0: By rank 1: By Phase
6950 01:15:04.110286 ==============================================================
6951 01:15:04.114135 GAT_TRACK_EN = 1
6952 01:15:04.114207 RX_GATING_MODE = 2
6953 01:15:04.117005 RX_GATING_TRACK_MODE = 2
6954 01:15:04.120079 SELPH_MODE = 1
6955 01:15:04.123459 PICG_EARLY_EN = 1
6956 01:15:04.126942 VALID_LAT_VALUE = 1
6957 01:15:04.133574 ==============================================================
6958 01:15:04.136574 Enter into Gating configuration >>>>
6959 01:15:04.140040 Exit from Gating configuration <<<<
6960 01:15:04.143285 Enter into DVFS_PRE_config >>>>>
6961 01:15:04.153071 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6962 01:15:04.156407 Exit from DVFS_PRE_config <<<<<
6963 01:15:04.159966 Enter into PICG configuration >>>>
6964 01:15:04.163019 Exit from PICG configuration <<<<
6965 01:15:04.166346 [RX_INPUT] configuration >>>>>
6966 01:15:04.169771 [RX_INPUT] configuration <<<<<
6967 01:15:04.173012 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6968 01:15:04.179778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6969 01:15:04.185996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6970 01:15:04.192681 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6971 01:15:04.195986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6972 01:15:04.202560 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6973 01:15:04.209234 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6974 01:15:04.212444 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6975 01:15:04.215786 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6976 01:15:04.219224 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6977 01:15:04.222371 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6978 01:15:04.229048 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6979 01:15:04.232390 ===================================
6980 01:15:04.235629 LPDDR4 DRAM CONFIGURATION
6981 01:15:04.239141 ===================================
6982 01:15:04.239213 EX_ROW_EN[0] = 0x0
6983 01:15:04.242356 EX_ROW_EN[1] = 0x0
6984 01:15:04.242447 LP4Y_EN = 0x0
6985 01:15:04.245496 WORK_FSP = 0x1
6986 01:15:04.245599 WL = 0x5
6987 01:15:04.248890 RL = 0x5
6988 01:15:04.248989 BL = 0x2
6989 01:15:04.252090 RPST = 0x0
6990 01:15:04.252196 RD_PRE = 0x0
6991 01:15:04.255646 WR_PRE = 0x1
6992 01:15:04.255741 WR_PST = 0x1
6993 01:15:04.258744 DBI_WR = 0x0
6994 01:15:04.262320 DBI_RD = 0x0
6995 01:15:04.262401 OTF = 0x1
6996 01:15:04.265478 ===================================
6997 01:15:04.268581 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6998 01:15:04.271974 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6999 01:15:04.278442 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7000 01:15:04.281845 ===================================
7001 01:15:04.285212 LPDDR4 DRAM CONFIGURATION
7002 01:15:04.288680 ===================================
7003 01:15:04.288760 EX_ROW_EN[0] = 0x10
7004 01:15:04.291721 EX_ROW_EN[1] = 0x0
7005 01:15:04.291801 LP4Y_EN = 0x0
7006 01:15:04.295051 WORK_FSP = 0x1
7007 01:15:04.295131 WL = 0x5
7008 01:15:04.298416 RL = 0x5
7009 01:15:04.298519 BL = 0x2
7010 01:15:04.301683 RPST = 0x0
7011 01:15:04.301762 RD_PRE = 0x0
7012 01:15:04.305037 WR_PRE = 0x1
7013 01:15:04.305142 WR_PST = 0x1
7014 01:15:04.308351 DBI_WR = 0x0
7015 01:15:04.308431 DBI_RD = 0x0
7016 01:15:04.311824 OTF = 0x1
7017 01:15:04.314890 ===================================
7018 01:15:04.321785 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7019 01:15:04.321890 ==
7020 01:15:04.325271 Dram Type= 6, Freq= 0, CH_0, rank 0
7021 01:15:04.328412 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7022 01:15:04.328493 ==
7023 01:15:04.331316 [Duty_Offset_Calibration]
7024 01:15:04.331395 B0:0 B1:2 CA:1
7025 01:15:04.334603
7026 01:15:04.337950 [DutyScan_Calibration_Flow] k_type=0
7027 01:15:04.346047
7028 01:15:04.346168 ==CLK 0==
7029 01:15:04.349424 Final CLK duty delay cell = 0
7030 01:15:04.352537 [0] MAX Duty = 5156%(X100), DQS PI = 22
7031 01:15:04.355950 [0] MIN Duty = 4938%(X100), DQS PI = 54
7032 01:15:04.359179 [0] AVG Duty = 5047%(X100)
7033 01:15:04.359250
7034 01:15:04.362513 CH0 CLK Duty spec in!! Max-Min= 218%
7035 01:15:04.365975 [DutyScan_Calibration_Flow] ====Done====
7036 01:15:04.366096
7037 01:15:04.369266 [DutyScan_Calibration_Flow] k_type=1
7038 01:15:04.385945
7039 01:15:04.386079 ==DQS 0 ==
7040 01:15:04.389450 Final DQS duty delay cell = 0
7041 01:15:04.392678 [0] MAX Duty = 5125%(X100), DQS PI = 32
7042 01:15:04.396141 [0] MIN Duty = 5000%(X100), DQS PI = 8
7043 01:15:04.399429 [0] AVG Duty = 5062%(X100)
7044 01:15:04.399529
7045 01:15:04.399616 ==DQS 1 ==
7046 01:15:04.402584 Final DQS duty delay cell = 0
7047 01:15:04.405937 [0] MAX Duty = 5031%(X100), DQS PI = 2
7048 01:15:04.409325 [0] MIN Duty = 4876%(X100), DQS PI = 18
7049 01:15:04.409420 [0] AVG Duty = 4953%(X100)
7050 01:15:04.412592
7051 01:15:04.416352 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7052 01:15:04.416443
7053 01:15:04.419087 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7054 01:15:04.422488 [DutyScan_Calibration_Flow] ====Done====
7055 01:15:04.422556
7056 01:15:04.426119 [DutyScan_Calibration_Flow] k_type=3
7057 01:15:04.443178
7058 01:15:04.443249 ==DQM 0 ==
7059 01:15:04.446327 Final DQM duty delay cell = 0
7060 01:15:04.449586 [0] MAX Duty = 5187%(X100), DQS PI = 24
7061 01:15:04.452936 [0] MIN Duty = 4907%(X100), DQS PI = 42
7062 01:15:04.456293 [0] AVG Duty = 5047%(X100)
7063 01:15:04.456386
7064 01:15:04.456472 ==DQM 1 ==
7065 01:15:04.459540 Final DQM duty delay cell = 0
7066 01:15:04.462966 [0] MAX Duty = 5031%(X100), DQS PI = 4
7067 01:15:04.466339 [0] MIN Duty = 4782%(X100), DQS PI = 14
7068 01:15:04.469519 [0] AVG Duty = 4906%(X100)
7069 01:15:04.469610
7070 01:15:04.472944 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7071 01:15:04.473044
7072 01:15:04.476265 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7073 01:15:04.479452 [DutyScan_Calibration_Flow] ====Done====
7074 01:15:04.479519
7075 01:15:04.482726 [DutyScan_Calibration_Flow] k_type=2
7076 01:15:04.499448
7077 01:15:04.499531 ==DQ 0 ==
7078 01:15:04.502606 Final DQ duty delay cell = 0
7079 01:15:04.506072 [0] MAX Duty = 5218%(X100), DQS PI = 18
7080 01:15:04.509447 [0] MIN Duty = 4938%(X100), DQS PI = 56
7081 01:15:04.509540 [0] AVG Duty = 5078%(X100)
7082 01:15:04.512545
7083 01:15:04.512613 ==DQ 1 ==
7084 01:15:04.516034 Final DQ duty delay cell = -4
7085 01:15:04.519036 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7086 01:15:04.522582 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7087 01:15:04.525713 [-4] AVG Duty = 4953%(X100)
7088 01:15:04.525779
7089 01:15:04.528952 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7090 01:15:04.529029
7091 01:15:04.532238 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7092 01:15:04.535434 [DutyScan_Calibration_Flow] ====Done====
7093 01:15:04.535531 ==
7094 01:15:04.538709 Dram Type= 6, Freq= 0, CH_1, rank 0
7095 01:15:04.542163 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7096 01:15:04.542231 ==
7097 01:15:04.545596 [Duty_Offset_Calibration]
7098 01:15:04.545690 B0:0 B1:4 CA:-5
7099 01:15:04.548813
7100 01:15:04.551768 [DutyScan_Calibration_Flow] k_type=0
7101 01:15:04.560253
7102 01:15:04.560351 ==CLK 0==
7103 01:15:04.563211 Final CLK duty delay cell = 0
7104 01:15:04.566544 [0] MAX Duty = 5156%(X100), DQS PI = 20
7105 01:15:04.570051 [0] MIN Duty = 4875%(X100), DQS PI = 50
7106 01:15:04.573150 [0] AVG Duty = 5015%(X100)
7107 01:15:04.573242
7108 01:15:04.576459 CH1 CLK Duty spec in!! Max-Min= 281%
7109 01:15:04.580234 [DutyScan_Calibration_Flow] ====Done====
7110 01:15:04.580304
7111 01:15:04.583055 [DutyScan_Calibration_Flow] k_type=1
7112 01:15:04.599210
7113 01:15:04.599284 ==DQS 0 ==
7114 01:15:04.602389 Final DQS duty delay cell = 0
7115 01:15:04.605355 [0] MAX Duty = 5187%(X100), DQS PI = 20
7116 01:15:04.608727 [0] MIN Duty = 4876%(X100), DQS PI = 44
7117 01:15:04.612073 [0] AVG Duty = 5031%(X100)
7118 01:15:04.612172
7119 01:15:04.612259 ==DQS 1 ==
7120 01:15:04.615641 Final DQS duty delay cell = -4
7121 01:15:04.618717 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7122 01:15:04.622249 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7123 01:15:04.625419 [-4] AVG Duty = 4922%(X100)
7124 01:15:04.625486
7125 01:15:04.628533 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7126 01:15:04.628626
7127 01:15:04.632059 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7128 01:15:04.635315 [DutyScan_Calibration_Flow] ====Done====
7129 01:15:04.635414
7130 01:15:04.638453 [DutyScan_Calibration_Flow] k_type=3
7131 01:15:04.654684
7132 01:15:04.654760 ==DQM 0 ==
7133 01:15:04.657995 Final DQM duty delay cell = -4
7134 01:15:04.661354 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7135 01:15:04.664227 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7136 01:15:04.667598 [-4] AVG Duty = 4937%(X100)
7137 01:15:04.667666
7138 01:15:04.667726 ==DQM 1 ==
7139 01:15:04.670808 Final DQM duty delay cell = -4
7140 01:15:04.674094 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7141 01:15:04.677826 [-4] MIN Duty = 4875%(X100), DQS PI = 40
7142 01:15:04.680841 [-4] AVG Duty = 4984%(X100)
7143 01:15:04.680922
7144 01:15:04.684284 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7145 01:15:04.684365
7146 01:15:04.687392 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7147 01:15:04.690806 [DutyScan_Calibration_Flow] ====Done====
7148 01:15:04.690886
7149 01:15:04.693677 [DutyScan_Calibration_Flow] k_type=2
7150 01:15:04.712190
7151 01:15:04.712271 ==DQ 0 ==
7152 01:15:04.715573 Final DQ duty delay cell = 0
7153 01:15:04.718864 [0] MAX Duty = 5093%(X100), DQS PI = 20
7154 01:15:04.721966 [0] MIN Duty = 4938%(X100), DQS PI = 46
7155 01:15:04.722070 [0] AVG Duty = 5015%(X100)
7156 01:15:04.725430
7157 01:15:04.725510 ==DQ 1 ==
7158 01:15:04.728689 Final DQ duty delay cell = 0
7159 01:15:04.731948 [0] MAX Duty = 5031%(X100), DQS PI = 4
7160 01:15:04.735262 [0] MIN Duty = 4876%(X100), DQS PI = 28
7161 01:15:04.735342 [0] AVG Duty = 4953%(X100)
7162 01:15:04.735407
7163 01:15:04.742077 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7164 01:15:04.742171
7165 01:15:04.745339 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7166 01:15:04.748585 [DutyScan_Calibration_Flow] ====Done====
7167 01:15:04.751925 nWR fixed to 30
7168 01:15:04.752006 [ModeRegInit_LP4] CH0 RK0
7169 01:15:04.755027 [ModeRegInit_LP4] CH0 RK1
7170 01:15:04.758388 [ModeRegInit_LP4] CH1 RK0
7171 01:15:04.761584 [ModeRegInit_LP4] CH1 RK1
7172 01:15:04.761664 match AC timing 4
7173 01:15:04.768119 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7174 01:15:04.771460 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7175 01:15:04.775053 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7176 01:15:04.781687 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7177 01:15:04.784824 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7178 01:15:04.784933 [MiockJmeterHQA]
7179 01:15:04.785021
7180 01:15:04.788552 [DramcMiockJmeter] u1RxGatingPI = 0
7181 01:15:04.791497 0 : 4255, 4030
7182 01:15:04.791567 4 : 4252, 4027
7183 01:15:04.794697 8 : 4252, 4027
7184 01:15:04.794795 12 : 4252, 4027
7185 01:15:04.794891 16 : 4366, 4139
7186 01:15:04.797942 20 : 4363, 4137
7187 01:15:04.798055 24 : 4363, 4138
7188 01:15:04.801322 28 : 4253, 4027
7189 01:15:04.801417 32 : 4363, 4138
7190 01:15:04.804696 36 : 4257, 4029
7191 01:15:04.804780 40 : 4250, 4026
7192 01:15:04.808226 44 : 4252, 4027
7193 01:15:04.808324 48 : 4253, 4027
7194 01:15:04.808423 52 : 4252, 4027
7195 01:15:04.811291 56 : 4252, 4027
7196 01:15:04.811387 60 : 4250, 4026
7197 01:15:04.814538 64 : 4250, 4027
7198 01:15:04.814615 68 : 4363, 4140
7199 01:15:04.817645 72 : 4253, 4029
7200 01:15:04.817743 76 : 4252, 4029
7201 01:15:04.820997 80 : 4250, 4027
7202 01:15:04.821072 84 : 4360, 4138
7203 01:15:04.821150 88 : 4250, 4027
7204 01:15:04.824621 92 : 4252, 4029
7205 01:15:04.824692 96 : 4252, 4030
7206 01:15:04.827740 100 : 4250, 1398
7207 01:15:04.827838 104 : 4250, 0
7208 01:15:04.831239 108 : 4252, 0
7209 01:15:04.831336 112 : 4252, 0
7210 01:15:04.831433 116 : 4361, 0
7211 01:15:04.834634 120 : 4250, 0
7212 01:15:04.834709 124 : 4253, 0
7213 01:15:04.837683 128 : 4360, 0
7214 01:15:04.837781 132 : 4250, 0
7215 01:15:04.837878 136 : 4249, 0
7216 01:15:04.841371 140 : 4250, 0
7217 01:15:04.841444 144 : 4250, 0
7218 01:15:04.844142 148 : 4249, 0
7219 01:15:04.844216 152 : 4249, 0
7220 01:15:04.844307 156 : 4250, 0
7221 01:15:04.847440 160 : 4249, 0
7222 01:15:04.847544 164 : 4249, 0
7223 01:15:04.847641 168 : 4250, 0
7224 01:15:04.850675 172 : 4360, 0
7225 01:15:04.850779 176 : 4361, 0
7226 01:15:04.854259 180 : 4250, 0
7227 01:15:04.854334 184 : 4250, 0
7228 01:15:04.854415 188 : 4249, 0
7229 01:15:04.857507 192 : 4250, 0
7230 01:15:04.857580 196 : 4250, 0
7231 01:15:04.860767 200 : 4249, 0
7232 01:15:04.860867 204 : 4252, 0
7233 01:15:04.860965 208 : 4249, 0
7234 01:15:04.863929 212 : 4249, 0
7235 01:15:04.864026 216 : 4252, 0
7236 01:15:04.867134 220 : 4363, 1020
7237 01:15:04.867210 224 : 4253, 4012
7238 01:15:04.870459 228 : 4253, 4029
7239 01:15:04.870534 232 : 4250, 4027
7240 01:15:04.873739 236 : 4250, 4026
7241 01:15:04.873813 240 : 4361, 4138
7242 01:15:04.873912 244 : 4250, 4027
7243 01:15:04.877147 248 : 4360, 4138
7244 01:15:04.877245 252 : 4250, 4026
7245 01:15:04.880552 256 : 4250, 4026
7246 01:15:04.880650 260 : 4250, 4027
7247 01:15:04.883822 264 : 4249, 4027
7248 01:15:04.883919 268 : 4255, 4030
7249 01:15:04.887255 272 : 4361, 4137
7250 01:15:04.887338 276 : 4250, 4027
7251 01:15:04.890431 280 : 4250, 4027
7252 01:15:04.890528 284 : 4255, 4029
7253 01:15:04.893760 288 : 4250, 4026
7254 01:15:04.893859 292 : 4360, 4138
7255 01:15:04.897087 296 : 4250, 4027
7256 01:15:04.897173 300 : 4363, 4138
7257 01:15:04.897251 304 : 4252, 4029
7258 01:15:04.900471 308 : 4250, 4027
7259 01:15:04.900573 312 : 4249, 4027
7260 01:15:04.903666 316 : 4249, 4027
7261 01:15:04.903743 320 : 4250, 4027
7262 01:15:04.906847 324 : 4361, 4137
7263 01:15:04.906920 328 : 4250, 4027
7264 01:15:04.910411 332 : 4250, 4027
7265 01:15:04.910483 336 : 4250, 3414
7266 01:15:04.913583 340 : 4250, 1470
7267 01:15:04.913683
7268 01:15:04.913777 MIOCK jitter meter ch=0
7269 01:15:04.917144
7270 01:15:04.917216 1T = (340-100) = 240 dly cells
7271 01:15:04.923412 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7272 01:15:04.923490 ==
7273 01:15:04.926639 Dram Type= 6, Freq= 0, CH_0, rank 0
7274 01:15:04.930122 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7275 01:15:04.930195 ==
7276 01:15:04.936641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7277 01:15:04.940007 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7278 01:15:04.946719 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7279 01:15:04.950270 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7280 01:15:04.959495 [CA 0] Center 42 (12~73) winsize 62
7281 01:15:04.962842 [CA 1] Center 42 (12~73) winsize 62
7282 01:15:04.966048 [CA 2] Center 39 (9~69) winsize 61
7283 01:15:04.969285 [CA 3] Center 38 (9~68) winsize 60
7284 01:15:04.972657 [CA 4] Center 37 (7~67) winsize 61
7285 01:15:04.975958 [CA 5] Center 36 (6~66) winsize 61
7286 01:15:04.976030
7287 01:15:04.979481 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7288 01:15:04.979553
7289 01:15:04.985769 [CATrainingPosCal] consider 1 rank data
7290 01:15:04.985864 u2DelayCellTimex100 = 271/100 ps
7291 01:15:04.992545 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7292 01:15:04.995702 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7293 01:15:04.999039 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7294 01:15:05.002408 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7295 01:15:05.005950 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7296 01:15:05.009047 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7297 01:15:05.009126
7298 01:15:05.012441 CA PerBit enable=1, Macro0, CA PI delay=36
7299 01:15:05.012543
7300 01:15:05.015448 [CBTSetCACLKResult] CA Dly = 36
7301 01:15:05.018956 CS Dly: 10 (0~41)
7302 01:15:05.022212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7303 01:15:05.025508 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7304 01:15:05.025584 ==
7305 01:15:05.028995 Dram Type= 6, Freq= 0, CH_0, rank 1
7306 01:15:05.035499 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7307 01:15:05.035600 ==
7308 01:15:05.039081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7309 01:15:05.045383 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7310 01:15:05.048620 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7311 01:15:05.055181 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7312 01:15:05.062353 [CA 0] Center 42 (12~73) winsize 62
7313 01:15:05.065637 [CA 1] Center 42 (12~73) winsize 62
7314 01:15:05.068855 [CA 2] Center 38 (9~68) winsize 60
7315 01:15:05.072106 [CA 3] Center 37 (8~67) winsize 60
7316 01:15:05.075676 [CA 4] Center 36 (6~66) winsize 61
7317 01:15:05.078651 [CA 5] Center 36 (6~66) winsize 61
7318 01:15:05.078788
7319 01:15:05.082140 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7320 01:15:05.082239
7321 01:15:05.088571 [CATrainingPosCal] consider 2 rank data
7322 01:15:05.088668 u2DelayCellTimex100 = 271/100 ps
7323 01:15:05.095246 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7324 01:15:05.098398 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7325 01:15:05.101746 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7326 01:15:05.105107 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7327 01:15:05.108438 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7328 01:15:05.111646 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7329 01:15:05.111745
7330 01:15:05.115480 CA PerBit enable=1, Macro0, CA PI delay=36
7331 01:15:05.115576
7332 01:15:05.118299 [CBTSetCACLKResult] CA Dly = 36
7333 01:15:05.121799 CS Dly: 10 (0~42)
7334 01:15:05.124934 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7335 01:15:05.128466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7336 01:15:05.128563
7337 01:15:05.131654 ----->DramcWriteLeveling(PI) begin...
7338 01:15:05.131749 ==
7339 01:15:05.134977 Dram Type= 6, Freq= 0, CH_0, rank 0
7340 01:15:05.141600 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7341 01:15:05.141701 ==
7342 01:15:05.144758 Write leveling (Byte 0): 28 => 28
7343 01:15:05.148456 Write leveling (Byte 1): 28 => 28
7344 01:15:05.148556 DramcWriteLeveling(PI) end<-----
7345 01:15:05.148646
7346 01:15:05.151736 ==
7347 01:15:05.154937 Dram Type= 6, Freq= 0, CH_0, rank 0
7348 01:15:05.158173 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7349 01:15:05.158278 ==
7350 01:15:05.161450 [Gating] SW mode calibration
7351 01:15:05.168020 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7352 01:15:05.171400 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7353 01:15:05.178292 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7354 01:15:05.181351 0 12 4 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
7355 01:15:05.184601 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7356 01:15:05.191107 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7357 01:15:05.194621 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7358 01:15:05.197901 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7359 01:15:05.204329 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7360 01:15:05.207932 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7361 01:15:05.211064 0 13 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7362 01:15:05.217678 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
7363 01:15:05.221036 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7364 01:15:05.224409 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7365 01:15:05.230956 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7366 01:15:05.234145 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7367 01:15:05.237232 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7368 01:15:05.243796 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7369 01:15:05.247213 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7370 01:15:05.250412 0 14 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7371 01:15:05.257124 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7372 01:15:05.260377 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7373 01:15:05.263989 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7374 01:15:05.270331 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7375 01:15:05.273690 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7376 01:15:05.276950 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7377 01:15:05.283682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7378 01:15:05.287165 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7379 01:15:05.290398 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7380 01:15:05.296943 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7381 01:15:05.300102 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7382 01:15:05.303327 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7383 01:15:05.309879 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7384 01:15:05.313332 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7385 01:15:05.316555 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7386 01:15:05.323245 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7387 01:15:05.326451 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7388 01:15:05.329754 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7389 01:15:05.336300 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7390 01:15:05.339897 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7391 01:15:05.342989 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7392 01:15:05.349869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7393 01:15:05.352917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7394 01:15:05.356267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7395 01:15:05.362723 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7396 01:15:05.362802 Total UI for P1: 0, mck2ui 16
7397 01:15:05.369563 best dqsien dly found for B0: ( 1, 1, 2)
7398 01:15:05.373263 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 01:15:05.376354 Total UI for P1: 0, mck2ui 16
7400 01:15:05.379442 best dqsien dly found for B1: ( 1, 1, 6)
7401 01:15:05.382537 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7402 01:15:05.386001 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7403 01:15:05.386084
7404 01:15:05.389498 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7405 01:15:05.392634 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7406 01:15:05.395827 [Gating] SW calibration Done
7407 01:15:05.395915 ==
7408 01:15:05.399292 Dram Type= 6, Freq= 0, CH_0, rank 0
7409 01:15:05.402539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7410 01:15:05.402609 ==
7411 01:15:05.405796 RX Vref Scan: 0
7412 01:15:05.405898
7413 01:15:05.409281 RX Vref 0 -> 0, step: 1
7414 01:15:05.409351
7415 01:15:05.409410 RX Delay 0 -> 252, step: 8
7416 01:15:05.415602 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7417 01:15:05.418939 iDelay=192, Bit 1, Center 131 (72 ~ 191) 120
7418 01:15:05.422228 iDelay=192, Bit 2, Center 123 (64 ~ 183) 120
7419 01:15:05.425607 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7420 01:15:05.428790 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7421 01:15:05.435605 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7422 01:15:05.438694 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7423 01:15:05.441935 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7424 01:15:05.445419 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7425 01:15:05.448586 iDelay=192, Bit 9, Center 107 (56 ~ 159) 104
7426 01:15:05.455219 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7427 01:15:05.458386 iDelay=192, Bit 11, Center 115 (64 ~ 167) 104
7428 01:15:05.461931 iDelay=192, Bit 12, Center 131 (80 ~ 183) 104
7429 01:15:05.465269 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7430 01:15:05.471756 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7431 01:15:05.475032 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7432 01:15:05.475111 ==
7433 01:15:05.478443 Dram Type= 6, Freq= 0, CH_0, rank 0
7434 01:15:05.481671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7435 01:15:05.481750 ==
7436 01:15:05.484938 DQS Delay:
7437 01:15:05.485017 DQS0 = 0, DQS1 = 0
7438 01:15:05.485079 DQM Delay:
7439 01:15:05.488093 DQM0 = 129, DQM1 = 124
7440 01:15:05.488173 DQ Delay:
7441 01:15:05.491667 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7442 01:15:05.495220 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =135
7443 01:15:05.497981 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7444 01:15:05.504664 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7445 01:15:05.504743
7446 01:15:05.504805
7447 01:15:05.504863 ==
7448 01:15:05.508031 Dram Type= 6, Freq= 0, CH_0, rank 0
7449 01:15:05.511246 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7450 01:15:05.511325 ==
7451 01:15:05.511387
7452 01:15:05.511445
7453 01:15:05.514788 TX Vref Scan disable
7454 01:15:05.514868 == TX Byte 0 ==
7455 01:15:05.521306 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7456 01:15:05.524437 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7457 01:15:05.524518 == TX Byte 1 ==
7458 01:15:05.531530 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7459 01:15:05.534517 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7460 01:15:05.534598 ==
7461 01:15:05.537864 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 01:15:05.541045 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7463 01:15:05.541126 ==
7464 01:15:05.555762
7465 01:15:05.559098 TX Vref early break, caculate TX vref
7466 01:15:05.562621 TX Vref=16, minBit 9, minWin=21, winSum=377
7467 01:15:05.565824 TX Vref=18, minBit 7, minWin=23, winSum=385
7468 01:15:05.569083 TX Vref=20, minBit 8, minWin=23, winSum=396
7469 01:15:05.572243 TX Vref=22, minBit 8, minWin=24, winSum=403
7470 01:15:05.575572 TX Vref=24, minBit 9, minWin=24, winSum=411
7471 01:15:05.582620 TX Vref=26, minBit 8, minWin=25, winSum=416
7472 01:15:05.585301 TX Vref=28, minBit 0, minWin=25, winSum=417
7473 01:15:05.588545 TX Vref=30, minBit 3, minWin=25, winSum=416
7474 01:15:05.591915 TX Vref=32, minBit 1, minWin=24, winSum=405
7475 01:15:05.595191 TX Vref=34, minBit 0, minWin=24, winSum=397
7476 01:15:05.601979 TX Vref=36, minBit 6, minWin=22, winSum=390
7477 01:15:05.605254 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7478 01:15:05.605334
7479 01:15:05.608662 Final TX Range 0 Vref 28
7480 01:15:05.608743
7481 01:15:05.608806 ==
7482 01:15:05.612317 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 01:15:05.615044 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7484 01:15:05.615125 ==
7485 01:15:05.618349
7486 01:15:05.618429
7487 01:15:05.618492 TX Vref Scan disable
7488 01:15:05.625405 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7489 01:15:05.625484 == TX Byte 0 ==
7490 01:15:05.628526 u2DelayCellOfst[0]=14 cells (4 PI)
7491 01:15:05.631465 u2DelayCellOfst[1]=18 cells (5 PI)
7492 01:15:05.635233 u2DelayCellOfst[2]=14 cells (4 PI)
7493 01:15:05.638304 u2DelayCellOfst[3]=10 cells (3 PI)
7494 01:15:05.641575 u2DelayCellOfst[4]=7 cells (2 PI)
7495 01:15:05.644735 u2DelayCellOfst[5]=0 cells (0 PI)
7496 01:15:05.648029 u2DelayCellOfst[6]=18 cells (5 PI)
7497 01:15:05.651242 u2DelayCellOfst[7]=18 cells (5 PI)
7498 01:15:05.654990 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7499 01:15:05.658056 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7500 01:15:05.661112 == TX Byte 1 ==
7501 01:15:05.664584 u2DelayCellOfst[8]=3 cells (1 PI)
7502 01:15:05.667891 u2DelayCellOfst[9]=0 cells (0 PI)
7503 01:15:05.671101 u2DelayCellOfst[10]=10 cells (3 PI)
7504 01:15:05.674360 u2DelayCellOfst[11]=3 cells (1 PI)
7505 01:15:05.677701 u2DelayCellOfst[12]=10 cells (3 PI)
7506 01:15:05.681221 u2DelayCellOfst[13]=10 cells (3 PI)
7507 01:15:05.684458 u2DelayCellOfst[14]=18 cells (5 PI)
7508 01:15:05.684554 u2DelayCellOfst[15]=14 cells (4 PI)
7509 01:15:05.691016 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7510 01:15:05.694407 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7511 01:15:05.697465 DramC Write-DBI on
7512 01:15:05.697561 ==
7513 01:15:05.700895 Dram Type= 6, Freq= 0, CH_0, rank 0
7514 01:15:05.704189 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7515 01:15:05.704259 ==
7516 01:15:05.704328
7517 01:15:05.704388
7518 01:15:05.707584 TX Vref Scan disable
7519 01:15:05.707652 == TX Byte 0 ==
7520 01:15:05.714162 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7521 01:15:05.714234 == TX Byte 1 ==
7522 01:15:05.717478 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7523 01:15:05.720794 DramC Write-DBI off
7524 01:15:05.720894
7525 01:15:05.720982 [DATLAT]
7526 01:15:05.724054 Freq=1600, CH0 RK0
7527 01:15:05.724123
7528 01:15:05.724183 DATLAT Default: 0xf
7529 01:15:05.727482 0, 0xFFFF, sum = 0
7530 01:15:05.727577 1, 0xFFFF, sum = 0
7531 01:15:05.730602 2, 0xFFFF, sum = 0
7532 01:15:05.734031 3, 0xFFFF, sum = 0
7533 01:15:05.734126 4, 0xFFFF, sum = 0
7534 01:15:05.737102 5, 0xFFFF, sum = 0
7535 01:15:05.737171 6, 0xFFFF, sum = 0
7536 01:15:05.740578 7, 0xFFFF, sum = 0
7537 01:15:05.740660 8, 0xFFFF, sum = 0
7538 01:15:05.743961 9, 0xFFFF, sum = 0
7539 01:15:05.744044 10, 0xFFFF, sum = 0
7540 01:15:05.747322 11, 0xFFFF, sum = 0
7541 01:15:05.747404 12, 0xBFF, sum = 0
7542 01:15:05.750606 13, 0x0, sum = 1
7543 01:15:05.750688 14, 0x0, sum = 2
7544 01:15:05.753852 15, 0x0, sum = 3
7545 01:15:05.753933 16, 0x0, sum = 4
7546 01:15:05.757343 best_step = 14
7547 01:15:05.757423
7548 01:15:05.757486 ==
7549 01:15:05.760371 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 01:15:05.763637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7551 01:15:05.763718 ==
7552 01:15:05.767068 RX Vref Scan: 1
7553 01:15:05.767149
7554 01:15:05.767213 Set Vref Range= 24 -> 127
7555 01:15:05.767272
7556 01:15:05.770368 RX Vref 24 -> 127, step: 1
7557 01:15:05.770448
7558 01:15:05.773631 RX Delay 11 -> 252, step: 4
7559 01:15:05.773712
7560 01:15:05.776964 Set Vref, RX VrefLevel [Byte0]: 24
7561 01:15:05.780393 [Byte1]: 24
7562 01:15:05.780474
7563 01:15:05.783557 Set Vref, RX VrefLevel [Byte0]: 25
7564 01:15:05.786671 [Byte1]: 25
7565 01:15:05.790226
7566 01:15:05.790306 Set Vref, RX VrefLevel [Byte0]: 26
7567 01:15:05.793137 [Byte1]: 26
7568 01:15:05.797957
7569 01:15:05.798075 Set Vref, RX VrefLevel [Byte0]: 27
7570 01:15:05.800706 [Byte1]: 27
7571 01:15:05.804981
7572 01:15:05.805061 Set Vref, RX VrefLevel [Byte0]: 28
7573 01:15:05.808424 [Byte1]: 28
7574 01:15:05.812942
7575 01:15:05.813022 Set Vref, RX VrefLevel [Byte0]: 29
7576 01:15:05.816321 [Byte1]: 29
7577 01:15:05.820544
7578 01:15:05.820625 Set Vref, RX VrefLevel [Byte0]: 30
7579 01:15:05.823663 [Byte1]: 30
7580 01:15:05.827880
7581 01:15:05.827961 Set Vref, RX VrefLevel [Byte0]: 31
7582 01:15:05.831557 [Byte1]: 31
7583 01:15:05.835572
7584 01:15:05.835652 Set Vref, RX VrefLevel [Byte0]: 32
7585 01:15:05.839214 [Byte1]: 32
7586 01:15:05.843212
7587 01:15:05.843293 Set Vref, RX VrefLevel [Byte0]: 33
7588 01:15:05.846607 [Byte1]: 33
7589 01:15:05.850977
7590 01:15:05.851057 Set Vref, RX VrefLevel [Byte0]: 34
7591 01:15:05.854000 [Byte1]: 34
7592 01:15:05.858510
7593 01:15:05.858591 Set Vref, RX VrefLevel [Byte0]: 35
7594 01:15:05.862000 [Byte1]: 35
7595 01:15:05.866291
7596 01:15:05.866371 Set Vref, RX VrefLevel [Byte0]: 36
7597 01:15:05.869188 [Byte1]: 36
7598 01:15:05.874388
7599 01:15:05.874468 Set Vref, RX VrefLevel [Byte0]: 37
7600 01:15:05.877002 [Byte1]: 37
7601 01:15:05.881385
7602 01:15:05.881465 Set Vref, RX VrefLevel [Byte0]: 38
7603 01:15:05.884584 [Byte1]: 38
7604 01:15:05.888895
7605 01:15:05.888977 Set Vref, RX VrefLevel [Byte0]: 39
7606 01:15:05.892264 [Byte1]: 39
7607 01:15:05.896549
7608 01:15:05.896629 Set Vref, RX VrefLevel [Byte0]: 40
7609 01:15:05.899866 [Byte1]: 40
7610 01:15:05.903989
7611 01:15:05.904069 Set Vref, RX VrefLevel [Byte0]: 41
7612 01:15:05.907434 [Byte1]: 41
7613 01:15:05.912158
7614 01:15:05.912239 Set Vref, RX VrefLevel [Byte0]: 42
7615 01:15:05.915012 [Byte1]: 42
7616 01:15:05.919283
7617 01:15:05.919364 Set Vref, RX VrefLevel [Byte0]: 43
7618 01:15:05.922474 [Byte1]: 43
7619 01:15:05.926940
7620 01:15:05.927020 Set Vref, RX VrefLevel [Byte0]: 44
7621 01:15:05.930584 [Byte1]: 44
7622 01:15:05.934699
7623 01:15:05.934782 Set Vref, RX VrefLevel [Byte0]: 45
7624 01:15:05.937809 [Byte1]: 45
7625 01:15:05.942298
7626 01:15:05.942378 Set Vref, RX VrefLevel [Byte0]: 46
7627 01:15:05.945704 [Byte1]: 46
7628 01:15:05.950212
7629 01:15:05.950293 Set Vref, RX VrefLevel [Byte0]: 47
7630 01:15:05.953143 [Byte1]: 47
7631 01:15:05.957329
7632 01:15:05.957410 Set Vref, RX VrefLevel [Byte0]: 48
7633 01:15:05.960744 [Byte1]: 48
7634 01:15:05.964991
7635 01:15:05.965072 Set Vref, RX VrefLevel [Byte0]: 49
7636 01:15:05.968417 [Byte1]: 49
7637 01:15:05.972645
7638 01:15:05.972725 Set Vref, RX VrefLevel [Byte0]: 50
7639 01:15:05.976425 [Byte1]: 50
7640 01:15:05.980119
7641 01:15:05.980199 Set Vref, RX VrefLevel [Byte0]: 51
7642 01:15:05.983765 [Byte1]: 51
7643 01:15:05.987724
7644 01:15:05.987805 Set Vref, RX VrefLevel [Byte0]: 52
7645 01:15:05.991367 [Byte1]: 52
7646 01:15:05.995552
7647 01:15:05.995633 Set Vref, RX VrefLevel [Byte0]: 53
7648 01:15:05.998897 [Byte1]: 53
7649 01:15:06.003017
7650 01:15:06.003097 Set Vref, RX VrefLevel [Byte0]: 54
7651 01:15:06.006514 [Byte1]: 54
7652 01:15:06.011001
7653 01:15:06.011082 Set Vref, RX VrefLevel [Byte0]: 55
7654 01:15:06.014313 [Byte1]: 55
7655 01:15:06.018678
7656 01:15:06.018758 Set Vref, RX VrefLevel [Byte0]: 56
7657 01:15:06.021640 [Byte1]: 56
7658 01:15:06.025875
7659 01:15:06.025955 Set Vref, RX VrefLevel [Byte0]: 57
7660 01:15:06.029236 [Byte1]: 57
7661 01:15:06.033469
7662 01:15:06.033549 Set Vref, RX VrefLevel [Byte0]: 58
7663 01:15:06.036959 [Byte1]: 58
7664 01:15:06.041140
7665 01:15:06.041221 Set Vref, RX VrefLevel [Byte0]: 59
7666 01:15:06.044508 [Byte1]: 59
7667 01:15:06.049037
7668 01:15:06.049118 Set Vref, RX VrefLevel [Byte0]: 60
7669 01:15:06.052205 [Byte1]: 60
7670 01:15:06.056297
7671 01:15:06.056378 Set Vref, RX VrefLevel [Byte0]: 61
7672 01:15:06.059662 [Byte1]: 61
7673 01:15:06.063858
7674 01:15:06.063938 Set Vref, RX VrefLevel [Byte0]: 62
7675 01:15:06.067480 [Byte1]: 62
7676 01:15:06.071561
7677 01:15:06.071641 Set Vref, RX VrefLevel [Byte0]: 63
7678 01:15:06.074948 [Byte1]: 63
7679 01:15:06.079303
7680 01:15:06.079383 Set Vref, RX VrefLevel [Byte0]: 64
7681 01:15:06.082826 [Byte1]: 64
7682 01:15:06.086784
7683 01:15:06.086864 Set Vref, RX VrefLevel [Byte0]: 65
7684 01:15:06.090322 [Byte1]: 65
7685 01:15:06.094813
7686 01:15:06.094897 Set Vref, RX VrefLevel [Byte0]: 66
7687 01:15:06.097649 [Byte1]: 66
7688 01:15:06.102417
7689 01:15:06.102496 Set Vref, RX VrefLevel [Byte0]: 67
7690 01:15:06.105386 [Byte1]: 67
7691 01:15:06.109644
7692 01:15:06.109724 Set Vref, RX VrefLevel [Byte0]: 68
7693 01:15:06.113007 [Byte1]: 68
7694 01:15:06.117247
7695 01:15:06.117327 Set Vref, RX VrefLevel [Byte0]: 69
7696 01:15:06.121182 [Byte1]: 69
7697 01:15:06.124756
7698 01:15:06.124836 Set Vref, RX VrefLevel [Byte0]: 70
7699 01:15:06.128143 [Byte1]: 70
7700 01:15:06.132932
7701 01:15:06.133012 Set Vref, RX VrefLevel [Byte0]: 71
7702 01:15:06.135658 [Byte1]: 71
7703 01:15:06.140037
7704 01:15:06.140117 Final RX Vref Byte 0 = 53 to rank0
7705 01:15:06.143331 Final RX Vref Byte 1 = 55 to rank0
7706 01:15:06.146796 Final RX Vref Byte 0 = 53 to rank1
7707 01:15:06.150052 Final RX Vref Byte 1 = 55 to rank1==
7708 01:15:06.153515 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 01:15:06.160386 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7710 01:15:06.160468 ==
7711 01:15:06.160570 DQS Delay:
7712 01:15:06.163192 DQS0 = 0, DQS1 = 0
7713 01:15:06.163273 DQM Delay:
7714 01:15:06.163337 DQM0 = 127, DQM1 = 121
7715 01:15:06.166724 DQ Delay:
7716 01:15:06.169824 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7717 01:15:06.173431 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7718 01:15:06.176253 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7719 01:15:06.179808 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7720 01:15:06.179888
7721 01:15:06.179951
7722 01:15:06.180009
7723 01:15:06.183263 [DramC_TX_OE_Calibration] TA2
7724 01:15:06.186440 Original DQ_B0 (3 6) =30, OEN = 27
7725 01:15:06.189488 Original DQ_B1 (3 6) =30, OEN = 27
7726 01:15:06.192826 24, 0x0, End_B0=24 End_B1=24
7727 01:15:06.192909 25, 0x0, End_B0=25 End_B1=25
7728 01:15:06.196175 26, 0x0, End_B0=26 End_B1=26
7729 01:15:06.199619 27, 0x0, End_B0=27 End_B1=27
7730 01:15:06.203094 28, 0x0, End_B0=28 End_B1=28
7731 01:15:06.206573 29, 0x0, End_B0=29 End_B1=29
7732 01:15:06.206655 30, 0x0, End_B0=30 End_B1=30
7733 01:15:06.209402 31, 0x4141, End_B0=30 End_B1=30
7734 01:15:06.212872 Byte0 end_step=30 best_step=27
7735 01:15:06.216096 Byte1 end_step=30 best_step=27
7736 01:15:06.219470 Byte0 TX OE(2T, 0.5T) = (3, 3)
7737 01:15:06.222725 Byte1 TX OE(2T, 0.5T) = (3, 3)
7738 01:15:06.222806
7739 01:15:06.222869
7740 01:15:06.231265 [DQSOSCAuto] RK0, (LSB)MR18= 0x1717, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7741 01:15:06.232758 CH0 RK0: MR19=303, MR18=1717
7742 01:15:06.239473 CH0_RK0: MR19=0x303, MR18=0x1717, DQSOSC=398, MR23=63, INC=23, DEC=15
7743 01:15:06.239555
7744 01:15:06.242717 ----->DramcWriteLeveling(PI) begin...
7745 01:15:06.242816 ==
7746 01:15:06.246183 Dram Type= 6, Freq= 0, CH_0, rank 1
7747 01:15:06.249659 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7748 01:15:06.249741 ==
7749 01:15:06.252813 Write leveling (Byte 0): 29 => 29
7750 01:15:06.256300 Write leveling (Byte 1): 28 => 28
7751 01:15:06.259208 DramcWriteLeveling(PI) end<-----
7752 01:15:06.259288
7753 01:15:06.259351 ==
7754 01:15:06.262476 Dram Type= 6, Freq= 0, CH_0, rank 1
7755 01:15:06.266044 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7756 01:15:06.266139 ==
7757 01:15:06.269356 [Gating] SW mode calibration
7758 01:15:06.275849 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7759 01:15:06.282524 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7760 01:15:06.285705 0 12 0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7761 01:15:06.292782 0 12 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7762 01:15:06.295629 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7763 01:15:06.299322 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7764 01:15:06.305502 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7765 01:15:06.309285 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7766 01:15:06.312325 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7767 01:15:06.318656 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7768 01:15:06.322291 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
7769 01:15:06.325263 0 13 4 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
7770 01:15:06.331953 0 13 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7771 01:15:06.335185 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7772 01:15:06.338606 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7773 01:15:06.345403 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7774 01:15:06.348758 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7775 01:15:06.351906 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7776 01:15:06.358500 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7777 01:15:06.361889 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7778 01:15:06.364885 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7779 01:15:06.371543 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7780 01:15:06.375156 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7781 01:15:06.378273 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7782 01:15:06.381799 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7783 01:15:06.388396 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7784 01:15:06.391440 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7785 01:15:06.394812 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7786 01:15:06.401687 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7787 01:15:06.405105 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7788 01:15:06.408112 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7789 01:15:06.414707 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7790 01:15:06.417853 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7791 01:15:06.421199 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7792 01:15:06.428111 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7793 01:15:06.431276 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7794 01:15:06.434609 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7795 01:15:06.441579 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7796 01:15:06.444895 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7797 01:15:06.448027 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7798 01:15:06.454656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7799 01:15:06.457857 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7800 01:15:06.461472 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7801 01:15:06.467720 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7802 01:15:06.471164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7803 01:15:06.474618 Total UI for P1: 0, mck2ui 16
7804 01:15:06.477481 best dqsien dly found for B0: ( 1, 1, 0)
7805 01:15:06.480996 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 01:15:06.484174 Total UI for P1: 0, mck2ui 16
7807 01:15:06.487479 best dqsien dly found for B1: ( 1, 1, 4)
7808 01:15:06.490958 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7809 01:15:06.494170 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7810 01:15:06.494251
7811 01:15:06.497517 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7812 01:15:06.504092 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7813 01:15:06.504173 [Gating] SW calibration Done
7814 01:15:06.507627 ==
7815 01:15:06.507708 Dram Type= 6, Freq= 0, CH_0, rank 1
7816 01:15:06.514092 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7817 01:15:06.514177 ==
7818 01:15:06.514242 RX Vref Scan: 0
7819 01:15:06.514302
7820 01:15:06.517375 RX Vref 0 -> 0, step: 1
7821 01:15:06.517455
7822 01:15:06.520640 RX Delay 0 -> 252, step: 8
7823 01:15:06.524531 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7824 01:15:06.527576 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7825 01:15:06.530526 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7826 01:15:06.537297 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7827 01:15:06.540409 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7828 01:15:06.544195 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7829 01:15:06.547276 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7830 01:15:06.550464 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7831 01:15:06.556896 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7832 01:15:06.560528 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7833 01:15:06.564358 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7834 01:15:06.567034 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7835 01:15:06.570468 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7836 01:15:06.577203 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7837 01:15:06.580285 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7838 01:15:06.583426 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7839 01:15:06.583508 ==
7840 01:15:06.587032 Dram Type= 6, Freq= 0, CH_0, rank 1
7841 01:15:06.589956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7842 01:15:06.593512 ==
7843 01:15:06.593593 DQS Delay:
7844 01:15:06.593657 DQS0 = 0, DQS1 = 0
7845 01:15:06.596578 DQM Delay:
7846 01:15:06.596659 DQM0 = 130, DQM1 = 124
7847 01:15:06.599897 DQ Delay:
7848 01:15:06.603201 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7849 01:15:06.606891 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7850 01:15:06.609988 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7851 01:15:06.613440 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7852 01:15:06.613521
7853 01:15:06.613585
7854 01:15:06.613644 ==
7855 01:15:06.616802 Dram Type= 6, Freq= 0, CH_0, rank 1
7856 01:15:06.619973 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7857 01:15:06.620054 ==
7858 01:15:06.623060
7859 01:15:06.623141
7860 01:15:06.623204 TX Vref Scan disable
7861 01:15:06.626740 == TX Byte 0 ==
7862 01:15:06.629903 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7863 01:15:06.633111 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7864 01:15:06.637034 == TX Byte 1 ==
7865 01:15:06.639906 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7866 01:15:06.643180 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7867 01:15:06.646194 ==
7868 01:15:06.646274 Dram Type= 6, Freq= 0, CH_0, rank 1
7869 01:15:06.652796 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7870 01:15:06.652878 ==
7871 01:15:06.664693
7872 01:15:06.668053 TX Vref early break, caculate TX vref
7873 01:15:06.671751 TX Vref=16, minBit 0, minWin=23, winSum=380
7874 01:15:06.674885 TX Vref=18, minBit 9, minWin=22, winSum=385
7875 01:15:06.678231 TX Vref=20, minBit 9, minWin=23, winSum=396
7876 01:15:06.681082 TX Vref=22, minBit 1, minWin=24, winSum=402
7877 01:15:06.684410 TX Vref=24, minBit 1, minWin=24, winSum=412
7878 01:15:06.690999 TX Vref=26, minBit 1, minWin=25, winSum=418
7879 01:15:06.694282 TX Vref=28, minBit 8, minWin=25, winSum=425
7880 01:15:06.697608 TX Vref=30, minBit 0, minWin=25, winSum=417
7881 01:15:06.700847 TX Vref=32, minBit 4, minWin=24, winSum=404
7882 01:15:06.704005 TX Vref=34, minBit 8, minWin=23, winSum=398
7883 01:15:06.710742 [TxChooseVref] Worse bit 8, Min win 25, Win sum 425, Final Vref 28
7884 01:15:06.710823
7885 01:15:06.713996 Final TX Range 0 Vref 28
7886 01:15:06.714110
7887 01:15:06.714174 ==
7888 01:15:06.718042 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 01:15:06.720623 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 01:15:06.720704 ==
7891 01:15:06.720768
7892 01:15:06.720827
7893 01:15:06.723969 TX Vref Scan disable
7894 01:15:06.730862 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7895 01:15:06.730944 == TX Byte 0 ==
7896 01:15:06.733913 u2DelayCellOfst[0]=14 cells (4 PI)
7897 01:15:06.737013 u2DelayCellOfst[1]=18 cells (5 PI)
7898 01:15:06.740402 u2DelayCellOfst[2]=14 cells (4 PI)
7899 01:15:06.743857 u2DelayCellOfst[3]=14 cells (4 PI)
7900 01:15:06.747014 u2DelayCellOfst[4]=10 cells (3 PI)
7901 01:15:06.750534 u2DelayCellOfst[5]=0 cells (0 PI)
7902 01:15:06.753650 u2DelayCellOfst[6]=21 cells (6 PI)
7903 01:15:06.756887 u2DelayCellOfst[7]=18 cells (5 PI)
7904 01:15:06.760501 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7905 01:15:06.763566 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7906 01:15:06.766855 == TX Byte 1 ==
7907 01:15:06.770033 u2DelayCellOfst[8]=3 cells (1 PI)
7908 01:15:06.773497 u2DelayCellOfst[9]=0 cells (0 PI)
7909 01:15:06.776593 u2DelayCellOfst[10]=10 cells (3 PI)
7910 01:15:06.776673 u2DelayCellOfst[11]=3 cells (1 PI)
7911 01:15:06.779930 u2DelayCellOfst[12]=14 cells (4 PI)
7912 01:15:06.783327 u2DelayCellOfst[13]=14 cells (4 PI)
7913 01:15:06.786774 u2DelayCellOfst[14]=18 cells (5 PI)
7914 01:15:06.789997 u2DelayCellOfst[15]=14 cells (4 PI)
7915 01:15:06.796555 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7916 01:15:06.799880 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7917 01:15:06.799961 DramC Write-DBI on
7918 01:15:06.803093 ==
7919 01:15:06.803174 Dram Type= 6, Freq= 0, CH_0, rank 1
7920 01:15:06.809805 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7921 01:15:06.809886 ==
7922 01:15:06.809949
7923 01:15:06.810008
7924 01:15:06.812964 TX Vref Scan disable
7925 01:15:06.813045 == TX Byte 0 ==
7926 01:15:06.819624 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7927 01:15:06.819705 == TX Byte 1 ==
7928 01:15:06.822973 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7929 01:15:06.826452 DramC Write-DBI off
7930 01:15:06.826532
7931 01:15:06.826596 [DATLAT]
7932 01:15:06.829811 Freq=1600, CH0 RK1
7933 01:15:06.829892
7934 01:15:06.829956 DATLAT Default: 0xe
7935 01:15:06.832998 0, 0xFFFF, sum = 0
7936 01:15:06.833081 1, 0xFFFF, sum = 0
7937 01:15:06.836355 2, 0xFFFF, sum = 0
7938 01:15:06.836436 3, 0xFFFF, sum = 0
7939 01:15:06.839745 4, 0xFFFF, sum = 0
7940 01:15:06.839826 5, 0xFFFF, sum = 0
7941 01:15:06.843058 6, 0xFFFF, sum = 0
7942 01:15:06.843140 7, 0xFFFF, sum = 0
7943 01:15:06.846246 8, 0xFFFF, sum = 0
7944 01:15:06.849343 9, 0xFFFF, sum = 0
7945 01:15:06.849447 10, 0xFFFF, sum = 0
7946 01:15:06.852535 11, 0xFFFF, sum = 0
7947 01:15:06.852617 12, 0x8FFF, sum = 0
7948 01:15:06.855836 13, 0x0, sum = 1
7949 01:15:06.855917 14, 0x0, sum = 2
7950 01:15:06.859142 15, 0x0, sum = 3
7951 01:15:06.859223 16, 0x0, sum = 4
7952 01:15:06.859288 best_step = 14
7953 01:15:06.862487
7954 01:15:06.862567 ==
7955 01:15:06.865763 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 01:15:06.868992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7957 01:15:06.869074 ==
7958 01:15:06.869137 RX Vref Scan: 0
7959 01:15:06.869196
7960 01:15:06.872345 RX Vref 0 -> 0, step: 1
7961 01:15:06.872426
7962 01:15:06.875751 RX Delay 11 -> 252, step: 4
7963 01:15:06.879083 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7964 01:15:06.885556 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7965 01:15:06.889329 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7966 01:15:06.892034 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7967 01:15:06.895462 iDelay=195, Bit 4, Center 134 (79 ~ 190) 112
7968 01:15:06.898647 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7969 01:15:06.905289 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7970 01:15:06.908628 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7971 01:15:06.911797 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7972 01:15:06.915128 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7973 01:15:06.918532 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7974 01:15:06.925080 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7975 01:15:06.928517 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7976 01:15:06.932378 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7977 01:15:06.935476 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7978 01:15:06.941648 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7979 01:15:06.941729 ==
7980 01:15:06.945649 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 01:15:06.948501 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7982 01:15:06.948582 ==
7983 01:15:06.948646 DQS Delay:
7984 01:15:06.951645 DQS0 = 0, DQS1 = 0
7985 01:15:06.951726 DQM Delay:
7986 01:15:06.955099 DQM0 = 129, DQM1 = 120
7987 01:15:06.955180 DQ Delay:
7988 01:15:06.958261 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7989 01:15:06.961853 DQ4 =134, DQ5 =120, DQ6 =138, DQ7 =138
7990 01:15:06.964998 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7991 01:15:06.968270 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7992 01:15:06.968351
7993 01:15:06.968414
7994 01:15:06.968473
7995 01:15:06.971635 [DramC_TX_OE_Calibration] TA2
7996 01:15:06.974763 Original DQ_B0 (3 6) =30, OEN = 27
7997 01:15:06.978227 Original DQ_B1 (3 6) =30, OEN = 27
7998 01:15:06.981701 24, 0x0, End_B0=24 End_B1=24
7999 01:15:06.984994 25, 0x0, End_B0=25 End_B1=25
8000 01:15:06.985076 26, 0x0, End_B0=26 End_B1=26
8001 01:15:06.988165 27, 0x0, End_B0=27 End_B1=27
8002 01:15:06.991185 28, 0x0, End_B0=28 End_B1=28
8003 01:15:06.994622 29, 0x0, End_B0=29 End_B1=29
8004 01:15:06.997842 30, 0x0, End_B0=30 End_B1=30
8005 01:15:06.997924 31, 0x4141, End_B0=30 End_B1=30
8006 01:15:07.001312 Byte0 end_step=30 best_step=27
8007 01:15:07.004748 Byte1 end_step=30 best_step=27
8008 01:15:07.007913 Byte0 TX OE(2T, 0.5T) = (3, 3)
8009 01:15:07.011073 Byte1 TX OE(2T, 0.5T) = (3, 3)
8010 01:15:07.011153
8011 01:15:07.011217
8012 01:15:07.017914 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8013 01:15:07.021314 CH0 RK1: MR19=303, MR18=2222
8014 01:15:07.027843 CH0_RK1: MR19=0x303, MR18=0x2222, DQSOSC=392, MR23=63, INC=24, DEC=16
8015 01:15:07.031090 [RxdqsGatingPostProcess] freq 1600
8016 01:15:07.037804 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8017 01:15:07.040965 Pre-setting of DQS Precalculation
8018 01:15:07.044638 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8019 01:15:07.044719 ==
8020 01:15:07.047570 Dram Type= 6, Freq= 0, CH_1, rank 0
8021 01:15:07.050980 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8022 01:15:07.051062 ==
8023 01:15:07.057360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8024 01:15:07.060913 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8025 01:15:07.067562 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8026 01:15:07.070641 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8027 01:15:07.080095 [CA 0] Center 41 (11~71) winsize 61
8028 01:15:07.083271 [CA 1] Center 40 (10~70) winsize 61
8029 01:15:07.086986 [CA 2] Center 36 (7~66) winsize 60
8030 01:15:07.090021 [CA 3] Center 35 (6~65) winsize 60
8031 01:15:07.093686 [CA 4] Center 33 (4~63) winsize 60
8032 01:15:07.096602 [CA 5] Center 33 (4~63) winsize 60
8033 01:15:07.096707
8034 01:15:07.100152 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8035 01:15:07.100233
8036 01:15:07.106540 [CATrainingPosCal] consider 1 rank data
8037 01:15:07.106623 u2DelayCellTimex100 = 271/100 ps
8038 01:15:07.113182 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8039 01:15:07.116254 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8040 01:15:07.119547 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8041 01:15:07.122875 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8042 01:15:07.126239 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8043 01:15:07.129507 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8044 01:15:07.129588
8045 01:15:07.133117 CA PerBit enable=1, Macro0, CA PI delay=33
8046 01:15:07.133205
8047 01:15:07.136123 [CBTSetCACLKResult] CA Dly = 33
8048 01:15:07.139675 CS Dly: 8 (0~39)
8049 01:15:07.142804 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8050 01:15:07.146156 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8051 01:15:07.146237 ==
8052 01:15:07.149553 Dram Type= 6, Freq= 0, CH_1, rank 1
8053 01:15:07.155987 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8054 01:15:07.156069 ==
8055 01:15:07.159488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8056 01:15:07.166312 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8057 01:15:07.169596 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8058 01:15:07.176090 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8059 01:15:07.182399 [CA 0] Center 40 (10~70) winsize 61
8060 01:15:07.185853 [CA 1] Center 39 (9~70) winsize 62
8061 01:15:07.188960 [CA 2] Center 35 (6~65) winsize 60
8062 01:15:07.192529 [CA 3] Center 35 (5~65) winsize 61
8063 01:15:07.195753 [CA 4] Center 32 (3~62) winsize 60
8064 01:15:07.198955 [CA 5] Center 33 (4~63) winsize 60
8065 01:15:07.199035
8066 01:15:07.202690 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8067 01:15:07.202772
8068 01:15:07.205653 [CATrainingPosCal] consider 2 rank data
8069 01:15:07.208997 u2DelayCellTimex100 = 271/100 ps
8070 01:15:07.212236 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8071 01:15:07.219070 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8072 01:15:07.222127 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8073 01:15:07.225650 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8074 01:15:07.228869 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8075 01:15:07.232006 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8076 01:15:07.232087
8077 01:15:07.235368 CA PerBit enable=1, Macro0, CA PI delay=33
8078 01:15:07.235449
8079 01:15:07.238438 [CBTSetCACLKResult] CA Dly = 33
8080 01:15:07.241867 CS Dly: 9 (0~41)
8081 01:15:07.245117 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8082 01:15:07.248607 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8083 01:15:07.248713
8084 01:15:07.251721 ----->DramcWriteLeveling(PI) begin...
8085 01:15:07.251803 ==
8086 01:15:07.255500 Dram Type= 6, Freq= 0, CH_1, rank 0
8087 01:15:07.261643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8088 01:15:07.261724 ==
8089 01:15:07.265365 Write leveling (Byte 0): 22 => 22
8090 01:15:07.265446 Write leveling (Byte 1): 22 => 22
8091 01:15:07.268392 DramcWriteLeveling(PI) end<-----
8092 01:15:07.268473
8093 01:15:07.271898 ==
8094 01:15:07.271978 Dram Type= 6, Freq= 0, CH_1, rank 0
8095 01:15:07.278281 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8096 01:15:07.278362 ==
8097 01:15:07.281637 [Gating] SW mode calibration
8098 01:15:07.288053 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8099 01:15:07.291616 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8100 01:15:07.297985 0 12 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8101 01:15:07.301593 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 01:15:07.304682 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 01:15:07.311349 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 01:15:07.314652 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 01:15:07.318131 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 01:15:07.324815 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8107 01:15:07.328172 0 12 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
8108 01:15:07.331320 0 13 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8109 01:15:07.337857 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8110 01:15:07.341015 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 01:15:07.344512 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 01:15:07.351175 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 01:15:07.354148 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 01:15:07.357863 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8115 01:15:07.364513 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8116 01:15:07.367532 0 14 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8117 01:15:07.370782 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 01:15:07.377605 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 01:15:07.380849 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 01:15:07.384125 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 01:15:07.390725 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 01:15:07.394134 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8123 01:15:07.397364 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8124 01:15:07.404075 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8125 01:15:07.407205 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8126 01:15:07.410656 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 01:15:07.417116 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 01:15:07.420629 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 01:15:07.423903 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 01:15:07.430545 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 01:15:07.433963 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 01:15:07.437668 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 01:15:07.444160 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 01:15:07.447308 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 01:15:07.450325 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 01:15:07.456967 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 01:15:07.460569 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 01:15:07.464080 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 01:15:07.470226 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8140 01:15:07.473719 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8141 01:15:07.476694 Total UI for P1: 0, mck2ui 16
8142 01:15:07.480048 best dqsien dly found for B0: ( 1, 0, 28)
8143 01:15:07.483377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8144 01:15:07.490324 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 01:15:07.490815 Total UI for P1: 0, mck2ui 16
8146 01:15:07.493327 best dqsien dly found for B1: ( 1, 1, 2)
8147 01:15:07.499785 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8148 01:15:07.503233 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8149 01:15:07.503714
8150 01:15:07.506743 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8151 01:15:07.510212 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8152 01:15:07.513322 [Gating] SW calibration Done
8153 01:15:07.513801 ==
8154 01:15:07.516344 Dram Type= 6, Freq= 0, CH_1, rank 0
8155 01:15:07.519599 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8156 01:15:07.520074 ==
8157 01:15:07.523201 RX Vref Scan: 0
8158 01:15:07.523618
8159 01:15:07.523947 RX Vref 0 -> 0, step: 1
8160 01:15:07.524254
8161 01:15:07.526326 RX Delay 0 -> 252, step: 8
8162 01:15:07.529809 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8163 01:15:07.533553 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8164 01:15:07.539752 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8165 01:15:07.543129 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8166 01:15:07.546299 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8167 01:15:07.549492 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8168 01:15:07.552818 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8169 01:15:07.559450 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8170 01:15:07.562646 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8171 01:15:07.566123 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8172 01:15:07.569340 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8173 01:15:07.576206 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8174 01:15:07.579666 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8175 01:15:07.582456 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8176 01:15:07.585798 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8177 01:15:07.588963 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8178 01:15:07.592503 ==
8179 01:15:07.595964 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 01:15:07.598778 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 01:15:07.599196 ==
8182 01:15:07.599518 DQS Delay:
8183 01:15:07.602118 DQS0 = 0, DQS1 = 0
8184 01:15:07.602535 DQM Delay:
8185 01:15:07.605587 DQM0 = 130, DQM1 = 126
8186 01:15:07.606004 DQ Delay:
8187 01:15:07.609027 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8188 01:15:07.612057 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8189 01:15:07.615411 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8190 01:15:07.618901 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8191 01:15:07.619318
8192 01:15:07.619647
8193 01:15:07.619951 ==
8194 01:15:07.622125 Dram Type= 6, Freq= 0, CH_1, rank 0
8195 01:15:07.628735 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8196 01:15:07.629152 ==
8197 01:15:07.629484
8198 01:15:07.629789
8199 01:15:07.631938 TX Vref Scan disable
8200 01:15:07.632346 == TX Byte 0 ==
8201 01:15:07.635225 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8202 01:15:07.641864 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8203 01:15:07.642315 == TX Byte 1 ==
8204 01:15:07.645263 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8205 01:15:07.651985 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8206 01:15:07.652394 ==
8207 01:15:07.655156 Dram Type= 6, Freq= 0, CH_1, rank 0
8208 01:15:07.658386 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8209 01:15:07.658796 ==
8210 01:15:07.670873
8211 01:15:07.674220 TX Vref early break, caculate TX vref
8212 01:15:07.677884 TX Vref=16, minBit 3, minWin=21, winSum=369
8213 01:15:07.680806 TX Vref=18, minBit 7, minWin=22, winSum=377
8214 01:15:07.684426 TX Vref=20, minBit 0, minWin=23, winSum=385
8215 01:15:07.687549 TX Vref=22, minBit 3, minWin=23, winSum=393
8216 01:15:07.690344 TX Vref=24, minBit 0, minWin=24, winSum=400
8217 01:15:07.697204 TX Vref=26, minBit 3, minWin=24, winSum=410
8218 01:15:07.699974 TX Vref=28, minBit 3, minWin=24, winSum=413
8219 01:15:07.703516 TX Vref=30, minBit 0, minWin=25, winSum=408
8220 01:15:07.706767 TX Vref=32, minBit 3, minWin=23, winSum=397
8221 01:15:07.709938 TX Vref=34, minBit 3, minWin=23, winSum=388
8222 01:15:07.716673 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 30
8223 01:15:07.716752
8224 01:15:07.719816 Final TX Range 0 Vref 30
8225 01:15:07.719896
8226 01:15:07.719958 ==
8227 01:15:07.723148 Dram Type= 6, Freq= 0, CH_1, rank 0
8228 01:15:07.726365 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8229 01:15:07.726445 ==
8230 01:15:07.726507
8231 01:15:07.726565
8232 01:15:07.730121 TX Vref Scan disable
8233 01:15:07.736666 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8234 01:15:07.736757 == TX Byte 0 ==
8235 01:15:07.739785 u2DelayCellOfst[0]=14 cells (4 PI)
8236 01:15:07.742942 u2DelayCellOfst[1]=10 cells (3 PI)
8237 01:15:07.746257 u2DelayCellOfst[2]=0 cells (0 PI)
8238 01:15:07.749425 u2DelayCellOfst[3]=7 cells (2 PI)
8239 01:15:07.752765 u2DelayCellOfst[4]=7 cells (2 PI)
8240 01:15:07.756056 u2DelayCellOfst[5]=14 cells (4 PI)
8241 01:15:07.759566 u2DelayCellOfst[6]=18 cells (5 PI)
8242 01:15:07.762676 u2DelayCellOfst[7]=7 cells (2 PI)
8243 01:15:07.765915 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8244 01:15:07.769642 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8245 01:15:07.772697 == TX Byte 1 ==
8246 01:15:07.776270 u2DelayCellOfst[8]=0 cells (0 PI)
8247 01:15:07.779644 u2DelayCellOfst[9]=7 cells (2 PI)
8248 01:15:07.782506 u2DelayCellOfst[10]=10 cells (3 PI)
8249 01:15:07.782797 u2DelayCellOfst[11]=3 cells (1 PI)
8250 01:15:07.786185 u2DelayCellOfst[12]=18 cells (5 PI)
8251 01:15:07.789518 u2DelayCellOfst[13]=21 cells (6 PI)
8252 01:15:07.792940 u2DelayCellOfst[14]=21 cells (6 PI)
8253 01:15:07.795733 u2DelayCellOfst[15]=21 cells (6 PI)
8254 01:15:07.802573 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8255 01:15:07.805518 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8256 01:15:07.805597 DramC Write-DBI on
8257 01:15:07.805660 ==
8258 01:15:07.808982 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 01:15:07.815331 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8260 01:15:07.815411 ==
8261 01:15:07.815473
8262 01:15:07.815530
8263 01:15:07.818993 TX Vref Scan disable
8264 01:15:07.819072 == TX Byte 0 ==
8265 01:15:07.825079 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8266 01:15:07.825159 == TX Byte 1 ==
8267 01:15:07.828489 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8268 01:15:07.831851 DramC Write-DBI off
8269 01:15:07.831930
8270 01:15:07.831992 [DATLAT]
8271 01:15:07.835037 Freq=1600, CH1 RK0
8272 01:15:07.835116
8273 01:15:07.835178 DATLAT Default: 0xf
8274 01:15:07.838648 0, 0xFFFF, sum = 0
8275 01:15:07.838729 1, 0xFFFF, sum = 0
8276 01:15:07.841881 2, 0xFFFF, sum = 0
8277 01:15:07.841988 3, 0xFFFF, sum = 0
8278 01:15:07.845364 4, 0xFFFF, sum = 0
8279 01:15:07.845445 5, 0xFFFF, sum = 0
8280 01:15:07.848298 6, 0xFFFF, sum = 0
8281 01:15:07.848378 7, 0xFFFF, sum = 0
8282 01:15:07.851750 8, 0xFFFF, sum = 0
8283 01:15:07.851831 9, 0xFFFF, sum = 0
8284 01:15:07.855065 10, 0xFFFF, sum = 0
8285 01:15:07.858303 11, 0xFFFF, sum = 0
8286 01:15:07.858384 12, 0x8FFF, sum = 0
8287 01:15:07.861769 13, 0x0, sum = 1
8288 01:15:07.861875 14, 0x0, sum = 2
8289 01:15:07.864875 15, 0x0, sum = 3
8290 01:15:07.864956 16, 0x0, sum = 4
8291 01:15:07.865020 best_step = 14
8292 01:15:07.865077
8293 01:15:07.868113 ==
8294 01:15:07.871904 Dram Type= 6, Freq= 0, CH_1, rank 0
8295 01:15:07.874772 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8296 01:15:07.874852 ==
8297 01:15:07.874914 RX Vref Scan: 1
8298 01:15:07.874971
8299 01:15:07.878114 Set Vref Range= 24 -> 127
8300 01:15:07.878193
8301 01:15:07.881287 RX Vref 24 -> 127, step: 1
8302 01:15:07.881372
8303 01:15:07.885047 RX Delay 3 -> 252, step: 4
8304 01:15:07.885125
8305 01:15:07.888054 Set Vref, RX VrefLevel [Byte0]: 24
8306 01:15:07.891588 [Byte1]: 24
8307 01:15:07.891668
8308 01:15:07.894681 Set Vref, RX VrefLevel [Byte0]: 25
8309 01:15:07.898687 [Byte1]: 25
8310 01:15:07.898791
8311 01:15:07.901586 Set Vref, RX VrefLevel [Byte0]: 26
8312 01:15:07.904701 [Byte1]: 26
8313 01:15:07.908286
8314 01:15:07.908367 Set Vref, RX VrefLevel [Byte0]: 27
8315 01:15:07.911498 [Byte1]: 27
8316 01:15:07.915919
8317 01:15:07.915998 Set Vref, RX VrefLevel [Byte0]: 28
8318 01:15:07.919105 [Byte1]: 28
8319 01:15:07.923692
8320 01:15:07.923770 Set Vref, RX VrefLevel [Byte0]: 29
8321 01:15:07.926715 [Byte1]: 29
8322 01:15:07.931079
8323 01:15:07.931157 Set Vref, RX VrefLevel [Byte0]: 30
8324 01:15:07.934557 [Byte1]: 30
8325 01:15:07.938770
8326 01:15:07.938849 Set Vref, RX VrefLevel [Byte0]: 31
8327 01:15:07.942341 [Byte1]: 31
8328 01:15:07.946365
8329 01:15:07.946444 Set Vref, RX VrefLevel [Byte0]: 32
8330 01:15:07.949758 [Byte1]: 32
8331 01:15:07.954272
8332 01:15:07.954351 Set Vref, RX VrefLevel [Byte0]: 33
8333 01:15:07.957354 [Byte1]: 33
8334 01:15:07.961947
8335 01:15:07.962100 Set Vref, RX VrefLevel [Byte0]: 34
8336 01:15:07.965097 [Byte1]: 34
8337 01:15:07.969467
8338 01:15:07.969545 Set Vref, RX VrefLevel [Byte0]: 35
8339 01:15:07.972713 [Byte1]: 35
8340 01:15:07.977088
8341 01:15:07.977169 Set Vref, RX VrefLevel [Byte0]: 36
8342 01:15:07.980656 [Byte1]: 36
8343 01:15:07.984755
8344 01:15:07.984833 Set Vref, RX VrefLevel [Byte0]: 37
8345 01:15:07.988063 [Byte1]: 37
8346 01:15:07.992571
8347 01:15:07.992649 Set Vref, RX VrefLevel [Byte0]: 38
8348 01:15:07.995647 [Byte1]: 38
8349 01:15:08.000269
8350 01:15:08.000348 Set Vref, RX VrefLevel [Byte0]: 39
8351 01:15:08.003497 [Byte1]: 39
8352 01:15:08.007633
8353 01:15:08.007711 Set Vref, RX VrefLevel [Byte0]: 40
8354 01:15:08.011021 [Byte1]: 40
8355 01:15:08.015460
8356 01:15:08.015574 Set Vref, RX VrefLevel [Byte0]: 41
8357 01:15:08.018967 [Byte1]: 41
8358 01:15:08.023020
8359 01:15:08.023098 Set Vref, RX VrefLevel [Byte0]: 42
8360 01:15:08.026218 [Byte1]: 42
8361 01:15:08.030817
8362 01:15:08.030895 Set Vref, RX VrefLevel [Byte0]: 43
8363 01:15:08.033929 [Byte1]: 43
8364 01:15:08.038112
8365 01:15:08.038191 Set Vref, RX VrefLevel [Byte0]: 44
8366 01:15:08.041562 [Byte1]: 44
8367 01:15:08.046284
8368 01:15:08.046363 Set Vref, RX VrefLevel [Byte0]: 45
8369 01:15:08.049199 [Byte1]: 45
8370 01:15:08.053478
8371 01:15:08.053557 Set Vref, RX VrefLevel [Byte0]: 46
8372 01:15:08.056763 [Byte1]: 46
8373 01:15:08.061231
8374 01:15:08.061308 Set Vref, RX VrefLevel [Byte0]: 47
8375 01:15:08.064494 [Byte1]: 47
8376 01:15:08.068970
8377 01:15:08.069048 Set Vref, RX VrefLevel [Byte0]: 48
8378 01:15:08.072073 [Byte1]: 48
8379 01:15:08.076844
8380 01:15:08.076922 Set Vref, RX VrefLevel [Byte0]: 49
8381 01:15:08.079843 [Byte1]: 49
8382 01:15:08.084401
8383 01:15:08.084479 Set Vref, RX VrefLevel [Byte0]: 50
8384 01:15:08.087677 [Byte1]: 50
8385 01:15:08.091985
8386 01:15:08.092069 Set Vref, RX VrefLevel [Byte0]: 51
8387 01:15:08.095114 [Byte1]: 51
8388 01:15:08.099545
8389 01:15:08.099655 Set Vref, RX VrefLevel [Byte0]: 52
8390 01:15:08.102756 [Byte1]: 52
8391 01:15:08.107216
8392 01:15:08.107294 Set Vref, RX VrefLevel [Byte0]: 53
8393 01:15:08.110538 [Byte1]: 53
8394 01:15:08.114788
8395 01:15:08.114867 Set Vref, RX VrefLevel [Byte0]: 54
8396 01:15:08.117954 [Byte1]: 54
8397 01:15:08.122176
8398 01:15:08.125860 Set Vref, RX VrefLevel [Byte0]: 55
8399 01:15:08.128849 [Byte1]: 55
8400 01:15:08.128928
8401 01:15:08.132118 Set Vref, RX VrefLevel [Byte0]: 56
8402 01:15:08.135503 [Byte1]: 56
8403 01:15:08.135582
8404 01:15:08.139099 Set Vref, RX VrefLevel [Byte0]: 57
8405 01:15:08.142013 [Byte1]: 57
8406 01:15:08.145348
8407 01:15:08.145430 Set Vref, RX VrefLevel [Byte0]: 58
8408 01:15:08.149267 [Byte1]: 58
8409 01:15:08.153226
8410 01:15:08.153304 Set Vref, RX VrefLevel [Byte0]: 59
8411 01:15:08.156264 [Byte1]: 59
8412 01:15:08.160873
8413 01:15:08.160951 Set Vref, RX VrefLevel [Byte0]: 60
8414 01:15:08.164147 [Byte1]: 60
8415 01:15:08.168278
8416 01:15:08.168357 Set Vref, RX VrefLevel [Byte0]: 61
8417 01:15:08.171680 [Byte1]: 61
8418 01:15:08.175969
8419 01:15:08.176053 Set Vref, RX VrefLevel [Byte0]: 62
8420 01:15:08.179363 [Byte1]: 62
8421 01:15:08.183755
8422 01:15:08.183890 Set Vref, RX VrefLevel [Byte0]: 63
8423 01:15:08.187299 [Byte1]: 63
8424 01:15:08.191334
8425 01:15:08.191441 Set Vref, RX VrefLevel [Byte0]: 64
8426 01:15:08.194681 [Byte1]: 64
8427 01:15:08.198950
8428 01:15:08.199081 Set Vref, RX VrefLevel [Byte0]: 65
8429 01:15:08.202279 [Byte1]: 65
8430 01:15:08.206822
8431 01:15:08.207015 Set Vref, RX VrefLevel [Byte0]: 66
8432 01:15:08.210381 [Byte1]: 66
8433 01:15:08.214526
8434 01:15:08.214724 Set Vref, RX VrefLevel [Byte0]: 67
8435 01:15:08.217604 [Byte1]: 67
8436 01:15:08.222354
8437 01:15:08.222598 Set Vref, RX VrefLevel [Byte0]: 68
8438 01:15:08.225603 [Byte1]: 68
8439 01:15:08.229962
8440 01:15:08.230385 Set Vref, RX VrefLevel [Byte0]: 69
8441 01:15:08.233389 [Byte1]: 69
8442 01:15:08.237827
8443 01:15:08.238274 Set Vref, RX VrefLevel [Byte0]: 70
8444 01:15:08.240894 [Byte1]: 70
8445 01:15:08.245325
8446 01:15:08.245740 Set Vref, RX VrefLevel [Byte0]: 71
8447 01:15:08.248777 [Byte1]: 71
8448 01:15:08.253150
8449 01:15:08.253746 Set Vref, RX VrefLevel [Byte0]: 72
8450 01:15:08.256291 [Byte1]: 72
8451 01:15:08.260651
8452 01:15:08.261064 Set Vref, RX VrefLevel [Byte0]: 73
8453 01:15:08.263811 [Byte1]: 73
8454 01:15:08.268097
8455 01:15:08.268511 Set Vref, RX VrefLevel [Byte0]: 74
8456 01:15:08.271446 [Byte1]: 74
8457 01:15:08.275489
8458 01:15:08.275569 Set Vref, RX VrefLevel [Byte0]: 75
8459 01:15:08.278772 [Byte1]: 75
8460 01:15:08.283555
8461 01:15:08.283635 Set Vref, RX VrefLevel [Byte0]: 76
8462 01:15:08.286645 [Byte1]: 76
8463 01:15:08.290687
8464 01:15:08.290767 Set Vref, RX VrefLevel [Byte0]: 77
8465 01:15:08.294077 [Byte1]: 77
8466 01:15:08.298433
8467 01:15:08.298513 Final RX Vref Byte 0 = 57 to rank0
8468 01:15:08.301819 Final RX Vref Byte 1 = 54 to rank0
8469 01:15:08.305015 Final RX Vref Byte 0 = 57 to rank1
8470 01:15:08.308485 Final RX Vref Byte 1 = 54 to rank1==
8471 01:15:08.311560 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 01:15:08.318440 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8473 01:15:08.318521 ==
8474 01:15:08.318585 DQS Delay:
8475 01:15:08.321498 DQS0 = 0, DQS1 = 0
8476 01:15:08.321579 DQM Delay:
8477 01:15:08.321643 DQM0 = 128, DQM1 = 123
8478 01:15:08.324794 DQ Delay:
8479 01:15:08.328388 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =128
8480 01:15:08.331456 DQ4 =128, DQ5 =140, DQ6 =136, DQ7 =126
8481 01:15:08.334864 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8482 01:15:08.338270 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8483 01:15:08.338351
8484 01:15:08.338414
8485 01:15:08.338472
8486 01:15:08.341769 [DramC_TX_OE_Calibration] TA2
8487 01:15:08.344744 Original DQ_B0 (3 6) =30, OEN = 27
8488 01:15:08.348111 Original DQ_B1 (3 6) =30, OEN = 27
8489 01:15:08.351381 24, 0x0, End_B0=24 End_B1=24
8490 01:15:08.351462 25, 0x0, End_B0=25 End_B1=25
8491 01:15:08.354597 26, 0x0, End_B0=26 End_B1=26
8492 01:15:08.357826 27, 0x0, End_B0=27 End_B1=27
8493 01:15:08.361015 28, 0x0, End_B0=28 End_B1=28
8494 01:15:08.364293 29, 0x0, End_B0=29 End_B1=29
8495 01:15:08.364376 30, 0x0, End_B0=30 End_B1=30
8496 01:15:08.367825 31, 0x4545, End_B0=30 End_B1=30
8497 01:15:08.371249 Byte0 end_step=30 best_step=27
8498 01:15:08.374615 Byte1 end_step=30 best_step=27
8499 01:15:08.377602 Byte0 TX OE(2T, 0.5T) = (3, 3)
8500 01:15:08.380905 Byte1 TX OE(2T, 0.5T) = (3, 3)
8501 01:15:08.380986
8502 01:15:08.381050
8503 01:15:08.387610 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8504 01:15:08.391212 CH1 RK0: MR19=303, MR18=2525
8505 01:15:08.397689 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8506 01:15:08.397770
8507 01:15:08.400887 ----->DramcWriteLeveling(PI) begin...
8508 01:15:08.400969 ==
8509 01:15:08.404384 Dram Type= 6, Freq= 0, CH_1, rank 1
8510 01:15:08.407280 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8511 01:15:08.407361 ==
8512 01:15:08.410706 Write leveling (Byte 0): 21 => 21
8513 01:15:08.413882 Write leveling (Byte 1): 19 => 19
8514 01:15:08.417301 DramcWriteLeveling(PI) end<-----
8515 01:15:08.417382
8516 01:15:08.417445 ==
8517 01:15:08.420711 Dram Type= 6, Freq= 0, CH_1, rank 1
8518 01:15:08.423977 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8519 01:15:08.427314 ==
8520 01:15:08.427395 [Gating] SW mode calibration
8521 01:15:08.437166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8522 01:15:08.440241 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8523 01:15:08.443480 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8524 01:15:08.450266 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8525 01:15:08.453844 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8526 01:15:08.456700 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8527 01:15:08.463508 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8528 01:15:08.466844 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8529 01:15:08.470082 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8530 01:15:08.476894 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8531 01:15:08.479991 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8532 01:15:08.483437 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8533 01:15:08.489774 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8534 01:15:08.493441 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8535 01:15:08.496474 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8536 01:15:08.503166 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8537 01:15:08.506492 0 13 24 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8538 01:15:08.509819 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8539 01:15:08.516131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8540 01:15:08.519692 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8541 01:15:08.522752 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8542 01:15:08.529539 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8543 01:15:08.532776 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8544 01:15:08.536019 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8545 01:15:08.542624 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8546 01:15:08.546174 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8547 01:15:08.549206 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8548 01:15:08.556242 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8549 01:15:08.559555 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8550 01:15:08.562555 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8551 01:15:08.569096 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8552 01:15:08.572516 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8553 01:15:08.576212 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8554 01:15:08.582337 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8555 01:15:08.585684 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8556 01:15:08.588833 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 01:15:08.595532 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 01:15:08.598686 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 01:15:08.602005 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 01:15:08.608788 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 01:15:08.612160 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8562 01:15:08.615370 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8563 01:15:08.621918 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8564 01:15:08.622020 Total UI for P1: 0, mck2ui 16
8565 01:15:08.628841 best dqsien dly found for B0: ( 1, 0, 26)
8566 01:15:08.632274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 01:15:08.635222 Total UI for P1: 0, mck2ui 16
8568 01:15:08.638417 best dqsien dly found for B1: ( 1, 1, 0)
8569 01:15:08.642210 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8570 01:15:08.645270 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8571 01:15:08.645340
8572 01:15:08.648873 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8573 01:15:08.651674 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8574 01:15:08.655243 [Gating] SW calibration Done
8575 01:15:08.655332 ==
8576 01:15:08.658335 Dram Type= 6, Freq= 0, CH_1, rank 1
8577 01:15:08.661671 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8578 01:15:08.661740 ==
8579 01:15:08.665172 RX Vref Scan: 0
8580 01:15:08.665253
8581 01:15:08.668328 RX Vref 0 -> 0, step: 1
8582 01:15:08.668409
8583 01:15:08.668473 RX Delay 0 -> 252, step: 8
8584 01:15:08.674986 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8585 01:15:08.678545 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8586 01:15:08.681707 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8587 01:15:08.684774 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8588 01:15:08.688356 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8589 01:15:08.694928 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8590 01:15:08.698073 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8591 01:15:08.701437 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8592 01:15:08.704838 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8593 01:15:08.708366 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8594 01:15:08.714631 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8595 01:15:08.717837 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8596 01:15:08.721215 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8597 01:15:08.724561 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8598 01:15:08.731140 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8599 01:15:08.734324 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8600 01:15:08.734405 ==
8601 01:15:08.737665 Dram Type= 6, Freq= 0, CH_1, rank 1
8602 01:15:08.741236 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8603 01:15:08.741317 ==
8604 01:15:08.744402 DQS Delay:
8605 01:15:08.744483 DQS0 = 0, DQS1 = 0
8606 01:15:08.744546 DQM Delay:
8607 01:15:08.747625 DQM0 = 131, DQM1 = 124
8608 01:15:08.747706 DQ Delay:
8609 01:15:08.751187 DQ0 =135, DQ1 =123, DQ2 =115, DQ3 =131
8610 01:15:08.754367 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8611 01:15:08.757406 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8612 01:15:08.764075 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8613 01:15:08.764156
8614 01:15:08.764219
8615 01:15:08.764298 ==
8616 01:15:08.767905 Dram Type= 6, Freq= 0, CH_1, rank 1
8617 01:15:08.770649 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8618 01:15:08.770725 ==
8619 01:15:08.770788
8620 01:15:08.770847
8621 01:15:08.774211 TX Vref Scan disable
8622 01:15:08.774280 == TX Byte 0 ==
8623 01:15:08.780658 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8624 01:15:08.784057 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8625 01:15:08.784153 == TX Byte 1 ==
8626 01:15:08.790609 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8627 01:15:08.793829 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8628 01:15:08.793927 ==
8629 01:15:08.797120 Dram Type= 6, Freq= 0, CH_1, rank 1
8630 01:15:08.800349 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8631 01:15:08.800422 ==
8632 01:15:08.815463
8633 01:15:08.818574 TX Vref early break, caculate TX vref
8634 01:15:08.821795 TX Vref=16, minBit 0, minWin=22, winSum=381
8635 01:15:08.825365 TX Vref=18, minBit 1, minWin=23, winSum=390
8636 01:15:08.828482 TX Vref=20, minBit 0, minWin=24, winSum=400
8637 01:15:08.831639 TX Vref=22, minBit 2, minWin=24, winSum=411
8638 01:15:08.834951 TX Vref=24, minBit 2, minWin=24, winSum=413
8639 01:15:08.841687 TX Vref=26, minBit 3, minWin=24, winSum=419
8640 01:15:08.845021 TX Vref=28, minBit 0, minWin=25, winSum=419
8641 01:15:08.848463 TX Vref=30, minBit 2, minWin=25, winSum=422
8642 01:15:08.851821 TX Vref=32, minBit 0, minWin=24, winSum=417
8643 01:15:08.854681 TX Vref=34, minBit 0, minWin=23, winSum=406
8644 01:15:08.861312 TX Vref=36, minBit 0, minWin=23, winSum=397
8645 01:15:08.864574 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 30
8646 01:15:08.864656
8647 01:15:08.867815 Final TX Range 0 Vref 30
8648 01:15:08.867897
8649 01:15:08.867961 ==
8650 01:15:08.871275 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 01:15:08.874462 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 01:15:08.877821 ==
8653 01:15:08.877901
8654 01:15:08.877964
8655 01:15:08.878031 TX Vref Scan disable
8656 01:15:08.884443 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8657 01:15:08.884525 == TX Byte 0 ==
8658 01:15:08.887734 u2DelayCellOfst[0]=18 cells (5 PI)
8659 01:15:08.891086 u2DelayCellOfst[1]=10 cells (3 PI)
8660 01:15:08.894339 u2DelayCellOfst[2]=0 cells (0 PI)
8661 01:15:08.897609 u2DelayCellOfst[3]=10 cells (3 PI)
8662 01:15:08.901048 u2DelayCellOfst[4]=10 cells (3 PI)
8663 01:15:08.904369 u2DelayCellOfst[5]=14 cells (4 PI)
8664 01:15:08.907757 u2DelayCellOfst[6]=14 cells (4 PI)
8665 01:15:08.910823 u2DelayCellOfst[7]=7 cells (2 PI)
8666 01:15:08.914324 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8667 01:15:08.917402 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8668 01:15:08.920541 == TX Byte 1 ==
8669 01:15:08.924088 u2DelayCellOfst[8]=0 cells (0 PI)
8670 01:15:08.927538 u2DelayCellOfst[9]=7 cells (2 PI)
8671 01:15:08.930554 u2DelayCellOfst[10]=7 cells (2 PI)
8672 01:15:08.934081 u2DelayCellOfst[11]=3 cells (1 PI)
8673 01:15:08.937299 u2DelayCellOfst[12]=14 cells (4 PI)
8674 01:15:08.940617 u2DelayCellOfst[13]=18 cells (5 PI)
8675 01:15:08.943947 u2DelayCellOfst[14]=18 cells (5 PI)
8676 01:15:08.944028 u2DelayCellOfst[15]=18 cells (5 PI)
8677 01:15:08.951131 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8678 01:15:08.954167 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8679 01:15:08.957107 DramC Write-DBI on
8680 01:15:08.957187 ==
8681 01:15:08.960614 Dram Type= 6, Freq= 0, CH_1, rank 1
8682 01:15:08.963716 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8683 01:15:08.963797 ==
8684 01:15:08.963861
8685 01:15:08.963920
8686 01:15:08.966942 TX Vref Scan disable
8687 01:15:08.967023 == TX Byte 0 ==
8688 01:15:08.973699 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8689 01:15:08.973780 == TX Byte 1 ==
8690 01:15:08.976838 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8691 01:15:08.979916 DramC Write-DBI off
8692 01:15:08.979996
8693 01:15:08.980060 [DATLAT]
8694 01:15:08.983345 Freq=1600, CH1 RK1
8695 01:15:08.983426
8696 01:15:08.983490 DATLAT Default: 0xe
8697 01:15:08.986674 0, 0xFFFF, sum = 0
8698 01:15:08.989836 1, 0xFFFF, sum = 0
8699 01:15:08.989918 2, 0xFFFF, sum = 0
8700 01:15:08.993432 3, 0xFFFF, sum = 0
8701 01:15:08.993515 4, 0xFFFF, sum = 0
8702 01:15:08.996625 5, 0xFFFF, sum = 0
8703 01:15:08.996707 6, 0xFFFF, sum = 0
8704 01:15:08.999844 7, 0xFFFF, sum = 0
8705 01:15:08.999927 8, 0xFFFF, sum = 0
8706 01:15:09.003150 9, 0xFFFF, sum = 0
8707 01:15:09.003233 10, 0xFFFF, sum = 0
8708 01:15:09.006487 11, 0xFFFF, sum = 0
8709 01:15:09.006569 12, 0xF7F, sum = 0
8710 01:15:09.009708 13, 0x0, sum = 1
8711 01:15:09.009790 14, 0x0, sum = 2
8712 01:15:09.013028 15, 0x0, sum = 3
8713 01:15:09.013110 16, 0x0, sum = 4
8714 01:15:09.016247 best_step = 14
8715 01:15:09.016327
8716 01:15:09.016390 ==
8717 01:15:09.019770 Dram Type= 6, Freq= 0, CH_1, rank 1
8718 01:15:09.022933 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8719 01:15:09.023014 ==
8720 01:15:09.026067 RX Vref Scan: 0
8721 01:15:09.026147
8722 01:15:09.026211 RX Vref 0 -> 0, step: 1
8723 01:15:09.026270
8724 01:15:09.029447 RX Delay 3 -> 252, step: 4
8725 01:15:09.035968 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8726 01:15:09.039184 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8727 01:15:09.042488 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8728 01:15:09.045891 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8729 01:15:09.049371 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8730 01:15:09.055879 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8731 01:15:09.059131 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8732 01:15:09.062319 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8733 01:15:09.065563 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8734 01:15:09.068963 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8735 01:15:09.075464 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8736 01:15:09.078836 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8737 01:15:09.082226 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8738 01:15:09.085227 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8739 01:15:09.092215 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8740 01:15:09.095148 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8741 01:15:09.095229 ==
8742 01:15:09.098426 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 01:15:09.101898 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8744 01:15:09.101979 ==
8745 01:15:09.102055 DQS Delay:
8746 01:15:09.105349 DQS0 = 0, DQS1 = 0
8747 01:15:09.105429 DQM Delay:
8748 01:15:09.108397 DQM0 = 127, DQM1 = 122
8749 01:15:09.108478 DQ Delay:
8750 01:15:09.111955 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8751 01:15:09.115067 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =124
8752 01:15:09.118196 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8753 01:15:09.124805 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8754 01:15:09.124886
8755 01:15:09.124949
8756 01:15:09.125008
8757 01:15:09.128473 [DramC_TX_OE_Calibration] TA2
8758 01:15:09.128554 Original DQ_B0 (3 6) =30, OEN = 27
8759 01:15:09.131330 Original DQ_B1 (3 6) =30, OEN = 27
8760 01:15:09.135234 24, 0x0, End_B0=24 End_B1=24
8761 01:15:09.138077 25, 0x0, End_B0=25 End_B1=25
8762 01:15:09.141243 26, 0x0, End_B0=26 End_B1=26
8763 01:15:09.144614 27, 0x0, End_B0=27 End_B1=27
8764 01:15:09.144696 28, 0x0, End_B0=28 End_B1=28
8765 01:15:09.148271 29, 0x0, End_B0=29 End_B1=29
8766 01:15:09.151643 30, 0x0, End_B0=30 End_B1=30
8767 01:15:09.154502 31, 0x4141, End_B0=30 End_B1=30
8768 01:15:09.158054 Byte0 end_step=30 best_step=27
8769 01:15:09.158150 Byte1 end_step=30 best_step=27
8770 01:15:09.161265 Byte0 TX OE(2T, 0.5T) = (3, 3)
8771 01:15:09.164519 Byte1 TX OE(2T, 0.5T) = (3, 3)
8772 01:15:09.164599
8773 01:15:09.164663
8774 01:15:09.174560 [DQSOSCAuto] RK1, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
8775 01:15:09.174642 CH1 RK1: MR19=303, MR18=1919
8776 01:15:09.181202 CH1_RK1: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
8777 01:15:09.184738 [RxdqsGatingPostProcess] freq 1600
8778 01:15:09.191053 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8779 01:15:09.194423 Pre-setting of DQS Precalculation
8780 01:15:09.197836 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8781 01:15:09.207586 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8782 01:15:09.213942 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8783 01:15:09.214028
8784 01:15:09.214093
8785 01:15:09.217279 [Calibration Summary] 3200 Mbps
8786 01:15:09.217360 CH 0, Rank 0
8787 01:15:09.220772 SW Impedance : PASS
8788 01:15:09.220852 DUTY Scan : NO K
8789 01:15:09.223886 ZQ Calibration : PASS
8790 01:15:09.227134 Jitter Meter : NO K
8791 01:15:09.227215 CBT Training : PASS
8792 01:15:09.230692 Write leveling : PASS
8793 01:15:09.234008 RX DQS gating : PASS
8794 01:15:09.234123 RX DQ/DQS(RDDQC) : PASS
8795 01:15:09.237202 TX DQ/DQS : PASS
8796 01:15:09.240400 RX DATLAT : PASS
8797 01:15:09.240481 RX DQ/DQS(Engine): PASS
8798 01:15:09.243816 TX OE : PASS
8799 01:15:09.243897 All Pass.
8800 01:15:09.243960
8801 01:15:09.247162 CH 0, Rank 1
8802 01:15:09.247243 SW Impedance : PASS
8803 01:15:09.250206 DUTY Scan : NO K
8804 01:15:09.253769 ZQ Calibration : PASS
8805 01:15:09.253850 Jitter Meter : NO K
8806 01:15:09.256860 CBT Training : PASS
8807 01:15:09.259955 Write leveling : PASS
8808 01:15:09.260035 RX DQS gating : PASS
8809 01:15:09.263618 RX DQ/DQS(RDDQC) : PASS
8810 01:15:09.266725 TX DQ/DQS : PASS
8811 01:15:09.266806 RX DATLAT : PASS
8812 01:15:09.269902 RX DQ/DQS(Engine): PASS
8813 01:15:09.269982 TX OE : PASS
8814 01:15:09.273624 All Pass.
8815 01:15:09.273704
8816 01:15:09.273767 CH 1, Rank 0
8817 01:15:09.276626 SW Impedance : PASS
8818 01:15:09.276705 DUTY Scan : NO K
8819 01:15:09.280004 ZQ Calibration : PASS
8820 01:15:09.283386 Jitter Meter : NO K
8821 01:15:09.283467 CBT Training : PASS
8822 01:15:09.286788 Write leveling : PASS
8823 01:15:09.290044 RX DQS gating : PASS
8824 01:15:09.290140 RX DQ/DQS(RDDQC) : PASS
8825 01:15:09.293607 TX DQ/DQS : PASS
8826 01:15:09.296758 RX DATLAT : PASS
8827 01:15:09.296838 RX DQ/DQS(Engine): PASS
8828 01:15:09.300109 TX OE : PASS
8829 01:15:09.300190 All Pass.
8830 01:15:09.300253
8831 01:15:09.303370 CH 1, Rank 1
8832 01:15:09.303454 SW Impedance : PASS
8833 01:15:09.306715 DUTY Scan : NO K
8834 01:15:09.309776 ZQ Calibration : PASS
8835 01:15:09.309856 Jitter Meter : NO K
8836 01:15:09.312923 CBT Training : PASS
8837 01:15:09.316104 Write leveling : PASS
8838 01:15:09.316185 RX DQS gating : PASS
8839 01:15:09.319605 RX DQ/DQS(RDDQC) : PASS
8840 01:15:09.322839 TX DQ/DQS : PASS
8841 01:15:09.322920 RX DATLAT : PASS
8842 01:15:09.326284 RX DQ/DQS(Engine): PASS
8843 01:15:09.329377 TX OE : PASS
8844 01:15:09.329494 All Pass.
8845 01:15:09.329562
8846 01:15:09.329622 DramC Write-DBI on
8847 01:15:09.332742 PER_BANK_REFRESH: Hybrid Mode
8848 01:15:09.336130 TX_TRACKING: ON
8849 01:15:09.342519 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8850 01:15:09.352736 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8851 01:15:09.359105 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8852 01:15:09.362337 [FAST_K] Save calibration result to emmc
8853 01:15:09.365608 sync common calibartion params.
8854 01:15:09.369366 sync cbt_mode0:0, 1:0
8855 01:15:09.369446 dram_init: ddr_geometry: 0
8856 01:15:09.372475 dram_init: ddr_geometry: 0
8857 01:15:09.375585 dram_init: ddr_geometry: 0
8858 01:15:09.375665 0:dram_rank_size:80000000
8859 01:15:09.378999 1:dram_rank_size:80000000
8860 01:15:09.385801 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8861 01:15:09.385883 DFS_SHUFFLE_HW_MODE: ON
8862 01:15:09.392287 dramc_set_vcore_voltage set vcore to 725000
8863 01:15:09.392368 Read voltage for 1600, 0
8864 01:15:09.395835 Vio18 = 0
8865 01:15:09.395916 Vcore = 725000
8866 01:15:09.395979 Vdram = 0
8867 01:15:09.398860 Vddq = 0
8868 01:15:09.398939 Vmddr = 0
8869 01:15:09.402026 switch to 3200 Mbps bootup
8870 01:15:09.402108 [DramcRunTimeConfig]
8871 01:15:09.402172 PHYPLL
8872 01:15:09.405327 DPM_CONTROL_AFTERK: ON
8873 01:15:09.408637 PER_BANK_REFRESH: ON
8874 01:15:09.408718 REFRESH_OVERHEAD_REDUCTION: ON
8875 01:15:09.412085 CMD_PICG_NEW_MODE: OFF
8876 01:15:09.415512 XRTWTW_NEW_MODE: ON
8877 01:15:09.415592 XRTRTR_NEW_MODE: ON
8878 01:15:09.418707 TX_TRACKING: ON
8879 01:15:09.418788 RDSEL_TRACKING: OFF
8880 01:15:09.421915 DQS Precalculation for DVFS: ON
8881 01:15:09.422013 RX_TRACKING: OFF
8882 01:15:09.425351 HW_GATING DBG: ON
8883 01:15:09.428500 ZQCS_ENABLE_LP4: ON
8884 01:15:09.428581 RX_PICG_NEW_MODE: ON
8885 01:15:09.431917 TX_PICG_NEW_MODE: ON
8886 01:15:09.431997 ENABLE_RX_DCM_DPHY: ON
8887 01:15:09.435309 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8888 01:15:09.438648 DUMMY_READ_FOR_TRACKING: OFF
8889 01:15:09.441497 !!! SPM_CONTROL_AFTERK: OFF
8890 01:15:09.444905 !!! SPM could not control APHY
8891 01:15:09.444986 IMPEDANCE_TRACKING: ON
8892 01:15:09.448311 TEMP_SENSOR: ON
8893 01:15:09.448391 HW_SAVE_FOR_SR: OFF
8894 01:15:09.451617 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8895 01:15:09.455035 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8896 01:15:09.457947 Read ODT Tracking: ON
8897 01:15:09.461378 Refresh Rate DeBounce: ON
8898 01:15:09.461459 DFS_NO_QUEUE_FLUSH: ON
8899 01:15:09.464859 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8900 01:15:09.468059 ENABLE_DFS_RUNTIME_MRW: OFF
8901 01:15:09.471581 DDR_RESERVE_NEW_MODE: ON
8902 01:15:09.471664 MR_CBT_SWITCH_FREQ: ON
8903 01:15:09.474548 =========================
8904 01:15:09.492872 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8905 01:15:09.496207 dram_init: ddr_geometry: 0
8906 01:15:09.514363 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8907 01:15:09.517701 dram_init: dram init end (result: 0)
8908 01:15:09.524114 DRAM-K: Full calibration passed in 23447 msecs
8909 01:15:09.527348 MRC: failed to locate region type 0.
8910 01:15:09.527429 DRAM rank0 size:0x80000000,
8911 01:15:09.530715 DRAM rank1 size=0x80000000
8912 01:15:09.540806 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8913 01:15:09.547348 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8914 01:15:09.553984 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8915 01:15:09.560483 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8916 01:15:09.563715 DRAM rank0 size:0x80000000,
8917 01:15:09.567661 DRAM rank1 size=0x80000000
8918 01:15:09.567742 CBMEM:
8919 01:15:09.570426 IMD: root @ 0xfffff000 254 entries.
8920 01:15:09.573805 IMD: root @ 0xffffec00 62 entries.
8921 01:15:09.576971 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8922 01:15:09.580590 WARNING: RO_VPD is uninitialized or empty.
8923 01:15:09.586915 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8924 01:15:09.593979 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8925 01:15:09.606605 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8926 01:15:09.618273 BS: romstage times (exec / console): total (unknown) / 22984 ms
8927 01:15:09.618356
8928 01:15:09.618418
8929 01:15:09.628289 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8930 01:15:09.631256 ARM64: Exception handlers installed.
8931 01:15:09.634443 ARM64: Testing exception
8932 01:15:09.637939 ARM64: Done test exception
8933 01:15:09.638020 Enumerating buses...
8934 01:15:09.641201 Show all devs... Before device enumeration.
8935 01:15:09.644532 Root Device: enabled 1
8936 01:15:09.647985 CPU_CLUSTER: 0: enabled 1
8937 01:15:09.648067 CPU: 00: enabled 1
8938 01:15:09.651105 Compare with tree...
8939 01:15:09.651185 Root Device: enabled 1
8940 01:15:09.654322 CPU_CLUSTER: 0: enabled 1
8941 01:15:09.657816 CPU: 00: enabled 1
8942 01:15:09.657897 Root Device scanning...
8943 01:15:09.660798 scan_static_bus for Root Device
8944 01:15:09.664329 CPU_CLUSTER: 0 enabled
8945 01:15:09.667464 scan_static_bus for Root Device done
8946 01:15:09.671078 scan_bus: bus Root Device finished in 8 msecs
8947 01:15:09.671159 done
8948 01:15:09.677771 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8949 01:15:09.680744 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8950 01:15:09.687387 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8951 01:15:09.690920 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8952 01:15:09.694130 Allocating resources...
8953 01:15:09.697472 Reading resources...
8954 01:15:09.700891 Root Device read_resources bus 0 link: 0
8955 01:15:09.700972 DRAM rank0 size:0x80000000,
8956 01:15:09.704108 DRAM rank1 size=0x80000000
8957 01:15:09.707415 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8958 01:15:09.710757 CPU: 00 missing read_resources
8959 01:15:09.717128 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8960 01:15:09.720791 Root Device read_resources bus 0 link: 0 done
8961 01:15:09.720872 Done reading resources.
8962 01:15:09.726943 Show resources in subtree (Root Device)...After reading.
8963 01:15:09.730434 Root Device child on link 0 CPU_CLUSTER: 0
8964 01:15:09.733765 CPU_CLUSTER: 0 child on link 0 CPU: 00
8965 01:15:09.743384 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8966 01:15:09.743465 CPU: 00
8967 01:15:09.746700 Root Device assign_resources, bus 0 link: 0
8968 01:15:09.750264 CPU_CLUSTER: 0 missing set_resources
8969 01:15:09.756629 Root Device assign_resources, bus 0 link: 0 done
8970 01:15:09.756714 Done setting resources.
8971 01:15:09.763552 Show resources in subtree (Root Device)...After assigning values.
8972 01:15:09.766540 Root Device child on link 0 CPU_CLUSTER: 0
8973 01:15:09.769828 CPU_CLUSTER: 0 child on link 0 CPU: 00
8974 01:15:09.779569 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8975 01:15:09.779651 CPU: 00
8976 01:15:09.783018 Done allocating resources.
8977 01:15:09.789458 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8978 01:15:09.789539 Enabling resources...
8979 01:15:09.789602 done.
8980 01:15:09.796631 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8981 01:15:09.799794 Initializing devices...
8982 01:15:09.799888 Root Device init
8983 01:15:09.802856 init hardware done!
8984 01:15:09.802936 0x00000018: ctrlr->caps
8985 01:15:09.806199 52.000 MHz: ctrlr->f_max
8986 01:15:09.809461 0.400 MHz: ctrlr->f_min
8987 01:15:09.809544 0x40ff8080: ctrlr->voltages
8988 01:15:09.812673 sclk: 390625
8989 01:15:09.812771 Bus Width = 1
8990 01:15:09.812867 sclk: 390625
8991 01:15:09.815849 Bus Width = 1
8992 01:15:09.819351 Early init status = 3
8993 01:15:09.822701 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8994 01:15:09.825938 in-header: 03 fc 00 00 01 00 00 00
8995 01:15:09.829453 in-data: 00
8996 01:15:09.832308 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8997 01:15:09.836954 in-header: 03 fd 00 00 00 00 00 00
8998 01:15:09.840052 in-data:
8999 01:15:09.843065 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9000 01:15:09.846915 in-header: 03 fc 00 00 01 00 00 00
9001 01:15:09.850224 in-data: 00
9002 01:15:09.853074 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9003 01:15:09.858243 in-header: 03 fd 00 00 00 00 00 00
9004 01:15:09.861767 in-data:
9005 01:15:09.864850 [SSUSB] Setting up USB HOST controller...
9006 01:15:09.868039 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9007 01:15:09.871692 [SSUSB] phy power-on done.
9008 01:15:09.874793 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9009 01:15:09.881276 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9010 01:15:09.884539 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9011 01:15:09.891005 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9012 01:15:09.897940 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9013 01:15:09.904710 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9014 01:15:09.910801 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9015 01:15:09.917368 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9016 01:15:09.920724 SPM: binary array size = 0x9dc
9017 01:15:09.923993 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9018 01:15:09.930649 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9019 01:15:09.937502 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9020 01:15:09.943842 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9021 01:15:09.947252 configure_display: Starting display init
9022 01:15:09.981248 anx7625_power_on_init: Init interface.
9023 01:15:09.984708 anx7625_disable_pd_protocol: Disabled PD feature.
9024 01:15:09.987813 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9025 01:15:10.015819 anx7625_start_dp_work: Secure OCM version=00
9026 01:15:10.019292 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9027 01:15:10.033720 sp_tx_get_edid_block: EDID Block = 1
9028 01:15:10.136619 Extracted contents:
9029 01:15:10.139694 header: 00 ff ff ff ff ff ff 00
9030 01:15:10.142960 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9031 01:15:10.146694 version: 01 04
9032 01:15:10.149908 basic params: 95 1f 11 78 0a
9033 01:15:10.152987 chroma info: 76 90 94 55 54 90 27 21 50 54
9034 01:15:10.156023 established: 00 00 00
9035 01:15:10.162757 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9036 01:15:10.169625 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9037 01:15:10.172771 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9038 01:15:10.179202 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9039 01:15:10.185955 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9040 01:15:10.189396 extensions: 00
9041 01:15:10.189477 checksum: fb
9042 01:15:10.189541
9043 01:15:10.195853 Manufacturer: IVO Model 57d Serial Number 0
9044 01:15:10.195934 Made week 0 of 2020
9045 01:15:10.199066 EDID version: 1.4
9046 01:15:10.199147 Digital display
9047 01:15:10.202612 6 bits per primary color channel
9048 01:15:10.202694 DisplayPort interface
9049 01:15:10.205612 Maximum image size: 31 cm x 17 cm
9050 01:15:10.208885 Gamma: 220%
9051 01:15:10.208965 Check DPMS levels
9052 01:15:10.215680 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9053 01:15:10.218932 First detailed timing is preferred timing
9054 01:15:10.219017 Established timings supported:
9055 01:15:10.222261 Standard timings supported:
9056 01:15:10.225727 Detailed timings
9057 01:15:10.228778 Hex of detail: 383680a07038204018303c0035ae10000019
9058 01:15:10.235482 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9059 01:15:10.238605 0780 0798 07c8 0820 hborder 0
9060 01:15:10.241907 0438 043b 0447 0458 vborder 0
9061 01:15:10.245211 -hsync -vsync
9062 01:15:10.245295 Did detailed timing
9063 01:15:10.251757 Hex of detail: 000000000000000000000000000000000000
9064 01:15:10.255193 Manufacturer-specified data, tag 0
9065 01:15:10.258447 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9066 01:15:10.261891 ASCII string: InfoVision
9067 01:15:10.265099 Hex of detail: 000000fe00523134304e574635205248200a
9068 01:15:10.268889 ASCII string: R140NWF5 RH
9069 01:15:10.268969 Checksum
9070 01:15:10.271796 Checksum: 0xfb (valid)
9071 01:15:10.274973 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9072 01:15:10.278246 DSI data_rate: 832800000 bps
9073 01:15:10.285059 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9074 01:15:10.288212 anx7625_parse_edid: pixelclock(138800).
9075 01:15:10.291846 hactive(1920), hsync(48), hfp(24), hbp(88)
9076 01:15:10.294755 vactive(1080), vsync(12), vfp(3), vbp(17)
9077 01:15:10.298439 anx7625_dsi_config: config dsi.
9078 01:15:10.305217 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9079 01:15:10.318717 anx7625_dsi_config: success to config DSI
9080 01:15:10.321893 anx7625_dp_start: MIPI phy setup OK.
9081 01:15:10.325144 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9082 01:15:10.328332 mtk_ddp_mode_set invalid vrefresh 60
9083 01:15:10.331680 main_disp_path_setup
9084 01:15:10.331760 ovl_layer_smi_id_en
9085 01:15:10.334883 ovl_layer_smi_id_en
9086 01:15:10.334963 ccorr_config
9087 01:15:10.335026 aal_config
9088 01:15:10.338277 gamma_config
9089 01:15:10.338358 postmask_config
9090 01:15:10.341320 dither_config
9091 01:15:10.344872 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9092 01:15:10.351376 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9093 01:15:10.354841 Root Device init finished in 551 msecs
9094 01:15:10.358089 CPU_CLUSTER: 0 init
9095 01:15:10.364553 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9096 01:15:10.371216 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9097 01:15:10.371297 APU_MBOX 0x190000b0 = 0x10001
9098 01:15:10.374668 APU_MBOX 0x190001b0 = 0x10001
9099 01:15:10.378018 APU_MBOX 0x190005b0 = 0x10001
9100 01:15:10.380991 APU_MBOX 0x190006b0 = 0x10001
9101 01:15:10.387576 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9102 01:15:10.397212 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9103 01:15:10.409770 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9104 01:15:10.416195 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9105 01:15:10.428383 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9106 01:15:10.437068 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9107 01:15:10.440707 CPU_CLUSTER: 0 init finished in 81 msecs
9108 01:15:10.443928 Devices initialized
9109 01:15:10.447101 Show all devs... After init.
9110 01:15:10.447181 Root Device: enabled 1
9111 01:15:10.450455 CPU_CLUSTER: 0: enabled 1
9112 01:15:10.453580 CPU: 00: enabled 1
9113 01:15:10.457043 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9114 01:15:10.460335 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9115 01:15:10.463563 ELOG: NV offset 0x57f000 size 0x1000
9116 01:15:10.470211 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9117 01:15:10.476802 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9118 01:15:10.480084 ELOG: Event(17) added with size 13 at 2024-04-23 01:15:10 UTC
9119 01:15:10.486956 out: cmd=0x121: 03 db 21 01 00 00 00 00
9120 01:15:10.490056 in-header: 03 c8 00 00 2c 00 00 00
9121 01:15:10.503124 in-data: 9a 65 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9122 01:15:10.506455 ELOG: Event(A1) added with size 10 at 2024-04-23 01:15:10 UTC
9123 01:15:10.513302 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9124 01:15:10.520312 ELOG: Event(A0) added with size 9 at 2024-04-23 01:15:10 UTC
9125 01:15:10.523037 elog_add_boot_reason: Logged dev mode boot
9126 01:15:10.529609 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9127 01:15:10.529690 Finalize devices...
9128 01:15:10.533045 Devices finalized
9129 01:15:10.536169 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9130 01:15:10.539429 Writing coreboot table at 0xffe64000
9131 01:15:10.546330 0. 000000000010a000-0000000000113fff: RAMSTAGE
9132 01:15:10.549247 1. 0000000040000000-00000000400fffff: RAM
9133 01:15:10.552695 2. 0000000040100000-000000004032afff: RAMSTAGE
9134 01:15:10.555820 3. 000000004032b000-00000000545fffff: RAM
9135 01:15:10.559186 4. 0000000054600000-000000005465ffff: BL31
9136 01:15:10.565868 5. 0000000054660000-00000000ffe63fff: RAM
9137 01:15:10.569173 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9138 01:15:10.572471 7. 0000000100000000-000000013fffffff: RAM
9139 01:15:10.575773 Passing 5 GPIOs to payload:
9140 01:15:10.579004 NAME | PORT | POLARITY | VALUE
9141 01:15:10.585828 EC in RW | 0x000000aa | low | undefined
9142 01:15:10.588874 EC interrupt | 0x00000005 | low | undefined
9143 01:15:10.595510 TPM interrupt | 0x000000ab | high | undefined
9144 01:15:10.598782 SD card detect | 0x00000011 | high | undefined
9145 01:15:10.602227 speaker enable | 0x00000093 | high | undefined
9146 01:15:10.608762 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9147 01:15:10.612089 in-header: 03 f8 00 00 02 00 00 00
9148 01:15:10.612170 in-data: 03 00
9149 01:15:10.615469 ADC[4]: Raw value=668222 ID=5
9150 01:15:10.618669 ADC[3]: Raw value=212917 ID=1
9151 01:15:10.618750 RAM Code: 0x51
9152 01:15:10.622125 ADC[6]: Raw value=74410 ID=0
9153 01:15:10.625205 ADC[5]: Raw value=211812 ID=1
9154 01:15:10.625285 SKU Code: 0x1
9155 01:15:10.631833 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd9a
9156 01:15:10.635575 coreboot table: 964 bytes.
9157 01:15:10.638348 IMD ROOT 0. 0xfffff000 0x00001000
9158 01:15:10.641529 IMD SMALL 1. 0xffffe000 0x00001000
9159 01:15:10.644805 RO MCACHE 2. 0xffffc000 0x00001104
9160 01:15:10.648131 CONSOLE 3. 0xfff7c000 0x00080000
9161 01:15:10.651560 FMAP 4. 0xfff7b000 0x00000452
9162 01:15:10.651641 TIME STAMP 5. 0xfff7a000 0x00000910
9163 01:15:10.655456 VBOOT WORK 6. 0xfff66000 0x00014000
9164 01:15:10.658287 RAMOOPS 7. 0xffe66000 0x00100000
9165 01:15:10.664515 COREBOOT 8. 0xffe64000 0x00002000
9166 01:15:10.664597 IMD small region:
9167 01:15:10.667985 IMD ROOT 0. 0xffffec00 0x00000400
9168 01:15:10.671406 VPD 1. 0xffffeb80 0x0000006c
9169 01:15:10.674871 MMC STATUS 2. 0xffffeb60 0x00000004
9170 01:15:10.681152 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9171 01:15:10.681233 Probing TPM: done!
9172 01:15:10.687816 Connected to device vid:did:rid of 1ae0:0028:00
9173 01:15:10.694710 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9174 01:15:10.697847 Initialized TPM device CR50 revision 0
9175 01:15:10.701909 Checking cr50 for pending updates
9176 01:15:10.707445 Reading cr50 TPM mode
9177 01:15:10.715931 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9178 01:15:10.722563 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9179 01:15:10.762557 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9180 01:15:10.766264 Checking segment from ROM address 0x40100000
9181 01:15:10.769432 Checking segment from ROM address 0x4010001c
9182 01:15:10.776067 Loading segment from ROM address 0x40100000
9183 01:15:10.776149 code (compression=0)
9184 01:15:10.785972 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9185 01:15:10.792716 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9186 01:15:10.792797 it's not compressed!
9187 01:15:10.799316 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9188 01:15:10.802630 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9189 01:15:10.823155 Loading segment from ROM address 0x4010001c
9190 01:15:10.823237 Entry Point 0x80000000
9191 01:15:10.826161 Loaded segments
9192 01:15:10.829737 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9193 01:15:10.836605 Jumping to boot code at 0x80000000(0xffe64000)
9194 01:15:10.842702 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9195 01:15:10.849546 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9196 01:15:10.857667 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9197 01:15:10.861087 Checking segment from ROM address 0x40100000
9198 01:15:10.864470 Checking segment from ROM address 0x4010001c
9199 01:15:10.870817 Loading segment from ROM address 0x40100000
9200 01:15:10.870898 code (compression=1)
9201 01:15:10.877473 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9202 01:15:10.887505 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9203 01:15:10.887586 using LZMA
9204 01:15:10.895884 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9205 01:15:10.902764 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9206 01:15:10.906214 Loading segment from ROM address 0x4010001c
9207 01:15:10.906295 Entry Point 0x54601000
9208 01:15:10.909678 Loaded segments
9209 01:15:10.912440 NOTICE: MT8192 bl31_setup
9210 01:15:10.919622 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9211 01:15:10.922726 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9212 01:15:10.926608 WARNING: region 0:
9213 01:15:10.929437 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9214 01:15:10.929519 WARNING: region 1:
9215 01:15:10.936082 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9216 01:15:10.939596 WARNING: region 2:
9217 01:15:10.942607 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9218 01:15:10.945942 WARNING: region 3:
9219 01:15:10.949307 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9220 01:15:10.952699 WARNING: region 4:
9221 01:15:10.959317 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9222 01:15:10.959400 WARNING: region 5:
9223 01:15:10.962651 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9224 01:15:10.966257 WARNING: region 6:
9225 01:15:10.969302 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9226 01:15:10.972576 WARNING: region 7:
9227 01:15:10.975816 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9228 01:15:10.982677 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9229 01:15:10.986176 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9230 01:15:10.989413 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9231 01:15:10.995968 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9232 01:15:10.999587 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9233 01:15:11.002810 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9234 01:15:11.009353 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9235 01:15:11.012776 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9236 01:15:11.019228 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9237 01:15:11.022600 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9238 01:15:11.025979 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9239 01:15:11.032663 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9240 01:15:11.036304 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9241 01:15:11.039200 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9242 01:15:11.045844 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9243 01:15:11.049419 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9244 01:15:11.055584 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9245 01:15:11.059186 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9246 01:15:11.063000 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9247 01:15:11.069188 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9248 01:15:11.072328 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9249 01:15:11.075483 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9250 01:15:11.082492 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9251 01:15:11.085553 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9252 01:15:11.092218 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9253 01:15:11.095815 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9254 01:15:11.102292 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9255 01:15:11.105715 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9256 01:15:11.108911 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9257 01:15:11.115572 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9258 01:15:11.118830 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9259 01:15:11.122230 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9260 01:15:11.128742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9261 01:15:11.132212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9262 01:15:11.135577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9263 01:15:11.138919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9264 01:15:11.146048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9265 01:15:11.148744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9266 01:15:11.152084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9267 01:15:11.155684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9268 01:15:11.162237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9269 01:15:11.165393 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9270 01:15:11.169111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9271 01:15:11.172469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9272 01:15:11.178969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9273 01:15:11.182144 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9274 01:15:11.185633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9275 01:15:11.188917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9276 01:15:11.195766 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9277 01:15:11.198814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9278 01:15:11.205664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9279 01:15:11.209107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9280 01:15:11.215545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9281 01:15:11.218830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9282 01:15:11.222101 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9283 01:15:11.229122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9284 01:15:11.232834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9285 01:15:11.238596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9286 01:15:11.242123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9287 01:15:11.248894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9288 01:15:11.252041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9289 01:15:11.258636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9290 01:15:11.261973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9291 01:15:11.265276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9292 01:15:11.272129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9293 01:15:11.275432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9294 01:15:11.282102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9295 01:15:11.285203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9296 01:15:11.291940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9297 01:15:11.295452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9298 01:15:11.298628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9299 01:15:11.305453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9300 01:15:11.308796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9301 01:15:11.315870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9302 01:15:11.318932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9303 01:15:11.325610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9304 01:15:11.328986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9305 01:15:11.331930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9306 01:15:11.338912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9307 01:15:11.341972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9308 01:15:11.348511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9309 01:15:11.351960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9310 01:15:11.358660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9311 01:15:11.362167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9312 01:15:11.365410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9313 01:15:11.372123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9314 01:15:11.375509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9315 01:15:11.381948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9316 01:15:11.385524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9317 01:15:11.392038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9318 01:15:11.395635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9319 01:15:11.398804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9320 01:15:11.405579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9321 01:15:11.408935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9322 01:15:11.415390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9323 01:15:11.418633 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9324 01:15:11.422426 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9325 01:15:11.428963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9326 01:15:11.431928 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9327 01:15:11.435757 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9328 01:15:11.438748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9329 01:15:11.445235 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9330 01:15:11.449025 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9331 01:15:11.455241 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9332 01:15:11.458574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9333 01:15:11.462168 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9334 01:15:11.468614 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9335 01:15:11.472249 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9336 01:15:11.478624 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9337 01:15:11.481751 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9338 01:15:11.485329 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9339 01:15:11.491981 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9340 01:15:11.495128 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9341 01:15:11.501896 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9342 01:15:11.505313 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9343 01:15:11.508425 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9344 01:15:11.515149 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9345 01:15:11.518313 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9346 01:15:11.521798 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9347 01:15:11.528370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9348 01:15:11.531843 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9349 01:15:11.534921 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9350 01:15:11.538269 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9351 01:15:11.545028 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9352 01:15:11.548256 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9353 01:15:11.551665 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9354 01:15:11.558522 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9355 01:15:11.561642 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9356 01:15:11.568313 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9357 01:15:11.571573 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9358 01:15:11.574892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9359 01:15:11.581566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9360 01:15:11.585122 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9361 01:15:11.588153 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9362 01:15:11.595133 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9363 01:15:11.598501 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9364 01:15:11.604969 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9365 01:15:11.608736 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9366 01:15:11.611725 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9367 01:15:11.617999 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9368 01:15:11.621457 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9369 01:15:11.628129 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9370 01:15:11.631600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9371 01:15:11.634513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9372 01:15:11.641301 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9373 01:15:11.644867 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9374 01:15:11.651167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9375 01:15:11.654476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9376 01:15:11.658093 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9377 01:15:11.664626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9378 01:15:11.667750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9379 01:15:11.674687 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9380 01:15:11.678158 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9381 01:15:11.681090 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9382 01:15:11.687636 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9383 01:15:11.691052 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9384 01:15:11.697806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9385 01:15:11.701070 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9386 01:15:11.704379 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9387 01:15:11.710886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9388 01:15:11.714346 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9389 01:15:11.717542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9390 01:15:11.724202 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9391 01:15:11.727483 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9392 01:15:11.734106 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9393 01:15:11.737484 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9394 01:15:11.740696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9395 01:15:11.747327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9396 01:15:11.750618 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9397 01:15:11.757025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9398 01:15:11.760450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9399 01:15:11.767100 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9400 01:15:11.770260 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9401 01:15:11.773638 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9402 01:15:11.780215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9403 01:15:11.783650 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9404 01:15:11.790236 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9405 01:15:11.793479 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9406 01:15:11.796712 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9407 01:15:11.803375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9408 01:15:11.806777 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9409 01:15:11.810155 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9410 01:15:11.816700 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9411 01:15:11.819715 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9412 01:15:11.826410 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9413 01:15:11.829531 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9414 01:15:11.832888 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9415 01:15:11.839563 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9416 01:15:11.843026 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9417 01:15:11.849689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9418 01:15:11.853043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9419 01:15:11.859636 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9420 01:15:11.862932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9421 01:15:11.866371 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9422 01:15:11.872754 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9423 01:15:11.876537 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9424 01:15:11.883118 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9425 01:15:11.885965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9426 01:15:11.892458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9427 01:15:11.895948 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9428 01:15:11.899273 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9429 01:15:11.905910 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9430 01:15:11.909027 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9431 01:15:11.916072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9432 01:15:11.919398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9433 01:15:11.925762 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9434 01:15:11.928691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9435 01:15:11.932007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9436 01:15:11.938802 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9437 01:15:11.942205 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9438 01:15:11.948365 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9439 01:15:11.951937 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9440 01:15:11.958415 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9441 01:15:11.961778 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9442 01:15:11.965099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9443 01:15:11.971541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9444 01:15:11.975193 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9445 01:15:11.981394 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9446 01:15:11.984850 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9447 01:15:11.991200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9448 01:15:11.994488 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9449 01:15:11.998027 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9450 01:15:12.004931 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9451 01:15:12.007690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9452 01:15:12.014425 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9453 01:15:12.017780 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9454 01:15:12.024169 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9455 01:15:12.027983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9456 01:15:12.030847 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9457 01:15:12.037523 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9458 01:15:12.040972 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9459 01:15:12.044105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9460 01:15:12.047485 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9461 01:15:12.051063 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9462 01:15:12.057211 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9463 01:15:12.060372 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9464 01:15:12.067252 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9465 01:15:12.070689 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9466 01:15:12.073958 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9467 01:15:12.080660 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9468 01:15:12.083572 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9469 01:15:12.090402 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9470 01:15:12.093383 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9471 01:15:12.096710 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9472 01:15:12.103395 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9473 01:15:12.106939 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9474 01:15:12.110258 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9475 01:15:12.116577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9476 01:15:12.119877 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9477 01:15:12.123444 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9478 01:15:12.129973 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9479 01:15:12.133138 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9480 01:15:12.140049 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9481 01:15:12.143312 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9482 01:15:12.146575 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9483 01:15:12.153158 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9484 01:15:12.156511 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9485 01:15:12.162877 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9486 01:15:12.166327 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9487 01:15:12.169430 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9488 01:15:12.176065 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9489 01:15:12.179636 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9490 01:15:12.182711 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9491 01:15:12.189506 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9492 01:15:12.192762 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9493 01:15:12.196413 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9494 01:15:12.202574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9495 01:15:12.206013 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9496 01:15:12.209419 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9497 01:15:12.215944 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9498 01:15:12.219299 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9499 01:15:12.222622 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9500 01:15:12.225956 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9501 01:15:12.229084 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9502 01:15:12.235904 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9503 01:15:12.239490 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9504 01:15:12.242293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9505 01:15:12.248926 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9506 01:15:12.252184 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9507 01:15:12.255288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9508 01:15:12.261967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9509 01:15:12.265658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9510 01:15:12.268683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9511 01:15:12.275563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9512 01:15:12.278599 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9513 01:15:12.285497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9514 01:15:12.288686 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9515 01:15:12.291827 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9516 01:15:12.298607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9517 01:15:12.301719 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9518 01:15:12.308688 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9519 01:15:12.311709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9520 01:15:12.314966 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9521 01:15:12.321549 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9522 01:15:12.324787 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9523 01:15:12.331607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9524 01:15:12.335108 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9525 01:15:12.337945 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9526 01:15:12.344730 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9527 01:15:12.348176 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9528 01:15:12.354583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9529 01:15:12.358088 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9530 01:15:12.364570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9531 01:15:12.367740 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9532 01:15:12.371507 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9533 01:15:12.377569 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9534 01:15:12.381229 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9535 01:15:12.387507 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9536 01:15:12.390802 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9537 01:15:12.394016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9538 01:15:12.400849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9539 01:15:12.403919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9540 01:15:12.411006 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9541 01:15:12.414015 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9542 01:15:12.417216 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9543 01:15:12.424100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9544 01:15:12.427117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9545 01:15:12.433657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9546 01:15:12.437032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9547 01:15:12.443648 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9548 01:15:12.447100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9549 01:15:12.450501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9550 01:15:12.457122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9551 01:15:12.460306 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9552 01:15:12.466912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9553 01:15:12.470240 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9554 01:15:12.476691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9555 01:15:12.479934 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9556 01:15:12.483270 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9557 01:15:12.489735 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9558 01:15:12.493252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9559 01:15:12.500038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9560 01:15:12.503275 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9561 01:15:12.506602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9562 01:15:12.512952 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9563 01:15:12.516438 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9564 01:15:12.523027 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9565 01:15:12.526419 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9566 01:15:12.529467 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9567 01:15:12.536188 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9568 01:15:12.539410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9569 01:15:12.545978 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9570 01:15:12.549423 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9571 01:15:12.555888 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9572 01:15:12.559407 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9573 01:15:12.562406 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9574 01:15:12.569413 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9575 01:15:12.572330 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9576 01:15:12.578945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9577 01:15:12.582486 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9578 01:15:12.588853 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9579 01:15:12.592149 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9580 01:15:12.595301 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9581 01:15:12.602625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9582 01:15:12.605241 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9583 01:15:12.611896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9584 01:15:12.615249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9585 01:15:12.621693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9586 01:15:12.625061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9587 01:15:12.631566 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9588 01:15:12.634872 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9589 01:15:12.638114 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9590 01:15:12.644926 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9591 01:15:12.648300 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9592 01:15:12.654843 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9593 01:15:12.658426 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9594 01:15:12.664982 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9595 01:15:12.668221 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9596 01:15:12.671819 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9597 01:15:12.678391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9598 01:15:12.681753 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9599 01:15:12.688269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9600 01:15:12.691481 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9601 01:15:12.697907 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9602 01:15:12.701296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9603 01:15:12.707693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9604 01:15:12.710998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9605 01:15:12.714824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9606 01:15:12.720976 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9607 01:15:12.724415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9608 01:15:12.730892 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9609 01:15:12.734151 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9610 01:15:12.740807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9611 01:15:12.743991 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9612 01:15:12.750592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9613 01:15:12.753983 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9614 01:15:12.757434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9615 01:15:12.764091 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9616 01:15:12.767501 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9617 01:15:12.773751 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9618 01:15:12.777718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9619 01:15:12.784069 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9620 01:15:12.787112 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9621 01:15:12.790536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9622 01:15:12.796849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9623 01:15:12.800184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9624 01:15:12.806791 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9625 01:15:12.810117 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9626 01:15:12.816740 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9627 01:15:12.820193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9628 01:15:12.826730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9629 01:15:12.829941 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9630 01:15:12.833456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9631 01:15:12.839756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9632 01:15:12.843093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9633 01:15:12.849835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9634 01:15:12.853059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9635 01:15:12.859627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9636 01:15:12.863114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9637 01:15:12.869876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9638 01:15:12.873060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9639 01:15:12.879590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9640 01:15:12.882789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9641 01:15:12.889265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9642 01:15:12.892721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9643 01:15:12.899287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9644 01:15:12.902718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9645 01:15:12.909129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9646 01:15:12.912563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9647 01:15:12.915722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9648 01:15:12.922586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9649 01:15:12.926075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9650 01:15:12.932177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9651 01:15:12.938936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9652 01:15:12.942276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9653 01:15:12.949021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9654 01:15:12.952253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9655 01:15:12.958944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9656 01:15:12.961946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9657 01:15:12.968683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9658 01:15:12.972211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9659 01:15:12.978678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9660 01:15:12.981953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9661 01:15:12.988784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9662 01:15:12.992068 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9663 01:15:12.995012 INFO: [APUAPC] vio 0
9664 01:15:12.998228 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9665 01:15:13.001473 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9666 01:15:13.005354 INFO: [APUAPC] D0_APC_0: 0x400510
9667 01:15:13.008250 INFO: [APUAPC] D0_APC_1: 0x0
9668 01:15:13.011561 INFO: [APUAPC] D0_APC_2: 0x1540
9669 01:15:13.015079 INFO: [APUAPC] D0_APC_3: 0x0
9670 01:15:13.018211 INFO: [APUAPC] D1_APC_0: 0xffffffff
9671 01:15:13.021594 INFO: [APUAPC] D1_APC_1: 0xffffffff
9672 01:15:13.024762 INFO: [APUAPC] D1_APC_2: 0x3fffff
9673 01:15:13.028497 INFO: [APUAPC] D1_APC_3: 0x0
9674 01:15:13.031448 INFO: [APUAPC] D2_APC_0: 0xffffffff
9675 01:15:13.034762 INFO: [APUAPC] D2_APC_1: 0xffffffff
9676 01:15:13.038102 INFO: [APUAPC] D2_APC_2: 0x3fffff
9677 01:15:13.041550 INFO: [APUAPC] D2_APC_3: 0x0
9678 01:15:13.044622 INFO: [APUAPC] D3_APC_0: 0xffffffff
9679 01:15:13.048138 INFO: [APUAPC] D3_APC_1: 0xffffffff
9680 01:15:13.051285 INFO: [APUAPC] D3_APC_2: 0x3fffff
9681 01:15:13.054654 INFO: [APUAPC] D3_APC_3: 0x0
9682 01:15:13.058169 INFO: [APUAPC] D4_APC_0: 0xffffffff
9683 01:15:13.061354 INFO: [APUAPC] D4_APC_1: 0xffffffff
9684 01:15:13.064615 INFO: [APUAPC] D4_APC_2: 0x3fffff
9685 01:15:13.068364 INFO: [APUAPC] D4_APC_3: 0x0
9686 01:15:13.071209 INFO: [APUAPC] D5_APC_0: 0xffffffff
9687 01:15:13.074666 INFO: [APUAPC] D5_APC_1: 0xffffffff
9688 01:15:13.077990 INFO: [APUAPC] D5_APC_2: 0x3fffff
9689 01:15:13.081227 INFO: [APUAPC] D5_APC_3: 0x0
9690 01:15:13.084421 INFO: [APUAPC] D6_APC_0: 0xffffffff
9691 01:15:13.087797 INFO: [APUAPC] D6_APC_1: 0xffffffff
9692 01:15:13.091012 INFO: [APUAPC] D6_APC_2: 0x3fffff
9693 01:15:13.094576 INFO: [APUAPC] D6_APC_3: 0x0
9694 01:15:13.097820 INFO: [APUAPC] D7_APC_0: 0xffffffff
9695 01:15:13.100865 INFO: [APUAPC] D7_APC_1: 0xffffffff
9696 01:15:13.104265 INFO: [APUAPC] D7_APC_2: 0x3fffff
9697 01:15:13.107454 INFO: [APUAPC] D7_APC_3: 0x0
9698 01:15:13.110944 INFO: [APUAPC] D8_APC_0: 0xffffffff
9699 01:15:13.114116 INFO: [APUAPC] D8_APC_1: 0xffffffff
9700 01:15:13.117389 INFO: [APUAPC] D8_APC_2: 0x3fffff
9701 01:15:13.120747 INFO: [APUAPC] D8_APC_3: 0x0
9702 01:15:13.123922 INFO: [APUAPC] D9_APC_0: 0xffffffff
9703 01:15:13.127419 INFO: [APUAPC] D9_APC_1: 0xffffffff
9704 01:15:13.130642 INFO: [APUAPC] D9_APC_2: 0x3fffff
9705 01:15:13.130727 INFO: [APUAPC] D9_APC_3: 0x0
9706 01:15:13.137564 INFO: [APUAPC] D10_APC_0: 0xffffffff
9707 01:15:13.140685 INFO: [APUAPC] D10_APC_1: 0xffffffff
9708 01:15:13.143819 INFO: [APUAPC] D10_APC_2: 0x3fffff
9709 01:15:13.147096 INFO: [APUAPC] D10_APC_3: 0x0
9710 01:15:13.150486 INFO: [APUAPC] D11_APC_0: 0xffffffff
9711 01:15:13.153719 INFO: [APUAPC] D11_APC_1: 0xffffffff
9712 01:15:13.156996 INFO: [APUAPC] D11_APC_2: 0x3fffff
9713 01:15:13.160464 INFO: [APUAPC] D11_APC_3: 0x0
9714 01:15:13.163938 INFO: [APUAPC] D12_APC_0: 0xffffffff
9715 01:15:13.167445 INFO: [APUAPC] D12_APC_1: 0xffffffff
9716 01:15:13.170516 INFO: [APUAPC] D12_APC_2: 0x3fffff
9717 01:15:13.173887 INFO: [APUAPC] D12_APC_3: 0x0
9718 01:15:13.176970 INFO: [APUAPC] D13_APC_0: 0xffffffff
9719 01:15:13.180520 INFO: [APUAPC] D13_APC_1: 0xffffffff
9720 01:15:13.183766 INFO: [APUAPC] D13_APC_2: 0x3fffff
9721 01:15:13.187310 INFO: [APUAPC] D13_APC_3: 0x0
9722 01:15:13.190456 INFO: [APUAPC] D14_APC_0: 0xffffffff
9723 01:15:13.193631 INFO: [APUAPC] D14_APC_1: 0xffffffff
9724 01:15:13.197298 INFO: [APUAPC] D14_APC_2: 0x3fffff
9725 01:15:13.200155 INFO: [APUAPC] D14_APC_3: 0x0
9726 01:15:13.203285 INFO: [APUAPC] D15_APC_0: 0xffffffff
9727 01:15:13.206630 INFO: [APUAPC] D15_APC_1: 0xffffffff
9728 01:15:13.210240 INFO: [APUAPC] D15_APC_2: 0x3fffff
9729 01:15:13.213620 INFO: [APUAPC] D15_APC_3: 0x0
9730 01:15:13.216962 INFO: [APUAPC] APC_CON: 0x4
9731 01:15:13.217034 INFO: [NOCDAPC] D0_APC_0: 0x0
9732 01:15:13.220086 INFO: [NOCDAPC] D0_APC_1: 0x0
9733 01:15:13.223284 INFO: [NOCDAPC] D1_APC_0: 0x0
9734 01:15:13.226941 INFO: [NOCDAPC] D1_APC_1: 0xfff
9735 01:15:13.229838 INFO: [NOCDAPC] D2_APC_0: 0x0
9736 01:15:13.233363 INFO: [NOCDAPC] D2_APC_1: 0xfff
9737 01:15:13.236896 INFO: [NOCDAPC] D3_APC_0: 0x0
9738 01:15:13.239737 INFO: [NOCDAPC] D3_APC_1: 0xfff
9739 01:15:13.243017 INFO: [NOCDAPC] D4_APC_0: 0x0
9740 01:15:13.246421 INFO: [NOCDAPC] D4_APC_1: 0xfff
9741 01:15:13.249965 INFO: [NOCDAPC] D5_APC_0: 0x0
9742 01:15:13.250068 INFO: [NOCDAPC] D5_APC_1: 0xfff
9743 01:15:13.253124 INFO: [NOCDAPC] D6_APC_0: 0x0
9744 01:15:13.256016 INFO: [NOCDAPC] D6_APC_1: 0xfff
9745 01:15:13.259510 INFO: [NOCDAPC] D7_APC_0: 0x0
9746 01:15:13.262523 INFO: [NOCDAPC] D7_APC_1: 0xfff
9747 01:15:13.265940 INFO: [NOCDAPC] D8_APC_0: 0x0
9748 01:15:13.269109 INFO: [NOCDAPC] D8_APC_1: 0xfff
9749 01:15:13.272322 INFO: [NOCDAPC] D9_APC_0: 0x0
9750 01:15:13.275829 INFO: [NOCDAPC] D9_APC_1: 0xfff
9751 01:15:13.278926 INFO: [NOCDAPC] D10_APC_0: 0x0
9752 01:15:13.282591 INFO: [NOCDAPC] D10_APC_1: 0xfff
9753 01:15:13.285746 INFO: [NOCDAPC] D11_APC_0: 0x0
9754 01:15:13.289456 INFO: [NOCDAPC] D11_APC_1: 0xfff
9755 01:15:13.292409 INFO: [NOCDAPC] D12_APC_0: 0x0
9756 01:15:13.292488 INFO: [NOCDAPC] D12_APC_1: 0xfff
9757 01:15:13.295520 INFO: [NOCDAPC] D13_APC_0: 0x0
9758 01:15:13.298949 INFO: [NOCDAPC] D13_APC_1: 0xfff
9759 01:15:13.302321 INFO: [NOCDAPC] D14_APC_0: 0x0
9760 01:15:13.305487 INFO: [NOCDAPC] D14_APC_1: 0xfff
9761 01:15:13.308648 INFO: [NOCDAPC] D15_APC_0: 0x0
9762 01:15:13.312112 INFO: [NOCDAPC] D15_APC_1: 0xfff
9763 01:15:13.315207 INFO: [NOCDAPC] APC_CON: 0x4
9764 01:15:13.318426 INFO: [APUAPC] set_apusys_apc done
9765 01:15:13.321995 INFO: [DEVAPC] devapc_init done
9766 01:15:13.325150 INFO: GICv3 without legacy support detected.
9767 01:15:13.328705 INFO: ARM GICv3 driver initialized in EL3
9768 01:15:13.335042 INFO: Maximum SPI INTID supported: 639
9769 01:15:13.338737 INFO: BL31: Initializing runtime services
9770 01:15:13.345784 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9771 01:15:13.345864 INFO: SPM: enable CPC mode
9772 01:15:13.351972 INFO: mcdi ready for mcusys-off-idle and system suspend
9773 01:15:13.354979 INFO: BL31: Preparing for EL3 exit to normal world
9774 01:15:13.358508 INFO: Entry point address = 0x80000000
9775 01:15:13.361860 INFO: SPSR = 0x8
9776 01:15:13.367409
9777 01:15:13.367492
9778 01:15:13.367560
9779 01:15:13.370900 Starting depthcharge on Spherion...
9780 01:15:13.370980
9781 01:15:13.371044 Wipe memory regions:
9782 01:15:13.371103
9783 01:15:13.371720 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9784 01:15:13.371820 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9785 01:15:13.371902 Setting prompt string to ['asurada:']
9786 01:15:13.371980 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9787 01:15:13.374004 [0x00000040000000, 0x00000054600000)
9788 01:15:13.496397
9789 01:15:13.496504 [0x00000054660000, 0x00000080000000)
9790 01:15:13.757043
9791 01:15:13.757171 [0x000000821a7280, 0x000000ffe64000)
9792 01:15:14.501825
9793 01:15:14.501961 [0x00000100000000, 0x00000140000000)
9794 01:15:14.883267
9795 01:15:14.886687 Initializing XHCI USB controller at 0x11200000.
9796 01:15:15.924609
9797 01:15:15.928019 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9798 01:15:15.928113
9799 01:15:15.928178
9800 01:15:15.928239
9801 01:15:15.928521 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9803 01:15:16.028869 asurada: tftpboot 192.168.201.1 13468779/tftp-deploy-xr4cs4k4/kernel/image.itb 13468779/tftp-deploy-xr4cs4k4/kernel/cmdline
9804 01:15:16.028990 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9805 01:15:16.029093 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
9806 01:15:16.033164 tftpboot 192.168.201.1 13468779/tftp-deploy-xr4cs4k4/kernel/image.itp-deploy-xr4cs4k4/kernel/cmdline
9807 01:15:16.033247
9808 01:15:16.033310 Waiting for link
9809 01:15:16.191412
9810 01:15:16.191534 R8152: Initializing
9811 01:15:16.191604
9812 01:15:16.194862 Version 9 (ocp_data = 6010)
9813 01:15:16.194943
9814 01:15:16.197767 R8152: Done initializing
9815 01:15:16.197848
9816 01:15:16.197911 Adding net device
9817 01:15:18.086336
9818 01:15:18.086486 done.
9819 01:15:18.086558
9820 01:15:18.086618 MAC: 00:e0:4c:68:03:bd
9821 01:15:18.086675
9822 01:15:18.089810 Sending DHCP discover... done.
9823 01:15:18.089898
9824 01:15:18.093132 Waiting for reply... done.
9825 01:15:18.093235
9826 01:15:18.096319 Sending DHCP request... done.
9827 01:15:18.096411
9828 01:15:18.096484 Waiting for reply... done.
9829 01:15:18.096552
9830 01:15:18.099695 My ip is 192.168.201.16
9831 01:15:18.099795
9832 01:15:18.103023 The DHCP server ip is 192.168.201.1
9833 01:15:18.103123
9834 01:15:18.106520 TFTP server IP predefined by user: 192.168.201.1
9835 01:15:18.106629
9836 01:15:18.112659 Bootfile predefined by user: 13468779/tftp-deploy-xr4cs4k4/kernel/image.itb
9837 01:15:18.112779
9838 01:15:18.116547 Sending tftp read request... done.
9839 01:15:18.116679
9840 01:15:18.119486 Waiting for the transfer...
9841 01:15:18.119634
9842 01:15:18.387901 00000000 ################################################################
9843 01:15:18.388029
9844 01:15:18.650228 00080000 ################################################################
9845 01:15:18.650361
9846 01:15:18.898409 00100000 ################################################################
9847 01:15:18.898535
9848 01:15:19.148282 00180000 ################################################################
9849 01:15:19.148413
9850 01:15:19.398831 00200000 ################################################################
9851 01:15:19.398954
9852 01:15:19.655839 00280000 ################################################################
9853 01:15:19.655970
9854 01:15:19.908445 00300000 ################################################################
9855 01:15:19.908580
9856 01:15:20.189169 00380000 ################################################################
9857 01:15:20.189307
9858 01:15:20.443564 00400000 ################################################################
9859 01:15:20.443693
9860 01:15:20.695318 00480000 ################################################################
9861 01:15:20.695447
9862 01:15:20.947254 00500000 ################################################################
9863 01:15:20.947382
9864 01:15:21.210000 00580000 ################################################################
9865 01:15:21.210161
9866 01:15:21.468150 00600000 ################################################################
9867 01:15:21.468288
9868 01:15:21.718543 00680000 ################################################################
9869 01:15:21.718674
9870 01:15:21.979549 00700000 ################################################################
9871 01:15:21.979679
9872 01:15:22.241400 00780000 ################################################################
9873 01:15:22.241525
9874 01:15:22.504896 00800000 ################################################################
9875 01:15:22.505030
9876 01:15:22.760650 00880000 ################################################################
9877 01:15:22.760777
9878 01:15:23.024154 00900000 ################################################################
9879 01:15:23.024282
9880 01:15:23.306483 00980000 ################################################################
9881 01:15:23.306612
9882 01:15:23.583219 00a00000 ################################################################
9883 01:15:23.583355
9884 01:15:23.839122 00a80000 ################################################################
9885 01:15:23.839248
9886 01:15:24.100165 00b00000 ################################################################
9887 01:15:24.100293
9888 01:15:24.356506 00b80000 ################################################################
9889 01:15:24.356645
9890 01:15:24.614322 00c00000 ################################################################
9891 01:15:24.614445
9892 01:15:24.885951 00c80000 ################################################################
9893 01:15:24.886120
9894 01:15:25.159136 00d00000 ################################################################
9895 01:15:25.159278
9896 01:15:25.409697 00d80000 ################################################################
9897 01:15:25.409826
9898 01:15:25.667455 00e00000 ################################################################
9899 01:15:25.667586
9900 01:15:25.949577 00e80000 ################################################################
9901 01:15:25.949718
9902 01:15:26.236141 00f00000 ################################################################
9903 01:15:26.236274
9904 01:15:26.511165 00f80000 ################################################################
9905 01:15:26.511290
9906 01:15:26.801908 01000000 ################################################################
9907 01:15:26.802087
9908 01:15:27.059469 01080000 ################################################################
9909 01:15:27.059605
9910 01:15:27.341358 01100000 ################################################################
9911 01:15:27.341497
9912 01:15:27.633963 01180000 ################################################################
9913 01:15:27.634173
9914 01:15:27.928298 01200000 ################################################################
9915 01:15:27.928433
9916 01:15:28.201429 01280000 ################################################################
9917 01:15:28.201578
9918 01:15:28.469472 01300000 ################################################################
9919 01:15:28.469603
9920 01:15:28.744565 01380000 ################################################################
9921 01:15:28.744719
9922 01:15:29.033070 01400000 ################################################################
9923 01:15:29.033206
9924 01:15:29.320420 01480000 ################################################################
9925 01:15:29.320566
9926 01:15:29.579105 01500000 ################################################################
9927 01:15:29.579236
9928 01:15:29.854401 01580000 ################################################################
9929 01:15:29.854534
9930 01:15:30.137248 01600000 ################################################################
9931 01:15:30.137382
9932 01:15:30.405775 01680000 ################################################################
9933 01:15:30.405930
9934 01:15:30.696054 01700000 ################################################################
9935 01:15:30.696190
9936 01:15:30.955850 01780000 ################################################################
9937 01:15:30.955976
9938 01:15:31.217807 01800000 ################################################################
9939 01:15:31.217941
9940 01:15:31.489708 01880000 ################################################################
9941 01:15:31.489856
9942 01:15:31.808684 01900000 ################################################################
9943 01:15:31.808829
9944 01:15:32.076491 01980000 ################################################################
9945 01:15:32.076630
9946 01:15:32.346150 01a00000 ################################################################
9947 01:15:32.346285
9948 01:15:32.596682 01a80000 ################################################################
9949 01:15:32.596811
9950 01:15:32.848515 01b00000 ################################################################
9951 01:15:32.848655
9952 01:15:33.101584 01b80000 ################################################################
9953 01:15:33.101776
9954 01:15:33.382710 01c00000 ################################################################
9955 01:15:33.382848
9956 01:15:33.669575 01c80000 ################################################################
9957 01:15:33.669719
9958 01:15:33.960170 01d00000 ################################################################
9959 01:15:33.960312
9960 01:15:34.256874 01d80000 ################################################################
9961 01:15:34.257008
9962 01:15:34.415405 01e00000 ################################## done.
9963 01:15:34.415522
9964 01:15:34.418528 The bootfile was 31734950 bytes long.
9965 01:15:34.418615
9966 01:15:34.422148 Sending tftp read request... done.
9967 01:15:34.422234
9968 01:15:34.422301 Waiting for the transfer...
9969 01:15:34.422364
9970 01:15:34.425257 00000000 # done.
9971 01:15:34.425427
9972 01:15:34.431989 Command line loaded dynamically from TFTP file: 13468779/tftp-deploy-xr4cs4k4/kernel/cmdline
9973 01:15:34.432167
9974 01:15:34.455023 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9975 01:15:34.455281
9976 01:15:34.455419 Loading FIT.
9977 01:15:34.455544
9978 01:15:34.458346 Image ramdisk-1 has 18775635 bytes.
9979 01:15:34.458616
9980 01:15:34.461491 Image fdt-1 has 47230 bytes.
9981 01:15:34.461773
9982 01:15:34.464966 Image kernel-1 has 12910050 bytes.
9983 01:15:34.465281
9984 01:15:34.474876 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9985 01:15:34.475377
9986 01:15:34.491306 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9987 01:15:34.491873
9988 01:15:34.498183 Choosing best match conf-1 for compat google,spherion-rev3.
9989 01:15:34.498738
9990 01:15:34.505969 Connected to device vid:did:rid of 1ae0:0028:00
9991 01:15:34.512800
9992 01:15:34.515807 tpm_get_response: command 0x17b, return code 0x0
9993 01:15:34.516268
9994 01:15:34.522961 ec_init: CrosEC protocol v3 supported (256, 248)
9995 01:15:34.523514
9996 01:15:34.526315 tpm_cleanup: add release locality here.
9997 01:15:34.526772
9998 01:15:34.529318 Shutting down all USB controllers.
9999 01:15:34.529868
10000 01:15:34.533065 Removing current net device
10001 01:15:34.533625
10002 01:15:34.535975 Exiting depthcharge with code 4 at timestamp: 49464458
10003 01:15:34.539204
10004 01:15:34.542714 LZMA decompressing kernel-1 to 0x821a6718
10005 01:15:34.543172
10006 01:15:34.545694 LZMA decompressing kernel-1 to 0x40000000
10007 01:15:36.138436
10008 01:15:36.139041 jumping to kernel
10009 01:15:36.140903 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10010 01:15:36.141516 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10011 01:15:36.141980 Setting prompt string to ['Linux version [0-9]']
10012 01:15:36.142484 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10013 01:15:36.143037 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10014 01:15:36.188927
10015 01:15:36.192191 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10016 01:15:36.195372 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10017 01:15:36.195692 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10018 01:15:36.196021 Setting prompt string to []
10019 01:15:36.196440 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10020 01:15:36.196760 Using line separator: #'\n'#
10021 01:15:36.197024 No login prompt set.
10022 01:15:36.197299 Parsing kernel messages
10023 01:15:36.197554 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10024 01:15:36.197885 [login-action] Waiting for messages, (timeout 00:04:03)
10025 01:15:36.198342 Waiting using forced prompt support (timeout 00:02:02)
10026 01:15:36.215055 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10027 01:15:36.218306 [ 0.000000] random: crng init done
10028 01:15:36.225157 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10029 01:15:36.228054 [ 0.000000] efi: UEFI not found.
10030 01:15:36.234766 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10031 01:15:36.244675 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10032 01:15:36.254645 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10033 01:15:36.261593 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10034 01:15:36.268193 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10035 01:15:36.274378 [ 0.000000] printk: bootconsole [mtk8250] enabled
10036 01:15:36.280877 [ 0.000000] NUMA: No NUMA configuration found
10037 01:15:36.287738 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10038 01:15:36.294081 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10039 01:15:36.294548 [ 0.000000] Zone ranges:
10040 01:15:36.300416 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10041 01:15:36.303828 [ 0.000000] DMA32 empty
10042 01:15:36.310472 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10043 01:15:36.314084 [ 0.000000] Movable zone start for each node
10044 01:15:36.317270 [ 0.000000] Early memory node ranges
10045 01:15:36.324236 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10046 01:15:36.330668 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10047 01:15:36.337239 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10048 01:15:36.343578 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10049 01:15:36.350198 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10050 01:15:36.356787 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10051 01:15:36.387697 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10052 01:15:36.394232 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10053 01:15:36.400750 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10054 01:15:36.404299 [ 0.000000] psci: probing for conduit method from DT.
10055 01:15:36.411016 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10056 01:15:36.414174 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10057 01:15:36.420707 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10058 01:15:36.424275 [ 0.000000] psci: SMC Calling Convention v1.2
10059 01:15:36.430778 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10060 01:15:36.433903 [ 0.000000] Detected VIPT I-cache on CPU0
10061 01:15:36.440410 [ 0.000000] CPU features: detected: GIC system register CPU interface
10062 01:15:36.446939 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10063 01:15:36.453613 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10064 01:15:36.460604 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10065 01:15:36.470392 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10066 01:15:36.476656 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10067 01:15:36.480211 [ 0.000000] alternatives: applying boot alternatives
10068 01:15:36.486640 [ 0.000000] Fallback order for Node 0: 0
10069 01:15:36.493628 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10070 01:15:36.496378 [ 0.000000] Policy zone: Normal
10071 01:15:36.519410 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10072 01:15:36.529492 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10073 01:15:36.539633 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10074 01:15:36.546567 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10075 01:15:36.552411 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10076 01:15:36.559435 <6>[ 0.000000] software IO TLB: area num 8.
10077 01:15:36.614649 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10078 01:15:36.694912 <6>[ 0.000000] Memory: 3831760K/4191232K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 326704K reserved, 32768K cma-reserved)
10079 01:15:36.701300 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10080 01:15:36.707855 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10081 01:15:36.710954 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10082 01:15:36.717655 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10083 01:15:36.724618 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10084 01:15:36.727577 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10085 01:15:36.738172 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10086 01:15:36.744249 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10087 01:15:36.750729 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10088 01:15:36.757559 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10089 01:15:36.760592 <6>[ 0.000000] GICv3: 608 SPIs implemented
10090 01:15:36.763855 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10091 01:15:36.770486 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10092 01:15:36.773781 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10093 01:15:36.780751 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10094 01:15:36.793578 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10095 01:15:36.806690 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10096 01:15:36.813410 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10097 01:15:36.821504 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10098 01:15:36.834757 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10099 01:15:36.841107 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10100 01:15:36.847856 <6>[ 0.009228] Console: colour dummy device 80x25
10101 01:15:36.857697 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10102 01:15:36.864112 <6>[ 0.024463] pid_max: default: 32768 minimum: 301
10103 01:15:36.867694 <6>[ 0.029364] LSM: Security Framework initializing
10104 01:15:36.873980 <6>[ 0.034277] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10105 01:15:36.884168 <6>[ 0.041931] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10106 01:15:36.890567 <6>[ 0.051156] cblist_init_generic: Setting adjustable number of callback queues.
10107 01:15:36.897461 <6>[ 0.058600] cblist_init_generic: Setting shift to 3 and lim to 1.
10108 01:15:36.907829 <6>[ 0.064977] cblist_init_generic: Setting adjustable number of callback queues.
10109 01:15:36.913939 <6>[ 0.072404] cblist_init_generic: Setting shift to 3 and lim to 1.
10110 01:15:36.917557 <6>[ 0.078843] rcu: Hierarchical SRCU implementation.
10111 01:15:36.924256 <6>[ 0.083889] rcu: Max phase no-delay instances is 1000.
10112 01:15:36.930499 <6>[ 0.090938] EFI services will not be available.
10113 01:15:36.934004 <6>[ 0.095892] smp: Bringing up secondary CPUs ...
10114 01:15:36.941862 <6>[ 0.100940] Detected VIPT I-cache on CPU1
10115 01:15:36.948428 <6>[ 0.101009] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10116 01:15:36.955180 <6>[ 0.101039] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10117 01:15:36.958584 <6>[ 0.101368] Detected VIPT I-cache on CPU2
10118 01:15:36.968216 <6>[ 0.101414] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10119 01:15:36.974985 <6>[ 0.101429] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10120 01:15:36.978354 <6>[ 0.101685] Detected VIPT I-cache on CPU3
10121 01:15:36.984641 <6>[ 0.101731] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10122 01:15:36.991198 <6>[ 0.101745] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10123 01:15:36.994782 <6>[ 0.102048] CPU features: detected: Spectre-v4
10124 01:15:37.001009 <6>[ 0.102054] CPU features: detected: Spectre-BHB
10125 01:15:37.004505 <6>[ 0.102059] Detected PIPT I-cache on CPU4
10126 01:15:37.011164 <6>[ 0.102118] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10127 01:15:37.017632 <6>[ 0.102135] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10128 01:15:37.024594 <6>[ 0.102424] Detected PIPT I-cache on CPU5
10129 01:15:37.030787 <6>[ 0.102486] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10130 01:15:37.037471 <6>[ 0.102503] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10131 01:15:37.040911 <6>[ 0.102781] Detected PIPT I-cache on CPU6
10132 01:15:37.047287 <6>[ 0.102842] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10133 01:15:37.057535 <6>[ 0.102858] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10134 01:15:37.060816 <6>[ 0.103158] Detected PIPT I-cache on CPU7
10135 01:15:37.066854 <6>[ 0.103223] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10136 01:15:37.073730 <6>[ 0.103239] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10137 01:15:37.077240 <6>[ 0.103287] smp: Brought up 1 node, 8 CPUs
10138 01:15:37.083525 <6>[ 0.244630] SMP: Total of 8 processors activated.
10139 01:15:37.090395 <6>[ 0.249582] CPU features: detected: 32-bit EL0 Support
10140 01:15:37.096833 <6>[ 0.254945] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10141 01:15:37.103044 <6>[ 0.263800] CPU features: detected: Common not Private translations
10142 01:15:37.109788 <6>[ 0.270276] CPU features: detected: CRC32 instructions
10143 01:15:37.116602 <6>[ 0.275627] CPU features: detected: RCpc load-acquire (LDAPR)
10144 01:15:37.119547 <6>[ 0.281587] CPU features: detected: LSE atomic instructions
10145 01:15:37.126454 <6>[ 0.287369] CPU features: detected: Privileged Access Never
10146 01:15:37.132854 <6>[ 0.293149] CPU features: detected: RAS Extension Support
10147 01:15:37.139675 <6>[ 0.298792] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10148 01:15:37.142544 <6>[ 0.306056] CPU: All CPU(s) started at EL2
10149 01:15:37.149223 <6>[ 0.310373] alternatives: applying system-wide alternatives
10150 01:15:37.159416 <6>[ 0.320375] devtmpfs: initialized
10151 01:15:37.174182 <6>[ 0.328585] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10152 01:15:37.180740 <6>[ 0.338546] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10153 01:15:37.186823 <6>[ 0.346772] pinctrl core: initialized pinctrl subsystem
10154 01:15:37.190130 <6>[ 0.353471] DMI not present or invalid.
10155 01:15:37.197001 <6>[ 0.357787] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10156 01:15:37.206724 <6>[ 0.364653] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10157 01:15:37.213265 <6>[ 0.372097] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10158 01:15:37.223065 <6>[ 0.380191] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10159 01:15:37.226453 <6>[ 0.388348] audit: initializing netlink subsys (disabled)
10160 01:15:37.236471 <5>[ 0.394042] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10161 01:15:37.243161 <6>[ 0.394749] thermal_sys: Registered thermal governor 'step_wise'
10162 01:15:37.249734 <6>[ 0.402008] thermal_sys: Registered thermal governor 'power_allocator'
10163 01:15:37.253120 <6>[ 0.408262] cpuidle: using governor menu
10164 01:15:37.259799 <6>[ 0.419224] NET: Registered PF_QIPCRTR protocol family
10165 01:15:37.266497 <6>[ 0.424694] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10166 01:15:37.269680 <6>[ 0.431796] ASID allocator initialised with 32768 entries
10167 01:15:37.277183 <6>[ 0.438357] Serial: AMBA PL011 UART driver
10168 01:15:37.285976 <4>[ 0.447106] Trying to register duplicate clock ID: 134
10169 01:15:37.339960 <6>[ 0.504696] KASLR enabled
10170 01:15:37.354010 <6>[ 0.512395] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10171 01:15:37.361114 <6>[ 0.519407] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10172 01:15:37.367241 <6>[ 0.525897] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10173 01:15:37.374085 <6>[ 0.532903] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10174 01:15:37.380564 <6>[ 0.539389] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10175 01:15:37.387166 <6>[ 0.546392] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10176 01:15:37.393539 <6>[ 0.552877] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10177 01:15:37.400662 <6>[ 0.559882] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10178 01:15:37.403872 <6>[ 0.567372] ACPI: Interpreter disabled.
10179 01:15:37.412528 <6>[ 0.573780] iommu: Default domain type: Translated
10180 01:15:37.418978 <6>[ 0.578893] iommu: DMA domain TLB invalidation policy: strict mode
10181 01:15:37.422634 <5>[ 0.585550] SCSI subsystem initialized
10182 01:15:37.429286 <6>[ 0.589713] usbcore: registered new interface driver usbfs
10183 01:15:37.435507 <6>[ 0.595444] usbcore: registered new interface driver hub
10184 01:15:37.438705 <6>[ 0.600994] usbcore: registered new device driver usb
10185 01:15:37.445698 <6>[ 0.607091] pps_core: LinuxPPS API ver. 1 registered
10186 01:15:37.455692 <6>[ 0.612284] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10187 01:15:37.458575 <6>[ 0.621626] PTP clock support registered
10188 01:15:37.462082 <6>[ 0.625863] EDAC MC: Ver: 3.0.0
10189 01:15:37.469536 <6>[ 0.631014] FPGA manager framework
10190 01:15:37.476216 <6>[ 0.634692] Advanced Linux Sound Architecture Driver Initialized.
10191 01:15:37.479711 <6>[ 0.641462] vgaarb: loaded
10192 01:15:37.486838 <6>[ 0.644634] clocksource: Switched to clocksource arch_sys_counter
10193 01:15:37.489526 <5>[ 0.651077] VFS: Disk quotas dquot_6.6.0
10194 01:15:37.495816 <6>[ 0.655260] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10195 01:15:37.499353 <6>[ 0.662447] pnp: PnP ACPI: disabled
10196 01:15:37.507776 <6>[ 0.669129] NET: Registered PF_INET protocol family
10197 01:15:37.514282 <6>[ 0.674519] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10198 01:15:37.526481 <6>[ 0.684525] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10199 01:15:37.536508 <6>[ 0.693314] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10200 01:15:37.543174 <6>[ 0.701278] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10201 01:15:37.549729 <6>[ 0.709669] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10202 01:15:37.560374 <6>[ 0.718319] TCP: Hash tables configured (established 32768 bind 32768)
10203 01:15:37.566681 <6>[ 0.725163] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10204 01:15:37.573382 <6>[ 0.732180] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10205 01:15:37.580080 <6>[ 0.739691] NET: Registered PF_UNIX/PF_LOCAL protocol family
10206 01:15:37.586725 <6>[ 0.745845] RPC: Registered named UNIX socket transport module.
10207 01:15:37.589904 <6>[ 0.751997] RPC: Registered udp transport module.
10208 01:15:37.596858 <6>[ 0.756932] RPC: Registered tcp transport module.
10209 01:15:37.603375 <6>[ 0.761864] RPC: Registered tcp NFSv4.1 backchannel transport module.
10210 01:15:37.606363 <6>[ 0.768530] PCI: CLS 0 bytes, default 64
10211 01:15:37.609769 <6>[ 0.772847] Unpacking initramfs...
10212 01:15:37.619548 <6>[ 0.776789] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10213 01:15:37.626496 <6>[ 0.785445] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10214 01:15:37.632772 <6>[ 0.794289] kvm [1]: IPA Size Limit: 40 bits
10215 01:15:37.636448 <6>[ 0.798812] kvm [1]: GICv3: no GICV resource entry
10216 01:15:37.642875 <6>[ 0.803833] kvm [1]: disabling GICv2 emulation
10217 01:15:37.649275 <6>[ 0.808515] kvm [1]: GIC system register CPU interface enabled
10218 01:15:37.652657 <6>[ 0.814664] kvm [1]: vgic interrupt IRQ18
10219 01:15:37.659291 <6>[ 0.819025] kvm [1]: VHE mode initialized successfully
10220 01:15:37.663212 <5>[ 0.825353] Initialise system trusted keyrings
10221 01:15:37.669198 <6>[ 0.830128] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10222 01:15:37.678725 <6>[ 0.840046] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10223 01:15:37.685352 <5>[ 0.846400] NFS: Registering the id_resolver key type
10224 01:15:37.688291 <5>[ 0.851700] Key type id_resolver registered
10225 01:15:37.695389 <5>[ 0.856113] Key type id_legacy registered
10226 01:15:37.701680 <6>[ 0.860384] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10227 01:15:37.708762 <6>[ 0.867306] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10228 01:15:37.714581 <6>[ 0.875002] 9p: Installing v9fs 9p2000 file system support
10229 01:15:37.750657 <5>[ 0.912086] Key type asymmetric registered
10230 01:15:37.753929 <5>[ 0.916415] Asymmetric key parser 'x509' registered
10231 01:15:37.763723 <6>[ 0.921549] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10232 01:15:37.766901 <6>[ 0.929162] io scheduler mq-deadline registered
10233 01:15:37.770305 <6>[ 0.933922] io scheduler kyber registered
10234 01:15:37.789531 <6>[ 0.950804] EINJ: ACPI disabled.
10235 01:15:37.821273 <4>[ 0.976114] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10236 01:15:37.830943 <4>[ 0.986730] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10237 01:15:37.845729 <6>[ 1.007218] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10238 01:15:37.853387 <6>[ 1.015139] printk: console [ttyS0] disabled
10239 01:15:37.881735 <6>[ 1.039768] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10240 01:15:37.888006 <6>[ 1.049242] printk: console [ttyS0] enabled
10241 01:15:37.891428 <6>[ 1.049242] printk: console [ttyS0] enabled
10242 01:15:37.898252 <6>[ 1.058133] printk: bootconsole [mtk8250] disabled
10243 01:15:37.901494 <6>[ 1.058133] printk: bootconsole [mtk8250] disabled
10244 01:15:37.907853 <6>[ 1.069151] SuperH (H)SCI(F) driver initialized
10245 01:15:37.911397 <6>[ 1.074404] msm_serial: driver initialized
10246 01:15:37.925277 <6>[ 1.083314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10247 01:15:37.935064 <6>[ 1.091866] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10248 01:15:37.941595 <6>[ 1.100408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10249 01:15:37.951752 <6>[ 1.109035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10250 01:15:37.961748 <6>[ 1.117740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10251 01:15:37.968054 <6>[ 1.126460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10252 01:15:37.978231 <6>[ 1.135000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10253 01:15:37.984977 <6>[ 1.143798] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10254 01:15:37.994500 <6>[ 1.152339] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10255 01:15:38.005970 <6>[ 1.167736] loop: module loaded
10256 01:15:38.013096 <6>[ 1.173667] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10257 01:15:38.034654 <4>[ 1.196346] mtk-pmic-keys: Failed to locate of_node [id: -1]
10258 01:15:38.041608 <6>[ 1.203112] megasas: 07.719.03.00-rc1
10259 01:15:38.051178 <6>[ 1.212711] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10260 01:15:38.058703 <6>[ 1.220019] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10261 01:15:38.074965 <6>[ 1.236569] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10262 01:15:38.131329 <6>[ 1.285796] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10263 01:15:38.444916 <6>[ 1.606527] Freeing initrd memory: 18332K
10264 01:15:38.456606 <6>[ 1.618177] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10265 01:15:38.467403 <6>[ 1.629120] tun: Universal TUN/TAP device driver, 1.6
10266 01:15:38.470786 <6>[ 1.635172] thunder_xcv, ver 1.0
10267 01:15:38.474241 <6>[ 1.638694] thunder_bgx, ver 1.0
10268 01:15:38.477195 <6>[ 1.642189] nicpf, ver 1.0
10269 01:15:38.487897 <6>[ 1.646202] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10270 01:15:38.492089 <6>[ 1.653678] hns3: Copyright (c) 2017 Huawei Corporation.
10271 01:15:38.501466 <6>[ 1.659268] hclge is initializing
10272 01:15:38.502169 <6>[ 1.662850] e1000: Intel(R) PRO/1000 Network Driver
10273 01:15:38.507644 <6>[ 1.667979] e1000: Copyright (c) 1999-2006 Intel Corporation.
10274 01:15:38.511142 <6>[ 1.673992] e1000e: Intel(R) PRO/1000 Network Driver
10275 01:15:38.517602 <6>[ 1.679208] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10276 01:15:38.524329 <6>[ 1.685392] igb: Intel(R) Gigabit Ethernet Network Driver
10277 01:15:38.531103 <6>[ 1.691041] igb: Copyright (c) 2007-2014 Intel Corporation.
10278 01:15:38.537818 <6>[ 1.696881] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10279 01:15:38.544289 <6>[ 1.703398] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10280 01:15:38.547680 <6>[ 1.709861] sky2: driver version 1.30
10281 01:15:38.554518 <6>[ 1.714848] VFIO - User Level meta-driver version: 0.3
10282 01:15:38.561517 <6>[ 1.723065] usbcore: registered new interface driver usb-storage
10283 01:15:38.567812 <6>[ 1.729513] usbcore: registered new device driver onboard-usb-hub
10284 01:15:38.577123 <6>[ 1.738696] mt6397-rtc mt6359-rtc: registered as rtc0
10285 01:15:38.587366 <6>[ 1.744169] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:15:38 UTC (1713834938)
10286 01:15:38.590597 <6>[ 1.753780] i2c_dev: i2c /dev entries driver
10287 01:15:38.606927 <6>[ 1.765570] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10288 01:15:38.613845 <4>[ 1.774298] cpu cpu0: supply cpu not found, using dummy regulator
10289 01:15:38.620480 <4>[ 1.780719] cpu cpu1: supply cpu not found, using dummy regulator
10290 01:15:38.627243 <4>[ 1.787124] cpu cpu2: supply cpu not found, using dummy regulator
10291 01:15:38.633962 <4>[ 1.793543] cpu cpu3: supply cpu not found, using dummy regulator
10292 01:15:38.640629 <4>[ 1.799939] cpu cpu4: supply cpu not found, using dummy regulator
10293 01:15:38.647095 <4>[ 1.806335] cpu cpu5: supply cpu not found, using dummy regulator
10294 01:15:38.653751 <4>[ 1.812730] cpu cpu6: supply cpu not found, using dummy regulator
10295 01:15:38.660144 <4>[ 1.819128] cpu cpu7: supply cpu not found, using dummy regulator
10296 01:15:38.678011 <6>[ 1.839756] cpu cpu0: EM: created perf domain
10297 01:15:38.681525 <6>[ 1.844677] cpu cpu4: EM: created perf domain
10298 01:15:38.688716 <6>[ 1.850197] sdhci: Secure Digital Host Controller Interface driver
10299 01:15:38.695111 <6>[ 1.856632] sdhci: Copyright(c) Pierre Ossman
10300 01:15:38.702097 <6>[ 1.861561] Synopsys Designware Multimedia Card Interface Driver
10301 01:15:38.708564 <6>[ 1.868152] sdhci-pltfm: SDHCI platform and OF driver helper
10302 01:15:38.712064 <6>[ 1.868227] mmc0: CQHCI version 5.10
10303 01:15:38.718761 <6>[ 1.878263] ledtrig-cpu: registered to indicate activity on CPUs
10304 01:15:38.725193 <6>[ 1.885240] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10305 01:15:38.732095 <6>[ 1.892297] usbcore: registered new interface driver usbhid
10306 01:15:38.735026 <6>[ 1.898120] usbhid: USB HID core driver
10307 01:15:38.741839 <6>[ 1.902324] spi_master spi0: will run message pump with realtime priority
10308 01:15:38.786295 <6>[ 1.941295] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10309 01:15:38.804836 <6>[ 1.956018] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10310 01:15:38.807932 <6>[ 1.969609] mmc0: Command Queue Engine enabled
10311 01:15:38.814390 <6>[ 1.974380] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10312 01:15:38.821124 <6>[ 1.981340] cros-ec-spi spi0.0: Chrome EC device registered
10313 01:15:38.824246 <6>[ 1.981763] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10314 01:15:38.838876 <6>[ 2.000637] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10315 01:15:38.846516 <6>[ 2.007989] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10316 01:15:38.856620 <6>[ 2.010701] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10317 01:15:38.860101 <6>[ 2.013881] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10318 01:15:38.866400 <6>[ 2.023479] NET: Registered PF_PACKET protocol family
10319 01:15:38.872961 <6>[ 2.028389] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10320 01:15:38.876237 <6>[ 2.033125] 9pnet: Installing 9P2000 support
10321 01:15:38.883376 <5>[ 2.044164] Key type dns_resolver registered
10322 01:15:38.886297 <6>[ 2.049121] registered taskstats version 1
10323 01:15:38.892720 <5>[ 2.053502] Loading compiled-in X.509 certificates
10324 01:15:38.919905 <4>[ 2.074736] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10325 01:15:38.929656 <4>[ 2.085494] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10326 01:15:38.936508 <3>[ 2.096044] debugfs: File 'uA_load' in directory '/' already present!
10327 01:15:38.943324 <3>[ 2.102813] debugfs: File 'min_uV' in directory '/' already present!
10328 01:15:38.949902 <3>[ 2.109441] debugfs: File 'max_uV' in directory '/' already present!
10329 01:15:38.956341 <3>[ 2.116053] debugfs: File 'constraint_flags' in directory '/' already present!
10330 01:15:38.967034 <3>[ 2.125570] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10331 01:15:38.976020 <6>[ 2.137565] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10332 01:15:38.982880 <6>[ 2.144495] xhci-mtk 11200000.usb: xHCI Host Controller
10333 01:15:38.989474 <6>[ 2.149999] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10334 01:15:38.999354 <6>[ 2.157833] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10335 01:15:39.006392 <6>[ 2.167265] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10336 01:15:39.012783 <6>[ 2.173340] xhci-mtk 11200000.usb: xHCI Host Controller
10337 01:15:39.019848 <6>[ 2.178815] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10338 01:15:39.026300 <6>[ 2.186460] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10339 01:15:39.032929 <6>[ 2.194070] hub 1-0:1.0: USB hub found
10340 01:15:39.036080 <6>[ 2.198091] hub 1-0:1.0: 1 port detected
10341 01:15:39.042557 <6>[ 2.202353] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10342 01:15:39.049281 <6>[ 2.210956] hub 2-0:1.0: USB hub found
10343 01:15:39.052635 <6>[ 2.214969] hub 2-0:1.0: 1 port detected
10344 01:15:39.060023 <6>[ 2.221583] mtk-msdc 11f70000.mmc: Got CD GPIO
10345 01:15:39.072169 <6>[ 2.230334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10346 01:15:39.078849 <6>[ 2.238375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10347 01:15:39.088924 <4>[ 2.246288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10348 01:15:39.098563 <6>[ 2.255809] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10349 01:15:39.105044 <6>[ 2.263886] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10350 01:15:39.111621 <6>[ 2.271921] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10351 01:15:39.121657 <6>[ 2.279838] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10352 01:15:39.128511 <6>[ 2.287662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10353 01:15:39.137802 <6>[ 2.295477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10354 01:15:39.147814 <6>[ 2.305879] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10355 01:15:39.154908 <6>[ 2.314266] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10356 01:15:39.164584 <6>[ 2.322605] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10357 01:15:39.171052 <6>[ 2.330942] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10358 01:15:39.181576 <6>[ 2.339279] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10359 01:15:39.190910 <6>[ 2.347624] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10360 01:15:39.197801 <6>[ 2.355961] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10361 01:15:39.207525 <6>[ 2.364298] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10362 01:15:39.213847 <6>[ 2.372636] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10363 01:15:39.223646 <6>[ 2.380974] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10364 01:15:39.230278 <6>[ 2.389311] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10365 01:15:39.240357 <6>[ 2.397661] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10366 01:15:39.246787 <6>[ 2.405998] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10367 01:15:39.256894 <6>[ 2.414336] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10368 01:15:39.263826 <6>[ 2.422673] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10369 01:15:39.270290 <6>[ 2.431399] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10370 01:15:39.276976 <6>[ 2.438511] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10371 01:15:39.283702 <6>[ 2.445242] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10372 01:15:39.293727 <6>[ 2.451970] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10373 01:15:39.300150 <6>[ 2.458865] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10374 01:15:39.307002 <6>[ 2.465726] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10375 01:15:39.317013 <6>[ 2.474875] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10376 01:15:39.326404 <6>[ 2.483998] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10377 01:15:39.336410 <6>[ 2.493290] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10378 01:15:39.346436 <6>[ 2.502766] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10379 01:15:39.352979 <6>[ 2.512233] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10380 01:15:39.363114 <6>[ 2.521352] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10381 01:15:39.373428 <6>[ 2.530817] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10382 01:15:39.382939 <6>[ 2.539938] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10383 01:15:39.392615 <6>[ 2.549233] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10384 01:15:39.402705 <6>[ 2.559396] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10385 01:15:39.412327 <6>[ 2.570864] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10386 01:15:39.419406 <6>[ 2.580519] Trying to probe devices needed for running init ...
10387 01:15:39.442513 <6>[ 2.601091] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10388 01:15:39.472452 <6>[ 2.633382] hub 2-1:1.0: USB hub found
10389 01:15:39.474938 <6>[ 2.637919] hub 2-1:1.0: 3 ports detected
10390 01:15:39.484498 <6>[ 2.646035] hub 2-1:1.0: USB hub found
10391 01:15:39.487786 <6>[ 2.650588] hub 2-1:1.0: 3 ports detected
10392 01:15:39.595010 <6>[ 2.752801] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10393 01:15:39.748969 <6>[ 2.910812] hub 1-1:1.0: USB hub found
10394 01:15:39.752284 <6>[ 2.915230] hub 1-1:1.0: 4 ports detected
10395 01:15:39.761618 <6>[ 2.923193] hub 1-1:1.0: USB hub found
10396 01:15:39.764828 <6>[ 2.927563] hub 1-1:1.0: 4 ports detected
10397 01:15:39.834501 <6>[ 2.993083] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10398 01:15:40.086352 <6>[ 3.244951] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10399 01:15:40.218003 <6>[ 3.380512] hub 1-1.4:1.0: USB hub found
10400 01:15:40.221436 <6>[ 3.385192] hub 1-1.4:1.0: 2 ports detected
10401 01:15:40.230935 <6>[ 3.392814] hub 1-1.4:1.0: USB hub found
10402 01:15:40.233973 <6>[ 3.397351] hub 1-1.4:1.0: 2 ports detected
10403 01:15:40.530445 <6>[ 3.688922] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10404 01:15:40.722199 <6>[ 3.880922] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10405 01:15:51.696815 <6>[ 14.862275] ALSA device list:
10406 01:15:51.702403 <6>[ 14.865580] No soundcards found.
10407 01:15:51.710425 <6>[ 14.873302] Freeing unused kernel memory: 8448K
10408 01:15:51.713543 <6>[ 14.878354] Run /init as init process
10409 01:15:51.724088 Loading, please wait...
10410 01:15:51.749048 Starting systemd-udevd version 252.22-1~deb12u1
10411 01:15:51.749576
10412 01:15:51.961489 <6>[ 15.121219] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10413 01:15:51.971908 <6>[ 15.135250] remoteproc remoteproc0: scp is available
10414 01:15:51.979072 <6>[ 15.142229] remoteproc remoteproc0: powering up scp
10415 01:15:51.989055 <6>[ 15.147405] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10416 01:15:51.995499 <6>[ 15.148714] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10417 01:15:52.002330 <3>[ 15.150520] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10418 01:15:52.012265 <3>[ 15.150540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10419 01:15:52.018958 <3>[ 15.150547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 01:15:52.025291 <6>[ 15.155951] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10421 01:15:52.032136 <3>[ 15.164064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 01:15:52.042168 <6>[ 15.164142] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10423 01:15:52.051943 <6>[ 15.164159] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10424 01:15:52.058344 <6>[ 15.164554] usbcore: registered new device driver r8152-cfgselector
10425 01:15:52.061525 <6>[ 15.186081] mc: Linux media interface: v0.10
10426 01:15:52.071479 <3>[ 15.187984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 01:15:52.078493 <4>[ 15.194520] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10428 01:15:52.084714 <3>[ 15.201678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10429 01:15:52.092032 <3>[ 15.201719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10430 01:15:52.102077 <3>[ 15.201735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10431 01:15:52.108984 <3>[ 15.203756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10432 01:15:52.118931 <6>[ 15.209415] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10433 01:15:52.125951 <4>[ 15.211705] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10434 01:15:52.132548 <3>[ 15.219225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10435 01:15:52.142447 <4>[ 15.234850] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10436 01:15:52.145703 <4>[ 15.234850] Fallback method does not support PEC.
10437 01:15:52.155894 <3>[ 15.238297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10438 01:15:52.162434 <3>[ 15.238306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10439 01:15:52.172137 <3>[ 15.238950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10440 01:15:52.178731 <3>[ 15.261527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10441 01:15:52.188482 <3>[ 15.261880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10442 01:15:52.195024 <6>[ 15.262099] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10443 01:15:52.205242 <4>[ 15.283910] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10444 01:15:52.212032 <3>[ 15.285701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10445 01:15:52.221312 <3>[ 15.285707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10446 01:15:52.228072 <3>[ 15.285710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10447 01:15:52.234762 <6>[ 15.286026] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10448 01:15:52.241381 <6>[ 15.286031] pci_bus 0000:00: root bus resource [bus 00-ff]
10449 01:15:52.247843 <6>[ 15.286036] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10450 01:15:52.257864 <6>[ 15.286037] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10451 01:15:52.264792 <6>[ 15.286069] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10452 01:15:52.270862 <6>[ 15.286082] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10453 01:15:52.277719 <6>[ 15.286142] pci 0000:00:00.0: supports D1 D2
10454 01:15:52.284402 <6>[ 15.286144] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10455 01:15:52.291140 <6>[ 15.287030] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10456 01:15:52.298093 <6>[ 15.287097] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10457 01:15:52.307473 <6>[ 15.287120] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10458 01:15:52.314056 <6>[ 15.287135] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10459 01:15:52.320969 <6>[ 15.287151] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10460 01:15:52.324514 <6>[ 15.287251] pci 0000:01:00.0: supports D1 D2
10461 01:15:52.334413 <6>[ 15.287252] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10462 01:15:52.344519 <6>[ 15.289986] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10463 01:15:52.350646 <3>[ 15.290460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10464 01:15:52.360699 <6>[ 15.290547] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10465 01:15:52.367107 <4>[ 15.293322] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10466 01:15:52.377150 <6>[ 15.296826] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10467 01:15:52.383599 <6>[ 15.296845] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10468 01:15:52.390221 <6>[ 15.296848] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10469 01:15:52.399994 <6>[ 15.296855] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10470 01:15:52.406640 <6>[ 15.296868] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10471 01:15:52.416843 <6>[ 15.296880] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10472 01:15:52.420220 <6>[ 15.296892] pci 0000:00:00.0: PCI bridge to [bus 01]
10473 01:15:52.430386 <6>[ 15.296897] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10474 01:15:52.436470 <6>[ 15.296990] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10475 01:15:52.443081 <6>[ 15.297335] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10476 01:15:52.449817 <6>[ 15.297420] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10477 01:15:52.453138 <6>[ 15.298030] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10478 01:15:52.462861 <6>[ 15.301098] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10479 01:15:52.469675 <3>[ 15.304776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10480 01:15:52.479392 <6>[ 15.316209] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10481 01:15:52.485886 <6>[ 15.322805] remoteproc remoteproc0: remote processor scp is now up
10482 01:15:52.495995 <6>[ 15.404620] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10483 01:15:52.502567 <6>[ 15.412600] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10484 01:15:52.509020 <6>[ 15.434285] videodev: Linux video capture interface: v2.00
10485 01:15:52.515669 <5>[ 15.449214] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10486 01:15:52.519075 <6>[ 15.461567] Bluetooth: Core ver 2.22
10487 01:15:52.529146 <5>[ 15.484726] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10488 01:15:52.532427 <6>[ 15.489627] r8152 2-1.3:1.0 eth0: v1.12.13
10489 01:15:52.538797 <6>[ 15.489651] NET: Registered PF_BLUETOOTH protocol family
10490 01:15:52.545359 <6>[ 15.489654] Bluetooth: HCI device and connection manager initialized
10491 01:15:52.548610 <6>[ 15.489675] Bluetooth: HCI socket layer initialized
10492 01:15:52.555199 <6>[ 15.489679] Bluetooth: L2CAP socket layer initialized
10493 01:15:52.558657 <6>[ 15.489688] Bluetooth: SCO socket layer initialized
10494 01:15:52.565530 <6>[ 15.494786] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10495 01:15:52.575077 <5>[ 15.494987] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10496 01:15:52.584966 <4>[ 15.495085] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10497 01:15:52.588256 <6>[ 15.495095] cfg80211: failed to load regulatory.db
10498 01:15:52.594896 <6>[ 15.501109] usbcore: registered new interface driver r8152
10499 01:15:52.608403 <6>[ 15.538386] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10500 01:15:52.611387 <6>[ 15.545557] usbcore: registered new interface driver btusb
10501 01:15:52.625029 <4>[ 15.546202] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10502 01:15:52.628070 <3>[ 15.546211] Bluetooth: hci0: Failed to load firmware file (-2)
10503 01:15:52.634805 <3>[ 15.546214] Bluetooth: hci0: Failed to set up firmware (-2)
10504 01:15:52.644363 <4>[ 15.546218] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10505 01:15:52.650985 <6>[ 15.552065] usbcore: registered new interface driver uvcvideo
10506 01:15:52.657779 <6>[ 15.562015] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10507 01:15:52.664538 <6>[ 15.568377] usbcore: registered new interface driver cdc_ether
10508 01:15:52.671080 <6>[ 15.610570] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10509 01:15:52.677782 <6>[ 15.622683] usbcore: registered new interface driver r8153_ecm
10510 01:15:52.684200 <6>[ 15.631073] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10511 01:15:52.690571 <6>[ 15.667266] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10512 01:15:52.693848 <6>[ 15.691660] mt7921e 0000:01:00.0: ASIC revision: 79610010
10513 01:15:52.796349 <6>[ 15.956195] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10514 01:15:52.799649 <6>[ 15.956195]
10515 01:15:52.814522 Begin: Loading essential drivers ... done.
10516 01:15:52.817985 Begin: Running /scripts/init-premount ... done.
10517 01:15:52.824582 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10518 01:15:52.834629 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10519 01:15:52.837750 Device /sys/class/net/enx00e04c6803bd found
10520 01:15:52.838370 done.
10521 01:15:52.844274 Begin: Waiting up to 180 secs for any network device to become available ... done.
10522 01:15:52.900937 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10523 01:15:53.065934 <6>[ 16.225884] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10524 01:15:53.917672 <6>[ 17.080827] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10525 01:15:53.979864 <6>[ 17.143385] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10526 01:15:54.081081 IP-Config: no response after 2 secs - giving up
10527 01:15:54.117611 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10528 01:15:54.808395 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10529 01:15:54.812046 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10530 01:15:54.818653 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10531 01:15:54.828646 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10532 01:15:54.835359 host : mt8192-asurada-spherion-r0-cbg-4
10533 01:15:54.841557 domain : lava-rack
10534 01:15:54.844742 rootserver: 192.168.201.1 rootpath:
10535 01:15:54.845224 filename :
10536 01:15:54.944949 done.
10537 01:15:54.952545 Begin: Running /scripts/nfs-bottom ... done.
10538 01:15:54.967781 Begin: Running /scripts/init-bottom ... done.
10539 01:15:56.314184 <6>[ 19.477892] NET: Registered PF_INET6 protocol family
10540 01:15:56.322123 <6>[ 19.485510] Segment Routing with IPv6
10541 01:15:56.325155 <6>[ 19.489460] In-situ OAM (IOAM) with IPv6
10542 01:15:56.503705 <30>[ 19.640748] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10543 01:15:56.510181 <30>[ 19.673869] systemd[1]: Detected architecture arm64.
10544 01:15:56.518449
10545 01:15:56.522156 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10546 01:15:56.522619
10547 01:15:56.522984
10548 01:15:56.550852 <30>[ 19.714523] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10549 01:15:57.559097 <30>[ 20.719893] systemd[1]: Queued start job for default target graphical.target.
10550 01:15:57.609518 <30>[ 20.769807] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10551 01:15:57.615836 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10552 01:15:57.616379
10553 01:15:57.638167 <30>[ 20.798652] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10554 01:15:57.648116 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10555 01:15:57.648673
10556 01:15:57.666349 <30>[ 20.826690] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10557 01:15:57.676128 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10558 01:15:57.676689
10559 01:15:57.693999 <30>[ 20.854240] systemd[1]: Created slice user.slice - User and Session Slice.
10560 01:15:57.700630 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10561 01:15:57.701179
10562 01:15:57.724188 <30>[ 20.881237] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10563 01:15:57.730926 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10564 01:15:57.731482
10565 01:15:57.752044 <30>[ 20.909226] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10566 01:15:57.758542 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10567 01:15:57.759092
10568 01:15:57.786932 <30>[ 20.937562] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10569 01:15:57.797249 <30>[ 20.957457] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10570 01:15:57.803251 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10571 01:15:57.803705
10572 01:15:57.820077 <30>[ 20.980933] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10573 01:15:57.826925 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10574 01:15:57.827449
10575 01:15:57.844448 <30>[ 21.005057] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10576 01:15:57.854603 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10577 01:15:57.855195
10578 01:15:57.868979 <30>[ 21.033053] systemd[1]: Reached target paths.target - Path Units.
10579 01:15:57.875739 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10580 01:15:57.878997
10581 01:15:57.896809 <30>[ 21.057372] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10582 01:15:57.903431 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10583 01:15:57.903987
10584 01:15:57.916937 <30>[ 21.080911] systemd[1]: Reached target slices.target - Slice Units.
10585 01:15:57.926909 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10586 01:15:57.927463
10587 01:15:57.941712 <30>[ 21.105414] systemd[1]: Reached target swap.target - Swaps.
10588 01:15:57.948595 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10589 01:15:57.949159
10590 01:15:57.968701 <30>[ 21.129029] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10591 01:15:57.978140 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10592 01:15:57.978701
10593 01:15:57.996809 <30>[ 21.157389] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10594 01:15:58.006605 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10595 01:15:58.007156
10596 01:15:58.027640 <30>[ 21.188405] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10597 01:15:58.037451 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10598 01:15:58.038010
10599 01:15:58.054176 <30>[ 21.214393] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10600 01:15:58.063817 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10601 01:15:58.064395
10602 01:15:58.081466 <30>[ 21.241752] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10603 01:15:58.087996 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10604 01:15:58.088563
10605 01:15:58.106158 <30>[ 21.266414] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10606 01:15:58.115661 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10607 01:15:58.116222
10608 01:15:58.135584 <30>[ 21.295906] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10609 01:15:58.145385 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10610 01:15:58.145957
10611 01:15:58.161478 <30>[ 21.321423] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10612 01:15:58.170956 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10613 01:15:58.171529
10614 01:15:58.220790 <30>[ 21.381426] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10615 01:15:58.227384 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10616 01:15:58.227852
10617 01:15:58.249398 <30>[ 21.409968] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10618 01:15:58.255800 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10619 01:15:58.256340
10620 01:15:58.280390 <30>[ 21.440893] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10621 01:15:58.286800 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10622 01:15:58.287267
10623 01:15:58.311366 <30>[ 21.465327] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10624 01:15:58.365307 <30>[ 21.525784] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10625 01:15:58.374884 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10626 01:15:58.375354
10627 01:15:58.398061 <30>[ 21.558773] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10628 01:15:58.404641 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10629 01:15:58.405106
10630 01:15:58.430143 <30>[ 21.590776] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10631 01:15:58.436576 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10632 01:15:58.437044
10633 01:15:58.463775 <30>[ 21.624263] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10634 01:15:58.474511 Starting [0;1;39mmodpr<6>[ 21.634533] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10635 01:15:58.480098 obe@drm.service[0m - Load Kernel Module drm...
10636 01:15:58.480642
10637 01:15:58.537377 <30>[ 21.697665] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10638 01:15:58.546877 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10639 01:15:58.547442
10640 01:15:58.570408 <30>[ 21.730762] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10641 01:15:58.576724 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10642 01:15:58.577220
10643 01:15:58.604758 <30>[ 21.765133] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10644 01:15:58.611211 Starting [0;1;39mmodpr<6>[ 21.776182] fuse: init (API version 7.37)
10645 01:15:58.617755 obe@loop.ser…e[0m - Load Kernel Module loop...
10646 01:15:58.618273
10647 01:15:58.685179 <30>[ 21.845716] systemd[1]: Starting systemd-journald.service - Journal Service...
10648 01:15:58.691428 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10649 01:15:58.691922
10650 01:15:58.753124 <30>[ 21.913844] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10651 01:15:58.759990 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10652 01:15:58.760455
10653 01:15:58.788572 <30>[ 21.945870] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10654 01:15:58.794903 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10655 01:15:58.795327
10656 01:15:58.816493 <30>[ 21.977098] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10657 01:15:58.826098 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10658 01:15:58.826540
10659 01:15:58.850409 <30>[ 22.010935] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10660 01:15:58.860400 <3>[ 22.012431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 01:15:58.867017 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10662 01:15:58.867667
10663 01:15:58.888839 <30>[ 22.049152] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10664 01:15:58.895449 <3>[ 22.054037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 01:15:58.905098 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10666 01:15:58.905519
10667 01:15:58.925121 <30>[ 22.085345] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10668 01:15:58.935083 [[0;32m OK [<3>[ 22.094932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 01:15:58.941860 0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10670 01:15:58.942326
10671 01:15:58.964162 <3>[ 22.124601] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 01:15:58.973955 <30>[ 22.133999] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10673 01:15:58.980534 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10674 01:15:58.980957
10675 01:15:59.002418 <3>[ 22.163185] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10676 01:15:59.012619 <30>[ 22.167844] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10677 01:15:59.022255 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10678 01:15:59.022881
10679 01:15:59.037394 <30>[ 22.198142] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10680 01:15:59.043952 <3>[ 22.201432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10681 01:15:59.053879 <30>[ 22.206057] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10682 01:15:59.064568 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10683 01:15:59.064990
10684 01:15:59.074860 <3>[ 22.235651] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10685 01:15:59.085327 <30>[ 22.246204] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10686 01:15:59.092267 <30>[ 22.254175] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10687 01:15:59.108787 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 22.268042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10688 01:15:59.109306 - Load Kernel Module dm_mod.
10689 01:15:59.112095
10690 01:15:59.130148 <30>[ 22.290747] systemd[1]: modprobe@drm.service: Deactivated successfully.
10691 01:15:59.137480 <30>[ 22.298763] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10692 01:15:59.146852 <3>[ 22.300854] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10693 01:15:59.153458 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10694 01:15:59.153966
10695 01:15:59.174414 <30>[ 22.334947] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10696 01:15:59.181044 <3>[ 22.339012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 01:15:59.191269 <30>[ 22.343718] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10698 01:15:59.201058 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10699 01:15:59.201651
10700 01:15:59.218365 <30>[ 22.378964] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10701 01:15:59.225000 <30>[ 22.386686] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10702 01:15:59.234660 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10703 01:15:59.235204
10704 01:15:59.258753 <4>[ 22.412622] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10705 01:15:59.265533 <3>[ 22.428302] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10706 01:15:59.275379 <30>[ 22.429792] systemd[1]: modprobe@loop.service: Deactivated successfully.
10707 01:15:59.281951 <30>[ 22.443449] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10708 01:15:59.292007 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10709 01:15:59.292551
10710 01:15:59.308844 <30>[ 22.469552] systemd[1]: Started systemd-journald.service - Journal Service.
10711 01:15:59.315488 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10712 01:15:59.316056
10713 01:15:59.334131 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10714 01:15:59.334695
10715 01:15:59.353736 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10716 01:15:59.354461
10717 01:15:59.373756 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10718 01:15:59.374353
10719 01:15:59.393765 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10720 01:15:59.394432
10721 01:15:59.415097 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10722 01:15:59.415662
10723 01:15:59.481057 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10724 01:15:59.481606
10725 01:15:59.502233 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10726 01:15:59.502784
10727 01:15:59.522515 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10728 01:15:59.523159
10729 01:15:59.548501 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10730 01:15:59.548923
10731 01:15:59.575243 <46>[ 22.736072] systemd-journald[306]: Received client request to flush runtime journal.
10732 01:15:59.581707 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10733 01:15:59.582179
10734 01:15:59.612482 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10735 01:15:59.612911
10736 01:15:59.818952 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10737 01:15:59.819258
10738 01:15:59.836618 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10739 01:15:59.836854
10740 01:15:59.852847 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10741 01:15:59.852931
10742 01:15:59.877371 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10743 01:15:59.877454
10744 01:16:00.698772 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10745 01:16:00.698920
10746 01:16:00.740420 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10747 01:16:00.740516
10748 01:16:00.991019 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10749 01:16:00.991171
10750 01:16:01.095425 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10751 01:16:01.095978
10752 01:16:01.116929 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10753 01:16:01.117525
10754 01:16:01.136419 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10755 01:16:01.136980
10756 01:16:01.176899 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10757 01:16:01.177452
10758 01:16:01.204089 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10759 01:16:01.204648
10760 01:16:01.377545 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10761 01:16:01.378071
10762 01:16:01.433686 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10763 01:16:01.434184
10764 01:16:01.466732 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10765 01:16:01.467156
10766 01:16:01.788043 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10767 01:16:01.788559
10768 01:16:01.852718 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10769 01:16:01.852839
10770 01:16:01.873119 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10771 01:16:01.873207
10772 01:16:01.966816 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10773 01:16:01.966938
10774 01:16:01.983905 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10775 01:16:01.983992
10776 01:16:02.040311 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10777 01:16:02.040465
10778 01:16:02.065625 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10779 01:16:02.065725
10780 01:16:02.089517 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10781 01:16:02.089603
10782 01:16:02.111142 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10783 01:16:02.111690
10784 01:16:02.162872 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10785 01:16:02.163482
10786 01:16:02.204876 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10787 01:16:02.205525
10788 01:16:02.232195 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10789 01:16:02.232659
10790 01:16:02.254334 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10791 01:16:02.254426
10792 01:16:02.291193 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10793 01:16:02.291364
10794 01:16:02.308301 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10795 01:16:02.308814
10796 01:16:02.327879 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10797 01:16:02.328437
10798 01:16:02.343835 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10799 01:16:02.344301
10800 01:16:02.366203 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10801 01:16:02.366683
10802 01:16:02.391312 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10803 01:16:02.391883
10804 01:16:02.408028 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10805 01:16:02.408630
10806 01:16:02.427766 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10807 01:16:02.428412
10808 01:16:02.451694 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10809 01:16:02.452290
10810 01:16:02.471886 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10811 01:16:02.472458
10812 01:16:02.499539 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10813 01:16:02.500120
10814 01:16:02.515850 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10815 01:16:02.516421
10816 01:16:02.531920 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10817 01:16:02.532467
10818 01:16:02.577726 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10819 01:16:02.578313
10820 01:16:02.611439 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10821 01:16:02.613003
10822 01:16:02.700307 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10823 01:16:02.700654
10824 01:16:02.725468 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10825 01:16:02.726170
10826 01:16:02.910206 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10827 01:16:02.910368
10828 01:16:02.976552 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10829 01:16:02.976787
10830 01:16:02.998965 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10831 01:16:02.999093
10832 01:16:03.018910 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10833 01:16:03.019496
10834 01:16:03.038153 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10835 01:16:03.038620
10836 01:16:03.056873 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10837 01:16:03.057412
10838 01:16:03.093415 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10839 01:16:03.093975
10840 01:16:03.131465 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10841 01:16:03.132034
10842 01:16:03.149080 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10843 01:16:03.149639
10844 01:16:03.221965 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10845 01:16:03.222694
10846 01:16:03.243773 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10847 01:16:03.244327
10848 01:16:03.308603 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10849 01:16:03.309155
10850 01:16:03.372761 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10851 01:16:03.373380
10852 01:16:03.458498
10853 01:16:03.459120
10854 01:16:03.461462 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10855 01:16:03.462018
10856 01:16:03.464884 debian-bookworm-arm64 login: root (automatic login)
10857 01:16:03.465361
10858 01:16:03.465767
10859 01:16:03.702066 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
10860 01:16:03.702578
10861 01:16:03.708564 The programs included with the Debian GNU/Linux system are free software;
10862 01:16:03.715344 the exact distribution terms for each program are described in the
10863 01:16:03.718668 individual files in /usr/share/doc/*/copyright.
10864 01:16:03.719084
10865 01:16:03.725587 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10866 01:16:03.728395 permitted by applicable law.
10867 01:16:03.804574 Matched prompt #10: / #
10869 01:16:03.804822 Setting prompt string to ['/ #']
10870 01:16:03.804922 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10872 01:16:03.805124 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10873 01:16:03.805215 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
10874 01:16:03.805289 Setting prompt string to ['/ #']
10875 01:16:03.805354 Forcing a shell prompt, looking for ['/ #']
10877 01:16:03.855675 / #
10878 01:16:03.856145 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10879 01:16:03.856521 Waiting using forced prompt support (timeout 00:02:30)
10880 01:16:03.861603
10881 01:16:03.862466 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10882 01:16:03.862901 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
10884 01:16:03.964046 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj'
10885 01:16:03.970223 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468779/extract-nfsrootfs-pbe9htkj'
10887 01:16:04.071913 / # export NFS_SERVER_IP='192.168.201.1'
10888 01:16:04.078416 export NFS_SERVER_IP='192.168.201.1'
10889 01:16:04.079361 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10890 01:16:04.079889 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
10891 01:16:04.080349 end: 2 depthcharge-action (duration 00:01:25) [common]
10892 01:16:04.080855 start: 3 lava-test-retry (timeout 00:01:00) [common]
10893 01:16:04.081331 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10894 01:16:04.081749 Using namespace: common
10896 01:16:04.182985 / # #
10897 01:16:04.183630 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10898 01:16:04.189411 #
10899 01:16:04.190294 Using /lava-13468779
10901 01:16:04.291461 / # export SHELL=/bin/sh
10902 01:16:04.297635 export SHELL=/bin/sh
10904 01:16:04.399320 / # . /lava-13468779/environment
10905 01:16:04.405578 . /lava-13468779/environment
10907 01:16:04.512750 / # /lava-13468779/bin/lava-test-runner /lava-13468779/0
10908 01:16:04.513404 Test shell timeout: 10s (minimum of the action and connection timeout)
10909 01:16:04.518912 /lava-13468779/bin/lava-test-runner /lava-13468779/0
10910 01:16:04.563571 <46>[ 27.727914] systemd-journald[306]: Time jumped backwards, rotating.
10911 01:16:06.100941 + export TESTRUN_ID=0_dmesg
10912 01:16:06.104608 + cd /lava-13468779/0/tests/0_dmesg
10913 01:16:06.107637 + cat uuid
10914 01:16:06.114363 + UUID=13468779_1.<8>[ 29.278186] <LAVA_SIGNAL_STARTRUN 0_dmesg 13468779_1.6.2.3.1>
10915 01:16:06.114920 Received signal: <STARTRUN> 0_dmesg 13468779_1.6.2.3.1
10916 01:16:06.115183 Starting test lava.0_dmesg (13468779_1.6.2.3.1)
10917 01:16:06.115473 Skipping test definition patterns.
10918 01:16:06.117667 6.2.3.1
10919 01:16:06.117971 + set +x
10920 01:16:06.120820 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10921 01:16:06.211645 <8>[ 29.373053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10922 01:16:06.212504 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10924 01:16:06.281695 <8>[ 29.443288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10925 01:16:06.282664 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10927 01:16:06.351402 <8>[ 29.513080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10928 01:16:06.352199 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10930 01:16:06.355117 + set +x
10931 01:16:06.357940 <8>[ 29.522857] <LAVA_SIGNAL_ENDRUN 0_dmesg 13468779_1.6.2.3.1>
10932 01:16:06.358757 Received signal: <ENDRUN> 0_dmesg 13468779_1.6.2.3.1
10933 01:16:06.359271 Ending use of test pattern.
10934 01:16:06.359701 Ending test lava.0_dmesg (13468779_1.6.2.3.1), duration 0.24
10936 01:16:06.368083 <LAVA_TEST_RUNNER EXIT>
10937 01:16:06.368801 ok: lava_test_shell seems to have completed
10938 01:16:06.369390 alert: pass
crit: pass
emerg: pass
10939 01:16:06.369808 end: 3.1 lava-test-shell (duration 00:00:02) [common]
10940 01:16:06.370271 end: 3 lava-test-retry (duration 00:00:02) [common]
10941 01:16:06.370696 start: 4 finalize (timeout 00:08:08) [common]
10942 01:16:06.371151 start: 4.1 power-off (timeout 00:00:30) [common]
10943 01:16:06.371975 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10944 01:16:06.498930 >> Command sent successfully.
10945 01:16:06.503334 Returned 0 in 0 seconds
10946 01:16:06.604241 end: 4.1 power-off (duration 00:00:00) [common]
10948 01:16:06.605891 start: 4.2 read-feedback (timeout 00:08:08) [common]
10949 01:16:06.607338 Listened to connection for namespace 'common' for up to 1s
10950 01:16:07.607950 Finalising connection for namespace 'common'
10951 01:16:07.608641 Disconnecting from shell: Finalise
10952 01:16:07.609052 / #
10953 01:16:07.710142 end: 4.2 read-feedback (duration 00:00:01) [common]
10954 01:16:07.710862 end: 4 finalize (duration 00:00:01) [common]
10955 01:16:07.711497 Cleaning after the job
10956 01:16:07.712027 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/ramdisk
10957 01:16:07.722390 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/kernel
10958 01:16:07.756043 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/dtb
10959 01:16:07.756366 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/nfsrootfs
10960 01:16:07.819672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468779/tftp-deploy-xr4cs4k4/modules
10961 01:16:07.825296 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468779
10962 01:16:08.140564 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468779
10963 01:16:08.140741 Job finished correctly