Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 01:25:06.113541 lava-dispatcher, installed at version: 2024.01
2 01:25:06.113762 start: 0 validate
3 01:25:06.113969 Start time: 2024-04-23 01:25:06.113959+00:00 (UTC)
4 01:25:06.114186 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:25:06.114381 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:25:06.369327 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:25:06.369508 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 01:25:06.622189 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:25:06.622399 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 01:25:06.875924 Using caching service: 'http://localhost/cache/?uri=%s'
11 01:25:06.876097 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:25:07.128649 Using caching service: 'http://localhost/cache/?uri=%s'
13 01:25:07.128817 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19-44-g09a10637e8de%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 01:25:07.382342 validate duration: 1.27
16 01:25:07.382624 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:25:07.382729 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:25:07.382817 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:25:07.382945 Not decompressing ramdisk as can be used compressed.
20 01:25:07.383031 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 01:25:07.383103 saving as /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/ramdisk/initrd.cpio.gz
22 01:25:07.383170 total size: 5628169 (5 MB)
23 01:25:07.384283 progress 0 % (0 MB)
24 01:25:07.385892 progress 5 % (0 MB)
25 01:25:07.387546 progress 10 % (0 MB)
26 01:25:07.388977 progress 15 % (0 MB)
27 01:25:07.390717 progress 20 % (1 MB)
28 01:25:07.392306 progress 25 % (1 MB)
29 01:25:07.394091 progress 30 % (1 MB)
30 01:25:07.395906 progress 35 % (1 MB)
31 01:25:07.397402 progress 40 % (2 MB)
32 01:25:07.399152 progress 45 % (2 MB)
33 01:25:07.400694 progress 50 % (2 MB)
34 01:25:07.402571 progress 55 % (2 MB)
35 01:25:07.404156 progress 60 % (3 MB)
36 01:25:07.405599 progress 65 % (3 MB)
37 01:25:07.407252 progress 70 % (3 MB)
38 01:25:07.408796 progress 75 % (4 MB)
39 01:25:07.410421 progress 80 % (4 MB)
40 01:25:07.412004 progress 85 % (4 MB)
41 01:25:07.413631 progress 90 % (4 MB)
42 01:25:07.415351 progress 95 % (5 MB)
43 01:25:07.416773 progress 100 % (5 MB)
44 01:25:07.416991 5 MB downloaded in 0.03 s (158.71 MB/s)
45 01:25:07.417149 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:25:07.417443 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:25:07.417530 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:25:07.417624 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:25:07.417763 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 01:25:07.417837 saving as /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/kernel/Image
52 01:25:07.417898 total size: 54352384 (51 MB)
53 01:25:07.417966 No compression specified
54 01:25:07.419102 progress 0 % (0 MB)
55 01:25:07.433621 progress 5 % (2 MB)
56 01:25:07.448940 progress 10 % (5 MB)
57 01:25:07.463983 progress 15 % (7 MB)
58 01:25:07.479208 progress 20 % (10 MB)
59 01:25:07.494684 progress 25 % (12 MB)
60 01:25:07.511049 progress 30 % (15 MB)
61 01:25:07.528039 progress 35 % (18 MB)
62 01:25:07.550683 progress 40 % (20 MB)
63 01:25:07.565250 progress 45 % (23 MB)
64 01:25:07.579805 progress 50 % (25 MB)
65 01:25:07.594377 progress 55 % (28 MB)
66 01:25:07.608838 progress 60 % (31 MB)
67 01:25:07.623289 progress 65 % (33 MB)
68 01:25:07.637803 progress 70 % (36 MB)
69 01:25:07.652255 progress 75 % (38 MB)
70 01:25:07.666532 progress 80 % (41 MB)
71 01:25:07.681178 progress 85 % (44 MB)
72 01:25:07.696421 progress 90 % (46 MB)
73 01:25:07.710804 progress 95 % (49 MB)
74 01:25:07.724985 progress 100 % (51 MB)
75 01:25:07.725252 51 MB downloaded in 0.31 s (168.65 MB/s)
76 01:25:07.725416 end: 1.2.1 http-download (duration 00:00:00) [common]
78 01:25:07.725672 end: 1.2 download-retry (duration 00:00:00) [common]
79 01:25:07.725762 start: 1.3 download-retry (timeout 00:10:00) [common]
80 01:25:07.725858 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 01:25:07.726002 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 01:25:07.726073 saving as /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/dtb/mt8192-asurada-spherion-r0.dtb
83 01:25:07.726136 total size: 47230 (0 MB)
84 01:25:07.726206 No compression specified
85 01:25:07.727348 progress 69 % (0 MB)
86 01:25:07.727638 progress 100 % (0 MB)
87 01:25:07.727802 0 MB downloaded in 0.00 s (27.07 MB/s)
88 01:25:07.727935 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:25:07.728167 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:25:07.728254 start: 1.4 download-retry (timeout 00:10:00) [common]
92 01:25:07.728344 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 01:25:07.728460 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 01:25:07.728535 saving as /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/nfsrootfs/full.rootfs.tar
95 01:25:07.728597 total size: 120894716 (115 MB)
96 01:25:07.728659 Using unxz to decompress xz
97 01:25:07.732702 progress 0 % (0 MB)
98 01:25:08.100177 progress 5 % (5 MB)
99 01:25:08.489536 progress 10 % (11 MB)
100 01:25:08.870500 progress 15 % (17 MB)
101 01:25:09.230653 progress 20 % (23 MB)
102 01:25:09.543473 progress 25 % (28 MB)
103 01:25:09.943642 progress 30 % (34 MB)
104 01:25:10.312464 progress 35 % (40 MB)
105 01:25:10.481316 progress 40 % (46 MB)
106 01:25:10.662635 progress 45 % (51 MB)
107 01:25:10.984891 progress 50 % (57 MB)
108 01:25:11.374148 progress 55 % (63 MB)
109 01:25:11.732781 progress 60 % (69 MB)
110 01:25:12.098489 progress 65 % (74 MB)
111 01:25:12.470107 progress 70 % (80 MB)
112 01:25:12.857726 progress 75 % (86 MB)
113 01:25:13.228903 progress 80 % (92 MB)
114 01:25:13.598600 progress 85 % (98 MB)
115 01:25:13.986423 progress 90 % (103 MB)
116 01:25:14.343526 progress 95 % (109 MB)
117 01:25:14.713095 progress 100 % (115 MB)
118 01:25:14.718651 115 MB downloaded in 6.99 s (16.49 MB/s)
119 01:25:14.718932 end: 1.4.1 http-download (duration 00:00:07) [common]
121 01:25:14.719205 end: 1.4 download-retry (duration 00:00:07) [common]
122 01:25:14.719300 start: 1.5 download-retry (timeout 00:09:53) [common]
123 01:25:14.719393 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 01:25:14.719547 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 01:25:14.719621 saving as /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/modules/modules.tar
126 01:25:14.719688 total size: 8638160 (8 MB)
127 01:25:14.719754 Using unxz to decompress xz
128 01:25:14.724027 progress 0 % (0 MB)
129 01:25:14.743993 progress 5 % (0 MB)
130 01:25:14.768809 progress 10 % (0 MB)
131 01:25:14.793329 progress 15 % (1 MB)
132 01:25:14.818462 progress 20 % (1 MB)
133 01:25:14.844469 progress 25 % (2 MB)
134 01:25:14.870334 progress 30 % (2 MB)
135 01:25:14.894548 progress 35 % (2 MB)
136 01:25:14.920918 progress 40 % (3 MB)
137 01:25:14.945404 progress 45 % (3 MB)
138 01:25:14.970425 progress 50 % (4 MB)
139 01:25:14.995240 progress 55 % (4 MB)
140 01:25:15.023592 progress 60 % (4 MB)
141 01:25:15.048945 progress 65 % (5 MB)
142 01:25:15.074196 progress 70 % (5 MB)
143 01:25:15.098751 progress 75 % (6 MB)
144 01:25:15.123964 progress 80 % (6 MB)
145 01:25:15.152349 progress 85 % (7 MB)
146 01:25:15.179120 progress 90 % (7 MB)
147 01:25:15.208396 progress 95 % (7 MB)
148 01:25:15.235000 progress 100 % (8 MB)
149 01:25:15.240801 8 MB downloaded in 0.52 s (15.81 MB/s)
150 01:25:15.241075 end: 1.5.1 http-download (duration 00:00:01) [common]
152 01:25:15.241351 end: 1.5 download-retry (duration 00:00:01) [common]
153 01:25:15.241446 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 01:25:15.241548 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 01:25:19.308021 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4
156 01:25:19.308244 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 01:25:19.308357 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 01:25:19.308553 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp
159 01:25:19.308702 makedir: /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin
160 01:25:19.308818 makedir: /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/tests
161 01:25:19.308953 makedir: /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/results
162 01:25:19.309058 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-add-keys
163 01:25:19.309239 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-add-sources
164 01:25:19.309388 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-background-process-start
165 01:25:19.309534 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-background-process-stop
166 01:25:19.309676 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-common-functions
167 01:25:19.309856 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-echo-ipv4
168 01:25:19.310028 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-install-packages
169 01:25:19.310169 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-installed-packages
170 01:25:19.310304 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-os-build
171 01:25:19.310452 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-probe-channel
172 01:25:19.310576 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-probe-ip
173 01:25:19.310701 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-target-ip
174 01:25:19.310825 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-target-mac
175 01:25:19.310949 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-target-storage
176 01:25:19.311100 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-case
177 01:25:19.311240 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-event
178 01:25:19.311380 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-feedback
179 01:25:19.311519 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-raise
180 01:25:19.311652 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-reference
181 01:25:19.311806 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-runner
182 01:25:19.311944 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-set
183 01:25:19.312078 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-test-shell
184 01:25:19.312208 Updating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-add-keys (debian)
185 01:25:19.312378 Updating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-add-sources (debian)
186 01:25:19.312535 Updating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-install-packages (debian)
187 01:25:19.312690 Updating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-installed-packages (debian)
188 01:25:19.312840 Updating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/bin/lava-os-build (debian)
189 01:25:19.312965 Creating /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/environment
190 01:25:19.313127 LAVA metadata
191 01:25:19.313222 - LAVA_JOB_ID=13468775
192 01:25:19.313287 - LAVA_DISPATCHER_IP=192.168.201.1
193 01:25:19.313429 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 01:25:19.313498 skipped lava-vland-overlay
195 01:25:19.313589 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 01:25:19.313670 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 01:25:19.313732 skipped lava-multinode-overlay
198 01:25:19.313817 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 01:25:19.313895 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 01:25:19.313983 Loading test definitions
201 01:25:19.314072 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 01:25:19.314159 Using /lava-13468775 at stage 0
203 01:25:19.314487 uuid=13468775_1.6.2.3.1 testdef=None
204 01:25:19.314596 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 01:25:19.314681 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 01:25:19.315155 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 01:25:19.315393 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 01:25:19.316030 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 01:25:19.316280 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 01:25:19.316949 runner path: /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/0/tests/0_timesync-off test_uuid 13468775_1.6.2.3.1
213 01:25:19.317130 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 01:25:19.317367 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 01:25:19.317450 Using /lava-13468775 at stage 0
217 01:25:19.317548 Fetching tests from https://github.com/kernelci/test-definitions.git
218 01:25:19.317654 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/0/tests/1_kselftest-alsa'
219 01:25:21.689978 Running '/usr/bin/git checkout kernelci.org
220 01:25:21.842110 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 01:25:21.842899 uuid=13468775_1.6.2.3.5 testdef=None
222 01:25:21.843064 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 01:25:21.843408 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 01:25:21.844658 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 01:25:21.845041 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 01:25:21.846546 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 01:25:21.846796 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 01:25:21.848302 runner path: /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/0/tests/1_kselftest-alsa test_uuid 13468775_1.6.2.3.5
232 01:25:21.848427 BOARD='mt8192-asurada-spherion-r0'
233 01:25:21.848522 BRANCH='cip'
234 01:25:21.848616 SKIPFILE='/dev/null'
235 01:25:21.848705 SKIP_INSTALL='True'
236 01:25:21.848798 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 01:25:21.848887 TST_CASENAME=''
238 01:25:21.848977 TST_CMDFILES='alsa'
239 01:25:21.849167 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 01:25:21.849447 Creating lava-test-runner.conf files
242 01:25:21.849513 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13468775/lava-overlay-7nbyamkp/lava-13468775/0 for stage 0
243 01:25:21.849616 - 0_timesync-off
244 01:25:21.849690 - 1_kselftest-alsa
245 01:25:21.849810 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 01:25:21.849934 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 01:25:29.715746 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 01:25:29.715925 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 01:25:29.716023 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 01:25:29.716153 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 01:25:29.716279 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 01:25:29.893167 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 01:25:29.893574 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 01:25:29.893693 extracting modules file /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4
255 01:25:30.178668 extracting modules file /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13468775/extract-overlay-ramdisk-39au0p8p/ramdisk
256 01:25:30.416584 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 01:25:30.416765 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 01:25:30.416862 [common] Applying overlay to NFS
259 01:25:30.416934 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13468775/compress-overlay-6v8lzxyx/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4
260 01:25:31.347613 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 01:25:31.347792 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 01:25:31.347891 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 01:25:31.347979 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 01:25:31.348058 Building ramdisk /var/lib/lava/dispatcher/tmp/13468775/extract-overlay-ramdisk-39au0p8p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13468775/extract-overlay-ramdisk-39au0p8p/ramdisk
265 01:25:31.664156 >> 130624 blocks
266 01:25:33.871543 rename /var/lib/lava/dispatcher/tmp/13468775/extract-overlay-ramdisk-39au0p8p/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/ramdisk/ramdisk.cpio.gz
267 01:25:33.871996 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 01:25:33.872119 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 01:25:33.872242 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 01:25:33.872362 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/kernel/Image'
271 01:25:48.451995 Returned 0 in 14 seconds
272 01:25:48.552696 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/kernel/image.itb
273 01:25:48.908204 output: FIT description: Kernel Image image with one or more FDT blobs
274 01:25:48.908630 output: Created: Tue Apr 23 02:25:48 2024
275 01:25:48.908714 output: Image 0 (kernel-1)
276 01:25:48.908784 output: Description:
277 01:25:48.908848 output: Created: Tue Apr 23 02:25:48 2024
278 01:25:48.908910 output: Type: Kernel Image
279 01:25:48.908972 output: Compression: lzma compressed
280 01:25:48.909032 output: Data Size: 12910050 Bytes = 12607.47 KiB = 12.31 MiB
281 01:25:48.909094 output: Architecture: AArch64
282 01:25:48.909151 output: OS: Linux
283 01:25:48.909207 output: Load Address: 0x00000000
284 01:25:48.909265 output: Entry Point: 0x00000000
285 01:25:48.909322 output: Hash algo: crc32
286 01:25:48.909382 output: Hash value: 1126c3f9
287 01:25:48.909443 output: Image 1 (fdt-1)
288 01:25:48.909502 output: Description: mt8192-asurada-spherion-r0
289 01:25:48.909557 output: Created: Tue Apr 23 02:25:48 2024
290 01:25:48.909612 output: Type: Flat Device Tree
291 01:25:48.909667 output: Compression: uncompressed
292 01:25:48.909722 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 01:25:48.909777 output: Architecture: AArch64
294 01:25:48.909831 output: Hash algo: crc32
295 01:25:48.909885 output: Hash value: 4bf0d1ac
296 01:25:48.909940 output: Image 2 (ramdisk-1)
297 01:25:48.909994 output: Description: unavailable
298 01:25:48.910049 output: Created: Tue Apr 23 02:25:48 2024
299 01:25:48.910103 output: Type: RAMDisk Image
300 01:25:48.910158 output: Compression: Unknown Compression
301 01:25:48.910213 output: Data Size: 18777760 Bytes = 18337.66 KiB = 17.91 MiB
302 01:25:48.910268 output: Architecture: AArch64
303 01:25:48.910333 output: OS: Linux
304 01:25:48.910388 output: Load Address: unavailable
305 01:25:48.910442 output: Entry Point: unavailable
306 01:25:48.910496 output: Hash algo: crc32
307 01:25:48.910550 output: Hash value: 519bf395
308 01:25:48.910603 output: Default Configuration: 'conf-1'
309 01:25:48.910657 output: Configuration 0 (conf-1)
310 01:25:48.910711 output: Description: mt8192-asurada-spherion-r0
311 01:25:48.910766 output: Kernel: kernel-1
312 01:25:48.910820 output: Init Ramdisk: ramdisk-1
313 01:25:48.910874 output: FDT: fdt-1
314 01:25:48.910929 output: Loadables: kernel-1
315 01:25:48.910983 output:
316 01:25:48.911186 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 01:25:48.911288 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 01:25:48.911396 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 01:25:48.911495 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 01:25:48.911583 No LXC device requested
321 01:25:48.911665 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 01:25:48.911754 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 01:25:48.911835 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 01:25:48.911905 Checking files for TFTP limit of 4294967296 bytes.
325 01:25:48.912419 end: 1 tftp-deploy (duration 00:00:42) [common]
326 01:25:48.912530 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 01:25:48.912629 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 01:25:48.912763 substitutions:
329 01:25:48.912831 - {DTB}: 13468775/tftp-deploy-kqdu6js6/dtb/mt8192-asurada-spherion-r0.dtb
330 01:25:48.912898 - {INITRD}: 13468775/tftp-deploy-kqdu6js6/ramdisk/ramdisk.cpio.gz
331 01:25:48.912960 - {KERNEL}: 13468775/tftp-deploy-kqdu6js6/kernel/Image
332 01:25:48.913020 - {LAVA_MAC}: None
333 01:25:48.913079 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4
334 01:25:48.913136 - {NFS_SERVER_IP}: 192.168.201.1
335 01:25:48.913194 - {PRESEED_CONFIG}: None
336 01:25:48.913250 - {PRESEED_LOCAL}: None
337 01:25:48.913306 - {RAMDISK}: 13468775/tftp-deploy-kqdu6js6/ramdisk/ramdisk.cpio.gz
338 01:25:48.913362 - {ROOT_PART}: None
339 01:25:48.913422 - {ROOT}: None
340 01:25:48.913478 - {SERVER_IP}: 192.168.201.1
341 01:25:48.913577 - {TEE}: None
342 01:25:48.913671 Parsed boot commands:
343 01:25:48.913761 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 01:25:48.914008 Parsed boot commands: tftpboot 192.168.201.1 13468775/tftp-deploy-kqdu6js6/kernel/image.itb 13468775/tftp-deploy-kqdu6js6/kernel/cmdline
345 01:25:48.914109 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 01:25:48.914203 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 01:25:48.914299 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 01:25:48.914401 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 01:25:48.914479 Not connected, no need to disconnect.
350 01:25:48.914556 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 01:25:48.914639 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 01:25:48.914711 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 01:25:48.918753 Setting prompt string to ['lava-test: # ']
354 01:25:48.919214 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 01:25:48.919342 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 01:25:48.919445 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 01:25:48.919544 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 01:25:48.919760 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 01:25:54.052033 >> Command sent successfully.
360 01:25:54.054683 Returned 0 in 5 seconds
361 01:25:54.155085 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 01:25:54.155404 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 01:25:54.155505 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 01:25:54.155594 Setting prompt string to 'Starting depthcharge on Spherion...'
366 01:25:54.155665 Changing prompt to 'Starting depthcharge on Spherion...'
367 01:25:54.155735 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 01:25:54.156049 [Enter `^Ec?' for help]
369 01:25:54.327461
370 01:25:54.327608
371 01:25:54.327686 F0: 102B 0000
372 01:25:54.327755
373 01:25:54.327819 F3: 1001 0000 [0200]
374 01:25:54.327879
375 01:25:54.331027 F3: 1001 0000
376 01:25:54.331112
377 01:25:54.331181 F7: 102D 0000
378 01:25:54.331244
379 01:25:54.331304 F1: 0000 0000
380 01:25:54.331364
381 01:25:54.334327 V0: 0000 0000 [0001]
382 01:25:54.334428
383 01:25:54.334495 00: 0007 8000
384 01:25:54.334561
385 01:25:54.338296 01: 0000 0000
386 01:25:54.338404
387 01:25:54.338470 BP: 0C00 0209 [0000]
388 01:25:54.338532
389 01:25:54.338592 G0: 1182 0000
390 01:25:54.341728
391 01:25:54.341811 EC: 0000 0021 [4000]
392 01:25:54.341877
393 01:25:54.345779 S7: 0000 0000 [0000]
394 01:25:54.345864
395 01:25:54.345930 CC: 0000 0000 [0001]
396 01:25:54.345992
397 01:25:54.349241 T0: 0000 0040 [010F]
398 01:25:54.349325
399 01:25:54.349391 Jump to BL
400 01:25:54.349452
401 01:25:54.373945
402 01:25:54.374043
403 01:25:54.374111
404 01:25:54.381720 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 01:25:57.007232 ARM64: Exception handlers installed.
406 01:25:57.397638 ARM64: Testing exception
407 01:25:57.398073 ARM64: Done test exception
408 01:25:57.398430 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 01:25:57.398669 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 01:25:57.398884 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 01:25:57.399089 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 01:25:57.399292 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 01:25:57.399489 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 01:25:57.399690 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 01:25:57.399886 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 01:25:57.400082 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 01:25:57.400277 WDT: Last reset was cold boot
418 01:25:57.400470 SPI1(PAD0) initialized at 2873684 Hz
419 01:25:57.400750 SPI5(PAD0) initialized at 992727 Hz
420 01:25:57.401041 VBOOT: Loading verstage.
421 01:25:57.401294 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 01:25:57.401623 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 01:25:57.401895 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 01:25:57.402233 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 01:25:57.402522 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 01:25:57.402789 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 01:25:57.403004 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 01:25:57.403081
429 01:25:57.403175
430 01:25:57.403271 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 01:25:57.403367 ARM64: Exception handlers installed.
432 01:25:57.403462 ARM64: Testing exception
433 01:25:57.403557 ARM64: Done test exception
434 01:25:57.403652 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 01:25:57.403748 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 01:25:57.403843 Probing TPM: . done!
437 01:25:57.403938 TPM ready after 0 ms
438 01:25:57.404033 Connected to device vid:did:rid of 1ae0:0028:00
439 01:25:57.404129 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 01:25:57.404224 Initialized TPM device CR50 revision 0
441 01:25:57.404319 tlcl_send_startup: Startup return code is 0
442 01:25:57.404414 TPM: setup succeeded
443 01:25:57.404509 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 01:25:57.404604 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 01:25:57.404699 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 01:25:57.404794 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 01:25:57.404889 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 01:25:57.404984 in-header: 03 07 00 00 08 00 00 00
449 01:25:57.405078 in-data: aa e4 47 04 13 02 00 00
450 01:25:57.405171 Chrome EC: UHEPI supported
451 01:25:57.405266 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 01:25:57.405360 in-header: 03 95 00 00 08 00 00 00
453 01:25:57.405453 in-data: 18 20 20 08 00 00 00 00
454 01:25:57.405547 Phase 1
455 01:25:57.405641 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 01:25:57.405735 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 01:25:57.405829 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 01:25:57.405923 Recovery requested (1009000e)
459 01:25:57.406017 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 01:25:57.406111 tlcl_extend: response is 0
461 01:25:57.406205 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 01:25:57.406299 tlcl_extend: response is 0
463 01:25:57.406429 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 01:25:57.406524 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 01:25:57.406618 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 01:25:57.406713
467 01:25:57.406807
468 01:25:57.406900 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 01:25:57.406996 ARM64: Exception handlers installed.
470 01:25:57.407091 ARM64: Testing exception
471 01:25:57.407184 ARM64: Done test exception
472 01:25:57.407278 pmic_efuse_setting: Set efuses in 11 msecs
473 01:25:57.407371 pmwrap_interface_init: Select PMIF_VLD_RDY
474 01:25:57.407465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 01:25:57.407559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 01:25:57.407653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 01:25:57.407746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 01:25:57.407839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 01:25:57.407933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 01:25:57.408028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 01:25:57.408122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 01:25:57.408215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 01:25:57.408308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 01:25:57.408402 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 01:25:57.408713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 01:25:57.408823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 01:25:57.408920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 01:25:57.409016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 01:25:57.409112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 01:25:57.409206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 01:25:57.409301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 01:25:57.409395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 01:25:57.409489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 01:25:57.409583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 01:25:57.409677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 01:25:57.409770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 01:25:57.409893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 01:25:57.409987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 01:25:57.410081 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 01:25:57.410175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 01:25:57.410269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 01:25:57.410401 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 01:25:57.410495 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 01:25:57.410590 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 01:25:57.410684 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 01:25:57.410793 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 01:25:57.410903 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 01:25:57.410996 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 01:25:57.411090 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 01:25:57.411183 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 01:25:57.411277 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 01:25:57.411408 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 01:25:57.411532 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 01:25:57.411657 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 01:25:57.411751 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 01:25:57.411844 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 01:25:57.411938 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 01:25:57.412030 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 01:25:57.412124 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 01:25:57.412217 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 01:25:57.412310 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 01:25:57.412403 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 01:25:57.412495 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 01:25:57.412589 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 01:25:57.412682 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 01:25:57.412777 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 01:25:57.412871 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 01:25:57.412964 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 01:25:57.413058 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 01:25:57.413152 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 01:25:57.413245 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 01:25:57.413363 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 01:25:57.413521 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
534 01:25:57.413627 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 01:25:57.413713 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 01:25:57.413799 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 01:25:57.413884 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 01:25:57.413968 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 01:25:57.414053 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 01:25:57.414138 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 01:25:57.414222 [RTC]rtc_get_frequency_meter,154: input=16, output=781
542 01:25:57.414312 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 01:25:57.414431 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 01:25:57.414519 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 01:25:57.414612 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 01:25:57.414705 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 01:25:57.414798 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 01:25:57.414891 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 01:25:57.414984 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 01:25:57.415077 ADC[4]: Raw value=906942 ID=7
551 01:25:57.415170 ADC[3]: Raw value=213810 ID=1
552 01:25:57.415263 RAM Code: 0x71
553 01:25:57.415356 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 01:25:57.415450 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 01:25:57.415544 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 01:25:57.415852 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 01:25:57.415956 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 01:25:57.416053 in-header: 03 07 00 00 08 00 00 00
559 01:25:57.416149 in-data: aa e4 47 04 13 02 00 00
560 01:25:57.416245 Chrome EC: UHEPI supported
561 01:25:57.416341 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 01:25:57.416436 in-header: 03 95 00 00 08 00 00 00
563 01:25:57.416531 in-data: 18 20 20 08 00 00 00 00
564 01:25:57.416626 MRC: failed to locate region type 0.
565 01:25:57.416721 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 01:25:57.416815 DRAM-K: Running full calibration
567 01:25:57.416908 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 01:25:57.417002 header.status = 0x0
569 01:25:57.417096 header.version = 0x6 (expected: 0x6)
570 01:25:57.417190 header.size = 0xd00 (expected: 0xd00)
571 01:25:57.417284 header.flags = 0x0
572 01:25:57.417377 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 01:25:57.417472 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 01:25:57.417566 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 01:25:57.417660 dram_init: ddr_geometry: 2
576 01:25:57.417754 [EMI] MDL number = 2
577 01:25:57.417847 [EMI] Get MDL freq = 0
578 01:25:57.417941 dram_init: ddr_type: 0
579 01:25:57.418034 is_discrete_lpddr4: 1
580 01:25:57.418127 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 01:25:57.418220
582 01:25:57.418338
583 01:25:57.418447 [Bian_co] ETT version 0.0.0.1
584 01:25:57.418541 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 01:25:57.418635
586 01:25:57.418729 dramc_set_vcore_voltage set vcore to 650000
587 01:25:57.418822 Read voltage for 800, 4
588 01:25:57.418914 Vio18 = 0
589 01:25:57.419007 Vcore = 650000
590 01:25:57.419100 Vdram = 0
591 01:25:57.419192 Vddq = 0
592 01:25:57.419284 Vmddr = 0
593 01:25:57.419376 dram_init: config_dvfs: 1
594 01:25:57.419470 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 01:25:57.419563 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 01:25:57.419657 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 01:25:57.419750 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 01:25:57.419843 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 01:25:57.419936 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 01:25:57.420029 MEM_TYPE=3, freq_sel=18
601 01:25:57.420121 sv_algorithm_assistance_LP4_1600
602 01:25:57.420214 ============ PULL DRAM RESETB DOWN ============
603 01:25:57.420310 ========== PULL DRAM RESETB DOWN end =========
604 01:25:57.420405 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 01:25:57.420499 ===================================
606 01:25:57.420592 LPDDR4 DRAM CONFIGURATION
607 01:25:57.420685 ===================================
608 01:25:57.420778 EX_ROW_EN[0] = 0x0
609 01:25:57.420871 EX_ROW_EN[1] = 0x0
610 01:25:57.420963 LP4Y_EN = 0x0
611 01:25:57.421056 WORK_FSP = 0x0
612 01:25:57.421148 WL = 0x2
613 01:25:57.421240 RL = 0x2
614 01:25:57.421333 BL = 0x2
615 01:25:57.421425 RPST = 0x0
616 01:25:57.421518 RD_PRE = 0x0
617 01:25:57.421610 WR_PRE = 0x1
618 01:25:57.421702 WR_PST = 0x0
619 01:25:57.421794 DBI_WR = 0x0
620 01:25:57.421886 DBI_RD = 0x0
621 01:25:57.421978 OTF = 0x1
622 01:25:57.422071 ===================================
623 01:25:57.422163 ===================================
624 01:25:57.422257 ANA top config
625 01:25:57.422396 ===================================
626 01:25:57.422492 DLL_ASYNC_EN = 0
627 01:25:57.422586 ALL_SLAVE_EN = 1
628 01:25:57.422679 NEW_RANK_MODE = 1
629 01:25:57.422774 DLL_IDLE_MODE = 1
630 01:25:57.422867 LP45_APHY_COMB_EN = 1
631 01:25:57.422960 TX_ODT_DIS = 1
632 01:25:57.423053 NEW_8X_MODE = 1
633 01:25:57.423147 ===================================
634 01:25:57.423240 ===================================
635 01:25:57.423335 data_rate = 1600
636 01:25:57.423428 CKR = 1
637 01:25:57.423520 DQ_P2S_RATIO = 8
638 01:25:57.423613 ===================================
639 01:25:57.423706 CA_P2S_RATIO = 8
640 01:25:57.423799 DQ_CA_OPEN = 0
641 01:25:57.423891 DQ_SEMI_OPEN = 0
642 01:25:57.423983 CA_SEMI_OPEN = 0
643 01:25:57.424075 CA_FULL_RATE = 0
644 01:25:57.424168 DQ_CKDIV4_EN = 1
645 01:25:57.424260 CA_CKDIV4_EN = 1
646 01:25:57.424352 CA_PREDIV_EN = 0
647 01:25:57.424444 PH8_DLY = 0
648 01:25:57.424537 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 01:25:57.424629 DQ_AAMCK_DIV = 4
650 01:25:57.424727 CA_AAMCK_DIV = 4
651 01:25:57.424820 CA_ADMCK_DIV = 4
652 01:25:57.424912 DQ_TRACK_CA_EN = 0
653 01:25:57.425005 CA_PICK = 800
654 01:25:57.425098 CA_MCKIO = 800
655 01:25:57.425191 MCKIO_SEMI = 0
656 01:25:57.425283 PLL_FREQ = 3068
657 01:25:57.425376 DQ_UI_PI_RATIO = 32
658 01:25:57.425468 CA_UI_PI_RATIO = 0
659 01:25:57.425561 ===================================
660 01:25:57.425655 ===================================
661 01:25:57.425748 memory_type:LPDDR4
662 01:25:57.425841 GP_NUM : 10
663 01:25:57.425934 SRAM_EN : 1
664 01:25:57.426027 MD32_EN : 0
665 01:25:57.426119 ===================================
666 01:25:57.426213 [ANA_INIT] >>>>>>>>>>>>>>
667 01:25:57.426313 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 01:25:57.426441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 01:25:57.426535 ===================================
670 01:25:57.426628 data_rate = 1600,PCW = 0X7600
671 01:25:57.426721 ===================================
672 01:25:57.426815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 01:25:57.426908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 01:25:57.427002 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 01:25:57.427096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 01:25:57.427189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 01:25:57.427282 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 01:25:57.427593 [ANA_INIT] flow start
679 01:25:57.427688 [ANA_INIT] PLL >>>>>>>>
680 01:25:57.427787 [ANA_INIT] PLL <<<<<<<<
681 01:25:57.427883 [ANA_INIT] MIDPI >>>>>>>>
682 01:25:57.427978 [ANA_INIT] MIDPI <<<<<<<<
683 01:25:57.428073 [ANA_INIT] DLL >>>>>>>>
684 01:25:57.428167 [ANA_INIT] flow end
685 01:25:57.428261 ============ LP4 DIFF to SE enter ============
686 01:25:57.428356 ============ LP4 DIFF to SE exit ============
687 01:25:57.428451 [ANA_INIT] <<<<<<<<<<<<<
688 01:25:57.428544 [Flow] Enable top DCM control >>>>>
689 01:25:57.428638 [Flow] Enable top DCM control <<<<<
690 01:25:57.428732 Enable DLL master slave shuffle
691 01:25:57.428825 ==============================================================
692 01:25:57.428922 Gating Mode config
693 01:25:57.429016 ==============================================================
694 01:25:57.429111 Config description:
695 01:25:57.429206 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 01:25:57.429302 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 01:25:57.429396 SELPH_MODE 0: By rank 1: By Phase
698 01:25:57.429490 ==============================================================
699 01:25:57.429585 GAT_TRACK_EN = 1
700 01:25:57.429678 RX_GATING_MODE = 2
701 01:25:57.429771 RX_GATING_TRACK_MODE = 2
702 01:25:57.429865 SELPH_MODE = 1
703 01:25:57.429958 PICG_EARLY_EN = 1
704 01:25:57.430052 VALID_LAT_VALUE = 1
705 01:25:57.430145 ==============================================================
706 01:25:57.430239 Enter into Gating configuration >>>>
707 01:25:57.430358 Exit from Gating configuration <<<<
708 01:25:57.430466 Enter into DVFS_PRE_config >>>>>
709 01:25:57.430560 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 01:25:57.430657 Exit from DVFS_PRE_config <<<<<
711 01:25:57.430751 Enter into PICG configuration >>>>
712 01:25:57.430844 Exit from PICG configuration <<<<
713 01:25:57.430939 [RX_INPUT] configuration >>>>>
714 01:25:57.431033 [RX_INPUT] configuration <<<<<
715 01:25:57.431126 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 01:25:57.431220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 01:25:57.431314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 01:25:57.431409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 01:25:57.431503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 01:25:57.431596 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 01:25:57.431690 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 01:25:57.431786 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 01:25:57.431879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 01:25:57.431972 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 01:25:57.432065 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 01:25:57.432158 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 01:25:57.432251 ===================================
728 01:25:57.432345 LPDDR4 DRAM CONFIGURATION
729 01:25:57.432438 ===================================
730 01:25:57.432532 EX_ROW_EN[0] = 0x0
731 01:25:57.432625 EX_ROW_EN[1] = 0x0
732 01:25:57.432718 LP4Y_EN = 0x0
733 01:25:57.432811 WORK_FSP = 0x0
734 01:25:57.432904 WL = 0x2
735 01:25:57.432997 RL = 0x2
736 01:25:57.433089 BL = 0x2
737 01:25:57.433182 RPST = 0x0
738 01:25:57.433275 RD_PRE = 0x0
739 01:25:57.433371 WR_PRE = 0x1
740 01:25:57.433461 WR_PST = 0x0
741 01:25:57.433546 DBI_WR = 0x0
742 01:25:57.433630 DBI_RD = 0x0
743 01:25:57.433713 OTF = 0x1
744 01:25:57.433798 ===================================
745 01:25:57.433884 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 01:25:57.433969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 01:25:57.434054 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 01:25:57.434138 ===================================
749 01:25:57.434223 LPDDR4 DRAM CONFIGURATION
750 01:25:57.434313 ===================================
751 01:25:57.434399 EX_ROW_EN[0] = 0x10
752 01:25:57.434483 EX_ROW_EN[1] = 0x0
753 01:25:57.434567 LP4Y_EN = 0x0
754 01:25:57.434650 WORK_FSP = 0x0
755 01:25:57.434734 WL = 0x2
756 01:25:57.434817 RL = 0x2
757 01:25:57.434901 BL = 0x2
758 01:25:57.434987 RPST = 0x0
759 01:25:57.435074 RD_PRE = 0x0
760 01:25:57.435160 WR_PRE = 0x1
761 01:25:57.435250 WR_PST = 0x0
762 01:25:57.435335 DBI_WR = 0x0
763 01:25:57.435420 DBI_RD = 0x0
764 01:25:57.435504 OTF = 0x1
765 01:25:57.435588 ===================================
766 01:25:57.435674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 01:25:57.435759 nWR fixed to 40
768 01:25:57.435844 [ModeRegInit_LP4] CH0 RK0
769 01:25:57.435928 [ModeRegInit_LP4] CH0 RK1
770 01:25:57.436012 [ModeRegInit_LP4] CH1 RK0
771 01:25:57.436095 [ModeRegInit_LP4] CH1 RK1
772 01:25:57.436178 match AC timing 13
773 01:25:57.436262 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 01:25:57.436346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 01:25:57.436431 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 01:25:57.436516 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 01:25:57.436600 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 01:25:57.436684 [EMI DOE] emi_dcm 0
779 01:25:57.436768 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 01:25:57.436851 ==
781 01:25:57.436935 Dram Type= 6, Freq= 0, CH_0, rank 0
782 01:25:57.437020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 01:25:57.437103 ==
784 01:25:57.437188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 01:25:57.437273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 01:25:57.437357 [CA 0] Center 36 (6~67) winsize 62
787 01:25:57.437642 [CA 1] Center 36 (6~67) winsize 62
788 01:25:57.437758 [CA 2] Center 34 (4~65) winsize 62
789 01:25:57.437819 [CA 3] Center 33 (3~64) winsize 62
790 01:25:57.437875 [CA 4] Center 33 (2~64) winsize 63
791 01:25:57.437931 [CA 5] Center 32 (2~62) winsize 61
792 01:25:57.437986
793 01:25:57.438041 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 01:25:57.438096
795 01:25:57.438150 [CATrainingPosCal] consider 1 rank data
796 01:25:57.438205 u2DelayCellTimex100 = 270/100 ps
797 01:25:57.438260 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 01:25:57.438326 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 01:25:57.438384 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 01:25:57.438439 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 01:25:57.438493 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
802 01:25:57.438548 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 01:25:57.438603
804 01:25:57.438658 CA PerBit enable=1, Macro0, CA PI delay=32
805 01:25:57.438713
806 01:25:57.438767 [CBTSetCACLKResult] CA Dly = 32
807 01:25:57.438822 CS Dly: 5 (0~36)
808 01:25:57.438877 ==
809 01:25:57.438935 Dram Type= 6, Freq= 0, CH_0, rank 1
810 01:25:57.439013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 01:25:57.439107 ==
812 01:25:57.439201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 01:25:57.439295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 01:25:57.439397 [CA 0] Center 36 (6~67) winsize 62
815 01:25:57.439492 [CA 1] Center 36 (6~67) winsize 62
816 01:25:57.439586 [CA 2] Center 33 (3~64) winsize 62
817 01:25:57.439680 [CA 3] Center 33 (3~64) winsize 62
818 01:25:57.439773 [CA 4] Center 33 (3~63) winsize 61
819 01:25:57.439866 [CA 5] Center 32 (2~63) winsize 62
820 01:25:57.439958
821 01:25:57.440051 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 01:25:57.440144
823 01:25:57.440236 [CATrainingPosCal] consider 2 rank data
824 01:25:57.440330 u2DelayCellTimex100 = 270/100 ps
825 01:25:57.440424 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 01:25:57.440518 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 01:25:57.440611 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
828 01:25:57.440704 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 01:25:57.440798 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 01:25:57.440892 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 01:25:57.440985
832 01:25:57.441078 CA PerBit enable=1, Macro0, CA PI delay=32
833 01:25:57.441171
834 01:25:57.441264 [CBTSetCACLKResult] CA Dly = 32
835 01:25:57.441358 CS Dly: 5 (0~37)
836 01:25:57.441451
837 01:25:57.441544 ----->DramcWriteLeveling(PI) begin...
838 01:25:57.441641 ==
839 01:25:57.441735 Dram Type= 6, Freq= 0, CH_0, rank 0
840 01:25:57.441829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 01:25:57.441923 ==
842 01:25:57.442016 Write leveling (Byte 0): 33 => 33
843 01:25:57.442109 Write leveling (Byte 1): 32 => 32
844 01:25:57.442203 DramcWriteLeveling(PI) end<-----
845 01:25:57.442296
846 01:25:57.442395 ==
847 01:25:57.442489 Dram Type= 6, Freq= 0, CH_0, rank 0
848 01:25:57.442583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 01:25:57.442677 ==
850 01:25:57.442771 [Gating] SW mode calibration
851 01:25:57.442873 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 01:25:57.442969 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 01:25:57.443067 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 01:25:57.443162 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 01:25:57.443257 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 01:25:57.443351 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 01:25:57.443445 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 01:25:57.443538 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 01:25:57.443632 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 01:25:57.443725 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 01:25:57.443818 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 01:25:57.443911 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 01:25:57.444004 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 01:25:57.444098 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 01:25:57.444192 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 01:25:57.444285 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 01:25:57.444377 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 01:25:57.444471 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 01:25:57.444564 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 01:25:57.444657 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 01:25:57.444750 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 01:25:57.444843 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 01:25:57.444935 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 01:25:57.445028 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 01:25:57.445121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 01:25:57.445214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 01:25:57.445307 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 01:25:57.445399 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 01:25:57.445492 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
880 01:25:57.445585 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 01:25:57.445678 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 01:25:57.445770 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 01:25:57.445863 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 01:25:57.445955 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 01:25:57.446049 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 01:25:57.446148 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
887 01:25:57.446242 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (1 0) (0 0)
888 01:25:57.446342 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 01:25:57.446439 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 01:25:57.446538 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 01:25:57.446633 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 01:25:57.446932 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 01:25:57.447027 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 01:25:57.447124 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 01:25:57.447219 0 11 8 | B1->B0 | 2c2c 3d3d | 0 0 | (1 1) (1 1)
896 01:25:57.447314 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 01:25:57.447409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 01:25:57.447503 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 01:25:57.447596 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 01:25:57.447690 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 01:25:57.447783 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 01:25:57.447877 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 01:25:57.447970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 01:25:57.448063 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 01:25:57.448157 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 01:25:57.448250 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 01:25:57.448344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 01:25:57.448437 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 01:25:57.448531 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 01:25:57.448625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 01:25:57.448718 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 01:25:57.448815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 01:25:57.448909 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 01:25:57.449002 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 01:25:57.449095 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 01:25:57.449188 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 01:25:57.449281 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 01:25:57.449374 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 01:25:57.449467 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 01:25:57.449560 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 01:25:57.449652 Total UI for P1: 0, mck2ui 16
922 01:25:57.449745 best dqsien dly found for B0: ( 0, 14, 6)
923 01:25:57.449838 Total UI for P1: 0, mck2ui 16
924 01:25:57.449932 best dqsien dly found for B1: ( 0, 14, 10)
925 01:25:57.450025 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 01:25:57.450118 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 01:25:57.450210
928 01:25:57.450309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 01:25:57.450404 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 01:25:57.450497 [Gating] SW calibration Done
931 01:25:57.450590 ==
932 01:25:57.450683 Dram Type= 6, Freq= 0, CH_0, rank 0
933 01:25:57.450776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 01:25:57.450870 ==
935 01:25:57.450963 RX Vref Scan: 0
936 01:25:57.451056
937 01:25:57.451149 RX Vref 0 -> 0, step: 1
938 01:25:57.451241
939 01:25:57.451334 RX Delay -130 -> 252, step: 16
940 01:25:57.451427 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 01:25:57.451521 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 01:25:57.451613 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 01:25:57.451705 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 01:25:57.451803 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 01:25:57.451897 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 01:25:57.451990 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 01:25:57.452083 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 01:25:57.452176 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 01:25:57.452269 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 01:25:57.452363 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 01:25:57.452455 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 01:25:57.452548 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 01:25:57.452641 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 01:25:57.452734 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 01:25:57.452827 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 01:25:57.452920 ==
957 01:25:57.453013 Dram Type= 6, Freq= 0, CH_0, rank 0
958 01:25:57.453105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 01:25:57.453199 ==
960 01:25:57.453292 DQS Delay:
961 01:25:57.453384 DQS0 = 0, DQS1 = 0
962 01:25:57.453476 DQM Delay:
963 01:25:57.453568 DQM0 = 89, DQM1 = 82
964 01:25:57.453661 DQ Delay:
965 01:25:57.453754 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 01:25:57.453847 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 01:25:57.453940 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
968 01:25:57.454033 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
969 01:25:57.454126
970 01:25:57.454218
971 01:25:57.454318 ==
972 01:25:57.454412 Dram Type= 6, Freq= 0, CH_0, rank 0
973 01:25:57.454506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 01:25:57.454600 ==
975 01:25:57.454694
976 01:25:57.454787
977 01:25:57.454879 TX Vref Scan disable
978 01:25:57.454972 == TX Byte 0 ==
979 01:25:57.455065 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 01:25:57.455159 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 01:25:57.455252 == TX Byte 1 ==
982 01:25:57.455345 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
983 01:25:57.455438 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
984 01:25:57.455531 ==
985 01:25:57.455624 Dram Type= 6, Freq= 0, CH_0, rank 0
986 01:25:57.455717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 01:25:57.455811 ==
988 01:25:57.455904 TX Vref=22, minBit 5, minWin=27, winSum=446
989 01:25:57.455998 TX Vref=24, minBit 8, minWin=27, winSum=449
990 01:25:57.456092 TX Vref=26, minBit 8, minWin=28, winSum=456
991 01:25:57.456185 TX Vref=28, minBit 7, minWin=28, winSum=457
992 01:25:57.456278 TX Vref=30, minBit 8, minWin=28, winSum=456
993 01:25:57.456371 TX Vref=32, minBit 10, minWin=27, winSum=453
994 01:25:57.456466 [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 28
995 01:25:57.456559
996 01:25:57.456652 Final TX Range 1 Vref 28
997 01:25:57.456745
998 01:25:57.456837 ==
999 01:25:57.456930 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 01:25:57.457023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 01:25:57.457116 ==
1002 01:25:57.457208
1003 01:25:57.457300
1004 01:25:57.457392 TX Vref Scan disable
1005 01:25:57.457485 == TX Byte 0 ==
1006 01:25:57.457577 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 01:25:57.457673 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 01:25:57.457963 == TX Byte 1 ==
1009 01:25:57.458057 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 01:25:57.458154 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 01:25:57.458250
1012 01:25:57.458353 [DATLAT]
1013 01:25:57.458448 Freq=800, CH0 RK0
1014 01:25:57.458542
1015 01:25:57.458635 DATLAT Default: 0xa
1016 01:25:57.458728 0, 0xFFFF, sum = 0
1017 01:25:57.458823 1, 0xFFFF, sum = 0
1018 01:25:57.458922 2, 0xFFFF, sum = 0
1019 01:25:57.459017 3, 0xFFFF, sum = 0
1020 01:25:57.459114 4, 0xFFFF, sum = 0
1021 01:25:57.459209 5, 0xFFFF, sum = 0
1022 01:25:57.459304 6, 0xFFFF, sum = 0
1023 01:25:57.459398 7, 0xFFFF, sum = 0
1024 01:25:57.459493 8, 0xFFFF, sum = 0
1025 01:25:57.459594 9, 0x0, sum = 1
1026 01:25:57.459695 10, 0x0, sum = 2
1027 01:25:57.459799 11, 0x0, sum = 3
1028 01:25:57.459896 12, 0x0, sum = 4
1029 01:25:57.459993 best_step = 10
1030 01:25:57.460086
1031 01:25:57.460180 ==
1032 01:25:57.460273 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 01:25:57.460366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 01:25:57.460460 ==
1035 01:25:57.460553 RX Vref Scan: 1
1036 01:25:57.460645
1037 01:25:57.460737 Set Vref Range= 32 -> 127
1038 01:25:57.460829
1039 01:25:57.460920 RX Vref 32 -> 127, step: 1
1040 01:25:57.461011
1041 01:25:57.461102 RX Delay -95 -> 252, step: 8
1042 01:25:57.461194
1043 01:25:57.461285 Set Vref, RX VrefLevel [Byte0]: 32
1044 01:25:57.461377 [Byte1]: 32
1045 01:25:57.461468
1046 01:25:57.461559 Set Vref, RX VrefLevel [Byte0]: 33
1047 01:25:57.461650 [Byte1]: 33
1048 01:25:57.461742
1049 01:25:57.461833 Set Vref, RX VrefLevel [Byte0]: 34
1050 01:25:57.461925 [Byte1]: 34
1051 01:25:57.462017
1052 01:25:57.462108 Set Vref, RX VrefLevel [Byte0]: 35
1053 01:25:57.462199 [Byte1]: 35
1054 01:25:57.462290
1055 01:25:57.462420 Set Vref, RX VrefLevel [Byte0]: 36
1056 01:25:57.462512 [Byte1]: 36
1057 01:25:57.462604
1058 01:25:57.462695 Set Vref, RX VrefLevel [Byte0]: 37
1059 01:25:57.462787 [Byte1]: 37
1060 01:25:57.462878
1061 01:25:57.462976 Set Vref, RX VrefLevel [Byte0]: 38
1062 01:25:57.463070 [Byte1]: 38
1063 01:25:57.463161
1064 01:25:57.463253 Set Vref, RX VrefLevel [Byte0]: 39
1065 01:25:57.463344 [Byte1]: 39
1066 01:25:57.463436
1067 01:25:57.463527 Set Vref, RX VrefLevel [Byte0]: 40
1068 01:25:57.463619 [Byte1]: 40
1069 01:25:57.463711
1070 01:25:57.463802 Set Vref, RX VrefLevel [Byte0]: 41
1071 01:25:57.463894 [Byte1]: 41
1072 01:25:57.463985
1073 01:25:57.464076 Set Vref, RX VrefLevel [Byte0]: 42
1074 01:25:57.464170 [Byte1]: 42
1075 01:25:57.464263
1076 01:25:57.464354 Set Vref, RX VrefLevel [Byte0]: 43
1077 01:25:57.464446 [Byte1]: 43
1078 01:25:57.464537
1079 01:25:57.464629 Set Vref, RX VrefLevel [Byte0]: 44
1080 01:25:57.464721 [Byte1]: 44
1081 01:25:57.464813
1082 01:25:57.464903 Set Vref, RX VrefLevel [Byte0]: 45
1083 01:25:57.464995 [Byte1]: 45
1084 01:25:57.465086
1085 01:25:57.465177 Set Vref, RX VrefLevel [Byte0]: 46
1086 01:25:57.465268 [Byte1]: 46
1087 01:25:57.465359
1088 01:25:57.465450 Set Vref, RX VrefLevel [Byte0]: 47
1089 01:25:57.465541 [Byte1]: 47
1090 01:25:57.465633
1091 01:25:57.465724 Set Vref, RX VrefLevel [Byte0]: 48
1092 01:25:57.465857 [Byte1]: 48
1093 01:25:57.465950
1094 01:25:57.466042 Set Vref, RX VrefLevel [Byte0]: 49
1095 01:25:57.466134 [Byte1]: 49
1096 01:25:57.466225
1097 01:25:57.466340 Set Vref, RX VrefLevel [Byte0]: 50
1098 01:25:57.466447 [Byte1]: 50
1099 01:25:57.466539
1100 01:25:57.466630 Set Vref, RX VrefLevel [Byte0]: 51
1101 01:25:57.466722 [Byte1]: 51
1102 01:25:57.466822
1103 01:25:57.466914 Set Vref, RX VrefLevel [Byte0]: 52
1104 01:25:57.467006 [Byte1]: 52
1105 01:25:57.467098
1106 01:25:57.467192 Set Vref, RX VrefLevel [Byte0]: 53
1107 01:25:57.467284 [Byte1]: 53
1108 01:25:57.467376
1109 01:25:57.467467 Set Vref, RX VrefLevel [Byte0]: 54
1110 01:25:57.467560 [Byte1]: 54
1111 01:25:57.467649
1112 01:25:57.467733 Set Vref, RX VrefLevel [Byte0]: 55
1113 01:25:57.467816 [Byte1]: 55
1114 01:25:57.467898
1115 01:25:57.467980 Set Vref, RX VrefLevel [Byte0]: 56
1116 01:25:57.468063 [Byte1]: 56
1117 01:25:57.468144
1118 01:25:57.468227 Set Vref, RX VrefLevel [Byte0]: 57
1119 01:25:57.468309 [Byte1]: 57
1120 01:25:57.468391
1121 01:25:57.468473 Set Vref, RX VrefLevel [Byte0]: 58
1122 01:25:57.468555 [Byte1]: 58
1123 01:25:57.468636
1124 01:25:57.468718 Set Vref, RX VrefLevel [Byte0]: 59
1125 01:25:57.468801 [Byte1]: 59
1126 01:25:57.468882
1127 01:25:57.468965 Set Vref, RX VrefLevel [Byte0]: 60
1128 01:25:57.469047 [Byte1]: 60
1129 01:25:57.469129
1130 01:25:57.469211 Set Vref, RX VrefLevel [Byte0]: 61
1131 01:25:57.469293 [Byte1]: 61
1132 01:25:57.469375
1133 01:25:57.469456 Set Vref, RX VrefLevel [Byte0]: 62
1134 01:25:57.469539 [Byte1]: 62
1135 01:25:57.469620
1136 01:25:57.469702 Set Vref, RX VrefLevel [Byte0]: 63
1137 01:25:57.469784 [Byte1]: 63
1138 01:25:57.469866
1139 01:25:57.469948 Set Vref, RX VrefLevel [Byte0]: 64
1140 01:25:57.470030 [Byte1]: 64
1141 01:25:57.470112
1142 01:25:57.470202 Set Vref, RX VrefLevel [Byte0]: 65
1143 01:25:57.470286 [Byte1]: 65
1144 01:25:57.470409
1145 01:25:57.470492 Set Vref, RX VrefLevel [Byte0]: 66
1146 01:25:57.470574 [Byte1]: 66
1147 01:25:57.470655
1148 01:25:57.470737 Set Vref, RX VrefLevel [Byte0]: 67
1149 01:25:57.470819 [Byte1]: 67
1150 01:25:57.470901
1151 01:25:57.470983 Set Vref, RX VrefLevel [Byte0]: 68
1152 01:25:57.471065 [Byte1]: 68
1153 01:25:57.471146
1154 01:25:57.471228 Set Vref, RX VrefLevel [Byte0]: 69
1155 01:25:57.471311 [Byte1]: 69
1156 01:25:57.471392
1157 01:25:57.471473 Set Vref, RX VrefLevel [Byte0]: 70
1158 01:25:57.471555 [Byte1]: 70
1159 01:25:57.471637
1160 01:25:57.471719 Set Vref, RX VrefLevel [Byte0]: 71
1161 01:25:57.471801 [Byte1]: 71
1162 01:25:57.471882
1163 01:25:57.471964 Set Vref, RX VrefLevel [Byte0]: 72
1164 01:25:57.472046 [Byte1]: 72
1165 01:25:57.472127
1166 01:25:57.472209 Set Vref, RX VrefLevel [Byte0]: 73
1167 01:25:57.472291 [Byte1]: 73
1168 01:25:57.472372
1169 01:25:57.472454 Set Vref, RX VrefLevel [Byte0]: 74
1170 01:25:57.472536 [Byte1]: 74
1171 01:25:57.472618
1172 01:25:57.472700 Set Vref, RX VrefLevel [Byte0]: 75
1173 01:25:57.472782 [Byte1]: 75
1174 01:25:57.472869
1175 01:25:57.472956 Set Vref, RX VrefLevel [Byte0]: 76
1176 01:25:57.473038 [Byte1]: 76
1177 01:25:57.473120
1178 01:25:57.473202 Set Vref, RX VrefLevel [Byte0]: 77
1179 01:25:57.473479 [Byte1]: 77
1180 01:25:57.473567
1181 01:25:57.473651 Final RX Vref Byte 0 = 58 to rank0
1182 01:25:57.473735 Final RX Vref Byte 1 = 58 to rank0
1183 01:25:57.473818 Final RX Vref Byte 0 = 58 to rank1
1184 01:25:57.473901 Final RX Vref Byte 1 = 58 to rank1==
1185 01:25:57.473988 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 01:25:57.474047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 01:25:57.474102 ==
1188 01:25:57.474156 DQS Delay:
1189 01:25:57.474210 DQS0 = 0, DQS1 = 0
1190 01:25:57.474265 DQM Delay:
1191 01:25:57.474345 DQM0 = 92, DQM1 = 84
1192 01:25:57.474414 DQ Delay:
1193 01:25:57.474468 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1194 01:25:57.474521 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1195 01:25:57.474575 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1196 01:25:57.474628 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1197 01:25:57.474681
1198 01:25:57.474734
1199 01:25:57.474787 [DQSOSCAuto] RK0, (LSB)MR18= 0x463c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1200 01:25:57.474842 CH0 RK0: MR19=606, MR18=463C
1201 01:25:57.474896 CH0_RK0: MR19=0x606, MR18=0x463C, DQSOSC=392, MR23=63, INC=96, DEC=64
1202 01:25:57.474952
1203 01:25:57.475006 ----->DramcWriteLeveling(PI) begin...
1204 01:25:57.475061 ==
1205 01:25:57.475114 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 01:25:57.475168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 01:25:57.475222 ==
1208 01:25:57.475275 Write leveling (Byte 0): 32 => 32
1209 01:25:57.475328 Write leveling (Byte 1): 32 => 32
1210 01:25:57.475382 DramcWriteLeveling(PI) end<-----
1211 01:25:57.475435
1212 01:25:57.475488 ==
1213 01:25:57.475541 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 01:25:57.475594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 01:25:57.475648 ==
1216 01:25:57.475702 [Gating] SW mode calibration
1217 01:25:57.475755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 01:25:57.475810 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 01:25:57.475864 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 01:25:57.475918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 01:25:57.475971 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1222 01:25:57.476025 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 01:25:57.476078 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 01:25:57.476132 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 01:25:57.476185 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 01:25:57.476239 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 01:25:57.476292 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 01:25:57.476345 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 01:25:57.476398 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 01:25:57.476452 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 01:25:57.476519 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 01:25:57.476577 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 01:25:57.476631 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 01:25:57.476685 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 01:25:57.476738 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 01:25:57.476791 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 01:25:57.476844 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1238 01:25:57.476898 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 01:25:57.476951 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 01:25:57.477004 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 01:25:57.477057 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 01:25:57.477110 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 01:25:57.477164 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 01:25:57.477217 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1245 01:25:57.477271 0 9 8 | B1->B0 | 2a2a 2626 | 1 0 | (1 1) (0 0)
1246 01:25:57.477325 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 01:25:57.477379 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 01:25:57.477432 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 01:25:57.477486 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 01:25:57.477539 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 01:25:57.477593 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 01:25:57.477646 0 10 4 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
1253 01:25:57.477700 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (1 0) (1 1)
1254 01:25:57.477753 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 01:25:57.477806 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 01:25:57.477860 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 01:25:57.477913 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 01:25:57.477967 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 01:25:57.478021 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 01:25:57.478074 0 11 4 | B1->B0 | 2626 2524 | 0 1 | (0 0) (0 0)
1261 01:25:57.478128 0 11 8 | B1->B0 | 4343 3c3c | 0 0 | (0 0) (0 0)
1262 01:25:57.478181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 01:25:57.478235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 01:25:57.478288 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 01:25:57.478386 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 01:25:57.478440 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 01:25:57.478494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 01:25:57.478547 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1269 01:25:57.480017 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1270 01:25:57.483412 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 01:25:57.487387 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 01:25:57.493161 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 01:25:57.496581 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 01:25:57.500396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 01:25:57.506785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 01:25:57.510166 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 01:25:57.513829 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 01:25:57.520407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 01:25:57.523736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 01:25:57.527023 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 01:25:57.533692 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 01:25:57.536791 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 01:25:57.540212 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 01:25:57.547097 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 01:25:57.550655 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1286 01:25:57.553397 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1287 01:25:57.557223 Total UI for P1: 0, mck2ui 16
1288 01:25:57.560628 best dqsien dly found for B0: ( 0, 14, 6)
1289 01:25:57.564009 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 01:25:57.567375 Total UI for P1: 0, mck2ui 16
1291 01:25:57.570625 best dqsien dly found for B1: ( 0, 14, 10)
1292 01:25:57.573960 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1293 01:25:57.580762 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1294 01:25:57.581283
1295 01:25:57.583996 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1296 01:25:57.587473 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1297 01:25:57.590247 [Gating] SW calibration Done
1298 01:25:57.590714 ==
1299 01:25:57.593669 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 01:25:57.597098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 01:25:57.597525 ==
1302 01:25:57.597862 RX Vref Scan: 0
1303 01:25:57.598176
1304 01:25:57.600598 RX Vref 0 -> 0, step: 1
1305 01:25:57.601037
1306 01:25:57.604147 RX Delay -130 -> 252, step: 16
1307 01:25:57.607370 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1308 01:25:57.610603 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1309 01:25:57.617331 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1310 01:25:57.620799 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1311 01:25:57.624410 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1312 01:25:57.626886 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1313 01:25:57.630621 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1314 01:25:57.637130 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1315 01:25:57.640538 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1316 01:25:57.644218 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1317 01:25:57.646931 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1318 01:25:57.650691 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1319 01:25:57.657283 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1320 01:25:57.660217 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1321 01:25:57.663789 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1322 01:25:57.667189 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1323 01:25:57.667629 ==
1324 01:25:57.669994 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 01:25:57.676965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 01:25:57.677488 ==
1327 01:25:57.677936 DQS Delay:
1328 01:25:57.680495 DQS0 = 0, DQS1 = 0
1329 01:25:57.681021 DQM Delay:
1330 01:25:57.681468 DQM0 = 92, DQM1 = 83
1331 01:25:57.683894 DQ Delay:
1332 01:25:57.686847 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1333 01:25:57.690296 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1334 01:25:57.693518 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1335 01:25:57.696817 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1336 01:25:57.697235
1337 01:25:57.697567
1338 01:25:57.697877 ==
1339 01:25:57.700245 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 01:25:57.703496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 01:25:57.703918 ==
1342 01:25:57.704255
1343 01:25:57.704572
1344 01:25:57.707058 TX Vref Scan disable
1345 01:25:57.707476 == TX Byte 0 ==
1346 01:25:57.713611 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1347 01:25:57.716964 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1348 01:25:57.717384 == TX Byte 1 ==
1349 01:25:57.723961 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1350 01:25:57.727031 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1351 01:25:57.727452 ==
1352 01:25:57.730547 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 01:25:57.733767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 01:25:57.734189 ==
1355 01:25:57.747992 TX Vref=22, minBit 10, minWin=27, winSum=448
1356 01:25:57.751195 TX Vref=24, minBit 1, minWin=28, winSum=456
1357 01:25:57.754384 TX Vref=26, minBit 13, minWin=27, winSum=457
1358 01:25:57.757691 TX Vref=28, minBit 7, minWin=28, winSum=459
1359 01:25:57.760729 TX Vref=30, minBit 8, minWin=28, winSum=461
1360 01:25:57.767642 TX Vref=32, minBit 4, minWin=28, winSum=457
1361 01:25:57.770780 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1362 01:25:57.771339
1363 01:25:57.774394 Final TX Range 1 Vref 30
1364 01:25:57.774920
1365 01:25:57.775391 ==
1366 01:25:57.777135 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 01:25:57.780599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 01:25:57.781109 ==
1369 01:25:57.784087
1370 01:25:57.784633
1371 01:25:57.785078 TX Vref Scan disable
1372 01:25:57.787361 == TX Byte 0 ==
1373 01:25:57.790781 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1374 01:25:57.793954 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1375 01:25:57.797357 == TX Byte 1 ==
1376 01:25:57.800684 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1377 01:25:57.804248 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1378 01:25:57.807760
1379 01:25:57.808057 [DATLAT]
1380 01:25:57.808297 Freq=800, CH0 RK1
1381 01:25:57.808521
1382 01:25:57.810431 DATLAT Default: 0xa
1383 01:25:57.810732 0, 0xFFFF, sum = 0
1384 01:25:57.813958 1, 0xFFFF, sum = 0
1385 01:25:57.814261 2, 0xFFFF, sum = 0
1386 01:25:57.817333 3, 0xFFFF, sum = 0
1387 01:25:57.817634 4, 0xFFFF, sum = 0
1388 01:25:57.820518 5, 0xFFFF, sum = 0
1389 01:25:57.824087 6, 0xFFFF, sum = 0
1390 01:25:57.824389 7, 0xFFFF, sum = 0
1391 01:25:57.827563 8, 0xFFFF, sum = 0
1392 01:25:57.827867 9, 0x0, sum = 1
1393 01:25:57.828107 10, 0x0, sum = 2
1394 01:25:57.830787 11, 0x0, sum = 3
1395 01:25:57.831138 12, 0x0, sum = 4
1396 01:25:57.834240 best_step = 10
1397 01:25:57.834562
1398 01:25:57.834811 ==
1399 01:25:57.837594 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 01:25:57.840892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 01:25:57.841192 ==
1402 01:25:57.844200 RX Vref Scan: 0
1403 01:25:57.844501
1404 01:25:57.844740 RX Vref 0 -> 0, step: 1
1405 01:25:57.844963
1406 01:25:57.847502 RX Delay -79 -> 252, step: 8
1407 01:25:57.854261 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1408 01:25:57.857644 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1409 01:25:57.861077 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1410 01:25:57.864557 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1411 01:25:57.867317 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1412 01:25:57.873929 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1413 01:25:57.877860 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1414 01:25:57.880890 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 01:25:57.884501 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1416 01:25:57.887292 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1417 01:25:57.894216 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1418 01:25:57.897552 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1419 01:25:57.900873 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1420 01:25:57.904164 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1421 01:25:57.907621 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 01:25:57.914357 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1423 01:25:57.914675 ==
1424 01:25:57.917626 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 01:25:57.920287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 01:25:57.920592 ==
1427 01:25:57.920892 DQS Delay:
1428 01:25:57.923761 DQS0 = 0, DQS1 = 0
1429 01:25:57.923956 DQM Delay:
1430 01:25:57.927214 DQM0 = 93, DQM1 = 83
1431 01:25:57.927364 DQ Delay:
1432 01:25:57.930513 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1433 01:25:57.934037 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1434 01:25:57.937291 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1435 01:25:57.940772 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1436 01:25:57.940867
1437 01:25:57.940934
1438 01:25:57.947187 [DQSOSCAuto] RK1, (LSB)MR18= 0x4113, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1439 01:25:57.950496 CH0 RK1: MR19=606, MR18=4113
1440 01:25:57.957033 CH0_RK1: MR19=0x606, MR18=0x4113, DQSOSC=393, MR23=63, INC=95, DEC=63
1441 01:25:57.960547 [RxdqsGatingPostProcess] freq 800
1442 01:25:57.967368 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 01:25:57.967451 Pre-setting of DQS Precalculation
1444 01:25:57.974099 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 01:25:57.974211 ==
1446 01:25:57.977529 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 01:25:57.980418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 01:25:57.980501 ==
1449 01:25:57.987191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 01:25:57.993765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 01:25:58.002184 [CA 0] Center 36 (6~67) winsize 62
1452 01:25:58.005466 [CA 1] Center 36 (6~67) winsize 62
1453 01:25:58.008561 [CA 2] Center 35 (5~65) winsize 61
1454 01:25:58.012245 [CA 3] Center 34 (4~65) winsize 62
1455 01:25:58.015201 [CA 4] Center 34 (4~65) winsize 62
1456 01:25:58.018723 [CA 5] Center 34 (4~64) winsize 61
1457 01:25:58.018833
1458 01:25:58.021908 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1459 01:25:58.022026
1460 01:25:58.025071 [CATrainingPosCal] consider 1 rank data
1461 01:25:58.028455 u2DelayCellTimex100 = 270/100 ps
1462 01:25:58.031762 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 01:25:58.035135 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 01:25:58.042037 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1465 01:25:58.045419 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 01:25:58.048970 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 01:25:58.051739 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 01:25:58.051818
1469 01:25:58.055084 CA PerBit enable=1, Macro0, CA PI delay=34
1470 01:25:58.055161
1471 01:25:58.058424 [CBTSetCACLKResult] CA Dly = 34
1472 01:25:58.058499 CS Dly: 6 (0~37)
1473 01:25:58.058560 ==
1474 01:25:58.062206 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 01:25:58.068504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 01:25:58.068588 ==
1477 01:25:58.071982 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 01:25:58.078870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 01:25:58.088381 [CA 0] Center 36 (6~67) winsize 62
1480 01:25:58.092493 [CA 1] Center 36 (6~67) winsize 62
1481 01:25:58.096047 [CA 2] Center 35 (5~66) winsize 62
1482 01:25:58.099978 [CA 3] Center 34 (4~65) winsize 62
1483 01:25:58.103558 [CA 4] Center 34 (4~65) winsize 62
1484 01:25:58.103705 [CA 5] Center 34 (4~65) winsize 62
1485 01:25:58.103787
1486 01:25:58.111013 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1487 01:25:58.111120
1488 01:25:58.114614 [CATrainingPosCal] consider 2 rank data
1489 01:25:58.114700 u2DelayCellTimex100 = 270/100 ps
1490 01:25:58.118097 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 01:25:58.121381 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 01:25:58.127933 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1493 01:25:58.131042 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 01:25:58.134744 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 01:25:58.137748 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 01:25:58.137834
1497 01:25:58.141089 CA PerBit enable=1, Macro0, CA PI delay=34
1498 01:25:58.141173
1499 01:25:58.144842 [CBTSetCACLKResult] CA Dly = 34
1500 01:25:58.144958 CS Dly: 6 (0~38)
1501 01:25:58.145050
1502 01:25:58.151081 ----->DramcWriteLeveling(PI) begin...
1503 01:25:58.151175 ==
1504 01:25:58.154556 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 01:25:58.157717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 01:25:58.157808 ==
1507 01:25:58.161092 Write leveling (Byte 0): 28 => 28
1508 01:25:58.164510 Write leveling (Byte 1): 28 => 28
1509 01:25:58.168339 DramcWriteLeveling(PI) end<-----
1510 01:25:58.168426
1511 01:25:58.168524 ==
1512 01:25:58.170965 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 01:25:58.174344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 01:25:58.174419 ==
1515 01:25:58.177762 [Gating] SW mode calibration
1516 01:25:58.184538 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 01:25:58.191449 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 01:25:58.194768 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 01:25:58.197534 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1520 01:25:58.200946 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 01:25:58.207849 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 01:25:58.211432 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 01:25:58.214760 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 01:25:58.221549 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 01:25:58.224289 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 01:25:58.227779 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 01:25:58.234404 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 01:25:58.237690 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 01:25:58.241371 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 01:25:58.247968 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 01:25:58.251300 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 01:25:58.254405 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 01:25:58.261087 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 01:25:58.264522 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 01:25:58.267485 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 01:25:58.274578 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 01:25:58.277680 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 01:25:58.281295 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 01:25:58.288225 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 01:25:58.291533 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 01:25:58.294281 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 01:25:58.297619 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 01:25:58.304647 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (1 1) (1 1)
1544 01:25:58.308080 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1545 01:25:58.311429 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 01:25:58.318371 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 01:25:58.321724 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 01:25:58.324608 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 01:25:58.331411 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 01:25:58.334636 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1551 01:25:58.338073 0 10 4 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 0)
1552 01:25:58.345160 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1553 01:25:58.347956 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 01:25:58.351302 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 01:25:58.358411 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 01:25:58.361730 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 01:25:58.365068 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 01:25:58.368503 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 01:25:58.375080 0 11 4 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
1560 01:25:58.378179 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
1561 01:25:58.381708 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 01:25:58.387981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 01:25:58.391396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 01:25:58.394875 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 01:25:58.401638 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 01:25:58.405188 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 01:25:58.408260 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 01:25:58.414848 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1569 01:25:58.418288 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 01:25:58.421455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 01:25:58.428655 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 01:25:58.432013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 01:25:58.435506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 01:25:58.441433 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 01:25:58.444999 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 01:25:58.448301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 01:25:58.451751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 01:25:58.458672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 01:25:58.461573 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 01:25:58.465059 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 01:25:58.472018 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 01:25:58.474873 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 01:25:58.478198 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 01:25:58.485162 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 01:25:58.485248 Total UI for P1: 0, mck2ui 16
1586 01:25:58.491797 best dqsien dly found for B0: ( 0, 14, 4)
1587 01:25:58.491883 Total UI for P1: 0, mck2ui 16
1588 01:25:58.498140 best dqsien dly found for B1: ( 0, 14, 4)
1589 01:25:58.501751 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1590 01:25:58.505181 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1591 01:25:58.505269
1592 01:25:58.508429 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 01:25:58.511584 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 01:25:58.514995 [Gating] SW calibration Done
1595 01:25:58.515081 ==
1596 01:25:58.518081 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 01:25:58.521577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 01:25:58.521658 ==
1599 01:25:58.525391 RX Vref Scan: 0
1600 01:25:58.525491
1601 01:25:58.525581 RX Vref 0 -> 0, step: 1
1602 01:25:58.525671
1603 01:25:58.528054 RX Delay -130 -> 252, step: 16
1604 01:25:58.531443 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1605 01:25:58.538156 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1606 01:25:58.541463 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 01:25:58.544951 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1608 01:25:58.548272 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1609 01:25:58.551802 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1610 01:25:58.554993 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1611 01:25:58.561667 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1612 01:25:58.565092 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1613 01:25:58.568540 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1614 01:25:58.572075 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1615 01:25:58.574861 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1616 01:25:58.581692 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1617 01:25:58.585270 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1618 01:25:58.588772 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1619 01:25:58.591495 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1620 01:25:58.591567 ==
1621 01:25:58.594841 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 01:25:58.601610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 01:25:58.601680 ==
1624 01:25:58.601740 DQS Delay:
1625 01:25:58.605107 DQS0 = 0, DQS1 = 0
1626 01:25:58.605179 DQM Delay:
1627 01:25:58.605238 DQM0 = 94, DQM1 = 90
1628 01:25:58.607946 DQ Delay:
1629 01:25:58.611359 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1630 01:25:58.614853 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1631 01:25:58.618156 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1632 01:25:58.621682 DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101
1633 01:25:58.621777
1634 01:25:58.621850
1635 01:25:58.621906 ==
1636 01:25:58.625153 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 01:25:58.628518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 01:25:58.628594 ==
1639 01:25:58.628654
1640 01:25:58.628711
1641 01:25:58.631237 TX Vref Scan disable
1642 01:25:58.634823 == TX Byte 0 ==
1643 01:25:58.638314 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1644 01:25:58.641671 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1645 01:25:58.644629 == TX Byte 1 ==
1646 01:25:58.648392 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1647 01:25:58.651537 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1648 01:25:58.651626 ==
1649 01:25:58.654601 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 01:25:58.658216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 01:25:58.661493 ==
1652 01:25:58.672788 TX Vref=22, minBit 3, minWin=26, winSum=437
1653 01:25:58.675844 TX Vref=24, minBit 0, minWin=27, winSum=444
1654 01:25:58.679420 TX Vref=26, minBit 0, minWin=27, winSum=446
1655 01:25:58.682792 TX Vref=28, minBit 2, minWin=27, winSum=447
1656 01:25:58.686482 TX Vref=30, minBit 2, minWin=27, winSum=451
1657 01:25:58.689467 TX Vref=32, minBit 2, minWin=27, winSum=448
1658 01:25:58.696085 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1659 01:25:58.696186
1660 01:25:58.699371 Final TX Range 1 Vref 30
1661 01:25:58.699471
1662 01:25:58.699570 ==
1663 01:25:58.702950 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 01:25:58.706436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 01:25:58.706535 ==
1666 01:25:58.706616
1667 01:25:58.709153
1668 01:25:58.709233 TX Vref Scan disable
1669 01:25:58.712485 == TX Byte 0 ==
1670 01:25:58.716067 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1671 01:25:58.719422 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1672 01:25:58.722917 == TX Byte 1 ==
1673 01:25:58.726361 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1674 01:25:58.729181 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1675 01:25:58.733127
1676 01:25:58.733204 [DATLAT]
1677 01:25:58.733293 Freq=800, CH1 RK0
1678 01:25:58.733430
1679 01:25:58.735895 DATLAT Default: 0xa
1680 01:25:58.735978 0, 0xFFFF, sum = 0
1681 01:25:58.739413 1, 0xFFFF, sum = 0
1682 01:25:58.739490 2, 0xFFFF, sum = 0
1683 01:25:58.742849 3, 0xFFFF, sum = 0
1684 01:25:58.742918 4, 0xFFFF, sum = 0
1685 01:25:58.746195 5, 0xFFFF, sum = 0
1686 01:25:58.746315 6, 0xFFFF, sum = 0
1687 01:25:58.749766 7, 0xFFFF, sum = 0
1688 01:25:58.749868 8, 0xFFFF, sum = 0
1689 01:25:58.753238 9, 0x0, sum = 1
1690 01:25:58.753338 10, 0x0, sum = 2
1691 01:25:58.756021 11, 0x0, sum = 3
1692 01:25:58.756121 12, 0x0, sum = 4
1693 01:25:58.759611 best_step = 10
1694 01:25:58.759692
1695 01:25:58.759757 ==
1696 01:25:58.763029 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 01:25:58.766293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 01:25:58.766415 ==
1699 01:25:58.769633 RX Vref Scan: 1
1700 01:25:58.769715
1701 01:25:58.769783 Set Vref Range= 32 -> 127
1702 01:25:58.769844
1703 01:25:58.773196 RX Vref 32 -> 127, step: 1
1704 01:25:58.773278
1705 01:25:58.776235 RX Delay -79 -> 252, step: 8
1706 01:25:58.776317
1707 01:25:58.779242 Set Vref, RX VrefLevel [Byte0]: 32
1708 01:25:58.782574 [Byte1]: 32
1709 01:25:58.782656
1710 01:25:58.786069 Set Vref, RX VrefLevel [Byte0]: 33
1711 01:25:58.789450 [Byte1]: 33
1712 01:25:58.792708
1713 01:25:58.792790 Set Vref, RX VrefLevel [Byte0]: 34
1714 01:25:58.795895 [Byte1]: 34
1715 01:25:58.800588
1716 01:25:58.800677 Set Vref, RX VrefLevel [Byte0]: 35
1717 01:25:58.803957 [Byte1]: 35
1718 01:25:58.808302
1719 01:25:58.808430 Set Vref, RX VrefLevel [Byte0]: 36
1720 01:25:58.811286 [Byte1]: 36
1721 01:25:58.815489
1722 01:25:58.815736 Set Vref, RX VrefLevel [Byte0]: 37
1723 01:25:58.819101 [Byte1]: 37
1724 01:25:58.823285
1725 01:25:58.823377 Set Vref, RX VrefLevel [Byte0]: 38
1726 01:25:58.826167 [Byte1]: 38
1727 01:25:58.830433
1728 01:25:58.830543 Set Vref, RX VrefLevel [Byte0]: 39
1729 01:25:58.833941 [Byte1]: 39
1730 01:25:58.837921
1731 01:25:58.838010 Set Vref, RX VrefLevel [Byte0]: 40
1732 01:25:58.841437 [Byte1]: 40
1733 01:25:58.845715
1734 01:25:58.845790 Set Vref, RX VrefLevel [Byte0]: 41
1735 01:25:58.849226 [Byte1]: 41
1736 01:25:58.853341
1737 01:25:58.853422 Set Vref, RX VrefLevel [Byte0]: 42
1738 01:25:58.856857 [Byte1]: 42
1739 01:25:58.860993
1740 01:25:58.861105 Set Vref, RX VrefLevel [Byte0]: 43
1741 01:25:58.863977 [Byte1]: 43
1742 01:25:58.868118
1743 01:25:58.868200 Set Vref, RX VrefLevel [Byte0]: 44
1744 01:25:58.871519 [Byte1]: 44
1745 01:25:58.876218
1746 01:25:58.876330 Set Vref, RX VrefLevel [Byte0]: 45
1747 01:25:58.879115 [Byte1]: 45
1748 01:25:58.883186
1749 01:25:58.883270 Set Vref, RX VrefLevel [Byte0]: 46
1750 01:25:58.886614 [Byte1]: 46
1751 01:25:58.891298
1752 01:25:58.891381 Set Vref, RX VrefLevel [Byte0]: 47
1753 01:25:58.894219 [Byte1]: 47
1754 01:25:58.898345
1755 01:25:58.898427 Set Vref, RX VrefLevel [Byte0]: 48
1756 01:25:58.901851 [Byte1]: 48
1757 01:25:58.906493
1758 01:25:58.906580 Set Vref, RX VrefLevel [Byte0]: 49
1759 01:25:58.909148 [Byte1]: 49
1760 01:25:58.913712
1761 01:25:58.913794 Set Vref, RX VrefLevel [Byte0]: 50
1762 01:25:58.916957 [Byte1]: 50
1763 01:25:58.921083
1764 01:25:58.921166 Set Vref, RX VrefLevel [Byte0]: 51
1765 01:25:58.924453 [Byte1]: 51
1766 01:25:58.928763
1767 01:25:58.928845 Set Vref, RX VrefLevel [Byte0]: 52
1768 01:25:58.931889 [Byte1]: 52
1769 01:25:58.936433
1770 01:25:58.936516 Set Vref, RX VrefLevel [Byte0]: 53
1771 01:25:58.939968 [Byte1]: 53
1772 01:25:58.943893
1773 01:25:58.943975 Set Vref, RX VrefLevel [Byte0]: 54
1774 01:25:58.947376 [Byte1]: 54
1775 01:25:58.951712
1776 01:25:58.951795 Set Vref, RX VrefLevel [Byte0]: 55
1777 01:25:58.954433 [Byte1]: 55
1778 01:25:58.958770
1779 01:25:58.958853 Set Vref, RX VrefLevel [Byte0]: 56
1780 01:25:58.962228 [Byte1]: 56
1781 01:25:58.966354
1782 01:25:58.966436 Set Vref, RX VrefLevel [Byte0]: 57
1783 01:25:58.969827 [Byte1]: 57
1784 01:25:58.974228
1785 01:25:58.974327 Set Vref, RX VrefLevel [Byte0]: 58
1786 01:25:58.977036 [Byte1]: 58
1787 01:25:58.981681
1788 01:25:58.981763 Set Vref, RX VrefLevel [Byte0]: 59
1789 01:25:58.984997 [Byte1]: 59
1790 01:25:58.988901
1791 01:25:58.988978 Set Vref, RX VrefLevel [Byte0]: 60
1792 01:25:58.992371 [Byte1]: 60
1793 01:25:58.996429
1794 01:25:58.996508 Set Vref, RX VrefLevel [Byte0]: 61
1795 01:25:58.999834 [Byte1]: 61
1796 01:25:59.004093
1797 01:25:59.004171 Set Vref, RX VrefLevel [Byte0]: 62
1798 01:25:59.007424 [Byte1]: 62
1799 01:25:59.011809
1800 01:25:59.011891 Set Vref, RX VrefLevel [Byte0]: 63
1801 01:25:59.014771 [Byte1]: 63
1802 01:25:59.019393
1803 01:25:59.019472 Set Vref, RX VrefLevel [Byte0]: 64
1804 01:25:59.022692 [Byte1]: 64
1805 01:25:59.026648
1806 01:25:59.026729 Set Vref, RX VrefLevel [Byte0]: 65
1807 01:25:59.030100 [Byte1]: 65
1808 01:25:59.034225
1809 01:25:59.034311 Set Vref, RX VrefLevel [Byte0]: 66
1810 01:25:59.037890 [Byte1]: 66
1811 01:25:59.041639
1812 01:25:59.041715 Set Vref, RX VrefLevel [Byte0]: 67
1813 01:25:59.044843 [Byte1]: 67
1814 01:25:59.049353
1815 01:25:59.049459 Set Vref, RX VrefLevel [Byte0]: 68
1816 01:25:59.053005 [Byte1]: 68
1817 01:25:59.057156
1818 01:25:59.057311 Set Vref, RX VrefLevel [Byte0]: 69
1819 01:25:59.060340 [Byte1]: 69
1820 01:25:59.064325
1821 01:25:59.064406 Set Vref, RX VrefLevel [Byte0]: 70
1822 01:25:59.067819 [Byte1]: 70
1823 01:25:59.071992
1824 01:25:59.072069 Set Vref, RX VrefLevel [Byte0]: 71
1825 01:25:59.075628 [Byte1]: 71
1826 01:25:59.080127
1827 01:25:59.080211 Set Vref, RX VrefLevel [Byte0]: 72
1828 01:25:59.082880 [Byte1]: 72
1829 01:25:59.087189
1830 01:25:59.087267 Set Vref, RX VrefLevel [Byte0]: 73
1831 01:25:59.090654 [Byte1]: 73
1832 01:25:59.094679
1833 01:25:59.094763 Set Vref, RX VrefLevel [Byte0]: 74
1834 01:25:59.097861 [Byte1]: 74
1835 01:25:59.102563
1836 01:25:59.102654 Set Vref, RX VrefLevel [Byte0]: 75
1837 01:25:59.105864 [Byte1]: 75
1838 01:25:59.110161
1839 01:25:59.110248 Final RX Vref Byte 0 = 50 to rank0
1840 01:25:59.112943 Final RX Vref Byte 1 = 56 to rank0
1841 01:25:59.116535 Final RX Vref Byte 0 = 50 to rank1
1842 01:25:59.119864 Final RX Vref Byte 1 = 56 to rank1==
1843 01:25:59.123333 Dram Type= 6, Freq= 0, CH_1, rank 0
1844 01:25:59.130065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1845 01:25:59.130146 ==
1846 01:25:59.130244 DQS Delay:
1847 01:25:59.130381 DQS0 = 0, DQS1 = 0
1848 01:25:59.133251 DQM Delay:
1849 01:25:59.133328 DQM0 = 95, DQM1 = 90
1850 01:25:59.136388 DQ Delay:
1851 01:25:59.139815 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =88
1852 01:25:59.139894 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1853 01:25:59.143290 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1854 01:25:59.149688 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96
1855 01:25:59.149771
1856 01:25:59.149857
1857 01:25:59.156580 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1858 01:25:59.160018 CH1 RK0: MR19=606, MR18=2F4B
1859 01:25:59.166749 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1860 01:25:59.166831
1861 01:25:59.169791 ----->DramcWriteLeveling(PI) begin...
1862 01:25:59.169870 ==
1863 01:25:59.173548 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 01:25:59.176696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 01:25:59.176773 ==
1866 01:25:59.180038 Write leveling (Byte 0): 29 => 29
1867 01:25:59.183552 Write leveling (Byte 1): 28 => 28
1868 01:25:59.186455 DramcWriteLeveling(PI) end<-----
1869 01:25:59.186532
1870 01:25:59.186615 ==
1871 01:25:59.189958 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 01:25:59.193625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 01:25:59.193704 ==
1874 01:25:59.197141 [Gating] SW mode calibration
1875 01:25:59.203124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1876 01:25:59.209669 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1877 01:25:59.213663 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1878 01:25:59.217096 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1879 01:25:59.223090 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1880 01:25:59.226627 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 01:25:59.230173 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 01:25:59.236447 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 01:25:59.239739 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 01:25:59.243820 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 01:25:59.250340 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 01:25:59.253296 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 01:25:59.256638 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 01:25:59.259971 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 01:25:59.267071 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 01:25:59.270646 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 01:25:59.273369 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 01:25:59.280005 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1893 01:25:59.283859 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1894 01:25:59.287100 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1895 01:25:59.293443 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 01:25:59.296681 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 01:25:59.300077 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 01:25:59.307158 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 01:25:59.309967 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 01:25:59.313495 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 01:25:59.320104 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 01:25:59.323654 0 9 4 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
1903 01:25:59.326974 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1904 01:25:59.333680 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 01:25:59.336787 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 01:25:59.340336 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 01:25:59.346622 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 01:25:59.349999 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 01:25:59.353347 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 01:25:59.357050 0 10 4 | B1->B0 | 2e2e 3131 | 0 0 | (1 1) (0 1)
1911 01:25:59.363834 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1912 01:25:59.366675 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 01:25:59.370296 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 01:25:59.376661 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 01:25:59.380055 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 01:25:59.383680 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 01:25:59.390476 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1918 01:25:59.393340 0 11 4 | B1->B0 | 3b3b 2a2a | 1 0 | (0 0) (0 0)
1919 01:25:59.396775 0 11 8 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
1920 01:25:59.403246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 01:25:59.407155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 01:25:59.410480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 01:25:59.416635 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 01:25:59.420188 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 01:25:59.423594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 01:25:59.430621 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1927 01:25:59.433419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1928 01:25:59.436997 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 01:25:59.443751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 01:25:59.447109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 01:25:59.450346 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 01:25:59.453578 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 01:25:59.460357 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 01:25:59.463699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 01:25:59.466958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 01:25:59.473724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 01:25:59.477195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 01:25:59.479995 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 01:25:59.487182 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 01:25:59.489870 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 01:25:59.493912 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1942 01:25:59.500130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1943 01:25:59.503713 Total UI for P1: 0, mck2ui 16
1944 01:25:59.507208 best dqsien dly found for B1: ( 0, 14, 0)
1945 01:25:59.510321 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 01:25:59.513796 Total UI for P1: 0, mck2ui 16
1947 01:25:59.517152 best dqsien dly found for B0: ( 0, 14, 2)
1948 01:25:59.520590 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1949 01:25:59.523831 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1950 01:25:59.523915
1951 01:25:59.527114 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1952 01:25:59.530260 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1953 01:25:59.533559 [Gating] SW calibration Done
1954 01:25:59.533641 ==
1955 01:25:59.536979 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 01:25:59.540442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 01:25:59.540528 ==
1958 01:25:59.543344 RX Vref Scan: 0
1959 01:25:59.543427
1960 01:25:59.546919 RX Vref 0 -> 0, step: 1
1961 01:25:59.547001
1962 01:25:59.547067 RX Delay -130 -> 252, step: 16
1963 01:25:59.553112 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1964 01:25:59.556636 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1965 01:25:59.560075 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1966 01:25:59.563367 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1967 01:25:59.566729 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1968 01:25:59.573117 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1969 01:25:59.576438 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1970 01:25:59.580194 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1971 01:25:59.583162 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1972 01:25:59.586848 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1973 01:25:59.593035 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1974 01:25:59.596519 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1975 01:25:59.599799 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1976 01:25:59.603394 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1977 01:25:59.610488 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1978 01:25:59.613350 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1979 01:25:59.613433 ==
1980 01:25:59.616674 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 01:25:59.620044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 01:25:59.620128 ==
1983 01:25:59.620193 DQS Delay:
1984 01:25:59.623538 DQS0 = 0, DQS1 = 0
1985 01:25:59.623620 DQM Delay:
1986 01:25:59.626880 DQM0 = 93, DQM1 = 89
1987 01:25:59.626974 DQ Delay:
1988 01:25:59.629699 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1989 01:25:59.633417 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1990 01:25:59.636719 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1991 01:25:59.640149 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1992 01:25:59.640232
1993 01:25:59.640298
1994 01:25:59.640358 ==
1995 01:25:59.643179 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 01:25:59.647166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 01:25:59.649949 ==
1998 01:25:59.650032
1999 01:25:59.650100
2000 01:25:59.650208 TX Vref Scan disable
2001 01:25:59.653713 == TX Byte 0 ==
2002 01:25:59.657015 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2003 01:25:59.659896 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2004 01:25:59.663410 == TX Byte 1 ==
2005 01:25:59.666977 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 01:25:59.670351 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 01:25:59.670434 ==
2008 01:25:59.673228 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 01:25:59.679905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 01:25:59.680026 ==
2011 01:25:59.692582 TX Vref=22, minBit 1, minWin=27, winSum=445
2012 01:25:59.695796 TX Vref=24, minBit 1, minWin=27, winSum=448
2013 01:25:59.698880 TX Vref=26, minBit 1, minWin=27, winSum=451
2014 01:25:59.702342 TX Vref=28, minBit 1, minWin=27, winSum=454
2015 01:25:59.705769 TX Vref=30, minBit 4, minWin=27, winSum=454
2016 01:25:59.709223 TX Vref=32, minBit 1, minWin=27, winSum=452
2017 01:25:59.716255 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
2018 01:25:59.716340
2019 01:25:59.719099 Final TX Range 1 Vref 28
2020 01:25:59.719182
2021 01:25:59.719247 ==
2022 01:25:59.722507 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 01:25:59.725965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 01:25:59.726088 ==
2025 01:25:59.726234
2026 01:25:59.726349
2027 01:25:59.729483 TX Vref Scan disable
2028 01:25:59.732745 == TX Byte 0 ==
2029 01:25:59.735639 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2030 01:25:59.739055 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2031 01:25:59.742478 == TX Byte 1 ==
2032 01:25:59.745907 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2033 01:25:59.749377 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2034 01:25:59.749460
2035 01:25:59.752672 [DATLAT]
2036 01:25:59.752755 Freq=800, CH1 RK1
2037 01:25:59.752820
2038 01:25:59.755679 DATLAT Default: 0xa
2039 01:25:59.755762 0, 0xFFFF, sum = 0
2040 01:25:59.759609 1, 0xFFFF, sum = 0
2041 01:25:59.759692 2, 0xFFFF, sum = 0
2042 01:25:59.763007 3, 0xFFFF, sum = 0
2043 01:25:59.763091 4, 0xFFFF, sum = 0
2044 01:25:59.765802 5, 0xFFFF, sum = 0
2045 01:25:59.765886 6, 0xFFFF, sum = 0
2046 01:25:59.769186 7, 0xFFFF, sum = 0
2047 01:25:59.769270 8, 0xFFFF, sum = 0
2048 01:25:59.772921 9, 0x0, sum = 1
2049 01:25:59.773004 10, 0x0, sum = 2
2050 01:25:59.775909 11, 0x0, sum = 3
2051 01:25:59.775992 12, 0x0, sum = 4
2052 01:25:59.779418 best_step = 10
2053 01:25:59.779500
2054 01:25:59.779565 ==
2055 01:25:59.782877 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 01:25:59.785721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 01:25:59.785804 ==
2058 01:25:59.789145 RX Vref Scan: 0
2059 01:25:59.789227
2060 01:25:59.789292 RX Vref 0 -> 0, step: 1
2061 01:25:59.789352
2062 01:25:59.792831 RX Delay -63 -> 252, step: 8
2063 01:25:59.799525 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2064 01:25:59.802681 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2065 01:25:59.805627 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2066 01:25:59.809306 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2067 01:25:59.812858 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2068 01:25:59.815824 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2069 01:25:59.822282 iDelay=209, Bit 6, Center 112 (17 ~ 208) 192
2070 01:25:59.825832 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2071 01:25:59.829360 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2072 01:25:59.832854 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2073 01:25:59.836344 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2074 01:25:59.839639 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2075 01:25:59.846012 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2076 01:25:59.849541 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2077 01:25:59.852969 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2078 01:25:59.856570 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2079 01:25:59.856652 ==
2080 01:25:59.859214 Dram Type= 6, Freq= 0, CH_1, rank 1
2081 01:25:59.865968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2082 01:25:59.866050 ==
2083 01:25:59.866139 DQS Delay:
2084 01:25:59.866201 DQS0 = 0, DQS1 = 0
2085 01:25:59.869697 DQM Delay:
2086 01:25:59.869780 DQM0 = 97, DQM1 = 91
2087 01:25:59.873024 DQ Delay:
2088 01:25:59.876308 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2089 01:25:59.879222 DQ4 =92, DQ5 =112, DQ6 =112, DQ7 =92
2090 01:25:59.882645 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2091 01:25:59.886183 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2092 01:25:59.886265
2093 01:25:59.886386
2094 01:25:59.892614 [DQSOSCAuto] RK1, (LSB)MR18= 0x450e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2095 01:25:59.896082 CH1 RK1: MR19=606, MR18=450E
2096 01:25:59.902475 CH1_RK1: MR19=0x606, MR18=0x450E, DQSOSC=392, MR23=63, INC=96, DEC=64
2097 01:25:59.905894 [RxdqsGatingPostProcess] freq 800
2098 01:25:59.909406 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2099 01:25:59.912861 Pre-setting of DQS Precalculation
2100 01:25:59.919517 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2101 01:25:59.925904 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2102 01:25:59.932315 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2103 01:25:59.932399
2104 01:25:59.932464
2105 01:25:59.935719 [Calibration Summary] 1600 Mbps
2106 01:25:59.935801 CH 0, Rank 0
2107 01:25:59.939193 SW Impedance : PASS
2108 01:25:59.942251 DUTY Scan : NO K
2109 01:25:59.942371 ZQ Calibration : PASS
2110 01:25:59.945875 Jitter Meter : NO K
2111 01:25:59.949090 CBT Training : PASS
2112 01:25:59.949172 Write leveling : PASS
2113 01:25:59.952476 RX DQS gating : PASS
2114 01:25:59.955717 RX DQ/DQS(RDDQC) : PASS
2115 01:25:59.955799 TX DQ/DQS : PASS
2116 01:25:59.958892 RX DATLAT : PASS
2117 01:25:59.962422 RX DQ/DQS(Engine): PASS
2118 01:25:59.962504 TX OE : NO K
2119 01:25:59.962568 All Pass.
2120 01:25:59.965883
2121 01:25:59.965964 CH 0, Rank 1
2122 01:25:59.969417 SW Impedance : PASS
2123 01:25:59.969498 DUTY Scan : NO K
2124 01:25:59.972709 ZQ Calibration : PASS
2125 01:25:59.976166 Jitter Meter : NO K
2126 01:25:59.976251 CBT Training : PASS
2127 01:25:59.978905 Write leveling : PASS
2128 01:25:59.978987 RX DQS gating : PASS
2129 01:25:59.982477 RX DQ/DQS(RDDQC) : PASS
2130 01:25:59.985762 TX DQ/DQS : PASS
2131 01:25:59.985844 RX DATLAT : PASS
2132 01:25:59.989150 RX DQ/DQS(Engine): PASS
2133 01:25:59.992678 TX OE : NO K
2134 01:25:59.992760 All Pass.
2135 01:25:59.992825
2136 01:25:59.992884 CH 1, Rank 0
2137 01:25:59.995563 SW Impedance : PASS
2138 01:25:59.998964 DUTY Scan : NO K
2139 01:25:59.999046 ZQ Calibration : PASS
2140 01:26:00.002418 Jitter Meter : NO K
2141 01:26:00.005793 CBT Training : PASS
2142 01:26:00.005876 Write leveling : PASS
2143 01:26:00.009266 RX DQS gating : PASS
2144 01:26:00.012023 RX DQ/DQS(RDDQC) : PASS
2145 01:26:00.012105 TX DQ/DQS : PASS
2146 01:26:00.015463 RX DATLAT : PASS
2147 01:26:00.019033 RX DQ/DQS(Engine): PASS
2148 01:26:00.019115 TX OE : NO K
2149 01:26:00.019181 All Pass.
2150 01:26:00.022272
2151 01:26:00.022394 CH 1, Rank 1
2152 01:26:00.025830 SW Impedance : PASS
2153 01:26:00.025911 DUTY Scan : NO K
2154 01:26:00.028680 ZQ Calibration : PASS
2155 01:26:00.028763 Jitter Meter : NO K
2156 01:26:00.032259 CBT Training : PASS
2157 01:26:00.035629 Write leveling : PASS
2158 01:26:00.035711 RX DQS gating : PASS
2159 01:26:00.038972 RX DQ/DQS(RDDQC) : PASS
2160 01:26:00.042177 TX DQ/DQS : PASS
2161 01:26:00.042259 RX DATLAT : PASS
2162 01:26:00.045696 RX DQ/DQS(Engine): PASS
2163 01:26:00.048734 TX OE : NO K
2164 01:26:00.048822 All Pass.
2165 01:26:00.048888
2166 01:26:00.048978 DramC Write-DBI off
2167 01:26:00.052656 PER_BANK_REFRESH: Hybrid Mode
2168 01:26:00.055976 TX_TRACKING: ON
2169 01:26:00.059174 [GetDramInforAfterCalByMRR] Vendor 6.
2170 01:26:00.062137 [GetDramInforAfterCalByMRR] Revision 606.
2171 01:26:00.065804 [GetDramInforAfterCalByMRR] Revision 2 0.
2172 01:26:00.065905 MR0 0x3b3b
2173 01:26:00.069181 MR8 0x5151
2174 01:26:00.072663 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 01:26:00.072747
2176 01:26:00.072812 MR0 0x3b3b
2177 01:26:00.072918 MR8 0x5151
2178 01:26:00.075895 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 01:26:00.079292
2180 01:26:00.085905 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2181 01:26:00.089309 [FAST_K] Save calibration result to emmc
2182 01:26:00.092613 [FAST_K] Save calibration result to emmc
2183 01:26:00.096052 dram_init: config_dvfs: 1
2184 01:26:00.098893 dramc_set_vcore_voltage set vcore to 662500
2185 01:26:00.102413 Read voltage for 1200, 2
2186 01:26:00.102519 Vio18 = 0
2187 01:26:00.105837 Vcore = 662500
2188 01:26:00.105919 Vdram = 0
2189 01:26:00.105984 Vddq = 0
2190 01:26:00.106043 Vmddr = 0
2191 01:26:00.112390 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2192 01:26:00.119501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2193 01:26:00.119585 MEM_TYPE=3, freq_sel=15
2194 01:26:00.122221 sv_algorithm_assistance_LP4_1600
2195 01:26:00.125692 ============ PULL DRAM RESETB DOWN ============
2196 01:26:00.132506 ========== PULL DRAM RESETB DOWN end =========
2197 01:26:00.135885 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2198 01:26:00.139441 ===================================
2199 01:26:00.142365 LPDDR4 DRAM CONFIGURATION
2200 01:26:00.145860 ===================================
2201 01:26:00.145943 EX_ROW_EN[0] = 0x0
2202 01:26:00.148705 EX_ROW_EN[1] = 0x0
2203 01:26:00.148787 LP4Y_EN = 0x0
2204 01:26:00.152111 WORK_FSP = 0x0
2205 01:26:00.152193 WL = 0x4
2206 01:26:00.155952 RL = 0x4
2207 01:26:00.156035 BL = 0x2
2208 01:26:00.159250 RPST = 0x0
2209 01:26:00.159334 RD_PRE = 0x0
2210 01:26:00.162541 WR_PRE = 0x1
2211 01:26:00.165348 WR_PST = 0x0
2212 01:26:00.165430 DBI_WR = 0x0
2213 01:26:00.168740 DBI_RD = 0x0
2214 01:26:00.168822 OTF = 0x1
2215 01:26:00.172093 ===================================
2216 01:26:00.175360 ===================================
2217 01:26:00.175442 ANA top config
2218 01:26:00.178870 ===================================
2219 01:26:00.182108 DLL_ASYNC_EN = 0
2220 01:26:00.185381 ALL_SLAVE_EN = 0
2221 01:26:00.189153 NEW_RANK_MODE = 1
2222 01:26:00.192354 DLL_IDLE_MODE = 1
2223 01:26:00.192435 LP45_APHY_COMB_EN = 1
2224 01:26:00.195560 TX_ODT_DIS = 1
2225 01:26:00.198839 NEW_8X_MODE = 1
2226 01:26:00.201882 ===================================
2227 01:26:00.205357 ===================================
2228 01:26:00.208955 data_rate = 2400
2229 01:26:00.211787 CKR = 1
2230 01:26:00.211869 DQ_P2S_RATIO = 8
2231 01:26:00.215134 ===================================
2232 01:26:00.218601 CA_P2S_RATIO = 8
2233 01:26:00.222255 DQ_CA_OPEN = 0
2234 01:26:00.225187 DQ_SEMI_OPEN = 0
2235 01:26:00.228566 CA_SEMI_OPEN = 0
2236 01:26:00.232232 CA_FULL_RATE = 0
2237 01:26:00.232327 DQ_CKDIV4_EN = 0
2238 01:26:00.235521 CA_CKDIV4_EN = 0
2239 01:26:00.239142 CA_PREDIV_EN = 0
2240 01:26:00.241860 PH8_DLY = 17
2241 01:26:00.245440 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2242 01:26:00.248964 DQ_AAMCK_DIV = 4
2243 01:26:00.249046 CA_AAMCK_DIV = 4
2244 01:26:00.252355 CA_ADMCK_DIV = 4
2245 01:26:00.255318 DQ_TRACK_CA_EN = 0
2246 01:26:00.258710 CA_PICK = 1200
2247 01:26:00.262156 CA_MCKIO = 1200
2248 01:26:00.265359 MCKIO_SEMI = 0
2249 01:26:00.268568 PLL_FREQ = 2366
2250 01:26:00.268651 DQ_UI_PI_RATIO = 32
2251 01:26:00.272100 CA_UI_PI_RATIO = 0
2252 01:26:00.275446 ===================================
2253 01:26:00.278850 ===================================
2254 01:26:00.281826 memory_type:LPDDR4
2255 01:26:00.285288 GP_NUM : 10
2256 01:26:00.285442 SRAM_EN : 1
2257 01:26:00.288763 MD32_EN : 0
2258 01:26:00.291691 ===================================
2259 01:26:00.295203 [ANA_INIT] >>>>>>>>>>>>>>
2260 01:26:00.295316 <<<<<< [CONFIGURE PHASE]: ANA_TX
2261 01:26:00.298850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2262 01:26:00.302197 ===================================
2263 01:26:00.305644 data_rate = 2400,PCW = 0X5b00
2264 01:26:00.308538 ===================================
2265 01:26:00.312047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2266 01:26:00.318224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 01:26:00.325185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 01:26:00.328408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2269 01:26:00.332190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2270 01:26:00.335325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2271 01:26:00.338351 [ANA_INIT] flow start
2272 01:26:00.338429 [ANA_INIT] PLL >>>>>>>>
2273 01:26:00.341751 [ANA_INIT] PLL <<<<<<<<
2274 01:26:00.345459 [ANA_INIT] MIDPI >>>>>>>>
2275 01:26:00.345536 [ANA_INIT] MIDPI <<<<<<<<
2276 01:26:00.348402 [ANA_INIT] DLL >>>>>>>>
2277 01:26:00.351670 [ANA_INIT] DLL <<<<<<<<
2278 01:26:00.351745 [ANA_INIT] flow end
2279 01:26:00.358817 ============ LP4 DIFF to SE enter ============
2280 01:26:00.362062 ============ LP4 DIFF to SE exit ============
2281 01:26:00.362144 [ANA_INIT] <<<<<<<<<<<<<
2282 01:26:00.365442 [Flow] Enable top DCM control >>>>>
2283 01:26:00.368911 [Flow] Enable top DCM control <<<<<
2284 01:26:00.372409 Enable DLL master slave shuffle
2285 01:26:00.378573 ==============================================================
2286 01:26:00.382095 Gating Mode config
2287 01:26:00.384938 ==============================================================
2288 01:26:00.388431 Config description:
2289 01:26:00.398432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2290 01:26:00.405434 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2291 01:26:00.409009 SELPH_MODE 0: By rank 1: By Phase
2292 01:26:00.415643 ==============================================================
2293 01:26:00.418335 GAT_TRACK_EN = 1
2294 01:26:00.422261 RX_GATING_MODE = 2
2295 01:26:00.422390 RX_GATING_TRACK_MODE = 2
2296 01:26:00.425743 SELPH_MODE = 1
2297 01:26:00.428580 PICG_EARLY_EN = 1
2298 01:26:00.432187 VALID_LAT_VALUE = 1
2299 01:26:00.438490 ==============================================================
2300 01:26:00.442086 Enter into Gating configuration >>>>
2301 01:26:00.445353 Exit from Gating configuration <<<<
2302 01:26:00.448562 Enter into DVFS_PRE_config >>>>>
2303 01:26:00.458471 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2304 01:26:00.461661 Exit from DVFS_PRE_config <<<<<
2305 01:26:00.465241 Enter into PICG configuration >>>>
2306 01:26:00.468332 Exit from PICG configuration <<<<
2307 01:26:00.472085 [RX_INPUT] configuration >>>>>
2308 01:26:00.475269 [RX_INPUT] configuration <<<<<
2309 01:26:00.478236 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2310 01:26:00.485041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2311 01:26:00.491775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 01:26:00.495274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 01:26:00.501534 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 01:26:00.508604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 01:26:00.512165 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2316 01:26:00.518410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2317 01:26:00.521736 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2318 01:26:00.524979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2319 01:26:00.528451 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2320 01:26:00.535056 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 01:26:00.538394 ===================================
2322 01:26:00.538470 LPDDR4 DRAM CONFIGURATION
2323 01:26:00.542006 ===================================
2324 01:26:00.545424 EX_ROW_EN[0] = 0x0
2325 01:26:00.548335 EX_ROW_EN[1] = 0x0
2326 01:26:00.548434 LP4Y_EN = 0x0
2327 01:26:00.551897 WORK_FSP = 0x0
2328 01:26:00.551998 WL = 0x4
2329 01:26:00.555150 RL = 0x4
2330 01:26:00.555234 BL = 0x2
2331 01:26:00.558354 RPST = 0x0
2332 01:26:00.558425 RD_PRE = 0x0
2333 01:26:00.561893 WR_PRE = 0x1
2334 01:26:00.561995 WR_PST = 0x0
2335 01:26:00.565208 DBI_WR = 0x0
2336 01:26:00.565305 DBI_RD = 0x0
2337 01:26:00.568845 OTF = 0x1
2338 01:26:00.571468 ===================================
2339 01:26:00.575322 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2340 01:26:00.578528 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2341 01:26:00.584844 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2342 01:26:00.588412 ===================================
2343 01:26:00.588526 LPDDR4 DRAM CONFIGURATION
2344 01:26:00.591807 ===================================
2345 01:26:00.594842 EX_ROW_EN[0] = 0x10
2346 01:26:00.594917 EX_ROW_EN[1] = 0x0
2347 01:26:00.598696 LP4Y_EN = 0x0
2348 01:26:00.598773 WORK_FSP = 0x0
2349 01:26:00.602127 WL = 0x4
2350 01:26:00.602223 RL = 0x4
2351 01:26:00.604903 BL = 0x2
2352 01:26:00.608458 RPST = 0x0
2353 01:26:00.608532 RD_PRE = 0x0
2354 01:26:00.611764 WR_PRE = 0x1
2355 01:26:00.611873 WR_PST = 0x0
2356 01:26:00.615224 DBI_WR = 0x0
2357 01:26:00.615333 DBI_RD = 0x0
2358 01:26:00.618120 OTF = 0x1
2359 01:26:00.621438 ===================================
2360 01:26:00.625025 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2361 01:26:00.628451 ==
2362 01:26:00.631814 Dram Type= 6, Freq= 0, CH_0, rank 0
2363 01:26:00.635120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 01:26:00.635214 ==
2365 01:26:00.638492 [Duty_Offset_Calibration]
2366 01:26:00.638565 B0:2 B1:1 CA:1
2367 01:26:00.638625
2368 01:26:00.641858 [DutyScan_Calibration_Flow] k_type=0
2369 01:26:00.650888
2370 01:26:00.650970 ==CLK 0==
2371 01:26:00.654259 Final CLK duty delay cell = 0
2372 01:26:00.657809 [0] MAX Duty = 5187%(X100), DQS PI = 24
2373 01:26:00.661183 [0] MIN Duty = 4875%(X100), DQS PI = 0
2374 01:26:00.661280 [0] AVG Duty = 5031%(X100)
2375 01:26:00.664373
2376 01:26:00.664472 CH0 CLK Duty spec in!! Max-Min= 312%
2377 01:26:00.671128 [DutyScan_Calibration_Flow] ====Done====
2378 01:26:00.671203
2379 01:26:00.674678 [DutyScan_Calibration_Flow] k_type=1
2380 01:26:00.689642
2381 01:26:00.689728 ==DQS 0 ==
2382 01:26:00.692586 Final DQS duty delay cell = -4
2383 01:26:00.695953 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2384 01:26:00.699794 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2385 01:26:00.703035 [-4] AVG Duty = 4937%(X100)
2386 01:26:00.703131
2387 01:26:00.703207 ==DQS 1 ==
2388 01:26:00.706122 Final DQS duty delay cell = 0
2389 01:26:00.709766 [0] MAX Duty = 5156%(X100), DQS PI = 62
2390 01:26:00.713018 [0] MIN Duty = 5000%(X100), DQS PI = 32
2391 01:26:00.715973 [0] AVG Duty = 5078%(X100)
2392 01:26:00.716083
2393 01:26:00.719622 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2394 01:26:00.719708
2395 01:26:00.722733 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2396 01:26:00.726607 [DutyScan_Calibration_Flow] ====Done====
2397 01:26:00.726690
2398 01:26:00.729807 [DutyScan_Calibration_Flow] k_type=3
2399 01:26:00.746353
2400 01:26:00.746437 ==DQM 0 ==
2401 01:26:00.749824 Final DQM duty delay cell = 0
2402 01:26:00.753105 [0] MAX Duty = 5156%(X100), DQS PI = 30
2403 01:26:00.756555 [0] MIN Duty = 4907%(X100), DQS PI = 58
2404 01:26:00.756638 [0] AVG Duty = 5031%(X100)
2405 01:26:00.760032
2406 01:26:00.760140 ==DQM 1 ==
2407 01:26:00.763464 Final DQM duty delay cell = 0
2408 01:26:00.766285 [0] MAX Duty = 5093%(X100), DQS PI = 4
2409 01:26:00.769685 [0] MIN Duty = 5031%(X100), DQS PI = 14
2410 01:26:00.769766 [0] AVG Duty = 5062%(X100)
2411 01:26:00.772983
2412 01:26:00.776340 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2413 01:26:00.776418
2414 01:26:00.779761 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2415 01:26:00.783404 [DutyScan_Calibration_Flow] ====Done====
2416 01:26:00.783476
2417 01:26:00.786212 [DutyScan_Calibration_Flow] k_type=2
2418 01:26:00.802949
2419 01:26:00.803051 ==DQ 0 ==
2420 01:26:00.806380 Final DQ duty delay cell = 0
2421 01:26:00.809249 [0] MAX Duty = 5031%(X100), DQS PI = 26
2422 01:26:00.812652 [0] MIN Duty = 4875%(X100), DQS PI = 0
2423 01:26:00.812765 [0] AVG Duty = 4953%(X100)
2424 01:26:00.812855
2425 01:26:00.816037 ==DQ 1 ==
2426 01:26:00.819393 Final DQ duty delay cell = 0
2427 01:26:00.822841 [0] MAX Duty = 5093%(X100), DQS PI = 24
2428 01:26:00.826030 [0] MIN Duty = 4938%(X100), DQS PI = 36
2429 01:26:00.826135 [0] AVG Duty = 5015%(X100)
2430 01:26:00.826226
2431 01:26:00.829306 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2432 01:26:00.829407
2433 01:26:00.832531 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2434 01:26:00.839537 [DutyScan_Calibration_Flow] ====Done====
2435 01:26:00.839643 ==
2436 01:26:00.842715 Dram Type= 6, Freq= 0, CH_1, rank 0
2437 01:26:00.846427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2438 01:26:00.846510 ==
2439 01:26:00.849588 [Duty_Offset_Calibration]
2440 01:26:00.849663 B0:1 B1:0 CA:0
2441 01:26:00.849726
2442 01:26:00.852593 [DutyScan_Calibration_Flow] k_type=0
2443 01:26:00.862085
2444 01:26:00.862188 ==CLK 0==
2445 01:26:00.865324 Final CLK duty delay cell = -4
2446 01:26:00.868815 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2447 01:26:00.872441 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2448 01:26:00.875278 [-4] AVG Duty = 4937%(X100)
2449 01:26:00.875360
2450 01:26:00.878510 CH1 CLK Duty spec in!! Max-Min= 125%
2451 01:26:00.882017 [DutyScan_Calibration_Flow] ====Done====
2452 01:26:00.882117
2453 01:26:00.885656 [DutyScan_Calibration_Flow] k_type=1
2454 01:26:00.902135
2455 01:26:00.902251 ==DQS 0 ==
2456 01:26:00.904854 Final DQS duty delay cell = 0
2457 01:26:00.908238 [0] MAX Duty = 5094%(X100), DQS PI = 26
2458 01:26:00.911803 [0] MIN Duty = 4875%(X100), DQS PI = 0
2459 01:26:00.911902 [0] AVG Duty = 4984%(X100)
2460 01:26:00.915225
2461 01:26:00.915321 ==DQS 1 ==
2462 01:26:00.918837 Final DQS duty delay cell = 0
2463 01:26:00.921508 [0] MAX Duty = 5187%(X100), DQS PI = 18
2464 01:26:00.925103 [0] MIN Duty = 4969%(X100), DQS PI = 10
2465 01:26:00.925201 [0] AVG Duty = 5078%(X100)
2466 01:26:00.928554
2467 01:26:00.932150 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2468 01:26:00.932222
2469 01:26:00.935393 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2470 01:26:00.938110 [DutyScan_Calibration_Flow] ====Done====
2471 01:26:00.938206
2472 01:26:00.941483 [DutyScan_Calibration_Flow] k_type=3
2473 01:26:00.958562
2474 01:26:00.958644 ==DQM 0 ==
2475 01:26:00.961720 Final DQM duty delay cell = 0
2476 01:26:00.964907 [0] MAX Duty = 5156%(X100), DQS PI = 6
2477 01:26:00.968191 [0] MIN Duty = 5031%(X100), DQS PI = 0
2478 01:26:00.968294 [0] AVG Duty = 5093%(X100)
2479 01:26:00.968383
2480 01:26:00.971495 ==DQM 1 ==
2481 01:26:00.974574 Final DQM duty delay cell = 0
2482 01:26:00.977844 [0] MAX Duty = 5031%(X100), DQS PI = 16
2483 01:26:00.981684 [0] MIN Duty = 4907%(X100), DQS PI = 34
2484 01:26:00.981782 [0] AVG Duty = 4969%(X100)
2485 01:26:00.984932
2486 01:26:00.988174 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2487 01:26:00.988268
2488 01:26:00.991479 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2489 01:26:00.994863 [DutyScan_Calibration_Flow] ====Done====
2490 01:26:00.994942
2491 01:26:00.998261 [DutyScan_Calibration_Flow] k_type=2
2492 01:26:01.013984
2493 01:26:01.014072 ==DQ 0 ==
2494 01:26:01.017519 Final DQ duty delay cell = -4
2495 01:26:01.020495 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2496 01:26:01.023928 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2497 01:26:01.027507 [-4] AVG Duty = 4984%(X100)
2498 01:26:01.027587
2499 01:26:01.027650 ==DQ 1 ==
2500 01:26:01.030394 Final DQ duty delay cell = 0
2501 01:26:01.033906 [0] MAX Duty = 5125%(X100), DQS PI = 20
2502 01:26:01.037512 [0] MIN Duty = 4969%(X100), DQS PI = 12
2503 01:26:01.037630 [0] AVG Duty = 5047%(X100)
2504 01:26:01.040999
2505 01:26:01.043907 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2506 01:26:01.044012
2507 01:26:01.047289 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2508 01:26:01.050875 [DutyScan_Calibration_Flow] ====Done====
2509 01:26:01.054365 nWR fixed to 30
2510 01:26:01.054442 [ModeRegInit_LP4] CH0 RK0
2511 01:26:01.057096 [ModeRegInit_LP4] CH0 RK1
2512 01:26:01.060672 [ModeRegInit_LP4] CH1 RK0
2513 01:26:01.060770 [ModeRegInit_LP4] CH1 RK1
2514 01:26:01.064341 match AC timing 7
2515 01:26:01.067112 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2516 01:26:01.071112 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2517 01:26:01.077838 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2518 01:26:01.081128 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2519 01:26:01.087431 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2520 01:26:01.087558 ==
2521 01:26:01.090979 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 01:26:01.094393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 01:26:01.094475 ==
2524 01:26:01.100891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2525 01:26:01.104039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2526 01:26:01.114492 [CA 0] Center 39 (8~70) winsize 63
2527 01:26:01.117920 [CA 1] Center 39 (8~70) winsize 63
2528 01:26:01.120660 [CA 2] Center 35 (5~66) winsize 62
2529 01:26:01.124177 [CA 3] Center 34 (4~65) winsize 62
2530 01:26:01.127795 [CA 4] Center 33 (3~64) winsize 62
2531 01:26:01.131242 [CA 5] Center 32 (3~62) winsize 60
2532 01:26:01.131325
2533 01:26:01.134187 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2534 01:26:01.134270
2535 01:26:01.137806 [CATrainingPosCal] consider 1 rank data
2536 01:26:01.141130 u2DelayCellTimex100 = 270/100 ps
2537 01:26:01.144440 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2538 01:26:01.147954 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2539 01:26:01.154188 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2540 01:26:01.157781 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2541 01:26:01.161302 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2542 01:26:01.164140 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2543 01:26:01.164240
2544 01:26:01.167500 CA PerBit enable=1, Macro0, CA PI delay=32
2545 01:26:01.167603
2546 01:26:01.170922 [CBTSetCACLKResult] CA Dly = 32
2547 01:26:01.171002 CS Dly: 6 (0~37)
2548 01:26:01.171066 ==
2549 01:26:01.174338 Dram Type= 6, Freq= 0, CH_0, rank 1
2550 01:26:01.181222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 01:26:01.181299 ==
2552 01:26:01.184112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2553 01:26:01.190859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2554 01:26:01.200209 [CA 0] Center 38 (8~69) winsize 62
2555 01:26:01.203449 [CA 1] Center 38 (8~69) winsize 62
2556 01:26:01.206393 [CA 2] Center 35 (4~66) winsize 63
2557 01:26:01.209695 [CA 3] Center 34 (4~65) winsize 62
2558 01:26:01.213054 [CA 4] Center 33 (3~64) winsize 62
2559 01:26:01.216731 [CA 5] Center 32 (3~62) winsize 60
2560 01:26:01.216809
2561 01:26:01.219813 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2562 01:26:01.219914
2563 01:26:01.223249 [CATrainingPosCal] consider 2 rank data
2564 01:26:01.226914 u2DelayCellTimex100 = 270/100 ps
2565 01:26:01.229991 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2566 01:26:01.233209 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2567 01:26:01.240219 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2568 01:26:01.243147 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2569 01:26:01.246563 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2570 01:26:01.250050 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2571 01:26:01.250161
2572 01:26:01.253454 CA PerBit enable=1, Macro0, CA PI delay=32
2573 01:26:01.253556
2574 01:26:01.256878 [CBTSetCACLKResult] CA Dly = 32
2575 01:26:01.256976 CS Dly: 6 (0~38)
2576 01:26:01.257069
2577 01:26:01.260411 ----->DramcWriteLeveling(PI) begin...
2578 01:26:01.260524 ==
2579 01:26:01.263233 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 01:26:01.270098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 01:26:01.270201 ==
2582 01:26:01.273582 Write leveling (Byte 0): 34 => 34
2583 01:26:01.276567 Write leveling (Byte 1): 29 => 29
2584 01:26:01.276678 DramcWriteLeveling(PI) end<-----
2585 01:26:01.279920
2586 01:26:01.280020 ==
2587 01:26:01.283526 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 01:26:01.286928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 01:26:01.287034 ==
2590 01:26:01.290446 [Gating] SW mode calibration
2591 01:26:01.296819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2592 01:26:01.300167 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2593 01:26:01.306561 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2594 01:26:01.309783 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2595 01:26:01.313229 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 01:26:01.320363 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 01:26:01.323117 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 01:26:01.326533 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 01:26:01.333760 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2600 01:26:01.336817 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
2601 01:26:01.340026 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2602 01:26:01.347099 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 01:26:01.350158 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 01:26:01.353421 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 01:26:01.360142 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 01:26:01.363510 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 01:26:01.367034 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2608 01:26:01.370510 1 0 28 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
2609 01:26:01.376617 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2610 01:26:01.380153 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 01:26:01.383627 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 01:26:01.390466 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 01:26:01.393849 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 01:26:01.396632 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 01:26:01.403584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 01:26:01.406942 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2617 01:26:01.410322 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 01:26:01.416697 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 01:26:01.419991 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 01:26:01.423447 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 01:26:01.430288 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 01:26:01.433276 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 01:26:01.436699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 01:26:01.443655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 01:26:01.446449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 01:26:01.449805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 01:26:01.457122 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 01:26:01.460338 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 01:26:01.463727 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 01:26:01.469962 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 01:26:01.473448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 01:26:01.476938 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2633 01:26:01.479904 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 01:26:01.483324 Total UI for P1: 0, mck2ui 16
2635 01:26:01.486911 best dqsien dly found for B0: ( 1, 3, 26)
2636 01:26:01.490443 Total UI for P1: 0, mck2ui 16
2637 01:26:01.493152 best dqsien dly found for B1: ( 1, 3, 30)
2638 01:26:01.496450 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2639 01:26:01.500053 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2640 01:26:01.503565
2641 01:26:01.506493 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2642 01:26:01.509778 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2643 01:26:01.513195 [Gating] SW calibration Done
2644 01:26:01.513293 ==
2645 01:26:01.516565 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 01:26:01.520523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 01:26:01.520605 ==
2648 01:26:01.520672 RX Vref Scan: 0
2649 01:26:01.520732
2650 01:26:01.523344 RX Vref 0 -> 0, step: 1
2651 01:26:01.523455
2652 01:26:01.526638 RX Delay -40 -> 252, step: 8
2653 01:26:01.530045 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2654 01:26:01.533305 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2655 01:26:01.540341 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2656 01:26:01.543133 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2657 01:26:01.546585 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2658 01:26:01.549959 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2659 01:26:01.553363 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2660 01:26:01.560240 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2661 01:26:01.563646 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2662 01:26:01.566450 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2663 01:26:01.569925 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2664 01:26:01.573252 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2665 01:26:01.579982 iDelay=200, Bit 12, Center 119 (56 ~ 183) 128
2666 01:26:01.583374 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2667 01:26:01.586832 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2668 01:26:01.590066 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2669 01:26:01.590148 ==
2670 01:26:01.593748 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 01:26:01.596436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 01:26:01.599758 ==
2673 01:26:01.599839 DQS Delay:
2674 01:26:01.599905 DQS0 = 0, DQS1 = 0
2675 01:26:01.603244 DQM Delay:
2676 01:26:01.603327 DQM0 = 121, DQM1 = 114
2677 01:26:01.606537 DQ Delay:
2678 01:26:01.610099 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2679 01:26:01.613393 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2680 01:26:01.616800 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2681 01:26:01.620291 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =123
2682 01:26:01.620467
2683 01:26:01.620562
2684 01:26:01.620650 ==
2685 01:26:01.623687 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 01:26:01.627063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 01:26:01.627167 ==
2688 01:26:01.627258
2689 01:26:01.627346
2690 01:26:01.629761 TX Vref Scan disable
2691 01:26:01.633084 == TX Byte 0 ==
2692 01:26:01.636973 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2693 01:26:01.639613 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2694 01:26:01.643046 == TX Byte 1 ==
2695 01:26:01.646562 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2696 01:26:01.650038 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2697 01:26:01.650140 ==
2698 01:26:01.653530 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 01:26:01.659885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 01:26:01.659988 ==
2701 01:26:01.670829 TX Vref=22, minBit 0, minWin=25, winSum=409
2702 01:26:01.674239 TX Vref=24, minBit 1, minWin=25, winSum=411
2703 01:26:01.677045 TX Vref=26, minBit 7, minWin=25, winSum=419
2704 01:26:01.680505 TX Vref=28, minBit 10, minWin=25, winSum=421
2705 01:26:01.683938 TX Vref=30, minBit 0, minWin=26, winSum=423
2706 01:26:01.690475 TX Vref=32, minBit 5, minWin=25, winSum=424
2707 01:26:01.693786 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
2708 01:26:01.693894
2709 01:26:01.697230 Final TX Range 1 Vref 30
2710 01:26:01.697333
2711 01:26:01.697426 ==
2712 01:26:01.700773 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 01:26:01.704210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 01:26:01.704313 ==
2715 01:26:01.704404
2716 01:26:01.707563
2717 01:26:01.707662 TX Vref Scan disable
2718 01:26:01.710954 == TX Byte 0 ==
2719 01:26:01.713790 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2720 01:26:01.717247 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2721 01:26:01.720732 == TX Byte 1 ==
2722 01:26:01.724201 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2723 01:26:01.727724 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2724 01:26:01.727827
2725 01:26:01.730976 [DATLAT]
2726 01:26:01.731083 Freq=1200, CH0 RK0
2727 01:26:01.731175
2728 01:26:01.734432 DATLAT Default: 0xd
2729 01:26:01.734527 0, 0xFFFF, sum = 0
2730 01:26:01.737182 1, 0xFFFF, sum = 0
2731 01:26:01.737283 2, 0xFFFF, sum = 0
2732 01:26:01.740652 3, 0xFFFF, sum = 0
2733 01:26:01.740751 4, 0xFFFF, sum = 0
2734 01:26:01.744068 5, 0xFFFF, sum = 0
2735 01:26:01.744174 6, 0xFFFF, sum = 0
2736 01:26:01.747445 7, 0xFFFF, sum = 0
2737 01:26:01.747546 8, 0xFFFF, sum = 0
2738 01:26:01.750779 9, 0xFFFF, sum = 0
2739 01:26:01.754218 10, 0xFFFF, sum = 0
2740 01:26:01.754342 11, 0xFFFF, sum = 0
2741 01:26:01.757619 12, 0x0, sum = 1
2742 01:26:01.757717 13, 0x0, sum = 2
2743 01:26:01.757814 14, 0x0, sum = 3
2744 01:26:01.761029 15, 0x0, sum = 4
2745 01:26:01.761125 best_step = 13
2746 01:26:01.761212
2747 01:26:01.763905 ==
2748 01:26:01.763998 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 01:26:01.770854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 01:26:01.770957 ==
2751 01:26:01.771050 RX Vref Scan: 1
2752 01:26:01.771137
2753 01:26:01.774223 Set Vref Range= 32 -> 127
2754 01:26:01.774357
2755 01:26:01.777701 RX Vref 32 -> 127, step: 1
2756 01:26:01.777793
2757 01:26:01.781112 RX Delay -13 -> 252, step: 4
2758 01:26:01.781194
2759 01:26:01.784462 Set Vref, RX VrefLevel [Byte0]: 32
2760 01:26:01.787924 [Byte1]: 32
2761 01:26:01.788005
2762 01:26:01.790628 Set Vref, RX VrefLevel [Byte0]: 33
2763 01:26:01.793893 [Byte1]: 33
2764 01:26:01.793974
2765 01:26:01.797285 Set Vref, RX VrefLevel [Byte0]: 34
2766 01:26:01.800743 [Byte1]: 34
2767 01:26:01.804739
2768 01:26:01.804835 Set Vref, RX VrefLevel [Byte0]: 35
2769 01:26:01.808169 [Byte1]: 35
2770 01:26:01.812399
2771 01:26:01.812481 Set Vref, RX VrefLevel [Byte0]: 36
2772 01:26:01.815840 [Byte1]: 36
2773 01:26:01.820390
2774 01:26:01.820501 Set Vref, RX VrefLevel [Byte0]: 37
2775 01:26:01.823883 [Byte1]: 37
2776 01:26:01.828669
2777 01:26:01.828777 Set Vref, RX VrefLevel [Byte0]: 38
2778 01:26:01.831374 [Byte1]: 38
2779 01:26:01.836121
2780 01:26:01.836229 Set Vref, RX VrefLevel [Byte0]: 39
2781 01:26:01.839508 [Byte1]: 39
2782 01:26:01.844420
2783 01:26:01.844522 Set Vref, RX VrefLevel [Byte0]: 40
2784 01:26:01.847875 [Byte1]: 40
2785 01:26:01.852001
2786 01:26:01.852104 Set Vref, RX VrefLevel [Byte0]: 41
2787 01:26:01.855337 [Byte1]: 41
2788 01:26:01.859642
2789 01:26:01.859746 Set Vref, RX VrefLevel [Byte0]: 42
2790 01:26:01.863148 [Byte1]: 42
2791 01:26:01.867615
2792 01:26:01.867724 Set Vref, RX VrefLevel [Byte0]: 43
2793 01:26:01.871099 [Byte1]: 43
2794 01:26:01.875911
2795 01:26:01.876017 Set Vref, RX VrefLevel [Byte0]: 44
2796 01:26:01.878787 [Byte1]: 44
2797 01:26:01.883577
2798 01:26:01.883689 Set Vref, RX VrefLevel [Byte0]: 45
2799 01:26:01.886780 [Byte1]: 45
2800 01:26:01.891455
2801 01:26:01.891568 Set Vref, RX VrefLevel [Byte0]: 46
2802 01:26:01.894806 [Byte1]: 46
2803 01:26:01.899618
2804 01:26:01.899716 Set Vref, RX VrefLevel [Byte0]: 47
2805 01:26:01.902360 [Byte1]: 47
2806 01:26:01.907203
2807 01:26:01.907306 Set Vref, RX VrefLevel [Byte0]: 48
2808 01:26:01.910544 [Byte1]: 48
2809 01:26:01.915010
2810 01:26:01.915114 Set Vref, RX VrefLevel [Byte0]: 49
2811 01:26:01.918506 [Byte1]: 49
2812 01:26:01.923384
2813 01:26:01.923485 Set Vref, RX VrefLevel [Byte0]: 50
2814 01:26:01.926159 [Byte1]: 50
2815 01:26:01.930810
2816 01:26:01.930919 Set Vref, RX VrefLevel [Byte0]: 51
2817 01:26:01.934163 [Byte1]: 51
2818 01:26:01.939152
2819 01:26:01.939259 Set Vref, RX VrefLevel [Byte0]: 52
2820 01:26:01.942414 [Byte1]: 52
2821 01:26:01.946598
2822 01:26:01.946700 Set Vref, RX VrefLevel [Byte0]: 53
2823 01:26:01.950093 [Byte1]: 53
2824 01:26:01.955055
2825 01:26:01.955155 Set Vref, RX VrefLevel [Byte0]: 54
2826 01:26:01.957871 [Byte1]: 54
2827 01:26:01.962391
2828 01:26:01.962494 Set Vref, RX VrefLevel [Byte0]: 55
2829 01:26:01.965921 [Byte1]: 55
2830 01:26:01.970587
2831 01:26:01.970672 Set Vref, RX VrefLevel [Byte0]: 56
2832 01:26:01.973954 [Byte1]: 56
2833 01:26:01.978074
2834 01:26:01.978158 Set Vref, RX VrefLevel [Byte0]: 57
2835 01:26:01.981638 [Byte1]: 57
2836 01:26:01.986553
2837 01:26:01.986636 Set Vref, RX VrefLevel [Byte0]: 58
2838 01:26:01.989402 [Byte1]: 58
2839 01:26:01.994104
2840 01:26:01.994187 Set Vref, RX VrefLevel [Byte0]: 59
2841 01:26:01.997227 [Byte1]: 59
2842 01:26:02.002275
2843 01:26:02.002376 Set Vref, RX VrefLevel [Byte0]: 60
2844 01:26:02.005104 [Byte1]: 60
2845 01:26:02.009965
2846 01:26:02.010049 Set Vref, RX VrefLevel [Byte0]: 61
2847 01:26:02.013395 [Byte1]: 61
2848 01:26:02.017637
2849 01:26:02.017720 Set Vref, RX VrefLevel [Byte0]: 62
2850 01:26:02.020844 [Byte1]: 62
2851 01:26:02.025466
2852 01:26:02.025550 Set Vref, RX VrefLevel [Byte0]: 63
2853 01:26:02.028825 [Byte1]: 63
2854 01:26:02.033682
2855 01:26:02.033764 Set Vref, RX VrefLevel [Byte0]: 64
2856 01:26:02.037096 [Byte1]: 64
2857 01:26:02.041557
2858 01:26:02.041667 Set Vref, RX VrefLevel [Byte0]: 65
2859 01:26:02.045049 [Byte1]: 65
2860 01:26:02.049096
2861 01:26:02.049231 Set Vref, RX VrefLevel [Byte0]: 66
2862 01:26:02.052616 [Byte1]: 66
2863 01:26:02.057678
2864 01:26:02.057760 Set Vref, RX VrefLevel [Byte0]: 67
2865 01:26:02.060429 [Byte1]: 67
2866 01:26:02.065099
2867 01:26:02.065186 Set Vref, RX VrefLevel [Byte0]: 68
2868 01:26:02.068617 [Byte1]: 68
2869 01:26:02.072871
2870 01:26:02.072967 Set Vref, RX VrefLevel [Byte0]: 69
2871 01:26:02.076168 [Byte1]: 69
2872 01:26:02.080583
2873 01:26:02.080671 Set Vref, RX VrefLevel [Byte0]: 70
2874 01:26:02.084123 [Byte1]: 70
2875 01:26:02.088997
2876 01:26:02.089113 Set Vref, RX VrefLevel [Byte0]: 71
2877 01:26:02.091803 [Byte1]: 71
2878 01:26:02.096769
2879 01:26:02.096846 Final RX Vref Byte 0 = 56 to rank0
2880 01:26:02.100235 Final RX Vref Byte 1 = 46 to rank0
2881 01:26:02.103123 Final RX Vref Byte 0 = 56 to rank1
2882 01:26:02.107080 Final RX Vref Byte 1 = 46 to rank1==
2883 01:26:02.110118 Dram Type= 6, Freq= 0, CH_0, rank 0
2884 01:26:02.116397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 01:26:02.116514 ==
2886 01:26:02.116581 DQS Delay:
2887 01:26:02.116642 DQS0 = 0, DQS1 = 0
2888 01:26:02.120023 DQM Delay:
2889 01:26:02.120098 DQM0 = 120, DQM1 = 110
2890 01:26:02.123479 DQ Delay:
2891 01:26:02.126810 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =120
2892 01:26:02.130196 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2893 01:26:02.133362 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
2894 01:26:02.136859 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =118
2895 01:26:02.136965
2896 01:26:02.137033
2897 01:26:02.143802 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2898 01:26:02.147073 CH0 RK0: MR19=404, MR18=120B
2899 01:26:02.153625 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2900 01:26:02.153712
2901 01:26:02.156823 ----->DramcWriteLeveling(PI) begin...
2902 01:26:02.156907 ==
2903 01:26:02.160139 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 01:26:02.163811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 01:26:02.163895 ==
2906 01:26:02.166544 Write leveling (Byte 0): 36 => 36
2907 01:26:02.170314 Write leveling (Byte 1): 29 => 29
2908 01:26:02.173228 DramcWriteLeveling(PI) end<-----
2909 01:26:02.173310
2910 01:26:02.173376 ==
2911 01:26:02.176897 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 01:26:02.183644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 01:26:02.183730 ==
2914 01:26:02.183795 [Gating] SW mode calibration
2915 01:26:02.193911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2916 01:26:02.197102 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2917 01:26:02.200041 0 15 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
2918 01:26:02.206908 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 01:26:02.210510 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 01:26:02.213899 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 01:26:02.220365 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 01:26:02.223694 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 01:26:02.227009 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 01:26:02.233862 0 15 28 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (0 1)
2925 01:26:02.237336 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2926 01:26:02.240719 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 01:26:02.243998 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 01:26:02.250872 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 01:26:02.253541 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 01:26:02.256959 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 01:26:02.263797 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 01:26:02.266978 1 0 28 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
2933 01:26:02.270278 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2934 01:26:02.277057 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 01:26:02.280642 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 01:26:02.284151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 01:26:02.290946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 01:26:02.293666 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 01:26:02.297105 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 01:26:02.303958 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2941 01:26:02.307557 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 01:26:02.310280 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 01:26:02.317488 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 01:26:02.320231 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 01:26:02.323868 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 01:26:02.330472 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 01:26:02.333717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 01:26:02.337138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 01:26:02.340429 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 01:26:02.347368 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 01:26:02.350684 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 01:26:02.353987 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 01:26:02.360524 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 01:26:02.363756 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 01:26:02.367026 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 01:26:02.373742 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2957 01:26:02.377062 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 01:26:02.380265 Total UI for P1: 0, mck2ui 16
2959 01:26:02.383371 best dqsien dly found for B0: ( 1, 3, 28)
2960 01:26:02.387218 Total UI for P1: 0, mck2ui 16
2961 01:26:02.389984 best dqsien dly found for B1: ( 1, 3, 28)
2962 01:26:02.393556 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2963 01:26:02.396991 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2964 01:26:02.397066
2965 01:26:02.400198 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 01:26:02.403670 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2967 01:26:02.407025 [Gating] SW calibration Done
2968 01:26:02.407097 ==
2969 01:26:02.410514 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 01:26:02.413515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 01:26:02.416946 ==
2972 01:26:02.417019 RX Vref Scan: 0
2973 01:26:02.417081
2974 01:26:02.420682 RX Vref 0 -> 0, step: 1
2975 01:26:02.420751
2976 01:26:02.423505 RX Delay -40 -> 252, step: 8
2977 01:26:02.426828 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2978 01:26:02.430451 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2979 01:26:02.433604 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2980 01:26:02.437084 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2981 01:26:02.443746 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2982 01:26:02.447046 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2983 01:26:02.449920 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2984 01:26:02.453630 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2985 01:26:02.457114 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2986 01:26:02.460436 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2987 01:26:02.466926 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2988 01:26:02.470087 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2989 01:26:02.473370 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2990 01:26:02.477140 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2991 01:26:02.480296 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2992 01:26:02.487445 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2993 01:26:02.487524 ==
2994 01:26:02.490150 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 01:26:02.494087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 01:26:02.494171 ==
2997 01:26:02.494236 DQS Delay:
2998 01:26:02.497301 DQS0 = 0, DQS1 = 0
2999 01:26:02.497383 DQM Delay:
3000 01:26:02.500749 DQM0 = 122, DQM1 = 111
3001 01:26:02.500824 DQ Delay:
3002 01:26:02.504016 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
3003 01:26:02.507332 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
3004 01:26:02.510679 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3005 01:26:02.514151 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
3006 01:26:02.514234
3007 01:26:02.514298
3008 01:26:02.516936 ==
3009 01:26:02.520559 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 01:26:02.524084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 01:26:02.524167 ==
3012 01:26:02.524232
3013 01:26:02.524292
3014 01:26:02.526907 TX Vref Scan disable
3015 01:26:02.526996 == TX Byte 0 ==
3016 01:26:02.530284 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
3017 01:26:02.537301 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
3018 01:26:02.537384 == TX Byte 1 ==
3019 01:26:02.540203 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3020 01:26:02.546858 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3021 01:26:02.546986 ==
3022 01:26:02.550239 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 01:26:02.553501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 01:26:02.553584 ==
3025 01:26:02.566283 TX Vref=22, minBit 1, minWin=25, winSum=414
3026 01:26:02.569798 TX Vref=24, minBit 1, minWin=24, winSum=417
3027 01:26:02.573079 TX Vref=26, minBit 1, minWin=26, winSum=424
3028 01:26:02.576516 TX Vref=28, minBit 0, minWin=26, winSum=430
3029 01:26:02.579745 TX Vref=30, minBit 1, minWin=26, winSum=433
3030 01:26:02.586295 TX Vref=32, minBit 0, minWin=25, winSum=426
3031 01:26:02.589477 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
3032 01:26:02.589560
3033 01:26:02.593034 Final TX Range 1 Vref 30
3034 01:26:02.593117
3035 01:26:02.593181 ==
3036 01:26:02.596420 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 01:26:02.599754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 01:26:02.602936 ==
3039 01:26:02.603023
3040 01:26:02.603088
3041 01:26:02.603149 TX Vref Scan disable
3042 01:26:02.605837 == TX Byte 0 ==
3043 01:26:02.609712 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
3044 01:26:02.612876 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
3045 01:26:02.616634 == TX Byte 1 ==
3046 01:26:02.619799 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3047 01:26:02.622897 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3048 01:26:02.626161
3049 01:26:02.626244 [DATLAT]
3050 01:26:02.626336 Freq=1200, CH0 RK1
3051 01:26:02.626413
3052 01:26:02.629619 DATLAT Default: 0xd
3053 01:26:02.629701 0, 0xFFFF, sum = 0
3054 01:26:02.633194 1, 0xFFFF, sum = 0
3055 01:26:02.633277 2, 0xFFFF, sum = 0
3056 01:26:02.636023 3, 0xFFFF, sum = 0
3057 01:26:02.636107 4, 0xFFFF, sum = 0
3058 01:26:02.639485 5, 0xFFFF, sum = 0
3059 01:26:02.642911 6, 0xFFFF, sum = 0
3060 01:26:02.642988 7, 0xFFFF, sum = 0
3061 01:26:02.646242 8, 0xFFFF, sum = 0
3062 01:26:02.646377 9, 0xFFFF, sum = 0
3063 01:26:02.649660 10, 0xFFFF, sum = 0
3064 01:26:02.649742 11, 0xFFFF, sum = 0
3065 01:26:02.653118 12, 0x0, sum = 1
3066 01:26:02.653200 13, 0x0, sum = 2
3067 01:26:02.656439 14, 0x0, sum = 3
3068 01:26:02.656520 15, 0x0, sum = 4
3069 01:26:02.656585 best_step = 13
3070 01:26:02.656643
3071 01:26:02.659823 ==
3072 01:26:02.662587 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 01:26:02.666102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 01:26:02.666183 ==
3075 01:26:02.666247 RX Vref Scan: 0
3076 01:26:02.666315
3077 01:26:02.669449 RX Vref 0 -> 0, step: 1
3078 01:26:02.669529
3079 01:26:02.673191 RX Delay -13 -> 252, step: 4
3080 01:26:02.675998 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3081 01:26:02.683081 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3082 01:26:02.686236 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3083 01:26:02.689683 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3084 01:26:02.692943 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3085 01:26:02.696435 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3086 01:26:02.699686 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3087 01:26:02.706146 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3088 01:26:02.709621 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3089 01:26:02.713011 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3090 01:26:02.716421 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3091 01:26:02.719762 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3092 01:26:02.726469 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3093 01:26:02.729806 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3094 01:26:02.732989 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3095 01:26:02.736005 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3096 01:26:02.736088 ==
3097 01:26:02.739901 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 01:26:02.746165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 01:26:02.746248 ==
3100 01:26:02.746337 DQS Delay:
3101 01:26:02.749747 DQS0 = 0, DQS1 = 0
3102 01:26:02.749829 DQM Delay:
3103 01:26:02.749893 DQM0 = 121, DQM1 = 109
3104 01:26:02.753205 DQ Delay:
3105 01:26:02.756481 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3106 01:26:02.759454 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3107 01:26:02.762767 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3108 01:26:02.766169 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3109 01:26:02.766252
3110 01:26:02.766358
3111 01:26:02.773186 [DQSOSCAuto] RK1, (LSB)MR18= 0xbed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3112 01:26:02.776729 CH0 RK1: MR19=403, MR18=BED
3113 01:26:02.783069 CH0_RK1: MR19=0x403, MR18=0xBED, DQSOSC=405, MR23=63, INC=39, DEC=26
3114 01:26:02.786670 [RxdqsGatingPostProcess] freq 1200
3115 01:26:02.792817 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3116 01:26:02.796196 best DQS0 dly(2T, 0.5T) = (0, 11)
3117 01:26:02.796279 best DQS1 dly(2T, 0.5T) = (0, 11)
3118 01:26:02.799602 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3119 01:26:02.803424 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3120 01:26:02.806882 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 01:26:02.809647 best DQS1 dly(2T, 0.5T) = (0, 11)
3122 01:26:02.812883 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 01:26:02.816296 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3124 01:26:02.819740 Pre-setting of DQS Precalculation
3125 01:26:02.826832 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3126 01:26:02.826916 ==
3127 01:26:02.830188 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 01:26:02.833086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 01:26:02.833169 ==
3130 01:26:02.840109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 01:26:02.843477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3132 01:26:02.852433 [CA 0] Center 37 (7~68) winsize 62
3133 01:26:02.855729 [CA 1] Center 37 (7~68) winsize 62
3134 01:26:02.859500 [CA 2] Center 35 (5~65) winsize 61
3135 01:26:02.862679 [CA 3] Center 34 (4~64) winsize 61
3136 01:26:02.866251 [CA 4] Center 34 (4~64) winsize 61
3137 01:26:02.869690 [CA 5] Center 33 (3~63) winsize 61
3138 01:26:02.869772
3139 01:26:02.873008 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3140 01:26:02.873090
3141 01:26:02.875895 [CATrainingPosCal] consider 1 rank data
3142 01:26:02.879370 u2DelayCellTimex100 = 270/100 ps
3143 01:26:02.882835 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 01:26:02.886315 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3145 01:26:02.889257 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3146 01:26:02.895788 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 01:26:02.899186 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 01:26:02.902668 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 01:26:02.902750
3150 01:26:02.906097 CA PerBit enable=1, Macro0, CA PI delay=33
3151 01:26:02.906179
3152 01:26:02.909479 [CBTSetCACLKResult] CA Dly = 33
3153 01:26:02.909562 CS Dly: 7 (0~38)
3154 01:26:02.909627 ==
3155 01:26:02.912896 Dram Type= 6, Freq= 0, CH_1, rank 1
3156 01:26:02.919192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 01:26:02.919275 ==
3158 01:26:02.922613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 01:26:02.929447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3160 01:26:02.938056 [CA 0] Center 37 (7~68) winsize 62
3161 01:26:02.941470 [CA 1] Center 37 (7~68) winsize 62
3162 01:26:02.944802 [CA 2] Center 35 (5~65) winsize 61
3163 01:26:02.948402 [CA 3] Center 35 (5~65) winsize 61
3164 01:26:02.951274 [CA 4] Center 34 (4~65) winsize 62
3165 01:26:02.954909 [CA 5] Center 34 (4~64) winsize 61
3166 01:26:02.954992
3167 01:26:02.958120 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3168 01:26:02.958203
3169 01:26:02.961305 [CATrainingPosCal] consider 2 rank data
3170 01:26:02.964730 u2DelayCellTimex100 = 270/100 ps
3171 01:26:02.967845 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 01:26:02.974702 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3173 01:26:02.977789 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3174 01:26:02.981077 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3175 01:26:02.984590 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 01:26:02.988151 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3177 01:26:02.988234
3178 01:26:02.991707 CA PerBit enable=1, Macro0, CA PI delay=33
3179 01:26:02.991790
3180 01:26:02.994388 [CBTSetCACLKResult] CA Dly = 33
3181 01:26:02.994470 CS Dly: 8 (0~41)
3182 01:26:02.997866
3183 01:26:03.001098 ----->DramcWriteLeveling(PI) begin...
3184 01:26:03.001185 ==
3185 01:26:03.004617 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 01:26:03.008176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 01:26:03.008258 ==
3188 01:26:03.011656 Write leveling (Byte 0): 26 => 26
3189 01:26:03.014542 Write leveling (Byte 1): 26 => 26
3190 01:26:03.017852 DramcWriteLeveling(PI) end<-----
3191 01:26:03.017934
3192 01:26:03.017999 ==
3193 01:26:03.021377 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 01:26:03.024715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 01:26:03.024799 ==
3196 01:26:03.027931 [Gating] SW mode calibration
3197 01:26:03.034697 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3198 01:26:03.037993 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3199 01:26:03.045079 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 01:26:03.048363 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 01:26:03.051698 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 01:26:03.057988 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 01:26:03.061474 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 01:26:03.064982 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 01:26:03.071491 0 15 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 1)
3206 01:26:03.075000 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3207 01:26:03.078225 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 01:26:03.084730 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 01:26:03.087892 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 01:26:03.091679 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 01:26:03.097736 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 01:26:03.101448 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3213 01:26:03.104717 1 0 24 | B1->B0 | 2e2e 3c3b | 0 1 | (1 1) (0 0)
3214 01:26:03.111797 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 01:26:03.114785 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 01:26:03.118292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 01:26:03.124896 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 01:26:03.128291 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 01:26:03.131103 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 01:26:03.134597 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 01:26:03.141413 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3222 01:26:03.144827 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3223 01:26:03.148232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 01:26:03.154789 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 01:26:03.158045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 01:26:03.161286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 01:26:03.168171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 01:26:03.171614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 01:26:03.174381 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 01:26:03.181447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 01:26:03.184357 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 01:26:03.187880 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 01:26:03.194502 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 01:26:03.197762 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 01:26:03.201702 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 01:26:03.208322 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 01:26:03.211121 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3238 01:26:03.214605 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3239 01:26:03.221616 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 01:26:03.221699 Total UI for P1: 0, mck2ui 16
3241 01:26:03.224535 best dqsien dly found for B0: ( 1, 3, 26)
3242 01:26:03.228095 Total UI for P1: 0, mck2ui 16
3243 01:26:03.231558 best dqsien dly found for B1: ( 1, 3, 28)
3244 01:26:03.235056 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3245 01:26:03.237849 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3246 01:26:03.241400
3247 01:26:03.244870 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3248 01:26:03.248276 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3249 01:26:03.251679 [Gating] SW calibration Done
3250 01:26:03.251762 ==
3251 01:26:03.255106 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 01:26:03.257902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 01:26:03.257985 ==
3254 01:26:03.258052 RX Vref Scan: 0
3255 01:26:03.261101
3256 01:26:03.261183 RX Vref 0 -> 0, step: 1
3257 01:26:03.261247
3258 01:26:03.265084 RX Delay -40 -> 252, step: 8
3259 01:26:03.268277 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3260 01:26:03.271439 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3261 01:26:03.277965 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3262 01:26:03.281253 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3263 01:26:03.285128 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3264 01:26:03.288306 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3265 01:26:03.291776 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3266 01:26:03.298519 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3267 01:26:03.301265 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3268 01:26:03.304664 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3269 01:26:03.307994 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3270 01:26:03.311391 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3271 01:26:03.318139 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3272 01:26:03.321276 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3273 01:26:03.324799 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3274 01:26:03.328366 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3275 01:26:03.328449 ==
3276 01:26:03.331821 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 01:26:03.335277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 01:26:03.338027 ==
3279 01:26:03.338109 DQS Delay:
3280 01:26:03.338174 DQS0 = 0, DQS1 = 0
3281 01:26:03.341548 DQM Delay:
3282 01:26:03.341669 DQM0 = 119, DQM1 = 116
3283 01:26:03.344859 DQ Delay:
3284 01:26:03.348350 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3285 01:26:03.351781 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3286 01:26:03.355176 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3287 01:26:03.358453 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3288 01:26:03.358536
3289 01:26:03.358638
3290 01:26:03.358699 ==
3291 01:26:03.361693 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 01:26:03.365097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 01:26:03.365181 ==
3294 01:26:03.365247
3295 01:26:03.368062
3296 01:26:03.368152 TX Vref Scan disable
3297 01:26:03.371407 == TX Byte 0 ==
3298 01:26:03.375489 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3299 01:26:03.378192 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3300 01:26:03.381347 == TX Byte 1 ==
3301 01:26:03.384805 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3302 01:26:03.388225 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3303 01:26:03.388310 ==
3304 01:26:03.391533 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 01:26:03.398284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 01:26:03.398391 ==
3307 01:26:03.408244 TX Vref=22, minBit 9, minWin=24, winSum=410
3308 01:26:03.411527 TX Vref=24, minBit 3, minWin=25, winSum=417
3309 01:26:03.415079 TX Vref=26, minBit 10, minWin=25, winSum=422
3310 01:26:03.418461 TX Vref=28, minBit 9, minWin=25, winSum=427
3311 01:26:03.421806 TX Vref=30, minBit 1, minWin=26, winSum=430
3312 01:26:03.425115 TX Vref=32, minBit 9, minWin=26, winSum=427
3313 01:26:03.432061 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3314 01:26:03.432148
3315 01:26:03.435038 Final TX Range 1 Vref 30
3316 01:26:03.435121
3317 01:26:03.435186 ==
3318 01:26:03.438760 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 01:26:03.442168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 01:26:03.442288 ==
3321 01:26:03.442372
3322 01:26:03.444881
3323 01:26:03.444970 TX Vref Scan disable
3324 01:26:03.448117 == TX Byte 0 ==
3325 01:26:03.451684 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3326 01:26:03.455043 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3327 01:26:03.458491 == TX Byte 1 ==
3328 01:26:03.461980 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3329 01:26:03.465246 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3330 01:26:03.465371
3331 01:26:03.468697 [DATLAT]
3332 01:26:03.468844 Freq=1200, CH1 RK0
3333 01:26:03.468954
3334 01:26:03.471467 DATLAT Default: 0xd
3335 01:26:03.471583 0, 0xFFFF, sum = 0
3336 01:26:03.474948 1, 0xFFFF, sum = 0
3337 01:26:03.475105 2, 0xFFFF, sum = 0
3338 01:26:03.478296 3, 0xFFFF, sum = 0
3339 01:26:03.478447 4, 0xFFFF, sum = 0
3340 01:26:03.481706 5, 0xFFFF, sum = 0
3341 01:26:03.481831 6, 0xFFFF, sum = 0
3342 01:26:03.485190 7, 0xFFFF, sum = 0
3343 01:26:03.488554 8, 0xFFFF, sum = 0
3344 01:26:03.488703 9, 0xFFFF, sum = 0
3345 01:26:03.491956 10, 0xFFFF, sum = 0
3346 01:26:03.492097 11, 0xFFFF, sum = 0
3347 01:26:03.495334 12, 0x0, sum = 1
3348 01:26:03.495507 13, 0x0, sum = 2
3349 01:26:03.495633 14, 0x0, sum = 3
3350 01:26:03.521028 15, 0x0, sum = 4
3351 01:26:03.521178 best_step = 13
3352 01:26:03.521260
3353 01:26:03.521322 ==
3354 01:26:03.521387 Dram Type= 6, Freq= 0, CH_1, rank 0
3355 01:26:03.521487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3356 01:26:03.521593 ==
3357 01:26:03.521656 RX Vref Scan: 1
3358 01:26:03.521714
3359 01:26:03.521768 Set Vref Range= 32 -> 127
3360 01:26:03.521823
3361 01:26:03.521882 RX Vref 32 -> 127, step: 1
3362 01:26:03.521941
3363 01:26:03.521995 RX Delay -5 -> 252, step: 4
3364 01:26:03.522048
3365 01:26:03.522415 Set Vref, RX VrefLevel [Byte0]: 32
3366 01:26:03.525047 [Byte1]: 32
3367 01:26:03.525154
3368 01:26:03.528388 Set Vref, RX VrefLevel [Byte0]: 33
3369 01:26:03.531916 [Byte1]: 33
3370 01:26:03.532011
3371 01:26:03.534689 Set Vref, RX VrefLevel [Byte0]: 34
3372 01:26:03.538071 [Byte1]: 34
3373 01:26:03.542153
3374 01:26:03.542266 Set Vref, RX VrefLevel [Byte0]: 35
3375 01:26:03.545341 [Byte1]: 35
3376 01:26:03.549785
3377 01:26:03.549873 Set Vref, RX VrefLevel [Byte0]: 36
3378 01:26:03.553502 [Byte1]: 36
3379 01:26:03.557697
3380 01:26:03.557786 Set Vref, RX VrefLevel [Byte0]: 37
3381 01:26:03.561354 [Byte1]: 37
3382 01:26:03.565289
3383 01:26:03.565377 Set Vref, RX VrefLevel [Byte0]: 38
3384 01:26:03.568898 [Byte1]: 38
3385 01:26:03.573684
3386 01:26:03.573802 Set Vref, RX VrefLevel [Byte0]: 39
3387 01:26:03.576944 [Byte1]: 39
3388 01:26:03.581669
3389 01:26:03.581827 Set Vref, RX VrefLevel [Byte0]: 40
3390 01:26:03.584398 [Byte1]: 40
3391 01:26:03.589185
3392 01:26:03.589379 Set Vref, RX VrefLevel [Byte0]: 41
3393 01:26:03.592864 [Byte1]: 41
3394 01:26:03.596791
3395 01:26:03.596938 Set Vref, RX VrefLevel [Byte0]: 42
3396 01:26:03.600188 [Byte1]: 42
3397 01:26:03.604659
3398 01:26:03.604766 Set Vref, RX VrefLevel [Byte0]: 43
3399 01:26:03.608246 [Byte1]: 43
3400 01:26:03.612920
3401 01:26:03.613036 Set Vref, RX VrefLevel [Byte0]: 44
3402 01:26:03.616231 [Byte1]: 44
3403 01:26:03.620730
3404 01:26:03.620811 Set Vref, RX VrefLevel [Byte0]: 45
3405 01:26:03.623896 [Byte1]: 45
3406 01:26:03.628819
3407 01:26:03.628901 Set Vref, RX VrefLevel [Byte0]: 46
3408 01:26:03.631554 [Byte1]: 46
3409 01:26:03.636422
3410 01:26:03.636500 Set Vref, RX VrefLevel [Byte0]: 47
3411 01:26:03.639942 [Byte1]: 47
3412 01:26:03.644070
3413 01:26:03.644145 Set Vref, RX VrefLevel [Byte0]: 48
3414 01:26:03.647592 [Byte1]: 48
3415 01:26:03.652370
3416 01:26:03.652455 Set Vref, RX VrefLevel [Byte0]: 49
3417 01:26:03.655118 [Byte1]: 49
3418 01:26:03.659785
3419 01:26:03.659874 Set Vref, RX VrefLevel [Byte0]: 50
3420 01:26:03.663001 [Byte1]: 50
3421 01:26:03.667774
3422 01:26:03.667865 Set Vref, RX VrefLevel [Byte0]: 51
3423 01:26:03.670818 [Byte1]: 51
3424 01:26:03.675941
3425 01:26:03.676047 Set Vref, RX VrefLevel [Byte0]: 52
3426 01:26:03.678789 [Byte1]: 52
3427 01:26:03.683348
3428 01:26:03.683443 Set Vref, RX VrefLevel [Byte0]: 53
3429 01:26:03.686634 [Byte1]: 53
3430 01:26:03.690947
3431 01:26:03.691030 Set Vref, RX VrefLevel [Byte0]: 54
3432 01:26:03.694711 [Byte1]: 54
3433 01:26:03.698892
3434 01:26:03.698966 Set Vref, RX VrefLevel [Byte0]: 55
3435 01:26:03.702421 [Byte1]: 55
3436 01:26:03.707023
3437 01:26:03.707096 Set Vref, RX VrefLevel [Byte0]: 56
3438 01:26:03.710394 [Byte1]: 56
3439 01:26:03.715151
3440 01:26:03.715236 Set Vref, RX VrefLevel [Byte0]: 57
3441 01:26:03.718465 [Byte1]: 57
3442 01:26:03.722528
3443 01:26:03.722626 Set Vref, RX VrefLevel [Byte0]: 58
3444 01:26:03.725748 [Byte1]: 58
3445 01:26:03.730372
3446 01:26:03.730452 Set Vref, RX VrefLevel [Byte0]: 59
3447 01:26:03.733607 [Byte1]: 59
3448 01:26:03.738152
3449 01:26:03.738276 Set Vref, RX VrefLevel [Byte0]: 60
3450 01:26:03.741572 [Byte1]: 60
3451 01:26:03.746523
3452 01:26:03.746606 Set Vref, RX VrefLevel [Byte0]: 61
3453 01:26:03.749443 [Byte1]: 61
3454 01:26:03.754090
3455 01:26:03.754192 Set Vref, RX VrefLevel [Byte0]: 62
3456 01:26:03.757673 [Byte1]: 62
3457 01:26:03.761812
3458 01:26:03.761893 Set Vref, RX VrefLevel [Byte0]: 63
3459 01:26:03.765030 [Byte1]: 63
3460 01:26:03.769806
3461 01:26:03.769890 Set Vref, RX VrefLevel [Byte0]: 64
3462 01:26:03.773130 [Byte1]: 64
3463 01:26:03.777415
3464 01:26:03.777492 Set Vref, RX VrefLevel [Byte0]: 65
3465 01:26:03.781005 [Byte1]: 65
3466 01:26:03.785581
3467 01:26:03.785660 Set Vref, RX VrefLevel [Byte0]: 66
3468 01:26:03.789031 [Byte1]: 66
3469 01:26:03.793168
3470 01:26:03.793272 Set Vref, RX VrefLevel [Byte0]: 67
3471 01:26:03.796801 [Byte1]: 67
3472 01:26:03.801020
3473 01:26:03.801100 Set Vref, RX VrefLevel [Byte0]: 68
3474 01:26:03.804617 [Byte1]: 68
3475 01:26:03.809178
3476 01:26:03.809285 Final RX Vref Byte 0 = 54 to rank0
3477 01:26:03.812468 Final RX Vref Byte 1 = 51 to rank0
3478 01:26:03.815978 Final RX Vref Byte 0 = 54 to rank1
3479 01:26:03.819248 Final RX Vref Byte 1 = 51 to rank1==
3480 01:26:03.822402 Dram Type= 6, Freq= 0, CH_1, rank 0
3481 01:26:03.829036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 01:26:03.829155 ==
3483 01:26:03.829252 DQS Delay:
3484 01:26:03.829345 DQS0 = 0, DQS1 = 0
3485 01:26:03.832388 DQM Delay:
3486 01:26:03.832487 DQM0 = 120, DQM1 = 116
3487 01:26:03.835970 DQ Delay:
3488 01:26:03.839298 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3489 01:26:03.842604 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3490 01:26:03.845719 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3491 01:26:03.849063 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3492 01:26:03.849163
3493 01:26:03.849265
3494 01:26:03.858851 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
3495 01:26:03.858960 CH1 RK0: MR19=304, MR18=FD10
3496 01:26:03.865864 CH1_RK0: MR19=0x304, MR18=0xFD10, DQSOSC=403, MR23=63, INC=40, DEC=26
3497 01:26:03.865971
3498 01:26:03.869173 ----->DramcWriteLeveling(PI) begin...
3499 01:26:03.869254 ==
3500 01:26:03.872357 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 01:26:03.875835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 01:26:03.879142 ==
3503 01:26:03.879219 Write leveling (Byte 0): 26 => 26
3504 01:26:03.882751 Write leveling (Byte 1): 28 => 28
3505 01:26:03.885403 DramcWriteLeveling(PI) end<-----
3506 01:26:03.885471
3507 01:26:03.885533 ==
3508 01:26:03.888871 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 01:26:03.895811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 01:26:03.895927 ==
3511 01:26:03.896025 [Gating] SW mode calibration
3512 01:26:03.905857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3513 01:26:03.909119 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3514 01:26:03.915932 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 01:26:03.919217 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 01:26:03.922402 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 01:26:03.925617 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 01:26:03.932809 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 01:26:03.935846 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 01:26:03.939023 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (1 0) (0 1)
3521 01:26:03.946134 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3522 01:26:03.948761 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 01:26:03.952168 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 01:26:03.958841 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 01:26:03.962230 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 01:26:03.965867 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 01:26:03.972118 1 0 20 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3528 01:26:03.975516 1 0 24 | B1->B0 | 4141 2929 | 0 0 | (0 0) (0 0)
3529 01:26:03.978829 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 01:26:03.985693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 01:26:03.989116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 01:26:03.991864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 01:26:03.999055 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 01:26:04.002372 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3535 01:26:04.005624 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3536 01:26:04.011766 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3537 01:26:04.015259 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3538 01:26:04.018576 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 01:26:04.025180 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 01:26:04.028574 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 01:26:04.032013 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 01:26:04.038155 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 01:26:04.041612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 01:26:04.044984 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 01:26:04.051681 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 01:26:04.054809 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 01:26:04.058076 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 01:26:04.064614 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 01:26:04.068107 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 01:26:04.071672 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 01:26:04.078046 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3552 01:26:04.081481 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3553 01:26:04.084801 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3554 01:26:04.087671 Total UI for P1: 0, mck2ui 16
3555 01:26:04.091104 best dqsien dly found for B1: ( 1, 3, 22)
3556 01:26:04.097977 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 01:26:04.098082 Total UI for P1: 0, mck2ui 16
3558 01:26:04.101474 best dqsien dly found for B0: ( 1, 3, 28)
3559 01:26:04.107659 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3560 01:26:04.111012 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3561 01:26:04.111116
3562 01:26:04.114735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3563 01:26:04.118127 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3564 01:26:04.120880 [Gating] SW calibration Done
3565 01:26:04.120982 ==
3566 01:26:04.124472 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 01:26:04.127915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 01:26:04.127993 ==
3569 01:26:04.131263 RX Vref Scan: 0
3570 01:26:04.131399
3571 01:26:04.131471 RX Vref 0 -> 0, step: 1
3572 01:26:04.131540
3573 01:26:04.134648 RX Delay -40 -> 252, step: 8
3574 01:26:04.137958 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3575 01:26:04.144635 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3576 01:26:04.147373 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3577 01:26:04.150867 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3578 01:26:04.154368 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3579 01:26:04.157820 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3580 01:26:04.164493 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3581 01:26:04.167036 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3582 01:26:04.170923 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3583 01:26:04.174001 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3584 01:26:04.177196 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3585 01:26:04.183807 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3586 01:26:04.186953 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3587 01:26:04.190604 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3588 01:26:04.193738 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3589 01:26:04.197047 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3590 01:26:04.200552 ==
3591 01:26:04.204113 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 01:26:04.207579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 01:26:04.207666 ==
3594 01:26:04.207731 DQS Delay:
3595 01:26:04.210970 DQS0 = 0, DQS1 = 0
3596 01:26:04.211068 DQM Delay:
3597 01:26:04.213718 DQM0 = 121, DQM1 = 118
3598 01:26:04.213846 DQ Delay:
3599 01:26:04.217168 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3600 01:26:04.220413 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3601 01:26:04.224003 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3602 01:26:04.227385 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3603 01:26:04.227489
3604 01:26:04.227580
3605 01:26:04.227667 ==
3606 01:26:04.230725 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 01:26:04.236889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 01:26:04.236967 ==
3609 01:26:04.237035
3610 01:26:04.237098
3611 01:26:04.237155 TX Vref Scan disable
3612 01:26:04.240876 == TX Byte 0 ==
3613 01:26:04.244141 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3614 01:26:04.247490 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3615 01:26:04.250722 == TX Byte 1 ==
3616 01:26:04.254185 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3617 01:26:04.260459 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3618 01:26:04.260535 ==
3619 01:26:04.263859 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 01:26:04.267218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 01:26:04.267296 ==
3622 01:26:04.278128 TX Vref=22, minBit 9, minWin=25, winSum=418
3623 01:26:04.281413 TX Vref=24, minBit 8, minWin=26, winSum=428
3624 01:26:04.284632 TX Vref=26, minBit 9, minWin=26, winSum=432
3625 01:26:04.288037 TX Vref=28, minBit 10, minWin=25, winSum=432
3626 01:26:04.291378 TX Vref=30, minBit 9, minWin=26, winSum=435
3627 01:26:04.298082 TX Vref=32, minBit 0, minWin=27, winSum=435
3628 01:26:04.301214 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 32
3629 01:26:04.301289
3630 01:26:04.304844 Final TX Range 1 Vref 32
3631 01:26:04.304919
3632 01:26:04.304987 ==
3633 01:26:04.308138 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 01:26:04.311470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 01:26:04.315046 ==
3636 01:26:04.315135
3637 01:26:04.315203
3638 01:26:04.315262 TX Vref Scan disable
3639 01:26:04.318511 == TX Byte 0 ==
3640 01:26:04.321386 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3641 01:26:04.324879 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3642 01:26:04.328306 == TX Byte 1 ==
3643 01:26:04.331843 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3644 01:26:04.338217 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3645 01:26:04.338297
3646 01:26:04.338376 [DATLAT]
3647 01:26:04.338441 Freq=1200, CH1 RK1
3648 01:26:04.338500
3649 01:26:04.341616 DATLAT Default: 0xd
3650 01:26:04.341690 0, 0xFFFF, sum = 0
3651 01:26:04.344868 1, 0xFFFF, sum = 0
3652 01:26:04.348234 2, 0xFFFF, sum = 0
3653 01:26:04.348311 3, 0xFFFF, sum = 0
3654 01:26:04.351486 4, 0xFFFF, sum = 0
3655 01:26:04.351560 5, 0xFFFF, sum = 0
3656 01:26:04.354806 6, 0xFFFF, sum = 0
3657 01:26:04.354881 7, 0xFFFF, sum = 0
3658 01:26:04.358055 8, 0xFFFF, sum = 0
3659 01:26:04.358136 9, 0xFFFF, sum = 0
3660 01:26:04.361601 10, 0xFFFF, sum = 0
3661 01:26:04.361687 11, 0xFFFF, sum = 0
3662 01:26:04.364435 12, 0x0, sum = 1
3663 01:26:04.364516 13, 0x0, sum = 2
3664 01:26:04.367824 14, 0x0, sum = 3
3665 01:26:04.367902 15, 0x0, sum = 4
3666 01:26:04.371154 best_step = 13
3667 01:26:04.371234
3668 01:26:04.371301 ==
3669 01:26:04.374715 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 01:26:04.378117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 01:26:04.378196 ==
3672 01:26:04.378260 RX Vref Scan: 0
3673 01:26:04.380944
3674 01:26:04.381019 RX Vref 0 -> 0, step: 1
3675 01:26:04.381082
3676 01:26:04.384259 RX Delay -5 -> 252, step: 4
3677 01:26:04.387698 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3678 01:26:04.394337 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3679 01:26:04.397651 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3680 01:26:04.400951 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3681 01:26:04.404619 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3682 01:26:04.407909 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3683 01:26:04.413977 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3684 01:26:04.417734 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3685 01:26:04.420834 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3686 01:26:04.424047 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3687 01:26:04.427294 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3688 01:26:04.434082 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3689 01:26:04.437519 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3690 01:26:04.440376 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3691 01:26:04.443855 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3692 01:26:04.450731 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3693 01:26:04.450823 ==
3694 01:26:04.454118 Dram Type= 6, Freq= 0, CH_1, rank 1
3695 01:26:04.456960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3696 01:26:04.457061 ==
3697 01:26:04.457150 DQS Delay:
3698 01:26:04.460352 DQS0 = 0, DQS1 = 0
3699 01:26:04.460435 DQM Delay:
3700 01:26:04.463623 DQM0 = 120, DQM1 = 117
3701 01:26:04.463698 DQ Delay:
3702 01:26:04.466960 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3703 01:26:04.470337 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3704 01:26:04.473715 DQ8 =106, DQ9 =106, DQ10 =118, DQ11 =112
3705 01:26:04.477301 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3706 01:26:04.477376
3707 01:26:04.477438
3708 01:26:04.487157 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3709 01:26:04.490390 CH1 RK1: MR19=403, MR18=10ED
3710 01:26:04.497241 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3711 01:26:04.497318 [RxdqsGatingPostProcess] freq 1200
3712 01:26:04.504006 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3713 01:26:04.507318 best DQS0 dly(2T, 0.5T) = (0, 11)
3714 01:26:04.510107 best DQS1 dly(2T, 0.5T) = (0, 11)
3715 01:26:04.513519 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3716 01:26:04.516886 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3717 01:26:04.520333 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 01:26:04.523512 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 01:26:04.526812 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 01:26:04.529992 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 01:26:04.533296 Pre-setting of DQS Precalculation
3722 01:26:04.536563 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3723 01:26:04.543294 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3724 01:26:04.553370 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3725 01:26:04.553454
3726 01:26:04.553527
3727 01:26:04.556813 [Calibration Summary] 2400 Mbps
3728 01:26:04.556892 CH 0, Rank 0
3729 01:26:04.559660 SW Impedance : PASS
3730 01:26:04.559728 DUTY Scan : NO K
3731 01:26:04.563065 ZQ Calibration : PASS
3732 01:26:04.563137 Jitter Meter : NO K
3733 01:26:04.566483 CBT Training : PASS
3734 01:26:04.570059 Write leveling : PASS
3735 01:26:04.570137 RX DQS gating : PASS
3736 01:26:04.573544 RX DQ/DQS(RDDQC) : PASS
3737 01:26:04.576936 TX DQ/DQS : PASS
3738 01:26:04.577042 RX DATLAT : PASS
3739 01:26:04.579735 RX DQ/DQS(Engine): PASS
3740 01:26:04.582897 TX OE : NO K
3741 01:26:04.582969 All Pass.
3742 01:26:04.583038
3743 01:26:04.583096 CH 0, Rank 1
3744 01:26:04.586828 SW Impedance : PASS
3745 01:26:04.589577 DUTY Scan : NO K
3746 01:26:04.589654 ZQ Calibration : PASS
3747 01:26:04.592975 Jitter Meter : NO K
3748 01:26:04.596732 CBT Training : PASS
3749 01:26:04.596815 Write leveling : PASS
3750 01:26:04.600026 RX DQS gating : PASS
3751 01:26:04.603327 RX DQ/DQS(RDDQC) : PASS
3752 01:26:04.603409 TX DQ/DQS : PASS
3753 01:26:04.606126 RX DATLAT : PASS
3754 01:26:04.609360 RX DQ/DQS(Engine): PASS
3755 01:26:04.609435 TX OE : NO K
3756 01:26:04.609506 All Pass.
3757 01:26:04.612699
3758 01:26:04.612773 CH 1, Rank 0
3759 01:26:04.616087 SW Impedance : PASS
3760 01:26:04.616173 DUTY Scan : NO K
3761 01:26:04.619687 ZQ Calibration : PASS
3762 01:26:04.619765 Jitter Meter : NO K
3763 01:26:04.622947 CBT Training : PASS
3764 01:26:04.626529 Write leveling : PASS
3765 01:26:04.626614 RX DQS gating : PASS
3766 01:26:04.629934 RX DQ/DQS(RDDQC) : PASS
3767 01:26:04.633181 TX DQ/DQS : PASS
3768 01:26:04.633271 RX DATLAT : PASS
3769 01:26:04.636540 RX DQ/DQS(Engine): PASS
3770 01:26:04.639258 TX OE : NO K
3771 01:26:04.639345 All Pass.
3772 01:26:04.639430
3773 01:26:04.639510 CH 1, Rank 1
3774 01:26:04.642594 SW Impedance : PASS
3775 01:26:04.646044 DUTY Scan : NO K
3776 01:26:04.646130 ZQ Calibration : PASS
3777 01:26:04.649188 Jitter Meter : NO K
3778 01:26:04.653297 CBT Training : PASS
3779 01:26:04.653383 Write leveling : PASS
3780 01:26:04.655993 RX DQS gating : PASS
3781 01:26:04.659271 RX DQ/DQS(RDDQC) : PASS
3782 01:26:04.659358 TX DQ/DQS : PASS
3783 01:26:04.662875 RX DATLAT : PASS
3784 01:26:04.662961 RX DQ/DQS(Engine): PASS
3785 01:26:04.666279 TX OE : NO K
3786 01:26:04.666375 All Pass.
3787 01:26:04.666460
3788 01:26:04.669193 DramC Write-DBI off
3789 01:26:04.672580 PER_BANK_REFRESH: Hybrid Mode
3790 01:26:04.672667 TX_TRACKING: ON
3791 01:26:04.682678 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3792 01:26:04.686157 [FAST_K] Save calibration result to emmc
3793 01:26:04.689675 dramc_set_vcore_voltage set vcore to 650000
3794 01:26:04.692849 Read voltage for 600, 5
3795 01:26:04.692935 Vio18 = 0
3796 01:26:04.696002 Vcore = 650000
3797 01:26:04.696088 Vdram = 0
3798 01:26:04.696175 Vddq = 0
3799 01:26:04.696256 Vmddr = 0
3800 01:26:04.702734 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3801 01:26:04.709004 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3802 01:26:04.709090 MEM_TYPE=3, freq_sel=19
3803 01:26:04.712705 sv_algorithm_assistance_LP4_1600
3804 01:26:04.716103 ============ PULL DRAM RESETB DOWN ============
3805 01:26:04.722546 ========== PULL DRAM RESETB DOWN end =========
3806 01:26:04.725927 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3807 01:26:04.729514 ===================================
3808 01:26:04.732219 LPDDR4 DRAM CONFIGURATION
3809 01:26:04.735552 ===================================
3810 01:26:04.735631 EX_ROW_EN[0] = 0x0
3811 01:26:04.738869 EX_ROW_EN[1] = 0x0
3812 01:26:04.738952 LP4Y_EN = 0x0
3813 01:26:04.742281 WORK_FSP = 0x0
3814 01:26:04.742405 WL = 0x2
3815 01:26:04.745680 RL = 0x2
3816 01:26:04.748979 BL = 0x2
3817 01:26:04.749063 RPST = 0x0
3818 01:26:04.752337 RD_PRE = 0x0
3819 01:26:04.752446 WR_PRE = 0x1
3820 01:26:04.755521 WR_PST = 0x0
3821 01:26:04.755598 DBI_WR = 0x0
3822 01:26:04.758580 DBI_RD = 0x0
3823 01:26:04.758658 OTF = 0x1
3824 01:26:04.762410 ===================================
3825 01:26:04.765885 ===================================
3826 01:26:04.768668 ANA top config
3827 01:26:04.772115 ===================================
3828 01:26:04.772203 DLL_ASYNC_EN = 0
3829 01:26:04.775673 ALL_SLAVE_EN = 1
3830 01:26:04.778487 NEW_RANK_MODE = 1
3831 01:26:04.781935 DLL_IDLE_MODE = 1
3832 01:26:04.782034 LP45_APHY_COMB_EN = 1
3833 01:26:04.785368 TX_ODT_DIS = 1
3834 01:26:04.788615 NEW_8X_MODE = 1
3835 01:26:04.791981 ===================================
3836 01:26:04.795502 ===================================
3837 01:26:04.798632 data_rate = 1200
3838 01:26:04.801918 CKR = 1
3839 01:26:04.805296 DQ_P2S_RATIO = 8
3840 01:26:04.808539 ===================================
3841 01:26:04.808611 CA_P2S_RATIO = 8
3842 01:26:04.811918 DQ_CA_OPEN = 0
3843 01:26:04.815278 DQ_SEMI_OPEN = 0
3844 01:26:04.818876 CA_SEMI_OPEN = 0
3845 01:26:04.821736 CA_FULL_RATE = 0
3846 01:26:04.825011 DQ_CKDIV4_EN = 1
3847 01:26:04.825091 CA_CKDIV4_EN = 1
3848 01:26:04.828464 CA_PREDIV_EN = 0
3849 01:26:04.831863 PH8_DLY = 0
3850 01:26:04.835221 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3851 01:26:04.838585 DQ_AAMCK_DIV = 4
3852 01:26:04.841900 CA_AAMCK_DIV = 4
3853 01:26:04.842015 CA_ADMCK_DIV = 4
3854 01:26:04.844826 DQ_TRACK_CA_EN = 0
3855 01:26:04.848746 CA_PICK = 600
3856 01:26:04.851960 CA_MCKIO = 600
3857 01:26:04.855324 MCKIO_SEMI = 0
3858 01:26:04.858625 PLL_FREQ = 2288
3859 01:26:04.858760 DQ_UI_PI_RATIO = 32
3860 01:26:04.862072 CA_UI_PI_RATIO = 0
3861 01:26:04.864715 ===================================
3862 01:26:04.868617 ===================================
3863 01:26:04.871833 memory_type:LPDDR4
3864 01:26:04.875339 GP_NUM : 10
3865 01:26:04.875415 SRAM_EN : 1
3866 01:26:04.878070 MD32_EN : 0
3867 01:26:04.881616 ===================================
3868 01:26:04.885096 [ANA_INIT] >>>>>>>>>>>>>>
3869 01:26:04.885181 <<<<<< [CONFIGURE PHASE]: ANA_TX
3870 01:26:04.888526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3871 01:26:04.891938 ===================================
3872 01:26:04.895274 data_rate = 1200,PCW = 0X5800
3873 01:26:04.898072 ===================================
3874 01:26:04.901425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3875 01:26:04.908280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3876 01:26:04.914930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 01:26:04.918249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3878 01:26:04.921572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3879 01:26:04.925155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3880 01:26:04.928577 [ANA_INIT] flow start
3881 01:26:04.928662 [ANA_INIT] PLL >>>>>>>>
3882 01:26:04.931900 [ANA_INIT] PLL <<<<<<<<
3883 01:26:04.935106 [ANA_INIT] MIDPI >>>>>>>>
3884 01:26:04.935218 [ANA_INIT] MIDPI <<<<<<<<
3885 01:26:04.937886 [ANA_INIT] DLL >>>>>>>>
3886 01:26:04.941290 [ANA_INIT] flow end
3887 01:26:04.945055 ============ LP4 DIFF to SE enter ============
3888 01:26:04.948368 ============ LP4 DIFF to SE exit ============
3889 01:26:04.951826 [ANA_INIT] <<<<<<<<<<<<<
3890 01:26:04.955108 [Flow] Enable top DCM control >>>>>
3891 01:26:04.958471 [Flow] Enable top DCM control <<<<<
3892 01:26:04.961633 Enable DLL master slave shuffle
3893 01:26:04.964878 ==============================================================
3894 01:26:04.968352 Gating Mode config
3895 01:26:04.974838 ==============================================================
3896 01:26:04.974940 Config description:
3897 01:26:04.984257 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3898 01:26:04.991039 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3899 01:26:04.997809 SELPH_MODE 0: By rank 1: By Phase
3900 01:26:05.001146 ==============================================================
3901 01:26:05.004411 GAT_TRACK_EN = 1
3902 01:26:05.007734 RX_GATING_MODE = 2
3903 01:26:05.011201 RX_GATING_TRACK_MODE = 2
3904 01:26:05.014676 SELPH_MODE = 1
3905 01:26:05.017405 PICG_EARLY_EN = 1
3906 01:26:05.020858 VALID_LAT_VALUE = 1
3907 01:26:05.024090 ==============================================================
3908 01:26:05.027575 Enter into Gating configuration >>>>
3909 01:26:05.031101 Exit from Gating configuration <<<<
3910 01:26:05.034524 Enter into DVFS_PRE_config >>>>>
3911 01:26:05.047541 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3912 01:26:05.050711 Exit from DVFS_PRE_config <<<<<
3913 01:26:05.054107 Enter into PICG configuration >>>>
3914 01:26:05.054185 Exit from PICG configuration <<<<
3915 01:26:05.057522 [RX_INPUT] configuration >>>>>
3916 01:26:05.060698 [RX_INPUT] configuration <<<<<
3917 01:26:05.067370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3918 01:26:05.070620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3919 01:26:05.077324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 01:26:05.083836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 01:26:05.090809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 01:26:05.097017 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 01:26:05.100400 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3924 01:26:05.103972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3925 01:26:05.109890 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3926 01:26:05.113440 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3927 01:26:05.116848 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3928 01:26:05.120082 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3929 01:26:05.123609 ===================================
3930 01:26:05.127008 LPDDR4 DRAM CONFIGURATION
3931 01:26:05.130274 ===================================
3932 01:26:05.133764 EX_ROW_EN[0] = 0x0
3933 01:26:05.133850 EX_ROW_EN[1] = 0x0
3934 01:26:05.136600 LP4Y_EN = 0x0
3935 01:26:05.136672 WORK_FSP = 0x0
3936 01:26:05.140006 WL = 0x2
3937 01:26:05.140081 RL = 0x2
3938 01:26:05.143409 BL = 0x2
3939 01:26:05.143494 RPST = 0x0
3940 01:26:05.147033 RD_PRE = 0x0
3941 01:26:05.147117 WR_PRE = 0x1
3942 01:26:05.150394 WR_PST = 0x0
3943 01:26:05.150468 DBI_WR = 0x0
3944 01:26:05.153727 DBI_RD = 0x0
3945 01:26:05.157184 OTF = 0x1
3946 01:26:05.160395 ===================================
3947 01:26:05.163709 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3948 01:26:05.167142 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3949 01:26:05.169844 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3950 01:26:05.173224 ===================================
3951 01:26:05.176621 LPDDR4 DRAM CONFIGURATION
3952 01:26:05.180173 ===================================
3953 01:26:05.182969 EX_ROW_EN[0] = 0x10
3954 01:26:05.183051 EX_ROW_EN[1] = 0x0
3955 01:26:05.186873 LP4Y_EN = 0x0
3956 01:26:05.186949 WORK_FSP = 0x0
3957 01:26:05.190151 WL = 0x2
3958 01:26:05.190235 RL = 0x2
3959 01:26:05.193371 BL = 0x2
3960 01:26:05.193457 RPST = 0x0
3961 01:26:05.196761 RD_PRE = 0x0
3962 01:26:05.196853 WR_PRE = 0x1
3963 01:26:05.200183 WR_PST = 0x0
3964 01:26:05.200266 DBI_WR = 0x0
3965 01:26:05.202880 DBI_RD = 0x0
3966 01:26:05.206420 OTF = 0x1
3967 01:26:05.206504 ===================================
3968 01:26:05.213081 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3969 01:26:05.217872 nWR fixed to 30
3970 01:26:05.221314 [ModeRegInit_LP4] CH0 RK0
3971 01:26:05.221399 [ModeRegInit_LP4] CH0 RK1
3972 01:26:05.224834 [ModeRegInit_LP4] CH1 RK0
3973 01:26:05.228344 [ModeRegInit_LP4] CH1 RK1
3974 01:26:05.228428 match AC timing 17
3975 01:26:05.234199 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3976 01:26:05.237595 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3977 01:26:05.241208 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3978 01:26:05.247921 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3979 01:26:05.250704 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3980 01:26:05.250787 ==
3981 01:26:05.254338 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 01:26:05.257755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 01:26:05.257837 ==
3984 01:26:05.264457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 01:26:05.271083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3986 01:26:05.274442 [CA 0] Center 35 (5~66) winsize 62
3987 01:26:05.277851 [CA 1] Center 35 (5~66) winsize 62
3988 01:26:05.280599 [CA 2] Center 34 (3~65) winsize 63
3989 01:26:05.284036 [CA 3] Center 33 (3~64) winsize 62
3990 01:26:05.287554 [CA 4] Center 33 (2~64) winsize 63
3991 01:26:05.290500 [CA 5] Center 32 (2~63) winsize 62
3992 01:26:05.290573
3993 01:26:05.293865 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3994 01:26:05.293949
3995 01:26:05.297232 [CATrainingPosCal] consider 1 rank data
3996 01:26:05.300527 u2DelayCellTimex100 = 270/100 ps
3997 01:26:05.304371 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3998 01:26:05.307709 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3999 01:26:05.310895 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4000 01:26:05.314252 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4001 01:26:05.317778 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4002 01:26:05.323804 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4003 01:26:05.323893
4004 01:26:05.327126 CA PerBit enable=1, Macro0, CA PI delay=32
4005 01:26:05.327204
4006 01:26:05.330886 [CBTSetCACLKResult] CA Dly = 32
4007 01:26:05.330958 CS Dly: 4 (0~35)
4008 01:26:05.331027 ==
4009 01:26:05.334135 Dram Type= 6, Freq= 0, CH_0, rank 1
4010 01:26:05.337409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 01:26:05.340727 ==
4012 01:26:05.344051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4013 01:26:05.350611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4014 01:26:05.354076 [CA 0] Center 35 (5~66) winsize 62
4015 01:26:05.357687 [CA 1] Center 35 (5~66) winsize 62
4016 01:26:05.360495 [CA 2] Center 34 (3~65) winsize 63
4017 01:26:05.363997 [CA 3] Center 33 (3~64) winsize 62
4018 01:26:05.367261 [CA 4] Center 33 (2~64) winsize 63
4019 01:26:05.370657 [CA 5] Center 32 (2~63) winsize 62
4020 01:26:05.370742
4021 01:26:05.373825 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4022 01:26:05.373896
4023 01:26:05.377208 [CATrainingPosCal] consider 2 rank data
4024 01:26:05.380428 u2DelayCellTimex100 = 270/100 ps
4025 01:26:05.383620 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4026 01:26:05.387082 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4027 01:26:05.390605 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4028 01:26:05.397521 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4029 01:26:05.400232 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4030 01:26:05.403675 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4031 01:26:05.403759
4032 01:26:05.407154 CA PerBit enable=1, Macro0, CA PI delay=32
4033 01:26:05.407238
4034 01:26:05.410521 [CBTSetCACLKResult] CA Dly = 32
4035 01:26:05.410592 CS Dly: 4 (0~36)
4036 01:26:05.410660
4037 01:26:05.413568 ----->DramcWriteLeveling(PI) begin...
4038 01:26:05.413644 ==
4039 01:26:05.416803 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 01:26:05.423942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 01:26:05.424020 ==
4042 01:26:05.426840 Write leveling (Byte 0): 34 => 34
4043 01:26:05.430242 Write leveling (Byte 1): 31 => 31
4044 01:26:05.430369 DramcWriteLeveling(PI) end<-----
4045 01:26:05.433629
4046 01:26:05.433697 ==
4047 01:26:05.437087 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 01:26:05.440485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 01:26:05.440556 ==
4050 01:26:05.443821 [Gating] SW mode calibration
4051 01:26:05.450027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4052 01:26:05.453683 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4053 01:26:05.460088 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 01:26:05.463502 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 01:26:05.467071 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4056 01:26:05.473315 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4057 01:26:05.476631 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4058 01:26:05.479967 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 01:26:05.487039 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 01:26:05.490273 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 01:26:05.493718 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 01:26:05.499869 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 01:26:05.503241 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 01:26:05.506713 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
4065 01:26:05.513015 0 10 16 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
4066 01:26:05.516463 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 01:26:05.519662 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 01:26:05.526895 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 01:26:05.529620 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 01:26:05.532893 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 01:26:05.539921 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 01:26:05.542768 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4073 01:26:05.546054 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4074 01:26:05.553093 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 01:26:05.556496 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 01:26:05.559706 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 01:26:05.566079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 01:26:05.569551 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 01:26:05.572662 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 01:26:05.579693 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 01:26:05.583020 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 01:26:05.586381 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 01:26:05.592797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 01:26:05.595911 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 01:26:05.599325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 01:26:05.605987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 01:26:05.609487 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 01:26:05.612337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 01:26:05.619018 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4090 01:26:05.619109 Total UI for P1: 0, mck2ui 16
4091 01:26:05.622690 best dqsien dly found for B0: ( 0, 13, 14)
4092 01:26:05.629284 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 01:26:05.632582 Total UI for P1: 0, mck2ui 16
4094 01:26:05.635969 best dqsien dly found for B1: ( 0, 13, 18)
4095 01:26:05.639363 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4096 01:26:05.642114 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4097 01:26:05.642197
4098 01:26:05.645756 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4099 01:26:05.649030 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4100 01:26:05.652639 [Gating] SW calibration Done
4101 01:26:05.652722 ==
4102 01:26:05.655390 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 01:26:05.658943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 01:26:05.659025 ==
4105 01:26:05.662245 RX Vref Scan: 0
4106 01:26:05.662347
4107 01:26:05.665624 RX Vref 0 -> 0, step: 1
4108 01:26:05.665702
4109 01:26:05.665763 RX Delay -230 -> 252, step: 16
4110 01:26:05.671961 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4111 01:26:05.675292 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4112 01:26:05.678963 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4113 01:26:05.682178 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4114 01:26:05.689104 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4115 01:26:05.692299 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4116 01:26:05.695591 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4117 01:26:05.699002 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4118 01:26:05.702192 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4119 01:26:05.708616 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4120 01:26:05.711857 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4121 01:26:05.715350 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4122 01:26:05.718716 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4123 01:26:05.725749 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4124 01:26:05.728990 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4125 01:26:05.731836 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4126 01:26:05.731910 ==
4127 01:26:05.735207 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 01:26:05.738370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 01:26:05.741797 ==
4130 01:26:05.741870 DQS Delay:
4131 01:26:05.741941 DQS0 = 0, DQS1 = 0
4132 01:26:05.745057 DQM Delay:
4133 01:26:05.745128 DQM0 = 53, DQM1 = 45
4134 01:26:05.748599 DQ Delay:
4135 01:26:05.751907 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4136 01:26:05.751987 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =65
4137 01:26:05.755606 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4138 01:26:05.759114 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4139 01:26:05.759192
4140 01:26:05.761807
4141 01:26:05.761878 ==
4142 01:26:05.765412 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 01:26:05.768842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 01:26:05.768918 ==
4145 01:26:05.768980
4146 01:26:05.769053
4147 01:26:05.772367 TX Vref Scan disable
4148 01:26:05.772438 == TX Byte 0 ==
4149 01:26:05.778459 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4150 01:26:05.781998 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4151 01:26:05.782102 == TX Byte 1 ==
4152 01:26:05.788677 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4153 01:26:05.791961 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4154 01:26:05.792040 ==
4155 01:26:05.795288 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 01:26:05.798469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 01:26:05.798560 ==
4158 01:26:05.798625
4159 01:26:05.798691
4160 01:26:05.801564 TX Vref Scan disable
4161 01:26:05.805374 == TX Byte 0 ==
4162 01:26:05.808661 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4163 01:26:05.811855 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4164 01:26:05.815304 == TX Byte 1 ==
4165 01:26:05.818483 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4166 01:26:05.821593 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4167 01:26:05.821690
4168 01:26:05.825232 [DATLAT]
4169 01:26:05.825316 Freq=600, CH0 RK0
4170 01:26:05.825390
4171 01:26:05.828722 DATLAT Default: 0x9
4172 01:26:05.828802 0, 0xFFFF, sum = 0
4173 01:26:05.831947 1, 0xFFFF, sum = 0
4174 01:26:05.832032 2, 0xFFFF, sum = 0
4175 01:26:05.834848 3, 0xFFFF, sum = 0
4176 01:26:05.834920 4, 0xFFFF, sum = 0
4177 01:26:05.838240 5, 0xFFFF, sum = 0
4178 01:26:05.838352 6, 0xFFFF, sum = 0
4179 01:26:05.841621 7, 0xFFFF, sum = 0
4180 01:26:05.841695 8, 0x0, sum = 1
4181 01:26:05.844998 9, 0x0, sum = 2
4182 01:26:05.845082 10, 0x0, sum = 3
4183 01:26:05.848535 11, 0x0, sum = 4
4184 01:26:05.848607 best_step = 9
4185 01:26:05.848668
4186 01:26:05.848734 ==
4187 01:26:05.851804 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 01:26:05.858140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 01:26:05.858248 ==
4190 01:26:05.858355 RX Vref Scan: 1
4191 01:26:05.858417
4192 01:26:05.861523 RX Vref 0 -> 0, step: 1
4193 01:26:05.861601
4194 01:26:05.865016 RX Delay -179 -> 252, step: 8
4195 01:26:05.865092
4196 01:26:05.868638 Set Vref, RX VrefLevel [Byte0]: 56
4197 01:26:05.871248 [Byte1]: 46
4198 01:26:05.871318
4199 01:26:05.874779 Final RX Vref Byte 0 = 56 to rank0
4200 01:26:05.878351 Final RX Vref Byte 1 = 46 to rank0
4201 01:26:05.881763 Final RX Vref Byte 0 = 56 to rank1
4202 01:26:05.885066 Final RX Vref Byte 1 = 46 to rank1==
4203 01:26:05.888493 Dram Type= 6, Freq= 0, CH_0, rank 0
4204 01:26:05.891294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 01:26:05.891375 ==
4206 01:26:05.894898 DQS Delay:
4207 01:26:05.894975 DQS0 = 0, DQS1 = 0
4208 01:26:05.895047 DQM Delay:
4209 01:26:05.898292 DQM0 = 52, DQM1 = 47
4210 01:26:05.898373 DQ Delay:
4211 01:26:05.901208 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4212 01:26:05.904701 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4213 01:26:05.907914 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4214 01:26:05.911367 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4215 01:26:05.911441
4216 01:26:05.911512
4217 01:26:05.920932 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4218 01:26:05.924371 CH0 RK0: MR19=808, MR18=7063
4219 01:26:05.928255 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4220 01:26:05.928331
4221 01:26:05.931621 ----->DramcWriteLeveling(PI) begin...
4222 01:26:05.934749 ==
4223 01:26:05.937634 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 01:26:05.941234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 01:26:05.941324 ==
4226 01:26:05.944699 Write leveling (Byte 0): 35 => 35
4227 01:26:05.947898 Write leveling (Byte 1): 30 => 30
4228 01:26:05.951125 DramcWriteLeveling(PI) end<-----
4229 01:26:05.951210
4230 01:26:05.951275 ==
4231 01:26:05.954445 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 01:26:05.957800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 01:26:05.957886 ==
4234 01:26:05.961190 [Gating] SW mode calibration
4235 01:26:05.967351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4236 01:26:05.974395 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4237 01:26:05.977796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 01:26:05.981242 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 01:26:05.987467 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 01:26:05.990854 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4241 01:26:05.994221 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4242 01:26:06.001081 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 01:26:06.003849 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 01:26:06.007105 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 01:26:06.010722 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 01:26:06.017246 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 01:26:06.020642 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 01:26:06.023918 0 10 12 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4249 01:26:06.030391 0 10 16 | B1->B0 | 4242 4343 | 0 0 | (0 0) (0 0)
4250 01:26:06.033672 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 01:26:06.037240 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 01:26:06.043990 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 01:26:06.047280 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 01:26:06.050638 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 01:26:06.056957 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 01:26:06.060867 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4257 01:26:06.063948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 01:26:06.070596 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 01:26:06.073791 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 01:26:06.077289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 01:26:06.084044 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 01:26:06.086757 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 01:26:06.090296 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 01:26:06.097184 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 01:26:06.100059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 01:26:06.103353 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 01:26:06.110160 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 01:26:06.113702 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 01:26:06.117131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 01:26:06.123260 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 01:26:06.126801 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4272 01:26:06.130288 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 01:26:06.136863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 01:26:06.136958 Total UI for P1: 0, mck2ui 16
4275 01:26:06.143120 best dqsien dly found for B0: ( 0, 13, 14)
4276 01:26:06.143205 Total UI for P1: 0, mck2ui 16
4277 01:26:06.150027 best dqsien dly found for B1: ( 0, 13, 14)
4278 01:26:06.153471 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4279 01:26:06.156937 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4280 01:26:06.157015
4281 01:26:06.159688 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4282 01:26:06.162868 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4283 01:26:06.166849 [Gating] SW calibration Done
4284 01:26:06.166949 ==
4285 01:26:06.169536 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 01:26:06.172930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 01:26:06.173011 ==
4288 01:26:06.176380 RX Vref Scan: 0
4289 01:26:06.176454
4290 01:26:06.176516 RX Vref 0 -> 0, step: 1
4291 01:26:06.176575
4292 01:26:06.179709 RX Delay -230 -> 252, step: 16
4293 01:26:06.186806 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4294 01:26:06.189883 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4295 01:26:06.193482 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4296 01:26:06.196461 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4297 01:26:06.199709 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4298 01:26:06.206969 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4299 01:26:06.210279 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4300 01:26:06.212907 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4301 01:26:06.216382 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4302 01:26:06.219796 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4303 01:26:06.226722 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4304 01:26:06.229894 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4305 01:26:06.232627 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4306 01:26:06.235992 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4307 01:26:06.242775 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4308 01:26:06.246121 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4309 01:26:06.246197 ==
4310 01:26:06.249283 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 01:26:06.252843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 01:26:06.252926 ==
4313 01:26:06.256413 DQS Delay:
4314 01:26:06.256515 DQS0 = 0, DQS1 = 0
4315 01:26:06.259236 DQM Delay:
4316 01:26:06.259311 DQM0 = 51, DQM1 = 43
4317 01:26:06.259371 DQ Delay:
4318 01:26:06.262738 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4319 01:26:06.265663 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4320 01:26:06.269106 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4321 01:26:06.272435 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4322 01:26:06.272513
4323 01:26:06.272579
4324 01:26:06.275727 ==
4325 01:26:06.275802 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 01:26:06.282450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 01:26:06.282557 ==
4328 01:26:06.282660
4329 01:26:06.282765
4330 01:26:06.285809 TX Vref Scan disable
4331 01:26:06.285907 == TX Byte 0 ==
4332 01:26:06.289369 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4333 01:26:06.296155 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4334 01:26:06.296238 == TX Byte 1 ==
4335 01:26:06.302800 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4336 01:26:06.305866 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4337 01:26:06.305966 ==
4338 01:26:06.309013 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 01:26:06.312462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 01:26:06.312545 ==
4341 01:26:06.312615
4342 01:26:06.312693
4343 01:26:06.315451 TX Vref Scan disable
4344 01:26:06.319248 == TX Byte 0 ==
4345 01:26:06.322579 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4346 01:26:06.326185 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4347 01:26:06.329035 == TX Byte 1 ==
4348 01:26:06.332551 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4349 01:26:06.335931 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4350 01:26:06.336030
4351 01:26:06.339023 [DATLAT]
4352 01:26:06.339110 Freq=600, CH0 RK1
4353 01:26:06.339191
4354 01:26:06.342611 DATLAT Default: 0x9
4355 01:26:06.342692 0, 0xFFFF, sum = 0
4356 01:26:06.345974 1, 0xFFFF, sum = 0
4357 01:26:06.346053 2, 0xFFFF, sum = 0
4358 01:26:06.349194 3, 0xFFFF, sum = 0
4359 01:26:06.349274 4, 0xFFFF, sum = 0
4360 01:26:06.352717 5, 0xFFFF, sum = 0
4361 01:26:06.352833 6, 0xFFFF, sum = 0
4362 01:26:06.355980 7, 0xFFFF, sum = 0
4363 01:26:06.356108 8, 0x0, sum = 1
4364 01:26:06.358736 9, 0x0, sum = 2
4365 01:26:06.358822 10, 0x0, sum = 3
4366 01:26:06.362405 11, 0x0, sum = 4
4367 01:26:06.362490 best_step = 9
4368 01:26:06.362558
4369 01:26:06.362624 ==
4370 01:26:06.365195 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 01:26:06.368697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 01:26:06.371969 ==
4373 01:26:06.372066 RX Vref Scan: 0
4374 01:26:06.372167
4375 01:26:06.375330 RX Vref 0 -> 0, step: 1
4376 01:26:06.375428
4377 01:26:06.378939 RX Delay -163 -> 252, step: 8
4378 01:26:06.381640 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4379 01:26:06.385561 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4380 01:26:06.391940 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4381 01:26:06.395275 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4382 01:26:06.398509 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4383 01:26:06.401829 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4384 01:26:06.405164 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4385 01:26:06.411997 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4386 01:26:06.415476 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4387 01:26:06.418141 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4388 01:26:06.421580 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4389 01:26:06.425024 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4390 01:26:06.431434 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4391 01:26:06.435227 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4392 01:26:06.438028 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4393 01:26:06.441609 iDelay=205, Bit 15, Center 56 (-83 ~ 196) 280
4394 01:26:06.441687 ==
4395 01:26:06.444865 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 01:26:06.451612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 01:26:06.451691 ==
4398 01:26:06.451755 DQS Delay:
4399 01:26:06.454952 DQS0 = 0, DQS1 = 0
4400 01:26:06.455033 DQM Delay:
4401 01:26:06.455098 DQM0 = 52, DQM1 = 47
4402 01:26:06.458415 DQ Delay:
4403 01:26:06.461805 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4404 01:26:06.464491 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4405 01:26:06.467862 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4406 01:26:06.471412 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4407 01:26:06.471489
4408 01:26:06.471558
4409 01:26:06.477784 [DQSOSCAuto] RK1, (LSB)MR18= 0x6324, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4410 01:26:06.481305 CH0 RK1: MR19=808, MR18=6324
4411 01:26:06.488314 CH0_RK1: MR19=0x808, MR18=0x6324, DQSOSC=391, MR23=63, INC=171, DEC=114
4412 01:26:06.491640 [RxdqsGatingPostProcess] freq 600
4413 01:26:06.494957 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4414 01:26:06.497982 Pre-setting of DQS Precalculation
4415 01:26:06.504675 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4416 01:26:06.504755 ==
4417 01:26:06.507992 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 01:26:06.511172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 01:26:06.511242 ==
4420 01:26:06.517839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 01:26:06.524687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4422 01:26:06.527382 [CA 0] Center 36 (5~67) winsize 63
4423 01:26:06.530915 [CA 1] Center 36 (5~67) winsize 63
4424 01:26:06.534177 [CA 2] Center 34 (4~65) winsize 62
4425 01:26:06.537494 [CA 3] Center 34 (4~65) winsize 62
4426 01:26:06.540752 [CA 4] Center 34 (4~65) winsize 62
4427 01:26:06.544015 [CA 5] Center 33 (3~64) winsize 62
4428 01:26:06.544097
4429 01:26:06.547859 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4430 01:26:06.547943
4431 01:26:06.551225 [CATrainingPosCal] consider 1 rank data
4432 01:26:06.554075 u2DelayCellTimex100 = 270/100 ps
4433 01:26:06.557409 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4434 01:26:06.560717 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4435 01:26:06.564194 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 01:26:06.567609 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 01:26:06.570966 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 01:26:06.574498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 01:26:06.574596
4440 01:26:06.580839 CA PerBit enable=1, Macro0, CA PI delay=33
4441 01:26:06.580920
4442 01:26:06.581010 [CBTSetCACLKResult] CA Dly = 33
4443 01:26:06.584114 CS Dly: 6 (0~37)
4444 01:26:06.584198 ==
4445 01:26:06.587712 Dram Type= 6, Freq= 0, CH_1, rank 1
4446 01:26:06.591065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 01:26:06.591150 ==
4448 01:26:06.597286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4449 01:26:06.603964 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4450 01:26:06.607727 [CA 0] Center 36 (5~67) winsize 63
4451 01:26:06.611081 [CA 1] Center 36 (5~67) winsize 63
4452 01:26:06.613830 [CA 2] Center 34 (4~65) winsize 62
4453 01:26:06.617141 [CA 3] Center 34 (4~65) winsize 62
4454 01:26:06.621081 [CA 4] Center 34 (4~65) winsize 62
4455 01:26:06.623934 [CA 5] Center 34 (3~65) winsize 63
4456 01:26:06.624012
4457 01:26:06.627160 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4458 01:26:06.627237
4459 01:26:06.630318 [CATrainingPosCal] consider 2 rank data
4460 01:26:06.634215 u2DelayCellTimex100 = 270/100 ps
4461 01:26:06.637642 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4462 01:26:06.640467 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4463 01:26:06.643741 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 01:26:06.647712 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 01:26:06.650506 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 01:26:06.653697 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 01:26:06.653786
4468 01:26:06.660977 CA PerBit enable=1, Macro0, CA PI delay=33
4469 01:26:06.661068
4470 01:26:06.664016 [CBTSetCACLKResult] CA Dly = 33
4471 01:26:06.664098 CS Dly: 6 (0~38)
4472 01:26:06.664165
4473 01:26:06.667157 ----->DramcWriteLeveling(PI) begin...
4474 01:26:06.667236 ==
4475 01:26:06.670546 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 01:26:06.674041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 01:26:06.677291 ==
4478 01:26:06.677366 Write leveling (Byte 0): 31 => 31
4479 01:26:06.680833 Write leveling (Byte 1): 31 => 31
4480 01:26:06.683633 DramcWriteLeveling(PI) end<-----
4481 01:26:06.683706
4482 01:26:06.683767 ==
4483 01:26:06.686983 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 01:26:06.693930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 01:26:06.694011 ==
4486 01:26:06.696764 [Gating] SW mode calibration
4487 01:26:06.703618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4488 01:26:06.707051 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4489 01:26:06.713580 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 01:26:06.717024 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 01:26:06.720577 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 01:26:06.723929 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 1) (0 1)
4493 01:26:06.730259 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 01:26:06.733662 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 01:26:06.736912 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 01:26:06.743706 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 01:26:06.746690 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 01:26:06.750261 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 01:26:06.756585 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 01:26:06.759911 0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
4501 01:26:06.763142 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 01:26:06.770040 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 01:26:06.773463 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 01:26:06.776759 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 01:26:06.783116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 01:26:06.786384 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 01:26:06.789738 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 01:26:06.796203 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4509 01:26:06.799651 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 01:26:06.803084 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 01:26:06.809851 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 01:26:06.813358 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 01:26:06.815943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 01:26:06.822638 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 01:26:06.826092 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 01:26:06.829369 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 01:26:06.836244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 01:26:06.839120 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 01:26:06.842539 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 01:26:06.849262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 01:26:06.852821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 01:26:06.856015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 01:26:06.862770 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 01:26:06.865874 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4525 01:26:06.869144 Total UI for P1: 0, mck2ui 16
4526 01:26:06.872316 best dqsien dly found for B0: ( 0, 13, 10)
4527 01:26:06.875959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 01:26:06.879257 Total UI for P1: 0, mck2ui 16
4529 01:26:06.882533 best dqsien dly found for B1: ( 0, 13, 12)
4530 01:26:06.885862 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4531 01:26:06.889190 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4532 01:26:06.889271
4533 01:26:06.896234 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4534 01:26:06.899578 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4535 01:26:06.899663 [Gating] SW calibration Done
4536 01:26:06.902394 ==
4537 01:26:06.902478 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 01:26:06.909377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 01:26:06.909462 ==
4540 01:26:06.909528 RX Vref Scan: 0
4541 01:26:06.909589
4542 01:26:06.912676 RX Vref 0 -> 0, step: 1
4543 01:26:06.912758
4544 01:26:06.915476 RX Delay -230 -> 252, step: 16
4545 01:26:06.918939 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4546 01:26:06.922435 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4547 01:26:06.928819 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4548 01:26:06.932221 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4549 01:26:06.935551 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4550 01:26:06.939142 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4551 01:26:06.942396 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4552 01:26:06.949170 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4553 01:26:06.952085 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4554 01:26:06.955413 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4555 01:26:06.959074 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4556 01:26:06.965207 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4557 01:26:06.968606 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4558 01:26:06.972130 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4559 01:26:06.975377 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4560 01:26:06.981898 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4561 01:26:06.981983 ==
4562 01:26:06.985359 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 01:26:06.988396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 01:26:06.988480 ==
4565 01:26:06.988547 DQS Delay:
4566 01:26:06.991624 DQS0 = 0, DQS1 = 0
4567 01:26:06.991707 DQM Delay:
4568 01:26:06.994954 DQM0 = 52, DQM1 = 49
4569 01:26:06.995037 DQ Delay:
4570 01:26:06.998119 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4571 01:26:07.002067 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4572 01:26:07.005014 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4573 01:26:07.008224 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4574 01:26:07.008308
4575 01:26:07.008373
4576 01:26:07.008433 ==
4577 01:26:07.012176 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 01:26:07.015560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 01:26:07.018085 ==
4580 01:26:07.018195
4581 01:26:07.018287
4582 01:26:07.018363 TX Vref Scan disable
4583 01:26:07.021725 == TX Byte 0 ==
4584 01:26:07.025009 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4585 01:26:07.028590 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4586 01:26:07.031916 == TX Byte 1 ==
4587 01:26:07.034657 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4588 01:26:07.038569 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4589 01:26:07.041612 ==
4590 01:26:07.041708 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 01:26:07.048555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 01:26:07.048641 ==
4593 01:26:07.048733
4594 01:26:07.048809
4595 01:26:07.051913 TX Vref Scan disable
4596 01:26:07.051992 == TX Byte 0 ==
4597 01:26:07.058135 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4598 01:26:07.061762 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4599 01:26:07.061851 == TX Byte 1 ==
4600 01:26:07.067928 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4601 01:26:07.071517 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4602 01:26:07.071601
4603 01:26:07.071667 [DATLAT]
4604 01:26:07.074961 Freq=600, CH1 RK0
4605 01:26:07.075044
4606 01:26:07.075110 DATLAT Default: 0x9
4607 01:26:07.077859 0, 0xFFFF, sum = 0
4608 01:26:07.077944 1, 0xFFFF, sum = 0
4609 01:26:07.081327 2, 0xFFFF, sum = 0
4610 01:26:07.081411 3, 0xFFFF, sum = 0
4611 01:26:07.084601 4, 0xFFFF, sum = 0
4612 01:26:07.087916 5, 0xFFFF, sum = 0
4613 01:26:07.088001 6, 0xFFFF, sum = 0
4614 01:26:07.091493 7, 0xFFFF, sum = 0
4615 01:26:07.091577 8, 0x0, sum = 1
4616 01:26:07.091644 9, 0x0, sum = 2
4617 01:26:07.094810 10, 0x0, sum = 3
4618 01:26:07.094895 11, 0x0, sum = 4
4619 01:26:07.098082 best_step = 9
4620 01:26:07.098165
4621 01:26:07.098229 ==
4622 01:26:07.101308 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 01:26:07.104819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 01:26:07.104904 ==
4625 01:26:07.108253 RX Vref Scan: 1
4626 01:26:07.108336
4627 01:26:07.108401 RX Vref 0 -> 0, step: 1
4628 01:26:07.108462
4629 01:26:07.111401 RX Delay -147 -> 252, step: 8
4630 01:26:07.111483
4631 01:26:07.114742 Set Vref, RX VrefLevel [Byte0]: 54
4632 01:26:07.118048 [Byte1]: 51
4633 01:26:07.121961
4634 01:26:07.122046 Final RX Vref Byte 0 = 54 to rank0
4635 01:26:07.125113 Final RX Vref Byte 1 = 51 to rank0
4636 01:26:07.128130 Final RX Vref Byte 0 = 54 to rank1
4637 01:26:07.131999 Final RX Vref Byte 1 = 51 to rank1==
4638 01:26:07.135322 Dram Type= 6, Freq= 0, CH_1, rank 0
4639 01:26:07.141627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 01:26:07.141714 ==
4641 01:26:07.141780 DQS Delay:
4642 01:26:07.141841 DQS0 = 0, DQS1 = 0
4643 01:26:07.144953 DQM Delay:
4644 01:26:07.145064 DQM0 = 48, DQM1 = 45
4645 01:26:07.148237 DQ Delay:
4646 01:26:07.152018 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4647 01:26:07.152103 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4648 01:26:07.155241 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4649 01:26:07.158585 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4650 01:26:07.162060
4651 01:26:07.162143
4652 01:26:07.168457 [DQSOSCAuto] RK0, (LSB)MR18= 0x446a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4653 01:26:07.171880 CH1 RK0: MR19=808, MR18=446A
4654 01:26:07.178155 CH1_RK0: MR19=0x808, MR18=0x446A, DQSOSC=389, MR23=63, INC=173, DEC=115
4655 01:26:07.178240
4656 01:26:07.181647 ----->DramcWriteLeveling(PI) begin...
4657 01:26:07.181732 ==
4658 01:26:07.185147 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 01:26:07.187901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 01:26:07.187984 ==
4661 01:26:07.191320 Write leveling (Byte 0): 31 => 31
4662 01:26:07.194630 Write leveling (Byte 1): 31 => 31
4663 01:26:07.197973 DramcWriteLeveling(PI) end<-----
4664 01:26:07.198062
4665 01:26:07.198127 ==
4666 01:26:07.201365 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 01:26:07.204595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 01:26:07.204679 ==
4669 01:26:07.207971 [Gating] SW mode calibration
4670 01:26:07.214097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4671 01:26:07.221012 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4672 01:26:07.224299 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 01:26:07.231075 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 01:26:07.234561 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4675 01:26:07.237278 0 9 12 | B1->B0 | 2f2f 3030 | 1 0 | (1 0) (0 1)
4676 01:26:07.243786 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4677 01:26:07.247565 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 01:26:07.250933 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 01:26:07.257753 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 01:26:07.260813 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 01:26:07.263892 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 01:26:07.270673 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 01:26:07.274060 0 10 12 | B1->B0 | 3a3a 3636 | 0 0 | (0 0) (1 1)
4684 01:26:07.277544 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 01:26:07.283918 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 01:26:07.287500 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 01:26:07.290893 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 01:26:07.293823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 01:26:07.300622 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 01:26:07.303956 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 01:26:07.307063 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 01:26:07.313549 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 01:26:07.316845 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 01:26:07.320332 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 01:26:07.327089 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 01:26:07.330441 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 01:26:07.333773 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 01:26:07.340373 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 01:26:07.343929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 01:26:07.346701 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 01:26:07.353550 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 01:26:07.356906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 01:26:07.359943 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 01:26:07.366845 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 01:26:07.369989 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 01:26:07.373020 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 01:26:07.379966 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4708 01:26:07.383532 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 01:26:07.386400 Total UI for P1: 0, mck2ui 16
4710 01:26:07.389838 best dqsien dly found for B0: ( 0, 13, 14)
4711 01:26:07.393333 Total UI for P1: 0, mck2ui 16
4712 01:26:07.396772 best dqsien dly found for B1: ( 0, 13, 12)
4713 01:26:07.399568 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4714 01:26:07.403188 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4715 01:26:07.403272
4716 01:26:07.406727 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4717 01:26:07.410026 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4718 01:26:07.413392 [Gating] SW calibration Done
4719 01:26:07.413476 ==
4720 01:26:07.416551 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 01:26:07.422968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 01:26:07.423062 ==
4723 01:26:07.423130 RX Vref Scan: 0
4724 01:26:07.423192
4725 01:26:07.426297 RX Vref 0 -> 0, step: 1
4726 01:26:07.426396
4727 01:26:07.429472 RX Delay -230 -> 252, step: 16
4728 01:26:07.433317 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4729 01:26:07.435993 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4730 01:26:07.439373 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4731 01:26:07.446636 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4732 01:26:07.449305 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4733 01:26:07.452778 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4734 01:26:07.456356 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4735 01:26:07.459712 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4736 01:26:07.465903 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4737 01:26:07.469192 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4738 01:26:07.472889 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4739 01:26:07.476344 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4740 01:26:07.483031 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4741 01:26:07.486105 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4742 01:26:07.489180 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4743 01:26:07.492935 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4744 01:26:07.493049 ==
4745 01:26:07.495573 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 01:26:07.502469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 01:26:07.502560 ==
4748 01:26:07.502629 DQS Delay:
4749 01:26:07.502689 DQS0 = 0, DQS1 = 0
4750 01:26:07.505995 DQM Delay:
4751 01:26:07.506078 DQM0 = 53, DQM1 = 51
4752 01:26:07.509406 DQ Delay:
4753 01:26:07.512885 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4754 01:26:07.515843 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4755 01:26:07.519192 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4756 01:26:07.522580 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4757 01:26:07.522679
4758 01:26:07.522782
4759 01:26:07.522878 ==
4760 01:26:07.526013 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 01:26:07.529259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 01:26:07.529340 ==
4763 01:26:07.529421
4764 01:26:07.529506
4765 01:26:07.532462 TX Vref Scan disable
4766 01:26:07.532544 == TX Byte 0 ==
4767 01:26:07.539257 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 01:26:07.541988 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 01:26:07.542069 == TX Byte 1 ==
4770 01:26:07.549193 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4771 01:26:07.552590 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4772 01:26:07.552680 ==
4773 01:26:07.555887 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 01:26:07.558571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 01:26:07.558657 ==
4776 01:26:07.558739
4777 01:26:07.562132
4778 01:26:07.562212 TX Vref Scan disable
4779 01:26:07.565532 == TX Byte 0 ==
4780 01:26:07.569035 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4781 01:26:07.572405 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4782 01:26:07.575849 == TX Byte 1 ==
4783 01:26:07.579141 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4784 01:26:07.585522 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4785 01:26:07.585625
4786 01:26:07.585710 [DATLAT]
4787 01:26:07.585789 Freq=600, CH1 RK1
4788 01:26:07.585872
4789 01:26:07.588958 DATLAT Default: 0x9
4790 01:26:07.589061 0, 0xFFFF, sum = 0
4791 01:26:07.592409 1, 0xFFFF, sum = 0
4792 01:26:07.592490 2, 0xFFFF, sum = 0
4793 01:26:07.595610 3, 0xFFFF, sum = 0
4794 01:26:07.595712 4, 0xFFFF, sum = 0
4795 01:26:07.598857 5, 0xFFFF, sum = 0
4796 01:26:07.602068 6, 0xFFFF, sum = 0
4797 01:26:07.602151 7, 0xFFFF, sum = 0
4798 01:26:07.602259 8, 0x0, sum = 1
4799 01:26:07.605335 9, 0x0, sum = 2
4800 01:26:07.605420 10, 0x0, sum = 3
4801 01:26:07.608695 11, 0x0, sum = 4
4802 01:26:07.608773 best_step = 9
4803 01:26:07.608855
4804 01:26:07.608940 ==
4805 01:26:07.612010 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 01:26:07.618789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 01:26:07.618875 ==
4808 01:26:07.618966 RX Vref Scan: 0
4809 01:26:07.619046
4810 01:26:07.622306 RX Vref 0 -> 0, step: 1
4811 01:26:07.622383
4812 01:26:07.625023 RX Delay -163 -> 252, step: 8
4813 01:26:07.628429 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4814 01:26:07.635315 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4815 01:26:07.638650 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4816 01:26:07.642012 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4817 01:26:07.646039 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4818 01:26:07.648784 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4819 01:26:07.652067 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4820 01:26:07.658707 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4821 01:26:07.662061 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4822 01:26:07.665315 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4823 01:26:07.668817 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4824 01:26:07.675796 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4825 01:26:07.678624 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4826 01:26:07.682034 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4827 01:26:07.685320 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4828 01:26:07.688741 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4829 01:26:07.692133 ==
4830 01:26:07.695267 Dram Type= 6, Freq= 0, CH_1, rank 1
4831 01:26:07.698941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4832 01:26:07.699025 ==
4833 01:26:07.699091 DQS Delay:
4834 01:26:07.702374 DQS0 = 0, DQS1 = 0
4835 01:26:07.702457 DQM Delay:
4836 01:26:07.705401 DQM0 = 49, DQM1 = 45
4837 01:26:07.705504 DQ Delay:
4838 01:26:07.708338 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4839 01:26:07.712117 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4840 01:26:07.715162 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4841 01:26:07.718865 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4842 01:26:07.718951
4843 01:26:07.719017
4844 01:26:07.725448 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4845 01:26:07.728340 CH1 RK1: MR19=808, MR18=6A22
4846 01:26:07.735312 CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115
4847 01:26:07.738765 [RxdqsGatingPostProcess] freq 600
4848 01:26:07.744869 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4849 01:26:07.744976 Pre-setting of DQS Precalculation
4850 01:26:07.751621 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4851 01:26:07.758332 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4852 01:26:07.765290 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4853 01:26:07.765376
4854 01:26:07.765443
4855 01:26:07.768038 [Calibration Summary] 1200 Mbps
4856 01:26:07.771381 CH 0, Rank 0
4857 01:26:07.771456 SW Impedance : PASS
4858 01:26:07.774748 DUTY Scan : NO K
4859 01:26:07.774827 ZQ Calibration : PASS
4860 01:26:07.778697 Jitter Meter : NO K
4861 01:26:07.781520 CBT Training : PASS
4862 01:26:07.781606 Write leveling : PASS
4863 01:26:07.784880 RX DQS gating : PASS
4864 01:26:07.788421 RX DQ/DQS(RDDQC) : PASS
4865 01:26:07.788505 TX DQ/DQS : PASS
4866 01:26:07.791860 RX DATLAT : PASS
4867 01:26:07.794560 RX DQ/DQS(Engine): PASS
4868 01:26:07.794652 TX OE : NO K
4869 01:26:07.798168 All Pass.
4870 01:26:07.798251
4871 01:26:07.798361 CH 0, Rank 1
4872 01:26:07.801588 SW Impedance : PASS
4873 01:26:07.801691 DUTY Scan : NO K
4874 01:26:07.804755 ZQ Calibration : PASS
4875 01:26:07.808074 Jitter Meter : NO K
4876 01:26:07.808181 CBT Training : PASS
4877 01:26:07.811137 Write leveling : PASS
4878 01:26:07.814704 RX DQS gating : PASS
4879 01:26:07.814786 RX DQ/DQS(RDDQC) : PASS
4880 01:26:07.817968 TX DQ/DQS : PASS
4881 01:26:07.821246 RX DATLAT : PASS
4882 01:26:07.821327 RX DQ/DQS(Engine): PASS
4883 01:26:07.824465 TX OE : NO K
4884 01:26:07.824542 All Pass.
4885 01:26:07.824604
4886 01:26:07.827819 CH 1, Rank 0
4887 01:26:07.827915 SW Impedance : PASS
4888 01:26:07.831565 DUTY Scan : NO K
4889 01:26:07.831648 ZQ Calibration : PASS
4890 01:26:07.834729 Jitter Meter : NO K
4891 01:26:07.838032 CBT Training : PASS
4892 01:26:07.838139 Write leveling : PASS
4893 01:26:07.841414 RX DQS gating : PASS
4894 01:26:07.844971 RX DQ/DQS(RDDQC) : PASS
4895 01:26:07.845066 TX DQ/DQS : PASS
4896 01:26:07.848390 RX DATLAT : PASS
4897 01:26:07.851129 RX DQ/DQS(Engine): PASS
4898 01:26:07.851228 TX OE : NO K
4899 01:26:07.854609 All Pass.
4900 01:26:07.854719
4901 01:26:07.854822 CH 1, Rank 1
4902 01:26:07.857743 SW Impedance : PASS
4903 01:26:07.857823 DUTY Scan : NO K
4904 01:26:07.861519 ZQ Calibration : PASS
4905 01:26:07.864655 Jitter Meter : NO K
4906 01:26:07.864760 CBT Training : PASS
4907 01:26:07.867954 Write leveling : PASS
4908 01:26:07.871470 RX DQS gating : PASS
4909 01:26:07.871577 RX DQ/DQS(RDDQC) : PASS
4910 01:26:07.874915 TX DQ/DQS : PASS
4911 01:26:07.875017 RX DATLAT : PASS
4912 01:26:07.877720 RX DQ/DQS(Engine): PASS
4913 01:26:07.880945 TX OE : NO K
4914 01:26:07.881050 All Pass.
4915 01:26:07.881142
4916 01:26:07.884830 DramC Write-DBI off
4917 01:26:07.887880 PER_BANK_REFRESH: Hybrid Mode
4918 01:26:07.887992 TX_TRACKING: ON
4919 01:26:07.897581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4920 01:26:07.900967 [FAST_K] Save calibration result to emmc
4921 01:26:07.904483 dramc_set_vcore_voltage set vcore to 662500
4922 01:26:07.904587 Read voltage for 933, 3
4923 01:26:07.908048 Vio18 = 0
4924 01:26:07.908150 Vcore = 662500
4925 01:26:07.908240 Vdram = 0
4926 01:26:07.910849 Vddq = 0
4927 01:26:07.910941 Vmddr = 0
4928 01:26:07.914118 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4929 01:26:07.921340 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4930 01:26:07.924522 MEM_TYPE=3, freq_sel=17
4931 01:26:07.927522 sv_algorithm_assistance_LP4_1600
4932 01:26:07.930849 ============ PULL DRAM RESETB DOWN ============
4933 01:26:07.934262 ========== PULL DRAM RESETB DOWN end =========
4934 01:26:07.940786 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4935 01:26:07.944515 ===================================
4936 01:26:07.944623 LPDDR4 DRAM CONFIGURATION
4937 01:26:07.947531 ===================================
4938 01:26:07.951048 EX_ROW_EN[0] = 0x0
4939 01:26:07.951156 EX_ROW_EN[1] = 0x0
4940 01:26:07.954386 LP4Y_EN = 0x0
4941 01:26:07.954486 WORK_FSP = 0x0
4942 01:26:07.957974 WL = 0x3
4943 01:26:07.961293 RL = 0x3
4944 01:26:07.961394 BL = 0x2
4945 01:26:07.964038 RPST = 0x0
4946 01:26:07.964138 RD_PRE = 0x0
4947 01:26:07.967347 WR_PRE = 0x1
4948 01:26:07.967463 WR_PST = 0x0
4949 01:26:07.970836 DBI_WR = 0x0
4950 01:26:07.970943 DBI_RD = 0x0
4951 01:26:07.974013 OTF = 0x1
4952 01:26:07.977821 ===================================
4953 01:26:07.980981 ===================================
4954 01:26:07.981092 ANA top config
4955 01:26:07.984388 ===================================
4956 01:26:07.987755 DLL_ASYNC_EN = 0
4957 01:26:07.991138 ALL_SLAVE_EN = 1
4958 01:26:07.991221 NEW_RANK_MODE = 1
4959 01:26:07.993875 DLL_IDLE_MODE = 1
4960 01:26:07.997972 LP45_APHY_COMB_EN = 1
4961 01:26:08.000859 TX_ODT_DIS = 1
4962 01:26:08.000936 NEW_8X_MODE = 1
4963 01:26:08.004342 ===================================
4964 01:26:08.007797 ===================================
4965 01:26:08.011142 data_rate = 1866
4966 01:26:08.014151 CKR = 1
4967 01:26:08.017562 DQ_P2S_RATIO = 8
4968 01:26:08.020942 ===================================
4969 01:26:08.024451 CA_P2S_RATIO = 8
4970 01:26:08.027854 DQ_CA_OPEN = 0
4971 01:26:08.027969 DQ_SEMI_OPEN = 0
4972 01:26:08.030702 CA_SEMI_OPEN = 0
4973 01:26:08.033847 CA_FULL_RATE = 0
4974 01:26:08.037589 DQ_CKDIV4_EN = 1
4975 01:26:08.040370 CA_CKDIV4_EN = 1
4976 01:26:08.043945 CA_PREDIV_EN = 0
4977 01:26:08.047034 PH8_DLY = 0
4978 01:26:08.047143 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4979 01:26:08.050645 DQ_AAMCK_DIV = 4
4980 01:26:08.053616 CA_AAMCK_DIV = 4
4981 01:26:08.057477 CA_ADMCK_DIV = 4
4982 01:26:08.060552 DQ_TRACK_CA_EN = 0
4983 01:26:08.063788 CA_PICK = 933
4984 01:26:08.063909 CA_MCKIO = 933
4985 01:26:08.067268 MCKIO_SEMI = 0
4986 01:26:08.070642 PLL_FREQ = 3732
4987 01:26:08.074129 DQ_UI_PI_RATIO = 32
4988 01:26:08.077025 CA_UI_PI_RATIO = 0
4989 01:26:08.080352 ===================================
4990 01:26:08.083783 ===================================
4991 01:26:08.086826 memory_type:LPDDR4
4992 01:26:08.086940 GP_NUM : 10
4993 01:26:08.090111 SRAM_EN : 1
4994 01:26:08.090216 MD32_EN : 0
4995 01:26:08.093474 ===================================
4996 01:26:08.096989 [ANA_INIT] >>>>>>>>>>>>>>
4997 01:26:08.100494 <<<<<< [CONFIGURE PHASE]: ANA_TX
4998 01:26:08.103487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4999 01:26:08.107039 ===================================
5000 01:26:08.110334 data_rate = 1866,PCW = 0X8f00
5001 01:26:08.113548 ===================================
5002 01:26:08.116707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5003 01:26:08.123823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5004 01:26:08.126705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 01:26:08.133568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5006 01:26:08.137061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5007 01:26:08.139957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5008 01:26:08.140063 [ANA_INIT] flow start
5009 01:26:08.143345 [ANA_INIT] PLL >>>>>>>>
5010 01:26:08.146791 [ANA_INIT] PLL <<<<<<<<
5011 01:26:08.146900 [ANA_INIT] MIDPI >>>>>>>>
5012 01:26:08.150139 [ANA_INIT] MIDPI <<<<<<<<
5013 01:26:08.153317 [ANA_INIT] DLL >>>>>>>>
5014 01:26:08.153420 [ANA_INIT] flow end
5015 01:26:08.159767 ============ LP4 DIFF to SE enter ============
5016 01:26:08.163482 ============ LP4 DIFF to SE exit ============
5017 01:26:08.166555 [ANA_INIT] <<<<<<<<<<<<<
5018 01:26:08.166630 [Flow] Enable top DCM control >>>>>
5019 01:26:08.170151 [Flow] Enable top DCM control <<<<<
5020 01:26:08.173516 Enable DLL master slave shuffle
5021 01:26:08.179897 ==============================================================
5022 01:26:08.183692 Gating Mode config
5023 01:26:08.186976 ==============================================================
5024 01:26:08.190285 Config description:
5025 01:26:08.200358 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5026 01:26:08.206539 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5027 01:26:08.209794 SELPH_MODE 0: By rank 1: By Phase
5028 01:26:08.217009 ==============================================================
5029 01:26:08.219665 GAT_TRACK_EN = 1
5030 01:26:08.222986 RX_GATING_MODE = 2
5031 01:26:08.226783 RX_GATING_TRACK_MODE = 2
5032 01:26:08.226883 SELPH_MODE = 1
5033 01:26:08.229587 PICG_EARLY_EN = 1
5034 01:26:08.232904 VALID_LAT_VALUE = 1
5035 01:26:08.240012 ==============================================================
5036 01:26:08.242865 Enter into Gating configuration >>>>
5037 01:26:08.246254 Exit from Gating configuration <<<<
5038 01:26:08.249728 Enter into DVFS_PRE_config >>>>>
5039 01:26:08.259615 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5040 01:26:08.262873 Exit from DVFS_PRE_config <<<<<
5041 01:26:08.266232 Enter into PICG configuration >>>>
5042 01:26:08.269607 Exit from PICG configuration <<<<
5043 01:26:08.272980 [RX_INPUT] configuration >>>>>
5044 01:26:08.276257 [RX_INPUT] configuration <<<<<
5045 01:26:08.279983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5046 01:26:08.286508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5047 01:26:08.292996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 01:26:08.299898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 01:26:08.303098 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 01:26:08.309388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 01:26:08.313060 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5052 01:26:08.319283 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5053 01:26:08.323207 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5054 01:26:08.326114 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5055 01:26:08.329393 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5056 01:26:08.336175 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 01:26:08.339505 ===================================
5058 01:26:08.342798 LPDDR4 DRAM CONFIGURATION
5059 01:26:08.346276 ===================================
5060 01:26:08.346386 EX_ROW_EN[0] = 0x0
5061 01:26:08.348946 EX_ROW_EN[1] = 0x0
5062 01:26:08.349044 LP4Y_EN = 0x0
5063 01:26:08.352389 WORK_FSP = 0x0
5064 01:26:08.352486 WL = 0x3
5065 01:26:08.356022 RL = 0x3
5066 01:26:08.356117 BL = 0x2
5067 01:26:08.359490 RPST = 0x0
5068 01:26:08.359592 RD_PRE = 0x0
5069 01:26:08.362439 WR_PRE = 0x1
5070 01:26:08.362543 WR_PST = 0x0
5071 01:26:08.365769 DBI_WR = 0x0
5072 01:26:08.365870 DBI_RD = 0x0
5073 01:26:08.369219 OTF = 0x1
5074 01:26:08.372773 ===================================
5075 01:26:08.375412 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5076 01:26:08.379036 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5077 01:26:08.385698 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5078 01:26:08.389023 ===================================
5079 01:26:08.389101 LPDDR4 DRAM CONFIGURATION
5080 01:26:08.392234 ===================================
5081 01:26:08.396056 EX_ROW_EN[0] = 0x10
5082 01:26:08.399427 EX_ROW_EN[1] = 0x0
5083 01:26:08.399508 LP4Y_EN = 0x0
5084 01:26:08.402703 WORK_FSP = 0x0
5085 01:26:08.402784 WL = 0x3
5086 01:26:08.405949 RL = 0x3
5087 01:26:08.406053 BL = 0x2
5088 01:26:08.408984 RPST = 0x0
5089 01:26:08.409087 RD_PRE = 0x0
5090 01:26:08.412172 WR_PRE = 0x1
5091 01:26:08.412251 WR_PST = 0x0
5092 01:26:08.415577 DBI_WR = 0x0
5093 01:26:08.415665 DBI_RD = 0x0
5094 01:26:08.419047 OTF = 0x1
5095 01:26:08.422579 ===================================
5096 01:26:08.429267 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5097 01:26:08.432271 nWR fixed to 30
5098 01:26:08.435679 [ModeRegInit_LP4] CH0 RK0
5099 01:26:08.435786 [ModeRegInit_LP4] CH0 RK1
5100 01:26:08.438711 [ModeRegInit_LP4] CH1 RK0
5101 01:26:08.442221 [ModeRegInit_LP4] CH1 RK1
5102 01:26:08.442338 match AC timing 9
5103 01:26:08.448929 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5104 01:26:08.452072 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5105 01:26:08.455411 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5106 01:26:08.462380 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5107 01:26:08.465202 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5108 01:26:08.465313 ==
5109 01:26:08.468578 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 01:26:08.472106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 01:26:08.472208 ==
5112 01:26:08.478327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 01:26:08.485265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5114 01:26:08.488657 [CA 0] Center 37 (6~68) winsize 63
5115 01:26:08.491405 [CA 1] Center 37 (7~68) winsize 62
5116 01:26:08.494972 [CA 2] Center 34 (4~65) winsize 62
5117 01:26:08.498376 [CA 3] Center 33 (3~64) winsize 62
5118 01:26:08.501817 [CA 4] Center 33 (3~64) winsize 62
5119 01:26:08.505061 [CA 5] Center 32 (2~62) winsize 61
5120 01:26:08.505170
5121 01:26:08.508104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5122 01:26:08.508217
5123 01:26:08.511749 [CATrainingPosCal] consider 1 rank data
5124 01:26:08.515213 u2DelayCellTimex100 = 270/100 ps
5125 01:26:08.518356 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5126 01:26:08.521537 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5127 01:26:08.524940 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5128 01:26:08.528535 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5129 01:26:08.531872 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5130 01:26:08.535334 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5131 01:26:08.535436
5132 01:26:08.541636 CA PerBit enable=1, Macro0, CA PI delay=32
5133 01:26:08.541738
5134 01:26:08.544972 [CBTSetCACLKResult] CA Dly = 32
5135 01:26:08.545054 CS Dly: 5 (0~36)
5136 01:26:08.545136 ==
5137 01:26:08.548503 Dram Type= 6, Freq= 0, CH_0, rank 1
5138 01:26:08.551479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 01:26:08.551583 ==
5140 01:26:08.558524 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5141 01:26:08.564951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5142 01:26:08.568171 [CA 0] Center 37 (6~68) winsize 63
5143 01:26:08.571478 [CA 1] Center 37 (6~68) winsize 63
5144 01:26:08.575061 [CA 2] Center 34 (4~65) winsize 62
5145 01:26:08.578192 [CA 3] Center 34 (4~65) winsize 62
5146 01:26:08.581822 [CA 4] Center 33 (3~63) winsize 61
5147 01:26:08.585260 [CA 5] Center 32 (2~62) winsize 61
5148 01:26:08.585364
5149 01:26:08.588108 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5150 01:26:08.588207
5151 01:26:08.591607 [CATrainingPosCal] consider 2 rank data
5152 01:26:08.594956 u2DelayCellTimex100 = 270/100 ps
5153 01:26:08.598343 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5154 01:26:08.601961 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5155 01:26:08.604694 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5156 01:26:08.608310 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5157 01:26:08.611771 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5158 01:26:08.614721 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5159 01:26:08.617916
5160 01:26:08.621793 CA PerBit enable=1, Macro0, CA PI delay=32
5161 01:26:08.621900
5162 01:26:08.624890 [CBTSetCACLKResult] CA Dly = 32
5163 01:26:08.624993 CS Dly: 5 (0~37)
5164 01:26:08.625085
5165 01:26:08.627903 ----->DramcWriteLeveling(PI) begin...
5166 01:26:08.628007 ==
5167 01:26:08.631464 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 01:26:08.634793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 01:26:08.638056 ==
5170 01:26:08.638162 Write leveling (Byte 0): 32 => 32
5171 01:26:08.641279 Write leveling (Byte 1): 31 => 31
5172 01:26:08.644598 DramcWriteLeveling(PI) end<-----
5173 01:26:08.644706
5174 01:26:08.644803 ==
5175 01:26:08.648104 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 01:26:08.654888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 01:26:08.654973 ==
5178 01:26:08.655039 [Gating] SW mode calibration
5179 01:26:08.664861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5180 01:26:08.668118 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5181 01:26:08.674756 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5182 01:26:08.677844 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 01:26:08.681040 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 01:26:08.684344 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 01:26:08.691039 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 01:26:08.694597 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 01:26:08.697896 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5188 01:26:08.704312 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
5189 01:26:08.707727 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
5190 01:26:08.711200 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 01:26:08.717987 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 01:26:08.721451 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 01:26:08.724244 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 01:26:08.731159 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 01:26:08.734538 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5196 01:26:08.738151 0 15 28 | B1->B0 | 2626 3737 | 0 1 | (0 0) (0 0)
5197 01:26:08.744133 1 0 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5198 01:26:08.748027 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 01:26:08.751019 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 01:26:08.757443 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 01:26:08.760910 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 01:26:08.764300 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 01:26:08.770851 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5204 01:26:08.774375 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5205 01:26:08.777373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5206 01:26:08.784060 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 01:26:08.787323 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 01:26:08.790830 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 01:26:08.797388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 01:26:08.800570 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 01:26:08.804085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 01:26:08.810692 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 01:26:08.814105 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 01:26:08.817612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 01:26:08.823849 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 01:26:08.827373 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 01:26:08.830769 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 01:26:08.834224 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5219 01:26:08.840523 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5220 01:26:08.844023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5221 01:26:08.847469 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5222 01:26:08.853744 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 01:26:08.857199 Total UI for P1: 0, mck2ui 16
5224 01:26:08.860558 best dqsien dly found for B0: ( 1, 2, 26)
5225 01:26:08.863325 Total UI for P1: 0, mck2ui 16
5226 01:26:08.866781 best dqsien dly found for B1: ( 1, 2, 30)
5227 01:26:08.870173 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5228 01:26:08.873692 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5229 01:26:08.873778
5230 01:26:08.877205 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5231 01:26:08.880046 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5232 01:26:08.883537 [Gating] SW calibration Done
5233 01:26:08.883621 ==
5234 01:26:08.886921 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 01:26:08.890258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 01:26:08.890362 ==
5237 01:26:08.893630 RX Vref Scan: 0
5238 01:26:08.893717
5239 01:26:08.896784 RX Vref 0 -> 0, step: 1
5240 01:26:08.896868
5241 01:26:08.896934 RX Delay -80 -> 252, step: 8
5242 01:26:08.903104 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5243 01:26:08.906588 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5244 01:26:08.909570 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5245 01:26:08.913384 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5246 01:26:08.916621 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5247 01:26:08.923221 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5248 01:26:08.926175 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5249 01:26:08.929435 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5250 01:26:08.933016 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5251 01:26:08.936645 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5252 01:26:08.939260 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5253 01:26:08.946166 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5254 01:26:08.949829 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5255 01:26:08.952524 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5256 01:26:08.956141 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5257 01:26:08.959616 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5258 01:26:08.959699 ==
5259 01:26:08.962381 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 01:26:08.969167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 01:26:08.969251 ==
5262 01:26:08.969316 DQS Delay:
5263 01:26:08.972688 DQS0 = 0, DQS1 = 0
5264 01:26:08.972771 DQM Delay:
5265 01:26:08.972837 DQM0 = 103, DQM1 = 93
5266 01:26:08.976238 DQ Delay:
5267 01:26:08.978929 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5268 01:26:08.982398 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5269 01:26:08.985834 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5270 01:26:08.989267 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5271 01:26:08.989350
5272 01:26:08.989415
5273 01:26:08.989475 ==
5274 01:26:08.992650 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 01:26:08.995942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 01:26:08.996026 ==
5277 01:26:08.996093
5278 01:26:08.996171
5279 01:26:08.999119 TX Vref Scan disable
5280 01:26:09.002161 == TX Byte 0 ==
5281 01:26:09.006060 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5282 01:26:09.009191 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5283 01:26:09.012276 == TX Byte 1 ==
5284 01:26:09.015757 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5285 01:26:09.018780 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5286 01:26:09.018886 ==
5287 01:26:09.022628 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 01:26:09.028579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 01:26:09.028687 ==
5290 01:26:09.028782
5291 01:26:09.028882
5292 01:26:09.028971 TX Vref Scan disable
5293 01:26:09.033059 == TX Byte 0 ==
5294 01:26:09.035924 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5295 01:26:09.042731 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5296 01:26:09.042811 == TX Byte 1 ==
5297 01:26:09.045679 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5298 01:26:09.052413 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5299 01:26:09.052529
5300 01:26:09.052622 [DATLAT]
5301 01:26:09.052723 Freq=933, CH0 RK0
5302 01:26:09.052812
5303 01:26:09.055932 DATLAT Default: 0xd
5304 01:26:09.056031 0, 0xFFFF, sum = 0
5305 01:26:09.059208 1, 0xFFFF, sum = 0
5306 01:26:09.059310 2, 0xFFFF, sum = 0
5307 01:26:09.062728 3, 0xFFFF, sum = 0
5308 01:26:09.066152 4, 0xFFFF, sum = 0
5309 01:26:09.066262 5, 0xFFFF, sum = 0
5310 01:26:09.069574 6, 0xFFFF, sum = 0
5311 01:26:09.069681 7, 0xFFFF, sum = 0
5312 01:26:09.072996 8, 0xFFFF, sum = 0
5313 01:26:09.073100 9, 0xFFFF, sum = 0
5314 01:26:09.075750 10, 0x0, sum = 1
5315 01:26:09.075850 11, 0x0, sum = 2
5316 01:26:09.075951 12, 0x0, sum = 3
5317 01:26:09.079094 13, 0x0, sum = 4
5318 01:26:09.079198 best_step = 11
5319 01:26:09.079287
5320 01:26:09.082613 ==
5321 01:26:09.082714 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 01:26:09.089509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 01:26:09.089620 ==
5324 01:26:09.089718 RX Vref Scan: 1
5325 01:26:09.089795
5326 01:26:09.092270 RX Vref 0 -> 0, step: 1
5327 01:26:09.092370
5328 01:26:09.095591 RX Delay -53 -> 252, step: 4
5329 01:26:09.095692
5330 01:26:09.099114 Set Vref, RX VrefLevel [Byte0]: 56
5331 01:26:09.102697 [Byte1]: 46
5332 01:26:09.102775
5333 01:26:09.105564 Final RX Vref Byte 0 = 56 to rank0
5334 01:26:09.108940 Final RX Vref Byte 1 = 46 to rank0
5335 01:26:09.112286 Final RX Vref Byte 0 = 56 to rank1
5336 01:26:09.115670 Final RX Vref Byte 1 = 46 to rank1==
5337 01:26:09.118973 Dram Type= 6, Freq= 0, CH_0, rank 0
5338 01:26:09.122325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 01:26:09.122431 ==
5340 01:26:09.125582 DQS Delay:
5341 01:26:09.125685 DQS0 = 0, DQS1 = 0
5342 01:26:09.129236 DQM Delay:
5343 01:26:09.129324 DQM0 = 105, DQM1 = 94
5344 01:26:09.129386 DQ Delay:
5345 01:26:09.135683 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5346 01:26:09.138996 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =110
5347 01:26:09.139075 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5348 01:26:09.145792 DQ12 =98, DQ13 =98, DQ14 =108, DQ15 =100
5349 01:26:09.145871
5350 01:26:09.145933
5351 01:26:09.152403 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5352 01:26:09.155472 CH0 RK0: MR19=505, MR18=2D24
5353 01:26:09.162543 CH0_RK0: MR19=0x505, MR18=0x2D24, DQSOSC=407, MR23=63, INC=65, DEC=43
5354 01:26:09.162622
5355 01:26:09.165580 ----->DramcWriteLeveling(PI) begin...
5356 01:26:09.165683 ==
5357 01:26:09.169180 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 01:26:09.172125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 01:26:09.172198 ==
5360 01:26:09.175577 Write leveling (Byte 0): 35 => 35
5361 01:26:09.179125 Write leveling (Byte 1): 29 => 29
5362 01:26:09.182540 DramcWriteLeveling(PI) end<-----
5363 01:26:09.182637
5364 01:26:09.182732 ==
5365 01:26:09.186075 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 01:26:09.188903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 01:26:09.188991 ==
5368 01:26:09.192318 [Gating] SW mode calibration
5369 01:26:09.199132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5370 01:26:09.205944 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5371 01:26:09.209353 0 14 0 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
5372 01:26:09.212657 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 01:26:09.218936 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 01:26:09.222494 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 01:26:09.225236 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 01:26:09.232091 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 01:26:09.235297 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5378 01:26:09.238700 0 14 28 | B1->B0 | 2727 2b2b | 1 1 | (0 0) (0 0)
5379 01:26:09.245326 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5380 01:26:09.248904 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 01:26:09.252069 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 01:26:09.259047 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 01:26:09.262188 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 01:26:09.265687 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 01:26:09.271922 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5386 01:26:09.275322 0 15 28 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (0 0)
5387 01:26:09.278626 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 01:26:09.285002 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 01:26:09.288605 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 01:26:09.291708 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 01:26:09.298636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 01:26:09.302039 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 01:26:09.305331 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 01:26:09.312178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5395 01:26:09.314998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 01:26:09.318392 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 01:26:09.325476 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 01:26:09.328207 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 01:26:09.331814 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 01:26:09.338757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 01:26:09.342055 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 01:26:09.345562 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 01:26:09.351864 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 01:26:09.355095 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 01:26:09.358591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 01:26:09.364835 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 01:26:09.367898 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 01:26:09.371683 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 01:26:09.374722 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5410 01:26:09.381923 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5411 01:26:09.384520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5412 01:26:09.387900 Total UI for P1: 0, mck2ui 16
5413 01:26:09.391569 best dqsien dly found for B1: ( 1, 2, 28)
5414 01:26:09.394955 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 01:26:09.398234 Total UI for P1: 0, mck2ui 16
5416 01:26:09.401599 best dqsien dly found for B0: ( 1, 2, 28)
5417 01:26:09.404831 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5418 01:26:09.407894 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5419 01:26:09.411302
5420 01:26:09.414792 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5421 01:26:09.418129 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5422 01:26:09.421005 [Gating] SW calibration Done
5423 01:26:09.421119 ==
5424 01:26:09.424297 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 01:26:09.427697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 01:26:09.427777 ==
5427 01:26:09.427850 RX Vref Scan: 0
5428 01:26:09.431057
5429 01:26:09.431131 RX Vref 0 -> 0, step: 1
5430 01:26:09.431201
5431 01:26:09.434538 RX Delay -80 -> 252, step: 8
5432 01:26:09.438140 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5433 01:26:09.441533 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5434 01:26:09.447749 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5435 01:26:09.451095 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5436 01:26:09.454726 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5437 01:26:09.458113 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5438 01:26:09.461440 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5439 01:26:09.464610 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5440 01:26:09.471002 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5441 01:26:09.474426 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5442 01:26:09.477756 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5443 01:26:09.481183 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5444 01:26:09.484499 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5445 01:26:09.487774 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5446 01:26:09.494170 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5447 01:26:09.497586 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5448 01:26:09.497666 ==
5449 01:26:09.501107 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 01:26:09.504503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 01:26:09.504603 ==
5452 01:26:09.507849 DQS Delay:
5453 01:26:09.507951 DQS0 = 0, DQS1 = 0
5454 01:26:09.508041 DQM Delay:
5455 01:26:09.511360 DQM0 = 104, DQM1 = 93
5456 01:26:09.511472 DQ Delay:
5457 01:26:09.514253 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5458 01:26:09.517621 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5459 01:26:09.520878 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5460 01:26:09.524178 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5461 01:26:09.524285
5462 01:26:09.524377
5463 01:26:09.527357 ==
5464 01:26:09.531300 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 01:26:09.534059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 01:26:09.534160 ==
5467 01:26:09.534252
5468 01:26:09.534338
5469 01:26:09.537580 TX Vref Scan disable
5470 01:26:09.537676 == TX Byte 0 ==
5471 01:26:09.544186 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5472 01:26:09.547618 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5473 01:26:09.547727 == TX Byte 1 ==
5474 01:26:09.550584 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5475 01:26:09.557313 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5476 01:26:09.557418 ==
5477 01:26:09.560845 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 01:26:09.564182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 01:26:09.564279 ==
5480 01:26:09.564372
5481 01:26:09.564465
5482 01:26:09.567559 TX Vref Scan disable
5483 01:26:09.571058 == TX Byte 0 ==
5484 01:26:09.573851 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5485 01:26:09.577271 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5486 01:26:09.580707 == TX Byte 1 ==
5487 01:26:09.584195 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5488 01:26:09.587585 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5489 01:26:09.587698
5490 01:26:09.590382 [DATLAT]
5491 01:26:09.590481 Freq=933, CH0 RK1
5492 01:26:09.590572
5493 01:26:09.593807 DATLAT Default: 0xb
5494 01:26:09.593878 0, 0xFFFF, sum = 0
5495 01:26:09.597033 1, 0xFFFF, sum = 0
5496 01:26:09.597105 2, 0xFFFF, sum = 0
5497 01:26:09.600930 3, 0xFFFF, sum = 0
5498 01:26:09.601036 4, 0xFFFF, sum = 0
5499 01:26:09.604107 5, 0xFFFF, sum = 0
5500 01:26:09.604180 6, 0xFFFF, sum = 0
5501 01:26:09.607363 7, 0xFFFF, sum = 0
5502 01:26:09.607444 8, 0xFFFF, sum = 0
5503 01:26:09.610790 9, 0xFFFF, sum = 0
5504 01:26:09.610890 10, 0x0, sum = 1
5505 01:26:09.613472 11, 0x0, sum = 2
5506 01:26:09.613541 12, 0x0, sum = 3
5507 01:26:09.617013 13, 0x0, sum = 4
5508 01:26:09.617081 best_step = 11
5509 01:26:09.617139
5510 01:26:09.617207 ==
5511 01:26:09.620399 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 01:26:09.627305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 01:26:09.627394 ==
5514 01:26:09.627457 RX Vref Scan: 0
5515 01:26:09.627526
5516 01:26:09.630133 RX Vref 0 -> 0, step: 1
5517 01:26:09.630233
5518 01:26:09.633514 RX Delay -53 -> 252, step: 4
5519 01:26:09.636990 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5520 01:26:09.640281 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5521 01:26:09.646899 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5522 01:26:09.650008 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5523 01:26:09.653125 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5524 01:26:09.656763 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5525 01:26:09.659663 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5526 01:26:09.666299 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5527 01:26:09.669842 iDelay=199, Bit 8, Center 84 (3 ~ 166) 164
5528 01:26:09.673072 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5529 01:26:09.676208 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5530 01:26:09.679917 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5531 01:26:09.686249 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5532 01:26:09.689519 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5533 01:26:09.692960 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5534 01:26:09.696268 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5535 01:26:09.696345 ==
5536 01:26:09.699621 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 01:26:09.703057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 01:26:09.706333 ==
5539 01:26:09.706406 DQS Delay:
5540 01:26:09.706471 DQS0 = 0, DQS1 = 0
5541 01:26:09.709773 DQM Delay:
5542 01:26:09.709845 DQM0 = 104, DQM1 = 93
5543 01:26:09.713036 DQ Delay:
5544 01:26:09.716179 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5545 01:26:09.719659 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =112
5546 01:26:09.723001 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5547 01:26:09.726296 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5548 01:26:09.726409
5549 01:26:09.726504
5550 01:26:09.732543 [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5551 01:26:09.736033 CH0 RK1: MR19=505, MR18=2700
5552 01:26:09.742377 CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43
5553 01:26:09.745821 [RxdqsGatingPostProcess] freq 933
5554 01:26:09.752729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5555 01:26:09.755623 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 01:26:09.755697 best DQS1 dly(2T, 0.5T) = (0, 10)
5557 01:26:09.759057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 01:26:09.762524 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5559 01:26:09.766088 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 01:26:09.768813 best DQS1 dly(2T, 0.5T) = (0, 10)
5561 01:26:09.772064 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 01:26:09.775354 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5563 01:26:09.778573 Pre-setting of DQS Precalculation
5564 01:26:09.785303 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5565 01:26:09.785410 ==
5566 01:26:09.788728 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 01:26:09.791625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 01:26:09.791733 ==
5569 01:26:09.798396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 01:26:09.804857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5571 01:26:09.808049 [CA 0] Center 36 (6~67) winsize 62
5572 01:26:09.811591 [CA 1] Center 37 (6~68) winsize 63
5573 01:26:09.815251 [CA 2] Center 35 (5~65) winsize 61
5574 01:26:09.818313 [CA 3] Center 34 (4~65) winsize 62
5575 01:26:09.821681 [CA 4] Center 34 (4~65) winsize 62
5576 01:26:09.821796 [CA 5] Center 33 (3~64) winsize 62
5577 01:26:09.824915
5578 01:26:09.827934 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5579 01:26:09.828035
5580 01:26:09.831604 [CATrainingPosCal] consider 1 rank data
5581 01:26:09.834958 u2DelayCellTimex100 = 270/100 ps
5582 01:26:09.837831 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 01:26:09.841276 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5584 01:26:09.844928 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5585 01:26:09.848298 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 01:26:09.851664 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5587 01:26:09.855001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5588 01:26:09.855079
5589 01:26:09.861371 CA PerBit enable=1, Macro0, CA PI delay=33
5590 01:26:09.861448
5591 01:26:09.861511 [CBTSetCACLKResult] CA Dly = 33
5592 01:26:09.864778 CS Dly: 6 (0~37)
5593 01:26:09.864850 ==
5594 01:26:09.867617 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 01:26:09.871039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 01:26:09.871121 ==
5597 01:26:09.878097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5598 01:26:09.884918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5599 01:26:09.887712 [CA 0] Center 37 (7~67) winsize 61
5600 01:26:09.891353 [CA 1] Center 37 (7~68) winsize 62
5601 01:26:09.894582 [CA 2] Center 35 (5~65) winsize 61
5602 01:26:09.898160 [CA 3] Center 34 (4~65) winsize 62
5603 01:26:09.900916 [CA 4] Center 34 (4~65) winsize 62
5604 01:26:09.904346 [CA 5] Center 33 (3~64) winsize 62
5605 01:26:09.904445
5606 01:26:09.907657 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5607 01:26:09.907734
5608 01:26:09.910829 [CATrainingPosCal] consider 2 rank data
5609 01:26:09.914175 u2DelayCellTimex100 = 270/100 ps
5610 01:26:09.917445 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5611 01:26:09.921226 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5612 01:26:09.924173 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5613 01:26:09.927791 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5614 01:26:09.931202 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5615 01:26:09.933999 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5616 01:26:09.937205
5617 01:26:09.941023 CA PerBit enable=1, Macro0, CA PI delay=33
5618 01:26:09.941128
5619 01:26:09.944251 [CBTSetCACLKResult] CA Dly = 33
5620 01:26:09.944360 CS Dly: 7 (0~40)
5621 01:26:09.944452
5622 01:26:09.947565 ----->DramcWriteLeveling(PI) begin...
5623 01:26:09.947670 ==
5624 01:26:09.950388 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 01:26:09.954195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 01:26:09.957231 ==
5627 01:26:09.957313 Write leveling (Byte 0): 27 => 27
5628 01:26:09.960369 Write leveling (Byte 1): 26 => 26
5629 01:26:09.964178 DramcWriteLeveling(PI) end<-----
5630 01:26:09.964260
5631 01:26:09.964324 ==
5632 01:26:09.967113 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 01:26:09.973970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 01:26:09.974074 ==
5635 01:26:09.976866 [Gating] SW mode calibration
5636 01:26:09.983708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5637 01:26:09.987143 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5638 01:26:09.994022 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 01:26:09.996838 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 01:26:10.000210 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 01:26:10.006439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 01:26:10.009961 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 01:26:10.013292 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5644 01:26:10.020180 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
5645 01:26:10.023599 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
5646 01:26:10.026445 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 01:26:10.033223 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 01:26:10.036708 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 01:26:10.040184 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 01:26:10.046850 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 01:26:10.049548 0 15 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5652 01:26:10.053297 0 15 24 | B1->B0 | 2727 3131 | 0 1 | (0 0) (0 0)
5653 01:26:10.059645 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5654 01:26:10.062821 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 01:26:10.066680 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 01:26:10.072836 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 01:26:10.076304 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 01:26:10.079434 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 01:26:10.082776 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 01:26:10.089812 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5661 01:26:10.093321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 01:26:10.096133 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 01:26:10.102982 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 01:26:10.106520 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 01:26:10.109846 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 01:26:10.116225 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 01:26:10.119757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 01:26:10.123264 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 01:26:10.129377 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 01:26:10.132914 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 01:26:10.136346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 01:26:10.143101 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 01:26:10.145822 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 01:26:10.149365 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 01:26:10.155992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 01:26:10.159276 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5677 01:26:10.162647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5678 01:26:10.169351 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 01:26:10.169463 Total UI for P1: 0, mck2ui 16
5680 01:26:10.176254 best dqsien dly found for B0: ( 1, 2, 26)
5681 01:26:10.176341 Total UI for P1: 0, mck2ui 16
5682 01:26:10.182436 best dqsien dly found for B1: ( 1, 2, 26)
5683 01:26:10.185944 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5684 01:26:10.189330 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5685 01:26:10.189429
5686 01:26:10.192625 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5687 01:26:10.195839 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5688 01:26:10.198824 [Gating] SW calibration Done
5689 01:26:10.198898 ==
5690 01:26:10.202670 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 01:26:10.205672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 01:26:10.205772 ==
5693 01:26:10.208903 RX Vref Scan: 0
5694 01:26:10.208999
5695 01:26:10.209096 RX Vref 0 -> 0, step: 1
5696 01:26:10.209183
5697 01:26:10.212146 RX Delay -80 -> 252, step: 8
5698 01:26:10.215561 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5699 01:26:10.221986 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5700 01:26:10.225577 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5701 01:26:10.229049 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5702 01:26:10.232364 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5703 01:26:10.235731 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5704 01:26:10.239297 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5705 01:26:10.246034 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5706 01:26:10.249252 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5707 01:26:10.252100 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5708 01:26:10.255410 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5709 01:26:10.258819 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5710 01:26:10.262225 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5711 01:26:10.269222 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5712 01:26:10.271965 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5713 01:26:10.275804 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5714 01:26:10.275908 ==
5715 01:26:10.279299 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 01:26:10.282203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 01:26:10.282314 ==
5718 01:26:10.285606 DQS Delay:
5719 01:26:10.285683 DQS0 = 0, DQS1 = 0
5720 01:26:10.289022 DQM Delay:
5721 01:26:10.289096 DQM0 = 102, DQM1 = 98
5722 01:26:10.289157 DQ Delay:
5723 01:26:10.292554 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5724 01:26:10.295517 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5725 01:26:10.298952 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5726 01:26:10.305273 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5727 01:26:10.305350
5728 01:26:10.305416
5729 01:26:10.305476 ==
5730 01:26:10.308517 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 01:26:10.311897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 01:26:10.312000 ==
5733 01:26:10.312091
5734 01:26:10.312193
5735 01:26:10.315318 TX Vref Scan disable
5736 01:26:10.315392 == TX Byte 0 ==
5737 01:26:10.321749 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5738 01:26:10.325396 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5739 01:26:10.325478 == TX Byte 1 ==
5740 01:26:10.331589 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5741 01:26:10.335091 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5742 01:26:10.335179 ==
5743 01:26:10.338229 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 01:26:10.341916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 01:26:10.341999 ==
5746 01:26:10.342068
5747 01:26:10.345179
5748 01:26:10.345261 TX Vref Scan disable
5749 01:26:10.348520 == TX Byte 0 ==
5750 01:26:10.351852 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5751 01:26:10.355278 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5752 01:26:10.358772 == TX Byte 1 ==
5753 01:26:10.362001 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5754 01:26:10.365275 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5755 01:26:10.365376
5756 01:26:10.368839 [DATLAT]
5757 01:26:10.368914 Freq=933, CH1 RK0
5758 01:26:10.368977
5759 01:26:10.371648 DATLAT Default: 0xd
5760 01:26:10.371724 0, 0xFFFF, sum = 0
5761 01:26:10.375088 1, 0xFFFF, sum = 0
5762 01:26:10.375162 2, 0xFFFF, sum = 0
5763 01:26:10.378368 3, 0xFFFF, sum = 0
5764 01:26:10.378444 4, 0xFFFF, sum = 0
5765 01:26:10.381769 5, 0xFFFF, sum = 0
5766 01:26:10.381849 6, 0xFFFF, sum = 0
5767 01:26:10.385111 7, 0xFFFF, sum = 0
5768 01:26:10.388353 8, 0xFFFF, sum = 0
5769 01:26:10.388431 9, 0xFFFF, sum = 0
5770 01:26:10.388494 10, 0x0, sum = 1
5771 01:26:10.391458 11, 0x0, sum = 2
5772 01:26:10.391564 12, 0x0, sum = 3
5773 01:26:10.394899 13, 0x0, sum = 4
5774 01:26:10.394971 best_step = 11
5775 01:26:10.395032
5776 01:26:10.395090 ==
5777 01:26:10.398278 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 01:26:10.404727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 01:26:10.404805 ==
5780 01:26:10.404872 RX Vref Scan: 1
5781 01:26:10.404931
5782 01:26:10.408153 RX Vref 0 -> 0, step: 1
5783 01:26:10.408223
5784 01:26:10.411539 RX Delay -45 -> 252, step: 4
5785 01:26:10.411610
5786 01:26:10.415068 Set Vref, RX VrefLevel [Byte0]: 54
5787 01:26:10.418293 [Byte1]: 51
5788 01:26:10.418376
5789 01:26:10.421842 Final RX Vref Byte 0 = 54 to rank0
5790 01:26:10.424720 Final RX Vref Byte 1 = 51 to rank0
5791 01:26:10.428157 Final RX Vref Byte 0 = 54 to rank1
5792 01:26:10.431622 Final RX Vref Byte 1 = 51 to rank1==
5793 01:26:10.435049 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 01:26:10.438365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 01:26:10.438442 ==
5796 01:26:10.441515 DQS Delay:
5797 01:26:10.441588 DQS0 = 0, DQS1 = 0
5798 01:26:10.444643 DQM Delay:
5799 01:26:10.444714 DQM0 = 103, DQM1 = 99
5800 01:26:10.444777 DQ Delay:
5801 01:26:10.447789 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5802 01:26:10.451103 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5803 01:26:10.454896 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5804 01:26:10.461645 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =108
5805 01:26:10.461733
5806 01:26:10.461798
5807 01:26:10.468065 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5808 01:26:10.471186 CH1 RK0: MR19=505, MR18=152D
5809 01:26:10.478037 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5810 01:26:10.478117
5811 01:26:10.481290 ----->DramcWriteLeveling(PI) begin...
5812 01:26:10.481369 ==
5813 01:26:10.484753 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 01:26:10.488300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 01:26:10.488373 ==
5816 01:26:10.491037 Write leveling (Byte 0): 28 => 28
5817 01:26:10.494349 Write leveling (Byte 1): 29 => 29
5818 01:26:10.497689 DramcWriteLeveling(PI) end<-----
5819 01:26:10.497760
5820 01:26:10.497820 ==
5821 01:26:10.500995 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 01:26:10.504325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 01:26:10.504399 ==
5824 01:26:10.507868 [Gating] SW mode calibration
5825 01:26:10.514835 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5826 01:26:10.520960 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5827 01:26:10.524467 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 01:26:10.531298 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 01:26:10.534128 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 01:26:10.537527 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 01:26:10.544387 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 01:26:10.547989 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 01:26:10.550748 0 14 24 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
5834 01:26:10.554090 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5835 01:26:10.560893 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 01:26:10.564046 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 01:26:10.567838 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 01:26:10.574497 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 01:26:10.577681 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 01:26:10.581023 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 01:26:10.587265 0 15 24 | B1->B0 | 3535 2929 | 1 0 | (0 0) (0 0)
5842 01:26:10.590653 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (1 1)
5843 01:26:10.594172 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 01:26:10.600773 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 01:26:10.603915 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 01:26:10.607084 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 01:26:10.613960 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 01:26:10.616915 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 01:26:10.620592 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5850 01:26:10.627328 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5851 01:26:10.630698 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 01:26:10.633532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 01:26:10.640539 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 01:26:10.643968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 01:26:10.646711 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 01:26:10.653761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 01:26:10.657283 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 01:26:10.660087 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 01:26:10.667146 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 01:26:10.670354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 01:26:10.673661 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 01:26:10.680586 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 01:26:10.683699 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 01:26:10.687281 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5865 01:26:10.693841 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5866 01:26:10.696718 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5867 01:26:10.700038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 01:26:10.703544 Total UI for P1: 0, mck2ui 16
5869 01:26:10.706999 best dqsien dly found for B0: ( 1, 2, 28)
5870 01:26:10.709768 Total UI for P1: 0, mck2ui 16
5871 01:26:10.713138 best dqsien dly found for B1: ( 1, 2, 24)
5872 01:26:10.716483 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5873 01:26:10.719735 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5874 01:26:10.719818
5875 01:26:10.723477 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5876 01:26:10.729879 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5877 01:26:10.729969 [Gating] SW calibration Done
5878 01:26:10.730035 ==
5879 01:26:10.733372 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 01:26:10.740058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 01:26:10.740142 ==
5882 01:26:10.740207 RX Vref Scan: 0
5883 01:26:10.740267
5884 01:26:10.743379 RX Vref 0 -> 0, step: 1
5885 01:26:10.743461
5886 01:26:10.746634 RX Delay -80 -> 252, step: 8
5887 01:26:10.750046 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5888 01:26:10.753107 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5889 01:26:10.756555 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5890 01:26:10.759991 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5891 01:26:10.766316 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5892 01:26:10.769702 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5893 01:26:10.773052 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5894 01:26:10.776643 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5895 01:26:10.779987 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5896 01:26:10.783457 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5897 01:26:10.790145 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5898 01:26:10.793470 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5899 01:26:10.796599 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5900 01:26:10.799984 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5901 01:26:10.803389 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5902 01:26:10.809705 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5903 01:26:10.809813 ==
5904 01:26:10.813093 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 01:26:10.816588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 01:26:10.816694 ==
5907 01:26:10.816786 DQS Delay:
5908 01:26:10.820055 DQS0 = 0, DQS1 = 0
5909 01:26:10.820129 DQM Delay:
5910 01:26:10.822810 DQM0 = 102, DQM1 = 99
5911 01:26:10.822884 DQ Delay:
5912 01:26:10.826282 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =95
5913 01:26:10.829779 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5914 01:26:10.833211 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5915 01:26:10.836727 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5916 01:26:10.836845
5917 01:26:10.836940
5918 01:26:10.837035 ==
5919 01:26:10.839924 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 01:26:10.843362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 01:26:10.846578 ==
5922 01:26:10.846654
5923 01:26:10.846718
5924 01:26:10.846784 TX Vref Scan disable
5925 01:26:10.850005 == TX Byte 0 ==
5926 01:26:10.853288 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5927 01:26:10.856641 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5928 01:26:10.859828 == TX Byte 1 ==
5929 01:26:10.862913 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5930 01:26:10.866492 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5931 01:26:10.869489 ==
5932 01:26:10.873078 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 01:26:10.876073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 01:26:10.876148 ==
5935 01:26:10.876241
5936 01:26:10.876328
5937 01:26:10.879835 TX Vref Scan disable
5938 01:26:10.879911 == TX Byte 0 ==
5939 01:26:10.885860 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5940 01:26:10.889271 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5941 01:26:10.889372 == TX Byte 1 ==
5942 01:26:10.896084 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5943 01:26:10.899589 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5944 01:26:10.899696
5945 01:26:10.899789 [DATLAT]
5946 01:26:10.903010 Freq=933, CH1 RK1
5947 01:26:10.903083
5948 01:26:10.903145 DATLAT Default: 0xb
5949 01:26:10.906020 0, 0xFFFF, sum = 0
5950 01:26:10.906120 1, 0xFFFF, sum = 0
5951 01:26:10.909161 2, 0xFFFF, sum = 0
5952 01:26:10.909261 3, 0xFFFF, sum = 0
5953 01:26:10.912598 4, 0xFFFF, sum = 0
5954 01:26:10.912672 5, 0xFFFF, sum = 0
5955 01:26:10.915719 6, 0xFFFF, sum = 0
5956 01:26:10.919556 7, 0xFFFF, sum = 0
5957 01:26:10.919635 8, 0xFFFF, sum = 0
5958 01:26:10.922297 9, 0xFFFF, sum = 0
5959 01:26:10.922407 10, 0x0, sum = 1
5960 01:26:10.922502 11, 0x0, sum = 2
5961 01:26:10.925746 12, 0x0, sum = 3
5962 01:26:10.925849 13, 0x0, sum = 4
5963 01:26:10.929154 best_step = 11
5964 01:26:10.929230
5965 01:26:10.929293 ==
5966 01:26:10.932724 Dram Type= 6, Freq= 0, CH_1, rank 1
5967 01:26:10.936036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5968 01:26:10.936140 ==
5969 01:26:10.939490 RX Vref Scan: 0
5970 01:26:10.939596
5971 01:26:10.939689 RX Vref 0 -> 0, step: 1
5972 01:26:10.939784
5973 01:26:10.942321 RX Delay -45 -> 252, step: 4
5974 01:26:10.949841 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5975 01:26:10.953074 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5976 01:26:10.956517 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5977 01:26:10.960042 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5978 01:26:10.963015 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5979 01:26:10.969895 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5980 01:26:10.973291 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5981 01:26:10.976747 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5982 01:26:10.980266 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5983 01:26:10.983522 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5984 01:26:10.986647 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5985 01:26:10.992886 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5986 01:26:10.996297 iDelay=203, Bit 12, Center 112 (27 ~ 198) 172
5987 01:26:10.999741 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5988 01:26:11.003303 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5989 01:26:11.009464 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5990 01:26:11.009567 ==
5991 01:26:11.012825 Dram Type= 6, Freq= 0, CH_1, rank 1
5992 01:26:11.016262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5993 01:26:11.016361 ==
5994 01:26:11.016461 DQS Delay:
5995 01:26:11.019757 DQS0 = 0, DQS1 = 0
5996 01:26:11.019860 DQM Delay:
5997 01:26:11.022922 DQM0 = 104, DQM1 = 101
5998 01:26:11.022996 DQ Delay:
5999 01:26:11.026260 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
6000 01:26:11.029322 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
6001 01:26:11.033176 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
6002 01:26:11.036323 DQ12 =112, DQ13 =106, DQ14 =106, DQ15 =110
6003 01:26:11.036426
6004 01:26:11.036517
6005 01:26:11.045969 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
6006 01:26:11.046076 CH1 RK1: MR19=504, MR18=2AFD
6007 01:26:11.052816 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
6008 01:26:11.056227 [RxdqsGatingPostProcess] freq 933
6009 01:26:11.062940 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6010 01:26:11.066408 best DQS0 dly(2T, 0.5T) = (0, 10)
6011 01:26:11.069137 best DQS1 dly(2T, 0.5T) = (0, 10)
6012 01:26:11.072752 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6013 01:26:11.076162 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6014 01:26:11.079332 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 01:26:11.082846 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 01:26:11.085651 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 01:26:11.089073 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 01:26:11.089156 Pre-setting of DQS Precalculation
6019 01:26:11.095925 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6020 01:26:11.103046 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6021 01:26:11.109319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6022 01:26:11.109403
6023 01:26:11.109469
6024 01:26:11.112309 [Calibration Summary] 1866 Mbps
6025 01:26:11.115710 CH 0, Rank 0
6026 01:26:11.115791 SW Impedance : PASS
6027 01:26:11.119170 DUTY Scan : NO K
6028 01:26:11.122254 ZQ Calibration : PASS
6029 01:26:11.122373 Jitter Meter : NO K
6030 01:26:11.125554 CBT Training : PASS
6031 01:26:11.129117 Write leveling : PASS
6032 01:26:11.129232 RX DQS gating : PASS
6033 01:26:11.132585 RX DQ/DQS(RDDQC) : PASS
6034 01:26:11.135713 TX DQ/DQS : PASS
6035 01:26:11.135816 RX DATLAT : PASS
6036 01:26:11.139198 RX DQ/DQS(Engine): PASS
6037 01:26:11.139304 TX OE : NO K
6038 01:26:11.142522 All Pass.
6039 01:26:11.142598
6040 01:26:11.142660 CH 0, Rank 1
6041 01:26:11.145651 SW Impedance : PASS
6042 01:26:11.145755 DUTY Scan : NO K
6043 01:26:11.148846 ZQ Calibration : PASS
6044 01:26:11.151951 Jitter Meter : NO K
6045 01:26:11.152051 CBT Training : PASS
6046 01:26:11.155388 Write leveling : PASS
6047 01:26:11.158545 RX DQS gating : PASS
6048 01:26:11.158622 RX DQ/DQS(RDDQC) : PASS
6049 01:26:11.161718 TX DQ/DQS : PASS
6050 01:26:11.165265 RX DATLAT : PASS
6051 01:26:11.165365 RX DQ/DQS(Engine): PASS
6052 01:26:11.168662 TX OE : NO K
6053 01:26:11.168763 All Pass.
6054 01:26:11.168852
6055 01:26:11.171940 CH 1, Rank 0
6056 01:26:11.172033 SW Impedance : PASS
6057 01:26:11.175519 DUTY Scan : NO K
6058 01:26:11.178214 ZQ Calibration : PASS
6059 01:26:11.178332 Jitter Meter : NO K
6060 01:26:11.181671 CBT Training : PASS
6061 01:26:11.184992 Write leveling : PASS
6062 01:26:11.185091 RX DQS gating : PASS
6063 01:26:11.188361 RX DQ/DQS(RDDQC) : PASS
6064 01:26:11.191621 TX DQ/DQS : PASS
6065 01:26:11.191695 RX DATLAT : PASS
6066 01:26:11.195187 RX DQ/DQS(Engine): PASS
6067 01:26:11.198693 TX OE : NO K
6068 01:26:11.198766 All Pass.
6069 01:26:11.198846
6070 01:26:11.198906 CH 1, Rank 1
6071 01:26:11.202174 SW Impedance : PASS
6072 01:26:11.202297 DUTY Scan : NO K
6073 01:26:11.204945 ZQ Calibration : PASS
6074 01:26:11.208522 Jitter Meter : NO K
6075 01:26:11.208596 CBT Training : PASS
6076 01:26:11.211940 Write leveling : PASS
6077 01:26:11.215335 RX DQS gating : PASS
6078 01:26:11.215432 RX DQ/DQS(RDDQC) : PASS
6079 01:26:11.218084 TX DQ/DQS : PASS
6080 01:26:11.222087 RX DATLAT : PASS
6081 01:26:11.222183 RX DQ/DQS(Engine): PASS
6082 01:26:11.225167 TX OE : NO K
6083 01:26:11.225268 All Pass.
6084 01:26:11.225357
6085 01:26:11.228264 DramC Write-DBI off
6086 01:26:11.231837 PER_BANK_REFRESH: Hybrid Mode
6087 01:26:11.231935 TX_TRACKING: ON
6088 01:26:11.241535 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6089 01:26:11.244741 [FAST_K] Save calibration result to emmc
6090 01:26:11.248429 dramc_set_vcore_voltage set vcore to 650000
6091 01:26:11.251824 Read voltage for 400, 6
6092 01:26:11.251932 Vio18 = 0
6093 01:26:11.252025 Vcore = 650000
6094 01:26:11.254737 Vdram = 0
6095 01:26:11.254810 Vddq = 0
6096 01:26:11.254872 Vmddr = 0
6097 01:26:11.261515 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6098 01:26:11.264700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6099 01:26:11.268390 MEM_TYPE=3, freq_sel=20
6100 01:26:11.271485 sv_algorithm_assistance_LP4_800
6101 01:26:11.274984 ============ PULL DRAM RESETB DOWN ============
6102 01:26:11.278403 ========== PULL DRAM RESETB DOWN end =========
6103 01:26:11.284461 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6104 01:26:11.287833 ===================================
6105 01:26:11.287906 LPDDR4 DRAM CONFIGURATION
6106 01:26:11.291763 ===================================
6107 01:26:11.294454 EX_ROW_EN[0] = 0x0
6108 01:26:11.297826 EX_ROW_EN[1] = 0x0
6109 01:26:11.297922 LP4Y_EN = 0x0
6110 01:26:11.301275 WORK_FSP = 0x0
6111 01:26:11.301346 WL = 0x2
6112 01:26:11.304720 RL = 0x2
6113 01:26:11.304820 BL = 0x2
6114 01:26:11.308274 RPST = 0x0
6115 01:26:11.308344 RD_PRE = 0x0
6116 01:26:11.311014 WR_PRE = 0x1
6117 01:26:11.311083 WR_PST = 0x0
6118 01:26:11.314449 DBI_WR = 0x0
6119 01:26:11.314557 DBI_RD = 0x0
6120 01:26:11.318072 OTF = 0x1
6121 01:26:11.321558 ===================================
6122 01:26:11.324294 ===================================
6123 01:26:11.324400 ANA top config
6124 01:26:11.327874 ===================================
6125 01:26:11.331297 DLL_ASYNC_EN = 0
6126 01:26:11.334627 ALL_SLAVE_EN = 1
6127 01:26:11.337782 NEW_RANK_MODE = 1
6128 01:26:11.337859 DLL_IDLE_MODE = 1
6129 01:26:11.341106 LP45_APHY_COMB_EN = 1
6130 01:26:11.344371 TX_ODT_DIS = 1
6131 01:26:11.347550 NEW_8X_MODE = 1
6132 01:26:11.350701 ===================================
6133 01:26:11.354444 ===================================
6134 01:26:11.357241 data_rate = 800
6135 01:26:11.360656 CKR = 1
6136 01:26:11.360753 DQ_P2S_RATIO = 4
6137 01:26:11.364053 ===================================
6138 01:26:11.367890 CA_P2S_RATIO = 4
6139 01:26:11.370573 DQ_CA_OPEN = 0
6140 01:26:11.374047 DQ_SEMI_OPEN = 1
6141 01:26:11.377439 CA_SEMI_OPEN = 1
6142 01:26:11.381069 CA_FULL_RATE = 0
6143 01:26:11.381174 DQ_CKDIV4_EN = 0
6144 01:26:11.384424 CA_CKDIV4_EN = 1
6145 01:26:11.387555 CA_PREDIV_EN = 0
6146 01:26:11.390834 PH8_DLY = 0
6147 01:26:11.393917 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6148 01:26:11.396889 DQ_AAMCK_DIV = 0
6149 01:26:11.396988 CA_AAMCK_DIV = 0
6150 01:26:11.400480 CA_ADMCK_DIV = 4
6151 01:26:11.404013 DQ_TRACK_CA_EN = 0
6152 01:26:11.407615 CA_PICK = 800
6153 01:26:11.410461 CA_MCKIO = 400
6154 01:26:11.414034 MCKIO_SEMI = 400
6155 01:26:11.416883 PLL_FREQ = 3016
6156 01:26:11.417012 DQ_UI_PI_RATIO = 32
6157 01:26:11.420342 CA_UI_PI_RATIO = 32
6158 01:26:11.423728 ===================================
6159 01:26:11.427199 ===================================
6160 01:26:11.430561 memory_type:LPDDR4
6161 01:26:11.433509 GP_NUM : 10
6162 01:26:11.433607 SRAM_EN : 1
6163 01:26:11.437012 MD32_EN : 0
6164 01:26:11.440470 ===================================
6165 01:26:11.443052 [ANA_INIT] >>>>>>>>>>>>>>
6166 01:26:11.447048 <<<<<< [CONFIGURE PHASE]: ANA_TX
6167 01:26:11.449744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6168 01:26:11.453236 ===================================
6169 01:26:11.453338 data_rate = 800,PCW = 0X7400
6170 01:26:11.456651 ===================================
6171 01:26:11.460181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6172 01:26:11.467017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 01:26:11.476417 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6174 01:26:11.483300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6175 01:26:11.486632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6176 01:26:11.489954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6177 01:26:11.493096 [ANA_INIT] flow start
6178 01:26:11.493177 [ANA_INIT] PLL >>>>>>>>
6179 01:26:11.496631 [ANA_INIT] PLL <<<<<<<<
6180 01:26:11.500093 [ANA_INIT] MIDPI >>>>>>>>
6181 01:26:11.500171 [ANA_INIT] MIDPI <<<<<<<<
6182 01:26:11.502763 [ANA_INIT] DLL >>>>>>>>
6183 01:26:11.506789 [ANA_INIT] flow end
6184 01:26:11.510035 ============ LP4 DIFF to SE enter ============
6185 01:26:11.512830 ============ LP4 DIFF to SE exit ============
6186 01:26:11.516293 [ANA_INIT] <<<<<<<<<<<<<
6187 01:26:11.519746 [Flow] Enable top DCM control >>>>>
6188 01:26:11.522912 [Flow] Enable top DCM control <<<<<
6189 01:26:11.526105 Enable DLL master slave shuffle
6190 01:26:11.529934 ==============================================================
6191 01:26:11.532786 Gating Mode config
6192 01:26:11.539682 ==============================================================
6193 01:26:11.539772 Config description:
6194 01:26:11.549435 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6195 01:26:11.555633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6196 01:26:11.562595 SELPH_MODE 0: By rank 1: By Phase
6197 01:26:11.565543 ==============================================================
6198 01:26:11.568974 GAT_TRACK_EN = 0
6199 01:26:11.572506 RX_GATING_MODE = 2
6200 01:26:11.575337 RX_GATING_TRACK_MODE = 2
6201 01:26:11.578675 SELPH_MODE = 1
6202 01:26:11.582191 PICG_EARLY_EN = 1
6203 01:26:11.585774 VALID_LAT_VALUE = 1
6204 01:26:11.588970 ==============================================================
6205 01:26:11.592164 Enter into Gating configuration >>>>
6206 01:26:11.595334 Exit from Gating configuration <<<<
6207 01:26:11.598571 Enter into DVFS_PRE_config >>>>>
6208 01:26:11.611790 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6209 01:26:11.615193 Exit from DVFS_PRE_config <<<<<
6210 01:26:11.618534 Enter into PICG configuration >>>>
6211 01:26:11.621725 Exit from PICG configuration <<<<
6212 01:26:11.621823 [RX_INPUT] configuration >>>>>
6213 01:26:11.625052 [RX_INPUT] configuration <<<<<
6214 01:26:11.631771 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6215 01:26:11.635062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6216 01:26:11.641533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 01:26:11.647995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 01:26:11.655173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 01:26:11.661383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 01:26:11.664667 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6221 01:26:11.668286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6222 01:26:11.675102 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6223 01:26:11.677920 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6224 01:26:11.681243 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6225 01:26:11.684664 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6226 01:26:11.688265 ===================================
6227 01:26:11.691795 LPDDR4 DRAM CONFIGURATION
6228 01:26:11.694612 ===================================
6229 01:26:11.697931 EX_ROW_EN[0] = 0x0
6230 01:26:11.698006 EX_ROW_EN[1] = 0x0
6231 01:26:11.701266 LP4Y_EN = 0x0
6232 01:26:11.701370 WORK_FSP = 0x0
6233 01:26:11.704634 WL = 0x2
6234 01:26:11.704736 RL = 0x2
6235 01:26:11.708058 BL = 0x2
6236 01:26:11.708160 RPST = 0x0
6237 01:26:11.711542 RD_PRE = 0x0
6238 01:26:11.711610 WR_PRE = 0x1
6239 01:26:11.714331 WR_PST = 0x0
6240 01:26:11.714422 DBI_WR = 0x0
6241 01:26:11.717702 DBI_RD = 0x0
6242 01:26:11.721142 OTF = 0x1
6243 01:26:11.724676 ===================================
6244 01:26:11.727787 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6245 01:26:11.730935 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6246 01:26:11.734659 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6247 01:26:11.737644 ===================================
6248 01:26:11.741121 LPDDR4 DRAM CONFIGURATION
6249 01:26:11.744526 ===================================
6250 01:26:11.747876 EX_ROW_EN[0] = 0x10
6251 01:26:11.747981 EX_ROW_EN[1] = 0x0
6252 01:26:11.750968 LP4Y_EN = 0x0
6253 01:26:11.751048 WORK_FSP = 0x0
6254 01:26:11.754340 WL = 0x2
6255 01:26:11.754412 RL = 0x2
6256 01:26:11.757268 BL = 0x2
6257 01:26:11.757366 RPST = 0x0
6258 01:26:11.761089 RD_PRE = 0x0
6259 01:26:11.761184 WR_PRE = 0x1
6260 01:26:11.763967 WR_PST = 0x0
6261 01:26:11.764063 DBI_WR = 0x0
6262 01:26:11.767405 DBI_RD = 0x0
6263 01:26:11.770963 OTF = 0x1
6264 01:26:11.771039 ===================================
6265 01:26:11.777730 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6266 01:26:11.782329 nWR fixed to 30
6267 01:26:11.785719 [ModeRegInit_LP4] CH0 RK0
6268 01:26:11.785799 [ModeRegInit_LP4] CH0 RK1
6269 01:26:11.789169 [ModeRegInit_LP4] CH1 RK0
6270 01:26:11.792573 [ModeRegInit_LP4] CH1 RK1
6271 01:26:11.792647 match AC timing 19
6272 01:26:11.798931 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6273 01:26:11.802539 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6274 01:26:11.805857 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6275 01:26:11.812580 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6276 01:26:11.815331 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6277 01:26:11.815405 ==
6278 01:26:11.818855 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 01:26:11.822148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 01:26:11.822251 ==
6281 01:26:11.829132 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6282 01:26:11.835434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6283 01:26:11.838775 [CA 0] Center 36 (8~64) winsize 57
6284 01:26:11.842280 [CA 1] Center 36 (8~64) winsize 57
6285 01:26:11.845730 [CA 2] Center 36 (8~64) winsize 57
6286 01:26:11.848367 [CA 3] Center 36 (8~64) winsize 57
6287 01:26:11.851861 [CA 4] Center 36 (8~64) winsize 57
6288 01:26:11.851967 [CA 5] Center 36 (8~64) winsize 57
6289 01:26:11.855321
6290 01:26:11.858649 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6291 01:26:11.858721
6292 01:26:11.861884 [CATrainingPosCal] consider 1 rank data
6293 01:26:11.865010 u2DelayCellTimex100 = 270/100 ps
6294 01:26:11.868744 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 01:26:11.872073 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 01:26:11.875110 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 01:26:11.878711 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 01:26:11.881709 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 01:26:11.885395 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 01:26:11.885472
6301 01:26:11.888424 CA PerBit enable=1, Macro0, CA PI delay=36
6302 01:26:11.888505
6303 01:26:11.891965 [CBTSetCACLKResult] CA Dly = 36
6304 01:26:11.894981 CS Dly: 1 (0~32)
6305 01:26:11.895060 ==
6306 01:26:11.898530 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 01:26:11.901489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 01:26:11.901563 ==
6309 01:26:11.908466 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6310 01:26:11.915204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6311 01:26:11.918064 [CA 0] Center 36 (8~64) winsize 57
6312 01:26:11.918168 [CA 1] Center 36 (8~64) winsize 57
6313 01:26:11.921329 [CA 2] Center 36 (8~64) winsize 57
6314 01:26:11.924960 [CA 3] Center 36 (8~64) winsize 57
6315 01:26:11.928199 [CA 4] Center 36 (8~64) winsize 57
6316 01:26:11.931706 [CA 5] Center 36 (8~64) winsize 57
6317 01:26:11.931810
6318 01:26:11.934559 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6319 01:26:11.934638
6320 01:26:11.938087 [CATrainingPosCal] consider 2 rank data
6321 01:26:11.941630 u2DelayCellTimex100 = 270/100 ps
6322 01:26:11.945059 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 01:26:11.951228 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 01:26:11.954541 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 01:26:11.957974 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 01:26:11.961486 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 01:26:11.964836 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 01:26:11.964939
6329 01:26:11.968285 CA PerBit enable=1, Macro0, CA PI delay=36
6330 01:26:11.968385
6331 01:26:11.971632 [CBTSetCACLKResult] CA Dly = 36
6332 01:26:11.971735 CS Dly: 1 (0~32)
6333 01:26:11.974918
6334 01:26:11.977777 ----->DramcWriteLeveling(PI) begin...
6335 01:26:11.977886 ==
6336 01:26:11.981230 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 01:26:11.984708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 01:26:11.984784 ==
6339 01:26:11.988049 Write leveling (Byte 0): 40 => 8
6340 01:26:11.991348 Write leveling (Byte 1): 40 => 8
6341 01:26:11.994706 DramcWriteLeveling(PI) end<-----
6342 01:26:11.994781
6343 01:26:11.994844 ==
6344 01:26:11.997909 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 01:26:12.001158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 01:26:12.001257 ==
6347 01:26:12.004296 [Gating] SW mode calibration
6348 01:26:12.011216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6349 01:26:12.017518 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6350 01:26:12.020993 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 01:26:12.024604 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6352 01:26:12.030768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 01:26:12.034264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6354 01:26:12.037547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 01:26:12.044414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 01:26:12.047197 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 01:26:12.050720 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 01:26:12.057617 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 01:26:12.057730 Total UI for P1: 0, mck2ui 16
6360 01:26:12.061072 best dqsien dly found for B0: ( 0, 14, 24)
6361 01:26:12.064480 Total UI for P1: 0, mck2ui 16
6362 01:26:12.067326 best dqsien dly found for B1: ( 0, 14, 24)
6363 01:26:12.074019 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6364 01:26:12.077449 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6365 01:26:12.077547
6366 01:26:12.080656 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 01:26:12.084070 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6368 01:26:12.087655 [Gating] SW calibration Done
6369 01:26:12.087757 ==
6370 01:26:12.090484 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 01:26:12.093822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 01:26:12.093919 ==
6373 01:26:12.097141 RX Vref Scan: 0
6374 01:26:12.097239
6375 01:26:12.097339 RX Vref 0 -> 0, step: 1
6376 01:26:12.097428
6377 01:26:12.100619 RX Delay -410 -> 252, step: 16
6378 01:26:12.103997 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6379 01:26:12.110632 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6380 01:26:12.113987 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6381 01:26:12.117273 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6382 01:26:12.120890 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6383 01:26:12.126838 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6384 01:26:12.130048 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6385 01:26:12.133690 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6386 01:26:12.137084 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6387 01:26:12.143493 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6388 01:26:12.147330 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6389 01:26:12.150587 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6390 01:26:12.156812 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6391 01:26:12.160391 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6392 01:26:12.163731 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6393 01:26:12.167050 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6394 01:26:12.167157 ==
6395 01:26:12.169870 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 01:26:12.176654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 01:26:12.176762 ==
6398 01:26:12.176873 DQS Delay:
6399 01:26:12.180120 DQS0 = 27, DQS1 = 35
6400 01:26:12.180223 DQM Delay:
6401 01:26:12.183373 DQM0 = 11, DQM1 = 11
6402 01:26:12.183477 DQ Delay:
6403 01:26:12.186640 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6404 01:26:12.190177 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6405 01:26:12.190280 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6406 01:26:12.196948 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6407 01:26:12.197054
6408 01:26:12.197146
6409 01:26:12.197238 ==
6410 01:26:12.199735 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 01:26:12.203048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 01:26:12.203125 ==
6413 01:26:12.203188
6414 01:26:12.203250
6415 01:26:12.206468 TX Vref Scan disable
6416 01:26:12.206545 == TX Byte 0 ==
6417 01:26:12.209920 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6418 01:26:12.216558 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6419 01:26:12.216660 == TX Byte 1 ==
6420 01:26:12.219790 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 01:26:12.226275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 01:26:12.226394 ==
6423 01:26:12.229556 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 01:26:12.232934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 01:26:12.233050 ==
6426 01:26:12.233146
6427 01:26:12.233236
6428 01:26:12.236280 TX Vref Scan disable
6429 01:26:12.236368 == TX Byte 0 ==
6430 01:26:12.243201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 01:26:12.246019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 01:26:12.246124 == TX Byte 1 ==
6433 01:26:12.252677 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 01:26:12.255991 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 01:26:12.256092
6436 01:26:12.256187 [DATLAT]
6437 01:26:12.259358 Freq=400, CH0 RK0
6438 01:26:12.259432
6439 01:26:12.259493 DATLAT Default: 0xf
6440 01:26:12.262648 0, 0xFFFF, sum = 0
6441 01:26:12.262719 1, 0xFFFF, sum = 0
6442 01:26:12.265903 2, 0xFFFF, sum = 0
6443 01:26:12.265979 3, 0xFFFF, sum = 0
6444 01:26:12.269607 4, 0xFFFF, sum = 0
6445 01:26:12.269708 5, 0xFFFF, sum = 0
6446 01:26:12.272569 6, 0xFFFF, sum = 0
6447 01:26:12.272681 7, 0xFFFF, sum = 0
6448 01:26:12.275982 8, 0xFFFF, sum = 0
6449 01:26:12.276064 9, 0xFFFF, sum = 0
6450 01:26:12.279379 10, 0xFFFF, sum = 0
6451 01:26:12.279456 11, 0xFFFF, sum = 0
6452 01:26:12.282614 12, 0xFFFF, sum = 0
6453 01:26:12.282713 13, 0x0, sum = 1
6454 01:26:12.285993 14, 0x0, sum = 2
6455 01:26:12.286066 15, 0x0, sum = 3
6456 01:26:12.289522 16, 0x0, sum = 4
6457 01:26:12.289621 best_step = 14
6458 01:26:12.289708
6459 01:26:12.289797 ==
6460 01:26:12.292829 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 01:26:12.299547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 01:26:12.299646 ==
6463 01:26:12.299739 RX Vref Scan: 1
6464 01:26:12.299826
6465 01:26:12.303081 RX Vref 0 -> 0, step: 1
6466 01:26:12.303176
6467 01:26:12.305777 RX Delay -311 -> 252, step: 8
6468 01:26:12.305843
6469 01:26:12.309190 Set Vref, RX VrefLevel [Byte0]: 56
6470 01:26:12.312408 [Byte1]: 46
6471 01:26:12.312481
6472 01:26:12.316020 Final RX Vref Byte 0 = 56 to rank0
6473 01:26:12.319467 Final RX Vref Byte 1 = 46 to rank0
6474 01:26:12.322957 Final RX Vref Byte 0 = 56 to rank1
6475 01:26:12.326291 Final RX Vref Byte 1 = 46 to rank1==
6476 01:26:12.329566 Dram Type= 6, Freq= 0, CH_0, rank 0
6477 01:26:12.332802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 01:26:12.336058 ==
6479 01:26:12.336156 DQS Delay:
6480 01:26:12.336247 DQS0 = 28, DQS1 = 36
6481 01:26:12.339222 DQM Delay:
6482 01:26:12.339319 DQM0 = 10, DQM1 = 13
6483 01:26:12.342443 DQ Delay:
6484 01:26:12.342538 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6485 01:26:12.345960 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6486 01:26:12.349427 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6487 01:26:12.352270 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6488 01:26:12.352363
6489 01:26:12.352454
6490 01:26:12.362370 [DQSOSCAuto] RK0, (LSB)MR18= 0xc5b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6491 01:26:12.365794 CH0 RK0: MR19=C0C, MR18=C5B2
6492 01:26:12.372622 CH0_RK0: MR19=0xC0C, MR18=0xC5B2, DQSOSC=385, MR23=63, INC=398, DEC=265
6493 01:26:12.372730 ==
6494 01:26:12.375391 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 01:26:12.378698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 01:26:12.378804 ==
6497 01:26:12.381917 [Gating] SW mode calibration
6498 01:26:12.388793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6499 01:26:12.395386 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6500 01:26:12.398698 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 01:26:12.402172 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6502 01:26:12.409024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 01:26:12.411725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6504 01:26:12.415098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 01:26:12.421772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 01:26:12.425326 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 01:26:12.428887 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 01:26:12.431606 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 01:26:12.435102 Total UI for P1: 0, mck2ui 16
6510 01:26:12.438360 best dqsien dly found for B0: ( 0, 14, 24)
6511 01:26:12.441714 Total UI for P1: 0, mck2ui 16
6512 01:26:12.444995 best dqsien dly found for B1: ( 0, 14, 24)
6513 01:26:12.448167 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6514 01:26:12.455018 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6515 01:26:12.455138
6516 01:26:12.458427 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 01:26:12.461865 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6518 01:26:12.465244 [Gating] SW calibration Done
6519 01:26:12.465343 ==
6520 01:26:12.467890 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 01:26:12.471446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 01:26:12.471544 ==
6523 01:26:12.474976 RX Vref Scan: 0
6524 01:26:12.475062
6525 01:26:12.475144 RX Vref 0 -> 0, step: 1
6526 01:26:12.475226
6527 01:26:12.478629 RX Delay -410 -> 252, step: 16
6528 01:26:12.481289 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6529 01:26:12.488233 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6530 01:26:12.491739 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6531 01:26:12.494514 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6532 01:26:12.497904 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6533 01:26:12.504871 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6534 01:26:12.507995 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6535 01:26:12.511480 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6536 01:26:12.514483 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6537 01:26:12.521051 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6538 01:26:12.524253 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6539 01:26:12.528098 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6540 01:26:12.534353 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6541 01:26:12.537826 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6542 01:26:12.541417 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6543 01:26:12.544167 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6544 01:26:12.544248 ==
6545 01:26:12.547563 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 01:26:12.554313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 01:26:12.554398 ==
6548 01:26:12.554490 DQS Delay:
6549 01:26:12.557621 DQS0 = 19, DQS1 = 35
6550 01:26:12.557700 DQM Delay:
6551 01:26:12.560914 DQM0 = 5, DQM1 = 13
6552 01:26:12.561026 DQ Delay:
6553 01:26:12.564039 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6554 01:26:12.567432 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6555 01:26:12.567530 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6556 01:26:12.570549 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6557 01:26:12.574103
6558 01:26:12.574203
6559 01:26:12.574293 ==
6560 01:26:12.577484 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 01:26:12.580985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 01:26:12.581083 ==
6563 01:26:12.581173
6564 01:26:12.581262
6565 01:26:12.583780 TX Vref Scan disable
6566 01:26:12.583876 == TX Byte 0 ==
6567 01:26:12.587194 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6568 01:26:12.593743 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6569 01:26:12.593822 == TX Byte 1 ==
6570 01:26:12.597225 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6571 01:26:12.604213 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6572 01:26:12.604290 ==
6573 01:26:12.606994 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 01:26:12.610399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 01:26:12.610501 ==
6576 01:26:12.610595
6577 01:26:12.610682
6578 01:26:12.613833 TX Vref Scan disable
6579 01:26:12.613911 == TX Byte 0 ==
6580 01:26:12.617456 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6581 01:26:12.624001 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6582 01:26:12.624110 == TX Byte 1 ==
6583 01:26:12.627204 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6584 01:26:12.633807 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6585 01:26:12.633910
6586 01:26:12.634000 [DATLAT]
6587 01:26:12.634090 Freq=400, CH0 RK1
6588 01:26:12.637143
6589 01:26:12.637239 DATLAT Default: 0xe
6590 01:26:12.640501 0, 0xFFFF, sum = 0
6591 01:26:12.640578 1, 0xFFFF, sum = 0
6592 01:26:12.643516 2, 0xFFFF, sum = 0
6593 01:26:12.643620 3, 0xFFFF, sum = 0
6594 01:26:12.647156 4, 0xFFFF, sum = 0
6595 01:26:12.647278 5, 0xFFFF, sum = 0
6596 01:26:12.650370 6, 0xFFFF, sum = 0
6597 01:26:12.650441 7, 0xFFFF, sum = 0
6598 01:26:12.653675 8, 0xFFFF, sum = 0
6599 01:26:12.653752 9, 0xFFFF, sum = 0
6600 01:26:12.656957 10, 0xFFFF, sum = 0
6601 01:26:12.657058 11, 0xFFFF, sum = 0
6602 01:26:12.660627 12, 0xFFFF, sum = 0
6603 01:26:12.660731 13, 0x0, sum = 1
6604 01:26:12.663298 14, 0x0, sum = 2
6605 01:26:12.663409 15, 0x0, sum = 3
6606 01:26:12.666770 16, 0x0, sum = 4
6607 01:26:12.666844 best_step = 14
6608 01:26:12.666909
6609 01:26:12.666968 ==
6610 01:26:12.669902 Dram Type= 6, Freq= 0, CH_0, rank 1
6611 01:26:12.676672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6612 01:26:12.676756 ==
6613 01:26:12.676820 RX Vref Scan: 0
6614 01:26:12.676880
6615 01:26:12.679937 RX Vref 0 -> 0, step: 1
6616 01:26:12.680010
6617 01:26:12.683254 RX Delay -311 -> 252, step: 8
6618 01:26:12.690200 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6619 01:26:12.693095 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6620 01:26:12.696559 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6621 01:26:12.699880 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6622 01:26:12.706911 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6623 01:26:12.710212 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6624 01:26:12.713092 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6625 01:26:12.716444 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6626 01:26:12.723378 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6627 01:26:12.726786 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6628 01:26:12.729687 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6629 01:26:12.733033 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6630 01:26:12.739605 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6631 01:26:12.743085 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6632 01:26:12.746218 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6633 01:26:12.749811 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6634 01:26:12.753048 ==
6635 01:26:12.756138 Dram Type= 6, Freq= 0, CH_0, rank 1
6636 01:26:12.759513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 01:26:12.759612 ==
6638 01:26:12.759703 DQS Delay:
6639 01:26:12.762625 DQS0 = 24, DQS1 = 36
6640 01:26:12.762718 DQM Delay:
6641 01:26:12.766277 DQM0 = 8, DQM1 = 13
6642 01:26:12.766381 DQ Delay:
6643 01:26:12.769258 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6644 01:26:12.772760 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6645 01:26:12.776097 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6646 01:26:12.779384 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6647 01:26:12.779459
6648 01:26:12.779521
6649 01:26:12.786167 [DQSOSCAuto] RK1, (LSB)MR18= 0xb254, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6650 01:26:12.789778 CH0 RK1: MR19=C0C, MR18=B254
6651 01:26:12.795856 CH0_RK1: MR19=0xC0C, MR18=0xB254, DQSOSC=387, MR23=63, INC=394, DEC=262
6652 01:26:12.799536 [RxdqsGatingPostProcess] freq 400
6653 01:26:12.802677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6654 01:26:12.806082 best DQS0 dly(2T, 0.5T) = (0, 10)
6655 01:26:12.809520 best DQS1 dly(2T, 0.5T) = (0, 10)
6656 01:26:12.812852 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6657 01:26:12.815666 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6658 01:26:12.819056 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 01:26:12.822423 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 01:26:12.826005 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 01:26:12.829379 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 01:26:12.832985 Pre-setting of DQS Precalculation
6663 01:26:12.836303 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6664 01:26:12.836410 ==
6665 01:26:12.839191 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 01:26:12.845882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 01:26:12.845984 ==
6668 01:26:12.849423 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6669 01:26:12.856309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6670 01:26:12.859674 [CA 0] Center 36 (8~64) winsize 57
6671 01:26:12.862965 [CA 1] Center 36 (8~64) winsize 57
6672 01:26:12.865750 [CA 2] Center 36 (8~64) winsize 57
6673 01:26:12.869219 [CA 3] Center 36 (8~64) winsize 57
6674 01:26:12.872621 [CA 4] Center 36 (8~64) winsize 57
6675 01:26:12.875771 [CA 5] Center 36 (8~64) winsize 57
6676 01:26:12.875847
6677 01:26:12.879125 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6678 01:26:12.879212
6679 01:26:12.882347 [CATrainingPosCal] consider 1 rank data
6680 01:26:12.885685 u2DelayCellTimex100 = 270/100 ps
6681 01:26:12.888903 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 01:26:12.892617 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 01:26:12.895547 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 01:26:12.899123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 01:26:12.902038 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 01:26:12.909194 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 01:26:12.909296
6688 01:26:12.912127 CA PerBit enable=1, Macro0, CA PI delay=36
6689 01:26:12.912224
6690 01:26:12.915761 [CBTSetCACLKResult] CA Dly = 36
6691 01:26:12.915841 CS Dly: 1 (0~32)
6692 01:26:12.915910 ==
6693 01:26:12.918972 Dram Type= 6, Freq= 0, CH_1, rank 1
6694 01:26:12.922523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 01:26:12.922604 ==
6696 01:26:12.929289 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6697 01:26:12.935366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6698 01:26:12.938677 [CA 0] Center 36 (8~64) winsize 57
6699 01:26:12.942246 [CA 1] Center 36 (8~64) winsize 57
6700 01:26:12.945696 [CA 2] Center 36 (8~64) winsize 57
6701 01:26:12.949118 [CA 3] Center 36 (8~64) winsize 57
6702 01:26:12.951833 [CA 4] Center 36 (8~64) winsize 57
6703 01:26:12.955333 [CA 5] Center 36 (8~64) winsize 57
6704 01:26:12.955432
6705 01:26:12.958783 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6706 01:26:12.958866
6707 01:26:12.962008 [CATrainingPosCal] consider 2 rank data
6708 01:26:12.965249 u2DelayCellTimex100 = 270/100 ps
6709 01:26:12.968572 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 01:26:12.971996 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 01:26:12.975312 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 01:26:12.978841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 01:26:12.981492 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 01:26:12.984991 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 01:26:12.985091
6716 01:26:12.988564 CA PerBit enable=1, Macro0, CA PI delay=36
6717 01:26:12.991992
6718 01:26:12.992067 [CBTSetCACLKResult] CA Dly = 36
6719 01:26:12.994810 CS Dly: 1 (0~32)
6720 01:26:12.994882
6721 01:26:12.998087 ----->DramcWriteLeveling(PI) begin...
6722 01:26:12.998174 ==
6723 01:26:13.002001 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 01:26:13.005206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 01:26:13.005312 ==
6726 01:26:13.008188 Write leveling (Byte 0): 40 => 8
6727 01:26:13.011979 Write leveling (Byte 1): 40 => 8
6728 01:26:13.015383 DramcWriteLeveling(PI) end<-----
6729 01:26:13.015467
6730 01:26:13.015532 ==
6731 01:26:13.018646 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 01:26:13.021837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 01:26:13.021910 ==
6734 01:26:13.025012 [Gating] SW mode calibration
6735 01:26:13.031555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6736 01:26:13.038313 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6737 01:26:13.041228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 01:26:13.048350 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6739 01:26:13.051598 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 01:26:13.055077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6741 01:26:13.061318 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 01:26:13.064921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 01:26:13.068262 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 01:26:13.074675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 01:26:13.078096 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 01:26:13.081513 Total UI for P1: 0, mck2ui 16
6747 01:26:13.084955 best dqsien dly found for B0: ( 0, 14, 24)
6748 01:26:13.088215 Total UI for P1: 0, mck2ui 16
6749 01:26:13.091695 best dqsien dly found for B1: ( 0, 14, 24)
6750 01:26:13.094369 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6751 01:26:13.097975 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6752 01:26:13.098090
6753 01:26:13.101396 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 01:26:13.104873 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6755 01:26:13.107701 [Gating] SW calibration Done
6756 01:26:13.107815 ==
6757 01:26:13.111012 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 01:26:13.115017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 01:26:13.115121 ==
6760 01:26:13.118021 RX Vref Scan: 0
6761 01:26:13.118121
6762 01:26:13.120917 RX Vref 0 -> 0, step: 1
6763 01:26:13.121039
6764 01:26:13.121130 RX Delay -410 -> 252, step: 16
6765 01:26:13.127997 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6766 01:26:13.131302 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6767 01:26:13.134569 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6768 01:26:13.138338 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6769 01:26:13.144741 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6770 01:26:13.148097 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6771 01:26:13.151272 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6772 01:26:13.154506 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6773 01:26:13.161361 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6774 01:26:13.164822 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6775 01:26:13.167842 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6776 01:26:13.171314 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6777 01:26:13.178143 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6778 01:26:13.181278 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6779 01:26:13.184948 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6780 01:26:13.191140 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6781 01:26:13.191219 ==
6782 01:26:13.194372 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 01:26:13.197687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 01:26:13.197760 ==
6785 01:26:13.197824 DQS Delay:
6786 01:26:13.201185 DQS0 = 35, DQS1 = 35
6787 01:26:13.201286 DQM Delay:
6788 01:26:13.204573 DQM0 = 18, DQM1 = 12
6789 01:26:13.204678 DQ Delay:
6790 01:26:13.208102 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6791 01:26:13.210777 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6792 01:26:13.214191 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6793 01:26:13.217610 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6794 01:26:13.217716
6795 01:26:13.217807
6796 01:26:13.217904 ==
6797 01:26:13.221062 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 01:26:13.224470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 01:26:13.224569 ==
6800 01:26:13.224661
6801 01:26:13.224749
6802 01:26:13.227673 TX Vref Scan disable
6803 01:26:13.230875 == TX Byte 0 ==
6804 01:26:13.233955 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 01:26:13.237716 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 01:26:13.240868 == TX Byte 1 ==
6807 01:26:13.243989 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 01:26:13.247841 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 01:26:13.247945 ==
6810 01:26:13.250738 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 01:26:13.254014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 01:26:13.254125 ==
6813 01:26:13.254219
6814 01:26:13.257550
6815 01:26:13.257621 TX Vref Scan disable
6816 01:26:13.261094 == TX Byte 0 ==
6817 01:26:13.263924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 01:26:13.267260 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 01:26:13.270560 == TX Byte 1 ==
6820 01:26:13.274516 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 01:26:13.277389 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 01:26:13.277467
6823 01:26:13.277535 [DATLAT]
6824 01:26:13.280645 Freq=400, CH1 RK0
6825 01:26:13.280747
6826 01:26:13.280847 DATLAT Default: 0xf
6827 01:26:13.284238 0, 0xFFFF, sum = 0
6828 01:26:13.284337 1, 0xFFFF, sum = 0
6829 01:26:13.287451 2, 0xFFFF, sum = 0
6830 01:26:13.290532 3, 0xFFFF, sum = 0
6831 01:26:13.290619 4, 0xFFFF, sum = 0
6832 01:26:13.294157 5, 0xFFFF, sum = 0
6833 01:26:13.294258 6, 0xFFFF, sum = 0
6834 01:26:13.297249 7, 0xFFFF, sum = 0
6835 01:26:13.297327 8, 0xFFFF, sum = 0
6836 01:26:13.300518 9, 0xFFFF, sum = 0
6837 01:26:13.300629 10, 0xFFFF, sum = 0
6838 01:26:13.303994 11, 0xFFFF, sum = 0
6839 01:26:13.304099 12, 0xFFFF, sum = 0
6840 01:26:13.307545 13, 0x0, sum = 1
6841 01:26:13.307651 14, 0x0, sum = 2
6842 01:26:13.310257 15, 0x0, sum = 3
6843 01:26:13.310370 16, 0x0, sum = 4
6844 01:26:13.313717 best_step = 14
6845 01:26:13.313827
6846 01:26:13.313922 ==
6847 01:26:13.317268 Dram Type= 6, Freq= 0, CH_1, rank 0
6848 01:26:13.320773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6849 01:26:13.320876 ==
6850 01:26:13.320968 RX Vref Scan: 1
6851 01:26:13.324163
6852 01:26:13.324264 RX Vref 0 -> 0, step: 1
6853 01:26:13.324359
6854 01:26:13.327026 RX Delay -311 -> 252, step: 8
6855 01:26:13.327127
6856 01:26:13.330230 Set Vref, RX VrefLevel [Byte0]: 54
6857 01:26:13.334022 [Byte1]: 51
6858 01:26:13.337486
6859 01:26:13.337590 Final RX Vref Byte 0 = 54 to rank0
6860 01:26:13.341296 Final RX Vref Byte 1 = 51 to rank0
6861 01:26:13.344390 Final RX Vref Byte 0 = 54 to rank1
6862 01:26:13.347751 Final RX Vref Byte 1 = 51 to rank1==
6863 01:26:13.351169 Dram Type= 6, Freq= 0, CH_1, rank 0
6864 01:26:13.357701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 01:26:13.357809 ==
6866 01:26:13.357906 DQS Delay:
6867 01:26:13.361002 DQS0 = 32, DQS1 = 32
6868 01:26:13.361105 DQM Delay:
6869 01:26:13.361197 DQM0 = 14, DQM1 = 12
6870 01:26:13.364141 DQ Delay:
6871 01:26:13.367512 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6872 01:26:13.371099 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6873 01:26:13.371200 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6874 01:26:13.374472 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6875 01:26:13.377825
6876 01:26:13.377928
6877 01:26:13.384570 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6878 01:26:13.387294 CH1 RK0: MR19=C0C, MR18=8DC6
6879 01:26:13.394017 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6880 01:26:13.394131 ==
6881 01:26:13.397902 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 01:26:13.401060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 01:26:13.401166 ==
6884 01:26:13.404227 [Gating] SW mode calibration
6885 01:26:13.410993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6886 01:26:13.417625 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6887 01:26:13.421100 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 01:26:13.424078 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6889 01:26:13.430964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 01:26:13.434315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6891 01:26:13.437650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 01:26:13.441168 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 01:26:13.447864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 01:26:13.451113 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 01:26:13.454173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 01:26:13.457269 Total UI for P1: 0, mck2ui 16
6897 01:26:13.460633 best dqsien dly found for B0: ( 0, 14, 24)
6898 01:26:13.464399 Total UI for P1: 0, mck2ui 16
6899 01:26:13.467224 best dqsien dly found for B1: ( 0, 14, 24)
6900 01:26:13.470655 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6901 01:26:13.477035 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6902 01:26:13.477135
6903 01:26:13.481055 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 01:26:13.483869 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6905 01:26:13.487302 [Gating] SW calibration Done
6906 01:26:13.487376 ==
6907 01:26:13.490743 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 01:26:13.494116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 01:26:13.494218 ==
6910 01:26:13.494319 RX Vref Scan: 0
6911 01:26:13.497377
6912 01:26:13.497479 RX Vref 0 -> 0, step: 1
6913 01:26:13.497568
6914 01:26:13.500735 RX Delay -410 -> 252, step: 16
6915 01:26:13.504194 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6916 01:26:13.510540 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6917 01:26:13.513674 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6918 01:26:13.517562 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6919 01:26:13.520708 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6920 01:26:13.527506 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6921 01:26:13.530814 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6922 01:26:13.534144 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6923 01:26:13.537037 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6924 01:26:13.543809 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6925 01:26:13.547183 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6926 01:26:13.550802 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6927 01:26:13.553557 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6928 01:26:13.560241 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6929 01:26:13.563609 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6930 01:26:13.567390 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6931 01:26:13.567498 ==
6932 01:26:13.570618 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 01:26:13.573964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 01:26:13.577365 ==
6935 01:26:13.577463 DQS Delay:
6936 01:26:13.577557 DQS0 = 27, DQS1 = 27
6937 01:26:13.580283 DQM Delay:
6938 01:26:13.580388 DQM0 = 10, DQM1 = 8
6939 01:26:13.583495 DQ Delay:
6940 01:26:13.583594 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6941 01:26:13.587236 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6942 01:26:13.590534 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6943 01:26:13.593888 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6944 01:26:13.593992
6945 01:26:13.594083
6946 01:26:13.594175 ==
6947 01:26:13.597301 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 01:26:13.603956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 01:26:13.604064 ==
6950 01:26:13.604162
6951 01:26:13.604250
6952 01:26:13.604317 TX Vref Scan disable
6953 01:26:13.606680 == TX Byte 0 ==
6954 01:26:13.610628 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6955 01:26:13.613379 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6956 01:26:13.617044 == TX Byte 1 ==
6957 01:26:13.620371 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6958 01:26:13.623825 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6959 01:26:13.623924 ==
6960 01:26:13.627044 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 01:26:13.633642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 01:26:13.633750 ==
6963 01:26:13.633841
6964 01:26:13.633931
6965 01:26:13.634019 TX Vref Scan disable
6966 01:26:13.636999 == TX Byte 0 ==
6967 01:26:13.639973 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6968 01:26:13.643603 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6969 01:26:13.647089 == TX Byte 1 ==
6970 01:26:13.650382 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6971 01:26:13.653157 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6972 01:26:13.653233
6973 01:26:13.656708 [DATLAT]
6974 01:26:13.656783 Freq=400, CH1 RK1
6975 01:26:13.656848
6976 01:26:13.660196 DATLAT Default: 0xe
6977 01:26:13.660270 0, 0xFFFF, sum = 0
6978 01:26:13.663696 1, 0xFFFF, sum = 0
6979 01:26:13.663802 2, 0xFFFF, sum = 0
6980 01:26:13.666318 3, 0xFFFF, sum = 0
6981 01:26:13.666416 4, 0xFFFF, sum = 0
6982 01:26:13.669824 5, 0xFFFF, sum = 0
6983 01:26:13.669924 6, 0xFFFF, sum = 0
6984 01:26:13.673371 7, 0xFFFF, sum = 0
6985 01:26:13.673471 8, 0xFFFF, sum = 0
6986 01:26:13.676827 9, 0xFFFF, sum = 0
6987 01:26:13.680088 10, 0xFFFF, sum = 0
6988 01:26:13.680175 11, 0xFFFF, sum = 0
6989 01:26:13.683308 12, 0xFFFF, sum = 0
6990 01:26:13.683388 13, 0x0, sum = 1
6991 01:26:13.686786 14, 0x0, sum = 2
6992 01:26:13.686862 15, 0x0, sum = 3
6993 01:26:13.690181 16, 0x0, sum = 4
6994 01:26:13.690294 best_step = 14
6995 01:26:13.690369
6996 01:26:13.690432 ==
6997 01:26:13.692813 Dram Type= 6, Freq= 0, CH_1, rank 1
6998 01:26:13.696097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6999 01:26:13.696198 ==
7000 01:26:13.700026 RX Vref Scan: 0
7001 01:26:13.700138
7002 01:26:13.702727 RX Vref 0 -> 0, step: 1
7003 01:26:13.702827
7004 01:26:13.702927 RX Delay -295 -> 252, step: 8
7005 01:26:13.711919 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7006 01:26:13.715161 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
7007 01:26:13.718232 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7008 01:26:13.721473 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7009 01:26:13.728132 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7010 01:26:13.731618 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7011 01:26:13.734969 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7012 01:26:13.737967 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
7013 01:26:13.744966 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7014 01:26:13.748355 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7015 01:26:13.751696 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7016 01:26:13.754655 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7017 01:26:13.761531 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7018 01:26:13.764989 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7019 01:26:13.767742 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7020 01:26:13.774502 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7021 01:26:13.774577 ==
7022 01:26:13.777912 Dram Type= 6, Freq= 0, CH_1, rank 1
7023 01:26:13.781179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7024 01:26:13.781282 ==
7025 01:26:13.781405 DQS Delay:
7026 01:26:13.784519 DQS0 = 28, DQS1 = 36
7027 01:26:13.784589 DQM Delay:
7028 01:26:13.787877 DQM0 = 12, DQM1 = 15
7029 01:26:13.787944 DQ Delay:
7030 01:26:13.791304 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7031 01:26:13.794226 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7032 01:26:13.797518 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7033 01:26:13.801614 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7034 01:26:13.801713
7035 01:26:13.801800
7036 01:26:13.807625 [DQSOSCAuto] RK1, (LSB)MR18= 0xc253, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7037 01:26:13.811074 CH1 RK1: MR19=C0C, MR18=C253
7038 01:26:13.817659 CH1_RK1: MR19=0xC0C, MR18=0xC253, DQSOSC=385, MR23=63, INC=398, DEC=265
7039 01:26:13.820850 [RxdqsGatingPostProcess] freq 400
7040 01:26:13.827875 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7041 01:26:13.827974 best DQS0 dly(2T, 0.5T) = (0, 10)
7042 01:26:13.831161 best DQS1 dly(2T, 0.5T) = (0, 10)
7043 01:26:13.834211 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7044 01:26:13.837605 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7045 01:26:13.840749 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 01:26:13.844184 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 01:26:13.847674 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 01:26:13.851013 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 01:26:13.854575 Pre-setting of DQS Precalculation
7050 01:26:13.860880 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7051 01:26:13.867803 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7052 01:26:13.873843 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7053 01:26:13.873954
7054 01:26:13.874052
7055 01:26:13.877797 [Calibration Summary] 800 Mbps
7056 01:26:13.877898 CH 0, Rank 0
7057 01:26:13.880680 SW Impedance : PASS
7058 01:26:13.880783 DUTY Scan : NO K
7059 01:26:13.883997 ZQ Calibration : PASS
7060 01:26:13.887341 Jitter Meter : NO K
7061 01:26:13.887423 CBT Training : PASS
7062 01:26:13.890766 Write leveling : PASS
7063 01:26:13.893980 RX DQS gating : PASS
7064 01:26:13.894083 RX DQ/DQS(RDDQC) : PASS
7065 01:26:13.897323 TX DQ/DQS : PASS
7066 01:26:13.900735 RX DATLAT : PASS
7067 01:26:13.900840 RX DQ/DQS(Engine): PASS
7068 01:26:13.904279 TX OE : NO K
7069 01:26:13.904380 All Pass.
7070 01:26:13.904474
7071 01:26:13.907720 CH 0, Rank 1
7072 01:26:13.907793 SW Impedance : PASS
7073 01:26:13.910573 DUTY Scan : NO K
7074 01:26:13.914150 ZQ Calibration : PASS
7075 01:26:13.914254 Jitter Meter : NO K
7076 01:26:13.917724 CBT Training : PASS
7077 01:26:13.921028 Write leveling : NO K
7078 01:26:13.921137 RX DQS gating : PASS
7079 01:26:13.924426 RX DQ/DQS(RDDQC) : PASS
7080 01:26:13.924526 TX DQ/DQS : PASS
7081 01:26:13.927838 RX DATLAT : PASS
7082 01:26:13.931167 RX DQ/DQS(Engine): PASS
7083 01:26:13.931278 TX OE : NO K
7084 01:26:13.933851 All Pass.
7085 01:26:13.933952
7086 01:26:13.934053 CH 1, Rank 0
7087 01:26:13.937358 SW Impedance : PASS
7088 01:26:13.937440 DUTY Scan : NO K
7089 01:26:13.940686 ZQ Calibration : PASS
7090 01:26:13.944000 Jitter Meter : NO K
7091 01:26:13.944082 CBT Training : PASS
7092 01:26:13.947171 Write leveling : PASS
7093 01:26:13.950281 RX DQS gating : PASS
7094 01:26:13.950411 RX DQ/DQS(RDDQC) : PASS
7095 01:26:13.954144 TX DQ/DQS : PASS
7096 01:26:13.957362 RX DATLAT : PASS
7097 01:26:13.957476 RX DQ/DQS(Engine): PASS
7098 01:26:13.960192 TX OE : NO K
7099 01:26:13.960302 All Pass.
7100 01:26:13.960395
7101 01:26:13.963535 CH 1, Rank 1
7102 01:26:13.963634 SW Impedance : PASS
7103 01:26:13.966979 DUTY Scan : NO K
7104 01:26:13.970581 ZQ Calibration : PASS
7105 01:26:13.970681 Jitter Meter : NO K
7106 01:26:13.973930 CBT Training : PASS
7107 01:26:13.977173 Write leveling : NO K
7108 01:26:13.977310 RX DQS gating : PASS
7109 01:26:13.980204 RX DQ/DQS(RDDQC) : PASS
7110 01:26:13.983278 TX DQ/DQS : PASS
7111 01:26:13.983379 RX DATLAT : PASS
7112 01:26:13.986897 RX DQ/DQS(Engine): PASS
7113 01:26:13.986998 TX OE : NO K
7114 01:26:13.990236 All Pass.
7115 01:26:13.990340
7116 01:26:13.990430 DramC Write-DBI off
7117 01:26:13.993532 PER_BANK_REFRESH: Hybrid Mode
7118 01:26:13.996837 TX_TRACKING: ON
7119 01:26:14.003738 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7120 01:26:14.006531 [FAST_K] Save calibration result to emmc
7121 01:26:14.013325 dramc_set_vcore_voltage set vcore to 725000
7122 01:26:14.013431 Read voltage for 1600, 0
7123 01:26:14.017378 Vio18 = 0
7124 01:26:14.017479 Vcore = 725000
7125 01:26:14.017571 Vdram = 0
7126 01:26:14.017658 Vddq = 0
7127 01:26:14.020237 Vmddr = 0
7128 01:26:14.023682 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7129 01:26:14.029685 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7130 01:26:14.033143 MEM_TYPE=3, freq_sel=13
7131 01:26:14.033248 sv_algorithm_assistance_LP4_3733
7132 01:26:14.039952 ============ PULL DRAM RESETB DOWN ============
7133 01:26:14.043238 ========== PULL DRAM RESETB DOWN end =========
7134 01:26:14.046685 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7135 01:26:14.049968 ===================================
7136 01:26:14.053421 LPDDR4 DRAM CONFIGURATION
7137 01:26:14.056205 ===================================
7138 01:26:14.059948 EX_ROW_EN[0] = 0x0
7139 01:26:14.060055 EX_ROW_EN[1] = 0x0
7140 01:26:14.063043 LP4Y_EN = 0x0
7141 01:26:14.063152 WORK_FSP = 0x1
7142 01:26:14.066293 WL = 0x5
7143 01:26:14.066406 RL = 0x5
7144 01:26:14.069545 BL = 0x2
7145 01:26:14.069653 RPST = 0x0
7146 01:26:14.072942 RD_PRE = 0x0
7147 01:26:14.073044 WR_PRE = 0x1
7148 01:26:14.076332 WR_PST = 0x1
7149 01:26:14.076435 DBI_WR = 0x0
7150 01:26:14.079793 DBI_RD = 0x0
7151 01:26:14.082564 OTF = 0x1
7152 01:26:14.082644 ===================================
7153 01:26:14.086072 ===================================
7154 01:26:14.089489 ANA top config
7155 01:26:14.092836 ===================================
7156 01:26:14.096030 DLL_ASYNC_EN = 0
7157 01:26:14.096136 ALL_SLAVE_EN = 0
7158 01:26:14.099733 NEW_RANK_MODE = 1
7159 01:26:14.102538 DLL_IDLE_MODE = 1
7160 01:26:14.105954 LP45_APHY_COMB_EN = 1
7161 01:26:14.109464 TX_ODT_DIS = 0
7162 01:26:14.109569 NEW_8X_MODE = 1
7163 01:26:14.112984 ===================================
7164 01:26:14.116150 ===================================
7165 01:26:14.119539 data_rate = 3200
7166 01:26:14.122625 CKR = 1
7167 01:26:14.125947 DQ_P2S_RATIO = 8
7168 01:26:14.129459 ===================================
7169 01:26:14.132937 CA_P2S_RATIO = 8
7170 01:26:14.136346 DQ_CA_OPEN = 0
7171 01:26:14.136455 DQ_SEMI_OPEN = 0
7172 01:26:14.139105 CA_SEMI_OPEN = 0
7173 01:26:14.142421 CA_FULL_RATE = 0
7174 01:26:14.145899 DQ_CKDIV4_EN = 0
7175 01:26:14.149270 CA_CKDIV4_EN = 0
7176 01:26:14.152687 CA_PREDIV_EN = 0
7177 01:26:14.152793 PH8_DLY = 12
7178 01:26:14.155931 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7179 01:26:14.159186 DQ_AAMCK_DIV = 4
7180 01:26:14.162887 CA_AAMCK_DIV = 4
7181 01:26:14.165637 CA_ADMCK_DIV = 4
7182 01:26:14.168972 DQ_TRACK_CA_EN = 0
7183 01:26:14.169076 CA_PICK = 1600
7184 01:26:14.172201 CA_MCKIO = 1600
7185 01:26:14.175905 MCKIO_SEMI = 0
7186 01:26:14.179149 PLL_FREQ = 3068
7187 01:26:14.182529 DQ_UI_PI_RATIO = 32
7188 01:26:14.186181 CA_UI_PI_RATIO = 0
7189 01:26:14.189010 ===================================
7190 01:26:14.192211 ===================================
7191 01:26:14.192316 memory_type:LPDDR4
7192 01:26:14.195855 GP_NUM : 10
7193 01:26:14.199334 SRAM_EN : 1
7194 01:26:14.199410 MD32_EN : 0
7195 01:26:14.202015 ===================================
7196 01:26:14.205517 [ANA_INIT] >>>>>>>>>>>>>>
7197 01:26:14.208949 <<<<<< [CONFIGURE PHASE]: ANA_TX
7198 01:26:14.212256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7199 01:26:14.215770 ===================================
7200 01:26:14.219076 data_rate = 3200,PCW = 0X7600
7201 01:26:14.222202 ===================================
7202 01:26:14.225217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7203 01:26:14.228699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 01:26:14.235538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7205 01:26:14.238673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7206 01:26:14.245355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7207 01:26:14.248915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7208 01:26:14.249025 [ANA_INIT] flow start
7209 01:26:14.251869 [ANA_INIT] PLL >>>>>>>>
7210 01:26:14.255371 [ANA_INIT] PLL <<<<<<<<
7211 01:26:14.255503 [ANA_INIT] MIDPI >>>>>>>>
7212 01:26:14.258639 [ANA_INIT] MIDPI <<<<<<<<
7213 01:26:14.262102 [ANA_INIT] DLL >>>>>>>>
7214 01:26:14.262206 [ANA_INIT] DLL <<<<<<<<
7215 01:26:14.265462 [ANA_INIT] flow end
7216 01:26:14.268814 ============ LP4 DIFF to SE enter ============
7217 01:26:14.271679 ============ LP4 DIFF to SE exit ============
7218 01:26:14.275343 [ANA_INIT] <<<<<<<<<<<<<
7219 01:26:14.278699 [Flow] Enable top DCM control >>>>>
7220 01:26:14.282059 [Flow] Enable top DCM control <<<<<
7221 01:26:14.285231 Enable DLL master slave shuffle
7222 01:26:14.291537 ==============================================================
7223 01:26:14.291653 Gating Mode config
7224 01:26:14.298505 ==============================================================
7225 01:26:14.298585 Config description:
7226 01:26:14.308207 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7227 01:26:14.314929 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7228 01:26:14.322004 SELPH_MODE 0: By rank 1: By Phase
7229 01:26:14.324797 ==============================================================
7230 01:26:14.328137 GAT_TRACK_EN = 1
7231 01:26:14.331599 RX_GATING_MODE = 2
7232 01:26:14.335105 RX_GATING_TRACK_MODE = 2
7233 01:26:14.338038 SELPH_MODE = 1
7234 01:26:14.341304 PICG_EARLY_EN = 1
7235 01:26:14.344551 VALID_LAT_VALUE = 1
7236 01:26:14.351456 ==============================================================
7237 01:26:14.354746 Enter into Gating configuration >>>>
7238 01:26:14.358251 Exit from Gating configuration <<<<
7239 01:26:14.361037 Enter into DVFS_PRE_config >>>>>
7240 01:26:14.371176 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7241 01:26:14.374494 Exit from DVFS_PRE_config <<<<<
7242 01:26:14.377811 Enter into PICG configuration >>>>
7243 01:26:14.381234 Exit from PICG configuration <<<<
7244 01:26:14.384253 [RX_INPUT] configuration >>>>>
7245 01:26:14.384336 [RX_INPUT] configuration <<<<<
7246 01:26:14.391211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7247 01:26:14.398113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7248 01:26:14.401170 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 01:26:14.407516 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 01:26:14.414428 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 01:26:14.421278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 01:26:14.424091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7253 01:26:14.427483 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7254 01:26:14.434377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7255 01:26:14.437770 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7256 01:26:14.441073 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7257 01:26:14.447261 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7258 01:26:14.450764 ===================================
7259 01:26:14.450873 LPDDR4 DRAM CONFIGURATION
7260 01:26:14.454180 ===================================
7261 01:26:14.457790 EX_ROW_EN[0] = 0x0
7262 01:26:14.457872 EX_ROW_EN[1] = 0x0
7263 01:26:14.460518 LP4Y_EN = 0x0
7264 01:26:14.463923 WORK_FSP = 0x1
7265 01:26:14.464004 WL = 0x5
7266 01:26:14.467450 RL = 0x5
7267 01:26:14.467531 BL = 0x2
7268 01:26:14.470699 RPST = 0x0
7269 01:26:14.470798 RD_PRE = 0x0
7270 01:26:14.473827 WR_PRE = 0x1
7271 01:26:14.473909 WR_PST = 0x1
7272 01:26:14.477513 DBI_WR = 0x0
7273 01:26:14.477622 DBI_RD = 0x0
7274 01:26:14.481037 OTF = 0x1
7275 01:26:14.483685 ===================================
7276 01:26:14.486990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7277 01:26:14.490695 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7278 01:26:14.497265 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7279 01:26:14.500258 ===================================
7280 01:26:14.500361 LPDDR4 DRAM CONFIGURATION
7281 01:26:14.503683 ===================================
7282 01:26:14.507128 EX_ROW_EN[0] = 0x10
7283 01:26:14.507231 EX_ROW_EN[1] = 0x0
7284 01:26:14.510376 LP4Y_EN = 0x0
7285 01:26:14.510460 WORK_FSP = 0x1
7286 01:26:14.513527 WL = 0x5
7287 01:26:14.513611 RL = 0x5
7288 01:26:14.516968 BL = 0x2
7289 01:26:14.520482 RPST = 0x0
7290 01:26:14.520561 RD_PRE = 0x0
7291 01:26:14.524019 WR_PRE = 0x1
7292 01:26:14.524092 WR_PST = 0x1
7293 01:26:14.527495 DBI_WR = 0x0
7294 01:26:14.527580 DBI_RD = 0x0
7295 01:26:14.530285 OTF = 0x1
7296 01:26:14.533772 ===================================
7297 01:26:14.537116 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7298 01:26:14.540572 ==
7299 01:26:14.543541 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 01:26:14.546948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 01:26:14.547036 ==
7302 01:26:14.550427 [Duty_Offset_Calibration]
7303 01:26:14.550510 B0:2 B1:1 CA:1
7304 01:26:14.550575
7305 01:26:14.553894 [DutyScan_Calibration_Flow] k_type=0
7306 01:26:14.563493
7307 01:26:14.563576 ==CLK 0==
7308 01:26:14.566898 Final CLK duty delay cell = 0
7309 01:26:14.570372 [0] MAX Duty = 5156%(X100), DQS PI = 22
7310 01:26:14.573876 [0] MIN Duty = 4876%(X100), DQS PI = 48
7311 01:26:14.573975 [0] AVG Duty = 5016%(X100)
7312 01:26:14.576764
7313 01:26:14.580042 CH0 CLK Duty spec in!! Max-Min= 280%
7314 01:26:14.583211 [DutyScan_Calibration_Flow] ====Done====
7315 01:26:14.583287
7316 01:26:14.587058 [DutyScan_Calibration_Flow] k_type=1
7317 01:26:14.602583
7318 01:26:14.602686 ==DQS 0 ==
7319 01:26:14.605955 Final DQS duty delay cell = -4
7320 01:26:14.609258 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7321 01:26:14.612427 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7322 01:26:14.616315 [-4] AVG Duty = 4891%(X100)
7323 01:26:14.616398
7324 01:26:14.616463 ==DQS 1 ==
7325 01:26:14.619083 Final DQS duty delay cell = 0
7326 01:26:14.622502 [0] MAX Duty = 5187%(X100), DQS PI = 4
7327 01:26:14.625794 [0] MIN Duty = 5062%(X100), DQS PI = 34
7328 01:26:14.628904 [0] AVG Duty = 5124%(X100)
7329 01:26:14.629007
7330 01:26:14.632514 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7331 01:26:14.632598
7332 01:26:14.635929 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7333 01:26:14.638899 [DutyScan_Calibration_Flow] ====Done====
7334 01:26:14.638981
7335 01:26:14.642279 [DutyScan_Calibration_Flow] k_type=3
7336 01:26:14.659578
7337 01:26:14.659667 ==DQM 0 ==
7338 01:26:14.662784 Final DQM duty delay cell = 0
7339 01:26:14.666230 [0] MAX Duty = 5187%(X100), DQS PI = 26
7340 01:26:14.669016 [0] MIN Duty = 4907%(X100), DQS PI = 54
7341 01:26:14.672482 [0] AVG Duty = 5047%(X100)
7342 01:26:14.672564
7343 01:26:14.672630 ==DQM 1 ==
7344 01:26:14.675958 Final DQM duty delay cell = -4
7345 01:26:14.679269 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7346 01:26:14.682693 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7347 01:26:14.686122 [-4] AVG Duty = 4891%(X100)
7348 01:26:14.686205
7349 01:26:14.689056 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7350 01:26:14.689138
7351 01:26:14.692281 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7352 01:26:14.695688 [DutyScan_Calibration_Flow] ====Done====
7353 01:26:14.695769
7354 01:26:14.699243 [DutyScan_Calibration_Flow] k_type=2
7355 01:26:14.716921
7356 01:26:14.717008 ==DQ 0 ==
7357 01:26:14.720151 Final DQ duty delay cell = 0
7358 01:26:14.723897 [0] MAX Duty = 5062%(X100), DQS PI = 26
7359 01:26:14.727100 [0] MIN Duty = 4907%(X100), DQS PI = 0
7360 01:26:14.727181 [0] AVG Duty = 4984%(X100)
7361 01:26:14.730527
7362 01:26:14.730606 ==DQ 1 ==
7363 01:26:14.733350 Final DQ duty delay cell = 0
7364 01:26:14.736921 [0] MAX Duty = 5125%(X100), DQS PI = 6
7365 01:26:14.740302 [0] MIN Duty = 4907%(X100), DQS PI = 34
7366 01:26:14.740383 [0] AVG Duty = 5016%(X100)
7367 01:26:14.740446
7368 01:26:14.743233 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7369 01:26:14.747229
7370 01:26:14.750382 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7371 01:26:14.753614 [DutyScan_Calibration_Flow] ====Done====
7372 01:26:14.753693 ==
7373 01:26:14.756729 Dram Type= 6, Freq= 0, CH_1, rank 0
7374 01:26:14.759892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7375 01:26:14.760002 ==
7376 01:26:14.763665 [Duty_Offset_Calibration]
7377 01:26:14.763739 B0:1 B1:0 CA:1
7378 01:26:14.763800
7379 01:26:14.766735 [DutyScan_Calibration_Flow] k_type=0
7380 01:26:14.776491
7381 01:26:14.776602 ==CLK 0==
7382 01:26:14.779195 Final CLK duty delay cell = -4
7383 01:26:14.782767 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7384 01:26:14.786205 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7385 01:26:14.789587 [-4] AVG Duty = 4906%(X100)
7386 01:26:14.789689
7387 01:26:14.792319 CH1 CLK Duty spec in!! Max-Min= 125%
7388 01:26:14.795816 [DutyScan_Calibration_Flow] ====Done====
7389 01:26:14.795910
7390 01:26:14.799137 [DutyScan_Calibration_Flow] k_type=1
7391 01:26:14.816211
7392 01:26:14.816291 ==DQS 0 ==
7393 01:26:14.819934 Final DQS duty delay cell = 0
7394 01:26:14.822905 [0] MAX Duty = 5094%(X100), DQS PI = 16
7395 01:26:14.826597 [0] MIN Duty = 4844%(X100), DQS PI = 46
7396 01:26:14.829611 [0] AVG Duty = 4969%(X100)
7397 01:26:14.829690
7398 01:26:14.829753 ==DQS 1 ==
7399 01:26:14.832773 Final DQS duty delay cell = 0
7400 01:26:14.836046 [0] MAX Duty = 5249%(X100), DQS PI = 18
7401 01:26:14.839715 [0] MIN Duty = 4938%(X100), DQS PI = 8
7402 01:26:14.842872 [0] AVG Duty = 5093%(X100)
7403 01:26:14.842953
7404 01:26:14.846243 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7405 01:26:14.846401
7406 01:26:14.849852 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7407 01:26:14.852600 [DutyScan_Calibration_Flow] ====Done====
7408 01:26:14.852680
7409 01:26:14.855990 [DutyScan_Calibration_Flow] k_type=3
7410 01:26:14.873333
7411 01:26:14.873442 ==DQM 0 ==
7412 01:26:14.876816 Final DQM duty delay cell = 0
7413 01:26:14.879887 [0] MAX Duty = 5187%(X100), DQS PI = 8
7414 01:26:14.883037 [0] MIN Duty = 4969%(X100), DQS PI = 48
7415 01:26:14.883135 [0] AVG Duty = 5078%(X100)
7416 01:26:14.883232
7417 01:26:14.886951 ==DQM 1 ==
7418 01:26:14.889723 Final DQM duty delay cell = 0
7419 01:26:14.893103 [0] MAX Duty = 5093%(X100), DQS PI = 16
7420 01:26:14.896656 [0] MIN Duty = 4907%(X100), DQS PI = 34
7421 01:26:14.896727 [0] AVG Duty = 5000%(X100)
7422 01:26:14.900077
7423 01:26:14.903310 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7424 01:26:14.903389
7425 01:26:14.906699 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7426 01:26:14.909977 [DutyScan_Calibration_Flow] ====Done====
7427 01:26:14.910048
7428 01:26:14.912798 [DutyScan_Calibration_Flow] k_type=2
7429 01:26:14.929489
7430 01:26:14.929567 ==DQ 0 ==
7431 01:26:14.932633 Final DQ duty delay cell = -4
7432 01:26:14.935815 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7433 01:26:14.939047 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7434 01:26:14.942241 [-4] AVG Duty = 4953%(X100)
7435 01:26:14.942364
7436 01:26:14.942433 ==DQ 1 ==
7437 01:26:14.945877 Final DQ duty delay cell = 0
7438 01:26:14.948928 [0] MAX Duty = 5156%(X100), DQS PI = 18
7439 01:26:14.952482 [0] MIN Duty = 4938%(X100), DQS PI = 8
7440 01:26:14.952564 [0] AVG Duty = 5047%(X100)
7441 01:26:14.955939
7442 01:26:14.959313 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7443 01:26:14.959392
7444 01:26:14.962575 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7445 01:26:14.965926 [DutyScan_Calibration_Flow] ====Done====
7446 01:26:14.969455 nWR fixed to 30
7447 01:26:14.969526 [ModeRegInit_LP4] CH0 RK0
7448 01:26:14.972269 [ModeRegInit_LP4] CH0 RK1
7449 01:26:14.975630 [ModeRegInit_LP4] CH1 RK0
7450 01:26:14.978914 [ModeRegInit_LP4] CH1 RK1
7451 01:26:14.978983 match AC timing 5
7452 01:26:14.986017 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7453 01:26:14.989241 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7454 01:26:14.992529 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7455 01:26:14.998998 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7456 01:26:15.002523 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7457 01:26:15.002598 [MiockJmeterHQA]
7458 01:26:15.002667
7459 01:26:15.006111 [DramcMiockJmeter] u1RxGatingPI = 0
7460 01:26:15.008845 0 : 4252, 4027
7461 01:26:15.008957 4 : 4253, 4027
7462 01:26:15.012184 8 : 4365, 4140
7463 01:26:15.012266 12 : 4368, 4140
7464 01:26:15.012334 16 : 4257, 4029
7465 01:26:15.015661 20 : 4258, 4029
7466 01:26:15.015734 24 : 4252, 4027
7467 01:26:15.019007 28 : 4253, 4026
7468 01:26:15.019085 32 : 4252, 4027
7469 01:26:15.021830 36 : 4252, 4027
7470 01:26:15.021902 40 : 4363, 4137
7471 01:26:15.025290 44 : 4252, 4027
7472 01:26:15.025363 48 : 4255, 4029
7473 01:26:15.025430 52 : 4252, 4027
7474 01:26:15.028861 56 : 4252, 4027
7475 01:26:15.028934 60 : 4253, 4026
7476 01:26:15.032162 64 : 4360, 4138
7477 01:26:15.032238 68 : 4360, 4137
7478 01:26:15.035129 72 : 4250, 4027
7479 01:26:15.035211 76 : 4250, 4027
7480 01:26:15.039211 80 : 4250, 4026
7481 01:26:15.039284 84 : 4250, 4026
7482 01:26:15.039345 88 : 4250, 187
7483 01:26:15.042416 92 : 4250, 0
7484 01:26:15.042500 96 : 4361, 0
7485 01:26:15.042566 100 : 4250, 0
7486 01:26:15.045645 104 : 4250, 0
7487 01:26:15.045723 108 : 4250, 0
7488 01:26:15.049006 112 : 4250, 0
7489 01:26:15.049088 116 : 4250, 0
7490 01:26:15.049150 120 : 4363, 0
7491 01:26:15.051888 124 : 4250, 0
7492 01:26:15.051963 128 : 4250, 0
7493 01:26:15.055173 132 : 4253, 0
7494 01:26:15.055250 136 : 4360, 0
7495 01:26:15.055311 140 : 4361, 0
7496 01:26:15.058707 144 : 4250, 0
7497 01:26:15.058789 148 : 4255, 0
7498 01:26:15.061954 152 : 4250, 0
7499 01:26:15.062032 156 : 4253, 0
7500 01:26:15.062097 160 : 4252, 0
7501 01:26:15.065282 164 : 4250, 0
7502 01:26:15.065361 168 : 4253, 0
7503 01:26:15.065425 172 : 4360, 0
7504 01:26:15.068436 176 : 4250, 0
7505 01:26:15.068510 180 : 4250, 0
7506 01:26:15.071586 184 : 4250, 0
7507 01:26:15.071700 188 : 4361, 0
7508 01:26:15.071797 192 : 4360, 0
7509 01:26:15.075083 196 : 4250, 0
7510 01:26:15.075192 200 : 4250, 0
7511 01:26:15.078642 204 : 4250, 1002
7512 01:26:15.078717 208 : 4252, 3980
7513 01:26:15.081975 212 : 4361, 4137
7514 01:26:15.082047 216 : 4250, 4027
7515 01:26:15.085294 220 : 4361, 4138
7516 01:26:15.085406 224 : 4361, 4137
7517 01:26:15.085495 228 : 4250, 4027
7518 01:26:15.088374 232 : 4249, 4027
7519 01:26:15.088466 236 : 4360, 4137
7520 01:26:15.091664 240 : 4250, 4026
7521 01:26:15.091788 244 : 4250, 4027
7522 01:26:15.095161 248 : 4250, 4027
7523 01:26:15.095242 252 : 4250, 4027
7524 01:26:15.098366 256 : 4250, 4027
7525 01:26:15.098467 260 : 4250, 4027
7526 01:26:15.101657 264 : 4360, 4138
7527 01:26:15.101770 268 : 4250, 4027
7528 01:26:15.104861 272 : 4250, 4026
7529 01:26:15.104932 276 : 4361, 4137
7530 01:26:15.108623 280 : 4250, 4027
7531 01:26:15.108693 284 : 4252, 4027
7532 01:26:15.111991 288 : 4360, 4138
7533 01:26:15.112086 292 : 4250, 4026
7534 01:26:15.112152 296 : 4250, 4027
7535 01:26:15.115238 300 : 4250, 4027
7536 01:26:15.115326 304 : 4255, 4031
7537 01:26:15.117961 308 : 4250, 3998
7538 01:26:15.118032 312 : 4252, 1985
7539 01:26:15.118100
7540 01:26:15.121534 MIOCK jitter meter ch=0
7541 01:26:15.121604
7542 01:26:15.124951 1T = (312-88) = 224 dly cells
7543 01:26:15.131298 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7544 01:26:15.131419 ==
7545 01:26:15.134845 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 01:26:15.138243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 01:26:15.138374 ==
7548 01:26:15.145154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 01:26:15.147878 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 01:26:15.151265 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 01:26:15.158164 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 01:26:15.166698 [CA 0] Center 42 (12~73) winsize 62
7553 01:26:15.170446 [CA 1] Center 42 (12~73) winsize 62
7554 01:26:15.173878 [CA 2] Center 38 (8~68) winsize 61
7555 01:26:15.176538 [CA 3] Center 37 (8~67) winsize 60
7556 01:26:15.180140 [CA 4] Center 36 (6~66) winsize 61
7557 01:26:15.183375 [CA 5] Center 35 (6~64) winsize 59
7558 01:26:15.183445
7559 01:26:15.186985 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7560 01:26:15.187059
7561 01:26:15.190195 [CATrainingPosCal] consider 1 rank data
7562 01:26:15.193512 u2DelayCellTimex100 = 290/100 ps
7563 01:26:15.196796 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7564 01:26:15.203454 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7565 01:26:15.206994 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7566 01:26:15.210462 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7567 01:26:15.213296 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7568 01:26:15.216655 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7569 01:26:15.216754
7570 01:26:15.220723 CA PerBit enable=1, Macro0, CA PI delay=35
7571 01:26:15.220796
7572 01:26:15.223605 [CBTSetCACLKResult] CA Dly = 35
7573 01:26:15.226470 CS Dly: 9 (0~40)
7574 01:26:15.230004 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 01:26:15.233533 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 01:26:15.233627 ==
7577 01:26:15.236508 Dram Type= 6, Freq= 0, CH_0, rank 1
7578 01:26:15.240184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 01:26:15.240284 ==
7580 01:26:15.246517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 01:26:15.250075 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 01:26:15.256851 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 01:26:15.259499 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 01:26:15.270267 [CA 0] Center 42 (12~73) winsize 62
7585 01:26:15.273643 [CA 1] Center 42 (12~73) winsize 62
7586 01:26:15.276436 [CA 2] Center 38 (8~68) winsize 61
7587 01:26:15.280099 [CA 3] Center 37 (8~67) winsize 60
7588 01:26:15.283568 [CA 4] Center 36 (6~66) winsize 61
7589 01:26:15.286995 [CA 5] Center 35 (5~65) winsize 61
7590 01:26:15.287064
7591 01:26:15.289701 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7592 01:26:15.289799
7593 01:26:15.292958 [CATrainingPosCal] consider 2 rank data
7594 01:26:15.296281 u2DelayCellTimex100 = 290/100 ps
7595 01:26:15.299628 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7596 01:26:15.306605 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7597 01:26:15.309515 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7598 01:26:15.312703 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7599 01:26:15.316238 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7600 01:26:15.319752 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7601 01:26:15.319845
7602 01:26:15.323063 CA PerBit enable=1, Macro0, CA PI delay=35
7603 01:26:15.323155
7604 01:26:15.326520 [CBTSetCACLKResult] CA Dly = 35
7605 01:26:15.329839 CS Dly: 10 (0~42)
7606 01:26:15.333280 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 01:26:15.336513 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 01:26:15.336608
7609 01:26:15.339747 ----->DramcWriteLeveling(PI) begin...
7610 01:26:15.339820 ==
7611 01:26:15.342867 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 01:26:15.349443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 01:26:15.349579 ==
7614 01:26:15.352706 Write leveling (Byte 0): 35 => 35
7615 01:26:15.352802 Write leveling (Byte 1): 29 => 29
7616 01:26:15.356500 DramcWriteLeveling(PI) end<-----
7617 01:26:15.356595
7618 01:26:15.359689 ==
7619 01:26:15.359757 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 01:26:15.366754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 01:26:15.366832 ==
7622 01:26:15.370028 [Gating] SW mode calibration
7623 01:26:15.376021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7624 01:26:15.379841 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7625 01:26:15.385941 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 01:26:15.389635 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7627 01:26:15.393018 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 01:26:15.399757 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7629 01:26:15.403234 1 4 16 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
7630 01:26:15.406128 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7631 01:26:15.412899 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7632 01:26:15.416080 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7633 01:26:15.419422 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7634 01:26:15.426170 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7635 01:26:15.429444 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7636 01:26:15.432822 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7637 01:26:15.439355 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7638 01:26:15.442805 1 5 20 | B1->B0 | 2929 2828 | 1 0 | (1 0) (0 0)
7639 01:26:15.446245 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7640 01:26:15.449101 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7641 01:26:15.455810 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7642 01:26:15.459401 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 01:26:15.462850 1 6 8 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7644 01:26:15.469362 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7645 01:26:15.472700 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7646 01:26:15.475841 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7647 01:26:15.482832 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7648 01:26:15.485875 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 01:26:15.488932 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 01:26:15.495510 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 01:26:15.499094 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 01:26:15.502470 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7653 01:26:15.508805 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7654 01:26:15.512122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7655 01:26:15.515605 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 01:26:15.522108 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 01:26:15.525406 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 01:26:15.528806 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 01:26:15.535753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 01:26:15.539043 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 01:26:15.541729 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 01:26:15.548581 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 01:26:15.552078 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 01:26:15.555545 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 01:26:15.561923 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 01:26:15.565318 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 01:26:15.568764 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 01:26:15.574947 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7669 01:26:15.578266 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7670 01:26:15.581754 Total UI for P1: 0, mck2ui 16
7671 01:26:15.585276 best dqsien dly found for B0: ( 1, 9, 12)
7672 01:26:15.588818 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 01:26:15.592182 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 01:26:15.595479 Total UI for P1: 0, mck2ui 16
7675 01:26:15.598881 best dqsien dly found for B1: ( 1, 9, 18)
7676 01:26:15.604795 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7677 01:26:15.608414 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7678 01:26:15.608495
7679 01:26:15.611736 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7680 01:26:15.614897 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7681 01:26:15.618057 [Gating] SW calibration Done
7682 01:26:15.618133 ==
7683 01:26:15.621826 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 01:26:15.624880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 01:26:15.624957 ==
7686 01:26:15.628516 RX Vref Scan: 0
7687 01:26:15.628595
7688 01:26:15.628659 RX Vref 0 -> 0, step: 1
7689 01:26:15.628716
7690 01:26:15.631527 RX Delay 0 -> 252, step: 8
7691 01:26:15.634540 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7692 01:26:15.641673 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7693 01:26:15.644797 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7694 01:26:15.648033 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7695 01:26:15.651654 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7696 01:26:15.654722 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7697 01:26:15.658227 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7698 01:26:15.665110 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7699 01:26:15.667924 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7700 01:26:15.671360 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7701 01:26:15.674727 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7702 01:26:15.677995 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7703 01:26:15.684668 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7704 01:26:15.687967 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7705 01:26:15.691465 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7706 01:26:15.694923 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7707 01:26:15.695000 ==
7708 01:26:15.698411 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 01:26:15.704698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 01:26:15.704775 ==
7711 01:26:15.704838 DQS Delay:
7712 01:26:15.707968 DQS0 = 0, DQS1 = 0
7713 01:26:15.708042 DQM Delay:
7714 01:26:15.708102 DQM0 = 136, DQM1 = 129
7715 01:26:15.711611 DQ Delay:
7716 01:26:15.715152 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7717 01:26:15.717845 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7718 01:26:15.721459 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7719 01:26:15.724776 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7720 01:26:15.724848
7721 01:26:15.724915
7722 01:26:15.724976 ==
7723 01:26:15.728461 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 01:26:15.731126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 01:26:15.734445 ==
7726 01:26:15.734522
7727 01:26:15.734586
7728 01:26:15.734652 TX Vref Scan disable
7729 01:26:15.737972 == TX Byte 0 ==
7730 01:26:15.741447 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7731 01:26:15.744894 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7732 01:26:15.748037 == TX Byte 1 ==
7733 01:26:15.751246 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7734 01:26:15.754656 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7735 01:26:15.757967 ==
7736 01:26:15.761219 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 01:26:15.764303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 01:26:15.764379 ==
7739 01:26:15.777415
7740 01:26:15.780590 TX Vref early break, caculate TX vref
7741 01:26:15.783915 TX Vref=16, minBit 7, minWin=22, winSum=379
7742 01:26:15.787201 TX Vref=18, minBit 4, minWin=23, winSum=387
7743 01:26:15.790356 TX Vref=20, minBit 0, minWin=24, winSum=399
7744 01:26:15.793621 TX Vref=22, minBit 7, minWin=24, winSum=406
7745 01:26:15.797020 TX Vref=24, minBit 0, minWin=25, winSum=416
7746 01:26:15.804075 TX Vref=26, minBit 2, minWin=24, winSum=423
7747 01:26:15.807372 TX Vref=28, minBit 2, minWin=25, winSum=422
7748 01:26:15.810203 TX Vref=30, minBit 1, minWin=24, winSum=418
7749 01:26:15.813448 TX Vref=32, minBit 7, minWin=23, winSum=402
7750 01:26:15.816994 TX Vref=34, minBit 0, minWin=23, winSum=390
7751 01:26:15.823830 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 28
7752 01:26:15.823911
7753 01:26:15.827289 Final TX Range 0 Vref 28
7754 01:26:15.827369
7755 01:26:15.827432 ==
7756 01:26:15.830056 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 01:26:15.833546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 01:26:15.833624 ==
7759 01:26:15.833686
7760 01:26:15.833744
7761 01:26:15.836964 TX Vref Scan disable
7762 01:26:15.843775 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7763 01:26:15.843848 == TX Byte 0 ==
7764 01:26:15.847323 u2DelayCellOfst[0]=10 cells (3 PI)
7765 01:26:15.850138 u2DelayCellOfst[1]=13 cells (4 PI)
7766 01:26:15.853451 u2DelayCellOfst[2]=10 cells (3 PI)
7767 01:26:15.856734 u2DelayCellOfst[3]=10 cells (3 PI)
7768 01:26:15.860142 u2DelayCellOfst[4]=10 cells (3 PI)
7769 01:26:15.864030 u2DelayCellOfst[5]=0 cells (0 PI)
7770 01:26:15.866839 u2DelayCellOfst[6]=16 cells (5 PI)
7771 01:26:15.866910 u2DelayCellOfst[7]=16 cells (5 PI)
7772 01:26:15.873907 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7773 01:26:15.876623 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7774 01:26:15.876693 == TX Byte 1 ==
7775 01:26:15.880042 u2DelayCellOfst[8]=0 cells (0 PI)
7776 01:26:15.883532 u2DelayCellOfst[9]=0 cells (0 PI)
7777 01:26:15.887023 u2DelayCellOfst[10]=10 cells (3 PI)
7778 01:26:15.890158 u2DelayCellOfst[11]=3 cells (1 PI)
7779 01:26:15.893256 u2DelayCellOfst[12]=13 cells (4 PI)
7780 01:26:15.896511 u2DelayCellOfst[13]=10 cells (3 PI)
7781 01:26:15.900270 u2DelayCellOfst[14]=13 cells (4 PI)
7782 01:26:15.903221 u2DelayCellOfst[15]=13 cells (4 PI)
7783 01:26:15.906707 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7784 01:26:15.913165 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7785 01:26:15.913274 DramC Write-DBI on
7786 01:26:15.913396 ==
7787 01:26:15.916380 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 01:26:15.919962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 01:26:15.923210 ==
7790 01:26:15.923282
7791 01:26:15.923343
7792 01:26:15.923400 TX Vref Scan disable
7793 01:26:15.927000 == TX Byte 0 ==
7794 01:26:15.929991 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7795 01:26:15.933462 == TX Byte 1 ==
7796 01:26:15.936861 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7797 01:26:15.936932 DramC Write-DBI off
7798 01:26:15.940359
7799 01:26:15.940439 [DATLAT]
7800 01:26:15.940503 Freq=1600, CH0 RK0
7801 01:26:15.940595
7802 01:26:15.943487 DATLAT Default: 0xf
7803 01:26:15.943567 0, 0xFFFF, sum = 0
7804 01:26:15.947039 1, 0xFFFF, sum = 0
7805 01:26:15.947124 2, 0xFFFF, sum = 0
7806 01:26:15.950558 3, 0xFFFF, sum = 0
7807 01:26:15.950633 4, 0xFFFF, sum = 0
7808 01:26:15.953734 5, 0xFFFF, sum = 0
7809 01:26:15.957169 6, 0xFFFF, sum = 0
7810 01:26:15.957244 7, 0xFFFF, sum = 0
7811 01:26:15.960001 8, 0xFFFF, sum = 0
7812 01:26:15.960072 9, 0xFFFF, sum = 0
7813 01:26:15.963412 10, 0xFFFF, sum = 0
7814 01:26:15.963492 11, 0xFFFF, sum = 0
7815 01:26:15.966799 12, 0xFFFF, sum = 0
7816 01:26:15.966873 13, 0xFFFF, sum = 0
7817 01:26:15.969913 14, 0x0, sum = 1
7818 01:26:15.969987 15, 0x0, sum = 2
7819 01:26:15.973251 16, 0x0, sum = 3
7820 01:26:15.973331 17, 0x0, sum = 4
7821 01:26:15.976797 best_step = 15
7822 01:26:15.976865
7823 01:26:15.976925 ==
7824 01:26:15.980180 Dram Type= 6, Freq= 0, CH_0, rank 0
7825 01:26:15.983504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7826 01:26:15.983590 ==
7827 01:26:15.983670 RX Vref Scan: 1
7828 01:26:15.983742
7829 01:26:15.986836 Set Vref Range= 24 -> 127
7830 01:26:15.986939
7831 01:26:15.990228 RX Vref 24 -> 127, step: 1
7832 01:26:15.990366
7833 01:26:15.993729 RX Delay 19 -> 252, step: 4
7834 01:26:15.993809
7835 01:26:15.996683 Set Vref, RX VrefLevel [Byte0]: 24
7836 01:26:16.000008 [Byte1]: 24
7837 01:26:16.000088
7838 01:26:16.003281 Set Vref, RX VrefLevel [Byte0]: 25
7839 01:26:16.006656 [Byte1]: 25
7840 01:26:16.006795
7841 01:26:16.009947 Set Vref, RX VrefLevel [Byte0]: 26
7842 01:26:16.013375 [Byte1]: 26
7843 01:26:16.016752
7844 01:26:16.016832 Set Vref, RX VrefLevel [Byte0]: 27
7845 01:26:16.020223 [Byte1]: 27
7846 01:26:16.024346
7847 01:26:16.024425 Set Vref, RX VrefLevel [Byte0]: 28
7848 01:26:16.028117 [Byte1]: 28
7849 01:26:16.031893
7850 01:26:16.032013 Set Vref, RX VrefLevel [Byte0]: 29
7851 01:26:16.035256 [Byte1]: 29
7852 01:26:16.039584
7853 01:26:16.039663 Set Vref, RX VrefLevel [Byte0]: 30
7854 01:26:16.043035 [Byte1]: 30
7855 01:26:16.046969
7856 01:26:16.047043 Set Vref, RX VrefLevel [Byte0]: 31
7857 01:26:16.050231 [Byte1]: 31
7858 01:26:16.054769
7859 01:26:16.054853 Set Vref, RX VrefLevel [Byte0]: 32
7860 01:26:16.057813 [Byte1]: 32
7861 01:26:16.062680
7862 01:26:16.062761 Set Vref, RX VrefLevel [Byte0]: 33
7863 01:26:16.065512 [Byte1]: 33
7864 01:26:16.070421
7865 01:26:16.070501 Set Vref, RX VrefLevel [Byte0]: 34
7866 01:26:16.073074 [Byte1]: 34
7867 01:26:16.077881
7868 01:26:16.077961 Set Vref, RX VrefLevel [Byte0]: 35
7869 01:26:16.081079 [Byte1]: 35
7870 01:26:16.085291
7871 01:26:16.085370 Set Vref, RX VrefLevel [Byte0]: 36
7872 01:26:16.088648 [Byte1]: 36
7873 01:26:16.092576
7874 01:26:16.092656 Set Vref, RX VrefLevel [Byte0]: 37
7875 01:26:16.096082 [Byte1]: 37
7876 01:26:16.100200
7877 01:26:16.100279 Set Vref, RX VrefLevel [Byte0]: 38
7878 01:26:16.103678 [Byte1]: 38
7879 01:26:16.107756
7880 01:26:16.107836 Set Vref, RX VrefLevel [Byte0]: 39
7881 01:26:16.111104 [Byte1]: 39
7882 01:26:16.115723
7883 01:26:16.115803 Set Vref, RX VrefLevel [Byte0]: 40
7884 01:26:16.118560 [Byte1]: 40
7885 01:26:16.123235
7886 01:26:16.123314 Set Vref, RX VrefLevel [Byte0]: 41
7887 01:26:16.126743 [Byte1]: 41
7888 01:26:16.130913
7889 01:26:16.130992 Set Vref, RX VrefLevel [Byte0]: 42
7890 01:26:16.133721 [Byte1]: 42
7891 01:26:16.138481
7892 01:26:16.138560 Set Vref, RX VrefLevel [Byte0]: 43
7893 01:26:16.141810 [Byte1]: 43
7894 01:26:16.146081
7895 01:26:16.146160 Set Vref, RX VrefLevel [Byte0]: 44
7896 01:26:16.148790 [Byte1]: 44
7897 01:26:16.153408
7898 01:26:16.153487 Set Vref, RX VrefLevel [Byte0]: 45
7899 01:26:16.156791 [Byte1]: 45
7900 01:26:16.160751
7901 01:26:16.160830 Set Vref, RX VrefLevel [Byte0]: 46
7902 01:26:16.163990 [Byte1]: 46
7903 01:26:16.168703
7904 01:26:16.168783 Set Vref, RX VrefLevel [Byte0]: 47
7905 01:26:16.171600 [Byte1]: 47
7906 01:26:16.175911
7907 01:26:16.175994 Set Vref, RX VrefLevel [Byte0]: 48
7908 01:26:16.178979 [Byte1]: 48
7909 01:26:16.183699
7910 01:26:16.183774 Set Vref, RX VrefLevel [Byte0]: 49
7911 01:26:16.186463 [Byte1]: 49
7912 01:26:16.191175
7913 01:26:16.191251 Set Vref, RX VrefLevel [Byte0]: 50
7914 01:26:16.194351 [Byte1]: 50
7915 01:26:16.198611
7916 01:26:16.198707 Set Vref, RX VrefLevel [Byte0]: 51
7917 01:26:16.201753 [Byte1]: 51
7918 01:26:16.206406
7919 01:26:16.206488 Set Vref, RX VrefLevel [Byte0]: 52
7920 01:26:16.209958 [Byte1]: 52
7921 01:26:16.213976
7922 01:26:16.214055 Set Vref, RX VrefLevel [Byte0]: 53
7923 01:26:16.217472 [Byte1]: 53
7924 01:26:16.221432
7925 01:26:16.221512 Set Vref, RX VrefLevel [Byte0]: 54
7926 01:26:16.225088 [Byte1]: 54
7927 01:26:16.228972
7928 01:26:16.229051 Set Vref, RX VrefLevel [Byte0]: 55
7929 01:26:16.232581 [Byte1]: 55
7930 01:26:16.236733
7931 01:26:16.236810 Set Vref, RX VrefLevel [Byte0]: 56
7932 01:26:16.240038 [Byte1]: 56
7933 01:26:16.244196
7934 01:26:16.244275 Set Vref, RX VrefLevel [Byte0]: 57
7935 01:26:16.247648 [Byte1]: 57
7936 01:26:16.251951
7937 01:26:16.252025 Set Vref, RX VrefLevel [Byte0]: 58
7938 01:26:16.254726 [Byte1]: 58
7939 01:26:16.259450
7940 01:26:16.259534 Set Vref, RX VrefLevel [Byte0]: 59
7941 01:26:16.262808 [Byte1]: 59
7942 01:26:16.267073
7943 01:26:16.267154 Set Vref, RX VrefLevel [Byte0]: 60
7944 01:26:16.270553 [Byte1]: 60
7945 01:26:16.274437
7946 01:26:16.274519 Set Vref, RX VrefLevel [Byte0]: 61
7947 01:26:16.277653 [Byte1]: 61
7948 01:26:16.282119
7949 01:26:16.282193 Set Vref, RX VrefLevel [Byte0]: 62
7950 01:26:16.285273 [Byte1]: 62
7951 01:26:16.289181
7952 01:26:16.289254 Set Vref, RX VrefLevel [Byte0]: 63
7953 01:26:16.293006 [Byte1]: 63
7954 01:26:16.296753
7955 01:26:16.296832 Set Vref, RX VrefLevel [Byte0]: 64
7956 01:26:16.300353 [Byte1]: 64
7957 01:26:16.304446
7958 01:26:16.304521 Set Vref, RX VrefLevel [Byte0]: 65
7959 01:26:16.307645 [Byte1]: 65
7960 01:26:16.312484
7961 01:26:16.312607 Set Vref, RX VrefLevel [Byte0]: 66
7962 01:26:16.315425 [Byte1]: 66
7963 01:26:16.319781
7964 01:26:16.319855 Set Vref, RX VrefLevel [Byte0]: 67
7965 01:26:16.322855 [Byte1]: 67
7966 01:26:16.327506
7967 01:26:16.327588 Set Vref, RX VrefLevel [Byte0]: 68
7968 01:26:16.330551 [Byte1]: 68
7969 01:26:16.335005
7970 01:26:16.335083 Set Vref, RX VrefLevel [Byte0]: 69
7971 01:26:16.338308 [Byte1]: 69
7972 01:26:16.342614
7973 01:26:16.342693 Set Vref, RX VrefLevel [Byte0]: 70
7974 01:26:16.345826 [Byte1]: 70
7975 01:26:16.350033
7976 01:26:16.350109 Set Vref, RX VrefLevel [Byte0]: 71
7977 01:26:16.353498 [Byte1]: 71
7978 01:26:16.357603
7979 01:26:16.357685 Set Vref, RX VrefLevel [Byte0]: 72
7980 01:26:16.360931 [Byte1]: 72
7981 01:26:16.365130
7982 01:26:16.365209 Set Vref, RX VrefLevel [Byte0]: 73
7983 01:26:16.368771 [Byte1]: 73
7984 01:26:16.372819
7985 01:26:16.372890 Set Vref, RX VrefLevel [Byte0]: 74
7986 01:26:16.376354 [Byte1]: 74
7987 01:26:16.380534
7988 01:26:16.380619 Set Vref, RX VrefLevel [Byte0]: 75
7989 01:26:16.383882 [Byte1]: 75
7990 01:26:16.387809
7991 01:26:16.387885 Final RX Vref Byte 0 = 53 to rank0
7992 01:26:16.391049 Final RX Vref Byte 1 = 59 to rank0
7993 01:26:16.394224 Final RX Vref Byte 0 = 53 to rank1
7994 01:26:16.397657 Final RX Vref Byte 1 = 59 to rank1==
7995 01:26:16.401175 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 01:26:16.408103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 01:26:16.408191 ==
7998 01:26:16.408256 DQS Delay:
7999 01:26:16.411476 DQS0 = 0, DQS1 = 0
8000 01:26:16.411556 DQM Delay:
8001 01:26:16.411619 DQM0 = 133, DQM1 = 127
8002 01:26:16.414278 DQ Delay:
8003 01:26:16.417638 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
8004 01:26:16.420998 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
8005 01:26:16.424033 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8006 01:26:16.427578 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
8007 01:26:16.427682
8008 01:26:16.427772
8009 01:26:16.427860
8010 01:26:16.430725 [DramC_TX_OE_Calibration] TA2
8011 01:26:16.434289 Original DQ_B0 (3 6) =30, OEN = 27
8012 01:26:16.437232 Original DQ_B1 (3 6) =30, OEN = 27
8013 01:26:16.440687 24, 0x0, End_B0=24 End_B1=24
8014 01:26:16.440764 25, 0x0, End_B0=25 End_B1=25
8015 01:26:16.444094 26, 0x0, End_B0=26 End_B1=26
8016 01:26:16.447302 27, 0x0, End_B0=27 End_B1=27
8017 01:26:16.450811 28, 0x0, End_B0=28 End_B1=28
8018 01:26:16.454200 29, 0x0, End_B0=29 End_B1=29
8019 01:26:16.454321 30, 0x0, End_B0=30 End_B1=30
8020 01:26:16.457132 31, 0x4141, End_B0=30 End_B1=30
8021 01:26:16.460711 Byte0 end_step=30 best_step=27
8022 01:26:16.463854 Byte1 end_step=30 best_step=27
8023 01:26:16.467142 Byte0 TX OE(2T, 0.5T) = (3, 3)
8024 01:26:16.470530 Byte1 TX OE(2T, 0.5T) = (3, 3)
8025 01:26:16.470610
8026 01:26:16.470672
8027 01:26:16.477490 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8028 01:26:16.480382 CH0 RK0: MR19=303, MR18=231F
8029 01:26:16.487209 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
8030 01:26:16.487289
8031 01:26:16.490755 ----->DramcWriteLeveling(PI) begin...
8032 01:26:16.490835 ==
8033 01:26:16.494046 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 01:26:16.497542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 01:26:16.497624 ==
8036 01:26:16.500283 Write leveling (Byte 0): 34 => 34
8037 01:26:16.503525 Write leveling (Byte 1): 26 => 26
8038 01:26:16.506814 DramcWriteLeveling(PI) end<-----
8039 01:26:16.506892
8040 01:26:16.506965 ==
8041 01:26:16.510277 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 01:26:16.513954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 01:26:16.514027 ==
8044 01:26:16.516673 [Gating] SW mode calibration
8045 01:26:16.523639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8046 01:26:16.530580 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8047 01:26:16.533891 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8048 01:26:16.540011 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 01:26:16.543386 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 01:26:16.546730 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8051 01:26:16.553548 1 4 16 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (0 0)
8052 01:26:16.556766 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8053 01:26:16.559920 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8054 01:26:16.566645 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8055 01:26:16.570196 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8056 01:26:16.573333 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8057 01:26:16.580030 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 01:26:16.583427 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
8059 01:26:16.586332 1 5 16 | B1->B0 | 3030 2928 | 0 1 | (1 1) (0 0)
8060 01:26:16.593391 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8061 01:26:16.596811 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8062 01:26:16.600106 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8063 01:26:16.602835 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8064 01:26:16.610211 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8065 01:26:16.613287 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8066 01:26:16.616617 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8067 01:26:16.622798 1 6 16 | B1->B0 | 3d3d 4645 | 0 1 | (0 0) (0 0)
8068 01:26:16.626206 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
8069 01:26:16.629669 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8070 01:26:16.636596 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 01:26:16.639486 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 01:26:16.642917 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 01:26:16.649741 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 01:26:16.653083 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8075 01:26:16.656271 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8076 01:26:16.663280 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 01:26:16.666107 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 01:26:16.669402 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 01:26:16.676051 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 01:26:16.679759 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 01:26:16.682621 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 01:26:16.689505 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 01:26:16.692673 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 01:26:16.695844 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 01:26:16.702734 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 01:26:16.706180 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 01:26:16.709365 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 01:26:16.716016 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 01:26:16.719189 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 01:26:16.722377 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8091 01:26:16.729182 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8092 01:26:16.729263 Total UI for P1: 0, mck2ui 16
8093 01:26:16.736027 best dqsien dly found for B0: ( 1, 9, 12)
8094 01:26:16.738734 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 01:26:16.742225 Total UI for P1: 0, mck2ui 16
8096 01:26:16.745633 best dqsien dly found for B1: ( 1, 9, 14)
8097 01:26:16.748930 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8098 01:26:16.752331 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8099 01:26:16.752419
8100 01:26:16.755778 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8101 01:26:16.758972 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8102 01:26:16.762452 [Gating] SW calibration Done
8103 01:26:16.762548 ==
8104 01:26:16.765889 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 01:26:16.769265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 01:26:16.772169 ==
8107 01:26:16.772248 RX Vref Scan: 0
8108 01:26:16.772311
8109 01:26:16.775626 RX Vref 0 -> 0, step: 1
8110 01:26:16.775709
8111 01:26:16.775774 RX Delay 0 -> 252, step: 8
8112 01:26:16.782335 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8113 01:26:16.785414 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8114 01:26:16.788769 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8115 01:26:16.792094 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8116 01:26:16.795588 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8117 01:26:16.802395 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8118 01:26:16.805284 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8119 01:26:16.808739 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8120 01:26:16.812328 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8121 01:26:16.815635 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8122 01:26:16.822565 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8123 01:26:16.825452 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8124 01:26:16.828515 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8125 01:26:16.831882 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8126 01:26:16.838535 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8127 01:26:16.841875 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8128 01:26:16.841955 ==
8129 01:26:16.845520 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 01:26:16.848711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 01:26:16.848802 ==
8132 01:26:16.848868 DQS Delay:
8133 01:26:16.852392 DQS0 = 0, DQS1 = 0
8134 01:26:16.852473 DQM Delay:
8135 01:26:16.855630 DQM0 = 136, DQM1 = 128
8136 01:26:16.855710 DQ Delay:
8137 01:26:16.858836 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8138 01:26:16.862230 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8139 01:26:16.865632 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8140 01:26:16.868860 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8141 01:26:16.872201
8142 01:26:16.872280
8143 01:26:16.872342 ==
8144 01:26:16.874964 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 01:26:16.878563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 01:26:16.878644 ==
8147 01:26:16.878708
8148 01:26:16.878766
8149 01:26:16.882063 TX Vref Scan disable
8150 01:26:16.882143 == TX Byte 0 ==
8151 01:26:16.888237 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8152 01:26:16.891535 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8153 01:26:16.891615 == TX Byte 1 ==
8154 01:26:16.898891 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8155 01:26:16.901636 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8156 01:26:16.901717 ==
8157 01:26:16.904978 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 01:26:16.908553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 01:26:16.908634 ==
8160 01:26:16.924293
8161 01:26:16.927855 TX Vref early break, caculate TX vref
8162 01:26:16.930586 TX Vref=16, minBit 1, minWin=23, winSum=387
8163 01:26:16.934135 TX Vref=18, minBit 1, minWin=22, winSum=394
8164 01:26:16.937635 TX Vref=20, minBit 0, minWin=24, winSum=403
8165 01:26:16.940535 TX Vref=22, minBit 1, minWin=24, winSum=413
8166 01:26:16.943856 TX Vref=24, minBit 1, minWin=24, winSum=418
8167 01:26:16.950665 TX Vref=26, minBit 1, minWin=25, winSum=425
8168 01:26:16.953869 TX Vref=28, minBit 7, minWin=25, winSum=426
8169 01:26:16.957642 TX Vref=30, minBit 1, minWin=25, winSum=418
8170 01:26:16.960537 TX Vref=32, minBit 0, minWin=25, winSum=411
8171 01:26:16.963598 TX Vref=34, minBit 4, minWin=24, winSum=405
8172 01:26:16.967097 TX Vref=36, minBit 0, minWin=23, winSum=392
8173 01:26:16.973664 [TxChooseVref] Worse bit 7, Min win 25, Win sum 426, Final Vref 28
8174 01:26:16.973745
8175 01:26:16.977608 Final TX Range 0 Vref 28
8176 01:26:16.977687
8177 01:26:16.977749 ==
8178 01:26:16.980427 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 01:26:16.983557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 01:26:16.983637 ==
8181 01:26:16.983700
8182 01:26:16.986918
8183 01:26:16.986998 TX Vref Scan disable
8184 01:26:16.993765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8185 01:26:16.993845 == TX Byte 0 ==
8186 01:26:16.997146 u2DelayCellOfst[0]=13 cells (4 PI)
8187 01:26:17.000234 u2DelayCellOfst[1]=16 cells (5 PI)
8188 01:26:17.003499 u2DelayCellOfst[2]=10 cells (3 PI)
8189 01:26:17.006828 u2DelayCellOfst[3]=10 cells (3 PI)
8190 01:26:17.010167 u2DelayCellOfst[4]=6 cells (2 PI)
8191 01:26:17.013780 u2DelayCellOfst[5]=0 cells (0 PI)
8192 01:26:17.017135 u2DelayCellOfst[6]=16 cells (5 PI)
8193 01:26:17.020683 u2DelayCellOfst[7]=16 cells (5 PI)
8194 01:26:17.023474 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8195 01:26:17.026892 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8196 01:26:17.030335 == TX Byte 1 ==
8197 01:26:17.033646 u2DelayCellOfst[8]=0 cells (0 PI)
8198 01:26:17.037099 u2DelayCellOfst[9]=0 cells (0 PI)
8199 01:26:17.040532 u2DelayCellOfst[10]=3 cells (1 PI)
8200 01:26:17.040613 u2DelayCellOfst[11]=0 cells (0 PI)
8201 01:26:17.043321 u2DelayCellOfst[12]=10 cells (3 PI)
8202 01:26:17.046734 u2DelayCellOfst[13]=6 cells (2 PI)
8203 01:26:17.050189 u2DelayCellOfst[14]=13 cells (4 PI)
8204 01:26:17.053654 u2DelayCellOfst[15]=10 cells (3 PI)
8205 01:26:17.059793 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8206 01:26:17.063063 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8207 01:26:17.063145 DramC Write-DBI on
8208 01:26:17.063240 ==
8209 01:26:17.066501 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 01:26:17.073216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 01:26:17.073293 ==
8212 01:26:17.073356
8213 01:26:17.073415
8214 01:26:17.073472 TX Vref Scan disable
8215 01:26:17.077305 == TX Byte 0 ==
8216 01:26:17.080574 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8217 01:26:17.084254 == TX Byte 1 ==
8218 01:26:17.087695 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8219 01:26:17.090755 DramC Write-DBI off
8220 01:26:17.090924
8221 01:26:17.091016 [DATLAT]
8222 01:26:17.091103 Freq=1600, CH0 RK1
8223 01:26:17.091188
8224 01:26:17.094168 DATLAT Default: 0xf
8225 01:26:17.094248 0, 0xFFFF, sum = 0
8226 01:26:17.097539 1, 0xFFFF, sum = 0
8227 01:26:17.100922 2, 0xFFFF, sum = 0
8228 01:26:17.101003 3, 0xFFFF, sum = 0
8229 01:26:17.104344 4, 0xFFFF, sum = 0
8230 01:26:17.104425 5, 0xFFFF, sum = 0
8231 01:26:17.107522 6, 0xFFFF, sum = 0
8232 01:26:17.107603 7, 0xFFFF, sum = 0
8233 01:26:17.110540 8, 0xFFFF, sum = 0
8234 01:26:17.110621 9, 0xFFFF, sum = 0
8235 01:26:17.113954 10, 0xFFFF, sum = 0
8236 01:26:17.114035 11, 0xFFFF, sum = 0
8237 01:26:17.117479 12, 0xFFFF, sum = 0
8238 01:26:17.117561 13, 0xFFFF, sum = 0
8239 01:26:17.120681 14, 0x0, sum = 1
8240 01:26:17.120763 15, 0x0, sum = 2
8241 01:26:17.123961 16, 0x0, sum = 3
8242 01:26:17.124042 17, 0x0, sum = 4
8243 01:26:17.127129 best_step = 15
8244 01:26:17.127199
8245 01:26:17.127297 ==
8246 01:26:17.130963 Dram Type= 6, Freq= 0, CH_0, rank 1
8247 01:26:17.134088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8248 01:26:17.134194 ==
8249 01:26:17.137578 RX Vref Scan: 0
8250 01:26:17.137658
8251 01:26:17.137722 RX Vref 0 -> 0, step: 1
8252 01:26:17.137781
8253 01:26:17.140321 RX Delay 19 -> 252, step: 4
8254 01:26:17.143944 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8255 01:26:17.150208 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8256 01:26:17.153742 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8257 01:26:17.157077 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8258 01:26:17.160280 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8259 01:26:17.163829 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8260 01:26:17.170195 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8261 01:26:17.173524 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8262 01:26:17.176956 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8263 01:26:17.180494 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8264 01:26:17.183943 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8265 01:26:17.190637 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8266 01:26:17.193788 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8267 01:26:17.196846 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8268 01:26:17.200250 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8269 01:26:17.206466 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8270 01:26:17.206547 ==
8271 01:26:17.209976 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 01:26:17.213328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 01:26:17.213409 ==
8274 01:26:17.213473 DQS Delay:
8275 01:26:17.216842 DQS0 = 0, DQS1 = 0
8276 01:26:17.216922 DQM Delay:
8277 01:26:17.219887 DQM0 = 133, DQM1 = 127
8278 01:26:17.219987 DQ Delay:
8279 01:26:17.223347 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =132
8280 01:26:17.226728 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =142
8281 01:26:17.230054 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8282 01:26:17.233228 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8283 01:26:17.233308
8284 01:26:17.233402
8285 01:26:17.233476
8286 01:26:17.236539 [DramC_TX_OE_Calibration] TA2
8287 01:26:17.239766 Original DQ_B0 (3 6) =30, OEN = 27
8288 01:26:17.243255 Original DQ_B1 (3 6) =30, OEN = 27
8289 01:26:17.246629 24, 0x0, End_B0=24 End_B1=24
8290 01:26:17.250002 25, 0x0, End_B0=25 End_B1=25
8291 01:26:17.250111 26, 0x0, End_B0=26 End_B1=26
8292 01:26:17.252946 27, 0x0, End_B0=27 End_B1=27
8293 01:26:17.256253 28, 0x0, End_B0=28 End_B1=28
8294 01:26:17.259792 29, 0x0, End_B0=29 End_B1=29
8295 01:26:17.262960 30, 0x0, End_B0=30 End_B1=30
8296 01:26:17.263042 31, 0x4141, End_B0=30 End_B1=30
8297 01:26:17.266722 Byte0 end_step=30 best_step=27
8298 01:26:17.269968 Byte1 end_step=30 best_step=27
8299 01:26:17.273317 Byte0 TX OE(2T, 0.5T) = (3, 3)
8300 01:26:17.276551 Byte1 TX OE(2T, 0.5T) = (3, 3)
8301 01:26:17.276631
8302 01:26:17.276694
8303 01:26:17.282757 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8304 01:26:17.286363 CH0 RK1: MR19=303, MR18=1E07
8305 01:26:17.292927 CH0_RK1: MR19=0x303, MR18=0x1E07, DQSOSC=394, MR23=63, INC=23, DEC=15
8306 01:26:17.296555 [RxdqsGatingPostProcess] freq 1600
8307 01:26:17.303000 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8308 01:26:17.303081 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 01:26:17.306257 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 01:26:17.309737 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 01:26:17.312765 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 01:26:17.316035 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 01:26:17.319477 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 01:26:17.322862 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 01:26:17.326309 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 01:26:17.329714 Pre-setting of DQS Precalculation
8317 01:26:17.332706 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8318 01:26:17.332787 ==
8319 01:26:17.336117 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 01:26:17.343028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 01:26:17.343109 ==
8322 01:26:17.345802 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8323 01:26:17.352483 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8324 01:26:17.355887 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8325 01:26:17.362736 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8326 01:26:17.370607 [CA 0] Center 42 (12~72) winsize 61
8327 01:26:17.373732 [CA 1] Center 42 (12~72) winsize 61
8328 01:26:17.377191 [CA 2] Center 38 (9~68) winsize 60
8329 01:26:17.380148 [CA 3] Center 38 (9~67) winsize 59
8330 01:26:17.383773 [CA 4] Center 38 (9~68) winsize 60
8331 01:26:17.387216 [CA 5] Center 37 (8~67) winsize 60
8332 01:26:17.387318
8333 01:26:17.390548 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8334 01:26:17.390687
8335 01:26:17.393560 [CATrainingPosCal] consider 1 rank data
8336 01:26:17.397135 u2DelayCellTimex100 = 290/100 ps
8337 01:26:17.400534 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8338 01:26:17.407068 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8339 01:26:17.410390 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8340 01:26:17.413664 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8341 01:26:17.417198 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8342 01:26:17.420861 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8343 01:26:17.420972
8344 01:26:17.423756 CA PerBit enable=1, Macro0, CA PI delay=37
8345 01:26:17.423836
8346 01:26:17.427140 [CBTSetCACLKResult] CA Dly = 37
8347 01:26:17.427244 CS Dly: 10 (0~41)
8348 01:26:17.434032 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8349 01:26:17.436972 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8350 01:26:17.437083 ==
8351 01:26:17.440328 Dram Type= 6, Freq= 0, CH_1, rank 1
8352 01:26:17.443950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 01:26:17.444054 ==
8354 01:26:17.450215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8355 01:26:17.453662 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8356 01:26:17.460646 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8357 01:26:17.463233 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8358 01:26:17.473554 [CA 0] Center 41 (12~71) winsize 60
8359 01:26:17.477168 [CA 1] Center 42 (12~72) winsize 61
8360 01:26:17.480579 [CA 2] Center 38 (9~68) winsize 60
8361 01:26:17.483311 [CA 3] Center 38 (8~68) winsize 61
8362 01:26:17.486674 [CA 4] Center 38 (8~69) winsize 62
8363 01:26:17.490078 [CA 5] Center 37 (8~66) winsize 59
8364 01:26:17.490194
8365 01:26:17.493562 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8366 01:26:17.493665
8367 01:26:17.497020 [CATrainingPosCal] consider 2 rank data
8368 01:26:17.500413 u2DelayCellTimex100 = 290/100 ps
8369 01:26:17.503636 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8370 01:26:17.510224 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8371 01:26:17.513608 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8372 01:26:17.516661 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8373 01:26:17.520079 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8374 01:26:17.523469 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8375 01:26:17.523573
8376 01:26:17.526439 CA PerBit enable=1, Macro0, CA PI delay=37
8377 01:26:17.526519
8378 01:26:17.529686 [CBTSetCACLKResult] CA Dly = 37
8379 01:26:17.533468 CS Dly: 12 (0~45)
8380 01:26:17.536547 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8381 01:26:17.540013 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8382 01:26:17.540114
8383 01:26:17.543765 ----->DramcWriteLeveling(PI) begin...
8384 01:26:17.543869 ==
8385 01:26:17.546626 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 01:26:17.550071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 01:26:17.553186 ==
8388 01:26:17.553285 Write leveling (Byte 0): 26 => 26
8389 01:26:17.556554 Write leveling (Byte 1): 28 => 28
8390 01:26:17.560007 DramcWriteLeveling(PI) end<-----
8391 01:26:17.560103
8392 01:26:17.560193 ==
8393 01:26:17.563484 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 01:26:17.570212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 01:26:17.570319 ==
8396 01:26:17.573765 [Gating] SW mode calibration
8397 01:26:17.579890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8398 01:26:17.583399 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8399 01:26:17.590327 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 01:26:17.593037 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 01:26:17.596539 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8402 01:26:17.603252 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
8403 01:26:17.606683 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 01:26:17.609424 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 01:26:17.616413 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 01:26:17.619959 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 01:26:17.622728 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 01:26:17.629246 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 01:26:17.632740 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
8410 01:26:17.636133 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8411 01:26:17.642876 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8412 01:26:17.646397 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 01:26:17.649558 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 01:26:17.656180 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 01:26:17.659380 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 01:26:17.662484 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 01:26:17.665862 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8418 01:26:17.672674 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8419 01:26:17.675761 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 01:26:17.678882 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 01:26:17.685700 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 01:26:17.688875 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 01:26:17.692518 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 01:26:17.699235 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 01:26:17.702646 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8426 01:26:17.705353 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8427 01:26:17.712410 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8428 01:26:17.715977 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 01:26:17.718858 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 01:26:17.725663 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 01:26:17.729185 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 01:26:17.732642 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 01:26:17.738667 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 01:26:17.742060 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 01:26:17.745302 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 01:26:17.752329 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 01:26:17.755854 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 01:26:17.759290 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 01:26:17.765574 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 01:26:17.769053 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 01:26:17.772404 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8442 01:26:17.778662 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8443 01:26:17.782003 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 01:26:17.785754 Total UI for P1: 0, mck2ui 16
8445 01:26:17.789120 best dqsien dly found for B0: ( 1, 9, 10)
8446 01:26:17.792426 Total UI for P1: 0, mck2ui 16
8447 01:26:17.795717 best dqsien dly found for B1: ( 1, 9, 10)
8448 01:26:17.798832 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8449 01:26:17.802052 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8450 01:26:17.802153
8451 01:26:17.805641 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8452 01:26:17.808478 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8453 01:26:17.811811 [Gating] SW calibration Done
8454 01:26:17.811912 ==
8455 01:26:17.815204 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 01:26:17.818442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 01:26:17.818534 ==
8458 01:26:17.821935 RX Vref Scan: 0
8459 01:26:17.822041
8460 01:26:17.825463 RX Vref 0 -> 0, step: 1
8461 01:26:17.825568
8462 01:26:17.825662 RX Delay 0 -> 252, step: 8
8463 01:26:17.832164 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8464 01:26:17.835580 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8465 01:26:17.838466 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8466 01:26:17.841716 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8467 01:26:17.845053 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8468 01:26:17.851623 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8469 01:26:17.855177 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8470 01:26:17.858640 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8471 01:26:17.862131 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8472 01:26:17.865544 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8473 01:26:17.871736 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8474 01:26:17.875095 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8475 01:26:17.878636 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8476 01:26:17.882062 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8477 01:26:17.884830 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8478 01:26:17.891907 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8479 01:26:17.892011 ==
8480 01:26:17.895223 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 01:26:17.898508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 01:26:17.898610 ==
8483 01:26:17.898712 DQS Delay:
8484 01:26:17.901969 DQS0 = 0, DQS1 = 0
8485 01:26:17.902071 DQM Delay:
8486 01:26:17.904652 DQM0 = 136, DQM1 = 133
8487 01:26:17.904752 DQ Delay:
8488 01:26:17.908103 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8489 01:26:17.911598 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8490 01:26:17.915068 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8491 01:26:17.917743 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8492 01:26:17.921220
8493 01:26:17.921317
8494 01:26:17.921415 ==
8495 01:26:17.924414 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 01:26:17.927679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 01:26:17.927781 ==
8498 01:26:17.927878
8499 01:26:17.927974
8500 01:26:17.931242 TX Vref Scan disable
8501 01:26:17.931340 == TX Byte 0 ==
8502 01:26:17.938162 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8503 01:26:17.941051 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8504 01:26:17.941154 == TX Byte 1 ==
8505 01:26:17.947877 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8506 01:26:17.951200 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8507 01:26:17.951320 ==
8508 01:26:17.954158 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 01:26:17.957524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 01:26:17.957625 ==
8511 01:26:17.971091
8512 01:26:17.974228 TX Vref early break, caculate TX vref
8513 01:26:17.977755 TX Vref=16, minBit 1, minWin=23, winSum=374
8514 01:26:17.981056 TX Vref=18, minBit 1, minWin=23, winSum=386
8515 01:26:17.984444 TX Vref=20, minBit 0, minWin=23, winSum=396
8516 01:26:17.987892 TX Vref=22, minBit 0, minWin=25, winSum=409
8517 01:26:17.990758 TX Vref=24, minBit 0, minWin=25, winSum=417
8518 01:26:17.997446 TX Vref=26, minBit 0, minWin=25, winSum=422
8519 01:26:18.000926 TX Vref=28, minBit 0, minWin=25, winSum=428
8520 01:26:18.004243 TX Vref=30, minBit 0, minWin=25, winSum=420
8521 01:26:18.007523 TX Vref=32, minBit 6, minWin=24, winSum=414
8522 01:26:18.011040 TX Vref=34, minBit 0, minWin=23, winSum=400
8523 01:26:18.017243 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8524 01:26:18.017349
8525 01:26:18.020730 Final TX Range 0 Vref 28
8526 01:26:18.020832
8527 01:26:18.020930 ==
8528 01:26:18.024223 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 01:26:18.027735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 01:26:18.027835 ==
8531 01:26:18.027936
8532 01:26:18.028032
8533 01:26:18.031193 TX Vref Scan disable
8534 01:26:18.037320 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8535 01:26:18.037438 == TX Byte 0 ==
8536 01:26:18.040750 u2DelayCellOfst[0]=16 cells (5 PI)
8537 01:26:18.044318 u2DelayCellOfst[1]=10 cells (3 PI)
8538 01:26:18.046987 u2DelayCellOfst[2]=0 cells (0 PI)
8539 01:26:18.050480 u2DelayCellOfst[3]=6 cells (2 PI)
8540 01:26:18.053964 u2DelayCellOfst[4]=6 cells (2 PI)
8541 01:26:18.057184 u2DelayCellOfst[5]=16 cells (5 PI)
8542 01:26:18.060701 u2DelayCellOfst[6]=16 cells (5 PI)
8543 01:26:18.060772 u2DelayCellOfst[7]=3 cells (1 PI)
8544 01:26:18.067073 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8545 01:26:18.070520 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8546 01:26:18.073777 == TX Byte 1 ==
8547 01:26:18.073877 u2DelayCellOfst[8]=0 cells (0 PI)
8548 01:26:18.076799 u2DelayCellOfst[9]=6 cells (2 PI)
8549 01:26:18.079926 u2DelayCellOfst[10]=13 cells (4 PI)
8550 01:26:18.083499 u2DelayCellOfst[11]=6 cells (2 PI)
8551 01:26:18.086988 u2DelayCellOfst[12]=16 cells (5 PI)
8552 01:26:18.090233 u2DelayCellOfst[13]=16 cells (5 PI)
8553 01:26:18.093632 u2DelayCellOfst[14]=20 cells (6 PI)
8554 01:26:18.096640 u2DelayCellOfst[15]=16 cells (5 PI)
8555 01:26:18.099915 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8556 01:26:18.106747 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8557 01:26:18.106855 DramC Write-DBI on
8558 01:26:18.106960 ==
8559 01:26:18.109691 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 01:26:18.116563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 01:26:18.116666 ==
8562 01:26:18.116761
8563 01:26:18.116850
8564 01:26:18.116935 TX Vref Scan disable
8565 01:26:18.120630 == TX Byte 0 ==
8566 01:26:18.123914 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8567 01:26:18.126700 == TX Byte 1 ==
8568 01:26:18.130140 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8569 01:26:18.133711 DramC Write-DBI off
8570 01:26:18.133790
8571 01:26:18.133853 [DATLAT]
8572 01:26:18.133912 Freq=1600, CH1 RK0
8573 01:26:18.133970
8574 01:26:18.137058 DATLAT Default: 0xf
8575 01:26:18.137160 0, 0xFFFF, sum = 0
8576 01:26:18.140665 1, 0xFFFF, sum = 0
8577 01:26:18.140746 2, 0xFFFF, sum = 0
8578 01:26:18.143476 3, 0xFFFF, sum = 0
8579 01:26:18.146830 4, 0xFFFF, sum = 0
8580 01:26:18.146912 5, 0xFFFF, sum = 0
8581 01:26:18.150413 6, 0xFFFF, sum = 0
8582 01:26:18.150494 7, 0xFFFF, sum = 0
8583 01:26:18.153830 8, 0xFFFF, sum = 0
8584 01:26:18.153911 9, 0xFFFF, sum = 0
8585 01:26:18.156644 10, 0xFFFF, sum = 0
8586 01:26:18.156727 11, 0xFFFF, sum = 0
8587 01:26:18.159969 12, 0xFFFF, sum = 0
8588 01:26:18.160053 13, 0xFFFF, sum = 0
8589 01:26:18.163887 14, 0x0, sum = 1
8590 01:26:18.163968 15, 0x0, sum = 2
8591 01:26:18.166583 16, 0x0, sum = 3
8592 01:26:18.166680 17, 0x0, sum = 4
8593 01:26:18.169953 best_step = 15
8594 01:26:18.170034
8595 01:26:18.170123 ==
8596 01:26:18.173585 Dram Type= 6, Freq= 0, CH_1, rank 0
8597 01:26:18.177066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8598 01:26:18.177147 ==
8599 01:26:18.177210 RX Vref Scan: 1
8600 01:26:18.180529
8601 01:26:18.180608 Set Vref Range= 24 -> 127
8602 01:26:18.180671
8603 01:26:18.183255 RX Vref 24 -> 127, step: 1
8604 01:26:18.183334
8605 01:26:18.186834 RX Delay 27 -> 252, step: 4
8606 01:26:18.186914
8607 01:26:18.190287 Set Vref, RX VrefLevel [Byte0]: 24
8608 01:26:18.193592 [Byte1]: 24
8609 01:26:18.193671
8610 01:26:18.196977 Set Vref, RX VrefLevel [Byte0]: 25
8611 01:26:18.199884 [Byte1]: 25
8612 01:26:18.199981
8613 01:26:18.203145 Set Vref, RX VrefLevel [Byte0]: 26
8614 01:26:18.206481 [Byte1]: 26
8615 01:26:18.210874
8616 01:26:18.210953 Set Vref, RX VrefLevel [Byte0]: 27
8617 01:26:18.214023 [Byte1]: 27
8618 01:26:18.218079
8619 01:26:18.218172 Set Vref, RX VrefLevel [Byte0]: 28
8620 01:26:18.221053 [Byte1]: 28
8621 01:26:18.225668
8622 01:26:18.225747 Set Vref, RX VrefLevel [Byte0]: 29
8623 01:26:18.228908 [Byte1]: 29
8624 01:26:18.233188
8625 01:26:18.233268 Set Vref, RX VrefLevel [Byte0]: 30
8626 01:26:18.236591 [Byte1]: 30
8627 01:26:18.240888
8628 01:26:18.240968 Set Vref, RX VrefLevel [Byte0]: 31
8629 01:26:18.243678 [Byte1]: 31
8630 01:26:18.248138
8631 01:26:18.248210 Set Vref, RX VrefLevel [Byte0]: 32
8632 01:26:18.251156 [Byte1]: 32
8633 01:26:18.255663
8634 01:26:18.255743 Set Vref, RX VrefLevel [Byte0]: 33
8635 01:26:18.259236 [Byte1]: 33
8636 01:26:18.263015
8637 01:26:18.263099 Set Vref, RX VrefLevel [Byte0]: 34
8638 01:26:18.266287 [Byte1]: 34
8639 01:26:18.270870
8640 01:26:18.270952 Set Vref, RX VrefLevel [Byte0]: 35
8641 01:26:18.273695 [Byte1]: 35
8642 01:26:18.278577
8643 01:26:18.278656 Set Vref, RX VrefLevel [Byte0]: 36
8644 01:26:18.281316 [Byte1]: 36
8645 01:26:18.285495
8646 01:26:18.285604 Set Vref, RX VrefLevel [Byte0]: 37
8647 01:26:18.288989 [Byte1]: 37
8648 01:26:18.293048
8649 01:26:18.293128 Set Vref, RX VrefLevel [Byte0]: 38
8650 01:26:18.296597 [Byte1]: 38
8651 01:26:18.300759
8652 01:26:18.300875 Set Vref, RX VrefLevel [Byte0]: 39
8653 01:26:18.304293 [Byte1]: 39
8654 01:26:18.308457
8655 01:26:18.308536 Set Vref, RX VrefLevel [Byte0]: 40
8656 01:26:18.311911 [Byte1]: 40
8657 01:26:18.316062
8658 01:26:18.316148 Set Vref, RX VrefLevel [Byte0]: 41
8659 01:26:18.319588 [Byte1]: 41
8660 01:26:18.323510
8661 01:26:18.323618 Set Vref, RX VrefLevel [Byte0]: 42
8662 01:26:18.326928 [Byte1]: 42
8663 01:26:18.331287
8664 01:26:18.331367 Set Vref, RX VrefLevel [Byte0]: 43
8665 01:26:18.337288 [Byte1]: 43
8666 01:26:18.337369
8667 01:26:18.340853 Set Vref, RX VrefLevel [Byte0]: 44
8668 01:26:18.343742 [Byte1]: 44
8669 01:26:18.343823
8670 01:26:18.347069 Set Vref, RX VrefLevel [Byte0]: 45
8671 01:26:18.350349 [Byte1]: 45
8672 01:26:18.350467
8673 01:26:18.353533 Set Vref, RX VrefLevel [Byte0]: 46
8674 01:26:18.356858 [Byte1]: 46
8675 01:26:18.360834
8676 01:26:18.360936 Set Vref, RX VrefLevel [Byte0]: 47
8677 01:26:18.364653 [Byte1]: 47
8678 01:26:18.369400
8679 01:26:18.369545 Set Vref, RX VrefLevel [Byte0]: 48
8680 01:26:18.372008 [Byte1]: 48
8681 01:26:18.376169
8682 01:26:18.376268 Set Vref, RX VrefLevel [Byte0]: 49
8683 01:26:18.379150 [Byte1]: 49
8684 01:26:18.383688
8685 01:26:18.383786 Set Vref, RX VrefLevel [Byte0]: 50
8686 01:26:18.386997 [Byte1]: 50
8687 01:26:18.391317
8688 01:26:18.391413 Set Vref, RX VrefLevel [Byte0]: 51
8689 01:26:18.394447 [Byte1]: 51
8690 01:26:18.398629
8691 01:26:18.398708 Set Vref, RX VrefLevel [Byte0]: 52
8692 01:26:18.402095 [Byte1]: 52
8693 01:26:18.406322
8694 01:26:18.406441 Set Vref, RX VrefLevel [Byte0]: 53
8695 01:26:18.409730 [Byte1]: 53
8696 01:26:18.414061
8697 01:26:18.414183 Set Vref, RX VrefLevel [Byte0]: 54
8698 01:26:18.417356 [Byte1]: 54
8699 01:26:18.421268
8700 01:26:18.421347 Set Vref, RX VrefLevel [Byte0]: 55
8701 01:26:18.424878 [Byte1]: 55
8702 01:26:18.428980
8703 01:26:18.429063 Set Vref, RX VrefLevel [Byte0]: 56
8704 01:26:18.432406 [Byte1]: 56
8705 01:26:18.436797
8706 01:26:18.436877 Set Vref, RX VrefLevel [Byte0]: 57
8707 01:26:18.439360 [Byte1]: 57
8708 01:26:18.443588
8709 01:26:18.443667 Set Vref, RX VrefLevel [Byte0]: 58
8710 01:26:18.447061 [Byte1]: 58
8711 01:26:18.451308
8712 01:26:18.451388 Set Vref, RX VrefLevel [Byte0]: 59
8713 01:26:18.454779 [Byte1]: 59
8714 01:26:18.458710
8715 01:26:18.458789 Set Vref, RX VrefLevel [Byte0]: 60
8716 01:26:18.462085 [Byte1]: 60
8717 01:26:18.466925
8718 01:26:18.467005 Set Vref, RX VrefLevel [Byte0]: 61
8719 01:26:18.469777 [Byte1]: 61
8720 01:26:18.473950
8721 01:26:18.474031 Set Vref, RX VrefLevel [Byte0]: 62
8722 01:26:18.477379 [Byte1]: 62
8723 01:26:18.481856
8724 01:26:18.481936 Set Vref, RX VrefLevel [Byte0]: 63
8725 01:26:18.485168 [Byte1]: 63
8726 01:26:18.489403
8727 01:26:18.489505 Set Vref, RX VrefLevel [Byte0]: 64
8728 01:26:18.492524 [Byte1]: 64
8729 01:26:18.496610
8730 01:26:18.496711 Set Vref, RX VrefLevel [Byte0]: 65
8731 01:26:18.499926 [Byte1]: 65
8732 01:26:18.504176
8733 01:26:18.504280 Set Vref, RX VrefLevel [Byte0]: 66
8734 01:26:18.507212 [Byte1]: 66
8735 01:26:18.511468
8736 01:26:18.511573 Set Vref, RX VrefLevel [Byte0]: 67
8737 01:26:18.515190 [Byte1]: 67
8738 01:26:18.519384
8739 01:26:18.519481 Set Vref, RX VrefLevel [Byte0]: 68
8740 01:26:18.522622 [Byte1]: 68
8741 01:26:18.526639
8742 01:26:18.526712 Set Vref, RX VrefLevel [Byte0]: 69
8743 01:26:18.530198 [Byte1]: 69
8744 01:26:18.534279
8745 01:26:18.534396 Set Vref, RX VrefLevel [Byte0]: 70
8746 01:26:18.537908 [Byte1]: 70
8747 01:26:18.541927
8748 01:26:18.542006 Set Vref, RX VrefLevel [Byte0]: 71
8749 01:26:18.545276 [Byte1]: 71
8750 01:26:18.549313
8751 01:26:18.549393 Set Vref, RX VrefLevel [Byte0]: 72
8752 01:26:18.552914 [Byte1]: 72
8753 01:26:18.557189
8754 01:26:18.557269 Set Vref, RX VrefLevel [Byte0]: 73
8755 01:26:18.559987 [Byte1]: 73
8756 01:26:18.564574
8757 01:26:18.564660 Set Vref, RX VrefLevel [Byte0]: 74
8758 01:26:18.567892 [Byte1]: 74
8759 01:26:18.572159
8760 01:26:18.572238 Set Vref, RX VrefLevel [Byte0]: 75
8761 01:26:18.575637 [Byte1]: 75
8762 01:26:18.579757
8763 01:26:18.579836 Set Vref, RX VrefLevel [Byte0]: 76
8764 01:26:18.583189 [Byte1]: 76
8765 01:26:18.587130
8766 01:26:18.587213 Set Vref, RX VrefLevel [Byte0]: 77
8767 01:26:18.590637 [Byte1]: 77
8768 01:26:18.594632
8769 01:26:18.594711 Set Vref, RX VrefLevel [Byte0]: 78
8770 01:26:18.598014 [Byte1]: 78
8771 01:26:18.602090
8772 01:26:18.602171 Final RX Vref Byte 0 = 58 to rank0
8773 01:26:18.605819 Final RX Vref Byte 1 = 57 to rank0
8774 01:26:18.609124 Final RX Vref Byte 0 = 58 to rank1
8775 01:26:18.612396 Final RX Vref Byte 1 = 57 to rank1==
8776 01:26:18.615705 Dram Type= 6, Freq= 0, CH_1, rank 0
8777 01:26:18.622006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 01:26:18.622086 ==
8779 01:26:18.622150 DQS Delay:
8780 01:26:18.622208 DQS0 = 0, DQS1 = 0
8781 01:26:18.625411 DQM Delay:
8782 01:26:18.625491 DQM0 = 134, DQM1 = 131
8783 01:26:18.628851 DQ Delay:
8784 01:26:18.632312 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8785 01:26:18.635620 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8786 01:26:18.638805 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8787 01:26:18.641914 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8788 01:26:18.641994
8789 01:26:18.642057
8790 01:26:18.642115
8791 01:26:18.645314 [DramC_TX_OE_Calibration] TA2
8792 01:26:18.648708 Original DQ_B0 (3 6) =30, OEN = 27
8793 01:26:18.651981 Original DQ_B1 (3 6) =30, OEN = 27
8794 01:26:18.655138 24, 0x0, End_B0=24 End_B1=24
8795 01:26:18.655221 25, 0x0, End_B0=25 End_B1=25
8796 01:26:18.658374 26, 0x0, End_B0=26 End_B1=26
8797 01:26:18.662187 27, 0x0, End_B0=27 End_B1=27
8798 01:26:18.665045 28, 0x0, End_B0=28 End_B1=28
8799 01:26:18.665191 29, 0x0, End_B0=29 End_B1=29
8800 01:26:18.668679 30, 0x0, End_B0=30 End_B1=30
8801 01:26:18.671916 31, 0x4141, End_B0=30 End_B1=30
8802 01:26:18.675143 Byte0 end_step=30 best_step=27
8803 01:26:18.678453 Byte1 end_step=30 best_step=27
8804 01:26:18.681857 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 01:26:18.685372 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 01:26:18.685453
8807 01:26:18.685517
8808 01:26:18.692179 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8809 01:26:18.695618 CH1 RK0: MR19=303, MR18=1523
8810 01:26:18.702155 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8811 01:26:18.702238
8812 01:26:18.705006 ----->DramcWriteLeveling(PI) begin...
8813 01:26:18.705116 ==
8814 01:26:18.708562 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 01:26:18.712081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 01:26:18.712187 ==
8817 01:26:18.715426 Write leveling (Byte 0): 26 => 26
8818 01:26:18.718713 Write leveling (Byte 1): 29 => 29
8819 01:26:18.722170 DramcWriteLeveling(PI) end<-----
8820 01:26:18.722251
8821 01:26:18.722323 ==
8822 01:26:18.725461 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 01:26:18.728931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 01:26:18.729012 ==
8825 01:26:18.731844 [Gating] SW mode calibration
8826 01:26:18.738650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8827 01:26:18.745478 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8828 01:26:18.748143 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 01:26:18.751599 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 01:26:18.758348 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8831 01:26:18.762035 1 4 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8832 01:26:18.765203 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 01:26:18.771840 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 01:26:18.774971 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 01:26:18.778192 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 01:26:18.784813 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 01:26:18.788295 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8838 01:26:18.791670 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8839 01:26:18.797892 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
8840 01:26:18.801294 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 01:26:18.804514 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 01:26:18.811112 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 01:26:18.814810 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 01:26:18.817828 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 01:26:18.824541 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 01:26:18.828319 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8847 01:26:18.831816 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8848 01:26:18.838114 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 01:26:18.841566 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 01:26:18.845044 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 01:26:18.851460 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 01:26:18.854961 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 01:26:18.857790 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8854 01:26:18.864733 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8855 01:26:18.868183 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8856 01:26:18.871512 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8857 01:26:18.874254 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 01:26:18.881649 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 01:26:18.884304 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 01:26:18.887689 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 01:26:18.894127 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 01:26:18.897534 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 01:26:18.901060 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 01:26:18.907213 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 01:26:18.910715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 01:26:18.913927 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 01:26:18.920765 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 01:26:18.923873 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 01:26:18.927429 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8870 01:26:18.933548 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8871 01:26:18.937417 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8872 01:26:18.940629 Total UI for P1: 0, mck2ui 16
8873 01:26:18.944175 best dqsien dly found for B1: ( 1, 9, 6)
8874 01:26:18.947076 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 01:26:18.950632 Total UI for P1: 0, mck2ui 16
8876 01:26:18.953877 best dqsien dly found for B0: ( 1, 9, 10)
8877 01:26:18.956995 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8878 01:26:18.960384 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8879 01:26:18.960464
8880 01:26:18.967288 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8881 01:26:18.970720 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8882 01:26:18.974032 [Gating] SW calibration Done
8883 01:26:18.974137 ==
8884 01:26:18.976835 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 01:26:18.980335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 01:26:18.980416 ==
8887 01:26:18.980480 RX Vref Scan: 0
8888 01:26:18.980539
8889 01:26:18.983837 RX Vref 0 -> 0, step: 1
8890 01:26:18.983917
8891 01:26:18.987313 RX Delay 0 -> 252, step: 8
8892 01:26:18.990795 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8893 01:26:18.993403 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8894 01:26:19.000466 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8895 01:26:19.003826 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8896 01:26:19.007338 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8897 01:26:19.010058 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8898 01:26:19.013588 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8899 01:26:19.017144 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8900 01:26:19.023598 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8901 01:26:19.027108 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8902 01:26:19.030428 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8903 01:26:19.033209 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8904 01:26:19.039872 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8905 01:26:19.043258 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8906 01:26:19.046939 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8907 01:26:19.050186 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8908 01:26:19.050293 ==
8909 01:26:19.053703 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 01:26:19.059896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 01:26:19.059977 ==
8912 01:26:19.060042 DQS Delay:
8913 01:26:19.060101 DQS0 = 0, DQS1 = 0
8914 01:26:19.063275 DQM Delay:
8915 01:26:19.063355 DQM0 = 136, DQM1 = 133
8916 01:26:19.066497 DQ Delay:
8917 01:26:19.069756 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8918 01:26:19.073582 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8919 01:26:19.076647 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8920 01:26:19.080211 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8921 01:26:19.080291
8922 01:26:19.080355
8923 01:26:19.080413 ==
8924 01:26:19.083664 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 01:26:19.086753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 01:26:19.086833 ==
8927 01:26:19.089768
8928 01:26:19.089847
8929 01:26:19.089909 TX Vref Scan disable
8930 01:26:19.093389 == TX Byte 0 ==
8931 01:26:19.096583 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8932 01:26:19.100231 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8933 01:26:19.103224 == TX Byte 1 ==
8934 01:26:19.106572 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8935 01:26:19.109811 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8936 01:26:19.109891 ==
8937 01:26:19.113536 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 01:26:19.119495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 01:26:19.119576 ==
8940 01:26:19.130608
8941 01:26:19.134153 TX Vref early break, caculate TX vref
8942 01:26:19.136756 TX Vref=16, minBit 0, minWin=23, winSum=387
8943 01:26:19.140385 TX Vref=18, minBit 0, minWin=24, winSum=394
8944 01:26:19.143795 TX Vref=20, minBit 1, minWin=24, winSum=401
8945 01:26:19.147210 TX Vref=22, minBit 6, minWin=24, winSum=409
8946 01:26:19.150653 TX Vref=24, minBit 0, minWin=25, winSum=414
8947 01:26:19.156784 TX Vref=26, minBit 0, minWin=25, winSum=421
8948 01:26:19.160008 TX Vref=28, minBit 0, minWin=26, winSum=427
8949 01:26:19.163349 TX Vref=30, minBit 1, minWin=25, winSum=425
8950 01:26:19.166900 TX Vref=32, minBit 0, minWin=24, winSum=403
8951 01:26:19.173348 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8952 01:26:19.173430
8953 01:26:19.176700 Final TX Range 0 Vref 28
8954 01:26:19.176783
8955 01:26:19.176847 ==
8956 01:26:19.180185 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 01:26:19.183761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 01:26:19.183843 ==
8959 01:26:19.183906
8960 01:26:19.183965
8961 01:26:19.186656 TX Vref Scan disable
8962 01:26:19.190023 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8963 01:26:19.193498 == TX Byte 0 ==
8964 01:26:19.196865 u2DelayCellOfst[0]=16 cells (5 PI)
8965 01:26:19.200227 u2DelayCellOfst[1]=10 cells (3 PI)
8966 01:26:19.203677 u2DelayCellOfst[2]=0 cells (0 PI)
8967 01:26:19.206854 u2DelayCellOfst[3]=6 cells (2 PI)
8968 01:26:19.206935 u2DelayCellOfst[4]=6 cells (2 PI)
8969 01:26:19.210076 u2DelayCellOfst[5]=16 cells (5 PI)
8970 01:26:19.213669 u2DelayCellOfst[6]=16 cells (5 PI)
8971 01:26:19.216909 u2DelayCellOfst[7]=6 cells (2 PI)
8972 01:26:19.220491 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8973 01:26:19.226594 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8974 01:26:19.226675 == TX Byte 1 ==
8975 01:26:19.230145 u2DelayCellOfst[8]=0 cells (0 PI)
8976 01:26:19.233604 u2DelayCellOfst[9]=3 cells (1 PI)
8977 01:26:19.237091 u2DelayCellOfst[10]=10 cells (3 PI)
8978 01:26:19.240287 u2DelayCellOfst[11]=3 cells (1 PI)
8979 01:26:19.243498 u2DelayCellOfst[12]=16 cells (5 PI)
8980 01:26:19.246749 u2DelayCellOfst[13]=16 cells (5 PI)
8981 01:26:19.250076 u2DelayCellOfst[14]=16 cells (5 PI)
8982 01:26:19.253282 u2DelayCellOfst[15]=16 cells (5 PI)
8983 01:26:19.256815 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8984 01:26:19.260008 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8985 01:26:19.263187 DramC Write-DBI on
8986 01:26:19.263268 ==
8987 01:26:19.266534 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 01:26:19.270455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 01:26:19.270586 ==
8990 01:26:19.270684
8991 01:26:19.270759
8992 01:26:19.273068 TX Vref Scan disable
8993 01:26:19.276698 == TX Byte 0 ==
8994 01:26:19.279970 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8995 01:26:19.280053 == TX Byte 1 ==
8996 01:26:19.286836 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8997 01:26:19.286918 DramC Write-DBI off
8998 01:26:19.286982
8999 01:26:19.289625 [DATLAT]
9000 01:26:19.289706 Freq=1600, CH1 RK1
9001 01:26:19.289771
9002 01:26:19.293247 DATLAT Default: 0xf
9003 01:26:19.293328 0, 0xFFFF, sum = 0
9004 01:26:19.296799 1, 0xFFFF, sum = 0
9005 01:26:19.296882 2, 0xFFFF, sum = 0
9006 01:26:19.300225 3, 0xFFFF, sum = 0
9007 01:26:19.300310 4, 0xFFFF, sum = 0
9008 01:26:19.303170 5, 0xFFFF, sum = 0
9009 01:26:19.303252 6, 0xFFFF, sum = 0
9010 01:26:19.306643 7, 0xFFFF, sum = 0
9011 01:26:19.306726 8, 0xFFFF, sum = 0
9012 01:26:19.309680 9, 0xFFFF, sum = 0
9013 01:26:19.309762 10, 0xFFFF, sum = 0
9014 01:26:19.312999 11, 0xFFFF, sum = 0
9015 01:26:19.316437 12, 0xFFFF, sum = 0
9016 01:26:19.316523 13, 0xFFFF, sum = 0
9017 01:26:19.319945 14, 0x0, sum = 1
9018 01:26:19.320027 15, 0x0, sum = 2
9019 01:26:19.320093 16, 0x0, sum = 3
9020 01:26:19.323105 17, 0x0, sum = 4
9021 01:26:19.323188 best_step = 15
9022 01:26:19.323252
9023 01:26:19.326275 ==
9024 01:26:19.326395 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 01:26:19.333271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 01:26:19.333354 ==
9027 01:26:19.333420 RX Vref Scan: 0
9028 01:26:19.333481
9029 01:26:19.336595 RX Vref 0 -> 0, step: 1
9030 01:26:19.336675
9031 01:26:19.339529 RX Delay 19 -> 252, step: 4
9032 01:26:19.342905 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9033 01:26:19.346294 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9034 01:26:19.353168 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9035 01:26:19.355823 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9036 01:26:19.359229 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9037 01:26:19.362917 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9038 01:26:19.366076 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9039 01:26:19.369101 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9040 01:26:19.375712 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9041 01:26:19.379250 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9042 01:26:19.382737 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9043 01:26:19.385876 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9044 01:26:19.392648 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9045 01:26:19.395790 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9046 01:26:19.398945 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9047 01:26:19.402517 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9048 01:26:19.402601 ==
9049 01:26:19.406021 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 01:26:19.412224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 01:26:19.412338 ==
9052 01:26:19.412440 DQS Delay:
9053 01:26:19.412538 DQS0 = 0, DQS1 = 0
9054 01:26:19.415596 DQM Delay:
9055 01:26:19.415680 DQM0 = 134, DQM1 = 130
9056 01:26:19.419141 DQ Delay:
9057 01:26:19.422540 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9058 01:26:19.426036 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9059 01:26:19.429054 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9060 01:26:19.432591 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9061 01:26:19.432674
9062 01:26:19.432758
9063 01:26:19.432838
9064 01:26:19.436036 [DramC_TX_OE_Calibration] TA2
9065 01:26:19.439393 Original DQ_B0 (3 6) =30, OEN = 27
9066 01:26:19.442789 Original DQ_B1 (3 6) =30, OEN = 27
9067 01:26:19.445621 24, 0x0, End_B0=24 End_B1=24
9068 01:26:19.445707 25, 0x0, End_B0=25 End_B1=25
9069 01:26:19.449096 26, 0x0, End_B0=26 End_B1=26
9070 01:26:19.452507 27, 0x0, End_B0=27 End_B1=27
9071 01:26:19.455888 28, 0x0, End_B0=28 End_B1=28
9072 01:26:19.455993 29, 0x0, End_B0=29 End_B1=29
9073 01:26:19.459289 30, 0x0, End_B0=30 End_B1=30
9074 01:26:19.462141 31, 0x4141, End_B0=30 End_B1=30
9075 01:26:19.465486 Byte0 end_step=30 best_step=27
9076 01:26:19.469062 Byte1 end_step=30 best_step=27
9077 01:26:19.472448 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 01:26:19.472530 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 01:26:19.475889
9080 01:26:19.475970
9081 01:26:19.482408 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9082 01:26:19.485353 CH1 RK1: MR19=303, MR18=2107
9083 01:26:19.492257 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
9084 01:26:19.495654 [RxdqsGatingPostProcess] freq 1600
9085 01:26:19.498955 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 01:26:19.502186 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 01:26:19.505429 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 01:26:19.508534 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 01:26:19.512215 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 01:26:19.515165 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 01:26:19.518971 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 01:26:19.521954 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 01:26:19.525343 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 01:26:19.528715 Pre-setting of DQS Precalculation
9095 01:26:19.531882 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 01:26:19.538450 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 01:26:19.545320 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 01:26:19.545404
9099 01:26:19.545469
9100 01:26:19.549036 [Calibration Summary] 3200 Mbps
9101 01:26:19.552033 CH 0, Rank 0
9102 01:26:19.552114 SW Impedance : PASS
9103 01:26:19.555542 DUTY Scan : NO K
9104 01:26:19.559026 ZQ Calibration : PASS
9105 01:26:19.559177 Jitter Meter : NO K
9106 01:26:19.562294 CBT Training : PASS
9107 01:26:19.565176 Write leveling : PASS
9108 01:26:19.565257 RX DQS gating : PASS
9109 01:26:19.568577 RX DQ/DQS(RDDQC) : PASS
9110 01:26:19.572033 TX DQ/DQS : PASS
9111 01:26:19.572115 RX DATLAT : PASS
9112 01:26:19.575355 RX DQ/DQS(Engine): PASS
9113 01:26:19.575437 TX OE : PASS
9114 01:26:19.578765 All Pass.
9115 01:26:19.578846
9116 01:26:19.578910 CH 0, Rank 1
9117 01:26:19.582228 SW Impedance : PASS
9118 01:26:19.582316 DUTY Scan : NO K
9119 01:26:19.585633 ZQ Calibration : PASS
9120 01:26:19.588468 Jitter Meter : NO K
9121 01:26:19.588550 CBT Training : PASS
9122 01:26:19.592003 Write leveling : PASS
9123 01:26:19.595431 RX DQS gating : PASS
9124 01:26:19.595512 RX DQ/DQS(RDDQC) : PASS
9125 01:26:19.598916 TX DQ/DQS : PASS
9126 01:26:19.601707 RX DATLAT : PASS
9127 01:26:19.601788 RX DQ/DQS(Engine): PASS
9128 01:26:19.605336 TX OE : PASS
9129 01:26:19.605417 All Pass.
9130 01:26:19.605481
9131 01:26:19.608804 CH 1, Rank 0
9132 01:26:19.608885 SW Impedance : PASS
9133 01:26:19.612158 DUTY Scan : NO K
9134 01:26:19.614715 ZQ Calibration : PASS
9135 01:26:19.614823 Jitter Meter : NO K
9136 01:26:19.618086 CBT Training : PASS
9137 01:26:19.621505 Write leveling : PASS
9138 01:26:19.621586 RX DQS gating : PASS
9139 01:26:19.625110 RX DQ/DQS(RDDQC) : PASS
9140 01:26:19.628546 TX DQ/DQS : PASS
9141 01:26:19.628628 RX DATLAT : PASS
9142 01:26:19.631339 RX DQ/DQS(Engine): PASS
9143 01:26:19.631419 TX OE : PASS
9144 01:26:19.634920 All Pass.
9145 01:26:19.635001
9146 01:26:19.635066 CH 1, Rank 1
9147 01:26:19.638520 SW Impedance : PASS
9148 01:26:19.638601 DUTY Scan : NO K
9149 01:26:19.641914 ZQ Calibration : PASS
9150 01:26:19.644662 Jitter Meter : NO K
9151 01:26:19.644743 CBT Training : PASS
9152 01:26:19.647909 Write leveling : PASS
9153 01:26:19.651580 RX DQS gating : PASS
9154 01:26:19.651661 RX DQ/DQS(RDDQC) : PASS
9155 01:26:19.654682 TX DQ/DQS : PASS
9156 01:26:19.658149 RX DATLAT : PASS
9157 01:26:19.658230 RX DQ/DQS(Engine): PASS
9158 01:26:19.661377 TX OE : PASS
9159 01:26:19.661458 All Pass.
9160 01:26:19.661525
9161 01:26:19.665025 DramC Write-DBI on
9162 01:26:19.667997 PER_BANK_REFRESH: Hybrid Mode
9163 01:26:19.668078 TX_TRACKING: ON
9164 01:26:19.678157 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 01:26:19.684803 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 01:26:19.691333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 01:26:19.694869 [FAST_K] Save calibration result to emmc
9168 01:26:19.698108 sync common calibartion params.
9169 01:26:19.701416 sync cbt_mode0:1, 1:1
9170 01:26:19.704840 dram_init: ddr_geometry: 2
9171 01:26:19.704921 dram_init: ddr_geometry: 2
9172 01:26:19.707613 dram_init: ddr_geometry: 2
9173 01:26:19.711111 0:dram_rank_size:100000000
9174 01:26:19.714602 1:dram_rank_size:100000000
9175 01:26:19.718037 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 01:26:19.721327 DFS_SHUFFLE_HW_MODE: ON
9177 01:26:19.724848 dramc_set_vcore_voltage set vcore to 725000
9178 01:26:19.727690 Read voltage for 1600, 0
9179 01:26:19.727771 Vio18 = 0
9180 01:26:19.727836 Vcore = 725000
9181 01:26:19.731230 Vdram = 0
9182 01:26:19.731327 Vddq = 0
9183 01:26:19.731420 Vmddr = 0
9184 01:26:19.734541 switch to 3200 Mbps bootup
9185 01:26:19.738078 [DramcRunTimeConfig]
9186 01:26:19.738185 PHYPLL
9187 01:26:19.738278 DPM_CONTROL_AFTERK: ON
9188 01:26:19.740848 PER_BANK_REFRESH: ON
9189 01:26:19.744293 REFRESH_OVERHEAD_REDUCTION: ON
9190 01:26:19.744375 CMD_PICG_NEW_MODE: OFF
9191 01:26:19.747788 XRTWTW_NEW_MODE: ON
9192 01:26:19.751255 XRTRTR_NEW_MODE: ON
9193 01:26:19.751336 TX_TRACKING: ON
9194 01:26:19.754650 RDSEL_TRACKING: OFF
9195 01:26:19.754731 DQS Precalculation for DVFS: ON
9196 01:26:19.757513 RX_TRACKING: OFF
9197 01:26:19.757594 HW_GATING DBG: ON
9198 01:26:19.761113 ZQCS_ENABLE_LP4: ON
9199 01:26:19.761222 RX_PICG_NEW_MODE: ON
9200 01:26:19.764394 TX_PICG_NEW_MODE: ON
9201 01:26:19.768072 ENABLE_RX_DCM_DPHY: ON
9202 01:26:19.770864 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 01:26:19.770945 DUMMY_READ_FOR_TRACKING: OFF
9204 01:26:19.774212 !!! SPM_CONTROL_AFTERK: OFF
9205 01:26:19.777547 !!! SPM could not control APHY
9206 01:26:19.780970 IMPEDANCE_TRACKING: ON
9207 01:26:19.781050 TEMP_SENSOR: ON
9208 01:26:19.781118 HW_SAVE_FOR_SR: OFF
9209 01:26:19.784406 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 01:26:19.787745 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 01:26:19.790961 Read ODT Tracking: ON
9212 01:26:19.794757 Refresh Rate DeBounce: ON
9213 01:26:19.794838 DFS_NO_QUEUE_FLUSH: ON
9214 01:26:19.797707 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 01:26:19.801205 ENABLE_DFS_RUNTIME_MRW: OFF
9216 01:26:19.804520 DDR_RESERVE_NEW_MODE: ON
9217 01:26:19.804609 MR_CBT_SWITCH_FREQ: ON
9218 01:26:19.807328 =========================
9219 01:26:19.826771 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 01:26:19.830139 dram_init: ddr_geometry: 2
9221 01:26:19.848848 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 01:26:19.851763 dram_init: dram init end (result: 0)
9223 01:26:19.858622 DRAM-K: Full calibration passed in 24506 msecs
9224 01:26:19.862020 MRC: failed to locate region type 0.
9225 01:26:19.862101 DRAM rank0 size:0x100000000,
9226 01:26:19.865431 DRAM rank1 size=0x100000000
9227 01:26:19.875100 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 01:26:19.881805 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 01:26:19.888296 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 01:26:19.895130 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 01:26:19.898028 DRAM rank0 size:0x100000000,
9232 01:26:19.901504 DRAM rank1 size=0x100000000
9233 01:26:19.901611 CBMEM:
9234 01:26:19.905402 IMD: root @ 0xfffff000 254 entries.
9235 01:26:19.907949 IMD: root @ 0xffffec00 62 entries.
9236 01:26:19.911311 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 01:26:19.914475 WARNING: RO_VPD is uninitialized or empty.
9238 01:26:19.921209 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 01:26:19.928226 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 01:26:19.941270 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9241 01:26:19.952419 BS: romstage times (exec / console): total (unknown) / 24029 ms
9242 01:26:19.952504
9243 01:26:19.952569
9244 01:26:19.962854 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 01:26:19.965555 ARM64: Exception handlers installed.
9246 01:26:19.969311 ARM64: Testing exception
9247 01:26:19.972769 ARM64: Done test exception
9248 01:26:19.972851 Enumerating buses...
9249 01:26:19.976120 Show all devs... Before device enumeration.
9250 01:26:19.978806 Root Device: enabled 1
9251 01:26:19.982802 CPU_CLUSTER: 0: enabled 1
9252 01:26:19.982884 CPU: 00: enabled 1
9253 01:26:19.985969 Compare with tree...
9254 01:26:19.986050 Root Device: enabled 1
9255 01:26:19.989481 CPU_CLUSTER: 0: enabled 1
9256 01:26:19.992918 CPU: 00: enabled 1
9257 01:26:19.992999 Root Device scanning...
9258 01:26:19.995733 scan_static_bus for Root Device
9259 01:26:19.999170 CPU_CLUSTER: 0 enabled
9260 01:26:20.002499 scan_static_bus for Root Device done
9261 01:26:20.006095 scan_bus: bus Root Device finished in 8 msecs
9262 01:26:20.006238 done
9263 01:26:20.012298 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 01:26:20.016130 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 01:26:20.022483 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 01:26:20.025845 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 01:26:20.029253 Allocating resources...
9268 01:26:20.032823 Reading resources...
9269 01:26:20.035536 Root Device read_resources bus 0 link: 0
9270 01:26:20.035617 DRAM rank0 size:0x100000000,
9271 01:26:20.038751 DRAM rank1 size=0x100000000
9272 01:26:20.042312 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 01:26:20.045769 CPU: 00 missing read_resources
9274 01:26:20.048965 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 01:26:20.055954 Root Device read_resources bus 0 link: 0 done
9276 01:26:20.056036 Done reading resources.
9277 01:26:20.062095 Show resources in subtree (Root Device)...After reading.
9278 01:26:20.065605 Root Device child on link 0 CPU_CLUSTER: 0
9279 01:26:20.068983 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 01:26:20.079028 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 01:26:20.079116 CPU: 00
9282 01:26:20.082348 Root Device assign_resources, bus 0 link: 0
9283 01:26:20.085517 CPU_CLUSTER: 0 missing set_resources
9284 01:26:20.088730 Root Device assign_resources, bus 0 link: 0 done
9285 01:26:20.092330 Done setting resources.
9286 01:26:20.098747 Show resources in subtree (Root Device)...After assigning values.
9287 01:26:20.102021 Root Device child on link 0 CPU_CLUSTER: 0
9288 01:26:20.105560 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 01:26:20.115291 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 01:26:20.115374 CPU: 00
9291 01:26:20.118556 Done allocating resources.
9292 01:26:20.121949 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 01:26:20.125140 Enabling resources...
9294 01:26:20.125222 done.
9295 01:26:20.132148 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 01:26:20.132231 Initializing devices...
9297 01:26:20.135344 Root Device init
9298 01:26:20.135425 init hardware done!
9299 01:26:20.138254 0x00000018: ctrlr->caps
9300 01:26:20.141639 52.000 MHz: ctrlr->f_max
9301 01:26:20.141723 0.400 MHz: ctrlr->f_min
9302 01:26:20.145302 0x40ff8080: ctrlr->voltages
9303 01:26:20.145385 sclk: 390625
9304 01:26:20.148781 Bus Width = 1
9305 01:26:20.148861 sclk: 390625
9306 01:26:20.151768 Bus Width = 1
9307 01:26:20.151850 Early init status = 3
9308 01:26:20.158282 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 01:26:20.161745 in-header: 03 fc 00 00 01 00 00 00
9310 01:26:20.165372 in-data: 00
9311 01:26:20.168121 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 01:26:20.173646 in-header: 03 fd 00 00 00 00 00 00
9313 01:26:20.176537 in-data:
9314 01:26:20.179924 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 01:26:20.184089 in-header: 03 fc 00 00 01 00 00 00
9316 01:26:20.187495 in-data: 00
9317 01:26:20.191050 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 01:26:20.196538 in-header: 03 fd 00 00 00 00 00 00
9319 01:26:20.199951 in-data:
9320 01:26:20.203164 [SSUSB] Setting up USB HOST controller...
9321 01:26:20.206437 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 01:26:20.209747 [SSUSB] phy power-on done.
9323 01:26:20.213324 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 01:26:20.219413 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 01:26:20.223022 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 01:26:20.229621 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 01:26:20.235880 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 01:26:20.242622 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 01:26:20.249622 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 01:26:20.256120 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 01:26:20.259159 SPM: binary array size = 0x9dc
9332 01:26:20.262893 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 01:26:20.269318 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 01:26:20.275926 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 01:26:20.279537 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 01:26:20.286144 configure_display: Starting display init
9337 01:26:20.320011 anx7625_power_on_init: Init interface.
9338 01:26:20.322921 anx7625_disable_pd_protocol: Disabled PD feature.
9339 01:26:20.326442 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 01:26:20.354170 anx7625_start_dp_work: Secure OCM version=00
9341 01:26:20.357686 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 01:26:20.372623 sp_tx_get_edid_block: EDID Block = 1
9343 01:26:20.474630 Extracted contents:
9344 01:26:20.477934 header: 00 ff ff ff ff ff ff 00
9345 01:26:20.481521 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 01:26:20.485063 version: 01 04
9347 01:26:20.488257 basic params: 95 1f 11 78 0a
9348 01:26:20.491117 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 01:26:20.494839 established: 00 00 00
9350 01:26:20.501561 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 01:26:20.505155 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 01:26:20.511327 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 01:26:20.517962 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 01:26:20.524785 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 01:26:20.528177 extensions: 00
9356 01:26:20.528258 checksum: fb
9357 01:26:20.528322
9358 01:26:20.530854 Manufacturer: IVO Model 57d Serial Number 0
9359 01:26:20.534157 Made week 0 of 2020
9360 01:26:20.534238 EDID version: 1.4
9361 01:26:20.537965 Digital display
9362 01:26:20.541022 6 bits per primary color channel
9363 01:26:20.541128 DisplayPort interface
9364 01:26:20.544545 Maximum image size: 31 cm x 17 cm
9365 01:26:20.547750 Gamma: 220%
9366 01:26:20.547869 Check DPMS levels
9367 01:26:20.550936 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 01:26:20.554340 First detailed timing is preferred timing
9369 01:26:20.558103 Established timings supported:
9370 01:26:20.561294 Standard timings supported:
9371 01:26:20.564205 Detailed timings
9372 01:26:20.567885 Hex of detail: 383680a07038204018303c0035ae10000019
9373 01:26:20.570810 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 01:26:20.577550 0780 0798 07c8 0820 hborder 0
9375 01:26:20.580971 0438 043b 0447 0458 vborder 0
9376 01:26:20.584061 -hsync -vsync
9377 01:26:20.584142 Did detailed timing
9378 01:26:20.591030 Hex of detail: 000000000000000000000000000000000000
9379 01:26:20.591110 Manufacturer-specified data, tag 0
9380 01:26:20.597323 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 01:26:20.600856 ASCII string: InfoVision
9382 01:26:20.604436 Hex of detail: 000000fe00523134304e574635205248200a
9383 01:26:20.607067 ASCII string: R140NWF5 RH
9384 01:26:20.607148 Checksum
9385 01:26:20.610592 Checksum: 0xfb (valid)
9386 01:26:20.614105 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 01:26:20.617493 DSI data_rate: 832800000 bps
9388 01:26:20.624224 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 01:26:20.627131 anx7625_parse_edid: pixelclock(138800).
9390 01:26:20.630475 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 01:26:20.633958 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 01:26:20.637353 anx7625_dsi_config: config dsi.
9393 01:26:20.643714 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 01:26:20.656994 anx7625_dsi_config: success to config DSI
9395 01:26:20.660426 anx7625_dp_start: MIPI phy setup OK.
9396 01:26:20.663767 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 01:26:20.666540 mtk_ddp_mode_set invalid vrefresh 60
9398 01:26:20.670546 main_disp_path_setup
9399 01:26:20.670631 ovl_layer_smi_id_en
9400 01:26:20.673174 ovl_layer_smi_id_en
9401 01:26:20.673280 ccorr_config
9402 01:26:20.673370 aal_config
9403 01:26:20.676652 gamma_config
9404 01:26:20.676734 postmask_config
9405 01:26:20.679862 dither_config
9406 01:26:20.683192 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 01:26:20.690276 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 01:26:20.693627 Root Device init finished in 555 msecs
9409 01:26:20.696638 CPU_CLUSTER: 0 init
9410 01:26:20.703169 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 01:26:20.706738 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 01:26:20.710040 APU_MBOX 0x190000b0 = 0x10001
9413 01:26:20.713396 APU_MBOX 0x190001b0 = 0x10001
9414 01:26:20.716862 APU_MBOX 0x190005b0 = 0x10001
9415 01:26:20.719806 APU_MBOX 0x190006b0 = 0x10001
9416 01:26:20.723293 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 01:26:20.735951 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 01:26:20.748288 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 01:26:20.754962 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 01:26:20.766510 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9421 01:26:20.775501 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 01:26:20.778902 CPU_CLUSTER: 0 init finished in 81 msecs
9423 01:26:20.782665 Devices initialized
9424 01:26:20.785481 Show all devs... After init.
9425 01:26:20.785563 Root Device: enabled 1
9426 01:26:20.788867 CPU_CLUSTER: 0: enabled 1
9427 01:26:20.792214 CPU: 00: enabled 1
9428 01:26:20.795785 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9429 01:26:20.799207 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 01:26:20.802108 ELOG: NV offset 0x57f000 size 0x1000
9431 01:26:20.808660 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9432 01:26:20.815365 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 01:26:20.818675 ELOG: Event(17) added with size 13 at 2024-04-23 01:22:09 UTC
9434 01:26:20.822237 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 01:26:20.825753 in-header: 03 aa 00 00 2c 00 00 00
9436 01:26:20.839551 in-data: b5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 01:26:20.846104 ELOG: Event(A1) added with size 10 at 2024-04-23 01:22:09 UTC
9438 01:26:20.852316 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 01:26:20.858960 ELOG: Event(A0) added with size 9 at 2024-04-23 01:22:09 UTC
9440 01:26:20.862427 elog_add_boot_reason: Logged dev mode boot
9441 01:26:20.865731 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 01:26:20.869048 Finalize devices...
9443 01:26:20.869130 Devices finalized
9444 01:26:20.875860 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 01:26:20.878728 Writing coreboot table at 0xffe64000
9446 01:26:20.882140 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 01:26:20.885598 1. 0000000040000000-00000000400fffff: RAM
9448 01:26:20.891957 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 01:26:20.895440 3. 000000004032b000-00000000545fffff: RAM
9450 01:26:20.898776 4. 0000000054600000-000000005465ffff: BL31
9451 01:26:20.902236 5. 0000000054660000-00000000ffe63fff: RAM
9452 01:26:20.909078 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 01:26:20.912107 7. 0000000100000000-000000023fffffff: RAM
9454 01:26:20.912202 Passing 5 GPIOs to payload:
9455 01:26:20.918718 NAME | PORT | POLARITY | VALUE
9456 01:26:20.922222 EC in RW | 0x000000aa | low | undefined
9457 01:26:20.928456 EC interrupt | 0x00000005 | low | undefined
9458 01:26:20.931910 TPM interrupt | 0x000000ab | high | undefined
9459 01:26:20.935872 SD card detect | 0x00000011 | high | undefined
9460 01:26:20.942026 speaker enable | 0x00000093 | high | undefined
9461 01:26:20.945546 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 01:26:20.948848 in-header: 03 f9 00 00 02 00 00 00
9463 01:26:20.951872 in-data: 02 00
9464 01:26:20.951953 ADC[4]: Raw value=904357 ID=7
9465 01:26:20.955662 ADC[3]: Raw value=213441 ID=1
9466 01:26:20.958362 RAM Code: 0x71
9467 01:26:20.958443 ADC[6]: Raw value=75332 ID=0
9468 01:26:20.962245 ADC[5]: Raw value=213810 ID=1
9469 01:26:20.964906 SKU Code: 0x1
9470 01:26:20.968851 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cac8
9471 01:26:20.971574 coreboot table: 964 bytes.
9472 01:26:20.974998 IMD ROOT 0. 0xfffff000 0x00001000
9473 01:26:20.978419 IMD SMALL 1. 0xffffe000 0x00001000
9474 01:26:20.981766 RO MCACHE 2. 0xffffc000 0x00001104
9475 01:26:20.985287 CONSOLE 3. 0xfff7c000 0x00080000
9476 01:26:20.988707 FMAP 4. 0xfff7b000 0x00000452
9477 01:26:20.992182 TIME STAMP 5. 0xfff7a000 0x00000910
9478 01:26:20.995412 VBOOT WORK 6. 0xfff66000 0x00014000
9479 01:26:20.998680 RAMOOPS 7. 0xffe66000 0x00100000
9480 01:26:21.002177 COREBOOT 8. 0xffe64000 0x00002000
9481 01:26:21.002259 IMD small region:
9482 01:26:21.004805 IMD ROOT 0. 0xffffec00 0x00000400
9483 01:26:21.008814 VPD 1. 0xffffeb80 0x0000006c
9484 01:26:21.015272 MMC STATUS 2. 0xffffeb60 0x00000004
9485 01:26:21.018683 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9486 01:26:21.022062 Probing TPM: done!
9487 01:26:21.025256 Connected to device vid:did:rid of 1ae0:0028:00
9488 01:26:21.035441 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 01:26:21.038269 Initialized TPM device CR50 revision 0
9490 01:26:21.041701 Checking cr50 for pending updates
9491 01:26:21.045946 Reading cr50 TPM mode
9492 01:26:21.054878 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 01:26:21.061177 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 01:26:21.101518 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9495 01:26:21.104780 Checking segment from ROM address 0x40100000
9496 01:26:21.108156 Checking segment from ROM address 0x4010001c
9497 01:26:21.114831 Loading segment from ROM address 0x40100000
9498 01:26:21.114913 code (compression=0)
9499 01:26:21.121850 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 01:26:21.131233 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 01:26:21.131314 it's not compressed!
9502 01:26:21.137931 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 01:26:21.141279 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 01:26:21.162028 Loading segment from ROM address 0x4010001c
9505 01:26:21.162112 Entry Point 0x80000000
9506 01:26:21.164883 Loaded segments
9507 01:26:21.168301 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 01:26:21.175481 Jumping to boot code at 0x80000000(0xffe64000)
9509 01:26:21.181782 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 01:26:21.188681 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 01:26:21.196608 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9512 01:26:21.199857 Checking segment from ROM address 0x40100000
9513 01:26:21.202905 Checking segment from ROM address 0x4010001c
9514 01:26:21.209990 Loading segment from ROM address 0x40100000
9515 01:26:21.210071 code (compression=1)
9516 01:26:21.216386 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 01:26:21.226061 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 01:26:21.226144 using LZMA
9519 01:26:21.234722 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 01:26:21.241316 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 01:26:21.244598 Loading segment from ROM address 0x4010001c
9522 01:26:21.244680 Entry Point 0x54601000
9523 01:26:21.247727 Loaded segments
9524 01:26:21.251088 NOTICE: MT8192 bl31_setup
9525 01:26:21.258182 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 01:26:21.261695 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 01:26:21.265042 WARNING: region 0:
9528 01:26:21.268616 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 01:26:21.268697 WARNING: region 1:
9530 01:26:21.274744 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 01:26:21.278233 WARNING: region 2:
9532 01:26:21.281315 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 01:26:21.284727 WARNING: region 3:
9534 01:26:21.287982 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 01:26:21.291502 WARNING: region 4:
9536 01:26:21.294992 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 01:26:21.298518 WARNING: region 5:
9538 01:26:21.301937 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 01:26:21.305395 WARNING: region 6:
9540 01:26:21.308267 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 01:26:21.308348 WARNING: region 7:
9542 01:26:21.315144 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 01:26:21.321881 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 01:26:21.325203 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 01:26:21.328393 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 01:26:21.334920 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 01:26:21.338365 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 01:26:21.341164 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 01:26:21.348272 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 01:26:21.351180 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 01:26:21.358029 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 01:26:21.361220 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 01:26:21.364637 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 01:26:21.371516 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 01:26:21.374959 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 01:26:21.377763 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 01:26:21.384724 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 01:26:21.387964 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 01:26:21.394664 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 01:26:21.397896 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 01:26:21.401431 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 01:26:21.407743 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 01:26:21.411330 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 01:26:21.414851 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 01:26:21.421056 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 01:26:21.424400 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 01:26:21.431083 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 01:26:21.434231 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 01:26:21.441264 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 01:26:21.444756 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 01:26:21.447536 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 01:26:21.454543 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 01:26:21.458047 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 01:26:21.461772 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 01:26:21.467708 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 01:26:21.471607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 01:26:21.474803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 01:26:21.477816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 01:26:21.484784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 01:26:21.487840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 01:26:21.491050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 01:26:21.494515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 01:26:21.501423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 01:26:21.504665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 01:26:21.507841 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 01:26:21.511404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 01:26:21.517518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 01:26:21.521003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 01:26:21.524608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 01:26:21.527893 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 01:26:21.538774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 01:26:21.538900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 01:26:21.544614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 01:26:21.547818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 01:26:21.554211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 01:26:21.557682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 01:26:21.561302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 01:26:21.568055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 01:26:21.571436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 01:26:21.577617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 01:26:21.581119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 01:26:21.587701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 01:26:21.591032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 01:26:21.594496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 01:26:21.601183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 01:26:21.604401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 01:26:21.611422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 01:26:21.614859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 01:26:21.621301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 01:26:21.624278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 01:26:21.627824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 01:26:21.634731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 01:26:21.638023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 01:26:21.644340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 01:26:21.648292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 01:26:21.654780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 01:26:21.658038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 01:26:21.661147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 01:26:21.668081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 01:26:21.671436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 01:26:21.677676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 01:26:21.681153 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 01:26:21.688041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 01:26:21.691562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 01:26:21.694267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 01:26:21.701099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 01:26:21.704489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 01:26:21.711306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 01:26:21.714810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 01:26:21.720853 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 01:26:21.724943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 01:26:21.728463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 01:26:21.735111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 01:26:21.738068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 01:26:21.744835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 01:26:21.747897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 01:26:21.754380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 01:26:21.757777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 01:26:21.761615 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 01:26:21.768188 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 01:26:21.771770 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 01:26:21.775107 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 01:26:21.777891 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 01:26:21.784650 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 01:26:21.788143 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 01:26:21.791620 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 01:26:21.798317 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 01:26:21.801622 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 01:26:21.808534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 01:26:21.811802 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 01:26:21.814654 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 01:26:21.821493 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 01:26:21.825078 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 01:26:21.831319 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 01:26:21.834698 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 01:26:21.838050 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 01:26:21.845109 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 01:26:21.848293 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 01:26:21.851832 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 01:26:21.858437 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 01:26:21.861623 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 01:26:21.864686 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 01:26:21.871400 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 01:26:21.874705 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 01:26:21.877908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 01:26:21.881399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 01:26:21.888098 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 01:26:21.891876 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 01:26:21.895287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 01:26:21.901921 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 01:26:21.905424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 01:26:21.911409 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 01:26:21.914862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 01:26:21.918264 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 01:26:21.925382 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 01:26:21.928163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 01:26:21.934934 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 01:26:21.938339 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 01:26:21.941749 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 01:26:21.948589 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 01:26:21.951333 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 01:26:21.954965 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 01:26:21.961665 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 01:26:21.965325 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 01:26:21.971345 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 01:26:21.974893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 01:26:21.978180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 01:26:21.984744 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 01:26:21.987870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 01:26:21.995108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 01:26:21.997952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 01:26:22.001515 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 01:26:22.008252 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 01:26:22.011599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 01:26:22.014890 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 01:26:22.021435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 01:26:22.024987 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 01:26:22.031799 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 01:26:22.035288 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 01:26:22.038689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 01:26:22.045059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 01:26:22.048360 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 01:26:22.054583 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 01:26:22.058077 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 01:26:22.061447 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 01:26:22.068330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 01:26:22.071724 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 01:26:22.074648 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 01:26:22.081568 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 01:26:22.085181 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 01:26:22.091262 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 01:26:22.094847 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 01:26:22.098254 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 01:26:22.104450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 01:26:22.107848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 01:26:22.114852 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 01:26:22.117616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 01:26:22.121013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 01:26:22.127688 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 01:26:22.131076 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 01:26:22.138184 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 01:26:22.141181 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 01:26:22.144370 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 01:26:22.151246 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 01:26:22.154551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 01:26:22.157748 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 01:26:22.164652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 01:26:22.167950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 01:26:22.174538 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 01:26:22.178109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 01:26:22.180819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 01:26:22.187752 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 01:26:22.191130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 01:26:22.197303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 01:26:22.200804 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 01:26:22.207630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 01:26:22.211021 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 01:26:22.214553 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 01:26:22.220865 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 01:26:22.224230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 01:26:22.230907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 01:26:22.234180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 01:26:22.237541 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 01:26:22.244398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 01:26:22.247246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 01:26:22.254215 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 01:26:22.257038 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 01:26:22.263744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 01:26:22.267001 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 01:26:22.270600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 01:26:22.276898 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 01:26:22.280387 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 01:26:22.286895 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 01:26:22.290354 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 01:26:22.297070 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 01:26:22.300425 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 01:26:22.303898 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 01:26:22.310633 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 01:26:22.313397 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 01:26:22.320485 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 01:26:22.323124 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 01:26:22.330042 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 01:26:22.333479 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 01:26:22.336943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 01:26:22.343471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 01:26:22.346285 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 01:26:22.353068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 01:26:22.356595 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 01:26:22.362665 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 01:26:22.366089 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 01:26:22.369612 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 01:26:22.376471 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 01:26:22.379366 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 01:26:22.382867 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 01:26:22.385953 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 01:26:22.389151 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 01:26:22.396091 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 01:26:22.399299 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 01:26:22.405878 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 01:26:22.409516 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 01:26:22.412474 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 01:26:22.419058 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 01:26:22.422649 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 01:26:22.429495 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 01:26:22.432280 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 01:26:22.435818 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 01:26:22.442429 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 01:26:22.445631 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 01:26:22.448805 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 01:26:22.455415 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 01:26:22.458722 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 01:26:22.462213 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 01:26:22.468952 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 01:26:22.472494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 01:26:22.478852 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 01:26:22.481622 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 01:26:22.485020 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 01:26:22.492118 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 01:26:22.495480 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 01:26:22.498693 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 01:26:22.505056 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 01:26:22.508348 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 01:26:22.511848 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 01:26:22.518687 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 01:26:22.521510 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 01:26:22.528490 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 01:26:22.531515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 01:26:22.534812 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 01:26:22.541333 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 01:26:22.544679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 01:26:22.547757 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 01:26:22.555091 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 01:26:22.558172 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 01:26:22.561431 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 01:26:22.564653 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 01:26:22.568215 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 01:26:22.574712 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 01:26:22.578099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 01:26:22.581115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 01:26:22.588193 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 01:26:22.591367 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 01:26:22.594229 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 01:26:22.597723 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 01:26:22.604503 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 01:26:22.607820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 01:26:22.614565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 01:26:22.617740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 01:26:22.621167 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 01:26:22.627515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 01:26:22.631041 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 01:26:22.637225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 01:26:22.640785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 01:26:22.644122 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 01:26:22.650851 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 01:26:22.654212 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 01:26:22.661096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 01:26:22.664214 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 01:26:22.667385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 01:26:22.674220 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 01:26:22.677562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 01:26:22.683816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 01:26:22.687262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 01:26:22.690621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 01:26:22.697086 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 01:26:22.700799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 01:26:22.707301 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 01:26:22.710636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 01:26:22.713891 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 01:26:22.720766 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 01:26:22.724072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 01:26:22.730775 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 01:26:22.734265 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 01:26:22.740341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 01:26:22.743829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 01:26:22.747327 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 01:26:22.753567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 01:26:22.757070 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 01:26:22.763895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 01:26:22.767422 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 01:26:22.770234 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 01:26:22.777141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 01:26:22.780520 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 01:26:22.786697 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 01:26:22.790009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 01:26:22.793838 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 01:26:22.800264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 01:26:22.803590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 01:26:22.810494 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 01:26:22.813227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 01:26:22.819904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 01:26:22.823253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 01:26:22.826815 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 01:26:22.833476 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 01:26:22.836739 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 01:26:22.843228 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 01:26:22.846895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 01:26:22.850290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 01:26:22.857035 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 01:26:22.859836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 01:26:22.866789 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 01:26:22.870163 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 01:26:22.873006 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 01:26:22.879438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 01:26:22.882870 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 01:26:22.889716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 01:26:22.893050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 01:26:22.899342 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 01:26:22.902629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 01:26:22.905844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 01:26:22.912763 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 01:26:22.916083 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 01:26:22.923043 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 01:26:22.926233 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 01:26:22.929686 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 01:26:22.936224 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 01:26:22.938965 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 01:26:22.945756 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 01:26:22.948987 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 01:26:22.955652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 01:26:22.959035 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 01:26:22.962073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 01:26:22.969119 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 01:26:22.972400 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 01:26:22.978822 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 01:26:22.982450 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 01:26:22.988601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 01:26:22.992008 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 01:26:22.998313 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 01:26:23.001762 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 01:26:23.005319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 01:26:23.011924 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 01:26:23.015241 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 01:26:23.021614 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 01:26:23.025159 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 01:26:23.031404 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 01:26:23.034931 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 01:26:23.041489 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 01:26:23.044858 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 01:26:23.048473 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 01:26:23.054779 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 01:26:23.058358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 01:26:23.064999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 01:26:23.068271 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 01:26:23.074791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 01:26:23.078522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 01:26:23.081560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 01:26:23.087903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 01:26:23.091280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 01:26:23.098193 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 01:26:23.101642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 01:26:23.107908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 01:26:23.111294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 01:26:23.114883 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 01:26:23.121636 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 01:26:23.124852 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 01:26:23.131113 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 01:26:23.134573 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 01:26:23.141453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 01:26:23.144896 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 01:26:23.148249 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 01:26:23.154460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 01:26:23.157888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 01:26:23.164735 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 01:26:23.167980 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 01:26:23.171188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 01:26:23.178057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 01:26:23.180987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 01:26:23.187794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 01:26:23.191271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 01:26:23.197732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 01:26:23.200755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 01:26:23.207515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 01:26:23.211119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 01:26:23.217759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 01:26:23.220609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 01:26:23.227653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 01:26:23.231015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 01:26:23.237489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 01:26:23.240708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 01:26:23.247124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 01:26:23.251074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 01:26:23.257038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 01:26:23.260414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 01:26:23.267390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 01:26:23.270689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 01:26:23.277221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 01:26:23.280810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 01:26:23.286905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 01:26:23.290357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 01:26:23.297058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 01:26:23.300383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 01:26:23.307233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 01:26:23.309930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 01:26:23.316581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 01:26:23.320097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 01:26:23.326775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 01:26:23.330017 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 01:26:23.333290 INFO: [APUAPC] vio 0
9979 01:26:23.336467 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 01:26:23.340114 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 01:26:23.343396 INFO: [APUAPC] D0_APC_0: 0x400510
9982 01:26:23.346888 INFO: [APUAPC] D0_APC_1: 0x0
9983 01:26:23.349806 INFO: [APUAPC] D0_APC_2: 0x1540
9984 01:26:23.353551 INFO: [APUAPC] D0_APC_3: 0x0
9985 01:26:23.356608 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 01:26:23.360111 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 01:26:23.362880 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 01:26:23.366252 INFO: [APUAPC] D1_APC_3: 0x0
9989 01:26:23.370130 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 01:26:23.373094 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 01:26:23.376427 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 01:26:23.379759 INFO: [APUAPC] D2_APC_3: 0x0
9993 01:26:23.383364 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 01:26:23.386101 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 01:26:23.389671 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 01:26:23.393123 INFO: [APUAPC] D3_APC_3: 0x0
9997 01:26:23.396675 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 01:26:23.399393 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 01:26:23.402839 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 01:26:23.406478 INFO: [APUAPC] D4_APC_3: 0x0
10001 01:26:23.409391 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 01:26:23.412638 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 01:26:23.416086 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 01:26:23.419382 INFO: [APUAPC] D5_APC_3: 0x0
10005 01:26:23.422803 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 01:26:23.426207 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 01:26:23.429545 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 01:26:23.433088 INFO: [APUAPC] D6_APC_3: 0x0
10009 01:26:23.436371 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 01:26:23.439762 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 01:26:23.443108 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 01:26:23.446009 INFO: [APUAPC] D7_APC_3: 0x0
10013 01:26:23.449258 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 01:26:23.452706 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 01:26:23.455927 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 01:26:23.456023 INFO: [APUAPC] D8_APC_3: 0x0
10017 01:26:23.462835 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 01:26:23.465975 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 01:26:23.469191 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 01:26:23.469290 INFO: [APUAPC] D9_APC_3: 0x0
10021 01:26:23.475564 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 01:26:23.479403 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 01:26:23.482456 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 01:26:23.485727 INFO: [APUAPC] D10_APC_3: 0x0
10025 01:26:23.489290 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 01:26:23.492185 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 01:26:23.495749 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 01:26:23.498787 INFO: [APUAPC] D11_APC_3: 0x0
10029 01:26:23.502185 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 01:26:23.505667 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 01:26:23.509136 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 01:26:23.511923 INFO: [APUAPC] D12_APC_3: 0x0
10033 01:26:23.515486 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 01:26:23.518949 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 01:26:23.522279 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 01:26:23.525653 INFO: [APUAPC] D13_APC_3: 0x0
10037 01:26:23.528832 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 01:26:23.532279 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 01:26:23.535093 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 01:26:23.538487 INFO: [APUAPC] D14_APC_3: 0x0
10041 01:26:23.541795 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 01:26:23.545284 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 01:26:23.548747 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 01:26:23.552270 INFO: [APUAPC] D15_APC_3: 0x0
10045 01:26:23.554958 INFO: [APUAPC] APC_CON: 0x4
10046 01:26:23.555029 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 01:26:23.558448 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 01:26:23.562012 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 01:26:23.565395 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 01:26:23.568714 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 01:26:23.572053 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 01:26:23.575235 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 01:26:23.578524 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 01:26:23.581628 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 01:26:23.584930 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 01:26:23.585010 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 01:26:23.588174 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 01:26:23.591630 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 01:26:23.594853 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 01:26:23.598135 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 01:26:23.601352 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 01:26:23.604513 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 01:26:23.608182 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 01:26:23.611411 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 01:26:23.614572 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 01:26:23.618330 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 01:26:23.621653 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 01:26:23.621734 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 01:26:23.624668 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 01:26:23.627980 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 01:26:23.631537 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 01:26:23.634816 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 01:26:23.638241 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 01:26:23.641091 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 01:26:23.644354 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 01:26:23.647795 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 01:26:23.651340 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 01:26:23.654712 INFO: [NOCDAPC] APC_CON: 0x4
10079 01:26:23.658203 INFO: [APUAPC] set_apusys_apc done
10080 01:26:23.661062 INFO: [DEVAPC] devapc_init done
10081 01:26:23.664565 INFO: GICv3 without legacy support detected.
10082 01:26:23.668028 INFO: ARM GICv3 driver initialized in EL3
10083 01:26:23.671563 INFO: Maximum SPI INTID supported: 639
10084 01:26:23.675069 INFO: BL31: Initializing runtime services
10085 01:26:23.681101 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 01:26:23.684869 INFO: SPM: enable CPC mode
10087 01:26:23.691483 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 01:26:23.694749 INFO: BL31: Preparing for EL3 exit to normal world
10089 01:26:23.697691 INFO: Entry point address = 0x80000000
10090 01:26:23.701280 INFO: SPSR = 0x8
10091 01:26:23.705875
10092 01:26:23.705947
10093 01:26:23.706007
10094 01:26:23.709360 Starting depthcharge on Spherion...
10095 01:26:23.709427
10096 01:26:23.709484 Wipe memory regions:
10097 01:26:23.709540
10098 01:26:23.710164 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 01:26:23.710260 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 01:26:23.710376 Setting prompt string to ['asurada:']
10101 01:26:23.710457 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 01:26:23.713051 [0x00000040000000, 0x00000054600000)
10103 01:26:23.834856
10104 01:26:23.834972 [0x00000054660000, 0x00000080000000)
10105 01:26:24.095715
10106 01:26:24.095853 [0x000000821a7280, 0x000000ffe64000)
10107 01:26:24.840177
10108 01:26:24.840328 [0x00000100000000, 0x00000240000000)
10109 01:26:26.730203
10110 01:26:26.733336 Initializing XHCI USB controller at 0x11200000.
10111 01:26:27.771102
10112 01:26:27.773792 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 01:26:27.774215
10114 01:26:27.774637
10115 01:26:27.774959
10116 01:26:27.775721 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 01:26:27.876731 asurada: tftpboot 192.168.201.1 13468775/tftp-deploy-kqdu6js6/kernel/image.itb 13468775/tftp-deploy-kqdu6js6/kernel/cmdline
10119 01:26:27.877292 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 01:26:27.877680 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 01:26:27.881628 tftpboot 192.168.201.1 13468775/tftp-deploy-kqdu6js6/kernel/image.ittp-deploy-kqdu6js6/kernel/cmdline
10122 01:26:27.882085
10123 01:26:27.882467 Waiting for link
10124 01:26:28.042441
10125 01:26:28.043063 R8152: Initializing
10126 01:26:28.043532
10127 01:26:28.045997 Version 9 (ocp_data = 6010)
10128 01:26:28.046454
10129 01:26:28.049225 R8152: Done initializing
10130 01:26:28.049788
10131 01:26:28.050144 Adding net device
10132 01:26:29.993022
10133 01:26:29.993505 done.
10134 01:26:29.993918
10135 01:26:29.994269 MAC: 00:e0:4c:78:7a:aa
10136 01:26:29.994741
10137 01:26:29.995702 Sending DHCP discover... done.
10138 01:26:29.996121
10139 01:26:29.999151 Waiting for reply... done.
10140 01:26:29.999568
10141 01:26:30.002366 Sending DHCP request... done.
10142 01:26:30.002786
10143 01:26:30.006184 Waiting for reply... done.
10144 01:26:30.006648
10145 01:26:30.006982 My ip is 192.168.201.12
10146 01:26:30.007308
10147 01:26:30.009959 The DHCP server ip is 192.168.201.1
10148 01:26:30.010429
10149 01:26:30.017019 TFTP server IP predefined by user: 192.168.201.1
10150 01:26:30.017431
10151 01:26:30.023392 Bootfile predefined by user: 13468775/tftp-deploy-kqdu6js6/kernel/image.itb
10152 01:26:30.023803
10153 01:26:30.024127 Sending tftp read request... done.
10154 01:26:30.026755
10155 01:26:30.032076 Waiting for the transfer...
10156 01:26:30.032630
10157 01:26:30.339390 00000000 ################################################################
10158 01:26:30.339536
10159 01:26:30.595716 00080000 ################################################################
10160 01:26:30.595869
10161 01:26:30.849358 00100000 ################################################################
10162 01:26:30.849495
10163 01:26:31.109332 00180000 ################################################################
10164 01:26:31.109468
10165 01:26:31.385575 00200000 ################################################################
10166 01:26:31.385717
10167 01:26:31.638490 00280000 ################################################################
10168 01:26:31.638620
10169 01:26:31.887006 00300000 ################################################################
10170 01:26:31.887143
10171 01:26:32.139021 00380000 ################################################################
10172 01:26:32.139156
10173 01:26:32.391920 00400000 ################################################################
10174 01:26:32.392091
10175 01:26:32.738762 00480000 ################################################################
10176 01:26:32.738924
10177 01:26:33.020519 00500000 ################################################################
10178 01:26:33.020757
10179 01:26:33.275109 00580000 ################################################################
10180 01:26:33.275281
10181 01:26:33.531937 00600000 ################################################################
10182 01:26:33.532072
10183 01:26:33.782865 00680000 ################################################################
10184 01:26:33.783002
10185 01:26:34.028834 00700000 ################################################################
10186 01:26:34.029002
10187 01:26:34.275780 00780000 ################################################################
10188 01:26:34.275947
10189 01:26:34.524068 00800000 ################################################################
10190 01:26:34.524211
10191 01:26:34.806675 00880000 ################################################################
10192 01:26:34.806853
10193 01:26:35.084033 00900000 ################################################################
10194 01:26:35.084215
10195 01:26:35.362244 00980000 ################################################################
10196 01:26:35.362436
10197 01:26:35.657486 00a00000 ################################################################
10198 01:26:35.657617
10199 01:26:35.937721 00a80000 ################################################################
10200 01:26:35.937848
10201 01:26:36.194299 00b00000 ################################################################
10202 01:26:36.194512
10203 01:26:36.461419 00b80000 ################################################################
10204 01:26:36.461576
10205 01:26:36.764922 00c00000 ################################################################
10206 01:26:36.765099
10207 01:26:37.076813 00c80000 ################################################################
10208 01:26:37.076982
10209 01:26:37.357858 00d00000 ################################################################
10210 01:26:37.358002
10211 01:26:37.630272 00d80000 ################################################################
10212 01:26:37.630442
10213 01:26:37.896015 00e00000 ################################################################
10214 01:26:37.896152
10215 01:26:38.163083 00e80000 ################################################################
10216 01:26:38.163232
10217 01:26:38.431352 00f00000 ################################################################
10218 01:26:38.431498
10219 01:26:38.686325 00f80000 ################################################################
10220 01:26:38.686473
10221 01:26:38.958854 01000000 ################################################################
10222 01:26:38.958980
10223 01:26:39.216386 01080000 ################################################################
10224 01:26:39.216518
10225 01:26:39.493910 01100000 ################################################################
10226 01:26:39.494042
10227 01:26:39.749059 01180000 ################################################################
10228 01:26:39.749185
10229 01:26:40.021199 01200000 ################################################################
10230 01:26:40.021334
10231 01:26:40.290207 01280000 ################################################################
10232 01:26:40.290409
10233 01:26:40.557131 01300000 ################################################################
10234 01:26:40.557298
10235 01:26:40.824173 01380000 ################################################################
10236 01:26:40.824335
10237 01:26:41.169550 01400000 ################################################################
10238 01:26:41.169713
10239 01:26:41.508671 01480000 ################################################################
10240 01:26:41.508832
10241 01:26:41.847591 01500000 ################################################################
10242 01:26:41.847749
10243 01:26:42.184888 01580000 ################################################################
10244 01:26:42.185053
10245 01:26:42.449159 01600000 ################################################################
10246 01:26:42.449324
10247 01:26:42.704873 01680000 ################################################################
10248 01:26:42.705031
10249 01:26:42.977604 01700000 ################################################################
10250 01:26:42.977769
10251 01:26:43.255473 01780000 ################################################################
10252 01:26:43.255640
10253 01:26:43.539298 01800000 ################################################################
10254 01:26:43.539462
10255 01:26:43.810254 01880000 ################################################################
10256 01:26:43.810467
10257 01:26:44.065961 01900000 ################################################################
10258 01:26:44.066120
10259 01:26:44.336566 01980000 ################################################################
10260 01:26:44.336728
10261 01:26:44.585973 01a00000 ################################################################
10262 01:26:44.586136
10263 01:26:44.841719 01a80000 ################################################################
10264 01:26:44.841879
10265 01:26:45.098404 01b00000 ################################################################
10266 01:26:45.098625
10267 01:26:45.361368 01b80000 ################################################################
10268 01:26:45.361524
10269 01:26:45.641935 01c00000 ################################################################
10270 01:26:45.642092
10271 01:26:45.915130 01c80000 ################################################################
10272 01:26:45.915284
10273 01:26:46.172635 01d00000 ################################################################
10274 01:26:46.172799
10275 01:26:46.436686 01d80000 ################################################################
10276 01:26:46.436852
10277 01:26:46.592571 01e00000 ################################### done.
10278 01:26:46.592702
10279 01:26:46.596579 The bootfile was 31737074 bytes long.
10280 01:26:46.596665
10281 01:26:46.599468 Sending tftp read request... done.
10282 01:26:46.599550
10283 01:26:46.602825 Waiting for the transfer...
10284 01:26:46.602907
10285 01:26:46.602971 00000000 # done.
10286 01:26:46.603034
10287 01:26:46.609573 Command line loaded dynamically from TFTP file: 13468775/tftp-deploy-kqdu6js6/kernel/cmdline
10288 01:26:46.609661
10289 01:26:46.632616 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10290 01:26:46.632754
10291 01:26:46.632853 Loading FIT.
10292 01:26:46.632943
10293 01:26:46.636288 Image ramdisk-1 has 18777760 bytes.
10294 01:26:46.636424
10295 01:26:46.639608 Image fdt-1 has 47230 bytes.
10296 01:26:46.639762
10297 01:26:46.642856 Image kernel-1 has 12910050 bytes.
10298 01:26:46.643040
10299 01:26:46.652605 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10300 01:26:46.652899
10301 01:26:46.668998 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10302 01:26:46.669178
10303 01:26:46.675684 Choosing best match conf-1 for compat google,spherion-rev2.
10304 01:26:46.675832
10305 01:26:46.683876 Connected to device vid:did:rid of 1ae0:0028:00
10306 01:26:46.691870
10307 01:26:46.695043 tpm_get_response: command 0x17b, return code 0x0
10308 01:26:46.695146
10309 01:26:46.698733 ec_init: CrosEC protocol v3 supported (256, 248)
10310 01:26:46.702679
10311 01:26:46.705684 tpm_cleanup: add release locality here.
10312 01:26:46.705766
10313 01:26:46.705830 Shutting down all USB controllers.
10314 01:26:46.709618
10315 01:26:46.709699 Removing current net device
10316 01:26:46.709764
10317 01:26:46.716012 Exiting depthcharge with code 4 at timestamp: 52338544
10318 01:26:46.716093
10319 01:26:46.719521 LZMA decompressing kernel-1 to 0x821a6718
10320 01:26:46.719640
10321 01:26:46.722309 LZMA decompressing kernel-1 to 0x40000000
10322 01:26:48.317354
10323 01:26:48.317502 jumping to kernel
10324 01:26:48.317963 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10325 01:26:48.318058 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10326 01:26:48.318134 Setting prompt string to ['Linux version [0-9]']
10327 01:26:48.318202 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10328 01:26:48.318268 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10329 01:26:48.400340
10330 01:26:48.403634 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10331 01:26:48.406995 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10332 01:26:48.407089 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10333 01:26:48.407161 Setting prompt string to []
10334 01:26:48.407238 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10335 01:26:48.407337 Using line separator: #'\n'#
10336 01:26:48.407440 No login prompt set.
10337 01:26:48.407531 Parsing kernel messages
10338 01:26:48.407615 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10339 01:26:48.407785 [login-action] Waiting for messages, (timeout 00:04:01)
10340 01:26:48.407878 Waiting using forced prompt support (timeout 00:02:00)
10341 01:26:48.426561 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j174389-arm64-gcc-10-defconfig-arm64-chromebook-96m9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024
10342 01:26:48.430018 [ 0.000000] random: crng init done
10343 01:26:48.436466 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 01:26:48.440104 [ 0.000000] efi: UEFI not found.
10345 01:26:48.446288 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 01:26:48.453236 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 01:26:48.463086 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 01:26:48.472908 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 01:26:48.479670 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 01:26:48.485938 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 01:26:48.492503 [ 0.000000] NUMA: No NUMA configuration found
10352 01:26:48.499549 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 01:26:48.502796 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10354 01:26:48.505592 [ 0.000000] Zone ranges:
10355 01:26:48.512253 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 01:26:48.515726 [ 0.000000] DMA32 empty
10357 01:26:48.522569 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 01:26:48.526061 [ 0.000000] Movable zone start for each node
10359 01:26:48.528892 [ 0.000000] Early memory node ranges
10360 01:26:48.535669 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 01:26:48.542483 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 01:26:48.549093 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 01:26:48.555644 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 01:26:48.562281 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 01:26:48.568868 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 01:26:48.624377 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 01:26:48.630619 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 01:26:48.637250 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 01:26:48.640724 [ 0.000000] psci: probing for conduit method from DT.
10370 01:26:48.646908 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 01:26:48.650412 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 01:26:48.657377 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 01:26:48.660886 [ 0.000000] psci: SMC Calling Convention v1.2
10374 01:26:48.667113 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10375 01:26:48.670591 [ 0.000000] Detected VIPT I-cache on CPU0
10376 01:26:48.676897 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 01:26:48.683659 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 01:26:48.690560 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 01:26:48.696816 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 01:26:48.703437 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 01:26:48.713285 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 01:26:48.716538 [ 0.000000] alternatives: applying boot alternatives
10383 01:26:48.723100 [ 0.000000] Fallback order for Node 0: 0
10384 01:26:48.729902 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 01:26:48.733472 [ 0.000000] Policy zone: Normal
10386 01:26:48.756289 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10387 01:26:48.766067 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 01:26:48.777245 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 01:26:48.786770 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 01:26:48.793887 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10391 01:26:48.796755 <6>[ 0.000000] software IO TLB: area num 8.
10392 01:26:48.853339 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 01:26:49.002480 <6>[ 0.000000] Memory: 7946172K/8385536K available (18048K kernel code, 4118K rwdata, 22292K rodata, 8448K init, 616K bss, 406596K reserved, 32768K cma-reserved)
10394 01:26:49.009264 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 01:26:49.015467 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 01:26:49.018931 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 01:26:49.025866 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 01:26:49.032021 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 01:26:49.035424 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 01:26:49.045382 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 01:26:49.051931 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 01:26:49.059010 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 01:26:49.065412 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 01:26:49.068462 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 01:26:49.071769 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 01:26:49.078532 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 01:26:49.081994 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 01:26:49.088461 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 01:26:49.101657 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 01:26:49.114877 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 01:26:49.121618 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 01:26:49.129158 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 01:26:49.142153 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 01:26:49.148893 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 01:26:49.155952 <6>[ 0.009179] Console: colour dummy device 80x25
10416 01:26:49.165712 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 01:26:49.172248 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10418 01:26:49.175513 <6>[ 0.029252] LSM: Security Framework initializing
10419 01:26:49.182206 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 01:26:49.192160 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 01:26:49.198691 <6>[ 0.051442] cblist_init_generic: Setting adjustable number of callback queues.
10422 01:26:49.205531 <6>[ 0.058885] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 01:26:49.215491 <6>[ 0.065263] cblist_init_generic: Setting adjustable number of callback queues.
10424 01:26:49.218736 <6>[ 0.072690] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 01:26:49.225792 <6>[ 0.079091] rcu: Hierarchical SRCU implementation.
10426 01:26:49.232324 <6>[ 0.084106] rcu: Max phase no-delay instances is 1000.
10427 01:26:49.238750 <6>[ 0.091172] EFI services will not be available.
10428 01:26:49.242199 <6>[ 0.096124] smp: Bringing up secondary CPUs ...
10429 01:26:49.250203 <6>[ 0.101199] Detected VIPT I-cache on CPU1
10430 01:26:49.256433 <6>[ 0.101271] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10431 01:26:49.263318 <6>[ 0.101302] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10432 01:26:49.266684 <6>[ 0.101630] Detected VIPT I-cache on CPU2
10433 01:26:49.276434 <6>[ 0.101678] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10434 01:26:49.282927 <6>[ 0.101694] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10435 01:26:49.286531 <6>[ 0.101949] Detected VIPT I-cache on CPU3
10436 01:26:49.293046 <6>[ 0.101995] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10437 01:26:49.299865 <6>[ 0.102008] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10438 01:26:49.302893 <6>[ 0.102310] CPU features: detected: Spectre-v4
10439 01:26:49.309212 <6>[ 0.102316] CPU features: detected: Spectre-BHB
10440 01:26:49.312622 <6>[ 0.102321] Detected PIPT I-cache on CPU4
10441 01:26:49.319347 <6>[ 0.102378] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10442 01:26:49.326204 <6>[ 0.102395] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10443 01:26:49.332931 <6>[ 0.102687] Detected PIPT I-cache on CPU5
10444 01:26:49.339600 <6>[ 0.102748] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10445 01:26:49.345816 <6>[ 0.102764] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10446 01:26:49.349178 <6>[ 0.103045] Detected PIPT I-cache on CPU6
10447 01:26:49.355862 <6>[ 0.103112] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10448 01:26:49.362691 <6>[ 0.103127] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10449 01:26:49.368647 <6>[ 0.103426] Detected PIPT I-cache on CPU7
10450 01:26:49.375615 <6>[ 0.103491] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10451 01:26:49.382317 <6>[ 0.103507] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10452 01:26:49.385583 <6>[ 0.103553] smp: Brought up 1 node, 8 CPUs
10453 01:26:49.392148 <6>[ 0.244950] SMP: Total of 8 processors activated.
10454 01:26:49.395300 <6>[ 0.249872] CPU features: detected: 32-bit EL0 Support
10455 01:26:49.405296 <6>[ 0.255235] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10456 01:26:49.412259 <6>[ 0.264036] CPU features: detected: Common not Private translations
10457 01:26:49.418864 <6>[ 0.270512] CPU features: detected: CRC32 instructions
10458 01:26:49.421852 <6>[ 0.275864] CPU features: detected: RCpc load-acquire (LDAPR)
10459 01:26:49.428730 <6>[ 0.281823] CPU features: detected: LSE atomic instructions
10460 01:26:49.435475 <6>[ 0.287641] CPU features: detected: Privileged Access Never
10461 01:26:49.441592 <6>[ 0.293421] CPU features: detected: RAS Extension Support
10462 01:26:49.448475 <6>[ 0.299029] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10463 01:26:49.451713 <6>[ 0.306251] CPU: All CPU(s) started at EL2
10464 01:26:49.458221 <6>[ 0.310568] alternatives: applying system-wide alternatives
10465 01:26:49.468184 <6>[ 0.321426] devtmpfs: initialized
10466 01:26:49.480345 <6>[ 0.330342] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10467 01:26:49.490088 <6>[ 0.340308] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10468 01:26:49.496519 <6>[ 0.348184] pinctrl core: initialized pinctrl subsystem
10469 01:26:49.500324 <6>[ 0.354825] DMI not present or invalid.
10470 01:26:49.506206 <6>[ 0.359238] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10471 01:26:49.516925 <6>[ 0.366129] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10472 01:26:49.522969 <6>[ 0.373718] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10473 01:26:49.532833 <6>[ 0.381937] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10474 01:26:49.536780 <6>[ 0.390175] audit: initializing netlink subsys (disabled)
10475 01:26:49.546205 <5>[ 0.395865] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10476 01:26:49.552939 <6>[ 0.396562] thermal_sys: Registered thermal governor 'step_wise'
10477 01:26:49.559821 <6>[ 0.403830] thermal_sys: Registered thermal governor 'power_allocator'
10478 01:26:49.562578 <6>[ 0.410082] cpuidle: using governor menu
10479 01:26:49.569348 <6>[ 0.421039] NET: Registered PF_QIPCRTR protocol family
10480 01:26:49.575854 <6>[ 0.426538] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10481 01:26:49.579568 <6>[ 0.433643] ASID allocator initialised with 32768 entries
10482 01:26:49.586835 <6>[ 0.440209] Serial: AMBA PL011 UART driver
10483 01:26:49.595652 <4>[ 0.448915] Trying to register duplicate clock ID: 134
10484 01:26:49.649679 <6>[ 0.506370] KASLR enabled
10485 01:26:49.663707 <6>[ 0.514077] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10486 01:26:49.670480 <6>[ 0.521089] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10487 01:26:49.677342 <6>[ 0.527578] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10488 01:26:49.683918 <6>[ 0.534582] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10489 01:26:49.690480 <6>[ 0.541068] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10490 01:26:49.697283 <6>[ 0.548075] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10491 01:26:49.703368 <6>[ 0.554561] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10492 01:26:49.710050 <6>[ 0.561568] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10493 01:26:49.713176 <6>[ 0.569081] ACPI: Interpreter disabled.
10494 01:26:49.722081 <6>[ 0.575501] iommu: Default domain type: Translated
10495 01:26:49.728900 <6>[ 0.580614] iommu: DMA domain TLB invalidation policy: strict mode
10496 01:26:49.732085 <5>[ 0.587275] SCSI subsystem initialized
10497 01:26:49.738663 <6>[ 0.591436] usbcore: registered new interface driver usbfs
10498 01:26:49.745208 <6>[ 0.597170] usbcore: registered new interface driver hub
10499 01:26:49.748470 <6>[ 0.602722] usbcore: registered new device driver usb
10500 01:26:49.755221 <6>[ 0.608813] pps_core: LinuxPPS API ver. 1 registered
10501 01:26:49.764937 <6>[ 0.614008] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10502 01:26:49.768736 <6>[ 0.623353] PTP clock support registered
10503 01:26:49.771911 <6>[ 0.627594] EDAC MC: Ver: 3.0.0
10504 01:26:49.778998 <6>[ 0.632741] FPGA manager framework
10505 01:26:49.785753 <6>[ 0.636420] Advanced Linux Sound Architecture Driver Initialized.
10506 01:26:49.789210 <6>[ 0.643198] vgaarb: loaded
10507 01:26:49.795762 <6>[ 0.646377] clocksource: Switched to clocksource arch_sys_counter
10508 01:26:49.798863 <5>[ 0.652818] VFS: Disk quotas dquot_6.6.0
10509 01:26:49.805648 <6>[ 0.657008] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10510 01:26:49.808837 <6>[ 0.664194] pnp: PnP ACPI: disabled
10511 01:26:49.817627 <6>[ 0.670887] NET: Registered PF_INET protocol family
10512 01:26:49.826957 <6>[ 0.676489] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10513 01:26:49.838462 <6>[ 0.688792] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10514 01:26:49.848750 <6>[ 0.697608] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10515 01:26:49.854965 <6>[ 0.705576] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10516 01:26:49.861832 <6>[ 0.714273] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10517 01:26:49.873625 <6>[ 0.724006] TCP: Hash tables configured (established 65536 bind 65536)
10518 01:26:49.880450 <6>[ 0.730866] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 01:26:49.886832 <6>[ 0.738063] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10520 01:26:49.893384 <6>[ 0.745766] NET: Registered PF_UNIX/PF_LOCAL protocol family
10521 01:26:49.900499 <6>[ 0.751936] RPC: Registered named UNIX socket transport module.
10522 01:26:49.903863 <6>[ 0.758093] RPC: Registered udp transport module.
10523 01:26:49.910121 <6>[ 0.763026] RPC: Registered tcp transport module.
10524 01:26:49.917063 <6>[ 0.767959] RPC: Registered tcp NFSv4.1 backchannel transport module.
10525 01:26:49.920386 <6>[ 0.774622] PCI: CLS 0 bytes, default 64
10526 01:26:49.923580 <6>[ 0.779054] Unpacking initramfs...
10527 01:26:49.933433 <6>[ 0.783229] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10528 01:26:49.943297 <6>[ 0.791880] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10529 01:26:49.946634 <6>[ 0.800656] kvm [1]: IPA Size Limit: 40 bits
10530 01:26:49.953200 <6>[ 0.805181] kvm [1]: GICv3: no GICV resource entry
10531 01:26:49.956460 <6>[ 0.810201] kvm [1]: disabling GICv2 emulation
10532 01:26:49.963370 <6>[ 0.814883] kvm [1]: GIC system register CPU interface enabled
10533 01:26:49.966716 <6>[ 0.821049] kvm [1]: vgic interrupt IRQ18
10534 01:26:49.973038 <6>[ 0.826444] kvm [1]: VHE mode initialized successfully
10535 01:26:49.979860 <5>[ 0.832890] Initialise system trusted keyrings
10536 01:26:49.986727 <6>[ 0.837679] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10537 01:26:49.993961 <6>[ 0.847675] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10538 01:26:50.001084 <5>[ 0.854069] NFS: Registering the id_resolver key type
10539 01:26:50.004054 <5>[ 0.859367] Key type id_resolver registered
10540 01:26:50.010836 <5>[ 0.863779] Key type id_legacy registered
10541 01:26:50.017365 <6>[ 0.868060] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10542 01:26:50.024074 <6>[ 0.874983] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10543 01:26:50.030586 <6>[ 0.882722] 9p: Installing v9fs 9p2000 file system support
10544 01:26:50.067013 <5>[ 0.920356] Key type asymmetric registered
10545 01:26:50.069784 <5>[ 0.924683] Asymmetric key parser 'x509' registered
10546 01:26:50.080140 <6>[ 0.929819] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10547 01:26:50.083562 <6>[ 0.937433] io scheduler mq-deadline registered
10548 01:26:50.086419 <6>[ 0.942192] io scheduler kyber registered
10549 01:26:50.105336 <6>[ 0.959175] EINJ: ACPI disabled.
10550 01:26:50.137752 <4>[ 0.984390] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 01:26:50.147745 <4>[ 0.995133] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 01:26:50.162590 <6>[ 1.015767] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10553 01:26:50.170144 <6>[ 1.023739] printk: console [ttyS0] disabled
10554 01:26:50.197813 <6>[ 1.048368] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10555 01:26:50.204749 <6>[ 1.057855] printk: console [ttyS0] enabled
10556 01:26:50.207763 <6>[ 1.057855] printk: console [ttyS0] enabled
10557 01:26:50.214546 <6>[ 1.066748] printk: bootconsole [mtk8250] disabled
10558 01:26:50.218007 <6>[ 1.066748] printk: bootconsole [mtk8250] disabled
10559 01:26:50.224671 <6>[ 1.077771] SuperH (H)SCI(F) driver initialized
10560 01:26:50.227816 <6>[ 1.083049] msm_serial: driver initialized
10561 01:26:50.241578 <6>[ 1.091973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10562 01:26:50.251585 <6>[ 1.100519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10563 01:26:50.258327 <6>[ 1.109060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10564 01:26:50.268244 <6>[ 1.117687] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10565 01:26:50.277970 <6>[ 1.126393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10566 01:26:50.285062 <6>[ 1.135106] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10567 01:26:50.294644 <6>[ 1.143647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10568 01:26:50.301393 <6>[ 1.152436] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10569 01:26:50.311275 <6>[ 1.160977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10570 01:26:50.322835 <6>[ 1.176427] loop: module loaded
10571 01:26:50.329123 <6>[ 1.182510] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10572 01:26:50.352340 <4>[ 1.205672] mtk-pmic-keys: Failed to locate of_node [id: -1]
10573 01:26:50.358887 <6>[ 1.212470] megasas: 07.719.03.00-rc1
10574 01:26:50.368499 <6>[ 1.221973] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10575 01:26:50.376121 <6>[ 1.229745] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10576 01:26:50.393250 <6>[ 1.246381] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10577 01:26:50.448631 <6>[ 1.295983] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10578 01:26:50.715554 <6>[ 1.568971] Freeing initrd memory: 18332K
10579 01:26:50.726616 <6>[ 1.580582] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10580 01:26:50.738047 <6>[ 1.591441] tun: Universal TUN/TAP device driver, 1.6
10581 01:26:50.741096 <6>[ 1.597497] thunder_xcv, ver 1.0
10582 01:26:50.744619 <6>[ 1.601003] thunder_bgx, ver 1.0
10583 01:26:50.747623 <6>[ 1.604500] nicpf, ver 1.0
10584 01:26:50.758294 <6>[ 1.608511] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10585 01:26:50.761636 <6>[ 1.615986] hns3: Copyright (c) 2017 Huawei Corporation.
10586 01:26:50.768214 <6>[ 1.621571] hclge is initializing
10587 01:26:50.771538 <6>[ 1.625151] e1000: Intel(R) PRO/1000 Network Driver
10588 01:26:50.778320 <6>[ 1.630280] e1000: Copyright (c) 1999-2006 Intel Corporation.
10589 01:26:50.781435 <6>[ 1.636295] e1000e: Intel(R) PRO/1000 Network Driver
10590 01:26:50.788200 <6>[ 1.641512] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10591 01:26:50.795012 <6>[ 1.647699] igb: Intel(R) Gigabit Ethernet Network Driver
10592 01:26:50.801124 <6>[ 1.653349] igb: Copyright (c) 2007-2014 Intel Corporation.
10593 01:26:50.808040 <6>[ 1.659185] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10594 01:26:50.814624 <6>[ 1.665703] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10595 01:26:50.818103 <6>[ 1.672166] sky2: driver version 1.30
10596 01:26:50.824520 <6>[ 1.677148] VFIO - User Level meta-driver version: 0.3
10597 01:26:50.831838 <6>[ 1.685369] usbcore: registered new interface driver usb-storage
10598 01:26:50.838181 <6>[ 1.691816] usbcore: registered new device driver onboard-usb-hub
10599 01:26:50.847697 <6>[ 1.700975] mt6397-rtc mt6359-rtc: registered as rtc0
10600 01:26:50.857154 <6>[ 1.706448] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-23T01:22:39 UTC (1713835359)
10601 01:26:50.860334 <6>[ 1.716030] i2c_dev: i2c /dev entries driver
10602 01:26:50.877595 <6>[ 1.727691] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10603 01:26:50.884421 <4>[ 1.736421] cpu cpu0: supply cpu not found, using dummy regulator
10604 01:26:50.890696 <4>[ 1.742846] cpu cpu1: supply cpu not found, using dummy regulator
10605 01:26:50.897473 <4>[ 1.749266] cpu cpu2: supply cpu not found, using dummy regulator
10606 01:26:50.904155 <4>[ 1.755661] cpu cpu3: supply cpu not found, using dummy regulator
10607 01:26:50.911114 <4>[ 1.762056] cpu cpu4: supply cpu not found, using dummy regulator
10608 01:26:50.917320 <4>[ 1.768454] cpu cpu5: supply cpu not found, using dummy regulator
10609 01:26:50.923890 <4>[ 1.774848] cpu cpu6: supply cpu not found, using dummy regulator
10610 01:26:50.927601 <4>[ 1.781243] cpu cpu7: supply cpu not found, using dummy regulator
10611 01:26:50.948859 <6>[ 1.802926] cpu cpu0: EM: created perf domain
10612 01:26:50.952295 <6>[ 1.807855] cpu cpu4: EM: created perf domain
10613 01:26:50.959935 <6>[ 1.813422] sdhci: Secure Digital Host Controller Interface driver
10614 01:26:50.966723 <6>[ 1.819852] sdhci: Copyright(c) Pierre Ossman
10615 01:26:50.972894 <6>[ 1.824808] Synopsys Designware Multimedia Card Interface Driver
10616 01:26:50.979787 <6>[ 1.831457] sdhci-pltfm: SDHCI platform and OF driver helper
10617 01:26:50.982770 <6>[ 1.831496] mmc0: CQHCI version 5.10
10618 01:26:50.989770 <6>[ 1.841335] ledtrig-cpu: registered to indicate activity on CPUs
10619 01:26:50.996135 <6>[ 1.848280] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10620 01:26:51.002977 <6>[ 1.855339] usbcore: registered new interface driver usbhid
10621 01:26:51.006237 <6>[ 1.861163] usbhid: USB HID core driver
10622 01:26:51.012680 <6>[ 1.865358] spi_master spi0: will run message pump with realtime priority
10623 01:26:51.055485 <6>[ 1.902544] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10624 01:26:51.070955 <6>[ 1.917785] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10625 01:26:51.079204 <6>[ 1.932435] cros-ec-spi spi0.0: Chrome EC device registered
10626 01:26:51.085921 <6>[ 1.938404] mmc0: Command Queue Engine enabled
10627 01:26:51.092384 <6>[ 1.943131] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10628 01:26:51.095590 <6>[ 1.950627] mmcblk0: mmc0:0001 DA4128 116 GiB
10629 01:26:51.105631 <6>[ 1.951241] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10630 01:26:51.112307 <6>[ 1.958318] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10631 01:26:51.119025 <6>[ 1.965617] NET: Registered PF_PACKET protocol family
10632 01:26:51.122001 <6>[ 1.971393] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10633 01:26:51.125478 <6>[ 1.975952] 9pnet: Installing 9P2000 support
10634 01:26:51.132234 <6>[ 1.981684] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10635 01:26:51.135671 <5>[ 1.985657] Key type dns_resolver registered
10636 01:26:51.142202 <6>[ 1.991376] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10637 01:26:51.148385 <6>[ 1.995944] registered taskstats version 1
10638 01:26:51.152102 <5>[ 2.006254] Loading compiled-in X.509 certificates
10639 01:26:51.179993 <4>[ 2.027392] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10640 01:26:51.190148 <4>[ 2.038105] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 01:26:51.197459 <3>[ 2.048636] debugfs: File 'uA_load' in directory '/' already present!
10642 01:26:51.203789 <3>[ 2.055336] debugfs: File 'min_uV' in directory '/' already present!
10643 01:26:51.210193 <3>[ 2.061944] debugfs: File 'max_uV' in directory '/' already present!
10644 01:26:51.217149 <3>[ 2.068643] debugfs: File 'constraint_flags' in directory '/' already present!
10645 01:26:51.227829 <3>[ 2.078090] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10646 01:26:51.237259 <6>[ 2.091006] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10647 01:26:51.244194 <6>[ 2.097937] xhci-mtk 11200000.usb: xHCI Host Controller
10648 01:26:51.250839 <6>[ 2.103455] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10649 01:26:51.260793 <6>[ 2.111295] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10650 01:26:51.267730 <6>[ 2.120720] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10651 01:26:51.274445 <6>[ 2.126767] xhci-mtk 11200000.usb: xHCI Host Controller
10652 01:26:51.281058 <6>[ 2.132242] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10653 01:26:51.287739 <6>[ 2.139890] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10654 01:26:51.294505 <6>[ 2.147496] hub 1-0:1.0: USB hub found
10655 01:26:51.298016 <6>[ 2.151529] hub 1-0:1.0: 1 port detected
10656 01:26:51.303998 <6>[ 2.155806] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10657 01:26:51.310469 <6>[ 2.164585] hub 2-0:1.0: USB hub found
10658 01:26:51.314198 <6>[ 2.168635] hub 2-0:1.0: 1 port detected
10659 01:26:51.322828 <6>[ 2.176658] mtk-msdc 11f70000.mmc: Got CD GPIO
10660 01:26:51.332865 <6>[ 2.182873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10661 01:26:51.339555 <6>[ 2.190890] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10662 01:26:51.349551 <4>[ 2.198782] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10663 01:26:51.356362 <6>[ 2.208299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10664 01:26:51.366369 <6>[ 2.216377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10665 01:26:51.372748 <6>[ 2.224385] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10666 01:26:51.382931 <6>[ 2.232307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10667 01:26:51.389798 <6>[ 2.240125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10668 01:26:51.399671 <6>[ 2.247942] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10669 01:26:51.409900 <6>[ 2.258397] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10670 01:26:51.415884 <6>[ 2.266749] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10671 01:26:51.425846 <6>[ 2.275091] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10672 01:26:51.432384 <6>[ 2.283433] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10673 01:26:51.442558 <6>[ 2.291771] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10674 01:26:51.449294 <6>[ 2.300109] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10675 01:26:51.459516 <6>[ 2.308447] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10676 01:26:51.465504 <6>[ 2.316784] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10677 01:26:51.475823 <6>[ 2.325122] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10678 01:26:51.482392 <6>[ 2.333459] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10679 01:26:51.492233 <6>[ 2.341796] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10680 01:26:51.498493 <6>[ 2.350135] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10681 01:26:51.508432 <6>[ 2.358472] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10682 01:26:51.515142 <6>[ 2.366813] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10683 01:26:51.525543 <6>[ 2.375151] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10684 01:26:51.531474 <6>[ 2.383937] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10685 01:26:51.538287 <6>[ 2.391124] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10686 01:26:51.545242 <6>[ 2.397893] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10687 01:26:51.551352 <6>[ 2.404662] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10688 01:26:51.558003 <6>[ 2.411584] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10689 01:26:51.568257 <6>[ 2.418433] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10690 01:26:51.578288 <6>[ 2.427562] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10691 01:26:51.588217 <6>[ 2.436680] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10692 01:26:51.598012 <6>[ 2.445973] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10693 01:26:51.607475 <6>[ 2.455440] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10694 01:26:51.614570 <6>[ 2.464908] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10695 01:26:51.624622 <6>[ 2.474027] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10696 01:26:51.634190 <6>[ 2.483493] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10697 01:26:51.644275 <6>[ 2.492612] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10698 01:26:51.654216 <6>[ 2.501909] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10699 01:26:51.664414 <6>[ 2.512070] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10700 01:26:51.673952 <6>[ 2.523746] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10701 01:26:51.680578 <6>[ 2.533484] Trying to probe devices needed for running init ...
10702 01:26:51.704460 <6>[ 2.554759] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10703 01:26:51.731375 <6>[ 2.585117] hub 2-1:1.0: USB hub found
10704 01:26:51.734523 <6>[ 2.589512] hub 2-1:1.0: 3 ports detected
10705 01:26:51.742091 <6>[ 2.595898] hub 2-1:1.0: USB hub found
10706 01:26:51.745222 <6>[ 2.600258] hub 2-1:1.0: 3 ports detected
10707 01:26:51.856443 <6>[ 2.706770] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10708 01:26:52.010106 <6>[ 2.863811] hub 1-1:1.0: USB hub found
10709 01:26:52.013537 <6>[ 2.868270] hub 1-1:1.0: 4 ports detected
10710 01:26:52.022727 <6>[ 2.876439] hub 1-1:1.0: USB hub found
10711 01:26:52.025817 <6>[ 2.880937] hub 1-1:1.0: 4 ports detected
10712 01:26:52.091899 <6>[ 2.942738] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10713 01:26:52.348235 <6>[ 3.198663] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10714 01:26:52.480507 <6>[ 3.334401] hub 1-1.4:1.0: USB hub found
10715 01:26:52.483864 <6>[ 3.339038] hub 1-1.4:1.0: 2 ports detected
10716 01:26:52.494081 <6>[ 3.347531] hub 1-1.4:1.0: USB hub found
10717 01:26:52.496870 <6>[ 3.352118] hub 1-1.4:1.0: 2 ports detected
10718 01:26:52.795963 <6>[ 3.646664] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10719 01:26:52.987967 <6>[ 3.838665] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10720 01:27:03.973351 <6>[ 14.831706] ALSA device list:
10721 01:27:03.980022 <6>[ 14.834991] No soundcards found.
10722 01:27:03.987491 <6>[ 14.842959] Freeing unused kernel memory: 8448K
10723 01:27:03.990896 <6>[ 14.848512] Run /init as init process
10724 01:27:04.002480 Loading, please wait...
10725 01:27:04.032982 Starting systemd-udevd version 252.22-1~deb12u1
10726 01:27:04.033082
10727 01:27:04.245946 <6>[ 15.097535] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10728 01:27:04.252668 <6>[ 15.105251] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10729 01:27:04.262495 <6>[ 15.113995] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10730 01:27:04.276787 <6>[ 15.128650] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10731 01:27:04.287491 <3>[ 15.139626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 01:27:04.294365 <6>[ 15.142056] remoteproc remoteproc0: scp is available
10733 01:27:04.301144 <3>[ 15.148071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 01:27:04.310932 <3>[ 15.148107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 01:27:04.317480 <3>[ 15.148419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 01:27:04.327332 <3>[ 15.148437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 01:27:04.333887 <3>[ 15.148444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 01:27:04.340744 <3>[ 15.148462] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 01:27:04.350612 <3>[ 15.148471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 01:27:04.357396 <3>[ 15.148567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 01:27:04.363652 <6>[ 15.154045] remoteproc remoteproc0: powering up scp
10742 01:27:04.366960 <6>[ 15.154325] mc: Linux media interface: v0.10
10743 01:27:04.377288 <3>[ 15.162431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 01:27:04.384015 <6>[ 15.163703] usbcore: registered new device driver r8152-cfgselector
10745 01:27:04.390015 <6>[ 15.170054] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10746 01:27:04.396725 <6>[ 15.170117] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10747 01:27:04.403593 <6>[ 15.187205] videodev: Linux video capture interface: v2.00
10748 01:27:04.410292 <3>[ 15.194616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 01:27:04.416638 <4>[ 15.208528] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10750 01:27:04.427126 <3>[ 15.210797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 01:27:04.433223 <4>[ 15.219388] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10752 01:27:04.443541 <3>[ 15.224116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 01:27:04.449890 <6>[ 15.229862] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10754 01:27:04.456796 <3>[ 15.236567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 01:27:04.466989 <3>[ 15.236573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 01:27:04.474281 <3>[ 15.236581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 01:27:04.480201 <3>[ 15.236586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 01:27:04.490984 <3>[ 15.236630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 01:27:04.497855 <6>[ 15.246437] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10760 01:27:04.504649 <6>[ 15.266998] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10761 01:27:04.510809 <6>[ 15.271298] pci_bus 0000:00: root bus resource [bus 00-ff]
10762 01:27:04.521201 <4>[ 15.285152] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10763 01:27:04.524603 <4>[ 15.285152] Fallback method does not support PEC.
10764 01:27:04.530684 <6>[ 15.286978] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10765 01:27:04.537282 <6>[ 15.296600] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10766 01:27:04.547605 <6>[ 15.302050] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10767 01:27:04.553746 <6>[ 15.302056] remoteproc remoteproc0: remote processor scp is now up
10768 01:27:04.564154 <6>[ 15.302070] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10769 01:27:04.570439 <6>[ 15.302107] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10770 01:27:04.576998 <6>[ 15.302121] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10771 01:27:04.586807 <4>[ 15.313022] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10772 01:27:04.590555 <6>[ 15.317917] pci 0000:00:00.0: supports D1 D2
10773 01:27:04.600555 <6>[ 15.319727] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10774 01:27:04.610175 <6>[ 15.320703] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10775 01:27:04.617160 <6>[ 15.321213] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10776 01:27:04.626658 <6>[ 15.321844] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10777 01:27:04.636690 <3>[ 15.325130] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 01:27:04.643393 <4>[ 15.325949] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10779 01:27:04.649868 <6>[ 15.334013] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10780 01:27:04.660207 <6>[ 15.335031] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10781 01:27:04.666998 <6>[ 15.338768] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10782 01:27:04.670200 <6>[ 15.357788] Bluetooth: Core ver 2.22
10783 01:27:04.676868 <6>[ 15.365559] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10784 01:27:04.683260 <6>[ 15.371254] NET: Registered PF_BLUETOOTH protocol family
10785 01:27:04.690015 <6>[ 15.384817] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10786 01:27:04.696536 <6>[ 15.391929] Bluetooth: HCI device and connection manager initialized
10787 01:27:04.706157 <6>[ 15.398968] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10788 01:27:04.713018 <6>[ 15.399957] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10789 01:27:04.722610 <6>[ 15.401152] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10790 01:27:04.729467 <6>[ 15.401247] usbcore: registered new interface driver uvcvideo
10791 01:27:04.739112 <3>[ 15.407490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 01:27:04.742646 <6>[ 15.407577] Bluetooth: HCI socket layer initialized
10793 01:27:04.749211 <6>[ 15.407583] Bluetooth: L2CAP socket layer initialized
10794 01:27:04.756141 <6>[ 15.407592] Bluetooth: SCO socket layer initialized
10795 01:27:04.759152 <6>[ 15.407630] r8152 2-1.3:1.0 eth0: v1.12.13
10796 01:27:04.766005 <6>[ 15.407691] usbcore: registered new interface driver r8152
10797 01:27:04.772935 <6>[ 15.413910] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10798 01:27:04.779640 <6>[ 15.438049] usbcore: registered new interface driver cdc_ether
10799 01:27:04.782985 <6>[ 15.446678] pci 0000:01:00.0: supports D1 D2
10800 01:27:04.788925 <6>[ 15.447628] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10801 01:27:04.795921 <6>[ 15.459846] usbcore: registered new interface driver btusb
10802 01:27:04.805816 <4>[ 15.460602] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10803 01:27:04.812066 <3>[ 15.460612] Bluetooth: hci0: Failed to load firmware file (-2)
10804 01:27:04.818617 <3>[ 15.460616] Bluetooth: hci0: Failed to set up firmware (-2)
10805 01:27:04.828900 <4>[ 15.460620] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10806 01:27:04.835081 <6>[ 15.469415] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10807 01:27:04.841777 <6>[ 15.469695] usbcore: registered new interface driver r8153_ecm
10808 01:27:04.848532 <6>[ 15.482522] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10809 01:27:04.855244 <6>[ 15.496198] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10810 01:27:04.861996 <6>[ 15.503595] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10811 01:27:04.868385 <6>[ 15.722062] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10812 01:27:04.878205 <6>[ 15.730064] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10813 01:27:04.884659 <6>[ 15.738067] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10814 01:27:04.894813 <6>[ 15.746068] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10815 01:27:04.898224 <6>[ 15.754068] pci 0000:00:00.0: PCI bridge to [bus 01]
10816 01:27:04.907973 <6>[ 15.759284] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10817 01:27:04.914589 <6>[ 15.767417] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10818 01:27:04.921495 <6>[ 15.774263] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10819 01:27:04.927541 <6>[ 15.780694] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10820 01:27:04.960866 <5>[ 15.812560] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10821 01:27:04.979470 <5>[ 15.831767] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10822 01:27:04.986263 <5>[ 15.839254] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10823 01:27:04.996193 <4>[ 15.847761] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10824 01:27:05.002567 <6>[ 15.856666] cfg80211: failed to load regulatory.db
10825 01:27:05.054259 <6>[ 15.906361] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10826 01:27:05.060730 <6>[ 15.914046] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10827 01:27:05.085534 <6>[ 15.941120] mt7921e 0000:01:00.0: ASIC revision: 79610010
10828 01:27:05.190587 <6>[ 16.042582] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10829 01:27:05.193505 <6>[ 16.042582]
10830 01:27:05.220659 Begin: Loading essential drivers ... done.
10831 01:27:05.223874 Begin: Running /scripts/init-premount ... done.
10832 01:27:05.230420 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10833 01:27:05.240568 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10834 01:27:05.243474 Device /sys/class/net/enx00e04c787aaa found
10835 01:27:05.243556 done.
10836 01:27:05.250136 Begin: Waiting up to 180 secs for any network device to become available ... done.
10837 01:27:05.310520 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10838 01:27:05.460287 <6>[ 16.312526] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10839 01:27:06.145710 <6>[ 17.000998] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10840 01:27:06.315418 <6>[ 17.170548] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10841 01:27:06.350824 IP-Config: no response after 2 secs - giving up
10842 01:27:06.387396 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10843 01:27:07.046140 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10844 01:27:07.049580 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10845 01:27:07.056258 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10846 01:27:07.066194 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10847 01:27:07.069577 host : mt8192-asurada-spherion-r0-cbg-0
10848 01:27:07.076119 domain : lava-rack
10849 01:27:07.079549 rootserver: 192.168.201.1 rootpath:
10850 01:27:07.082863 filename :
10851 01:27:07.227630 done.
10852 01:27:07.234572 Begin: Running /scripts/nfs-bottom ... done.
10853 01:27:07.246094 Begin: Running /scripts/init-bottom ... done.
10854 01:27:08.557227 <6>[ 19.412829] NET: Registered PF_INET6 protocol family
10855 01:27:08.564677 <6>[ 19.420534] Segment Routing with IPv6
10856 01:27:08.567816 <6>[ 19.424552] In-situ OAM (IOAM) with IPv6
10857 01:27:08.732911 <30>[ 19.562281] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10858 01:27:08.739631 <30>[ 19.595437] systemd[1]: Detected architecture arm64.
10859 01:27:08.746949
10860 01:27:08.750026 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10861 01:27:08.750121
10862 01:27:08.750185
10863 01:27:08.775909 <30>[ 19.631557] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10864 01:27:09.766844 <30>[ 20.619601] systemd[1]: Queued start job for default target graphical.target.
10865 01:27:09.807623 <30>[ 20.659681] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10866 01:27:09.813523 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10867 01:27:09.813667
10868 01:27:09.836049 <30>[ 20.688539] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10869 01:27:09.845960 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10870 01:27:09.846068
10871 01:27:09.863832 <30>[ 20.716501] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10872 01:27:09.873938 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10873 01:27:09.874024
10874 01:27:09.891830 <30>[ 20.744211] systemd[1]: Created slice user.slice - User and Session Slice.
10875 01:27:09.897830 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10876 01:27:09.897921
10877 01:27:09.922377 <30>[ 20.771539] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10878 01:27:09.932689 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10879 01:27:09.933127
10880 01:27:09.949818 <30>[ 20.798963] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10881 01:27:09.956699 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10882 01:27:09.957121
10883 01:27:09.984130 <30>[ 20.826872] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10884 01:27:09.994508 <30>[ 20.846697] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10885 01:27:10.000752 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10886 01:27:10.001130
10887 01:27:10.018486 <30>[ 20.870998] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10888 01:27:10.024936 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10889 01:27:10.025028
10890 01:27:10.046615 <30>[ 20.899156] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10891 01:27:10.056490 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10892 01:27:10.056581
10893 01:27:10.070998 <30>[ 20.927216] systemd[1]: Reached target paths.target - Path Units.
10894 01:27:10.078402 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10895 01:27:10.081211
10896 01:27:10.098417 <30>[ 20.951114] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10897 01:27:10.105471 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10898 01:27:10.105551
10899 01:27:10.118713 <30>[ 20.974656] systemd[1]: Reached target slices.target - Slice Units.
10900 01:27:10.129098 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10901 01:27:10.129190
10902 01:27:10.143183 <30>[ 20.999078] systemd[1]: Reached target swap.target - Swaps.
10903 01:27:10.149955 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10904 01:27:10.150073
10905 01:27:10.171260 <30>[ 21.023188] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10906 01:27:10.180587 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10907 01:27:10.180892
10908 01:27:10.199721 <30>[ 21.051676] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10909 01:27:10.209083 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10910 01:27:10.209611
10911 01:27:10.228195 <30>[ 21.080895] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10912 01:27:10.237885 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10913 01:27:10.237978
10914 01:27:10.255330 <30>[ 21.107998] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10915 01:27:10.265539 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10916 01:27:10.265622
10917 01:27:10.283582 <30>[ 21.135987] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10918 01:27:10.289921 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10919 01:27:10.290024
10920 01:27:10.311777 <30>[ 21.164204] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10921 01:27:10.321891 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10922 01:27:10.322035
10923 01:27:10.340404 <30>[ 21.193147] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10924 01:27:10.350526 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10925 01:27:10.350613
10926 01:27:10.366773 <30>[ 21.219178] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10927 01:27:10.376437 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10928 01:27:10.376536
10929 01:27:10.426668 <30>[ 21.279038] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10930 01:27:10.432831 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10931 01:27:10.432938
10932 01:27:10.452939 <30>[ 21.305447] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10933 01:27:10.459706 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10934 01:27:10.459905
10935 01:27:10.481173 <30>[ 21.333981] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10936 01:27:10.488187 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10937 01:27:10.488296
10938 01:27:10.512827 <30>[ 21.359218] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10939 01:27:10.550828 <30>[ 21.403423] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10940 01:27:10.560571 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10941 01:27:10.560659
10942 01:27:10.584290 <30>[ 21.436606] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10943 01:27:10.590705 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10944 01:27:10.591187
10945 01:27:10.646957 <30>[ 21.499388] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10946 01:27:10.653282 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10947 01:27:10.653375
10948 01:27:10.677802 <30>[ 21.530316] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10949 01:27:10.687684 Starting [0;1;39mmodpr<6>[ 21.540791] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10950 01:27:10.693742 obe@drm.service[0m - Load Kernel Module drm...
10951 01:27:10.693821
10952 01:27:10.715903 <30>[ 21.568512] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10953 01:27:10.725538 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10954 01:27:10.725637
10955 01:27:10.748020 <30>[ 21.600396] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10956 01:27:10.753997 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10957 01:27:10.754113
10958 01:27:10.779784 <30>[ 21.632377] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10959 01:27:10.786535 Startin<6>[ 21.641217] fuse: init (API version 7.37)
10960 01:27:10.792872 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10961 01:27:10.792953
10962 01:27:10.819655 <30>[ 21.672474] systemd[1]: Starting systemd-journald.service - Journal Service...
10963 01:27:10.826651 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10964 01:27:10.826731
10965 01:27:10.858072 <30>[ 21.710819] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10966 01:27:10.864471 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10967 01:27:10.864552
10968 01:27:10.892669 <30>[ 21.742199] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10969 01:27:10.899529 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10970 01:27:10.899621
10971 01:27:10.924546 <30>[ 21.777337] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10972 01:27:10.934859 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10973 01:27:10.934944
10974 01:27:10.955791 <30>[ 21.807486] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10975 01:27:10.965475 Startin<3>[ 21.816921] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 01:27:10.971977 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10977 01:27:10.972064
10978 01:27:10.994582 <30>[ 21.846966] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10979 01:27:11.001294 <3>[ 21.851324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 01:27:11.011322 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10981 01:27:11.011404
10982 01:27:11.030571 <30>[ 21.883062] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10983 01:27:11.044152 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 21.896520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 01:27:11.047498 X Message Queue File System.
10985 01:27:11.047576
10986 01:27:11.066917 <30>[ 21.919043] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10987 01:27:11.073980 <3>[ 21.926746] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 01:27:11.083313 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10989 01:27:11.083451
10990 01:27:11.103614 <30>[ 21.955958] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10991 01:27:11.113315 <3>[ 21.965364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 01:27:11.120230 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10993 01:27:11.120457
10994 01:27:11.143279 <3>[ 21.995786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 01:27:11.149926 <30>[ 21.995877] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10996 01:27:11.160558 <30>[ 22.012519] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10997 01:27:11.174597 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.025225] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 01:27:11.177949 onfigfs…[0m - Load Kernel Module configfs.
10999 01:27:11.178430
11000 01:27:11.196384 <30>[ 22.047858] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11001 01:27:11.202695 <30>[ 22.055821] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11002 01:27:11.213129 <3>[ 22.056725] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 01:27:11.219840 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11004 01:27:11.220271
11005 01:27:11.240210 <30>[ 22.092608] systemd[1]: modprobe@drm.service: Deactivated successfully.
11006 01:27:11.246888 <3>[ 22.097318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 01:27:11.257236 <30>[ 22.100314] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11008 01:27:11.263339 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11009 01:27:11.263766
11010 01:27:11.279485 <3>[ 22.131863] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 01:27:11.290102 <30>[ 22.142478] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11012 01:27:11.300638 <30>[ 22.151210] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11013 01:27:11.307480 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11014 01:27:11.307949
11015 01:27:11.325000 <30>[ 22.179836] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11016 01:27:11.335576 <30>[ 22.187917] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11017 01:27:11.342462 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11018 01:27:11.342892
11019 01:27:11.369021 <4>[ 22.214742] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11020 01:27:11.375173 <30>[ 22.215055] systemd[1]: Started systemd-journald.service - Journal Service.
11021 01:27:11.385787 <3>[ 22.230406] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11022 01:27:11.392520 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11023 01:27:11.393068
11024 01:27:11.415371 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11025 01:27:11.415921
11026 01:27:11.436258 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11027 01:27:11.436758
11028 01:27:11.455892 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11029 01:27:11.456442
11030 01:27:11.475780 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11031 01:27:11.476416
11032 01:27:11.495531 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11033 01:27:11.495979
11034 01:27:11.517266 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11035 01:27:11.517839
11036 01:27:11.570812 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11037 01:27:11.570913
11038 01:27:11.588505 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11039 01:27:11.588619
11040 01:27:11.609699 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11041 01:27:11.609789
11042 01:27:11.654352 <46>[ 22.507186] systemd-journald[313]: Received client request to flush runtime journal.
11043 01:27:11.691540 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11044 01:27:11.691658
11045 01:27:12.174292 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11046 01:27:12.174449
11047 01:27:12.450804 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11048 01:27:12.450935
11049 01:27:12.710582 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11050 01:27:12.710718
11051 01:27:12.726833 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11052 01:27:12.726963
11053 01:27:12.780067 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11054 01:27:12.780215
11055 01:27:13.053996 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11056 01:27:13.054155
11057 01:27:13.074815 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11058 01:27:13.074904
11059 01:27:13.099315 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11060 01:27:13.099398
11061 01:27:13.154446 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11062 01:27:13.154579
11063 01:27:13.221528 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11064 01:27:13.221636
11065 01:27:13.242276 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11066 01:27:13.242397
11067 01:27:13.261880 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11068 01:27:13.261981
11069 01:27:13.322404 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11070 01:27:13.322510
11071 01:27:13.346359 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11072 01:27:13.346482
11073 01:27:13.580522 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11074 01:27:13.580682
11075 01:27:13.642704 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11076 01:27:13.642819
11077 01:27:13.666839 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11078 01:27:13.666928
11079 01:27:13.705858 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11080 01:27:13.705975
11081 01:27:13.915915 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11082 01:27:13.916049
11083 01:27:13.948691 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11084 01:27:13.948791
11085 01:27:14.099408 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11086 01:27:14.099542
11087 01:27:14.167551 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11088 01:27:14.167678
11089 01:27:14.189884 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11090 01:27:14.189984
11091 01:27:14.246185 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11092 01:27:14.246359
11093 01:27:14.297875 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11094 01:27:14.297993
11095 01:27:14.314632 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11096 01:27:14.314723
11097 01:27:14.362071 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11098 01:27:14.362192
11099 01:27:14.390966 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11100 01:27:14.391065
11101 01:27:14.409665 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11102 01:27:14.409754
11103 01:27:14.426026 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11104 01:27:14.426120
11105 01:27:14.441971 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11106 01:27:14.442060
11107 01:27:14.464298 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11108 01:27:14.464412
11109 01:27:14.484261 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11110 01:27:14.484357
11111 01:27:14.502197 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11112 01:27:14.502359
11113 01:27:14.520703 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11114 01:27:14.520810
11115 01:27:14.577533 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11116 01:27:14.577655
11117 01:27:14.594184 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11118 01:27:14.594324
11119 01:27:14.611518 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11120 01:27:14.611604
11121 01:27:14.629539 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11122 01:27:14.629629
11123 01:27:14.646121 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11124 01:27:14.646248
11125 01:27:14.662052 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11126 01:27:14.662159
11127 01:27:14.698998 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11128 01:27:14.699106
11129 01:27:14.733868 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11130 01:27:14.733968
11131 01:27:14.818844 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11132 01:27:14.818964
11133 01:27:14.849977 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11134 01:27:14.850099
11135 01:27:14.876972 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11136 01:27:14.877086
11137 01:27:15.006691 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11138 01:27:15.006823
11139 01:27:15.064015 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11140 01:27:15.064138
11141 01:27:15.134532 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11142 01:27:15.134648
11143 01:27:15.159151 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11144 01:27:15.159258
11145 01:27:15.174928 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11146 01:27:15.175015
11147 01:27:15.193649 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11148 01:27:15.193734
11149 01:27:15.226652 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11150 01:27:15.226755
11151 01:27:15.250519 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11152 01:27:15.250627
11153 01:27:15.278174 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11154 01:27:15.278289
11155 01:27:15.298726 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11156 01:27:15.298850
11157 01:27:15.369737 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11158 01:27:15.370220
11159 01:27:15.390581 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11160 01:27:15.391034
11161 01:27:15.439067 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11162 01:27:15.439759
11163 01:27:15.500411 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11164 01:27:15.500968
11165 01:27:15.585040
11166 01:27:15.585165
11167 01:27:15.587865 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11168 01:27:15.587946
11169 01:27:15.591289 debian-bookworm-arm64 login: root (automatic login)
11170 01:27:15.591362
11171 01:27:15.591422
11172 01:27:15.860495 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Tue Apr 23 00:57:17 UTC 2024 aarch64
11173 01:27:15.860647
11174 01:27:15.867054 The programs included with the Debian GNU/Linux system are free software;
11175 01:27:15.873897 the exact distribution terms for each program are described in the
11176 01:27:15.877210 individual files in /usr/share/doc/*/copyright.
11177 01:27:15.877286
11178 01:27:15.883372 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11179 01:27:15.886626 permitted by applicable law.
11180 01:27:16.871082 Matched prompt #10: / #
11182 01:27:16.871352 Setting prompt string to ['/ #']
11183 01:27:16.871447 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11185 01:27:16.871642 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11186 01:27:16.871731 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
11187 01:27:16.871803 Setting prompt string to ['/ #']
11188 01:27:16.871862 Forcing a shell prompt, looking for ['/ #']
11190 01:27:16.922055 / #
11191 01:27:16.922253 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11192 01:27:16.922414 Waiting using forced prompt support (timeout 00:02:30)
11193 01:27:16.927282
11194 01:27:16.927688 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11195 01:27:16.927880 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11197 01:27:17.028322 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4'
11198 01:27:17.033503 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13468775/extract-nfsrootfs-adky45n4'
11200 01:27:17.134129 / # export NFS_SERVER_IP='192.168.201.1'
11201 01:27:17.140134 export NFS_SERVER_IP='192.168.201.1'
11202 01:27:17.140925 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11203 01:27:17.141388 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11204 01:27:17.141819 end: 2 depthcharge-action (duration 00:01:28) [common]
11205 01:27:17.142271 start: 3 lava-test-retry (timeout 00:07:50) [common]
11206 01:27:17.142752 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11207 01:27:17.143344 Using namespace: common
11209 01:27:17.244738 / # #
11210 01:27:17.245513 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11211 01:27:17.251668 #
11212 01:27:17.252407 Using /lava-13468775
11214 01:27:17.353690 / # export SHELL=/bin/bash
11215 01:27:17.360087 export SHELL=/bin/bash
11217 01:27:17.461594 / # . /lava-13468775/environment
11218 01:27:17.466411 . /lava-13468775/environment
11220 01:27:17.572242 / # /lava-13468775/bin/lava-test-runner /lava-13468775/0
11221 01:27:17.572938 Test shell timeout: 10s (minimum of the action and connection timeout)
11222 01:27:17.578691 /lava-13468775/bin/lava-test-runner /lava-13468775/0
11223 01:27:17.800097 + export TESTRUN_ID=0_timesync-off
11224 01:27:17.803225 + TESTRUN_ID=0_timesync-off
11225 01:27:17.806843 + cd /lava-13468775/0/tests/0_timesync-off
11226 01:27:17.810167 ++ cat uuid
11227 01:27:17.813364 + UUID=13468775_1.6.2.3.1
11228 01:27:17.813468 + set +x
11229 01:27:17.816591 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13468775_1.6.2.3.1>
11230 01:27:17.816896 Received signal: <STARTRUN> 0_timesync-off 13468775_1.6.2.3.1
11231 01:27:17.816994 Starting test lava.0_timesync-off (13468775_1.6.2.3.1)
11232 01:27:17.817111 Skipping test definition patterns.
11233 01:27:17.819858 + systemctl stop systemd-timesyncd
11234 01:27:17.873279 + set +x
11235 01:27:17.876054 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13468775_1.6.2.3.1>
11236 01:27:17.876311 Received signal: <ENDRUN> 0_timesync-off 13468775_1.6.2.3.1
11237 01:27:17.876387 Ending use of test pattern.
11238 01:27:17.876447 Ending test lava.0_timesync-off (13468775_1.6.2.3.1), duration 0.06
11240 01:27:17.929473 + export TESTRUN_ID=1_kselftest-alsa
11241 01:27:17.933332 + TESTRUN_ID=1_kselftest-alsa
11242 01:27:17.939749 + cd /lava-13468775/0/tests/1_kselftest-alsa
11243 01:27:17.939828 ++ cat uuid
11244 01:27:17.943154 + UUID=13468775_1.6.2.3.5
11245 01:27:17.943263 + set +x
11246 01:27:17.945986 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 13468775_1.6.2.3.5>
11247 01:27:17.946261 Received signal: <STARTRUN> 1_kselftest-alsa 13468775_1.6.2.3.5
11248 01:27:17.946394 Starting test lava.1_kselftest-alsa (13468775_1.6.2.3.5)
11249 01:27:17.946524 Skipping test definition patterns.
11250 01:27:17.949301 + cd ./automated/linux/kselftest/
11251 01:27:17.975901 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11252 01:27:18.007986 INFO: install_deps skipped
11253 01:27:18.502546 --2024-04-23 01:23:07-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19-44-g09a10637e8de/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11254 01:27:18.512636 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11255 01:27:18.639442 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11256 01:27:18.765676 HTTP request sent, awaiting response... 200 OK
11257 01:27:18.769140 Length: 1651524 (1.6M) [application/octet-stream]
11258 01:27:18.772512 Saving to: 'kselftest_armhf.tar.gz'
11259 01:27:18.772612
11260 01:27:18.772705
11261 01:27:19.019085 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11262 01:27:19.272401 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11263 01:27:19.573372 kselftest_armhf.tar 13%[=> ] 217.50K 421KB/s
11264 01:27:19.700156 kselftest_armhf.tar 51%[=========> ] 822.71K 1000KB/s
11265 01:27:19.706897 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 1.0s
11266 01:27:19.707012
11267 01:27:19.851668 2024-04-23 01:23:08 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1651524/1651524]
11268 01:27:19.851826
11269 01:27:23.546987 skiplist:
11270 01:27:23.550447 ========================================
11271 01:27:23.553992 ========================================
11272 01:27:23.600122 alsa:mixer-test
11273 01:27:23.619916 ============== Tests to run ===============
11274 01:27:23.620509 alsa:mixer-test
11275 01:27:23.623607 ===========End Tests to run ===============
11276 01:27:23.626967 shardfile-alsa pass
11277 01:27:23.728100 <12>[ 34.585151] kselftest: Running tests in alsa
11278 01:27:23.736294 TAP version 13
11279 01:27:23.750281 1..1
11280 01:27:23.761537 # selftests: alsa: mixer-test
11281 01:27:24.245468 # TAP version 13
11282 01:27:24.245952 # 1..0
11283 01:27:24.251585 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11284 01:27:24.254789 ok 1 selftests: alsa: mixer-test
11285 01:27:25.641059 alsa_mixer-test pass
11286 01:27:25.717836 + ../../utils/send-to-lava.sh ./output/result.txt
11287 01:27:25.772816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11288 01:27:25.773113 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11290 01:27:25.805258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11291 01:27:25.805353 + set +x
11292 01:27:25.805610 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11294 01:27:25.811857 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 13468775_1.6.2.3.5>
11295 01:27:25.812100 Received signal: <ENDRUN> 1_kselftest-alsa 13468775_1.6.2.3.5
11296 01:27:25.812170 Ending use of test pattern.
11297 01:27:25.812231 Ending test lava.1_kselftest-alsa (13468775_1.6.2.3.5), duration 7.87
11299 01:27:25.814837 <LAVA_TEST_RUNNER EXIT>
11300 01:27:25.815074 ok: lava_test_shell seems to have completed
11301 01:27:25.815166 alsa_mixer-test: pass
shardfile-alsa: pass
11302 01:27:25.815255 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11303 01:27:25.815336 end: 3 lava-test-retry (duration 00:00:09) [common]
11304 01:27:25.815417 start: 4 finalize (timeout 00:07:42) [common]
11305 01:27:25.815508 start: 4.1 power-off (timeout 00:00:30) [common]
11306 01:27:25.815663 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11307 01:27:25.896081 >> Command sent successfully.
11308 01:27:25.899084 Returned 0 in 0 seconds
11309 01:27:25.999473 end: 4.1 power-off (duration 00:00:00) [common]
11311 01:27:25.999953 start: 4.2 read-feedback (timeout 00:07:41) [common]
11312 01:27:26.000367 Listened to connection for namespace 'common' for up to 1s
11313 01:27:27.001355 Finalising connection for namespace 'common'
11314 01:27:27.001818 Disconnecting from shell: Finalise
11315 01:27:27.002085 / #
11316 01:27:27.102728 end: 4.2 read-feedback (duration 00:00:01) [common]
11317 01:27:27.102892 end: 4 finalize (duration 00:00:01) [common]
11318 01:27:27.103012 Cleaning after the job
11319 01:27:27.103115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/ramdisk
11320 01:27:27.105219 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/kernel
11321 01:27:27.115602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/dtb
11322 01:27:27.115771 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/nfsrootfs
11323 01:27:27.179135 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13468775/tftp-deploy-kqdu6js6/modules
11324 01:27:27.184963 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13468775
11325 01:27:27.768987 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13468775
11326 01:27:27.769152 Job finished correctly